SelectionDAGBuilder.cpp revision 77fffa6fdd389ad6d70a42b36c1c36c768c2de41
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DebugInfo.h" 25#include "llvm/DerivedTypes.h" 26#include "llvm/Function.h" 27#include "llvm/GlobalVariable.h" 28#include "llvm/InlineAsm.h" 29#include "llvm/Instructions.h" 30#include "llvm/Intrinsics.h" 31#include "llvm/IntrinsicInst.h" 32#include "llvm/LLVMContext.h" 33#include "llvm/Module.h" 34#include "llvm/CodeGen/Analysis.h" 35#include "llvm/CodeGen/FastISel.h" 36#include "llvm/CodeGen/FunctionLoweringInfo.h" 37#include "llvm/CodeGen/GCStrategy.h" 38#include "llvm/CodeGen/GCMetadata.h" 39#include "llvm/CodeGen/MachineFunction.h" 40#include "llvm/CodeGen/MachineFrameInfo.h" 41#include "llvm/CodeGen/MachineInstrBuilder.h" 42#include "llvm/CodeGen/MachineJumpTableInfo.h" 43#include "llvm/CodeGen/MachineModuleInfo.h" 44#include "llvm/CodeGen/MachineRegisterInfo.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameLowering.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetIntrinsicInfo.h" 50#include "llvm/Target/TargetLibraryInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/IntegersSubsetMapping.h" 55#include "llvm/Support/Debug.h" 56#include "llvm/Support/ErrorHandling.h" 57#include "llvm/Support/MathExtras.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62/// LimitFloatPrecision - Generate low-precision inline sequences for 63/// some float libcalls (6, 8 or 12 bits). 64static unsigned LimitFloatPrecision; 65 66static cl::opt<unsigned, true> 67LimitFPPrecision("limit-float-precision", 68 cl::desc("Generate low-precision inline sequences " 69 "for some float libcalls"), 70 cl::location(LimitFloatPrecision), 71 cl::init(0)); 72 73// Limit the width of DAG chains. This is important in general to prevent 74// prevent DAG-based analysis from blowing up. For example, alias analysis and 75// load clustering may not complete in reasonable time. It is difficult to 76// recognize and avoid this situation within each individual analysis, and 77// future analyses are likely to have the same behavior. Limiting DAG width is 78// the safe approach, and will be especially important with global DAGs. 79// 80// MaxParallelChains default is arbitrarily high to avoid affecting 81// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 82// sequence over this should have been converted to llvm.memcpy by the 83// frontend. It easy to induce this behavior with .ll code such as: 84// %buffer = alloca [4096 x i8] 85// %data = load [4096 x i8]* %argPtr 86// store [4096 x i8] %data, [4096 x i8]* %buffer 87static const unsigned MaxParallelChains = 64; 88 89static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 90 const SDValue *Parts, unsigned NumParts, 91 EVT PartVT, EVT ValueVT); 92 93/// getCopyFromParts - Create a value that contains the specified legal parts 94/// combined into the value they represent. If the parts combine to a type 95/// larger then ValueVT then AssertOp can be used to specify whether the extra 96/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 97/// (ISD::AssertSext). 98static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 99 const SDValue *Parts, 100 unsigned NumParts, EVT PartVT, EVT ValueVT, 101 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 102 if (ValueVT.isVector()) 103 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 104 105 assert(NumParts > 0 && "No parts to assemble!"); 106 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 107 SDValue Val = Parts[0]; 108 109 if (NumParts > 1) { 110 // Assemble the value from multiple parts. 111 if (ValueVT.isInteger()) { 112 unsigned PartBits = PartVT.getSizeInBits(); 113 unsigned ValueBits = ValueVT.getSizeInBits(); 114 115 // Assemble the power of 2 part. 116 unsigned RoundParts = NumParts & (NumParts - 1) ? 117 1 << Log2_32(NumParts) : NumParts; 118 unsigned RoundBits = PartBits * RoundParts; 119 EVT RoundVT = RoundBits == ValueBits ? 120 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 121 SDValue Lo, Hi; 122 123 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 124 125 if (RoundParts > 2) { 126 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 127 PartVT, HalfVT); 128 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 129 RoundParts / 2, PartVT, HalfVT); 130 } else { 131 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 132 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 133 } 134 135 if (TLI.isBigEndian()) 136 std::swap(Lo, Hi); 137 138 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 139 140 if (RoundParts < NumParts) { 141 // Assemble the trailing non-power-of-2 part. 142 unsigned OddParts = NumParts - RoundParts; 143 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 144 Hi = getCopyFromParts(DAG, DL, 145 Parts + RoundParts, OddParts, PartVT, OddVT); 146 147 // Combine the round and odd parts. 148 Lo = Val; 149 if (TLI.isBigEndian()) 150 std::swap(Lo, Hi); 151 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 152 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 153 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 154 DAG.getConstant(Lo.getValueType().getSizeInBits(), 155 TLI.getPointerTy())); 156 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 157 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 158 } 159 } else if (PartVT.isFloatingPoint()) { 160 // FP split into multiple FP parts (for ppcf128) 161 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 162 "Unexpected split"); 163 SDValue Lo, Hi; 164 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 165 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 166 if (TLI.isBigEndian()) 167 std::swap(Lo, Hi); 168 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 169 } else { 170 // FP split into integer parts (soft fp) 171 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 172 !PartVT.isVector() && "Unexpected split"); 173 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 174 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 175 } 176 } 177 178 // There is now one part, held in Val. Correct it to match ValueVT. 179 PartVT = Val.getValueType(); 180 181 if (PartVT == ValueVT) 182 return Val; 183 184 if (PartVT.isInteger() && ValueVT.isInteger()) { 185 if (ValueVT.bitsLT(PartVT)) { 186 // For a truncate, see if we have any information to 187 // indicate whether the truncated bits will always be 188 // zero or sign-extension. 189 if (AssertOp != ISD::DELETED_NODE) 190 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 191 DAG.getValueType(ValueVT)); 192 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 193 } 194 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 195 } 196 197 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 198 // FP_ROUND's are always exact here. 199 if (ValueVT.bitsLT(Val.getValueType())) 200 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 201 DAG.getTargetConstant(1, TLI.getPointerTy())); 202 203 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 204 } 205 206 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 207 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 208 209 llvm_unreachable("Unknown mismatch!"); 210} 211 212/// getCopyFromParts - Create a value that contains the specified legal parts 213/// combined into the value they represent. If the parts combine to a type 214/// larger then ValueVT then AssertOp can be used to specify whether the extra 215/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216/// (ISD::AssertSext). 217static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 287 "Cannot handle this kind of promotion"); 288 // Promoted vector extract 289 bool Smaller = ValueVT.bitsLE(PartVT); 290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 291 DL, ValueVT, Val); 292 293 } 294 295 // Trivial bitcast if the types are the same size and the destination 296 // vector type is legal. 297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 298 TLI.isTypeLegal(ValueVT)) 299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 300 301 // Handle cases such as i8 -> <1 x i1> 302 assert(ValueVT.getVectorNumElements() == 1 && 303 "Only trivial scalar-to-vector conversions should get here!"); 304 305 if (ValueVT.getVectorNumElements() == 1 && 306 ValueVT.getVectorElementType() != PartVT) { 307 bool Smaller = ValueVT.bitsLE(PartVT); 308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 309 DL, ValueVT.getScalarType(), Val); 310 } 311 312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 313} 314 315 316 317 318static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 319 SDValue Val, SDValue *Parts, unsigned NumParts, 320 EVT PartVT); 321 322/// getCopyToParts - Create a series of nodes that contain the specified value 323/// split into legal parts. If the parts contain more bits than Val, then, for 324/// integers, ExtendKind can be used to specify how to generate the extra bits. 325static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 326 SDValue Val, SDValue *Parts, unsigned NumParts, 327 EVT PartVT, 328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 329 EVT ValueVT = Val.getValueType(); 330 331 // Handle the vector case separately. 332 if (ValueVT.isVector()) 333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 334 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 336 unsigned PartBits = PartVT.getSizeInBits(); 337 unsigned OrigNumParts = NumParts; 338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 339 340 if (NumParts == 0) 341 return; 342 343 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 344 if (PartVT == ValueVT) { 345 assert(NumParts == 1 && "No-op copy with multiple parts!"); 346 Parts[0] = Val; 347 return; 348 } 349 350 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 351 // If the parts cover more bits than the value has, promote the value. 352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 353 assert(NumParts == 1 && "Do not know what to promote to!"); 354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 355 } else { 356 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 357 ValueVT.isInteger() && 358 "Unknown mismatch!"); 359 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 360 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 361 if (PartVT == MVT::x86mmx) 362 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 363 } 364 } else if (PartBits == ValueVT.getSizeInBits()) { 365 // Different types of the same size. 366 assert(NumParts == 1 && PartVT != ValueVT); 367 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 368 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 369 // If the parts cover less bits than value has, truncate the value. 370 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 371 ValueVT.isInteger() && 372 "Unknown mismatch!"); 373 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 374 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 375 if (PartVT == MVT::x86mmx) 376 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 377 } 378 379 // The value may have changed - recompute ValueVT. 380 ValueVT = Val.getValueType(); 381 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 382 "Failed to tile the value with PartVT!"); 383 384 if (NumParts == 1) { 385 assert(PartVT == ValueVT && "Type conversion failed!"); 386 Parts[0] = Val; 387 return; 388 } 389 390 // Expand the value into multiple parts. 391 if (NumParts & (NumParts - 1)) { 392 // The number of parts is not a power of 2. Split off and copy the tail. 393 assert(PartVT.isInteger() && ValueVT.isInteger() && 394 "Do not know what to expand to!"); 395 unsigned RoundParts = 1 << Log2_32(NumParts); 396 unsigned RoundBits = RoundParts * PartBits; 397 unsigned OddParts = NumParts - RoundParts; 398 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 399 DAG.getIntPtrConstant(RoundBits)); 400 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 401 402 if (TLI.isBigEndian()) 403 // The odd parts were reversed by getCopyToParts - unreverse them. 404 std::reverse(Parts + RoundParts, Parts + NumParts); 405 406 NumParts = RoundParts; 407 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 408 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 409 } 410 411 // The number of parts is a power of 2. Repeatedly bisect the value using 412 // EXTRACT_ELEMENT. 413 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 414 EVT::getIntegerVT(*DAG.getContext(), 415 ValueVT.getSizeInBits()), 416 Val); 417 418 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 419 for (unsigned i = 0; i < NumParts; i += StepSize) { 420 unsigned ThisBits = StepSize * PartBits / 2; 421 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 422 SDValue &Part0 = Parts[i]; 423 SDValue &Part1 = Parts[i+StepSize/2]; 424 425 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 426 ThisVT, Part0, DAG.getIntPtrConstant(1)); 427 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 428 ThisVT, Part0, DAG.getIntPtrConstant(0)); 429 430 if (ThisBits == PartBits && ThisVT != PartVT) { 431 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 432 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 433 } 434 } 435 } 436 437 if (TLI.isBigEndian()) 438 std::reverse(Parts, Parts + OrigNumParts); 439} 440 441 442/// getCopyToPartsVector - Create a series of nodes that contain the specified 443/// value split into legal parts. 444static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 445 SDValue Val, SDValue *Parts, unsigned NumParts, 446 EVT PartVT) { 447 EVT ValueVT = Val.getValueType(); 448 assert(ValueVT.isVector() && "Not a vector"); 449 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 450 451 if (NumParts == 1) { 452 if (PartVT == ValueVT) { 453 // Nothing to do. 454 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 455 // Bitconvert vector->vector case. 456 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 457 } else if (PartVT.isVector() && 458 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 459 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 460 EVT ElementVT = PartVT.getVectorElementType(); 461 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 462 // undef elements. 463 SmallVector<SDValue, 16> Ops; 464 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 465 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 466 ElementVT, Val, DAG.getIntPtrConstant(i))); 467 468 for (unsigned i = ValueVT.getVectorNumElements(), 469 e = PartVT.getVectorNumElements(); i != e; ++i) 470 Ops.push_back(DAG.getUNDEF(ElementVT)); 471 472 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 473 474 // FIXME: Use CONCAT for 2x -> 4x. 475 476 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 477 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 478 } else if (PartVT.isVector() && 479 PartVT.getVectorElementType().bitsGE( 480 ValueVT.getVectorElementType()) && 481 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 482 483 // Promoted vector extract 484 bool Smaller = PartVT.bitsLE(ValueVT); 485 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 486 DL, PartVT, Val); 487 } else{ 488 // Vector -> scalar conversion. 489 assert(ValueVT.getVectorNumElements() == 1 && 490 "Only trivial vector-to-scalar conversions should get here!"); 491 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 492 PartVT, Val, DAG.getIntPtrConstant(0)); 493 494 bool Smaller = ValueVT.bitsLE(PartVT); 495 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 496 DL, PartVT, Val); 497 } 498 499 Parts[0] = Val; 500 return; 501 } 502 503 // Handle a multi-element vector. 504 EVT IntermediateVT, RegisterVT; 505 unsigned NumIntermediates; 506 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 507 IntermediateVT, 508 NumIntermediates, RegisterVT); 509 unsigned NumElements = ValueVT.getVectorNumElements(); 510 511 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 512 NumParts = NumRegs; // Silence a compiler warning. 513 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 514 515 // Split the vector into intermediate operands. 516 SmallVector<SDValue, 8> Ops(NumIntermediates); 517 for (unsigned i = 0; i != NumIntermediates; ++i) { 518 if (IntermediateVT.isVector()) 519 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 520 IntermediateVT, Val, 521 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 522 else 523 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 524 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 525 } 526 527 // Split the intermediate operands into legal parts. 528 if (NumParts == NumIntermediates) { 529 // If the register was not expanded, promote or copy the value, 530 // as appropriate. 531 for (unsigned i = 0; i != NumParts; ++i) 532 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 533 } else if (NumParts > 0) { 534 // If the intermediate type was expanded, split each the value into 535 // legal parts. 536 assert(NumParts % NumIntermediates == 0 && 537 "Must expand into a divisible number of parts!"); 538 unsigned Factor = NumParts / NumIntermediates; 539 for (unsigned i = 0; i != NumIntermediates; ++i) 540 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 541 } 542} 543 544 545 546 547namespace { 548 /// RegsForValue - This struct represents the registers (physical or virtual) 549 /// that a particular set of values is assigned, and the type information 550 /// about the value. The most common situation is to represent one value at a 551 /// time, but struct or array values are handled element-wise as multiple 552 /// values. The splitting of aggregates is performed recursively, so that we 553 /// never have aggregate-typed registers. The values at this point do not 554 /// necessarily have legal types, so each value may require one or more 555 /// registers of some legal type. 556 /// 557 struct RegsForValue { 558 /// ValueVTs - The value types of the values, which may not be legal, and 559 /// may need be promoted or synthesized from one or more registers. 560 /// 561 SmallVector<EVT, 4> ValueVTs; 562 563 /// RegVTs - The value types of the registers. This is the same size as 564 /// ValueVTs and it records, for each value, what the type of the assigned 565 /// register or registers are. (Individual values are never synthesized 566 /// from more than one type of register.) 567 /// 568 /// With virtual registers, the contents of RegVTs is redundant with TLI's 569 /// getRegisterType member function, however when with physical registers 570 /// it is necessary to have a separate record of the types. 571 /// 572 SmallVector<EVT, 4> RegVTs; 573 574 /// Regs - This list holds the registers assigned to the values. 575 /// Each legal or promoted value requires one register, and each 576 /// expanded value requires multiple registers. 577 /// 578 SmallVector<unsigned, 4> Regs; 579 580 RegsForValue() {} 581 582 RegsForValue(const SmallVector<unsigned, 4> ®s, 583 EVT regvt, EVT valuevt) 584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 585 586 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 587 unsigned Reg, Type *Ty) { 588 ComputeValueVTs(tli, Ty, ValueVTs); 589 590 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 591 EVT ValueVT = ValueVTs[Value]; 592 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 593 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 594 for (unsigned i = 0; i != NumRegs; ++i) 595 Regs.push_back(Reg + i); 596 RegVTs.push_back(RegisterVT); 597 Reg += NumRegs; 598 } 599 } 600 601 /// areValueTypesLegal - Return true if types of all the values are legal. 602 bool areValueTypesLegal(const TargetLowering &TLI) { 603 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 604 EVT RegisterVT = RegVTs[Value]; 605 if (!TLI.isTypeLegal(RegisterVT)) 606 return false; 607 } 608 return true; 609 } 610 611 /// append - Add the specified values to this one. 612 void append(const RegsForValue &RHS) { 613 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 614 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 615 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 616 } 617 618 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 619 /// this value and returns the result as a ValueVTs value. This uses 620 /// Chain/Flag as the input and updates them for the output Chain/Flag. 621 /// If the Flag pointer is NULL, no flag is used. 622 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 623 DebugLoc dl, 624 SDValue &Chain, SDValue *Flag) const; 625 626 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 627 /// specified value into the registers specified by this object. This uses 628 /// Chain/Flag as the input and updates them for the output Chain/Flag. 629 /// If the Flag pointer is NULL, no flag is used. 630 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 631 SDValue &Chain, SDValue *Flag) const; 632 633 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 634 /// operand list. This adds the code marker, matching input operand index 635 /// (if applicable), and includes the number of values added into it. 636 void AddInlineAsmOperands(unsigned Kind, 637 bool HasMatching, unsigned MatchingIdx, 638 SelectionDAG &DAG, 639 std::vector<SDValue> &Ops) const; 640 }; 641} 642 643/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 644/// this value and returns the result as a ValueVT value. This uses 645/// Chain/Flag as the input and updates them for the output Chain/Flag. 646/// If the Flag pointer is NULL, no flag is used. 647SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 648 FunctionLoweringInfo &FuncInfo, 649 DebugLoc dl, 650 SDValue &Chain, SDValue *Flag) const { 651 // A Value with type {} or [0 x %t] needs no registers. 652 if (ValueVTs.empty()) 653 return SDValue(); 654 655 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 656 657 // Assemble the legal parts into the final values. 658 SmallVector<SDValue, 4> Values(ValueVTs.size()); 659 SmallVector<SDValue, 8> Parts; 660 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 661 // Copy the legal parts from the registers. 662 EVT ValueVT = ValueVTs[Value]; 663 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 664 EVT RegisterVT = RegVTs[Value]; 665 666 Parts.resize(NumRegs); 667 for (unsigned i = 0; i != NumRegs; ++i) { 668 SDValue P; 669 if (Flag == 0) { 670 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 671 } else { 672 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 673 *Flag = P.getValue(2); 674 } 675 676 Chain = P.getValue(1); 677 Parts[i] = P; 678 679 // If the source register was virtual and if we know something about it, 680 // add an assert node. 681 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 682 !RegisterVT.isInteger() || RegisterVT.isVector()) 683 continue; 684 685 const FunctionLoweringInfo::LiveOutInfo *LOI = 686 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 687 if (!LOI) 688 continue; 689 690 unsigned RegSize = RegisterVT.getSizeInBits(); 691 unsigned NumSignBits = LOI->NumSignBits; 692 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 693 694 // FIXME: We capture more information than the dag can represent. For 695 // now, just use the tightest assertzext/assertsext possible. 696 bool isSExt = true; 697 EVT FromVT(MVT::Other); 698 if (NumSignBits == RegSize) 699 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 700 else if (NumZeroBits >= RegSize-1) 701 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 702 else if (NumSignBits > RegSize-8) 703 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 704 else if (NumZeroBits >= RegSize-8) 705 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 706 else if (NumSignBits > RegSize-16) 707 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 708 else if (NumZeroBits >= RegSize-16) 709 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 710 else if (NumSignBits > RegSize-32) 711 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 712 else if (NumZeroBits >= RegSize-32) 713 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 714 else 715 continue; 716 717 // Add an assertion node. 718 assert(FromVT != MVT::Other); 719 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 720 RegisterVT, P, DAG.getValueType(FromVT)); 721 } 722 723 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 724 NumRegs, RegisterVT, ValueVT); 725 Part += NumRegs; 726 Parts.clear(); 727 } 728 729 return DAG.getNode(ISD::MERGE_VALUES, dl, 730 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 731 &Values[0], ValueVTs.size()); 732} 733 734/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 735/// specified value into the registers specified by this object. This uses 736/// Chain/Flag as the input and updates them for the output Chain/Flag. 737/// If the Flag pointer is NULL, no flag is used. 738void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 739 SDValue &Chain, SDValue *Flag) const { 740 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 741 742 // Get the list of the values's legal parts. 743 unsigned NumRegs = Regs.size(); 744 SmallVector<SDValue, 8> Parts(NumRegs); 745 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 746 EVT ValueVT = ValueVTs[Value]; 747 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 748 EVT RegisterVT = RegVTs[Value]; 749 750 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 751 &Parts[Part], NumParts, RegisterVT); 752 Part += NumParts; 753 } 754 755 // Copy the parts into the registers. 756 SmallVector<SDValue, 8> Chains(NumRegs); 757 for (unsigned i = 0; i != NumRegs; ++i) { 758 SDValue Part; 759 if (Flag == 0) { 760 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 761 } else { 762 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 763 *Flag = Part.getValue(1); 764 } 765 766 Chains[i] = Part.getValue(0); 767 } 768 769 if (NumRegs == 1 || Flag) 770 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 771 // flagged to it. That is the CopyToReg nodes and the user are considered 772 // a single scheduling unit. If we create a TokenFactor and return it as 773 // chain, then the TokenFactor is both a predecessor (operand) of the 774 // user as well as a successor (the TF operands are flagged to the user). 775 // c1, f1 = CopyToReg 776 // c2, f2 = CopyToReg 777 // c3 = TokenFactor c1, c2 778 // ... 779 // = op c3, ..., f2 780 Chain = Chains[NumRegs-1]; 781 else 782 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 783} 784 785/// AddInlineAsmOperands - Add this value to the specified inlineasm node 786/// operand list. This adds the code marker and includes the number of 787/// values added into it. 788void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 789 unsigned MatchingIdx, 790 SelectionDAG &DAG, 791 std::vector<SDValue> &Ops) const { 792 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 793 794 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 795 if (HasMatching) 796 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 797 else if (!Regs.empty() && 798 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 799 // Put the register class of the virtual registers in the flag word. That 800 // way, later passes can recompute register class constraints for inline 801 // assembly as well as normal instructions. 802 // Don't do this for tied operands that can use the regclass information 803 // from the def. 804 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 805 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 806 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 807 } 808 809 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 810 Ops.push_back(Res); 811 812 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 813 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 814 EVT RegisterVT = RegVTs[Value]; 815 for (unsigned i = 0; i != NumRegs; ++i) { 816 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 817 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 818 } 819 } 820} 821 822void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 823 const TargetLibraryInfo *li) { 824 AA = &aa; 825 GFI = gfi; 826 LibInfo = li; 827 TD = DAG.getTarget().getTargetData(); 828 Context = DAG.getContext(); 829 LPadToCallSiteMap.clear(); 830} 831 832/// clear - Clear out the current SelectionDAG and the associated 833/// state and prepare this SelectionDAGBuilder object to be used 834/// for a new block. This doesn't clear out information about 835/// additional blocks that are needed to complete switch lowering 836/// or PHI node updating; that information is cleared out as it is 837/// consumed. 838void SelectionDAGBuilder::clear() { 839 NodeMap.clear(); 840 UnusedArgNodeMap.clear(); 841 PendingLoads.clear(); 842 PendingExports.clear(); 843 CurDebugLoc = DebugLoc(); 844 HasTailCall = false; 845} 846 847/// clearDanglingDebugInfo - Clear the dangling debug information 848/// map. This function is separated from the clear so that debug 849/// information that is dangling in a basic block can be properly 850/// resolved in a different basic block. This allows the 851/// SelectionDAG to resolve dangling debug information attached 852/// to PHI nodes. 853void SelectionDAGBuilder::clearDanglingDebugInfo() { 854 DanglingDebugInfoMap.clear(); 855} 856 857/// getRoot - Return the current virtual root of the Selection DAG, 858/// flushing any PendingLoad items. This must be done before emitting 859/// a store or any other node that may need to be ordered after any 860/// prior load instructions. 861/// 862SDValue SelectionDAGBuilder::getRoot() { 863 if (PendingLoads.empty()) 864 return DAG.getRoot(); 865 866 if (PendingLoads.size() == 1) { 867 SDValue Root = PendingLoads[0]; 868 DAG.setRoot(Root); 869 PendingLoads.clear(); 870 return Root; 871 } 872 873 // Otherwise, we have to make a token factor node. 874 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 875 &PendingLoads[0], PendingLoads.size()); 876 PendingLoads.clear(); 877 DAG.setRoot(Root); 878 return Root; 879} 880 881/// getControlRoot - Similar to getRoot, but instead of flushing all the 882/// PendingLoad items, flush all the PendingExports items. It is necessary 883/// to do this before emitting a terminator instruction. 884/// 885SDValue SelectionDAGBuilder::getControlRoot() { 886 SDValue Root = DAG.getRoot(); 887 888 if (PendingExports.empty()) 889 return Root; 890 891 // Turn all of the CopyToReg chains into one factored node. 892 if (Root.getOpcode() != ISD::EntryToken) { 893 unsigned i = 0, e = PendingExports.size(); 894 for (; i != e; ++i) { 895 assert(PendingExports[i].getNode()->getNumOperands() > 1); 896 if (PendingExports[i].getNode()->getOperand(0) == Root) 897 break; // Don't add the root if we already indirectly depend on it. 898 } 899 900 if (i == e) 901 PendingExports.push_back(Root); 902 } 903 904 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 905 &PendingExports[0], 906 PendingExports.size()); 907 PendingExports.clear(); 908 DAG.setRoot(Root); 909 return Root; 910} 911 912void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 913 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 914 DAG.AssignOrdering(Node, SDNodeOrder); 915 916 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 917 AssignOrderingToNode(Node->getOperand(I).getNode()); 918} 919 920void SelectionDAGBuilder::visit(const Instruction &I) { 921 // Set up outgoing PHI node register values before emitting the terminator. 922 if (isa<TerminatorInst>(&I)) 923 HandlePHINodesInSuccessorBlocks(I.getParent()); 924 925 CurDebugLoc = I.getDebugLoc(); 926 927 visit(I.getOpcode(), I); 928 929 if (!isa<TerminatorInst>(&I) && !HasTailCall) 930 CopyToExportRegsIfNeeded(&I); 931 932 CurDebugLoc = DebugLoc(); 933} 934 935void SelectionDAGBuilder::visitPHI(const PHINode &) { 936 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 937} 938 939void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 940 // Note: this doesn't use InstVisitor, because it has to work with 941 // ConstantExpr's in addition to instructions. 942 switch (Opcode) { 943 default: llvm_unreachable("Unknown instruction type encountered!"); 944 // Build the switch statement using the Instruction.def file. 945#define HANDLE_INST(NUM, OPCODE, CLASS) \ 946 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break; 947#include "llvm/Instruction.def" 948 } 949 950 // Assign the ordering to the freshly created DAG nodes. 951 if (NodeMap.count(&I)) { 952 ++SDNodeOrder; 953 AssignOrderingToNode(getValue(&I).getNode()); 954 } 955} 956 957// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 958// generate the debug data structures now that we've seen its definition. 959void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 960 SDValue Val) { 961 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 962 if (DDI.getDI()) { 963 const DbgValueInst *DI = DDI.getDI(); 964 DebugLoc dl = DDI.getdl(); 965 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 966 MDNode *Variable = DI->getVariable(); 967 uint64_t Offset = DI->getOffset(); 968 SDDbgValue *SDV; 969 if (Val.getNode()) { 970 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 971 SDV = DAG.getDbgValue(Variable, Val.getNode(), 972 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 973 DAG.AddDbgValue(SDV, Val.getNode(), false); 974 } 975 } else 976 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 977 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 978 } 979} 980 981/// getValue - Return an SDValue for the given Value. 982SDValue SelectionDAGBuilder::getValue(const Value *V) { 983 // If we already have an SDValue for this value, use it. It's important 984 // to do this first, so that we don't create a CopyFromReg if we already 985 // have a regular SDValue. 986 SDValue &N = NodeMap[V]; 987 if (N.getNode()) return N; 988 989 // If there's a virtual register allocated and initialized for this 990 // value, use it. 991 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 992 if (It != FuncInfo.ValueMap.end()) { 993 unsigned InReg = It->second; 994 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 995 SDValue Chain = DAG.getEntryNode(); 996 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 997 resolveDanglingDebugInfo(V, N); 998 return N; 999 } 1000 1001 // Otherwise create a new SDValue and remember it. 1002 SDValue Val = getValueImpl(V); 1003 NodeMap[V] = Val; 1004 resolveDanglingDebugInfo(V, Val); 1005 return Val; 1006} 1007 1008/// getNonRegisterValue - Return an SDValue for the given Value, but 1009/// don't look in FuncInfo.ValueMap for a virtual register. 1010SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1011 // If we already have an SDValue for this value, use it. 1012 SDValue &N = NodeMap[V]; 1013 if (N.getNode()) return N; 1014 1015 // Otherwise create a new SDValue and remember it. 1016 SDValue Val = getValueImpl(V); 1017 NodeMap[V] = Val; 1018 resolveDanglingDebugInfo(V, Val); 1019 return Val; 1020} 1021 1022/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1023/// Create an SDValue for the given value. 1024SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1025 if (const Constant *C = dyn_cast<Constant>(V)) { 1026 EVT VT = TLI.getValueType(V->getType(), true); 1027 1028 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1029 return DAG.getConstant(*CI, VT); 1030 1031 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1032 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1033 1034 if (isa<ConstantPointerNull>(C)) 1035 return DAG.getConstant(0, TLI.getPointerTy()); 1036 1037 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1038 return DAG.getConstantFP(*CFP, VT); 1039 1040 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1041 return DAG.getUNDEF(VT); 1042 1043 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1044 visit(CE->getOpcode(), *CE); 1045 SDValue N1 = NodeMap[V]; 1046 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1047 return N1; 1048 } 1049 1050 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1051 SmallVector<SDValue, 4> Constants; 1052 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1053 OI != OE; ++OI) { 1054 SDNode *Val = getValue(*OI).getNode(); 1055 // If the operand is an empty aggregate, there are no values. 1056 if (!Val) continue; 1057 // Add each leaf value from the operand to the Constants list 1058 // to form a flattened list of all the values. 1059 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1060 Constants.push_back(SDValue(Val, i)); 1061 } 1062 1063 return DAG.getMergeValues(&Constants[0], Constants.size(), 1064 getCurDebugLoc()); 1065 } 1066 1067 if (const ConstantDataSequential *CDS = 1068 dyn_cast<ConstantDataSequential>(C)) { 1069 SmallVector<SDValue, 4> Ops; 1070 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { 1071 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1072 // Add each leaf value from the operand to the Constants list 1073 // to form a flattened list of all the values. 1074 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1075 Ops.push_back(SDValue(Val, i)); 1076 } 1077 1078 if (isa<ArrayType>(CDS->getType())) 1079 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc()); 1080 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1081 VT, &Ops[0], Ops.size()); 1082 } 1083 1084 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1085 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1086 "Unknown struct or array constant!"); 1087 1088 SmallVector<EVT, 4> ValueVTs; 1089 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1090 unsigned NumElts = ValueVTs.size(); 1091 if (NumElts == 0) 1092 return SDValue(); // empty struct 1093 SmallVector<SDValue, 4> Constants(NumElts); 1094 for (unsigned i = 0; i != NumElts; ++i) { 1095 EVT EltVT = ValueVTs[i]; 1096 if (isa<UndefValue>(C)) 1097 Constants[i] = DAG.getUNDEF(EltVT); 1098 else if (EltVT.isFloatingPoint()) 1099 Constants[i] = DAG.getConstantFP(0, EltVT); 1100 else 1101 Constants[i] = DAG.getConstant(0, EltVT); 1102 } 1103 1104 return DAG.getMergeValues(&Constants[0], NumElts, 1105 getCurDebugLoc()); 1106 } 1107 1108 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1109 return DAG.getBlockAddress(BA, VT); 1110 1111 VectorType *VecTy = cast<VectorType>(V->getType()); 1112 unsigned NumElements = VecTy->getNumElements(); 1113 1114 // Now that we know the number and type of the elements, get that number of 1115 // elements into the Ops array based on what kind of constant it is. 1116 SmallVector<SDValue, 16> Ops; 1117 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1118 for (unsigned i = 0; i != NumElements; ++i) 1119 Ops.push_back(getValue(CV->getOperand(i))); 1120 } else { 1121 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1122 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1123 1124 SDValue Op; 1125 if (EltVT.isFloatingPoint()) 1126 Op = DAG.getConstantFP(0, EltVT); 1127 else 1128 Op = DAG.getConstant(0, EltVT); 1129 Ops.assign(NumElements, Op); 1130 } 1131 1132 // Create a BUILD_VECTOR node. 1133 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1134 VT, &Ops[0], Ops.size()); 1135 } 1136 1137 // If this is a static alloca, generate it as the frameindex instead of 1138 // computation. 1139 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1140 DenseMap<const AllocaInst*, int>::iterator SI = 1141 FuncInfo.StaticAllocaMap.find(AI); 1142 if (SI != FuncInfo.StaticAllocaMap.end()) 1143 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1144 } 1145 1146 // If this is an instruction which fast-isel has deferred, select it now. 1147 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1148 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1149 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1150 SDValue Chain = DAG.getEntryNode(); 1151 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1152 } 1153 1154 llvm_unreachable("Can't get register for value!"); 1155} 1156 1157void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1158 SDValue Chain = getControlRoot(); 1159 SmallVector<ISD::OutputArg, 8> Outs; 1160 SmallVector<SDValue, 8> OutVals; 1161 1162 if (!FuncInfo.CanLowerReturn) { 1163 unsigned DemoteReg = FuncInfo.DemoteRegister; 1164 const Function *F = I.getParent()->getParent(); 1165 1166 // Emit a store of the return value through the virtual register. 1167 // Leave Outs empty so that LowerReturn won't try to load return 1168 // registers the usual way. 1169 SmallVector<EVT, 1> PtrValueVTs; 1170 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1171 PtrValueVTs); 1172 1173 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1174 SDValue RetOp = getValue(I.getOperand(0)); 1175 1176 SmallVector<EVT, 4> ValueVTs; 1177 SmallVector<uint64_t, 4> Offsets; 1178 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1179 unsigned NumValues = ValueVTs.size(); 1180 1181 SmallVector<SDValue, 4> Chains(NumValues); 1182 for (unsigned i = 0; i != NumValues; ++i) { 1183 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1184 RetPtr.getValueType(), RetPtr, 1185 DAG.getIntPtrConstant(Offsets[i])); 1186 Chains[i] = 1187 DAG.getStore(Chain, getCurDebugLoc(), 1188 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1189 // FIXME: better loc info would be nice. 1190 Add, MachinePointerInfo(), false, false, 0); 1191 } 1192 1193 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1194 MVT::Other, &Chains[0], NumValues); 1195 } else if (I.getNumOperands() != 0) { 1196 SmallVector<EVT, 4> ValueVTs; 1197 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1198 unsigned NumValues = ValueVTs.size(); 1199 if (NumValues) { 1200 SDValue RetOp = getValue(I.getOperand(0)); 1201 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1202 EVT VT = ValueVTs[j]; 1203 1204 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1205 1206 const Function *F = I.getParent()->getParent(); 1207 if (F->paramHasAttr(0, Attribute::SExt)) 1208 ExtendKind = ISD::SIGN_EXTEND; 1209 else if (F->paramHasAttr(0, Attribute::ZExt)) 1210 ExtendKind = ISD::ZERO_EXTEND; 1211 1212 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1213 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1214 1215 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1216 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1217 SmallVector<SDValue, 4> Parts(NumParts); 1218 getCopyToParts(DAG, getCurDebugLoc(), 1219 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1220 &Parts[0], NumParts, PartVT, ExtendKind); 1221 1222 // 'inreg' on function refers to return value 1223 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1224 if (F->paramHasAttr(0, Attribute::InReg)) 1225 Flags.setInReg(); 1226 1227 // Propagate extension type if any 1228 if (ExtendKind == ISD::SIGN_EXTEND) 1229 Flags.setSExt(); 1230 else if (ExtendKind == ISD::ZERO_EXTEND) 1231 Flags.setZExt(); 1232 1233 for (unsigned i = 0; i < NumParts; ++i) { 1234 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1235 /*isfixed=*/true)); 1236 OutVals.push_back(Parts[i]); 1237 } 1238 } 1239 } 1240 } 1241 1242 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1243 CallingConv::ID CallConv = 1244 DAG.getMachineFunction().getFunction()->getCallingConv(); 1245 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1246 Outs, OutVals, getCurDebugLoc(), DAG); 1247 1248 // Verify that the target's LowerReturn behaved as expected. 1249 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1250 "LowerReturn didn't return a valid chain!"); 1251 1252 // Update the DAG with the new chain value resulting from return lowering. 1253 DAG.setRoot(Chain); 1254} 1255 1256/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1257/// created for it, emit nodes to copy the value into the virtual 1258/// registers. 1259void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1260 // Skip empty types 1261 if (V->getType()->isEmptyTy()) 1262 return; 1263 1264 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1265 if (VMI != FuncInfo.ValueMap.end()) { 1266 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1267 CopyValueToVirtualRegister(V, VMI->second); 1268 } 1269} 1270 1271/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1272/// the current basic block, add it to ValueMap now so that we'll get a 1273/// CopyTo/FromReg. 1274void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1275 // No need to export constants. 1276 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1277 1278 // Already exported? 1279 if (FuncInfo.isExportedInst(V)) return; 1280 1281 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1282 CopyValueToVirtualRegister(V, Reg); 1283} 1284 1285bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1286 const BasicBlock *FromBB) { 1287 // The operands of the setcc have to be in this block. We don't know 1288 // how to export them from some other block. 1289 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1290 // Can export from current BB. 1291 if (VI->getParent() == FromBB) 1292 return true; 1293 1294 // Is already exported, noop. 1295 return FuncInfo.isExportedInst(V); 1296 } 1297 1298 // If this is an argument, we can export it if the BB is the entry block or 1299 // if it is already exported. 1300 if (isa<Argument>(V)) { 1301 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1302 return true; 1303 1304 // Otherwise, can only export this if it is already exported. 1305 return FuncInfo.isExportedInst(V); 1306 } 1307 1308 // Otherwise, constants can always be exported. 1309 return true; 1310} 1311 1312/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1313uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1314 const MachineBasicBlock *Dst) const { 1315 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1316 if (!BPI) 1317 return 0; 1318 const BasicBlock *SrcBB = Src->getBasicBlock(); 1319 const BasicBlock *DstBB = Dst->getBasicBlock(); 1320 return BPI->getEdgeWeight(SrcBB, DstBB); 1321} 1322 1323void SelectionDAGBuilder:: 1324addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1325 uint32_t Weight /* = 0 */) { 1326 if (!Weight) 1327 Weight = getEdgeWeight(Src, Dst); 1328 Src->addSuccessor(Dst, Weight); 1329} 1330 1331 1332static bool InBlock(const Value *V, const BasicBlock *BB) { 1333 if (const Instruction *I = dyn_cast<Instruction>(V)) 1334 return I->getParent() == BB; 1335 return true; 1336} 1337 1338/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1339/// This function emits a branch and is used at the leaves of an OR or an 1340/// AND operator tree. 1341/// 1342void 1343SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1344 MachineBasicBlock *TBB, 1345 MachineBasicBlock *FBB, 1346 MachineBasicBlock *CurBB, 1347 MachineBasicBlock *SwitchBB) { 1348 const BasicBlock *BB = CurBB->getBasicBlock(); 1349 1350 // If the leaf of the tree is a comparison, merge the condition into 1351 // the caseblock. 1352 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1353 // The operands of the cmp have to be in this block. We don't know 1354 // how to export them from some other block. If this is the first block 1355 // of the sequence, no exporting is needed. 1356 if (CurBB == SwitchBB || 1357 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1358 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1359 ISD::CondCode Condition; 1360 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1361 Condition = getICmpCondCode(IC->getPredicate()); 1362 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1363 Condition = getFCmpCondCode(FC->getPredicate()); 1364 if (TM.Options.NoNaNsFPMath) 1365 Condition = getFCmpCodeWithoutNaN(Condition); 1366 } else { 1367 Condition = ISD::SETEQ; // silence warning. 1368 llvm_unreachable("Unknown compare instruction"); 1369 } 1370 1371 CaseBlock CB(Condition, BOp->getOperand(0), 1372 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1373 SwitchCases.push_back(CB); 1374 return; 1375 } 1376 } 1377 1378 // Create a CaseBlock record representing this branch. 1379 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1380 NULL, TBB, FBB, CurBB); 1381 SwitchCases.push_back(CB); 1382} 1383 1384/// FindMergedConditions - If Cond is an expression like 1385void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1386 MachineBasicBlock *TBB, 1387 MachineBasicBlock *FBB, 1388 MachineBasicBlock *CurBB, 1389 MachineBasicBlock *SwitchBB, 1390 unsigned Opc) { 1391 // If this node is not part of the or/and tree, emit it as a branch. 1392 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1393 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1394 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1395 BOp->getParent() != CurBB->getBasicBlock() || 1396 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1397 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1398 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1399 return; 1400 } 1401 1402 // Create TmpBB after CurBB. 1403 MachineFunction::iterator BBI = CurBB; 1404 MachineFunction &MF = DAG.getMachineFunction(); 1405 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1406 CurBB->getParent()->insert(++BBI, TmpBB); 1407 1408 if (Opc == Instruction::Or) { 1409 // Codegen X | Y as: 1410 // jmp_if_X TBB 1411 // jmp TmpBB 1412 // TmpBB: 1413 // jmp_if_Y TBB 1414 // jmp FBB 1415 // 1416 1417 // Emit the LHS condition. 1418 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1419 1420 // Emit the RHS condition into TmpBB. 1421 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1422 } else { 1423 assert(Opc == Instruction::And && "Unknown merge op!"); 1424 // Codegen X & Y as: 1425 // jmp_if_X TmpBB 1426 // jmp FBB 1427 // TmpBB: 1428 // jmp_if_Y TBB 1429 // jmp FBB 1430 // 1431 // This requires creation of TmpBB after CurBB. 1432 1433 // Emit the LHS condition. 1434 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1435 1436 // Emit the RHS condition into TmpBB. 1437 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1438 } 1439} 1440 1441/// If the set of cases should be emitted as a series of branches, return true. 1442/// If we should emit this as a bunch of and/or'd together conditions, return 1443/// false. 1444bool 1445SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1446 if (Cases.size() != 2) return true; 1447 1448 // If this is two comparisons of the same values or'd or and'd together, they 1449 // will get folded into a single comparison, so don't emit two blocks. 1450 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1451 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1452 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1453 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1454 return false; 1455 } 1456 1457 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1458 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1459 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1460 Cases[0].CC == Cases[1].CC && 1461 isa<Constant>(Cases[0].CmpRHS) && 1462 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1463 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1464 return false; 1465 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1466 return false; 1467 } 1468 1469 return true; 1470} 1471 1472void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1473 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1474 1475 // Update machine-CFG edges. 1476 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1477 1478 // Figure out which block is immediately after the current one. 1479 MachineBasicBlock *NextBlock = 0; 1480 MachineFunction::iterator BBI = BrMBB; 1481 if (++BBI != FuncInfo.MF->end()) 1482 NextBlock = BBI; 1483 1484 if (I.isUnconditional()) { 1485 // Update machine-CFG edges. 1486 BrMBB->addSuccessor(Succ0MBB); 1487 1488 // If this is not a fall-through branch, emit the branch. 1489 if (Succ0MBB != NextBlock) 1490 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1491 MVT::Other, getControlRoot(), 1492 DAG.getBasicBlock(Succ0MBB))); 1493 1494 return; 1495 } 1496 1497 // If this condition is one of the special cases we handle, do special stuff 1498 // now. 1499 const Value *CondVal = I.getCondition(); 1500 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1501 1502 // If this is a series of conditions that are or'd or and'd together, emit 1503 // this as a sequence of branches instead of setcc's with and/or operations. 1504 // As long as jumps are not expensive, this should improve performance. 1505 // For example, instead of something like: 1506 // cmp A, B 1507 // C = seteq 1508 // cmp D, E 1509 // F = setle 1510 // or C, F 1511 // jnz foo 1512 // Emit: 1513 // cmp A, B 1514 // je foo 1515 // cmp D, E 1516 // jle foo 1517 // 1518 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1519 if (!TLI.isJumpExpensive() && 1520 BOp->hasOneUse() && 1521 (BOp->getOpcode() == Instruction::And || 1522 BOp->getOpcode() == Instruction::Or)) { 1523 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1524 BOp->getOpcode()); 1525 // If the compares in later blocks need to use values not currently 1526 // exported from this block, export them now. This block should always 1527 // be the first entry. 1528 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1529 1530 // Allow some cases to be rejected. 1531 if (ShouldEmitAsBranches(SwitchCases)) { 1532 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1533 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1534 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1535 } 1536 1537 // Emit the branch for this block. 1538 visitSwitchCase(SwitchCases[0], BrMBB); 1539 SwitchCases.erase(SwitchCases.begin()); 1540 return; 1541 } 1542 1543 // Okay, we decided not to do this, remove any inserted MBB's and clear 1544 // SwitchCases. 1545 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1546 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1547 1548 SwitchCases.clear(); 1549 } 1550 } 1551 1552 // Create a CaseBlock record representing this branch. 1553 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1554 NULL, Succ0MBB, Succ1MBB, BrMBB); 1555 1556 // Use visitSwitchCase to actually insert the fast branch sequence for this 1557 // cond branch. 1558 visitSwitchCase(CB, BrMBB); 1559} 1560 1561/// visitSwitchCase - Emits the necessary code to represent a single node in 1562/// the binary search tree resulting from lowering a switch instruction. 1563void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1564 MachineBasicBlock *SwitchBB) { 1565 SDValue Cond; 1566 SDValue CondLHS = getValue(CB.CmpLHS); 1567 DebugLoc dl = getCurDebugLoc(); 1568 1569 // Build the setcc now. 1570 if (CB.CmpMHS == NULL) { 1571 // Fold "(X == true)" to X and "(X == false)" to !X to 1572 // handle common cases produced by branch lowering. 1573 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1574 CB.CC == ISD::SETEQ) 1575 Cond = CondLHS; 1576 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1577 CB.CC == ISD::SETEQ) { 1578 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1579 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1580 } else 1581 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1582 } else { 1583 assert(CB.CC == ISD::SETCC_INVALID && 1584 "Condition is undefined for to-the-range belonging check."); 1585 1586 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1587 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1588 1589 SDValue CmpOp = getValue(CB.CmpMHS); 1590 EVT VT = CmpOp.getValueType(); 1591 1592 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) { 1593 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1594 ISD::SETULE); 1595 } else { 1596 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1597 VT, CmpOp, DAG.getConstant(Low, VT)); 1598 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1599 DAG.getConstant(High-Low, VT), ISD::SETULE); 1600 } 1601 } 1602 1603 // Update successor info 1604 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1605 // TrueBB and FalseBB are always different unless the incoming IR is 1606 // degenerate. This only happens when running llc on weird IR. 1607 if (CB.TrueBB != CB.FalseBB) 1608 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1609 1610 // Set NextBlock to be the MBB immediately after the current one, if any. 1611 // This is used to avoid emitting unnecessary branches to the next block. 1612 MachineBasicBlock *NextBlock = 0; 1613 MachineFunction::iterator BBI = SwitchBB; 1614 if (++BBI != FuncInfo.MF->end()) 1615 NextBlock = BBI; 1616 1617 // If the lhs block is the next block, invert the condition so that we can 1618 // fall through to the lhs instead of the rhs block. 1619 if (CB.TrueBB == NextBlock) { 1620 std::swap(CB.TrueBB, CB.FalseBB); 1621 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1622 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1623 } 1624 1625 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1626 MVT::Other, getControlRoot(), Cond, 1627 DAG.getBasicBlock(CB.TrueBB)); 1628 1629 // Insert the false branch. Do this even if it's a fall through branch, 1630 // this makes it easier to do DAG optimizations which require inverting 1631 // the branch condition. 1632 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1633 DAG.getBasicBlock(CB.FalseBB)); 1634 1635 DAG.setRoot(BrCond); 1636} 1637 1638/// visitJumpTable - Emit JumpTable node in the current MBB 1639void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1640 // Emit the code for the jump table 1641 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1642 EVT PTy = TLI.getPointerTy(); 1643 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1644 JT.Reg, PTy); 1645 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1646 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1647 MVT::Other, Index.getValue(1), 1648 Table, Index); 1649 DAG.setRoot(BrJumpTable); 1650} 1651 1652/// visitJumpTableHeader - This function emits necessary code to produce index 1653/// in the JumpTable from switch case. 1654void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1655 JumpTableHeader &JTH, 1656 MachineBasicBlock *SwitchBB) { 1657 // Subtract the lowest switch case value from the value being switched on and 1658 // conditional branch to default mbb if the result is greater than the 1659 // difference between smallest and largest cases. 1660 SDValue SwitchOp = getValue(JTH.SValue); 1661 EVT VT = SwitchOp.getValueType(); 1662 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1663 DAG.getConstant(JTH.First, VT)); 1664 1665 // The SDNode we just created, which holds the value being switched on minus 1666 // the smallest case value, needs to be copied to a virtual register so it 1667 // can be used as an index into the jump table in a subsequent basic block. 1668 // This value may be smaller or larger than the target's pointer type, and 1669 // therefore require extension or truncating. 1670 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1671 1672 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1673 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1674 JumpTableReg, SwitchOp); 1675 JT.Reg = JumpTableReg; 1676 1677 // Emit the range check for the jump table, and branch to the default block 1678 // for the switch statement if the value being switched on exceeds the largest 1679 // case in the switch. 1680 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1681 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1682 DAG.getConstant(JTH.Last-JTH.First,VT), 1683 ISD::SETUGT); 1684 1685 // Set NextBlock to be the MBB immediately after the current one, if any. 1686 // This is used to avoid emitting unnecessary branches to the next block. 1687 MachineBasicBlock *NextBlock = 0; 1688 MachineFunction::iterator BBI = SwitchBB; 1689 1690 if (++BBI != FuncInfo.MF->end()) 1691 NextBlock = BBI; 1692 1693 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1694 MVT::Other, CopyTo, CMP, 1695 DAG.getBasicBlock(JT.Default)); 1696 1697 if (JT.MBB != NextBlock) 1698 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1699 DAG.getBasicBlock(JT.MBB)); 1700 1701 DAG.setRoot(BrCond); 1702} 1703 1704/// visitBitTestHeader - This function emits necessary code to produce value 1705/// suitable for "bit tests" 1706void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1707 MachineBasicBlock *SwitchBB) { 1708 // Subtract the minimum value 1709 SDValue SwitchOp = getValue(B.SValue); 1710 EVT VT = SwitchOp.getValueType(); 1711 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1712 DAG.getConstant(B.First, VT)); 1713 1714 // Check range 1715 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1716 TLI.getSetCCResultType(Sub.getValueType()), 1717 Sub, DAG.getConstant(B.Range, VT), 1718 ISD::SETUGT); 1719 1720 // Determine the type of the test operands. 1721 bool UsePtrType = false; 1722 if (!TLI.isTypeLegal(VT)) 1723 UsePtrType = true; 1724 else { 1725 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1726 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1727 // Switch table case range are encoded into series of masks. 1728 // Just use pointer type, it's guaranteed to fit. 1729 UsePtrType = true; 1730 break; 1731 } 1732 } 1733 if (UsePtrType) { 1734 VT = TLI.getPointerTy(); 1735 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1736 } 1737 1738 B.RegVT = VT; 1739 B.Reg = FuncInfo.CreateReg(VT); 1740 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1741 B.Reg, Sub); 1742 1743 // Set NextBlock to be the MBB immediately after the current one, if any. 1744 // This is used to avoid emitting unnecessary branches to the next block. 1745 MachineBasicBlock *NextBlock = 0; 1746 MachineFunction::iterator BBI = SwitchBB; 1747 if (++BBI != FuncInfo.MF->end()) 1748 NextBlock = BBI; 1749 1750 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1751 1752 addSuccessorWithWeight(SwitchBB, B.Default); 1753 addSuccessorWithWeight(SwitchBB, MBB); 1754 1755 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1756 MVT::Other, CopyTo, RangeCmp, 1757 DAG.getBasicBlock(B.Default)); 1758 1759 if (MBB != NextBlock) 1760 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1761 DAG.getBasicBlock(MBB)); 1762 1763 DAG.setRoot(BrRange); 1764} 1765 1766/// visitBitTestCase - this function produces one "bit test" 1767void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1768 MachineBasicBlock* NextMBB, 1769 uint32_t BranchWeightToNext, 1770 unsigned Reg, 1771 BitTestCase &B, 1772 MachineBasicBlock *SwitchBB) { 1773 EVT VT = BB.RegVT; 1774 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1775 Reg, VT); 1776 SDValue Cmp; 1777 unsigned PopCount = CountPopulation_64(B.Mask); 1778 if (PopCount == 1) { 1779 // Testing for a single bit; just compare the shift count with what it 1780 // would need to be to shift a 1 bit in that position. 1781 Cmp = DAG.getSetCC(getCurDebugLoc(), 1782 TLI.getSetCCResultType(VT), 1783 ShiftOp, 1784 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1785 ISD::SETEQ); 1786 } else if (PopCount == BB.Range) { 1787 // There is only one zero bit in the range, test for it directly. 1788 Cmp = DAG.getSetCC(getCurDebugLoc(), 1789 TLI.getSetCCResultType(VT), 1790 ShiftOp, 1791 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1792 ISD::SETNE); 1793 } else { 1794 // Make desired shift 1795 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1796 DAG.getConstant(1, VT), ShiftOp); 1797 1798 // Emit bit tests and jumps 1799 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1800 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1801 Cmp = DAG.getSetCC(getCurDebugLoc(), 1802 TLI.getSetCCResultType(VT), 1803 AndOp, DAG.getConstant(0, VT), 1804 ISD::SETNE); 1805 } 1806 1807 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight. 1808 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight); 1809 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext. 1810 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext); 1811 1812 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1813 MVT::Other, getControlRoot(), 1814 Cmp, DAG.getBasicBlock(B.TargetBB)); 1815 1816 // Set NextBlock to be the MBB immediately after the current one, if any. 1817 // This is used to avoid emitting unnecessary branches to the next block. 1818 MachineBasicBlock *NextBlock = 0; 1819 MachineFunction::iterator BBI = SwitchBB; 1820 if (++BBI != FuncInfo.MF->end()) 1821 NextBlock = BBI; 1822 1823 if (NextMBB != NextBlock) 1824 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1825 DAG.getBasicBlock(NextMBB)); 1826 1827 DAG.setRoot(BrAnd); 1828} 1829 1830void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1831 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1832 1833 // Retrieve successors. 1834 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1835 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1836 1837 const Value *Callee(I.getCalledValue()); 1838 const Function *Fn = dyn_cast<Function>(Callee); 1839 if (isa<InlineAsm>(Callee)) 1840 visitInlineAsm(&I); 1841 else if (Fn && Fn->isIntrinsic()) { 1842 assert(Fn->getIntrinsicID() == Intrinsic::donothing); 1843 // Ignore invokes to @llvm.donothing: jump directly to the next BB. 1844 } else 1845 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1846 1847 // If the value of the invoke is used outside of its defining block, make it 1848 // available as a virtual register. 1849 CopyToExportRegsIfNeeded(&I); 1850 1851 // Update successor info 1852 addSuccessorWithWeight(InvokeMBB, Return); 1853 addSuccessorWithWeight(InvokeMBB, LandingPad); 1854 1855 // Drop into normal successor. 1856 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1857 MVT::Other, getControlRoot(), 1858 DAG.getBasicBlock(Return))); 1859} 1860 1861void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1862 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1863} 1864 1865void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1866 assert(FuncInfo.MBB->isLandingPad() && 1867 "Call to landingpad not in landing pad!"); 1868 1869 MachineBasicBlock *MBB = FuncInfo.MBB; 1870 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1871 AddLandingPadInfo(LP, MMI, MBB); 1872 1873 // If there aren't registers to copy the values into (e.g., during SjLj 1874 // exceptions), then don't bother to create these DAG nodes. 1875 if (TLI.getExceptionPointerRegister() == 0 && 1876 TLI.getExceptionSelectorRegister() == 0) 1877 return; 1878 1879 SmallVector<EVT, 2> ValueVTs; 1880 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1881 1882 // Insert the EXCEPTIONADDR instruction. 1883 assert(FuncInfo.MBB->isLandingPad() && 1884 "Call to eh.exception not in landing pad!"); 1885 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1886 SDValue Ops[2]; 1887 Ops[0] = DAG.getRoot(); 1888 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1889 SDValue Chain = Op1.getValue(1); 1890 1891 // Insert the EHSELECTION instruction. 1892 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1893 Ops[0] = Op1; 1894 Ops[1] = Chain; 1895 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1896 Chain = Op2.getValue(1); 1897 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1898 1899 Ops[0] = Op1; 1900 Ops[1] = Op2; 1901 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1902 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1903 &Ops[0], 2); 1904 1905 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1906 setValue(&LP, RetPair.first); 1907 DAG.setRoot(RetPair.second); 1908} 1909 1910/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1911/// small case ranges). 1912bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1913 CaseRecVector& WorkList, 1914 const Value* SV, 1915 MachineBasicBlock *Default, 1916 MachineBasicBlock *SwitchBB) { 1917 // Size is the number of Cases represented by this range. 1918 size_t Size = CR.Range.second - CR.Range.first; 1919 if (Size > 3) 1920 return false; 1921 1922 // Get the MachineFunction which holds the current MBB. This is used when 1923 // inserting any additional MBBs necessary to represent the switch. 1924 MachineFunction *CurMF = FuncInfo.MF; 1925 1926 // Figure out which block is immediately after the current one. 1927 MachineBasicBlock *NextBlock = 0; 1928 MachineFunction::iterator BBI = CR.CaseBB; 1929 1930 if (++BBI != FuncInfo.MF->end()) 1931 NextBlock = BBI; 1932 1933 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1934 // If any two of the cases has the same destination, and if one value 1935 // is the same as the other, but has one bit unset that the other has set, 1936 // use bit manipulation to do two compares at once. For example: 1937 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1938 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1939 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1940 if (Size == 2 && CR.CaseBB == SwitchBB) { 1941 Case &Small = *CR.Range.first; 1942 Case &Big = *(CR.Range.second-1); 1943 1944 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1945 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1946 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1947 1948 // Check that there is only one bit different. 1949 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1950 (SmallValue | BigValue) == BigValue) { 1951 // Isolate the common bit. 1952 APInt CommonBit = BigValue & ~SmallValue; 1953 assert((SmallValue | CommonBit) == BigValue && 1954 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1955 1956 SDValue CondLHS = getValue(SV); 1957 EVT VT = CondLHS.getValueType(); 1958 DebugLoc DL = getCurDebugLoc(); 1959 1960 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1961 DAG.getConstant(CommonBit, VT)); 1962 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1963 Or, DAG.getConstant(BigValue, VT), 1964 ISD::SETEQ); 1965 1966 // Update successor info. 1967 // Both Small and Big will jump to Small.BB, so we sum up the weights. 1968 addSuccessorWithWeight(SwitchBB, Small.BB, 1969 Small.ExtraWeight + Big.ExtraWeight); 1970 addSuccessorWithWeight(SwitchBB, Default, 1971 // The default destination is the first successor in IR. 1972 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0); 1973 1974 // Insert the true branch. 1975 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1976 getControlRoot(), Cond, 1977 DAG.getBasicBlock(Small.BB)); 1978 1979 // Insert the false branch. 1980 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1981 DAG.getBasicBlock(Default)); 1982 1983 DAG.setRoot(BrCond); 1984 return true; 1985 } 1986 } 1987 } 1988 1989 // Order cases by weight so the most likely case will be checked first. 1990 uint32_t UnhandledWeights = 0; 1991 if (BPI) { 1992 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) { 1993 uint32_t IWeight = I->ExtraWeight; 1994 UnhandledWeights += IWeight; 1995 for (CaseItr J = CR.Range.first; J < I; ++J) { 1996 uint32_t JWeight = J->ExtraWeight; 1997 if (IWeight > JWeight) 1998 std::swap(*I, *J); 1999 } 2000 } 2001 } 2002 // Rearrange the case blocks so that the last one falls through if possible. 2003 Case &BackCase = *(CR.Range.second-1); 2004 if (Size > 1 && 2005 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 2006 // The last case block won't fall through into 'NextBlock' if we emit the 2007 // branches in this order. See if rearranging a case value would help. 2008 // We start at the bottom as it's the case with the least weight. 2009 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){ 2010 if (I->BB == NextBlock) { 2011 std::swap(*I, BackCase); 2012 break; 2013 } 2014 } 2015 } 2016 2017 // Create a CaseBlock record representing a conditional branch to 2018 // the Case's target mbb if the value being switched on SV is equal 2019 // to C. 2020 MachineBasicBlock *CurBlock = CR.CaseBB; 2021 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2022 MachineBasicBlock *FallThrough; 2023 if (I != E-1) { 2024 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 2025 CurMF->insert(BBI, FallThrough); 2026 2027 // Put SV in a virtual register to make it available from the new blocks. 2028 ExportFromCurrentBlock(SV); 2029 } else { 2030 // If the last case doesn't match, go to the default block. 2031 FallThrough = Default; 2032 } 2033 2034 const Value *RHS, *LHS, *MHS; 2035 ISD::CondCode CC; 2036 if (I->High == I->Low) { 2037 // This is just small small case range :) containing exactly 1 case 2038 CC = ISD::SETEQ; 2039 LHS = SV; RHS = I->High; MHS = NULL; 2040 } else { 2041 CC = ISD::SETCC_INVALID; 2042 LHS = I->Low; MHS = SV; RHS = I->High; 2043 } 2044 2045 // The false weight should be sum of all un-handled cases. 2046 UnhandledWeights -= I->ExtraWeight; 2047 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 2048 /* me */ CurBlock, 2049 /* trueweight */ I->ExtraWeight, 2050 /* falseweight */ UnhandledWeights); 2051 2052 // If emitting the first comparison, just call visitSwitchCase to emit the 2053 // code into the current block. Otherwise, push the CaseBlock onto the 2054 // vector to be later processed by SDISel, and insert the node's MBB 2055 // before the next MBB. 2056 if (CurBlock == SwitchBB) 2057 visitSwitchCase(CB, SwitchBB); 2058 else 2059 SwitchCases.push_back(CB); 2060 2061 CurBlock = FallThrough; 2062 } 2063 2064 return true; 2065} 2066 2067static inline bool areJTsAllowed(const TargetLowering &TLI) { 2068 return TLI.supportJumpTables() && 2069 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2070 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2071} 2072 2073static APInt ComputeRange(const APInt &First, const APInt &Last) { 2074 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2075 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth); 2076 return (LastExt - FirstExt + 1ULL); 2077} 2078 2079/// handleJTSwitchCase - Emit jumptable for current switch case range 2080bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2081 CaseRecVector &WorkList, 2082 const Value *SV, 2083 MachineBasicBlock *Default, 2084 MachineBasicBlock *SwitchBB) { 2085 Case& FrontCase = *CR.Range.first; 2086 Case& BackCase = *(CR.Range.second-1); 2087 2088 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2089 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2090 2091 APInt TSize(First.getBitWidth(), 0); 2092 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2093 TSize += I->size(); 2094 2095 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2096 return false; 2097 2098 APInt Range = ComputeRange(First, Last); 2099 // The density is TSize / Range. Require at least 40%. 2100 // It should not be possible for IntTSize to saturate for sane code, but make 2101 // sure we handle Range saturation correctly. 2102 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2103 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2104 if (IntTSize * 10 < IntRange * 4) 2105 return false; 2106 2107 DEBUG(dbgs() << "Lowering jump table\n" 2108 << "First entry: " << First << ". Last entry: " << Last << '\n' 2109 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2110 2111 // Get the MachineFunction which holds the current MBB. This is used when 2112 // inserting any additional MBBs necessary to represent the switch. 2113 MachineFunction *CurMF = FuncInfo.MF; 2114 2115 // Figure out which block is immediately after the current one. 2116 MachineFunction::iterator BBI = CR.CaseBB; 2117 ++BBI; 2118 2119 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2120 2121 // Create a new basic block to hold the code for loading the address 2122 // of the jump table, and jumping to it. Update successor information; 2123 // we will either branch to the default case for the switch, or the jump 2124 // table. 2125 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2126 CurMF->insert(BBI, JumpTableBB); 2127 2128 addSuccessorWithWeight(CR.CaseBB, Default); 2129 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2130 2131 // Build a vector of destination BBs, corresponding to each target 2132 // of the jump table. If the value of the jump table slot corresponds to 2133 // a case statement, push the case's BB onto the vector, otherwise, push 2134 // the default BB. 2135 std::vector<MachineBasicBlock*> DestBBs; 2136 APInt TEI = First; 2137 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2138 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2139 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2140 2141 if (Low.ule(TEI) && TEI.ule(High)) { 2142 DestBBs.push_back(I->BB); 2143 if (TEI==High) 2144 ++I; 2145 } else { 2146 DestBBs.push_back(Default); 2147 } 2148 } 2149 2150 // Calculate weight for each unique destination in CR. 2151 DenseMap<MachineBasicBlock*, uint32_t> DestWeights; 2152 if (FuncInfo.BPI) 2153 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2154 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr = 2155 DestWeights.find(I->BB); 2156 if (Itr != DestWeights.end()) 2157 Itr->second += I->ExtraWeight; 2158 else 2159 DestWeights[I->BB] = I->ExtraWeight; 2160 } 2161 2162 // Update successor info. Add one edge to each unique successor. 2163 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2164 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2165 E = DestBBs.end(); I != E; ++I) { 2166 if (!SuccsHandled[(*I)->getNumber()]) { 2167 SuccsHandled[(*I)->getNumber()] = true; 2168 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr = 2169 DestWeights.find(*I); 2170 addSuccessorWithWeight(JumpTableBB, *I, 2171 Itr != DestWeights.end() ? Itr->second : 0); 2172 } 2173 } 2174 2175 // Create a jump table index for this jump table. 2176 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2177 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2178 ->createJumpTableIndex(DestBBs); 2179 2180 // Set the jump table information so that we can codegen it as a second 2181 // MachineBasicBlock 2182 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2183 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2184 if (CR.CaseBB == SwitchBB) 2185 visitJumpTableHeader(JT, JTH, SwitchBB); 2186 2187 JTCases.push_back(JumpTableBlock(JTH, JT)); 2188 return true; 2189} 2190 2191/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2192/// 2 subtrees. 2193bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2194 CaseRecVector& WorkList, 2195 const Value* SV, 2196 MachineBasicBlock *Default, 2197 MachineBasicBlock *SwitchBB) { 2198 // Get the MachineFunction which holds the current MBB. This is used when 2199 // inserting any additional MBBs necessary to represent the switch. 2200 MachineFunction *CurMF = FuncInfo.MF; 2201 2202 // Figure out which block is immediately after the current one. 2203 MachineFunction::iterator BBI = CR.CaseBB; 2204 ++BBI; 2205 2206 Case& FrontCase = *CR.Range.first; 2207 Case& BackCase = *(CR.Range.second-1); 2208 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2209 2210 // Size is the number of Cases represented by this range. 2211 unsigned Size = CR.Range.second - CR.Range.first; 2212 2213 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2214 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2215 double FMetric = 0; 2216 CaseItr Pivot = CR.Range.first + Size/2; 2217 2218 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2219 // (heuristically) allow us to emit JumpTable's later. 2220 APInt TSize(First.getBitWidth(), 0); 2221 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2222 I!=E; ++I) 2223 TSize += I->size(); 2224 2225 APInt LSize = FrontCase.size(); 2226 APInt RSize = TSize-LSize; 2227 DEBUG(dbgs() << "Selecting best pivot: \n" 2228 << "First: " << First << ", Last: " << Last <<'\n' 2229 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2230 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2231 J!=E; ++I, ++J) { 2232 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2233 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2234 APInt Range = ComputeRange(LEnd, RBegin); 2235 assert((Range - 2ULL).isNonNegative() && 2236 "Invalid case distance"); 2237 // Use volatile double here to avoid excess precision issues on some hosts, 2238 // e.g. that use 80-bit X87 registers. 2239 volatile double LDensity = 2240 (double)LSize.roundToDouble() / 2241 (LEnd - First + 1ULL).roundToDouble(); 2242 volatile double RDensity = 2243 (double)RSize.roundToDouble() / 2244 (Last - RBegin + 1ULL).roundToDouble(); 2245 double Metric = Range.logBase2()*(LDensity+RDensity); 2246 // Should always split in some non-trivial place 2247 DEBUG(dbgs() <<"=>Step\n" 2248 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2249 << "LDensity: " << LDensity 2250 << ", RDensity: " << RDensity << '\n' 2251 << "Metric: " << Metric << '\n'); 2252 if (FMetric < Metric) { 2253 Pivot = J; 2254 FMetric = Metric; 2255 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2256 } 2257 2258 LSize += J->size(); 2259 RSize -= J->size(); 2260 } 2261 if (areJTsAllowed(TLI)) { 2262 // If our case is dense we *really* should handle it earlier! 2263 assert((FMetric > 0) && "Should handle dense range earlier!"); 2264 } else { 2265 Pivot = CR.Range.first + Size/2; 2266 } 2267 2268 CaseRange LHSR(CR.Range.first, Pivot); 2269 CaseRange RHSR(Pivot, CR.Range.second); 2270 const Constant *C = Pivot->Low; 2271 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2272 2273 // We know that we branch to the LHS if the Value being switched on is 2274 // less than the Pivot value, C. We use this to optimize our binary 2275 // tree a bit, by recognizing that if SV is greater than or equal to the 2276 // LHS's Case Value, and that Case Value is exactly one less than the 2277 // Pivot's Value, then we can branch directly to the LHS's Target, 2278 // rather than creating a leaf node for it. 2279 if ((LHSR.second - LHSR.first) == 1 && 2280 LHSR.first->High == CR.GE && 2281 cast<ConstantInt>(C)->getValue() == 2282 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2283 TrueBB = LHSR.first->BB; 2284 } else { 2285 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2286 CurMF->insert(BBI, TrueBB); 2287 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2288 2289 // Put SV in a virtual register to make it available from the new blocks. 2290 ExportFromCurrentBlock(SV); 2291 } 2292 2293 // Similar to the optimization above, if the Value being switched on is 2294 // known to be less than the Constant CR.LT, and the current Case Value 2295 // is CR.LT - 1, then we can branch directly to the target block for 2296 // the current Case Value, rather than emitting a RHS leaf node for it. 2297 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2298 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2299 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2300 FalseBB = RHSR.first->BB; 2301 } else { 2302 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2303 CurMF->insert(BBI, FalseBB); 2304 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2305 2306 // Put SV in a virtual register to make it available from the new blocks. 2307 ExportFromCurrentBlock(SV); 2308 } 2309 2310 // Create a CaseBlock record representing a conditional branch to 2311 // the LHS node if the value being switched on SV is less than C. 2312 // Otherwise, branch to LHS. 2313 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2314 2315 if (CR.CaseBB == SwitchBB) 2316 visitSwitchCase(CB, SwitchBB); 2317 else 2318 SwitchCases.push_back(CB); 2319 2320 return true; 2321} 2322 2323/// handleBitTestsSwitchCase - if current case range has few destination and 2324/// range span less, than machine word bitwidth, encode case range into series 2325/// of masks and emit bit tests with these masks. 2326bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2327 CaseRecVector& WorkList, 2328 const Value* SV, 2329 MachineBasicBlock* Default, 2330 MachineBasicBlock *SwitchBB){ 2331 EVT PTy = TLI.getPointerTy(); 2332 unsigned IntPtrBits = PTy.getSizeInBits(); 2333 2334 Case& FrontCase = *CR.Range.first; 2335 Case& BackCase = *(CR.Range.second-1); 2336 2337 // Get the MachineFunction which holds the current MBB. This is used when 2338 // inserting any additional MBBs necessary to represent the switch. 2339 MachineFunction *CurMF = FuncInfo.MF; 2340 2341 // If target does not have legal shift left, do not emit bit tests at all. 2342 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2343 return false; 2344 2345 size_t numCmps = 0; 2346 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2347 I!=E; ++I) { 2348 // Single case counts one, case range - two. 2349 numCmps += (I->Low == I->High ? 1 : 2); 2350 } 2351 2352 // Count unique destinations 2353 SmallSet<MachineBasicBlock*, 4> Dests; 2354 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2355 Dests.insert(I->BB); 2356 if (Dests.size() > 3) 2357 // Don't bother the code below, if there are too much unique destinations 2358 return false; 2359 } 2360 DEBUG(dbgs() << "Total number of unique destinations: " 2361 << Dests.size() << '\n' 2362 << "Total number of comparisons: " << numCmps << '\n'); 2363 2364 // Compute span of values. 2365 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2366 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2367 APInt cmpRange = maxValue - minValue; 2368 2369 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2370 << "Low bound: " << minValue << '\n' 2371 << "High bound: " << maxValue << '\n'); 2372 2373 if (cmpRange.uge(IntPtrBits) || 2374 (!(Dests.size() == 1 && numCmps >= 3) && 2375 !(Dests.size() == 2 && numCmps >= 5) && 2376 !(Dests.size() >= 3 && numCmps >= 6))) 2377 return false; 2378 2379 DEBUG(dbgs() << "Emitting bit tests\n"); 2380 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2381 2382 // Optimize the case where all the case values fit in a 2383 // word without having to subtract minValue. In this case, 2384 // we can optimize away the subtraction. 2385 if (maxValue.ult(IntPtrBits)) { 2386 cmpRange = maxValue; 2387 } else { 2388 lowBound = minValue; 2389 } 2390 2391 CaseBitsVector CasesBits; 2392 unsigned i, count = 0; 2393 2394 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2395 MachineBasicBlock* Dest = I->BB; 2396 for (i = 0; i < count; ++i) 2397 if (Dest == CasesBits[i].BB) 2398 break; 2399 2400 if (i == count) { 2401 assert((count < 3) && "Too much destinations to test!"); 2402 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/)); 2403 count++; 2404 } 2405 2406 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2407 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2408 2409 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2410 uint64_t hi = (highValue - lowBound).getZExtValue(); 2411 CasesBits[i].ExtraWeight += I->ExtraWeight; 2412 2413 for (uint64_t j = lo; j <= hi; j++) { 2414 CasesBits[i].Mask |= 1ULL << j; 2415 CasesBits[i].Bits++; 2416 } 2417 2418 } 2419 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2420 2421 BitTestInfo BTC; 2422 2423 // Figure out which block is immediately after the current one. 2424 MachineFunction::iterator BBI = CR.CaseBB; 2425 ++BBI; 2426 2427 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2428 2429 DEBUG(dbgs() << "Cases:\n"); 2430 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2431 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2432 << ", Bits: " << CasesBits[i].Bits 2433 << ", BB: " << CasesBits[i].BB << '\n'); 2434 2435 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2436 CurMF->insert(BBI, CaseBB); 2437 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2438 CaseBB, 2439 CasesBits[i].BB, CasesBits[i].ExtraWeight)); 2440 2441 // Put SV in a virtual register to make it available from the new blocks. 2442 ExportFromCurrentBlock(SV); 2443 } 2444 2445 BitTestBlock BTB(lowBound, cmpRange, SV, 2446 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2447 CR.CaseBB, Default, BTC); 2448 2449 if (CR.CaseBB == SwitchBB) 2450 visitBitTestHeader(BTB, SwitchBB); 2451 2452 BitTestCases.push_back(BTB); 2453 2454 return true; 2455} 2456 2457/// Clusterify - Transform simple list of Cases into list of CaseRange's 2458size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2459 const SwitchInst& SI) { 2460 2461 /// Use a shorter form of declaration, and also 2462 /// show the we want to use CRSBuilder as Clusterifier. 2463 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier; 2464 2465 Clusterifier TheClusterifier; 2466 2467 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2468 // Start with "simple" cases 2469 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end(); 2470 i != e; ++i) { 2471 const BasicBlock *SuccBB = i.getCaseSuccessor(); 2472 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2473 2474 TheClusterifier.add(i.getCaseValueEx(), SMBB, 2475 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0); 2476 } 2477 2478 TheClusterifier.optimize(); 2479 2480 size_t numCmps = 0; 2481 for (Clusterifier::RangeIterator i = TheClusterifier.begin(), 2482 e = TheClusterifier.end(); i != e; ++i, ++numCmps) { 2483 Clusterifier::Cluster &C = *i; 2484 // Update edge weight for the cluster. 2485 unsigned W = C.first.Weight; 2486 2487 // FIXME: Currently work with ConstantInt based numbers. 2488 // Changing it to APInt based is a pretty heavy for this commit. 2489 Cases.push_back(Case(C.first.getLow().toConstantInt(), 2490 C.first.getHigh().toConstantInt(), C.second, W)); 2491 2492 if (C.first.getLow() != C.first.getHigh()) 2493 // A range counts double, since it requires two compares. 2494 ++numCmps; 2495 } 2496 2497 return numCmps; 2498} 2499 2500void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2501 MachineBasicBlock *Last) { 2502 // Update JTCases. 2503 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2504 if (JTCases[i].first.HeaderBB == First) 2505 JTCases[i].first.HeaderBB = Last; 2506 2507 // Update BitTestCases. 2508 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2509 if (BitTestCases[i].Parent == First) 2510 BitTestCases[i].Parent = Last; 2511} 2512 2513void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2514 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2515 2516 // Figure out which block is immediately after the current one. 2517 MachineBasicBlock *NextBlock = 0; 2518 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2519 2520 // If there is only the default destination, branch to it if it is not the 2521 // next basic block. Otherwise, just fall through. 2522 if (!SI.getNumCases()) { 2523 // Update machine-CFG edges. 2524 2525 // If this is not a fall-through branch, emit the branch. 2526 SwitchMBB->addSuccessor(Default); 2527 if (Default != NextBlock) 2528 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2529 MVT::Other, getControlRoot(), 2530 DAG.getBasicBlock(Default))); 2531 2532 return; 2533 } 2534 2535 // If there are any non-default case statements, create a vector of Cases 2536 // representing each one, and sort the vector so that we can efficiently 2537 // create a binary search tree from them. 2538 CaseVector Cases; 2539 size_t numCmps = Clusterify(Cases, SI); 2540 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2541 << ". Total compares: " << numCmps << '\n'); 2542 (void)numCmps; 2543 2544 // Get the Value to be switched on and default basic blocks, which will be 2545 // inserted into CaseBlock records, representing basic blocks in the binary 2546 // search tree. 2547 const Value *SV = SI.getCondition(); 2548 2549 // Push the initial CaseRec onto the worklist 2550 CaseRecVector WorkList; 2551 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2552 CaseRange(Cases.begin(),Cases.end()))); 2553 2554 while (!WorkList.empty()) { 2555 // Grab a record representing a case range to process off the worklist 2556 CaseRec CR = WorkList.back(); 2557 WorkList.pop_back(); 2558 2559 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2560 continue; 2561 2562 // If the range has few cases (two or less) emit a series of specific 2563 // tests. 2564 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2565 continue; 2566 2567 // If the switch has more than 5 blocks, and at least 40% dense, and the 2568 // target supports indirect branches, then emit a jump table rather than 2569 // lowering the switch to a binary tree of conditional branches. 2570 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2571 continue; 2572 2573 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2574 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2575 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2576 } 2577} 2578 2579void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2580 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2581 2582 // Update machine-CFG edges with unique successors. 2583 SmallVector<BasicBlock*, 32> succs; 2584 succs.reserve(I.getNumSuccessors()); 2585 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2586 succs.push_back(I.getSuccessor(i)); 2587 array_pod_sort(succs.begin(), succs.end()); 2588 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2589 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2590 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2591 addSuccessorWithWeight(IndirectBrMBB, Succ); 2592 } 2593 2594 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2595 MVT::Other, getControlRoot(), 2596 getValue(I.getAddress()))); 2597} 2598 2599void SelectionDAGBuilder::visitFSub(const User &I) { 2600 // -0.0 - X --> fneg 2601 Type *Ty = I.getType(); 2602 if (isa<Constant>(I.getOperand(0)) && 2603 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2604 SDValue Op2 = getValue(I.getOperand(1)); 2605 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2606 Op2.getValueType(), Op2)); 2607 return; 2608 } 2609 2610 visitBinary(I, ISD::FSUB); 2611} 2612 2613void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2614 SDValue Op1 = getValue(I.getOperand(0)); 2615 SDValue Op2 = getValue(I.getOperand(1)); 2616 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2617 Op1.getValueType(), Op1, Op2)); 2618} 2619 2620void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2621 SDValue Op1 = getValue(I.getOperand(0)); 2622 SDValue Op2 = getValue(I.getOperand(1)); 2623 2624 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2625 2626 // Coerce the shift amount to the right type if we can. 2627 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2628 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2629 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2630 DebugLoc DL = getCurDebugLoc(); 2631 2632 // If the operand is smaller than the shift count type, promote it. 2633 if (ShiftSize > Op2Size) 2634 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2635 2636 // If the operand is larger than the shift count type but the shift 2637 // count type has enough bits to represent any shift value, truncate 2638 // it now. This is a common case and it exposes the truncate to 2639 // optimization early. 2640 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2641 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2642 // Otherwise we'll need to temporarily settle for some other convenient 2643 // type. Type legalization will make adjustments once the shiftee is split. 2644 else 2645 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2646 } 2647 2648 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2649 Op1.getValueType(), Op1, Op2)); 2650} 2651 2652void SelectionDAGBuilder::visitSDiv(const User &I) { 2653 SDValue Op1 = getValue(I.getOperand(0)); 2654 SDValue Op2 = getValue(I.getOperand(1)); 2655 2656 // Turn exact SDivs into multiplications. 2657 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2658 // exact bit. 2659 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2660 !isa<ConstantSDNode>(Op1) && 2661 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2662 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2663 else 2664 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2665 Op1, Op2)); 2666} 2667 2668void SelectionDAGBuilder::visitICmp(const User &I) { 2669 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2670 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2671 predicate = IC->getPredicate(); 2672 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2673 predicate = ICmpInst::Predicate(IC->getPredicate()); 2674 SDValue Op1 = getValue(I.getOperand(0)); 2675 SDValue Op2 = getValue(I.getOperand(1)); 2676 ISD::CondCode Opcode = getICmpCondCode(predicate); 2677 2678 EVT DestVT = TLI.getValueType(I.getType()); 2679 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2680} 2681 2682void SelectionDAGBuilder::visitFCmp(const User &I) { 2683 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2684 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2685 predicate = FC->getPredicate(); 2686 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2687 predicate = FCmpInst::Predicate(FC->getPredicate()); 2688 SDValue Op1 = getValue(I.getOperand(0)); 2689 SDValue Op2 = getValue(I.getOperand(1)); 2690 ISD::CondCode Condition = getFCmpCondCode(predicate); 2691 if (TM.Options.NoNaNsFPMath) 2692 Condition = getFCmpCodeWithoutNaN(Condition); 2693 EVT DestVT = TLI.getValueType(I.getType()); 2694 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2695} 2696 2697void SelectionDAGBuilder::visitSelect(const User &I) { 2698 SmallVector<EVT, 4> ValueVTs; 2699 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2700 unsigned NumValues = ValueVTs.size(); 2701 if (NumValues == 0) return; 2702 2703 SmallVector<SDValue, 4> Values(NumValues); 2704 SDValue Cond = getValue(I.getOperand(0)); 2705 SDValue TrueVal = getValue(I.getOperand(1)); 2706 SDValue FalseVal = getValue(I.getOperand(2)); 2707 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2708 ISD::VSELECT : ISD::SELECT; 2709 2710 for (unsigned i = 0; i != NumValues; ++i) 2711 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2712 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2713 Cond, 2714 SDValue(TrueVal.getNode(), 2715 TrueVal.getResNo() + i), 2716 SDValue(FalseVal.getNode(), 2717 FalseVal.getResNo() + i)); 2718 2719 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2720 DAG.getVTList(&ValueVTs[0], NumValues), 2721 &Values[0], NumValues)); 2722} 2723 2724void SelectionDAGBuilder::visitTrunc(const User &I) { 2725 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2726 SDValue N = getValue(I.getOperand(0)); 2727 EVT DestVT = TLI.getValueType(I.getType()); 2728 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2729} 2730 2731void SelectionDAGBuilder::visitZExt(const User &I) { 2732 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2733 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2734 SDValue N = getValue(I.getOperand(0)); 2735 EVT DestVT = TLI.getValueType(I.getType()); 2736 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2737} 2738 2739void SelectionDAGBuilder::visitSExt(const User &I) { 2740 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2741 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2742 SDValue N = getValue(I.getOperand(0)); 2743 EVT DestVT = TLI.getValueType(I.getType()); 2744 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2745} 2746 2747void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2748 // FPTrunc is never a no-op cast, no need to check 2749 SDValue N = getValue(I.getOperand(0)); 2750 EVT DestVT = TLI.getValueType(I.getType()); 2751 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2752 DestVT, N, 2753 DAG.getTargetConstant(0, TLI.getPointerTy()))); 2754} 2755 2756void SelectionDAGBuilder::visitFPExt(const User &I){ 2757 // FPExt is never a no-op cast, no need to check 2758 SDValue N = getValue(I.getOperand(0)); 2759 EVT DestVT = TLI.getValueType(I.getType()); 2760 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2761} 2762 2763void SelectionDAGBuilder::visitFPToUI(const User &I) { 2764 // FPToUI is never a no-op cast, no need to check 2765 SDValue N = getValue(I.getOperand(0)); 2766 EVT DestVT = TLI.getValueType(I.getType()); 2767 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2768} 2769 2770void SelectionDAGBuilder::visitFPToSI(const User &I) { 2771 // FPToSI is never a no-op cast, no need to check 2772 SDValue N = getValue(I.getOperand(0)); 2773 EVT DestVT = TLI.getValueType(I.getType()); 2774 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2775} 2776 2777void SelectionDAGBuilder::visitUIToFP(const User &I) { 2778 // UIToFP is never a no-op cast, no need to check 2779 SDValue N = getValue(I.getOperand(0)); 2780 EVT DestVT = TLI.getValueType(I.getType()); 2781 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2782} 2783 2784void SelectionDAGBuilder::visitSIToFP(const User &I){ 2785 // SIToFP is never a no-op cast, no need to check 2786 SDValue N = getValue(I.getOperand(0)); 2787 EVT DestVT = TLI.getValueType(I.getType()); 2788 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2789} 2790 2791void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2792 // What to do depends on the size of the integer and the size of the pointer. 2793 // We can either truncate, zero extend, or no-op, accordingly. 2794 SDValue N = getValue(I.getOperand(0)); 2795 EVT DestVT = TLI.getValueType(I.getType()); 2796 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2797} 2798 2799void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2800 // What to do depends on the size of the integer and the size of the pointer. 2801 // We can either truncate, zero extend, or no-op, accordingly. 2802 SDValue N = getValue(I.getOperand(0)); 2803 EVT DestVT = TLI.getValueType(I.getType()); 2804 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2805} 2806 2807void SelectionDAGBuilder::visitBitCast(const User &I) { 2808 SDValue N = getValue(I.getOperand(0)); 2809 EVT DestVT = TLI.getValueType(I.getType()); 2810 2811 // BitCast assures us that source and destination are the same size so this is 2812 // either a BITCAST or a no-op. 2813 if (DestVT != N.getValueType()) 2814 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2815 DestVT, N)); // convert types. 2816 else 2817 setValue(&I, N); // noop cast. 2818} 2819 2820void SelectionDAGBuilder::visitInsertElement(const User &I) { 2821 SDValue InVec = getValue(I.getOperand(0)); 2822 SDValue InVal = getValue(I.getOperand(1)); 2823 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2824 TLI.getPointerTy(), 2825 getValue(I.getOperand(2))); 2826 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2827 TLI.getValueType(I.getType()), 2828 InVec, InVal, InIdx)); 2829} 2830 2831void SelectionDAGBuilder::visitExtractElement(const User &I) { 2832 SDValue InVec = getValue(I.getOperand(0)); 2833 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2834 TLI.getPointerTy(), 2835 getValue(I.getOperand(1))); 2836 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2837 TLI.getValueType(I.getType()), InVec, InIdx)); 2838} 2839 2840// Utility for visitShuffleVector - Return true if every element in Mask, 2841// beginning from position Pos and ending in Pos+Size, falls within the 2842// specified sequential range [L, L+Pos). or is undef. 2843static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2844 unsigned Pos, unsigned Size, int Low) { 2845 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2846 if (Mask[i] >= 0 && Mask[i] != Low) 2847 return false; 2848 return true; 2849} 2850 2851void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2852 SDValue Src1 = getValue(I.getOperand(0)); 2853 SDValue Src2 = getValue(I.getOperand(1)); 2854 2855 SmallVector<int, 8> Mask; 2856 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); 2857 unsigned MaskNumElts = Mask.size(); 2858 2859 EVT VT = TLI.getValueType(I.getType()); 2860 EVT SrcVT = Src1.getValueType(); 2861 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2862 2863 if (SrcNumElts == MaskNumElts) { 2864 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2865 &Mask[0])); 2866 return; 2867 } 2868 2869 // Normalize the shuffle vector since mask and vector length don't match. 2870 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2871 // Mask is longer than the source vectors and is a multiple of the source 2872 // vectors. We can use concatenate vector to make the mask and vectors 2873 // lengths match. 2874 if (SrcNumElts*2 == MaskNumElts) { 2875 // First check for Src1 in low and Src2 in high 2876 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 2877 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 2878 // The shuffle is concatenating two vectors together. 2879 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2880 VT, Src1, Src2)); 2881 return; 2882 } 2883 // Then check for Src2 in low and Src1 in high 2884 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 2885 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 2886 // The shuffle is concatenating two vectors together. 2887 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2888 VT, Src2, Src1)); 2889 return; 2890 } 2891 } 2892 2893 // Pad both vectors with undefs to make them the same length as the mask. 2894 unsigned NumConcat = MaskNumElts / SrcNumElts; 2895 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2896 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2897 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2898 2899 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2900 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2901 MOps1[0] = Src1; 2902 MOps2[0] = Src2; 2903 2904 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2905 getCurDebugLoc(), VT, 2906 &MOps1[0], NumConcat); 2907 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2908 getCurDebugLoc(), VT, 2909 &MOps2[0], NumConcat); 2910 2911 // Readjust mask for new input vector length. 2912 SmallVector<int, 8> MappedOps; 2913 for (unsigned i = 0; i != MaskNumElts; ++i) { 2914 int Idx = Mask[i]; 2915 if (Idx >= (int)SrcNumElts) 2916 Idx -= SrcNumElts - MaskNumElts; 2917 MappedOps.push_back(Idx); 2918 } 2919 2920 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2921 &MappedOps[0])); 2922 return; 2923 } 2924 2925 if (SrcNumElts > MaskNumElts) { 2926 // Analyze the access pattern of the vector to see if we can extract 2927 // two subvectors and do the shuffle. The analysis is done by calculating 2928 // the range of elements the mask access on both vectors. 2929 int MinRange[2] = { static_cast<int>(SrcNumElts), 2930 static_cast<int>(SrcNumElts)}; 2931 int MaxRange[2] = {-1, -1}; 2932 2933 for (unsigned i = 0; i != MaskNumElts; ++i) { 2934 int Idx = Mask[i]; 2935 unsigned Input = 0; 2936 if (Idx < 0) 2937 continue; 2938 2939 if (Idx >= (int)SrcNumElts) { 2940 Input = 1; 2941 Idx -= SrcNumElts; 2942 } 2943 if (Idx > MaxRange[Input]) 2944 MaxRange[Input] = Idx; 2945 if (Idx < MinRange[Input]) 2946 MinRange[Input] = Idx; 2947 } 2948 2949 // Check if the access is smaller than the vector size and can we find 2950 // a reasonable extract index. 2951 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not 2952 // Extract. 2953 int StartIdx[2]; // StartIdx to extract from 2954 for (unsigned Input = 0; Input < 2; ++Input) { 2955 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) { 2956 RangeUse[Input] = 0; // Unused 2957 StartIdx[Input] = 0; 2958 continue; 2959 } 2960 2961 // Find a good start index that is a multiple of the mask length. Then 2962 // see if the rest of the elements are in range. 2963 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2964 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2965 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2966 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2967 } 2968 2969 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2970 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2971 return; 2972 } 2973 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) { 2974 // Extract appropriate subvector and generate a vector shuffle 2975 for (unsigned Input = 0; Input < 2; ++Input) { 2976 SDValue &Src = Input == 0 ? Src1 : Src2; 2977 if (RangeUse[Input] == 0) 2978 Src = DAG.getUNDEF(VT); 2979 else 2980 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2981 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2982 } 2983 2984 // Calculate new mask. 2985 SmallVector<int, 8> MappedOps; 2986 for (unsigned i = 0; i != MaskNumElts; ++i) { 2987 int Idx = Mask[i]; 2988 if (Idx >= 0) { 2989 if (Idx < (int)SrcNumElts) 2990 Idx -= StartIdx[0]; 2991 else 2992 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; 2993 } 2994 MappedOps.push_back(Idx); 2995 } 2996 2997 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2998 &MappedOps[0])); 2999 return; 3000 } 3001 } 3002 3003 // We can't use either concat vectors or extract subvectors so fall back to 3004 // replacing the shuffle with extract and build vector. 3005 // to insert and build vector. 3006 EVT EltVT = VT.getVectorElementType(); 3007 EVT PtrVT = TLI.getPointerTy(); 3008 SmallVector<SDValue,8> Ops; 3009 for (unsigned i = 0; i != MaskNumElts; ++i) { 3010 int Idx = Mask[i]; 3011 SDValue Res; 3012 3013 if (Idx < 0) { 3014 Res = DAG.getUNDEF(EltVT); 3015 } else { 3016 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; 3017 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; 3018 3019 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 3020 EltVT, Src, DAG.getConstant(Idx, PtrVT)); 3021 } 3022 3023 Ops.push_back(Res); 3024 } 3025 3026 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 3027 VT, &Ops[0], Ops.size())); 3028} 3029 3030void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 3031 const Value *Op0 = I.getOperand(0); 3032 const Value *Op1 = I.getOperand(1); 3033 Type *AggTy = I.getType(); 3034 Type *ValTy = Op1->getType(); 3035 bool IntoUndef = isa<UndefValue>(Op0); 3036 bool FromUndef = isa<UndefValue>(Op1); 3037 3038 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3039 3040 SmallVector<EVT, 4> AggValueVTs; 3041 ComputeValueVTs(TLI, AggTy, AggValueVTs); 3042 SmallVector<EVT, 4> ValValueVTs; 3043 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3044 3045 unsigned NumAggValues = AggValueVTs.size(); 3046 unsigned NumValValues = ValValueVTs.size(); 3047 SmallVector<SDValue, 4> Values(NumAggValues); 3048 3049 SDValue Agg = getValue(Op0); 3050 unsigned i = 0; 3051 // Copy the beginning value(s) from the original aggregate. 3052 for (; i != LinearIndex; ++i) 3053 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3054 SDValue(Agg.getNode(), Agg.getResNo() + i); 3055 // Copy values from the inserted value(s). 3056 if (NumValValues) { 3057 SDValue Val = getValue(Op1); 3058 for (; i != LinearIndex + NumValValues; ++i) 3059 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3060 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3061 } 3062 // Copy remaining value(s) from the original aggregate. 3063 for (; i != NumAggValues; ++i) 3064 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3065 SDValue(Agg.getNode(), Agg.getResNo() + i); 3066 3067 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3068 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3069 &Values[0], NumAggValues)); 3070} 3071 3072void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3073 const Value *Op0 = I.getOperand(0); 3074 Type *AggTy = Op0->getType(); 3075 Type *ValTy = I.getType(); 3076 bool OutOfUndef = isa<UndefValue>(Op0); 3077 3078 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3079 3080 SmallVector<EVT, 4> ValValueVTs; 3081 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3082 3083 unsigned NumValValues = ValValueVTs.size(); 3084 3085 // Ignore a extractvalue that produces an empty object 3086 if (!NumValValues) { 3087 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3088 return; 3089 } 3090 3091 SmallVector<SDValue, 4> Values(NumValValues); 3092 3093 SDValue Agg = getValue(Op0); 3094 // Copy out the selected value(s). 3095 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3096 Values[i - LinearIndex] = 3097 OutOfUndef ? 3098 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3099 SDValue(Agg.getNode(), Agg.getResNo() + i); 3100 3101 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3102 DAG.getVTList(&ValValueVTs[0], NumValValues), 3103 &Values[0], NumValValues)); 3104} 3105 3106void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3107 SDValue N = getValue(I.getOperand(0)); 3108 // Note that the pointer operand may be a vector of pointers. Take the scalar 3109 // element which holds a pointer. 3110 Type *Ty = I.getOperand(0)->getType()->getScalarType(); 3111 3112 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3113 OI != E; ++OI) { 3114 const Value *Idx = *OI; 3115 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3116 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3117 if (Field) { 3118 // N = N + Offset 3119 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3120 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3121 DAG.getIntPtrConstant(Offset)); 3122 } 3123 3124 Ty = StTy->getElementType(Field); 3125 } else { 3126 Ty = cast<SequentialType>(Ty)->getElementType(); 3127 3128 // If this is a constant subscript, handle it quickly. 3129 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3130 if (CI->isZero()) continue; 3131 uint64_t Offs = 3132 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3133 SDValue OffsVal; 3134 EVT PTy = TLI.getPointerTy(); 3135 unsigned PtrBits = PTy.getSizeInBits(); 3136 if (PtrBits < 64) 3137 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3138 TLI.getPointerTy(), 3139 DAG.getConstant(Offs, MVT::i64)); 3140 else 3141 OffsVal = DAG.getIntPtrConstant(Offs); 3142 3143 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3144 OffsVal); 3145 continue; 3146 } 3147 3148 // N = N + Idx * ElementSize; 3149 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3150 TD->getTypeAllocSize(Ty)); 3151 SDValue IdxN = getValue(Idx); 3152 3153 // If the index is smaller or larger than intptr_t, truncate or extend 3154 // it. 3155 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3156 3157 // If this is a multiply by a power of two, turn it into a shl 3158 // immediately. This is a very common case. 3159 if (ElementSize != 1) { 3160 if (ElementSize.isPowerOf2()) { 3161 unsigned Amt = ElementSize.logBase2(); 3162 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3163 N.getValueType(), IdxN, 3164 DAG.getConstant(Amt, IdxN.getValueType())); 3165 } else { 3166 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3167 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3168 N.getValueType(), IdxN, Scale); 3169 } 3170 } 3171 3172 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3173 N.getValueType(), N, IdxN); 3174 } 3175 } 3176 3177 setValue(&I, N); 3178} 3179 3180void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3181 // If this is a fixed sized alloca in the entry block of the function, 3182 // allocate it statically on the stack. 3183 if (FuncInfo.StaticAllocaMap.count(&I)) 3184 return; // getValue will auto-populate this. 3185 3186 Type *Ty = I.getAllocatedType(); 3187 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3188 unsigned Align = 3189 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3190 I.getAlignment()); 3191 3192 SDValue AllocSize = getValue(I.getArraySize()); 3193 3194 EVT IntPtr = TLI.getPointerTy(); 3195 if (AllocSize.getValueType() != IntPtr) 3196 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3197 3198 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3199 AllocSize, 3200 DAG.getConstant(TySize, IntPtr)); 3201 3202 // Handle alignment. If the requested alignment is less than or equal to 3203 // the stack alignment, ignore it. If the size is greater than or equal to 3204 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3205 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3206 if (Align <= StackAlign) 3207 Align = 0; 3208 3209 // Round the size of the allocation up to the stack alignment size 3210 // by add SA-1 to the size. 3211 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3212 AllocSize.getValueType(), AllocSize, 3213 DAG.getIntPtrConstant(StackAlign-1)); 3214 3215 // Mask out the low bits for alignment purposes. 3216 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3217 AllocSize.getValueType(), AllocSize, 3218 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3219 3220 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3221 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3222 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3223 VTs, Ops, 3); 3224 setValue(&I, DSA); 3225 DAG.setRoot(DSA.getValue(1)); 3226 3227 // Inform the Frame Information that we have just allocated a variable-sized 3228 // object. 3229 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3230} 3231 3232void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3233 if (I.isAtomic()) 3234 return visitAtomicLoad(I); 3235 3236 const Value *SV = I.getOperand(0); 3237 SDValue Ptr = getValue(SV); 3238 3239 Type *Ty = I.getType(); 3240 3241 bool isVolatile = I.isVolatile(); 3242 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3243 bool isInvariant = I.getMetadata("invariant.load") != 0; 3244 unsigned Alignment = I.getAlignment(); 3245 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3246 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 3247 3248 SmallVector<EVT, 4> ValueVTs; 3249 SmallVector<uint64_t, 4> Offsets; 3250 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3251 unsigned NumValues = ValueVTs.size(); 3252 if (NumValues == 0) 3253 return; 3254 3255 SDValue Root; 3256 bool ConstantMemory = false; 3257 if (I.isVolatile() || NumValues > MaxParallelChains) 3258 // Serialize volatile loads with other side effects. 3259 Root = getRoot(); 3260 else if (AA->pointsToConstantMemory( 3261 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3262 // Do not serialize (non-volatile) loads of constant memory with anything. 3263 Root = DAG.getEntryNode(); 3264 ConstantMemory = true; 3265 } else { 3266 // Do not serialize non-volatile loads against each other. 3267 Root = DAG.getRoot(); 3268 } 3269 3270 SmallVector<SDValue, 4> Values(NumValues); 3271 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3272 NumValues)); 3273 EVT PtrVT = Ptr.getValueType(); 3274 unsigned ChainI = 0; 3275 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3276 // Serializing loads here may result in excessive register pressure, and 3277 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3278 // could recover a bit by hoisting nodes upward in the chain by recognizing 3279 // they are side-effect free or do not alias. The optimizer should really 3280 // avoid this case by converting large object/array copies to llvm.memcpy 3281 // (MaxParallelChains should always remain as failsafe). 3282 if (ChainI == MaxParallelChains) { 3283 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3284 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3285 MVT::Other, &Chains[0], ChainI); 3286 Root = Chain; 3287 ChainI = 0; 3288 } 3289 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3290 PtrVT, Ptr, 3291 DAG.getConstant(Offsets[i], PtrVT)); 3292 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3293 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3294 isNonTemporal, isInvariant, Alignment, TBAAInfo, 3295 Ranges); 3296 3297 Values[i] = L; 3298 Chains[ChainI] = L.getValue(1); 3299 } 3300 3301 if (!ConstantMemory) { 3302 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3303 MVT::Other, &Chains[0], ChainI); 3304 if (isVolatile) 3305 DAG.setRoot(Chain); 3306 else 3307 PendingLoads.push_back(Chain); 3308 } 3309 3310 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3311 DAG.getVTList(&ValueVTs[0], NumValues), 3312 &Values[0], NumValues)); 3313} 3314 3315void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3316 if (I.isAtomic()) 3317 return visitAtomicStore(I); 3318 3319 const Value *SrcV = I.getOperand(0); 3320 const Value *PtrV = I.getOperand(1); 3321 3322 SmallVector<EVT, 4> ValueVTs; 3323 SmallVector<uint64_t, 4> Offsets; 3324 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3325 unsigned NumValues = ValueVTs.size(); 3326 if (NumValues == 0) 3327 return; 3328 3329 // Get the lowered operands. Note that we do this after 3330 // checking if NumResults is zero, because with zero results 3331 // the operands won't have values in the map. 3332 SDValue Src = getValue(SrcV); 3333 SDValue Ptr = getValue(PtrV); 3334 3335 SDValue Root = getRoot(); 3336 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3337 NumValues)); 3338 EVT PtrVT = Ptr.getValueType(); 3339 bool isVolatile = I.isVolatile(); 3340 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3341 unsigned Alignment = I.getAlignment(); 3342 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3343 3344 unsigned ChainI = 0; 3345 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3346 // See visitLoad comments. 3347 if (ChainI == MaxParallelChains) { 3348 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3349 MVT::Other, &Chains[0], ChainI); 3350 Root = Chain; 3351 ChainI = 0; 3352 } 3353 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3354 DAG.getConstant(Offsets[i], PtrVT)); 3355 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3356 SDValue(Src.getNode(), Src.getResNo() + i), 3357 Add, MachinePointerInfo(PtrV, Offsets[i]), 3358 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3359 Chains[ChainI] = St; 3360 } 3361 3362 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3363 MVT::Other, &Chains[0], ChainI); 3364 ++SDNodeOrder; 3365 AssignOrderingToNode(StoreNode.getNode()); 3366 DAG.setRoot(StoreNode); 3367} 3368 3369static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3370 SynchronizationScope Scope, 3371 bool Before, DebugLoc dl, 3372 SelectionDAG &DAG, 3373 const TargetLowering &TLI) { 3374 // Fence, if necessary 3375 if (Before) { 3376 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3377 Order = Release; 3378 else if (Order == Acquire || Order == Monotonic) 3379 return Chain; 3380 } else { 3381 if (Order == AcquireRelease) 3382 Order = Acquire; 3383 else if (Order == Release || Order == Monotonic) 3384 return Chain; 3385 } 3386 SDValue Ops[3]; 3387 Ops[0] = Chain; 3388 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3389 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3390 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3391} 3392 3393void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3394 DebugLoc dl = getCurDebugLoc(); 3395 AtomicOrdering Order = I.getOrdering(); 3396 SynchronizationScope Scope = I.getSynchScope(); 3397 3398 SDValue InChain = getRoot(); 3399 3400 if (TLI.getInsertFencesForAtomic()) 3401 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3402 DAG, TLI); 3403 3404 SDValue L = 3405 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3406 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3407 InChain, 3408 getValue(I.getPointerOperand()), 3409 getValue(I.getCompareOperand()), 3410 getValue(I.getNewValOperand()), 3411 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3412 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3413 Scope); 3414 3415 SDValue OutChain = L.getValue(1); 3416 3417 if (TLI.getInsertFencesForAtomic()) 3418 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3419 DAG, TLI); 3420 3421 setValue(&I, L); 3422 DAG.setRoot(OutChain); 3423} 3424 3425void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3426 DebugLoc dl = getCurDebugLoc(); 3427 ISD::NodeType NT; 3428 switch (I.getOperation()) { 3429 default: llvm_unreachable("Unknown atomicrmw operation"); 3430 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3431 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3432 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3433 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3434 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3435 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3436 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3437 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3438 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3439 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3440 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3441 } 3442 AtomicOrdering Order = I.getOrdering(); 3443 SynchronizationScope Scope = I.getSynchScope(); 3444 3445 SDValue InChain = getRoot(); 3446 3447 if (TLI.getInsertFencesForAtomic()) 3448 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3449 DAG, TLI); 3450 3451 SDValue L = 3452 DAG.getAtomic(NT, dl, 3453 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3454 InChain, 3455 getValue(I.getPointerOperand()), 3456 getValue(I.getValOperand()), 3457 I.getPointerOperand(), 0 /* Alignment */, 3458 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3459 Scope); 3460 3461 SDValue OutChain = L.getValue(1); 3462 3463 if (TLI.getInsertFencesForAtomic()) 3464 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3465 DAG, TLI); 3466 3467 setValue(&I, L); 3468 DAG.setRoot(OutChain); 3469} 3470 3471void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3472 DebugLoc dl = getCurDebugLoc(); 3473 SDValue Ops[3]; 3474 Ops[0] = getRoot(); 3475 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3476 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3477 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3478} 3479 3480void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3481 DebugLoc dl = getCurDebugLoc(); 3482 AtomicOrdering Order = I.getOrdering(); 3483 SynchronizationScope Scope = I.getSynchScope(); 3484 3485 SDValue InChain = getRoot(); 3486 3487 EVT VT = TLI.getValueType(I.getType()); 3488 3489 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3490 report_fatal_error("Cannot generate unaligned atomic load"); 3491 3492 SDValue L = 3493 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3494 getValue(I.getPointerOperand()), 3495 I.getPointerOperand(), I.getAlignment(), 3496 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3497 Scope); 3498 3499 SDValue OutChain = L.getValue(1); 3500 3501 if (TLI.getInsertFencesForAtomic()) 3502 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3503 DAG, TLI); 3504 3505 setValue(&I, L); 3506 DAG.setRoot(OutChain); 3507} 3508 3509void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3510 DebugLoc dl = getCurDebugLoc(); 3511 3512 AtomicOrdering Order = I.getOrdering(); 3513 SynchronizationScope Scope = I.getSynchScope(); 3514 3515 SDValue InChain = getRoot(); 3516 3517 EVT VT = TLI.getValueType(I.getValueOperand()->getType()); 3518 3519 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3520 report_fatal_error("Cannot generate unaligned atomic store"); 3521 3522 if (TLI.getInsertFencesForAtomic()) 3523 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3524 DAG, TLI); 3525 3526 SDValue OutChain = 3527 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3528 InChain, 3529 getValue(I.getPointerOperand()), 3530 getValue(I.getValueOperand()), 3531 I.getPointerOperand(), I.getAlignment(), 3532 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3533 Scope); 3534 3535 if (TLI.getInsertFencesForAtomic()) 3536 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3537 DAG, TLI); 3538 3539 DAG.setRoot(OutChain); 3540} 3541 3542/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3543/// node. 3544void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3545 unsigned Intrinsic) { 3546 bool HasChain = !I.doesNotAccessMemory(); 3547 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3548 3549 // Build the operand list. 3550 SmallVector<SDValue, 8> Ops; 3551 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3552 if (OnlyLoad) { 3553 // We don't need to serialize loads against other loads. 3554 Ops.push_back(DAG.getRoot()); 3555 } else { 3556 Ops.push_back(getRoot()); 3557 } 3558 } 3559 3560 // Info is set by getTgtMemInstrinsic 3561 TargetLowering::IntrinsicInfo Info; 3562 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3563 3564 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3565 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3566 Info.opc == ISD::INTRINSIC_W_CHAIN) 3567 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy())); 3568 3569 // Add all operands of the call to the operand list. 3570 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3571 SDValue Op = getValue(I.getArgOperand(i)); 3572 Ops.push_back(Op); 3573 } 3574 3575 SmallVector<EVT, 4> ValueVTs; 3576 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3577 3578 if (HasChain) 3579 ValueVTs.push_back(MVT::Other); 3580 3581 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3582 3583 // Create the node. 3584 SDValue Result; 3585 if (IsTgtIntrinsic) { 3586 // This is target intrinsic that touches memory 3587 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3588 VTs, &Ops[0], Ops.size(), 3589 Info.memVT, 3590 MachinePointerInfo(Info.ptrVal, Info.offset), 3591 Info.align, Info.vol, 3592 Info.readMem, Info.writeMem); 3593 } else if (!HasChain) { 3594 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3595 VTs, &Ops[0], Ops.size()); 3596 } else if (!I.getType()->isVoidTy()) { 3597 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3598 VTs, &Ops[0], Ops.size()); 3599 } else { 3600 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3601 VTs, &Ops[0], Ops.size()); 3602 } 3603 3604 if (HasChain) { 3605 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3606 if (OnlyLoad) 3607 PendingLoads.push_back(Chain); 3608 else 3609 DAG.setRoot(Chain); 3610 } 3611 3612 if (!I.getType()->isVoidTy()) { 3613 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3614 EVT VT = TLI.getValueType(PTy); 3615 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3616 } 3617 3618 setValue(&I, Result); 3619 } else { 3620 // Assign order to result here. If the intrinsic does not produce a result, 3621 // it won't be mapped to a SDNode and visit() will not assign it an order 3622 // number. 3623 ++SDNodeOrder; 3624 AssignOrderingToNode(Result.getNode()); 3625 } 3626} 3627 3628/// GetSignificand - Get the significand and build it into a floating-point 3629/// number with exponent of 1: 3630/// 3631/// Op = (Op & 0x007fffff) | 0x3f800000; 3632/// 3633/// where Op is the hexidecimal representation of floating point value. 3634static SDValue 3635GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3636 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3637 DAG.getConstant(0x007fffff, MVT::i32)); 3638 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3639 DAG.getConstant(0x3f800000, MVT::i32)); 3640 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3641} 3642 3643/// GetExponent - Get the exponent: 3644/// 3645/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3646/// 3647/// where Op is the hexidecimal representation of floating point value. 3648static SDValue 3649GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3650 DebugLoc dl) { 3651 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3652 DAG.getConstant(0x7f800000, MVT::i32)); 3653 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3654 DAG.getConstant(23, TLI.getPointerTy())); 3655 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3656 DAG.getConstant(127, MVT::i32)); 3657 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3658} 3659 3660/// getF32Constant - Get 32-bit floating point constant. 3661static SDValue 3662getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3663 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3664} 3665 3666/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3667/// limited-precision mode. 3668void 3669SelectionDAGBuilder::visitExp(const CallInst &I) { 3670 SDValue result; 3671 DebugLoc dl = getCurDebugLoc(); 3672 3673 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3674 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3675 SDValue Op = getValue(I.getArgOperand(0)); 3676 3677 // Put the exponent in the right bit position for later addition to the 3678 // final result: 3679 // 3680 // #define LOG2OFe 1.4426950f 3681 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3682 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3683 getF32Constant(DAG, 0x3fb8aa3b)); 3684 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3685 3686 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3687 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3688 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3689 3690 // IntegerPartOfX <<= 23; 3691 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3692 DAG.getConstant(23, TLI.getPointerTy())); 3693 3694 if (LimitFloatPrecision <= 6) { 3695 // For floating-point precision of 6: 3696 // 3697 // TwoToFractionalPartOfX = 3698 // 0.997535578f + 3699 // (0.735607626f + 0.252464424f * x) * x; 3700 // 3701 // error 0.0144103317, which is 6 bits 3702 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3703 getF32Constant(DAG, 0x3e814304)); 3704 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3705 getF32Constant(DAG, 0x3f3c50c8)); 3706 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3707 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3708 getF32Constant(DAG, 0x3f7f5e7e)); 3709 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3710 3711 // Add the exponent into the result in integer domain. 3712 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3713 TwoToFracPartOfX, IntegerPartOfX); 3714 3715 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3716 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3717 // For floating-point precision of 12: 3718 // 3719 // TwoToFractionalPartOfX = 3720 // 0.999892986f + 3721 // (0.696457318f + 3722 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3723 // 3724 // 0.000107046256 error, which is 13 to 14 bits 3725 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3726 getF32Constant(DAG, 0x3da235e3)); 3727 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3728 getF32Constant(DAG, 0x3e65b8f3)); 3729 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3730 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3731 getF32Constant(DAG, 0x3f324b07)); 3732 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3733 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3734 getF32Constant(DAG, 0x3f7ff8fd)); 3735 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3736 3737 // Add the exponent into the result in integer domain. 3738 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3739 TwoToFracPartOfX, IntegerPartOfX); 3740 3741 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3742 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3743 // For floating-point precision of 18: 3744 // 3745 // TwoToFractionalPartOfX = 3746 // 0.999999982f + 3747 // (0.693148872f + 3748 // (0.240227044f + 3749 // (0.554906021e-1f + 3750 // (0.961591928e-2f + 3751 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3752 // 3753 // error 2.47208000*10^(-7), which is better than 18 bits 3754 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3755 getF32Constant(DAG, 0x3924b03e)); 3756 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3757 getF32Constant(DAG, 0x3ab24b87)); 3758 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3759 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3760 getF32Constant(DAG, 0x3c1d8c17)); 3761 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3762 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3763 getF32Constant(DAG, 0x3d634a1d)); 3764 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3765 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3766 getF32Constant(DAG, 0x3e75fe14)); 3767 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3768 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3769 getF32Constant(DAG, 0x3f317234)); 3770 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3771 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3772 getF32Constant(DAG, 0x3f800000)); 3773 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3774 MVT::i32, t13); 3775 3776 // Add the exponent into the result in integer domain. 3777 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3778 TwoToFracPartOfX, IntegerPartOfX); 3779 3780 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3781 } 3782 } else { 3783 // No special expansion. 3784 result = DAG.getNode(ISD::FEXP, dl, 3785 getValue(I.getArgOperand(0)).getValueType(), 3786 getValue(I.getArgOperand(0))); 3787 } 3788 3789 setValue(&I, result); 3790} 3791 3792/// visitLog - Lower a log intrinsic. Handles the special sequences for 3793/// limited-precision mode. 3794void 3795SelectionDAGBuilder::visitLog(const CallInst &I) { 3796 SDValue result; 3797 DebugLoc dl = getCurDebugLoc(); 3798 3799 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3800 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3801 SDValue Op = getValue(I.getArgOperand(0)); 3802 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3803 3804 // Scale the exponent by log(2) [0.69314718f]. 3805 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3806 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3807 getF32Constant(DAG, 0x3f317218)); 3808 3809 // Get the significand and build it into a floating-point number with 3810 // exponent of 1. 3811 SDValue X = GetSignificand(DAG, Op1, dl); 3812 3813 if (LimitFloatPrecision <= 6) { 3814 // For floating-point precision of 6: 3815 // 3816 // LogofMantissa = 3817 // -1.1609546f + 3818 // (1.4034025f - 0.23903021f * x) * x; 3819 // 3820 // error 0.0034276066, which is better than 8 bits 3821 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3822 getF32Constant(DAG, 0xbe74c456)); 3823 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3824 getF32Constant(DAG, 0x3fb3a2b1)); 3825 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3826 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3827 getF32Constant(DAG, 0x3f949a29)); 3828 3829 result = DAG.getNode(ISD::FADD, dl, 3830 MVT::f32, LogOfExponent, LogOfMantissa); 3831 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3832 // For floating-point precision of 12: 3833 // 3834 // LogOfMantissa = 3835 // -1.7417939f + 3836 // (2.8212026f + 3837 // (-1.4699568f + 3838 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3839 // 3840 // error 0.000061011436, which is 14 bits 3841 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3842 getF32Constant(DAG, 0xbd67b6d6)); 3843 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3844 getF32Constant(DAG, 0x3ee4f4b8)); 3845 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3846 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3847 getF32Constant(DAG, 0x3fbc278b)); 3848 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3849 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3850 getF32Constant(DAG, 0x40348e95)); 3851 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3852 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3853 getF32Constant(DAG, 0x3fdef31a)); 3854 3855 result = DAG.getNode(ISD::FADD, dl, 3856 MVT::f32, LogOfExponent, LogOfMantissa); 3857 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3858 // For floating-point precision of 18: 3859 // 3860 // LogOfMantissa = 3861 // -2.1072184f + 3862 // (4.2372794f + 3863 // (-3.7029485f + 3864 // (2.2781945f + 3865 // (-0.87823314f + 3866 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3867 // 3868 // error 0.0000023660568, which is better than 18 bits 3869 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3870 getF32Constant(DAG, 0xbc91e5ac)); 3871 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3872 getF32Constant(DAG, 0x3e4350aa)); 3873 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3874 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3875 getF32Constant(DAG, 0x3f60d3e3)); 3876 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3877 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3878 getF32Constant(DAG, 0x4011cdf0)); 3879 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3880 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3881 getF32Constant(DAG, 0x406cfd1c)); 3882 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3883 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3884 getF32Constant(DAG, 0x408797cb)); 3885 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3886 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3887 getF32Constant(DAG, 0x4006dcab)); 3888 3889 result = DAG.getNode(ISD::FADD, dl, 3890 MVT::f32, LogOfExponent, LogOfMantissa); 3891 } 3892 } else { 3893 // No special expansion. 3894 result = DAG.getNode(ISD::FLOG, dl, 3895 getValue(I.getArgOperand(0)).getValueType(), 3896 getValue(I.getArgOperand(0))); 3897 } 3898 3899 setValue(&I, result); 3900} 3901 3902/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3903/// limited-precision mode. 3904void 3905SelectionDAGBuilder::visitLog2(const CallInst &I) { 3906 SDValue result; 3907 DebugLoc dl = getCurDebugLoc(); 3908 3909 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3910 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3911 SDValue Op = getValue(I.getArgOperand(0)); 3912 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3913 3914 // Get the exponent. 3915 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3916 3917 // Get the significand and build it into a floating-point number with 3918 // exponent of 1. 3919 SDValue X = GetSignificand(DAG, Op1, dl); 3920 3921 // Different possible minimax approximations of significand in 3922 // floating-point for various degrees of accuracy over [1,2]. 3923 if (LimitFloatPrecision <= 6) { 3924 // For floating-point precision of 6: 3925 // 3926 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3927 // 3928 // error 0.0049451742, which is more than 7 bits 3929 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3930 getF32Constant(DAG, 0xbeb08fe0)); 3931 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3932 getF32Constant(DAG, 0x40019463)); 3933 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3934 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3935 getF32Constant(DAG, 0x3fd6633d)); 3936 3937 result = DAG.getNode(ISD::FADD, dl, 3938 MVT::f32, LogOfExponent, Log2ofMantissa); 3939 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3940 // For floating-point precision of 12: 3941 // 3942 // Log2ofMantissa = 3943 // -2.51285454f + 3944 // (4.07009056f + 3945 // (-2.12067489f + 3946 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3947 // 3948 // error 0.0000876136000, which is better than 13 bits 3949 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3950 getF32Constant(DAG, 0xbda7262e)); 3951 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3952 getF32Constant(DAG, 0x3f25280b)); 3953 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3954 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3955 getF32Constant(DAG, 0x4007b923)); 3956 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3957 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3958 getF32Constant(DAG, 0x40823e2f)); 3959 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3960 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3961 getF32Constant(DAG, 0x4020d29c)); 3962 3963 result = DAG.getNode(ISD::FADD, dl, 3964 MVT::f32, LogOfExponent, Log2ofMantissa); 3965 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3966 // For floating-point precision of 18: 3967 // 3968 // Log2ofMantissa = 3969 // -3.0400495f + 3970 // (6.1129976f + 3971 // (-5.3420409f + 3972 // (3.2865683f + 3973 // (-1.2669343f + 3974 // (0.27515199f - 3975 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3976 // 3977 // error 0.0000018516, which is better than 18 bits 3978 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3979 getF32Constant(DAG, 0xbcd2769e)); 3980 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3981 getF32Constant(DAG, 0x3e8ce0b9)); 3982 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3983 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3984 getF32Constant(DAG, 0x3fa22ae7)); 3985 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3986 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3987 getF32Constant(DAG, 0x40525723)); 3988 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3989 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3990 getF32Constant(DAG, 0x40aaf200)); 3991 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3992 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3993 getF32Constant(DAG, 0x40c39dad)); 3994 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3995 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3996 getF32Constant(DAG, 0x4042902c)); 3997 3998 result = DAG.getNode(ISD::FADD, dl, 3999 MVT::f32, LogOfExponent, Log2ofMantissa); 4000 } 4001 } else { 4002 // No special expansion. 4003 result = DAG.getNode(ISD::FLOG2, dl, 4004 getValue(I.getArgOperand(0)).getValueType(), 4005 getValue(I.getArgOperand(0))); 4006 } 4007 4008 setValue(&I, result); 4009} 4010 4011/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 4012/// limited-precision mode. 4013void 4014SelectionDAGBuilder::visitLog10(const CallInst &I) { 4015 SDValue result; 4016 DebugLoc dl = getCurDebugLoc(); 4017 4018 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 4019 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4020 SDValue Op = getValue(I.getArgOperand(0)); 4021 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 4022 4023 // Scale the exponent by log10(2) [0.30102999f]. 4024 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 4025 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 4026 getF32Constant(DAG, 0x3e9a209a)); 4027 4028 // Get the significand and build it into a floating-point number with 4029 // exponent of 1. 4030 SDValue X = GetSignificand(DAG, Op1, dl); 4031 4032 if (LimitFloatPrecision <= 6) { 4033 // For floating-point precision of 6: 4034 // 4035 // Log10ofMantissa = 4036 // -0.50419619f + 4037 // (0.60948995f - 0.10380950f * x) * x; 4038 // 4039 // error 0.0014886165, which is 6 bits 4040 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4041 getF32Constant(DAG, 0xbdd49a13)); 4042 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4043 getF32Constant(DAG, 0x3f1c0789)); 4044 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4045 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4046 getF32Constant(DAG, 0x3f011300)); 4047 4048 result = DAG.getNode(ISD::FADD, dl, 4049 MVT::f32, LogOfExponent, Log10ofMantissa); 4050 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4051 // For floating-point precision of 12: 4052 // 4053 // Log10ofMantissa = 4054 // -0.64831180f + 4055 // (0.91751397f + 4056 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4057 // 4058 // error 0.00019228036, which is better than 12 bits 4059 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4060 getF32Constant(DAG, 0x3d431f31)); 4061 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4062 getF32Constant(DAG, 0x3ea21fb2)); 4063 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4064 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4065 getF32Constant(DAG, 0x3f6ae232)); 4066 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4067 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4068 getF32Constant(DAG, 0x3f25f7c3)); 4069 4070 result = DAG.getNode(ISD::FADD, dl, 4071 MVT::f32, LogOfExponent, Log10ofMantissa); 4072 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4073 // For floating-point precision of 18: 4074 // 4075 // Log10ofMantissa = 4076 // -0.84299375f + 4077 // (1.5327582f + 4078 // (-1.0688956f + 4079 // (0.49102474f + 4080 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4081 // 4082 // error 0.0000037995730, which is better than 18 bits 4083 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4084 getF32Constant(DAG, 0x3c5d51ce)); 4085 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4086 getF32Constant(DAG, 0x3e00685a)); 4087 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4088 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4089 getF32Constant(DAG, 0x3efb6798)); 4090 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4091 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4092 getF32Constant(DAG, 0x3f88d192)); 4093 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4094 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4095 getF32Constant(DAG, 0x3fc4316c)); 4096 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4097 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4098 getF32Constant(DAG, 0x3f57ce70)); 4099 4100 result = DAG.getNode(ISD::FADD, dl, 4101 MVT::f32, LogOfExponent, Log10ofMantissa); 4102 } 4103 } else { 4104 // No special expansion. 4105 result = DAG.getNode(ISD::FLOG10, dl, 4106 getValue(I.getArgOperand(0)).getValueType(), 4107 getValue(I.getArgOperand(0))); 4108 } 4109 4110 setValue(&I, result); 4111} 4112 4113/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4114/// limited-precision mode. 4115void 4116SelectionDAGBuilder::visitExp2(const CallInst &I) { 4117 SDValue result; 4118 DebugLoc dl = getCurDebugLoc(); 4119 4120 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 4121 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4122 SDValue Op = getValue(I.getArgOperand(0)); 4123 4124 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4125 4126 // FractionalPartOfX = x - (float)IntegerPartOfX; 4127 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4128 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4129 4130 // IntegerPartOfX <<= 23; 4131 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4132 DAG.getConstant(23, TLI.getPointerTy())); 4133 4134 if (LimitFloatPrecision <= 6) { 4135 // For floating-point precision of 6: 4136 // 4137 // TwoToFractionalPartOfX = 4138 // 0.997535578f + 4139 // (0.735607626f + 0.252464424f * x) * x; 4140 // 4141 // error 0.0144103317, which is 6 bits 4142 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4143 getF32Constant(DAG, 0x3e814304)); 4144 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4145 getF32Constant(DAG, 0x3f3c50c8)); 4146 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4147 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4148 getF32Constant(DAG, 0x3f7f5e7e)); 4149 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4150 SDValue TwoToFractionalPartOfX = 4151 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4152 4153 result = DAG.getNode(ISD::BITCAST, dl, 4154 MVT::f32, TwoToFractionalPartOfX); 4155 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4156 // For floating-point precision of 12: 4157 // 4158 // TwoToFractionalPartOfX = 4159 // 0.999892986f + 4160 // (0.696457318f + 4161 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4162 // 4163 // error 0.000107046256, which is 13 to 14 bits 4164 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4165 getF32Constant(DAG, 0x3da235e3)); 4166 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4167 getF32Constant(DAG, 0x3e65b8f3)); 4168 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4169 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4170 getF32Constant(DAG, 0x3f324b07)); 4171 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4172 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4173 getF32Constant(DAG, 0x3f7ff8fd)); 4174 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4175 SDValue TwoToFractionalPartOfX = 4176 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4177 4178 result = DAG.getNode(ISD::BITCAST, dl, 4179 MVT::f32, TwoToFractionalPartOfX); 4180 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4181 // For floating-point precision of 18: 4182 // 4183 // TwoToFractionalPartOfX = 4184 // 0.999999982f + 4185 // (0.693148872f + 4186 // (0.240227044f + 4187 // (0.554906021e-1f + 4188 // (0.961591928e-2f + 4189 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4190 // error 2.47208000*10^(-7), which is better than 18 bits 4191 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4192 getF32Constant(DAG, 0x3924b03e)); 4193 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4194 getF32Constant(DAG, 0x3ab24b87)); 4195 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4196 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4197 getF32Constant(DAG, 0x3c1d8c17)); 4198 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4199 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4200 getF32Constant(DAG, 0x3d634a1d)); 4201 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4202 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4203 getF32Constant(DAG, 0x3e75fe14)); 4204 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4205 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4206 getF32Constant(DAG, 0x3f317234)); 4207 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4208 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4209 getF32Constant(DAG, 0x3f800000)); 4210 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4211 SDValue TwoToFractionalPartOfX = 4212 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4213 4214 result = DAG.getNode(ISD::BITCAST, dl, 4215 MVT::f32, TwoToFractionalPartOfX); 4216 } 4217 } else { 4218 // No special expansion. 4219 result = DAG.getNode(ISD::FEXP2, dl, 4220 getValue(I.getArgOperand(0)).getValueType(), 4221 getValue(I.getArgOperand(0))); 4222 } 4223 4224 setValue(&I, result); 4225} 4226 4227/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4228/// limited-precision mode with x == 10.0f. 4229void 4230SelectionDAGBuilder::visitPow(const CallInst &I) { 4231 SDValue result; 4232 const Value *Val = I.getArgOperand(0); 4233 DebugLoc dl = getCurDebugLoc(); 4234 bool IsExp10 = false; 4235 4236 if (getValue(Val).getValueType() == MVT::f32 && 4237 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4238 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4239 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4240 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4241 APFloat Ten(10.0f); 4242 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4243 } 4244 } 4245 } 4246 4247 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4248 SDValue Op = getValue(I.getArgOperand(1)); 4249 4250 // Put the exponent in the right bit position for later addition to the 4251 // final result: 4252 // 4253 // #define LOG2OF10 3.3219281f 4254 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4255 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4256 getF32Constant(DAG, 0x40549a78)); 4257 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4258 4259 // FractionalPartOfX = x - (float)IntegerPartOfX; 4260 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4261 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4262 4263 // IntegerPartOfX <<= 23; 4264 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4265 DAG.getConstant(23, TLI.getPointerTy())); 4266 4267 if (LimitFloatPrecision <= 6) { 4268 // For floating-point precision of 6: 4269 // 4270 // twoToFractionalPartOfX = 4271 // 0.997535578f + 4272 // (0.735607626f + 0.252464424f * x) * x; 4273 // 4274 // error 0.0144103317, which is 6 bits 4275 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4276 getF32Constant(DAG, 0x3e814304)); 4277 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4278 getF32Constant(DAG, 0x3f3c50c8)); 4279 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4280 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4281 getF32Constant(DAG, 0x3f7f5e7e)); 4282 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4283 SDValue TwoToFractionalPartOfX = 4284 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4285 4286 result = DAG.getNode(ISD::BITCAST, dl, 4287 MVT::f32, TwoToFractionalPartOfX); 4288 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4289 // For floating-point precision of 12: 4290 // 4291 // TwoToFractionalPartOfX = 4292 // 0.999892986f + 4293 // (0.696457318f + 4294 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4295 // 4296 // error 0.000107046256, which is 13 to 14 bits 4297 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4298 getF32Constant(DAG, 0x3da235e3)); 4299 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4300 getF32Constant(DAG, 0x3e65b8f3)); 4301 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4302 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4303 getF32Constant(DAG, 0x3f324b07)); 4304 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4305 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4306 getF32Constant(DAG, 0x3f7ff8fd)); 4307 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4308 SDValue TwoToFractionalPartOfX = 4309 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4310 4311 result = DAG.getNode(ISD::BITCAST, dl, 4312 MVT::f32, TwoToFractionalPartOfX); 4313 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4314 // For floating-point precision of 18: 4315 // 4316 // TwoToFractionalPartOfX = 4317 // 0.999999982f + 4318 // (0.693148872f + 4319 // (0.240227044f + 4320 // (0.554906021e-1f + 4321 // (0.961591928e-2f + 4322 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4323 // error 2.47208000*10^(-7), which is better than 18 bits 4324 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4325 getF32Constant(DAG, 0x3924b03e)); 4326 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4327 getF32Constant(DAG, 0x3ab24b87)); 4328 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4329 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4330 getF32Constant(DAG, 0x3c1d8c17)); 4331 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4332 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4333 getF32Constant(DAG, 0x3d634a1d)); 4334 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4335 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4336 getF32Constant(DAG, 0x3e75fe14)); 4337 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4338 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4339 getF32Constant(DAG, 0x3f317234)); 4340 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4341 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4342 getF32Constant(DAG, 0x3f800000)); 4343 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4344 SDValue TwoToFractionalPartOfX = 4345 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4346 4347 result = DAG.getNode(ISD::BITCAST, dl, 4348 MVT::f32, TwoToFractionalPartOfX); 4349 } 4350 } else { 4351 // No special expansion. 4352 result = DAG.getNode(ISD::FPOW, dl, 4353 getValue(I.getArgOperand(0)).getValueType(), 4354 getValue(I.getArgOperand(0)), 4355 getValue(I.getArgOperand(1))); 4356 } 4357 4358 setValue(&I, result); 4359} 4360 4361 4362/// ExpandPowI - Expand a llvm.powi intrinsic. 4363static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4364 SelectionDAG &DAG) { 4365 // If RHS is a constant, we can expand this out to a multiplication tree, 4366 // otherwise we end up lowering to a call to __powidf2 (for example). When 4367 // optimizing for size, we only want to do this if the expansion would produce 4368 // a small number of multiplies, otherwise we do the full expansion. 4369 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4370 // Get the exponent as a positive value. 4371 unsigned Val = RHSC->getSExtValue(); 4372 if ((int)Val < 0) Val = -Val; 4373 4374 // powi(x, 0) -> 1.0 4375 if (Val == 0) 4376 return DAG.getConstantFP(1.0, LHS.getValueType()); 4377 4378 const Function *F = DAG.getMachineFunction().getFunction(); 4379 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4380 // If optimizing for size, don't insert too many multiplies. This 4381 // inserts up to 5 multiplies. 4382 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4383 // We use the simple binary decomposition method to generate the multiply 4384 // sequence. There are more optimal ways to do this (for example, 4385 // powi(x,15) generates one more multiply than it should), but this has 4386 // the benefit of being both really simple and much better than a libcall. 4387 SDValue Res; // Logically starts equal to 1.0 4388 SDValue CurSquare = LHS; 4389 while (Val) { 4390 if (Val & 1) { 4391 if (Res.getNode()) 4392 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4393 else 4394 Res = CurSquare; // 1.0*CurSquare. 4395 } 4396 4397 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4398 CurSquare, CurSquare); 4399 Val >>= 1; 4400 } 4401 4402 // If the original was negative, invert the result, producing 1/(x*x*x). 4403 if (RHSC->getSExtValue() < 0) 4404 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4405 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4406 return Res; 4407 } 4408 } 4409 4410 // Otherwise, expand to a libcall. 4411 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4412} 4413 4414// getTruncatedArgReg - Find underlying register used for an truncated 4415// argument. 4416static unsigned getTruncatedArgReg(const SDValue &N) { 4417 if (N.getOpcode() != ISD::TRUNCATE) 4418 return 0; 4419 4420 const SDValue &Ext = N.getOperand(0); 4421 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4422 const SDValue &CFR = Ext.getOperand(0); 4423 if (CFR.getOpcode() == ISD::CopyFromReg) 4424 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4425 if (CFR.getOpcode() == ISD::TRUNCATE) 4426 return getTruncatedArgReg(CFR); 4427 } 4428 return 0; 4429} 4430 4431/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4432/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4433/// At the end of instruction selection, they will be inserted to the entry BB. 4434bool 4435SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4436 int64_t Offset, 4437 const SDValue &N) { 4438 const Argument *Arg = dyn_cast<Argument>(V); 4439 if (!Arg) 4440 return false; 4441 4442 MachineFunction &MF = DAG.getMachineFunction(); 4443 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4444 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4445 4446 // Ignore inlined function arguments here. 4447 DIVariable DV(Variable); 4448 if (DV.isInlinedFnArgument(MF.getFunction())) 4449 return false; 4450 4451 unsigned Reg = 0; 4452 // Some arguments' frame index is recorded during argument lowering. 4453 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4454 if (Offset) 4455 Reg = TRI->getFrameRegister(MF); 4456 4457 if (!Reg && N.getNode()) { 4458 if (N.getOpcode() == ISD::CopyFromReg) 4459 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4460 else 4461 Reg = getTruncatedArgReg(N); 4462 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4463 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4464 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4465 if (PR) 4466 Reg = PR; 4467 } 4468 } 4469 4470 if (!Reg) { 4471 // Check if ValueMap has reg number. 4472 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4473 if (VMI != FuncInfo.ValueMap.end()) 4474 Reg = VMI->second; 4475 } 4476 4477 if (!Reg && N.getNode()) { 4478 // Check if frame index is available. 4479 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4480 if (FrameIndexSDNode *FINode = 4481 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4482 Reg = TRI->getFrameRegister(MF); 4483 Offset = FINode->getIndex(); 4484 } 4485 } 4486 4487 if (!Reg) 4488 return false; 4489 4490 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4491 TII->get(TargetOpcode::DBG_VALUE)) 4492 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4493 FuncInfo.ArgDbgValues.push_back(&*MIB); 4494 return true; 4495} 4496 4497// VisualStudio defines setjmp as _setjmp 4498#if defined(_MSC_VER) && defined(setjmp) && \ 4499 !defined(setjmp_undefined_for_msvc) 4500# pragma push_macro("setjmp") 4501# undef setjmp 4502# define setjmp_undefined_for_msvc 4503#endif 4504 4505/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4506/// we want to emit this as a call to a named external function, return the name 4507/// otherwise lower it and return null. 4508const char * 4509SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4510 DebugLoc dl = getCurDebugLoc(); 4511 SDValue Res; 4512 4513 switch (Intrinsic) { 4514 default: 4515 // By default, turn this into a target intrinsic node. 4516 visitTargetIntrinsic(I, Intrinsic); 4517 return 0; 4518 case Intrinsic::vastart: visitVAStart(I); return 0; 4519 case Intrinsic::vaend: visitVAEnd(I); return 0; 4520 case Intrinsic::vacopy: visitVACopy(I); return 0; 4521 case Intrinsic::returnaddress: 4522 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4523 getValue(I.getArgOperand(0)))); 4524 return 0; 4525 case Intrinsic::frameaddress: 4526 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4527 getValue(I.getArgOperand(0)))); 4528 return 0; 4529 case Intrinsic::setjmp: 4530 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()]; 4531 case Intrinsic::longjmp: 4532 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()]; 4533 case Intrinsic::memcpy: { 4534 // Assert for address < 256 since we support only user defined address 4535 // spaces. 4536 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4537 < 256 && 4538 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4539 < 256 && 4540 "Unknown address space"); 4541 SDValue Op1 = getValue(I.getArgOperand(0)); 4542 SDValue Op2 = getValue(I.getArgOperand(1)); 4543 SDValue Op3 = getValue(I.getArgOperand(2)); 4544 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4545 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4546 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4547 MachinePointerInfo(I.getArgOperand(0)), 4548 MachinePointerInfo(I.getArgOperand(1)))); 4549 return 0; 4550 } 4551 case Intrinsic::memset: { 4552 // Assert for address < 256 since we support only user defined address 4553 // spaces. 4554 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4555 < 256 && 4556 "Unknown address space"); 4557 SDValue Op1 = getValue(I.getArgOperand(0)); 4558 SDValue Op2 = getValue(I.getArgOperand(1)); 4559 SDValue Op3 = getValue(I.getArgOperand(2)); 4560 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4561 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4562 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4563 MachinePointerInfo(I.getArgOperand(0)))); 4564 return 0; 4565 } 4566 case Intrinsic::memmove: { 4567 // Assert for address < 256 since we support only user defined address 4568 // spaces. 4569 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4570 < 256 && 4571 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4572 < 256 && 4573 "Unknown address space"); 4574 SDValue Op1 = getValue(I.getArgOperand(0)); 4575 SDValue Op2 = getValue(I.getArgOperand(1)); 4576 SDValue Op3 = getValue(I.getArgOperand(2)); 4577 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4578 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4579 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4580 MachinePointerInfo(I.getArgOperand(0)), 4581 MachinePointerInfo(I.getArgOperand(1)))); 4582 return 0; 4583 } 4584 case Intrinsic::dbg_declare: { 4585 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4586 MDNode *Variable = DI.getVariable(); 4587 const Value *Address = DI.getAddress(); 4588 if (!Address || !DIVariable(Variable).Verify()) { 4589 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4590 return 0; 4591 } 4592 4593 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4594 // but do not always have a corresponding SDNode built. The SDNodeOrder 4595 // absolute, but not relative, values are different depending on whether 4596 // debug info exists. 4597 ++SDNodeOrder; 4598 4599 // Check if address has undef value. 4600 if (isa<UndefValue>(Address) || 4601 (Address->use_empty() && !isa<Argument>(Address))) { 4602 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4603 return 0; 4604 } 4605 4606 SDValue &N = NodeMap[Address]; 4607 if (!N.getNode() && isa<Argument>(Address)) 4608 // Check unused arguments map. 4609 N = UnusedArgNodeMap[Address]; 4610 SDDbgValue *SDV; 4611 if (N.getNode()) { 4612 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4613 Address = BCI->getOperand(0); 4614 // Parameters are handled specially. 4615 bool isParameter = 4616 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable || 4617 isa<Argument>(Address)); 4618 4619 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4620 4621 if (isParameter && !AI) { 4622 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4623 if (FINode) 4624 // Byval parameter. We have a frame index at this point. 4625 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4626 0, dl, SDNodeOrder); 4627 else { 4628 // Address is an argument, so try to emit its dbg value using 4629 // virtual register info from the FuncInfo.ValueMap. 4630 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4631 return 0; 4632 } 4633 } else if (AI) 4634 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4635 0, dl, SDNodeOrder); 4636 else { 4637 // Can't do anything with other non-AI cases yet. 4638 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4639 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t"); 4640 DEBUG(Address->dump()); 4641 return 0; 4642 } 4643 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4644 } else { 4645 // If Address is an argument then try to emit its dbg value using 4646 // virtual register info from the FuncInfo.ValueMap. 4647 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4648 // If variable is pinned by a alloca in dominating bb then 4649 // use StaticAllocaMap. 4650 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4651 if (AI->getParent() != DI.getParent()) { 4652 DenseMap<const AllocaInst*, int>::iterator SI = 4653 FuncInfo.StaticAllocaMap.find(AI); 4654 if (SI != FuncInfo.StaticAllocaMap.end()) { 4655 SDV = DAG.getDbgValue(Variable, SI->second, 4656 0, dl, SDNodeOrder); 4657 DAG.AddDbgValue(SDV, 0, false); 4658 return 0; 4659 } 4660 } 4661 } 4662 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4663 } 4664 } 4665 return 0; 4666 } 4667 case Intrinsic::dbg_value: { 4668 const DbgValueInst &DI = cast<DbgValueInst>(I); 4669 if (!DIVariable(DI.getVariable()).Verify()) 4670 return 0; 4671 4672 MDNode *Variable = DI.getVariable(); 4673 uint64_t Offset = DI.getOffset(); 4674 const Value *V = DI.getValue(); 4675 if (!V) 4676 return 0; 4677 4678 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4679 // but do not always have a corresponding SDNode built. The SDNodeOrder 4680 // absolute, but not relative, values are different depending on whether 4681 // debug info exists. 4682 ++SDNodeOrder; 4683 SDDbgValue *SDV; 4684 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4685 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4686 DAG.AddDbgValue(SDV, 0, false); 4687 } else { 4688 // Do not use getValue() in here; we don't want to generate code at 4689 // this point if it hasn't been done yet. 4690 SDValue N = NodeMap[V]; 4691 if (!N.getNode() && isa<Argument>(V)) 4692 // Check unused arguments map. 4693 N = UnusedArgNodeMap[V]; 4694 if (N.getNode()) { 4695 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4696 SDV = DAG.getDbgValue(Variable, N.getNode(), 4697 N.getResNo(), Offset, dl, SDNodeOrder); 4698 DAG.AddDbgValue(SDV, N.getNode(), false); 4699 } 4700 } else if (!V->use_empty() ) { 4701 // Do not call getValue(V) yet, as we don't want to generate code. 4702 // Remember it for later. 4703 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4704 DanglingDebugInfoMap[V] = DDI; 4705 } else { 4706 // We may expand this to cover more cases. One case where we have no 4707 // data available is an unreferenced parameter. 4708 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4709 } 4710 } 4711 4712 // Build a debug info table entry. 4713 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4714 V = BCI->getOperand(0); 4715 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4716 // Don't handle byval struct arguments or VLAs, for example. 4717 if (!AI) { 4718 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); 4719 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); 4720 return 0; 4721 } 4722 DenseMap<const AllocaInst*, int>::iterator SI = 4723 FuncInfo.StaticAllocaMap.find(AI); 4724 if (SI == FuncInfo.StaticAllocaMap.end()) 4725 return 0; // VLAs. 4726 int FI = SI->second; 4727 4728 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4729 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4730 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4731 return 0; 4732 } 4733 4734 case Intrinsic::eh_typeid_for: { 4735 // Find the type id for the given typeinfo. 4736 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4737 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4738 Res = DAG.getConstant(TypeID, MVT::i32); 4739 setValue(&I, Res); 4740 return 0; 4741 } 4742 4743 case Intrinsic::eh_return_i32: 4744 case Intrinsic::eh_return_i64: 4745 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4746 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4747 MVT::Other, 4748 getControlRoot(), 4749 getValue(I.getArgOperand(0)), 4750 getValue(I.getArgOperand(1)))); 4751 return 0; 4752 case Intrinsic::eh_unwind_init: 4753 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4754 return 0; 4755 case Intrinsic::eh_dwarf_cfa: { 4756 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4757 TLI.getPointerTy()); 4758 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4759 TLI.getPointerTy(), 4760 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4761 TLI.getPointerTy()), 4762 CfaArg); 4763 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4764 TLI.getPointerTy(), 4765 DAG.getConstant(0, TLI.getPointerTy())); 4766 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4767 FA, Offset)); 4768 return 0; 4769 } 4770 case Intrinsic::eh_sjlj_callsite: { 4771 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4772 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4773 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4774 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4775 4776 MMI.setCurrentCallSite(CI->getZExtValue()); 4777 return 0; 4778 } 4779 case Intrinsic::eh_sjlj_functioncontext: { 4780 // Get and store the index of the function context. 4781 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4782 AllocaInst *FnCtx = 4783 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4784 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4785 MFI->setFunctionContextIndex(FI); 4786 return 0; 4787 } 4788 case Intrinsic::eh_sjlj_setjmp: { 4789 SDValue Ops[2]; 4790 Ops[0] = getRoot(); 4791 Ops[1] = getValue(I.getArgOperand(0)); 4792 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, 4793 DAG.getVTList(MVT::i32, MVT::Other), 4794 Ops, 2); 4795 setValue(&I, Op.getValue(0)); 4796 DAG.setRoot(Op.getValue(1)); 4797 return 0; 4798 } 4799 case Intrinsic::eh_sjlj_longjmp: { 4800 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4801 getRoot(), getValue(I.getArgOperand(0)))); 4802 return 0; 4803 } 4804 4805 case Intrinsic::x86_mmx_pslli_w: 4806 case Intrinsic::x86_mmx_pslli_d: 4807 case Intrinsic::x86_mmx_pslli_q: 4808 case Intrinsic::x86_mmx_psrli_w: 4809 case Intrinsic::x86_mmx_psrli_d: 4810 case Intrinsic::x86_mmx_psrli_q: 4811 case Intrinsic::x86_mmx_psrai_w: 4812 case Intrinsic::x86_mmx_psrai_d: { 4813 SDValue ShAmt = getValue(I.getArgOperand(1)); 4814 if (isa<ConstantSDNode>(ShAmt)) { 4815 visitTargetIntrinsic(I, Intrinsic); 4816 return 0; 4817 } 4818 unsigned NewIntrinsic = 0; 4819 EVT ShAmtVT = MVT::v2i32; 4820 switch (Intrinsic) { 4821 case Intrinsic::x86_mmx_pslli_w: 4822 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4823 break; 4824 case Intrinsic::x86_mmx_pslli_d: 4825 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4826 break; 4827 case Intrinsic::x86_mmx_pslli_q: 4828 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4829 break; 4830 case Intrinsic::x86_mmx_psrli_w: 4831 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4832 break; 4833 case Intrinsic::x86_mmx_psrli_d: 4834 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4835 break; 4836 case Intrinsic::x86_mmx_psrli_q: 4837 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4838 break; 4839 case Intrinsic::x86_mmx_psrai_w: 4840 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4841 break; 4842 case Intrinsic::x86_mmx_psrai_d: 4843 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4844 break; 4845 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4846 } 4847 4848 // The vector shift intrinsics with scalars uses 32b shift amounts but 4849 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4850 // to be zero. 4851 // We must do this early because v2i32 is not a legal type. 4852 DebugLoc dl = getCurDebugLoc(); 4853 SDValue ShOps[2]; 4854 ShOps[0] = ShAmt; 4855 ShOps[1] = DAG.getConstant(0, MVT::i32); 4856 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4857 EVT DestVT = TLI.getValueType(I.getType()); 4858 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4859 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4860 DAG.getConstant(NewIntrinsic, MVT::i32), 4861 getValue(I.getArgOperand(0)), ShAmt); 4862 setValue(&I, Res); 4863 return 0; 4864 } 4865 case Intrinsic::x86_avx_vinsertf128_pd_256: 4866 case Intrinsic::x86_avx_vinsertf128_ps_256: 4867 case Intrinsic::x86_avx_vinsertf128_si_256: 4868 case Intrinsic::x86_avx2_vinserti128: { 4869 DebugLoc dl = getCurDebugLoc(); 4870 EVT DestVT = TLI.getValueType(I.getType()); 4871 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType()); 4872 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) * 4873 ElVT.getVectorNumElements(); 4874 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT, 4875 getValue(I.getArgOperand(0)), 4876 getValue(I.getArgOperand(1)), 4877 DAG.getIntPtrConstant(Idx)); 4878 setValue(&I, Res); 4879 return 0; 4880 } 4881 case Intrinsic::x86_avx_vextractf128_pd_256: 4882 case Intrinsic::x86_avx_vextractf128_ps_256: 4883 case Intrinsic::x86_avx_vextractf128_si_256: 4884 case Intrinsic::x86_avx2_vextracti128: { 4885 DebugLoc dl = getCurDebugLoc(); 4886 EVT DestVT = TLI.getValueType(I.getType()); 4887 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) * 4888 DestVT.getVectorNumElements(); 4889 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, 4890 getValue(I.getArgOperand(0)), 4891 DAG.getIntPtrConstant(Idx)); 4892 setValue(&I, Res); 4893 return 0; 4894 } 4895 case Intrinsic::convertff: 4896 case Intrinsic::convertfsi: 4897 case Intrinsic::convertfui: 4898 case Intrinsic::convertsif: 4899 case Intrinsic::convertuif: 4900 case Intrinsic::convertss: 4901 case Intrinsic::convertsu: 4902 case Intrinsic::convertus: 4903 case Intrinsic::convertuu: { 4904 ISD::CvtCode Code = ISD::CVT_INVALID; 4905 switch (Intrinsic) { 4906 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4907 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4908 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4909 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4910 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4911 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4912 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4913 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4914 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4915 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4916 } 4917 EVT DestVT = TLI.getValueType(I.getType()); 4918 const Value *Op1 = I.getArgOperand(0); 4919 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4920 DAG.getValueType(DestVT), 4921 DAG.getValueType(getValue(Op1).getValueType()), 4922 getValue(I.getArgOperand(1)), 4923 getValue(I.getArgOperand(2)), 4924 Code); 4925 setValue(&I, Res); 4926 return 0; 4927 } 4928 case Intrinsic::sqrt: 4929 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4930 getValue(I.getArgOperand(0)).getValueType(), 4931 getValue(I.getArgOperand(0)))); 4932 return 0; 4933 case Intrinsic::powi: 4934 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4935 getValue(I.getArgOperand(1)), DAG)); 4936 return 0; 4937 case Intrinsic::sin: 4938 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4939 getValue(I.getArgOperand(0)).getValueType(), 4940 getValue(I.getArgOperand(0)))); 4941 return 0; 4942 case Intrinsic::cos: 4943 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4944 getValue(I.getArgOperand(0)).getValueType(), 4945 getValue(I.getArgOperand(0)))); 4946 return 0; 4947 case Intrinsic::log: 4948 visitLog(I); 4949 return 0; 4950 case Intrinsic::log2: 4951 visitLog2(I); 4952 return 0; 4953 case Intrinsic::log10: 4954 visitLog10(I); 4955 return 0; 4956 case Intrinsic::exp: 4957 visitExp(I); 4958 return 0; 4959 case Intrinsic::exp2: 4960 visitExp2(I); 4961 return 0; 4962 case Intrinsic::pow: 4963 visitPow(I); 4964 return 0; 4965 case Intrinsic::fabs: 4966 setValue(&I, DAG.getNode(ISD::FABS, dl, 4967 getValue(I.getArgOperand(0)).getValueType(), 4968 getValue(I.getArgOperand(0)))); 4969 return 0; 4970 case Intrinsic::floor: 4971 setValue(&I, DAG.getNode(ISD::FFLOOR, dl, 4972 getValue(I.getArgOperand(0)).getValueType(), 4973 getValue(I.getArgOperand(0)))); 4974 return 0; 4975 case Intrinsic::fma: 4976 setValue(&I, DAG.getNode(ISD::FMA, dl, 4977 getValue(I.getArgOperand(0)).getValueType(), 4978 getValue(I.getArgOperand(0)), 4979 getValue(I.getArgOperand(1)), 4980 getValue(I.getArgOperand(2)))); 4981 return 0; 4982 case Intrinsic::fmuladd: { 4983 EVT VT = TLI.getValueType(I.getType()); 4984 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && 4985 TLI.isOperationLegal(ISD::FMA, VT) && 4986 TLI.isFMAFasterThanMulAndAdd(VT)){ 4987 setValue(&I, DAG.getNode(ISD::FMA, dl, 4988 getValue(I.getArgOperand(0)).getValueType(), 4989 getValue(I.getArgOperand(0)), 4990 getValue(I.getArgOperand(1)), 4991 getValue(I.getArgOperand(2)))); 4992 } else { 4993 SDValue Mul = DAG.getNode(ISD::FMUL, dl, 4994 getValue(I.getArgOperand(0)).getValueType(), 4995 getValue(I.getArgOperand(0)), 4996 getValue(I.getArgOperand(1))); 4997 SDValue Add = DAG.getNode(ISD::FADD, dl, 4998 getValue(I.getArgOperand(0)).getValueType(), 4999 Mul, 5000 getValue(I.getArgOperand(2))); 5001 setValue(&I, Add); 5002 } 5003 return 0; 5004 } 5005 case Intrinsic::convert_to_fp16: 5006 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 5007 MVT::i16, getValue(I.getArgOperand(0)))); 5008 return 0; 5009 case Intrinsic::convert_from_fp16: 5010 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 5011 MVT::f32, getValue(I.getArgOperand(0)))); 5012 return 0; 5013 case Intrinsic::pcmarker: { 5014 SDValue Tmp = getValue(I.getArgOperand(0)); 5015 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 5016 return 0; 5017 } 5018 case Intrinsic::readcyclecounter: { 5019 SDValue Op = getRoot(); 5020 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 5021 DAG.getVTList(MVT::i64, MVT::Other), 5022 &Op, 1); 5023 setValue(&I, Res); 5024 DAG.setRoot(Res.getValue(1)); 5025 return 0; 5026 } 5027 case Intrinsic::bswap: 5028 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 5029 getValue(I.getArgOperand(0)).getValueType(), 5030 getValue(I.getArgOperand(0)))); 5031 return 0; 5032 case Intrinsic::cttz: { 5033 SDValue Arg = getValue(I.getArgOperand(0)); 5034 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 5035 EVT Ty = Arg.getValueType(); 5036 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 5037 dl, Ty, Arg)); 5038 return 0; 5039 } 5040 case Intrinsic::ctlz: { 5041 SDValue Arg = getValue(I.getArgOperand(0)); 5042 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 5043 EVT Ty = Arg.getValueType(); 5044 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 5045 dl, Ty, Arg)); 5046 return 0; 5047 } 5048 case Intrinsic::ctpop: { 5049 SDValue Arg = getValue(I.getArgOperand(0)); 5050 EVT Ty = Arg.getValueType(); 5051 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 5052 return 0; 5053 } 5054 case Intrinsic::stacksave: { 5055 SDValue Op = getRoot(); 5056 Res = DAG.getNode(ISD::STACKSAVE, dl, 5057 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 5058 setValue(&I, Res); 5059 DAG.setRoot(Res.getValue(1)); 5060 return 0; 5061 } 5062 case Intrinsic::stackrestore: { 5063 Res = getValue(I.getArgOperand(0)); 5064 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 5065 return 0; 5066 } 5067 case Intrinsic::stackprotector: { 5068 // Emit code into the DAG to store the stack guard onto the stack. 5069 MachineFunction &MF = DAG.getMachineFunction(); 5070 MachineFrameInfo *MFI = MF.getFrameInfo(); 5071 EVT PtrTy = TLI.getPointerTy(); 5072 5073 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 5074 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 5075 5076 int FI = FuncInfo.StaticAllocaMap[Slot]; 5077 MFI->setStackProtectorIndex(FI); 5078 5079 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5080 5081 // Store the stack protector onto the stack. 5082 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 5083 MachinePointerInfo::getFixedStack(FI), 5084 true, false, 0); 5085 setValue(&I, Res); 5086 DAG.setRoot(Res); 5087 return 0; 5088 } 5089 case Intrinsic::objectsize: { 5090 // If we don't know by now, we're never going to know. 5091 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5092 5093 assert(CI && "Non-constant type in __builtin_object_size?"); 5094 5095 SDValue Arg = getValue(I.getCalledValue()); 5096 EVT Ty = Arg.getValueType(); 5097 5098 if (CI->isZero()) 5099 Res = DAG.getConstant(-1ULL, Ty); 5100 else 5101 Res = DAG.getConstant(0, Ty); 5102 5103 setValue(&I, Res); 5104 return 0; 5105 } 5106 case Intrinsic::var_annotation: 5107 // Discard annotate attributes 5108 return 0; 5109 5110 case Intrinsic::init_trampoline: { 5111 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5112 5113 SDValue Ops[6]; 5114 Ops[0] = getRoot(); 5115 Ops[1] = getValue(I.getArgOperand(0)); 5116 Ops[2] = getValue(I.getArgOperand(1)); 5117 Ops[3] = getValue(I.getArgOperand(2)); 5118 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5119 Ops[5] = DAG.getSrcValue(F); 5120 5121 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5122 5123 DAG.setRoot(Res); 5124 return 0; 5125 } 5126 case Intrinsic::adjust_trampoline: { 5127 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5128 TLI.getPointerTy(), 5129 getValue(I.getArgOperand(0)))); 5130 return 0; 5131 } 5132 case Intrinsic::gcroot: 5133 if (GFI) { 5134 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); 5135 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5136 5137 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5138 GFI->addStackRoot(FI->getIndex(), TypeMap); 5139 } 5140 return 0; 5141 case Intrinsic::gcread: 5142 case Intrinsic::gcwrite: 5143 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5144 case Intrinsic::flt_rounds: 5145 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5146 return 0; 5147 5148 case Intrinsic::expect: { 5149 // Just replace __builtin_expect(exp, c) with EXP. 5150 setValue(&I, getValue(I.getArgOperand(0))); 5151 return 0; 5152 } 5153 5154 case Intrinsic::trap: { 5155 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5156 if (TrapFuncName.empty()) { 5157 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 5158 return 0; 5159 } 5160 TargetLowering::ArgListTy Args; 5161 TargetLowering:: 5162 CallLoweringInfo CLI(getRoot(), I.getType(), 5163 false, false, false, false, 0, CallingConv::C, 5164 /*isTailCall=*/false, 5165 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 5166 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5167 Args, DAG, getCurDebugLoc()); 5168 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI); 5169 DAG.setRoot(Result.second); 5170 return 0; 5171 } 5172 case Intrinsic::debugtrap: { 5173 DAG.setRoot(DAG.getNode(ISD::DEBUGTRAP, dl,MVT::Other, getRoot())); 5174 return 0; 5175 } 5176 case Intrinsic::uadd_with_overflow: 5177 case Intrinsic::sadd_with_overflow: 5178 case Intrinsic::usub_with_overflow: 5179 case Intrinsic::ssub_with_overflow: 5180 case Intrinsic::umul_with_overflow: 5181 case Intrinsic::smul_with_overflow: { 5182 ISD::NodeType Op; 5183 switch (Intrinsic) { 5184 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 5185 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; 5186 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; 5187 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; 5188 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; 5189 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; 5190 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; 5191 } 5192 SDValue Op1 = getValue(I.getArgOperand(0)); 5193 SDValue Op2 = getValue(I.getArgOperand(1)); 5194 5195 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 5196 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 5197 return 0; 5198 } 5199 case Intrinsic::prefetch: { 5200 SDValue Ops[5]; 5201 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5202 Ops[0] = getRoot(); 5203 Ops[1] = getValue(I.getArgOperand(0)); 5204 Ops[2] = getValue(I.getArgOperand(1)); 5205 Ops[3] = getValue(I.getArgOperand(2)); 5206 Ops[4] = getValue(I.getArgOperand(3)); 5207 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5208 DAG.getVTList(MVT::Other), 5209 &Ops[0], 5, 5210 EVT::getIntegerVT(*Context, 8), 5211 MachinePointerInfo(I.getArgOperand(0)), 5212 0, /* align */ 5213 false, /* volatile */ 5214 rw==0, /* read */ 5215 rw==1)); /* write */ 5216 return 0; 5217 } 5218 5219 case Intrinsic::invariant_start: 5220 case Intrinsic::lifetime_start: 5221 // Discard region information. 5222 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5223 return 0; 5224 case Intrinsic::invariant_end: 5225 case Intrinsic::lifetime_end: 5226 // Discard region information. 5227 return 0; 5228 case Intrinsic::donothing: 5229 // ignore 5230 return 0; 5231 } 5232} 5233 5234void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5235 bool isTailCall, 5236 MachineBasicBlock *LandingPad) { 5237 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5238 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5239 Type *RetTy = FTy->getReturnType(); 5240 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5241 MCSymbol *BeginLabel = 0; 5242 5243 TargetLowering::ArgListTy Args; 5244 TargetLowering::ArgListEntry Entry; 5245 Args.reserve(CS.arg_size()); 5246 5247 // Check whether the function can return without sret-demotion. 5248 SmallVector<ISD::OutputArg, 4> Outs; 5249 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5250 Outs, TLI); 5251 5252 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5253 DAG.getMachineFunction(), 5254 FTy->isVarArg(), Outs, 5255 FTy->getContext()); 5256 5257 SDValue DemoteStackSlot; 5258 int DemoteStackIdx = -100; 5259 5260 if (!CanLowerReturn) { 5261 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5262 FTy->getReturnType()); 5263 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5264 FTy->getReturnType()); 5265 MachineFunction &MF = DAG.getMachineFunction(); 5266 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5267 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5268 5269 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5270 Entry.Node = DemoteStackSlot; 5271 Entry.Ty = StackSlotPtrType; 5272 Entry.isSExt = false; 5273 Entry.isZExt = false; 5274 Entry.isInReg = false; 5275 Entry.isSRet = true; 5276 Entry.isNest = false; 5277 Entry.isByVal = false; 5278 Entry.Alignment = Align; 5279 Args.push_back(Entry); 5280 RetTy = Type::getVoidTy(FTy->getContext()); 5281 } 5282 5283 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5284 i != e; ++i) { 5285 const Value *V = *i; 5286 5287 // Skip empty types 5288 if (V->getType()->isEmptyTy()) 5289 continue; 5290 5291 SDValue ArgNode = getValue(V); 5292 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5293 5294 unsigned attrInd = i - CS.arg_begin() + 1; 5295 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5296 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5297 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5298 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5299 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5300 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5301 Entry.Alignment = CS.getParamAlignment(attrInd); 5302 Args.push_back(Entry); 5303 } 5304 5305 if (LandingPad) { 5306 // Insert a label before the invoke call to mark the try range. This can be 5307 // used to detect deletion of the invoke via the MachineModuleInfo. 5308 BeginLabel = MMI.getContext().CreateTempSymbol(); 5309 5310 // For SjLj, keep track of which landing pads go with which invokes 5311 // so as to maintain the ordering of pads in the LSDA. 5312 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5313 if (CallSiteIndex) { 5314 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5315 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5316 5317 // Now that the call site is handled, stop tracking it. 5318 MMI.setCurrentCallSite(0); 5319 } 5320 5321 // Both PendingLoads and PendingExports must be flushed here; 5322 // this call might not return. 5323 (void)getRoot(); 5324 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5325 } 5326 5327 // Check if target-independent constraints permit a tail call here. 5328 // Target-dependent constraints are checked within TLI.LowerCallTo. 5329 if (isTailCall && 5330 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5331 isTailCall = false; 5332 5333 // If there's a possibility that fast-isel has already selected some amount 5334 // of the current basic block, don't emit a tail call. 5335 if (isTailCall && TM.Options.EnableFastISel) 5336 isTailCall = false; 5337 5338 TargetLowering:: 5339 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG, 5340 getCurDebugLoc(), CS); 5341 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI); 5342 assert((isTailCall || Result.second.getNode()) && 5343 "Non-null chain expected with non-tail call!"); 5344 assert((Result.second.getNode() || !Result.first.getNode()) && 5345 "Null value expected with tail call!"); 5346 if (Result.first.getNode()) { 5347 setValue(CS.getInstruction(), Result.first); 5348 } else if (!CanLowerReturn && Result.second.getNode()) { 5349 // The instruction result is the result of loading from the 5350 // hidden sret parameter. 5351 SmallVector<EVT, 1> PVTs; 5352 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5353 5354 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5355 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5356 EVT PtrVT = PVTs[0]; 5357 5358 SmallVector<EVT, 4> RetTys; 5359 SmallVector<uint64_t, 4> Offsets; 5360 RetTy = FTy->getReturnType(); 5361 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets); 5362 5363 unsigned NumValues = RetTys.size(); 5364 SmallVector<SDValue, 4> Values(NumValues); 5365 SmallVector<SDValue, 4> Chains(NumValues); 5366 5367 for (unsigned i = 0; i < NumValues; ++i) { 5368 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5369 DemoteStackSlot, 5370 DAG.getConstant(Offsets[i], PtrVT)); 5371 SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add, 5372 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5373 false, false, false, 1); 5374 Values[i] = L; 5375 Chains[i] = L.getValue(1); 5376 } 5377 5378 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5379 MVT::Other, &Chains[0], NumValues); 5380 PendingLoads.push_back(Chain); 5381 5382 setValue(CS.getInstruction(), 5383 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5384 DAG.getVTList(&RetTys[0], RetTys.size()), 5385 &Values[0], Values.size())); 5386 } 5387 5388 // Assign order to nodes here. If the call does not produce a result, it won't 5389 // be mapped to a SDNode and visit() will not assign it an order number. 5390 if (!Result.second.getNode()) { 5391 // As a special case, a null chain means that a tail call has been emitted and 5392 // the DAG root is already updated. 5393 HasTailCall = true; 5394 ++SDNodeOrder; 5395 AssignOrderingToNode(DAG.getRoot().getNode()); 5396 } else { 5397 DAG.setRoot(Result.second); 5398 ++SDNodeOrder; 5399 AssignOrderingToNode(Result.second.getNode()); 5400 } 5401 5402 if (LandingPad) { 5403 // Insert a label at the end of the invoke call to mark the try range. This 5404 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5405 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5406 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5407 5408 // Inform MachineModuleInfo of range. 5409 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5410 } 5411} 5412 5413/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5414/// value is equal or not-equal to zero. 5415static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5416 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5417 UI != E; ++UI) { 5418 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5419 if (IC->isEquality()) 5420 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5421 if (C->isNullValue()) 5422 continue; 5423 // Unknown instruction. 5424 return false; 5425 } 5426 return true; 5427} 5428 5429static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5430 Type *LoadTy, 5431 SelectionDAGBuilder &Builder) { 5432 5433 // Check to see if this load can be trivially constant folded, e.g. if the 5434 // input is from a string literal. 5435 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5436 // Cast pointer to the type we really want to load. 5437 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5438 PointerType::getUnqual(LoadTy)); 5439 5440 if (const Constant *LoadCst = 5441 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5442 Builder.TD)) 5443 return Builder.getValue(LoadCst); 5444 } 5445 5446 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5447 // still constant memory, the input chain can be the entry node. 5448 SDValue Root; 5449 bool ConstantMemory = false; 5450 5451 // Do not serialize (non-volatile) loads of constant memory with anything. 5452 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5453 Root = Builder.DAG.getEntryNode(); 5454 ConstantMemory = true; 5455 } else { 5456 // Do not serialize non-volatile loads against each other. 5457 Root = Builder.DAG.getRoot(); 5458 } 5459 5460 SDValue Ptr = Builder.getValue(PtrVal); 5461 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5462 Ptr, MachinePointerInfo(PtrVal), 5463 false /*volatile*/, 5464 false /*nontemporal*/, 5465 false /*isinvariant*/, 1 /* align=1 */); 5466 5467 if (!ConstantMemory) 5468 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5469 return LoadVal; 5470} 5471 5472 5473/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5474/// If so, return true and lower it, otherwise return false and it will be 5475/// lowered like a normal call. 5476bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5477 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5478 if (I.getNumArgOperands() != 3) 5479 return false; 5480 5481 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5482 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5483 !I.getArgOperand(2)->getType()->isIntegerTy() || 5484 !I.getType()->isIntegerTy()) 5485 return false; 5486 5487 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5488 5489 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5490 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5491 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5492 bool ActuallyDoIt = true; 5493 MVT LoadVT; 5494 Type *LoadTy; 5495 switch (Size->getZExtValue()) { 5496 default: 5497 LoadVT = MVT::Other; 5498 LoadTy = 0; 5499 ActuallyDoIt = false; 5500 break; 5501 case 2: 5502 LoadVT = MVT::i16; 5503 LoadTy = Type::getInt16Ty(Size->getContext()); 5504 break; 5505 case 4: 5506 LoadVT = MVT::i32; 5507 LoadTy = Type::getInt32Ty(Size->getContext()); 5508 break; 5509 case 8: 5510 LoadVT = MVT::i64; 5511 LoadTy = Type::getInt64Ty(Size->getContext()); 5512 break; 5513 /* 5514 case 16: 5515 LoadVT = MVT::v4i32; 5516 LoadTy = Type::getInt32Ty(Size->getContext()); 5517 LoadTy = VectorType::get(LoadTy, 4); 5518 break; 5519 */ 5520 } 5521 5522 // This turns into unaligned loads. We only do this if the target natively 5523 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5524 // we'll only produce a small number of byte loads. 5525 5526 // Require that we can find a legal MVT, and only do this if the target 5527 // supports unaligned loads of that type. Expanding into byte loads would 5528 // bloat the code. 5529 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5530 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5531 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5532 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5533 ActuallyDoIt = false; 5534 } 5535 5536 if (ActuallyDoIt) { 5537 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5538 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5539 5540 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5541 ISD::SETNE); 5542 EVT CallVT = TLI.getValueType(I.getType(), true); 5543 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5544 return true; 5545 } 5546 } 5547 5548 5549 return false; 5550} 5551 5552/// visitUnaryFloatCall - If a call instruction is a unary floating-point 5553/// operation (as expected), translate it to an SDNode with the specified opcode 5554/// and return true. 5555bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I, 5556 unsigned Opcode) { 5557 // Sanity check that it really is a unary floating-point call. 5558 if (I.getNumArgOperands() != 1 || 5559 !I.getArgOperand(0)->getType()->isFloatingPointTy() || 5560 I.getType() != I.getArgOperand(0)->getType() || 5561 !I.onlyReadsMemory()) 5562 return false; 5563 5564 SDValue Tmp = getValue(I.getArgOperand(0)); 5565 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), Tmp.getValueType(), Tmp)); 5566 return true; 5567} 5568 5569void SelectionDAGBuilder::visitCall(const CallInst &I) { 5570 // Handle inline assembly differently. 5571 if (isa<InlineAsm>(I.getCalledValue())) { 5572 visitInlineAsm(&I); 5573 return; 5574 } 5575 5576 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5577 ComputeUsesVAFloatArgument(I, &MMI); 5578 5579 const char *RenameFn = 0; 5580 if (Function *F = I.getCalledFunction()) { 5581 if (F->isDeclaration()) { 5582 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5583 if (unsigned IID = II->getIntrinsicID(F)) { 5584 RenameFn = visitIntrinsicCall(I, IID); 5585 if (!RenameFn) 5586 return; 5587 } 5588 } 5589 if (unsigned IID = F->getIntrinsicID()) { 5590 RenameFn = visitIntrinsicCall(I, IID); 5591 if (!RenameFn) 5592 return; 5593 } 5594 } 5595 5596 // Check for well-known libc/libm calls. If the function is internal, it 5597 // can't be a library call. 5598 LibFunc::Func Func; 5599 if (!F->hasLocalLinkage() && F->hasName() && 5600 LibInfo->getLibFunc(F->getName(), Func) && 5601 LibInfo->hasOptimizedCodeGen(Func)) { 5602 switch (Func) { 5603 default: break; 5604 case LibFunc::copysign: 5605 case LibFunc::copysignf: 5606 case LibFunc::copysignl: 5607 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5608 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5609 I.getType() == I.getArgOperand(0)->getType() && 5610 I.getType() == I.getArgOperand(1)->getType() && 5611 I.onlyReadsMemory()) { 5612 SDValue LHS = getValue(I.getArgOperand(0)); 5613 SDValue RHS = getValue(I.getArgOperand(1)); 5614 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5615 LHS.getValueType(), LHS, RHS)); 5616 return; 5617 } 5618 break; 5619 case LibFunc::fabs: 5620 case LibFunc::fabsf: 5621 case LibFunc::fabsl: 5622 if (visitUnaryFloatCall(I, ISD::FABS)) 5623 return; 5624 break; 5625 case LibFunc::sin: 5626 case LibFunc::sinf: 5627 case LibFunc::sinl: 5628 if (visitUnaryFloatCall(I, ISD::FSIN)) 5629 return; 5630 break; 5631 case LibFunc::cos: 5632 case LibFunc::cosf: 5633 case LibFunc::cosl: 5634 if (visitUnaryFloatCall(I, ISD::FCOS)) 5635 return; 5636 break; 5637 case LibFunc::sqrt: 5638 case LibFunc::sqrtf: 5639 case LibFunc::sqrtl: 5640 if (visitUnaryFloatCall(I, ISD::FSQRT)) 5641 return; 5642 break; 5643 case LibFunc::floor: 5644 case LibFunc::floorf: 5645 case LibFunc::floorl: 5646 if (visitUnaryFloatCall(I, ISD::FFLOOR)) 5647 return; 5648 break; 5649 case LibFunc::nearbyint: 5650 case LibFunc::nearbyintf: 5651 case LibFunc::nearbyintl: 5652 if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) 5653 return; 5654 break; 5655 case LibFunc::ceil: 5656 case LibFunc::ceilf: 5657 case LibFunc::ceill: 5658 if (visitUnaryFloatCall(I, ISD::FCEIL)) 5659 return; 5660 break; 5661 case LibFunc::rint: 5662 case LibFunc::rintf: 5663 case LibFunc::rintl: 5664 if (visitUnaryFloatCall(I, ISD::FRINT)) 5665 return; 5666 break; 5667 case LibFunc::trunc: 5668 case LibFunc::truncf: 5669 case LibFunc::truncl: 5670 if (visitUnaryFloatCall(I, ISD::FTRUNC)) 5671 return; 5672 break; 5673 case LibFunc::log2: 5674 case LibFunc::log2f: 5675 case LibFunc::log2l: 5676 if (visitUnaryFloatCall(I, ISD::FLOG2)) 5677 return; 5678 break; 5679 case LibFunc::exp2: 5680 case LibFunc::exp2f: 5681 case LibFunc::exp2l: 5682 if (visitUnaryFloatCall(I, ISD::FEXP2)) 5683 return; 5684 break; 5685 case LibFunc::memcmp: 5686 if (visitMemCmpCall(I)) 5687 return; 5688 break; 5689 } 5690 } 5691 } 5692 5693 SDValue Callee; 5694 if (!RenameFn) 5695 Callee = getValue(I.getCalledValue()); 5696 else 5697 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5698 5699 // Check if we can potentially perform a tail call. More detailed checking is 5700 // be done within LowerCallTo, after more information about the call is known. 5701 LowerCallTo(&I, Callee, I.isTailCall()); 5702} 5703 5704namespace { 5705 5706/// AsmOperandInfo - This contains information for each constraint that we are 5707/// lowering. 5708class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5709public: 5710 /// CallOperand - If this is the result output operand or a clobber 5711 /// this is null, otherwise it is the incoming operand to the CallInst. 5712 /// This gets modified as the asm is processed. 5713 SDValue CallOperand; 5714 5715 /// AssignedRegs - If this is a register or register class operand, this 5716 /// contains the set of register corresponding to the operand. 5717 RegsForValue AssignedRegs; 5718 5719 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5720 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5721 } 5722 5723 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5724 /// corresponds to. If there is no Value* for this operand, it returns 5725 /// MVT::Other. 5726 EVT getCallOperandValEVT(LLVMContext &Context, 5727 const TargetLowering &TLI, 5728 const TargetData *TD) const { 5729 if (CallOperandVal == 0) return MVT::Other; 5730 5731 if (isa<BasicBlock>(CallOperandVal)) 5732 return TLI.getPointerTy(); 5733 5734 llvm::Type *OpTy = CallOperandVal->getType(); 5735 5736 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5737 // If this is an indirect operand, the operand is a pointer to the 5738 // accessed type. 5739 if (isIndirect) { 5740 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5741 if (!PtrTy) 5742 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5743 OpTy = PtrTy->getElementType(); 5744 } 5745 5746 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5747 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5748 if (STy->getNumElements() == 1) 5749 OpTy = STy->getElementType(0); 5750 5751 // If OpTy is not a single value, it may be a struct/union that we 5752 // can tile with integers. 5753 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5754 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5755 switch (BitSize) { 5756 default: break; 5757 case 1: 5758 case 8: 5759 case 16: 5760 case 32: 5761 case 64: 5762 case 128: 5763 OpTy = IntegerType::get(Context, BitSize); 5764 break; 5765 } 5766 } 5767 5768 return TLI.getValueType(OpTy, true); 5769 } 5770}; 5771 5772typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5773 5774} // end anonymous namespace 5775 5776/// GetRegistersForValue - Assign registers (virtual or physical) for the 5777/// specified operand. We prefer to assign virtual registers, to allow the 5778/// register allocator to handle the assignment process. However, if the asm 5779/// uses features that we can't model on machineinstrs, we have SDISel do the 5780/// allocation. This produces generally horrible, but correct, code. 5781/// 5782/// OpInfo describes the operand. 5783/// 5784static void GetRegistersForValue(SelectionDAG &DAG, 5785 const TargetLowering &TLI, 5786 DebugLoc DL, 5787 SDISelAsmOperandInfo &OpInfo) { 5788 LLVMContext &Context = *DAG.getContext(); 5789 5790 MachineFunction &MF = DAG.getMachineFunction(); 5791 SmallVector<unsigned, 4> Regs; 5792 5793 // If this is a constraint for a single physreg, or a constraint for a 5794 // register class, find it. 5795 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5796 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5797 OpInfo.ConstraintVT); 5798 5799 unsigned NumRegs = 1; 5800 if (OpInfo.ConstraintVT != MVT::Other) { 5801 // If this is a FP input in an integer register (or visa versa) insert a bit 5802 // cast of the input value. More generally, handle any case where the input 5803 // value disagrees with the register class we plan to stick this in. 5804 if (OpInfo.Type == InlineAsm::isInput && 5805 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5806 // Try to convert to the first EVT that the reg class contains. If the 5807 // types are identical size, use a bitcast to convert (e.g. two differing 5808 // vector types). 5809 EVT RegVT = *PhysReg.second->vt_begin(); 5810 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5811 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5812 RegVT, OpInfo.CallOperand); 5813 OpInfo.ConstraintVT = RegVT; 5814 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5815 // If the input is a FP value and we want it in FP registers, do a 5816 // bitcast to the corresponding integer type. This turns an f64 value 5817 // into i64, which can be passed with two i32 values on a 32-bit 5818 // machine. 5819 RegVT = EVT::getIntegerVT(Context, 5820 OpInfo.ConstraintVT.getSizeInBits()); 5821 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5822 RegVT, OpInfo.CallOperand); 5823 OpInfo.ConstraintVT = RegVT; 5824 } 5825 } 5826 5827 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5828 } 5829 5830 EVT RegVT; 5831 EVT ValueVT = OpInfo.ConstraintVT; 5832 5833 // If this is a constraint for a specific physical register, like {r17}, 5834 // assign it now. 5835 if (unsigned AssignedReg = PhysReg.first) { 5836 const TargetRegisterClass *RC = PhysReg.second; 5837 if (OpInfo.ConstraintVT == MVT::Other) 5838 ValueVT = *RC->vt_begin(); 5839 5840 // Get the actual register value type. This is important, because the user 5841 // may have asked for (e.g.) the AX register in i32 type. We need to 5842 // remember that AX is actually i16 to get the right extension. 5843 RegVT = *RC->vt_begin(); 5844 5845 // This is a explicit reference to a physical register. 5846 Regs.push_back(AssignedReg); 5847 5848 // If this is an expanded reference, add the rest of the regs to Regs. 5849 if (NumRegs != 1) { 5850 TargetRegisterClass::iterator I = RC->begin(); 5851 for (; *I != AssignedReg; ++I) 5852 assert(I != RC->end() && "Didn't find reg!"); 5853 5854 // Already added the first reg. 5855 --NumRegs; ++I; 5856 for (; NumRegs; --NumRegs, ++I) { 5857 assert(I != RC->end() && "Ran out of registers to allocate!"); 5858 Regs.push_back(*I); 5859 } 5860 } 5861 5862 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5863 return; 5864 } 5865 5866 // Otherwise, if this was a reference to an LLVM register class, create vregs 5867 // for this reference. 5868 if (const TargetRegisterClass *RC = PhysReg.second) { 5869 RegVT = *RC->vt_begin(); 5870 if (OpInfo.ConstraintVT == MVT::Other) 5871 ValueVT = RegVT; 5872 5873 // Create the appropriate number of virtual registers. 5874 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5875 for (; NumRegs; --NumRegs) 5876 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5877 5878 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5879 return; 5880 } 5881 5882 // Otherwise, we couldn't allocate enough registers for this. 5883} 5884 5885/// visitInlineAsm - Handle a call to an InlineAsm object. 5886/// 5887void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5888 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5889 5890 /// ConstraintOperands - Information about all of the constraints. 5891 SDISelAsmOperandInfoVector ConstraintOperands; 5892 5893 TargetLowering::AsmOperandInfoVector 5894 TargetConstraints = TLI.ParseConstraints(CS); 5895 5896 bool hasMemory = false; 5897 5898 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5899 unsigned ResNo = 0; // ResNo - The result number of the next output. 5900 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5901 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5902 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5903 5904 EVT OpVT = MVT::Other; 5905 5906 // Compute the value type for each operand. 5907 switch (OpInfo.Type) { 5908 case InlineAsm::isOutput: 5909 // Indirect outputs just consume an argument. 5910 if (OpInfo.isIndirect) { 5911 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5912 break; 5913 } 5914 5915 // The return value of the call is this value. As such, there is no 5916 // corresponding argument. 5917 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5918 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5919 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5920 } else { 5921 assert(ResNo == 0 && "Asm only has one result!"); 5922 OpVT = TLI.getValueType(CS.getType()); 5923 } 5924 ++ResNo; 5925 break; 5926 case InlineAsm::isInput: 5927 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5928 break; 5929 case InlineAsm::isClobber: 5930 // Nothing to do. 5931 break; 5932 } 5933 5934 // If this is an input or an indirect output, process the call argument. 5935 // BasicBlocks are labels, currently appearing only in asm's. 5936 if (OpInfo.CallOperandVal) { 5937 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5938 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5939 } else { 5940 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5941 } 5942 5943 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5944 } 5945 5946 OpInfo.ConstraintVT = OpVT; 5947 5948 // Indirect operand accesses access memory. 5949 if (OpInfo.isIndirect) 5950 hasMemory = true; 5951 else { 5952 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5953 TargetLowering::ConstraintType 5954 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5955 if (CType == TargetLowering::C_Memory) { 5956 hasMemory = true; 5957 break; 5958 } 5959 } 5960 } 5961 } 5962 5963 SDValue Chain, Flag; 5964 5965 // We won't need to flush pending loads if this asm doesn't touch 5966 // memory and is nonvolatile. 5967 if (hasMemory || IA->hasSideEffects()) 5968 Chain = getRoot(); 5969 else 5970 Chain = DAG.getRoot(); 5971 5972 // Second pass over the constraints: compute which constraint option to use 5973 // and assign registers to constraints that want a specific physreg. 5974 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5975 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5976 5977 // If this is an output operand with a matching input operand, look up the 5978 // matching input. If their types mismatch, e.g. one is an integer, the 5979 // other is floating point, or their sizes are different, flag it as an 5980 // error. 5981 if (OpInfo.hasMatchingInput()) { 5982 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5983 5984 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5985 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5986 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5987 OpInfo.ConstraintVT); 5988 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5989 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 5990 Input.ConstraintVT); 5991 if ((OpInfo.ConstraintVT.isInteger() != 5992 Input.ConstraintVT.isInteger()) || 5993 (MatchRC.second != InputRC.second)) { 5994 report_fatal_error("Unsupported asm: input constraint" 5995 " with a matching output constraint of" 5996 " incompatible type!"); 5997 } 5998 Input.ConstraintVT = OpInfo.ConstraintVT; 5999 } 6000 } 6001 6002 // Compute the constraint code and ConstraintType to use. 6003 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 6004 6005 // If this is a memory input, and if the operand is not indirect, do what we 6006 // need to to provide an address for the memory input. 6007 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 6008 !OpInfo.isIndirect) { 6009 assert((OpInfo.isMultipleAlternative || 6010 (OpInfo.Type == InlineAsm::isInput)) && 6011 "Can only indirectify direct input operands!"); 6012 6013 // Memory operands really want the address of the value. If we don't have 6014 // an indirect input, put it in the constpool if we can, otherwise spill 6015 // it to a stack slot. 6016 // TODO: This isn't quite right. We need to handle these according to 6017 // the addressing mode that the constraint wants. Also, this may take 6018 // an additional register for the computation and we don't want that 6019 // either. 6020 6021 // If the operand is a float, integer, or vector constant, spill to a 6022 // constant pool entry to get its address. 6023 const Value *OpVal = OpInfo.CallOperandVal; 6024 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 6025 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { 6026 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 6027 TLI.getPointerTy()); 6028 } else { 6029 // Otherwise, create a stack slot and emit a store to it before the 6030 // asm. 6031 Type *Ty = OpVal->getType(); 6032 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 6033 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 6034 MachineFunction &MF = DAG.getMachineFunction(); 6035 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 6036 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 6037 Chain = DAG.getStore(Chain, getCurDebugLoc(), 6038 OpInfo.CallOperand, StackSlot, 6039 MachinePointerInfo::getFixedStack(SSFI), 6040 false, false, 0); 6041 OpInfo.CallOperand = StackSlot; 6042 } 6043 6044 // There is no longer a Value* corresponding to this operand. 6045 OpInfo.CallOperandVal = 0; 6046 6047 // It is now an indirect operand. 6048 OpInfo.isIndirect = true; 6049 } 6050 6051 // If this constraint is for a specific register, allocate it before 6052 // anything else. 6053 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6054 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6055 } 6056 6057 // Second pass - Loop over all of the operands, assigning virtual or physregs 6058 // to register class operands. 6059 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6060 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6061 6062 // C_Register operands have already been allocated, Other/Memory don't need 6063 // to be. 6064 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6065 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6066 } 6067 6068 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6069 std::vector<SDValue> AsmNodeOperands; 6070 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6071 AsmNodeOperands.push_back( 6072 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6073 TLI.getPointerTy())); 6074 6075 // If we have a !srcloc metadata node associated with it, we want to attach 6076 // this to the ultimately generated inline asm machineinstr. To do this, we 6077 // pass in the third operand as this (potentially null) inline asm MDNode. 6078 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6079 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6080 6081 // Remember the HasSideEffect, AlignStack and AsmDialect bits as operand 3. 6082 unsigned ExtraInfo = 0; 6083 if (IA->hasSideEffects()) 6084 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6085 if (IA->isAlignStack()) 6086 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6087 // Set the asm dialect. 6088 ExtraInfo |= IA->getDialect() << 2; 6089 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6090 TLI.getPointerTy())); 6091 6092 // Loop over all of the inputs, copying the operand values into the 6093 // appropriate registers and processing the output regs. 6094 RegsForValue RetValRegs; 6095 6096 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6097 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6098 6099 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6100 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6101 6102 switch (OpInfo.Type) { 6103 case InlineAsm::isOutput: { 6104 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6105 OpInfo.ConstraintType != TargetLowering::C_Register) { 6106 // Memory output, or 'other' output (e.g. 'X' constraint). 6107 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6108 6109 // Add information to the INLINEASM node to know about this output. 6110 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6111 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6112 TLI.getPointerTy())); 6113 AsmNodeOperands.push_back(OpInfo.CallOperand); 6114 break; 6115 } 6116 6117 // Otherwise, this is a register or register class output. 6118 6119 // Copy the output from the appropriate register. Find a register that 6120 // we can use. 6121 if (OpInfo.AssignedRegs.Regs.empty()) { 6122 LLVMContext &Ctx = *DAG.getContext(); 6123 Ctx.emitError(CS.getInstruction(), 6124 "couldn't allocate output register for constraint '" + 6125 Twine(OpInfo.ConstraintCode) + "'"); 6126 break; 6127 } 6128 6129 // If this is an indirect operand, store through the pointer after the 6130 // asm. 6131 if (OpInfo.isIndirect) { 6132 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6133 OpInfo.CallOperandVal)); 6134 } else { 6135 // This is the result value of the call. 6136 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6137 // Concatenate this output onto the outputs list. 6138 RetValRegs.append(OpInfo.AssignedRegs); 6139 } 6140 6141 // Add information to the INLINEASM node to know that this register is 6142 // set. 6143 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6144 InlineAsm::Kind_RegDefEarlyClobber : 6145 InlineAsm::Kind_RegDef, 6146 false, 6147 0, 6148 DAG, 6149 AsmNodeOperands); 6150 break; 6151 } 6152 case InlineAsm::isInput: { 6153 SDValue InOperandVal = OpInfo.CallOperand; 6154 6155 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6156 // If this is required to match an output register we have already set, 6157 // just use its register. 6158 unsigned OperandNo = OpInfo.getMatchedOperand(); 6159 6160 // Scan until we find the definition we already emitted of this operand. 6161 // When we find it, create a RegsForValue operand. 6162 unsigned CurOp = InlineAsm::Op_FirstOperand; 6163 for (; OperandNo; --OperandNo) { 6164 // Advance to the next operand. 6165 unsigned OpFlag = 6166 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6167 assert((InlineAsm::isRegDefKind(OpFlag) || 6168 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6169 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6170 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6171 } 6172 6173 unsigned OpFlag = 6174 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6175 if (InlineAsm::isRegDefKind(OpFlag) || 6176 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6177 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6178 if (OpInfo.isIndirect) { 6179 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6180 LLVMContext &Ctx = *DAG.getContext(); 6181 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6182 " don't know how to handle tied " 6183 "indirect register inputs"); 6184 } 6185 6186 RegsForValue MatchedRegs; 6187 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6188 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6189 MatchedRegs.RegVTs.push_back(RegVT); 6190 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6191 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6192 i != e; ++i) 6193 MatchedRegs.Regs.push_back 6194 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6195 6196 // Use the produced MatchedRegs object to 6197 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6198 Chain, &Flag); 6199 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6200 true, OpInfo.getMatchedOperand(), 6201 DAG, AsmNodeOperands); 6202 break; 6203 } 6204 6205 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6206 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6207 "Unexpected number of operands"); 6208 // Add information to the INLINEASM node to know about this input. 6209 // See InlineAsm.h isUseOperandTiedToDef. 6210 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6211 OpInfo.getMatchedOperand()); 6212 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6213 TLI.getPointerTy())); 6214 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6215 break; 6216 } 6217 6218 // Treat indirect 'X' constraint as memory. 6219 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6220 OpInfo.isIndirect) 6221 OpInfo.ConstraintType = TargetLowering::C_Memory; 6222 6223 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6224 std::vector<SDValue> Ops; 6225 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6226 Ops, DAG); 6227 if (Ops.empty()) { 6228 LLVMContext &Ctx = *DAG.getContext(); 6229 Ctx.emitError(CS.getInstruction(), 6230 "invalid operand for inline asm constraint '" + 6231 Twine(OpInfo.ConstraintCode) + "'"); 6232 break; 6233 } 6234 6235 // Add information to the INLINEASM node to know about this input. 6236 unsigned ResOpType = 6237 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6238 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6239 TLI.getPointerTy())); 6240 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6241 break; 6242 } 6243 6244 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6245 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6246 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6247 "Memory operands expect pointer values"); 6248 6249 // Add information to the INLINEASM node to know about this input. 6250 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6251 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6252 TLI.getPointerTy())); 6253 AsmNodeOperands.push_back(InOperandVal); 6254 break; 6255 } 6256 6257 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6258 OpInfo.ConstraintType == TargetLowering::C_Register) && 6259 "Unknown constraint type!"); 6260 6261 // TODO: Support this. 6262 if (OpInfo.isIndirect) { 6263 LLVMContext &Ctx = *DAG.getContext(); 6264 Ctx.emitError(CS.getInstruction(), 6265 "Don't know how to handle indirect register inputs yet " 6266 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'"); 6267 break; 6268 } 6269 6270 // Copy the input into the appropriate registers. 6271 if (OpInfo.AssignedRegs.Regs.empty()) { 6272 LLVMContext &Ctx = *DAG.getContext(); 6273 Ctx.emitError(CS.getInstruction(), 6274 "couldn't allocate input reg for constraint '" + 6275 Twine(OpInfo.ConstraintCode) + "'"); 6276 break; 6277 } 6278 6279 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6280 Chain, &Flag); 6281 6282 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6283 DAG, AsmNodeOperands); 6284 break; 6285 } 6286 case InlineAsm::isClobber: { 6287 // Add the clobbered value to the operand list, so that the register 6288 // allocator is aware that the physreg got clobbered. 6289 if (!OpInfo.AssignedRegs.Regs.empty()) 6290 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6291 false, 0, DAG, 6292 AsmNodeOperands); 6293 break; 6294 } 6295 } 6296 } 6297 6298 // Finish up input operands. Set the input chain and add the flag last. 6299 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6300 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6301 6302 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6303 DAG.getVTList(MVT::Other, MVT::Glue), 6304 &AsmNodeOperands[0], AsmNodeOperands.size()); 6305 Flag = Chain.getValue(1); 6306 6307 // If this asm returns a register value, copy the result from that register 6308 // and set it as the value of the call. 6309 if (!RetValRegs.Regs.empty()) { 6310 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6311 Chain, &Flag); 6312 6313 // FIXME: Why don't we do this for inline asms with MRVs? 6314 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6315 EVT ResultType = TLI.getValueType(CS.getType()); 6316 6317 // If any of the results of the inline asm is a vector, it may have the 6318 // wrong width/num elts. This can happen for register classes that can 6319 // contain multiple different value types. The preg or vreg allocated may 6320 // not have the same VT as was expected. Convert it to the right type 6321 // with bit_convert. 6322 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6323 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6324 ResultType, Val); 6325 6326 } else if (ResultType != Val.getValueType() && 6327 ResultType.isInteger() && Val.getValueType().isInteger()) { 6328 // If a result value was tied to an input value, the computed result may 6329 // have a wider width than the expected result. Extract the relevant 6330 // portion. 6331 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6332 } 6333 6334 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6335 } 6336 6337 setValue(CS.getInstruction(), Val); 6338 // Don't need to use this as a chain in this case. 6339 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6340 return; 6341 } 6342 6343 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6344 6345 // Process indirect outputs, first output all of the flagged copies out of 6346 // physregs. 6347 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6348 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6349 const Value *Ptr = IndirectStoresToEmit[i].second; 6350 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6351 Chain, &Flag); 6352 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6353 } 6354 6355 // Emit the non-flagged stores from the physregs. 6356 SmallVector<SDValue, 8> OutChains; 6357 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6358 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6359 StoresToEmit[i].first, 6360 getValue(StoresToEmit[i].second), 6361 MachinePointerInfo(StoresToEmit[i].second), 6362 false, false, 0); 6363 OutChains.push_back(Val); 6364 } 6365 6366 if (!OutChains.empty()) 6367 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6368 &OutChains[0], OutChains.size()); 6369 6370 DAG.setRoot(Chain); 6371} 6372 6373void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6374 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6375 MVT::Other, getRoot(), 6376 getValue(I.getArgOperand(0)), 6377 DAG.getSrcValue(I.getArgOperand(0)))); 6378} 6379 6380void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6381 const TargetData &TD = *TLI.getTargetData(); 6382 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6383 getRoot(), getValue(I.getOperand(0)), 6384 DAG.getSrcValue(I.getOperand(0)), 6385 TD.getABITypeAlignment(I.getType())); 6386 setValue(&I, V); 6387 DAG.setRoot(V.getValue(1)); 6388} 6389 6390void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6391 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6392 MVT::Other, getRoot(), 6393 getValue(I.getArgOperand(0)), 6394 DAG.getSrcValue(I.getArgOperand(0)))); 6395} 6396 6397void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6398 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6399 MVT::Other, getRoot(), 6400 getValue(I.getArgOperand(0)), 6401 getValue(I.getArgOperand(1)), 6402 DAG.getSrcValue(I.getArgOperand(0)), 6403 DAG.getSrcValue(I.getArgOperand(1)))); 6404} 6405 6406/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6407/// implementation, which just calls LowerCall. 6408/// FIXME: When all targets are 6409/// migrated to using LowerCall, this hook should be integrated into SDISel. 6410std::pair<SDValue, SDValue> 6411TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { 6412 // Handle all of the outgoing arguments. 6413 CLI.Outs.clear(); 6414 CLI.OutVals.clear(); 6415 ArgListTy &Args = CLI.Args; 6416 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6417 SmallVector<EVT, 4> ValueVTs; 6418 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6419 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6420 Value != NumValues; ++Value) { 6421 EVT VT = ValueVTs[Value]; 6422 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); 6423 SDValue Op = SDValue(Args[i].Node.getNode(), 6424 Args[i].Node.getResNo() + Value); 6425 ISD::ArgFlagsTy Flags; 6426 unsigned OriginalAlignment = 6427 getTargetData()->getABITypeAlignment(ArgTy); 6428 6429 if (Args[i].isZExt) 6430 Flags.setZExt(); 6431 if (Args[i].isSExt) 6432 Flags.setSExt(); 6433 if (Args[i].isInReg) 6434 Flags.setInReg(); 6435 if (Args[i].isSRet) 6436 Flags.setSRet(); 6437 if (Args[i].isByVal) { 6438 Flags.setByVal(); 6439 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6440 Type *ElementTy = Ty->getElementType(); 6441 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6442 // For ByVal, alignment should come from FE. BE will guess if this 6443 // info is not there but there are cases it cannot get right. 6444 unsigned FrameAlign; 6445 if (Args[i].Alignment) 6446 FrameAlign = Args[i].Alignment; 6447 else 6448 FrameAlign = getByValTypeAlignment(ElementTy); 6449 Flags.setByValAlign(FrameAlign); 6450 } 6451 if (Args[i].isNest) 6452 Flags.setNest(); 6453 Flags.setOrigAlign(OriginalAlignment); 6454 6455 EVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT); 6456 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT); 6457 SmallVector<SDValue, 4> Parts(NumParts); 6458 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6459 6460 if (Args[i].isSExt) 6461 ExtendKind = ISD::SIGN_EXTEND; 6462 else if (Args[i].isZExt) 6463 ExtendKind = ISD::ZERO_EXTEND; 6464 6465 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, 6466 PartVT, ExtendKind); 6467 6468 for (unsigned j = 0; j != NumParts; ++j) { 6469 // if it isn't first piece, alignment must be 1 6470 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6471 i < CLI.NumFixedArgs); 6472 if (NumParts > 1 && j == 0) 6473 MyFlags.Flags.setSplit(); 6474 else if (j != 0) 6475 MyFlags.Flags.setOrigAlign(1); 6476 6477 CLI.Outs.push_back(MyFlags); 6478 CLI.OutVals.push_back(Parts[j]); 6479 } 6480 } 6481 } 6482 6483 // Handle the incoming return values from the call. 6484 CLI.Ins.clear(); 6485 SmallVector<EVT, 4> RetTys; 6486 ComputeValueVTs(*this, CLI.RetTy, RetTys); 6487 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6488 EVT VT = RetTys[I]; 6489 EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6490 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6491 for (unsigned i = 0; i != NumRegs; ++i) { 6492 ISD::InputArg MyFlags; 6493 MyFlags.VT = RegisterVT.getSimpleVT(); 6494 MyFlags.Used = CLI.IsReturnValueUsed; 6495 if (CLI.RetSExt) 6496 MyFlags.Flags.setSExt(); 6497 if (CLI.RetZExt) 6498 MyFlags.Flags.setZExt(); 6499 if (CLI.IsInReg) 6500 MyFlags.Flags.setInReg(); 6501 CLI.Ins.push_back(MyFlags); 6502 } 6503 } 6504 6505 SmallVector<SDValue, 4> InVals; 6506 CLI.Chain = LowerCall(CLI, InVals); 6507 6508 // Verify that the target's LowerCall behaved as expected. 6509 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && 6510 "LowerCall didn't return a valid chain!"); 6511 assert((!CLI.IsTailCall || InVals.empty()) && 6512 "LowerCall emitted a return value for a tail call!"); 6513 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && 6514 "LowerCall didn't emit the correct number of values!"); 6515 6516 // For a tail call, the return value is merely live-out and there aren't 6517 // any nodes in the DAG representing it. Return a special value to 6518 // indicate that a tail call has been emitted and no more Instructions 6519 // should be processed in the current block. 6520 if (CLI.IsTailCall) { 6521 CLI.DAG.setRoot(CLI.Chain); 6522 return std::make_pair(SDValue(), SDValue()); 6523 } 6524 6525 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { 6526 assert(InVals[i].getNode() && 6527 "LowerCall emitted a null value!"); 6528 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && 6529 "LowerCall emitted a value with the wrong type!"); 6530 }); 6531 6532 // Collect the legal value parts into potentially illegal values 6533 // that correspond to the original function's return values. 6534 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6535 if (CLI.RetSExt) 6536 AssertOp = ISD::AssertSext; 6537 else if (CLI.RetZExt) 6538 AssertOp = ISD::AssertZext; 6539 SmallVector<SDValue, 4> ReturnValues; 6540 unsigned CurReg = 0; 6541 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6542 EVT VT = RetTys[I]; 6543 EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6544 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6545 6546 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], 6547 NumRegs, RegisterVT, VT, 6548 AssertOp)); 6549 CurReg += NumRegs; 6550 } 6551 6552 // For a function returning void, there is no return value. We can't create 6553 // such a node, so we just return a null return value in that case. In 6554 // that case, nothing will actually look at the value. 6555 if (ReturnValues.empty()) 6556 return std::make_pair(SDValue(), CLI.Chain); 6557 6558 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, 6559 CLI.DAG.getVTList(&RetTys[0], RetTys.size()), 6560 &ReturnValues[0], ReturnValues.size()); 6561 return std::make_pair(Res, CLI.Chain); 6562} 6563 6564void TargetLowering::LowerOperationWrapper(SDNode *N, 6565 SmallVectorImpl<SDValue> &Results, 6566 SelectionDAG &DAG) const { 6567 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6568 if (Res.getNode()) 6569 Results.push_back(Res); 6570} 6571 6572SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6573 llvm_unreachable("LowerOperation not implemented for this target!"); 6574} 6575 6576void 6577SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6578 SDValue Op = getNonRegisterValue(V); 6579 assert((Op.getOpcode() != ISD::CopyFromReg || 6580 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6581 "Copy from a reg to the same reg!"); 6582 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6583 6584 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6585 SDValue Chain = DAG.getEntryNode(); 6586 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6587 PendingExports.push_back(Chain); 6588} 6589 6590#include "llvm/CodeGen/SelectionDAGISel.h" 6591 6592/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6593/// entry block, return true. This includes arguments used by switches, since 6594/// the switch may expand into multiple basic blocks. 6595static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 6596 // With FastISel active, we may be splitting blocks, so force creation 6597 // of virtual registers for all non-dead arguments. 6598 if (FastISel) 6599 return A->use_empty(); 6600 6601 const BasicBlock *Entry = A->getParent()->begin(); 6602 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6603 UI != E; ++UI) { 6604 const User *U = *UI; 6605 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6606 return false; // Use not in entry block. 6607 } 6608 return true; 6609} 6610 6611void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6612 // If this is the entry block, emit arguments. 6613 const Function &F = *LLVMBB->getParent(); 6614 SelectionDAG &DAG = SDB->DAG; 6615 DebugLoc dl = SDB->getCurDebugLoc(); 6616 const TargetData *TD = TLI.getTargetData(); 6617 SmallVector<ISD::InputArg, 16> Ins; 6618 6619 // Check whether the function can return without sret-demotion. 6620 SmallVector<ISD::OutputArg, 4> Outs; 6621 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6622 Outs, TLI); 6623 6624 if (!FuncInfo->CanLowerReturn) { 6625 // Put in an sret pointer parameter before all the other parameters. 6626 SmallVector<EVT, 1> ValueVTs; 6627 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6628 6629 // NOTE: Assuming that a pointer will never break down to more than one VT 6630 // or one register. 6631 ISD::ArgFlagsTy Flags; 6632 Flags.setSRet(); 6633 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6634 ISD::InputArg RetArg(Flags, RegisterVT, true); 6635 Ins.push_back(RetArg); 6636 } 6637 6638 // Set up the incoming argument description vector. 6639 unsigned Idx = 1; 6640 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6641 I != E; ++I, ++Idx) { 6642 SmallVector<EVT, 4> ValueVTs; 6643 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6644 bool isArgValueUsed = !I->use_empty(); 6645 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6646 Value != NumValues; ++Value) { 6647 EVT VT = ValueVTs[Value]; 6648 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6649 ISD::ArgFlagsTy Flags; 6650 unsigned OriginalAlignment = 6651 TD->getABITypeAlignment(ArgTy); 6652 6653 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6654 Flags.setZExt(); 6655 if (F.paramHasAttr(Idx, Attribute::SExt)) 6656 Flags.setSExt(); 6657 if (F.paramHasAttr(Idx, Attribute::InReg)) 6658 Flags.setInReg(); 6659 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6660 Flags.setSRet(); 6661 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6662 Flags.setByVal(); 6663 PointerType *Ty = cast<PointerType>(I->getType()); 6664 Type *ElementTy = Ty->getElementType(); 6665 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6666 // For ByVal, alignment should be passed from FE. BE will guess if 6667 // this info is not there but there are cases it cannot get right. 6668 unsigned FrameAlign; 6669 if (F.getParamAlignment(Idx)) 6670 FrameAlign = F.getParamAlignment(Idx); 6671 else 6672 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6673 Flags.setByValAlign(FrameAlign); 6674 } 6675 if (F.paramHasAttr(Idx, Attribute::Nest)) 6676 Flags.setNest(); 6677 Flags.setOrigAlign(OriginalAlignment); 6678 6679 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6680 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6681 for (unsigned i = 0; i != NumRegs; ++i) { 6682 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6683 if (NumRegs > 1 && i == 0) 6684 MyFlags.Flags.setSplit(); 6685 // if it isn't first piece, alignment must be 1 6686 else if (i > 0) 6687 MyFlags.Flags.setOrigAlign(1); 6688 Ins.push_back(MyFlags); 6689 } 6690 } 6691 } 6692 6693 // Call the target to set up the argument values. 6694 SmallVector<SDValue, 8> InVals; 6695 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6696 F.isVarArg(), Ins, 6697 dl, DAG, InVals); 6698 6699 // Verify that the target's LowerFormalArguments behaved as expected. 6700 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6701 "LowerFormalArguments didn't return a valid chain!"); 6702 assert(InVals.size() == Ins.size() && 6703 "LowerFormalArguments didn't emit the correct number of values!"); 6704 DEBUG({ 6705 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6706 assert(InVals[i].getNode() && 6707 "LowerFormalArguments emitted a null value!"); 6708 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6709 "LowerFormalArguments emitted a value with the wrong type!"); 6710 } 6711 }); 6712 6713 // Update the DAG with the new chain value resulting from argument lowering. 6714 DAG.setRoot(NewRoot); 6715 6716 // Set up the argument values. 6717 unsigned i = 0; 6718 Idx = 1; 6719 if (!FuncInfo->CanLowerReturn) { 6720 // Create a virtual register for the sret pointer, and put in a copy 6721 // from the sret argument into it. 6722 SmallVector<EVT, 1> ValueVTs; 6723 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6724 EVT VT = ValueVTs[0]; 6725 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6726 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6727 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6728 RegVT, VT, AssertOp); 6729 6730 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6731 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6732 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6733 FuncInfo->DemoteRegister = SRetReg; 6734 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6735 SRetReg, ArgValue); 6736 DAG.setRoot(NewRoot); 6737 6738 // i indexes lowered arguments. Bump it past the hidden sret argument. 6739 // Idx indexes LLVM arguments. Don't touch it. 6740 ++i; 6741 } 6742 6743 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6744 ++I, ++Idx) { 6745 SmallVector<SDValue, 4> ArgValues; 6746 SmallVector<EVT, 4> ValueVTs; 6747 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6748 unsigned NumValues = ValueVTs.size(); 6749 6750 // If this argument is unused then remember its value. It is used to generate 6751 // debugging information. 6752 if (I->use_empty() && NumValues) 6753 SDB->setUnusedArgValue(I, InVals[i]); 6754 6755 for (unsigned Val = 0; Val != NumValues; ++Val) { 6756 EVT VT = ValueVTs[Val]; 6757 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6758 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6759 6760 if (!I->use_empty()) { 6761 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6762 if (F.paramHasAttr(Idx, Attribute::SExt)) 6763 AssertOp = ISD::AssertSext; 6764 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6765 AssertOp = ISD::AssertZext; 6766 6767 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6768 NumParts, PartVT, VT, 6769 AssertOp)); 6770 } 6771 6772 i += NumParts; 6773 } 6774 6775 // We don't need to do anything else for unused arguments. 6776 if (ArgValues.empty()) 6777 continue; 6778 6779 // Note down frame index. 6780 if (FrameIndexSDNode *FI = 6781 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6782 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6783 6784 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6785 SDB->getCurDebugLoc()); 6786 6787 SDB->setValue(I, Res); 6788 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6789 if (LoadSDNode *LNode = 6790 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6791 if (FrameIndexSDNode *FI = 6792 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6793 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6794 } 6795 6796 // If this argument is live outside of the entry block, insert a copy from 6797 // wherever we got it to the vreg that other BB's will reference it as. 6798 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6799 // If we can, though, try to skip creating an unnecessary vreg. 6800 // FIXME: This isn't very clean... it would be nice to make this more 6801 // general. It's also subtly incompatible with the hacks FastISel 6802 // uses with vregs. 6803 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6804 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6805 FuncInfo->ValueMap[I] = Reg; 6806 continue; 6807 } 6808 } 6809 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 6810 FuncInfo->InitializeRegForValue(I); 6811 SDB->CopyToExportRegsIfNeeded(I); 6812 } 6813 } 6814 6815 assert(i == InVals.size() && "Argument register count mismatch!"); 6816 6817 // Finally, if the target has anything special to do, allow it to do so. 6818 // FIXME: this should insert code into the DAG! 6819 EmitFunctionEntryCode(); 6820} 6821 6822/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6823/// ensure constants are generated when needed. Remember the virtual registers 6824/// that need to be added to the Machine PHI nodes as input. We cannot just 6825/// directly add them, because expansion might result in multiple MBB's for one 6826/// BB. As such, the start of the BB might correspond to a different MBB than 6827/// the end. 6828/// 6829void 6830SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6831 const TerminatorInst *TI = LLVMBB->getTerminator(); 6832 6833 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6834 6835 // Check successor nodes' PHI nodes that expect a constant to be available 6836 // from this block. 6837 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6838 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6839 if (!isa<PHINode>(SuccBB->begin())) continue; 6840 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6841 6842 // If this terminator has multiple identical successors (common for 6843 // switches), only handle each succ once. 6844 if (!SuccsHandled.insert(SuccMBB)) continue; 6845 6846 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6847 6848 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6849 // nodes and Machine PHI nodes, but the incoming operands have not been 6850 // emitted yet. 6851 for (BasicBlock::const_iterator I = SuccBB->begin(); 6852 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6853 // Ignore dead phi's. 6854 if (PN->use_empty()) continue; 6855 6856 // Skip empty types 6857 if (PN->getType()->isEmptyTy()) 6858 continue; 6859 6860 unsigned Reg; 6861 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6862 6863 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6864 unsigned &RegOut = ConstantsOut[C]; 6865 if (RegOut == 0) { 6866 RegOut = FuncInfo.CreateRegs(C->getType()); 6867 CopyValueToVirtualRegister(C, RegOut); 6868 } 6869 Reg = RegOut; 6870 } else { 6871 DenseMap<const Value *, unsigned>::iterator I = 6872 FuncInfo.ValueMap.find(PHIOp); 6873 if (I != FuncInfo.ValueMap.end()) 6874 Reg = I->second; 6875 else { 6876 assert(isa<AllocaInst>(PHIOp) && 6877 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6878 "Didn't codegen value into a register!??"); 6879 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6880 CopyValueToVirtualRegister(PHIOp, Reg); 6881 } 6882 } 6883 6884 // Remember that this register needs to added to the machine PHI node as 6885 // the input for this MBB. 6886 SmallVector<EVT, 4> ValueVTs; 6887 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6888 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6889 EVT VT = ValueVTs[vti]; 6890 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6891 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6892 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6893 Reg += NumRegisters; 6894 } 6895 } 6896 } 6897 ConstantsOut.clear(); 6898} 6899