SelectionDAGBuilder.cpp revision 92efda7e9183ae16bde7a3ad96b682e779d89cf3
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/PseudoSourceValue.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Analysis/DebugInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameLowering.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/CommandLine.h" 55#include "llvm/Support/Debug.h" 56#include "llvm/Support/ErrorHandling.h" 57#include "llvm/Support/MathExtras.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62/// LimitFloatPrecision - Generate low-precision inline sequences for 63/// some float libcalls (6, 8 or 12 bits). 64static unsigned LimitFloatPrecision; 65 66static cl::opt<unsigned, true> 67LimitFPPrecision("limit-float-precision", 68 cl::desc("Generate low-precision inline sequences " 69 "for some float libcalls"), 70 cl::location(LimitFloatPrecision), 71 cl::init(0)); 72 73// Limit the width of DAG chains. This is important in general to prevent 74// prevent DAG-based analysis from blowing up. For example, alias analysis and 75// load clustering may not complete in reasonable time. It is difficult to 76// recognize and avoid this situation within each individual analysis, and 77// future analyses are likely to have the same behavior. Limiting DAG width is 78// the safe approach, and will be especially important with global DAGs. 79// 80// MaxParallelChains default is arbitrarily high to avoid affecting 81// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 82// sequence over this should have been converted to llvm.memcpy by the 83// frontend. It easy to induce this behavior with .ll code such as: 84// %buffer = alloca [4096 x i8] 85// %data = load [4096 x i8]* %argPtr 86// store [4096 x i8] %data, [4096 x i8]* %buffer 87static cl::opt<unsigned> 88MaxParallelChains("dag-chain-limit", cl::desc("Max parallel isel dag chains"), 89 cl::init(64), cl::Hidden); 90 91static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 92 const SDValue *Parts, unsigned NumParts, 93 EVT PartVT, EVT ValueVT); 94 95/// getCopyFromParts - Create a value that contains the specified legal parts 96/// combined into the value they represent. If the parts combine to a type 97/// larger then ValueVT then AssertOp can be used to specify whether the extra 98/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 99/// (ISD::AssertSext). 100static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 101 const SDValue *Parts, 102 unsigned NumParts, EVT PartVT, EVT ValueVT, 103 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 104 if (ValueVT.isVector()) 105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 106 107 assert(NumParts > 0 && "No parts to assemble!"); 108 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 109 SDValue Val = Parts[0]; 110 111 if (NumParts > 1) { 112 // Assemble the value from multiple parts. 113 if (ValueVT.isInteger()) { 114 unsigned PartBits = PartVT.getSizeInBits(); 115 unsigned ValueBits = ValueVT.getSizeInBits(); 116 117 // Assemble the power of 2 part. 118 unsigned RoundParts = NumParts & (NumParts - 1) ? 119 1 << Log2_32(NumParts) : NumParts; 120 unsigned RoundBits = PartBits * RoundParts; 121 EVT RoundVT = RoundBits == ValueBits ? 122 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 123 SDValue Lo, Hi; 124 125 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 126 127 if (RoundParts > 2) { 128 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 129 PartVT, HalfVT); 130 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 131 RoundParts / 2, PartVT, HalfVT); 132 } else { 133 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 134 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 135 } 136 137 if (TLI.isBigEndian()) 138 std::swap(Lo, Hi); 139 140 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 141 142 if (RoundParts < NumParts) { 143 // Assemble the trailing non-power-of-2 part. 144 unsigned OddParts = NumParts - RoundParts; 145 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 146 Hi = getCopyFromParts(DAG, DL, 147 Parts + RoundParts, OddParts, PartVT, OddVT); 148 149 // Combine the round and odd parts. 150 Lo = Val; 151 if (TLI.isBigEndian()) 152 std::swap(Lo, Hi); 153 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 154 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 155 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 156 DAG.getConstant(Lo.getValueType().getSizeInBits(), 157 TLI.getPointerTy())); 158 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 159 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 160 } 161 } else if (PartVT.isFloatingPoint()) { 162 // FP split into multiple FP parts (for ppcf128) 163 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 164 "Unexpected split"); 165 SDValue Lo, Hi; 166 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 167 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 168 if (TLI.isBigEndian()) 169 std::swap(Lo, Hi); 170 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 171 } else { 172 // FP split into integer parts (soft fp) 173 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 174 !PartVT.isVector() && "Unexpected split"); 175 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 176 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 177 } 178 } 179 180 // There is now one part, held in Val. Correct it to match ValueVT. 181 PartVT = Val.getValueType(); 182 183 if (PartVT == ValueVT) 184 return Val; 185 186 if (PartVT.isInteger() && ValueVT.isInteger()) { 187 if (ValueVT.bitsLT(PartVT)) { 188 // For a truncate, see if we have any information to 189 // indicate whether the truncated bits will always be 190 // zero or sign-extension. 191 if (AssertOp != ISD::DELETED_NODE) 192 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 193 DAG.getValueType(ValueVT)); 194 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 195 } 196 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 197 } 198 199 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 200 // FP_ROUND's are always exact here. 201 if (ValueVT.bitsLT(Val.getValueType())) 202 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 203 DAG.getIntPtrConstant(1)); 204 205 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 206 } 207 208 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 209 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 210 211 llvm_unreachable("Unknown mismatch!"); 212 return SDValue(); 213} 214 215/// getCopyFromParts - Create a value that contains the specified legal parts 216/// combined into the value they represent. If the parts combine to a type 217/// larger then ValueVT then AssertOp can be used to specify whether the extra 218/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 219/// (ISD::AssertSext). 220static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 221 const SDValue *Parts, unsigned NumParts, 222 EVT PartVT, EVT ValueVT) { 223 assert(ValueVT.isVector() && "Not a vector value"); 224 assert(NumParts > 0 && "No parts to assemble!"); 225 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 226 SDValue Val = Parts[0]; 227 228 // Handle a multi-element vector. 229 if (NumParts > 1) { 230 EVT IntermediateVT, RegisterVT; 231 unsigned NumIntermediates; 232 unsigned NumRegs = 233 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 234 NumIntermediates, RegisterVT); 235 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 236 NumParts = NumRegs; // Silence a compiler warning. 237 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 238 assert(RegisterVT == Parts[0].getValueType() && 239 "Part type doesn't match part!"); 240 241 // Assemble the parts into intermediate operands. 242 SmallVector<SDValue, 8> Ops(NumIntermediates); 243 if (NumIntermediates == NumParts) { 244 // If the register was not expanded, truncate or copy the value, 245 // as appropriate. 246 for (unsigned i = 0; i != NumParts; ++i) 247 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 248 PartVT, IntermediateVT); 249 } else if (NumParts > 0) { 250 // If the intermediate type was expanded, build the intermediate 251 // operands from the parts. 252 assert(NumParts % NumIntermediates == 0 && 253 "Must expand into a divisible number of parts!"); 254 unsigned Factor = NumParts / NumIntermediates; 255 for (unsigned i = 0; i != NumIntermediates; ++i) 256 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 257 PartVT, IntermediateVT); 258 } 259 260 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 261 // intermediate operands. 262 Val = DAG.getNode(IntermediateVT.isVector() ? 263 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 264 ValueVT, &Ops[0], NumIntermediates); 265 } 266 267 // There is now one part, held in Val. Correct it to match ValueVT. 268 PartVT = Val.getValueType(); 269 270 if (PartVT == ValueVT) 271 return Val; 272 273 if (PartVT.isVector()) { 274 // If the element type of the source/dest vectors are the same, but the 275 // parts vector has more elements than the value vector, then we have a 276 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 277 // elements we want. 278 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 279 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 280 "Cannot narrow, it would be a lossy transformation"); 281 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 282 DAG.getIntPtrConstant(0)); 283 } 284 285 // Vector/Vector bitcast. 286 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 287 } 288 289 assert(ValueVT.getVectorElementType() == PartVT && 290 ValueVT.getVectorNumElements() == 1 && 291 "Only trivial scalar-to-vector conversions should get here!"); 292 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 293} 294 295 296 297 298static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 299 SDValue Val, SDValue *Parts, unsigned NumParts, 300 EVT PartVT); 301 302/// getCopyToParts - Create a series of nodes that contain the specified value 303/// split into legal parts. If the parts contain more bits than Val, then, for 304/// integers, ExtendKind can be used to specify how to generate the extra bits. 305static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 306 SDValue Val, SDValue *Parts, unsigned NumParts, 307 EVT PartVT, 308 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 309 EVT ValueVT = Val.getValueType(); 310 311 // Handle the vector case separately. 312 if (ValueVT.isVector()) 313 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 314 315 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 316 unsigned PartBits = PartVT.getSizeInBits(); 317 unsigned OrigNumParts = NumParts; 318 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 319 320 if (NumParts == 0) 321 return; 322 323 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 324 if (PartVT == ValueVT) { 325 assert(NumParts == 1 && "No-op copy with multiple parts!"); 326 Parts[0] = Val; 327 return; 328 } 329 330 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 331 // If the parts cover more bits than the value has, promote the value. 332 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 333 assert(NumParts == 1 && "Do not know what to promote to!"); 334 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 335 } else { 336 assert(PartVT.isInteger() && ValueVT.isInteger() && 337 "Unknown mismatch!"); 338 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 339 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 340 } 341 } else if (PartBits == ValueVT.getSizeInBits()) { 342 // Different types of the same size. 343 assert(NumParts == 1 && PartVT != ValueVT); 344 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 345 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 346 // If the parts cover less bits than value has, truncate the value. 347 assert(PartVT.isInteger() && ValueVT.isInteger() && 348 "Unknown mismatch!"); 349 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 350 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 351 } 352 353 // The value may have changed - recompute ValueVT. 354 ValueVT = Val.getValueType(); 355 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 356 "Failed to tile the value with PartVT!"); 357 358 if (NumParts == 1) { 359 assert(PartVT == ValueVT && "Type conversion failed!"); 360 Parts[0] = Val; 361 return; 362 } 363 364 // Expand the value into multiple parts. 365 if (NumParts & (NumParts - 1)) { 366 // The number of parts is not a power of 2. Split off and copy the tail. 367 assert(PartVT.isInteger() && ValueVT.isInteger() && 368 "Do not know what to expand to!"); 369 unsigned RoundParts = 1 << Log2_32(NumParts); 370 unsigned RoundBits = RoundParts * PartBits; 371 unsigned OddParts = NumParts - RoundParts; 372 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 373 DAG.getIntPtrConstant(RoundBits)); 374 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 375 376 if (TLI.isBigEndian()) 377 // The odd parts were reversed by getCopyToParts - unreverse them. 378 std::reverse(Parts + RoundParts, Parts + NumParts); 379 380 NumParts = RoundParts; 381 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 382 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 383 } 384 385 // The number of parts is a power of 2. Repeatedly bisect the value using 386 // EXTRACT_ELEMENT. 387 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 388 EVT::getIntegerVT(*DAG.getContext(), 389 ValueVT.getSizeInBits()), 390 Val); 391 392 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 393 for (unsigned i = 0; i < NumParts; i += StepSize) { 394 unsigned ThisBits = StepSize * PartBits / 2; 395 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 396 SDValue &Part0 = Parts[i]; 397 SDValue &Part1 = Parts[i+StepSize/2]; 398 399 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 400 ThisVT, Part0, DAG.getIntPtrConstant(1)); 401 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 402 ThisVT, Part0, DAG.getIntPtrConstant(0)); 403 404 if (ThisBits == PartBits && ThisVT != PartVT) { 405 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 406 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 407 } 408 } 409 } 410 411 if (TLI.isBigEndian()) 412 std::reverse(Parts, Parts + OrigNumParts); 413} 414 415 416/// getCopyToPartsVector - Create a series of nodes that contain the specified 417/// value split into legal parts. 418static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 419 SDValue Val, SDValue *Parts, unsigned NumParts, 420 EVT PartVT) { 421 EVT ValueVT = Val.getValueType(); 422 assert(ValueVT.isVector() && "Not a vector"); 423 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 424 425 if (NumParts == 1) { 426 if (PartVT == ValueVT) { 427 // Nothing to do. 428 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 429 // Bitconvert vector->vector case. 430 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 431 } else if (PartVT.isVector() && 432 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&& 433 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 434 EVT ElementVT = PartVT.getVectorElementType(); 435 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 436 // undef elements. 437 SmallVector<SDValue, 16> Ops; 438 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 439 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 440 ElementVT, Val, DAG.getIntPtrConstant(i))); 441 442 for (unsigned i = ValueVT.getVectorNumElements(), 443 e = PartVT.getVectorNumElements(); i != e; ++i) 444 Ops.push_back(DAG.getUNDEF(ElementVT)); 445 446 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 447 448 // FIXME: Use CONCAT for 2x -> 4x. 449 450 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 451 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 452 } else { 453 // Vector -> scalar conversion. 454 assert(ValueVT.getVectorElementType() == PartVT && 455 ValueVT.getVectorNumElements() == 1 && 456 "Only trivial vector-to-scalar conversions should get here!"); 457 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 458 PartVT, Val, DAG.getIntPtrConstant(0)); 459 } 460 461 Parts[0] = Val; 462 return; 463 } 464 465 // Handle a multi-element vector. 466 EVT IntermediateVT, RegisterVT; 467 unsigned NumIntermediates; 468 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 469 IntermediateVT, 470 NumIntermediates, RegisterVT); 471 unsigned NumElements = ValueVT.getVectorNumElements(); 472 473 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 474 NumParts = NumRegs; // Silence a compiler warning. 475 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 476 477 // Split the vector into intermediate operands. 478 SmallVector<SDValue, 8> Ops(NumIntermediates); 479 for (unsigned i = 0; i != NumIntermediates; ++i) { 480 if (IntermediateVT.isVector()) 481 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 482 IntermediateVT, Val, 483 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 484 else 485 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 486 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 487 } 488 489 // Split the intermediate operands into legal parts. 490 if (NumParts == NumIntermediates) { 491 // If the register was not expanded, promote or copy the value, 492 // as appropriate. 493 for (unsigned i = 0; i != NumParts; ++i) 494 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 495 } else if (NumParts > 0) { 496 // If the intermediate type was expanded, split each the value into 497 // legal parts. 498 assert(NumParts % NumIntermediates == 0 && 499 "Must expand into a divisible number of parts!"); 500 unsigned Factor = NumParts / NumIntermediates; 501 for (unsigned i = 0; i != NumIntermediates; ++i) 502 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 503 } 504} 505 506 507 508 509namespace { 510 /// RegsForValue - This struct represents the registers (physical or virtual) 511 /// that a particular set of values is assigned, and the type information 512 /// about the value. The most common situation is to represent one value at a 513 /// time, but struct or array values are handled element-wise as multiple 514 /// values. The splitting of aggregates is performed recursively, so that we 515 /// never have aggregate-typed registers. The values at this point do not 516 /// necessarily have legal types, so each value may require one or more 517 /// registers of some legal type. 518 /// 519 struct RegsForValue { 520 /// ValueVTs - The value types of the values, which may not be legal, and 521 /// may need be promoted or synthesized from one or more registers. 522 /// 523 SmallVector<EVT, 4> ValueVTs; 524 525 /// RegVTs - The value types of the registers. This is the same size as 526 /// ValueVTs and it records, for each value, what the type of the assigned 527 /// register or registers are. (Individual values are never synthesized 528 /// from more than one type of register.) 529 /// 530 /// With virtual registers, the contents of RegVTs is redundant with TLI's 531 /// getRegisterType member function, however when with physical registers 532 /// it is necessary to have a separate record of the types. 533 /// 534 SmallVector<EVT, 4> RegVTs; 535 536 /// Regs - This list holds the registers assigned to the values. 537 /// Each legal or promoted value requires one register, and each 538 /// expanded value requires multiple registers. 539 /// 540 SmallVector<unsigned, 4> Regs; 541 542 RegsForValue() {} 543 544 RegsForValue(const SmallVector<unsigned, 4> ®s, 545 EVT regvt, EVT valuevt) 546 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 547 548 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 549 unsigned Reg, const Type *Ty) { 550 ComputeValueVTs(tli, Ty, ValueVTs); 551 552 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 553 EVT ValueVT = ValueVTs[Value]; 554 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 555 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 556 for (unsigned i = 0; i != NumRegs; ++i) 557 Regs.push_back(Reg + i); 558 RegVTs.push_back(RegisterVT); 559 Reg += NumRegs; 560 } 561 } 562 563 /// areValueTypesLegal - Return true if types of all the values are legal. 564 bool areValueTypesLegal(const TargetLowering &TLI) { 565 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 566 EVT RegisterVT = RegVTs[Value]; 567 if (!TLI.isTypeLegal(RegisterVT)) 568 return false; 569 } 570 return true; 571 } 572 573 /// append - Add the specified values to this one. 574 void append(const RegsForValue &RHS) { 575 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 576 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 577 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 578 } 579 580 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 581 /// this value and returns the result as a ValueVTs value. This uses 582 /// Chain/Flag as the input and updates them for the output Chain/Flag. 583 /// If the Flag pointer is NULL, no flag is used. 584 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 585 DebugLoc dl, 586 SDValue &Chain, SDValue *Flag) const; 587 588 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 589 /// specified value into the registers specified by this object. This uses 590 /// Chain/Flag as the input and updates them for the output Chain/Flag. 591 /// If the Flag pointer is NULL, no flag is used. 592 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 593 SDValue &Chain, SDValue *Flag) const; 594 595 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 596 /// operand list. This adds the code marker, matching input operand index 597 /// (if applicable), and includes the number of values added into it. 598 void AddInlineAsmOperands(unsigned Kind, 599 bool HasMatching, unsigned MatchingIdx, 600 SelectionDAG &DAG, 601 std::vector<SDValue> &Ops) const; 602 }; 603} 604 605/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 606/// this value and returns the result as a ValueVT value. This uses 607/// Chain/Flag as the input and updates them for the output Chain/Flag. 608/// If the Flag pointer is NULL, no flag is used. 609SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 610 FunctionLoweringInfo &FuncInfo, 611 DebugLoc dl, 612 SDValue &Chain, SDValue *Flag) const { 613 // A Value with type {} or [0 x %t] needs no registers. 614 if (ValueVTs.empty()) 615 return SDValue(); 616 617 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 618 619 // Assemble the legal parts into the final values. 620 SmallVector<SDValue, 4> Values(ValueVTs.size()); 621 SmallVector<SDValue, 8> Parts; 622 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 623 // Copy the legal parts from the registers. 624 EVT ValueVT = ValueVTs[Value]; 625 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 626 EVT RegisterVT = RegVTs[Value]; 627 628 Parts.resize(NumRegs); 629 for (unsigned i = 0; i != NumRegs; ++i) { 630 SDValue P; 631 if (Flag == 0) { 632 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 633 } else { 634 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 635 *Flag = P.getValue(2); 636 } 637 638 Chain = P.getValue(1); 639 Parts[i] = P; 640 641 // If the source register was virtual and if we know something about it, 642 // add an assert node. 643 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 644 !RegisterVT.isInteger() || RegisterVT.isVector() || 645 !FuncInfo.LiveOutRegInfo.inBounds(Regs[Part+i])) 646 continue; 647 648 if (FuncInfo.PHIDestRegs.count(Regs[Part+i]) && !FuncInfo.AllPredsVisited) 649 continue; 650 651 const FunctionLoweringInfo::LiveOutInfo &LOI = 652 FuncInfo.LiveOutRegInfo[Regs[Part+i]]; 653 654 unsigned RegSize = RegisterVT.getSizeInBits(); 655 unsigned NumSignBits = LOI.NumSignBits; 656 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 657 658 // FIXME: We capture more information than the dag can represent. For 659 // now, just use the tightest assertzext/assertsext possible. 660 bool isSExt = true; 661 EVT FromVT(MVT::Other); 662 if (NumSignBits == RegSize) 663 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 664 else if (NumZeroBits >= RegSize-1) 665 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 666 else if (NumSignBits > RegSize-8) 667 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 668 else if (NumZeroBits >= RegSize-8) 669 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 670 else if (NumSignBits > RegSize-16) 671 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 672 else if (NumZeroBits >= RegSize-16) 673 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 674 else if (NumSignBits > RegSize-32) 675 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 676 else if (NumZeroBits >= RegSize-32) 677 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 678 else 679 continue; 680 681 // Add an assertion node. 682 assert(FromVT != MVT::Other); 683 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 684 RegisterVT, P, DAG.getValueType(FromVT)); 685 } 686 687 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 688 NumRegs, RegisterVT, ValueVT); 689 Part += NumRegs; 690 Parts.clear(); 691 } 692 693 return DAG.getNode(ISD::MERGE_VALUES, dl, 694 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 695 &Values[0], ValueVTs.size()); 696} 697 698/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 699/// specified value into the registers specified by this object. This uses 700/// Chain/Flag as the input and updates them for the output Chain/Flag. 701/// If the Flag pointer is NULL, no flag is used. 702void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 703 SDValue &Chain, SDValue *Flag) const { 704 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 705 706 // Get the list of the values's legal parts. 707 unsigned NumRegs = Regs.size(); 708 SmallVector<SDValue, 8> Parts(NumRegs); 709 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 710 EVT ValueVT = ValueVTs[Value]; 711 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 712 EVT RegisterVT = RegVTs[Value]; 713 714 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 715 &Parts[Part], NumParts, RegisterVT); 716 Part += NumParts; 717 } 718 719 // Copy the parts into the registers. 720 SmallVector<SDValue, 8> Chains(NumRegs); 721 for (unsigned i = 0; i != NumRegs; ++i) { 722 SDValue Part; 723 if (Flag == 0) { 724 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 725 } else { 726 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 727 *Flag = Part.getValue(1); 728 } 729 730 Chains[i] = Part.getValue(0); 731 } 732 733 if (NumRegs == 1 || Flag) 734 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 735 // flagged to it. That is the CopyToReg nodes and the user are considered 736 // a single scheduling unit. If we create a TokenFactor and return it as 737 // chain, then the TokenFactor is both a predecessor (operand) of the 738 // user as well as a successor (the TF operands are flagged to the user). 739 // c1, f1 = CopyToReg 740 // c2, f2 = CopyToReg 741 // c3 = TokenFactor c1, c2 742 // ... 743 // = op c3, ..., f2 744 Chain = Chains[NumRegs-1]; 745 else 746 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 747} 748 749/// AddInlineAsmOperands - Add this value to the specified inlineasm node 750/// operand list. This adds the code marker and includes the number of 751/// values added into it. 752void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 753 unsigned MatchingIdx, 754 SelectionDAG &DAG, 755 std::vector<SDValue> &Ops) const { 756 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 757 758 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 759 if (HasMatching) 760 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 761 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 762 Ops.push_back(Res); 763 764 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 765 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 766 EVT RegisterVT = RegVTs[Value]; 767 for (unsigned i = 0; i != NumRegs; ++i) { 768 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 769 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 770 } 771 } 772} 773 774void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 775 AA = &aa; 776 GFI = gfi; 777 TD = DAG.getTarget().getTargetData(); 778} 779 780/// clear - Clear out the current SelectionDAG and the associated 781/// state and prepare this SelectionDAGBuilder object to be used 782/// for a new block. This doesn't clear out information about 783/// additional blocks that are needed to complete switch lowering 784/// or PHI node updating; that information is cleared out as it is 785/// consumed. 786void SelectionDAGBuilder::clear() { 787 NodeMap.clear(); 788 UnusedArgNodeMap.clear(); 789 PendingLoads.clear(); 790 PendingExports.clear(); 791 DanglingDebugInfoMap.clear(); 792 CurDebugLoc = DebugLoc(); 793 HasTailCall = false; 794} 795 796/// getRoot - Return the current virtual root of the Selection DAG, 797/// flushing any PendingLoad items. This must be done before emitting 798/// a store or any other node that may need to be ordered after any 799/// prior load instructions. 800/// 801SDValue SelectionDAGBuilder::getRoot() { 802 if (PendingLoads.empty()) 803 return DAG.getRoot(); 804 805 if (PendingLoads.size() == 1) { 806 SDValue Root = PendingLoads[0]; 807 DAG.setRoot(Root); 808 PendingLoads.clear(); 809 return Root; 810 } 811 812 // Otherwise, we have to make a token factor node. 813 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 814 &PendingLoads[0], PendingLoads.size()); 815 PendingLoads.clear(); 816 DAG.setRoot(Root); 817 return Root; 818} 819 820/// getControlRoot - Similar to getRoot, but instead of flushing all the 821/// PendingLoad items, flush all the PendingExports items. It is necessary 822/// to do this before emitting a terminator instruction. 823/// 824SDValue SelectionDAGBuilder::getControlRoot() { 825 SDValue Root = DAG.getRoot(); 826 827 if (PendingExports.empty()) 828 return Root; 829 830 // Turn all of the CopyToReg chains into one factored node. 831 if (Root.getOpcode() != ISD::EntryToken) { 832 unsigned i = 0, e = PendingExports.size(); 833 for (; i != e; ++i) { 834 assert(PendingExports[i].getNode()->getNumOperands() > 1); 835 if (PendingExports[i].getNode()->getOperand(0) == Root) 836 break; // Don't add the root if we already indirectly depend on it. 837 } 838 839 if (i == e) 840 PendingExports.push_back(Root); 841 } 842 843 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 844 &PendingExports[0], 845 PendingExports.size()); 846 PendingExports.clear(); 847 DAG.setRoot(Root); 848 return Root; 849} 850 851void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 852 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 853 DAG.AssignOrdering(Node, SDNodeOrder); 854 855 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 856 AssignOrderingToNode(Node->getOperand(I).getNode()); 857} 858 859void SelectionDAGBuilder::visit(const Instruction &I) { 860 // Set up outgoing PHI node register values before emitting the terminator. 861 if (isa<TerminatorInst>(&I)) 862 HandlePHINodesInSuccessorBlocks(I.getParent()); 863 864 CurDebugLoc = I.getDebugLoc(); 865 866 visit(I.getOpcode(), I); 867 868 if (!isa<TerminatorInst>(&I) && !HasTailCall) 869 CopyToExportRegsIfNeeded(&I); 870 871 CurDebugLoc = DebugLoc(); 872} 873 874void SelectionDAGBuilder::visitPHI(const PHINode &) { 875 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 876} 877 878void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 879 // Note: this doesn't use InstVisitor, because it has to work with 880 // ConstantExpr's in addition to instructions. 881 switch (Opcode) { 882 default: llvm_unreachable("Unknown instruction type encountered!"); 883 // Build the switch statement using the Instruction.def file. 884#define HANDLE_INST(NUM, OPCODE, CLASS) \ 885 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 886#include "llvm/Instruction.def" 887 } 888 889 // Assign the ordering to the freshly created DAG nodes. 890 if (NodeMap.count(&I)) { 891 ++SDNodeOrder; 892 AssignOrderingToNode(getValue(&I).getNode()); 893 } 894} 895 896// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 897// generate the debug data structures now that we've seen its definition. 898void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 899 SDValue Val) { 900 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 901 if (DDI.getDI()) { 902 const DbgValueInst *DI = DDI.getDI(); 903 DebugLoc dl = DDI.getdl(); 904 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 905 MDNode *Variable = DI->getVariable(); 906 uint64_t Offset = DI->getOffset(); 907 SDDbgValue *SDV; 908 if (Val.getNode()) { 909 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 910 SDV = DAG.getDbgValue(Variable, Val.getNode(), 911 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 912 DAG.AddDbgValue(SDV, Val.getNode(), false); 913 } 914 } else 915 DEBUG(dbgs() << "Dropping debug info for " << DI); 916 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 917 } 918} 919 920// getValue - Return an SDValue for the given Value. 921SDValue SelectionDAGBuilder::getValue(const Value *V) { 922 // If we already have an SDValue for this value, use it. It's important 923 // to do this first, so that we don't create a CopyFromReg if we already 924 // have a regular SDValue. 925 SDValue &N = NodeMap[V]; 926 if (N.getNode()) return N; 927 928 // If there's a virtual register allocated and initialized for this 929 // value, use it. 930 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 931 if (It != FuncInfo.ValueMap.end()) { 932 unsigned InReg = It->second; 933 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 934 SDValue Chain = DAG.getEntryNode(); 935 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 936 resolveDanglingDebugInfo(V, N); 937 return N; 938 } 939 940 // Otherwise create a new SDValue and remember it. 941 SDValue Val = getValueImpl(V); 942 NodeMap[V] = Val; 943 resolveDanglingDebugInfo(V, Val); 944 return Val; 945} 946 947/// getNonRegisterValue - Return an SDValue for the given Value, but 948/// don't look in FuncInfo.ValueMap for a virtual register. 949SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 950 // If we already have an SDValue for this value, use it. 951 SDValue &N = NodeMap[V]; 952 if (N.getNode()) return N; 953 954 // Otherwise create a new SDValue and remember it. 955 SDValue Val = getValueImpl(V); 956 NodeMap[V] = Val; 957 resolveDanglingDebugInfo(V, Val); 958 return Val; 959} 960 961/// getValueImpl - Helper function for getValue and getNonRegisterValue. 962/// Create an SDValue for the given value. 963SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 964 if (const Constant *C = dyn_cast<Constant>(V)) { 965 EVT VT = TLI.getValueType(V->getType(), true); 966 967 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 968 return DAG.getConstant(*CI, VT); 969 970 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 971 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 972 973 if (isa<ConstantPointerNull>(C)) 974 return DAG.getConstant(0, TLI.getPointerTy()); 975 976 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 977 return DAG.getConstantFP(*CFP, VT); 978 979 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 980 return DAG.getUNDEF(VT); 981 982 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 983 visit(CE->getOpcode(), *CE); 984 SDValue N1 = NodeMap[V]; 985 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 986 return N1; 987 } 988 989 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 990 SmallVector<SDValue, 4> Constants; 991 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 992 OI != OE; ++OI) { 993 SDNode *Val = getValue(*OI).getNode(); 994 // If the operand is an empty aggregate, there are no values. 995 if (!Val) continue; 996 // Add each leaf value from the operand to the Constants list 997 // to form a flattened list of all the values. 998 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 999 Constants.push_back(SDValue(Val, i)); 1000 } 1001 1002 return DAG.getMergeValues(&Constants[0], Constants.size(), 1003 getCurDebugLoc()); 1004 } 1005 1006 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1007 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1008 "Unknown struct or array constant!"); 1009 1010 SmallVector<EVT, 4> ValueVTs; 1011 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1012 unsigned NumElts = ValueVTs.size(); 1013 if (NumElts == 0) 1014 return SDValue(); // empty struct 1015 SmallVector<SDValue, 4> Constants(NumElts); 1016 for (unsigned i = 0; i != NumElts; ++i) { 1017 EVT EltVT = ValueVTs[i]; 1018 if (isa<UndefValue>(C)) 1019 Constants[i] = DAG.getUNDEF(EltVT); 1020 else if (EltVT.isFloatingPoint()) 1021 Constants[i] = DAG.getConstantFP(0, EltVT); 1022 else 1023 Constants[i] = DAG.getConstant(0, EltVT); 1024 } 1025 1026 return DAG.getMergeValues(&Constants[0], NumElts, 1027 getCurDebugLoc()); 1028 } 1029 1030 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1031 return DAG.getBlockAddress(BA, VT); 1032 1033 const VectorType *VecTy = cast<VectorType>(V->getType()); 1034 unsigned NumElements = VecTy->getNumElements(); 1035 1036 // Now that we know the number and type of the elements, get that number of 1037 // elements into the Ops array based on what kind of constant it is. 1038 SmallVector<SDValue, 16> Ops; 1039 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1040 for (unsigned i = 0; i != NumElements; ++i) 1041 Ops.push_back(getValue(CP->getOperand(i))); 1042 } else { 1043 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1044 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1045 1046 SDValue Op; 1047 if (EltVT.isFloatingPoint()) 1048 Op = DAG.getConstantFP(0, EltVT); 1049 else 1050 Op = DAG.getConstant(0, EltVT); 1051 Ops.assign(NumElements, Op); 1052 } 1053 1054 // Create a BUILD_VECTOR node. 1055 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1056 VT, &Ops[0], Ops.size()); 1057 } 1058 1059 // If this is a static alloca, generate it as the frameindex instead of 1060 // computation. 1061 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1062 DenseMap<const AllocaInst*, int>::iterator SI = 1063 FuncInfo.StaticAllocaMap.find(AI); 1064 if (SI != FuncInfo.StaticAllocaMap.end()) 1065 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1066 } 1067 1068 // If this is an instruction which fast-isel has deferred, select it now. 1069 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1070 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1071 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1072 SDValue Chain = DAG.getEntryNode(); 1073 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1074 } 1075 1076 llvm_unreachable("Can't get register for value!"); 1077 return SDValue(); 1078} 1079 1080void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1081 SDValue Chain = getControlRoot(); 1082 SmallVector<ISD::OutputArg, 8> Outs; 1083 SmallVector<SDValue, 8> OutVals; 1084 1085 if (!FuncInfo.CanLowerReturn) { 1086 unsigned DemoteReg = FuncInfo.DemoteRegister; 1087 const Function *F = I.getParent()->getParent(); 1088 1089 // Emit a store of the return value through the virtual register. 1090 // Leave Outs empty so that LowerReturn won't try to load return 1091 // registers the usual way. 1092 SmallVector<EVT, 1> PtrValueVTs; 1093 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1094 PtrValueVTs); 1095 1096 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1097 SDValue RetOp = getValue(I.getOperand(0)); 1098 1099 SmallVector<EVT, 4> ValueVTs; 1100 SmallVector<uint64_t, 4> Offsets; 1101 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1102 unsigned NumValues = ValueVTs.size(); 1103 1104 SmallVector<SDValue, 4> Chains(NumValues); 1105 for (unsigned i = 0; i != NumValues; ++i) { 1106 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1107 RetPtr.getValueType(), RetPtr, 1108 DAG.getIntPtrConstant(Offsets[i])); 1109 Chains[i] = 1110 DAG.getStore(Chain, getCurDebugLoc(), 1111 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1112 // FIXME: better loc info would be nice. 1113 Add, MachinePointerInfo(), false, false, 0); 1114 } 1115 1116 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1117 MVT::Other, &Chains[0], NumValues); 1118 } else if (I.getNumOperands() != 0) { 1119 SmallVector<EVT, 4> ValueVTs; 1120 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1121 unsigned NumValues = ValueVTs.size(); 1122 if (NumValues) { 1123 SDValue RetOp = getValue(I.getOperand(0)); 1124 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1125 EVT VT = ValueVTs[j]; 1126 1127 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1128 1129 const Function *F = I.getParent()->getParent(); 1130 if (F->paramHasAttr(0, Attribute::SExt)) 1131 ExtendKind = ISD::SIGN_EXTEND; 1132 else if (F->paramHasAttr(0, Attribute::ZExt)) 1133 ExtendKind = ISD::ZERO_EXTEND; 1134 1135 // FIXME: C calling convention requires the return type to be promoted 1136 // to at least 32-bit. But this is not necessary for non-C calling 1137 // conventions. The frontend should mark functions whose return values 1138 // require promoting with signext or zeroext attributes. 1139 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1140 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32); 1141 if (VT.bitsLT(MinVT)) 1142 VT = MinVT; 1143 } 1144 1145 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1146 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1147 SmallVector<SDValue, 4> Parts(NumParts); 1148 getCopyToParts(DAG, getCurDebugLoc(), 1149 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1150 &Parts[0], NumParts, PartVT, ExtendKind); 1151 1152 // 'inreg' on function refers to return value 1153 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1154 if (F->paramHasAttr(0, Attribute::InReg)) 1155 Flags.setInReg(); 1156 1157 // Propagate extension type if any 1158 if (F->paramHasAttr(0, Attribute::SExt)) 1159 Flags.setSExt(); 1160 else if (F->paramHasAttr(0, Attribute::ZExt)) 1161 Flags.setZExt(); 1162 1163 for (unsigned i = 0; i < NumParts; ++i) { 1164 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1165 /*isfixed=*/true)); 1166 OutVals.push_back(Parts[i]); 1167 } 1168 } 1169 } 1170 } 1171 1172 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1173 CallingConv::ID CallConv = 1174 DAG.getMachineFunction().getFunction()->getCallingConv(); 1175 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1176 Outs, OutVals, getCurDebugLoc(), DAG); 1177 1178 // Verify that the target's LowerReturn behaved as expected. 1179 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1180 "LowerReturn didn't return a valid chain!"); 1181 1182 // Update the DAG with the new chain value resulting from return lowering. 1183 DAG.setRoot(Chain); 1184} 1185 1186/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1187/// created for it, emit nodes to copy the value into the virtual 1188/// registers. 1189void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1190 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1191 if (VMI != FuncInfo.ValueMap.end()) { 1192 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1193 CopyValueToVirtualRegister(V, VMI->second); 1194 } 1195} 1196 1197/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1198/// the current basic block, add it to ValueMap now so that we'll get a 1199/// CopyTo/FromReg. 1200void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1201 // No need to export constants. 1202 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1203 1204 // Already exported? 1205 if (FuncInfo.isExportedInst(V)) return; 1206 1207 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1208 CopyValueToVirtualRegister(V, Reg); 1209} 1210 1211bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1212 const BasicBlock *FromBB) { 1213 // The operands of the setcc have to be in this block. We don't know 1214 // how to export them from some other block. 1215 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1216 // Can export from current BB. 1217 if (VI->getParent() == FromBB) 1218 return true; 1219 1220 // Is already exported, noop. 1221 return FuncInfo.isExportedInst(V); 1222 } 1223 1224 // If this is an argument, we can export it if the BB is the entry block or 1225 // if it is already exported. 1226 if (isa<Argument>(V)) { 1227 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1228 return true; 1229 1230 // Otherwise, can only export this if it is already exported. 1231 return FuncInfo.isExportedInst(V); 1232 } 1233 1234 // Otherwise, constants can always be exported. 1235 return true; 1236} 1237 1238static bool InBlock(const Value *V, const BasicBlock *BB) { 1239 if (const Instruction *I = dyn_cast<Instruction>(V)) 1240 return I->getParent() == BB; 1241 return true; 1242} 1243 1244/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1245/// This function emits a branch and is used at the leaves of an OR or an 1246/// AND operator tree. 1247/// 1248void 1249SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1250 MachineBasicBlock *TBB, 1251 MachineBasicBlock *FBB, 1252 MachineBasicBlock *CurBB, 1253 MachineBasicBlock *SwitchBB) { 1254 const BasicBlock *BB = CurBB->getBasicBlock(); 1255 1256 // If the leaf of the tree is a comparison, merge the condition into 1257 // the caseblock. 1258 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1259 // The operands of the cmp have to be in this block. We don't know 1260 // how to export them from some other block. If this is the first block 1261 // of the sequence, no exporting is needed. 1262 if (CurBB == SwitchBB || 1263 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1264 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1265 ISD::CondCode Condition; 1266 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1267 Condition = getICmpCondCode(IC->getPredicate()); 1268 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1269 Condition = getFCmpCondCode(FC->getPredicate()); 1270 } else { 1271 Condition = ISD::SETEQ; // silence warning. 1272 llvm_unreachable("Unknown compare instruction"); 1273 } 1274 1275 CaseBlock CB(Condition, BOp->getOperand(0), 1276 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1277 SwitchCases.push_back(CB); 1278 return; 1279 } 1280 } 1281 1282 // Create a CaseBlock record representing this branch. 1283 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1284 NULL, TBB, FBB, CurBB); 1285 SwitchCases.push_back(CB); 1286} 1287 1288/// FindMergedConditions - If Cond is an expression like 1289void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1290 MachineBasicBlock *TBB, 1291 MachineBasicBlock *FBB, 1292 MachineBasicBlock *CurBB, 1293 MachineBasicBlock *SwitchBB, 1294 unsigned Opc) { 1295 // If this node is not part of the or/and tree, emit it as a branch. 1296 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1297 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1298 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1299 BOp->getParent() != CurBB->getBasicBlock() || 1300 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1301 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1302 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1303 return; 1304 } 1305 1306 // Create TmpBB after CurBB. 1307 MachineFunction::iterator BBI = CurBB; 1308 MachineFunction &MF = DAG.getMachineFunction(); 1309 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1310 CurBB->getParent()->insert(++BBI, TmpBB); 1311 1312 if (Opc == Instruction::Or) { 1313 // Codegen X | Y as: 1314 // jmp_if_X TBB 1315 // jmp TmpBB 1316 // TmpBB: 1317 // jmp_if_Y TBB 1318 // jmp FBB 1319 // 1320 1321 // Emit the LHS condition. 1322 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1323 1324 // Emit the RHS condition into TmpBB. 1325 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1326 } else { 1327 assert(Opc == Instruction::And && "Unknown merge op!"); 1328 // Codegen X & Y as: 1329 // jmp_if_X TmpBB 1330 // jmp FBB 1331 // TmpBB: 1332 // jmp_if_Y TBB 1333 // jmp FBB 1334 // 1335 // This requires creation of TmpBB after CurBB. 1336 1337 // Emit the LHS condition. 1338 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1339 1340 // Emit the RHS condition into TmpBB. 1341 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1342 } 1343} 1344 1345/// If the set of cases should be emitted as a series of branches, return true. 1346/// If we should emit this as a bunch of and/or'd together conditions, return 1347/// false. 1348bool 1349SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1350 if (Cases.size() != 2) return true; 1351 1352 // If this is two comparisons of the same values or'd or and'd together, they 1353 // will get folded into a single comparison, so don't emit two blocks. 1354 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1355 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1356 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1357 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1358 return false; 1359 } 1360 1361 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1362 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1363 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1364 Cases[0].CC == Cases[1].CC && 1365 isa<Constant>(Cases[0].CmpRHS) && 1366 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1367 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1368 return false; 1369 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1370 return false; 1371 } 1372 1373 return true; 1374} 1375 1376void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1377 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1378 1379 // Update machine-CFG edges. 1380 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1381 1382 // Figure out which block is immediately after the current one. 1383 MachineBasicBlock *NextBlock = 0; 1384 MachineFunction::iterator BBI = BrMBB; 1385 if (++BBI != FuncInfo.MF->end()) 1386 NextBlock = BBI; 1387 1388 if (I.isUnconditional()) { 1389 // Update machine-CFG edges. 1390 BrMBB->addSuccessor(Succ0MBB); 1391 1392 // If this is not a fall-through branch, emit the branch. 1393 if (Succ0MBB != NextBlock) 1394 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1395 MVT::Other, getControlRoot(), 1396 DAG.getBasicBlock(Succ0MBB))); 1397 1398 return; 1399 } 1400 1401 // If this condition is one of the special cases we handle, do special stuff 1402 // now. 1403 const Value *CondVal = I.getCondition(); 1404 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1405 1406 // If this is a series of conditions that are or'd or and'd together, emit 1407 // this as a sequence of branches instead of setcc's with and/or operations. 1408 // As long as jumps are not expensive, this should improve performance. 1409 // For example, instead of something like: 1410 // cmp A, B 1411 // C = seteq 1412 // cmp D, E 1413 // F = setle 1414 // or C, F 1415 // jnz foo 1416 // Emit: 1417 // cmp A, B 1418 // je foo 1419 // cmp D, E 1420 // jle foo 1421 // 1422 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1423 if (!TLI.isJumpExpensive() && 1424 BOp->hasOneUse() && 1425 (BOp->getOpcode() == Instruction::And || 1426 BOp->getOpcode() == Instruction::Or)) { 1427 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1428 BOp->getOpcode()); 1429 // If the compares in later blocks need to use values not currently 1430 // exported from this block, export them now. This block should always 1431 // be the first entry. 1432 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1433 1434 // Allow some cases to be rejected. 1435 if (ShouldEmitAsBranches(SwitchCases)) { 1436 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1437 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1438 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1439 } 1440 1441 // Emit the branch for this block. 1442 visitSwitchCase(SwitchCases[0], BrMBB); 1443 SwitchCases.erase(SwitchCases.begin()); 1444 return; 1445 } 1446 1447 // Okay, we decided not to do this, remove any inserted MBB's and clear 1448 // SwitchCases. 1449 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1450 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1451 1452 SwitchCases.clear(); 1453 } 1454 } 1455 1456 // Create a CaseBlock record representing this branch. 1457 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1458 NULL, Succ0MBB, Succ1MBB, BrMBB); 1459 1460 // Use visitSwitchCase to actually insert the fast branch sequence for this 1461 // cond branch. 1462 visitSwitchCase(CB, BrMBB); 1463} 1464 1465/// visitSwitchCase - Emits the necessary code to represent a single node in 1466/// the binary search tree resulting from lowering a switch instruction. 1467void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1468 MachineBasicBlock *SwitchBB) { 1469 SDValue Cond; 1470 SDValue CondLHS = getValue(CB.CmpLHS); 1471 DebugLoc dl = getCurDebugLoc(); 1472 1473 // Build the setcc now. 1474 if (CB.CmpMHS == NULL) { 1475 // Fold "(X == true)" to X and "(X == false)" to !X to 1476 // handle common cases produced by branch lowering. 1477 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1478 CB.CC == ISD::SETEQ) 1479 Cond = CondLHS; 1480 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1481 CB.CC == ISD::SETEQ) { 1482 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1483 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1484 } else 1485 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1486 } else { 1487 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1488 1489 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1490 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1491 1492 SDValue CmpOp = getValue(CB.CmpMHS); 1493 EVT VT = CmpOp.getValueType(); 1494 1495 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1496 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1497 ISD::SETLE); 1498 } else { 1499 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1500 VT, CmpOp, DAG.getConstant(Low, VT)); 1501 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1502 DAG.getConstant(High-Low, VT), ISD::SETULE); 1503 } 1504 } 1505 1506 // Update successor info 1507 SwitchBB->addSuccessor(CB.TrueBB); 1508 SwitchBB->addSuccessor(CB.FalseBB); 1509 1510 // Set NextBlock to be the MBB immediately after the current one, if any. 1511 // This is used to avoid emitting unnecessary branches to the next block. 1512 MachineBasicBlock *NextBlock = 0; 1513 MachineFunction::iterator BBI = SwitchBB; 1514 if (++BBI != FuncInfo.MF->end()) 1515 NextBlock = BBI; 1516 1517 // If the lhs block is the next block, invert the condition so that we can 1518 // fall through to the lhs instead of the rhs block. 1519 if (CB.TrueBB == NextBlock) { 1520 std::swap(CB.TrueBB, CB.FalseBB); 1521 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1522 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1523 } 1524 1525 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1526 MVT::Other, getControlRoot(), Cond, 1527 DAG.getBasicBlock(CB.TrueBB)); 1528 1529 // Insert the false branch. Do this even if it's a fall through branch, 1530 // this makes it easier to do DAG optimizations which require inverting 1531 // the branch condition. 1532 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1533 DAG.getBasicBlock(CB.FalseBB)); 1534 1535 DAG.setRoot(BrCond); 1536} 1537 1538/// visitJumpTable - Emit JumpTable node in the current MBB 1539void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1540 // Emit the code for the jump table 1541 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1542 EVT PTy = TLI.getPointerTy(); 1543 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1544 JT.Reg, PTy); 1545 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1546 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1547 MVT::Other, Index.getValue(1), 1548 Table, Index); 1549 DAG.setRoot(BrJumpTable); 1550} 1551 1552/// visitJumpTableHeader - This function emits necessary code to produce index 1553/// in the JumpTable from switch case. 1554void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1555 JumpTableHeader &JTH, 1556 MachineBasicBlock *SwitchBB) { 1557 // Subtract the lowest switch case value from the value being switched on and 1558 // conditional branch to default mbb if the result is greater than the 1559 // difference between smallest and largest cases. 1560 SDValue SwitchOp = getValue(JTH.SValue); 1561 EVT VT = SwitchOp.getValueType(); 1562 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1563 DAG.getConstant(JTH.First, VT)); 1564 1565 // The SDNode we just created, which holds the value being switched on minus 1566 // the smallest case value, needs to be copied to a virtual register so it 1567 // can be used as an index into the jump table in a subsequent basic block. 1568 // This value may be smaller or larger than the target's pointer type, and 1569 // therefore require extension or truncating. 1570 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1571 1572 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1573 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1574 JumpTableReg, SwitchOp); 1575 JT.Reg = JumpTableReg; 1576 1577 // Emit the range check for the jump table, and branch to the default block 1578 // for the switch statement if the value being switched on exceeds the largest 1579 // case in the switch. 1580 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1581 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1582 DAG.getConstant(JTH.Last-JTH.First,VT), 1583 ISD::SETUGT); 1584 1585 // Set NextBlock to be the MBB immediately after the current one, if any. 1586 // This is used to avoid emitting unnecessary branches to the next block. 1587 MachineBasicBlock *NextBlock = 0; 1588 MachineFunction::iterator BBI = SwitchBB; 1589 1590 if (++BBI != FuncInfo.MF->end()) 1591 NextBlock = BBI; 1592 1593 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1594 MVT::Other, CopyTo, CMP, 1595 DAG.getBasicBlock(JT.Default)); 1596 1597 if (JT.MBB != NextBlock) 1598 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1599 DAG.getBasicBlock(JT.MBB)); 1600 1601 DAG.setRoot(BrCond); 1602} 1603 1604/// visitBitTestHeader - This function emits necessary code to produce value 1605/// suitable for "bit tests" 1606void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1607 MachineBasicBlock *SwitchBB) { 1608 // Subtract the minimum value 1609 SDValue SwitchOp = getValue(B.SValue); 1610 EVT VT = SwitchOp.getValueType(); 1611 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1612 DAG.getConstant(B.First, VT)); 1613 1614 // Check range 1615 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1616 TLI.getSetCCResultType(Sub.getValueType()), 1617 Sub, DAG.getConstant(B.Range, VT), 1618 ISD::SETUGT); 1619 1620 // Determine the type of the test operands. 1621 bool UsePtrType = false; 1622 if (!TLI.isTypeLegal(VT)) 1623 UsePtrType = true; 1624 else { 1625 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1626 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) { 1627 // Switch table case range are encoded into series of masks. 1628 // Just use pointer type, it's guaranteed to fit. 1629 UsePtrType = true; 1630 break; 1631 } 1632 } 1633 if (UsePtrType) { 1634 VT = TLI.getPointerTy(); 1635 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1636 } 1637 1638 B.RegVT = VT; 1639 B.Reg = FuncInfo.CreateReg(VT); 1640 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1641 B.Reg, Sub); 1642 1643 // Set NextBlock to be the MBB immediately after the current one, if any. 1644 // This is used to avoid emitting unnecessary branches to the next block. 1645 MachineBasicBlock *NextBlock = 0; 1646 MachineFunction::iterator BBI = SwitchBB; 1647 if (++BBI != FuncInfo.MF->end()) 1648 NextBlock = BBI; 1649 1650 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1651 1652 SwitchBB->addSuccessor(B.Default); 1653 SwitchBB->addSuccessor(MBB); 1654 1655 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1656 MVT::Other, CopyTo, RangeCmp, 1657 DAG.getBasicBlock(B.Default)); 1658 1659 if (MBB != NextBlock) 1660 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1661 DAG.getBasicBlock(MBB)); 1662 1663 DAG.setRoot(BrRange); 1664} 1665 1666/// visitBitTestCase - this function produces one "bit test" 1667void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1668 MachineBasicBlock* NextMBB, 1669 unsigned Reg, 1670 BitTestCase &B, 1671 MachineBasicBlock *SwitchBB) { 1672 EVT VT = BB.RegVT; 1673 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1674 Reg, VT); 1675 SDValue Cmp; 1676 if (CountPopulation_64(B.Mask) == 1) { 1677 // Testing for a single bit; just compare the shift count with what it 1678 // would need to be to shift a 1 bit in that position. 1679 Cmp = DAG.getSetCC(getCurDebugLoc(), 1680 TLI.getSetCCResultType(VT), 1681 ShiftOp, 1682 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1683 ISD::SETEQ); 1684 } else { 1685 // Make desired shift 1686 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1687 DAG.getConstant(1, VT), ShiftOp); 1688 1689 // Emit bit tests and jumps 1690 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1691 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1692 Cmp = DAG.getSetCC(getCurDebugLoc(), 1693 TLI.getSetCCResultType(VT), 1694 AndOp, DAG.getConstant(0, VT), 1695 ISD::SETNE); 1696 } 1697 1698 SwitchBB->addSuccessor(B.TargetBB); 1699 SwitchBB->addSuccessor(NextMBB); 1700 1701 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1702 MVT::Other, getControlRoot(), 1703 Cmp, DAG.getBasicBlock(B.TargetBB)); 1704 1705 // Set NextBlock to be the MBB immediately after the current one, if any. 1706 // This is used to avoid emitting unnecessary branches to the next block. 1707 MachineBasicBlock *NextBlock = 0; 1708 MachineFunction::iterator BBI = SwitchBB; 1709 if (++BBI != FuncInfo.MF->end()) 1710 NextBlock = BBI; 1711 1712 if (NextMBB != NextBlock) 1713 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1714 DAG.getBasicBlock(NextMBB)); 1715 1716 DAG.setRoot(BrAnd); 1717} 1718 1719void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1720 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1721 1722 // Retrieve successors. 1723 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1724 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1725 1726 const Value *Callee(I.getCalledValue()); 1727 if (isa<InlineAsm>(Callee)) 1728 visitInlineAsm(&I); 1729 else 1730 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1731 1732 // If the value of the invoke is used outside of its defining block, make it 1733 // available as a virtual register. 1734 CopyToExportRegsIfNeeded(&I); 1735 1736 // Update successor info 1737 InvokeMBB->addSuccessor(Return); 1738 InvokeMBB->addSuccessor(LandingPad); 1739 1740 // Drop into normal successor. 1741 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1742 MVT::Other, getControlRoot(), 1743 DAG.getBasicBlock(Return))); 1744} 1745 1746void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1747} 1748 1749/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1750/// small case ranges). 1751bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1752 CaseRecVector& WorkList, 1753 const Value* SV, 1754 MachineBasicBlock *Default, 1755 MachineBasicBlock *SwitchBB) { 1756 Case& BackCase = *(CR.Range.second-1); 1757 1758 // Size is the number of Cases represented by this range. 1759 size_t Size = CR.Range.second - CR.Range.first; 1760 if (Size > 3) 1761 return false; 1762 1763 // Get the MachineFunction which holds the current MBB. This is used when 1764 // inserting any additional MBBs necessary to represent the switch. 1765 MachineFunction *CurMF = FuncInfo.MF; 1766 1767 // Figure out which block is immediately after the current one. 1768 MachineBasicBlock *NextBlock = 0; 1769 MachineFunction::iterator BBI = CR.CaseBB; 1770 1771 if (++BBI != FuncInfo.MF->end()) 1772 NextBlock = BBI; 1773 1774 // If any two of the cases has the same destination, and if one value 1775 // is the same as the other, but has one bit unset that the other has set, 1776 // use bit manipulation to do two compares at once. For example: 1777 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1778 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1779 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1780 if (Size == 2 && CR.CaseBB == SwitchBB) { 1781 Case &Small = *CR.Range.first; 1782 Case &Big = *(CR.Range.second-1); 1783 1784 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1785 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1786 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1787 1788 // Check that there is only one bit different. 1789 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1790 (SmallValue | BigValue) == BigValue) { 1791 // Isolate the common bit. 1792 APInt CommonBit = BigValue & ~SmallValue; 1793 assert((SmallValue | CommonBit) == BigValue && 1794 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1795 1796 SDValue CondLHS = getValue(SV); 1797 EVT VT = CondLHS.getValueType(); 1798 DebugLoc DL = getCurDebugLoc(); 1799 1800 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1801 DAG.getConstant(CommonBit, VT)); 1802 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1803 Or, DAG.getConstant(BigValue, VT), 1804 ISD::SETEQ); 1805 1806 // Update successor info. 1807 SwitchBB->addSuccessor(Small.BB); 1808 SwitchBB->addSuccessor(Default); 1809 1810 // Insert the true branch. 1811 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1812 getControlRoot(), Cond, 1813 DAG.getBasicBlock(Small.BB)); 1814 1815 // Insert the false branch. 1816 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1817 DAG.getBasicBlock(Default)); 1818 1819 DAG.setRoot(BrCond); 1820 return true; 1821 } 1822 } 1823 } 1824 1825 // Rearrange the case blocks so that the last one falls through if possible. 1826 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1827 // The last case block won't fall through into 'NextBlock' if we emit the 1828 // branches in this order. See if rearranging a case value would help. 1829 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1830 if (I->BB == NextBlock) { 1831 std::swap(*I, BackCase); 1832 break; 1833 } 1834 } 1835 } 1836 1837 // Create a CaseBlock record representing a conditional branch to 1838 // the Case's target mbb if the value being switched on SV is equal 1839 // to C. 1840 MachineBasicBlock *CurBlock = CR.CaseBB; 1841 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1842 MachineBasicBlock *FallThrough; 1843 if (I != E-1) { 1844 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1845 CurMF->insert(BBI, FallThrough); 1846 1847 // Put SV in a virtual register to make it available from the new blocks. 1848 ExportFromCurrentBlock(SV); 1849 } else { 1850 // If the last case doesn't match, go to the default block. 1851 FallThrough = Default; 1852 } 1853 1854 const Value *RHS, *LHS, *MHS; 1855 ISD::CondCode CC; 1856 if (I->High == I->Low) { 1857 // This is just small small case range :) containing exactly 1 case 1858 CC = ISD::SETEQ; 1859 LHS = SV; RHS = I->High; MHS = NULL; 1860 } else { 1861 CC = ISD::SETLE; 1862 LHS = I->Low; MHS = SV; RHS = I->High; 1863 } 1864 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1865 1866 // If emitting the first comparison, just call visitSwitchCase to emit the 1867 // code into the current block. Otherwise, push the CaseBlock onto the 1868 // vector to be later processed by SDISel, and insert the node's MBB 1869 // before the next MBB. 1870 if (CurBlock == SwitchBB) 1871 visitSwitchCase(CB, SwitchBB); 1872 else 1873 SwitchCases.push_back(CB); 1874 1875 CurBlock = FallThrough; 1876 } 1877 1878 return true; 1879} 1880 1881static inline bool areJTsAllowed(const TargetLowering &TLI) { 1882 return !DisableJumpTables && 1883 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1884 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1885} 1886 1887static APInt ComputeRange(const APInt &First, const APInt &Last) { 1888 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1889 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 1890 return (LastExt - FirstExt + 1ULL); 1891} 1892 1893/// handleJTSwitchCase - Emit jumptable for current switch case range 1894bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1895 CaseRecVector& WorkList, 1896 const Value* SV, 1897 MachineBasicBlock* Default, 1898 MachineBasicBlock *SwitchBB) { 1899 Case& FrontCase = *CR.Range.first; 1900 Case& BackCase = *(CR.Range.second-1); 1901 1902 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1903 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1904 1905 APInt TSize(First.getBitWidth(), 0); 1906 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1907 I!=E; ++I) 1908 TSize += I->size(); 1909 1910 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1911 return false; 1912 1913 APInt Range = ComputeRange(First, Last); 1914 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1915 if (Density < 0.4) 1916 return false; 1917 1918 DEBUG(dbgs() << "Lowering jump table\n" 1919 << "First entry: " << First << ". Last entry: " << Last << '\n' 1920 << "Range: " << Range 1921 << "Size: " << TSize << ". Density: " << Density << "\n\n"); 1922 1923 // Get the MachineFunction which holds the current MBB. This is used when 1924 // inserting any additional MBBs necessary to represent the switch. 1925 MachineFunction *CurMF = FuncInfo.MF; 1926 1927 // Figure out which block is immediately after the current one. 1928 MachineFunction::iterator BBI = CR.CaseBB; 1929 ++BBI; 1930 1931 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1932 1933 // Create a new basic block to hold the code for loading the address 1934 // of the jump table, and jumping to it. Update successor information; 1935 // we will either branch to the default case for the switch, or the jump 1936 // table. 1937 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1938 CurMF->insert(BBI, JumpTableBB); 1939 CR.CaseBB->addSuccessor(Default); 1940 CR.CaseBB->addSuccessor(JumpTableBB); 1941 1942 // Build a vector of destination BBs, corresponding to each target 1943 // of the jump table. If the value of the jump table slot corresponds to 1944 // a case statement, push the case's BB onto the vector, otherwise, push 1945 // the default BB. 1946 std::vector<MachineBasicBlock*> DestBBs; 1947 APInt TEI = First; 1948 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1949 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 1950 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 1951 1952 if (Low.sle(TEI) && TEI.sle(High)) { 1953 DestBBs.push_back(I->BB); 1954 if (TEI==High) 1955 ++I; 1956 } else { 1957 DestBBs.push_back(Default); 1958 } 1959 } 1960 1961 // Update successor info. Add one edge to each unique successor. 1962 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1963 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1964 E = DestBBs.end(); I != E; ++I) { 1965 if (!SuccsHandled[(*I)->getNumber()]) { 1966 SuccsHandled[(*I)->getNumber()] = true; 1967 JumpTableBB->addSuccessor(*I); 1968 } 1969 } 1970 1971 // Create a jump table index for this jump table. 1972 unsigned JTEncoding = TLI.getJumpTableEncoding(); 1973 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 1974 ->createJumpTableIndex(DestBBs); 1975 1976 // Set the jump table information so that we can codegen it as a second 1977 // MachineBasicBlock 1978 JumpTable JT(-1U, JTI, JumpTableBB, Default); 1979 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 1980 if (CR.CaseBB == SwitchBB) 1981 visitJumpTableHeader(JT, JTH, SwitchBB); 1982 1983 JTCases.push_back(JumpTableBlock(JTH, JT)); 1984 1985 return true; 1986} 1987 1988/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1989/// 2 subtrees. 1990bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 1991 CaseRecVector& WorkList, 1992 const Value* SV, 1993 MachineBasicBlock *Default, 1994 MachineBasicBlock *SwitchBB) { 1995 // Get the MachineFunction which holds the current MBB. This is used when 1996 // inserting any additional MBBs necessary to represent the switch. 1997 MachineFunction *CurMF = FuncInfo.MF; 1998 1999 // Figure out which block is immediately after the current one. 2000 MachineFunction::iterator BBI = CR.CaseBB; 2001 ++BBI; 2002 2003 Case& FrontCase = *CR.Range.first; 2004 Case& BackCase = *(CR.Range.second-1); 2005 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2006 2007 // Size is the number of Cases represented by this range. 2008 unsigned Size = CR.Range.second - CR.Range.first; 2009 2010 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2011 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2012 double FMetric = 0; 2013 CaseItr Pivot = CR.Range.first + Size/2; 2014 2015 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2016 // (heuristically) allow us to emit JumpTable's later. 2017 APInt TSize(First.getBitWidth(), 0); 2018 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2019 I!=E; ++I) 2020 TSize += I->size(); 2021 2022 APInt LSize = FrontCase.size(); 2023 APInt RSize = TSize-LSize; 2024 DEBUG(dbgs() << "Selecting best pivot: \n" 2025 << "First: " << First << ", Last: " << Last <<'\n' 2026 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2027 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2028 J!=E; ++I, ++J) { 2029 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2030 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2031 APInt Range = ComputeRange(LEnd, RBegin); 2032 assert((Range - 2ULL).isNonNegative() && 2033 "Invalid case distance"); 2034 double LDensity = (double)LSize.roundToDouble() / 2035 (LEnd - First + 1ULL).roundToDouble(); 2036 double RDensity = (double)RSize.roundToDouble() / 2037 (Last - RBegin + 1ULL).roundToDouble(); 2038 double Metric = Range.logBase2()*(LDensity+RDensity); 2039 // Should always split in some non-trivial place 2040 DEBUG(dbgs() <<"=>Step\n" 2041 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2042 << "LDensity: " << LDensity 2043 << ", RDensity: " << RDensity << '\n' 2044 << "Metric: " << Metric << '\n'); 2045 if (FMetric < Metric) { 2046 Pivot = J; 2047 FMetric = Metric; 2048 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2049 } 2050 2051 LSize += J->size(); 2052 RSize -= J->size(); 2053 } 2054 if (areJTsAllowed(TLI)) { 2055 // If our case is dense we *really* should handle it earlier! 2056 assert((FMetric > 0) && "Should handle dense range earlier!"); 2057 } else { 2058 Pivot = CR.Range.first + Size/2; 2059 } 2060 2061 CaseRange LHSR(CR.Range.first, Pivot); 2062 CaseRange RHSR(Pivot, CR.Range.second); 2063 Constant *C = Pivot->Low; 2064 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2065 2066 // We know that we branch to the LHS if the Value being switched on is 2067 // less than the Pivot value, C. We use this to optimize our binary 2068 // tree a bit, by recognizing that if SV is greater than or equal to the 2069 // LHS's Case Value, and that Case Value is exactly one less than the 2070 // Pivot's Value, then we can branch directly to the LHS's Target, 2071 // rather than creating a leaf node for it. 2072 if ((LHSR.second - LHSR.first) == 1 && 2073 LHSR.first->High == CR.GE && 2074 cast<ConstantInt>(C)->getValue() == 2075 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2076 TrueBB = LHSR.first->BB; 2077 } else { 2078 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2079 CurMF->insert(BBI, TrueBB); 2080 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2081 2082 // Put SV in a virtual register to make it available from the new blocks. 2083 ExportFromCurrentBlock(SV); 2084 } 2085 2086 // Similar to the optimization above, if the Value being switched on is 2087 // known to be less than the Constant CR.LT, and the current Case Value 2088 // is CR.LT - 1, then we can branch directly to the target block for 2089 // the current Case Value, rather than emitting a RHS leaf node for it. 2090 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2091 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2092 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2093 FalseBB = RHSR.first->BB; 2094 } else { 2095 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2096 CurMF->insert(BBI, FalseBB); 2097 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2098 2099 // Put SV in a virtual register to make it available from the new blocks. 2100 ExportFromCurrentBlock(SV); 2101 } 2102 2103 // Create a CaseBlock record representing a conditional branch to 2104 // the LHS node if the value being switched on SV is less than C. 2105 // Otherwise, branch to LHS. 2106 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2107 2108 if (CR.CaseBB == SwitchBB) 2109 visitSwitchCase(CB, SwitchBB); 2110 else 2111 SwitchCases.push_back(CB); 2112 2113 return true; 2114} 2115 2116/// handleBitTestsSwitchCase - if current case range has few destination and 2117/// range span less, than machine word bitwidth, encode case range into series 2118/// of masks and emit bit tests with these masks. 2119bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2120 CaseRecVector& WorkList, 2121 const Value* SV, 2122 MachineBasicBlock* Default, 2123 MachineBasicBlock *SwitchBB){ 2124 EVT PTy = TLI.getPointerTy(); 2125 unsigned IntPtrBits = PTy.getSizeInBits(); 2126 2127 Case& FrontCase = *CR.Range.first; 2128 Case& BackCase = *(CR.Range.second-1); 2129 2130 // Get the MachineFunction which holds the current MBB. This is used when 2131 // inserting any additional MBBs necessary to represent the switch. 2132 MachineFunction *CurMF = FuncInfo.MF; 2133 2134 // If target does not have legal shift left, do not emit bit tests at all. 2135 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2136 return false; 2137 2138 size_t numCmps = 0; 2139 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2140 I!=E; ++I) { 2141 // Single case counts one, case range - two. 2142 numCmps += (I->Low == I->High ? 1 : 2); 2143 } 2144 2145 // Count unique destinations 2146 SmallSet<MachineBasicBlock*, 4> Dests; 2147 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2148 Dests.insert(I->BB); 2149 if (Dests.size() > 3) 2150 // Don't bother the code below, if there are too much unique destinations 2151 return false; 2152 } 2153 DEBUG(dbgs() << "Total number of unique destinations: " 2154 << Dests.size() << '\n' 2155 << "Total number of comparisons: " << numCmps << '\n'); 2156 2157 // Compute span of values. 2158 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2159 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2160 APInt cmpRange = maxValue - minValue; 2161 2162 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2163 << "Low bound: " << minValue << '\n' 2164 << "High bound: " << maxValue << '\n'); 2165 2166 if (cmpRange.uge(IntPtrBits) || 2167 (!(Dests.size() == 1 && numCmps >= 3) && 2168 !(Dests.size() == 2 && numCmps >= 5) && 2169 !(Dests.size() >= 3 && numCmps >= 6))) 2170 return false; 2171 2172 DEBUG(dbgs() << "Emitting bit tests\n"); 2173 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2174 2175 // Optimize the case where all the case values fit in a 2176 // word without having to subtract minValue. In this case, 2177 // we can optimize away the subtraction. 2178 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2179 cmpRange = maxValue; 2180 } else { 2181 lowBound = minValue; 2182 } 2183 2184 CaseBitsVector CasesBits; 2185 unsigned i, count = 0; 2186 2187 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2188 MachineBasicBlock* Dest = I->BB; 2189 for (i = 0; i < count; ++i) 2190 if (Dest == CasesBits[i].BB) 2191 break; 2192 2193 if (i == count) { 2194 assert((count < 3) && "Too much destinations to test!"); 2195 CasesBits.push_back(CaseBits(0, Dest, 0)); 2196 count++; 2197 } 2198 2199 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2200 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2201 2202 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2203 uint64_t hi = (highValue - lowBound).getZExtValue(); 2204 2205 for (uint64_t j = lo; j <= hi; j++) { 2206 CasesBits[i].Mask |= 1ULL << j; 2207 CasesBits[i].Bits++; 2208 } 2209 2210 } 2211 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2212 2213 BitTestInfo BTC; 2214 2215 // Figure out which block is immediately after the current one. 2216 MachineFunction::iterator BBI = CR.CaseBB; 2217 ++BBI; 2218 2219 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2220 2221 DEBUG(dbgs() << "Cases:\n"); 2222 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2223 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2224 << ", Bits: " << CasesBits[i].Bits 2225 << ", BB: " << CasesBits[i].BB << '\n'); 2226 2227 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2228 CurMF->insert(BBI, CaseBB); 2229 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2230 CaseBB, 2231 CasesBits[i].BB)); 2232 2233 // Put SV in a virtual register to make it available from the new blocks. 2234 ExportFromCurrentBlock(SV); 2235 } 2236 2237 BitTestBlock BTB(lowBound, cmpRange, SV, 2238 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2239 CR.CaseBB, Default, BTC); 2240 2241 if (CR.CaseBB == SwitchBB) 2242 visitBitTestHeader(BTB, SwitchBB); 2243 2244 BitTestCases.push_back(BTB); 2245 2246 return true; 2247} 2248 2249/// Clusterify - Transform simple list of Cases into list of CaseRange's 2250size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2251 const SwitchInst& SI) { 2252 size_t numCmps = 0; 2253 2254 // Start with "simple" cases 2255 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2256 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2257 Cases.push_back(Case(SI.getSuccessorValue(i), 2258 SI.getSuccessorValue(i), 2259 SMBB)); 2260 } 2261 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2262 2263 // Merge case into clusters 2264 if (Cases.size() >= 2) 2265 // Must recompute end() each iteration because it may be 2266 // invalidated by erase if we hold on to it 2267 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2268 J != Cases.end(); ) { 2269 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2270 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2271 MachineBasicBlock* nextBB = J->BB; 2272 MachineBasicBlock* currentBB = I->BB; 2273 2274 // If the two neighboring cases go to the same destination, merge them 2275 // into a single case. 2276 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2277 I->High = J->High; 2278 J = Cases.erase(J); 2279 } else { 2280 I = J++; 2281 } 2282 } 2283 2284 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2285 if (I->Low != I->High) 2286 // A range counts double, since it requires two compares. 2287 ++numCmps; 2288 } 2289 2290 return numCmps; 2291} 2292 2293void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2294 MachineBasicBlock *Last) { 2295 // Update JTCases. 2296 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2297 if (JTCases[i].first.HeaderBB == First) 2298 JTCases[i].first.HeaderBB = Last; 2299 2300 // Update BitTestCases. 2301 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2302 if (BitTestCases[i].Parent == First) 2303 BitTestCases[i].Parent = Last; 2304} 2305 2306void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2307 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2308 2309 // Figure out which block is immediately after the current one. 2310 MachineBasicBlock *NextBlock = 0; 2311 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2312 2313 // If there is only the default destination, branch to it if it is not the 2314 // next basic block. Otherwise, just fall through. 2315 if (SI.getNumOperands() == 2) { 2316 // Update machine-CFG edges. 2317 2318 // If this is not a fall-through branch, emit the branch. 2319 SwitchMBB->addSuccessor(Default); 2320 if (Default != NextBlock) 2321 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2322 MVT::Other, getControlRoot(), 2323 DAG.getBasicBlock(Default))); 2324 2325 return; 2326 } 2327 2328 // If there are any non-default case statements, create a vector of Cases 2329 // representing each one, and sort the vector so that we can efficiently 2330 // create a binary search tree from them. 2331 CaseVector Cases; 2332 size_t numCmps = Clusterify(Cases, SI); 2333 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2334 << ". Total compares: " << numCmps << '\n'); 2335 numCmps = 0; 2336 2337 // Get the Value to be switched on and default basic blocks, which will be 2338 // inserted into CaseBlock records, representing basic blocks in the binary 2339 // search tree. 2340 const Value *SV = SI.getOperand(0); 2341 2342 // Push the initial CaseRec onto the worklist 2343 CaseRecVector WorkList; 2344 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2345 CaseRange(Cases.begin(),Cases.end()))); 2346 2347 while (!WorkList.empty()) { 2348 // Grab a record representing a case range to process off the worklist 2349 CaseRec CR = WorkList.back(); 2350 WorkList.pop_back(); 2351 2352 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2353 continue; 2354 2355 // If the range has few cases (two or less) emit a series of specific 2356 // tests. 2357 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2358 continue; 2359 2360 // If the switch has more than 5 blocks, and at least 40% dense, and the 2361 // target supports indirect branches, then emit a jump table rather than 2362 // lowering the switch to a binary tree of conditional branches. 2363 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2364 continue; 2365 2366 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2367 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2368 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2369 } 2370} 2371 2372void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2373 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2374 2375 // Update machine-CFG edges with unique successors. 2376 SmallVector<BasicBlock*, 32> succs; 2377 succs.reserve(I.getNumSuccessors()); 2378 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2379 succs.push_back(I.getSuccessor(i)); 2380 array_pod_sort(succs.begin(), succs.end()); 2381 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2382 for (unsigned i = 0, e = succs.size(); i != e; ++i) 2383 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]); 2384 2385 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2386 MVT::Other, getControlRoot(), 2387 getValue(I.getAddress()))); 2388} 2389 2390void SelectionDAGBuilder::visitFSub(const User &I) { 2391 // -0.0 - X --> fneg 2392 const Type *Ty = I.getType(); 2393 if (isa<Constant>(I.getOperand(0)) && 2394 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2395 SDValue Op2 = getValue(I.getOperand(1)); 2396 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2397 Op2.getValueType(), Op2)); 2398 return; 2399 } 2400 2401 visitBinary(I, ISD::FSUB); 2402} 2403 2404void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2405 SDValue Op1 = getValue(I.getOperand(0)); 2406 SDValue Op2 = getValue(I.getOperand(1)); 2407 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2408 Op1.getValueType(), Op1, Op2)); 2409} 2410 2411void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2412 SDValue Op1 = getValue(I.getOperand(0)); 2413 SDValue Op2 = getValue(I.getOperand(1)); 2414 2415 MVT ShiftTy = TLI.getShiftAmountTy(); 2416 2417 // Coerce the shift amount to the right type if we can. 2418 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2419 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2420 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2421 DebugLoc DL = getCurDebugLoc(); 2422 2423 // If the operand is smaller than the shift count type, promote it. 2424 if (ShiftSize > Op2Size) 2425 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2426 2427 // If the operand is larger than the shift count type but the shift 2428 // count type has enough bits to represent any shift value, truncate 2429 // it now. This is a common case and it exposes the truncate to 2430 // optimization early. 2431 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2432 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2433 // Otherwise we'll need to temporarily settle for some other convenient 2434 // type. Type legalization will make adjustments once the shiftee is split. 2435 else 2436 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2437 } 2438 2439 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2440 Op1.getValueType(), Op1, Op2)); 2441} 2442 2443void SelectionDAGBuilder::visitICmp(const User &I) { 2444 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2445 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2446 predicate = IC->getPredicate(); 2447 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2448 predicate = ICmpInst::Predicate(IC->getPredicate()); 2449 SDValue Op1 = getValue(I.getOperand(0)); 2450 SDValue Op2 = getValue(I.getOperand(1)); 2451 ISD::CondCode Opcode = getICmpCondCode(predicate); 2452 2453 EVT DestVT = TLI.getValueType(I.getType()); 2454 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2455} 2456 2457void SelectionDAGBuilder::visitFCmp(const User &I) { 2458 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2459 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2460 predicate = FC->getPredicate(); 2461 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2462 predicate = FCmpInst::Predicate(FC->getPredicate()); 2463 SDValue Op1 = getValue(I.getOperand(0)); 2464 SDValue Op2 = getValue(I.getOperand(1)); 2465 ISD::CondCode Condition = getFCmpCondCode(predicate); 2466 EVT DestVT = TLI.getValueType(I.getType()); 2467 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2468} 2469 2470void SelectionDAGBuilder::visitSelect(const User &I) { 2471 SmallVector<EVT, 4> ValueVTs; 2472 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2473 unsigned NumValues = ValueVTs.size(); 2474 if (NumValues == 0) return; 2475 2476 SmallVector<SDValue, 4> Values(NumValues); 2477 SDValue Cond = getValue(I.getOperand(0)); 2478 SDValue TrueVal = getValue(I.getOperand(1)); 2479 SDValue FalseVal = getValue(I.getOperand(2)); 2480 2481 for (unsigned i = 0; i != NumValues; ++i) 2482 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2483 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2484 Cond, 2485 SDValue(TrueVal.getNode(), 2486 TrueVal.getResNo() + i), 2487 SDValue(FalseVal.getNode(), 2488 FalseVal.getResNo() + i)); 2489 2490 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2491 DAG.getVTList(&ValueVTs[0], NumValues), 2492 &Values[0], NumValues)); 2493} 2494 2495void SelectionDAGBuilder::visitTrunc(const User &I) { 2496 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2497 SDValue N = getValue(I.getOperand(0)); 2498 EVT DestVT = TLI.getValueType(I.getType()); 2499 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2500} 2501 2502void SelectionDAGBuilder::visitZExt(const User &I) { 2503 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2504 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2505 SDValue N = getValue(I.getOperand(0)); 2506 EVT DestVT = TLI.getValueType(I.getType()); 2507 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2508} 2509 2510void SelectionDAGBuilder::visitSExt(const User &I) { 2511 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2512 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2513 SDValue N = getValue(I.getOperand(0)); 2514 EVT DestVT = TLI.getValueType(I.getType()); 2515 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2516} 2517 2518void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2519 // FPTrunc is never a no-op cast, no need to check 2520 SDValue N = getValue(I.getOperand(0)); 2521 EVT DestVT = TLI.getValueType(I.getType()); 2522 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2523 DestVT, N, DAG.getIntPtrConstant(0))); 2524} 2525 2526void SelectionDAGBuilder::visitFPExt(const User &I){ 2527 // FPTrunc is never a no-op cast, no need to check 2528 SDValue N = getValue(I.getOperand(0)); 2529 EVT DestVT = TLI.getValueType(I.getType()); 2530 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2531} 2532 2533void SelectionDAGBuilder::visitFPToUI(const User &I) { 2534 // FPToUI is never a no-op cast, no need to check 2535 SDValue N = getValue(I.getOperand(0)); 2536 EVT DestVT = TLI.getValueType(I.getType()); 2537 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2538} 2539 2540void SelectionDAGBuilder::visitFPToSI(const User &I) { 2541 // FPToSI is never a no-op cast, no need to check 2542 SDValue N = getValue(I.getOperand(0)); 2543 EVT DestVT = TLI.getValueType(I.getType()); 2544 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2545} 2546 2547void SelectionDAGBuilder::visitUIToFP(const User &I) { 2548 // UIToFP is never a no-op cast, no need to check 2549 SDValue N = getValue(I.getOperand(0)); 2550 EVT DestVT = TLI.getValueType(I.getType()); 2551 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2552} 2553 2554void SelectionDAGBuilder::visitSIToFP(const User &I){ 2555 // SIToFP is never a no-op cast, no need to check 2556 SDValue N = getValue(I.getOperand(0)); 2557 EVT DestVT = TLI.getValueType(I.getType()); 2558 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2559} 2560 2561void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2562 // What to do depends on the size of the integer and the size of the pointer. 2563 // We can either truncate, zero extend, or no-op, accordingly. 2564 SDValue N = getValue(I.getOperand(0)); 2565 EVT DestVT = TLI.getValueType(I.getType()); 2566 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2567} 2568 2569void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2570 // What to do depends on the size of the integer and the size of the pointer. 2571 // We can either truncate, zero extend, or no-op, accordingly. 2572 SDValue N = getValue(I.getOperand(0)); 2573 EVT DestVT = TLI.getValueType(I.getType()); 2574 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2575} 2576 2577void SelectionDAGBuilder::visitBitCast(const User &I) { 2578 SDValue N = getValue(I.getOperand(0)); 2579 EVT DestVT = TLI.getValueType(I.getType()); 2580 2581 // BitCast assures us that source and destination are the same size so this is 2582 // either a BITCAST or a no-op. 2583 if (DestVT != N.getValueType()) 2584 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2585 DestVT, N)); // convert types. 2586 else 2587 setValue(&I, N); // noop cast. 2588} 2589 2590void SelectionDAGBuilder::visitInsertElement(const User &I) { 2591 SDValue InVec = getValue(I.getOperand(0)); 2592 SDValue InVal = getValue(I.getOperand(1)); 2593 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2594 TLI.getPointerTy(), 2595 getValue(I.getOperand(2))); 2596 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2597 TLI.getValueType(I.getType()), 2598 InVec, InVal, InIdx)); 2599} 2600 2601void SelectionDAGBuilder::visitExtractElement(const User &I) { 2602 SDValue InVec = getValue(I.getOperand(0)); 2603 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2604 TLI.getPointerTy(), 2605 getValue(I.getOperand(1))); 2606 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2607 TLI.getValueType(I.getType()), InVec, InIdx)); 2608} 2609 2610// Utility for visitShuffleVector - Returns true if the mask is mask starting 2611// from SIndx and increasing to the element length (undefs are allowed). 2612static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2613 unsigned MaskNumElts = Mask.size(); 2614 for (unsigned i = 0; i != MaskNumElts; ++i) 2615 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2616 return false; 2617 return true; 2618} 2619 2620void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2621 SmallVector<int, 8> Mask; 2622 SDValue Src1 = getValue(I.getOperand(0)); 2623 SDValue Src2 = getValue(I.getOperand(1)); 2624 2625 // Convert the ConstantVector mask operand into an array of ints, with -1 2626 // representing undef values. 2627 SmallVector<Constant*, 8> MaskElts; 2628 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2629 unsigned MaskNumElts = MaskElts.size(); 2630 for (unsigned i = 0; i != MaskNumElts; ++i) { 2631 if (isa<UndefValue>(MaskElts[i])) 2632 Mask.push_back(-1); 2633 else 2634 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2635 } 2636 2637 EVT VT = TLI.getValueType(I.getType()); 2638 EVT SrcVT = Src1.getValueType(); 2639 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2640 2641 if (SrcNumElts == MaskNumElts) { 2642 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2643 &Mask[0])); 2644 return; 2645 } 2646 2647 // Normalize the shuffle vector since mask and vector length don't match. 2648 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2649 // Mask is longer than the source vectors and is a multiple of the source 2650 // vectors. We can use concatenate vector to make the mask and vectors 2651 // lengths match. 2652 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2653 // The shuffle is concatenating two vectors together. 2654 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2655 VT, Src1, Src2)); 2656 return; 2657 } 2658 2659 // Pad both vectors with undefs to make them the same length as the mask. 2660 unsigned NumConcat = MaskNumElts / SrcNumElts; 2661 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2662 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2663 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2664 2665 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2666 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2667 MOps1[0] = Src1; 2668 MOps2[0] = Src2; 2669 2670 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2671 getCurDebugLoc(), VT, 2672 &MOps1[0], NumConcat); 2673 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2674 getCurDebugLoc(), VT, 2675 &MOps2[0], NumConcat); 2676 2677 // Readjust mask for new input vector length. 2678 SmallVector<int, 8> MappedOps; 2679 for (unsigned i = 0; i != MaskNumElts; ++i) { 2680 int Idx = Mask[i]; 2681 if (Idx < (int)SrcNumElts) 2682 MappedOps.push_back(Idx); 2683 else 2684 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2685 } 2686 2687 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2688 &MappedOps[0])); 2689 return; 2690 } 2691 2692 if (SrcNumElts > MaskNumElts) { 2693 // Analyze the access pattern of the vector to see if we can extract 2694 // two subvectors and do the shuffle. The analysis is done by calculating 2695 // the range of elements the mask access on both vectors. 2696 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2697 int MaxRange[2] = {-1, -1}; 2698 2699 for (unsigned i = 0; i != MaskNumElts; ++i) { 2700 int Idx = Mask[i]; 2701 int Input = 0; 2702 if (Idx < 0) 2703 continue; 2704 2705 if (Idx >= (int)SrcNumElts) { 2706 Input = 1; 2707 Idx -= SrcNumElts; 2708 } 2709 if (Idx > MaxRange[Input]) 2710 MaxRange[Input] = Idx; 2711 if (Idx < MinRange[Input]) 2712 MinRange[Input] = Idx; 2713 } 2714 2715 // Check if the access is smaller than the vector size and can we find 2716 // a reasonable extract index. 2717 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2718 // Extract. 2719 int StartIdx[2]; // StartIdx to extract from 2720 for (int Input=0; Input < 2; ++Input) { 2721 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2722 RangeUse[Input] = 0; // Unused 2723 StartIdx[Input] = 0; 2724 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2725 // Fits within range but we should see if we can find a good 2726 // start index that is a multiple of the mask length. 2727 if (MaxRange[Input] < (int)MaskNumElts) { 2728 RangeUse[Input] = 1; // Extract from beginning of the vector 2729 StartIdx[Input] = 0; 2730 } else { 2731 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2732 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2733 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2734 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2735 } 2736 } 2737 } 2738 2739 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2740 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2741 return; 2742 } 2743 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2744 // Extract appropriate subvector and generate a vector shuffle 2745 for (int Input=0; Input < 2; ++Input) { 2746 SDValue &Src = Input == 0 ? Src1 : Src2; 2747 if (RangeUse[Input] == 0) 2748 Src = DAG.getUNDEF(VT); 2749 else 2750 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2751 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2752 } 2753 2754 // Calculate new mask. 2755 SmallVector<int, 8> MappedOps; 2756 for (unsigned i = 0; i != MaskNumElts; ++i) { 2757 int Idx = Mask[i]; 2758 if (Idx < 0) 2759 MappedOps.push_back(Idx); 2760 else if (Idx < (int)SrcNumElts) 2761 MappedOps.push_back(Idx - StartIdx[0]); 2762 else 2763 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2764 } 2765 2766 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2767 &MappedOps[0])); 2768 return; 2769 } 2770 } 2771 2772 // We can't use either concat vectors or extract subvectors so fall back to 2773 // replacing the shuffle with extract and build vector. 2774 // to insert and build vector. 2775 EVT EltVT = VT.getVectorElementType(); 2776 EVT PtrVT = TLI.getPointerTy(); 2777 SmallVector<SDValue,8> Ops; 2778 for (unsigned i = 0; i != MaskNumElts; ++i) { 2779 if (Mask[i] < 0) { 2780 Ops.push_back(DAG.getUNDEF(EltVT)); 2781 } else { 2782 int Idx = Mask[i]; 2783 SDValue Res; 2784 2785 if (Idx < (int)SrcNumElts) 2786 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2787 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2788 else 2789 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2790 EltVT, Src2, 2791 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2792 2793 Ops.push_back(Res); 2794 } 2795 } 2796 2797 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2798 VT, &Ops[0], Ops.size())); 2799} 2800 2801void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2802 const Value *Op0 = I.getOperand(0); 2803 const Value *Op1 = I.getOperand(1); 2804 const Type *AggTy = I.getType(); 2805 const Type *ValTy = Op1->getType(); 2806 bool IntoUndef = isa<UndefValue>(Op0); 2807 bool FromUndef = isa<UndefValue>(Op1); 2808 2809 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2810 2811 SmallVector<EVT, 4> AggValueVTs; 2812 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2813 SmallVector<EVT, 4> ValValueVTs; 2814 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2815 2816 unsigned NumAggValues = AggValueVTs.size(); 2817 unsigned NumValValues = ValValueVTs.size(); 2818 SmallVector<SDValue, 4> Values(NumAggValues); 2819 2820 SDValue Agg = getValue(Op0); 2821 SDValue Val = getValue(Op1); 2822 unsigned i = 0; 2823 // Copy the beginning value(s) from the original aggregate. 2824 for (; i != LinearIndex; ++i) 2825 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2826 SDValue(Agg.getNode(), Agg.getResNo() + i); 2827 // Copy values from the inserted value(s). 2828 for (; i != LinearIndex + NumValValues; ++i) 2829 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2830 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2831 // Copy remaining value(s) from the original aggregate. 2832 for (; i != NumAggValues; ++i) 2833 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2834 SDValue(Agg.getNode(), Agg.getResNo() + i); 2835 2836 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2837 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2838 &Values[0], NumAggValues)); 2839} 2840 2841void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2842 const Value *Op0 = I.getOperand(0); 2843 const Type *AggTy = Op0->getType(); 2844 const Type *ValTy = I.getType(); 2845 bool OutOfUndef = isa<UndefValue>(Op0); 2846 2847 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2848 2849 SmallVector<EVT, 4> ValValueVTs; 2850 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2851 2852 unsigned NumValValues = ValValueVTs.size(); 2853 SmallVector<SDValue, 4> Values(NumValValues); 2854 2855 SDValue Agg = getValue(Op0); 2856 // Copy out the selected value(s). 2857 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2858 Values[i - LinearIndex] = 2859 OutOfUndef ? 2860 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2861 SDValue(Agg.getNode(), Agg.getResNo() + i); 2862 2863 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2864 DAG.getVTList(&ValValueVTs[0], NumValValues), 2865 &Values[0], NumValValues)); 2866} 2867 2868void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2869 SDValue N = getValue(I.getOperand(0)); 2870 const Type *Ty = I.getOperand(0)->getType(); 2871 2872 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2873 OI != E; ++OI) { 2874 const Value *Idx = *OI; 2875 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2876 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2877 if (Field) { 2878 // N = N + Offset 2879 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2880 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2881 DAG.getIntPtrConstant(Offset)); 2882 } 2883 2884 Ty = StTy->getElementType(Field); 2885 } else { 2886 Ty = cast<SequentialType>(Ty)->getElementType(); 2887 2888 // If this is a constant subscript, handle it quickly. 2889 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2890 if (CI->isZero()) continue; 2891 uint64_t Offs = 2892 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2893 SDValue OffsVal; 2894 EVT PTy = TLI.getPointerTy(); 2895 unsigned PtrBits = PTy.getSizeInBits(); 2896 if (PtrBits < 64) 2897 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2898 TLI.getPointerTy(), 2899 DAG.getConstant(Offs, MVT::i64)); 2900 else 2901 OffsVal = DAG.getIntPtrConstant(Offs); 2902 2903 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2904 OffsVal); 2905 continue; 2906 } 2907 2908 // N = N + Idx * ElementSize; 2909 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2910 TD->getTypeAllocSize(Ty)); 2911 SDValue IdxN = getValue(Idx); 2912 2913 // If the index is smaller or larger than intptr_t, truncate or extend 2914 // it. 2915 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2916 2917 // If this is a multiply by a power of two, turn it into a shl 2918 // immediately. This is a very common case. 2919 if (ElementSize != 1) { 2920 if (ElementSize.isPowerOf2()) { 2921 unsigned Amt = ElementSize.logBase2(); 2922 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2923 N.getValueType(), IdxN, 2924 DAG.getConstant(Amt, TLI.getPointerTy())); 2925 } else { 2926 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2927 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2928 N.getValueType(), IdxN, Scale); 2929 } 2930 } 2931 2932 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2933 N.getValueType(), N, IdxN); 2934 } 2935 } 2936 2937 setValue(&I, N); 2938} 2939 2940void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 2941 // If this is a fixed sized alloca in the entry block of the function, 2942 // allocate it statically on the stack. 2943 if (FuncInfo.StaticAllocaMap.count(&I)) 2944 return; // getValue will auto-populate this. 2945 2946 const Type *Ty = I.getAllocatedType(); 2947 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 2948 unsigned Align = 2949 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2950 I.getAlignment()); 2951 2952 SDValue AllocSize = getValue(I.getArraySize()); 2953 2954 EVT IntPtr = TLI.getPointerTy(); 2955 if (AllocSize.getValueType() != IntPtr) 2956 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 2957 2958 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 2959 AllocSize, 2960 DAG.getConstant(TySize, IntPtr)); 2961 2962 // Handle alignment. If the requested alignment is less than or equal to 2963 // the stack alignment, ignore it. If the size is greater than or equal to 2964 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2965 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 2966 if (Align <= StackAlign) 2967 Align = 0; 2968 2969 // Round the size of the allocation up to the stack alignment size 2970 // by add SA-1 to the size. 2971 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2972 AllocSize.getValueType(), AllocSize, 2973 DAG.getIntPtrConstant(StackAlign-1)); 2974 2975 // Mask out the low bits for alignment purposes. 2976 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 2977 AllocSize.getValueType(), AllocSize, 2978 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2979 2980 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2981 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 2982 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 2983 VTs, Ops, 3); 2984 setValue(&I, DSA); 2985 DAG.setRoot(DSA.getValue(1)); 2986 2987 // Inform the Frame Information that we have just allocated a variable-sized 2988 // object. 2989 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 2990} 2991 2992void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 2993 const Value *SV = I.getOperand(0); 2994 SDValue Ptr = getValue(SV); 2995 2996 const Type *Ty = I.getType(); 2997 2998 bool isVolatile = I.isVolatile(); 2999 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3000 unsigned Alignment = I.getAlignment(); 3001 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3002 3003 SmallVector<EVT, 4> ValueVTs; 3004 SmallVector<uint64_t, 4> Offsets; 3005 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3006 unsigned NumValues = ValueVTs.size(); 3007 if (NumValues == 0) 3008 return; 3009 3010 SDValue Root; 3011 bool ConstantMemory = false; 3012 if (I.isVolatile() || NumValues > MaxParallelChains) 3013 // Serialize volatile loads with other side effects. 3014 Root = getRoot(); 3015 else if (AA->pointsToConstantMemory( 3016 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3017 // Do not serialize (non-volatile) loads of constant memory with anything. 3018 Root = DAG.getEntryNode(); 3019 ConstantMemory = true; 3020 } else { 3021 // Do not serialize non-volatile loads against each other. 3022 Root = DAG.getRoot(); 3023 } 3024 3025 SmallVector<SDValue, 4> Values(NumValues); 3026 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3027 NumValues)); 3028 EVT PtrVT = Ptr.getValueType(); 3029 unsigned ChainI = 0; 3030 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3031 // Serializing loads here may result in excessive register pressure, and 3032 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3033 // could recover a bit by hoisting nodes upward in the chain by recognizing 3034 // they are side-effect free or do not alias. The optimizer should really 3035 // avoid this case by converting large object/array copies to llvm.memcpy 3036 // (MaxParallelChains should always remain as failsafe). 3037 if (ChainI == MaxParallelChains) { 3038 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3039 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3040 MVT::Other, &Chains[0], ChainI); 3041 Root = Chain; 3042 ChainI = 0; 3043 } 3044 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3045 PtrVT, Ptr, 3046 DAG.getConstant(Offsets[i], PtrVT)); 3047 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3048 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3049 isNonTemporal, Alignment, TBAAInfo); 3050 3051 Values[i] = L; 3052 Chains[ChainI] = L.getValue(1); 3053 } 3054 3055 if (!ConstantMemory) { 3056 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3057 MVT::Other, &Chains[0], ChainI); 3058 if (isVolatile) 3059 DAG.setRoot(Chain); 3060 else 3061 PendingLoads.push_back(Chain); 3062 } 3063 3064 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3065 DAG.getVTList(&ValueVTs[0], NumValues), 3066 &Values[0], NumValues)); 3067} 3068 3069void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3070 const Value *SrcV = I.getOperand(0); 3071 const Value *PtrV = I.getOperand(1); 3072 3073 SmallVector<EVT, 4> ValueVTs; 3074 SmallVector<uint64_t, 4> Offsets; 3075 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3076 unsigned NumValues = ValueVTs.size(); 3077 if (NumValues == 0) 3078 return; 3079 3080 // Get the lowered operands. Note that we do this after 3081 // checking if NumResults is zero, because with zero results 3082 // the operands won't have values in the map. 3083 SDValue Src = getValue(SrcV); 3084 SDValue Ptr = getValue(PtrV); 3085 3086 SDValue Root = getRoot(); 3087 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3088 NumValues)); 3089 EVT PtrVT = Ptr.getValueType(); 3090 bool isVolatile = I.isVolatile(); 3091 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3092 unsigned Alignment = I.getAlignment(); 3093 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3094 3095 unsigned ChainI = 0; 3096 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3097 // See visitLoad comments. 3098 if (ChainI == MaxParallelChains) { 3099 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3100 MVT::Other, &Chains[0], ChainI); 3101 Root = Chain; 3102 ChainI = 0; 3103 } 3104 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3105 DAG.getConstant(Offsets[i], PtrVT)); 3106 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3107 SDValue(Src.getNode(), Src.getResNo() + i), 3108 Add, MachinePointerInfo(PtrV, Offsets[i]), 3109 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3110 Chains[ChainI] = St; 3111 } 3112 3113 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3114 MVT::Other, &Chains[0], ChainI); 3115 ++SDNodeOrder; 3116 AssignOrderingToNode(StoreNode.getNode()); 3117 DAG.setRoot(StoreNode); 3118} 3119 3120/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3121/// node. 3122void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3123 unsigned Intrinsic) { 3124 bool HasChain = !I.doesNotAccessMemory(); 3125 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3126 3127 // Build the operand list. 3128 SmallVector<SDValue, 8> Ops; 3129 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3130 if (OnlyLoad) { 3131 // We don't need to serialize loads against other loads. 3132 Ops.push_back(DAG.getRoot()); 3133 } else { 3134 Ops.push_back(getRoot()); 3135 } 3136 } 3137 3138 // Info is set by getTgtMemInstrinsic 3139 TargetLowering::IntrinsicInfo Info; 3140 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3141 3142 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3143 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3144 Info.opc == ISD::INTRINSIC_W_CHAIN) 3145 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3146 3147 // Add all operands of the call to the operand list. 3148 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3149 SDValue Op = getValue(I.getArgOperand(i)); 3150 assert(TLI.isTypeLegal(Op.getValueType()) && 3151 "Intrinsic uses a non-legal type?"); 3152 Ops.push_back(Op); 3153 } 3154 3155 SmallVector<EVT, 4> ValueVTs; 3156 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3157#ifndef NDEBUG 3158 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3159 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3160 "Intrinsic uses a non-legal type?"); 3161 } 3162#endif // NDEBUG 3163 3164 if (HasChain) 3165 ValueVTs.push_back(MVT::Other); 3166 3167 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3168 3169 // Create the node. 3170 SDValue Result; 3171 if (IsTgtIntrinsic) { 3172 // This is target intrinsic that touches memory 3173 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3174 VTs, &Ops[0], Ops.size(), 3175 Info.memVT, 3176 MachinePointerInfo(Info.ptrVal, Info.offset), 3177 Info.align, Info.vol, 3178 Info.readMem, Info.writeMem); 3179 } else if (!HasChain) { 3180 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3181 VTs, &Ops[0], Ops.size()); 3182 } else if (!I.getType()->isVoidTy()) { 3183 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3184 VTs, &Ops[0], Ops.size()); 3185 } else { 3186 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3187 VTs, &Ops[0], Ops.size()); 3188 } 3189 3190 if (HasChain) { 3191 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3192 if (OnlyLoad) 3193 PendingLoads.push_back(Chain); 3194 else 3195 DAG.setRoot(Chain); 3196 } 3197 3198 if (!I.getType()->isVoidTy()) { 3199 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3200 EVT VT = TLI.getValueType(PTy); 3201 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3202 } 3203 3204 setValue(&I, Result); 3205 } 3206} 3207 3208/// GetSignificand - Get the significand and build it into a floating-point 3209/// number with exponent of 1: 3210/// 3211/// Op = (Op & 0x007fffff) | 0x3f800000; 3212/// 3213/// where Op is the hexidecimal representation of floating point value. 3214static SDValue 3215GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3216 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3217 DAG.getConstant(0x007fffff, MVT::i32)); 3218 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3219 DAG.getConstant(0x3f800000, MVT::i32)); 3220 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3221} 3222 3223/// GetExponent - Get the exponent: 3224/// 3225/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3226/// 3227/// where Op is the hexidecimal representation of floating point value. 3228static SDValue 3229GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3230 DebugLoc dl) { 3231 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3232 DAG.getConstant(0x7f800000, MVT::i32)); 3233 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3234 DAG.getConstant(23, TLI.getPointerTy())); 3235 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3236 DAG.getConstant(127, MVT::i32)); 3237 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3238} 3239 3240/// getF32Constant - Get 32-bit floating point constant. 3241static SDValue 3242getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3243 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3244} 3245 3246/// Inlined utility function to implement binary input atomic intrinsics for 3247/// visitIntrinsicCall: I is a call instruction 3248/// Op is the associated NodeType for I 3249const char * 3250SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3251 ISD::NodeType Op) { 3252 SDValue Root = getRoot(); 3253 SDValue L = 3254 DAG.getAtomic(Op, getCurDebugLoc(), 3255 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3256 Root, 3257 getValue(I.getArgOperand(0)), 3258 getValue(I.getArgOperand(1)), 3259 I.getArgOperand(0)); 3260 setValue(&I, L); 3261 DAG.setRoot(L.getValue(1)); 3262 return 0; 3263} 3264 3265// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3266const char * 3267SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3268 SDValue Op1 = getValue(I.getArgOperand(0)); 3269 SDValue Op2 = getValue(I.getArgOperand(1)); 3270 3271 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3272 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3273 return 0; 3274} 3275 3276/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3277/// limited-precision mode. 3278void 3279SelectionDAGBuilder::visitExp(const CallInst &I) { 3280 SDValue result; 3281 DebugLoc dl = getCurDebugLoc(); 3282 3283 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3284 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3285 SDValue Op = getValue(I.getArgOperand(0)); 3286 3287 // Put the exponent in the right bit position for later addition to the 3288 // final result: 3289 // 3290 // #define LOG2OFe 1.4426950f 3291 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3292 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3293 getF32Constant(DAG, 0x3fb8aa3b)); 3294 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3295 3296 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3297 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3298 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3299 3300 // IntegerPartOfX <<= 23; 3301 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3302 DAG.getConstant(23, TLI.getPointerTy())); 3303 3304 if (LimitFloatPrecision <= 6) { 3305 // For floating-point precision of 6: 3306 // 3307 // TwoToFractionalPartOfX = 3308 // 0.997535578f + 3309 // (0.735607626f + 0.252464424f * x) * x; 3310 // 3311 // error 0.0144103317, which is 6 bits 3312 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3313 getF32Constant(DAG, 0x3e814304)); 3314 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3315 getF32Constant(DAG, 0x3f3c50c8)); 3316 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3317 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3318 getF32Constant(DAG, 0x3f7f5e7e)); 3319 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3320 3321 // Add the exponent into the result in integer domain. 3322 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3323 TwoToFracPartOfX, IntegerPartOfX); 3324 3325 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3326 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3327 // For floating-point precision of 12: 3328 // 3329 // TwoToFractionalPartOfX = 3330 // 0.999892986f + 3331 // (0.696457318f + 3332 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3333 // 3334 // 0.000107046256 error, which is 13 to 14 bits 3335 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3336 getF32Constant(DAG, 0x3da235e3)); 3337 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3338 getF32Constant(DAG, 0x3e65b8f3)); 3339 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3340 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3341 getF32Constant(DAG, 0x3f324b07)); 3342 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3343 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3344 getF32Constant(DAG, 0x3f7ff8fd)); 3345 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3346 3347 // Add the exponent into the result in integer domain. 3348 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3349 TwoToFracPartOfX, IntegerPartOfX); 3350 3351 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3352 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3353 // For floating-point precision of 18: 3354 // 3355 // TwoToFractionalPartOfX = 3356 // 0.999999982f + 3357 // (0.693148872f + 3358 // (0.240227044f + 3359 // (0.554906021e-1f + 3360 // (0.961591928e-2f + 3361 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3362 // 3363 // error 2.47208000*10^(-7), which is better than 18 bits 3364 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3365 getF32Constant(DAG, 0x3924b03e)); 3366 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3367 getF32Constant(DAG, 0x3ab24b87)); 3368 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3369 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3370 getF32Constant(DAG, 0x3c1d8c17)); 3371 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3372 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3373 getF32Constant(DAG, 0x3d634a1d)); 3374 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3375 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3376 getF32Constant(DAG, 0x3e75fe14)); 3377 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3378 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3379 getF32Constant(DAG, 0x3f317234)); 3380 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3381 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3382 getF32Constant(DAG, 0x3f800000)); 3383 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3384 MVT::i32, t13); 3385 3386 // Add the exponent into the result in integer domain. 3387 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3388 TwoToFracPartOfX, IntegerPartOfX); 3389 3390 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3391 } 3392 } else { 3393 // No special expansion. 3394 result = DAG.getNode(ISD::FEXP, dl, 3395 getValue(I.getArgOperand(0)).getValueType(), 3396 getValue(I.getArgOperand(0))); 3397 } 3398 3399 setValue(&I, result); 3400} 3401 3402/// visitLog - Lower a log intrinsic. Handles the special sequences for 3403/// limited-precision mode. 3404void 3405SelectionDAGBuilder::visitLog(const CallInst &I) { 3406 SDValue result; 3407 DebugLoc dl = getCurDebugLoc(); 3408 3409 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3410 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3411 SDValue Op = getValue(I.getArgOperand(0)); 3412 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3413 3414 // Scale the exponent by log(2) [0.69314718f]. 3415 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3416 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3417 getF32Constant(DAG, 0x3f317218)); 3418 3419 // Get the significand and build it into a floating-point number with 3420 // exponent of 1. 3421 SDValue X = GetSignificand(DAG, Op1, dl); 3422 3423 if (LimitFloatPrecision <= 6) { 3424 // For floating-point precision of 6: 3425 // 3426 // LogofMantissa = 3427 // -1.1609546f + 3428 // (1.4034025f - 0.23903021f * x) * x; 3429 // 3430 // error 0.0034276066, which is better than 8 bits 3431 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3432 getF32Constant(DAG, 0xbe74c456)); 3433 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3434 getF32Constant(DAG, 0x3fb3a2b1)); 3435 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3436 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3437 getF32Constant(DAG, 0x3f949a29)); 3438 3439 result = DAG.getNode(ISD::FADD, dl, 3440 MVT::f32, LogOfExponent, LogOfMantissa); 3441 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3442 // For floating-point precision of 12: 3443 // 3444 // LogOfMantissa = 3445 // -1.7417939f + 3446 // (2.8212026f + 3447 // (-1.4699568f + 3448 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3449 // 3450 // error 0.000061011436, which is 14 bits 3451 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3452 getF32Constant(DAG, 0xbd67b6d6)); 3453 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3454 getF32Constant(DAG, 0x3ee4f4b8)); 3455 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3456 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3457 getF32Constant(DAG, 0x3fbc278b)); 3458 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3459 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3460 getF32Constant(DAG, 0x40348e95)); 3461 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3462 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3463 getF32Constant(DAG, 0x3fdef31a)); 3464 3465 result = DAG.getNode(ISD::FADD, dl, 3466 MVT::f32, LogOfExponent, LogOfMantissa); 3467 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3468 // For floating-point precision of 18: 3469 // 3470 // LogOfMantissa = 3471 // -2.1072184f + 3472 // (4.2372794f + 3473 // (-3.7029485f + 3474 // (2.2781945f + 3475 // (-0.87823314f + 3476 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3477 // 3478 // error 0.0000023660568, which is better than 18 bits 3479 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3480 getF32Constant(DAG, 0xbc91e5ac)); 3481 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3482 getF32Constant(DAG, 0x3e4350aa)); 3483 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3484 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3485 getF32Constant(DAG, 0x3f60d3e3)); 3486 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3487 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3488 getF32Constant(DAG, 0x4011cdf0)); 3489 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3490 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3491 getF32Constant(DAG, 0x406cfd1c)); 3492 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3493 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3494 getF32Constant(DAG, 0x408797cb)); 3495 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3496 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3497 getF32Constant(DAG, 0x4006dcab)); 3498 3499 result = DAG.getNode(ISD::FADD, dl, 3500 MVT::f32, LogOfExponent, LogOfMantissa); 3501 } 3502 } else { 3503 // No special expansion. 3504 result = DAG.getNode(ISD::FLOG, dl, 3505 getValue(I.getArgOperand(0)).getValueType(), 3506 getValue(I.getArgOperand(0))); 3507 } 3508 3509 setValue(&I, result); 3510} 3511 3512/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3513/// limited-precision mode. 3514void 3515SelectionDAGBuilder::visitLog2(const CallInst &I) { 3516 SDValue result; 3517 DebugLoc dl = getCurDebugLoc(); 3518 3519 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3520 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3521 SDValue Op = getValue(I.getArgOperand(0)); 3522 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3523 3524 // Get the exponent. 3525 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3526 3527 // Get the significand and build it into a floating-point number with 3528 // exponent of 1. 3529 SDValue X = GetSignificand(DAG, Op1, dl); 3530 3531 // Different possible minimax approximations of significand in 3532 // floating-point for various degrees of accuracy over [1,2]. 3533 if (LimitFloatPrecision <= 6) { 3534 // For floating-point precision of 6: 3535 // 3536 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3537 // 3538 // error 0.0049451742, which is more than 7 bits 3539 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3540 getF32Constant(DAG, 0xbeb08fe0)); 3541 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3542 getF32Constant(DAG, 0x40019463)); 3543 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3544 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3545 getF32Constant(DAG, 0x3fd6633d)); 3546 3547 result = DAG.getNode(ISD::FADD, dl, 3548 MVT::f32, LogOfExponent, Log2ofMantissa); 3549 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3550 // For floating-point precision of 12: 3551 // 3552 // Log2ofMantissa = 3553 // -2.51285454f + 3554 // (4.07009056f + 3555 // (-2.12067489f + 3556 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3557 // 3558 // error 0.0000876136000, which is better than 13 bits 3559 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3560 getF32Constant(DAG, 0xbda7262e)); 3561 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3562 getF32Constant(DAG, 0x3f25280b)); 3563 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3564 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3565 getF32Constant(DAG, 0x4007b923)); 3566 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3567 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3568 getF32Constant(DAG, 0x40823e2f)); 3569 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3570 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3571 getF32Constant(DAG, 0x4020d29c)); 3572 3573 result = DAG.getNode(ISD::FADD, dl, 3574 MVT::f32, LogOfExponent, Log2ofMantissa); 3575 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3576 // For floating-point precision of 18: 3577 // 3578 // Log2ofMantissa = 3579 // -3.0400495f + 3580 // (6.1129976f + 3581 // (-5.3420409f + 3582 // (3.2865683f + 3583 // (-1.2669343f + 3584 // (0.27515199f - 3585 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3586 // 3587 // error 0.0000018516, which is better than 18 bits 3588 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3589 getF32Constant(DAG, 0xbcd2769e)); 3590 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3591 getF32Constant(DAG, 0x3e8ce0b9)); 3592 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3593 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3594 getF32Constant(DAG, 0x3fa22ae7)); 3595 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3596 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3597 getF32Constant(DAG, 0x40525723)); 3598 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3599 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3600 getF32Constant(DAG, 0x40aaf200)); 3601 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3602 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3603 getF32Constant(DAG, 0x40c39dad)); 3604 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3605 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3606 getF32Constant(DAG, 0x4042902c)); 3607 3608 result = DAG.getNode(ISD::FADD, dl, 3609 MVT::f32, LogOfExponent, Log2ofMantissa); 3610 } 3611 } else { 3612 // No special expansion. 3613 result = DAG.getNode(ISD::FLOG2, dl, 3614 getValue(I.getArgOperand(0)).getValueType(), 3615 getValue(I.getArgOperand(0))); 3616 } 3617 3618 setValue(&I, result); 3619} 3620 3621/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3622/// limited-precision mode. 3623void 3624SelectionDAGBuilder::visitLog10(const CallInst &I) { 3625 SDValue result; 3626 DebugLoc dl = getCurDebugLoc(); 3627 3628 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3629 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3630 SDValue Op = getValue(I.getArgOperand(0)); 3631 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3632 3633 // Scale the exponent by log10(2) [0.30102999f]. 3634 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3635 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3636 getF32Constant(DAG, 0x3e9a209a)); 3637 3638 // Get the significand and build it into a floating-point number with 3639 // exponent of 1. 3640 SDValue X = GetSignificand(DAG, Op1, dl); 3641 3642 if (LimitFloatPrecision <= 6) { 3643 // For floating-point precision of 6: 3644 // 3645 // Log10ofMantissa = 3646 // -0.50419619f + 3647 // (0.60948995f - 0.10380950f * x) * x; 3648 // 3649 // error 0.0014886165, which is 6 bits 3650 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3651 getF32Constant(DAG, 0xbdd49a13)); 3652 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3653 getF32Constant(DAG, 0x3f1c0789)); 3654 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3655 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3656 getF32Constant(DAG, 0x3f011300)); 3657 3658 result = DAG.getNode(ISD::FADD, dl, 3659 MVT::f32, LogOfExponent, Log10ofMantissa); 3660 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3661 // For floating-point precision of 12: 3662 // 3663 // Log10ofMantissa = 3664 // -0.64831180f + 3665 // (0.91751397f + 3666 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3667 // 3668 // error 0.00019228036, which is better than 12 bits 3669 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3670 getF32Constant(DAG, 0x3d431f31)); 3671 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3672 getF32Constant(DAG, 0x3ea21fb2)); 3673 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3674 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3675 getF32Constant(DAG, 0x3f6ae232)); 3676 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3677 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3678 getF32Constant(DAG, 0x3f25f7c3)); 3679 3680 result = DAG.getNode(ISD::FADD, dl, 3681 MVT::f32, LogOfExponent, Log10ofMantissa); 3682 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3683 // For floating-point precision of 18: 3684 // 3685 // Log10ofMantissa = 3686 // -0.84299375f + 3687 // (1.5327582f + 3688 // (-1.0688956f + 3689 // (0.49102474f + 3690 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3691 // 3692 // error 0.0000037995730, which is better than 18 bits 3693 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3694 getF32Constant(DAG, 0x3c5d51ce)); 3695 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3696 getF32Constant(DAG, 0x3e00685a)); 3697 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3698 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3699 getF32Constant(DAG, 0x3efb6798)); 3700 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3701 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3702 getF32Constant(DAG, 0x3f88d192)); 3703 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3704 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3705 getF32Constant(DAG, 0x3fc4316c)); 3706 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3707 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3708 getF32Constant(DAG, 0x3f57ce70)); 3709 3710 result = DAG.getNode(ISD::FADD, dl, 3711 MVT::f32, LogOfExponent, Log10ofMantissa); 3712 } 3713 } else { 3714 // No special expansion. 3715 result = DAG.getNode(ISD::FLOG10, dl, 3716 getValue(I.getArgOperand(0)).getValueType(), 3717 getValue(I.getArgOperand(0))); 3718 } 3719 3720 setValue(&I, result); 3721} 3722 3723/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3724/// limited-precision mode. 3725void 3726SelectionDAGBuilder::visitExp2(const CallInst &I) { 3727 SDValue result; 3728 DebugLoc dl = getCurDebugLoc(); 3729 3730 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3731 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3732 SDValue Op = getValue(I.getArgOperand(0)); 3733 3734 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3735 3736 // FractionalPartOfX = x - (float)IntegerPartOfX; 3737 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3738 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3739 3740 // IntegerPartOfX <<= 23; 3741 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3742 DAG.getConstant(23, TLI.getPointerTy())); 3743 3744 if (LimitFloatPrecision <= 6) { 3745 // For floating-point precision of 6: 3746 // 3747 // TwoToFractionalPartOfX = 3748 // 0.997535578f + 3749 // (0.735607626f + 0.252464424f * x) * x; 3750 // 3751 // error 0.0144103317, which is 6 bits 3752 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3753 getF32Constant(DAG, 0x3e814304)); 3754 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3755 getF32Constant(DAG, 0x3f3c50c8)); 3756 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3757 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3758 getF32Constant(DAG, 0x3f7f5e7e)); 3759 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3760 SDValue TwoToFractionalPartOfX = 3761 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3762 3763 result = DAG.getNode(ISD::BITCAST, dl, 3764 MVT::f32, TwoToFractionalPartOfX); 3765 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3766 // For floating-point precision of 12: 3767 // 3768 // TwoToFractionalPartOfX = 3769 // 0.999892986f + 3770 // (0.696457318f + 3771 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3772 // 3773 // error 0.000107046256, which is 13 to 14 bits 3774 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3775 getF32Constant(DAG, 0x3da235e3)); 3776 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3777 getF32Constant(DAG, 0x3e65b8f3)); 3778 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3779 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3780 getF32Constant(DAG, 0x3f324b07)); 3781 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3782 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3783 getF32Constant(DAG, 0x3f7ff8fd)); 3784 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3785 SDValue TwoToFractionalPartOfX = 3786 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3787 3788 result = DAG.getNode(ISD::BITCAST, dl, 3789 MVT::f32, TwoToFractionalPartOfX); 3790 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3791 // For floating-point precision of 18: 3792 // 3793 // TwoToFractionalPartOfX = 3794 // 0.999999982f + 3795 // (0.693148872f + 3796 // (0.240227044f + 3797 // (0.554906021e-1f + 3798 // (0.961591928e-2f + 3799 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3800 // error 2.47208000*10^(-7), which is better than 18 bits 3801 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3802 getF32Constant(DAG, 0x3924b03e)); 3803 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3804 getF32Constant(DAG, 0x3ab24b87)); 3805 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3806 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3807 getF32Constant(DAG, 0x3c1d8c17)); 3808 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3809 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3810 getF32Constant(DAG, 0x3d634a1d)); 3811 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3812 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3813 getF32Constant(DAG, 0x3e75fe14)); 3814 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3815 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3816 getF32Constant(DAG, 0x3f317234)); 3817 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3818 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3819 getF32Constant(DAG, 0x3f800000)); 3820 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 3821 SDValue TwoToFractionalPartOfX = 3822 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3823 3824 result = DAG.getNode(ISD::BITCAST, dl, 3825 MVT::f32, TwoToFractionalPartOfX); 3826 } 3827 } else { 3828 // No special expansion. 3829 result = DAG.getNode(ISD::FEXP2, dl, 3830 getValue(I.getArgOperand(0)).getValueType(), 3831 getValue(I.getArgOperand(0))); 3832 } 3833 3834 setValue(&I, result); 3835} 3836 3837/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3838/// limited-precision mode with x == 10.0f. 3839void 3840SelectionDAGBuilder::visitPow(const CallInst &I) { 3841 SDValue result; 3842 const Value *Val = I.getArgOperand(0); 3843 DebugLoc dl = getCurDebugLoc(); 3844 bool IsExp10 = false; 3845 3846 if (getValue(Val).getValueType() == MVT::f32 && 3847 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 3848 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3849 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3850 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3851 APFloat Ten(10.0f); 3852 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3853 } 3854 } 3855 } 3856 3857 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3858 SDValue Op = getValue(I.getArgOperand(1)); 3859 3860 // Put the exponent in the right bit position for later addition to the 3861 // final result: 3862 // 3863 // #define LOG2OF10 3.3219281f 3864 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3865 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3866 getF32Constant(DAG, 0x40549a78)); 3867 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3868 3869 // FractionalPartOfX = x - (float)IntegerPartOfX; 3870 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3871 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3872 3873 // IntegerPartOfX <<= 23; 3874 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3875 DAG.getConstant(23, TLI.getPointerTy())); 3876 3877 if (LimitFloatPrecision <= 6) { 3878 // For floating-point precision of 6: 3879 // 3880 // twoToFractionalPartOfX = 3881 // 0.997535578f + 3882 // (0.735607626f + 0.252464424f * x) * x; 3883 // 3884 // error 0.0144103317, which is 6 bits 3885 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3886 getF32Constant(DAG, 0x3e814304)); 3887 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3888 getF32Constant(DAG, 0x3f3c50c8)); 3889 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3890 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3891 getF32Constant(DAG, 0x3f7f5e7e)); 3892 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3893 SDValue TwoToFractionalPartOfX = 3894 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3895 3896 result = DAG.getNode(ISD::BITCAST, dl, 3897 MVT::f32, TwoToFractionalPartOfX); 3898 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3899 // For floating-point precision of 12: 3900 // 3901 // TwoToFractionalPartOfX = 3902 // 0.999892986f + 3903 // (0.696457318f + 3904 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3905 // 3906 // error 0.000107046256, which is 13 to 14 bits 3907 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3908 getF32Constant(DAG, 0x3da235e3)); 3909 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3910 getF32Constant(DAG, 0x3e65b8f3)); 3911 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3912 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3913 getF32Constant(DAG, 0x3f324b07)); 3914 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3915 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3916 getF32Constant(DAG, 0x3f7ff8fd)); 3917 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3918 SDValue TwoToFractionalPartOfX = 3919 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3920 3921 result = DAG.getNode(ISD::BITCAST, dl, 3922 MVT::f32, TwoToFractionalPartOfX); 3923 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3924 // For floating-point precision of 18: 3925 // 3926 // TwoToFractionalPartOfX = 3927 // 0.999999982f + 3928 // (0.693148872f + 3929 // (0.240227044f + 3930 // (0.554906021e-1f + 3931 // (0.961591928e-2f + 3932 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3933 // error 2.47208000*10^(-7), which is better than 18 bits 3934 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3935 getF32Constant(DAG, 0x3924b03e)); 3936 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3937 getF32Constant(DAG, 0x3ab24b87)); 3938 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3939 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3940 getF32Constant(DAG, 0x3c1d8c17)); 3941 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3942 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3943 getF32Constant(DAG, 0x3d634a1d)); 3944 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3945 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3946 getF32Constant(DAG, 0x3e75fe14)); 3947 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3948 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3949 getF32Constant(DAG, 0x3f317234)); 3950 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3951 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3952 getF32Constant(DAG, 0x3f800000)); 3953 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 3954 SDValue TwoToFractionalPartOfX = 3955 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3956 3957 result = DAG.getNode(ISD::BITCAST, dl, 3958 MVT::f32, TwoToFractionalPartOfX); 3959 } 3960 } else { 3961 // No special expansion. 3962 result = DAG.getNode(ISD::FPOW, dl, 3963 getValue(I.getArgOperand(0)).getValueType(), 3964 getValue(I.getArgOperand(0)), 3965 getValue(I.getArgOperand(1))); 3966 } 3967 3968 setValue(&I, result); 3969} 3970 3971 3972/// ExpandPowI - Expand a llvm.powi intrinsic. 3973static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 3974 SelectionDAG &DAG) { 3975 // If RHS is a constant, we can expand this out to a multiplication tree, 3976 // otherwise we end up lowering to a call to __powidf2 (for example). When 3977 // optimizing for size, we only want to do this if the expansion would produce 3978 // a small number of multiplies, otherwise we do the full expansion. 3979 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3980 // Get the exponent as a positive value. 3981 unsigned Val = RHSC->getSExtValue(); 3982 if ((int)Val < 0) Val = -Val; 3983 3984 // powi(x, 0) -> 1.0 3985 if (Val == 0) 3986 return DAG.getConstantFP(1.0, LHS.getValueType()); 3987 3988 const Function *F = DAG.getMachineFunction().getFunction(); 3989 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 3990 // If optimizing for size, don't insert too many multiplies. This 3991 // inserts up to 5 multiplies. 3992 CountPopulation_32(Val)+Log2_32(Val) < 7) { 3993 // We use the simple binary decomposition method to generate the multiply 3994 // sequence. There are more optimal ways to do this (for example, 3995 // powi(x,15) generates one more multiply than it should), but this has 3996 // the benefit of being both really simple and much better than a libcall. 3997 SDValue Res; // Logically starts equal to 1.0 3998 SDValue CurSquare = LHS; 3999 while (Val) { 4000 if (Val & 1) { 4001 if (Res.getNode()) 4002 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4003 else 4004 Res = CurSquare; // 1.0*CurSquare. 4005 } 4006 4007 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4008 CurSquare, CurSquare); 4009 Val >>= 1; 4010 } 4011 4012 // If the original was negative, invert the result, producing 1/(x*x*x). 4013 if (RHSC->getSExtValue() < 0) 4014 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4015 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4016 return Res; 4017 } 4018 } 4019 4020 // Otherwise, expand to a libcall. 4021 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4022} 4023 4024/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4025/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4026/// At the end of instruction selection, they will be inserted to the entry BB. 4027bool 4028SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4029 int64_t Offset, 4030 const SDValue &N) { 4031 const Argument *Arg = dyn_cast<Argument>(V); 4032 if (!Arg) 4033 return false; 4034 4035 MachineFunction &MF = DAG.getMachineFunction(); 4036 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4037 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4038 4039 // Ignore inlined function arguments here. 4040 DIVariable DV(Variable); 4041 if (DV.isInlinedFnArgument(MF.getFunction())) 4042 return false; 4043 4044 MachineBasicBlock *MBB = FuncInfo.MBB; 4045 if (MBB != &MF.front()) 4046 return false; 4047 4048 unsigned Reg = 0; 4049 if (Arg->hasByValAttr()) { 4050 // Byval arguments' frame index is recorded during argument lowering. 4051 // Use this info directly. 4052 Reg = TRI->getFrameRegister(MF); 4053 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 4054 // If byval argument ofset is not recorded then ignore this. 4055 if (!Offset) 4056 Reg = 0; 4057 } 4058 4059 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) { 4060 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4061 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 4062 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4063 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4064 if (PR) 4065 Reg = PR; 4066 } 4067 } 4068 4069 if (!Reg) { 4070 // Check if ValueMap has reg number. 4071 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4072 if (VMI != FuncInfo.ValueMap.end()) 4073 Reg = VMI->second; 4074 } 4075 4076 if (!Reg && N.getNode()) { 4077 // Check if frame index is available. 4078 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4079 if (FrameIndexSDNode *FINode = 4080 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4081 Reg = TRI->getFrameRegister(MF); 4082 Offset = FINode->getIndex(); 4083 } 4084 } 4085 4086 if (!Reg) 4087 return false; 4088 4089 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4090 TII->get(TargetOpcode::DBG_VALUE)) 4091 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4092 FuncInfo.ArgDbgValues.push_back(&*MIB); 4093 return true; 4094} 4095 4096// VisualStudio defines setjmp as _setjmp 4097#if defined(_MSC_VER) && defined(setjmp) && \ 4098 !defined(setjmp_undefined_for_msvc) 4099# pragma push_macro("setjmp") 4100# undef setjmp 4101# define setjmp_undefined_for_msvc 4102#endif 4103 4104/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4105/// we want to emit this as a call to a named external function, return the name 4106/// otherwise lower it and return null. 4107const char * 4108SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4109 DebugLoc dl = getCurDebugLoc(); 4110 SDValue Res; 4111 4112 switch (Intrinsic) { 4113 default: 4114 // By default, turn this into a target intrinsic node. 4115 visitTargetIntrinsic(I, Intrinsic); 4116 return 0; 4117 case Intrinsic::vastart: visitVAStart(I); return 0; 4118 case Intrinsic::vaend: visitVAEnd(I); return 0; 4119 case Intrinsic::vacopy: visitVACopy(I); return 0; 4120 case Intrinsic::returnaddress: 4121 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4122 getValue(I.getArgOperand(0)))); 4123 return 0; 4124 case Intrinsic::frameaddress: 4125 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4126 getValue(I.getArgOperand(0)))); 4127 return 0; 4128 case Intrinsic::setjmp: 4129 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4130 case Intrinsic::longjmp: 4131 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4132 case Intrinsic::memcpy: { 4133 // Assert for address < 256 since we support only user defined address 4134 // spaces. 4135 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4136 < 256 && 4137 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4138 < 256 && 4139 "Unknown address space"); 4140 SDValue Op1 = getValue(I.getArgOperand(0)); 4141 SDValue Op2 = getValue(I.getArgOperand(1)); 4142 SDValue Op3 = getValue(I.getArgOperand(2)); 4143 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4144 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4145 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4146 MachinePointerInfo(I.getArgOperand(0)), 4147 MachinePointerInfo(I.getArgOperand(1)))); 4148 return 0; 4149 } 4150 case Intrinsic::memset: { 4151 // Assert for address < 256 since we support only user defined address 4152 // spaces. 4153 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4154 < 256 && 4155 "Unknown address space"); 4156 SDValue Op1 = getValue(I.getArgOperand(0)); 4157 SDValue Op2 = getValue(I.getArgOperand(1)); 4158 SDValue Op3 = getValue(I.getArgOperand(2)); 4159 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4160 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4161 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4162 MachinePointerInfo(I.getArgOperand(0)))); 4163 return 0; 4164 } 4165 case Intrinsic::memmove: { 4166 // Assert for address < 256 since we support only user defined address 4167 // spaces. 4168 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4169 < 256 && 4170 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4171 < 256 && 4172 "Unknown address space"); 4173 SDValue Op1 = getValue(I.getArgOperand(0)); 4174 SDValue Op2 = getValue(I.getArgOperand(1)); 4175 SDValue Op3 = getValue(I.getArgOperand(2)); 4176 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4177 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4178 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4179 MachinePointerInfo(I.getArgOperand(0)), 4180 MachinePointerInfo(I.getArgOperand(1)))); 4181 return 0; 4182 } 4183 case Intrinsic::dbg_declare: { 4184 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4185 MDNode *Variable = DI.getVariable(); 4186 const Value *Address = DI.getAddress(); 4187 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4188 return 0; 4189 4190 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4191 // but do not always have a corresponding SDNode built. The SDNodeOrder 4192 // absolute, but not relative, values are different depending on whether 4193 // debug info exists. 4194 ++SDNodeOrder; 4195 4196 // Check if address has undef value. 4197 if (isa<UndefValue>(Address) || 4198 (Address->use_empty() && !isa<Argument>(Address))) { 4199 DEBUG(dbgs() << "Dropping debug info for " << DI); 4200 return 0; 4201 } 4202 4203 SDValue &N = NodeMap[Address]; 4204 if (!N.getNode() && isa<Argument>(Address)) 4205 // Check unused arguments map. 4206 N = UnusedArgNodeMap[Address]; 4207 SDDbgValue *SDV; 4208 if (N.getNode()) { 4209 // Parameters are handled specially. 4210 bool isParameter = 4211 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4212 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4213 Address = BCI->getOperand(0); 4214 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4215 4216 if (isParameter && !AI) { 4217 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4218 if (FINode) 4219 // Byval parameter. We have a frame index at this point. 4220 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4221 0, dl, SDNodeOrder); 4222 else { 4223 // Can't do anything with other non-AI cases yet. This might be a 4224 // parameter of a callee function that got inlined, for example. 4225 DEBUG(dbgs() << "Dropping debug info for " << DI); 4226 return 0; 4227 } 4228 } else if (AI) 4229 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4230 0, dl, SDNodeOrder); 4231 else { 4232 // Can't do anything with other non-AI cases yet. 4233 DEBUG(dbgs() << "Dropping debug info for " << DI); 4234 return 0; 4235 } 4236 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4237 } else { 4238 // If Address is an argument then try to emit its dbg value using 4239 // virtual register info from the FuncInfo.ValueMap. 4240 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4241 // If variable is pinned by a alloca in dominating bb then 4242 // use StaticAllocaMap. 4243 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4244 if (AI->getParent() != DI.getParent()) { 4245 DenseMap<const AllocaInst*, int>::iterator SI = 4246 FuncInfo.StaticAllocaMap.find(AI); 4247 if (SI != FuncInfo.StaticAllocaMap.end()) { 4248 SDV = DAG.getDbgValue(Variable, SI->second, 4249 0, dl, SDNodeOrder); 4250 DAG.AddDbgValue(SDV, 0, false); 4251 return 0; 4252 } 4253 } 4254 } 4255 DEBUG(dbgs() << "Dropping debug info for " << DI); 4256 } 4257 } 4258 return 0; 4259 } 4260 case Intrinsic::dbg_value: { 4261 const DbgValueInst &DI = cast<DbgValueInst>(I); 4262 if (!DIVariable(DI.getVariable()).Verify()) 4263 return 0; 4264 4265 MDNode *Variable = DI.getVariable(); 4266 uint64_t Offset = DI.getOffset(); 4267 const Value *V = DI.getValue(); 4268 if (!V) 4269 return 0; 4270 4271 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4272 // but do not always have a corresponding SDNode built. The SDNodeOrder 4273 // absolute, but not relative, values are different depending on whether 4274 // debug info exists. 4275 ++SDNodeOrder; 4276 SDDbgValue *SDV; 4277 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4278 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4279 DAG.AddDbgValue(SDV, 0, false); 4280 } else { 4281 // Do not use getValue() in here; we don't want to generate code at 4282 // this point if it hasn't been done yet. 4283 SDValue N = NodeMap[V]; 4284 if (!N.getNode() && isa<Argument>(V)) 4285 // Check unused arguments map. 4286 N = UnusedArgNodeMap[V]; 4287 if (N.getNode()) { 4288 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4289 SDV = DAG.getDbgValue(Variable, N.getNode(), 4290 N.getResNo(), Offset, dl, SDNodeOrder); 4291 DAG.AddDbgValue(SDV, N.getNode(), false); 4292 } 4293 } else if (!V->use_empty() ) { 4294 // Do not call getValue(V) yet, as we don't want to generate code. 4295 // Remember it for later. 4296 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4297 DanglingDebugInfoMap[V] = DDI; 4298 } else { 4299 // We may expand this to cover more cases. One case where we have no 4300 // data available is an unreferenced parameter. 4301 DEBUG(dbgs() << "Dropping debug info for " << DI); 4302 } 4303 } 4304 4305 // Build a debug info table entry. 4306 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4307 V = BCI->getOperand(0); 4308 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4309 // Don't handle byval struct arguments or VLAs, for example. 4310 if (!AI) 4311 return 0; 4312 DenseMap<const AllocaInst*, int>::iterator SI = 4313 FuncInfo.StaticAllocaMap.find(AI); 4314 if (SI == FuncInfo.StaticAllocaMap.end()) 4315 return 0; // VLAs. 4316 int FI = SI->second; 4317 4318 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4319 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4320 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4321 return 0; 4322 } 4323 case Intrinsic::eh_exception: { 4324 // Insert the EXCEPTIONADDR instruction. 4325 assert(FuncInfo.MBB->isLandingPad() && 4326 "Call to eh.exception not in landing pad!"); 4327 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4328 SDValue Ops[1]; 4329 Ops[0] = DAG.getRoot(); 4330 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4331 setValue(&I, Op); 4332 DAG.setRoot(Op.getValue(1)); 4333 return 0; 4334 } 4335 4336 case Intrinsic::eh_selector: { 4337 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4338 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4339 if (CallMBB->isLandingPad()) 4340 AddCatchInfo(I, &MMI, CallMBB); 4341 else { 4342#ifndef NDEBUG 4343 FuncInfo.CatchInfoLost.insert(&I); 4344#endif 4345 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4346 unsigned Reg = TLI.getExceptionSelectorRegister(); 4347 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4348 } 4349 4350 // Insert the EHSELECTION instruction. 4351 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4352 SDValue Ops[2]; 4353 Ops[0] = getValue(I.getArgOperand(0)); 4354 Ops[1] = getRoot(); 4355 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4356 DAG.setRoot(Op.getValue(1)); 4357 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4358 return 0; 4359 } 4360 4361 case Intrinsic::eh_typeid_for: { 4362 // Find the type id for the given typeinfo. 4363 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4364 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4365 Res = DAG.getConstant(TypeID, MVT::i32); 4366 setValue(&I, Res); 4367 return 0; 4368 } 4369 4370 case Intrinsic::eh_return_i32: 4371 case Intrinsic::eh_return_i64: 4372 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4373 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4374 MVT::Other, 4375 getControlRoot(), 4376 getValue(I.getArgOperand(0)), 4377 getValue(I.getArgOperand(1)))); 4378 return 0; 4379 case Intrinsic::eh_unwind_init: 4380 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4381 return 0; 4382 case Intrinsic::eh_dwarf_cfa: { 4383 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4384 TLI.getPointerTy()); 4385 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4386 TLI.getPointerTy(), 4387 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4388 TLI.getPointerTy()), 4389 CfaArg); 4390 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4391 TLI.getPointerTy(), 4392 DAG.getConstant(0, TLI.getPointerTy())); 4393 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4394 FA, Offset)); 4395 return 0; 4396 } 4397 case Intrinsic::eh_sjlj_callsite: { 4398 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4399 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4400 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4401 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4402 4403 MMI.setCurrentCallSite(CI->getZExtValue()); 4404 return 0; 4405 } 4406 case Intrinsic::eh_sjlj_setjmp: { 4407 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4408 getValue(I.getArgOperand(0)))); 4409 return 0; 4410 } 4411 case Intrinsic::eh_sjlj_longjmp: { 4412 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4413 getRoot(), getValue(I.getArgOperand(0)))); 4414 return 0; 4415 } 4416 case Intrinsic::eh_sjlj_dispatch_setup: { 4417 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4418 getRoot(), getValue(I.getArgOperand(0)))); 4419 return 0; 4420 } 4421 4422 case Intrinsic::x86_mmx_pslli_w: 4423 case Intrinsic::x86_mmx_pslli_d: 4424 case Intrinsic::x86_mmx_pslli_q: 4425 case Intrinsic::x86_mmx_psrli_w: 4426 case Intrinsic::x86_mmx_psrli_d: 4427 case Intrinsic::x86_mmx_psrli_q: 4428 case Intrinsic::x86_mmx_psrai_w: 4429 case Intrinsic::x86_mmx_psrai_d: { 4430 SDValue ShAmt = getValue(I.getArgOperand(1)); 4431 if (isa<ConstantSDNode>(ShAmt)) { 4432 visitTargetIntrinsic(I, Intrinsic); 4433 return 0; 4434 } 4435 unsigned NewIntrinsic = 0; 4436 EVT ShAmtVT = MVT::v2i32; 4437 switch (Intrinsic) { 4438 case Intrinsic::x86_mmx_pslli_w: 4439 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4440 break; 4441 case Intrinsic::x86_mmx_pslli_d: 4442 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4443 break; 4444 case Intrinsic::x86_mmx_pslli_q: 4445 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4446 break; 4447 case Intrinsic::x86_mmx_psrli_w: 4448 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4449 break; 4450 case Intrinsic::x86_mmx_psrli_d: 4451 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4452 break; 4453 case Intrinsic::x86_mmx_psrli_q: 4454 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4455 break; 4456 case Intrinsic::x86_mmx_psrai_w: 4457 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4458 break; 4459 case Intrinsic::x86_mmx_psrai_d: 4460 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4461 break; 4462 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4463 } 4464 4465 // The vector shift intrinsics with scalars uses 32b shift amounts but 4466 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4467 // to be zero. 4468 // We must do this early because v2i32 is not a legal type. 4469 DebugLoc dl = getCurDebugLoc(); 4470 SDValue ShOps[2]; 4471 ShOps[0] = ShAmt; 4472 ShOps[1] = DAG.getConstant(0, MVT::i32); 4473 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4474 EVT DestVT = TLI.getValueType(I.getType()); 4475 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4476 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4477 DAG.getConstant(NewIntrinsic, MVT::i32), 4478 getValue(I.getArgOperand(0)), ShAmt); 4479 setValue(&I, Res); 4480 return 0; 4481 } 4482 case Intrinsic::convertff: 4483 case Intrinsic::convertfsi: 4484 case Intrinsic::convertfui: 4485 case Intrinsic::convertsif: 4486 case Intrinsic::convertuif: 4487 case Intrinsic::convertss: 4488 case Intrinsic::convertsu: 4489 case Intrinsic::convertus: 4490 case Intrinsic::convertuu: { 4491 ISD::CvtCode Code = ISD::CVT_INVALID; 4492 switch (Intrinsic) { 4493 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4494 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4495 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4496 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4497 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4498 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4499 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4500 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4501 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4502 } 4503 EVT DestVT = TLI.getValueType(I.getType()); 4504 const Value *Op1 = I.getArgOperand(0); 4505 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4506 DAG.getValueType(DestVT), 4507 DAG.getValueType(getValue(Op1).getValueType()), 4508 getValue(I.getArgOperand(1)), 4509 getValue(I.getArgOperand(2)), 4510 Code); 4511 setValue(&I, Res); 4512 return 0; 4513 } 4514 case Intrinsic::sqrt: 4515 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4516 getValue(I.getArgOperand(0)).getValueType(), 4517 getValue(I.getArgOperand(0)))); 4518 return 0; 4519 case Intrinsic::powi: 4520 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4521 getValue(I.getArgOperand(1)), DAG)); 4522 return 0; 4523 case Intrinsic::sin: 4524 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4525 getValue(I.getArgOperand(0)).getValueType(), 4526 getValue(I.getArgOperand(0)))); 4527 return 0; 4528 case Intrinsic::cos: 4529 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4530 getValue(I.getArgOperand(0)).getValueType(), 4531 getValue(I.getArgOperand(0)))); 4532 return 0; 4533 case Intrinsic::log: 4534 visitLog(I); 4535 return 0; 4536 case Intrinsic::log2: 4537 visitLog2(I); 4538 return 0; 4539 case Intrinsic::log10: 4540 visitLog10(I); 4541 return 0; 4542 case Intrinsic::exp: 4543 visitExp(I); 4544 return 0; 4545 case Intrinsic::exp2: 4546 visitExp2(I); 4547 return 0; 4548 case Intrinsic::pow: 4549 visitPow(I); 4550 return 0; 4551 case Intrinsic::convert_to_fp16: 4552 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4553 MVT::i16, getValue(I.getArgOperand(0)))); 4554 return 0; 4555 case Intrinsic::convert_from_fp16: 4556 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4557 MVT::f32, getValue(I.getArgOperand(0)))); 4558 return 0; 4559 case Intrinsic::pcmarker: { 4560 SDValue Tmp = getValue(I.getArgOperand(0)); 4561 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4562 return 0; 4563 } 4564 case Intrinsic::readcyclecounter: { 4565 SDValue Op = getRoot(); 4566 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4567 DAG.getVTList(MVT::i64, MVT::Other), 4568 &Op, 1); 4569 setValue(&I, Res); 4570 DAG.setRoot(Res.getValue(1)); 4571 return 0; 4572 } 4573 case Intrinsic::bswap: 4574 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4575 getValue(I.getArgOperand(0)).getValueType(), 4576 getValue(I.getArgOperand(0)))); 4577 return 0; 4578 case Intrinsic::cttz: { 4579 SDValue Arg = getValue(I.getArgOperand(0)); 4580 EVT Ty = Arg.getValueType(); 4581 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4582 return 0; 4583 } 4584 case Intrinsic::ctlz: { 4585 SDValue Arg = getValue(I.getArgOperand(0)); 4586 EVT Ty = Arg.getValueType(); 4587 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4588 return 0; 4589 } 4590 case Intrinsic::ctpop: { 4591 SDValue Arg = getValue(I.getArgOperand(0)); 4592 EVT Ty = Arg.getValueType(); 4593 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4594 return 0; 4595 } 4596 case Intrinsic::stacksave: { 4597 SDValue Op = getRoot(); 4598 Res = DAG.getNode(ISD::STACKSAVE, dl, 4599 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4600 setValue(&I, Res); 4601 DAG.setRoot(Res.getValue(1)); 4602 return 0; 4603 } 4604 case Intrinsic::stackrestore: { 4605 Res = getValue(I.getArgOperand(0)); 4606 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4607 return 0; 4608 } 4609 case Intrinsic::stackprotector: { 4610 // Emit code into the DAG to store the stack guard onto the stack. 4611 MachineFunction &MF = DAG.getMachineFunction(); 4612 MachineFrameInfo *MFI = MF.getFrameInfo(); 4613 EVT PtrTy = TLI.getPointerTy(); 4614 4615 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4616 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4617 4618 int FI = FuncInfo.StaticAllocaMap[Slot]; 4619 MFI->setStackProtectorIndex(FI); 4620 4621 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4622 4623 // Store the stack protector onto the stack. 4624 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4625 MachinePointerInfo::getFixedStack(FI), 4626 true, false, 0); 4627 setValue(&I, Res); 4628 DAG.setRoot(Res); 4629 return 0; 4630 } 4631 case Intrinsic::objectsize: { 4632 // If we don't know by now, we're never going to know. 4633 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4634 4635 assert(CI && "Non-constant type in __builtin_object_size?"); 4636 4637 SDValue Arg = getValue(I.getCalledValue()); 4638 EVT Ty = Arg.getValueType(); 4639 4640 if (CI->isZero()) 4641 Res = DAG.getConstant(-1ULL, Ty); 4642 else 4643 Res = DAG.getConstant(0, Ty); 4644 4645 setValue(&I, Res); 4646 return 0; 4647 } 4648 case Intrinsic::var_annotation: 4649 // Discard annotate attributes 4650 return 0; 4651 4652 case Intrinsic::init_trampoline: { 4653 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4654 4655 SDValue Ops[6]; 4656 Ops[0] = getRoot(); 4657 Ops[1] = getValue(I.getArgOperand(0)); 4658 Ops[2] = getValue(I.getArgOperand(1)); 4659 Ops[3] = getValue(I.getArgOperand(2)); 4660 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4661 Ops[5] = DAG.getSrcValue(F); 4662 4663 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4664 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4665 Ops, 6); 4666 4667 setValue(&I, Res); 4668 DAG.setRoot(Res.getValue(1)); 4669 return 0; 4670 } 4671 case Intrinsic::gcroot: 4672 if (GFI) { 4673 const Value *Alloca = I.getArgOperand(0); 4674 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4675 4676 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4677 GFI->addStackRoot(FI->getIndex(), TypeMap); 4678 } 4679 return 0; 4680 case Intrinsic::gcread: 4681 case Intrinsic::gcwrite: 4682 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4683 return 0; 4684 case Intrinsic::flt_rounds: 4685 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4686 return 0; 4687 case Intrinsic::trap: 4688 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4689 return 0; 4690 case Intrinsic::uadd_with_overflow: 4691 return implVisitAluOverflow(I, ISD::UADDO); 4692 case Intrinsic::sadd_with_overflow: 4693 return implVisitAluOverflow(I, ISD::SADDO); 4694 case Intrinsic::usub_with_overflow: 4695 return implVisitAluOverflow(I, ISD::USUBO); 4696 case Intrinsic::ssub_with_overflow: 4697 return implVisitAluOverflow(I, ISD::SSUBO); 4698 case Intrinsic::umul_with_overflow: 4699 return implVisitAluOverflow(I, ISD::UMULO); 4700 case Intrinsic::smul_with_overflow: 4701 return implVisitAluOverflow(I, ISD::SMULO); 4702 4703 case Intrinsic::prefetch: { 4704 SDValue Ops[4]; 4705 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 4706 Ops[0] = getRoot(); 4707 Ops[1] = getValue(I.getArgOperand(0)); 4708 Ops[2] = getValue(I.getArgOperand(1)); 4709 Ops[3] = getValue(I.getArgOperand(2)); 4710 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 4711 DAG.getVTList(MVT::Other), 4712 &Ops[0], 4, 4713 EVT::getIntegerVT(*Context, 8), 4714 MachinePointerInfo(I.getArgOperand(0)), 4715 0, /* align */ 4716 false, /* volatile */ 4717 rw==0, /* read */ 4718 rw==1)); /* write */ 4719 return 0; 4720 } 4721 case Intrinsic::memory_barrier: { 4722 SDValue Ops[6]; 4723 Ops[0] = getRoot(); 4724 for (int x = 1; x < 6; ++x) 4725 Ops[x] = getValue(I.getArgOperand(x - 1)); 4726 4727 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4728 return 0; 4729 } 4730 case Intrinsic::atomic_cmp_swap: { 4731 SDValue Root = getRoot(); 4732 SDValue L = 4733 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4734 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 4735 Root, 4736 getValue(I.getArgOperand(0)), 4737 getValue(I.getArgOperand(1)), 4738 getValue(I.getArgOperand(2)), 4739 MachinePointerInfo(I.getArgOperand(0))); 4740 setValue(&I, L); 4741 DAG.setRoot(L.getValue(1)); 4742 return 0; 4743 } 4744 case Intrinsic::atomic_load_add: 4745 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4746 case Intrinsic::atomic_load_sub: 4747 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4748 case Intrinsic::atomic_load_or: 4749 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4750 case Intrinsic::atomic_load_xor: 4751 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4752 case Intrinsic::atomic_load_and: 4753 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4754 case Intrinsic::atomic_load_nand: 4755 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4756 case Intrinsic::atomic_load_max: 4757 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4758 case Intrinsic::atomic_load_min: 4759 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4760 case Intrinsic::atomic_load_umin: 4761 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4762 case Intrinsic::atomic_load_umax: 4763 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4764 case Intrinsic::atomic_swap: 4765 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4766 4767 case Intrinsic::invariant_start: 4768 case Intrinsic::lifetime_start: 4769 // Discard region information. 4770 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4771 return 0; 4772 case Intrinsic::invariant_end: 4773 case Intrinsic::lifetime_end: 4774 // Discard region information. 4775 return 0; 4776 } 4777} 4778 4779void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 4780 bool isTailCall, 4781 MachineBasicBlock *LandingPad) { 4782 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4783 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4784 const Type *RetTy = FTy->getReturnType(); 4785 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4786 MCSymbol *BeginLabel = 0; 4787 4788 TargetLowering::ArgListTy Args; 4789 TargetLowering::ArgListEntry Entry; 4790 Args.reserve(CS.arg_size()); 4791 4792 // Check whether the function can return without sret-demotion. 4793 SmallVector<ISD::OutputArg, 4> Outs; 4794 SmallVector<uint64_t, 4> Offsets; 4795 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4796 Outs, TLI, &Offsets); 4797 4798 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4799 FTy->isVarArg(), Outs, FTy->getContext()); 4800 4801 SDValue DemoteStackSlot; 4802 int DemoteStackIdx = -100; 4803 4804 if (!CanLowerReturn) { 4805 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4806 FTy->getReturnType()); 4807 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4808 FTy->getReturnType()); 4809 MachineFunction &MF = DAG.getMachineFunction(); 4810 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4811 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4812 4813 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 4814 Entry.Node = DemoteStackSlot; 4815 Entry.Ty = StackSlotPtrType; 4816 Entry.isSExt = false; 4817 Entry.isZExt = false; 4818 Entry.isInReg = false; 4819 Entry.isSRet = true; 4820 Entry.isNest = false; 4821 Entry.isByVal = false; 4822 Entry.Alignment = Align; 4823 Args.push_back(Entry); 4824 RetTy = Type::getVoidTy(FTy->getContext()); 4825 } 4826 4827 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4828 i != e; ++i) { 4829 SDValue ArgNode = getValue(*i); 4830 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 4831 4832 unsigned attrInd = i - CS.arg_begin() + 1; 4833 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4834 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4835 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4836 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4837 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4838 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4839 Entry.Alignment = CS.getParamAlignment(attrInd); 4840 Args.push_back(Entry); 4841 } 4842 4843 if (LandingPad) { 4844 // Insert a label before the invoke call to mark the try range. This can be 4845 // used to detect deletion of the invoke via the MachineModuleInfo. 4846 BeginLabel = MMI.getContext().CreateTempSymbol(); 4847 4848 // For SjLj, keep track of which landing pads go with which invokes 4849 // so as to maintain the ordering of pads in the LSDA. 4850 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 4851 if (CallSiteIndex) { 4852 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4853 // Now that the call site is handled, stop tracking it. 4854 MMI.setCurrentCallSite(0); 4855 } 4856 4857 // Both PendingLoads and PendingExports must be flushed here; 4858 // this call might not return. 4859 (void)getRoot(); 4860 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4861 } 4862 4863 // Check if target-independent constraints permit a tail call here. 4864 // Target-dependent constraints are checked within TLI.LowerCallTo. 4865 if (isTailCall && 4866 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4867 isTailCall = false; 4868 4869 // If there's a possibility that fast-isel has already selected some amount 4870 // of the current basic block, don't emit a tail call. 4871 if (isTailCall && EnableFastISel) 4872 isTailCall = false; 4873 4874 std::pair<SDValue,SDValue> Result = 4875 TLI.LowerCallTo(getRoot(), RetTy, 4876 CS.paramHasAttr(0, Attribute::SExt), 4877 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4878 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4879 CS.getCallingConv(), 4880 isTailCall, 4881 !CS.getInstruction()->use_empty(), 4882 Callee, Args, DAG, getCurDebugLoc()); 4883 assert((isTailCall || Result.second.getNode()) && 4884 "Non-null chain expected with non-tail call!"); 4885 assert((Result.second.getNode() || !Result.first.getNode()) && 4886 "Null value expected with tail call!"); 4887 if (Result.first.getNode()) { 4888 setValue(CS.getInstruction(), Result.first); 4889 } else if (!CanLowerReturn && Result.second.getNode()) { 4890 // The instruction result is the result of loading from the 4891 // hidden sret parameter. 4892 SmallVector<EVT, 1> PVTs; 4893 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 4894 4895 ComputeValueVTs(TLI, PtrRetTy, PVTs); 4896 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 4897 EVT PtrVT = PVTs[0]; 4898 unsigned NumValues = Outs.size(); 4899 SmallVector<SDValue, 4> Values(NumValues); 4900 SmallVector<SDValue, 4> Chains(NumValues); 4901 4902 for (unsigned i = 0; i < NumValues; ++i) { 4903 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 4904 DemoteStackSlot, 4905 DAG.getConstant(Offsets[i], PtrVT)); 4906 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 4907 Add, 4908 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 4909 false, false, 1); 4910 Values[i] = L; 4911 Chains[i] = L.getValue(1); 4912 } 4913 4914 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 4915 MVT::Other, &Chains[0], NumValues); 4916 PendingLoads.push_back(Chain); 4917 4918 // Collect the legal value parts into potentially illegal values 4919 // that correspond to the original function's return values. 4920 SmallVector<EVT, 4> RetTys; 4921 RetTy = FTy->getReturnType(); 4922 ComputeValueVTs(TLI, RetTy, RetTys); 4923 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4924 SmallVector<SDValue, 4> ReturnValues; 4925 unsigned CurReg = 0; 4926 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4927 EVT VT = RetTys[I]; 4928 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 4929 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 4930 4931 SDValue ReturnValue = 4932 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 4933 RegisterVT, VT, AssertOp); 4934 ReturnValues.push_back(ReturnValue); 4935 CurReg += NumRegs; 4936 } 4937 4938 setValue(CS.getInstruction(), 4939 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 4940 DAG.getVTList(&RetTys[0], RetTys.size()), 4941 &ReturnValues[0], ReturnValues.size())); 4942 4943 } 4944 4945 // As a special case, a null chain means that a tail call has been emitted and 4946 // the DAG root is already updated. 4947 if (Result.second.getNode()) 4948 DAG.setRoot(Result.second); 4949 else 4950 HasTailCall = true; 4951 4952 if (LandingPad) { 4953 // Insert a label at the end of the invoke call to mark the try range. This 4954 // can be used to detect deletion of the invoke via the MachineModuleInfo. 4955 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 4956 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 4957 4958 // Inform MachineModuleInfo of range. 4959 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 4960 } 4961} 4962 4963/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 4964/// value is equal or not-equal to zero. 4965static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 4966 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 4967 UI != E; ++UI) { 4968 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 4969 if (IC->isEquality()) 4970 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 4971 if (C->isNullValue()) 4972 continue; 4973 // Unknown instruction. 4974 return false; 4975 } 4976 return true; 4977} 4978 4979static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 4980 const Type *LoadTy, 4981 SelectionDAGBuilder &Builder) { 4982 4983 // Check to see if this load can be trivially constant folded, e.g. if the 4984 // input is from a string literal. 4985 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 4986 // Cast pointer to the type we really want to load. 4987 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 4988 PointerType::getUnqual(LoadTy)); 4989 4990 if (const Constant *LoadCst = 4991 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 4992 Builder.TD)) 4993 return Builder.getValue(LoadCst); 4994 } 4995 4996 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 4997 // still constant memory, the input chain can be the entry node. 4998 SDValue Root; 4999 bool ConstantMemory = false; 5000 5001 // Do not serialize (non-volatile) loads of constant memory with anything. 5002 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5003 Root = Builder.DAG.getEntryNode(); 5004 ConstantMemory = true; 5005 } else { 5006 // Do not serialize non-volatile loads against each other. 5007 Root = Builder.DAG.getRoot(); 5008 } 5009 5010 SDValue Ptr = Builder.getValue(PtrVal); 5011 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5012 Ptr, MachinePointerInfo(PtrVal), 5013 false /*volatile*/, 5014 false /*nontemporal*/, 1 /* align=1 */); 5015 5016 if (!ConstantMemory) 5017 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5018 return LoadVal; 5019} 5020 5021 5022/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5023/// If so, return true and lower it, otherwise return false and it will be 5024/// lowered like a normal call. 5025bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5026 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5027 if (I.getNumArgOperands() != 3) 5028 return false; 5029 5030 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5031 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5032 !I.getArgOperand(2)->getType()->isIntegerTy() || 5033 !I.getType()->isIntegerTy()) 5034 return false; 5035 5036 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5037 5038 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5039 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5040 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5041 bool ActuallyDoIt = true; 5042 MVT LoadVT; 5043 const Type *LoadTy; 5044 switch (Size->getZExtValue()) { 5045 default: 5046 LoadVT = MVT::Other; 5047 LoadTy = 0; 5048 ActuallyDoIt = false; 5049 break; 5050 case 2: 5051 LoadVT = MVT::i16; 5052 LoadTy = Type::getInt16Ty(Size->getContext()); 5053 break; 5054 case 4: 5055 LoadVT = MVT::i32; 5056 LoadTy = Type::getInt32Ty(Size->getContext()); 5057 break; 5058 case 8: 5059 LoadVT = MVT::i64; 5060 LoadTy = Type::getInt64Ty(Size->getContext()); 5061 break; 5062 /* 5063 case 16: 5064 LoadVT = MVT::v4i32; 5065 LoadTy = Type::getInt32Ty(Size->getContext()); 5066 LoadTy = VectorType::get(LoadTy, 4); 5067 break; 5068 */ 5069 } 5070 5071 // This turns into unaligned loads. We only do this if the target natively 5072 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5073 // we'll only produce a small number of byte loads. 5074 5075 // Require that we can find a legal MVT, and only do this if the target 5076 // supports unaligned loads of that type. Expanding into byte loads would 5077 // bloat the code. 5078 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5079 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5080 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5081 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5082 ActuallyDoIt = false; 5083 } 5084 5085 if (ActuallyDoIt) { 5086 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5087 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5088 5089 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5090 ISD::SETNE); 5091 EVT CallVT = TLI.getValueType(I.getType(), true); 5092 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5093 return true; 5094 } 5095 } 5096 5097 5098 return false; 5099} 5100 5101 5102void SelectionDAGBuilder::visitCall(const CallInst &I) { 5103 // Handle inline assembly differently. 5104 if (isa<InlineAsm>(I.getCalledValue())) { 5105 visitInlineAsm(&I); 5106 return; 5107 } 5108 5109 // See if any floating point values are being passed to this function. This is 5110 // used to emit an undefined reference to fltused on Windows. 5111 const FunctionType *FT = 5112 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5113 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5114 if (FT->isVarArg() && 5115 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5116 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5117 const Type* T = I.getArgOperand(i)->getType(); 5118 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T); 5119 i != e; ++i) { 5120 if (!i->isFloatingPointTy()) continue; 5121 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5122 break; 5123 } 5124 } 5125 } 5126 5127 const char *RenameFn = 0; 5128 if (Function *F = I.getCalledFunction()) { 5129 if (F->isDeclaration()) { 5130 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5131 if (unsigned IID = II->getIntrinsicID(F)) { 5132 RenameFn = visitIntrinsicCall(I, IID); 5133 if (!RenameFn) 5134 return; 5135 } 5136 } 5137 if (unsigned IID = F->getIntrinsicID()) { 5138 RenameFn = visitIntrinsicCall(I, IID); 5139 if (!RenameFn) 5140 return; 5141 } 5142 } 5143 5144 // Check for well-known libc/libm calls. If the function is internal, it 5145 // can't be a library call. 5146 if (!F->hasLocalLinkage() && F->hasName()) { 5147 StringRef Name = F->getName(); 5148 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5149 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5150 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5151 I.getType() == I.getArgOperand(0)->getType() && 5152 I.getType() == I.getArgOperand(1)->getType()) { 5153 SDValue LHS = getValue(I.getArgOperand(0)); 5154 SDValue RHS = getValue(I.getArgOperand(1)); 5155 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5156 LHS.getValueType(), LHS, RHS)); 5157 return; 5158 } 5159 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5160 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5161 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5162 I.getType() == I.getArgOperand(0)->getType()) { 5163 SDValue Tmp = getValue(I.getArgOperand(0)); 5164 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5165 Tmp.getValueType(), Tmp)); 5166 return; 5167 } 5168 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5169 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5170 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5171 I.getType() == I.getArgOperand(0)->getType() && 5172 I.onlyReadsMemory()) { 5173 SDValue Tmp = getValue(I.getArgOperand(0)); 5174 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5175 Tmp.getValueType(), Tmp)); 5176 return; 5177 } 5178 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5179 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5180 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5181 I.getType() == I.getArgOperand(0)->getType() && 5182 I.onlyReadsMemory()) { 5183 SDValue Tmp = getValue(I.getArgOperand(0)); 5184 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5185 Tmp.getValueType(), Tmp)); 5186 return; 5187 } 5188 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5189 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5190 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5191 I.getType() == I.getArgOperand(0)->getType() && 5192 I.onlyReadsMemory()) { 5193 SDValue Tmp = getValue(I.getArgOperand(0)); 5194 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5195 Tmp.getValueType(), Tmp)); 5196 return; 5197 } 5198 } else if (Name == "memcmp") { 5199 if (visitMemCmpCall(I)) 5200 return; 5201 } 5202 } 5203 } 5204 5205 SDValue Callee; 5206 if (!RenameFn) 5207 Callee = getValue(I.getCalledValue()); 5208 else 5209 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5210 5211 // Check if we can potentially perform a tail call. More detailed checking is 5212 // be done within LowerCallTo, after more information about the call is known. 5213 LowerCallTo(&I, Callee, I.isTailCall()); 5214} 5215 5216namespace llvm { 5217 5218/// AsmOperandInfo - This contains information for each constraint that we are 5219/// lowering. 5220class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo : 5221 public TargetLowering::AsmOperandInfo { 5222public: 5223 /// CallOperand - If this is the result output operand or a clobber 5224 /// this is null, otherwise it is the incoming operand to the CallInst. 5225 /// This gets modified as the asm is processed. 5226 SDValue CallOperand; 5227 5228 /// AssignedRegs - If this is a register or register class operand, this 5229 /// contains the set of register corresponding to the operand. 5230 RegsForValue AssignedRegs; 5231 5232 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5233 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5234 } 5235 5236 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5237 /// busy in OutputRegs/InputRegs. 5238 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5239 std::set<unsigned> &OutputRegs, 5240 std::set<unsigned> &InputRegs, 5241 const TargetRegisterInfo &TRI) const { 5242 if (isOutReg) { 5243 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5244 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5245 } 5246 if (isInReg) { 5247 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5248 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5249 } 5250 } 5251 5252 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5253 /// corresponds to. If there is no Value* for this operand, it returns 5254 /// MVT::Other. 5255 EVT getCallOperandValEVT(LLVMContext &Context, 5256 const TargetLowering &TLI, 5257 const TargetData *TD) const { 5258 if (CallOperandVal == 0) return MVT::Other; 5259 5260 if (isa<BasicBlock>(CallOperandVal)) 5261 return TLI.getPointerTy(); 5262 5263 const llvm::Type *OpTy = CallOperandVal->getType(); 5264 5265 // If this is an indirect operand, the operand is a pointer to the 5266 // accessed type. 5267 if (isIndirect) { 5268 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5269 if (!PtrTy) 5270 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5271 OpTy = PtrTy->getElementType(); 5272 } 5273 5274 // If OpTy is not a single value, it may be a struct/union that we 5275 // can tile with integers. 5276 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5277 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5278 switch (BitSize) { 5279 default: break; 5280 case 1: 5281 case 8: 5282 case 16: 5283 case 32: 5284 case 64: 5285 case 128: 5286 OpTy = IntegerType::get(Context, BitSize); 5287 break; 5288 } 5289 } 5290 5291 return TLI.getValueType(OpTy, true); 5292 } 5293 5294private: 5295 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5296 /// specified set. 5297 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5298 const TargetRegisterInfo &TRI) { 5299 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5300 Regs.insert(Reg); 5301 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5302 for (; *Aliases; ++Aliases) 5303 Regs.insert(*Aliases); 5304 } 5305}; 5306 5307typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5308 5309} // end llvm namespace. 5310 5311/// isAllocatableRegister - If the specified register is safe to allocate, 5312/// i.e. it isn't a stack pointer or some other special register, return the 5313/// register class for the register. Otherwise, return null. 5314static const TargetRegisterClass * 5315isAllocatableRegister(unsigned Reg, MachineFunction &MF, 5316 const TargetLowering &TLI, 5317 const TargetRegisterInfo *TRI) { 5318 EVT FoundVT = MVT::Other; 5319 const TargetRegisterClass *FoundRC = 0; 5320 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 5321 E = TRI->regclass_end(); RCI != E; ++RCI) { 5322 EVT ThisVT = MVT::Other; 5323 5324 const TargetRegisterClass *RC = *RCI; 5325 // If none of the value types for this register class are valid, we 5326 // can't use it. For example, 64-bit reg classes on 32-bit targets. 5327 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 5328 I != E; ++I) { 5329 if (TLI.isTypeLegal(*I)) { 5330 // If we have already found this register in a different register class, 5331 // choose the one with the largest VT specified. For example, on 5332 // PowerPC, we favor f64 register classes over f32. 5333 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 5334 ThisVT = *I; 5335 break; 5336 } 5337 } 5338 } 5339 5340 if (ThisVT == MVT::Other) continue; 5341 5342 // NOTE: This isn't ideal. In particular, this might allocate the 5343 // frame pointer in functions that need it (due to them not being taken 5344 // out of allocation, because a variable sized allocation hasn't been seen 5345 // yet). This is a slight code pessimization, but should still work. 5346 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 5347 E = RC->allocation_order_end(MF); I != E; ++I) 5348 if (*I == Reg) { 5349 // We found a matching register class. Keep looking at others in case 5350 // we find one with larger registers that this physreg is also in. 5351 FoundRC = RC; 5352 FoundVT = ThisVT; 5353 break; 5354 } 5355 } 5356 return FoundRC; 5357} 5358 5359/// GetRegistersForValue - Assign registers (virtual or physical) for the 5360/// specified operand. We prefer to assign virtual registers, to allow the 5361/// register allocator to handle the assignment process. However, if the asm 5362/// uses features that we can't model on machineinstrs, we have SDISel do the 5363/// allocation. This produces generally horrible, but correct, code. 5364/// 5365/// OpInfo describes the operand. 5366/// Input and OutputRegs are the set of already allocated physical registers. 5367/// 5368void SelectionDAGBuilder:: 5369GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, 5370 std::set<unsigned> &OutputRegs, 5371 std::set<unsigned> &InputRegs) { 5372 LLVMContext &Context = FuncInfo.Fn->getContext(); 5373 5374 // Compute whether this value requires an input register, an output register, 5375 // or both. 5376 bool isOutReg = false; 5377 bool isInReg = false; 5378 switch (OpInfo.Type) { 5379 case InlineAsm::isOutput: 5380 isOutReg = true; 5381 5382 // If there is an input constraint that matches this, we need to reserve 5383 // the input register so no other inputs allocate to it. 5384 isInReg = OpInfo.hasMatchingInput(); 5385 break; 5386 case InlineAsm::isInput: 5387 isInReg = true; 5388 isOutReg = false; 5389 break; 5390 case InlineAsm::isClobber: 5391 isOutReg = true; 5392 isInReg = true; 5393 break; 5394 } 5395 5396 5397 MachineFunction &MF = DAG.getMachineFunction(); 5398 SmallVector<unsigned, 4> Regs; 5399 5400 // If this is a constraint for a single physreg, or a constraint for a 5401 // register class, find it. 5402 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5403 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5404 OpInfo.ConstraintVT); 5405 5406 unsigned NumRegs = 1; 5407 if (OpInfo.ConstraintVT != MVT::Other) { 5408 // If this is a FP input in an integer register (or visa versa) insert a bit 5409 // cast of the input value. More generally, handle any case where the input 5410 // value disagrees with the register class we plan to stick this in. 5411 if (OpInfo.Type == InlineAsm::isInput && 5412 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5413 // Try to convert to the first EVT that the reg class contains. If the 5414 // types are identical size, use a bitcast to convert (e.g. two differing 5415 // vector types). 5416 EVT RegVT = *PhysReg.second->vt_begin(); 5417 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5418 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 5419 RegVT, OpInfo.CallOperand); 5420 OpInfo.ConstraintVT = RegVT; 5421 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5422 // If the input is a FP value and we want it in FP registers, do a 5423 // bitcast to the corresponding integer type. This turns an f64 value 5424 // into i64, which can be passed with two i32 values on a 32-bit 5425 // machine. 5426 RegVT = EVT::getIntegerVT(Context, 5427 OpInfo.ConstraintVT.getSizeInBits()); 5428 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 5429 RegVT, OpInfo.CallOperand); 5430 OpInfo.ConstraintVT = RegVT; 5431 } 5432 } 5433 5434 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5435 } 5436 5437 EVT RegVT; 5438 EVT ValueVT = OpInfo.ConstraintVT; 5439 5440 // If this is a constraint for a specific physical register, like {r17}, 5441 // assign it now. 5442 if (unsigned AssignedReg = PhysReg.first) { 5443 const TargetRegisterClass *RC = PhysReg.second; 5444 if (OpInfo.ConstraintVT == MVT::Other) 5445 ValueVT = *RC->vt_begin(); 5446 5447 // Get the actual register value type. This is important, because the user 5448 // may have asked for (e.g.) the AX register in i32 type. We need to 5449 // remember that AX is actually i16 to get the right extension. 5450 RegVT = *RC->vt_begin(); 5451 5452 // This is a explicit reference to a physical register. 5453 Regs.push_back(AssignedReg); 5454 5455 // If this is an expanded reference, add the rest of the regs to Regs. 5456 if (NumRegs != 1) { 5457 TargetRegisterClass::iterator I = RC->begin(); 5458 for (; *I != AssignedReg; ++I) 5459 assert(I != RC->end() && "Didn't find reg!"); 5460 5461 // Already added the first reg. 5462 --NumRegs; ++I; 5463 for (; NumRegs; --NumRegs, ++I) { 5464 assert(I != RC->end() && "Ran out of registers to allocate!"); 5465 Regs.push_back(*I); 5466 } 5467 } 5468 5469 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5470 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5471 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5472 return; 5473 } 5474 5475 // Otherwise, if this was a reference to an LLVM register class, create vregs 5476 // for this reference. 5477 if (const TargetRegisterClass *RC = PhysReg.second) { 5478 RegVT = *RC->vt_begin(); 5479 if (OpInfo.ConstraintVT == MVT::Other) 5480 ValueVT = RegVT; 5481 5482 // Create the appropriate number of virtual registers. 5483 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5484 for (; NumRegs; --NumRegs) 5485 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5486 5487 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5488 return; 5489 } 5490 5491 // This is a reference to a register class that doesn't directly correspond 5492 // to an LLVM register class. Allocate NumRegs consecutive, available, 5493 // registers from the class. 5494 std::vector<unsigned> RegClassRegs 5495 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 5496 OpInfo.ConstraintVT); 5497 5498 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5499 unsigned NumAllocated = 0; 5500 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 5501 unsigned Reg = RegClassRegs[i]; 5502 // See if this register is available. 5503 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 5504 (isInReg && InputRegs.count(Reg))) { // Already used. 5505 // Make sure we find consecutive registers. 5506 NumAllocated = 0; 5507 continue; 5508 } 5509 5510 // Check to see if this register is allocatable (i.e. don't give out the 5511 // stack pointer). 5512 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); 5513 if (!RC) { // Couldn't allocate this register. 5514 // Reset NumAllocated to make sure we return consecutive registers. 5515 NumAllocated = 0; 5516 continue; 5517 } 5518 5519 // Okay, this register is good, we can use it. 5520 ++NumAllocated; 5521 5522 // If we allocated enough consecutive registers, succeed. 5523 if (NumAllocated == NumRegs) { 5524 unsigned RegStart = (i-NumAllocated)+1; 5525 unsigned RegEnd = i+1; 5526 // Mark all of the allocated registers used. 5527 for (unsigned i = RegStart; i != RegEnd; ++i) 5528 Regs.push_back(RegClassRegs[i]); 5529 5530 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 5531 OpInfo.ConstraintVT); 5532 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5533 return; 5534 } 5535 } 5536 5537 // Otherwise, we couldn't allocate enough registers for this. 5538} 5539 5540/// visitInlineAsm - Handle a call to an InlineAsm object. 5541/// 5542void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5543 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5544 5545 /// ConstraintOperands - Information about all of the constraints. 5546 SDISelAsmOperandInfoVector ConstraintOperands; 5547 5548 std::set<unsigned> OutputRegs, InputRegs; 5549 5550 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS); 5551 bool hasMemory = false; 5552 5553 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5554 unsigned ResNo = 0; // ResNo - The result number of the next output. 5555 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5556 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5557 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5558 5559 EVT OpVT = MVT::Other; 5560 5561 // Compute the value type for each operand. 5562 switch (OpInfo.Type) { 5563 case InlineAsm::isOutput: 5564 // Indirect outputs just consume an argument. 5565 if (OpInfo.isIndirect) { 5566 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5567 break; 5568 } 5569 5570 // The return value of the call is this value. As such, there is no 5571 // corresponding argument. 5572 assert(!CS.getType()->isVoidTy() && 5573 "Bad inline asm!"); 5574 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5575 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5576 } else { 5577 assert(ResNo == 0 && "Asm only has one result!"); 5578 OpVT = TLI.getValueType(CS.getType()); 5579 } 5580 ++ResNo; 5581 break; 5582 case InlineAsm::isInput: 5583 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5584 break; 5585 case InlineAsm::isClobber: 5586 // Nothing to do. 5587 break; 5588 } 5589 5590 // If this is an input or an indirect output, process the call argument. 5591 // BasicBlocks are labels, currently appearing only in asm's. 5592 if (OpInfo.CallOperandVal) { 5593 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5594 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5595 } else { 5596 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5597 } 5598 5599 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5600 } 5601 5602 OpInfo.ConstraintVT = OpVT; 5603 5604 // Indirect operand accesses access memory. 5605 if (OpInfo.isIndirect) 5606 hasMemory = true; 5607 else { 5608 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5609 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]); 5610 if (CType == TargetLowering::C_Memory) { 5611 hasMemory = true; 5612 break; 5613 } 5614 } 5615 } 5616 } 5617 5618 SDValue Chain, Flag; 5619 5620 // We won't need to flush pending loads if this asm doesn't touch 5621 // memory and is nonvolatile. 5622 if (hasMemory || IA->hasSideEffects()) 5623 Chain = getRoot(); 5624 else 5625 Chain = DAG.getRoot(); 5626 5627 // Second pass over the constraints: compute which constraint option to use 5628 // and assign registers to constraints that want a specific physreg. 5629 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5630 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5631 5632 // If this is an output operand with a matching input operand, look up the 5633 // matching input. If their types mismatch, e.g. one is an integer, the 5634 // other is floating point, or their sizes are different, flag it as an 5635 // error. 5636 if (OpInfo.hasMatchingInput()) { 5637 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5638 5639 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5640 if ((OpInfo.ConstraintVT.isInteger() != 5641 Input.ConstraintVT.isInteger()) || 5642 (OpInfo.ConstraintVT.getSizeInBits() != 5643 Input.ConstraintVT.getSizeInBits())) { 5644 report_fatal_error("Unsupported asm: input constraint" 5645 " with a matching output constraint of" 5646 " incompatible type!"); 5647 } 5648 Input.ConstraintVT = OpInfo.ConstraintVT; 5649 } 5650 } 5651 5652 // Compute the constraint code and ConstraintType to use. 5653 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5654 5655 // If this is a memory input, and if the operand is not indirect, do what we 5656 // need to to provide an address for the memory input. 5657 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5658 !OpInfo.isIndirect) { 5659 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && 5660 "Can only indirectify direct input operands!"); 5661 5662 // Memory operands really want the address of the value. If we don't have 5663 // an indirect input, put it in the constpool if we can, otherwise spill 5664 // it to a stack slot. 5665 5666 // If the operand is a float, integer, or vector constant, spill to a 5667 // constant pool entry to get its address. 5668 const Value *OpVal = OpInfo.CallOperandVal; 5669 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5670 isa<ConstantVector>(OpVal)) { 5671 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5672 TLI.getPointerTy()); 5673 } else { 5674 // Otherwise, create a stack slot and emit a store to it before the 5675 // asm. 5676 const Type *Ty = OpVal->getType(); 5677 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5678 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5679 MachineFunction &MF = DAG.getMachineFunction(); 5680 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5681 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5682 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5683 OpInfo.CallOperand, StackSlot, 5684 MachinePointerInfo::getFixedStack(SSFI), 5685 false, false, 0); 5686 OpInfo.CallOperand = StackSlot; 5687 } 5688 5689 // There is no longer a Value* corresponding to this operand. 5690 OpInfo.CallOperandVal = 0; 5691 5692 // It is now an indirect operand. 5693 OpInfo.isIndirect = true; 5694 } 5695 5696 // If this constraint is for a specific register, allocate it before 5697 // anything else. 5698 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5699 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5700 } 5701 5702 // Second pass - Loop over all of the operands, assigning virtual or physregs 5703 // to register class operands. 5704 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5705 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5706 5707 // C_Register operands have already been allocated, Other/Memory don't need 5708 // to be. 5709 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5710 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5711 } 5712 5713 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5714 std::vector<SDValue> AsmNodeOperands; 5715 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5716 AsmNodeOperands.push_back( 5717 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5718 TLI.getPointerTy())); 5719 5720 // If we have a !srcloc metadata node associated with it, we want to attach 5721 // this to the ultimately generated inline asm machineinstr. To do this, we 5722 // pass in the third operand as this (potentially null) inline asm MDNode. 5723 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5724 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5725 5726 // Remember the HasSideEffect and AlignStack bits as operand 3. 5727 unsigned ExtraInfo = 0; 5728 if (IA->hasSideEffects()) 5729 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 5730 if (IA->isAlignStack()) 5731 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 5732 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 5733 TLI.getPointerTy())); 5734 5735 // Loop over all of the inputs, copying the operand values into the 5736 // appropriate registers and processing the output regs. 5737 RegsForValue RetValRegs; 5738 5739 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5740 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5741 5742 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5743 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5744 5745 switch (OpInfo.Type) { 5746 case InlineAsm::isOutput: { 5747 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5748 OpInfo.ConstraintType != TargetLowering::C_Register) { 5749 // Memory output, or 'other' output (e.g. 'X' constraint). 5750 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5751 5752 // Add information to the INLINEASM node to know about this output. 5753 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5754 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5755 TLI.getPointerTy())); 5756 AsmNodeOperands.push_back(OpInfo.CallOperand); 5757 break; 5758 } 5759 5760 // Otherwise, this is a register or register class output. 5761 5762 // Copy the output from the appropriate register. Find a register that 5763 // we can use. 5764 if (OpInfo.AssignedRegs.Regs.empty()) 5765 report_fatal_error("Couldn't allocate output reg for constraint '" + 5766 Twine(OpInfo.ConstraintCode) + "'!"); 5767 5768 // If this is an indirect operand, store through the pointer after the 5769 // asm. 5770 if (OpInfo.isIndirect) { 5771 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5772 OpInfo.CallOperandVal)); 5773 } else { 5774 // This is the result value of the call. 5775 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5776 // Concatenate this output onto the outputs list. 5777 RetValRegs.append(OpInfo.AssignedRegs); 5778 } 5779 5780 // Add information to the INLINEASM node to know that this register is 5781 // set. 5782 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5783 InlineAsm::Kind_RegDefEarlyClobber : 5784 InlineAsm::Kind_RegDef, 5785 false, 5786 0, 5787 DAG, 5788 AsmNodeOperands); 5789 break; 5790 } 5791 case InlineAsm::isInput: { 5792 SDValue InOperandVal = OpInfo.CallOperand; 5793 5794 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5795 // If this is required to match an output register we have already set, 5796 // just use its register. 5797 unsigned OperandNo = OpInfo.getMatchedOperand(); 5798 5799 // Scan until we find the definition we already emitted of this operand. 5800 // When we find it, create a RegsForValue operand. 5801 unsigned CurOp = InlineAsm::Op_FirstOperand; 5802 for (; OperandNo; --OperandNo) { 5803 // Advance to the next operand. 5804 unsigned OpFlag = 5805 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5806 assert((InlineAsm::isRegDefKind(OpFlag) || 5807 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5808 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5809 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5810 } 5811 5812 unsigned OpFlag = 5813 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5814 if (InlineAsm::isRegDefKind(OpFlag) || 5815 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5816 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5817 if (OpInfo.isIndirect) { 5818 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5819 LLVMContext &Ctx = *DAG.getContext(); 5820 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5821 " don't know how to handle tied " 5822 "indirect register inputs"); 5823 } 5824 5825 RegsForValue MatchedRegs; 5826 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5827 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5828 MatchedRegs.RegVTs.push_back(RegVT); 5829 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5830 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5831 i != e; ++i) 5832 MatchedRegs.Regs.push_back 5833 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5834 5835 // Use the produced MatchedRegs object to 5836 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5837 Chain, &Flag); 5838 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 5839 true, OpInfo.getMatchedOperand(), 5840 DAG, AsmNodeOperands); 5841 break; 5842 } 5843 5844 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 5845 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 5846 "Unexpected number of operands"); 5847 // Add information to the INLINEASM node to know about this input. 5848 // See InlineAsm.h isUseOperandTiedToDef. 5849 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 5850 OpInfo.getMatchedOperand()); 5851 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5852 TLI.getPointerTy())); 5853 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5854 break; 5855 } 5856 5857 // Treat indirect 'X' constraint as memory. 5858 if (OpInfo.ConstraintType == TargetLowering::C_Other && 5859 OpInfo.isIndirect) 5860 OpInfo.ConstraintType = TargetLowering::C_Memory; 5861 5862 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5863 std::vector<SDValue> Ops; 5864 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 5865 Ops, DAG); 5866 if (Ops.empty()) 5867 report_fatal_error("Invalid operand for inline asm constraint '" + 5868 Twine(OpInfo.ConstraintCode) + "'!"); 5869 5870 // Add information to the INLINEASM node to know about this input. 5871 unsigned ResOpType = 5872 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 5873 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5874 TLI.getPointerTy())); 5875 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5876 break; 5877 } 5878 5879 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5880 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5881 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5882 "Memory operands expect pointer values"); 5883 5884 // Add information to the INLINEASM node to know about this input. 5885 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5886 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5887 TLI.getPointerTy())); 5888 AsmNodeOperands.push_back(InOperandVal); 5889 break; 5890 } 5891 5892 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5893 OpInfo.ConstraintType == TargetLowering::C_Register) && 5894 "Unknown constraint type!"); 5895 assert(!OpInfo.isIndirect && 5896 "Don't know how to handle indirect register inputs yet!"); 5897 5898 // Copy the input into the appropriate registers. 5899 if (OpInfo.AssignedRegs.Regs.empty() || 5900 !OpInfo.AssignedRegs.areValueTypesLegal(TLI)) 5901 report_fatal_error("Couldn't allocate input reg for constraint '" + 5902 Twine(OpInfo.ConstraintCode) + "'!"); 5903 5904 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5905 Chain, &Flag); 5906 5907 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 5908 DAG, AsmNodeOperands); 5909 break; 5910 } 5911 case InlineAsm::isClobber: { 5912 // Add the clobbered value to the operand list, so that the register 5913 // allocator is aware that the physreg got clobbered. 5914 if (!OpInfo.AssignedRegs.Regs.empty()) 5915 OpInfo.AssignedRegs.AddInlineAsmOperands( 5916 InlineAsm::Kind_RegDefEarlyClobber, 5917 false, 0, DAG, 5918 AsmNodeOperands); 5919 break; 5920 } 5921 } 5922 } 5923 5924 // Finish up input operands. Set the input chain and add the flag last. 5925 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 5926 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5927 5928 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5929 DAG.getVTList(MVT::Other, MVT::Glue), 5930 &AsmNodeOperands[0], AsmNodeOperands.size()); 5931 Flag = Chain.getValue(1); 5932 5933 // If this asm returns a register value, copy the result from that register 5934 // and set it as the value of the call. 5935 if (!RetValRegs.Regs.empty()) { 5936 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5937 Chain, &Flag); 5938 5939 // FIXME: Why don't we do this for inline asms with MRVs? 5940 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5941 EVT ResultType = TLI.getValueType(CS.getType()); 5942 5943 // If any of the results of the inline asm is a vector, it may have the 5944 // wrong width/num elts. This can happen for register classes that can 5945 // contain multiple different value types. The preg or vreg allocated may 5946 // not have the same VT as was expected. Convert it to the right type 5947 // with bit_convert. 5948 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5949 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 5950 ResultType, Val); 5951 5952 } else if (ResultType != Val.getValueType() && 5953 ResultType.isInteger() && Val.getValueType().isInteger()) { 5954 // If a result value was tied to an input value, the computed result may 5955 // have a wider width than the expected result. Extract the relevant 5956 // portion. 5957 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 5958 } 5959 5960 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 5961 } 5962 5963 setValue(CS.getInstruction(), Val); 5964 // Don't need to use this as a chain in this case. 5965 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 5966 return; 5967 } 5968 5969 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 5970 5971 // Process indirect outputs, first output all of the flagged copies out of 5972 // physregs. 5973 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 5974 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 5975 const Value *Ptr = IndirectStoresToEmit[i].second; 5976 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5977 Chain, &Flag); 5978 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 5979 } 5980 5981 // Emit the non-flagged stores from the physregs. 5982 SmallVector<SDValue, 8> OutChains; 5983 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 5984 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 5985 StoresToEmit[i].first, 5986 getValue(StoresToEmit[i].second), 5987 MachinePointerInfo(StoresToEmit[i].second), 5988 false, false, 0); 5989 OutChains.push_back(Val); 5990 } 5991 5992 if (!OutChains.empty()) 5993 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 5994 &OutChains[0], OutChains.size()); 5995 5996 DAG.setRoot(Chain); 5997} 5998 5999void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6000 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6001 MVT::Other, getRoot(), 6002 getValue(I.getArgOperand(0)), 6003 DAG.getSrcValue(I.getArgOperand(0)))); 6004} 6005 6006void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6007 const TargetData &TD = *TLI.getTargetData(); 6008 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6009 getRoot(), getValue(I.getOperand(0)), 6010 DAG.getSrcValue(I.getOperand(0)), 6011 TD.getABITypeAlignment(I.getType())); 6012 setValue(&I, V); 6013 DAG.setRoot(V.getValue(1)); 6014} 6015 6016void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6017 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6018 MVT::Other, getRoot(), 6019 getValue(I.getArgOperand(0)), 6020 DAG.getSrcValue(I.getArgOperand(0)))); 6021} 6022 6023void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6024 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6025 MVT::Other, getRoot(), 6026 getValue(I.getArgOperand(0)), 6027 getValue(I.getArgOperand(1)), 6028 DAG.getSrcValue(I.getArgOperand(0)), 6029 DAG.getSrcValue(I.getArgOperand(1)))); 6030} 6031 6032/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6033/// implementation, which just calls LowerCall. 6034/// FIXME: When all targets are 6035/// migrated to using LowerCall, this hook should be integrated into SDISel. 6036std::pair<SDValue, SDValue> 6037TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 6038 bool RetSExt, bool RetZExt, bool isVarArg, 6039 bool isInreg, unsigned NumFixedArgs, 6040 CallingConv::ID CallConv, bool isTailCall, 6041 bool isReturnValueUsed, 6042 SDValue Callee, 6043 ArgListTy &Args, SelectionDAG &DAG, 6044 DebugLoc dl) const { 6045 // Handle all of the outgoing arguments. 6046 SmallVector<ISD::OutputArg, 32> Outs; 6047 SmallVector<SDValue, 32> OutVals; 6048 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6049 SmallVector<EVT, 4> ValueVTs; 6050 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6051 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6052 Value != NumValues; ++Value) { 6053 EVT VT = ValueVTs[Value]; 6054 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6055 SDValue Op = SDValue(Args[i].Node.getNode(), 6056 Args[i].Node.getResNo() + Value); 6057 ISD::ArgFlagsTy Flags; 6058 unsigned OriginalAlignment = 6059 getTargetData()->getABITypeAlignment(ArgTy); 6060 6061 if (Args[i].isZExt) 6062 Flags.setZExt(); 6063 if (Args[i].isSExt) 6064 Flags.setSExt(); 6065 if (Args[i].isInReg) 6066 Flags.setInReg(); 6067 if (Args[i].isSRet) 6068 Flags.setSRet(); 6069 if (Args[i].isByVal) { 6070 Flags.setByVal(); 6071 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 6072 const Type *ElementTy = Ty->getElementType(); 6073 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 6074 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy); 6075 // For ByVal, alignment should come from FE. BE will guess if this 6076 // info is not there but there are cases it cannot get right. 6077 if (Args[i].Alignment) 6078 FrameAlign = Args[i].Alignment; 6079 Flags.setByValAlign(FrameAlign); 6080 Flags.setByValSize(FrameSize); 6081 } 6082 if (Args[i].isNest) 6083 Flags.setNest(); 6084 Flags.setOrigAlign(OriginalAlignment); 6085 6086 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6087 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6088 SmallVector<SDValue, 4> Parts(NumParts); 6089 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6090 6091 if (Args[i].isSExt) 6092 ExtendKind = ISD::SIGN_EXTEND; 6093 else if (Args[i].isZExt) 6094 ExtendKind = ISD::ZERO_EXTEND; 6095 6096 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6097 PartVT, ExtendKind); 6098 6099 for (unsigned j = 0; j != NumParts; ++j) { 6100 // if it isn't first piece, alignment must be 1 6101 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6102 i < NumFixedArgs); 6103 if (NumParts > 1 && j == 0) 6104 MyFlags.Flags.setSplit(); 6105 else if (j != 0) 6106 MyFlags.Flags.setOrigAlign(1); 6107 6108 Outs.push_back(MyFlags); 6109 OutVals.push_back(Parts[j]); 6110 } 6111 } 6112 } 6113 6114 // Handle the incoming return values from the call. 6115 SmallVector<ISD::InputArg, 32> Ins; 6116 SmallVector<EVT, 4> RetTys; 6117 ComputeValueVTs(*this, RetTy, RetTys); 6118 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6119 EVT VT = RetTys[I]; 6120 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6121 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6122 for (unsigned i = 0; i != NumRegs; ++i) { 6123 ISD::InputArg MyFlags; 6124 MyFlags.VT = RegisterVT.getSimpleVT(); 6125 MyFlags.Used = isReturnValueUsed; 6126 if (RetSExt) 6127 MyFlags.Flags.setSExt(); 6128 if (RetZExt) 6129 MyFlags.Flags.setZExt(); 6130 if (isInreg) 6131 MyFlags.Flags.setInReg(); 6132 Ins.push_back(MyFlags); 6133 } 6134 } 6135 6136 SmallVector<SDValue, 4> InVals; 6137 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6138 Outs, OutVals, Ins, dl, DAG, InVals); 6139 6140 // Verify that the target's LowerCall behaved as expected. 6141 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6142 "LowerCall didn't return a valid chain!"); 6143 assert((!isTailCall || InVals.empty()) && 6144 "LowerCall emitted a return value for a tail call!"); 6145 assert((isTailCall || InVals.size() == Ins.size()) && 6146 "LowerCall didn't emit the correct number of values!"); 6147 6148 // For a tail call, the return value is merely live-out and there aren't 6149 // any nodes in the DAG representing it. Return a special value to 6150 // indicate that a tail call has been emitted and no more Instructions 6151 // should be processed in the current block. 6152 if (isTailCall) { 6153 DAG.setRoot(Chain); 6154 return std::make_pair(SDValue(), SDValue()); 6155 } 6156 6157 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6158 assert(InVals[i].getNode() && 6159 "LowerCall emitted a null value!"); 6160 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6161 "LowerCall emitted a value with the wrong type!"); 6162 }); 6163 6164 // Collect the legal value parts into potentially illegal values 6165 // that correspond to the original function's return values. 6166 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6167 if (RetSExt) 6168 AssertOp = ISD::AssertSext; 6169 else if (RetZExt) 6170 AssertOp = ISD::AssertZext; 6171 SmallVector<SDValue, 4> ReturnValues; 6172 unsigned CurReg = 0; 6173 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6174 EVT VT = RetTys[I]; 6175 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6176 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6177 6178 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6179 NumRegs, RegisterVT, VT, 6180 AssertOp)); 6181 CurReg += NumRegs; 6182 } 6183 6184 // For a function returning void, there is no return value. We can't create 6185 // such a node, so we just return a null return value in that case. In 6186 // that case, nothing will actualy look at the value. 6187 if (ReturnValues.empty()) 6188 return std::make_pair(SDValue(), Chain); 6189 6190 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6191 DAG.getVTList(&RetTys[0], RetTys.size()), 6192 &ReturnValues[0], ReturnValues.size()); 6193 return std::make_pair(Res, Chain); 6194} 6195 6196void TargetLowering::LowerOperationWrapper(SDNode *N, 6197 SmallVectorImpl<SDValue> &Results, 6198 SelectionDAG &DAG) const { 6199 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6200 if (Res.getNode()) 6201 Results.push_back(Res); 6202} 6203 6204SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6205 llvm_unreachable("LowerOperation not implemented for this target!"); 6206 return SDValue(); 6207} 6208 6209void 6210SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6211 SDValue Op = getNonRegisterValue(V); 6212 assert((Op.getOpcode() != ISD::CopyFromReg || 6213 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6214 "Copy from a reg to the same reg!"); 6215 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6216 6217 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6218 SDValue Chain = DAG.getEntryNode(); 6219 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6220 PendingExports.push_back(Chain); 6221} 6222 6223#include "llvm/CodeGen/SelectionDAGISel.h" 6224 6225void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6226 // If this is the entry block, emit arguments. 6227 const Function &F = *LLVMBB->getParent(); 6228 SelectionDAG &DAG = SDB->DAG; 6229 DebugLoc dl = SDB->getCurDebugLoc(); 6230 const TargetData *TD = TLI.getTargetData(); 6231 SmallVector<ISD::InputArg, 16> Ins; 6232 6233 // Check whether the function can return without sret-demotion. 6234 SmallVector<ISD::OutputArg, 4> Outs; 6235 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6236 Outs, TLI); 6237 6238 if (!FuncInfo->CanLowerReturn) { 6239 // Put in an sret pointer parameter before all the other parameters. 6240 SmallVector<EVT, 1> ValueVTs; 6241 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6242 6243 // NOTE: Assuming that a pointer will never break down to more than one VT 6244 // or one register. 6245 ISD::ArgFlagsTy Flags; 6246 Flags.setSRet(); 6247 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6248 ISD::InputArg RetArg(Flags, RegisterVT, true); 6249 Ins.push_back(RetArg); 6250 } 6251 6252 // Set up the incoming argument description vector. 6253 unsigned Idx = 1; 6254 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6255 I != E; ++I, ++Idx) { 6256 SmallVector<EVT, 4> ValueVTs; 6257 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6258 bool isArgValueUsed = !I->use_empty(); 6259 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6260 Value != NumValues; ++Value) { 6261 EVT VT = ValueVTs[Value]; 6262 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6263 ISD::ArgFlagsTy Flags; 6264 unsigned OriginalAlignment = 6265 TD->getABITypeAlignment(ArgTy); 6266 6267 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6268 Flags.setZExt(); 6269 if (F.paramHasAttr(Idx, Attribute::SExt)) 6270 Flags.setSExt(); 6271 if (F.paramHasAttr(Idx, Attribute::InReg)) 6272 Flags.setInReg(); 6273 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6274 Flags.setSRet(); 6275 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6276 Flags.setByVal(); 6277 const PointerType *Ty = cast<PointerType>(I->getType()); 6278 const Type *ElementTy = Ty->getElementType(); 6279 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6280 unsigned FrameSize = TD->getTypeAllocSize(ElementTy); 6281 // For ByVal, alignment should be passed from FE. BE will guess if 6282 // this info is not there but there are cases it cannot get right. 6283 if (F.getParamAlignment(Idx)) 6284 FrameAlign = F.getParamAlignment(Idx); 6285 Flags.setByValAlign(FrameAlign); 6286 Flags.setByValSize(FrameSize); 6287 } 6288 if (F.paramHasAttr(Idx, Attribute::Nest)) 6289 Flags.setNest(); 6290 Flags.setOrigAlign(OriginalAlignment); 6291 6292 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6293 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6294 for (unsigned i = 0; i != NumRegs; ++i) { 6295 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6296 if (NumRegs > 1 && i == 0) 6297 MyFlags.Flags.setSplit(); 6298 // if it isn't first piece, alignment must be 1 6299 else if (i > 0) 6300 MyFlags.Flags.setOrigAlign(1); 6301 Ins.push_back(MyFlags); 6302 } 6303 } 6304 } 6305 6306 // Call the target to set up the argument values. 6307 SmallVector<SDValue, 8> InVals; 6308 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6309 F.isVarArg(), Ins, 6310 dl, DAG, InVals); 6311 6312 // Verify that the target's LowerFormalArguments behaved as expected. 6313 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6314 "LowerFormalArguments didn't return a valid chain!"); 6315 assert(InVals.size() == Ins.size() && 6316 "LowerFormalArguments didn't emit the correct number of values!"); 6317 DEBUG({ 6318 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6319 assert(InVals[i].getNode() && 6320 "LowerFormalArguments emitted a null value!"); 6321 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6322 "LowerFormalArguments emitted a value with the wrong type!"); 6323 } 6324 }); 6325 6326 // Update the DAG with the new chain value resulting from argument lowering. 6327 DAG.setRoot(NewRoot); 6328 6329 // Set up the argument values. 6330 unsigned i = 0; 6331 Idx = 1; 6332 if (!FuncInfo->CanLowerReturn) { 6333 // Create a virtual register for the sret pointer, and put in a copy 6334 // from the sret argument into it. 6335 SmallVector<EVT, 1> ValueVTs; 6336 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6337 EVT VT = ValueVTs[0]; 6338 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6339 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6340 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6341 RegVT, VT, AssertOp); 6342 6343 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6344 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6345 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6346 FuncInfo->DemoteRegister = SRetReg; 6347 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6348 SRetReg, ArgValue); 6349 DAG.setRoot(NewRoot); 6350 6351 // i indexes lowered arguments. Bump it past the hidden sret argument. 6352 // Idx indexes LLVM arguments. Don't touch it. 6353 ++i; 6354 } 6355 6356 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6357 ++I, ++Idx) { 6358 SmallVector<SDValue, 4> ArgValues; 6359 SmallVector<EVT, 4> ValueVTs; 6360 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6361 unsigned NumValues = ValueVTs.size(); 6362 6363 // If this argument is unused then remember its value. It is used to generate 6364 // debugging information. 6365 if (I->use_empty() && NumValues) 6366 SDB->setUnusedArgValue(I, InVals[i]); 6367 6368 for (unsigned Value = 0; Value != NumValues; ++Value) { 6369 EVT VT = ValueVTs[Value]; 6370 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6371 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6372 6373 if (!I->use_empty()) { 6374 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6375 if (F.paramHasAttr(Idx, Attribute::SExt)) 6376 AssertOp = ISD::AssertSext; 6377 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6378 AssertOp = ISD::AssertZext; 6379 6380 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6381 NumParts, PartVT, VT, 6382 AssertOp)); 6383 } 6384 6385 i += NumParts; 6386 } 6387 6388 // Note down frame index for byval arguments. 6389 if (I->hasByValAttr() && !ArgValues.empty()) 6390 if (FrameIndexSDNode *FI = 6391 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6392 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6393 6394 if (!I->use_empty()) { 6395 SDValue Res; 6396 if (!ArgValues.empty()) 6397 Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6398 SDB->getCurDebugLoc()); 6399 SDB->setValue(I, Res); 6400 6401 // If this argument is live outside of the entry block, insert a copy from 6402 // whereever we got it to the vreg that other BB's will reference it as. 6403 SDB->CopyToExportRegsIfNeeded(I); 6404 } 6405 } 6406 6407 assert(i == InVals.size() && "Argument register count mismatch!"); 6408 6409 // Finally, if the target has anything special to do, allow it to do so. 6410 // FIXME: this should insert code into the DAG! 6411 EmitFunctionEntryCode(); 6412} 6413 6414/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6415/// ensure constants are generated when needed. Remember the virtual registers 6416/// that need to be added to the Machine PHI nodes as input. We cannot just 6417/// directly add them, because expansion might result in multiple MBB's for one 6418/// BB. As such, the start of the BB might correspond to a different MBB than 6419/// the end. 6420/// 6421void 6422SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6423 const TerminatorInst *TI = LLVMBB->getTerminator(); 6424 6425 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6426 6427 // Check successor nodes' PHI nodes that expect a constant to be available 6428 // from this block. 6429 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6430 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6431 if (!isa<PHINode>(SuccBB->begin())) continue; 6432 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6433 6434 // If this terminator has multiple identical successors (common for 6435 // switches), only handle each succ once. 6436 if (!SuccsHandled.insert(SuccMBB)) continue; 6437 6438 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6439 6440 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6441 // nodes and Machine PHI nodes, but the incoming operands have not been 6442 // emitted yet. 6443 for (BasicBlock::const_iterator I = SuccBB->begin(); 6444 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6445 // Ignore dead phi's. 6446 if (PN->use_empty()) continue; 6447 6448 unsigned Reg; 6449 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6450 6451 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6452 unsigned &RegOut = ConstantsOut[C]; 6453 if (RegOut == 0) { 6454 RegOut = FuncInfo.CreateRegs(C->getType()); 6455 CopyValueToVirtualRegister(C, RegOut); 6456 } 6457 Reg = RegOut; 6458 } else { 6459 DenseMap<const Value *, unsigned>::iterator I = 6460 FuncInfo.ValueMap.find(PHIOp); 6461 if (I != FuncInfo.ValueMap.end()) 6462 Reg = I->second; 6463 else { 6464 assert(isa<AllocaInst>(PHIOp) && 6465 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6466 "Didn't codegen value into a register!??"); 6467 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6468 CopyValueToVirtualRegister(PHIOp, Reg); 6469 } 6470 } 6471 6472 if (!EnableFastISel) 6473 FuncInfo.PHISrcToDestMap[Reg] = FuncInfo.ValueMap[PN]; 6474 6475 // Remember that this register needs to added to the machine PHI node as 6476 // the input for this MBB. 6477 SmallVector<EVT, 4> ValueVTs; 6478 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6479 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6480 EVT VT = ValueVTs[vti]; 6481 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6482 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6483 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6484 Reg += NumRegisters; 6485 } 6486 } 6487 } 6488 ConstantsOut.clear(); 6489} 6490