SelectionDAGBuilder.cpp revision 9d0796a0e06e3b44bbdd696259f80066c285d9c3
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/SmallSet.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/ConstantFolding.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/Module.h" 32#include "llvm/CodeGen/Analysis.h" 33#include "llvm/CodeGen/FastISel.h" 34#include "llvm/CodeGen/FunctionLoweringInfo.h" 35#include "llvm/CodeGen/GCStrategy.h" 36#include "llvm/CodeGen/GCMetadata.h" 37#include "llvm/CodeGen/MachineFunction.h" 38#include "llvm/CodeGen/MachineFrameInfo.h" 39#include "llvm/CodeGen/MachineInstrBuilder.h" 40#include "llvm/CodeGen/MachineJumpTableInfo.h" 41#include "llvm/CodeGen/MachineModuleInfo.h" 42#include "llvm/CodeGen/MachineRegisterInfo.h" 43#include "llvm/CodeGen/PseudoSourceValue.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Analysis/DebugInfo.h" 46#include "llvm/Target/TargetRegisterInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/CommandLine.h" 55#include "llvm/Support/Debug.h" 56#include "llvm/Support/ErrorHandling.h" 57#include "llvm/Support/MathExtras.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62/// LimitFloatPrecision - Generate low-precision inline sequences for 63/// some float libcalls (6, 8 or 12 bits). 64static unsigned LimitFloatPrecision; 65 66static cl::opt<unsigned, true> 67LimitFPPrecision("limit-float-precision", 68 cl::desc("Generate low-precision inline sequences " 69 "for some float libcalls"), 70 cl::location(LimitFloatPrecision), 71 cl::init(0)); 72 73static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 74 const SDValue *Parts, unsigned NumParts, 75 EVT PartVT, EVT ValueVT); 76 77/// getCopyFromParts - Create a value that contains the specified legal parts 78/// combined into the value they represent. If the parts combine to a type 79/// larger then ValueVT then AssertOp can be used to specify whether the extra 80/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 81/// (ISD::AssertSext). 82static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 83 const SDValue *Parts, 84 unsigned NumParts, EVT PartVT, EVT ValueVT, 85 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 86 if (ValueVT.isVector()) 87 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 88 89 assert(NumParts > 0 && "No parts to assemble!"); 90 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 91 SDValue Val = Parts[0]; 92 93 if (NumParts > 1) { 94 // Assemble the value from multiple parts. 95 if (ValueVT.isInteger()) { 96 unsigned PartBits = PartVT.getSizeInBits(); 97 unsigned ValueBits = ValueVT.getSizeInBits(); 98 99 // Assemble the power of 2 part. 100 unsigned RoundParts = NumParts & (NumParts - 1) ? 101 1 << Log2_32(NumParts) : NumParts; 102 unsigned RoundBits = PartBits * RoundParts; 103 EVT RoundVT = RoundBits == ValueBits ? 104 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 105 SDValue Lo, Hi; 106 107 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 108 109 if (RoundParts > 2) { 110 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 111 PartVT, HalfVT); 112 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 113 RoundParts / 2, PartVT, HalfVT); 114 } else { 115 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[0]); 116 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[1]); 117 } 118 119 if (TLI.isBigEndian()) 120 std::swap(Lo, Hi); 121 122 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 123 124 if (RoundParts < NumParts) { 125 // Assemble the trailing non-power-of-2 part. 126 unsigned OddParts = NumParts - RoundParts; 127 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 128 Hi = getCopyFromParts(DAG, DL, 129 Parts + RoundParts, OddParts, PartVT, OddVT); 130 131 // Combine the round and odd parts. 132 Lo = Val; 133 if (TLI.isBigEndian()) 134 std::swap(Lo, Hi); 135 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 136 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 137 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 138 DAG.getConstant(Lo.getValueType().getSizeInBits(), 139 TLI.getPointerTy())); 140 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 141 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 142 } 143 } else if (PartVT.isFloatingPoint()) { 144 // FP split into multiple FP parts (for ppcf128) 145 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 146 "Unexpected split"); 147 SDValue Lo, Hi; 148 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[0]); 149 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[1]); 150 if (TLI.isBigEndian()) 151 std::swap(Lo, Hi); 152 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 153 } else { 154 // FP split into integer parts (soft fp) 155 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 156 !PartVT.isVector() && "Unexpected split"); 157 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 158 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 159 } 160 } 161 162 // There is now one part, held in Val. Correct it to match ValueVT. 163 PartVT = Val.getValueType(); 164 165 if (PartVT == ValueVT) 166 return Val; 167 168 if (PartVT.isInteger() && ValueVT.isInteger()) { 169 if (ValueVT.bitsLT(PartVT)) { 170 // For a truncate, see if we have any information to 171 // indicate whether the truncated bits will always be 172 // zero or sign-extension. 173 if (AssertOp != ISD::DELETED_NODE) 174 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 175 DAG.getValueType(ValueVT)); 176 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 177 } 178 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 179 } 180 181 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 182 // FP_ROUND's are always exact here. 183 if (ValueVT.bitsLT(Val.getValueType())) 184 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 185 DAG.getIntPtrConstant(1)); 186 187 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 188 } 189 190 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 191 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val); 192 193 llvm_unreachable("Unknown mismatch!"); 194 return SDValue(); 195} 196 197/// getCopyFromParts - Create a value that contains the specified legal parts 198/// combined into the value they represent. If the parts combine to a type 199/// larger then ValueVT then AssertOp can be used to specify whether the extra 200/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 201/// (ISD::AssertSext). 202static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 203 const SDValue *Parts, unsigned NumParts, 204 EVT PartVT, EVT ValueVT) { 205 assert(ValueVT.isVector() && "Not a vector value"); 206 assert(NumParts > 0 && "No parts to assemble!"); 207 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 208 SDValue Val = Parts[0]; 209 210 // Handle a multi-element vector. 211 if (NumParts > 1) { 212 EVT IntermediateVT, RegisterVT; 213 unsigned NumIntermediates; 214 unsigned NumRegs = 215 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 216 NumIntermediates, RegisterVT); 217 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 218 NumParts = NumRegs; // Silence a compiler warning. 219 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 220 assert(RegisterVT == Parts[0].getValueType() && 221 "Part type doesn't match part!"); 222 223 // Assemble the parts into intermediate operands. 224 SmallVector<SDValue, 8> Ops(NumIntermediates); 225 if (NumIntermediates == NumParts) { 226 // If the register was not expanded, truncate or copy the value, 227 // as appropriate. 228 for (unsigned i = 0; i != NumParts; ++i) 229 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 230 PartVT, IntermediateVT); 231 } else if (NumParts > 0) { 232 // If the intermediate type was expanded, build the intermediate 233 // operands from the parts. 234 assert(NumParts % NumIntermediates == 0 && 235 "Must expand into a divisible number of parts!"); 236 unsigned Factor = NumParts / NumIntermediates; 237 for (unsigned i = 0; i != NumIntermediates; ++i) 238 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 239 PartVT, IntermediateVT); 240 } 241 242 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 243 // intermediate operands. 244 Val = DAG.getNode(IntermediateVT.isVector() ? 245 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 246 ValueVT, &Ops[0], NumIntermediates); 247 } 248 249 // There is now one part, held in Val. Correct it to match ValueVT. 250 PartVT = Val.getValueType(); 251 252 if (PartVT == ValueVT) 253 return Val; 254 255 if (PartVT.isVector()) { 256 // If the element type of the source/dest vectors are the same, but the 257 // parts vector has more elements than the value vector, then we have a 258 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 259 // elements we want. 260 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 261 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 262 "Cannot narrow, it would be a lossy transformation"); 263 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 264 DAG.getIntPtrConstant(0)); 265 } 266 267 // Vector/Vector bitcast. 268 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val); 269 } 270 271 assert(ValueVT.getVectorElementType() == PartVT && 272 ValueVT.getVectorNumElements() == 1 && 273 "Only trivial scalar-to-vector conversions should get here!"); 274 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 275} 276 277 278 279 280static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 281 SDValue Val, SDValue *Parts, unsigned NumParts, 282 EVT PartVT); 283 284/// getCopyToParts - Create a series of nodes that contain the specified value 285/// split into legal parts. If the parts contain more bits than Val, then, for 286/// integers, ExtendKind can be used to specify how to generate the extra bits. 287static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 288 SDValue Val, SDValue *Parts, unsigned NumParts, 289 EVT PartVT, 290 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 291 EVT ValueVT = Val.getValueType(); 292 293 // Handle the vector case separately. 294 if (ValueVT.isVector()) 295 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 296 297 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 298 unsigned PartBits = PartVT.getSizeInBits(); 299 unsigned OrigNumParts = NumParts; 300 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 301 302 if (NumParts == 0) 303 return; 304 305 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 306 if (PartVT == ValueVT) { 307 assert(NumParts == 1 && "No-op copy with multiple parts!"); 308 Parts[0] = Val; 309 return; 310 } 311 312 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 313 // If the parts cover more bits than the value has, promote the value. 314 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 315 assert(NumParts == 1 && "Do not know what to promote to!"); 316 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 317 } else { 318 assert(PartVT.isInteger() && ValueVT.isInteger() && 319 "Unknown mismatch!"); 320 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 321 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 322 } 323 } else if (PartBits == ValueVT.getSizeInBits()) { 324 // Different types of the same size. 325 assert(NumParts == 1 && PartVT != ValueVT); 326 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val); 327 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 328 // If the parts cover less bits than value has, truncate the value. 329 assert(PartVT.isInteger() && ValueVT.isInteger() && 330 "Unknown mismatch!"); 331 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 332 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 333 } 334 335 // The value may have changed - recompute ValueVT. 336 ValueVT = Val.getValueType(); 337 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 338 "Failed to tile the value with PartVT!"); 339 340 if (NumParts == 1) { 341 assert(PartVT == ValueVT && "Type conversion failed!"); 342 Parts[0] = Val; 343 return; 344 } 345 346 // Expand the value into multiple parts. 347 if (NumParts & (NumParts - 1)) { 348 // The number of parts is not a power of 2. Split off and copy the tail. 349 assert(PartVT.isInteger() && ValueVT.isInteger() && 350 "Do not know what to expand to!"); 351 unsigned RoundParts = 1 << Log2_32(NumParts); 352 unsigned RoundBits = RoundParts * PartBits; 353 unsigned OddParts = NumParts - RoundParts; 354 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 355 DAG.getIntPtrConstant(RoundBits)); 356 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 357 358 if (TLI.isBigEndian()) 359 // The odd parts were reversed by getCopyToParts - unreverse them. 360 std::reverse(Parts + RoundParts, Parts + NumParts); 361 362 NumParts = RoundParts; 363 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 364 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 365 } 366 367 // The number of parts is a power of 2. Repeatedly bisect the value using 368 // EXTRACT_ELEMENT. 369 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, DL, 370 EVT::getIntegerVT(*DAG.getContext(), 371 ValueVT.getSizeInBits()), 372 Val); 373 374 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 375 for (unsigned i = 0; i < NumParts; i += StepSize) { 376 unsigned ThisBits = StepSize * PartBits / 2; 377 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 378 SDValue &Part0 = Parts[i]; 379 SDValue &Part1 = Parts[i+StepSize/2]; 380 381 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 382 ThisVT, Part0, DAG.getIntPtrConstant(1)); 383 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 384 ThisVT, Part0, DAG.getIntPtrConstant(0)); 385 386 if (ThisBits == PartBits && ThisVT != PartVT) { 387 Part0 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part0); 388 Part1 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part1); 389 } 390 } 391 } 392 393 if (TLI.isBigEndian()) 394 std::reverse(Parts, Parts + OrigNumParts); 395} 396 397 398/// getCopyToPartsVector - Create a series of nodes that contain the specified 399/// value split into legal parts. 400static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 401 SDValue Val, SDValue *Parts, unsigned NumParts, 402 EVT PartVT) { 403 EVT ValueVT = Val.getValueType(); 404 assert(ValueVT.isVector() && "Not a vector"); 405 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 406 407 if (NumParts == 1) { 408 if (PartVT == ValueVT) { 409 // Nothing to do. 410 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 411 // Bitconvert vector->vector case. 412 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val); 413 } else if (PartVT.isVector() && 414 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&& 415 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 416 EVT ElementVT = PartVT.getVectorElementType(); 417 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 418 // undef elements. 419 SmallVector<SDValue, 16> Ops; 420 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 421 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 422 ElementVT, Val, DAG.getIntPtrConstant(i))); 423 424 for (unsigned i = ValueVT.getVectorNumElements(), 425 e = PartVT.getVectorNumElements(); i != e; ++i) 426 Ops.push_back(DAG.getUNDEF(ElementVT)); 427 428 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 429 430 // FIXME: Use CONCAT for 2x -> 4x. 431 432 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 433 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 434 } else { 435 // Vector -> scalar conversion. 436 assert(ValueVT.getVectorElementType() == PartVT && 437 ValueVT.getVectorNumElements() == 1 && 438 "Only trivial vector-to-scalar conversions should get here!"); 439 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 440 PartVT, Val, DAG.getIntPtrConstant(0)); 441 } 442 443 Parts[0] = Val; 444 return; 445 } 446 447 // Handle a multi-element vector. 448 EVT IntermediateVT, RegisterVT; 449 unsigned NumIntermediates; 450 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 451 IntermediateVT, NumIntermediates, RegisterVT); 452 unsigned NumElements = ValueVT.getVectorNumElements(); 453 454 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 455 NumParts = NumRegs; // Silence a compiler warning. 456 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 457 458 // Split the vector into intermediate operands. 459 SmallVector<SDValue, 8> Ops(NumIntermediates); 460 for (unsigned i = 0; i != NumIntermediates; ++i) { 461 if (IntermediateVT.isVector()) 462 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 463 IntermediateVT, Val, 464 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 465 else 466 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 467 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 468 } 469 470 // Split the intermediate operands into legal parts. 471 if (NumParts == NumIntermediates) { 472 // If the register was not expanded, promote or copy the value, 473 // as appropriate. 474 for (unsigned i = 0; i != NumParts; ++i) 475 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 476 } else if (NumParts > 0) { 477 // If the intermediate type was expanded, split each the value into 478 // legal parts. 479 assert(NumParts % NumIntermediates == 0 && 480 "Must expand into a divisible number of parts!"); 481 unsigned Factor = NumParts / NumIntermediates; 482 for (unsigned i = 0; i != NumIntermediates; ++i) 483 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 484 } 485} 486 487 488 489 490namespace { 491 /// RegsForValue - This struct represents the registers (physical or virtual) 492 /// that a particular set of values is assigned, and the type information 493 /// about the value. The most common situation is to represent one value at a 494 /// time, but struct or array values are handled element-wise as multiple 495 /// values. The splitting of aggregates is performed recursively, so that we 496 /// never have aggregate-typed registers. The values at this point do not 497 /// necessarily have legal types, so each value may require one or more 498 /// registers of some legal type. 499 /// 500 struct RegsForValue { 501 /// ValueVTs - The value types of the values, which may not be legal, and 502 /// may need be promoted or synthesized from one or more registers. 503 /// 504 SmallVector<EVT, 4> ValueVTs; 505 506 /// RegVTs - The value types of the registers. This is the same size as 507 /// ValueVTs and it records, for each value, what the type of the assigned 508 /// register or registers are. (Individual values are never synthesized 509 /// from more than one type of register.) 510 /// 511 /// With virtual registers, the contents of RegVTs is redundant with TLI's 512 /// getRegisterType member function, however when with physical registers 513 /// it is necessary to have a separate record of the types. 514 /// 515 SmallVector<EVT, 4> RegVTs; 516 517 /// Regs - This list holds the registers assigned to the values. 518 /// Each legal or promoted value requires one register, and each 519 /// expanded value requires multiple registers. 520 /// 521 SmallVector<unsigned, 4> Regs; 522 523 RegsForValue() {} 524 525 RegsForValue(const SmallVector<unsigned, 4> ®s, 526 EVT regvt, EVT valuevt) 527 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 528 529 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 530 unsigned Reg, const Type *Ty) { 531 ComputeValueVTs(tli, Ty, ValueVTs); 532 533 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 534 EVT ValueVT = ValueVTs[Value]; 535 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 536 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 537 for (unsigned i = 0; i != NumRegs; ++i) 538 Regs.push_back(Reg + i); 539 RegVTs.push_back(RegisterVT); 540 Reg += NumRegs; 541 } 542 } 543 544 /// areValueTypesLegal - Return true if types of all the values are legal. 545 bool areValueTypesLegal(const TargetLowering &TLI) { 546 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 547 EVT RegisterVT = RegVTs[Value]; 548 if (!TLI.isTypeLegal(RegisterVT)) 549 return false; 550 } 551 return true; 552 } 553 554 /// append - Add the specified values to this one. 555 void append(const RegsForValue &RHS) { 556 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 557 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 558 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 559 } 560 561 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 562 /// this value and returns the result as a ValueVTs value. This uses 563 /// Chain/Flag as the input and updates them for the output Chain/Flag. 564 /// If the Flag pointer is NULL, no flag is used. 565 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 566 DebugLoc dl, 567 SDValue &Chain, SDValue *Flag) const; 568 569 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 570 /// specified value into the registers specified by this object. This uses 571 /// Chain/Flag as the input and updates them for the output Chain/Flag. 572 /// If the Flag pointer is NULL, no flag is used. 573 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 574 SDValue &Chain, SDValue *Flag) const; 575 576 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 577 /// operand list. This adds the code marker, matching input operand index 578 /// (if applicable), and includes the number of values added into it. 579 void AddInlineAsmOperands(unsigned Kind, 580 bool HasMatching, unsigned MatchingIdx, 581 SelectionDAG &DAG, 582 std::vector<SDValue> &Ops) const; 583 }; 584} 585 586/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 587/// this value and returns the result as a ValueVT value. This uses 588/// Chain/Flag as the input and updates them for the output Chain/Flag. 589/// If the Flag pointer is NULL, no flag is used. 590SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 591 FunctionLoweringInfo &FuncInfo, 592 DebugLoc dl, 593 SDValue &Chain, SDValue *Flag) const { 594 // A Value with type {} or [0 x %t] needs no registers. 595 if (ValueVTs.empty()) 596 return SDValue(); 597 598 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 599 600 // Assemble the legal parts into the final values. 601 SmallVector<SDValue, 4> Values(ValueVTs.size()); 602 SmallVector<SDValue, 8> Parts; 603 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 604 // Copy the legal parts from the registers. 605 EVT ValueVT = ValueVTs[Value]; 606 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 607 EVT RegisterVT = RegVTs[Value]; 608 609 Parts.resize(NumRegs); 610 for (unsigned i = 0; i != NumRegs; ++i) { 611 SDValue P; 612 if (Flag == 0) { 613 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 614 } else { 615 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 616 *Flag = P.getValue(2); 617 } 618 619 Chain = P.getValue(1); 620 621 // If the source register was virtual and if we know something about it, 622 // add an assert node. 623 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && 624 RegisterVT.isInteger() && !RegisterVT.isVector()) { 625 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; 626 if (FuncInfo.LiveOutRegInfo.size() > SlotNo) { 627 const FunctionLoweringInfo::LiveOutInfo &LOI = 628 FuncInfo.LiveOutRegInfo[SlotNo]; 629 630 unsigned RegSize = RegisterVT.getSizeInBits(); 631 unsigned NumSignBits = LOI.NumSignBits; 632 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 633 634 // FIXME: We capture more information than the dag can represent. For 635 // now, just use the tightest assertzext/assertsext possible. 636 bool isSExt = true; 637 EVT FromVT(MVT::Other); 638 if (NumSignBits == RegSize) 639 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 640 else if (NumZeroBits >= RegSize-1) 641 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 642 else if (NumSignBits > RegSize-8) 643 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 644 else if (NumZeroBits >= RegSize-8) 645 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 646 else if (NumSignBits > RegSize-16) 647 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 648 else if (NumZeroBits >= RegSize-16) 649 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 650 else if (NumSignBits > RegSize-32) 651 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 652 else if (NumZeroBits >= RegSize-32) 653 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 654 655 if (FromVT != MVT::Other) 656 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 657 RegisterVT, P, DAG.getValueType(FromVT)); 658 } 659 } 660 661 Parts[i] = P; 662 } 663 664 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 665 NumRegs, RegisterVT, ValueVT); 666 Part += NumRegs; 667 Parts.clear(); 668 } 669 670 return DAG.getNode(ISD::MERGE_VALUES, dl, 671 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 672 &Values[0], ValueVTs.size()); 673} 674 675/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 676/// specified value into the registers specified by this object. This uses 677/// Chain/Flag as the input and updates them for the output Chain/Flag. 678/// If the Flag pointer is NULL, no flag is used. 679void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 680 SDValue &Chain, SDValue *Flag) const { 681 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 682 683 // Get the list of the values's legal parts. 684 unsigned NumRegs = Regs.size(); 685 SmallVector<SDValue, 8> Parts(NumRegs); 686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 687 EVT ValueVT = ValueVTs[Value]; 688 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 689 EVT RegisterVT = RegVTs[Value]; 690 691 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 692 &Parts[Part], NumParts, RegisterVT); 693 Part += NumParts; 694 } 695 696 // Copy the parts into the registers. 697 SmallVector<SDValue, 8> Chains(NumRegs); 698 for (unsigned i = 0; i != NumRegs; ++i) { 699 SDValue Part; 700 if (Flag == 0) { 701 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 702 } else { 703 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 704 *Flag = Part.getValue(1); 705 } 706 707 Chains[i] = Part.getValue(0); 708 } 709 710 if (NumRegs == 1 || Flag) 711 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 712 // flagged to it. That is the CopyToReg nodes and the user are considered 713 // a single scheduling unit. If we create a TokenFactor and return it as 714 // chain, then the TokenFactor is both a predecessor (operand) of the 715 // user as well as a successor (the TF operands are flagged to the user). 716 // c1, f1 = CopyToReg 717 // c2, f2 = CopyToReg 718 // c3 = TokenFactor c1, c2 719 // ... 720 // = op c3, ..., f2 721 Chain = Chains[NumRegs-1]; 722 else 723 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 724} 725 726/// AddInlineAsmOperands - Add this value to the specified inlineasm node 727/// operand list. This adds the code marker and includes the number of 728/// values added into it. 729void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 730 unsigned MatchingIdx, 731 SelectionDAG &DAG, 732 std::vector<SDValue> &Ops) const { 733 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 734 735 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 736 if (HasMatching) 737 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 738 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 739 Ops.push_back(Res); 740 741 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 742 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 743 EVT RegisterVT = RegVTs[Value]; 744 for (unsigned i = 0; i != NumRegs; ++i) { 745 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 746 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 747 } 748 } 749} 750 751void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 752 AA = &aa; 753 GFI = gfi; 754 TD = DAG.getTarget().getTargetData(); 755} 756 757/// clear - Clear out the current SelectionDAG and the associated 758/// state and prepare this SelectionDAGBuilder object to be used 759/// for a new block. This doesn't clear out information about 760/// additional blocks that are needed to complete switch lowering 761/// or PHI node updating; that information is cleared out as it is 762/// consumed. 763void SelectionDAGBuilder::clear() { 764 NodeMap.clear(); 765 UnusedArgNodeMap.clear(); 766 PendingLoads.clear(); 767 PendingExports.clear(); 768 DanglingDebugInfoMap.clear(); 769 CurDebugLoc = DebugLoc(); 770 HasTailCall = false; 771} 772 773/// getRoot - Return the current virtual root of the Selection DAG, 774/// flushing any PendingLoad items. This must be done before emitting 775/// a store or any other node that may need to be ordered after any 776/// prior load instructions. 777/// 778SDValue SelectionDAGBuilder::getRoot() { 779 if (PendingLoads.empty()) 780 return DAG.getRoot(); 781 782 if (PendingLoads.size() == 1) { 783 SDValue Root = PendingLoads[0]; 784 DAG.setRoot(Root); 785 PendingLoads.clear(); 786 return Root; 787 } 788 789 // Otherwise, we have to make a token factor node. 790 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 791 &PendingLoads[0], PendingLoads.size()); 792 PendingLoads.clear(); 793 DAG.setRoot(Root); 794 return Root; 795} 796 797/// getControlRoot - Similar to getRoot, but instead of flushing all the 798/// PendingLoad items, flush all the PendingExports items. It is necessary 799/// to do this before emitting a terminator instruction. 800/// 801SDValue SelectionDAGBuilder::getControlRoot() { 802 SDValue Root = DAG.getRoot(); 803 804 if (PendingExports.empty()) 805 return Root; 806 807 // Turn all of the CopyToReg chains into one factored node. 808 if (Root.getOpcode() != ISD::EntryToken) { 809 unsigned i = 0, e = PendingExports.size(); 810 for (; i != e; ++i) { 811 assert(PendingExports[i].getNode()->getNumOperands() > 1); 812 if (PendingExports[i].getNode()->getOperand(0) == Root) 813 break; // Don't add the root if we already indirectly depend on it. 814 } 815 816 if (i == e) 817 PendingExports.push_back(Root); 818 } 819 820 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 821 &PendingExports[0], 822 PendingExports.size()); 823 PendingExports.clear(); 824 DAG.setRoot(Root); 825 return Root; 826} 827 828void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 829 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 830 DAG.AssignOrdering(Node, SDNodeOrder); 831 832 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 833 AssignOrderingToNode(Node->getOperand(I).getNode()); 834} 835 836void SelectionDAGBuilder::visit(const Instruction &I) { 837 // Set up outgoing PHI node register values before emitting the terminator. 838 if (isa<TerminatorInst>(&I)) 839 HandlePHINodesInSuccessorBlocks(I.getParent()); 840 841 CurDebugLoc = I.getDebugLoc(); 842 843 visit(I.getOpcode(), I); 844 845 if (!isa<TerminatorInst>(&I) && !HasTailCall) 846 CopyToExportRegsIfNeeded(&I); 847 848 CurDebugLoc = DebugLoc(); 849} 850 851void SelectionDAGBuilder::visitPHI(const PHINode &) { 852 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 853} 854 855void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 856 // Note: this doesn't use InstVisitor, because it has to work with 857 // ConstantExpr's in addition to instructions. 858 switch (Opcode) { 859 default: llvm_unreachable("Unknown instruction type encountered!"); 860 // Build the switch statement using the Instruction.def file. 861#define HANDLE_INST(NUM, OPCODE, CLASS) \ 862 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 863#include "llvm/Instruction.def" 864 } 865 866 // Assign the ordering to the freshly created DAG nodes. 867 if (NodeMap.count(&I)) { 868 ++SDNodeOrder; 869 AssignOrderingToNode(getValue(&I).getNode()); 870 } 871} 872 873// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 874// generate the debug data structures now that we've seen its definition. 875void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 876 SDValue Val) { 877 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 878 if (DDI.getDI()) { 879 const DbgValueInst *DI = DDI.getDI(); 880 DebugLoc dl = DDI.getdl(); 881 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 882 MDNode *Variable = DI->getVariable(); 883 uint64_t Offset = DI->getOffset(); 884 SDDbgValue *SDV; 885 if (Val.getNode()) { 886 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 887 SDV = DAG.getDbgValue(Variable, Val.getNode(), 888 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 889 DAG.AddDbgValue(SDV, Val.getNode(), false); 890 } 891 } else { 892 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()), 893 Offset, dl, SDNodeOrder); 894 DAG.AddDbgValue(SDV, 0, false); 895 } 896 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 897 } 898} 899 900// getValue - Return an SDValue for the given Value. 901SDValue SelectionDAGBuilder::getValue(const Value *V) { 902 // If we already have an SDValue for this value, use it. It's important 903 // to do this first, so that we don't create a CopyFromReg if we already 904 // have a regular SDValue. 905 SDValue &N = NodeMap[V]; 906 if (N.getNode()) return N; 907 908 // If there's a virtual register allocated and initialized for this 909 // value, use it. 910 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 911 if (It != FuncInfo.ValueMap.end()) { 912 unsigned InReg = It->second; 913 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 914 SDValue Chain = DAG.getEntryNode(); 915 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 916 resolveDanglingDebugInfo(V, N); 917 return N; 918 } 919 920 // Otherwise create a new SDValue and remember it. 921 SDValue Val = getValueImpl(V); 922 NodeMap[V] = Val; 923 resolveDanglingDebugInfo(V, Val); 924 return Val; 925} 926 927/// getNonRegisterValue - Return an SDValue for the given Value, but 928/// don't look in FuncInfo.ValueMap for a virtual register. 929SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 930 // If we already have an SDValue for this value, use it. 931 SDValue &N = NodeMap[V]; 932 if (N.getNode()) return N; 933 934 // Otherwise create a new SDValue and remember it. 935 SDValue Val = getValueImpl(V); 936 NodeMap[V] = Val; 937 resolveDanglingDebugInfo(V, Val); 938 return Val; 939} 940 941/// getValueImpl - Helper function for getValue and getNonRegisterValue. 942/// Create an SDValue for the given value. 943SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 944 if (const Constant *C = dyn_cast<Constant>(V)) { 945 EVT VT = TLI.getValueType(V->getType(), true); 946 947 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 948 return DAG.getConstant(*CI, VT); 949 950 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 951 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 952 953 if (isa<ConstantPointerNull>(C)) 954 return DAG.getConstant(0, TLI.getPointerTy()); 955 956 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 957 return DAG.getConstantFP(*CFP, VT); 958 959 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 960 return DAG.getUNDEF(VT); 961 962 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 963 visit(CE->getOpcode(), *CE); 964 SDValue N1 = NodeMap[V]; 965 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 966 return N1; 967 } 968 969 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 970 SmallVector<SDValue, 4> Constants; 971 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 972 OI != OE; ++OI) { 973 SDNode *Val = getValue(*OI).getNode(); 974 // If the operand is an empty aggregate, there are no values. 975 if (!Val) continue; 976 // Add each leaf value from the operand to the Constants list 977 // to form a flattened list of all the values. 978 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 979 Constants.push_back(SDValue(Val, i)); 980 } 981 982 return DAG.getMergeValues(&Constants[0], Constants.size(), 983 getCurDebugLoc()); 984 } 985 986 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 987 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 988 "Unknown struct or array constant!"); 989 990 SmallVector<EVT, 4> ValueVTs; 991 ComputeValueVTs(TLI, C->getType(), ValueVTs); 992 unsigned NumElts = ValueVTs.size(); 993 if (NumElts == 0) 994 return SDValue(); // empty struct 995 SmallVector<SDValue, 4> Constants(NumElts); 996 for (unsigned i = 0; i != NumElts; ++i) { 997 EVT EltVT = ValueVTs[i]; 998 if (isa<UndefValue>(C)) 999 Constants[i] = DAG.getUNDEF(EltVT); 1000 else if (EltVT.isFloatingPoint()) 1001 Constants[i] = DAG.getConstantFP(0, EltVT); 1002 else 1003 Constants[i] = DAG.getConstant(0, EltVT); 1004 } 1005 1006 return DAG.getMergeValues(&Constants[0], NumElts, 1007 getCurDebugLoc()); 1008 } 1009 1010 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1011 return DAG.getBlockAddress(BA, VT); 1012 1013 const VectorType *VecTy = cast<VectorType>(V->getType()); 1014 unsigned NumElements = VecTy->getNumElements(); 1015 1016 // Now that we know the number and type of the elements, get that number of 1017 // elements into the Ops array based on what kind of constant it is. 1018 SmallVector<SDValue, 16> Ops; 1019 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1020 for (unsigned i = 0; i != NumElements; ++i) 1021 Ops.push_back(getValue(CP->getOperand(i))); 1022 } else { 1023 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1024 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1025 1026 SDValue Op; 1027 if (EltVT.isFloatingPoint()) 1028 Op = DAG.getConstantFP(0, EltVT); 1029 else 1030 Op = DAG.getConstant(0, EltVT); 1031 Ops.assign(NumElements, Op); 1032 } 1033 1034 // Create a BUILD_VECTOR node. 1035 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1036 VT, &Ops[0], Ops.size()); 1037 } 1038 1039 // If this is a static alloca, generate it as the frameindex instead of 1040 // computation. 1041 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1042 DenseMap<const AllocaInst*, int>::iterator SI = 1043 FuncInfo.StaticAllocaMap.find(AI); 1044 if (SI != FuncInfo.StaticAllocaMap.end()) 1045 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1046 } 1047 1048 // If this is an instruction which fast-isel has deferred, select it now. 1049 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1050 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1051 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1052 SDValue Chain = DAG.getEntryNode(); 1053 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1054 } 1055 1056 llvm_unreachable("Can't get register for value!"); 1057 return SDValue(); 1058} 1059 1060void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1061 SDValue Chain = getControlRoot(); 1062 SmallVector<ISD::OutputArg, 8> Outs; 1063 SmallVector<SDValue, 8> OutVals; 1064 1065 if (!FuncInfo.CanLowerReturn) { 1066 unsigned DemoteReg = FuncInfo.DemoteRegister; 1067 const Function *F = I.getParent()->getParent(); 1068 1069 // Emit a store of the return value through the virtual register. 1070 // Leave Outs empty so that LowerReturn won't try to load return 1071 // registers the usual way. 1072 SmallVector<EVT, 1> PtrValueVTs; 1073 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1074 PtrValueVTs); 1075 1076 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1077 SDValue RetOp = getValue(I.getOperand(0)); 1078 1079 SmallVector<EVT, 4> ValueVTs; 1080 SmallVector<uint64_t, 4> Offsets; 1081 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1082 unsigned NumValues = ValueVTs.size(); 1083 1084 SmallVector<SDValue, 4> Chains(NumValues); 1085 for (unsigned i = 0; i != NumValues; ++i) { 1086 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1087 RetPtr.getValueType(), RetPtr, 1088 DAG.getIntPtrConstant(Offsets[i])); 1089 Chains[i] = 1090 DAG.getStore(Chain, getCurDebugLoc(), 1091 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1092 Add, NULL, Offsets[i], false, false, 0); 1093 } 1094 1095 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1096 MVT::Other, &Chains[0], NumValues); 1097 } else if (I.getNumOperands() != 0) { 1098 SmallVector<EVT, 4> ValueVTs; 1099 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1100 unsigned NumValues = ValueVTs.size(); 1101 if (NumValues) { 1102 SDValue RetOp = getValue(I.getOperand(0)); 1103 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1104 EVT VT = ValueVTs[j]; 1105 1106 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1107 1108 const Function *F = I.getParent()->getParent(); 1109 if (F->paramHasAttr(0, Attribute::SExt)) 1110 ExtendKind = ISD::SIGN_EXTEND; 1111 else if (F->paramHasAttr(0, Attribute::ZExt)) 1112 ExtendKind = ISD::ZERO_EXTEND; 1113 1114 // FIXME: C calling convention requires the return type to be promoted 1115 // to at least 32-bit. But this is not necessary for non-C calling 1116 // conventions. The frontend should mark functions whose return values 1117 // require promoting with signext or zeroext attributes. 1118 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1119 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32); 1120 if (VT.bitsLT(MinVT)) 1121 VT = MinVT; 1122 } 1123 1124 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1125 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1126 SmallVector<SDValue, 4> Parts(NumParts); 1127 getCopyToParts(DAG, getCurDebugLoc(), 1128 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1129 &Parts[0], NumParts, PartVT, ExtendKind); 1130 1131 // 'inreg' on function refers to return value 1132 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1133 if (F->paramHasAttr(0, Attribute::InReg)) 1134 Flags.setInReg(); 1135 1136 // Propagate extension type if any 1137 if (F->paramHasAttr(0, Attribute::SExt)) 1138 Flags.setSExt(); 1139 else if (F->paramHasAttr(0, Attribute::ZExt)) 1140 Flags.setZExt(); 1141 1142 for (unsigned i = 0; i < NumParts; ++i) { 1143 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1144 /*isfixed=*/true)); 1145 OutVals.push_back(Parts[i]); 1146 } 1147 } 1148 } 1149 } 1150 1151 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1152 CallingConv::ID CallConv = 1153 DAG.getMachineFunction().getFunction()->getCallingConv(); 1154 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1155 Outs, OutVals, getCurDebugLoc(), DAG); 1156 1157 // Verify that the target's LowerReturn behaved as expected. 1158 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1159 "LowerReturn didn't return a valid chain!"); 1160 1161 // Update the DAG with the new chain value resulting from return lowering. 1162 DAG.setRoot(Chain); 1163} 1164 1165/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1166/// created for it, emit nodes to copy the value into the virtual 1167/// registers. 1168void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1169 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1170 if (VMI != FuncInfo.ValueMap.end()) { 1171 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1172 CopyValueToVirtualRegister(V, VMI->second); 1173 } 1174} 1175 1176/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1177/// the current basic block, add it to ValueMap now so that we'll get a 1178/// CopyTo/FromReg. 1179void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1180 // No need to export constants. 1181 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1182 1183 // Already exported? 1184 if (FuncInfo.isExportedInst(V)) return; 1185 1186 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1187 CopyValueToVirtualRegister(V, Reg); 1188} 1189 1190bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1191 const BasicBlock *FromBB) { 1192 // The operands of the setcc have to be in this block. We don't know 1193 // how to export them from some other block. 1194 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1195 // Can export from current BB. 1196 if (VI->getParent() == FromBB) 1197 return true; 1198 1199 // Is already exported, noop. 1200 return FuncInfo.isExportedInst(V); 1201 } 1202 1203 // If this is an argument, we can export it if the BB is the entry block or 1204 // if it is already exported. 1205 if (isa<Argument>(V)) { 1206 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1207 return true; 1208 1209 // Otherwise, can only export this if it is already exported. 1210 return FuncInfo.isExportedInst(V); 1211 } 1212 1213 // Otherwise, constants can always be exported. 1214 return true; 1215} 1216 1217static bool InBlock(const Value *V, const BasicBlock *BB) { 1218 if (const Instruction *I = dyn_cast<Instruction>(V)) 1219 return I->getParent() == BB; 1220 return true; 1221} 1222 1223/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1224/// This function emits a branch and is used at the leaves of an OR or an 1225/// AND operator tree. 1226/// 1227void 1228SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1229 MachineBasicBlock *TBB, 1230 MachineBasicBlock *FBB, 1231 MachineBasicBlock *CurBB, 1232 MachineBasicBlock *SwitchBB) { 1233 const BasicBlock *BB = CurBB->getBasicBlock(); 1234 1235 // If the leaf of the tree is a comparison, merge the condition into 1236 // the caseblock. 1237 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1238 // The operands of the cmp have to be in this block. We don't know 1239 // how to export them from some other block. If this is the first block 1240 // of the sequence, no exporting is needed. 1241 if (CurBB == SwitchBB || 1242 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1243 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1244 ISD::CondCode Condition; 1245 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1246 Condition = getICmpCondCode(IC->getPredicate()); 1247 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1248 Condition = getFCmpCondCode(FC->getPredicate()); 1249 } else { 1250 Condition = ISD::SETEQ; // silence warning. 1251 llvm_unreachable("Unknown compare instruction"); 1252 } 1253 1254 CaseBlock CB(Condition, BOp->getOperand(0), 1255 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1256 SwitchCases.push_back(CB); 1257 return; 1258 } 1259 } 1260 1261 // Create a CaseBlock record representing this branch. 1262 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1263 NULL, TBB, FBB, CurBB); 1264 SwitchCases.push_back(CB); 1265} 1266 1267/// FindMergedConditions - If Cond is an expression like 1268void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1269 MachineBasicBlock *TBB, 1270 MachineBasicBlock *FBB, 1271 MachineBasicBlock *CurBB, 1272 MachineBasicBlock *SwitchBB, 1273 unsigned Opc) { 1274 // If this node is not part of the or/and tree, emit it as a branch. 1275 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1276 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1277 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1278 BOp->getParent() != CurBB->getBasicBlock() || 1279 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1280 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1281 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1282 return; 1283 } 1284 1285 // Create TmpBB after CurBB. 1286 MachineFunction::iterator BBI = CurBB; 1287 MachineFunction &MF = DAG.getMachineFunction(); 1288 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1289 CurBB->getParent()->insert(++BBI, TmpBB); 1290 1291 if (Opc == Instruction::Or) { 1292 // Codegen X | Y as: 1293 // jmp_if_X TBB 1294 // jmp TmpBB 1295 // TmpBB: 1296 // jmp_if_Y TBB 1297 // jmp FBB 1298 // 1299 1300 // Emit the LHS condition. 1301 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1302 1303 // Emit the RHS condition into TmpBB. 1304 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1305 } else { 1306 assert(Opc == Instruction::And && "Unknown merge op!"); 1307 // Codegen X & Y as: 1308 // jmp_if_X TmpBB 1309 // jmp FBB 1310 // TmpBB: 1311 // jmp_if_Y TBB 1312 // jmp FBB 1313 // 1314 // This requires creation of TmpBB after CurBB. 1315 1316 // Emit the LHS condition. 1317 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1318 1319 // Emit the RHS condition into TmpBB. 1320 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1321 } 1322} 1323 1324/// If the set of cases should be emitted as a series of branches, return true. 1325/// If we should emit this as a bunch of and/or'd together conditions, return 1326/// false. 1327bool 1328SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1329 if (Cases.size() != 2) return true; 1330 1331 // If this is two comparisons of the same values or'd or and'd together, they 1332 // will get folded into a single comparison, so don't emit two blocks. 1333 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1334 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1335 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1336 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1337 return false; 1338 } 1339 1340 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1341 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1342 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1343 Cases[0].CC == Cases[1].CC && 1344 isa<Constant>(Cases[0].CmpRHS) && 1345 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1346 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1347 return false; 1348 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1349 return false; 1350 } 1351 1352 return true; 1353} 1354 1355void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1356 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1357 1358 // Update machine-CFG edges. 1359 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1360 1361 // Figure out which block is immediately after the current one. 1362 MachineBasicBlock *NextBlock = 0; 1363 MachineFunction::iterator BBI = BrMBB; 1364 if (++BBI != FuncInfo.MF->end()) 1365 NextBlock = BBI; 1366 1367 if (I.isUnconditional()) { 1368 // Update machine-CFG edges. 1369 BrMBB->addSuccessor(Succ0MBB); 1370 1371 // If this is not a fall-through branch, emit the branch. 1372 if (Succ0MBB != NextBlock) 1373 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1374 MVT::Other, getControlRoot(), 1375 DAG.getBasicBlock(Succ0MBB))); 1376 1377 return; 1378 } 1379 1380 // If this condition is one of the special cases we handle, do special stuff 1381 // now. 1382 const Value *CondVal = I.getCondition(); 1383 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1384 1385 // If this is a series of conditions that are or'd or and'd together, emit 1386 // this as a sequence of branches instead of setcc's with and/or operations. 1387 // For example, instead of something like: 1388 // cmp A, B 1389 // C = seteq 1390 // cmp D, E 1391 // F = setle 1392 // or C, F 1393 // jnz foo 1394 // Emit: 1395 // cmp A, B 1396 // je foo 1397 // cmp D, E 1398 // jle foo 1399 // 1400 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1401 if (BOp->hasOneUse() && 1402 (BOp->getOpcode() == Instruction::And || 1403 BOp->getOpcode() == Instruction::Or)) { 1404 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1405 BOp->getOpcode()); 1406 // If the compares in later blocks need to use values not currently 1407 // exported from this block, export them now. This block should always 1408 // be the first entry. 1409 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1410 1411 // Allow some cases to be rejected. 1412 if (ShouldEmitAsBranches(SwitchCases)) { 1413 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1414 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1415 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1416 } 1417 1418 // Emit the branch for this block. 1419 visitSwitchCase(SwitchCases[0], BrMBB); 1420 SwitchCases.erase(SwitchCases.begin()); 1421 return; 1422 } 1423 1424 // Okay, we decided not to do this, remove any inserted MBB's and clear 1425 // SwitchCases. 1426 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1427 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1428 1429 SwitchCases.clear(); 1430 } 1431 } 1432 1433 // Create a CaseBlock record representing this branch. 1434 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1435 NULL, Succ0MBB, Succ1MBB, BrMBB); 1436 1437 // Use visitSwitchCase to actually insert the fast branch sequence for this 1438 // cond branch. 1439 visitSwitchCase(CB, BrMBB); 1440} 1441 1442/// visitSwitchCase - Emits the necessary code to represent a single node in 1443/// the binary search tree resulting from lowering a switch instruction. 1444void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1445 MachineBasicBlock *SwitchBB) { 1446 SDValue Cond; 1447 SDValue CondLHS = getValue(CB.CmpLHS); 1448 DebugLoc dl = getCurDebugLoc(); 1449 1450 // Build the setcc now. 1451 if (CB.CmpMHS == NULL) { 1452 // Fold "(X == true)" to X and "(X == false)" to !X to 1453 // handle common cases produced by branch lowering. 1454 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1455 CB.CC == ISD::SETEQ) 1456 Cond = CondLHS; 1457 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1458 CB.CC == ISD::SETEQ) { 1459 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1460 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1461 } else 1462 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1463 } else { 1464 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1465 1466 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1467 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1468 1469 SDValue CmpOp = getValue(CB.CmpMHS); 1470 EVT VT = CmpOp.getValueType(); 1471 1472 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1473 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1474 ISD::SETLE); 1475 } else { 1476 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1477 VT, CmpOp, DAG.getConstant(Low, VT)); 1478 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1479 DAG.getConstant(High-Low, VT), ISD::SETULE); 1480 } 1481 } 1482 1483 // Update successor info 1484 SwitchBB->addSuccessor(CB.TrueBB); 1485 SwitchBB->addSuccessor(CB.FalseBB); 1486 1487 // Set NextBlock to be the MBB immediately after the current one, if any. 1488 // This is used to avoid emitting unnecessary branches to the next block. 1489 MachineBasicBlock *NextBlock = 0; 1490 MachineFunction::iterator BBI = SwitchBB; 1491 if (++BBI != FuncInfo.MF->end()) 1492 NextBlock = BBI; 1493 1494 // If the lhs block is the next block, invert the condition so that we can 1495 // fall through to the lhs instead of the rhs block. 1496 if (CB.TrueBB == NextBlock) { 1497 std::swap(CB.TrueBB, CB.FalseBB); 1498 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1499 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1500 } 1501 1502 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1503 MVT::Other, getControlRoot(), Cond, 1504 DAG.getBasicBlock(CB.TrueBB)); 1505 1506 // Insert the false branch. 1507 if (CB.FalseBB != NextBlock) 1508 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1509 DAG.getBasicBlock(CB.FalseBB)); 1510 1511 DAG.setRoot(BrCond); 1512} 1513 1514/// visitJumpTable - Emit JumpTable node in the current MBB 1515void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1516 // Emit the code for the jump table 1517 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1518 EVT PTy = TLI.getPointerTy(); 1519 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1520 JT.Reg, PTy); 1521 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1522 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1523 MVT::Other, Index.getValue(1), 1524 Table, Index); 1525 DAG.setRoot(BrJumpTable); 1526} 1527 1528/// visitJumpTableHeader - This function emits necessary code to produce index 1529/// in the JumpTable from switch case. 1530void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1531 JumpTableHeader &JTH, 1532 MachineBasicBlock *SwitchBB) { 1533 // Subtract the lowest switch case value from the value being switched on and 1534 // conditional branch to default mbb if the result is greater than the 1535 // difference between smallest and largest cases. 1536 SDValue SwitchOp = getValue(JTH.SValue); 1537 EVT VT = SwitchOp.getValueType(); 1538 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1539 DAG.getConstant(JTH.First, VT)); 1540 1541 // The SDNode we just created, which holds the value being switched on minus 1542 // the smallest case value, needs to be copied to a virtual register so it 1543 // can be used as an index into the jump table in a subsequent basic block. 1544 // This value may be smaller or larger than the target's pointer type, and 1545 // therefore require extension or truncating. 1546 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1547 1548 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1549 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1550 JumpTableReg, SwitchOp); 1551 JT.Reg = JumpTableReg; 1552 1553 // Emit the range check for the jump table, and branch to the default block 1554 // for the switch statement if the value being switched on exceeds the largest 1555 // case in the switch. 1556 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1557 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1558 DAG.getConstant(JTH.Last-JTH.First,VT), 1559 ISD::SETUGT); 1560 1561 // Set NextBlock to be the MBB immediately after the current one, if any. 1562 // This is used to avoid emitting unnecessary branches to the next block. 1563 MachineBasicBlock *NextBlock = 0; 1564 MachineFunction::iterator BBI = SwitchBB; 1565 1566 if (++BBI != FuncInfo.MF->end()) 1567 NextBlock = BBI; 1568 1569 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1570 MVT::Other, CopyTo, CMP, 1571 DAG.getBasicBlock(JT.Default)); 1572 1573 if (JT.MBB != NextBlock) 1574 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1575 DAG.getBasicBlock(JT.MBB)); 1576 1577 DAG.setRoot(BrCond); 1578} 1579 1580/// visitBitTestHeader - This function emits necessary code to produce value 1581/// suitable for "bit tests" 1582void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1583 MachineBasicBlock *SwitchBB) { 1584 // Subtract the minimum value 1585 SDValue SwitchOp = getValue(B.SValue); 1586 EVT VT = SwitchOp.getValueType(); 1587 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1588 DAG.getConstant(B.First, VT)); 1589 1590 // Check range 1591 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1592 TLI.getSetCCResultType(Sub.getValueType()), 1593 Sub, DAG.getConstant(B.Range, VT), 1594 ISD::SETUGT); 1595 1596 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), 1597 TLI.getPointerTy()); 1598 1599 B.Reg = FuncInfo.CreateReg(TLI.getPointerTy()); 1600 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1601 B.Reg, ShiftOp); 1602 1603 // Set NextBlock to be the MBB immediately after the current one, if any. 1604 // This is used to avoid emitting unnecessary branches to the next block. 1605 MachineBasicBlock *NextBlock = 0; 1606 MachineFunction::iterator BBI = SwitchBB; 1607 if (++BBI != FuncInfo.MF->end()) 1608 NextBlock = BBI; 1609 1610 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1611 1612 SwitchBB->addSuccessor(B.Default); 1613 SwitchBB->addSuccessor(MBB); 1614 1615 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1616 MVT::Other, CopyTo, RangeCmp, 1617 DAG.getBasicBlock(B.Default)); 1618 1619 if (MBB != NextBlock) 1620 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1621 DAG.getBasicBlock(MBB)); 1622 1623 DAG.setRoot(BrRange); 1624} 1625 1626/// visitBitTestCase - this function produces one "bit test" 1627void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB, 1628 unsigned Reg, 1629 BitTestCase &B, 1630 MachineBasicBlock *SwitchBB) { 1631 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg, 1632 TLI.getPointerTy()); 1633 SDValue Cmp; 1634 if (CountPopulation_64(B.Mask) == 1) { 1635 // Testing for a single bit; just compare the shift count with what it 1636 // would need to be to shift a 1 bit in that position. 1637 Cmp = DAG.getSetCC(getCurDebugLoc(), 1638 TLI.getSetCCResultType(ShiftOp.getValueType()), 1639 ShiftOp, 1640 DAG.getConstant(CountTrailingZeros_64(B.Mask), 1641 TLI.getPointerTy()), 1642 ISD::SETEQ); 1643 } else { 1644 // Make desired shift 1645 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), 1646 TLI.getPointerTy(), 1647 DAG.getConstant(1, TLI.getPointerTy()), 1648 ShiftOp); 1649 1650 // Emit bit tests and jumps 1651 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1652 TLI.getPointerTy(), SwitchVal, 1653 DAG.getConstant(B.Mask, TLI.getPointerTy())); 1654 Cmp = DAG.getSetCC(getCurDebugLoc(), 1655 TLI.getSetCCResultType(AndOp.getValueType()), 1656 AndOp, DAG.getConstant(0, TLI.getPointerTy()), 1657 ISD::SETNE); 1658 } 1659 1660 SwitchBB->addSuccessor(B.TargetBB); 1661 SwitchBB->addSuccessor(NextMBB); 1662 1663 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1664 MVT::Other, getControlRoot(), 1665 Cmp, DAG.getBasicBlock(B.TargetBB)); 1666 1667 // Set NextBlock to be the MBB immediately after the current one, if any. 1668 // This is used to avoid emitting unnecessary branches to the next block. 1669 MachineBasicBlock *NextBlock = 0; 1670 MachineFunction::iterator BBI = SwitchBB; 1671 if (++BBI != FuncInfo.MF->end()) 1672 NextBlock = BBI; 1673 1674 if (NextMBB != NextBlock) 1675 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1676 DAG.getBasicBlock(NextMBB)); 1677 1678 DAG.setRoot(BrAnd); 1679} 1680 1681void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1682 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1683 1684 // Retrieve successors. 1685 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1686 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1687 1688 const Value *Callee(I.getCalledValue()); 1689 if (isa<InlineAsm>(Callee)) 1690 visitInlineAsm(&I); 1691 else 1692 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1693 1694 // If the value of the invoke is used outside of its defining block, make it 1695 // available as a virtual register. 1696 CopyToExportRegsIfNeeded(&I); 1697 1698 // Update successor info 1699 InvokeMBB->addSuccessor(Return); 1700 InvokeMBB->addSuccessor(LandingPad); 1701 1702 // Drop into normal successor. 1703 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1704 MVT::Other, getControlRoot(), 1705 DAG.getBasicBlock(Return))); 1706} 1707 1708void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1709} 1710 1711/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1712/// small case ranges). 1713bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1714 CaseRecVector& WorkList, 1715 const Value* SV, 1716 MachineBasicBlock *Default, 1717 MachineBasicBlock *SwitchBB) { 1718 Case& BackCase = *(CR.Range.second-1); 1719 1720 // Size is the number of Cases represented by this range. 1721 size_t Size = CR.Range.second - CR.Range.first; 1722 if (Size > 3) 1723 return false; 1724 1725 // Get the MachineFunction which holds the current MBB. This is used when 1726 // inserting any additional MBBs necessary to represent the switch. 1727 MachineFunction *CurMF = FuncInfo.MF; 1728 1729 // Figure out which block is immediately after the current one. 1730 MachineBasicBlock *NextBlock = 0; 1731 MachineFunction::iterator BBI = CR.CaseBB; 1732 1733 if (++BBI != FuncInfo.MF->end()) 1734 NextBlock = BBI; 1735 1736 // TODO: If any two of the cases has the same destination, and if one value 1737 // is the same as the other, but has one bit unset that the other has set, 1738 // use bit manipulation to do two compares at once. For example: 1739 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1740 1741 // Rearrange the case blocks so that the last one falls through if possible. 1742 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1743 // The last case block won't fall through into 'NextBlock' if we emit the 1744 // branches in this order. See if rearranging a case value would help. 1745 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1746 if (I->BB == NextBlock) { 1747 std::swap(*I, BackCase); 1748 break; 1749 } 1750 } 1751 } 1752 1753 // Create a CaseBlock record representing a conditional branch to 1754 // the Case's target mbb if the value being switched on SV is equal 1755 // to C. 1756 MachineBasicBlock *CurBlock = CR.CaseBB; 1757 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1758 MachineBasicBlock *FallThrough; 1759 if (I != E-1) { 1760 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1761 CurMF->insert(BBI, FallThrough); 1762 1763 // Put SV in a virtual register to make it available from the new blocks. 1764 ExportFromCurrentBlock(SV); 1765 } else { 1766 // If the last case doesn't match, go to the default block. 1767 FallThrough = Default; 1768 } 1769 1770 const Value *RHS, *LHS, *MHS; 1771 ISD::CondCode CC; 1772 if (I->High == I->Low) { 1773 // This is just small small case range :) containing exactly 1 case 1774 CC = ISD::SETEQ; 1775 LHS = SV; RHS = I->High; MHS = NULL; 1776 } else { 1777 CC = ISD::SETLE; 1778 LHS = I->Low; MHS = SV; RHS = I->High; 1779 } 1780 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1781 1782 // If emitting the first comparison, just call visitSwitchCase to emit the 1783 // code into the current block. Otherwise, push the CaseBlock onto the 1784 // vector to be later processed by SDISel, and insert the node's MBB 1785 // before the next MBB. 1786 if (CurBlock == SwitchBB) 1787 visitSwitchCase(CB, SwitchBB); 1788 else 1789 SwitchCases.push_back(CB); 1790 1791 CurBlock = FallThrough; 1792 } 1793 1794 return true; 1795} 1796 1797static inline bool areJTsAllowed(const TargetLowering &TLI) { 1798 return !DisableJumpTables && 1799 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1800 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1801} 1802 1803static APInt ComputeRange(const APInt &First, const APInt &Last) { 1804 APInt LastExt(Last), FirstExt(First); 1805 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1806 LastExt.sext(BitWidth); FirstExt.sext(BitWidth); 1807 return (LastExt - FirstExt + 1ULL); 1808} 1809 1810/// handleJTSwitchCase - Emit jumptable for current switch case range 1811bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1812 CaseRecVector& WorkList, 1813 const Value* SV, 1814 MachineBasicBlock* Default, 1815 MachineBasicBlock *SwitchBB) { 1816 Case& FrontCase = *CR.Range.first; 1817 Case& BackCase = *(CR.Range.second-1); 1818 1819 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1820 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1821 1822 APInt TSize(First.getBitWidth(), 0); 1823 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1824 I!=E; ++I) 1825 TSize += I->size(); 1826 1827 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1828 return false; 1829 1830 APInt Range = ComputeRange(First, Last); 1831 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1832 if (Density < 0.4) 1833 return false; 1834 1835 DEBUG(dbgs() << "Lowering jump table\n" 1836 << "First entry: " << First << ". Last entry: " << Last << '\n' 1837 << "Range: " << Range 1838 << "Size: " << TSize << ". Density: " << Density << "\n\n"); 1839 1840 // Get the MachineFunction which holds the current MBB. This is used when 1841 // inserting any additional MBBs necessary to represent the switch. 1842 MachineFunction *CurMF = FuncInfo.MF; 1843 1844 // Figure out which block is immediately after the current one. 1845 MachineFunction::iterator BBI = CR.CaseBB; 1846 ++BBI; 1847 1848 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1849 1850 // Create a new basic block to hold the code for loading the address 1851 // of the jump table, and jumping to it. Update successor information; 1852 // we will either branch to the default case for the switch, or the jump 1853 // table. 1854 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1855 CurMF->insert(BBI, JumpTableBB); 1856 CR.CaseBB->addSuccessor(Default); 1857 CR.CaseBB->addSuccessor(JumpTableBB); 1858 1859 // Build a vector of destination BBs, corresponding to each target 1860 // of the jump table. If the value of the jump table slot corresponds to 1861 // a case statement, push the case's BB onto the vector, otherwise, push 1862 // the default BB. 1863 std::vector<MachineBasicBlock*> DestBBs; 1864 APInt TEI = First; 1865 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1866 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 1867 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 1868 1869 if (Low.sle(TEI) && TEI.sle(High)) { 1870 DestBBs.push_back(I->BB); 1871 if (TEI==High) 1872 ++I; 1873 } else { 1874 DestBBs.push_back(Default); 1875 } 1876 } 1877 1878 // Update successor info. Add one edge to each unique successor. 1879 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1880 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1881 E = DestBBs.end(); I != E; ++I) { 1882 if (!SuccsHandled[(*I)->getNumber()]) { 1883 SuccsHandled[(*I)->getNumber()] = true; 1884 JumpTableBB->addSuccessor(*I); 1885 } 1886 } 1887 1888 // Create a jump table index for this jump table. 1889 unsigned JTEncoding = TLI.getJumpTableEncoding(); 1890 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 1891 ->createJumpTableIndex(DestBBs); 1892 1893 // Set the jump table information so that we can codegen it as a second 1894 // MachineBasicBlock 1895 JumpTable JT(-1U, JTI, JumpTableBB, Default); 1896 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 1897 if (CR.CaseBB == SwitchBB) 1898 visitJumpTableHeader(JT, JTH, SwitchBB); 1899 1900 JTCases.push_back(JumpTableBlock(JTH, JT)); 1901 1902 return true; 1903} 1904 1905/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1906/// 2 subtrees. 1907bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 1908 CaseRecVector& WorkList, 1909 const Value* SV, 1910 MachineBasicBlock *Default, 1911 MachineBasicBlock *SwitchBB) { 1912 // Get the MachineFunction which holds the current MBB. This is used when 1913 // inserting any additional MBBs necessary to represent the switch. 1914 MachineFunction *CurMF = FuncInfo.MF; 1915 1916 // Figure out which block is immediately after the current one. 1917 MachineFunction::iterator BBI = CR.CaseBB; 1918 ++BBI; 1919 1920 Case& FrontCase = *CR.Range.first; 1921 Case& BackCase = *(CR.Range.second-1); 1922 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1923 1924 // Size is the number of Cases represented by this range. 1925 unsigned Size = CR.Range.second - CR.Range.first; 1926 1927 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1928 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1929 double FMetric = 0; 1930 CaseItr Pivot = CR.Range.first + Size/2; 1931 1932 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1933 // (heuristically) allow us to emit JumpTable's later. 1934 APInt TSize(First.getBitWidth(), 0); 1935 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1936 I!=E; ++I) 1937 TSize += I->size(); 1938 1939 APInt LSize = FrontCase.size(); 1940 APInt RSize = TSize-LSize; 1941 DEBUG(dbgs() << "Selecting best pivot: \n" 1942 << "First: " << First << ", Last: " << Last <<'\n' 1943 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 1944 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1945 J!=E; ++I, ++J) { 1946 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 1947 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 1948 APInt Range = ComputeRange(LEnd, RBegin); 1949 assert((Range - 2ULL).isNonNegative() && 1950 "Invalid case distance"); 1951 double LDensity = (double)LSize.roundToDouble() / 1952 (LEnd - First + 1ULL).roundToDouble(); 1953 double RDensity = (double)RSize.roundToDouble() / 1954 (Last - RBegin + 1ULL).roundToDouble(); 1955 double Metric = Range.logBase2()*(LDensity+RDensity); 1956 // Should always split in some non-trivial place 1957 DEBUG(dbgs() <<"=>Step\n" 1958 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 1959 << "LDensity: " << LDensity 1960 << ", RDensity: " << RDensity << '\n' 1961 << "Metric: " << Metric << '\n'); 1962 if (FMetric < Metric) { 1963 Pivot = J; 1964 FMetric = Metric; 1965 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 1966 } 1967 1968 LSize += J->size(); 1969 RSize -= J->size(); 1970 } 1971 if (areJTsAllowed(TLI)) { 1972 // If our case is dense we *really* should handle it earlier! 1973 assert((FMetric > 0) && "Should handle dense range earlier!"); 1974 } else { 1975 Pivot = CR.Range.first + Size/2; 1976 } 1977 1978 CaseRange LHSR(CR.Range.first, Pivot); 1979 CaseRange RHSR(Pivot, CR.Range.second); 1980 Constant *C = Pivot->Low; 1981 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1982 1983 // We know that we branch to the LHS if the Value being switched on is 1984 // less than the Pivot value, C. We use this to optimize our binary 1985 // tree a bit, by recognizing that if SV is greater than or equal to the 1986 // LHS's Case Value, and that Case Value is exactly one less than the 1987 // Pivot's Value, then we can branch directly to the LHS's Target, 1988 // rather than creating a leaf node for it. 1989 if ((LHSR.second - LHSR.first) == 1 && 1990 LHSR.first->High == CR.GE && 1991 cast<ConstantInt>(C)->getValue() == 1992 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 1993 TrueBB = LHSR.first->BB; 1994 } else { 1995 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1996 CurMF->insert(BBI, TrueBB); 1997 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1998 1999 // Put SV in a virtual register to make it available from the new blocks. 2000 ExportFromCurrentBlock(SV); 2001 } 2002 2003 // Similar to the optimization above, if the Value being switched on is 2004 // known to be less than the Constant CR.LT, and the current Case Value 2005 // is CR.LT - 1, then we can branch directly to the target block for 2006 // the current Case Value, rather than emitting a RHS leaf node for it. 2007 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2008 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2009 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2010 FalseBB = RHSR.first->BB; 2011 } else { 2012 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2013 CurMF->insert(BBI, FalseBB); 2014 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2015 2016 // Put SV in a virtual register to make it available from the new blocks. 2017 ExportFromCurrentBlock(SV); 2018 } 2019 2020 // Create a CaseBlock record representing a conditional branch to 2021 // the LHS node if the value being switched on SV is less than C. 2022 // Otherwise, branch to LHS. 2023 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2024 2025 if (CR.CaseBB == SwitchBB) 2026 visitSwitchCase(CB, SwitchBB); 2027 else 2028 SwitchCases.push_back(CB); 2029 2030 return true; 2031} 2032 2033/// handleBitTestsSwitchCase - if current case range has few destination and 2034/// range span less, than machine word bitwidth, encode case range into series 2035/// of masks and emit bit tests with these masks. 2036bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2037 CaseRecVector& WorkList, 2038 const Value* SV, 2039 MachineBasicBlock* Default, 2040 MachineBasicBlock *SwitchBB){ 2041 EVT PTy = TLI.getPointerTy(); 2042 unsigned IntPtrBits = PTy.getSizeInBits(); 2043 2044 Case& FrontCase = *CR.Range.first; 2045 Case& BackCase = *(CR.Range.second-1); 2046 2047 // Get the MachineFunction which holds the current MBB. This is used when 2048 // inserting any additional MBBs necessary to represent the switch. 2049 MachineFunction *CurMF = FuncInfo.MF; 2050 2051 // If target does not have legal shift left, do not emit bit tests at all. 2052 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2053 return false; 2054 2055 size_t numCmps = 0; 2056 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2057 I!=E; ++I) { 2058 // Single case counts one, case range - two. 2059 numCmps += (I->Low == I->High ? 1 : 2); 2060 } 2061 2062 // Count unique destinations 2063 SmallSet<MachineBasicBlock*, 4> Dests; 2064 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2065 Dests.insert(I->BB); 2066 if (Dests.size() > 3) 2067 // Don't bother the code below, if there are too much unique destinations 2068 return false; 2069 } 2070 DEBUG(dbgs() << "Total number of unique destinations: " 2071 << Dests.size() << '\n' 2072 << "Total number of comparisons: " << numCmps << '\n'); 2073 2074 // Compute span of values. 2075 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2076 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2077 APInt cmpRange = maxValue - minValue; 2078 2079 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2080 << "Low bound: " << minValue << '\n' 2081 << "High bound: " << maxValue << '\n'); 2082 2083 if (cmpRange.uge(IntPtrBits) || 2084 (!(Dests.size() == 1 && numCmps >= 3) && 2085 !(Dests.size() == 2 && numCmps >= 5) && 2086 !(Dests.size() >= 3 && numCmps >= 6))) 2087 return false; 2088 2089 DEBUG(dbgs() << "Emitting bit tests\n"); 2090 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2091 2092 // Optimize the case where all the case values fit in a 2093 // word without having to subtract minValue. In this case, 2094 // we can optimize away the subtraction. 2095 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2096 cmpRange = maxValue; 2097 } else { 2098 lowBound = minValue; 2099 } 2100 2101 CaseBitsVector CasesBits; 2102 unsigned i, count = 0; 2103 2104 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2105 MachineBasicBlock* Dest = I->BB; 2106 for (i = 0; i < count; ++i) 2107 if (Dest == CasesBits[i].BB) 2108 break; 2109 2110 if (i == count) { 2111 assert((count < 3) && "Too much destinations to test!"); 2112 CasesBits.push_back(CaseBits(0, Dest, 0)); 2113 count++; 2114 } 2115 2116 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2117 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2118 2119 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2120 uint64_t hi = (highValue - lowBound).getZExtValue(); 2121 2122 for (uint64_t j = lo; j <= hi; j++) { 2123 CasesBits[i].Mask |= 1ULL << j; 2124 CasesBits[i].Bits++; 2125 } 2126 2127 } 2128 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2129 2130 BitTestInfo BTC; 2131 2132 // Figure out which block is immediately after the current one. 2133 MachineFunction::iterator BBI = CR.CaseBB; 2134 ++BBI; 2135 2136 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2137 2138 DEBUG(dbgs() << "Cases:\n"); 2139 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2140 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2141 << ", Bits: " << CasesBits[i].Bits 2142 << ", BB: " << CasesBits[i].BB << '\n'); 2143 2144 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2145 CurMF->insert(BBI, CaseBB); 2146 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2147 CaseBB, 2148 CasesBits[i].BB)); 2149 2150 // Put SV in a virtual register to make it available from the new blocks. 2151 ExportFromCurrentBlock(SV); 2152 } 2153 2154 BitTestBlock BTB(lowBound, cmpRange, SV, 2155 -1U, (CR.CaseBB == SwitchBB), 2156 CR.CaseBB, Default, BTC); 2157 2158 if (CR.CaseBB == SwitchBB) 2159 visitBitTestHeader(BTB, SwitchBB); 2160 2161 BitTestCases.push_back(BTB); 2162 2163 return true; 2164} 2165 2166/// Clusterify - Transform simple list of Cases into list of CaseRange's 2167size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2168 const SwitchInst& SI) { 2169 size_t numCmps = 0; 2170 2171 // Start with "simple" cases 2172 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2173 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2174 Cases.push_back(Case(SI.getSuccessorValue(i), 2175 SI.getSuccessorValue(i), 2176 SMBB)); 2177 } 2178 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2179 2180 // Merge case into clusters 2181 if (Cases.size() >= 2) 2182 // Must recompute end() each iteration because it may be 2183 // invalidated by erase if we hold on to it 2184 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) { 2185 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2186 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2187 MachineBasicBlock* nextBB = J->BB; 2188 MachineBasicBlock* currentBB = I->BB; 2189 2190 // If the two neighboring cases go to the same destination, merge them 2191 // into a single case. 2192 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2193 I->High = J->High; 2194 J = Cases.erase(J); 2195 } else { 2196 I = J++; 2197 } 2198 } 2199 2200 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2201 if (I->Low != I->High) 2202 // A range counts double, since it requires two compares. 2203 ++numCmps; 2204 } 2205 2206 return numCmps; 2207} 2208 2209void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2210 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2211 2212 // Figure out which block is immediately after the current one. 2213 MachineBasicBlock *NextBlock = 0; 2214 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2215 2216 // If there is only the default destination, branch to it if it is not the 2217 // next basic block. Otherwise, just fall through. 2218 if (SI.getNumOperands() == 2) { 2219 // Update machine-CFG edges. 2220 2221 // If this is not a fall-through branch, emit the branch. 2222 SwitchMBB->addSuccessor(Default); 2223 if (Default != NextBlock) 2224 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2225 MVT::Other, getControlRoot(), 2226 DAG.getBasicBlock(Default))); 2227 2228 return; 2229 } 2230 2231 // If there are any non-default case statements, create a vector of Cases 2232 // representing each one, and sort the vector so that we can efficiently 2233 // create a binary search tree from them. 2234 CaseVector Cases; 2235 size_t numCmps = Clusterify(Cases, SI); 2236 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2237 << ". Total compares: " << numCmps << '\n'); 2238 numCmps = 0; 2239 2240 // Get the Value to be switched on and default basic blocks, which will be 2241 // inserted into CaseBlock records, representing basic blocks in the binary 2242 // search tree. 2243 const Value *SV = SI.getOperand(0); 2244 2245 // Push the initial CaseRec onto the worklist 2246 CaseRecVector WorkList; 2247 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2248 CaseRange(Cases.begin(),Cases.end()))); 2249 2250 while (!WorkList.empty()) { 2251 // Grab a record representing a case range to process off the worklist 2252 CaseRec CR = WorkList.back(); 2253 WorkList.pop_back(); 2254 2255 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2256 continue; 2257 2258 // If the range has few cases (two or less) emit a series of specific 2259 // tests. 2260 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2261 continue; 2262 2263 // If the switch has more than 5 blocks, and at least 40% dense, and the 2264 // target supports indirect branches, then emit a jump table rather than 2265 // lowering the switch to a binary tree of conditional branches. 2266 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2267 continue; 2268 2269 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2270 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2271 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2272 } 2273} 2274 2275void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2276 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2277 2278 // Update machine-CFG edges with unique successors. 2279 SmallVector<BasicBlock*, 32> succs; 2280 succs.reserve(I.getNumSuccessors()); 2281 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2282 succs.push_back(I.getSuccessor(i)); 2283 array_pod_sort(succs.begin(), succs.end()); 2284 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2285 for (unsigned i = 0, e = succs.size(); i != e; ++i) 2286 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]); 2287 2288 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2289 MVT::Other, getControlRoot(), 2290 getValue(I.getAddress()))); 2291} 2292 2293void SelectionDAGBuilder::visitFSub(const User &I) { 2294 // -0.0 - X --> fneg 2295 const Type *Ty = I.getType(); 2296 if (Ty->isVectorTy()) { 2297 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2298 const VectorType *DestTy = cast<VectorType>(I.getType()); 2299 const Type *ElTy = DestTy->getElementType(); 2300 unsigned VL = DestTy->getNumElements(); 2301 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2302 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2303 if (CV == CNZ) { 2304 SDValue Op2 = getValue(I.getOperand(1)); 2305 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2306 Op2.getValueType(), Op2)); 2307 return; 2308 } 2309 } 2310 } 2311 2312 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2313 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2314 SDValue Op2 = getValue(I.getOperand(1)); 2315 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2316 Op2.getValueType(), Op2)); 2317 return; 2318 } 2319 2320 visitBinary(I, ISD::FSUB); 2321} 2322 2323void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2324 SDValue Op1 = getValue(I.getOperand(0)); 2325 SDValue Op2 = getValue(I.getOperand(1)); 2326 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2327 Op1.getValueType(), Op1, Op2)); 2328} 2329 2330void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2331 SDValue Op1 = getValue(I.getOperand(0)); 2332 SDValue Op2 = getValue(I.getOperand(1)); 2333 if (!I.getType()->isVectorTy() && 2334 Op2.getValueType() != TLI.getShiftAmountTy()) { 2335 // If the operand is smaller than the shift count type, promote it. 2336 EVT PTy = TLI.getPointerTy(); 2337 EVT STy = TLI.getShiftAmountTy(); 2338 if (STy.bitsGT(Op2.getValueType())) 2339 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2340 TLI.getShiftAmountTy(), Op2); 2341 // If the operand is larger than the shift count type but the shift 2342 // count type has enough bits to represent any shift value, truncate 2343 // it now. This is a common case and it exposes the truncate to 2344 // optimization early. 2345 else if (STy.getSizeInBits() >= 2346 Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2347 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2348 TLI.getShiftAmountTy(), Op2); 2349 // Otherwise we'll need to temporarily settle for some other 2350 // convenient type; type legalization will make adjustments as 2351 // needed. 2352 else if (PTy.bitsLT(Op2.getValueType())) 2353 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2354 TLI.getPointerTy(), Op2); 2355 else if (PTy.bitsGT(Op2.getValueType())) 2356 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2357 TLI.getPointerTy(), Op2); 2358 } 2359 2360 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2361 Op1.getValueType(), Op1, Op2)); 2362} 2363 2364void SelectionDAGBuilder::visitICmp(const User &I) { 2365 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2366 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2367 predicate = IC->getPredicate(); 2368 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2369 predicate = ICmpInst::Predicate(IC->getPredicate()); 2370 SDValue Op1 = getValue(I.getOperand(0)); 2371 SDValue Op2 = getValue(I.getOperand(1)); 2372 ISD::CondCode Opcode = getICmpCondCode(predicate); 2373 2374 EVT DestVT = TLI.getValueType(I.getType()); 2375 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2376} 2377 2378void SelectionDAGBuilder::visitFCmp(const User &I) { 2379 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2380 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2381 predicate = FC->getPredicate(); 2382 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2383 predicate = FCmpInst::Predicate(FC->getPredicate()); 2384 SDValue Op1 = getValue(I.getOperand(0)); 2385 SDValue Op2 = getValue(I.getOperand(1)); 2386 ISD::CondCode Condition = getFCmpCondCode(predicate); 2387 EVT DestVT = TLI.getValueType(I.getType()); 2388 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2389} 2390 2391void SelectionDAGBuilder::visitSelect(const User &I) { 2392 SmallVector<EVT, 4> ValueVTs; 2393 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2394 unsigned NumValues = ValueVTs.size(); 2395 if (NumValues == 0) return; 2396 2397 SmallVector<SDValue, 4> Values(NumValues); 2398 SDValue Cond = getValue(I.getOperand(0)); 2399 SDValue TrueVal = getValue(I.getOperand(1)); 2400 SDValue FalseVal = getValue(I.getOperand(2)); 2401 2402 for (unsigned i = 0; i != NumValues; ++i) 2403 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2404 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2405 Cond, 2406 SDValue(TrueVal.getNode(), 2407 TrueVal.getResNo() + i), 2408 SDValue(FalseVal.getNode(), 2409 FalseVal.getResNo() + i)); 2410 2411 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2412 DAG.getVTList(&ValueVTs[0], NumValues), 2413 &Values[0], NumValues)); 2414} 2415 2416void SelectionDAGBuilder::visitTrunc(const User &I) { 2417 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2418 SDValue N = getValue(I.getOperand(0)); 2419 EVT DestVT = TLI.getValueType(I.getType()); 2420 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2421} 2422 2423void SelectionDAGBuilder::visitZExt(const User &I) { 2424 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2425 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2426 SDValue N = getValue(I.getOperand(0)); 2427 EVT DestVT = TLI.getValueType(I.getType()); 2428 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2429} 2430 2431void SelectionDAGBuilder::visitSExt(const User &I) { 2432 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2433 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2434 SDValue N = getValue(I.getOperand(0)); 2435 EVT DestVT = TLI.getValueType(I.getType()); 2436 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2437} 2438 2439void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2440 // FPTrunc is never a no-op cast, no need to check 2441 SDValue N = getValue(I.getOperand(0)); 2442 EVT DestVT = TLI.getValueType(I.getType()); 2443 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2444 DestVT, N, DAG.getIntPtrConstant(0))); 2445} 2446 2447void SelectionDAGBuilder::visitFPExt(const User &I){ 2448 // FPTrunc is never a no-op cast, no need to check 2449 SDValue N = getValue(I.getOperand(0)); 2450 EVT DestVT = TLI.getValueType(I.getType()); 2451 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2452} 2453 2454void SelectionDAGBuilder::visitFPToUI(const User &I) { 2455 // FPToUI is never a no-op cast, no need to check 2456 SDValue N = getValue(I.getOperand(0)); 2457 EVT DestVT = TLI.getValueType(I.getType()); 2458 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2459} 2460 2461void SelectionDAGBuilder::visitFPToSI(const User &I) { 2462 // FPToSI is never a no-op cast, no need to check 2463 SDValue N = getValue(I.getOperand(0)); 2464 EVT DestVT = TLI.getValueType(I.getType()); 2465 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2466} 2467 2468void SelectionDAGBuilder::visitUIToFP(const User &I) { 2469 // UIToFP is never a no-op cast, no need to check 2470 SDValue N = getValue(I.getOperand(0)); 2471 EVT DestVT = TLI.getValueType(I.getType()); 2472 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2473} 2474 2475void SelectionDAGBuilder::visitSIToFP(const User &I){ 2476 // SIToFP is never a no-op cast, no need to check 2477 SDValue N = getValue(I.getOperand(0)); 2478 EVT DestVT = TLI.getValueType(I.getType()); 2479 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2480} 2481 2482void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2483 // What to do depends on the size of the integer and the size of the pointer. 2484 // We can either truncate, zero extend, or no-op, accordingly. 2485 SDValue N = getValue(I.getOperand(0)); 2486 EVT DestVT = TLI.getValueType(I.getType()); 2487 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2488} 2489 2490void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2491 // What to do depends on the size of the integer and the size of the pointer. 2492 // We can either truncate, zero extend, or no-op, accordingly. 2493 SDValue N = getValue(I.getOperand(0)); 2494 EVT DestVT = TLI.getValueType(I.getType()); 2495 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2496} 2497 2498void SelectionDAGBuilder::visitBitCast(const User &I) { 2499 SDValue N = getValue(I.getOperand(0)); 2500 EVT DestVT = TLI.getValueType(I.getType()); 2501 2502 // BitCast assures us that source and destination are the same size so this is 2503 // either a BIT_CONVERT or a no-op. 2504 if (DestVT != N.getValueType()) 2505 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 2506 DestVT, N)); // convert types. 2507 else 2508 setValue(&I, N); // noop cast. 2509} 2510 2511void SelectionDAGBuilder::visitInsertElement(const User &I) { 2512 SDValue InVec = getValue(I.getOperand(0)); 2513 SDValue InVal = getValue(I.getOperand(1)); 2514 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2515 TLI.getPointerTy(), 2516 getValue(I.getOperand(2))); 2517 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2518 TLI.getValueType(I.getType()), 2519 InVec, InVal, InIdx)); 2520} 2521 2522void SelectionDAGBuilder::visitExtractElement(const User &I) { 2523 SDValue InVec = getValue(I.getOperand(0)); 2524 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2525 TLI.getPointerTy(), 2526 getValue(I.getOperand(1))); 2527 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2528 TLI.getValueType(I.getType()), InVec, InIdx)); 2529} 2530 2531// Utility for visitShuffleVector - Returns true if the mask is mask starting 2532// from SIndx and increasing to the element length (undefs are allowed). 2533static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2534 unsigned MaskNumElts = Mask.size(); 2535 for (unsigned i = 0; i != MaskNumElts; ++i) 2536 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2537 return false; 2538 return true; 2539} 2540 2541void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2542 SmallVector<int, 8> Mask; 2543 SDValue Src1 = getValue(I.getOperand(0)); 2544 SDValue Src2 = getValue(I.getOperand(1)); 2545 2546 // Convert the ConstantVector mask operand into an array of ints, with -1 2547 // representing undef values. 2548 SmallVector<Constant*, 8> MaskElts; 2549 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2550 unsigned MaskNumElts = MaskElts.size(); 2551 for (unsigned i = 0; i != MaskNumElts; ++i) { 2552 if (isa<UndefValue>(MaskElts[i])) 2553 Mask.push_back(-1); 2554 else 2555 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2556 } 2557 2558 EVT VT = TLI.getValueType(I.getType()); 2559 EVT SrcVT = Src1.getValueType(); 2560 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2561 2562 if (SrcNumElts == MaskNumElts) { 2563 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2564 &Mask[0])); 2565 return; 2566 } 2567 2568 // Normalize the shuffle vector since mask and vector length don't match. 2569 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2570 // Mask is longer than the source vectors and is a multiple of the source 2571 // vectors. We can use concatenate vector to make the mask and vectors 2572 // lengths match. 2573 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2574 // The shuffle is concatenating two vectors together. 2575 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2576 VT, Src1, Src2)); 2577 return; 2578 } 2579 2580 // Pad both vectors with undefs to make them the same length as the mask. 2581 unsigned NumConcat = MaskNumElts / SrcNumElts; 2582 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2583 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2584 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2585 2586 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2587 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2588 MOps1[0] = Src1; 2589 MOps2[0] = Src2; 2590 2591 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2592 getCurDebugLoc(), VT, 2593 &MOps1[0], NumConcat); 2594 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2595 getCurDebugLoc(), VT, 2596 &MOps2[0], NumConcat); 2597 2598 // Readjust mask for new input vector length. 2599 SmallVector<int, 8> MappedOps; 2600 for (unsigned i = 0; i != MaskNumElts; ++i) { 2601 int Idx = Mask[i]; 2602 if (Idx < (int)SrcNumElts) 2603 MappedOps.push_back(Idx); 2604 else 2605 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2606 } 2607 2608 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2609 &MappedOps[0])); 2610 return; 2611 } 2612 2613 if (SrcNumElts > MaskNumElts) { 2614 // Analyze the access pattern of the vector to see if we can extract 2615 // two subvectors and do the shuffle. The analysis is done by calculating 2616 // the range of elements the mask access on both vectors. 2617 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2618 int MaxRange[2] = {-1, -1}; 2619 2620 for (unsigned i = 0; i != MaskNumElts; ++i) { 2621 int Idx = Mask[i]; 2622 int Input = 0; 2623 if (Idx < 0) 2624 continue; 2625 2626 if (Idx >= (int)SrcNumElts) { 2627 Input = 1; 2628 Idx -= SrcNumElts; 2629 } 2630 if (Idx > MaxRange[Input]) 2631 MaxRange[Input] = Idx; 2632 if (Idx < MinRange[Input]) 2633 MinRange[Input] = Idx; 2634 } 2635 2636 // Check if the access is smaller than the vector size and can we find 2637 // a reasonable extract index. 2638 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2639 // Extract. 2640 int StartIdx[2]; // StartIdx to extract from 2641 for (int Input=0; Input < 2; ++Input) { 2642 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2643 RangeUse[Input] = 0; // Unused 2644 StartIdx[Input] = 0; 2645 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2646 // Fits within range but we should see if we can find a good 2647 // start index that is a multiple of the mask length. 2648 if (MaxRange[Input] < (int)MaskNumElts) { 2649 RangeUse[Input] = 1; // Extract from beginning of the vector 2650 StartIdx[Input] = 0; 2651 } else { 2652 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2653 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2654 StartIdx[Input] + MaskNumElts < SrcNumElts) 2655 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2656 } 2657 } 2658 } 2659 2660 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2661 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2662 return; 2663 } 2664 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2665 // Extract appropriate subvector and generate a vector shuffle 2666 for (int Input=0; Input < 2; ++Input) { 2667 SDValue &Src = Input == 0 ? Src1 : Src2; 2668 if (RangeUse[Input] == 0) 2669 Src = DAG.getUNDEF(VT); 2670 else 2671 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2672 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2673 } 2674 2675 // Calculate new mask. 2676 SmallVector<int, 8> MappedOps; 2677 for (unsigned i = 0; i != MaskNumElts; ++i) { 2678 int Idx = Mask[i]; 2679 if (Idx < 0) 2680 MappedOps.push_back(Idx); 2681 else if (Idx < (int)SrcNumElts) 2682 MappedOps.push_back(Idx - StartIdx[0]); 2683 else 2684 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2685 } 2686 2687 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2688 &MappedOps[0])); 2689 return; 2690 } 2691 } 2692 2693 // We can't use either concat vectors or extract subvectors so fall back to 2694 // replacing the shuffle with extract and build vector. 2695 // to insert and build vector. 2696 EVT EltVT = VT.getVectorElementType(); 2697 EVT PtrVT = TLI.getPointerTy(); 2698 SmallVector<SDValue,8> Ops; 2699 for (unsigned i = 0; i != MaskNumElts; ++i) { 2700 if (Mask[i] < 0) { 2701 Ops.push_back(DAG.getUNDEF(EltVT)); 2702 } else { 2703 int Idx = Mask[i]; 2704 SDValue Res; 2705 2706 if (Idx < (int)SrcNumElts) 2707 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2708 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2709 else 2710 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2711 EltVT, Src2, 2712 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2713 2714 Ops.push_back(Res); 2715 } 2716 } 2717 2718 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2719 VT, &Ops[0], Ops.size())); 2720} 2721 2722void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2723 const Value *Op0 = I.getOperand(0); 2724 const Value *Op1 = I.getOperand(1); 2725 const Type *AggTy = I.getType(); 2726 const Type *ValTy = Op1->getType(); 2727 bool IntoUndef = isa<UndefValue>(Op0); 2728 bool FromUndef = isa<UndefValue>(Op1); 2729 2730 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2731 I.idx_begin(), I.idx_end()); 2732 2733 SmallVector<EVT, 4> AggValueVTs; 2734 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2735 SmallVector<EVT, 4> ValValueVTs; 2736 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2737 2738 unsigned NumAggValues = AggValueVTs.size(); 2739 unsigned NumValValues = ValValueVTs.size(); 2740 SmallVector<SDValue, 4> Values(NumAggValues); 2741 2742 SDValue Agg = getValue(Op0); 2743 SDValue Val = getValue(Op1); 2744 unsigned i = 0; 2745 // Copy the beginning value(s) from the original aggregate. 2746 for (; i != LinearIndex; ++i) 2747 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2748 SDValue(Agg.getNode(), Agg.getResNo() + i); 2749 // Copy values from the inserted value(s). 2750 for (; i != LinearIndex + NumValValues; ++i) 2751 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2752 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2753 // Copy remaining value(s) from the original aggregate. 2754 for (; i != NumAggValues; ++i) 2755 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2756 SDValue(Agg.getNode(), Agg.getResNo() + i); 2757 2758 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2759 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2760 &Values[0], NumAggValues)); 2761} 2762 2763void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2764 const Value *Op0 = I.getOperand(0); 2765 const Type *AggTy = Op0->getType(); 2766 const Type *ValTy = I.getType(); 2767 bool OutOfUndef = isa<UndefValue>(Op0); 2768 2769 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2770 I.idx_begin(), I.idx_end()); 2771 2772 SmallVector<EVT, 4> ValValueVTs; 2773 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2774 2775 unsigned NumValValues = ValValueVTs.size(); 2776 SmallVector<SDValue, 4> Values(NumValValues); 2777 2778 SDValue Agg = getValue(Op0); 2779 // Copy out the selected value(s). 2780 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2781 Values[i - LinearIndex] = 2782 OutOfUndef ? 2783 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2784 SDValue(Agg.getNode(), Agg.getResNo() + i); 2785 2786 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2787 DAG.getVTList(&ValValueVTs[0], NumValValues), 2788 &Values[0], NumValValues)); 2789} 2790 2791void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2792 SDValue N = getValue(I.getOperand(0)); 2793 const Type *Ty = I.getOperand(0)->getType(); 2794 2795 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2796 OI != E; ++OI) { 2797 const Value *Idx = *OI; 2798 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2799 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2800 if (Field) { 2801 // N = N + Offset 2802 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2803 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2804 DAG.getIntPtrConstant(Offset)); 2805 } 2806 2807 Ty = StTy->getElementType(Field); 2808 } else if (const UnionType *UnTy = dyn_cast<UnionType>(Ty)) { 2809 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2810 2811 // Offset canonically 0 for unions, but type changes 2812 Ty = UnTy->getElementType(Field); 2813 } else { 2814 Ty = cast<SequentialType>(Ty)->getElementType(); 2815 2816 // If this is a constant subscript, handle it quickly. 2817 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2818 if (CI->isZero()) continue; 2819 uint64_t Offs = 2820 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2821 SDValue OffsVal; 2822 EVT PTy = TLI.getPointerTy(); 2823 unsigned PtrBits = PTy.getSizeInBits(); 2824 if (PtrBits < 64) 2825 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2826 TLI.getPointerTy(), 2827 DAG.getConstant(Offs, MVT::i64)); 2828 else 2829 OffsVal = DAG.getIntPtrConstant(Offs); 2830 2831 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2832 OffsVal); 2833 continue; 2834 } 2835 2836 // N = N + Idx * ElementSize; 2837 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2838 TD->getTypeAllocSize(Ty)); 2839 SDValue IdxN = getValue(Idx); 2840 2841 // If the index is smaller or larger than intptr_t, truncate or extend 2842 // it. 2843 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2844 2845 // If this is a multiply by a power of two, turn it into a shl 2846 // immediately. This is a very common case. 2847 if (ElementSize != 1) { 2848 if (ElementSize.isPowerOf2()) { 2849 unsigned Amt = ElementSize.logBase2(); 2850 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2851 N.getValueType(), IdxN, 2852 DAG.getConstant(Amt, TLI.getPointerTy())); 2853 } else { 2854 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2855 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2856 N.getValueType(), IdxN, Scale); 2857 } 2858 } 2859 2860 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2861 N.getValueType(), N, IdxN); 2862 } 2863 } 2864 2865 setValue(&I, N); 2866} 2867 2868void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 2869 // If this is a fixed sized alloca in the entry block of the function, 2870 // allocate it statically on the stack. 2871 if (FuncInfo.StaticAllocaMap.count(&I)) 2872 return; // getValue will auto-populate this. 2873 2874 const Type *Ty = I.getAllocatedType(); 2875 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 2876 unsigned Align = 2877 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2878 I.getAlignment()); 2879 2880 SDValue AllocSize = getValue(I.getArraySize()); 2881 2882 EVT IntPtr = TLI.getPointerTy(); 2883 if (AllocSize.getValueType() != IntPtr) 2884 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 2885 2886 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 2887 AllocSize, 2888 DAG.getConstant(TySize, IntPtr)); 2889 2890 // Handle alignment. If the requested alignment is less than or equal to 2891 // the stack alignment, ignore it. If the size is greater than or equal to 2892 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2893 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); 2894 if (Align <= StackAlign) 2895 Align = 0; 2896 2897 // Round the size of the allocation up to the stack alignment size 2898 // by add SA-1 to the size. 2899 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2900 AllocSize.getValueType(), AllocSize, 2901 DAG.getIntPtrConstant(StackAlign-1)); 2902 2903 // Mask out the low bits for alignment purposes. 2904 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 2905 AllocSize.getValueType(), AllocSize, 2906 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2907 2908 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2909 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 2910 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 2911 VTs, Ops, 3); 2912 setValue(&I, DSA); 2913 DAG.setRoot(DSA.getValue(1)); 2914 2915 // Inform the Frame Information that we have just allocated a variable-sized 2916 // object. 2917 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 2918} 2919 2920void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 2921 const Value *SV = I.getOperand(0); 2922 SDValue Ptr = getValue(SV); 2923 2924 const Type *Ty = I.getType(); 2925 2926 bool isVolatile = I.isVolatile(); 2927 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2928 unsigned Alignment = I.getAlignment(); 2929 2930 SmallVector<EVT, 4> ValueVTs; 2931 SmallVector<uint64_t, 4> Offsets; 2932 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2933 unsigned NumValues = ValueVTs.size(); 2934 if (NumValues == 0) 2935 return; 2936 2937 SDValue Root; 2938 bool ConstantMemory = false; 2939 if (I.isVolatile()) 2940 // Serialize volatile loads with other side effects. 2941 Root = getRoot(); 2942 else if (AA->pointsToConstantMemory(SV)) { 2943 // Do not serialize (non-volatile) loads of constant memory with anything. 2944 Root = DAG.getEntryNode(); 2945 ConstantMemory = true; 2946 } else { 2947 // Do not serialize non-volatile loads against each other. 2948 Root = DAG.getRoot(); 2949 } 2950 2951 SmallVector<SDValue, 4> Values(NumValues); 2952 SmallVector<SDValue, 4> Chains(NumValues); 2953 EVT PtrVT = Ptr.getValueType(); 2954 for (unsigned i = 0; i != NumValues; ++i) { 2955 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2956 PtrVT, Ptr, 2957 DAG.getConstant(Offsets[i], PtrVT)); 2958 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 2959 A, SV, Offsets[i], isVolatile, 2960 isNonTemporal, Alignment); 2961 2962 Values[i] = L; 2963 Chains[i] = L.getValue(1); 2964 } 2965 2966 if (!ConstantMemory) { 2967 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 2968 MVT::Other, &Chains[0], NumValues); 2969 if (isVolatile) 2970 DAG.setRoot(Chain); 2971 else 2972 PendingLoads.push_back(Chain); 2973 } 2974 2975 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2976 DAG.getVTList(&ValueVTs[0], NumValues), 2977 &Values[0], NumValues)); 2978} 2979 2980void SelectionDAGBuilder::visitStore(const StoreInst &I) { 2981 const Value *SrcV = I.getOperand(0); 2982 const Value *PtrV = I.getOperand(1); 2983 2984 SmallVector<EVT, 4> ValueVTs; 2985 SmallVector<uint64_t, 4> Offsets; 2986 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 2987 unsigned NumValues = ValueVTs.size(); 2988 if (NumValues == 0) 2989 return; 2990 2991 // Get the lowered operands. Note that we do this after 2992 // checking if NumResults is zero, because with zero results 2993 // the operands won't have values in the map. 2994 SDValue Src = getValue(SrcV); 2995 SDValue Ptr = getValue(PtrV); 2996 2997 SDValue Root = getRoot(); 2998 SmallVector<SDValue, 4> Chains(NumValues); 2999 EVT PtrVT = Ptr.getValueType(); 3000 bool isVolatile = I.isVolatile(); 3001 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3002 unsigned Alignment = I.getAlignment(); 3003 3004 for (unsigned i = 0; i != NumValues; ++i) { 3005 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3006 DAG.getConstant(Offsets[i], PtrVT)); 3007 Chains[i] = DAG.getStore(Root, getCurDebugLoc(), 3008 SDValue(Src.getNode(), Src.getResNo() + i), 3009 Add, PtrV, Offsets[i], isVolatile, 3010 isNonTemporal, Alignment); 3011 } 3012 3013 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3014 MVT::Other, &Chains[0], NumValues)); 3015} 3016 3017/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3018/// node. 3019void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3020 unsigned Intrinsic) { 3021 bool HasChain = !I.doesNotAccessMemory(); 3022 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3023 3024 // Build the operand list. 3025 SmallVector<SDValue, 8> Ops; 3026 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3027 if (OnlyLoad) { 3028 // We don't need to serialize loads against other loads. 3029 Ops.push_back(DAG.getRoot()); 3030 } else { 3031 Ops.push_back(getRoot()); 3032 } 3033 } 3034 3035 // Info is set by getTgtMemInstrinsic 3036 TargetLowering::IntrinsicInfo Info; 3037 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3038 3039 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3040 if (!IsTgtIntrinsic) 3041 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3042 3043 // Add all operands of the call to the operand list. 3044 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3045 SDValue Op = getValue(I.getArgOperand(i)); 3046 assert(TLI.isTypeLegal(Op.getValueType()) && 3047 "Intrinsic uses a non-legal type?"); 3048 Ops.push_back(Op); 3049 } 3050 3051 SmallVector<EVT, 4> ValueVTs; 3052 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3053#ifndef NDEBUG 3054 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3055 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3056 "Intrinsic uses a non-legal type?"); 3057 } 3058#endif // NDEBUG 3059 3060 if (HasChain) 3061 ValueVTs.push_back(MVT::Other); 3062 3063 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3064 3065 // Create the node. 3066 SDValue Result; 3067 if (IsTgtIntrinsic) { 3068 // This is target intrinsic that touches memory 3069 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3070 VTs, &Ops[0], Ops.size(), 3071 Info.memVT, Info.ptrVal, Info.offset, 3072 Info.align, Info.vol, 3073 Info.readMem, Info.writeMem); 3074 } else if (!HasChain) { 3075 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3076 VTs, &Ops[0], Ops.size()); 3077 } else if (!I.getType()->isVoidTy()) { 3078 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3079 VTs, &Ops[0], Ops.size()); 3080 } else { 3081 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3082 VTs, &Ops[0], Ops.size()); 3083 } 3084 3085 if (HasChain) { 3086 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3087 if (OnlyLoad) 3088 PendingLoads.push_back(Chain); 3089 else 3090 DAG.setRoot(Chain); 3091 } 3092 3093 if (!I.getType()->isVoidTy()) { 3094 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3095 EVT VT = TLI.getValueType(PTy); 3096 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result); 3097 } 3098 3099 setValue(&I, Result); 3100 } 3101} 3102 3103/// GetSignificand - Get the significand and build it into a floating-point 3104/// number with exponent of 1: 3105/// 3106/// Op = (Op & 0x007fffff) | 0x3f800000; 3107/// 3108/// where Op is the hexidecimal representation of floating point value. 3109static SDValue 3110GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3111 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3112 DAG.getConstant(0x007fffff, MVT::i32)); 3113 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3114 DAG.getConstant(0x3f800000, MVT::i32)); 3115 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2); 3116} 3117 3118/// GetExponent - Get the exponent: 3119/// 3120/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3121/// 3122/// where Op is the hexidecimal representation of floating point value. 3123static SDValue 3124GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3125 DebugLoc dl) { 3126 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3127 DAG.getConstant(0x7f800000, MVT::i32)); 3128 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3129 DAG.getConstant(23, TLI.getPointerTy())); 3130 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3131 DAG.getConstant(127, MVT::i32)); 3132 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3133} 3134 3135/// getF32Constant - Get 32-bit floating point constant. 3136static SDValue 3137getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3138 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3139} 3140 3141/// Inlined utility function to implement binary input atomic intrinsics for 3142/// visitIntrinsicCall: I is a call instruction 3143/// Op is the associated NodeType for I 3144const char * 3145SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3146 ISD::NodeType Op) { 3147 SDValue Root = getRoot(); 3148 SDValue L = 3149 DAG.getAtomic(Op, getCurDebugLoc(), 3150 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3151 Root, 3152 getValue(I.getArgOperand(0)), 3153 getValue(I.getArgOperand(1)), 3154 I.getArgOperand(0)); 3155 setValue(&I, L); 3156 DAG.setRoot(L.getValue(1)); 3157 return 0; 3158} 3159 3160// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3161const char * 3162SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3163 SDValue Op1 = getValue(I.getArgOperand(0)); 3164 SDValue Op2 = getValue(I.getArgOperand(1)); 3165 3166 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3167 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3168 return 0; 3169} 3170 3171/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3172/// limited-precision mode. 3173void 3174SelectionDAGBuilder::visitExp(const CallInst &I) { 3175 SDValue result; 3176 DebugLoc dl = getCurDebugLoc(); 3177 3178 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3179 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3180 SDValue Op = getValue(I.getArgOperand(0)); 3181 3182 // Put the exponent in the right bit position for later addition to the 3183 // final result: 3184 // 3185 // #define LOG2OFe 1.4426950f 3186 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3187 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3188 getF32Constant(DAG, 0x3fb8aa3b)); 3189 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3190 3191 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3192 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3193 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3194 3195 // IntegerPartOfX <<= 23; 3196 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3197 DAG.getConstant(23, TLI.getPointerTy())); 3198 3199 if (LimitFloatPrecision <= 6) { 3200 // For floating-point precision of 6: 3201 // 3202 // TwoToFractionalPartOfX = 3203 // 0.997535578f + 3204 // (0.735607626f + 0.252464424f * x) * x; 3205 // 3206 // error 0.0144103317, which is 6 bits 3207 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3208 getF32Constant(DAG, 0x3e814304)); 3209 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3210 getF32Constant(DAG, 0x3f3c50c8)); 3211 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3212 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3213 getF32Constant(DAG, 0x3f7f5e7e)); 3214 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5); 3215 3216 // Add the exponent into the result in integer domain. 3217 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3218 TwoToFracPartOfX, IntegerPartOfX); 3219 3220 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6); 3221 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3222 // For floating-point precision of 12: 3223 // 3224 // TwoToFractionalPartOfX = 3225 // 0.999892986f + 3226 // (0.696457318f + 3227 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3228 // 3229 // 0.000107046256 error, which is 13 to 14 bits 3230 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3231 getF32Constant(DAG, 0x3da235e3)); 3232 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3233 getF32Constant(DAG, 0x3e65b8f3)); 3234 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3235 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3236 getF32Constant(DAG, 0x3f324b07)); 3237 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3238 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3239 getF32Constant(DAG, 0x3f7ff8fd)); 3240 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7); 3241 3242 // Add the exponent into the result in integer domain. 3243 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3244 TwoToFracPartOfX, IntegerPartOfX); 3245 3246 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8); 3247 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3248 // For floating-point precision of 18: 3249 // 3250 // TwoToFractionalPartOfX = 3251 // 0.999999982f + 3252 // (0.693148872f + 3253 // (0.240227044f + 3254 // (0.554906021e-1f + 3255 // (0.961591928e-2f + 3256 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3257 // 3258 // error 2.47208000*10^(-7), which is better than 18 bits 3259 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3260 getF32Constant(DAG, 0x3924b03e)); 3261 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3262 getF32Constant(DAG, 0x3ab24b87)); 3263 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3264 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3265 getF32Constant(DAG, 0x3c1d8c17)); 3266 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3267 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3268 getF32Constant(DAG, 0x3d634a1d)); 3269 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3270 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3271 getF32Constant(DAG, 0x3e75fe14)); 3272 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3273 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3274 getF32Constant(DAG, 0x3f317234)); 3275 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3276 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3277 getF32Constant(DAG, 0x3f800000)); 3278 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl, 3279 MVT::i32, t13); 3280 3281 // Add the exponent into the result in integer domain. 3282 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3283 TwoToFracPartOfX, IntegerPartOfX); 3284 3285 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14); 3286 } 3287 } else { 3288 // No special expansion. 3289 result = DAG.getNode(ISD::FEXP, dl, 3290 getValue(I.getArgOperand(0)).getValueType(), 3291 getValue(I.getArgOperand(0))); 3292 } 3293 3294 setValue(&I, result); 3295} 3296 3297/// visitLog - Lower a log intrinsic. Handles the special sequences for 3298/// limited-precision mode. 3299void 3300SelectionDAGBuilder::visitLog(const CallInst &I) { 3301 SDValue result; 3302 DebugLoc dl = getCurDebugLoc(); 3303 3304 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3305 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3306 SDValue Op = getValue(I.getArgOperand(0)); 3307 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3308 3309 // Scale the exponent by log(2) [0.69314718f]. 3310 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3311 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3312 getF32Constant(DAG, 0x3f317218)); 3313 3314 // Get the significand and build it into a floating-point number with 3315 // exponent of 1. 3316 SDValue X = GetSignificand(DAG, Op1, dl); 3317 3318 if (LimitFloatPrecision <= 6) { 3319 // For floating-point precision of 6: 3320 // 3321 // LogofMantissa = 3322 // -1.1609546f + 3323 // (1.4034025f - 0.23903021f * x) * x; 3324 // 3325 // error 0.0034276066, which is better than 8 bits 3326 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3327 getF32Constant(DAG, 0xbe74c456)); 3328 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3329 getF32Constant(DAG, 0x3fb3a2b1)); 3330 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3331 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3332 getF32Constant(DAG, 0x3f949a29)); 3333 3334 result = DAG.getNode(ISD::FADD, dl, 3335 MVT::f32, LogOfExponent, LogOfMantissa); 3336 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3337 // For floating-point precision of 12: 3338 // 3339 // LogOfMantissa = 3340 // -1.7417939f + 3341 // (2.8212026f + 3342 // (-1.4699568f + 3343 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3344 // 3345 // error 0.000061011436, which is 14 bits 3346 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3347 getF32Constant(DAG, 0xbd67b6d6)); 3348 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3349 getF32Constant(DAG, 0x3ee4f4b8)); 3350 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3351 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3352 getF32Constant(DAG, 0x3fbc278b)); 3353 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3354 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3355 getF32Constant(DAG, 0x40348e95)); 3356 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3357 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3358 getF32Constant(DAG, 0x3fdef31a)); 3359 3360 result = DAG.getNode(ISD::FADD, dl, 3361 MVT::f32, LogOfExponent, LogOfMantissa); 3362 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3363 // For floating-point precision of 18: 3364 // 3365 // LogOfMantissa = 3366 // -2.1072184f + 3367 // (4.2372794f + 3368 // (-3.7029485f + 3369 // (2.2781945f + 3370 // (-0.87823314f + 3371 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3372 // 3373 // error 0.0000023660568, which is better than 18 bits 3374 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3375 getF32Constant(DAG, 0xbc91e5ac)); 3376 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3377 getF32Constant(DAG, 0x3e4350aa)); 3378 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3379 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3380 getF32Constant(DAG, 0x3f60d3e3)); 3381 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3382 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3383 getF32Constant(DAG, 0x4011cdf0)); 3384 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3385 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3386 getF32Constant(DAG, 0x406cfd1c)); 3387 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3388 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3389 getF32Constant(DAG, 0x408797cb)); 3390 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3391 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3392 getF32Constant(DAG, 0x4006dcab)); 3393 3394 result = DAG.getNode(ISD::FADD, dl, 3395 MVT::f32, LogOfExponent, LogOfMantissa); 3396 } 3397 } else { 3398 // No special expansion. 3399 result = DAG.getNode(ISD::FLOG, dl, 3400 getValue(I.getArgOperand(0)).getValueType(), 3401 getValue(I.getArgOperand(0))); 3402 } 3403 3404 setValue(&I, result); 3405} 3406 3407/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3408/// limited-precision mode. 3409void 3410SelectionDAGBuilder::visitLog2(const CallInst &I) { 3411 SDValue result; 3412 DebugLoc dl = getCurDebugLoc(); 3413 3414 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3415 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3416 SDValue Op = getValue(I.getArgOperand(0)); 3417 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3418 3419 // Get the exponent. 3420 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3421 3422 // Get the significand and build it into a floating-point number with 3423 // exponent of 1. 3424 SDValue X = GetSignificand(DAG, Op1, dl); 3425 3426 // Different possible minimax approximations of significand in 3427 // floating-point for various degrees of accuracy over [1,2]. 3428 if (LimitFloatPrecision <= 6) { 3429 // For floating-point precision of 6: 3430 // 3431 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3432 // 3433 // error 0.0049451742, which is more than 7 bits 3434 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3435 getF32Constant(DAG, 0xbeb08fe0)); 3436 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3437 getF32Constant(DAG, 0x40019463)); 3438 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3439 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3440 getF32Constant(DAG, 0x3fd6633d)); 3441 3442 result = DAG.getNode(ISD::FADD, dl, 3443 MVT::f32, LogOfExponent, Log2ofMantissa); 3444 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3445 // For floating-point precision of 12: 3446 // 3447 // Log2ofMantissa = 3448 // -2.51285454f + 3449 // (4.07009056f + 3450 // (-2.12067489f + 3451 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3452 // 3453 // error 0.0000876136000, which is better than 13 bits 3454 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3455 getF32Constant(DAG, 0xbda7262e)); 3456 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3457 getF32Constant(DAG, 0x3f25280b)); 3458 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3459 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3460 getF32Constant(DAG, 0x4007b923)); 3461 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3462 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3463 getF32Constant(DAG, 0x40823e2f)); 3464 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3465 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3466 getF32Constant(DAG, 0x4020d29c)); 3467 3468 result = DAG.getNode(ISD::FADD, dl, 3469 MVT::f32, LogOfExponent, Log2ofMantissa); 3470 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3471 // For floating-point precision of 18: 3472 // 3473 // Log2ofMantissa = 3474 // -3.0400495f + 3475 // (6.1129976f + 3476 // (-5.3420409f + 3477 // (3.2865683f + 3478 // (-1.2669343f + 3479 // (0.27515199f - 3480 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3481 // 3482 // error 0.0000018516, which is better than 18 bits 3483 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3484 getF32Constant(DAG, 0xbcd2769e)); 3485 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3486 getF32Constant(DAG, 0x3e8ce0b9)); 3487 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3488 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3489 getF32Constant(DAG, 0x3fa22ae7)); 3490 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3491 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3492 getF32Constant(DAG, 0x40525723)); 3493 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3494 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3495 getF32Constant(DAG, 0x40aaf200)); 3496 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3497 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3498 getF32Constant(DAG, 0x40c39dad)); 3499 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3500 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3501 getF32Constant(DAG, 0x4042902c)); 3502 3503 result = DAG.getNode(ISD::FADD, dl, 3504 MVT::f32, LogOfExponent, Log2ofMantissa); 3505 } 3506 } else { 3507 // No special expansion. 3508 result = DAG.getNode(ISD::FLOG2, dl, 3509 getValue(I.getArgOperand(0)).getValueType(), 3510 getValue(I.getArgOperand(0))); 3511 } 3512 3513 setValue(&I, result); 3514} 3515 3516/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3517/// limited-precision mode. 3518void 3519SelectionDAGBuilder::visitLog10(const CallInst &I) { 3520 SDValue result; 3521 DebugLoc dl = getCurDebugLoc(); 3522 3523 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3524 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3525 SDValue Op = getValue(I.getArgOperand(0)); 3526 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3527 3528 // Scale the exponent by log10(2) [0.30102999f]. 3529 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3530 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3531 getF32Constant(DAG, 0x3e9a209a)); 3532 3533 // Get the significand and build it into a floating-point number with 3534 // exponent of 1. 3535 SDValue X = GetSignificand(DAG, Op1, dl); 3536 3537 if (LimitFloatPrecision <= 6) { 3538 // For floating-point precision of 6: 3539 // 3540 // Log10ofMantissa = 3541 // -0.50419619f + 3542 // (0.60948995f - 0.10380950f * x) * x; 3543 // 3544 // error 0.0014886165, which is 6 bits 3545 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3546 getF32Constant(DAG, 0xbdd49a13)); 3547 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3548 getF32Constant(DAG, 0x3f1c0789)); 3549 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3550 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3551 getF32Constant(DAG, 0x3f011300)); 3552 3553 result = DAG.getNode(ISD::FADD, dl, 3554 MVT::f32, LogOfExponent, Log10ofMantissa); 3555 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3556 // For floating-point precision of 12: 3557 // 3558 // Log10ofMantissa = 3559 // -0.64831180f + 3560 // (0.91751397f + 3561 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3562 // 3563 // error 0.00019228036, which is better than 12 bits 3564 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3565 getF32Constant(DAG, 0x3d431f31)); 3566 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3567 getF32Constant(DAG, 0x3ea21fb2)); 3568 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3569 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3570 getF32Constant(DAG, 0x3f6ae232)); 3571 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3572 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3573 getF32Constant(DAG, 0x3f25f7c3)); 3574 3575 result = DAG.getNode(ISD::FADD, dl, 3576 MVT::f32, LogOfExponent, Log10ofMantissa); 3577 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3578 // For floating-point precision of 18: 3579 // 3580 // Log10ofMantissa = 3581 // -0.84299375f + 3582 // (1.5327582f + 3583 // (-1.0688956f + 3584 // (0.49102474f + 3585 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3586 // 3587 // error 0.0000037995730, which is better than 18 bits 3588 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3589 getF32Constant(DAG, 0x3c5d51ce)); 3590 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3591 getF32Constant(DAG, 0x3e00685a)); 3592 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3593 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3594 getF32Constant(DAG, 0x3efb6798)); 3595 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3596 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3597 getF32Constant(DAG, 0x3f88d192)); 3598 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3599 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3600 getF32Constant(DAG, 0x3fc4316c)); 3601 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3602 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3603 getF32Constant(DAG, 0x3f57ce70)); 3604 3605 result = DAG.getNode(ISD::FADD, dl, 3606 MVT::f32, LogOfExponent, Log10ofMantissa); 3607 } 3608 } else { 3609 // No special expansion. 3610 result = DAG.getNode(ISD::FLOG10, dl, 3611 getValue(I.getArgOperand(0)).getValueType(), 3612 getValue(I.getArgOperand(0))); 3613 } 3614 3615 setValue(&I, result); 3616} 3617 3618/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3619/// limited-precision mode. 3620void 3621SelectionDAGBuilder::visitExp2(const CallInst &I) { 3622 SDValue result; 3623 DebugLoc dl = getCurDebugLoc(); 3624 3625 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3626 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3627 SDValue Op = getValue(I.getArgOperand(0)); 3628 3629 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3630 3631 // FractionalPartOfX = x - (float)IntegerPartOfX; 3632 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3633 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3634 3635 // IntegerPartOfX <<= 23; 3636 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3637 DAG.getConstant(23, TLI.getPointerTy())); 3638 3639 if (LimitFloatPrecision <= 6) { 3640 // For floating-point precision of 6: 3641 // 3642 // TwoToFractionalPartOfX = 3643 // 0.997535578f + 3644 // (0.735607626f + 0.252464424f * x) * x; 3645 // 3646 // error 0.0144103317, which is 6 bits 3647 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3648 getF32Constant(DAG, 0x3e814304)); 3649 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3650 getF32Constant(DAG, 0x3f3c50c8)); 3651 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3652 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3653 getF32Constant(DAG, 0x3f7f5e7e)); 3654 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3655 SDValue TwoToFractionalPartOfX = 3656 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3657 3658 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3659 MVT::f32, TwoToFractionalPartOfX); 3660 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3661 // For floating-point precision of 12: 3662 // 3663 // TwoToFractionalPartOfX = 3664 // 0.999892986f + 3665 // (0.696457318f + 3666 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3667 // 3668 // error 0.000107046256, which is 13 to 14 bits 3669 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3670 getF32Constant(DAG, 0x3da235e3)); 3671 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3672 getF32Constant(DAG, 0x3e65b8f3)); 3673 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3674 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3675 getF32Constant(DAG, 0x3f324b07)); 3676 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3677 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3678 getF32Constant(DAG, 0x3f7ff8fd)); 3679 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3680 SDValue TwoToFractionalPartOfX = 3681 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3682 3683 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3684 MVT::f32, TwoToFractionalPartOfX); 3685 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3686 // For floating-point precision of 18: 3687 // 3688 // TwoToFractionalPartOfX = 3689 // 0.999999982f + 3690 // (0.693148872f + 3691 // (0.240227044f + 3692 // (0.554906021e-1f + 3693 // (0.961591928e-2f + 3694 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3695 // error 2.47208000*10^(-7), which is better than 18 bits 3696 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3697 getF32Constant(DAG, 0x3924b03e)); 3698 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3699 getF32Constant(DAG, 0x3ab24b87)); 3700 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3701 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3702 getF32Constant(DAG, 0x3c1d8c17)); 3703 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3704 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3705 getF32Constant(DAG, 0x3d634a1d)); 3706 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3707 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3708 getF32Constant(DAG, 0x3e75fe14)); 3709 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3710 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3711 getF32Constant(DAG, 0x3f317234)); 3712 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3713 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3714 getF32Constant(DAG, 0x3f800000)); 3715 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3716 SDValue TwoToFractionalPartOfX = 3717 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3718 3719 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3720 MVT::f32, TwoToFractionalPartOfX); 3721 } 3722 } else { 3723 // No special expansion. 3724 result = DAG.getNode(ISD::FEXP2, dl, 3725 getValue(I.getArgOperand(0)).getValueType(), 3726 getValue(I.getArgOperand(0))); 3727 } 3728 3729 setValue(&I, result); 3730} 3731 3732/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3733/// limited-precision mode with x == 10.0f. 3734void 3735SelectionDAGBuilder::visitPow(const CallInst &I) { 3736 SDValue result; 3737 const Value *Val = I.getArgOperand(0); 3738 DebugLoc dl = getCurDebugLoc(); 3739 bool IsExp10 = false; 3740 3741 if (getValue(Val).getValueType() == MVT::f32 && 3742 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 3743 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3744 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3745 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3746 APFloat Ten(10.0f); 3747 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3748 } 3749 } 3750 } 3751 3752 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3753 SDValue Op = getValue(I.getArgOperand(1)); 3754 3755 // Put the exponent in the right bit position for later addition to the 3756 // final result: 3757 // 3758 // #define LOG2OF10 3.3219281f 3759 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3760 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3761 getF32Constant(DAG, 0x40549a78)); 3762 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3763 3764 // FractionalPartOfX = x - (float)IntegerPartOfX; 3765 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3766 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3767 3768 // IntegerPartOfX <<= 23; 3769 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3770 DAG.getConstant(23, TLI.getPointerTy())); 3771 3772 if (LimitFloatPrecision <= 6) { 3773 // For floating-point precision of 6: 3774 // 3775 // twoToFractionalPartOfX = 3776 // 0.997535578f + 3777 // (0.735607626f + 0.252464424f * x) * x; 3778 // 3779 // error 0.0144103317, which is 6 bits 3780 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3781 getF32Constant(DAG, 0x3e814304)); 3782 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3783 getF32Constant(DAG, 0x3f3c50c8)); 3784 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3785 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3786 getF32Constant(DAG, 0x3f7f5e7e)); 3787 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3788 SDValue TwoToFractionalPartOfX = 3789 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3790 3791 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3792 MVT::f32, TwoToFractionalPartOfX); 3793 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3794 // For floating-point precision of 12: 3795 // 3796 // TwoToFractionalPartOfX = 3797 // 0.999892986f + 3798 // (0.696457318f + 3799 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3800 // 3801 // error 0.000107046256, which is 13 to 14 bits 3802 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3803 getF32Constant(DAG, 0x3da235e3)); 3804 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3805 getF32Constant(DAG, 0x3e65b8f3)); 3806 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3807 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3808 getF32Constant(DAG, 0x3f324b07)); 3809 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3810 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3811 getF32Constant(DAG, 0x3f7ff8fd)); 3812 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3813 SDValue TwoToFractionalPartOfX = 3814 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3815 3816 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3817 MVT::f32, TwoToFractionalPartOfX); 3818 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3819 // For floating-point precision of 18: 3820 // 3821 // TwoToFractionalPartOfX = 3822 // 0.999999982f + 3823 // (0.693148872f + 3824 // (0.240227044f + 3825 // (0.554906021e-1f + 3826 // (0.961591928e-2f + 3827 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3828 // error 2.47208000*10^(-7), which is better than 18 bits 3829 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3830 getF32Constant(DAG, 0x3924b03e)); 3831 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3832 getF32Constant(DAG, 0x3ab24b87)); 3833 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3834 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3835 getF32Constant(DAG, 0x3c1d8c17)); 3836 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3837 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3838 getF32Constant(DAG, 0x3d634a1d)); 3839 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3840 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3841 getF32Constant(DAG, 0x3e75fe14)); 3842 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3843 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3844 getF32Constant(DAG, 0x3f317234)); 3845 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3846 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3847 getF32Constant(DAG, 0x3f800000)); 3848 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3849 SDValue TwoToFractionalPartOfX = 3850 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3851 3852 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3853 MVT::f32, TwoToFractionalPartOfX); 3854 } 3855 } else { 3856 // No special expansion. 3857 result = DAG.getNode(ISD::FPOW, dl, 3858 getValue(I.getArgOperand(0)).getValueType(), 3859 getValue(I.getArgOperand(0)), 3860 getValue(I.getArgOperand(1))); 3861 } 3862 3863 setValue(&I, result); 3864} 3865 3866 3867/// ExpandPowI - Expand a llvm.powi intrinsic. 3868static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 3869 SelectionDAG &DAG) { 3870 // If RHS is a constant, we can expand this out to a multiplication tree, 3871 // otherwise we end up lowering to a call to __powidf2 (for example). When 3872 // optimizing for size, we only want to do this if the expansion would produce 3873 // a small number of multiplies, otherwise we do the full expansion. 3874 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3875 // Get the exponent as a positive value. 3876 unsigned Val = RHSC->getSExtValue(); 3877 if ((int)Val < 0) Val = -Val; 3878 3879 // powi(x, 0) -> 1.0 3880 if (Val == 0) 3881 return DAG.getConstantFP(1.0, LHS.getValueType()); 3882 3883 const Function *F = DAG.getMachineFunction().getFunction(); 3884 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 3885 // If optimizing for size, don't insert too many multiplies. This 3886 // inserts up to 5 multiplies. 3887 CountPopulation_32(Val)+Log2_32(Val) < 7) { 3888 // We use the simple binary decomposition method to generate the multiply 3889 // sequence. There are more optimal ways to do this (for example, 3890 // powi(x,15) generates one more multiply than it should), but this has 3891 // the benefit of being both really simple and much better than a libcall. 3892 SDValue Res; // Logically starts equal to 1.0 3893 SDValue CurSquare = LHS; 3894 while (Val) { 3895 if (Val & 1) { 3896 if (Res.getNode()) 3897 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 3898 else 3899 Res = CurSquare; // 1.0*CurSquare. 3900 } 3901 3902 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 3903 CurSquare, CurSquare); 3904 Val >>= 1; 3905 } 3906 3907 // If the original was negative, invert the result, producing 1/(x*x*x). 3908 if (RHSC->getSExtValue() < 0) 3909 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 3910 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 3911 return Res; 3912 } 3913 } 3914 3915 // Otherwise, expand to a libcall. 3916 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 3917} 3918 3919/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 3920/// argument, create the corresponding DBG_VALUE machine instruction for it now. 3921/// At the end of instruction selection, they will be inserted to the entry BB. 3922bool 3923SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 3924 uint64_t Offset, 3925 const SDValue &N) { 3926 if (!isa<Argument>(V)) 3927 return false; 3928 3929 MachineFunction &MF = DAG.getMachineFunction(); 3930 // Ignore inlined function arguments here. 3931 DIVariable DV(Variable); 3932 if (DV.isInlinedFnArgument(MF.getFunction())) 3933 return false; 3934 3935 MachineBasicBlock *MBB = FuncInfo.MBB; 3936 if (MBB != &MF.front()) 3937 return false; 3938 3939 unsigned Reg = 0; 3940 if (N.getOpcode() == ISD::CopyFromReg) { 3941 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 3942 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 3943 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 3944 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 3945 if (PR) 3946 Reg = PR; 3947 } 3948 } 3949 3950 if (!Reg) { 3951 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 3952 if (VMI == FuncInfo.ValueMap.end()) 3953 return false; 3954 Reg = VMI->second; 3955 } 3956 3957 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 3958 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 3959 TII->get(TargetOpcode::DBG_VALUE)) 3960 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 3961 FuncInfo.ArgDbgValues.push_back(&*MIB); 3962 return true; 3963} 3964 3965// VisualStudio defines setjmp as _setjmp 3966#if defined(_MSC_VER) && defined(setjmp) 3967#define setjmp_undefined_for_visual_studio 3968#undef setjmp 3969#endif 3970 3971/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 3972/// we want to emit this as a call to a named external function, return the name 3973/// otherwise lower it and return null. 3974const char * 3975SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 3976 DebugLoc dl = getCurDebugLoc(); 3977 SDValue Res; 3978 3979 switch (Intrinsic) { 3980 default: 3981 // By default, turn this into a target intrinsic node. 3982 visitTargetIntrinsic(I, Intrinsic); 3983 return 0; 3984 case Intrinsic::vastart: visitVAStart(I); return 0; 3985 case Intrinsic::vaend: visitVAEnd(I); return 0; 3986 case Intrinsic::vacopy: visitVACopy(I); return 0; 3987 case Intrinsic::returnaddress: 3988 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 3989 getValue(I.getArgOperand(0)))); 3990 return 0; 3991 case Intrinsic::frameaddress: 3992 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 3993 getValue(I.getArgOperand(0)))); 3994 return 0; 3995 case Intrinsic::setjmp: 3996 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 3997 case Intrinsic::longjmp: 3998 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 3999 case Intrinsic::memcpy: { 4000 // Assert for address < 256 since we support only user defined address 4001 // spaces. 4002 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4003 < 256 && 4004 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4005 < 256 && 4006 "Unknown address space"); 4007 SDValue Op1 = getValue(I.getArgOperand(0)); 4008 SDValue Op2 = getValue(I.getArgOperand(1)); 4009 SDValue Op3 = getValue(I.getArgOperand(2)); 4010 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4011 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4012 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4013 I.getArgOperand(0), 0, I.getArgOperand(1), 0)); 4014 return 0; 4015 } 4016 case Intrinsic::memset: { 4017 // Assert for address < 256 since we support only user defined address 4018 // spaces. 4019 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4020 < 256 && 4021 "Unknown address space"); 4022 SDValue Op1 = getValue(I.getArgOperand(0)); 4023 SDValue Op2 = getValue(I.getArgOperand(1)); 4024 SDValue Op3 = getValue(I.getArgOperand(2)); 4025 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4026 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4027 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4028 I.getArgOperand(0), 0)); 4029 return 0; 4030 } 4031 case Intrinsic::memmove: { 4032 // Assert for address < 256 since we support only user defined address 4033 // spaces. 4034 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4035 < 256 && 4036 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4037 < 256 && 4038 "Unknown address space"); 4039 SDValue Op1 = getValue(I.getArgOperand(0)); 4040 SDValue Op2 = getValue(I.getArgOperand(1)); 4041 SDValue Op3 = getValue(I.getArgOperand(2)); 4042 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4043 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4044 4045 // If the source and destination are known to not be aliases, we can 4046 // lower memmove as memcpy. 4047 uint64_t Size = -1ULL; 4048 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 4049 Size = C->getZExtValue(); 4050 if (AA->alias(I.getArgOperand(0), Size, I.getArgOperand(1), Size) == 4051 AliasAnalysis::NoAlias) { 4052 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4053 false, I.getArgOperand(0), 0, 4054 I.getArgOperand(1), 0)); 4055 return 0; 4056 } 4057 4058 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4059 I.getArgOperand(0), 0, I.getArgOperand(1), 0)); 4060 return 0; 4061 } 4062 case Intrinsic::dbg_declare: { 4063 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4064 if (!DIVariable(DI.getVariable()).Verify()) 4065 return 0; 4066 4067 MDNode *Variable = DI.getVariable(); 4068 // Parameters are handled specially. 4069 bool isParameter = 4070 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4071 const Value *Address = DI.getAddress(); 4072 if (!Address) 4073 return 0; 4074 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4075 Address = BCI->getOperand(0); 4076 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4077 4078 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4079 // but do not always have a corresponding SDNode built. The SDNodeOrder 4080 // absolute, but not relative, values are different depending on whether 4081 // debug info exists. 4082 ++SDNodeOrder; 4083 SDValue &N = NodeMap[Address]; 4084 SDDbgValue *SDV; 4085 if (N.getNode()) { 4086 if (isParameter && !AI) { 4087 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4088 if (FINode) 4089 // Byval parameter. We have a frame index at this point. 4090 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4091 0, dl, SDNodeOrder); 4092 else 4093 // Can't do anything with other non-AI cases yet. This might be a 4094 // parameter of a callee function that got inlined, for example. 4095 return 0; 4096 } else if (AI) 4097 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4098 0, dl, SDNodeOrder); 4099 else 4100 // Can't do anything with other non-AI cases yet. 4101 return 0; 4102 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4103 } else { 4104 // This isn't useful, but it shows what we're missing. 4105 SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()), 4106 0, dl, SDNodeOrder); 4107 DAG.AddDbgValue(SDV, 0, isParameter); 4108 } 4109 return 0; 4110 } 4111 case Intrinsic::dbg_value: { 4112 const DbgValueInst &DI = cast<DbgValueInst>(I); 4113 if (!DIVariable(DI.getVariable()).Verify()) 4114 return 0; 4115 4116 MDNode *Variable = DI.getVariable(); 4117 uint64_t Offset = DI.getOffset(); 4118 const Value *V = DI.getValue(); 4119 if (!V) 4120 return 0; 4121 4122 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4123 // but do not always have a corresponding SDNode built. The SDNodeOrder 4124 // absolute, but not relative, values are different depending on whether 4125 // debug info exists. 4126 ++SDNodeOrder; 4127 SDDbgValue *SDV; 4128 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4129 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4130 DAG.AddDbgValue(SDV, 0, false); 4131 } else { 4132 bool createUndef = false; 4133 // Do not use getValue() in here; we don't want to generate code at 4134 // this point if it hasn't been done yet. 4135 SDValue N = NodeMap[V]; 4136 if (!N.getNode() && isa<Argument>(V)) 4137 // Check unused arguments map. 4138 N = UnusedArgNodeMap[V]; 4139 if (N.getNode()) { 4140 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4141 SDV = DAG.getDbgValue(Variable, N.getNode(), 4142 N.getResNo(), Offset, dl, SDNodeOrder); 4143 DAG.AddDbgValue(SDV, N.getNode(), false); 4144 } 4145 } else if (isa<PHINode>(V) && !V->use_empty() ) { 4146 // Do not call getValue(V) yet, as we don't want to generate code. 4147 // Remember it for later. 4148 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4149 DanglingDebugInfoMap[V] = DDI; 4150 } else 4151 createUndef = true; 4152 if (createUndef) { 4153 // We may expand this to cover more cases. One case where we have no 4154 // data available is an unreferenced parameter; we need this fallback. 4155 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()), 4156 Offset, dl, SDNodeOrder); 4157 DAG.AddDbgValue(SDV, 0, false); 4158 } 4159 } 4160 4161 // Build a debug info table entry. 4162 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4163 V = BCI->getOperand(0); 4164 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4165 // Don't handle byval struct arguments or VLAs, for example. 4166 if (!AI) 4167 return 0; 4168 DenseMap<const AllocaInst*, int>::iterator SI = 4169 FuncInfo.StaticAllocaMap.find(AI); 4170 if (SI == FuncInfo.StaticAllocaMap.end()) 4171 return 0; // VLAs. 4172 int FI = SI->second; 4173 4174 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4175 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4176 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4177 return 0; 4178 } 4179 case Intrinsic::eh_exception: { 4180 // Insert the EXCEPTIONADDR instruction. 4181 assert(FuncInfo.MBB->isLandingPad() && 4182 "Call to eh.exception not in landing pad!"); 4183 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4184 SDValue Ops[1]; 4185 Ops[0] = DAG.getRoot(); 4186 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4187 setValue(&I, Op); 4188 DAG.setRoot(Op.getValue(1)); 4189 return 0; 4190 } 4191 4192 case Intrinsic::eh_selector: { 4193 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4194 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4195 if (CallMBB->isLandingPad()) 4196 AddCatchInfo(I, &MMI, CallMBB); 4197 else { 4198#ifndef NDEBUG 4199 FuncInfo.CatchInfoLost.insert(&I); 4200#endif 4201 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4202 unsigned Reg = TLI.getExceptionSelectorRegister(); 4203 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4204 } 4205 4206 // Insert the EHSELECTION instruction. 4207 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4208 SDValue Ops[2]; 4209 Ops[0] = getValue(I.getArgOperand(0)); 4210 Ops[1] = getRoot(); 4211 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4212 DAG.setRoot(Op.getValue(1)); 4213 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4214 return 0; 4215 } 4216 4217 case Intrinsic::eh_typeid_for: { 4218 // Find the type id for the given typeinfo. 4219 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4220 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4221 Res = DAG.getConstant(TypeID, MVT::i32); 4222 setValue(&I, Res); 4223 return 0; 4224 } 4225 4226 case Intrinsic::eh_return_i32: 4227 case Intrinsic::eh_return_i64: 4228 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4229 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4230 MVT::Other, 4231 getControlRoot(), 4232 getValue(I.getArgOperand(0)), 4233 getValue(I.getArgOperand(1)))); 4234 return 0; 4235 case Intrinsic::eh_unwind_init: 4236 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4237 return 0; 4238 case Intrinsic::eh_dwarf_cfa: { 4239 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4240 TLI.getPointerTy()); 4241 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4242 TLI.getPointerTy(), 4243 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4244 TLI.getPointerTy()), 4245 CfaArg); 4246 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4247 TLI.getPointerTy(), 4248 DAG.getConstant(0, TLI.getPointerTy())); 4249 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4250 FA, Offset)); 4251 return 0; 4252 } 4253 case Intrinsic::eh_sjlj_callsite: { 4254 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4255 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4256 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4257 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4258 4259 MMI.setCurrentCallSite(CI->getZExtValue()); 4260 return 0; 4261 } 4262 case Intrinsic::eh_sjlj_setjmp: { 4263 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4264 getValue(I.getArgOperand(0)))); 4265 return 0; 4266 } 4267 case Intrinsic::eh_sjlj_longjmp: { 4268 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4269 getRoot(), 4270 getValue(I.getArgOperand(0)))); 4271 return 0; 4272 } 4273 4274 case Intrinsic::convertff: 4275 case Intrinsic::convertfsi: 4276 case Intrinsic::convertfui: 4277 case Intrinsic::convertsif: 4278 case Intrinsic::convertuif: 4279 case Intrinsic::convertss: 4280 case Intrinsic::convertsu: 4281 case Intrinsic::convertus: 4282 case Intrinsic::convertuu: { 4283 ISD::CvtCode Code = ISD::CVT_INVALID; 4284 switch (Intrinsic) { 4285 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4286 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4287 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4288 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4289 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4290 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4291 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4292 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4293 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4294 } 4295 EVT DestVT = TLI.getValueType(I.getType()); 4296 const Value *Op1 = I.getArgOperand(0); 4297 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4298 DAG.getValueType(DestVT), 4299 DAG.getValueType(getValue(Op1).getValueType()), 4300 getValue(I.getArgOperand(1)), 4301 getValue(I.getArgOperand(2)), 4302 Code); 4303 setValue(&I, Res); 4304 return 0; 4305 } 4306 case Intrinsic::sqrt: 4307 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4308 getValue(I.getArgOperand(0)).getValueType(), 4309 getValue(I.getArgOperand(0)))); 4310 return 0; 4311 case Intrinsic::powi: 4312 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4313 getValue(I.getArgOperand(1)), DAG)); 4314 return 0; 4315 case Intrinsic::sin: 4316 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4317 getValue(I.getArgOperand(0)).getValueType(), 4318 getValue(I.getArgOperand(0)))); 4319 return 0; 4320 case Intrinsic::cos: 4321 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4322 getValue(I.getArgOperand(0)).getValueType(), 4323 getValue(I.getArgOperand(0)))); 4324 return 0; 4325 case Intrinsic::log: 4326 visitLog(I); 4327 return 0; 4328 case Intrinsic::log2: 4329 visitLog2(I); 4330 return 0; 4331 case Intrinsic::log10: 4332 visitLog10(I); 4333 return 0; 4334 case Intrinsic::exp: 4335 visitExp(I); 4336 return 0; 4337 case Intrinsic::exp2: 4338 visitExp2(I); 4339 return 0; 4340 case Intrinsic::pow: 4341 visitPow(I); 4342 return 0; 4343 case Intrinsic::convert_to_fp16: 4344 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4345 MVT::i16, getValue(I.getArgOperand(0)))); 4346 return 0; 4347 case Intrinsic::convert_from_fp16: 4348 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4349 MVT::f32, getValue(I.getArgOperand(0)))); 4350 return 0; 4351 case Intrinsic::pcmarker: { 4352 SDValue Tmp = getValue(I.getArgOperand(0)); 4353 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4354 return 0; 4355 } 4356 case Intrinsic::readcyclecounter: { 4357 SDValue Op = getRoot(); 4358 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4359 DAG.getVTList(MVT::i64, MVT::Other), 4360 &Op, 1); 4361 setValue(&I, Res); 4362 DAG.setRoot(Res.getValue(1)); 4363 return 0; 4364 } 4365 case Intrinsic::bswap: 4366 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4367 getValue(I.getArgOperand(0)).getValueType(), 4368 getValue(I.getArgOperand(0)))); 4369 return 0; 4370 case Intrinsic::cttz: { 4371 SDValue Arg = getValue(I.getArgOperand(0)); 4372 EVT Ty = Arg.getValueType(); 4373 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4374 return 0; 4375 } 4376 case Intrinsic::ctlz: { 4377 SDValue Arg = getValue(I.getArgOperand(0)); 4378 EVT Ty = Arg.getValueType(); 4379 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4380 return 0; 4381 } 4382 case Intrinsic::ctpop: { 4383 SDValue Arg = getValue(I.getArgOperand(0)); 4384 EVT Ty = Arg.getValueType(); 4385 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4386 return 0; 4387 } 4388 case Intrinsic::stacksave: { 4389 SDValue Op = getRoot(); 4390 Res = DAG.getNode(ISD::STACKSAVE, dl, 4391 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4392 setValue(&I, Res); 4393 DAG.setRoot(Res.getValue(1)); 4394 return 0; 4395 } 4396 case Intrinsic::stackrestore: { 4397 Res = getValue(I.getArgOperand(0)); 4398 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4399 return 0; 4400 } 4401 case Intrinsic::stackprotector: { 4402 // Emit code into the DAG to store the stack guard onto the stack. 4403 MachineFunction &MF = DAG.getMachineFunction(); 4404 MachineFrameInfo *MFI = MF.getFrameInfo(); 4405 EVT PtrTy = TLI.getPointerTy(); 4406 4407 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4408 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4409 4410 int FI = FuncInfo.StaticAllocaMap[Slot]; 4411 MFI->setStackProtectorIndex(FI); 4412 4413 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4414 4415 // Store the stack protector onto the stack. 4416 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4417 PseudoSourceValue::getFixedStack(FI), 4418 0, true, false, 0); 4419 setValue(&I, Res); 4420 DAG.setRoot(Res); 4421 return 0; 4422 } 4423 case Intrinsic::objectsize: { 4424 // If we don't know by now, we're never going to know. 4425 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4426 4427 assert(CI && "Non-constant type in __builtin_object_size?"); 4428 4429 SDValue Arg = getValue(I.getCalledValue()); 4430 EVT Ty = Arg.getValueType(); 4431 4432 if (CI->isZero()) 4433 Res = DAG.getConstant(-1ULL, Ty); 4434 else 4435 Res = DAG.getConstant(0, Ty); 4436 4437 setValue(&I, Res); 4438 return 0; 4439 } 4440 case Intrinsic::var_annotation: 4441 // Discard annotate attributes 4442 return 0; 4443 4444 case Intrinsic::init_trampoline: { 4445 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4446 4447 SDValue Ops[6]; 4448 Ops[0] = getRoot(); 4449 Ops[1] = getValue(I.getArgOperand(0)); 4450 Ops[2] = getValue(I.getArgOperand(1)); 4451 Ops[3] = getValue(I.getArgOperand(2)); 4452 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4453 Ops[5] = DAG.getSrcValue(F); 4454 4455 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4456 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4457 Ops, 6); 4458 4459 setValue(&I, Res); 4460 DAG.setRoot(Res.getValue(1)); 4461 return 0; 4462 } 4463 case Intrinsic::gcroot: 4464 if (GFI) { 4465 const Value *Alloca = I.getArgOperand(0); 4466 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4467 4468 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4469 GFI->addStackRoot(FI->getIndex(), TypeMap); 4470 } 4471 return 0; 4472 case Intrinsic::gcread: 4473 case Intrinsic::gcwrite: 4474 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4475 return 0; 4476 case Intrinsic::flt_rounds: 4477 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4478 return 0; 4479 case Intrinsic::trap: 4480 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4481 return 0; 4482 case Intrinsic::uadd_with_overflow: 4483 return implVisitAluOverflow(I, ISD::UADDO); 4484 case Intrinsic::sadd_with_overflow: 4485 return implVisitAluOverflow(I, ISD::SADDO); 4486 case Intrinsic::usub_with_overflow: 4487 return implVisitAluOverflow(I, ISD::USUBO); 4488 case Intrinsic::ssub_with_overflow: 4489 return implVisitAluOverflow(I, ISD::SSUBO); 4490 case Intrinsic::umul_with_overflow: 4491 return implVisitAluOverflow(I, ISD::UMULO); 4492 case Intrinsic::smul_with_overflow: 4493 return implVisitAluOverflow(I, ISD::SMULO); 4494 4495 case Intrinsic::prefetch: { 4496 SDValue Ops[4]; 4497 Ops[0] = getRoot(); 4498 Ops[1] = getValue(I.getArgOperand(0)); 4499 Ops[2] = getValue(I.getArgOperand(1)); 4500 Ops[3] = getValue(I.getArgOperand(2)); 4501 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4)); 4502 return 0; 4503 } 4504 4505 case Intrinsic::memory_barrier: { 4506 SDValue Ops[6]; 4507 Ops[0] = getRoot(); 4508 for (int x = 1; x < 6; ++x) 4509 Ops[x] = getValue(I.getArgOperand(x - 1)); 4510 4511 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4512 return 0; 4513 } 4514 case Intrinsic::atomic_cmp_swap: { 4515 SDValue Root = getRoot(); 4516 SDValue L = 4517 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4518 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 4519 Root, 4520 getValue(I.getArgOperand(0)), 4521 getValue(I.getArgOperand(1)), 4522 getValue(I.getArgOperand(2)), 4523 I.getArgOperand(0)); 4524 setValue(&I, L); 4525 DAG.setRoot(L.getValue(1)); 4526 return 0; 4527 } 4528 case Intrinsic::atomic_load_add: 4529 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4530 case Intrinsic::atomic_load_sub: 4531 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4532 case Intrinsic::atomic_load_or: 4533 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4534 case Intrinsic::atomic_load_xor: 4535 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4536 case Intrinsic::atomic_load_and: 4537 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4538 case Intrinsic::atomic_load_nand: 4539 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4540 case Intrinsic::atomic_load_max: 4541 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4542 case Intrinsic::atomic_load_min: 4543 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4544 case Intrinsic::atomic_load_umin: 4545 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4546 case Intrinsic::atomic_load_umax: 4547 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4548 case Intrinsic::atomic_swap: 4549 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4550 4551 case Intrinsic::invariant_start: 4552 case Intrinsic::lifetime_start: 4553 // Discard region information. 4554 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4555 return 0; 4556 case Intrinsic::invariant_end: 4557 case Intrinsic::lifetime_end: 4558 // Discard region information. 4559 return 0; 4560 } 4561} 4562 4563void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 4564 bool isTailCall, 4565 MachineBasicBlock *LandingPad) { 4566 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4567 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4568 const Type *RetTy = FTy->getReturnType(); 4569 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4570 MCSymbol *BeginLabel = 0; 4571 4572 TargetLowering::ArgListTy Args; 4573 TargetLowering::ArgListEntry Entry; 4574 Args.reserve(CS.arg_size()); 4575 4576 // Check whether the function can return without sret-demotion. 4577 SmallVector<ISD::OutputArg, 4> Outs; 4578 SmallVector<uint64_t, 4> Offsets; 4579 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4580 Outs, TLI, &Offsets); 4581 4582 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4583 FTy->isVarArg(), Outs, FTy->getContext()); 4584 4585 SDValue DemoteStackSlot; 4586 4587 if (!CanLowerReturn) { 4588 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4589 FTy->getReturnType()); 4590 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4591 FTy->getReturnType()); 4592 MachineFunction &MF = DAG.getMachineFunction(); 4593 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4594 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4595 4596 DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4597 Entry.Node = DemoteStackSlot; 4598 Entry.Ty = StackSlotPtrType; 4599 Entry.isSExt = false; 4600 Entry.isZExt = false; 4601 Entry.isInReg = false; 4602 Entry.isSRet = true; 4603 Entry.isNest = false; 4604 Entry.isByVal = false; 4605 Entry.Alignment = Align; 4606 Args.push_back(Entry); 4607 RetTy = Type::getVoidTy(FTy->getContext()); 4608 } 4609 4610 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4611 i != e; ++i) { 4612 SDValue ArgNode = getValue(*i); 4613 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 4614 4615 unsigned attrInd = i - CS.arg_begin() + 1; 4616 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4617 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4618 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4619 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4620 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4621 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4622 Entry.Alignment = CS.getParamAlignment(attrInd); 4623 Args.push_back(Entry); 4624 } 4625 4626 if (LandingPad) { 4627 // Insert a label before the invoke call to mark the try range. This can be 4628 // used to detect deletion of the invoke via the MachineModuleInfo. 4629 BeginLabel = MMI.getContext().CreateTempSymbol(); 4630 4631 // For SjLj, keep track of which landing pads go with which invokes 4632 // so as to maintain the ordering of pads in the LSDA. 4633 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 4634 if (CallSiteIndex) { 4635 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4636 // Now that the call site is handled, stop tracking it. 4637 MMI.setCurrentCallSite(0); 4638 } 4639 4640 // Both PendingLoads and PendingExports must be flushed here; 4641 // this call might not return. 4642 (void)getRoot(); 4643 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4644 } 4645 4646 // Check if target-independent constraints permit a tail call here. 4647 // Target-dependent constraints are checked within TLI.LowerCallTo. 4648 if (isTailCall && 4649 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4650 isTailCall = false; 4651 4652 std::pair<SDValue,SDValue> Result = 4653 TLI.LowerCallTo(getRoot(), RetTy, 4654 CS.paramHasAttr(0, Attribute::SExt), 4655 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4656 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4657 CS.getCallingConv(), 4658 isTailCall, 4659 !CS.getInstruction()->use_empty(), 4660 Callee, Args, DAG, getCurDebugLoc()); 4661 assert((isTailCall || Result.second.getNode()) && 4662 "Non-null chain expected with non-tail call!"); 4663 assert((Result.second.getNode() || !Result.first.getNode()) && 4664 "Null value expected with tail call!"); 4665 if (Result.first.getNode()) { 4666 setValue(CS.getInstruction(), Result.first); 4667 } else if (!CanLowerReturn && Result.second.getNode()) { 4668 // The instruction result is the result of loading from the 4669 // hidden sret parameter. 4670 SmallVector<EVT, 1> PVTs; 4671 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 4672 4673 ComputeValueVTs(TLI, PtrRetTy, PVTs); 4674 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 4675 EVT PtrVT = PVTs[0]; 4676 unsigned NumValues = Outs.size(); 4677 SmallVector<SDValue, 4> Values(NumValues); 4678 SmallVector<SDValue, 4> Chains(NumValues); 4679 4680 for (unsigned i = 0; i < NumValues; ++i) { 4681 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 4682 DemoteStackSlot, 4683 DAG.getConstant(Offsets[i], PtrVT)); 4684 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 4685 Add, NULL, Offsets[i], false, false, 1); 4686 Values[i] = L; 4687 Chains[i] = L.getValue(1); 4688 } 4689 4690 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 4691 MVT::Other, &Chains[0], NumValues); 4692 PendingLoads.push_back(Chain); 4693 4694 // Collect the legal value parts into potentially illegal values 4695 // that correspond to the original function's return values. 4696 SmallVector<EVT, 4> RetTys; 4697 RetTy = FTy->getReturnType(); 4698 ComputeValueVTs(TLI, RetTy, RetTys); 4699 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4700 SmallVector<SDValue, 4> ReturnValues; 4701 unsigned CurReg = 0; 4702 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4703 EVT VT = RetTys[I]; 4704 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 4705 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 4706 4707 SDValue ReturnValue = 4708 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 4709 RegisterVT, VT, AssertOp); 4710 ReturnValues.push_back(ReturnValue); 4711 CurReg += NumRegs; 4712 } 4713 4714 setValue(CS.getInstruction(), 4715 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 4716 DAG.getVTList(&RetTys[0], RetTys.size()), 4717 &ReturnValues[0], ReturnValues.size())); 4718 4719 } 4720 4721 // As a special case, a null chain means that a tail call has been emitted and 4722 // the DAG root is already updated. 4723 if (Result.second.getNode()) 4724 DAG.setRoot(Result.second); 4725 else 4726 HasTailCall = true; 4727 4728 if (LandingPad) { 4729 // Insert a label at the end of the invoke call to mark the try range. This 4730 // can be used to detect deletion of the invoke via the MachineModuleInfo. 4731 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 4732 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 4733 4734 // Inform MachineModuleInfo of range. 4735 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 4736 } 4737} 4738 4739/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 4740/// value is equal or not-equal to zero. 4741static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 4742 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 4743 UI != E; ++UI) { 4744 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 4745 if (IC->isEquality()) 4746 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 4747 if (C->isNullValue()) 4748 continue; 4749 // Unknown instruction. 4750 return false; 4751 } 4752 return true; 4753} 4754 4755static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 4756 const Type *LoadTy, 4757 SelectionDAGBuilder &Builder) { 4758 4759 // Check to see if this load can be trivially constant folded, e.g. if the 4760 // input is from a string literal. 4761 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 4762 // Cast pointer to the type we really want to load. 4763 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 4764 PointerType::getUnqual(LoadTy)); 4765 4766 if (const Constant *LoadCst = 4767 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 4768 Builder.TD)) 4769 return Builder.getValue(LoadCst); 4770 } 4771 4772 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 4773 // still constant memory, the input chain can be the entry node. 4774 SDValue Root; 4775 bool ConstantMemory = false; 4776 4777 // Do not serialize (non-volatile) loads of constant memory with anything. 4778 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 4779 Root = Builder.DAG.getEntryNode(); 4780 ConstantMemory = true; 4781 } else { 4782 // Do not serialize non-volatile loads against each other. 4783 Root = Builder.DAG.getRoot(); 4784 } 4785 4786 SDValue Ptr = Builder.getValue(PtrVal); 4787 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 4788 Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/, 4789 false /*volatile*/, 4790 false /*nontemporal*/, 1 /* align=1 */); 4791 4792 if (!ConstantMemory) 4793 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 4794 return LoadVal; 4795} 4796 4797 4798/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 4799/// If so, return true and lower it, otherwise return false and it will be 4800/// lowered like a normal call. 4801bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 4802 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 4803 if (I.getNumArgOperands() != 3) 4804 return false; 4805 4806 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 4807 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 4808 !I.getArgOperand(2)->getType()->isIntegerTy() || 4809 !I.getType()->isIntegerTy()) 4810 return false; 4811 4812 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 4813 4814 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 4815 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 4816 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 4817 bool ActuallyDoIt = true; 4818 MVT LoadVT; 4819 const Type *LoadTy; 4820 switch (Size->getZExtValue()) { 4821 default: 4822 LoadVT = MVT::Other; 4823 LoadTy = 0; 4824 ActuallyDoIt = false; 4825 break; 4826 case 2: 4827 LoadVT = MVT::i16; 4828 LoadTy = Type::getInt16Ty(Size->getContext()); 4829 break; 4830 case 4: 4831 LoadVT = MVT::i32; 4832 LoadTy = Type::getInt32Ty(Size->getContext()); 4833 break; 4834 case 8: 4835 LoadVT = MVT::i64; 4836 LoadTy = Type::getInt64Ty(Size->getContext()); 4837 break; 4838 /* 4839 case 16: 4840 LoadVT = MVT::v4i32; 4841 LoadTy = Type::getInt32Ty(Size->getContext()); 4842 LoadTy = VectorType::get(LoadTy, 4); 4843 break; 4844 */ 4845 } 4846 4847 // This turns into unaligned loads. We only do this if the target natively 4848 // supports the MVT we'll be loading or if it is small enough (<= 4) that 4849 // we'll only produce a small number of byte loads. 4850 4851 // Require that we can find a legal MVT, and only do this if the target 4852 // supports unaligned loads of that type. Expanding into byte loads would 4853 // bloat the code. 4854 if (ActuallyDoIt && Size->getZExtValue() > 4) { 4855 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 4856 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 4857 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 4858 ActuallyDoIt = false; 4859 } 4860 4861 if (ActuallyDoIt) { 4862 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 4863 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 4864 4865 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 4866 ISD::SETNE); 4867 EVT CallVT = TLI.getValueType(I.getType(), true); 4868 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 4869 return true; 4870 } 4871 } 4872 4873 4874 return false; 4875} 4876 4877 4878void SelectionDAGBuilder::visitCall(const CallInst &I) { 4879 // Handle inline assembly differently. 4880 if (isa<InlineAsm>(I.getCalledValue())) { 4881 visitInlineAsm(&I); 4882 return; 4883 } 4884 4885 const char *RenameFn = 0; 4886 if (Function *F = I.getCalledFunction()) { 4887 if (F->isDeclaration()) { 4888 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 4889 if (unsigned IID = II->getIntrinsicID(F)) { 4890 RenameFn = visitIntrinsicCall(I, IID); 4891 if (!RenameFn) 4892 return; 4893 } 4894 } 4895 if (unsigned IID = F->getIntrinsicID()) { 4896 RenameFn = visitIntrinsicCall(I, IID); 4897 if (!RenameFn) 4898 return; 4899 } 4900 } 4901 4902 // Check for well-known libc/libm calls. If the function is internal, it 4903 // can't be a library call. 4904 if (!F->hasLocalLinkage() && F->hasName()) { 4905 StringRef Name = F->getName(); 4906 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 4907 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 4908 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4909 I.getType() == I.getArgOperand(0)->getType() && 4910 I.getType() == I.getArgOperand(1)->getType()) { 4911 SDValue LHS = getValue(I.getArgOperand(0)); 4912 SDValue RHS = getValue(I.getArgOperand(1)); 4913 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 4914 LHS.getValueType(), LHS, RHS)); 4915 return; 4916 } 4917 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 4918 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 4919 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4920 I.getType() == I.getArgOperand(0)->getType()) { 4921 SDValue Tmp = getValue(I.getArgOperand(0)); 4922 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 4923 Tmp.getValueType(), Tmp)); 4924 return; 4925 } 4926 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 4927 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 4928 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4929 I.getType() == I.getArgOperand(0)->getType() && 4930 I.onlyReadsMemory()) { 4931 SDValue Tmp = getValue(I.getArgOperand(0)); 4932 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 4933 Tmp.getValueType(), Tmp)); 4934 return; 4935 } 4936 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 4937 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 4938 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4939 I.getType() == I.getArgOperand(0)->getType() && 4940 I.onlyReadsMemory()) { 4941 SDValue Tmp = getValue(I.getArgOperand(0)); 4942 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 4943 Tmp.getValueType(), Tmp)); 4944 return; 4945 } 4946 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 4947 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 4948 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4949 I.getType() == I.getArgOperand(0)->getType() && 4950 I.onlyReadsMemory()) { 4951 SDValue Tmp = getValue(I.getArgOperand(0)); 4952 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 4953 Tmp.getValueType(), Tmp)); 4954 return; 4955 } 4956 } else if (Name == "memcmp") { 4957 if (visitMemCmpCall(I)) 4958 return; 4959 } 4960 } 4961 } 4962 4963 SDValue Callee; 4964 if (!RenameFn) 4965 Callee = getValue(I.getCalledValue()); 4966 else 4967 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 4968 4969 // Check if we can potentially perform a tail call. More detailed checking is 4970 // be done within LowerCallTo, after more information about the call is known. 4971 LowerCallTo(&I, Callee, I.isTailCall()); 4972} 4973 4974namespace llvm { 4975 4976/// AsmOperandInfo - This contains information for each constraint that we are 4977/// lowering. 4978class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo : 4979 public TargetLowering::AsmOperandInfo { 4980public: 4981 /// CallOperand - If this is the result output operand or a clobber 4982 /// this is null, otherwise it is the incoming operand to the CallInst. 4983 /// This gets modified as the asm is processed. 4984 SDValue CallOperand; 4985 4986 /// AssignedRegs - If this is a register or register class operand, this 4987 /// contains the set of register corresponding to the operand. 4988 RegsForValue AssignedRegs; 4989 4990 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info) 4991 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 4992 } 4993 4994 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 4995 /// busy in OutputRegs/InputRegs. 4996 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 4997 std::set<unsigned> &OutputRegs, 4998 std::set<unsigned> &InputRegs, 4999 const TargetRegisterInfo &TRI) const { 5000 if (isOutReg) { 5001 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5002 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5003 } 5004 if (isInReg) { 5005 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5006 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5007 } 5008 } 5009 5010 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5011 /// corresponds to. If there is no Value* for this operand, it returns 5012 /// MVT::Other. 5013 EVT getCallOperandValEVT(LLVMContext &Context, 5014 const TargetLowering &TLI, 5015 const TargetData *TD) const { 5016 if (CallOperandVal == 0) return MVT::Other; 5017 5018 if (isa<BasicBlock>(CallOperandVal)) 5019 return TLI.getPointerTy(); 5020 5021 const llvm::Type *OpTy = CallOperandVal->getType(); 5022 5023 // If this is an indirect operand, the operand is a pointer to the 5024 // accessed type. 5025 if (isIndirect) { 5026 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5027 if (!PtrTy) 5028 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5029 OpTy = PtrTy->getElementType(); 5030 } 5031 5032 // If OpTy is not a single value, it may be a struct/union that we 5033 // can tile with integers. 5034 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5035 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5036 switch (BitSize) { 5037 default: break; 5038 case 1: 5039 case 8: 5040 case 16: 5041 case 32: 5042 case 64: 5043 case 128: 5044 OpTy = IntegerType::get(Context, BitSize); 5045 break; 5046 } 5047 } 5048 5049 return TLI.getValueType(OpTy, true); 5050 } 5051 5052private: 5053 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5054 /// specified set. 5055 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5056 const TargetRegisterInfo &TRI) { 5057 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5058 Regs.insert(Reg); 5059 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5060 for (; *Aliases; ++Aliases) 5061 Regs.insert(*Aliases); 5062 } 5063}; 5064 5065} // end llvm namespace. 5066 5067/// isAllocatableRegister - If the specified register is safe to allocate, 5068/// i.e. it isn't a stack pointer or some other special register, return the 5069/// register class for the register. Otherwise, return null. 5070static const TargetRegisterClass * 5071isAllocatableRegister(unsigned Reg, MachineFunction &MF, 5072 const TargetLowering &TLI, 5073 const TargetRegisterInfo *TRI) { 5074 EVT FoundVT = MVT::Other; 5075 const TargetRegisterClass *FoundRC = 0; 5076 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 5077 E = TRI->regclass_end(); RCI != E; ++RCI) { 5078 EVT ThisVT = MVT::Other; 5079 5080 const TargetRegisterClass *RC = *RCI; 5081 // If none of the value types for this register class are valid, we 5082 // can't use it. For example, 64-bit reg classes on 32-bit targets. 5083 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 5084 I != E; ++I) { 5085 if (TLI.isTypeLegal(*I)) { 5086 // If we have already found this register in a different register class, 5087 // choose the one with the largest VT specified. For example, on 5088 // PowerPC, we favor f64 register classes over f32. 5089 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 5090 ThisVT = *I; 5091 break; 5092 } 5093 } 5094 } 5095 5096 if (ThisVT == MVT::Other) continue; 5097 5098 // NOTE: This isn't ideal. In particular, this might allocate the 5099 // frame pointer in functions that need it (due to them not being taken 5100 // out of allocation, because a variable sized allocation hasn't been seen 5101 // yet). This is a slight code pessimization, but should still work. 5102 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 5103 E = RC->allocation_order_end(MF); I != E; ++I) 5104 if (*I == Reg) { 5105 // We found a matching register class. Keep looking at others in case 5106 // we find one with larger registers that this physreg is also in. 5107 FoundRC = RC; 5108 FoundVT = ThisVT; 5109 break; 5110 } 5111 } 5112 return FoundRC; 5113} 5114 5115/// GetRegistersForValue - Assign registers (virtual or physical) for the 5116/// specified operand. We prefer to assign virtual registers, to allow the 5117/// register allocator to handle the assignment process. However, if the asm 5118/// uses features that we can't model on machineinstrs, we have SDISel do the 5119/// allocation. This produces generally horrible, but correct, code. 5120/// 5121/// OpInfo describes the operand. 5122/// Input and OutputRegs are the set of already allocated physical registers. 5123/// 5124void SelectionDAGBuilder:: 5125GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, 5126 std::set<unsigned> &OutputRegs, 5127 std::set<unsigned> &InputRegs) { 5128 LLVMContext &Context = FuncInfo.Fn->getContext(); 5129 5130 // Compute whether this value requires an input register, an output register, 5131 // or both. 5132 bool isOutReg = false; 5133 bool isInReg = false; 5134 switch (OpInfo.Type) { 5135 case InlineAsm::isOutput: 5136 isOutReg = true; 5137 5138 // If there is an input constraint that matches this, we need to reserve 5139 // the input register so no other inputs allocate to it. 5140 isInReg = OpInfo.hasMatchingInput(); 5141 break; 5142 case InlineAsm::isInput: 5143 isInReg = true; 5144 isOutReg = false; 5145 break; 5146 case InlineAsm::isClobber: 5147 isOutReg = true; 5148 isInReg = true; 5149 break; 5150 } 5151 5152 5153 MachineFunction &MF = DAG.getMachineFunction(); 5154 SmallVector<unsigned, 4> Regs; 5155 5156 // If this is a constraint for a single physreg, or a constraint for a 5157 // register class, find it. 5158 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5159 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5160 OpInfo.ConstraintVT); 5161 5162 unsigned NumRegs = 1; 5163 if (OpInfo.ConstraintVT != MVT::Other) { 5164 // If this is a FP input in an integer register (or visa versa) insert a bit 5165 // cast of the input value. More generally, handle any case where the input 5166 // value disagrees with the register class we plan to stick this in. 5167 if (OpInfo.Type == InlineAsm::isInput && 5168 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5169 // Try to convert to the first EVT that the reg class contains. If the 5170 // types are identical size, use a bitcast to convert (e.g. two differing 5171 // vector types). 5172 EVT RegVT = *PhysReg.second->vt_begin(); 5173 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5174 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5175 RegVT, OpInfo.CallOperand); 5176 OpInfo.ConstraintVT = RegVT; 5177 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5178 // If the input is a FP value and we want it in FP registers, do a 5179 // bitcast to the corresponding integer type. This turns an f64 value 5180 // into i64, which can be passed with two i32 values on a 32-bit 5181 // machine. 5182 RegVT = EVT::getIntegerVT(Context, 5183 OpInfo.ConstraintVT.getSizeInBits()); 5184 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5185 RegVT, OpInfo.CallOperand); 5186 OpInfo.ConstraintVT = RegVT; 5187 } 5188 } 5189 5190 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5191 } 5192 5193 EVT RegVT; 5194 EVT ValueVT = OpInfo.ConstraintVT; 5195 5196 // If this is a constraint for a specific physical register, like {r17}, 5197 // assign it now. 5198 if (unsigned AssignedReg = PhysReg.first) { 5199 const TargetRegisterClass *RC = PhysReg.second; 5200 if (OpInfo.ConstraintVT == MVT::Other) 5201 ValueVT = *RC->vt_begin(); 5202 5203 // Get the actual register value type. This is important, because the user 5204 // may have asked for (e.g.) the AX register in i32 type. We need to 5205 // remember that AX is actually i16 to get the right extension. 5206 RegVT = *RC->vt_begin(); 5207 5208 // This is a explicit reference to a physical register. 5209 Regs.push_back(AssignedReg); 5210 5211 // If this is an expanded reference, add the rest of the regs to Regs. 5212 if (NumRegs != 1) { 5213 TargetRegisterClass::iterator I = RC->begin(); 5214 for (; *I != AssignedReg; ++I) 5215 assert(I != RC->end() && "Didn't find reg!"); 5216 5217 // Already added the first reg. 5218 --NumRegs; ++I; 5219 for (; NumRegs; --NumRegs, ++I) { 5220 assert(I != RC->end() && "Ran out of registers to allocate!"); 5221 Regs.push_back(*I); 5222 } 5223 } 5224 5225 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5226 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5227 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5228 return; 5229 } 5230 5231 // Otherwise, if this was a reference to an LLVM register class, create vregs 5232 // for this reference. 5233 if (const TargetRegisterClass *RC = PhysReg.second) { 5234 RegVT = *RC->vt_begin(); 5235 if (OpInfo.ConstraintVT == MVT::Other) 5236 ValueVT = RegVT; 5237 5238 // Create the appropriate number of virtual registers. 5239 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5240 for (; NumRegs; --NumRegs) 5241 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5242 5243 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5244 return; 5245 } 5246 5247 // This is a reference to a register class that doesn't directly correspond 5248 // to an LLVM register class. Allocate NumRegs consecutive, available, 5249 // registers from the class. 5250 std::vector<unsigned> RegClassRegs 5251 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 5252 OpInfo.ConstraintVT); 5253 5254 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5255 unsigned NumAllocated = 0; 5256 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 5257 unsigned Reg = RegClassRegs[i]; 5258 // See if this register is available. 5259 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 5260 (isInReg && InputRegs.count(Reg))) { // Already used. 5261 // Make sure we find consecutive registers. 5262 NumAllocated = 0; 5263 continue; 5264 } 5265 5266 // Check to see if this register is allocatable (i.e. don't give out the 5267 // stack pointer). 5268 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); 5269 if (!RC) { // Couldn't allocate this register. 5270 // Reset NumAllocated to make sure we return consecutive registers. 5271 NumAllocated = 0; 5272 continue; 5273 } 5274 5275 // Okay, this register is good, we can use it. 5276 ++NumAllocated; 5277 5278 // If we allocated enough consecutive registers, succeed. 5279 if (NumAllocated == NumRegs) { 5280 unsigned RegStart = (i-NumAllocated)+1; 5281 unsigned RegEnd = i+1; 5282 // Mark all of the allocated registers used. 5283 for (unsigned i = RegStart; i != RegEnd; ++i) 5284 Regs.push_back(RegClassRegs[i]); 5285 5286 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 5287 OpInfo.ConstraintVT); 5288 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5289 return; 5290 } 5291 } 5292 5293 // Otherwise, we couldn't allocate enough registers for this. 5294} 5295 5296/// visitInlineAsm - Handle a call to an InlineAsm object. 5297/// 5298void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5299 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5300 5301 /// ConstraintOperands - Information about all of the constraints. 5302 std::vector<SDISelAsmOperandInfo> ConstraintOperands; 5303 5304 std::set<unsigned> OutputRegs, InputRegs; 5305 5306 // Do a prepass over the constraints, canonicalizing them, and building up the 5307 // ConstraintOperands list. 5308 std::vector<InlineAsm::ConstraintInfo> 5309 ConstraintInfos = IA->ParseConstraints(); 5310 5311 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI); 5312 5313 SDValue Chain, Flag; 5314 5315 // We won't need to flush pending loads if this asm doesn't touch 5316 // memory and is nonvolatile. 5317 if (hasMemory || IA->hasSideEffects()) 5318 Chain = getRoot(); 5319 else 5320 Chain = DAG.getRoot(); 5321 5322 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5323 unsigned ResNo = 0; // ResNo - The result number of the next output. 5324 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 5325 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); 5326 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5327 5328 EVT OpVT = MVT::Other; 5329 5330 // Compute the value type for each operand. 5331 switch (OpInfo.Type) { 5332 case InlineAsm::isOutput: 5333 // Indirect outputs just consume an argument. 5334 if (OpInfo.isIndirect) { 5335 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5336 break; 5337 } 5338 5339 // The return value of the call is this value. As such, there is no 5340 // corresponding argument. 5341 assert(!CS.getType()->isVoidTy() && 5342 "Bad inline asm!"); 5343 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5344 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5345 } else { 5346 assert(ResNo == 0 && "Asm only has one result!"); 5347 OpVT = TLI.getValueType(CS.getType()); 5348 } 5349 ++ResNo; 5350 break; 5351 case InlineAsm::isInput: 5352 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5353 break; 5354 case InlineAsm::isClobber: 5355 // Nothing to do. 5356 break; 5357 } 5358 5359 // If this is an input or an indirect output, process the call argument. 5360 // BasicBlocks are labels, currently appearing only in asm's. 5361 if (OpInfo.CallOperandVal) { 5362 // Strip bitcasts, if any. This mostly comes up for functions. 5363 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts(); 5364 5365 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5366 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5367 } else { 5368 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5369 } 5370 5371 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5372 } 5373 5374 OpInfo.ConstraintVT = OpVT; 5375 } 5376 5377 // Second pass over the constraints: compute which constraint option to use 5378 // and assign registers to constraints that want a specific physreg. 5379 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 5380 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5381 5382 // If this is an output operand with a matching input operand, look up the 5383 // matching input. If their types mismatch, e.g. one is an integer, the 5384 // other is floating point, or their sizes are different, flag it as an 5385 // error. 5386 if (OpInfo.hasMatchingInput()) { 5387 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5388 5389 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5390 if ((OpInfo.ConstraintVT.isInteger() != 5391 Input.ConstraintVT.isInteger()) || 5392 (OpInfo.ConstraintVT.getSizeInBits() != 5393 Input.ConstraintVT.getSizeInBits())) { 5394 report_fatal_error("Unsupported asm: input constraint" 5395 " with a matching output constraint of" 5396 " incompatible type!"); 5397 } 5398 Input.ConstraintVT = OpInfo.ConstraintVT; 5399 } 5400 } 5401 5402 // Compute the constraint code and ConstraintType to use. 5403 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5404 5405 // If this is a memory input, and if the operand is not indirect, do what we 5406 // need to to provide an address for the memory input. 5407 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5408 !OpInfo.isIndirect) { 5409 assert(OpInfo.Type == InlineAsm::isInput && 5410 "Can only indirectify direct input operands!"); 5411 5412 // Memory operands really want the address of the value. If we don't have 5413 // an indirect input, put it in the constpool if we can, otherwise spill 5414 // it to a stack slot. 5415 5416 // If the operand is a float, integer, or vector constant, spill to a 5417 // constant pool entry to get its address. 5418 const Value *OpVal = OpInfo.CallOperandVal; 5419 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5420 isa<ConstantVector>(OpVal)) { 5421 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5422 TLI.getPointerTy()); 5423 } else { 5424 // Otherwise, create a stack slot and emit a store to it before the 5425 // asm. 5426 const Type *Ty = OpVal->getType(); 5427 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5428 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5429 MachineFunction &MF = DAG.getMachineFunction(); 5430 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5431 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5432 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5433 OpInfo.CallOperand, StackSlot, NULL, 0, 5434 false, false, 0); 5435 OpInfo.CallOperand = StackSlot; 5436 } 5437 5438 // There is no longer a Value* corresponding to this operand. 5439 OpInfo.CallOperandVal = 0; 5440 5441 // It is now an indirect operand. 5442 OpInfo.isIndirect = true; 5443 } 5444 5445 // If this constraint is for a specific register, allocate it before 5446 // anything else. 5447 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5448 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5449 } 5450 5451 ConstraintInfos.clear(); 5452 5453 // Second pass - Loop over all of the operands, assigning virtual or physregs 5454 // to register class operands. 5455 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5456 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5457 5458 // C_Register operands have already been allocated, Other/Memory don't need 5459 // to be. 5460 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5461 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5462 } 5463 5464 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5465 std::vector<SDValue> AsmNodeOperands; 5466 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5467 AsmNodeOperands.push_back( 5468 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5469 TLI.getPointerTy())); 5470 5471 // If we have a !srcloc metadata node associated with it, we want to attach 5472 // this to the ultimately generated inline asm machineinstr. To do this, we 5473 // pass in the third operand as this (potentially null) inline asm MDNode. 5474 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5475 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5476 5477 // Remember the AlignStack bit as operand 3. 5478 AsmNodeOperands.push_back(DAG.getTargetConstant(IA->isAlignStack() ? 1 : 0, 5479 MVT::i1)); 5480 5481 // Loop over all of the inputs, copying the operand values into the 5482 // appropriate registers and processing the output regs. 5483 RegsForValue RetValRegs; 5484 5485 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5486 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5487 5488 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5489 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5490 5491 switch (OpInfo.Type) { 5492 case InlineAsm::isOutput: { 5493 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5494 OpInfo.ConstraintType != TargetLowering::C_Register) { 5495 // Memory output, or 'other' output (e.g. 'X' constraint). 5496 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5497 5498 // Add information to the INLINEASM node to know about this output. 5499 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5500 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5501 TLI.getPointerTy())); 5502 AsmNodeOperands.push_back(OpInfo.CallOperand); 5503 break; 5504 } 5505 5506 // Otherwise, this is a register or register class output. 5507 5508 // Copy the output from the appropriate register. Find a register that 5509 // we can use. 5510 if (OpInfo.AssignedRegs.Regs.empty()) 5511 report_fatal_error("Couldn't allocate output reg for constraint '" + 5512 Twine(OpInfo.ConstraintCode) + "'!"); 5513 5514 // If this is an indirect operand, store through the pointer after the 5515 // asm. 5516 if (OpInfo.isIndirect) { 5517 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5518 OpInfo.CallOperandVal)); 5519 } else { 5520 // This is the result value of the call. 5521 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5522 // Concatenate this output onto the outputs list. 5523 RetValRegs.append(OpInfo.AssignedRegs); 5524 } 5525 5526 // Add information to the INLINEASM node to know that this register is 5527 // set. 5528 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5529 InlineAsm::Kind_RegDefEarlyClobber : 5530 InlineAsm::Kind_RegDef, 5531 false, 5532 0, 5533 DAG, 5534 AsmNodeOperands); 5535 break; 5536 } 5537 case InlineAsm::isInput: { 5538 SDValue InOperandVal = OpInfo.CallOperand; 5539 5540 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5541 // If this is required to match an output register we have already set, 5542 // just use its register. 5543 unsigned OperandNo = OpInfo.getMatchedOperand(); 5544 5545 // Scan until we find the definition we already emitted of this operand. 5546 // When we find it, create a RegsForValue operand. 5547 unsigned CurOp = InlineAsm::Op_FirstOperand; 5548 for (; OperandNo; --OperandNo) { 5549 // Advance to the next operand. 5550 unsigned OpFlag = 5551 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5552 assert((InlineAsm::isRegDefKind(OpFlag) || 5553 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5554 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5555 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5556 } 5557 5558 unsigned OpFlag = 5559 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5560 if (InlineAsm::isRegDefKind(OpFlag) || 5561 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5562 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5563 if (OpInfo.isIndirect) { 5564 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5565 LLVMContext &Ctx = *DAG.getContext(); 5566 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5567 " don't know how to handle tied " 5568 "indirect register inputs"); 5569 } 5570 5571 RegsForValue MatchedRegs; 5572 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5573 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5574 MatchedRegs.RegVTs.push_back(RegVT); 5575 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5576 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5577 i != e; ++i) 5578 MatchedRegs.Regs.push_back 5579 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5580 5581 // Use the produced MatchedRegs object to 5582 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5583 Chain, &Flag); 5584 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 5585 true, OpInfo.getMatchedOperand(), 5586 DAG, AsmNodeOperands); 5587 break; 5588 } 5589 5590 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 5591 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 5592 "Unexpected number of operands"); 5593 // Add information to the INLINEASM node to know about this input. 5594 // See InlineAsm.h isUseOperandTiedToDef. 5595 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 5596 OpInfo.getMatchedOperand()); 5597 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5598 TLI.getPointerTy())); 5599 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5600 break; 5601 } 5602 5603 // Treat indirect 'X' constraint as memory. 5604 if (OpInfo.ConstraintType == TargetLowering::C_Other && 5605 OpInfo.isIndirect) 5606 OpInfo.ConstraintType = TargetLowering::C_Memory; 5607 5608 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5609 std::vector<SDValue> Ops; 5610 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 5611 Ops, DAG); 5612 if (Ops.empty()) 5613 report_fatal_error("Invalid operand for inline asm constraint '" + 5614 Twine(OpInfo.ConstraintCode) + "'!"); 5615 5616 // Add information to the INLINEASM node to know about this input. 5617 unsigned ResOpType = 5618 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 5619 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5620 TLI.getPointerTy())); 5621 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5622 break; 5623 } 5624 5625 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5626 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5627 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5628 "Memory operands expect pointer values"); 5629 5630 // Add information to the INLINEASM node to know about this input. 5631 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5632 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5633 TLI.getPointerTy())); 5634 AsmNodeOperands.push_back(InOperandVal); 5635 break; 5636 } 5637 5638 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5639 OpInfo.ConstraintType == TargetLowering::C_Register) && 5640 "Unknown constraint type!"); 5641 assert(!OpInfo.isIndirect && 5642 "Don't know how to handle indirect register inputs yet!"); 5643 5644 // Copy the input into the appropriate registers. 5645 if (OpInfo.AssignedRegs.Regs.empty() || 5646 !OpInfo.AssignedRegs.areValueTypesLegal(TLI)) 5647 report_fatal_error("Couldn't allocate input reg for constraint '" + 5648 Twine(OpInfo.ConstraintCode) + "'!"); 5649 5650 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5651 Chain, &Flag); 5652 5653 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 5654 DAG, AsmNodeOperands); 5655 break; 5656 } 5657 case InlineAsm::isClobber: { 5658 // Add the clobbered value to the operand list, so that the register 5659 // allocator is aware that the physreg got clobbered. 5660 if (!OpInfo.AssignedRegs.Regs.empty()) 5661 OpInfo.AssignedRegs.AddInlineAsmOperands( 5662 InlineAsm::Kind_RegDefEarlyClobber, 5663 false, 0, DAG, 5664 AsmNodeOperands); 5665 break; 5666 } 5667 } 5668 } 5669 5670 // Finish up input operands. Set the input chain and add the flag last. 5671 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 5672 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5673 5674 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5675 DAG.getVTList(MVT::Other, MVT::Flag), 5676 &AsmNodeOperands[0], AsmNodeOperands.size()); 5677 Flag = Chain.getValue(1); 5678 5679 // If this asm returns a register value, copy the result from that register 5680 // and set it as the value of the call. 5681 if (!RetValRegs.Regs.empty()) { 5682 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5683 Chain, &Flag); 5684 5685 // FIXME: Why don't we do this for inline asms with MRVs? 5686 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5687 EVT ResultType = TLI.getValueType(CS.getType()); 5688 5689 // If any of the results of the inline asm is a vector, it may have the 5690 // wrong width/num elts. This can happen for register classes that can 5691 // contain multiple different value types. The preg or vreg allocated may 5692 // not have the same VT as was expected. Convert it to the right type 5693 // with bit_convert. 5694 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5695 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5696 ResultType, Val); 5697 5698 } else if (ResultType != Val.getValueType() && 5699 ResultType.isInteger() && Val.getValueType().isInteger()) { 5700 // If a result value was tied to an input value, the computed result may 5701 // have a wider width than the expected result. Extract the relevant 5702 // portion. 5703 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 5704 } 5705 5706 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 5707 } 5708 5709 setValue(CS.getInstruction(), Val); 5710 // Don't need to use this as a chain in this case. 5711 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 5712 return; 5713 } 5714 5715 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 5716 5717 // Process indirect outputs, first output all of the flagged copies out of 5718 // physregs. 5719 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 5720 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 5721 const Value *Ptr = IndirectStoresToEmit[i].second; 5722 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5723 Chain, &Flag); 5724 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 5725 } 5726 5727 // Emit the non-flagged stores from the physregs. 5728 SmallVector<SDValue, 8> OutChains; 5729 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 5730 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 5731 StoresToEmit[i].first, 5732 getValue(StoresToEmit[i].second), 5733 StoresToEmit[i].second, 0, 5734 false, false, 0); 5735 OutChains.push_back(Val); 5736 } 5737 5738 if (!OutChains.empty()) 5739 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 5740 &OutChains[0], OutChains.size()); 5741 5742 DAG.setRoot(Chain); 5743} 5744 5745void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 5746 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 5747 MVT::Other, getRoot(), 5748 getValue(I.getArgOperand(0)), 5749 DAG.getSrcValue(I.getArgOperand(0)))); 5750} 5751 5752void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 5753 const TargetData &TD = *TLI.getTargetData(); 5754 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 5755 getRoot(), getValue(I.getOperand(0)), 5756 DAG.getSrcValue(I.getOperand(0)), 5757 TD.getABITypeAlignment(I.getType())); 5758 setValue(&I, V); 5759 DAG.setRoot(V.getValue(1)); 5760} 5761 5762void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 5763 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 5764 MVT::Other, getRoot(), 5765 getValue(I.getArgOperand(0)), 5766 DAG.getSrcValue(I.getArgOperand(0)))); 5767} 5768 5769void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 5770 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 5771 MVT::Other, getRoot(), 5772 getValue(I.getArgOperand(0)), 5773 getValue(I.getArgOperand(1)), 5774 DAG.getSrcValue(I.getArgOperand(0)), 5775 DAG.getSrcValue(I.getArgOperand(1)))); 5776} 5777 5778/// TargetLowering::LowerCallTo - This is the default LowerCallTo 5779/// implementation, which just calls LowerCall. 5780/// FIXME: When all targets are 5781/// migrated to using LowerCall, this hook should be integrated into SDISel. 5782std::pair<SDValue, SDValue> 5783TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 5784 bool RetSExt, bool RetZExt, bool isVarArg, 5785 bool isInreg, unsigned NumFixedArgs, 5786 CallingConv::ID CallConv, bool isTailCall, 5787 bool isReturnValueUsed, 5788 SDValue Callee, 5789 ArgListTy &Args, SelectionDAG &DAG, 5790 DebugLoc dl) const { 5791 // Handle all of the outgoing arguments. 5792 SmallVector<ISD::OutputArg, 32> Outs; 5793 SmallVector<SDValue, 32> OutVals; 5794 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 5795 SmallVector<EVT, 4> ValueVTs; 5796 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 5797 for (unsigned Value = 0, NumValues = ValueVTs.size(); 5798 Value != NumValues; ++Value) { 5799 EVT VT = ValueVTs[Value]; 5800 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 5801 SDValue Op = SDValue(Args[i].Node.getNode(), 5802 Args[i].Node.getResNo() + Value); 5803 ISD::ArgFlagsTy Flags; 5804 unsigned OriginalAlignment = 5805 getTargetData()->getABITypeAlignment(ArgTy); 5806 5807 if (Args[i].isZExt) 5808 Flags.setZExt(); 5809 if (Args[i].isSExt) 5810 Flags.setSExt(); 5811 if (Args[i].isInReg) 5812 Flags.setInReg(); 5813 if (Args[i].isSRet) 5814 Flags.setSRet(); 5815 if (Args[i].isByVal) { 5816 Flags.setByVal(); 5817 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 5818 const Type *ElementTy = Ty->getElementType(); 5819 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 5820 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy); 5821 // For ByVal, alignment should come from FE. BE will guess if this 5822 // info is not there but there are cases it cannot get right. 5823 if (Args[i].Alignment) 5824 FrameAlign = Args[i].Alignment; 5825 Flags.setByValAlign(FrameAlign); 5826 Flags.setByValSize(FrameSize); 5827 } 5828 if (Args[i].isNest) 5829 Flags.setNest(); 5830 Flags.setOrigAlign(OriginalAlignment); 5831 5832 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 5833 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 5834 SmallVector<SDValue, 4> Parts(NumParts); 5835 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 5836 5837 if (Args[i].isSExt) 5838 ExtendKind = ISD::SIGN_EXTEND; 5839 else if (Args[i].isZExt) 5840 ExtendKind = ISD::ZERO_EXTEND; 5841 5842 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 5843 PartVT, ExtendKind); 5844 5845 for (unsigned j = 0; j != NumParts; ++j) { 5846 // if it isn't first piece, alignment must be 1 5847 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 5848 i < NumFixedArgs); 5849 if (NumParts > 1 && j == 0) 5850 MyFlags.Flags.setSplit(); 5851 else if (j != 0) 5852 MyFlags.Flags.setOrigAlign(1); 5853 5854 Outs.push_back(MyFlags); 5855 OutVals.push_back(Parts[j]); 5856 } 5857 } 5858 } 5859 5860 // Handle the incoming return values from the call. 5861 SmallVector<ISD::InputArg, 32> Ins; 5862 SmallVector<EVT, 4> RetTys; 5863 ComputeValueVTs(*this, RetTy, RetTys); 5864 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5865 EVT VT = RetTys[I]; 5866 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5867 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5868 for (unsigned i = 0; i != NumRegs; ++i) { 5869 ISD::InputArg MyFlags; 5870 MyFlags.VT = RegisterVT; 5871 MyFlags.Used = isReturnValueUsed; 5872 if (RetSExt) 5873 MyFlags.Flags.setSExt(); 5874 if (RetZExt) 5875 MyFlags.Flags.setZExt(); 5876 if (isInreg) 5877 MyFlags.Flags.setInReg(); 5878 Ins.push_back(MyFlags); 5879 } 5880 } 5881 5882 SmallVector<SDValue, 4> InVals; 5883 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 5884 Outs, OutVals, Ins, dl, DAG, InVals); 5885 5886 // Verify that the target's LowerCall behaved as expected. 5887 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 5888 "LowerCall didn't return a valid chain!"); 5889 assert((!isTailCall || InVals.empty()) && 5890 "LowerCall emitted a return value for a tail call!"); 5891 assert((isTailCall || InVals.size() == Ins.size()) && 5892 "LowerCall didn't emit the correct number of values!"); 5893 5894 // For a tail call, the return value is merely live-out and there aren't 5895 // any nodes in the DAG representing it. Return a special value to 5896 // indicate that a tail call has been emitted and no more Instructions 5897 // should be processed in the current block. 5898 if (isTailCall) { 5899 DAG.setRoot(Chain); 5900 return std::make_pair(SDValue(), SDValue()); 5901 } 5902 5903 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 5904 assert(InVals[i].getNode() && 5905 "LowerCall emitted a null value!"); 5906 assert(Ins[i].VT == InVals[i].getValueType() && 5907 "LowerCall emitted a value with the wrong type!"); 5908 }); 5909 5910 // Collect the legal value parts into potentially illegal values 5911 // that correspond to the original function's return values. 5912 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5913 if (RetSExt) 5914 AssertOp = ISD::AssertSext; 5915 else if (RetZExt) 5916 AssertOp = ISD::AssertZext; 5917 SmallVector<SDValue, 4> ReturnValues; 5918 unsigned CurReg = 0; 5919 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5920 EVT VT = RetTys[I]; 5921 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5922 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5923 5924 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 5925 NumRegs, RegisterVT, VT, 5926 AssertOp)); 5927 CurReg += NumRegs; 5928 } 5929 5930 // For a function returning void, there is no return value. We can't create 5931 // such a node, so we just return a null return value in that case. In 5932 // that case, nothing will actualy look at the value. 5933 if (ReturnValues.empty()) 5934 return std::make_pair(SDValue(), Chain); 5935 5936 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 5937 DAG.getVTList(&RetTys[0], RetTys.size()), 5938 &ReturnValues[0], ReturnValues.size()); 5939 return std::make_pair(Res, Chain); 5940} 5941 5942void TargetLowering::LowerOperationWrapper(SDNode *N, 5943 SmallVectorImpl<SDValue> &Results, 5944 SelectionDAG &DAG) const { 5945 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 5946 if (Res.getNode()) 5947 Results.push_back(Res); 5948} 5949 5950SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 5951 llvm_unreachable("LowerOperation not implemented for this target!"); 5952 return SDValue(); 5953} 5954 5955void 5956SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 5957 SDValue Op = getNonRegisterValue(V); 5958 assert((Op.getOpcode() != ISD::CopyFromReg || 5959 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 5960 "Copy from a reg to the same reg!"); 5961 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 5962 5963 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 5964 SDValue Chain = DAG.getEntryNode(); 5965 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 5966 PendingExports.push_back(Chain); 5967} 5968 5969#include "llvm/CodeGen/SelectionDAGISel.h" 5970 5971void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 5972 // If this is the entry block, emit arguments. 5973 const Function &F = *LLVMBB->getParent(); 5974 SelectionDAG &DAG = SDB->DAG; 5975 DebugLoc dl = SDB->getCurDebugLoc(); 5976 const TargetData *TD = TLI.getTargetData(); 5977 SmallVector<ISD::InputArg, 16> Ins; 5978 5979 // Check whether the function can return without sret-demotion. 5980 SmallVector<ISD::OutputArg, 4> Outs; 5981 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 5982 Outs, TLI); 5983 5984 if (!FuncInfo->CanLowerReturn) { 5985 // Put in an sret pointer parameter before all the other parameters. 5986 SmallVector<EVT, 1> ValueVTs; 5987 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 5988 5989 // NOTE: Assuming that a pointer will never break down to more than one VT 5990 // or one register. 5991 ISD::ArgFlagsTy Flags; 5992 Flags.setSRet(); 5993 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 5994 ISD::InputArg RetArg(Flags, RegisterVT, true); 5995 Ins.push_back(RetArg); 5996 } 5997 5998 // Set up the incoming argument description vector. 5999 unsigned Idx = 1; 6000 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6001 I != E; ++I, ++Idx) { 6002 SmallVector<EVT, 4> ValueVTs; 6003 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6004 bool isArgValueUsed = !I->use_empty(); 6005 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6006 Value != NumValues; ++Value) { 6007 EVT VT = ValueVTs[Value]; 6008 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6009 ISD::ArgFlagsTy Flags; 6010 unsigned OriginalAlignment = 6011 TD->getABITypeAlignment(ArgTy); 6012 6013 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6014 Flags.setZExt(); 6015 if (F.paramHasAttr(Idx, Attribute::SExt)) 6016 Flags.setSExt(); 6017 if (F.paramHasAttr(Idx, Attribute::InReg)) 6018 Flags.setInReg(); 6019 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6020 Flags.setSRet(); 6021 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6022 Flags.setByVal(); 6023 const PointerType *Ty = cast<PointerType>(I->getType()); 6024 const Type *ElementTy = Ty->getElementType(); 6025 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6026 unsigned FrameSize = TD->getTypeAllocSize(ElementTy); 6027 // For ByVal, alignment should be passed from FE. BE will guess if 6028 // this info is not there but there are cases it cannot get right. 6029 if (F.getParamAlignment(Idx)) 6030 FrameAlign = F.getParamAlignment(Idx); 6031 Flags.setByValAlign(FrameAlign); 6032 Flags.setByValSize(FrameSize); 6033 } 6034 if (F.paramHasAttr(Idx, Attribute::Nest)) 6035 Flags.setNest(); 6036 Flags.setOrigAlign(OriginalAlignment); 6037 6038 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6039 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6040 for (unsigned i = 0; i != NumRegs; ++i) { 6041 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6042 if (NumRegs > 1 && i == 0) 6043 MyFlags.Flags.setSplit(); 6044 // if it isn't first piece, alignment must be 1 6045 else if (i > 0) 6046 MyFlags.Flags.setOrigAlign(1); 6047 Ins.push_back(MyFlags); 6048 } 6049 } 6050 } 6051 6052 // Call the target to set up the argument values. 6053 SmallVector<SDValue, 8> InVals; 6054 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6055 F.isVarArg(), Ins, 6056 dl, DAG, InVals); 6057 6058 // Verify that the target's LowerFormalArguments behaved as expected. 6059 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6060 "LowerFormalArguments didn't return a valid chain!"); 6061 assert(InVals.size() == Ins.size() && 6062 "LowerFormalArguments didn't emit the correct number of values!"); 6063 DEBUG({ 6064 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6065 assert(InVals[i].getNode() && 6066 "LowerFormalArguments emitted a null value!"); 6067 assert(Ins[i].VT == InVals[i].getValueType() && 6068 "LowerFormalArguments emitted a value with the wrong type!"); 6069 } 6070 }); 6071 6072 // Update the DAG with the new chain value resulting from argument lowering. 6073 DAG.setRoot(NewRoot); 6074 6075 // Set up the argument values. 6076 unsigned i = 0; 6077 Idx = 1; 6078 if (!FuncInfo->CanLowerReturn) { 6079 // Create a virtual register for the sret pointer, and put in a copy 6080 // from the sret argument into it. 6081 SmallVector<EVT, 1> ValueVTs; 6082 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6083 EVT VT = ValueVTs[0]; 6084 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6085 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6086 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6087 RegVT, VT, AssertOp); 6088 6089 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6090 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6091 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6092 FuncInfo->DemoteRegister = SRetReg; 6093 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6094 SRetReg, ArgValue); 6095 DAG.setRoot(NewRoot); 6096 6097 // i indexes lowered arguments. Bump it past the hidden sret argument. 6098 // Idx indexes LLVM arguments. Don't touch it. 6099 ++i; 6100 } 6101 6102 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6103 ++I, ++Idx) { 6104 SmallVector<SDValue, 4> ArgValues; 6105 SmallVector<EVT, 4> ValueVTs; 6106 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6107 unsigned NumValues = ValueVTs.size(); 6108 6109 // If this argument is unused then remember its value. It is used to generate 6110 // debugging information. 6111 if (I->use_empty() && NumValues) 6112 SDB->setUnusedArgValue(I, InVals[i]); 6113 6114 for (unsigned Value = 0; Value != NumValues; ++Value) { 6115 EVT VT = ValueVTs[Value]; 6116 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6117 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6118 6119 if (!I->use_empty()) { 6120 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6121 if (F.paramHasAttr(Idx, Attribute::SExt)) 6122 AssertOp = ISD::AssertSext; 6123 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6124 AssertOp = ISD::AssertZext; 6125 6126 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6127 NumParts, PartVT, VT, 6128 AssertOp)); 6129 } 6130 6131 i += NumParts; 6132 } 6133 6134 if (!I->use_empty()) { 6135 SDValue Res; 6136 if (!ArgValues.empty()) 6137 Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6138 SDB->getCurDebugLoc()); 6139 SDB->setValue(I, Res); 6140 6141 // If this argument is live outside of the entry block, insert a copy from 6142 // whereever we got it to the vreg that other BB's will reference it as. 6143 SDB->CopyToExportRegsIfNeeded(I); 6144 } 6145 } 6146 6147 assert(i == InVals.size() && "Argument register count mismatch!"); 6148 6149 // Finally, if the target has anything special to do, allow it to do so. 6150 // FIXME: this should insert code into the DAG! 6151 EmitFunctionEntryCode(); 6152} 6153 6154/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6155/// ensure constants are generated when needed. Remember the virtual registers 6156/// that need to be added to the Machine PHI nodes as input. We cannot just 6157/// directly add them, because expansion might result in multiple MBB's for one 6158/// BB. As such, the start of the BB might correspond to a different MBB than 6159/// the end. 6160/// 6161void 6162SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6163 const TerminatorInst *TI = LLVMBB->getTerminator(); 6164 6165 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6166 6167 // Check successor nodes' PHI nodes that expect a constant to be available 6168 // from this block. 6169 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6170 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6171 if (!isa<PHINode>(SuccBB->begin())) continue; 6172 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6173 6174 // If this terminator has multiple identical successors (common for 6175 // switches), only handle each succ once. 6176 if (!SuccsHandled.insert(SuccMBB)) continue; 6177 6178 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6179 6180 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6181 // nodes and Machine PHI nodes, but the incoming operands have not been 6182 // emitted yet. 6183 for (BasicBlock::const_iterator I = SuccBB->begin(); 6184 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6185 // Ignore dead phi's. 6186 if (PN->use_empty()) continue; 6187 6188 unsigned Reg; 6189 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6190 6191 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6192 unsigned &RegOut = ConstantsOut[C]; 6193 if (RegOut == 0) { 6194 RegOut = FuncInfo.CreateRegs(C->getType()); 6195 CopyValueToVirtualRegister(C, RegOut); 6196 } 6197 Reg = RegOut; 6198 } else { 6199 DenseMap<const Value *, unsigned>::iterator I = 6200 FuncInfo.ValueMap.find(PHIOp); 6201 if (I != FuncInfo.ValueMap.end()) 6202 Reg = I->second; 6203 else { 6204 assert(isa<AllocaInst>(PHIOp) && 6205 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6206 "Didn't codegen value into a register!??"); 6207 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6208 CopyValueToVirtualRegister(PHIOp, Reg); 6209 } 6210 } 6211 6212 // Remember that this register needs to added to the machine PHI node as 6213 // the input for this MBB. 6214 SmallVector<EVT, 4> ValueVTs; 6215 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6216 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6217 EVT VT = ValueVTs[vti]; 6218 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6219 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6220 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6221 Reg += NumRegisters; 6222 } 6223 } 6224 } 6225 ConstantsOut.clear(); 6226} 6227