SelectionDAGBuilder.cpp revision 9da9934e27dfb48de77b80a3e20ed2d869b52024
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/PseudoSourceValue.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Analysis/DebugInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameLowering.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72// Limit the width of DAG chains. This is important in general to prevent 73// prevent DAG-based analysis from blowing up. For example, alias analysis and 74// load clustering may not complete in reasonable time. It is difficult to 75// recognize and avoid this situation within each individual analysis, and 76// future analyses are likely to have the same behavior. Limiting DAG width is 77// the safe approach, and will be especially important with global DAGs. 78// 79// MaxParallelChains default is arbitrarily high to avoid affecting 80// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81// sequence over this should have been converted to llvm.memcpy by the 82// frontend. It easy to induce this behavior with .ll code such as: 83// %buffer = alloca [4096 x i8] 84// %data = load [4096 x i8]* %argPtr 85// store [4096 x i8] %data, [4096 x i8]* %buffer 86static const unsigned MaxParallelChains = 64; 87 88static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92/// getCopyFromParts - Create a value that contains the specified legal parts 93/// combined into the value they represent. If the parts combine to a type 94/// larger then ValueVT then AssertOp can be used to specify whether the extra 95/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96/// (ISD::AssertSext). 97static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getIntPtrConstant(1)); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209 return SDValue(); 210} 211 212/// getCopyFromParts - Create a value that contains the specified legal parts 213/// combined into the value they represent. If the parts combine to a type 214/// larger then ValueVT then AssertOp can be used to specify whether the extra 215/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216/// (ISD::AssertSext). 217static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 287 "Cannot handle this kind of promotion"); 288 // Promoted vector extract 289 bool Smaller = ValueVT.bitsLE(PartVT); 290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 291 DL, ValueVT, Val); 292 293 } 294 295 // Trivial bitcast if the types are the same size and the destination 296 // vector type is legal. 297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 298 TLI.isTypeLegal(ValueVT)) 299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 300 301 // Handle cases such as i8 -> <1 x i1> 302 assert(ValueVT.getVectorNumElements() == 1 && 303 "Only trivial scalar-to-vector conversions should get here!"); 304 305 if (ValueVT.getVectorNumElements() == 1 && 306 ValueVT.getVectorElementType() != PartVT) { 307 bool Smaller = ValueVT.bitsLE(PartVT); 308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 309 DL, ValueVT.getScalarType(), Val); 310 } 311 312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 313} 314 315 316 317 318static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 319 SDValue Val, SDValue *Parts, unsigned NumParts, 320 EVT PartVT); 321 322/// getCopyToParts - Create a series of nodes that contain the specified value 323/// split into legal parts. If the parts contain more bits than Val, then, for 324/// integers, ExtendKind can be used to specify how to generate the extra bits. 325static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 326 SDValue Val, SDValue *Parts, unsigned NumParts, 327 EVT PartVT, 328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 329 EVT ValueVT = Val.getValueType(); 330 331 // Handle the vector case separately. 332 if (ValueVT.isVector()) 333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 334 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 336 unsigned PartBits = PartVT.getSizeInBits(); 337 unsigned OrigNumParts = NumParts; 338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 339 340 if (NumParts == 0) 341 return; 342 343 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 344 if (PartVT == ValueVT) { 345 assert(NumParts == 1 && "No-op copy with multiple parts!"); 346 Parts[0] = Val; 347 return; 348 } 349 350 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 351 // If the parts cover more bits than the value has, promote the value. 352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 353 assert(NumParts == 1 && "Do not know what to promote to!"); 354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 355 } else { 356 assert(PartVT.isInteger() && ValueVT.isInteger() && 357 "Unknown mismatch!"); 358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 360 } 361 } else if (PartBits == ValueVT.getSizeInBits()) { 362 // Different types of the same size. 363 assert(NumParts == 1 && PartVT != ValueVT); 364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 366 // If the parts cover less bits than value has, truncate the value. 367 assert(PartVT.isInteger() && ValueVT.isInteger() && 368 "Unknown mismatch!"); 369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 371 } 372 373 // The value may have changed - recompute ValueVT. 374 ValueVT = Val.getValueType(); 375 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 376 "Failed to tile the value with PartVT!"); 377 378 if (NumParts == 1) { 379 assert(PartVT == ValueVT && "Type conversion failed!"); 380 Parts[0] = Val; 381 return; 382 } 383 384 // Expand the value into multiple parts. 385 if (NumParts & (NumParts - 1)) { 386 // The number of parts is not a power of 2. Split off and copy the tail. 387 assert(PartVT.isInteger() && ValueVT.isInteger() && 388 "Do not know what to expand to!"); 389 unsigned RoundParts = 1 << Log2_32(NumParts); 390 unsigned RoundBits = RoundParts * PartBits; 391 unsigned OddParts = NumParts - RoundParts; 392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 393 DAG.getIntPtrConstant(RoundBits)); 394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 395 396 if (TLI.isBigEndian()) 397 // The odd parts were reversed by getCopyToParts - unreverse them. 398 std::reverse(Parts + RoundParts, Parts + NumParts); 399 400 NumParts = RoundParts; 401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 403 } 404 405 // The number of parts is a power of 2. Repeatedly bisect the value using 406 // EXTRACT_ELEMENT. 407 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 408 EVT::getIntegerVT(*DAG.getContext(), 409 ValueVT.getSizeInBits()), 410 Val); 411 412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 413 for (unsigned i = 0; i < NumParts; i += StepSize) { 414 unsigned ThisBits = StepSize * PartBits / 2; 415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 416 SDValue &Part0 = Parts[i]; 417 SDValue &Part1 = Parts[i+StepSize/2]; 418 419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 420 ThisVT, Part0, DAG.getIntPtrConstant(1)); 421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 422 ThisVT, Part0, DAG.getIntPtrConstant(0)); 423 424 if (ThisBits == PartBits && ThisVT != PartVT) { 425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 427 } 428 } 429 } 430 431 if (TLI.isBigEndian()) 432 std::reverse(Parts, Parts + OrigNumParts); 433} 434 435 436/// getCopyToPartsVector - Create a series of nodes that contain the specified 437/// value split into legal parts. 438static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 439 SDValue Val, SDValue *Parts, unsigned NumParts, 440 EVT PartVT) { 441 EVT ValueVT = Val.getValueType(); 442 assert(ValueVT.isVector() && "Not a vector"); 443 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 444 445 if (NumParts == 1) { 446 if (PartVT == ValueVT) { 447 // Nothing to do. 448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 449 // Bitconvert vector->vector case. 450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 451 } else if (PartVT.isVector() && 452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 454 EVT ElementVT = PartVT.getVectorElementType(); 455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 456 // undef elements. 457 SmallVector<SDValue, 16> Ops; 458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 460 ElementVT, Val, DAG.getIntPtrConstant(i))); 461 462 for (unsigned i = ValueVT.getVectorNumElements(), 463 e = PartVT.getVectorNumElements(); i != e; ++i) 464 Ops.push_back(DAG.getUNDEF(ElementVT)); 465 466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 467 468 // FIXME: Use CONCAT for 2x -> 4x. 469 470 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 472 } else if (PartVT.isVector() && 473 PartVT.getVectorElementType().bitsGE( 474 ValueVT.getVectorElementType()) && 475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 476 477 // Promoted vector extract 478 bool Smaller = PartVT.bitsLE(ValueVT); 479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 480 DL, PartVT, Val); 481 } else{ 482 // Vector -> scalar conversion. 483 assert(ValueVT.getVectorNumElements() == 1 && 484 "Only trivial vector-to-scalar conversions should get here!"); 485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 486 PartVT, Val, DAG.getIntPtrConstant(0)); 487 488 bool Smaller = ValueVT.bitsLE(PartVT); 489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 490 DL, PartVT, Val); 491 } 492 493 Parts[0] = Val; 494 return; 495 } 496 497 // Handle a multi-element vector. 498 EVT IntermediateVT, RegisterVT; 499 unsigned NumIntermediates; 500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 501 IntermediateVT, 502 NumIntermediates, RegisterVT); 503 unsigned NumElements = ValueVT.getVectorNumElements(); 504 505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 506 NumParts = NumRegs; // Silence a compiler warning. 507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 508 509 // Split the vector into intermediate operands. 510 SmallVector<SDValue, 8> Ops(NumIntermediates); 511 for (unsigned i = 0; i != NumIntermediates; ++i) { 512 if (IntermediateVT.isVector()) 513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 514 IntermediateVT, Val, 515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 516 else 517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 518 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 519 } 520 521 // Split the intermediate operands into legal parts. 522 if (NumParts == NumIntermediates) { 523 // If the register was not expanded, promote or copy the value, 524 // as appropriate. 525 for (unsigned i = 0; i != NumParts; ++i) 526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 527 } else if (NumParts > 0) { 528 // If the intermediate type was expanded, split each the value into 529 // legal parts. 530 assert(NumParts % NumIntermediates == 0 && 531 "Must expand into a divisible number of parts!"); 532 unsigned Factor = NumParts / NumIntermediates; 533 for (unsigned i = 0; i != NumIntermediates; ++i) 534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 535 } 536} 537 538 539 540 541namespace { 542 /// RegsForValue - This struct represents the registers (physical or virtual) 543 /// that a particular set of values is assigned, and the type information 544 /// about the value. The most common situation is to represent one value at a 545 /// time, but struct or array values are handled element-wise as multiple 546 /// values. The splitting of aggregates is performed recursively, so that we 547 /// never have aggregate-typed registers. The values at this point do not 548 /// necessarily have legal types, so each value may require one or more 549 /// registers of some legal type. 550 /// 551 struct RegsForValue { 552 /// ValueVTs - The value types of the values, which may not be legal, and 553 /// may need be promoted or synthesized from one or more registers. 554 /// 555 SmallVector<EVT, 4> ValueVTs; 556 557 /// RegVTs - The value types of the registers. This is the same size as 558 /// ValueVTs and it records, for each value, what the type of the assigned 559 /// register or registers are. (Individual values are never synthesized 560 /// from more than one type of register.) 561 /// 562 /// With virtual registers, the contents of RegVTs is redundant with TLI's 563 /// getRegisterType member function, however when with physical registers 564 /// it is necessary to have a separate record of the types. 565 /// 566 SmallVector<EVT, 4> RegVTs; 567 568 /// Regs - This list holds the registers assigned to the values. 569 /// Each legal or promoted value requires one register, and each 570 /// expanded value requires multiple registers. 571 /// 572 SmallVector<unsigned, 4> Regs; 573 574 RegsForValue() {} 575 576 RegsForValue(const SmallVector<unsigned, 4> ®s, 577 EVT regvt, EVT valuevt) 578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 579 580 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 581 unsigned Reg, const Type *Ty) { 582 ComputeValueVTs(tli, Ty, ValueVTs); 583 584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 585 EVT ValueVT = ValueVTs[Value]; 586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 588 for (unsigned i = 0; i != NumRegs; ++i) 589 Regs.push_back(Reg + i); 590 RegVTs.push_back(RegisterVT); 591 Reg += NumRegs; 592 } 593 } 594 595 /// areValueTypesLegal - Return true if types of all the values are legal. 596 bool areValueTypesLegal(const TargetLowering &TLI) { 597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 598 EVT RegisterVT = RegVTs[Value]; 599 if (!TLI.isTypeLegal(RegisterVT)) 600 return false; 601 } 602 return true; 603 } 604 605 /// append - Add the specified values to this one. 606 void append(const RegsForValue &RHS) { 607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 609 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 610 } 611 612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 613 /// this value and returns the result as a ValueVTs value. This uses 614 /// Chain/Flag as the input and updates them for the output Chain/Flag. 615 /// If the Flag pointer is NULL, no flag is used. 616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 617 DebugLoc dl, 618 SDValue &Chain, SDValue *Flag) const; 619 620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 621 /// specified value into the registers specified by this object. This uses 622 /// Chain/Flag as the input and updates them for the output Chain/Flag. 623 /// If the Flag pointer is NULL, no flag is used. 624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 625 SDValue &Chain, SDValue *Flag) const; 626 627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 628 /// operand list. This adds the code marker, matching input operand index 629 /// (if applicable), and includes the number of values added into it. 630 void AddInlineAsmOperands(unsigned Kind, 631 bool HasMatching, unsigned MatchingIdx, 632 SelectionDAG &DAG, 633 std::vector<SDValue> &Ops) const; 634 }; 635} 636 637/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 638/// this value and returns the result as a ValueVT value. This uses 639/// Chain/Flag as the input and updates them for the output Chain/Flag. 640/// If the Flag pointer is NULL, no flag is used. 641SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 642 FunctionLoweringInfo &FuncInfo, 643 DebugLoc dl, 644 SDValue &Chain, SDValue *Flag) const { 645 // A Value with type {} or [0 x %t] needs no registers. 646 if (ValueVTs.empty()) 647 return SDValue(); 648 649 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 650 651 // Assemble the legal parts into the final values. 652 SmallVector<SDValue, 4> Values(ValueVTs.size()); 653 SmallVector<SDValue, 8> Parts; 654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 655 // Copy the legal parts from the registers. 656 EVT ValueVT = ValueVTs[Value]; 657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 658 EVT RegisterVT = RegVTs[Value]; 659 660 Parts.resize(NumRegs); 661 for (unsigned i = 0; i != NumRegs; ++i) { 662 SDValue P; 663 if (Flag == 0) { 664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 665 } else { 666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 667 *Flag = P.getValue(2); 668 } 669 670 Chain = P.getValue(1); 671 Parts[i] = P; 672 673 // If the source register was virtual and if we know something about it, 674 // add an assert node. 675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 676 !RegisterVT.isInteger() || RegisterVT.isVector()) 677 continue; 678 679 const FunctionLoweringInfo::LiveOutInfo *LOI = 680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 681 if (!LOI) 682 continue; 683 684 unsigned RegSize = RegisterVT.getSizeInBits(); 685 unsigned NumSignBits = LOI->NumSignBits; 686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 687 688 // FIXME: We capture more information than the dag can represent. For 689 // now, just use the tightest assertzext/assertsext possible. 690 bool isSExt = true; 691 EVT FromVT(MVT::Other); 692 if (NumSignBits == RegSize) 693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 694 else if (NumZeroBits >= RegSize-1) 695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 696 else if (NumSignBits > RegSize-8) 697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 698 else if (NumZeroBits >= RegSize-8) 699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 700 else if (NumSignBits > RegSize-16) 701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 702 else if (NumZeroBits >= RegSize-16) 703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 704 else if (NumSignBits > RegSize-32) 705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 706 else if (NumZeroBits >= RegSize-32) 707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 708 else 709 continue; 710 711 // Add an assertion node. 712 assert(FromVT != MVT::Other); 713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 714 RegisterVT, P, DAG.getValueType(FromVT)); 715 } 716 717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 718 NumRegs, RegisterVT, ValueVT); 719 Part += NumRegs; 720 Parts.clear(); 721 } 722 723 return DAG.getNode(ISD::MERGE_VALUES, dl, 724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 725 &Values[0], ValueVTs.size()); 726} 727 728/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 729/// specified value into the registers specified by this object. This uses 730/// Chain/Flag as the input and updates them for the output Chain/Flag. 731/// If the Flag pointer is NULL, no flag is used. 732void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 733 SDValue &Chain, SDValue *Flag) const { 734 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 735 736 // Get the list of the values's legal parts. 737 unsigned NumRegs = Regs.size(); 738 SmallVector<SDValue, 8> Parts(NumRegs); 739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 740 EVT ValueVT = ValueVTs[Value]; 741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 742 EVT RegisterVT = RegVTs[Value]; 743 744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 745 &Parts[Part], NumParts, RegisterVT); 746 Part += NumParts; 747 } 748 749 // Copy the parts into the registers. 750 SmallVector<SDValue, 8> Chains(NumRegs); 751 for (unsigned i = 0; i != NumRegs; ++i) { 752 SDValue Part; 753 if (Flag == 0) { 754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 755 } else { 756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 757 *Flag = Part.getValue(1); 758 } 759 760 Chains[i] = Part.getValue(0); 761 } 762 763 if (NumRegs == 1 || Flag) 764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 765 // flagged to it. That is the CopyToReg nodes and the user are considered 766 // a single scheduling unit. If we create a TokenFactor and return it as 767 // chain, then the TokenFactor is both a predecessor (operand) of the 768 // user as well as a successor (the TF operands are flagged to the user). 769 // c1, f1 = CopyToReg 770 // c2, f2 = CopyToReg 771 // c3 = TokenFactor c1, c2 772 // ... 773 // = op c3, ..., f2 774 Chain = Chains[NumRegs-1]; 775 else 776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 777} 778 779/// AddInlineAsmOperands - Add this value to the specified inlineasm node 780/// operand list. This adds the code marker and includes the number of 781/// values added into it. 782void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 783 unsigned MatchingIdx, 784 SelectionDAG &DAG, 785 std::vector<SDValue> &Ops) const { 786 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 787 788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 789 if (HasMatching) 790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 791 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 792 Ops.push_back(Res); 793 794 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 795 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 796 EVT RegisterVT = RegVTs[Value]; 797 for (unsigned i = 0; i != NumRegs; ++i) { 798 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 799 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 800 } 801 } 802} 803 804void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 805 AA = &aa; 806 GFI = gfi; 807 TD = DAG.getTarget().getTargetData(); 808} 809 810/// clear - Clear out the current SelectionDAG and the associated 811/// state and prepare this SelectionDAGBuilder object to be used 812/// for a new block. This doesn't clear out information about 813/// additional blocks that are needed to complete switch lowering 814/// or PHI node updating; that information is cleared out as it is 815/// consumed. 816void SelectionDAGBuilder::clear() { 817 NodeMap.clear(); 818 UnusedArgNodeMap.clear(); 819 PendingLoads.clear(); 820 PendingExports.clear(); 821 CurDebugLoc = DebugLoc(); 822 HasTailCall = false; 823} 824 825/// clearDanglingDebugInfo - Clear the dangling debug information 826/// map. This function is seperated from the clear so that debug 827/// information that is dangling in a basic block can be properly 828/// resolved in a different basic block. This allows the 829/// SelectionDAG to resolve dangling debug information attached 830/// to PHI nodes. 831void SelectionDAGBuilder::clearDanglingDebugInfo() { 832 DanglingDebugInfoMap.clear(); 833} 834 835/// getRoot - Return the current virtual root of the Selection DAG, 836/// flushing any PendingLoad items. This must be done before emitting 837/// a store or any other node that may need to be ordered after any 838/// prior load instructions. 839/// 840SDValue SelectionDAGBuilder::getRoot() { 841 if (PendingLoads.empty()) 842 return DAG.getRoot(); 843 844 if (PendingLoads.size() == 1) { 845 SDValue Root = PendingLoads[0]; 846 DAG.setRoot(Root); 847 PendingLoads.clear(); 848 return Root; 849 } 850 851 // Otherwise, we have to make a token factor node. 852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 853 &PendingLoads[0], PendingLoads.size()); 854 PendingLoads.clear(); 855 DAG.setRoot(Root); 856 return Root; 857} 858 859/// getControlRoot - Similar to getRoot, but instead of flushing all the 860/// PendingLoad items, flush all the PendingExports items. It is necessary 861/// to do this before emitting a terminator instruction. 862/// 863SDValue SelectionDAGBuilder::getControlRoot() { 864 SDValue Root = DAG.getRoot(); 865 866 if (PendingExports.empty()) 867 return Root; 868 869 // Turn all of the CopyToReg chains into one factored node. 870 if (Root.getOpcode() != ISD::EntryToken) { 871 unsigned i = 0, e = PendingExports.size(); 872 for (; i != e; ++i) { 873 assert(PendingExports[i].getNode()->getNumOperands() > 1); 874 if (PendingExports[i].getNode()->getOperand(0) == Root) 875 break; // Don't add the root if we already indirectly depend on it. 876 } 877 878 if (i == e) 879 PendingExports.push_back(Root); 880 } 881 882 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 883 &PendingExports[0], 884 PendingExports.size()); 885 PendingExports.clear(); 886 DAG.setRoot(Root); 887 return Root; 888} 889 890void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 891 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 892 DAG.AssignOrdering(Node, SDNodeOrder); 893 894 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 895 AssignOrderingToNode(Node->getOperand(I).getNode()); 896} 897 898void SelectionDAGBuilder::visit(const Instruction &I) { 899 // Set up outgoing PHI node register values before emitting the terminator. 900 if (isa<TerminatorInst>(&I)) 901 HandlePHINodesInSuccessorBlocks(I.getParent()); 902 903 CurDebugLoc = I.getDebugLoc(); 904 905 visit(I.getOpcode(), I); 906 907 if (!isa<TerminatorInst>(&I) && !HasTailCall) 908 CopyToExportRegsIfNeeded(&I); 909 910 CurDebugLoc = DebugLoc(); 911} 912 913void SelectionDAGBuilder::visitPHI(const PHINode &) { 914 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 915} 916 917void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 918 // Note: this doesn't use InstVisitor, because it has to work with 919 // ConstantExpr's in addition to instructions. 920 switch (Opcode) { 921 default: llvm_unreachable("Unknown instruction type encountered!"); 922 // Build the switch statement using the Instruction.def file. 923#define HANDLE_INST(NUM, OPCODE, CLASS) \ 924 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 925#include "llvm/Instruction.def" 926 } 927 928 // Assign the ordering to the freshly created DAG nodes. 929 if (NodeMap.count(&I)) { 930 ++SDNodeOrder; 931 AssignOrderingToNode(getValue(&I).getNode()); 932 } 933} 934 935// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 936// generate the debug data structures now that we've seen its definition. 937void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 938 SDValue Val) { 939 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 940 if (DDI.getDI()) { 941 const DbgValueInst *DI = DDI.getDI(); 942 DebugLoc dl = DDI.getdl(); 943 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 944 MDNode *Variable = DI->getVariable(); 945 uint64_t Offset = DI->getOffset(); 946 SDDbgValue *SDV; 947 if (Val.getNode()) { 948 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 949 SDV = DAG.getDbgValue(Variable, Val.getNode(), 950 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 951 DAG.AddDbgValue(SDV, Val.getNode(), false); 952 } 953 } else 954 DEBUG(dbgs() << "Dropping debug info for " << DI); 955 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 956 } 957} 958 959// getValue - Return an SDValue for the given Value. 960SDValue SelectionDAGBuilder::getValue(const Value *V) { 961 // If we already have an SDValue for this value, use it. It's important 962 // to do this first, so that we don't create a CopyFromReg if we already 963 // have a regular SDValue. 964 SDValue &N = NodeMap[V]; 965 if (N.getNode()) return N; 966 967 // If there's a virtual register allocated and initialized for this 968 // value, use it. 969 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 970 if (It != FuncInfo.ValueMap.end()) { 971 unsigned InReg = It->second; 972 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 973 SDValue Chain = DAG.getEntryNode(); 974 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 975 resolveDanglingDebugInfo(V, N); 976 return N; 977 } 978 979 // Otherwise create a new SDValue and remember it. 980 SDValue Val = getValueImpl(V); 981 NodeMap[V] = Val; 982 resolveDanglingDebugInfo(V, Val); 983 return Val; 984} 985 986/// getNonRegisterValue - Return an SDValue for the given Value, but 987/// don't look in FuncInfo.ValueMap for a virtual register. 988SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 989 // If we already have an SDValue for this value, use it. 990 SDValue &N = NodeMap[V]; 991 if (N.getNode()) return N; 992 993 // Otherwise create a new SDValue and remember it. 994 SDValue Val = getValueImpl(V); 995 NodeMap[V] = Val; 996 resolveDanglingDebugInfo(V, Val); 997 return Val; 998} 999 1000/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1001/// Create an SDValue for the given value. 1002SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1003 if (const Constant *C = dyn_cast<Constant>(V)) { 1004 EVT VT = TLI.getValueType(V->getType(), true); 1005 1006 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1007 return DAG.getConstant(*CI, VT); 1008 1009 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1010 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1011 1012 if (isa<ConstantPointerNull>(C)) 1013 return DAG.getConstant(0, TLI.getPointerTy()); 1014 1015 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1016 return DAG.getConstantFP(*CFP, VT); 1017 1018 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1019 return DAG.getUNDEF(VT); 1020 1021 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1022 visit(CE->getOpcode(), *CE); 1023 SDValue N1 = NodeMap[V]; 1024 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1025 return N1; 1026 } 1027 1028 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1029 SmallVector<SDValue, 4> Constants; 1030 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1031 OI != OE; ++OI) { 1032 SDNode *Val = getValue(*OI).getNode(); 1033 // If the operand is an empty aggregate, there are no values. 1034 if (!Val) continue; 1035 // Add each leaf value from the operand to the Constants list 1036 // to form a flattened list of all the values. 1037 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1038 Constants.push_back(SDValue(Val, i)); 1039 } 1040 1041 return DAG.getMergeValues(&Constants[0], Constants.size(), 1042 getCurDebugLoc()); 1043 } 1044 1045 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1046 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1047 "Unknown struct or array constant!"); 1048 1049 SmallVector<EVT, 4> ValueVTs; 1050 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1051 unsigned NumElts = ValueVTs.size(); 1052 if (NumElts == 0) 1053 return SDValue(); // empty struct 1054 SmallVector<SDValue, 4> Constants(NumElts); 1055 for (unsigned i = 0; i != NumElts; ++i) { 1056 EVT EltVT = ValueVTs[i]; 1057 if (isa<UndefValue>(C)) 1058 Constants[i] = DAG.getUNDEF(EltVT); 1059 else if (EltVT.isFloatingPoint()) 1060 Constants[i] = DAG.getConstantFP(0, EltVT); 1061 else 1062 Constants[i] = DAG.getConstant(0, EltVT); 1063 } 1064 1065 return DAG.getMergeValues(&Constants[0], NumElts, 1066 getCurDebugLoc()); 1067 } 1068 1069 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1070 return DAG.getBlockAddress(BA, VT); 1071 1072 const VectorType *VecTy = cast<VectorType>(V->getType()); 1073 unsigned NumElements = VecTy->getNumElements(); 1074 1075 // Now that we know the number and type of the elements, get that number of 1076 // elements into the Ops array based on what kind of constant it is. 1077 SmallVector<SDValue, 16> Ops; 1078 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1079 for (unsigned i = 0; i != NumElements; ++i) 1080 Ops.push_back(getValue(CP->getOperand(i))); 1081 } else { 1082 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1083 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1084 1085 SDValue Op; 1086 if (EltVT.isFloatingPoint()) 1087 Op = DAG.getConstantFP(0, EltVT); 1088 else 1089 Op = DAG.getConstant(0, EltVT); 1090 Ops.assign(NumElements, Op); 1091 } 1092 1093 // Create a BUILD_VECTOR node. 1094 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1095 VT, &Ops[0], Ops.size()); 1096 } 1097 1098 // If this is a static alloca, generate it as the frameindex instead of 1099 // computation. 1100 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1101 DenseMap<const AllocaInst*, int>::iterator SI = 1102 FuncInfo.StaticAllocaMap.find(AI); 1103 if (SI != FuncInfo.StaticAllocaMap.end()) 1104 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1105 } 1106 1107 // If this is an instruction which fast-isel has deferred, select it now. 1108 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1109 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1110 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1111 SDValue Chain = DAG.getEntryNode(); 1112 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1113 } 1114 1115 llvm_unreachable("Can't get register for value!"); 1116 return SDValue(); 1117} 1118 1119void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1120 SDValue Chain = getControlRoot(); 1121 SmallVector<ISD::OutputArg, 8> Outs; 1122 SmallVector<SDValue, 8> OutVals; 1123 1124 if (!FuncInfo.CanLowerReturn) { 1125 unsigned DemoteReg = FuncInfo.DemoteRegister; 1126 const Function *F = I.getParent()->getParent(); 1127 1128 // Emit a store of the return value through the virtual register. 1129 // Leave Outs empty so that LowerReturn won't try to load return 1130 // registers the usual way. 1131 SmallVector<EVT, 1> PtrValueVTs; 1132 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1133 PtrValueVTs); 1134 1135 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1136 SDValue RetOp = getValue(I.getOperand(0)); 1137 1138 SmallVector<EVT, 4> ValueVTs; 1139 SmallVector<uint64_t, 4> Offsets; 1140 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1141 unsigned NumValues = ValueVTs.size(); 1142 1143 SmallVector<SDValue, 4> Chains(NumValues); 1144 for (unsigned i = 0; i != NumValues; ++i) { 1145 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1146 RetPtr.getValueType(), RetPtr, 1147 DAG.getIntPtrConstant(Offsets[i])); 1148 Chains[i] = 1149 DAG.getStore(Chain, getCurDebugLoc(), 1150 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1151 // FIXME: better loc info would be nice. 1152 Add, MachinePointerInfo(), false, false, 0); 1153 } 1154 1155 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1156 MVT::Other, &Chains[0], NumValues); 1157 } else if (I.getNumOperands() != 0) { 1158 SmallVector<EVT, 4> ValueVTs; 1159 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1160 unsigned NumValues = ValueVTs.size(); 1161 if (NumValues) { 1162 SDValue RetOp = getValue(I.getOperand(0)); 1163 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1164 EVT VT = ValueVTs[j]; 1165 1166 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1167 1168 const Function *F = I.getParent()->getParent(); 1169 if (F->paramHasAttr(0, Attribute::SExt)) 1170 ExtendKind = ISD::SIGN_EXTEND; 1171 else if (F->paramHasAttr(0, Attribute::ZExt)) 1172 ExtendKind = ISD::ZERO_EXTEND; 1173 1174 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1175 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1176 1177 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1178 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1179 SmallVector<SDValue, 4> Parts(NumParts); 1180 getCopyToParts(DAG, getCurDebugLoc(), 1181 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1182 &Parts[0], NumParts, PartVT, ExtendKind); 1183 1184 // 'inreg' on function refers to return value 1185 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1186 if (F->paramHasAttr(0, Attribute::InReg)) 1187 Flags.setInReg(); 1188 1189 // Propagate extension type if any 1190 if (ExtendKind == ISD::SIGN_EXTEND) 1191 Flags.setSExt(); 1192 else if (ExtendKind == ISD::ZERO_EXTEND) 1193 Flags.setZExt(); 1194 1195 for (unsigned i = 0; i < NumParts; ++i) { 1196 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1197 /*isfixed=*/true)); 1198 OutVals.push_back(Parts[i]); 1199 } 1200 } 1201 } 1202 } 1203 1204 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1205 CallingConv::ID CallConv = 1206 DAG.getMachineFunction().getFunction()->getCallingConv(); 1207 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1208 Outs, OutVals, getCurDebugLoc(), DAG); 1209 1210 // Verify that the target's LowerReturn behaved as expected. 1211 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1212 "LowerReturn didn't return a valid chain!"); 1213 1214 // Update the DAG with the new chain value resulting from return lowering. 1215 DAG.setRoot(Chain); 1216} 1217 1218/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1219/// created for it, emit nodes to copy the value into the virtual 1220/// registers. 1221void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1222 // Skip empty types 1223 if (V->getType()->isEmptyTy()) 1224 return; 1225 1226 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1227 if (VMI != FuncInfo.ValueMap.end()) { 1228 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1229 CopyValueToVirtualRegister(V, VMI->second); 1230 } 1231} 1232 1233/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1234/// the current basic block, add it to ValueMap now so that we'll get a 1235/// CopyTo/FromReg. 1236void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1237 // No need to export constants. 1238 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1239 1240 // Already exported? 1241 if (FuncInfo.isExportedInst(V)) return; 1242 1243 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1244 CopyValueToVirtualRegister(V, Reg); 1245} 1246 1247bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1248 const BasicBlock *FromBB) { 1249 // The operands of the setcc have to be in this block. We don't know 1250 // how to export them from some other block. 1251 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1252 // Can export from current BB. 1253 if (VI->getParent() == FromBB) 1254 return true; 1255 1256 // Is already exported, noop. 1257 return FuncInfo.isExportedInst(V); 1258 } 1259 1260 // If this is an argument, we can export it if the BB is the entry block or 1261 // if it is already exported. 1262 if (isa<Argument>(V)) { 1263 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1264 return true; 1265 1266 // Otherwise, can only export this if it is already exported. 1267 return FuncInfo.isExportedInst(V); 1268 } 1269 1270 // Otherwise, constants can always be exported. 1271 return true; 1272} 1273 1274/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1275uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src, 1276 MachineBasicBlock *Dst) { 1277 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1278 if (!BPI) 1279 return 0; 1280 BasicBlock *SrcBB = const_cast<BasicBlock*>(Src->getBasicBlock()); 1281 BasicBlock *DstBB = const_cast<BasicBlock*>(Dst->getBasicBlock()); 1282 return BPI->getEdgeWeight(SrcBB, DstBB); 1283} 1284 1285void SelectionDAGBuilder::addSuccessorWithWeight(MachineBasicBlock *Src, 1286 MachineBasicBlock *Dst) { 1287 uint32_t weight = getEdgeWeight(Src, Dst); 1288 Src->addSuccessor(Dst, weight); 1289} 1290 1291 1292static bool InBlock(const Value *V, const BasicBlock *BB) { 1293 if (const Instruction *I = dyn_cast<Instruction>(V)) 1294 return I->getParent() == BB; 1295 return true; 1296} 1297 1298/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1299/// This function emits a branch and is used at the leaves of an OR or an 1300/// AND operator tree. 1301/// 1302void 1303SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1304 MachineBasicBlock *TBB, 1305 MachineBasicBlock *FBB, 1306 MachineBasicBlock *CurBB, 1307 MachineBasicBlock *SwitchBB) { 1308 const BasicBlock *BB = CurBB->getBasicBlock(); 1309 1310 // If the leaf of the tree is a comparison, merge the condition into 1311 // the caseblock. 1312 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1313 // The operands of the cmp have to be in this block. We don't know 1314 // how to export them from some other block. If this is the first block 1315 // of the sequence, no exporting is needed. 1316 if (CurBB == SwitchBB || 1317 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1318 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1319 ISD::CondCode Condition; 1320 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1321 Condition = getICmpCondCode(IC->getPredicate()); 1322 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1323 Condition = getFCmpCondCode(FC->getPredicate()); 1324 } else { 1325 Condition = ISD::SETEQ; // silence warning. 1326 llvm_unreachable("Unknown compare instruction"); 1327 } 1328 1329 CaseBlock CB(Condition, BOp->getOperand(0), 1330 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1331 SwitchCases.push_back(CB); 1332 return; 1333 } 1334 } 1335 1336 // Create a CaseBlock record representing this branch. 1337 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1338 NULL, TBB, FBB, CurBB); 1339 SwitchCases.push_back(CB); 1340} 1341 1342/// FindMergedConditions - If Cond is an expression like 1343void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1344 MachineBasicBlock *TBB, 1345 MachineBasicBlock *FBB, 1346 MachineBasicBlock *CurBB, 1347 MachineBasicBlock *SwitchBB, 1348 unsigned Opc) { 1349 // If this node is not part of the or/and tree, emit it as a branch. 1350 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1351 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1352 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1353 BOp->getParent() != CurBB->getBasicBlock() || 1354 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1355 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1356 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1357 return; 1358 } 1359 1360 // Create TmpBB after CurBB. 1361 MachineFunction::iterator BBI = CurBB; 1362 MachineFunction &MF = DAG.getMachineFunction(); 1363 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1364 CurBB->getParent()->insert(++BBI, TmpBB); 1365 1366 if (Opc == Instruction::Or) { 1367 // Codegen X | Y as: 1368 // jmp_if_X TBB 1369 // jmp TmpBB 1370 // TmpBB: 1371 // jmp_if_Y TBB 1372 // jmp FBB 1373 // 1374 1375 // Emit the LHS condition. 1376 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1377 1378 // Emit the RHS condition into TmpBB. 1379 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1380 } else { 1381 assert(Opc == Instruction::And && "Unknown merge op!"); 1382 // Codegen X & Y as: 1383 // jmp_if_X TmpBB 1384 // jmp FBB 1385 // TmpBB: 1386 // jmp_if_Y TBB 1387 // jmp FBB 1388 // 1389 // This requires creation of TmpBB after CurBB. 1390 1391 // Emit the LHS condition. 1392 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1393 1394 // Emit the RHS condition into TmpBB. 1395 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1396 } 1397} 1398 1399/// If the set of cases should be emitted as a series of branches, return true. 1400/// If we should emit this as a bunch of and/or'd together conditions, return 1401/// false. 1402bool 1403SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1404 if (Cases.size() != 2) return true; 1405 1406 // If this is two comparisons of the same values or'd or and'd together, they 1407 // will get folded into a single comparison, so don't emit two blocks. 1408 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1409 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1410 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1411 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1412 return false; 1413 } 1414 1415 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1416 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1417 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1418 Cases[0].CC == Cases[1].CC && 1419 isa<Constant>(Cases[0].CmpRHS) && 1420 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1421 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1422 return false; 1423 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1424 return false; 1425 } 1426 1427 return true; 1428} 1429 1430void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1431 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1432 1433 // Update machine-CFG edges. 1434 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1435 1436 // Figure out which block is immediately after the current one. 1437 MachineBasicBlock *NextBlock = 0; 1438 MachineFunction::iterator BBI = BrMBB; 1439 if (++BBI != FuncInfo.MF->end()) 1440 NextBlock = BBI; 1441 1442 if (I.isUnconditional()) { 1443 // Update machine-CFG edges. 1444 BrMBB->addSuccessor(Succ0MBB); 1445 1446 // If this is not a fall-through branch, emit the branch. 1447 if (Succ0MBB != NextBlock) 1448 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1449 MVT::Other, getControlRoot(), 1450 DAG.getBasicBlock(Succ0MBB))); 1451 1452 return; 1453 } 1454 1455 // If this condition is one of the special cases we handle, do special stuff 1456 // now. 1457 const Value *CondVal = I.getCondition(); 1458 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1459 1460 // If this is a series of conditions that are or'd or and'd together, emit 1461 // this as a sequence of branches instead of setcc's with and/or operations. 1462 // As long as jumps are not expensive, this should improve performance. 1463 // For example, instead of something like: 1464 // cmp A, B 1465 // C = seteq 1466 // cmp D, E 1467 // F = setle 1468 // or C, F 1469 // jnz foo 1470 // Emit: 1471 // cmp A, B 1472 // je foo 1473 // cmp D, E 1474 // jle foo 1475 // 1476 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1477 if (!TLI.isJumpExpensive() && 1478 BOp->hasOneUse() && 1479 (BOp->getOpcode() == Instruction::And || 1480 BOp->getOpcode() == Instruction::Or)) { 1481 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1482 BOp->getOpcode()); 1483 // If the compares in later blocks need to use values not currently 1484 // exported from this block, export them now. This block should always 1485 // be the first entry. 1486 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1487 1488 // Allow some cases to be rejected. 1489 if (ShouldEmitAsBranches(SwitchCases)) { 1490 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1491 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1492 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1493 } 1494 1495 // Emit the branch for this block. 1496 visitSwitchCase(SwitchCases[0], BrMBB); 1497 SwitchCases.erase(SwitchCases.begin()); 1498 return; 1499 } 1500 1501 // Okay, we decided not to do this, remove any inserted MBB's and clear 1502 // SwitchCases. 1503 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1504 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1505 1506 SwitchCases.clear(); 1507 } 1508 } 1509 1510 // Create a CaseBlock record representing this branch. 1511 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1512 NULL, Succ0MBB, Succ1MBB, BrMBB); 1513 1514 // Use visitSwitchCase to actually insert the fast branch sequence for this 1515 // cond branch. 1516 visitSwitchCase(CB, BrMBB); 1517} 1518 1519/// visitSwitchCase - Emits the necessary code to represent a single node in 1520/// the binary search tree resulting from lowering a switch instruction. 1521void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1522 MachineBasicBlock *SwitchBB) { 1523 SDValue Cond; 1524 SDValue CondLHS = getValue(CB.CmpLHS); 1525 DebugLoc dl = getCurDebugLoc(); 1526 1527 // Build the setcc now. 1528 if (CB.CmpMHS == NULL) { 1529 // Fold "(X == true)" to X and "(X == false)" to !X to 1530 // handle common cases produced by branch lowering. 1531 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1532 CB.CC == ISD::SETEQ) 1533 Cond = CondLHS; 1534 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1535 CB.CC == ISD::SETEQ) { 1536 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1537 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1538 } else 1539 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1540 } else { 1541 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1542 1543 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1544 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1545 1546 SDValue CmpOp = getValue(CB.CmpMHS); 1547 EVT VT = CmpOp.getValueType(); 1548 1549 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1550 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1551 ISD::SETLE); 1552 } else { 1553 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1554 VT, CmpOp, DAG.getConstant(Low, VT)); 1555 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1556 DAG.getConstant(High-Low, VT), ISD::SETULE); 1557 } 1558 } 1559 1560 // Update successor info 1561 addSuccessorWithWeight(SwitchBB, CB.TrueBB); 1562 addSuccessorWithWeight(SwitchBB, CB.FalseBB); 1563 1564 // Set NextBlock to be the MBB immediately after the current one, if any. 1565 // This is used to avoid emitting unnecessary branches to the next block. 1566 MachineBasicBlock *NextBlock = 0; 1567 MachineFunction::iterator BBI = SwitchBB; 1568 if (++BBI != FuncInfo.MF->end()) 1569 NextBlock = BBI; 1570 1571 // If the lhs block is the next block, invert the condition so that we can 1572 // fall through to the lhs instead of the rhs block. 1573 if (CB.TrueBB == NextBlock) { 1574 std::swap(CB.TrueBB, CB.FalseBB); 1575 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1576 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1577 } 1578 1579 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1580 MVT::Other, getControlRoot(), Cond, 1581 DAG.getBasicBlock(CB.TrueBB)); 1582 1583 // Insert the false branch. Do this even if it's a fall through branch, 1584 // this makes it easier to do DAG optimizations which require inverting 1585 // the branch condition. 1586 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1587 DAG.getBasicBlock(CB.FalseBB)); 1588 1589 DAG.setRoot(BrCond); 1590} 1591 1592/// visitJumpTable - Emit JumpTable node in the current MBB 1593void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1594 // Emit the code for the jump table 1595 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1596 EVT PTy = TLI.getPointerTy(); 1597 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1598 JT.Reg, PTy); 1599 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1600 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1601 MVT::Other, Index.getValue(1), 1602 Table, Index); 1603 DAG.setRoot(BrJumpTable); 1604} 1605 1606/// visitJumpTableHeader - This function emits necessary code to produce index 1607/// in the JumpTable from switch case. 1608void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1609 JumpTableHeader &JTH, 1610 MachineBasicBlock *SwitchBB) { 1611 // Subtract the lowest switch case value from the value being switched on and 1612 // conditional branch to default mbb if the result is greater than the 1613 // difference between smallest and largest cases. 1614 SDValue SwitchOp = getValue(JTH.SValue); 1615 EVT VT = SwitchOp.getValueType(); 1616 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1617 DAG.getConstant(JTH.First, VT)); 1618 1619 // The SDNode we just created, which holds the value being switched on minus 1620 // the smallest case value, needs to be copied to a virtual register so it 1621 // can be used as an index into the jump table in a subsequent basic block. 1622 // This value may be smaller or larger than the target's pointer type, and 1623 // therefore require extension or truncating. 1624 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1625 1626 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1627 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1628 JumpTableReg, SwitchOp); 1629 JT.Reg = JumpTableReg; 1630 1631 // Emit the range check for the jump table, and branch to the default block 1632 // for the switch statement if the value being switched on exceeds the largest 1633 // case in the switch. 1634 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1635 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1636 DAG.getConstant(JTH.Last-JTH.First,VT), 1637 ISD::SETUGT); 1638 1639 // Set NextBlock to be the MBB immediately after the current one, if any. 1640 // This is used to avoid emitting unnecessary branches to the next block. 1641 MachineBasicBlock *NextBlock = 0; 1642 MachineFunction::iterator BBI = SwitchBB; 1643 1644 if (++BBI != FuncInfo.MF->end()) 1645 NextBlock = BBI; 1646 1647 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1648 MVT::Other, CopyTo, CMP, 1649 DAG.getBasicBlock(JT.Default)); 1650 1651 if (JT.MBB != NextBlock) 1652 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1653 DAG.getBasicBlock(JT.MBB)); 1654 1655 DAG.setRoot(BrCond); 1656} 1657 1658/// visitBitTestHeader - This function emits necessary code to produce value 1659/// suitable for "bit tests" 1660void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1661 MachineBasicBlock *SwitchBB) { 1662 // Subtract the minimum value 1663 SDValue SwitchOp = getValue(B.SValue); 1664 EVT VT = SwitchOp.getValueType(); 1665 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1666 DAG.getConstant(B.First, VT)); 1667 1668 // Check range 1669 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1670 TLI.getSetCCResultType(Sub.getValueType()), 1671 Sub, DAG.getConstant(B.Range, VT), 1672 ISD::SETUGT); 1673 1674 // Determine the type of the test operands. 1675 bool UsePtrType = false; 1676 if (!TLI.isTypeLegal(VT)) 1677 UsePtrType = true; 1678 else { 1679 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1680 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) { 1681 // Switch table case range are encoded into series of masks. 1682 // Just use pointer type, it's guaranteed to fit. 1683 UsePtrType = true; 1684 break; 1685 } 1686 } 1687 if (UsePtrType) { 1688 VT = TLI.getPointerTy(); 1689 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1690 } 1691 1692 B.RegVT = VT; 1693 B.Reg = FuncInfo.CreateReg(VT); 1694 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1695 B.Reg, Sub); 1696 1697 // Set NextBlock to be the MBB immediately after the current one, if any. 1698 // This is used to avoid emitting unnecessary branches to the next block. 1699 MachineBasicBlock *NextBlock = 0; 1700 MachineFunction::iterator BBI = SwitchBB; 1701 if (++BBI != FuncInfo.MF->end()) 1702 NextBlock = BBI; 1703 1704 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1705 1706 addSuccessorWithWeight(SwitchBB, B.Default); 1707 addSuccessorWithWeight(SwitchBB, MBB); 1708 1709 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1710 MVT::Other, CopyTo, RangeCmp, 1711 DAG.getBasicBlock(B.Default)); 1712 1713 if (MBB != NextBlock) 1714 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1715 DAG.getBasicBlock(MBB)); 1716 1717 DAG.setRoot(BrRange); 1718} 1719 1720/// visitBitTestCase - this function produces one "bit test" 1721void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1722 MachineBasicBlock* NextMBB, 1723 unsigned Reg, 1724 BitTestCase &B, 1725 MachineBasicBlock *SwitchBB) { 1726 EVT VT = BB.RegVT; 1727 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1728 Reg, VT); 1729 SDValue Cmp; 1730 if (CountPopulation_64(B.Mask) == 1) { 1731 // Testing for a single bit; just compare the shift count with what it 1732 // would need to be to shift a 1 bit in that position. 1733 Cmp = DAG.getSetCC(getCurDebugLoc(), 1734 TLI.getSetCCResultType(VT), 1735 ShiftOp, 1736 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1737 ISD::SETEQ); 1738 } else { 1739 // Make desired shift 1740 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1741 DAG.getConstant(1, VT), ShiftOp); 1742 1743 // Emit bit tests and jumps 1744 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1745 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1746 Cmp = DAG.getSetCC(getCurDebugLoc(), 1747 TLI.getSetCCResultType(VT), 1748 AndOp, DAG.getConstant(0, VT), 1749 ISD::SETNE); 1750 } 1751 1752 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1753 addSuccessorWithWeight(SwitchBB, NextMBB); 1754 1755 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1756 MVT::Other, getControlRoot(), 1757 Cmp, DAG.getBasicBlock(B.TargetBB)); 1758 1759 // Set NextBlock to be the MBB immediately after the current one, if any. 1760 // This is used to avoid emitting unnecessary branches to the next block. 1761 MachineBasicBlock *NextBlock = 0; 1762 MachineFunction::iterator BBI = SwitchBB; 1763 if (++BBI != FuncInfo.MF->end()) 1764 NextBlock = BBI; 1765 1766 if (NextMBB != NextBlock) 1767 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1768 DAG.getBasicBlock(NextMBB)); 1769 1770 DAG.setRoot(BrAnd); 1771} 1772 1773void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1774 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1775 1776 // Retrieve successors. 1777 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1778 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1779 1780 const Value *Callee(I.getCalledValue()); 1781 if (isa<InlineAsm>(Callee)) 1782 visitInlineAsm(&I); 1783 else 1784 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1785 1786 // If the value of the invoke is used outside of its defining block, make it 1787 // available as a virtual register. 1788 CopyToExportRegsIfNeeded(&I); 1789 1790 // Update successor info 1791 InvokeMBB->addSuccessor(Return); 1792 InvokeMBB->addSuccessor(LandingPad); 1793 1794 // Drop into normal successor. 1795 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1796 MVT::Other, getControlRoot(), 1797 DAG.getBasicBlock(Return))); 1798} 1799 1800void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1801} 1802 1803/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1804/// small case ranges). 1805bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1806 CaseRecVector& WorkList, 1807 const Value* SV, 1808 MachineBasicBlock *Default, 1809 MachineBasicBlock *SwitchBB) { 1810 Case& BackCase = *(CR.Range.second-1); 1811 1812 // Size is the number of Cases represented by this range. 1813 size_t Size = CR.Range.second - CR.Range.first; 1814 if (Size > 3) 1815 return false; 1816 1817 // Get the MachineFunction which holds the current MBB. This is used when 1818 // inserting any additional MBBs necessary to represent the switch. 1819 MachineFunction *CurMF = FuncInfo.MF; 1820 1821 // Figure out which block is immediately after the current one. 1822 MachineBasicBlock *NextBlock = 0; 1823 MachineFunction::iterator BBI = CR.CaseBB; 1824 1825 if (++BBI != FuncInfo.MF->end()) 1826 NextBlock = BBI; 1827 1828 // If any two of the cases has the same destination, and if one value 1829 // is the same as the other, but has one bit unset that the other has set, 1830 // use bit manipulation to do two compares at once. For example: 1831 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1832 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1833 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1834 if (Size == 2 && CR.CaseBB == SwitchBB) { 1835 Case &Small = *CR.Range.first; 1836 Case &Big = *(CR.Range.second-1); 1837 1838 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1839 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1840 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1841 1842 // Check that there is only one bit different. 1843 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1844 (SmallValue | BigValue) == BigValue) { 1845 // Isolate the common bit. 1846 APInt CommonBit = BigValue & ~SmallValue; 1847 assert((SmallValue | CommonBit) == BigValue && 1848 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1849 1850 SDValue CondLHS = getValue(SV); 1851 EVT VT = CondLHS.getValueType(); 1852 DebugLoc DL = getCurDebugLoc(); 1853 1854 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1855 DAG.getConstant(CommonBit, VT)); 1856 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1857 Or, DAG.getConstant(BigValue, VT), 1858 ISD::SETEQ); 1859 1860 // Update successor info. 1861 SwitchBB->addSuccessor(Small.BB); 1862 SwitchBB->addSuccessor(Default); 1863 1864 // Insert the true branch. 1865 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1866 getControlRoot(), Cond, 1867 DAG.getBasicBlock(Small.BB)); 1868 1869 // Insert the false branch. 1870 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1871 DAG.getBasicBlock(Default)); 1872 1873 DAG.setRoot(BrCond); 1874 return true; 1875 } 1876 } 1877 } 1878 1879 // Rearrange the case blocks so that the last one falls through if possible. 1880 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1881 // The last case block won't fall through into 'NextBlock' if we emit the 1882 // branches in this order. See if rearranging a case value would help. 1883 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1884 if (I->BB == NextBlock) { 1885 std::swap(*I, BackCase); 1886 break; 1887 } 1888 } 1889 } 1890 1891 // Create a CaseBlock record representing a conditional branch to 1892 // the Case's target mbb if the value being switched on SV is equal 1893 // to C. 1894 MachineBasicBlock *CurBlock = CR.CaseBB; 1895 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1896 MachineBasicBlock *FallThrough; 1897 if (I != E-1) { 1898 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1899 CurMF->insert(BBI, FallThrough); 1900 1901 // Put SV in a virtual register to make it available from the new blocks. 1902 ExportFromCurrentBlock(SV); 1903 } else { 1904 // If the last case doesn't match, go to the default block. 1905 FallThrough = Default; 1906 } 1907 1908 const Value *RHS, *LHS, *MHS; 1909 ISD::CondCode CC; 1910 if (I->High == I->Low) { 1911 // This is just small small case range :) containing exactly 1 case 1912 CC = ISD::SETEQ; 1913 LHS = SV; RHS = I->High; MHS = NULL; 1914 } else { 1915 CC = ISD::SETLE; 1916 LHS = I->Low; MHS = SV; RHS = I->High; 1917 } 1918 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1919 1920 // If emitting the first comparison, just call visitSwitchCase to emit the 1921 // code into the current block. Otherwise, push the CaseBlock onto the 1922 // vector to be later processed by SDISel, and insert the node's MBB 1923 // before the next MBB. 1924 if (CurBlock == SwitchBB) 1925 visitSwitchCase(CB, SwitchBB); 1926 else 1927 SwitchCases.push_back(CB); 1928 1929 CurBlock = FallThrough; 1930 } 1931 1932 return true; 1933} 1934 1935static inline bool areJTsAllowed(const TargetLowering &TLI) { 1936 return !DisableJumpTables && 1937 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1938 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1939} 1940 1941static APInt ComputeRange(const APInt &First, const APInt &Last) { 1942 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1943 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 1944 return (LastExt - FirstExt + 1ULL); 1945} 1946 1947/// handleJTSwitchCase - Emit jumptable for current switch case range 1948bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1949 CaseRecVector& WorkList, 1950 const Value* SV, 1951 MachineBasicBlock* Default, 1952 MachineBasicBlock *SwitchBB) { 1953 Case& FrontCase = *CR.Range.first; 1954 Case& BackCase = *(CR.Range.second-1); 1955 1956 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1957 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1958 1959 APInt TSize(First.getBitWidth(), 0); 1960 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1961 I!=E; ++I) 1962 TSize += I->size(); 1963 1964 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1965 return false; 1966 1967 APInt Range = ComputeRange(First, Last); 1968 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1969 if (Density < 0.4) 1970 return false; 1971 1972 DEBUG(dbgs() << "Lowering jump table\n" 1973 << "First entry: " << First << ". Last entry: " << Last << '\n' 1974 << "Range: " << Range 1975 << ". Size: " << TSize << ". Density: " << Density << "\n\n"); 1976 1977 // Get the MachineFunction which holds the current MBB. This is used when 1978 // inserting any additional MBBs necessary to represent the switch. 1979 MachineFunction *CurMF = FuncInfo.MF; 1980 1981 // Figure out which block is immediately after the current one. 1982 MachineFunction::iterator BBI = CR.CaseBB; 1983 ++BBI; 1984 1985 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1986 1987 // Create a new basic block to hold the code for loading the address 1988 // of the jump table, and jumping to it. Update successor information; 1989 // we will either branch to the default case for the switch, or the jump 1990 // table. 1991 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1992 CurMF->insert(BBI, JumpTableBB); 1993 1994 addSuccessorWithWeight(CR.CaseBB, Default); 1995 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 1996 1997 // Build a vector of destination BBs, corresponding to each target 1998 // of the jump table. If the value of the jump table slot corresponds to 1999 // a case statement, push the case's BB onto the vector, otherwise, push 2000 // the default BB. 2001 std::vector<MachineBasicBlock*> DestBBs; 2002 APInt TEI = First; 2003 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2004 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2005 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2006 2007 if (Low.sle(TEI) && TEI.sle(High)) { 2008 DestBBs.push_back(I->BB); 2009 if (TEI==High) 2010 ++I; 2011 } else { 2012 DestBBs.push_back(Default); 2013 } 2014 } 2015 2016 // Update successor info. Add one edge to each unique successor. 2017 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2018 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2019 E = DestBBs.end(); I != E; ++I) { 2020 if (!SuccsHandled[(*I)->getNumber()]) { 2021 SuccsHandled[(*I)->getNumber()] = true; 2022 addSuccessorWithWeight(JumpTableBB, *I); 2023 } 2024 } 2025 2026 // Create a jump table index for this jump table. 2027 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2028 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2029 ->createJumpTableIndex(DestBBs); 2030 2031 // Set the jump table information so that we can codegen it as a second 2032 // MachineBasicBlock 2033 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2034 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2035 if (CR.CaseBB == SwitchBB) 2036 visitJumpTableHeader(JT, JTH, SwitchBB); 2037 2038 JTCases.push_back(JumpTableBlock(JTH, JT)); 2039 2040 return true; 2041} 2042 2043/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2044/// 2 subtrees. 2045bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2046 CaseRecVector& WorkList, 2047 const Value* SV, 2048 MachineBasicBlock *Default, 2049 MachineBasicBlock *SwitchBB) { 2050 // Get the MachineFunction which holds the current MBB. This is used when 2051 // inserting any additional MBBs necessary to represent the switch. 2052 MachineFunction *CurMF = FuncInfo.MF; 2053 2054 // Figure out which block is immediately after the current one. 2055 MachineFunction::iterator BBI = CR.CaseBB; 2056 ++BBI; 2057 2058 Case& FrontCase = *CR.Range.first; 2059 Case& BackCase = *(CR.Range.second-1); 2060 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2061 2062 // Size is the number of Cases represented by this range. 2063 unsigned Size = CR.Range.second - CR.Range.first; 2064 2065 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2066 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2067 double FMetric = 0; 2068 CaseItr Pivot = CR.Range.first + Size/2; 2069 2070 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2071 // (heuristically) allow us to emit JumpTable's later. 2072 APInt TSize(First.getBitWidth(), 0); 2073 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2074 I!=E; ++I) 2075 TSize += I->size(); 2076 2077 APInt LSize = FrontCase.size(); 2078 APInt RSize = TSize-LSize; 2079 DEBUG(dbgs() << "Selecting best pivot: \n" 2080 << "First: " << First << ", Last: " << Last <<'\n' 2081 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2082 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2083 J!=E; ++I, ++J) { 2084 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2085 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2086 APInt Range = ComputeRange(LEnd, RBegin); 2087 assert((Range - 2ULL).isNonNegative() && 2088 "Invalid case distance"); 2089 // Use volatile double here to avoid excess precision issues on some hosts, 2090 // e.g. that use 80-bit X87 registers. 2091 volatile double LDensity = 2092 (double)LSize.roundToDouble() / 2093 (LEnd - First + 1ULL).roundToDouble(); 2094 volatile double RDensity = 2095 (double)RSize.roundToDouble() / 2096 (Last - RBegin + 1ULL).roundToDouble(); 2097 double Metric = Range.logBase2()*(LDensity+RDensity); 2098 // Should always split in some non-trivial place 2099 DEBUG(dbgs() <<"=>Step\n" 2100 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2101 << "LDensity: " << LDensity 2102 << ", RDensity: " << RDensity << '\n' 2103 << "Metric: " << Metric << '\n'); 2104 if (FMetric < Metric) { 2105 Pivot = J; 2106 FMetric = Metric; 2107 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2108 } 2109 2110 LSize += J->size(); 2111 RSize -= J->size(); 2112 } 2113 if (areJTsAllowed(TLI)) { 2114 // If our case is dense we *really* should handle it earlier! 2115 assert((FMetric > 0) && "Should handle dense range earlier!"); 2116 } else { 2117 Pivot = CR.Range.first + Size/2; 2118 } 2119 2120 CaseRange LHSR(CR.Range.first, Pivot); 2121 CaseRange RHSR(Pivot, CR.Range.second); 2122 Constant *C = Pivot->Low; 2123 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2124 2125 // We know that we branch to the LHS if the Value being switched on is 2126 // less than the Pivot value, C. We use this to optimize our binary 2127 // tree a bit, by recognizing that if SV is greater than or equal to the 2128 // LHS's Case Value, and that Case Value is exactly one less than the 2129 // Pivot's Value, then we can branch directly to the LHS's Target, 2130 // rather than creating a leaf node for it. 2131 if ((LHSR.second - LHSR.first) == 1 && 2132 LHSR.first->High == CR.GE && 2133 cast<ConstantInt>(C)->getValue() == 2134 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2135 TrueBB = LHSR.first->BB; 2136 } else { 2137 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2138 CurMF->insert(BBI, TrueBB); 2139 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2140 2141 // Put SV in a virtual register to make it available from the new blocks. 2142 ExportFromCurrentBlock(SV); 2143 } 2144 2145 // Similar to the optimization above, if the Value being switched on is 2146 // known to be less than the Constant CR.LT, and the current Case Value 2147 // is CR.LT - 1, then we can branch directly to the target block for 2148 // the current Case Value, rather than emitting a RHS leaf node for it. 2149 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2150 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2151 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2152 FalseBB = RHSR.first->BB; 2153 } else { 2154 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2155 CurMF->insert(BBI, FalseBB); 2156 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2157 2158 // Put SV in a virtual register to make it available from the new blocks. 2159 ExportFromCurrentBlock(SV); 2160 } 2161 2162 // Create a CaseBlock record representing a conditional branch to 2163 // the LHS node if the value being switched on SV is less than C. 2164 // Otherwise, branch to LHS. 2165 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2166 2167 if (CR.CaseBB == SwitchBB) 2168 visitSwitchCase(CB, SwitchBB); 2169 else 2170 SwitchCases.push_back(CB); 2171 2172 return true; 2173} 2174 2175/// handleBitTestsSwitchCase - if current case range has few destination and 2176/// range span less, than machine word bitwidth, encode case range into series 2177/// of masks and emit bit tests with these masks. 2178bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2179 CaseRecVector& WorkList, 2180 const Value* SV, 2181 MachineBasicBlock* Default, 2182 MachineBasicBlock *SwitchBB){ 2183 EVT PTy = TLI.getPointerTy(); 2184 unsigned IntPtrBits = PTy.getSizeInBits(); 2185 2186 Case& FrontCase = *CR.Range.first; 2187 Case& BackCase = *(CR.Range.second-1); 2188 2189 // Get the MachineFunction which holds the current MBB. This is used when 2190 // inserting any additional MBBs necessary to represent the switch. 2191 MachineFunction *CurMF = FuncInfo.MF; 2192 2193 // If target does not have legal shift left, do not emit bit tests at all. 2194 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2195 return false; 2196 2197 size_t numCmps = 0; 2198 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2199 I!=E; ++I) { 2200 // Single case counts one, case range - two. 2201 numCmps += (I->Low == I->High ? 1 : 2); 2202 } 2203 2204 // Count unique destinations 2205 SmallSet<MachineBasicBlock*, 4> Dests; 2206 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2207 Dests.insert(I->BB); 2208 if (Dests.size() > 3) 2209 // Don't bother the code below, if there are too much unique destinations 2210 return false; 2211 } 2212 DEBUG(dbgs() << "Total number of unique destinations: " 2213 << Dests.size() << '\n' 2214 << "Total number of comparisons: " << numCmps << '\n'); 2215 2216 // Compute span of values. 2217 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2218 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2219 APInt cmpRange = maxValue - minValue; 2220 2221 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2222 << "Low bound: " << minValue << '\n' 2223 << "High bound: " << maxValue << '\n'); 2224 2225 if (cmpRange.uge(IntPtrBits) || 2226 (!(Dests.size() == 1 && numCmps >= 3) && 2227 !(Dests.size() == 2 && numCmps >= 5) && 2228 !(Dests.size() >= 3 && numCmps >= 6))) 2229 return false; 2230 2231 DEBUG(dbgs() << "Emitting bit tests\n"); 2232 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2233 2234 // Optimize the case where all the case values fit in a 2235 // word without having to subtract minValue. In this case, 2236 // we can optimize away the subtraction. 2237 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2238 cmpRange = maxValue; 2239 } else { 2240 lowBound = minValue; 2241 } 2242 2243 CaseBitsVector CasesBits; 2244 unsigned i, count = 0; 2245 2246 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2247 MachineBasicBlock* Dest = I->BB; 2248 for (i = 0; i < count; ++i) 2249 if (Dest == CasesBits[i].BB) 2250 break; 2251 2252 if (i == count) { 2253 assert((count < 3) && "Too much destinations to test!"); 2254 CasesBits.push_back(CaseBits(0, Dest, 0)); 2255 count++; 2256 } 2257 2258 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2259 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2260 2261 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2262 uint64_t hi = (highValue - lowBound).getZExtValue(); 2263 2264 for (uint64_t j = lo; j <= hi; j++) { 2265 CasesBits[i].Mask |= 1ULL << j; 2266 CasesBits[i].Bits++; 2267 } 2268 2269 } 2270 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2271 2272 BitTestInfo BTC; 2273 2274 // Figure out which block is immediately after the current one. 2275 MachineFunction::iterator BBI = CR.CaseBB; 2276 ++BBI; 2277 2278 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2279 2280 DEBUG(dbgs() << "Cases:\n"); 2281 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2282 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2283 << ", Bits: " << CasesBits[i].Bits 2284 << ", BB: " << CasesBits[i].BB << '\n'); 2285 2286 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2287 CurMF->insert(BBI, CaseBB); 2288 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2289 CaseBB, 2290 CasesBits[i].BB)); 2291 2292 // Put SV in a virtual register to make it available from the new blocks. 2293 ExportFromCurrentBlock(SV); 2294 } 2295 2296 BitTestBlock BTB(lowBound, cmpRange, SV, 2297 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2298 CR.CaseBB, Default, BTC); 2299 2300 if (CR.CaseBB == SwitchBB) 2301 visitBitTestHeader(BTB, SwitchBB); 2302 2303 BitTestCases.push_back(BTB); 2304 2305 return true; 2306} 2307 2308/// Clusterify - Transform simple list of Cases into list of CaseRange's 2309size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2310 const SwitchInst& SI) { 2311 size_t numCmps = 0; 2312 2313 // Start with "simple" cases 2314 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2315 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2316 Cases.push_back(Case(SI.getSuccessorValue(i), 2317 SI.getSuccessorValue(i), 2318 SMBB)); 2319 } 2320 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2321 2322 // Merge case into clusters 2323 if (Cases.size() >= 2) 2324 // Must recompute end() each iteration because it may be 2325 // invalidated by erase if we hold on to it 2326 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2327 J != Cases.end(); ) { 2328 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2329 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2330 MachineBasicBlock* nextBB = J->BB; 2331 MachineBasicBlock* currentBB = I->BB; 2332 2333 // If the two neighboring cases go to the same destination, merge them 2334 // into a single case. 2335 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2336 I->High = J->High; 2337 J = Cases.erase(J); 2338 } else { 2339 I = J++; 2340 } 2341 } 2342 2343 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2344 if (I->Low != I->High) 2345 // A range counts double, since it requires two compares. 2346 ++numCmps; 2347 } 2348 2349 return numCmps; 2350} 2351 2352void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2353 MachineBasicBlock *Last) { 2354 // Update JTCases. 2355 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2356 if (JTCases[i].first.HeaderBB == First) 2357 JTCases[i].first.HeaderBB = Last; 2358 2359 // Update BitTestCases. 2360 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2361 if (BitTestCases[i].Parent == First) 2362 BitTestCases[i].Parent = Last; 2363} 2364 2365void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2366 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2367 2368 // Figure out which block is immediately after the current one. 2369 MachineBasicBlock *NextBlock = 0; 2370 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2371 2372 // If there is only the default destination, branch to it if it is not the 2373 // next basic block. Otherwise, just fall through. 2374 if (SI.getNumOperands() == 2) { 2375 // Update machine-CFG edges. 2376 2377 // If this is not a fall-through branch, emit the branch. 2378 SwitchMBB->addSuccessor(Default); 2379 if (Default != NextBlock) 2380 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2381 MVT::Other, getControlRoot(), 2382 DAG.getBasicBlock(Default))); 2383 2384 return; 2385 } 2386 2387 // If there are any non-default case statements, create a vector of Cases 2388 // representing each one, and sort the vector so that we can efficiently 2389 // create a binary search tree from them. 2390 CaseVector Cases; 2391 size_t numCmps = Clusterify(Cases, SI); 2392 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2393 << ". Total compares: " << numCmps << '\n'); 2394 numCmps = 0; 2395 2396 // Get the Value to be switched on and default basic blocks, which will be 2397 // inserted into CaseBlock records, representing basic blocks in the binary 2398 // search tree. 2399 const Value *SV = SI.getOperand(0); 2400 2401 // Push the initial CaseRec onto the worklist 2402 CaseRecVector WorkList; 2403 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2404 CaseRange(Cases.begin(),Cases.end()))); 2405 2406 while (!WorkList.empty()) { 2407 // Grab a record representing a case range to process off the worklist 2408 CaseRec CR = WorkList.back(); 2409 WorkList.pop_back(); 2410 2411 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2412 continue; 2413 2414 // If the range has few cases (two or less) emit a series of specific 2415 // tests. 2416 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2417 continue; 2418 2419 // If the switch has more than 5 blocks, and at least 40% dense, and the 2420 // target supports indirect branches, then emit a jump table rather than 2421 // lowering the switch to a binary tree of conditional branches. 2422 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2423 continue; 2424 2425 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2426 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2427 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2428 } 2429} 2430 2431void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2432 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2433 2434 // Update machine-CFG edges with unique successors. 2435 SmallVector<BasicBlock*, 32> succs; 2436 succs.reserve(I.getNumSuccessors()); 2437 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2438 succs.push_back(I.getSuccessor(i)); 2439 array_pod_sort(succs.begin(), succs.end()); 2440 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2441 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2442 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2443 addSuccessorWithWeight(IndirectBrMBB, Succ); 2444 } 2445 2446 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2447 MVT::Other, getControlRoot(), 2448 getValue(I.getAddress()))); 2449} 2450 2451void SelectionDAGBuilder::visitFSub(const User &I) { 2452 // -0.0 - X --> fneg 2453 const Type *Ty = I.getType(); 2454 if (isa<Constant>(I.getOperand(0)) && 2455 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2456 SDValue Op2 = getValue(I.getOperand(1)); 2457 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2458 Op2.getValueType(), Op2)); 2459 return; 2460 } 2461 2462 visitBinary(I, ISD::FSUB); 2463} 2464 2465void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2466 SDValue Op1 = getValue(I.getOperand(0)); 2467 SDValue Op2 = getValue(I.getOperand(1)); 2468 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2469 Op1.getValueType(), Op1, Op2)); 2470} 2471 2472void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2473 SDValue Op1 = getValue(I.getOperand(0)); 2474 SDValue Op2 = getValue(I.getOperand(1)); 2475 2476 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2477 2478 // Coerce the shift amount to the right type if we can. 2479 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2480 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2481 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2482 DebugLoc DL = getCurDebugLoc(); 2483 2484 // If the operand is smaller than the shift count type, promote it. 2485 if (ShiftSize > Op2Size) 2486 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2487 2488 // If the operand is larger than the shift count type but the shift 2489 // count type has enough bits to represent any shift value, truncate 2490 // it now. This is a common case and it exposes the truncate to 2491 // optimization early. 2492 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2493 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2494 // Otherwise we'll need to temporarily settle for some other convenient 2495 // type. Type legalization will make adjustments once the shiftee is split. 2496 else 2497 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2498 } 2499 2500 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2501 Op1.getValueType(), Op1, Op2)); 2502} 2503 2504void SelectionDAGBuilder::visitICmp(const User &I) { 2505 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2506 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2507 predicate = IC->getPredicate(); 2508 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2509 predicate = ICmpInst::Predicate(IC->getPredicate()); 2510 SDValue Op1 = getValue(I.getOperand(0)); 2511 SDValue Op2 = getValue(I.getOperand(1)); 2512 ISD::CondCode Opcode = getICmpCondCode(predicate); 2513 2514 EVT DestVT = TLI.getValueType(I.getType()); 2515 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2516} 2517 2518void SelectionDAGBuilder::visitFCmp(const User &I) { 2519 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2520 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2521 predicate = FC->getPredicate(); 2522 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2523 predicate = FCmpInst::Predicate(FC->getPredicate()); 2524 SDValue Op1 = getValue(I.getOperand(0)); 2525 SDValue Op2 = getValue(I.getOperand(1)); 2526 ISD::CondCode Condition = getFCmpCondCode(predicate); 2527 EVT DestVT = TLI.getValueType(I.getType()); 2528 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2529} 2530 2531void SelectionDAGBuilder::visitSelect(const User &I) { 2532 SmallVector<EVT, 4> ValueVTs; 2533 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2534 unsigned NumValues = ValueVTs.size(); 2535 if (NumValues == 0) return; 2536 2537 SmallVector<SDValue, 4> Values(NumValues); 2538 SDValue Cond = getValue(I.getOperand(0)); 2539 SDValue TrueVal = getValue(I.getOperand(1)); 2540 SDValue FalseVal = getValue(I.getOperand(2)); 2541 2542 for (unsigned i = 0; i != NumValues; ++i) 2543 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2544 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2545 Cond, 2546 SDValue(TrueVal.getNode(), 2547 TrueVal.getResNo() + i), 2548 SDValue(FalseVal.getNode(), 2549 FalseVal.getResNo() + i)); 2550 2551 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2552 DAG.getVTList(&ValueVTs[0], NumValues), 2553 &Values[0], NumValues)); 2554} 2555 2556void SelectionDAGBuilder::visitTrunc(const User &I) { 2557 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2558 SDValue N = getValue(I.getOperand(0)); 2559 EVT DestVT = TLI.getValueType(I.getType()); 2560 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2561} 2562 2563void SelectionDAGBuilder::visitZExt(const User &I) { 2564 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2565 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2566 SDValue N = getValue(I.getOperand(0)); 2567 EVT DestVT = TLI.getValueType(I.getType()); 2568 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2569} 2570 2571void SelectionDAGBuilder::visitSExt(const User &I) { 2572 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2573 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2574 SDValue N = getValue(I.getOperand(0)); 2575 EVT DestVT = TLI.getValueType(I.getType()); 2576 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2577} 2578 2579void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2580 // FPTrunc is never a no-op cast, no need to check 2581 SDValue N = getValue(I.getOperand(0)); 2582 EVT DestVT = TLI.getValueType(I.getType()); 2583 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2584 DestVT, N, DAG.getIntPtrConstant(0))); 2585} 2586 2587void SelectionDAGBuilder::visitFPExt(const User &I){ 2588 // FPTrunc is never a no-op cast, no need to check 2589 SDValue N = getValue(I.getOperand(0)); 2590 EVT DestVT = TLI.getValueType(I.getType()); 2591 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2592} 2593 2594void SelectionDAGBuilder::visitFPToUI(const User &I) { 2595 // FPToUI is never a no-op cast, no need to check 2596 SDValue N = getValue(I.getOperand(0)); 2597 EVT DestVT = TLI.getValueType(I.getType()); 2598 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2599} 2600 2601void SelectionDAGBuilder::visitFPToSI(const User &I) { 2602 // FPToSI is never a no-op cast, no need to check 2603 SDValue N = getValue(I.getOperand(0)); 2604 EVT DestVT = TLI.getValueType(I.getType()); 2605 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2606} 2607 2608void SelectionDAGBuilder::visitUIToFP(const User &I) { 2609 // UIToFP is never a no-op cast, no need to check 2610 SDValue N = getValue(I.getOperand(0)); 2611 EVT DestVT = TLI.getValueType(I.getType()); 2612 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2613} 2614 2615void SelectionDAGBuilder::visitSIToFP(const User &I){ 2616 // SIToFP is never a no-op cast, no need to check 2617 SDValue N = getValue(I.getOperand(0)); 2618 EVT DestVT = TLI.getValueType(I.getType()); 2619 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2620} 2621 2622void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2623 // What to do depends on the size of the integer and the size of the pointer. 2624 // We can either truncate, zero extend, or no-op, accordingly. 2625 SDValue N = getValue(I.getOperand(0)); 2626 EVT DestVT = TLI.getValueType(I.getType()); 2627 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2628} 2629 2630void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2631 // What to do depends on the size of the integer and the size of the pointer. 2632 // We can either truncate, zero extend, or no-op, accordingly. 2633 SDValue N = getValue(I.getOperand(0)); 2634 EVT DestVT = TLI.getValueType(I.getType()); 2635 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2636} 2637 2638void SelectionDAGBuilder::visitBitCast(const User &I) { 2639 SDValue N = getValue(I.getOperand(0)); 2640 EVT DestVT = TLI.getValueType(I.getType()); 2641 2642 // BitCast assures us that source and destination are the same size so this is 2643 // either a BITCAST or a no-op. 2644 if (DestVT != N.getValueType()) 2645 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2646 DestVT, N)); // convert types. 2647 else 2648 setValue(&I, N); // noop cast. 2649} 2650 2651void SelectionDAGBuilder::visitInsertElement(const User &I) { 2652 SDValue InVec = getValue(I.getOperand(0)); 2653 SDValue InVal = getValue(I.getOperand(1)); 2654 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2655 TLI.getPointerTy(), 2656 getValue(I.getOperand(2))); 2657 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2658 TLI.getValueType(I.getType()), 2659 InVec, InVal, InIdx)); 2660} 2661 2662void SelectionDAGBuilder::visitExtractElement(const User &I) { 2663 SDValue InVec = getValue(I.getOperand(0)); 2664 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2665 TLI.getPointerTy(), 2666 getValue(I.getOperand(1))); 2667 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2668 TLI.getValueType(I.getType()), InVec, InIdx)); 2669} 2670 2671// Utility for visitShuffleVector - Returns true if the mask is mask starting 2672// from SIndx and increasing to the element length (undefs are allowed). 2673static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2674 unsigned MaskNumElts = Mask.size(); 2675 for (unsigned i = 0; i != MaskNumElts; ++i) 2676 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2677 return false; 2678 return true; 2679} 2680 2681void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2682 SmallVector<int, 8> Mask; 2683 SDValue Src1 = getValue(I.getOperand(0)); 2684 SDValue Src2 = getValue(I.getOperand(1)); 2685 2686 // Convert the ConstantVector mask operand into an array of ints, with -1 2687 // representing undef values. 2688 SmallVector<Constant*, 8> MaskElts; 2689 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2690 unsigned MaskNumElts = MaskElts.size(); 2691 for (unsigned i = 0; i != MaskNumElts; ++i) { 2692 if (isa<UndefValue>(MaskElts[i])) 2693 Mask.push_back(-1); 2694 else 2695 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2696 } 2697 2698 EVT VT = TLI.getValueType(I.getType()); 2699 EVT SrcVT = Src1.getValueType(); 2700 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2701 2702 if (SrcNumElts == MaskNumElts) { 2703 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2704 &Mask[0])); 2705 return; 2706 } 2707 2708 // Normalize the shuffle vector since mask and vector length don't match. 2709 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2710 // Mask is longer than the source vectors and is a multiple of the source 2711 // vectors. We can use concatenate vector to make the mask and vectors 2712 // lengths match. 2713 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2714 // The shuffle is concatenating two vectors together. 2715 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2716 VT, Src1, Src2)); 2717 return; 2718 } 2719 2720 // Pad both vectors with undefs to make them the same length as the mask. 2721 unsigned NumConcat = MaskNumElts / SrcNumElts; 2722 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2723 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2724 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2725 2726 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2727 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2728 MOps1[0] = Src1; 2729 MOps2[0] = Src2; 2730 2731 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2732 getCurDebugLoc(), VT, 2733 &MOps1[0], NumConcat); 2734 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2735 getCurDebugLoc(), VT, 2736 &MOps2[0], NumConcat); 2737 2738 // Readjust mask for new input vector length. 2739 SmallVector<int, 8> MappedOps; 2740 for (unsigned i = 0; i != MaskNumElts; ++i) { 2741 int Idx = Mask[i]; 2742 if (Idx < (int)SrcNumElts) 2743 MappedOps.push_back(Idx); 2744 else 2745 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2746 } 2747 2748 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2749 &MappedOps[0])); 2750 return; 2751 } 2752 2753 if (SrcNumElts > MaskNumElts) { 2754 // Analyze the access pattern of the vector to see if we can extract 2755 // two subvectors and do the shuffle. The analysis is done by calculating 2756 // the range of elements the mask access on both vectors. 2757 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2758 int MaxRange[2] = {-1, -1}; 2759 2760 for (unsigned i = 0; i != MaskNumElts; ++i) { 2761 int Idx = Mask[i]; 2762 int Input = 0; 2763 if (Idx < 0) 2764 continue; 2765 2766 if (Idx >= (int)SrcNumElts) { 2767 Input = 1; 2768 Idx -= SrcNumElts; 2769 } 2770 if (Idx > MaxRange[Input]) 2771 MaxRange[Input] = Idx; 2772 if (Idx < MinRange[Input]) 2773 MinRange[Input] = Idx; 2774 } 2775 2776 // Check if the access is smaller than the vector size and can we find 2777 // a reasonable extract index. 2778 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2779 // Extract. 2780 int StartIdx[2]; // StartIdx to extract from 2781 for (int Input=0; Input < 2; ++Input) { 2782 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2783 RangeUse[Input] = 0; // Unused 2784 StartIdx[Input] = 0; 2785 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2786 // Fits within range but we should see if we can find a good 2787 // start index that is a multiple of the mask length. 2788 if (MaxRange[Input] < (int)MaskNumElts) { 2789 RangeUse[Input] = 1; // Extract from beginning of the vector 2790 StartIdx[Input] = 0; 2791 } else { 2792 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2793 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2794 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2795 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2796 } 2797 } 2798 } 2799 2800 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2801 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2802 return; 2803 } 2804 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2805 // Extract appropriate subvector and generate a vector shuffle 2806 for (int Input=0; Input < 2; ++Input) { 2807 SDValue &Src = Input == 0 ? Src1 : Src2; 2808 if (RangeUse[Input] == 0) 2809 Src = DAG.getUNDEF(VT); 2810 else 2811 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2812 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2813 } 2814 2815 // Calculate new mask. 2816 SmallVector<int, 8> MappedOps; 2817 for (unsigned i = 0; i != MaskNumElts; ++i) { 2818 int Idx = Mask[i]; 2819 if (Idx < 0) 2820 MappedOps.push_back(Idx); 2821 else if (Idx < (int)SrcNumElts) 2822 MappedOps.push_back(Idx - StartIdx[0]); 2823 else 2824 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2825 } 2826 2827 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2828 &MappedOps[0])); 2829 return; 2830 } 2831 } 2832 2833 // We can't use either concat vectors or extract subvectors so fall back to 2834 // replacing the shuffle with extract and build vector. 2835 // to insert and build vector. 2836 EVT EltVT = VT.getVectorElementType(); 2837 EVT PtrVT = TLI.getPointerTy(); 2838 SmallVector<SDValue,8> Ops; 2839 for (unsigned i = 0; i != MaskNumElts; ++i) { 2840 if (Mask[i] < 0) { 2841 Ops.push_back(DAG.getUNDEF(EltVT)); 2842 } else { 2843 int Idx = Mask[i]; 2844 SDValue Res; 2845 2846 if (Idx < (int)SrcNumElts) 2847 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2848 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2849 else 2850 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2851 EltVT, Src2, 2852 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2853 2854 Ops.push_back(Res); 2855 } 2856 } 2857 2858 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2859 VT, &Ops[0], Ops.size())); 2860} 2861 2862void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2863 const Value *Op0 = I.getOperand(0); 2864 const Value *Op1 = I.getOperand(1); 2865 const Type *AggTy = I.getType(); 2866 const Type *ValTy = Op1->getType(); 2867 bool IntoUndef = isa<UndefValue>(Op0); 2868 bool FromUndef = isa<UndefValue>(Op1); 2869 2870 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2871 2872 SmallVector<EVT, 4> AggValueVTs; 2873 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2874 SmallVector<EVT, 4> ValValueVTs; 2875 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2876 2877 unsigned NumAggValues = AggValueVTs.size(); 2878 unsigned NumValValues = ValValueVTs.size(); 2879 SmallVector<SDValue, 4> Values(NumAggValues); 2880 2881 SDValue Agg = getValue(Op0); 2882 unsigned i = 0; 2883 // Copy the beginning value(s) from the original aggregate. 2884 for (; i != LinearIndex; ++i) 2885 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2886 SDValue(Agg.getNode(), Agg.getResNo() + i); 2887 // Copy values from the inserted value(s). 2888 if (NumValValues) { 2889 SDValue Val = getValue(Op1); 2890 for (; i != LinearIndex + NumValValues; ++i) 2891 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2892 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2893 } 2894 // Copy remaining value(s) from the original aggregate. 2895 for (; i != NumAggValues; ++i) 2896 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2897 SDValue(Agg.getNode(), Agg.getResNo() + i); 2898 2899 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2900 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2901 &Values[0], NumAggValues)); 2902} 2903 2904void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2905 const Value *Op0 = I.getOperand(0); 2906 const Type *AggTy = Op0->getType(); 2907 const Type *ValTy = I.getType(); 2908 bool OutOfUndef = isa<UndefValue>(Op0); 2909 2910 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2911 2912 SmallVector<EVT, 4> ValValueVTs; 2913 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2914 2915 unsigned NumValValues = ValValueVTs.size(); 2916 2917 // Ignore a extractvalue that produces an empty object 2918 if (!NumValValues) { 2919 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 2920 return; 2921 } 2922 2923 SmallVector<SDValue, 4> Values(NumValValues); 2924 2925 SDValue Agg = getValue(Op0); 2926 // Copy out the selected value(s). 2927 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2928 Values[i - LinearIndex] = 2929 OutOfUndef ? 2930 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2931 SDValue(Agg.getNode(), Agg.getResNo() + i); 2932 2933 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2934 DAG.getVTList(&ValValueVTs[0], NumValValues), 2935 &Values[0], NumValValues)); 2936} 2937 2938void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2939 SDValue N = getValue(I.getOperand(0)); 2940 const Type *Ty = I.getOperand(0)->getType(); 2941 2942 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2943 OI != E; ++OI) { 2944 const Value *Idx = *OI; 2945 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2946 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2947 if (Field) { 2948 // N = N + Offset 2949 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2950 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2951 DAG.getIntPtrConstant(Offset)); 2952 } 2953 2954 Ty = StTy->getElementType(Field); 2955 } else { 2956 Ty = cast<SequentialType>(Ty)->getElementType(); 2957 2958 // If this is a constant subscript, handle it quickly. 2959 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2960 if (CI->isZero()) continue; 2961 uint64_t Offs = 2962 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2963 SDValue OffsVal; 2964 EVT PTy = TLI.getPointerTy(); 2965 unsigned PtrBits = PTy.getSizeInBits(); 2966 if (PtrBits < 64) 2967 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2968 TLI.getPointerTy(), 2969 DAG.getConstant(Offs, MVT::i64)); 2970 else 2971 OffsVal = DAG.getIntPtrConstant(Offs); 2972 2973 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2974 OffsVal); 2975 continue; 2976 } 2977 2978 // N = N + Idx * ElementSize; 2979 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2980 TD->getTypeAllocSize(Ty)); 2981 SDValue IdxN = getValue(Idx); 2982 2983 // If the index is smaller or larger than intptr_t, truncate or extend 2984 // it. 2985 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2986 2987 // If this is a multiply by a power of two, turn it into a shl 2988 // immediately. This is a very common case. 2989 if (ElementSize != 1) { 2990 if (ElementSize.isPowerOf2()) { 2991 unsigned Amt = ElementSize.logBase2(); 2992 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2993 N.getValueType(), IdxN, 2994 DAG.getConstant(Amt, TLI.getPointerTy())); 2995 } else { 2996 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2997 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2998 N.getValueType(), IdxN, Scale); 2999 } 3000 } 3001 3002 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3003 N.getValueType(), N, IdxN); 3004 } 3005 } 3006 3007 setValue(&I, N); 3008} 3009 3010void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3011 // If this is a fixed sized alloca in the entry block of the function, 3012 // allocate it statically on the stack. 3013 if (FuncInfo.StaticAllocaMap.count(&I)) 3014 return; // getValue will auto-populate this. 3015 3016 const Type *Ty = I.getAllocatedType(); 3017 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3018 unsigned Align = 3019 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3020 I.getAlignment()); 3021 3022 SDValue AllocSize = getValue(I.getArraySize()); 3023 3024 EVT IntPtr = TLI.getPointerTy(); 3025 if (AllocSize.getValueType() != IntPtr) 3026 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3027 3028 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3029 AllocSize, 3030 DAG.getConstant(TySize, IntPtr)); 3031 3032 // Handle alignment. If the requested alignment is less than or equal to 3033 // the stack alignment, ignore it. If the size is greater than or equal to 3034 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3035 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3036 if (Align <= StackAlign) 3037 Align = 0; 3038 3039 // Round the size of the allocation up to the stack alignment size 3040 // by add SA-1 to the size. 3041 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3042 AllocSize.getValueType(), AllocSize, 3043 DAG.getIntPtrConstant(StackAlign-1)); 3044 3045 // Mask out the low bits for alignment purposes. 3046 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3047 AllocSize.getValueType(), AllocSize, 3048 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3049 3050 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3051 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3052 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3053 VTs, Ops, 3); 3054 setValue(&I, DSA); 3055 DAG.setRoot(DSA.getValue(1)); 3056 3057 // Inform the Frame Information that we have just allocated a variable-sized 3058 // object. 3059 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3060} 3061 3062void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3063 const Value *SV = I.getOperand(0); 3064 SDValue Ptr = getValue(SV); 3065 3066 const Type *Ty = I.getType(); 3067 3068 bool isVolatile = I.isVolatile(); 3069 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3070 unsigned Alignment = I.getAlignment(); 3071 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3072 3073 SmallVector<EVT, 4> ValueVTs; 3074 SmallVector<uint64_t, 4> Offsets; 3075 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3076 unsigned NumValues = ValueVTs.size(); 3077 if (NumValues == 0) 3078 return; 3079 3080 SDValue Root; 3081 bool ConstantMemory = false; 3082 if (I.isVolatile() || NumValues > MaxParallelChains) 3083 // Serialize volatile loads with other side effects. 3084 Root = getRoot(); 3085 else if (AA->pointsToConstantMemory( 3086 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3087 // Do not serialize (non-volatile) loads of constant memory with anything. 3088 Root = DAG.getEntryNode(); 3089 ConstantMemory = true; 3090 } else { 3091 // Do not serialize non-volatile loads against each other. 3092 Root = DAG.getRoot(); 3093 } 3094 3095 SmallVector<SDValue, 4> Values(NumValues); 3096 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3097 NumValues)); 3098 EVT PtrVT = Ptr.getValueType(); 3099 unsigned ChainI = 0; 3100 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3101 // Serializing loads here may result in excessive register pressure, and 3102 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3103 // could recover a bit by hoisting nodes upward in the chain by recognizing 3104 // they are side-effect free or do not alias. The optimizer should really 3105 // avoid this case by converting large object/array copies to llvm.memcpy 3106 // (MaxParallelChains should always remain as failsafe). 3107 if (ChainI == MaxParallelChains) { 3108 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3109 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3110 MVT::Other, &Chains[0], ChainI); 3111 Root = Chain; 3112 ChainI = 0; 3113 } 3114 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3115 PtrVT, Ptr, 3116 DAG.getConstant(Offsets[i], PtrVT)); 3117 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3118 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3119 isNonTemporal, Alignment, TBAAInfo); 3120 3121 Values[i] = L; 3122 Chains[ChainI] = L.getValue(1); 3123 } 3124 3125 if (!ConstantMemory) { 3126 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3127 MVT::Other, &Chains[0], ChainI); 3128 if (isVolatile) 3129 DAG.setRoot(Chain); 3130 else 3131 PendingLoads.push_back(Chain); 3132 } 3133 3134 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3135 DAG.getVTList(&ValueVTs[0], NumValues), 3136 &Values[0], NumValues)); 3137} 3138 3139void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3140 const Value *SrcV = I.getOperand(0); 3141 const Value *PtrV = I.getOperand(1); 3142 3143 SmallVector<EVT, 4> ValueVTs; 3144 SmallVector<uint64_t, 4> Offsets; 3145 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3146 unsigned NumValues = ValueVTs.size(); 3147 if (NumValues == 0) 3148 return; 3149 3150 // Get the lowered operands. Note that we do this after 3151 // checking if NumResults is zero, because with zero results 3152 // the operands won't have values in the map. 3153 SDValue Src = getValue(SrcV); 3154 SDValue Ptr = getValue(PtrV); 3155 3156 SDValue Root = getRoot(); 3157 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3158 NumValues)); 3159 EVT PtrVT = Ptr.getValueType(); 3160 bool isVolatile = I.isVolatile(); 3161 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3162 unsigned Alignment = I.getAlignment(); 3163 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3164 3165 unsigned ChainI = 0; 3166 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3167 // See visitLoad comments. 3168 if (ChainI == MaxParallelChains) { 3169 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3170 MVT::Other, &Chains[0], ChainI); 3171 Root = Chain; 3172 ChainI = 0; 3173 } 3174 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3175 DAG.getConstant(Offsets[i], PtrVT)); 3176 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3177 SDValue(Src.getNode(), Src.getResNo() + i), 3178 Add, MachinePointerInfo(PtrV, Offsets[i]), 3179 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3180 Chains[ChainI] = St; 3181 } 3182 3183 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3184 MVT::Other, &Chains[0], ChainI); 3185 ++SDNodeOrder; 3186 AssignOrderingToNode(StoreNode.getNode()); 3187 DAG.setRoot(StoreNode); 3188} 3189 3190/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3191/// node. 3192void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3193 unsigned Intrinsic) { 3194 bool HasChain = !I.doesNotAccessMemory(); 3195 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3196 3197 // Build the operand list. 3198 SmallVector<SDValue, 8> Ops; 3199 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3200 if (OnlyLoad) { 3201 // We don't need to serialize loads against other loads. 3202 Ops.push_back(DAG.getRoot()); 3203 } else { 3204 Ops.push_back(getRoot()); 3205 } 3206 } 3207 3208 // Info is set by getTgtMemInstrinsic 3209 TargetLowering::IntrinsicInfo Info; 3210 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3211 3212 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3213 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3214 Info.opc == ISD::INTRINSIC_W_CHAIN) 3215 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3216 3217 // Add all operands of the call to the operand list. 3218 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3219 SDValue Op = getValue(I.getArgOperand(i)); 3220 assert(TLI.isTypeLegal(Op.getValueType()) && 3221 "Intrinsic uses a non-legal type?"); 3222 Ops.push_back(Op); 3223 } 3224 3225 SmallVector<EVT, 4> ValueVTs; 3226 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3227#ifndef NDEBUG 3228 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3229 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3230 "Intrinsic uses a non-legal type?"); 3231 } 3232#endif // NDEBUG 3233 3234 if (HasChain) 3235 ValueVTs.push_back(MVT::Other); 3236 3237 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3238 3239 // Create the node. 3240 SDValue Result; 3241 if (IsTgtIntrinsic) { 3242 // This is target intrinsic that touches memory 3243 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3244 VTs, &Ops[0], Ops.size(), 3245 Info.memVT, 3246 MachinePointerInfo(Info.ptrVal, Info.offset), 3247 Info.align, Info.vol, 3248 Info.readMem, Info.writeMem); 3249 } else if (!HasChain) { 3250 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3251 VTs, &Ops[0], Ops.size()); 3252 } else if (!I.getType()->isVoidTy()) { 3253 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3254 VTs, &Ops[0], Ops.size()); 3255 } else { 3256 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3257 VTs, &Ops[0], Ops.size()); 3258 } 3259 3260 if (HasChain) { 3261 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3262 if (OnlyLoad) 3263 PendingLoads.push_back(Chain); 3264 else 3265 DAG.setRoot(Chain); 3266 } 3267 3268 if (!I.getType()->isVoidTy()) { 3269 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3270 EVT VT = TLI.getValueType(PTy); 3271 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3272 } 3273 3274 setValue(&I, Result); 3275 } 3276} 3277 3278/// GetSignificand - Get the significand and build it into a floating-point 3279/// number with exponent of 1: 3280/// 3281/// Op = (Op & 0x007fffff) | 0x3f800000; 3282/// 3283/// where Op is the hexidecimal representation of floating point value. 3284static SDValue 3285GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3286 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3287 DAG.getConstant(0x007fffff, MVT::i32)); 3288 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3289 DAG.getConstant(0x3f800000, MVT::i32)); 3290 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3291} 3292 3293/// GetExponent - Get the exponent: 3294/// 3295/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3296/// 3297/// where Op is the hexidecimal representation of floating point value. 3298static SDValue 3299GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3300 DebugLoc dl) { 3301 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3302 DAG.getConstant(0x7f800000, MVT::i32)); 3303 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3304 DAG.getConstant(23, TLI.getPointerTy())); 3305 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3306 DAG.getConstant(127, MVT::i32)); 3307 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3308} 3309 3310/// getF32Constant - Get 32-bit floating point constant. 3311static SDValue 3312getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3313 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3314} 3315 3316/// Inlined utility function to implement binary input atomic intrinsics for 3317/// visitIntrinsicCall: I is a call instruction 3318/// Op is the associated NodeType for I 3319const char * 3320SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3321 ISD::NodeType Op) { 3322 SDValue Root = getRoot(); 3323 SDValue L = 3324 DAG.getAtomic(Op, getCurDebugLoc(), 3325 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3326 Root, 3327 getValue(I.getArgOperand(0)), 3328 getValue(I.getArgOperand(1)), 3329 I.getArgOperand(0)); 3330 setValue(&I, L); 3331 DAG.setRoot(L.getValue(1)); 3332 return 0; 3333} 3334 3335// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3336const char * 3337SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3338 SDValue Op1 = getValue(I.getArgOperand(0)); 3339 SDValue Op2 = getValue(I.getArgOperand(1)); 3340 3341 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3342 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3343 return 0; 3344} 3345 3346/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3347/// limited-precision mode. 3348void 3349SelectionDAGBuilder::visitExp(const CallInst &I) { 3350 SDValue result; 3351 DebugLoc dl = getCurDebugLoc(); 3352 3353 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3354 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3355 SDValue Op = getValue(I.getArgOperand(0)); 3356 3357 // Put the exponent in the right bit position for later addition to the 3358 // final result: 3359 // 3360 // #define LOG2OFe 1.4426950f 3361 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3362 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3363 getF32Constant(DAG, 0x3fb8aa3b)); 3364 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3365 3366 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3367 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3368 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3369 3370 // IntegerPartOfX <<= 23; 3371 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3372 DAG.getConstant(23, TLI.getPointerTy())); 3373 3374 if (LimitFloatPrecision <= 6) { 3375 // For floating-point precision of 6: 3376 // 3377 // TwoToFractionalPartOfX = 3378 // 0.997535578f + 3379 // (0.735607626f + 0.252464424f * x) * x; 3380 // 3381 // error 0.0144103317, which is 6 bits 3382 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3383 getF32Constant(DAG, 0x3e814304)); 3384 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3385 getF32Constant(DAG, 0x3f3c50c8)); 3386 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3387 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3388 getF32Constant(DAG, 0x3f7f5e7e)); 3389 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3390 3391 // Add the exponent into the result in integer domain. 3392 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3393 TwoToFracPartOfX, IntegerPartOfX); 3394 3395 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3396 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3397 // For floating-point precision of 12: 3398 // 3399 // TwoToFractionalPartOfX = 3400 // 0.999892986f + 3401 // (0.696457318f + 3402 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3403 // 3404 // 0.000107046256 error, which is 13 to 14 bits 3405 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3406 getF32Constant(DAG, 0x3da235e3)); 3407 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3408 getF32Constant(DAG, 0x3e65b8f3)); 3409 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3410 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3411 getF32Constant(DAG, 0x3f324b07)); 3412 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3413 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3414 getF32Constant(DAG, 0x3f7ff8fd)); 3415 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3416 3417 // Add the exponent into the result in integer domain. 3418 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3419 TwoToFracPartOfX, IntegerPartOfX); 3420 3421 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3422 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3423 // For floating-point precision of 18: 3424 // 3425 // TwoToFractionalPartOfX = 3426 // 0.999999982f + 3427 // (0.693148872f + 3428 // (0.240227044f + 3429 // (0.554906021e-1f + 3430 // (0.961591928e-2f + 3431 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3432 // 3433 // error 2.47208000*10^(-7), which is better than 18 bits 3434 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3435 getF32Constant(DAG, 0x3924b03e)); 3436 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3437 getF32Constant(DAG, 0x3ab24b87)); 3438 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3439 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3440 getF32Constant(DAG, 0x3c1d8c17)); 3441 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3442 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3443 getF32Constant(DAG, 0x3d634a1d)); 3444 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3445 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3446 getF32Constant(DAG, 0x3e75fe14)); 3447 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3448 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3449 getF32Constant(DAG, 0x3f317234)); 3450 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3451 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3452 getF32Constant(DAG, 0x3f800000)); 3453 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3454 MVT::i32, t13); 3455 3456 // Add the exponent into the result in integer domain. 3457 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3458 TwoToFracPartOfX, IntegerPartOfX); 3459 3460 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3461 } 3462 } else { 3463 // No special expansion. 3464 result = DAG.getNode(ISD::FEXP, dl, 3465 getValue(I.getArgOperand(0)).getValueType(), 3466 getValue(I.getArgOperand(0))); 3467 } 3468 3469 setValue(&I, result); 3470} 3471 3472/// visitLog - Lower a log intrinsic. Handles the special sequences for 3473/// limited-precision mode. 3474void 3475SelectionDAGBuilder::visitLog(const CallInst &I) { 3476 SDValue result; 3477 DebugLoc dl = getCurDebugLoc(); 3478 3479 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3480 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3481 SDValue Op = getValue(I.getArgOperand(0)); 3482 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3483 3484 // Scale the exponent by log(2) [0.69314718f]. 3485 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3486 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3487 getF32Constant(DAG, 0x3f317218)); 3488 3489 // Get the significand and build it into a floating-point number with 3490 // exponent of 1. 3491 SDValue X = GetSignificand(DAG, Op1, dl); 3492 3493 if (LimitFloatPrecision <= 6) { 3494 // For floating-point precision of 6: 3495 // 3496 // LogofMantissa = 3497 // -1.1609546f + 3498 // (1.4034025f - 0.23903021f * x) * x; 3499 // 3500 // error 0.0034276066, which is better than 8 bits 3501 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3502 getF32Constant(DAG, 0xbe74c456)); 3503 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3504 getF32Constant(DAG, 0x3fb3a2b1)); 3505 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3506 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3507 getF32Constant(DAG, 0x3f949a29)); 3508 3509 result = DAG.getNode(ISD::FADD, dl, 3510 MVT::f32, LogOfExponent, LogOfMantissa); 3511 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3512 // For floating-point precision of 12: 3513 // 3514 // LogOfMantissa = 3515 // -1.7417939f + 3516 // (2.8212026f + 3517 // (-1.4699568f + 3518 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3519 // 3520 // error 0.000061011436, which is 14 bits 3521 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3522 getF32Constant(DAG, 0xbd67b6d6)); 3523 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3524 getF32Constant(DAG, 0x3ee4f4b8)); 3525 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3526 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3527 getF32Constant(DAG, 0x3fbc278b)); 3528 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3529 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3530 getF32Constant(DAG, 0x40348e95)); 3531 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3532 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3533 getF32Constant(DAG, 0x3fdef31a)); 3534 3535 result = DAG.getNode(ISD::FADD, dl, 3536 MVT::f32, LogOfExponent, LogOfMantissa); 3537 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3538 // For floating-point precision of 18: 3539 // 3540 // LogOfMantissa = 3541 // -2.1072184f + 3542 // (4.2372794f + 3543 // (-3.7029485f + 3544 // (2.2781945f + 3545 // (-0.87823314f + 3546 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3547 // 3548 // error 0.0000023660568, which is better than 18 bits 3549 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3550 getF32Constant(DAG, 0xbc91e5ac)); 3551 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3552 getF32Constant(DAG, 0x3e4350aa)); 3553 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3554 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3555 getF32Constant(DAG, 0x3f60d3e3)); 3556 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3557 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3558 getF32Constant(DAG, 0x4011cdf0)); 3559 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3560 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3561 getF32Constant(DAG, 0x406cfd1c)); 3562 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3563 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3564 getF32Constant(DAG, 0x408797cb)); 3565 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3566 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3567 getF32Constant(DAG, 0x4006dcab)); 3568 3569 result = DAG.getNode(ISD::FADD, dl, 3570 MVT::f32, LogOfExponent, LogOfMantissa); 3571 } 3572 } else { 3573 // No special expansion. 3574 result = DAG.getNode(ISD::FLOG, dl, 3575 getValue(I.getArgOperand(0)).getValueType(), 3576 getValue(I.getArgOperand(0))); 3577 } 3578 3579 setValue(&I, result); 3580} 3581 3582/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3583/// limited-precision mode. 3584void 3585SelectionDAGBuilder::visitLog2(const CallInst &I) { 3586 SDValue result; 3587 DebugLoc dl = getCurDebugLoc(); 3588 3589 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3590 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3591 SDValue Op = getValue(I.getArgOperand(0)); 3592 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3593 3594 // Get the exponent. 3595 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3596 3597 // Get the significand and build it into a floating-point number with 3598 // exponent of 1. 3599 SDValue X = GetSignificand(DAG, Op1, dl); 3600 3601 // Different possible minimax approximations of significand in 3602 // floating-point for various degrees of accuracy over [1,2]. 3603 if (LimitFloatPrecision <= 6) { 3604 // For floating-point precision of 6: 3605 // 3606 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3607 // 3608 // error 0.0049451742, which is more than 7 bits 3609 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3610 getF32Constant(DAG, 0xbeb08fe0)); 3611 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3612 getF32Constant(DAG, 0x40019463)); 3613 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3614 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3615 getF32Constant(DAG, 0x3fd6633d)); 3616 3617 result = DAG.getNode(ISD::FADD, dl, 3618 MVT::f32, LogOfExponent, Log2ofMantissa); 3619 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3620 // For floating-point precision of 12: 3621 // 3622 // Log2ofMantissa = 3623 // -2.51285454f + 3624 // (4.07009056f + 3625 // (-2.12067489f + 3626 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3627 // 3628 // error 0.0000876136000, which is better than 13 bits 3629 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3630 getF32Constant(DAG, 0xbda7262e)); 3631 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3632 getF32Constant(DAG, 0x3f25280b)); 3633 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3634 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3635 getF32Constant(DAG, 0x4007b923)); 3636 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3637 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3638 getF32Constant(DAG, 0x40823e2f)); 3639 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3640 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3641 getF32Constant(DAG, 0x4020d29c)); 3642 3643 result = DAG.getNode(ISD::FADD, dl, 3644 MVT::f32, LogOfExponent, Log2ofMantissa); 3645 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3646 // For floating-point precision of 18: 3647 // 3648 // Log2ofMantissa = 3649 // -3.0400495f + 3650 // (6.1129976f + 3651 // (-5.3420409f + 3652 // (3.2865683f + 3653 // (-1.2669343f + 3654 // (0.27515199f - 3655 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3656 // 3657 // error 0.0000018516, which is better than 18 bits 3658 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3659 getF32Constant(DAG, 0xbcd2769e)); 3660 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3661 getF32Constant(DAG, 0x3e8ce0b9)); 3662 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3663 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3664 getF32Constant(DAG, 0x3fa22ae7)); 3665 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3666 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3667 getF32Constant(DAG, 0x40525723)); 3668 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3669 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3670 getF32Constant(DAG, 0x40aaf200)); 3671 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3672 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3673 getF32Constant(DAG, 0x40c39dad)); 3674 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3675 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3676 getF32Constant(DAG, 0x4042902c)); 3677 3678 result = DAG.getNode(ISD::FADD, dl, 3679 MVT::f32, LogOfExponent, Log2ofMantissa); 3680 } 3681 } else { 3682 // No special expansion. 3683 result = DAG.getNode(ISD::FLOG2, dl, 3684 getValue(I.getArgOperand(0)).getValueType(), 3685 getValue(I.getArgOperand(0))); 3686 } 3687 3688 setValue(&I, result); 3689} 3690 3691/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3692/// limited-precision mode. 3693void 3694SelectionDAGBuilder::visitLog10(const CallInst &I) { 3695 SDValue result; 3696 DebugLoc dl = getCurDebugLoc(); 3697 3698 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3699 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3700 SDValue Op = getValue(I.getArgOperand(0)); 3701 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3702 3703 // Scale the exponent by log10(2) [0.30102999f]. 3704 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3705 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3706 getF32Constant(DAG, 0x3e9a209a)); 3707 3708 // Get the significand and build it into a floating-point number with 3709 // exponent of 1. 3710 SDValue X = GetSignificand(DAG, Op1, dl); 3711 3712 if (LimitFloatPrecision <= 6) { 3713 // For floating-point precision of 6: 3714 // 3715 // Log10ofMantissa = 3716 // -0.50419619f + 3717 // (0.60948995f - 0.10380950f * x) * x; 3718 // 3719 // error 0.0014886165, which is 6 bits 3720 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3721 getF32Constant(DAG, 0xbdd49a13)); 3722 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3723 getF32Constant(DAG, 0x3f1c0789)); 3724 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3725 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3726 getF32Constant(DAG, 0x3f011300)); 3727 3728 result = DAG.getNode(ISD::FADD, dl, 3729 MVT::f32, LogOfExponent, Log10ofMantissa); 3730 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3731 // For floating-point precision of 12: 3732 // 3733 // Log10ofMantissa = 3734 // -0.64831180f + 3735 // (0.91751397f + 3736 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3737 // 3738 // error 0.00019228036, which is better than 12 bits 3739 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3740 getF32Constant(DAG, 0x3d431f31)); 3741 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3742 getF32Constant(DAG, 0x3ea21fb2)); 3743 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3744 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3745 getF32Constant(DAG, 0x3f6ae232)); 3746 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3747 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3748 getF32Constant(DAG, 0x3f25f7c3)); 3749 3750 result = DAG.getNode(ISD::FADD, dl, 3751 MVT::f32, LogOfExponent, Log10ofMantissa); 3752 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3753 // For floating-point precision of 18: 3754 // 3755 // Log10ofMantissa = 3756 // -0.84299375f + 3757 // (1.5327582f + 3758 // (-1.0688956f + 3759 // (0.49102474f + 3760 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3761 // 3762 // error 0.0000037995730, which is better than 18 bits 3763 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3764 getF32Constant(DAG, 0x3c5d51ce)); 3765 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3766 getF32Constant(DAG, 0x3e00685a)); 3767 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3768 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3769 getF32Constant(DAG, 0x3efb6798)); 3770 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3771 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3772 getF32Constant(DAG, 0x3f88d192)); 3773 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3774 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3775 getF32Constant(DAG, 0x3fc4316c)); 3776 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3777 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3778 getF32Constant(DAG, 0x3f57ce70)); 3779 3780 result = DAG.getNode(ISD::FADD, dl, 3781 MVT::f32, LogOfExponent, Log10ofMantissa); 3782 } 3783 } else { 3784 // No special expansion. 3785 result = DAG.getNode(ISD::FLOG10, dl, 3786 getValue(I.getArgOperand(0)).getValueType(), 3787 getValue(I.getArgOperand(0))); 3788 } 3789 3790 setValue(&I, result); 3791} 3792 3793/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3794/// limited-precision mode. 3795void 3796SelectionDAGBuilder::visitExp2(const CallInst &I) { 3797 SDValue result; 3798 DebugLoc dl = getCurDebugLoc(); 3799 3800 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3801 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3802 SDValue Op = getValue(I.getArgOperand(0)); 3803 3804 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3805 3806 // FractionalPartOfX = x - (float)IntegerPartOfX; 3807 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3808 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3809 3810 // IntegerPartOfX <<= 23; 3811 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3812 DAG.getConstant(23, TLI.getPointerTy())); 3813 3814 if (LimitFloatPrecision <= 6) { 3815 // For floating-point precision of 6: 3816 // 3817 // TwoToFractionalPartOfX = 3818 // 0.997535578f + 3819 // (0.735607626f + 0.252464424f * x) * x; 3820 // 3821 // error 0.0144103317, which is 6 bits 3822 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3823 getF32Constant(DAG, 0x3e814304)); 3824 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3825 getF32Constant(DAG, 0x3f3c50c8)); 3826 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3827 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3828 getF32Constant(DAG, 0x3f7f5e7e)); 3829 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3830 SDValue TwoToFractionalPartOfX = 3831 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3832 3833 result = DAG.getNode(ISD::BITCAST, dl, 3834 MVT::f32, TwoToFractionalPartOfX); 3835 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3836 // For floating-point precision of 12: 3837 // 3838 // TwoToFractionalPartOfX = 3839 // 0.999892986f + 3840 // (0.696457318f + 3841 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3842 // 3843 // error 0.000107046256, which is 13 to 14 bits 3844 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3845 getF32Constant(DAG, 0x3da235e3)); 3846 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3847 getF32Constant(DAG, 0x3e65b8f3)); 3848 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3849 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3850 getF32Constant(DAG, 0x3f324b07)); 3851 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3852 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3853 getF32Constant(DAG, 0x3f7ff8fd)); 3854 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3855 SDValue TwoToFractionalPartOfX = 3856 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3857 3858 result = DAG.getNode(ISD::BITCAST, dl, 3859 MVT::f32, TwoToFractionalPartOfX); 3860 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3861 // For floating-point precision of 18: 3862 // 3863 // TwoToFractionalPartOfX = 3864 // 0.999999982f + 3865 // (0.693148872f + 3866 // (0.240227044f + 3867 // (0.554906021e-1f + 3868 // (0.961591928e-2f + 3869 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3870 // error 2.47208000*10^(-7), which is better than 18 bits 3871 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3872 getF32Constant(DAG, 0x3924b03e)); 3873 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3874 getF32Constant(DAG, 0x3ab24b87)); 3875 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3876 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3877 getF32Constant(DAG, 0x3c1d8c17)); 3878 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3879 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3880 getF32Constant(DAG, 0x3d634a1d)); 3881 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3882 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3883 getF32Constant(DAG, 0x3e75fe14)); 3884 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3885 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3886 getF32Constant(DAG, 0x3f317234)); 3887 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3888 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3889 getF32Constant(DAG, 0x3f800000)); 3890 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 3891 SDValue TwoToFractionalPartOfX = 3892 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3893 3894 result = DAG.getNode(ISD::BITCAST, dl, 3895 MVT::f32, TwoToFractionalPartOfX); 3896 } 3897 } else { 3898 // No special expansion. 3899 result = DAG.getNode(ISD::FEXP2, dl, 3900 getValue(I.getArgOperand(0)).getValueType(), 3901 getValue(I.getArgOperand(0))); 3902 } 3903 3904 setValue(&I, result); 3905} 3906 3907/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3908/// limited-precision mode with x == 10.0f. 3909void 3910SelectionDAGBuilder::visitPow(const CallInst &I) { 3911 SDValue result; 3912 const Value *Val = I.getArgOperand(0); 3913 DebugLoc dl = getCurDebugLoc(); 3914 bool IsExp10 = false; 3915 3916 if (getValue(Val).getValueType() == MVT::f32 && 3917 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 3918 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3919 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3920 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3921 APFloat Ten(10.0f); 3922 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3923 } 3924 } 3925 } 3926 3927 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3928 SDValue Op = getValue(I.getArgOperand(1)); 3929 3930 // Put the exponent in the right bit position for later addition to the 3931 // final result: 3932 // 3933 // #define LOG2OF10 3.3219281f 3934 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3935 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3936 getF32Constant(DAG, 0x40549a78)); 3937 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3938 3939 // FractionalPartOfX = x - (float)IntegerPartOfX; 3940 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3941 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3942 3943 // IntegerPartOfX <<= 23; 3944 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3945 DAG.getConstant(23, TLI.getPointerTy())); 3946 3947 if (LimitFloatPrecision <= 6) { 3948 // For floating-point precision of 6: 3949 // 3950 // twoToFractionalPartOfX = 3951 // 0.997535578f + 3952 // (0.735607626f + 0.252464424f * x) * x; 3953 // 3954 // error 0.0144103317, which is 6 bits 3955 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3956 getF32Constant(DAG, 0x3e814304)); 3957 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3958 getF32Constant(DAG, 0x3f3c50c8)); 3959 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3960 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3961 getF32Constant(DAG, 0x3f7f5e7e)); 3962 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3963 SDValue TwoToFractionalPartOfX = 3964 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3965 3966 result = DAG.getNode(ISD::BITCAST, dl, 3967 MVT::f32, TwoToFractionalPartOfX); 3968 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3969 // For floating-point precision of 12: 3970 // 3971 // TwoToFractionalPartOfX = 3972 // 0.999892986f + 3973 // (0.696457318f + 3974 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3975 // 3976 // error 0.000107046256, which is 13 to 14 bits 3977 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3978 getF32Constant(DAG, 0x3da235e3)); 3979 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3980 getF32Constant(DAG, 0x3e65b8f3)); 3981 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3982 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3983 getF32Constant(DAG, 0x3f324b07)); 3984 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3985 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3986 getF32Constant(DAG, 0x3f7ff8fd)); 3987 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3988 SDValue TwoToFractionalPartOfX = 3989 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3990 3991 result = DAG.getNode(ISD::BITCAST, dl, 3992 MVT::f32, TwoToFractionalPartOfX); 3993 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3994 // For floating-point precision of 18: 3995 // 3996 // TwoToFractionalPartOfX = 3997 // 0.999999982f + 3998 // (0.693148872f + 3999 // (0.240227044f + 4000 // (0.554906021e-1f + 4001 // (0.961591928e-2f + 4002 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4003 // error 2.47208000*10^(-7), which is better than 18 bits 4004 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4005 getF32Constant(DAG, 0x3924b03e)); 4006 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4007 getF32Constant(DAG, 0x3ab24b87)); 4008 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4009 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4010 getF32Constant(DAG, 0x3c1d8c17)); 4011 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4012 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4013 getF32Constant(DAG, 0x3d634a1d)); 4014 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4015 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4016 getF32Constant(DAG, 0x3e75fe14)); 4017 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4018 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4019 getF32Constant(DAG, 0x3f317234)); 4020 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4021 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4022 getF32Constant(DAG, 0x3f800000)); 4023 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4024 SDValue TwoToFractionalPartOfX = 4025 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4026 4027 result = DAG.getNode(ISD::BITCAST, dl, 4028 MVT::f32, TwoToFractionalPartOfX); 4029 } 4030 } else { 4031 // No special expansion. 4032 result = DAG.getNode(ISD::FPOW, dl, 4033 getValue(I.getArgOperand(0)).getValueType(), 4034 getValue(I.getArgOperand(0)), 4035 getValue(I.getArgOperand(1))); 4036 } 4037 4038 setValue(&I, result); 4039} 4040 4041 4042/// ExpandPowI - Expand a llvm.powi intrinsic. 4043static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4044 SelectionDAG &DAG) { 4045 // If RHS is a constant, we can expand this out to a multiplication tree, 4046 // otherwise we end up lowering to a call to __powidf2 (for example). When 4047 // optimizing for size, we only want to do this if the expansion would produce 4048 // a small number of multiplies, otherwise we do the full expansion. 4049 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4050 // Get the exponent as a positive value. 4051 unsigned Val = RHSC->getSExtValue(); 4052 if ((int)Val < 0) Val = -Val; 4053 4054 // powi(x, 0) -> 1.0 4055 if (Val == 0) 4056 return DAG.getConstantFP(1.0, LHS.getValueType()); 4057 4058 const Function *F = DAG.getMachineFunction().getFunction(); 4059 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4060 // If optimizing for size, don't insert too many multiplies. This 4061 // inserts up to 5 multiplies. 4062 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4063 // We use the simple binary decomposition method to generate the multiply 4064 // sequence. There are more optimal ways to do this (for example, 4065 // powi(x,15) generates one more multiply than it should), but this has 4066 // the benefit of being both really simple and much better than a libcall. 4067 SDValue Res; // Logically starts equal to 1.0 4068 SDValue CurSquare = LHS; 4069 while (Val) { 4070 if (Val & 1) { 4071 if (Res.getNode()) 4072 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4073 else 4074 Res = CurSquare; // 1.0*CurSquare. 4075 } 4076 4077 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4078 CurSquare, CurSquare); 4079 Val >>= 1; 4080 } 4081 4082 // If the original was negative, invert the result, producing 1/(x*x*x). 4083 if (RHSC->getSExtValue() < 0) 4084 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4085 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4086 return Res; 4087 } 4088 } 4089 4090 // Otherwise, expand to a libcall. 4091 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4092} 4093 4094// getTruncatedArgReg - Find underlying register used for an truncated 4095// argument. 4096static unsigned getTruncatedArgReg(const SDValue &N) { 4097 if (N.getOpcode() != ISD::TRUNCATE) 4098 return 0; 4099 4100 const SDValue &Ext = N.getOperand(0); 4101 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4102 const SDValue &CFR = Ext.getOperand(0); 4103 if (CFR.getOpcode() == ISD::CopyFromReg) 4104 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4105 else 4106 if (CFR.getOpcode() == ISD::TRUNCATE) 4107 return getTruncatedArgReg(CFR); 4108 } 4109 return 0; 4110} 4111 4112/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4113/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4114/// At the end of instruction selection, they will be inserted to the entry BB. 4115bool 4116SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4117 int64_t Offset, 4118 const SDValue &N) { 4119 const Argument *Arg = dyn_cast<Argument>(V); 4120 if (!Arg) 4121 return false; 4122 4123 MachineFunction &MF = DAG.getMachineFunction(); 4124 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4125 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4126 4127 // Ignore inlined function arguments here. 4128 DIVariable DV(Variable); 4129 if (DV.isInlinedFnArgument(MF.getFunction())) 4130 return false; 4131 4132 unsigned Reg = 0; 4133 if (Arg->hasByValAttr()) { 4134 // Byval arguments' frame index is recorded during argument lowering. 4135 // Use this info directly. 4136 Reg = TRI->getFrameRegister(MF); 4137 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 4138 // If byval argument ofset is not recorded then ignore this. 4139 if (!Offset) 4140 Reg = 0; 4141 } 4142 4143 if (N.getNode()) { 4144 if (N.getOpcode() == ISD::CopyFromReg) 4145 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4146 else 4147 Reg = getTruncatedArgReg(N); 4148 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4149 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4150 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4151 if (PR) 4152 Reg = PR; 4153 } 4154 } 4155 4156 if (!Reg) { 4157 // Check if ValueMap has reg number. 4158 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4159 if (VMI != FuncInfo.ValueMap.end()) 4160 Reg = VMI->second; 4161 } 4162 4163 if (!Reg && N.getNode()) { 4164 // Check if frame index is available. 4165 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4166 if (FrameIndexSDNode *FINode = 4167 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4168 Reg = TRI->getFrameRegister(MF); 4169 Offset = FINode->getIndex(); 4170 } 4171 } 4172 4173 if (!Reg) 4174 return false; 4175 4176 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4177 TII->get(TargetOpcode::DBG_VALUE)) 4178 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4179 FuncInfo.ArgDbgValues.push_back(&*MIB); 4180 return true; 4181} 4182 4183// VisualStudio defines setjmp as _setjmp 4184#if defined(_MSC_VER) && defined(setjmp) && \ 4185 !defined(setjmp_undefined_for_msvc) 4186# pragma push_macro("setjmp") 4187# undef setjmp 4188# define setjmp_undefined_for_msvc 4189#endif 4190 4191/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4192/// we want to emit this as a call to a named external function, return the name 4193/// otherwise lower it and return null. 4194const char * 4195SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4196 DebugLoc dl = getCurDebugLoc(); 4197 SDValue Res; 4198 4199 switch (Intrinsic) { 4200 default: 4201 // By default, turn this into a target intrinsic node. 4202 visitTargetIntrinsic(I, Intrinsic); 4203 return 0; 4204 case Intrinsic::vastart: visitVAStart(I); return 0; 4205 case Intrinsic::vaend: visitVAEnd(I); return 0; 4206 case Intrinsic::vacopy: visitVACopy(I); return 0; 4207 case Intrinsic::returnaddress: 4208 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4209 getValue(I.getArgOperand(0)))); 4210 return 0; 4211 case Intrinsic::frameaddress: 4212 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4213 getValue(I.getArgOperand(0)))); 4214 return 0; 4215 case Intrinsic::setjmp: 4216 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4217 case Intrinsic::longjmp: 4218 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4219 case Intrinsic::memcpy: { 4220 // Assert for address < 256 since we support only user defined address 4221 // spaces. 4222 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4223 < 256 && 4224 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4225 < 256 && 4226 "Unknown address space"); 4227 SDValue Op1 = getValue(I.getArgOperand(0)); 4228 SDValue Op2 = getValue(I.getArgOperand(1)); 4229 SDValue Op3 = getValue(I.getArgOperand(2)); 4230 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4231 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4232 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4233 MachinePointerInfo(I.getArgOperand(0)), 4234 MachinePointerInfo(I.getArgOperand(1)))); 4235 return 0; 4236 } 4237 case Intrinsic::memset: { 4238 // Assert for address < 256 since we support only user defined address 4239 // spaces. 4240 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4241 < 256 && 4242 "Unknown address space"); 4243 SDValue Op1 = getValue(I.getArgOperand(0)); 4244 SDValue Op2 = getValue(I.getArgOperand(1)); 4245 SDValue Op3 = getValue(I.getArgOperand(2)); 4246 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4247 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4248 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4249 MachinePointerInfo(I.getArgOperand(0)))); 4250 return 0; 4251 } 4252 case Intrinsic::memmove: { 4253 // Assert for address < 256 since we support only user defined address 4254 // spaces. 4255 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4256 < 256 && 4257 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4258 < 256 && 4259 "Unknown address space"); 4260 SDValue Op1 = getValue(I.getArgOperand(0)); 4261 SDValue Op2 = getValue(I.getArgOperand(1)); 4262 SDValue Op3 = getValue(I.getArgOperand(2)); 4263 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4264 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4265 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4266 MachinePointerInfo(I.getArgOperand(0)), 4267 MachinePointerInfo(I.getArgOperand(1)))); 4268 return 0; 4269 } 4270 case Intrinsic::dbg_declare: { 4271 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4272 MDNode *Variable = DI.getVariable(); 4273 const Value *Address = DI.getAddress(); 4274 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4275 return 0; 4276 4277 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4278 // but do not always have a corresponding SDNode built. The SDNodeOrder 4279 // absolute, but not relative, values are different depending on whether 4280 // debug info exists. 4281 ++SDNodeOrder; 4282 4283 // Check if address has undef value. 4284 if (isa<UndefValue>(Address) || 4285 (Address->use_empty() && !isa<Argument>(Address))) { 4286 DEBUG(dbgs() << "Dropping debug info for " << DI); 4287 return 0; 4288 } 4289 4290 SDValue &N = NodeMap[Address]; 4291 if (!N.getNode() && isa<Argument>(Address)) 4292 // Check unused arguments map. 4293 N = UnusedArgNodeMap[Address]; 4294 SDDbgValue *SDV; 4295 if (N.getNode()) { 4296 // Parameters are handled specially. 4297 bool isParameter = 4298 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4299 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4300 Address = BCI->getOperand(0); 4301 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4302 4303 if (isParameter && !AI) { 4304 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4305 if (FINode) 4306 // Byval parameter. We have a frame index at this point. 4307 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4308 0, dl, SDNodeOrder); 4309 else { 4310 // Address is an argument, so try to emit its dbg value using 4311 // virtual register info from the FuncInfo.ValueMap. 4312 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4313 return 0; 4314 } 4315 } else if (AI) 4316 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4317 0, dl, SDNodeOrder); 4318 else { 4319 // Can't do anything with other non-AI cases yet. 4320 DEBUG(dbgs() << "Dropping debug info for " << DI); 4321 return 0; 4322 } 4323 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4324 } else { 4325 // If Address is an argument then try to emit its dbg value using 4326 // virtual register info from the FuncInfo.ValueMap. 4327 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4328 // If variable is pinned by a alloca in dominating bb then 4329 // use StaticAllocaMap. 4330 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4331 if (AI->getParent() != DI.getParent()) { 4332 DenseMap<const AllocaInst*, int>::iterator SI = 4333 FuncInfo.StaticAllocaMap.find(AI); 4334 if (SI != FuncInfo.StaticAllocaMap.end()) { 4335 SDV = DAG.getDbgValue(Variable, SI->second, 4336 0, dl, SDNodeOrder); 4337 DAG.AddDbgValue(SDV, 0, false); 4338 return 0; 4339 } 4340 } 4341 } 4342 DEBUG(dbgs() << "Dropping debug info for " << DI); 4343 } 4344 } 4345 return 0; 4346 } 4347 case Intrinsic::dbg_value: { 4348 const DbgValueInst &DI = cast<DbgValueInst>(I); 4349 if (!DIVariable(DI.getVariable()).Verify()) 4350 return 0; 4351 4352 MDNode *Variable = DI.getVariable(); 4353 uint64_t Offset = DI.getOffset(); 4354 const Value *V = DI.getValue(); 4355 if (!V) 4356 return 0; 4357 4358 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4359 // but do not always have a corresponding SDNode built. The SDNodeOrder 4360 // absolute, but not relative, values are different depending on whether 4361 // debug info exists. 4362 ++SDNodeOrder; 4363 SDDbgValue *SDV; 4364 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4365 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4366 DAG.AddDbgValue(SDV, 0, false); 4367 } else { 4368 // Do not use getValue() in here; we don't want to generate code at 4369 // this point if it hasn't been done yet. 4370 SDValue N = NodeMap[V]; 4371 if (!N.getNode() && isa<Argument>(V)) 4372 // Check unused arguments map. 4373 N = UnusedArgNodeMap[V]; 4374 if (N.getNode()) { 4375 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4376 SDV = DAG.getDbgValue(Variable, N.getNode(), 4377 N.getResNo(), Offset, dl, SDNodeOrder); 4378 DAG.AddDbgValue(SDV, N.getNode(), false); 4379 } 4380 } else if (!V->use_empty() ) { 4381 // Do not call getValue(V) yet, as we don't want to generate code. 4382 // Remember it for later. 4383 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4384 DanglingDebugInfoMap[V] = DDI; 4385 } else { 4386 // We may expand this to cover more cases. One case where we have no 4387 // data available is an unreferenced parameter. 4388 DEBUG(dbgs() << "Dropping debug info for " << DI); 4389 } 4390 } 4391 4392 // Build a debug info table entry. 4393 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4394 V = BCI->getOperand(0); 4395 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4396 // Don't handle byval struct arguments or VLAs, for example. 4397 if (!AI) 4398 return 0; 4399 DenseMap<const AllocaInst*, int>::iterator SI = 4400 FuncInfo.StaticAllocaMap.find(AI); 4401 if (SI == FuncInfo.StaticAllocaMap.end()) 4402 return 0; // VLAs. 4403 int FI = SI->second; 4404 4405 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4406 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4407 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4408 return 0; 4409 } 4410 case Intrinsic::eh_exception: { 4411 // Insert the EXCEPTIONADDR instruction. 4412 assert(FuncInfo.MBB->isLandingPad() && 4413 "Call to eh.exception not in landing pad!"); 4414 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4415 SDValue Ops[1]; 4416 Ops[0] = DAG.getRoot(); 4417 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4418 setValue(&I, Op); 4419 DAG.setRoot(Op.getValue(1)); 4420 return 0; 4421 } 4422 4423 case Intrinsic::eh_selector: { 4424 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4425 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4426 if (CallMBB->isLandingPad()) 4427 AddCatchInfo(I, &MMI, CallMBB); 4428 else { 4429#ifndef NDEBUG 4430 FuncInfo.CatchInfoLost.insert(&I); 4431#endif 4432 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4433 unsigned Reg = TLI.getExceptionSelectorRegister(); 4434 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4435 } 4436 4437 // Insert the EHSELECTION instruction. 4438 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4439 SDValue Ops[2]; 4440 Ops[0] = getValue(I.getArgOperand(0)); 4441 Ops[1] = getRoot(); 4442 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4443 DAG.setRoot(Op.getValue(1)); 4444 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4445 return 0; 4446 } 4447 4448 case Intrinsic::eh_typeid_for: { 4449 // Find the type id for the given typeinfo. 4450 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4451 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4452 Res = DAG.getConstant(TypeID, MVT::i32); 4453 setValue(&I, Res); 4454 return 0; 4455 } 4456 4457 case Intrinsic::eh_return_i32: 4458 case Intrinsic::eh_return_i64: 4459 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4460 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4461 MVT::Other, 4462 getControlRoot(), 4463 getValue(I.getArgOperand(0)), 4464 getValue(I.getArgOperand(1)))); 4465 return 0; 4466 case Intrinsic::eh_unwind_init: 4467 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4468 return 0; 4469 case Intrinsic::eh_dwarf_cfa: { 4470 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4471 TLI.getPointerTy()); 4472 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4473 TLI.getPointerTy(), 4474 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4475 TLI.getPointerTy()), 4476 CfaArg); 4477 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4478 TLI.getPointerTy(), 4479 DAG.getConstant(0, TLI.getPointerTy())); 4480 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4481 FA, Offset)); 4482 return 0; 4483 } 4484 case Intrinsic::eh_sjlj_callsite: { 4485 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4486 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4487 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4488 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4489 4490 MMI.setCurrentCallSite(CI->getZExtValue()); 4491 return 0; 4492 } 4493 case Intrinsic::eh_sjlj_setjmp: { 4494 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4495 getValue(I.getArgOperand(0)))); 4496 return 0; 4497 } 4498 case Intrinsic::eh_sjlj_longjmp: { 4499 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4500 getRoot(), getValue(I.getArgOperand(0)))); 4501 return 0; 4502 } 4503 case Intrinsic::eh_sjlj_dispatch_setup: { 4504 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4505 getRoot(), getValue(I.getArgOperand(0)))); 4506 return 0; 4507 } 4508 4509 case Intrinsic::x86_mmx_pslli_w: 4510 case Intrinsic::x86_mmx_pslli_d: 4511 case Intrinsic::x86_mmx_pslli_q: 4512 case Intrinsic::x86_mmx_psrli_w: 4513 case Intrinsic::x86_mmx_psrli_d: 4514 case Intrinsic::x86_mmx_psrli_q: 4515 case Intrinsic::x86_mmx_psrai_w: 4516 case Intrinsic::x86_mmx_psrai_d: { 4517 SDValue ShAmt = getValue(I.getArgOperand(1)); 4518 if (isa<ConstantSDNode>(ShAmt)) { 4519 visitTargetIntrinsic(I, Intrinsic); 4520 return 0; 4521 } 4522 unsigned NewIntrinsic = 0; 4523 EVT ShAmtVT = MVT::v2i32; 4524 switch (Intrinsic) { 4525 case Intrinsic::x86_mmx_pslli_w: 4526 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4527 break; 4528 case Intrinsic::x86_mmx_pslli_d: 4529 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4530 break; 4531 case Intrinsic::x86_mmx_pslli_q: 4532 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4533 break; 4534 case Intrinsic::x86_mmx_psrli_w: 4535 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4536 break; 4537 case Intrinsic::x86_mmx_psrli_d: 4538 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4539 break; 4540 case Intrinsic::x86_mmx_psrli_q: 4541 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4542 break; 4543 case Intrinsic::x86_mmx_psrai_w: 4544 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4545 break; 4546 case Intrinsic::x86_mmx_psrai_d: 4547 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4548 break; 4549 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4550 } 4551 4552 // The vector shift intrinsics with scalars uses 32b shift amounts but 4553 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4554 // to be zero. 4555 // We must do this early because v2i32 is not a legal type. 4556 DebugLoc dl = getCurDebugLoc(); 4557 SDValue ShOps[2]; 4558 ShOps[0] = ShAmt; 4559 ShOps[1] = DAG.getConstant(0, MVT::i32); 4560 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4561 EVT DestVT = TLI.getValueType(I.getType()); 4562 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4563 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4564 DAG.getConstant(NewIntrinsic, MVT::i32), 4565 getValue(I.getArgOperand(0)), ShAmt); 4566 setValue(&I, Res); 4567 return 0; 4568 } 4569 case Intrinsic::convertff: 4570 case Intrinsic::convertfsi: 4571 case Intrinsic::convertfui: 4572 case Intrinsic::convertsif: 4573 case Intrinsic::convertuif: 4574 case Intrinsic::convertss: 4575 case Intrinsic::convertsu: 4576 case Intrinsic::convertus: 4577 case Intrinsic::convertuu: { 4578 ISD::CvtCode Code = ISD::CVT_INVALID; 4579 switch (Intrinsic) { 4580 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4581 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4582 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4583 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4584 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4585 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4586 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4587 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4588 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4589 } 4590 EVT DestVT = TLI.getValueType(I.getType()); 4591 const Value *Op1 = I.getArgOperand(0); 4592 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4593 DAG.getValueType(DestVT), 4594 DAG.getValueType(getValue(Op1).getValueType()), 4595 getValue(I.getArgOperand(1)), 4596 getValue(I.getArgOperand(2)), 4597 Code); 4598 setValue(&I, Res); 4599 return 0; 4600 } 4601 case Intrinsic::sqrt: 4602 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4603 getValue(I.getArgOperand(0)).getValueType(), 4604 getValue(I.getArgOperand(0)))); 4605 return 0; 4606 case Intrinsic::powi: 4607 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4608 getValue(I.getArgOperand(1)), DAG)); 4609 return 0; 4610 case Intrinsic::sin: 4611 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4612 getValue(I.getArgOperand(0)).getValueType(), 4613 getValue(I.getArgOperand(0)))); 4614 return 0; 4615 case Intrinsic::cos: 4616 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4617 getValue(I.getArgOperand(0)).getValueType(), 4618 getValue(I.getArgOperand(0)))); 4619 return 0; 4620 case Intrinsic::log: 4621 visitLog(I); 4622 return 0; 4623 case Intrinsic::log2: 4624 visitLog2(I); 4625 return 0; 4626 case Intrinsic::log10: 4627 visitLog10(I); 4628 return 0; 4629 case Intrinsic::exp: 4630 visitExp(I); 4631 return 0; 4632 case Intrinsic::exp2: 4633 visitExp2(I); 4634 return 0; 4635 case Intrinsic::pow: 4636 visitPow(I); 4637 return 0; 4638 case Intrinsic::convert_to_fp16: 4639 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4640 MVT::i16, getValue(I.getArgOperand(0)))); 4641 return 0; 4642 case Intrinsic::convert_from_fp16: 4643 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4644 MVT::f32, getValue(I.getArgOperand(0)))); 4645 return 0; 4646 case Intrinsic::pcmarker: { 4647 SDValue Tmp = getValue(I.getArgOperand(0)); 4648 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4649 return 0; 4650 } 4651 case Intrinsic::readcyclecounter: { 4652 SDValue Op = getRoot(); 4653 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4654 DAG.getVTList(MVT::i64, MVT::Other), 4655 &Op, 1); 4656 setValue(&I, Res); 4657 DAG.setRoot(Res.getValue(1)); 4658 return 0; 4659 } 4660 case Intrinsic::bswap: 4661 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4662 getValue(I.getArgOperand(0)).getValueType(), 4663 getValue(I.getArgOperand(0)))); 4664 return 0; 4665 case Intrinsic::cttz: { 4666 SDValue Arg = getValue(I.getArgOperand(0)); 4667 EVT Ty = Arg.getValueType(); 4668 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4669 return 0; 4670 } 4671 case Intrinsic::ctlz: { 4672 SDValue Arg = getValue(I.getArgOperand(0)); 4673 EVT Ty = Arg.getValueType(); 4674 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4675 return 0; 4676 } 4677 case Intrinsic::ctpop: { 4678 SDValue Arg = getValue(I.getArgOperand(0)); 4679 EVT Ty = Arg.getValueType(); 4680 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4681 return 0; 4682 } 4683 case Intrinsic::stacksave: { 4684 SDValue Op = getRoot(); 4685 Res = DAG.getNode(ISD::STACKSAVE, dl, 4686 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4687 setValue(&I, Res); 4688 DAG.setRoot(Res.getValue(1)); 4689 return 0; 4690 } 4691 case Intrinsic::stackrestore: { 4692 Res = getValue(I.getArgOperand(0)); 4693 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4694 return 0; 4695 } 4696 case Intrinsic::stackprotector: { 4697 // Emit code into the DAG to store the stack guard onto the stack. 4698 MachineFunction &MF = DAG.getMachineFunction(); 4699 MachineFrameInfo *MFI = MF.getFrameInfo(); 4700 EVT PtrTy = TLI.getPointerTy(); 4701 4702 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4703 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4704 4705 int FI = FuncInfo.StaticAllocaMap[Slot]; 4706 MFI->setStackProtectorIndex(FI); 4707 4708 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4709 4710 // Store the stack protector onto the stack. 4711 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4712 MachinePointerInfo::getFixedStack(FI), 4713 true, false, 0); 4714 setValue(&I, Res); 4715 DAG.setRoot(Res); 4716 return 0; 4717 } 4718 case Intrinsic::objectsize: { 4719 // If we don't know by now, we're never going to know. 4720 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4721 4722 assert(CI && "Non-constant type in __builtin_object_size?"); 4723 4724 SDValue Arg = getValue(I.getCalledValue()); 4725 EVT Ty = Arg.getValueType(); 4726 4727 if (CI->isZero()) 4728 Res = DAG.getConstant(-1ULL, Ty); 4729 else 4730 Res = DAG.getConstant(0, Ty); 4731 4732 setValue(&I, Res); 4733 return 0; 4734 } 4735 case Intrinsic::var_annotation: 4736 // Discard annotate attributes 4737 return 0; 4738 4739 case Intrinsic::init_trampoline: { 4740 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4741 4742 SDValue Ops[6]; 4743 Ops[0] = getRoot(); 4744 Ops[1] = getValue(I.getArgOperand(0)); 4745 Ops[2] = getValue(I.getArgOperand(1)); 4746 Ops[3] = getValue(I.getArgOperand(2)); 4747 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4748 Ops[5] = DAG.getSrcValue(F); 4749 4750 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4751 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4752 Ops, 6); 4753 4754 setValue(&I, Res); 4755 DAG.setRoot(Res.getValue(1)); 4756 return 0; 4757 } 4758 case Intrinsic::gcroot: 4759 if (GFI) { 4760 const Value *Alloca = I.getArgOperand(0); 4761 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4762 4763 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4764 GFI->addStackRoot(FI->getIndex(), TypeMap); 4765 } 4766 return 0; 4767 case Intrinsic::gcread: 4768 case Intrinsic::gcwrite: 4769 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4770 return 0; 4771 case Intrinsic::flt_rounds: 4772 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4773 return 0; 4774 4775 case Intrinsic::expect: { 4776 // Just replace __builtin_expect(exp, c) with EXP. 4777 setValue(&I, getValue(I.getArgOperand(0))); 4778 return 0; 4779 } 4780 4781 case Intrinsic::trap: { 4782 StringRef TrapFuncName = getTrapFunctionName(); 4783 if (TrapFuncName.empty()) { 4784 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4785 return 0; 4786 } 4787 TargetLowering::ArgListTy Args; 4788 std::pair<SDValue, SDValue> Result = 4789 TLI.LowerCallTo(getRoot(), I.getType(), 4790 false, false, false, false, 0, CallingConv::C, 4791 /*isTailCall=*/false, /*isReturnValueUsed=*/true, 4792 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 4793 Args, DAG, getCurDebugLoc()); 4794 DAG.setRoot(Result.second); 4795 return 0; 4796 } 4797 case Intrinsic::uadd_with_overflow: 4798 return implVisitAluOverflow(I, ISD::UADDO); 4799 case Intrinsic::sadd_with_overflow: 4800 return implVisitAluOverflow(I, ISD::SADDO); 4801 case Intrinsic::usub_with_overflow: 4802 return implVisitAluOverflow(I, ISD::USUBO); 4803 case Intrinsic::ssub_with_overflow: 4804 return implVisitAluOverflow(I, ISD::SSUBO); 4805 case Intrinsic::umul_with_overflow: 4806 return implVisitAluOverflow(I, ISD::UMULO); 4807 case Intrinsic::smul_with_overflow: 4808 return implVisitAluOverflow(I, ISD::SMULO); 4809 4810 case Intrinsic::prefetch: { 4811 SDValue Ops[5]; 4812 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 4813 Ops[0] = getRoot(); 4814 Ops[1] = getValue(I.getArgOperand(0)); 4815 Ops[2] = getValue(I.getArgOperand(1)); 4816 Ops[3] = getValue(I.getArgOperand(2)); 4817 Ops[4] = getValue(I.getArgOperand(3)); 4818 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 4819 DAG.getVTList(MVT::Other), 4820 &Ops[0], 5, 4821 EVT::getIntegerVT(*Context, 8), 4822 MachinePointerInfo(I.getArgOperand(0)), 4823 0, /* align */ 4824 false, /* volatile */ 4825 rw==0, /* read */ 4826 rw==1)); /* write */ 4827 return 0; 4828 } 4829 case Intrinsic::memory_barrier: { 4830 SDValue Ops[6]; 4831 Ops[0] = getRoot(); 4832 for (int x = 1; x < 6; ++x) 4833 Ops[x] = getValue(I.getArgOperand(x - 1)); 4834 4835 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4836 return 0; 4837 } 4838 case Intrinsic::atomic_cmp_swap: { 4839 SDValue Root = getRoot(); 4840 SDValue L = 4841 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4842 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 4843 Root, 4844 getValue(I.getArgOperand(0)), 4845 getValue(I.getArgOperand(1)), 4846 getValue(I.getArgOperand(2)), 4847 MachinePointerInfo(I.getArgOperand(0))); 4848 setValue(&I, L); 4849 DAG.setRoot(L.getValue(1)); 4850 return 0; 4851 } 4852 case Intrinsic::atomic_load_add: 4853 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4854 case Intrinsic::atomic_load_sub: 4855 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4856 case Intrinsic::atomic_load_or: 4857 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4858 case Intrinsic::atomic_load_xor: 4859 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4860 case Intrinsic::atomic_load_and: 4861 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4862 case Intrinsic::atomic_load_nand: 4863 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4864 case Intrinsic::atomic_load_max: 4865 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4866 case Intrinsic::atomic_load_min: 4867 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4868 case Intrinsic::atomic_load_umin: 4869 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4870 case Intrinsic::atomic_load_umax: 4871 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4872 case Intrinsic::atomic_swap: 4873 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4874 4875 case Intrinsic::invariant_start: 4876 case Intrinsic::lifetime_start: 4877 // Discard region information. 4878 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4879 return 0; 4880 case Intrinsic::invariant_end: 4881 case Intrinsic::lifetime_end: 4882 // Discard region information. 4883 return 0; 4884 } 4885} 4886 4887void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 4888 bool isTailCall, 4889 MachineBasicBlock *LandingPad) { 4890 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4891 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4892 const Type *RetTy = FTy->getReturnType(); 4893 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4894 MCSymbol *BeginLabel = 0; 4895 4896 TargetLowering::ArgListTy Args; 4897 TargetLowering::ArgListEntry Entry; 4898 Args.reserve(CS.arg_size()); 4899 4900 // Check whether the function can return without sret-demotion. 4901 SmallVector<ISD::OutputArg, 4> Outs; 4902 SmallVector<uint64_t, 4> Offsets; 4903 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4904 Outs, TLI, &Offsets); 4905 4906 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4907 DAG.getMachineFunction(), 4908 FTy->isVarArg(), Outs, 4909 FTy->getContext()); 4910 4911 SDValue DemoteStackSlot; 4912 int DemoteStackIdx = -100; 4913 4914 if (!CanLowerReturn) { 4915 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4916 FTy->getReturnType()); 4917 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4918 FTy->getReturnType()); 4919 MachineFunction &MF = DAG.getMachineFunction(); 4920 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4921 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4922 4923 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 4924 Entry.Node = DemoteStackSlot; 4925 Entry.Ty = StackSlotPtrType; 4926 Entry.isSExt = false; 4927 Entry.isZExt = false; 4928 Entry.isInReg = false; 4929 Entry.isSRet = true; 4930 Entry.isNest = false; 4931 Entry.isByVal = false; 4932 Entry.Alignment = Align; 4933 Args.push_back(Entry); 4934 RetTy = Type::getVoidTy(FTy->getContext()); 4935 } 4936 4937 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4938 i != e; ++i) { 4939 const Value *V = *i; 4940 4941 // Skip empty types 4942 if (V->getType()->isEmptyTy()) 4943 continue; 4944 4945 SDValue ArgNode = getValue(V); 4946 Entry.Node = ArgNode; Entry.Ty = V->getType(); 4947 4948 unsigned attrInd = i - CS.arg_begin() + 1; 4949 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4950 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4951 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4952 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4953 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4954 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4955 Entry.Alignment = CS.getParamAlignment(attrInd); 4956 Args.push_back(Entry); 4957 } 4958 4959 if (LandingPad) { 4960 // Insert a label before the invoke call to mark the try range. This can be 4961 // used to detect deletion of the invoke via the MachineModuleInfo. 4962 BeginLabel = MMI.getContext().CreateTempSymbol(); 4963 4964 // For SjLj, keep track of which landing pads go with which invokes 4965 // so as to maintain the ordering of pads in the LSDA. 4966 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 4967 if (CallSiteIndex) { 4968 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4969 // Now that the call site is handled, stop tracking it. 4970 MMI.setCurrentCallSite(0); 4971 } 4972 4973 // Both PendingLoads and PendingExports must be flushed here; 4974 // this call might not return. 4975 (void)getRoot(); 4976 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4977 } 4978 4979 // Check if target-independent constraints permit a tail call here. 4980 // Target-dependent constraints are checked within TLI.LowerCallTo. 4981 if (isTailCall && 4982 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4983 isTailCall = false; 4984 4985 // If there's a possibility that fast-isel has already selected some amount 4986 // of the current basic block, don't emit a tail call. 4987 if (isTailCall && EnableFastISel) 4988 isTailCall = false; 4989 4990 std::pair<SDValue,SDValue> Result = 4991 TLI.LowerCallTo(getRoot(), RetTy, 4992 CS.paramHasAttr(0, Attribute::SExt), 4993 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4994 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4995 CS.getCallingConv(), 4996 isTailCall, 4997 !CS.getInstruction()->use_empty(), 4998 Callee, Args, DAG, getCurDebugLoc()); 4999 assert((isTailCall || Result.second.getNode()) && 5000 "Non-null chain expected with non-tail call!"); 5001 assert((Result.second.getNode() || !Result.first.getNode()) && 5002 "Null value expected with tail call!"); 5003 if (Result.first.getNode()) { 5004 setValue(CS.getInstruction(), Result.first); 5005 } else if (!CanLowerReturn && Result.second.getNode()) { 5006 // The instruction result is the result of loading from the 5007 // hidden sret parameter. 5008 SmallVector<EVT, 1> PVTs; 5009 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5010 5011 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5012 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5013 EVT PtrVT = PVTs[0]; 5014 unsigned NumValues = Outs.size(); 5015 SmallVector<SDValue, 4> Values(NumValues); 5016 SmallVector<SDValue, 4> Chains(NumValues); 5017 5018 for (unsigned i = 0; i < NumValues; ++i) { 5019 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5020 DemoteStackSlot, 5021 DAG.getConstant(Offsets[i], PtrVT)); 5022 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 5023 Add, 5024 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5025 false, false, 1); 5026 Values[i] = L; 5027 Chains[i] = L.getValue(1); 5028 } 5029 5030 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5031 MVT::Other, &Chains[0], NumValues); 5032 PendingLoads.push_back(Chain); 5033 5034 // Collect the legal value parts into potentially illegal values 5035 // that correspond to the original function's return values. 5036 SmallVector<EVT, 4> RetTys; 5037 RetTy = FTy->getReturnType(); 5038 ComputeValueVTs(TLI, RetTy, RetTys); 5039 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5040 SmallVector<SDValue, 4> ReturnValues; 5041 unsigned CurReg = 0; 5042 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5043 EVT VT = RetTys[I]; 5044 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 5045 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 5046 5047 SDValue ReturnValue = 5048 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 5049 RegisterVT, VT, AssertOp); 5050 ReturnValues.push_back(ReturnValue); 5051 CurReg += NumRegs; 5052 } 5053 5054 setValue(CS.getInstruction(), 5055 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5056 DAG.getVTList(&RetTys[0], RetTys.size()), 5057 &ReturnValues[0], ReturnValues.size())); 5058 } 5059 5060 // Assign order to nodes here. If the call does not produce a result, it won't 5061 // be mapped to a SDNode and visit() will not assign it an order number. 5062 if (!Result.second.getNode()) { 5063 // As a special case, a null chain means that a tail call has been emitted and 5064 // the DAG root is already updated. 5065 HasTailCall = true; 5066 ++SDNodeOrder; 5067 AssignOrderingToNode(DAG.getRoot().getNode()); 5068 } else { 5069 DAG.setRoot(Result.second); 5070 ++SDNodeOrder; 5071 AssignOrderingToNode(Result.second.getNode()); 5072 } 5073 5074 if (LandingPad) { 5075 // Insert a label at the end of the invoke call to mark the try range. This 5076 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5077 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5078 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5079 5080 // Inform MachineModuleInfo of range. 5081 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5082 } 5083} 5084 5085/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5086/// value is equal or not-equal to zero. 5087static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5088 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5089 UI != E; ++UI) { 5090 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5091 if (IC->isEquality()) 5092 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5093 if (C->isNullValue()) 5094 continue; 5095 // Unknown instruction. 5096 return false; 5097 } 5098 return true; 5099} 5100 5101static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5102 const Type *LoadTy, 5103 SelectionDAGBuilder &Builder) { 5104 5105 // Check to see if this load can be trivially constant folded, e.g. if the 5106 // input is from a string literal. 5107 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5108 // Cast pointer to the type we really want to load. 5109 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5110 PointerType::getUnqual(LoadTy)); 5111 5112 if (const Constant *LoadCst = 5113 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5114 Builder.TD)) 5115 return Builder.getValue(LoadCst); 5116 } 5117 5118 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5119 // still constant memory, the input chain can be the entry node. 5120 SDValue Root; 5121 bool ConstantMemory = false; 5122 5123 // Do not serialize (non-volatile) loads of constant memory with anything. 5124 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5125 Root = Builder.DAG.getEntryNode(); 5126 ConstantMemory = true; 5127 } else { 5128 // Do not serialize non-volatile loads against each other. 5129 Root = Builder.DAG.getRoot(); 5130 } 5131 5132 SDValue Ptr = Builder.getValue(PtrVal); 5133 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5134 Ptr, MachinePointerInfo(PtrVal), 5135 false /*volatile*/, 5136 false /*nontemporal*/, 1 /* align=1 */); 5137 5138 if (!ConstantMemory) 5139 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5140 return LoadVal; 5141} 5142 5143 5144/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5145/// If so, return true and lower it, otherwise return false and it will be 5146/// lowered like a normal call. 5147bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5148 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5149 if (I.getNumArgOperands() != 3) 5150 return false; 5151 5152 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5153 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5154 !I.getArgOperand(2)->getType()->isIntegerTy() || 5155 !I.getType()->isIntegerTy()) 5156 return false; 5157 5158 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5159 5160 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5161 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5162 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5163 bool ActuallyDoIt = true; 5164 MVT LoadVT; 5165 const Type *LoadTy; 5166 switch (Size->getZExtValue()) { 5167 default: 5168 LoadVT = MVT::Other; 5169 LoadTy = 0; 5170 ActuallyDoIt = false; 5171 break; 5172 case 2: 5173 LoadVT = MVT::i16; 5174 LoadTy = Type::getInt16Ty(Size->getContext()); 5175 break; 5176 case 4: 5177 LoadVT = MVT::i32; 5178 LoadTy = Type::getInt32Ty(Size->getContext()); 5179 break; 5180 case 8: 5181 LoadVT = MVT::i64; 5182 LoadTy = Type::getInt64Ty(Size->getContext()); 5183 break; 5184 /* 5185 case 16: 5186 LoadVT = MVT::v4i32; 5187 LoadTy = Type::getInt32Ty(Size->getContext()); 5188 LoadTy = VectorType::get(LoadTy, 4); 5189 break; 5190 */ 5191 } 5192 5193 // This turns into unaligned loads. We only do this if the target natively 5194 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5195 // we'll only produce a small number of byte loads. 5196 5197 // Require that we can find a legal MVT, and only do this if the target 5198 // supports unaligned loads of that type. Expanding into byte loads would 5199 // bloat the code. 5200 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5201 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5202 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5203 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5204 ActuallyDoIt = false; 5205 } 5206 5207 if (ActuallyDoIt) { 5208 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5209 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5210 5211 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5212 ISD::SETNE); 5213 EVT CallVT = TLI.getValueType(I.getType(), true); 5214 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5215 return true; 5216 } 5217 } 5218 5219 5220 return false; 5221} 5222 5223 5224void SelectionDAGBuilder::visitCall(const CallInst &I) { 5225 // Handle inline assembly differently. 5226 if (isa<InlineAsm>(I.getCalledValue())) { 5227 visitInlineAsm(&I); 5228 return; 5229 } 5230 5231 // See if any floating point values are being passed to this function. This is 5232 // used to emit an undefined reference to fltused on Windows. 5233 const FunctionType *FT = 5234 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5235 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5236 if (FT->isVarArg() && 5237 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5238 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5239 const Type* T = I.getArgOperand(i)->getType(); 5240 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T); 5241 i != e; ++i) { 5242 if (!i->isFloatingPointTy()) continue; 5243 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5244 break; 5245 } 5246 } 5247 } 5248 5249 const char *RenameFn = 0; 5250 if (Function *F = I.getCalledFunction()) { 5251 if (F->isDeclaration()) { 5252 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5253 if (unsigned IID = II->getIntrinsicID(F)) { 5254 RenameFn = visitIntrinsicCall(I, IID); 5255 if (!RenameFn) 5256 return; 5257 } 5258 } 5259 if (unsigned IID = F->getIntrinsicID()) { 5260 RenameFn = visitIntrinsicCall(I, IID); 5261 if (!RenameFn) 5262 return; 5263 } 5264 } 5265 5266 // Check for well-known libc/libm calls. If the function is internal, it 5267 // can't be a library call. 5268 if (!F->hasLocalLinkage() && F->hasName()) { 5269 StringRef Name = F->getName(); 5270 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5271 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5272 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5273 I.getType() == I.getArgOperand(0)->getType() && 5274 I.getType() == I.getArgOperand(1)->getType()) { 5275 SDValue LHS = getValue(I.getArgOperand(0)); 5276 SDValue RHS = getValue(I.getArgOperand(1)); 5277 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5278 LHS.getValueType(), LHS, RHS)); 5279 return; 5280 } 5281 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5282 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5283 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5284 I.getType() == I.getArgOperand(0)->getType()) { 5285 SDValue Tmp = getValue(I.getArgOperand(0)); 5286 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5287 Tmp.getValueType(), Tmp)); 5288 return; 5289 } 5290 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5291 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5292 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5293 I.getType() == I.getArgOperand(0)->getType() && 5294 I.onlyReadsMemory()) { 5295 SDValue Tmp = getValue(I.getArgOperand(0)); 5296 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5297 Tmp.getValueType(), Tmp)); 5298 return; 5299 } 5300 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5301 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5302 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5303 I.getType() == I.getArgOperand(0)->getType() && 5304 I.onlyReadsMemory()) { 5305 SDValue Tmp = getValue(I.getArgOperand(0)); 5306 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5307 Tmp.getValueType(), Tmp)); 5308 return; 5309 } 5310 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5311 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5312 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5313 I.getType() == I.getArgOperand(0)->getType() && 5314 I.onlyReadsMemory()) { 5315 SDValue Tmp = getValue(I.getArgOperand(0)); 5316 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5317 Tmp.getValueType(), Tmp)); 5318 return; 5319 } 5320 } else if (Name == "memcmp") { 5321 if (visitMemCmpCall(I)) 5322 return; 5323 } 5324 } 5325 } 5326 5327 SDValue Callee; 5328 if (!RenameFn) 5329 Callee = getValue(I.getCalledValue()); 5330 else 5331 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5332 5333 // Check if we can potentially perform a tail call. More detailed checking is 5334 // be done within LowerCallTo, after more information about the call is known. 5335 LowerCallTo(&I, Callee, I.isTailCall()); 5336} 5337 5338namespace { 5339 5340/// AsmOperandInfo - This contains information for each constraint that we are 5341/// lowering. 5342class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5343public: 5344 /// CallOperand - If this is the result output operand or a clobber 5345 /// this is null, otherwise it is the incoming operand to the CallInst. 5346 /// This gets modified as the asm is processed. 5347 SDValue CallOperand; 5348 5349 /// AssignedRegs - If this is a register or register class operand, this 5350 /// contains the set of register corresponding to the operand. 5351 RegsForValue AssignedRegs; 5352 5353 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5354 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5355 } 5356 5357 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5358 /// busy in OutputRegs/InputRegs. 5359 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5360 std::set<unsigned> &OutputRegs, 5361 std::set<unsigned> &InputRegs, 5362 const TargetRegisterInfo &TRI) const { 5363 if (isOutReg) { 5364 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5365 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5366 } 5367 if (isInReg) { 5368 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5369 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5370 } 5371 } 5372 5373 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5374 /// corresponds to. If there is no Value* for this operand, it returns 5375 /// MVT::Other. 5376 EVT getCallOperandValEVT(LLVMContext &Context, 5377 const TargetLowering &TLI, 5378 const TargetData *TD) const { 5379 if (CallOperandVal == 0) return MVT::Other; 5380 5381 if (isa<BasicBlock>(CallOperandVal)) 5382 return TLI.getPointerTy(); 5383 5384 const llvm::Type *OpTy = CallOperandVal->getType(); 5385 5386 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5387 // If this is an indirect operand, the operand is a pointer to the 5388 // accessed type. 5389 if (isIndirect) { 5390 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5391 if (!PtrTy) 5392 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5393 OpTy = PtrTy->getElementType(); 5394 } 5395 5396 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5397 if (const StructType *STy = dyn_cast<StructType>(OpTy)) 5398 if (STy->getNumElements() == 1) 5399 OpTy = STy->getElementType(0); 5400 5401 // If OpTy is not a single value, it may be a struct/union that we 5402 // can tile with integers. 5403 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5404 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5405 switch (BitSize) { 5406 default: break; 5407 case 1: 5408 case 8: 5409 case 16: 5410 case 32: 5411 case 64: 5412 case 128: 5413 OpTy = IntegerType::get(Context, BitSize); 5414 break; 5415 } 5416 } 5417 5418 return TLI.getValueType(OpTy, true); 5419 } 5420 5421private: 5422 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5423 /// specified set. 5424 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5425 const TargetRegisterInfo &TRI) { 5426 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5427 Regs.insert(Reg); 5428 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5429 for (; *Aliases; ++Aliases) 5430 Regs.insert(*Aliases); 5431 } 5432}; 5433 5434typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5435 5436} // end anonymous namespace 5437 5438/// GetRegistersForValue - Assign registers (virtual or physical) for the 5439/// specified operand. We prefer to assign virtual registers, to allow the 5440/// register allocator to handle the assignment process. However, if the asm 5441/// uses features that we can't model on machineinstrs, we have SDISel do the 5442/// allocation. This produces generally horrible, but correct, code. 5443/// 5444/// OpInfo describes the operand. 5445/// Input and OutputRegs are the set of already allocated physical registers. 5446/// 5447static void GetRegistersForValue(SelectionDAG &DAG, 5448 const TargetLowering &TLI, 5449 DebugLoc DL, 5450 SDISelAsmOperandInfo &OpInfo, 5451 std::set<unsigned> &OutputRegs, 5452 std::set<unsigned> &InputRegs) { 5453 LLVMContext &Context = *DAG.getContext(); 5454 5455 // Compute whether this value requires an input register, an output register, 5456 // or both. 5457 bool isOutReg = false; 5458 bool isInReg = false; 5459 switch (OpInfo.Type) { 5460 case InlineAsm::isOutput: 5461 isOutReg = true; 5462 5463 // If there is an input constraint that matches this, we need to reserve 5464 // the input register so no other inputs allocate to it. 5465 isInReg = OpInfo.hasMatchingInput(); 5466 break; 5467 case InlineAsm::isInput: 5468 isInReg = true; 5469 isOutReg = false; 5470 break; 5471 case InlineAsm::isClobber: 5472 isOutReg = true; 5473 isInReg = true; 5474 break; 5475 } 5476 5477 5478 MachineFunction &MF = DAG.getMachineFunction(); 5479 SmallVector<unsigned, 4> Regs; 5480 5481 // If this is a constraint for a single physreg, or a constraint for a 5482 // register class, find it. 5483 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5484 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5485 OpInfo.ConstraintVT); 5486 5487 unsigned NumRegs = 1; 5488 if (OpInfo.ConstraintVT != MVT::Other) { 5489 // If this is a FP input in an integer register (or visa versa) insert a bit 5490 // cast of the input value. More generally, handle any case where the input 5491 // value disagrees with the register class we plan to stick this in. 5492 if (OpInfo.Type == InlineAsm::isInput && 5493 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5494 // Try to convert to the first EVT that the reg class contains. If the 5495 // types are identical size, use a bitcast to convert (e.g. two differing 5496 // vector types). 5497 EVT RegVT = *PhysReg.second->vt_begin(); 5498 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5499 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5500 RegVT, OpInfo.CallOperand); 5501 OpInfo.ConstraintVT = RegVT; 5502 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5503 // If the input is a FP value and we want it in FP registers, do a 5504 // bitcast to the corresponding integer type. This turns an f64 value 5505 // into i64, which can be passed with two i32 values on a 32-bit 5506 // machine. 5507 RegVT = EVT::getIntegerVT(Context, 5508 OpInfo.ConstraintVT.getSizeInBits()); 5509 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5510 RegVT, OpInfo.CallOperand); 5511 OpInfo.ConstraintVT = RegVT; 5512 } 5513 } 5514 5515 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5516 } 5517 5518 EVT RegVT; 5519 EVT ValueVT = OpInfo.ConstraintVT; 5520 5521 // If this is a constraint for a specific physical register, like {r17}, 5522 // assign it now. 5523 if (unsigned AssignedReg = PhysReg.first) { 5524 const TargetRegisterClass *RC = PhysReg.second; 5525 if (OpInfo.ConstraintVT == MVT::Other) 5526 ValueVT = *RC->vt_begin(); 5527 5528 // Get the actual register value type. This is important, because the user 5529 // may have asked for (e.g.) the AX register in i32 type. We need to 5530 // remember that AX is actually i16 to get the right extension. 5531 RegVT = *RC->vt_begin(); 5532 5533 // This is a explicit reference to a physical register. 5534 Regs.push_back(AssignedReg); 5535 5536 // If this is an expanded reference, add the rest of the regs to Regs. 5537 if (NumRegs != 1) { 5538 TargetRegisterClass::iterator I = RC->begin(); 5539 for (; *I != AssignedReg; ++I) 5540 assert(I != RC->end() && "Didn't find reg!"); 5541 5542 // Already added the first reg. 5543 --NumRegs; ++I; 5544 for (; NumRegs; --NumRegs, ++I) { 5545 assert(I != RC->end() && "Ran out of registers to allocate!"); 5546 Regs.push_back(*I); 5547 } 5548 } 5549 5550 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5551 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5552 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5553 return; 5554 } 5555 5556 // Otherwise, if this was a reference to an LLVM register class, create vregs 5557 // for this reference. 5558 if (const TargetRegisterClass *RC = PhysReg.second) { 5559 RegVT = *RC->vt_begin(); 5560 if (OpInfo.ConstraintVT == MVT::Other) 5561 ValueVT = RegVT; 5562 5563 // Create the appropriate number of virtual registers. 5564 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5565 for (; NumRegs; --NumRegs) 5566 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5567 5568 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5569 return; 5570 } 5571 5572 // Otherwise, we couldn't allocate enough registers for this. 5573} 5574 5575/// visitInlineAsm - Handle a call to an InlineAsm object. 5576/// 5577void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5578 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5579 5580 /// ConstraintOperands - Information about all of the constraints. 5581 SDISelAsmOperandInfoVector ConstraintOperands; 5582 5583 std::set<unsigned> OutputRegs, InputRegs; 5584 5585 TargetLowering::AsmOperandInfoVector 5586 TargetConstraints = TLI.ParseConstraints(CS); 5587 5588 bool hasMemory = false; 5589 5590 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5591 unsigned ResNo = 0; // ResNo - The result number of the next output. 5592 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5593 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5594 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5595 5596 EVT OpVT = MVT::Other; 5597 5598 // Compute the value type for each operand. 5599 switch (OpInfo.Type) { 5600 case InlineAsm::isOutput: 5601 // Indirect outputs just consume an argument. 5602 if (OpInfo.isIndirect) { 5603 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5604 break; 5605 } 5606 5607 // The return value of the call is this value. As such, there is no 5608 // corresponding argument. 5609 assert(!CS.getType()->isVoidTy() && 5610 "Bad inline asm!"); 5611 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5612 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5613 } else { 5614 assert(ResNo == 0 && "Asm only has one result!"); 5615 OpVT = TLI.getValueType(CS.getType()); 5616 } 5617 ++ResNo; 5618 break; 5619 case InlineAsm::isInput: 5620 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5621 break; 5622 case InlineAsm::isClobber: 5623 // Nothing to do. 5624 break; 5625 } 5626 5627 // If this is an input or an indirect output, process the call argument. 5628 // BasicBlocks are labels, currently appearing only in asm's. 5629 if (OpInfo.CallOperandVal) { 5630 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5631 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5632 } else { 5633 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5634 } 5635 5636 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5637 } 5638 5639 OpInfo.ConstraintVT = OpVT; 5640 5641 // Indirect operand accesses access memory. 5642 if (OpInfo.isIndirect) 5643 hasMemory = true; 5644 else { 5645 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5646 TargetLowering::ConstraintType 5647 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5648 if (CType == TargetLowering::C_Memory) { 5649 hasMemory = true; 5650 break; 5651 } 5652 } 5653 } 5654 } 5655 5656 SDValue Chain, Flag; 5657 5658 // We won't need to flush pending loads if this asm doesn't touch 5659 // memory and is nonvolatile. 5660 if (hasMemory || IA->hasSideEffects()) 5661 Chain = getRoot(); 5662 else 5663 Chain = DAG.getRoot(); 5664 5665 // Second pass over the constraints: compute which constraint option to use 5666 // and assign registers to constraints that want a specific physreg. 5667 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5668 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5669 5670 // If this is an output operand with a matching input operand, look up the 5671 // matching input. If their types mismatch, e.g. one is an integer, the 5672 // other is floating point, or their sizes are different, flag it as an 5673 // error. 5674 if (OpInfo.hasMatchingInput()) { 5675 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5676 5677 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5678 if ((OpInfo.ConstraintVT.isInteger() != 5679 Input.ConstraintVT.isInteger()) || 5680 (OpInfo.ConstraintVT.getSizeInBits() != 5681 Input.ConstraintVT.getSizeInBits())) { 5682 report_fatal_error("Unsupported asm: input constraint" 5683 " with a matching output constraint of" 5684 " incompatible type!"); 5685 } 5686 Input.ConstraintVT = OpInfo.ConstraintVT; 5687 } 5688 } 5689 5690 // Compute the constraint code and ConstraintType to use. 5691 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5692 5693 // If this is a memory input, and if the operand is not indirect, do what we 5694 // need to to provide an address for the memory input. 5695 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5696 !OpInfo.isIndirect) { 5697 assert((OpInfo.isMultipleAlternative || 5698 (OpInfo.Type == InlineAsm::isInput)) && 5699 "Can only indirectify direct input operands!"); 5700 5701 // Memory operands really want the address of the value. If we don't have 5702 // an indirect input, put it in the constpool if we can, otherwise spill 5703 // it to a stack slot. 5704 // TODO: This isn't quite right. We need to handle these according to 5705 // the addressing mode that the constraint wants. Also, this may take 5706 // an additional register for the computation and we don't want that 5707 // either. 5708 5709 // If the operand is a float, integer, or vector constant, spill to a 5710 // constant pool entry to get its address. 5711 const Value *OpVal = OpInfo.CallOperandVal; 5712 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5713 isa<ConstantVector>(OpVal)) { 5714 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5715 TLI.getPointerTy()); 5716 } else { 5717 // Otherwise, create a stack slot and emit a store to it before the 5718 // asm. 5719 const Type *Ty = OpVal->getType(); 5720 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5721 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5722 MachineFunction &MF = DAG.getMachineFunction(); 5723 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5724 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5725 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5726 OpInfo.CallOperand, StackSlot, 5727 MachinePointerInfo::getFixedStack(SSFI), 5728 false, false, 0); 5729 OpInfo.CallOperand = StackSlot; 5730 } 5731 5732 // There is no longer a Value* corresponding to this operand. 5733 OpInfo.CallOperandVal = 0; 5734 5735 // It is now an indirect operand. 5736 OpInfo.isIndirect = true; 5737 } 5738 5739 // If this constraint is for a specific register, allocate it before 5740 // anything else. 5741 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5742 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5743 InputRegs); 5744 } 5745 5746 // Second pass - Loop over all of the operands, assigning virtual or physregs 5747 // to register class operands. 5748 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5749 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5750 5751 // C_Register operands have already been allocated, Other/Memory don't need 5752 // to be. 5753 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5754 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5755 InputRegs); 5756 } 5757 5758 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5759 std::vector<SDValue> AsmNodeOperands; 5760 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5761 AsmNodeOperands.push_back( 5762 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5763 TLI.getPointerTy())); 5764 5765 // If we have a !srcloc metadata node associated with it, we want to attach 5766 // this to the ultimately generated inline asm machineinstr. To do this, we 5767 // pass in the third operand as this (potentially null) inline asm MDNode. 5768 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5769 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5770 5771 // Remember the HasSideEffect and AlignStack bits as operand 3. 5772 unsigned ExtraInfo = 0; 5773 if (IA->hasSideEffects()) 5774 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 5775 if (IA->isAlignStack()) 5776 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 5777 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 5778 TLI.getPointerTy())); 5779 5780 // Loop over all of the inputs, copying the operand values into the 5781 // appropriate registers and processing the output regs. 5782 RegsForValue RetValRegs; 5783 5784 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5785 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5786 5787 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5788 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5789 5790 switch (OpInfo.Type) { 5791 case InlineAsm::isOutput: { 5792 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5793 OpInfo.ConstraintType != TargetLowering::C_Register) { 5794 // Memory output, or 'other' output (e.g. 'X' constraint). 5795 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5796 5797 // Add information to the INLINEASM node to know about this output. 5798 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5799 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5800 TLI.getPointerTy())); 5801 AsmNodeOperands.push_back(OpInfo.CallOperand); 5802 break; 5803 } 5804 5805 // Otherwise, this is a register or register class output. 5806 5807 // Copy the output from the appropriate register. Find a register that 5808 // we can use. 5809 if (OpInfo.AssignedRegs.Regs.empty()) 5810 report_fatal_error("Couldn't allocate output reg for constraint '" + 5811 Twine(OpInfo.ConstraintCode) + "'!"); 5812 5813 // If this is an indirect operand, store through the pointer after the 5814 // asm. 5815 if (OpInfo.isIndirect) { 5816 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5817 OpInfo.CallOperandVal)); 5818 } else { 5819 // This is the result value of the call. 5820 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5821 // Concatenate this output onto the outputs list. 5822 RetValRegs.append(OpInfo.AssignedRegs); 5823 } 5824 5825 // Add information to the INLINEASM node to know that this register is 5826 // set. 5827 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5828 InlineAsm::Kind_RegDefEarlyClobber : 5829 InlineAsm::Kind_RegDef, 5830 false, 5831 0, 5832 DAG, 5833 AsmNodeOperands); 5834 break; 5835 } 5836 case InlineAsm::isInput: { 5837 SDValue InOperandVal = OpInfo.CallOperand; 5838 5839 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5840 // If this is required to match an output register we have already set, 5841 // just use its register. 5842 unsigned OperandNo = OpInfo.getMatchedOperand(); 5843 5844 // Scan until we find the definition we already emitted of this operand. 5845 // When we find it, create a RegsForValue operand. 5846 unsigned CurOp = InlineAsm::Op_FirstOperand; 5847 for (; OperandNo; --OperandNo) { 5848 // Advance to the next operand. 5849 unsigned OpFlag = 5850 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5851 assert((InlineAsm::isRegDefKind(OpFlag) || 5852 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5853 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5854 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5855 } 5856 5857 unsigned OpFlag = 5858 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5859 if (InlineAsm::isRegDefKind(OpFlag) || 5860 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5861 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5862 if (OpInfo.isIndirect) { 5863 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5864 LLVMContext &Ctx = *DAG.getContext(); 5865 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5866 " don't know how to handle tied " 5867 "indirect register inputs"); 5868 } 5869 5870 RegsForValue MatchedRegs; 5871 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5872 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5873 MatchedRegs.RegVTs.push_back(RegVT); 5874 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5875 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5876 i != e; ++i) 5877 MatchedRegs.Regs.push_back 5878 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5879 5880 // Use the produced MatchedRegs object to 5881 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5882 Chain, &Flag); 5883 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 5884 true, OpInfo.getMatchedOperand(), 5885 DAG, AsmNodeOperands); 5886 break; 5887 } 5888 5889 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 5890 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 5891 "Unexpected number of operands"); 5892 // Add information to the INLINEASM node to know about this input. 5893 // See InlineAsm.h isUseOperandTiedToDef. 5894 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 5895 OpInfo.getMatchedOperand()); 5896 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5897 TLI.getPointerTy())); 5898 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5899 break; 5900 } 5901 5902 // Treat indirect 'X' constraint as memory. 5903 if (OpInfo.ConstraintType == TargetLowering::C_Other && 5904 OpInfo.isIndirect) 5905 OpInfo.ConstraintType = TargetLowering::C_Memory; 5906 5907 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5908 std::vector<SDValue> Ops; 5909 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 5910 Ops, DAG); 5911 if (Ops.empty()) 5912 report_fatal_error("Invalid operand for inline asm constraint '" + 5913 Twine(OpInfo.ConstraintCode) + "'!"); 5914 5915 // Add information to the INLINEASM node to know about this input. 5916 unsigned ResOpType = 5917 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 5918 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5919 TLI.getPointerTy())); 5920 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5921 break; 5922 } 5923 5924 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5925 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5926 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5927 "Memory operands expect pointer values"); 5928 5929 // Add information to the INLINEASM node to know about this input. 5930 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5931 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5932 TLI.getPointerTy())); 5933 AsmNodeOperands.push_back(InOperandVal); 5934 break; 5935 } 5936 5937 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5938 OpInfo.ConstraintType == TargetLowering::C_Register) && 5939 "Unknown constraint type!"); 5940 assert(!OpInfo.isIndirect && 5941 "Don't know how to handle indirect register inputs yet!"); 5942 5943 // Copy the input into the appropriate registers. 5944 if (OpInfo.AssignedRegs.Regs.empty() || 5945 !OpInfo.AssignedRegs.areValueTypesLegal(TLI)) 5946 report_fatal_error("Couldn't allocate input reg for constraint '" + 5947 Twine(OpInfo.ConstraintCode) + "'!"); 5948 5949 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5950 Chain, &Flag); 5951 5952 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 5953 DAG, AsmNodeOperands); 5954 break; 5955 } 5956 case InlineAsm::isClobber: { 5957 // Add the clobbered value to the operand list, so that the register 5958 // allocator is aware that the physreg got clobbered. 5959 if (!OpInfo.AssignedRegs.Regs.empty()) 5960 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 5961 false, 0, DAG, 5962 AsmNodeOperands); 5963 break; 5964 } 5965 } 5966 } 5967 5968 // Finish up input operands. Set the input chain and add the flag last. 5969 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 5970 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5971 5972 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5973 DAG.getVTList(MVT::Other, MVT::Glue), 5974 &AsmNodeOperands[0], AsmNodeOperands.size()); 5975 Flag = Chain.getValue(1); 5976 5977 // If this asm returns a register value, copy the result from that register 5978 // and set it as the value of the call. 5979 if (!RetValRegs.Regs.empty()) { 5980 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5981 Chain, &Flag); 5982 5983 // FIXME: Why don't we do this for inline asms with MRVs? 5984 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5985 EVT ResultType = TLI.getValueType(CS.getType()); 5986 5987 // If any of the results of the inline asm is a vector, it may have the 5988 // wrong width/num elts. This can happen for register classes that can 5989 // contain multiple different value types. The preg or vreg allocated may 5990 // not have the same VT as was expected. Convert it to the right type 5991 // with bit_convert. 5992 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5993 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 5994 ResultType, Val); 5995 5996 } else if (ResultType != Val.getValueType() && 5997 ResultType.isInteger() && Val.getValueType().isInteger()) { 5998 // If a result value was tied to an input value, the computed result may 5999 // have a wider width than the expected result. Extract the relevant 6000 // portion. 6001 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6002 } 6003 6004 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6005 } 6006 6007 setValue(CS.getInstruction(), Val); 6008 // Don't need to use this as a chain in this case. 6009 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6010 return; 6011 } 6012 6013 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6014 6015 // Process indirect outputs, first output all of the flagged copies out of 6016 // physregs. 6017 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6018 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6019 const Value *Ptr = IndirectStoresToEmit[i].second; 6020 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6021 Chain, &Flag); 6022 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6023 } 6024 6025 // Emit the non-flagged stores from the physregs. 6026 SmallVector<SDValue, 8> OutChains; 6027 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6028 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6029 StoresToEmit[i].first, 6030 getValue(StoresToEmit[i].second), 6031 MachinePointerInfo(StoresToEmit[i].second), 6032 false, false, 0); 6033 OutChains.push_back(Val); 6034 } 6035 6036 if (!OutChains.empty()) 6037 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6038 &OutChains[0], OutChains.size()); 6039 6040 DAG.setRoot(Chain); 6041} 6042 6043void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6044 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6045 MVT::Other, getRoot(), 6046 getValue(I.getArgOperand(0)), 6047 DAG.getSrcValue(I.getArgOperand(0)))); 6048} 6049 6050void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6051 const TargetData &TD = *TLI.getTargetData(); 6052 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6053 getRoot(), getValue(I.getOperand(0)), 6054 DAG.getSrcValue(I.getOperand(0)), 6055 TD.getABITypeAlignment(I.getType())); 6056 setValue(&I, V); 6057 DAG.setRoot(V.getValue(1)); 6058} 6059 6060void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6061 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6062 MVT::Other, getRoot(), 6063 getValue(I.getArgOperand(0)), 6064 DAG.getSrcValue(I.getArgOperand(0)))); 6065} 6066 6067void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6068 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6069 MVT::Other, getRoot(), 6070 getValue(I.getArgOperand(0)), 6071 getValue(I.getArgOperand(1)), 6072 DAG.getSrcValue(I.getArgOperand(0)), 6073 DAG.getSrcValue(I.getArgOperand(1)))); 6074} 6075 6076/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6077/// implementation, which just calls LowerCall. 6078/// FIXME: When all targets are 6079/// migrated to using LowerCall, this hook should be integrated into SDISel. 6080std::pair<SDValue, SDValue> 6081TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 6082 bool RetSExt, bool RetZExt, bool isVarArg, 6083 bool isInreg, unsigned NumFixedArgs, 6084 CallingConv::ID CallConv, bool isTailCall, 6085 bool isReturnValueUsed, 6086 SDValue Callee, 6087 ArgListTy &Args, SelectionDAG &DAG, 6088 DebugLoc dl) const { 6089 // Handle all of the outgoing arguments. 6090 SmallVector<ISD::OutputArg, 32> Outs; 6091 SmallVector<SDValue, 32> OutVals; 6092 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6093 SmallVector<EVT, 4> ValueVTs; 6094 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6095 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6096 Value != NumValues; ++Value) { 6097 EVT VT = ValueVTs[Value]; 6098 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6099 SDValue Op = SDValue(Args[i].Node.getNode(), 6100 Args[i].Node.getResNo() + Value); 6101 ISD::ArgFlagsTy Flags; 6102 unsigned OriginalAlignment = 6103 getTargetData()->getABITypeAlignment(ArgTy); 6104 6105 if (Args[i].isZExt) 6106 Flags.setZExt(); 6107 if (Args[i].isSExt) 6108 Flags.setSExt(); 6109 if (Args[i].isInReg) 6110 Flags.setInReg(); 6111 if (Args[i].isSRet) 6112 Flags.setSRet(); 6113 if (Args[i].isByVal) { 6114 Flags.setByVal(); 6115 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 6116 const Type *ElementTy = Ty->getElementType(); 6117 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6118 // For ByVal, alignment should come from FE. BE will guess if this 6119 // info is not there but there are cases it cannot get right. 6120 unsigned FrameAlign; 6121 if (Args[i].Alignment) 6122 FrameAlign = Args[i].Alignment; 6123 else 6124 FrameAlign = getByValTypeAlignment(ElementTy); 6125 Flags.setByValAlign(FrameAlign); 6126 } 6127 if (Args[i].isNest) 6128 Flags.setNest(); 6129 Flags.setOrigAlign(OriginalAlignment); 6130 6131 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6132 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6133 SmallVector<SDValue, 4> Parts(NumParts); 6134 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6135 6136 if (Args[i].isSExt) 6137 ExtendKind = ISD::SIGN_EXTEND; 6138 else if (Args[i].isZExt) 6139 ExtendKind = ISD::ZERO_EXTEND; 6140 6141 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6142 PartVT, ExtendKind); 6143 6144 for (unsigned j = 0; j != NumParts; ++j) { 6145 // if it isn't first piece, alignment must be 1 6146 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6147 i < NumFixedArgs); 6148 if (NumParts > 1 && j == 0) 6149 MyFlags.Flags.setSplit(); 6150 else if (j != 0) 6151 MyFlags.Flags.setOrigAlign(1); 6152 6153 Outs.push_back(MyFlags); 6154 OutVals.push_back(Parts[j]); 6155 } 6156 } 6157 } 6158 6159 // Handle the incoming return values from the call. 6160 SmallVector<ISD::InputArg, 32> Ins; 6161 SmallVector<EVT, 4> RetTys; 6162 ComputeValueVTs(*this, RetTy, RetTys); 6163 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6164 EVT VT = RetTys[I]; 6165 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6166 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6167 for (unsigned i = 0; i != NumRegs; ++i) { 6168 ISD::InputArg MyFlags; 6169 MyFlags.VT = RegisterVT.getSimpleVT(); 6170 MyFlags.Used = isReturnValueUsed; 6171 if (RetSExt) 6172 MyFlags.Flags.setSExt(); 6173 if (RetZExt) 6174 MyFlags.Flags.setZExt(); 6175 if (isInreg) 6176 MyFlags.Flags.setInReg(); 6177 Ins.push_back(MyFlags); 6178 } 6179 } 6180 6181 SmallVector<SDValue, 4> InVals; 6182 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6183 Outs, OutVals, Ins, dl, DAG, InVals); 6184 6185 // Verify that the target's LowerCall behaved as expected. 6186 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6187 "LowerCall didn't return a valid chain!"); 6188 assert((!isTailCall || InVals.empty()) && 6189 "LowerCall emitted a return value for a tail call!"); 6190 assert((isTailCall || InVals.size() == Ins.size()) && 6191 "LowerCall didn't emit the correct number of values!"); 6192 6193 // For a tail call, the return value is merely live-out and there aren't 6194 // any nodes in the DAG representing it. Return a special value to 6195 // indicate that a tail call has been emitted and no more Instructions 6196 // should be processed in the current block. 6197 if (isTailCall) { 6198 DAG.setRoot(Chain); 6199 return std::make_pair(SDValue(), SDValue()); 6200 } 6201 6202 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6203 assert(InVals[i].getNode() && 6204 "LowerCall emitted a null value!"); 6205 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6206 "LowerCall emitted a value with the wrong type!"); 6207 }); 6208 6209 // Collect the legal value parts into potentially illegal values 6210 // that correspond to the original function's return values. 6211 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6212 if (RetSExt) 6213 AssertOp = ISD::AssertSext; 6214 else if (RetZExt) 6215 AssertOp = ISD::AssertZext; 6216 SmallVector<SDValue, 4> ReturnValues; 6217 unsigned CurReg = 0; 6218 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6219 EVT VT = RetTys[I]; 6220 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6221 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6222 6223 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6224 NumRegs, RegisterVT, VT, 6225 AssertOp)); 6226 CurReg += NumRegs; 6227 } 6228 6229 // For a function returning void, there is no return value. We can't create 6230 // such a node, so we just return a null return value in that case. In 6231 // that case, nothing will actually look at the value. 6232 if (ReturnValues.empty()) 6233 return std::make_pair(SDValue(), Chain); 6234 6235 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6236 DAG.getVTList(&RetTys[0], RetTys.size()), 6237 &ReturnValues[0], ReturnValues.size()); 6238 return std::make_pair(Res, Chain); 6239} 6240 6241void TargetLowering::LowerOperationWrapper(SDNode *N, 6242 SmallVectorImpl<SDValue> &Results, 6243 SelectionDAG &DAG) const { 6244 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6245 if (Res.getNode()) 6246 Results.push_back(Res); 6247} 6248 6249SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6250 llvm_unreachable("LowerOperation not implemented for this target!"); 6251 return SDValue(); 6252} 6253 6254void 6255SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6256 SDValue Op = getNonRegisterValue(V); 6257 assert((Op.getOpcode() != ISD::CopyFromReg || 6258 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6259 "Copy from a reg to the same reg!"); 6260 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6261 6262 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6263 SDValue Chain = DAG.getEntryNode(); 6264 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6265 PendingExports.push_back(Chain); 6266} 6267 6268#include "llvm/CodeGen/SelectionDAGISel.h" 6269 6270/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6271/// entry block, return true. This includes arguments used by switches, since 6272/// the switch may expand into multiple basic blocks. 6273static bool isOnlyUsedInEntryBlock(const Argument *A) { 6274 // With FastISel active, we may be splitting blocks, so force creation 6275 // of virtual registers for all non-dead arguments. 6276 if (EnableFastISel) 6277 return A->use_empty(); 6278 6279 const BasicBlock *Entry = A->getParent()->begin(); 6280 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6281 UI != E; ++UI) { 6282 const User *U = *UI; 6283 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6284 return false; // Use not in entry block. 6285 } 6286 return true; 6287} 6288 6289void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6290 // If this is the entry block, emit arguments. 6291 const Function &F = *LLVMBB->getParent(); 6292 SelectionDAG &DAG = SDB->DAG; 6293 DebugLoc dl = SDB->getCurDebugLoc(); 6294 const TargetData *TD = TLI.getTargetData(); 6295 SmallVector<ISD::InputArg, 16> Ins; 6296 6297 // Check whether the function can return without sret-demotion. 6298 SmallVector<ISD::OutputArg, 4> Outs; 6299 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6300 Outs, TLI); 6301 6302 if (!FuncInfo->CanLowerReturn) { 6303 // Put in an sret pointer parameter before all the other parameters. 6304 SmallVector<EVT, 1> ValueVTs; 6305 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6306 6307 // NOTE: Assuming that a pointer will never break down to more than one VT 6308 // or one register. 6309 ISD::ArgFlagsTy Flags; 6310 Flags.setSRet(); 6311 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6312 ISD::InputArg RetArg(Flags, RegisterVT, true); 6313 Ins.push_back(RetArg); 6314 } 6315 6316 // Set up the incoming argument description vector. 6317 unsigned Idx = 1; 6318 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6319 I != E; ++I, ++Idx) { 6320 SmallVector<EVT, 4> ValueVTs; 6321 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6322 bool isArgValueUsed = !I->use_empty(); 6323 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6324 Value != NumValues; ++Value) { 6325 EVT VT = ValueVTs[Value]; 6326 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6327 ISD::ArgFlagsTy Flags; 6328 unsigned OriginalAlignment = 6329 TD->getABITypeAlignment(ArgTy); 6330 6331 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6332 Flags.setZExt(); 6333 if (F.paramHasAttr(Idx, Attribute::SExt)) 6334 Flags.setSExt(); 6335 if (F.paramHasAttr(Idx, Attribute::InReg)) 6336 Flags.setInReg(); 6337 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6338 Flags.setSRet(); 6339 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6340 Flags.setByVal(); 6341 const PointerType *Ty = cast<PointerType>(I->getType()); 6342 const Type *ElementTy = Ty->getElementType(); 6343 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6344 // For ByVal, alignment should be passed from FE. BE will guess if 6345 // this info is not there but there are cases it cannot get right. 6346 unsigned FrameAlign; 6347 if (F.getParamAlignment(Idx)) 6348 FrameAlign = F.getParamAlignment(Idx); 6349 else 6350 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6351 Flags.setByValAlign(FrameAlign); 6352 } 6353 if (F.paramHasAttr(Idx, Attribute::Nest)) 6354 Flags.setNest(); 6355 Flags.setOrigAlign(OriginalAlignment); 6356 6357 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6358 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6359 for (unsigned i = 0; i != NumRegs; ++i) { 6360 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6361 if (NumRegs > 1 && i == 0) 6362 MyFlags.Flags.setSplit(); 6363 // if it isn't first piece, alignment must be 1 6364 else if (i > 0) 6365 MyFlags.Flags.setOrigAlign(1); 6366 Ins.push_back(MyFlags); 6367 } 6368 } 6369 } 6370 6371 // Call the target to set up the argument values. 6372 SmallVector<SDValue, 8> InVals; 6373 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6374 F.isVarArg(), Ins, 6375 dl, DAG, InVals); 6376 6377 // Verify that the target's LowerFormalArguments behaved as expected. 6378 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6379 "LowerFormalArguments didn't return a valid chain!"); 6380 assert(InVals.size() == Ins.size() && 6381 "LowerFormalArguments didn't emit the correct number of values!"); 6382 DEBUG({ 6383 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6384 assert(InVals[i].getNode() && 6385 "LowerFormalArguments emitted a null value!"); 6386 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6387 "LowerFormalArguments emitted a value with the wrong type!"); 6388 } 6389 }); 6390 6391 // Update the DAG with the new chain value resulting from argument lowering. 6392 DAG.setRoot(NewRoot); 6393 6394 // Set up the argument values. 6395 unsigned i = 0; 6396 Idx = 1; 6397 if (!FuncInfo->CanLowerReturn) { 6398 // Create a virtual register for the sret pointer, and put in a copy 6399 // from the sret argument into it. 6400 SmallVector<EVT, 1> ValueVTs; 6401 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6402 EVT VT = ValueVTs[0]; 6403 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6404 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6405 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6406 RegVT, VT, AssertOp); 6407 6408 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6409 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6410 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6411 FuncInfo->DemoteRegister = SRetReg; 6412 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6413 SRetReg, ArgValue); 6414 DAG.setRoot(NewRoot); 6415 6416 // i indexes lowered arguments. Bump it past the hidden sret argument. 6417 // Idx indexes LLVM arguments. Don't touch it. 6418 ++i; 6419 } 6420 6421 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6422 ++I, ++Idx) { 6423 SmallVector<SDValue, 4> ArgValues; 6424 SmallVector<EVT, 4> ValueVTs; 6425 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6426 unsigned NumValues = ValueVTs.size(); 6427 6428 // If this argument is unused then remember its value. It is used to generate 6429 // debugging information. 6430 if (I->use_empty() && NumValues) 6431 SDB->setUnusedArgValue(I, InVals[i]); 6432 6433 for (unsigned Val = 0; Val != NumValues; ++Val) { 6434 EVT VT = ValueVTs[Val]; 6435 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6436 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6437 6438 if (!I->use_empty()) { 6439 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6440 if (F.paramHasAttr(Idx, Attribute::SExt)) 6441 AssertOp = ISD::AssertSext; 6442 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6443 AssertOp = ISD::AssertZext; 6444 6445 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6446 NumParts, PartVT, VT, 6447 AssertOp)); 6448 } 6449 6450 i += NumParts; 6451 } 6452 6453 // We don't need to do anything else for unused arguments. 6454 if (ArgValues.empty()) 6455 continue; 6456 6457 // Note down frame index for byval arguments. 6458 if (I->hasByValAttr()) 6459 if (FrameIndexSDNode *FI = 6460 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6461 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6462 6463 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6464 SDB->getCurDebugLoc()); 6465 SDB->setValue(I, Res); 6466 6467 // If this argument is live outside of the entry block, insert a copy from 6468 // wherever we got it to the vreg that other BB's will reference it as. 6469 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6470 // If we can, though, try to skip creating an unnecessary vreg. 6471 // FIXME: This isn't very clean... it would be nice to make this more 6472 // general. It's also subtly incompatible with the hacks FastISel 6473 // uses with vregs. 6474 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6475 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6476 FuncInfo->ValueMap[I] = Reg; 6477 continue; 6478 } 6479 } 6480 if (!isOnlyUsedInEntryBlock(I)) { 6481 FuncInfo->InitializeRegForValue(I); 6482 SDB->CopyToExportRegsIfNeeded(I); 6483 } 6484 } 6485 6486 assert(i == InVals.size() && "Argument register count mismatch!"); 6487 6488 // Finally, if the target has anything special to do, allow it to do so. 6489 // FIXME: this should insert code into the DAG! 6490 EmitFunctionEntryCode(); 6491} 6492 6493/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6494/// ensure constants are generated when needed. Remember the virtual registers 6495/// that need to be added to the Machine PHI nodes as input. We cannot just 6496/// directly add them, because expansion might result in multiple MBB's for one 6497/// BB. As such, the start of the BB might correspond to a different MBB than 6498/// the end. 6499/// 6500void 6501SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6502 const TerminatorInst *TI = LLVMBB->getTerminator(); 6503 6504 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6505 6506 // Check successor nodes' PHI nodes that expect a constant to be available 6507 // from this block. 6508 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6509 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6510 if (!isa<PHINode>(SuccBB->begin())) continue; 6511 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6512 6513 // If this terminator has multiple identical successors (common for 6514 // switches), only handle each succ once. 6515 if (!SuccsHandled.insert(SuccMBB)) continue; 6516 6517 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6518 6519 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6520 // nodes and Machine PHI nodes, but the incoming operands have not been 6521 // emitted yet. 6522 for (BasicBlock::const_iterator I = SuccBB->begin(); 6523 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6524 // Ignore dead phi's. 6525 if (PN->use_empty()) continue; 6526 6527 // Skip empty types 6528 if (PN->getType()->isEmptyTy()) 6529 continue; 6530 6531 unsigned Reg; 6532 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6533 6534 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6535 unsigned &RegOut = ConstantsOut[C]; 6536 if (RegOut == 0) { 6537 RegOut = FuncInfo.CreateRegs(C->getType()); 6538 CopyValueToVirtualRegister(C, RegOut); 6539 } 6540 Reg = RegOut; 6541 } else { 6542 DenseMap<const Value *, unsigned>::iterator I = 6543 FuncInfo.ValueMap.find(PHIOp); 6544 if (I != FuncInfo.ValueMap.end()) 6545 Reg = I->second; 6546 else { 6547 assert(isa<AllocaInst>(PHIOp) && 6548 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6549 "Didn't codegen value into a register!??"); 6550 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6551 CopyValueToVirtualRegister(PHIOp, Reg); 6552 } 6553 } 6554 6555 // Remember that this register needs to added to the machine PHI node as 6556 // the input for this MBB. 6557 SmallVector<EVT, 4> ValueVTs; 6558 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6559 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6560 EVT VT = ValueVTs[vti]; 6561 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6562 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6563 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6564 Reg += NumRegisters; 6565 } 6566 } 6567 } 6568 ConstantsOut.clear(); 6569} 6570