SelectionDAGBuilder.cpp revision a44defeb2208376ca3113ffdddc391570ba865b8
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/PseudoSourceValue.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Analysis/DebugInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameLowering.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72// Limit the width of DAG chains. This is important in general to prevent 73// prevent DAG-based analysis from blowing up. For example, alias analysis and 74// load clustering may not complete in reasonable time. It is difficult to 75// recognize and avoid this situation within each individual analysis, and 76// future analyses are likely to have the same behavior. Limiting DAG width is 77// the safe approach, and will be especially important with global DAGs. 78// 79// MaxParallelChains default is arbitrarily high to avoid affecting 80// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81// sequence over this should have been converted to llvm.memcpy by the 82// frontend. It easy to induce this behavior with .ll code such as: 83// %buffer = alloca [4096 x i8] 84// %data = load [4096 x i8]* %argPtr 85// store [4096 x i8] %data, [4096 x i8]* %buffer 86static const unsigned MaxParallelChains = 64; 87 88static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92/// getCopyFromParts - Create a value that contains the specified legal parts 93/// combined into the value they represent. If the parts combine to a type 94/// larger then ValueVT then AssertOp can be used to specify whether the extra 95/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96/// (ISD::AssertSext). 97static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getIntPtrConstant(1)); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209 return SDValue(); 210} 211 212/// getCopyFromParts - Create a value that contains the specified legal parts 213/// combined into the value they represent. If the parts combine to a type 214/// larger then ValueVT then AssertOp can be used to specify whether the extra 215/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216/// (ISD::AssertSext). 217static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 287 "Cannot handle this kind of promotion"); 288 // Promoted vector extract 289 bool Smaller = ValueVT.bitsLE(PartVT); 290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 291 DL, ValueVT, Val); 292 293 } 294 295 // Trivial bitcast if the types are the same size and the destination 296 // vector type is legal. 297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 298 TLI.isTypeLegal(ValueVT)) 299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 300 301 // Handle cases such as i8 -> <1 x i1> 302 assert(ValueVT.getVectorNumElements() == 1 && 303 "Only trivial scalar-to-vector conversions should get here!"); 304 305 if (ValueVT.getVectorNumElements() == 1 && 306 ValueVT.getVectorElementType() != PartVT) { 307 bool Smaller = ValueVT.bitsLE(PartVT); 308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 309 DL, ValueVT.getScalarType(), Val); 310 } 311 312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 313} 314 315 316 317 318static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 319 SDValue Val, SDValue *Parts, unsigned NumParts, 320 EVT PartVT); 321 322/// getCopyToParts - Create a series of nodes that contain the specified value 323/// split into legal parts. If the parts contain more bits than Val, then, for 324/// integers, ExtendKind can be used to specify how to generate the extra bits. 325static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 326 SDValue Val, SDValue *Parts, unsigned NumParts, 327 EVT PartVT, 328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 329 EVT ValueVT = Val.getValueType(); 330 331 // Handle the vector case separately. 332 if (ValueVT.isVector()) 333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 334 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 336 unsigned PartBits = PartVT.getSizeInBits(); 337 unsigned OrigNumParts = NumParts; 338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 339 340 if (NumParts == 0) 341 return; 342 343 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 344 if (PartVT == ValueVT) { 345 assert(NumParts == 1 && "No-op copy with multiple parts!"); 346 Parts[0] = Val; 347 return; 348 } 349 350 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 351 // If the parts cover more bits than the value has, promote the value. 352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 353 assert(NumParts == 1 && "Do not know what to promote to!"); 354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 355 } else { 356 assert(PartVT.isInteger() && ValueVT.isInteger() && 357 "Unknown mismatch!"); 358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 360 } 361 } else if (PartBits == ValueVT.getSizeInBits()) { 362 // Different types of the same size. 363 assert(NumParts == 1 && PartVT != ValueVT); 364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 366 // If the parts cover less bits than value has, truncate the value. 367 assert(PartVT.isInteger() && ValueVT.isInteger() && 368 "Unknown mismatch!"); 369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 371 } 372 373 // The value may have changed - recompute ValueVT. 374 ValueVT = Val.getValueType(); 375 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 376 "Failed to tile the value with PartVT!"); 377 378 if (NumParts == 1) { 379 assert(PartVT == ValueVT && "Type conversion failed!"); 380 Parts[0] = Val; 381 return; 382 } 383 384 // Expand the value into multiple parts. 385 if (NumParts & (NumParts - 1)) { 386 // The number of parts is not a power of 2. Split off and copy the tail. 387 assert(PartVT.isInteger() && ValueVT.isInteger() && 388 "Do not know what to expand to!"); 389 unsigned RoundParts = 1 << Log2_32(NumParts); 390 unsigned RoundBits = RoundParts * PartBits; 391 unsigned OddParts = NumParts - RoundParts; 392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 393 DAG.getIntPtrConstant(RoundBits)); 394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 395 396 if (TLI.isBigEndian()) 397 // The odd parts were reversed by getCopyToParts - unreverse them. 398 std::reverse(Parts + RoundParts, Parts + NumParts); 399 400 NumParts = RoundParts; 401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 403 } 404 405 // The number of parts is a power of 2. Repeatedly bisect the value using 406 // EXTRACT_ELEMENT. 407 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 408 EVT::getIntegerVT(*DAG.getContext(), 409 ValueVT.getSizeInBits()), 410 Val); 411 412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 413 for (unsigned i = 0; i < NumParts; i += StepSize) { 414 unsigned ThisBits = StepSize * PartBits / 2; 415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 416 SDValue &Part0 = Parts[i]; 417 SDValue &Part1 = Parts[i+StepSize/2]; 418 419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 420 ThisVT, Part0, DAG.getIntPtrConstant(1)); 421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 422 ThisVT, Part0, DAG.getIntPtrConstant(0)); 423 424 if (ThisBits == PartBits && ThisVT != PartVT) { 425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 427 } 428 } 429 } 430 431 if (TLI.isBigEndian()) 432 std::reverse(Parts, Parts + OrigNumParts); 433} 434 435 436/// getCopyToPartsVector - Create a series of nodes that contain the specified 437/// value split into legal parts. 438static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 439 SDValue Val, SDValue *Parts, unsigned NumParts, 440 EVT PartVT) { 441 EVT ValueVT = Val.getValueType(); 442 assert(ValueVT.isVector() && "Not a vector"); 443 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 444 445 if (NumParts == 1) { 446 if (PartVT == ValueVT) { 447 // Nothing to do. 448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 449 // Bitconvert vector->vector case. 450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 451 } else if (PartVT.isVector() && 452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 454 EVT ElementVT = PartVT.getVectorElementType(); 455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 456 // undef elements. 457 SmallVector<SDValue, 16> Ops; 458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 460 ElementVT, Val, DAG.getIntPtrConstant(i))); 461 462 for (unsigned i = ValueVT.getVectorNumElements(), 463 e = PartVT.getVectorNumElements(); i != e; ++i) 464 Ops.push_back(DAG.getUNDEF(ElementVT)); 465 466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 467 468 // FIXME: Use CONCAT for 2x -> 4x. 469 470 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 472 } else if (PartVT.isVector() && 473 PartVT.getVectorElementType().bitsGE( 474 ValueVT.getVectorElementType()) && 475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 476 477 // Promoted vector extract 478 bool Smaller = PartVT.bitsLE(ValueVT); 479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 480 DL, PartVT, Val); 481 } else{ 482 // Vector -> scalar conversion. 483 assert(ValueVT.getVectorNumElements() == 1 && 484 "Only trivial vector-to-scalar conversions should get here!"); 485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 486 PartVT, Val, DAG.getIntPtrConstant(0)); 487 488 bool Smaller = ValueVT.bitsLE(PartVT); 489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 490 DL, PartVT, Val); 491 } 492 493 Parts[0] = Val; 494 return; 495 } 496 497 // Handle a multi-element vector. 498 EVT IntermediateVT, RegisterVT; 499 unsigned NumIntermediates; 500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 501 IntermediateVT, 502 NumIntermediates, RegisterVT); 503 unsigned NumElements = ValueVT.getVectorNumElements(); 504 505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 506 NumParts = NumRegs; // Silence a compiler warning. 507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 508 509 // Split the vector into intermediate operands. 510 SmallVector<SDValue, 8> Ops(NumIntermediates); 511 for (unsigned i = 0; i != NumIntermediates; ++i) { 512 if (IntermediateVT.isVector()) 513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 514 IntermediateVT, Val, 515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 516 else 517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 518 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 519 } 520 521 // Split the intermediate operands into legal parts. 522 if (NumParts == NumIntermediates) { 523 // If the register was not expanded, promote or copy the value, 524 // as appropriate. 525 for (unsigned i = 0; i != NumParts; ++i) 526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 527 } else if (NumParts > 0) { 528 // If the intermediate type was expanded, split each the value into 529 // legal parts. 530 assert(NumParts % NumIntermediates == 0 && 531 "Must expand into a divisible number of parts!"); 532 unsigned Factor = NumParts / NumIntermediates; 533 for (unsigned i = 0; i != NumIntermediates; ++i) 534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 535 } 536} 537 538 539 540 541namespace { 542 /// RegsForValue - This struct represents the registers (physical or virtual) 543 /// that a particular set of values is assigned, and the type information 544 /// about the value. The most common situation is to represent one value at a 545 /// time, but struct or array values are handled element-wise as multiple 546 /// values. The splitting of aggregates is performed recursively, so that we 547 /// never have aggregate-typed registers. The values at this point do not 548 /// necessarily have legal types, so each value may require one or more 549 /// registers of some legal type. 550 /// 551 struct RegsForValue { 552 /// ValueVTs - The value types of the values, which may not be legal, and 553 /// may need be promoted or synthesized from one or more registers. 554 /// 555 SmallVector<EVT, 4> ValueVTs; 556 557 /// RegVTs - The value types of the registers. This is the same size as 558 /// ValueVTs and it records, for each value, what the type of the assigned 559 /// register or registers are. (Individual values are never synthesized 560 /// from more than one type of register.) 561 /// 562 /// With virtual registers, the contents of RegVTs is redundant with TLI's 563 /// getRegisterType member function, however when with physical registers 564 /// it is necessary to have a separate record of the types. 565 /// 566 SmallVector<EVT, 4> RegVTs; 567 568 /// Regs - This list holds the registers assigned to the values. 569 /// Each legal or promoted value requires one register, and each 570 /// expanded value requires multiple registers. 571 /// 572 SmallVector<unsigned, 4> Regs; 573 574 RegsForValue() {} 575 576 RegsForValue(const SmallVector<unsigned, 4> ®s, 577 EVT regvt, EVT valuevt) 578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 579 580 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 581 unsigned Reg, Type *Ty) { 582 ComputeValueVTs(tli, Ty, ValueVTs); 583 584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 585 EVT ValueVT = ValueVTs[Value]; 586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 588 for (unsigned i = 0; i != NumRegs; ++i) 589 Regs.push_back(Reg + i); 590 RegVTs.push_back(RegisterVT); 591 Reg += NumRegs; 592 } 593 } 594 595 /// areValueTypesLegal - Return true if types of all the values are legal. 596 bool areValueTypesLegal(const TargetLowering &TLI) { 597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 598 EVT RegisterVT = RegVTs[Value]; 599 if (!TLI.isTypeLegal(RegisterVT)) 600 return false; 601 } 602 return true; 603 } 604 605 /// append - Add the specified values to this one. 606 void append(const RegsForValue &RHS) { 607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 609 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 610 } 611 612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 613 /// this value and returns the result as a ValueVTs value. This uses 614 /// Chain/Flag as the input and updates them for the output Chain/Flag. 615 /// If the Flag pointer is NULL, no flag is used. 616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 617 DebugLoc dl, 618 SDValue &Chain, SDValue *Flag) const; 619 620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 621 /// specified value into the registers specified by this object. This uses 622 /// Chain/Flag as the input and updates them for the output Chain/Flag. 623 /// If the Flag pointer is NULL, no flag is used. 624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 625 SDValue &Chain, SDValue *Flag) const; 626 627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 628 /// operand list. This adds the code marker, matching input operand index 629 /// (if applicable), and includes the number of values added into it. 630 void AddInlineAsmOperands(unsigned Kind, 631 bool HasMatching, unsigned MatchingIdx, 632 SelectionDAG &DAG, 633 std::vector<SDValue> &Ops) const; 634 }; 635} 636 637/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 638/// this value and returns the result as a ValueVT value. This uses 639/// Chain/Flag as the input and updates them for the output Chain/Flag. 640/// If the Flag pointer is NULL, no flag is used. 641SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 642 FunctionLoweringInfo &FuncInfo, 643 DebugLoc dl, 644 SDValue &Chain, SDValue *Flag) const { 645 // A Value with type {} or [0 x %t] needs no registers. 646 if (ValueVTs.empty()) 647 return SDValue(); 648 649 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 650 651 // Assemble the legal parts into the final values. 652 SmallVector<SDValue, 4> Values(ValueVTs.size()); 653 SmallVector<SDValue, 8> Parts; 654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 655 // Copy the legal parts from the registers. 656 EVT ValueVT = ValueVTs[Value]; 657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 658 EVT RegisterVT = RegVTs[Value]; 659 660 Parts.resize(NumRegs); 661 for (unsigned i = 0; i != NumRegs; ++i) { 662 SDValue P; 663 if (Flag == 0) { 664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 665 } else { 666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 667 *Flag = P.getValue(2); 668 } 669 670 Chain = P.getValue(1); 671 Parts[i] = P; 672 673 // If the source register was virtual and if we know something about it, 674 // add an assert node. 675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 676 !RegisterVT.isInteger() || RegisterVT.isVector()) 677 continue; 678 679 const FunctionLoweringInfo::LiveOutInfo *LOI = 680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 681 if (!LOI) 682 continue; 683 684 unsigned RegSize = RegisterVT.getSizeInBits(); 685 unsigned NumSignBits = LOI->NumSignBits; 686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 687 688 // FIXME: We capture more information than the dag can represent. For 689 // now, just use the tightest assertzext/assertsext possible. 690 bool isSExt = true; 691 EVT FromVT(MVT::Other); 692 if (NumSignBits == RegSize) 693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 694 else if (NumZeroBits >= RegSize-1) 695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 696 else if (NumSignBits > RegSize-8) 697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 698 else if (NumZeroBits >= RegSize-8) 699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 700 else if (NumSignBits > RegSize-16) 701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 702 else if (NumZeroBits >= RegSize-16) 703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 704 else if (NumSignBits > RegSize-32) 705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 706 else if (NumZeroBits >= RegSize-32) 707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 708 else 709 continue; 710 711 // Add an assertion node. 712 assert(FromVT != MVT::Other); 713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 714 RegisterVT, P, DAG.getValueType(FromVT)); 715 } 716 717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 718 NumRegs, RegisterVT, ValueVT); 719 Part += NumRegs; 720 Parts.clear(); 721 } 722 723 return DAG.getNode(ISD::MERGE_VALUES, dl, 724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 725 &Values[0], ValueVTs.size()); 726} 727 728/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 729/// specified value into the registers specified by this object. This uses 730/// Chain/Flag as the input and updates them for the output Chain/Flag. 731/// If the Flag pointer is NULL, no flag is used. 732void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 733 SDValue &Chain, SDValue *Flag) const { 734 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 735 736 // Get the list of the values's legal parts. 737 unsigned NumRegs = Regs.size(); 738 SmallVector<SDValue, 8> Parts(NumRegs); 739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 740 EVT ValueVT = ValueVTs[Value]; 741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 742 EVT RegisterVT = RegVTs[Value]; 743 744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 745 &Parts[Part], NumParts, RegisterVT); 746 Part += NumParts; 747 } 748 749 // Copy the parts into the registers. 750 SmallVector<SDValue, 8> Chains(NumRegs); 751 for (unsigned i = 0; i != NumRegs; ++i) { 752 SDValue Part; 753 if (Flag == 0) { 754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 755 } else { 756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 757 *Flag = Part.getValue(1); 758 } 759 760 Chains[i] = Part.getValue(0); 761 } 762 763 if (NumRegs == 1 || Flag) 764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 765 // flagged to it. That is the CopyToReg nodes and the user are considered 766 // a single scheduling unit. If we create a TokenFactor and return it as 767 // chain, then the TokenFactor is both a predecessor (operand) of the 768 // user as well as a successor (the TF operands are flagged to the user). 769 // c1, f1 = CopyToReg 770 // c2, f2 = CopyToReg 771 // c3 = TokenFactor c1, c2 772 // ... 773 // = op c3, ..., f2 774 Chain = Chains[NumRegs-1]; 775 else 776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 777} 778 779/// AddInlineAsmOperands - Add this value to the specified inlineasm node 780/// operand list. This adds the code marker and includes the number of 781/// values added into it. 782void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 783 unsigned MatchingIdx, 784 SelectionDAG &DAG, 785 std::vector<SDValue> &Ops) const { 786 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 787 788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 789 if (HasMatching) 790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 791 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 792 Ops.push_back(Res); 793 794 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 795 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 796 EVT RegisterVT = RegVTs[Value]; 797 for (unsigned i = 0; i != NumRegs; ++i) { 798 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 799 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 800 } 801 } 802} 803 804void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 805 AA = &aa; 806 GFI = gfi; 807 TD = DAG.getTarget().getTargetData(); 808} 809 810/// clear - Clear out the current SelectionDAG and the associated 811/// state and prepare this SelectionDAGBuilder object to be used 812/// for a new block. This doesn't clear out information about 813/// additional blocks that are needed to complete switch lowering 814/// or PHI node updating; that information is cleared out as it is 815/// consumed. 816void SelectionDAGBuilder::clear() { 817 NodeMap.clear(); 818 UnusedArgNodeMap.clear(); 819 PendingLoads.clear(); 820 PendingExports.clear(); 821 CurDebugLoc = DebugLoc(); 822 HasTailCall = false; 823} 824 825/// clearDanglingDebugInfo - Clear the dangling debug information 826/// map. This function is seperated from the clear so that debug 827/// information that is dangling in a basic block can be properly 828/// resolved in a different basic block. This allows the 829/// SelectionDAG to resolve dangling debug information attached 830/// to PHI nodes. 831void SelectionDAGBuilder::clearDanglingDebugInfo() { 832 DanglingDebugInfoMap.clear(); 833} 834 835/// getRoot - Return the current virtual root of the Selection DAG, 836/// flushing any PendingLoad items. This must be done before emitting 837/// a store or any other node that may need to be ordered after any 838/// prior load instructions. 839/// 840SDValue SelectionDAGBuilder::getRoot() { 841 if (PendingLoads.empty()) 842 return DAG.getRoot(); 843 844 if (PendingLoads.size() == 1) { 845 SDValue Root = PendingLoads[0]; 846 DAG.setRoot(Root); 847 PendingLoads.clear(); 848 return Root; 849 } 850 851 // Otherwise, we have to make a token factor node. 852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 853 &PendingLoads[0], PendingLoads.size()); 854 PendingLoads.clear(); 855 DAG.setRoot(Root); 856 return Root; 857} 858 859/// getControlRoot - Similar to getRoot, but instead of flushing all the 860/// PendingLoad items, flush all the PendingExports items. It is necessary 861/// to do this before emitting a terminator instruction. 862/// 863SDValue SelectionDAGBuilder::getControlRoot() { 864 SDValue Root = DAG.getRoot(); 865 866 if (PendingExports.empty()) 867 return Root; 868 869 // Turn all of the CopyToReg chains into one factored node. 870 if (Root.getOpcode() != ISD::EntryToken) { 871 unsigned i = 0, e = PendingExports.size(); 872 for (; i != e; ++i) { 873 assert(PendingExports[i].getNode()->getNumOperands() > 1); 874 if (PendingExports[i].getNode()->getOperand(0) == Root) 875 break; // Don't add the root if we already indirectly depend on it. 876 } 877 878 if (i == e) 879 PendingExports.push_back(Root); 880 } 881 882 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 883 &PendingExports[0], 884 PendingExports.size()); 885 PendingExports.clear(); 886 DAG.setRoot(Root); 887 return Root; 888} 889 890void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 891 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 892 DAG.AssignOrdering(Node, SDNodeOrder); 893 894 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 895 AssignOrderingToNode(Node->getOperand(I).getNode()); 896} 897 898void SelectionDAGBuilder::visit(const Instruction &I) { 899 // Set up outgoing PHI node register values before emitting the terminator. 900 if (isa<TerminatorInst>(&I)) 901 HandlePHINodesInSuccessorBlocks(I.getParent()); 902 903 CurDebugLoc = I.getDebugLoc(); 904 905 visit(I.getOpcode(), I); 906 907 if (!isa<TerminatorInst>(&I) && !HasTailCall) 908 CopyToExportRegsIfNeeded(&I); 909 910 CurDebugLoc = DebugLoc(); 911} 912 913void SelectionDAGBuilder::visitPHI(const PHINode &) { 914 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 915} 916 917void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 918 // Note: this doesn't use InstVisitor, because it has to work with 919 // ConstantExpr's in addition to instructions. 920 switch (Opcode) { 921 default: llvm_unreachable("Unknown instruction type encountered!"); 922 // Build the switch statement using the Instruction.def file. 923#define HANDLE_INST(NUM, OPCODE, CLASS) \ 924 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 925#include "llvm/Instruction.def" 926 } 927 928 // Assign the ordering to the freshly created DAG nodes. 929 if (NodeMap.count(&I)) { 930 ++SDNodeOrder; 931 AssignOrderingToNode(getValue(&I).getNode()); 932 } 933} 934 935// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 936// generate the debug data structures now that we've seen its definition. 937void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 938 SDValue Val) { 939 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 940 if (DDI.getDI()) { 941 const DbgValueInst *DI = DDI.getDI(); 942 DebugLoc dl = DDI.getdl(); 943 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 944 MDNode *Variable = DI->getVariable(); 945 uint64_t Offset = DI->getOffset(); 946 SDDbgValue *SDV; 947 if (Val.getNode()) { 948 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 949 SDV = DAG.getDbgValue(Variable, Val.getNode(), 950 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 951 DAG.AddDbgValue(SDV, Val.getNode(), false); 952 } 953 } else 954 DEBUG(dbgs() << "Dropping debug info for " << DI); 955 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 956 } 957} 958 959// getValue - Return an SDValue for the given Value. 960SDValue SelectionDAGBuilder::getValue(const Value *V) { 961 // If we already have an SDValue for this value, use it. It's important 962 // to do this first, so that we don't create a CopyFromReg if we already 963 // have a regular SDValue. 964 SDValue &N = NodeMap[V]; 965 if (N.getNode()) return N; 966 967 // If there's a virtual register allocated and initialized for this 968 // value, use it. 969 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 970 if (It != FuncInfo.ValueMap.end()) { 971 unsigned InReg = It->second; 972 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 973 SDValue Chain = DAG.getEntryNode(); 974 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 975 resolveDanglingDebugInfo(V, N); 976 return N; 977 } 978 979 // Otherwise create a new SDValue and remember it. 980 SDValue Val = getValueImpl(V); 981 NodeMap[V] = Val; 982 resolveDanglingDebugInfo(V, Val); 983 return Val; 984} 985 986/// getNonRegisterValue - Return an SDValue for the given Value, but 987/// don't look in FuncInfo.ValueMap for a virtual register. 988SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 989 // If we already have an SDValue for this value, use it. 990 SDValue &N = NodeMap[V]; 991 if (N.getNode()) return N; 992 993 // Otherwise create a new SDValue and remember it. 994 SDValue Val = getValueImpl(V); 995 NodeMap[V] = Val; 996 resolveDanglingDebugInfo(V, Val); 997 return Val; 998} 999 1000/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1001/// Create an SDValue for the given value. 1002SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1003 if (const Constant *C = dyn_cast<Constant>(V)) { 1004 EVT VT = TLI.getValueType(V->getType(), true); 1005 1006 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1007 return DAG.getConstant(*CI, VT); 1008 1009 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1010 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1011 1012 if (isa<ConstantPointerNull>(C)) 1013 return DAG.getConstant(0, TLI.getPointerTy()); 1014 1015 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1016 return DAG.getConstantFP(*CFP, VT); 1017 1018 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1019 return DAG.getUNDEF(VT); 1020 1021 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1022 visit(CE->getOpcode(), *CE); 1023 SDValue N1 = NodeMap[V]; 1024 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1025 return N1; 1026 } 1027 1028 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1029 SmallVector<SDValue, 4> Constants; 1030 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1031 OI != OE; ++OI) { 1032 SDNode *Val = getValue(*OI).getNode(); 1033 // If the operand is an empty aggregate, there are no values. 1034 if (!Val) continue; 1035 // Add each leaf value from the operand to the Constants list 1036 // to form a flattened list of all the values. 1037 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1038 Constants.push_back(SDValue(Val, i)); 1039 } 1040 1041 return DAG.getMergeValues(&Constants[0], Constants.size(), 1042 getCurDebugLoc()); 1043 } 1044 1045 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1046 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1047 "Unknown struct or array constant!"); 1048 1049 SmallVector<EVT, 4> ValueVTs; 1050 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1051 unsigned NumElts = ValueVTs.size(); 1052 if (NumElts == 0) 1053 return SDValue(); // empty struct 1054 SmallVector<SDValue, 4> Constants(NumElts); 1055 for (unsigned i = 0; i != NumElts; ++i) { 1056 EVT EltVT = ValueVTs[i]; 1057 if (isa<UndefValue>(C)) 1058 Constants[i] = DAG.getUNDEF(EltVT); 1059 else if (EltVT.isFloatingPoint()) 1060 Constants[i] = DAG.getConstantFP(0, EltVT); 1061 else 1062 Constants[i] = DAG.getConstant(0, EltVT); 1063 } 1064 1065 return DAG.getMergeValues(&Constants[0], NumElts, 1066 getCurDebugLoc()); 1067 } 1068 1069 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1070 return DAG.getBlockAddress(BA, VT); 1071 1072 VectorType *VecTy = cast<VectorType>(V->getType()); 1073 unsigned NumElements = VecTy->getNumElements(); 1074 1075 // Now that we know the number and type of the elements, get that number of 1076 // elements into the Ops array based on what kind of constant it is. 1077 SmallVector<SDValue, 16> Ops; 1078 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1079 for (unsigned i = 0; i != NumElements; ++i) 1080 Ops.push_back(getValue(CP->getOperand(i))); 1081 } else { 1082 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1083 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1084 1085 SDValue Op; 1086 if (EltVT.isFloatingPoint()) 1087 Op = DAG.getConstantFP(0, EltVT); 1088 else 1089 Op = DAG.getConstant(0, EltVT); 1090 Ops.assign(NumElements, Op); 1091 } 1092 1093 // Create a BUILD_VECTOR node. 1094 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1095 VT, &Ops[0], Ops.size()); 1096 } 1097 1098 // If this is a static alloca, generate it as the frameindex instead of 1099 // computation. 1100 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1101 DenseMap<const AllocaInst*, int>::iterator SI = 1102 FuncInfo.StaticAllocaMap.find(AI); 1103 if (SI != FuncInfo.StaticAllocaMap.end()) 1104 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1105 } 1106 1107 // If this is an instruction which fast-isel has deferred, select it now. 1108 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1109 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1110 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1111 SDValue Chain = DAG.getEntryNode(); 1112 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1113 } 1114 1115 llvm_unreachable("Can't get register for value!"); 1116 return SDValue(); 1117} 1118 1119void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1120 SDValue Chain = getControlRoot(); 1121 SmallVector<ISD::OutputArg, 8> Outs; 1122 SmallVector<SDValue, 8> OutVals; 1123 1124 if (!FuncInfo.CanLowerReturn) { 1125 unsigned DemoteReg = FuncInfo.DemoteRegister; 1126 const Function *F = I.getParent()->getParent(); 1127 1128 // Emit a store of the return value through the virtual register. 1129 // Leave Outs empty so that LowerReturn won't try to load return 1130 // registers the usual way. 1131 SmallVector<EVT, 1> PtrValueVTs; 1132 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1133 PtrValueVTs); 1134 1135 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1136 SDValue RetOp = getValue(I.getOperand(0)); 1137 1138 SmallVector<EVT, 4> ValueVTs; 1139 SmallVector<uint64_t, 4> Offsets; 1140 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1141 unsigned NumValues = ValueVTs.size(); 1142 1143 SmallVector<SDValue, 4> Chains(NumValues); 1144 for (unsigned i = 0; i != NumValues; ++i) { 1145 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1146 RetPtr.getValueType(), RetPtr, 1147 DAG.getIntPtrConstant(Offsets[i])); 1148 Chains[i] = 1149 DAG.getStore(Chain, getCurDebugLoc(), 1150 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1151 // FIXME: better loc info would be nice. 1152 Add, MachinePointerInfo(), false, false, 0); 1153 } 1154 1155 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1156 MVT::Other, &Chains[0], NumValues); 1157 } else if (I.getNumOperands() != 0) { 1158 SmallVector<EVT, 4> ValueVTs; 1159 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1160 unsigned NumValues = ValueVTs.size(); 1161 if (NumValues) { 1162 SDValue RetOp = getValue(I.getOperand(0)); 1163 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1164 EVT VT = ValueVTs[j]; 1165 1166 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1167 1168 const Function *F = I.getParent()->getParent(); 1169 if (F->paramHasAttr(0, Attribute::SExt)) 1170 ExtendKind = ISD::SIGN_EXTEND; 1171 else if (F->paramHasAttr(0, Attribute::ZExt)) 1172 ExtendKind = ISD::ZERO_EXTEND; 1173 1174 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1175 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1176 1177 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1178 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1179 SmallVector<SDValue, 4> Parts(NumParts); 1180 getCopyToParts(DAG, getCurDebugLoc(), 1181 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1182 &Parts[0], NumParts, PartVT, ExtendKind); 1183 1184 // 'inreg' on function refers to return value 1185 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1186 if (F->paramHasAttr(0, Attribute::InReg)) 1187 Flags.setInReg(); 1188 1189 // Propagate extension type if any 1190 if (ExtendKind == ISD::SIGN_EXTEND) 1191 Flags.setSExt(); 1192 else if (ExtendKind == ISD::ZERO_EXTEND) 1193 Flags.setZExt(); 1194 1195 for (unsigned i = 0; i < NumParts; ++i) { 1196 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1197 /*isfixed=*/true)); 1198 OutVals.push_back(Parts[i]); 1199 } 1200 } 1201 } 1202 } 1203 1204 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1205 CallingConv::ID CallConv = 1206 DAG.getMachineFunction().getFunction()->getCallingConv(); 1207 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1208 Outs, OutVals, getCurDebugLoc(), DAG); 1209 1210 // Verify that the target's LowerReturn behaved as expected. 1211 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1212 "LowerReturn didn't return a valid chain!"); 1213 1214 // Update the DAG with the new chain value resulting from return lowering. 1215 DAG.setRoot(Chain); 1216} 1217 1218/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1219/// created for it, emit nodes to copy the value into the virtual 1220/// registers. 1221void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1222 // Skip empty types 1223 if (V->getType()->isEmptyTy()) 1224 return; 1225 1226 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1227 if (VMI != FuncInfo.ValueMap.end()) { 1228 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1229 CopyValueToVirtualRegister(V, VMI->second); 1230 } 1231} 1232 1233/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1234/// the current basic block, add it to ValueMap now so that we'll get a 1235/// CopyTo/FromReg. 1236void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1237 // No need to export constants. 1238 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1239 1240 // Already exported? 1241 if (FuncInfo.isExportedInst(V)) return; 1242 1243 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1244 CopyValueToVirtualRegister(V, Reg); 1245} 1246 1247bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1248 const BasicBlock *FromBB) { 1249 // The operands of the setcc have to be in this block. We don't know 1250 // how to export them from some other block. 1251 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1252 // Can export from current BB. 1253 if (VI->getParent() == FromBB) 1254 return true; 1255 1256 // Is already exported, noop. 1257 return FuncInfo.isExportedInst(V); 1258 } 1259 1260 // If this is an argument, we can export it if the BB is the entry block or 1261 // if it is already exported. 1262 if (isa<Argument>(V)) { 1263 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1264 return true; 1265 1266 // Otherwise, can only export this if it is already exported. 1267 return FuncInfo.isExportedInst(V); 1268 } 1269 1270 // Otherwise, constants can always be exported. 1271 return true; 1272} 1273 1274/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1275uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src, 1276 MachineBasicBlock *Dst) { 1277 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1278 if (!BPI) 1279 return 0; 1280 BasicBlock *SrcBB = const_cast<BasicBlock*>(Src->getBasicBlock()); 1281 BasicBlock *DstBB = const_cast<BasicBlock*>(Dst->getBasicBlock()); 1282 return BPI->getEdgeWeight(SrcBB, DstBB); 1283} 1284 1285void SelectionDAGBuilder::addSuccessorWithWeight(MachineBasicBlock *Src, 1286 MachineBasicBlock *Dst) { 1287 uint32_t weight = getEdgeWeight(Src, Dst); 1288 Src->addSuccessor(Dst, weight); 1289} 1290 1291 1292static bool InBlock(const Value *V, const BasicBlock *BB) { 1293 if (const Instruction *I = dyn_cast<Instruction>(V)) 1294 return I->getParent() == BB; 1295 return true; 1296} 1297 1298/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1299/// This function emits a branch and is used at the leaves of an OR or an 1300/// AND operator tree. 1301/// 1302void 1303SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1304 MachineBasicBlock *TBB, 1305 MachineBasicBlock *FBB, 1306 MachineBasicBlock *CurBB, 1307 MachineBasicBlock *SwitchBB) { 1308 const BasicBlock *BB = CurBB->getBasicBlock(); 1309 1310 // If the leaf of the tree is a comparison, merge the condition into 1311 // the caseblock. 1312 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1313 // The operands of the cmp have to be in this block. We don't know 1314 // how to export them from some other block. If this is the first block 1315 // of the sequence, no exporting is needed. 1316 if (CurBB == SwitchBB || 1317 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1318 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1319 ISD::CondCode Condition; 1320 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1321 Condition = getICmpCondCode(IC->getPredicate()); 1322 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1323 Condition = getFCmpCondCode(FC->getPredicate()); 1324 } else { 1325 Condition = ISD::SETEQ; // silence warning. 1326 llvm_unreachable("Unknown compare instruction"); 1327 } 1328 1329 CaseBlock CB(Condition, BOp->getOperand(0), 1330 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1331 SwitchCases.push_back(CB); 1332 return; 1333 } 1334 } 1335 1336 // Create a CaseBlock record representing this branch. 1337 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1338 NULL, TBB, FBB, CurBB); 1339 SwitchCases.push_back(CB); 1340} 1341 1342/// FindMergedConditions - If Cond is an expression like 1343void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1344 MachineBasicBlock *TBB, 1345 MachineBasicBlock *FBB, 1346 MachineBasicBlock *CurBB, 1347 MachineBasicBlock *SwitchBB, 1348 unsigned Opc) { 1349 // If this node is not part of the or/and tree, emit it as a branch. 1350 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1351 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1352 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1353 BOp->getParent() != CurBB->getBasicBlock() || 1354 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1355 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1356 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1357 return; 1358 } 1359 1360 // Create TmpBB after CurBB. 1361 MachineFunction::iterator BBI = CurBB; 1362 MachineFunction &MF = DAG.getMachineFunction(); 1363 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1364 CurBB->getParent()->insert(++BBI, TmpBB); 1365 1366 if (Opc == Instruction::Or) { 1367 // Codegen X | Y as: 1368 // jmp_if_X TBB 1369 // jmp TmpBB 1370 // TmpBB: 1371 // jmp_if_Y TBB 1372 // jmp FBB 1373 // 1374 1375 // Emit the LHS condition. 1376 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1377 1378 // Emit the RHS condition into TmpBB. 1379 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1380 } else { 1381 assert(Opc == Instruction::And && "Unknown merge op!"); 1382 // Codegen X & Y as: 1383 // jmp_if_X TmpBB 1384 // jmp FBB 1385 // TmpBB: 1386 // jmp_if_Y TBB 1387 // jmp FBB 1388 // 1389 // This requires creation of TmpBB after CurBB. 1390 1391 // Emit the LHS condition. 1392 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1393 1394 // Emit the RHS condition into TmpBB. 1395 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1396 } 1397} 1398 1399/// If the set of cases should be emitted as a series of branches, return true. 1400/// If we should emit this as a bunch of and/or'd together conditions, return 1401/// false. 1402bool 1403SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1404 if (Cases.size() != 2) return true; 1405 1406 // If this is two comparisons of the same values or'd or and'd together, they 1407 // will get folded into a single comparison, so don't emit two blocks. 1408 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1409 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1410 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1411 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1412 return false; 1413 } 1414 1415 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1416 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1417 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1418 Cases[0].CC == Cases[1].CC && 1419 isa<Constant>(Cases[0].CmpRHS) && 1420 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1421 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1422 return false; 1423 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1424 return false; 1425 } 1426 1427 return true; 1428} 1429 1430void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1431 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1432 1433 // Update machine-CFG edges. 1434 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1435 1436 // Figure out which block is immediately after the current one. 1437 MachineBasicBlock *NextBlock = 0; 1438 MachineFunction::iterator BBI = BrMBB; 1439 if (++BBI != FuncInfo.MF->end()) 1440 NextBlock = BBI; 1441 1442 if (I.isUnconditional()) { 1443 // Update machine-CFG edges. 1444 BrMBB->addSuccessor(Succ0MBB); 1445 1446 // If this is not a fall-through branch, emit the branch. 1447 if (Succ0MBB != NextBlock) 1448 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1449 MVT::Other, getControlRoot(), 1450 DAG.getBasicBlock(Succ0MBB))); 1451 1452 return; 1453 } 1454 1455 // If this condition is one of the special cases we handle, do special stuff 1456 // now. 1457 const Value *CondVal = I.getCondition(); 1458 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1459 1460 // If this is a series of conditions that are or'd or and'd together, emit 1461 // this as a sequence of branches instead of setcc's with and/or operations. 1462 // As long as jumps are not expensive, this should improve performance. 1463 // For example, instead of something like: 1464 // cmp A, B 1465 // C = seteq 1466 // cmp D, E 1467 // F = setle 1468 // or C, F 1469 // jnz foo 1470 // Emit: 1471 // cmp A, B 1472 // je foo 1473 // cmp D, E 1474 // jle foo 1475 // 1476 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1477 if (!TLI.isJumpExpensive() && 1478 BOp->hasOneUse() && 1479 (BOp->getOpcode() == Instruction::And || 1480 BOp->getOpcode() == Instruction::Or)) { 1481 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1482 BOp->getOpcode()); 1483 // If the compares in later blocks need to use values not currently 1484 // exported from this block, export them now. This block should always 1485 // be the first entry. 1486 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1487 1488 // Allow some cases to be rejected. 1489 if (ShouldEmitAsBranches(SwitchCases)) { 1490 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1491 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1492 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1493 } 1494 1495 // Emit the branch for this block. 1496 visitSwitchCase(SwitchCases[0], BrMBB); 1497 SwitchCases.erase(SwitchCases.begin()); 1498 return; 1499 } 1500 1501 // Okay, we decided not to do this, remove any inserted MBB's and clear 1502 // SwitchCases. 1503 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1504 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1505 1506 SwitchCases.clear(); 1507 } 1508 } 1509 1510 // Create a CaseBlock record representing this branch. 1511 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1512 NULL, Succ0MBB, Succ1MBB, BrMBB); 1513 1514 // Use visitSwitchCase to actually insert the fast branch sequence for this 1515 // cond branch. 1516 visitSwitchCase(CB, BrMBB); 1517} 1518 1519/// visitSwitchCase - Emits the necessary code to represent a single node in 1520/// the binary search tree resulting from lowering a switch instruction. 1521void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1522 MachineBasicBlock *SwitchBB) { 1523 SDValue Cond; 1524 SDValue CondLHS = getValue(CB.CmpLHS); 1525 DebugLoc dl = getCurDebugLoc(); 1526 1527 // Build the setcc now. 1528 if (CB.CmpMHS == NULL) { 1529 // Fold "(X == true)" to X and "(X == false)" to !X to 1530 // handle common cases produced by branch lowering. 1531 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1532 CB.CC == ISD::SETEQ) 1533 Cond = CondLHS; 1534 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1535 CB.CC == ISD::SETEQ) { 1536 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1537 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1538 } else 1539 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1540 } else { 1541 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1542 1543 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1544 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1545 1546 SDValue CmpOp = getValue(CB.CmpMHS); 1547 EVT VT = CmpOp.getValueType(); 1548 1549 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1550 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1551 ISD::SETLE); 1552 } else { 1553 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1554 VT, CmpOp, DAG.getConstant(Low, VT)); 1555 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1556 DAG.getConstant(High-Low, VT), ISD::SETULE); 1557 } 1558 } 1559 1560 // Update successor info 1561 addSuccessorWithWeight(SwitchBB, CB.TrueBB); 1562 addSuccessorWithWeight(SwitchBB, CB.FalseBB); 1563 1564 // Set NextBlock to be the MBB immediately after the current one, if any. 1565 // This is used to avoid emitting unnecessary branches to the next block. 1566 MachineBasicBlock *NextBlock = 0; 1567 MachineFunction::iterator BBI = SwitchBB; 1568 if (++BBI != FuncInfo.MF->end()) 1569 NextBlock = BBI; 1570 1571 // If the lhs block is the next block, invert the condition so that we can 1572 // fall through to the lhs instead of the rhs block. 1573 if (CB.TrueBB == NextBlock) { 1574 std::swap(CB.TrueBB, CB.FalseBB); 1575 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1576 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1577 } 1578 1579 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1580 MVT::Other, getControlRoot(), Cond, 1581 DAG.getBasicBlock(CB.TrueBB)); 1582 1583 // Insert the false branch. Do this even if it's a fall through branch, 1584 // this makes it easier to do DAG optimizations which require inverting 1585 // the branch condition. 1586 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1587 DAG.getBasicBlock(CB.FalseBB)); 1588 1589 DAG.setRoot(BrCond); 1590} 1591 1592/// visitJumpTable - Emit JumpTable node in the current MBB 1593void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1594 // Emit the code for the jump table 1595 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1596 EVT PTy = TLI.getPointerTy(); 1597 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1598 JT.Reg, PTy); 1599 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1600 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1601 MVT::Other, Index.getValue(1), 1602 Table, Index); 1603 DAG.setRoot(BrJumpTable); 1604} 1605 1606/// visitJumpTableHeader - This function emits necessary code to produce index 1607/// in the JumpTable from switch case. 1608void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1609 JumpTableHeader &JTH, 1610 MachineBasicBlock *SwitchBB) { 1611 // Subtract the lowest switch case value from the value being switched on and 1612 // conditional branch to default mbb if the result is greater than the 1613 // difference between smallest and largest cases. 1614 SDValue SwitchOp = getValue(JTH.SValue); 1615 EVT VT = SwitchOp.getValueType(); 1616 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1617 DAG.getConstant(JTH.First, VT)); 1618 1619 // The SDNode we just created, which holds the value being switched on minus 1620 // the smallest case value, needs to be copied to a virtual register so it 1621 // can be used as an index into the jump table in a subsequent basic block. 1622 // This value may be smaller or larger than the target's pointer type, and 1623 // therefore require extension or truncating. 1624 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1625 1626 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1627 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1628 JumpTableReg, SwitchOp); 1629 JT.Reg = JumpTableReg; 1630 1631 // Emit the range check for the jump table, and branch to the default block 1632 // for the switch statement if the value being switched on exceeds the largest 1633 // case in the switch. 1634 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1635 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1636 DAG.getConstant(JTH.Last-JTH.First,VT), 1637 ISD::SETUGT); 1638 1639 // Set NextBlock to be the MBB immediately after the current one, if any. 1640 // This is used to avoid emitting unnecessary branches to the next block. 1641 MachineBasicBlock *NextBlock = 0; 1642 MachineFunction::iterator BBI = SwitchBB; 1643 1644 if (++BBI != FuncInfo.MF->end()) 1645 NextBlock = BBI; 1646 1647 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1648 MVT::Other, CopyTo, CMP, 1649 DAG.getBasicBlock(JT.Default)); 1650 1651 if (JT.MBB != NextBlock) 1652 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1653 DAG.getBasicBlock(JT.MBB)); 1654 1655 DAG.setRoot(BrCond); 1656} 1657 1658/// visitBitTestHeader - This function emits necessary code to produce value 1659/// suitable for "bit tests" 1660void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1661 MachineBasicBlock *SwitchBB) { 1662 // Subtract the minimum value 1663 SDValue SwitchOp = getValue(B.SValue); 1664 EVT VT = SwitchOp.getValueType(); 1665 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1666 DAG.getConstant(B.First, VT)); 1667 1668 // Check range 1669 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1670 TLI.getSetCCResultType(Sub.getValueType()), 1671 Sub, DAG.getConstant(B.Range, VT), 1672 ISD::SETUGT); 1673 1674 // Determine the type of the test operands. 1675 bool UsePtrType = false; 1676 if (!TLI.isTypeLegal(VT)) 1677 UsePtrType = true; 1678 else { 1679 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1680 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) { 1681 // Switch table case range are encoded into series of masks. 1682 // Just use pointer type, it's guaranteed to fit. 1683 UsePtrType = true; 1684 break; 1685 } 1686 } 1687 if (UsePtrType) { 1688 VT = TLI.getPointerTy(); 1689 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1690 } 1691 1692 B.RegVT = VT; 1693 B.Reg = FuncInfo.CreateReg(VT); 1694 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1695 B.Reg, Sub); 1696 1697 // Set NextBlock to be the MBB immediately after the current one, if any. 1698 // This is used to avoid emitting unnecessary branches to the next block. 1699 MachineBasicBlock *NextBlock = 0; 1700 MachineFunction::iterator BBI = SwitchBB; 1701 if (++BBI != FuncInfo.MF->end()) 1702 NextBlock = BBI; 1703 1704 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1705 1706 addSuccessorWithWeight(SwitchBB, B.Default); 1707 addSuccessorWithWeight(SwitchBB, MBB); 1708 1709 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1710 MVT::Other, CopyTo, RangeCmp, 1711 DAG.getBasicBlock(B.Default)); 1712 1713 if (MBB != NextBlock) 1714 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1715 DAG.getBasicBlock(MBB)); 1716 1717 DAG.setRoot(BrRange); 1718} 1719 1720/// visitBitTestCase - this function produces one "bit test" 1721void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1722 MachineBasicBlock* NextMBB, 1723 unsigned Reg, 1724 BitTestCase &B, 1725 MachineBasicBlock *SwitchBB) { 1726 EVT VT = BB.RegVT; 1727 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1728 Reg, VT); 1729 SDValue Cmp; 1730 unsigned PopCount = CountPopulation_64(B.Mask); 1731 if (PopCount == 1) { 1732 // Testing for a single bit; just compare the shift count with what it 1733 // would need to be to shift a 1 bit in that position. 1734 Cmp = DAG.getSetCC(getCurDebugLoc(), 1735 TLI.getSetCCResultType(VT), 1736 ShiftOp, 1737 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1738 ISD::SETEQ); 1739 } else if (PopCount == BB.Range) { 1740 // There is only one zero bit in the range, test for it directly. 1741 Cmp = DAG.getSetCC(getCurDebugLoc(), 1742 TLI.getSetCCResultType(VT), 1743 ShiftOp, 1744 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1745 ISD::SETNE); 1746 } else { 1747 // Make desired shift 1748 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1749 DAG.getConstant(1, VT), ShiftOp); 1750 1751 // Emit bit tests and jumps 1752 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1753 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1754 Cmp = DAG.getSetCC(getCurDebugLoc(), 1755 TLI.getSetCCResultType(VT), 1756 AndOp, DAG.getConstant(0, VT), 1757 ISD::SETNE); 1758 } 1759 1760 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1761 addSuccessorWithWeight(SwitchBB, NextMBB); 1762 1763 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1764 MVT::Other, getControlRoot(), 1765 Cmp, DAG.getBasicBlock(B.TargetBB)); 1766 1767 // Set NextBlock to be the MBB immediately after the current one, if any. 1768 // This is used to avoid emitting unnecessary branches to the next block. 1769 MachineBasicBlock *NextBlock = 0; 1770 MachineFunction::iterator BBI = SwitchBB; 1771 if (++BBI != FuncInfo.MF->end()) 1772 NextBlock = BBI; 1773 1774 if (NextMBB != NextBlock) 1775 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1776 DAG.getBasicBlock(NextMBB)); 1777 1778 DAG.setRoot(BrAnd); 1779} 1780 1781void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1782 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1783 1784 // Retrieve successors. 1785 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1786 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1787 1788 const Value *Callee(I.getCalledValue()); 1789 if (isa<InlineAsm>(Callee)) 1790 visitInlineAsm(&I); 1791 else 1792 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1793 1794 // If the value of the invoke is used outside of its defining block, make it 1795 // available as a virtual register. 1796 CopyToExportRegsIfNeeded(&I); 1797 1798 // Update successor info 1799 InvokeMBB->addSuccessor(Return); 1800 InvokeMBB->addSuccessor(LandingPad); 1801 1802 // Drop into normal successor. 1803 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1804 MVT::Other, getControlRoot(), 1805 DAG.getBasicBlock(Return))); 1806} 1807 1808void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1809} 1810 1811/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1812/// small case ranges). 1813bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1814 CaseRecVector& WorkList, 1815 const Value* SV, 1816 MachineBasicBlock *Default, 1817 MachineBasicBlock *SwitchBB) { 1818 Case& BackCase = *(CR.Range.second-1); 1819 1820 // Size is the number of Cases represented by this range. 1821 size_t Size = CR.Range.second - CR.Range.first; 1822 if (Size > 3) 1823 return false; 1824 1825 // Get the MachineFunction which holds the current MBB. This is used when 1826 // inserting any additional MBBs necessary to represent the switch. 1827 MachineFunction *CurMF = FuncInfo.MF; 1828 1829 // Figure out which block is immediately after the current one. 1830 MachineBasicBlock *NextBlock = 0; 1831 MachineFunction::iterator BBI = CR.CaseBB; 1832 1833 if (++BBI != FuncInfo.MF->end()) 1834 NextBlock = BBI; 1835 1836 // If any two of the cases has the same destination, and if one value 1837 // is the same as the other, but has one bit unset that the other has set, 1838 // use bit manipulation to do two compares at once. For example: 1839 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1840 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1841 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1842 if (Size == 2 && CR.CaseBB == SwitchBB) { 1843 Case &Small = *CR.Range.first; 1844 Case &Big = *(CR.Range.second-1); 1845 1846 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1847 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1848 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1849 1850 // Check that there is only one bit different. 1851 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1852 (SmallValue | BigValue) == BigValue) { 1853 // Isolate the common bit. 1854 APInt CommonBit = BigValue & ~SmallValue; 1855 assert((SmallValue | CommonBit) == BigValue && 1856 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1857 1858 SDValue CondLHS = getValue(SV); 1859 EVT VT = CondLHS.getValueType(); 1860 DebugLoc DL = getCurDebugLoc(); 1861 1862 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1863 DAG.getConstant(CommonBit, VT)); 1864 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1865 Or, DAG.getConstant(BigValue, VT), 1866 ISD::SETEQ); 1867 1868 // Update successor info. 1869 SwitchBB->addSuccessor(Small.BB); 1870 SwitchBB->addSuccessor(Default); 1871 1872 // Insert the true branch. 1873 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1874 getControlRoot(), Cond, 1875 DAG.getBasicBlock(Small.BB)); 1876 1877 // Insert the false branch. 1878 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1879 DAG.getBasicBlock(Default)); 1880 1881 DAG.setRoot(BrCond); 1882 return true; 1883 } 1884 } 1885 } 1886 1887 // Rearrange the case blocks so that the last one falls through if possible. 1888 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1889 // The last case block won't fall through into 'NextBlock' if we emit the 1890 // branches in this order. See if rearranging a case value would help. 1891 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1892 if (I->BB == NextBlock) { 1893 std::swap(*I, BackCase); 1894 break; 1895 } 1896 } 1897 } 1898 1899 // Create a CaseBlock record representing a conditional branch to 1900 // the Case's target mbb if the value being switched on SV is equal 1901 // to C. 1902 MachineBasicBlock *CurBlock = CR.CaseBB; 1903 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1904 MachineBasicBlock *FallThrough; 1905 if (I != E-1) { 1906 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1907 CurMF->insert(BBI, FallThrough); 1908 1909 // Put SV in a virtual register to make it available from the new blocks. 1910 ExportFromCurrentBlock(SV); 1911 } else { 1912 // If the last case doesn't match, go to the default block. 1913 FallThrough = Default; 1914 } 1915 1916 const Value *RHS, *LHS, *MHS; 1917 ISD::CondCode CC; 1918 if (I->High == I->Low) { 1919 // This is just small small case range :) containing exactly 1 case 1920 CC = ISD::SETEQ; 1921 LHS = SV; RHS = I->High; MHS = NULL; 1922 } else { 1923 CC = ISD::SETLE; 1924 LHS = I->Low; MHS = SV; RHS = I->High; 1925 } 1926 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1927 1928 // If emitting the first comparison, just call visitSwitchCase to emit the 1929 // code into the current block. Otherwise, push the CaseBlock onto the 1930 // vector to be later processed by SDISel, and insert the node's MBB 1931 // before the next MBB. 1932 if (CurBlock == SwitchBB) 1933 visitSwitchCase(CB, SwitchBB); 1934 else 1935 SwitchCases.push_back(CB); 1936 1937 CurBlock = FallThrough; 1938 } 1939 1940 return true; 1941} 1942 1943static inline bool areJTsAllowed(const TargetLowering &TLI) { 1944 return !DisableJumpTables && 1945 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1946 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1947} 1948 1949static APInt ComputeRange(const APInt &First, const APInt &Last) { 1950 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1951 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 1952 return (LastExt - FirstExt + 1ULL); 1953} 1954 1955/// handleJTSwitchCase - Emit jumptable for current switch case range 1956bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1957 CaseRecVector& WorkList, 1958 const Value* SV, 1959 MachineBasicBlock* Default, 1960 MachineBasicBlock *SwitchBB) { 1961 Case& FrontCase = *CR.Range.first; 1962 Case& BackCase = *(CR.Range.second-1); 1963 1964 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1965 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1966 1967 APInt TSize(First.getBitWidth(), 0); 1968 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1969 I!=E; ++I) 1970 TSize += I->size(); 1971 1972 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1973 return false; 1974 1975 APInt Range = ComputeRange(First, Last); 1976 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1977 if (Density < 0.4) 1978 return false; 1979 1980 DEBUG(dbgs() << "Lowering jump table\n" 1981 << "First entry: " << First << ". Last entry: " << Last << '\n' 1982 << "Range: " << Range 1983 << ". Size: " << TSize << ". Density: " << Density << "\n\n"); 1984 1985 // Get the MachineFunction which holds the current MBB. This is used when 1986 // inserting any additional MBBs necessary to represent the switch. 1987 MachineFunction *CurMF = FuncInfo.MF; 1988 1989 // Figure out which block is immediately after the current one. 1990 MachineFunction::iterator BBI = CR.CaseBB; 1991 ++BBI; 1992 1993 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1994 1995 // Create a new basic block to hold the code for loading the address 1996 // of the jump table, and jumping to it. Update successor information; 1997 // we will either branch to the default case for the switch, or the jump 1998 // table. 1999 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2000 CurMF->insert(BBI, JumpTableBB); 2001 2002 addSuccessorWithWeight(CR.CaseBB, Default); 2003 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2004 2005 // Build a vector of destination BBs, corresponding to each target 2006 // of the jump table. If the value of the jump table slot corresponds to 2007 // a case statement, push the case's BB onto the vector, otherwise, push 2008 // the default BB. 2009 std::vector<MachineBasicBlock*> DestBBs; 2010 APInt TEI = First; 2011 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2012 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2013 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2014 2015 if (Low.sle(TEI) && TEI.sle(High)) { 2016 DestBBs.push_back(I->BB); 2017 if (TEI==High) 2018 ++I; 2019 } else { 2020 DestBBs.push_back(Default); 2021 } 2022 } 2023 2024 // Update successor info. Add one edge to each unique successor. 2025 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2026 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2027 E = DestBBs.end(); I != E; ++I) { 2028 if (!SuccsHandled[(*I)->getNumber()]) { 2029 SuccsHandled[(*I)->getNumber()] = true; 2030 addSuccessorWithWeight(JumpTableBB, *I); 2031 } 2032 } 2033 2034 // Create a jump table index for this jump table. 2035 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2036 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2037 ->createJumpTableIndex(DestBBs); 2038 2039 // Set the jump table information so that we can codegen it as a second 2040 // MachineBasicBlock 2041 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2042 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2043 if (CR.CaseBB == SwitchBB) 2044 visitJumpTableHeader(JT, JTH, SwitchBB); 2045 2046 JTCases.push_back(JumpTableBlock(JTH, JT)); 2047 2048 return true; 2049} 2050 2051/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2052/// 2 subtrees. 2053bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2054 CaseRecVector& WorkList, 2055 const Value* SV, 2056 MachineBasicBlock *Default, 2057 MachineBasicBlock *SwitchBB) { 2058 // Get the MachineFunction which holds the current MBB. This is used when 2059 // inserting any additional MBBs necessary to represent the switch. 2060 MachineFunction *CurMF = FuncInfo.MF; 2061 2062 // Figure out which block is immediately after the current one. 2063 MachineFunction::iterator BBI = CR.CaseBB; 2064 ++BBI; 2065 2066 Case& FrontCase = *CR.Range.first; 2067 Case& BackCase = *(CR.Range.second-1); 2068 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2069 2070 // Size is the number of Cases represented by this range. 2071 unsigned Size = CR.Range.second - CR.Range.first; 2072 2073 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2074 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2075 double FMetric = 0; 2076 CaseItr Pivot = CR.Range.first + Size/2; 2077 2078 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2079 // (heuristically) allow us to emit JumpTable's later. 2080 APInt TSize(First.getBitWidth(), 0); 2081 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2082 I!=E; ++I) 2083 TSize += I->size(); 2084 2085 APInt LSize = FrontCase.size(); 2086 APInt RSize = TSize-LSize; 2087 DEBUG(dbgs() << "Selecting best pivot: \n" 2088 << "First: " << First << ", Last: " << Last <<'\n' 2089 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2090 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2091 J!=E; ++I, ++J) { 2092 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2093 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2094 APInt Range = ComputeRange(LEnd, RBegin); 2095 assert((Range - 2ULL).isNonNegative() && 2096 "Invalid case distance"); 2097 // Use volatile double here to avoid excess precision issues on some hosts, 2098 // e.g. that use 80-bit X87 registers. 2099 volatile double LDensity = 2100 (double)LSize.roundToDouble() / 2101 (LEnd - First + 1ULL).roundToDouble(); 2102 volatile double RDensity = 2103 (double)RSize.roundToDouble() / 2104 (Last - RBegin + 1ULL).roundToDouble(); 2105 double Metric = Range.logBase2()*(LDensity+RDensity); 2106 // Should always split in some non-trivial place 2107 DEBUG(dbgs() <<"=>Step\n" 2108 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2109 << "LDensity: " << LDensity 2110 << ", RDensity: " << RDensity << '\n' 2111 << "Metric: " << Metric << '\n'); 2112 if (FMetric < Metric) { 2113 Pivot = J; 2114 FMetric = Metric; 2115 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2116 } 2117 2118 LSize += J->size(); 2119 RSize -= J->size(); 2120 } 2121 if (areJTsAllowed(TLI)) { 2122 // If our case is dense we *really* should handle it earlier! 2123 assert((FMetric > 0) && "Should handle dense range earlier!"); 2124 } else { 2125 Pivot = CR.Range.first + Size/2; 2126 } 2127 2128 CaseRange LHSR(CR.Range.first, Pivot); 2129 CaseRange RHSR(Pivot, CR.Range.second); 2130 Constant *C = Pivot->Low; 2131 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2132 2133 // We know that we branch to the LHS if the Value being switched on is 2134 // less than the Pivot value, C. We use this to optimize our binary 2135 // tree a bit, by recognizing that if SV is greater than or equal to the 2136 // LHS's Case Value, and that Case Value is exactly one less than the 2137 // Pivot's Value, then we can branch directly to the LHS's Target, 2138 // rather than creating a leaf node for it. 2139 if ((LHSR.second - LHSR.first) == 1 && 2140 LHSR.first->High == CR.GE && 2141 cast<ConstantInt>(C)->getValue() == 2142 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2143 TrueBB = LHSR.first->BB; 2144 } else { 2145 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2146 CurMF->insert(BBI, TrueBB); 2147 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2148 2149 // Put SV in a virtual register to make it available from the new blocks. 2150 ExportFromCurrentBlock(SV); 2151 } 2152 2153 // Similar to the optimization above, if the Value being switched on is 2154 // known to be less than the Constant CR.LT, and the current Case Value 2155 // is CR.LT - 1, then we can branch directly to the target block for 2156 // the current Case Value, rather than emitting a RHS leaf node for it. 2157 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2158 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2159 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2160 FalseBB = RHSR.first->BB; 2161 } else { 2162 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2163 CurMF->insert(BBI, FalseBB); 2164 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2165 2166 // Put SV in a virtual register to make it available from the new blocks. 2167 ExportFromCurrentBlock(SV); 2168 } 2169 2170 // Create a CaseBlock record representing a conditional branch to 2171 // the LHS node if the value being switched on SV is less than C. 2172 // Otherwise, branch to LHS. 2173 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2174 2175 if (CR.CaseBB == SwitchBB) 2176 visitSwitchCase(CB, SwitchBB); 2177 else 2178 SwitchCases.push_back(CB); 2179 2180 return true; 2181} 2182 2183/// handleBitTestsSwitchCase - if current case range has few destination and 2184/// range span less, than machine word bitwidth, encode case range into series 2185/// of masks and emit bit tests with these masks. 2186bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2187 CaseRecVector& WorkList, 2188 const Value* SV, 2189 MachineBasicBlock* Default, 2190 MachineBasicBlock *SwitchBB){ 2191 EVT PTy = TLI.getPointerTy(); 2192 unsigned IntPtrBits = PTy.getSizeInBits(); 2193 2194 Case& FrontCase = *CR.Range.first; 2195 Case& BackCase = *(CR.Range.second-1); 2196 2197 // Get the MachineFunction which holds the current MBB. This is used when 2198 // inserting any additional MBBs necessary to represent the switch. 2199 MachineFunction *CurMF = FuncInfo.MF; 2200 2201 // If target does not have legal shift left, do not emit bit tests at all. 2202 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2203 return false; 2204 2205 size_t numCmps = 0; 2206 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2207 I!=E; ++I) { 2208 // Single case counts one, case range - two. 2209 numCmps += (I->Low == I->High ? 1 : 2); 2210 } 2211 2212 // Count unique destinations 2213 SmallSet<MachineBasicBlock*, 4> Dests; 2214 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2215 Dests.insert(I->BB); 2216 if (Dests.size() > 3) 2217 // Don't bother the code below, if there are too much unique destinations 2218 return false; 2219 } 2220 DEBUG(dbgs() << "Total number of unique destinations: " 2221 << Dests.size() << '\n' 2222 << "Total number of comparisons: " << numCmps << '\n'); 2223 2224 // Compute span of values. 2225 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2226 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2227 APInt cmpRange = maxValue - minValue; 2228 2229 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2230 << "Low bound: " << minValue << '\n' 2231 << "High bound: " << maxValue << '\n'); 2232 2233 if (cmpRange.uge(IntPtrBits) || 2234 (!(Dests.size() == 1 && numCmps >= 3) && 2235 !(Dests.size() == 2 && numCmps >= 5) && 2236 !(Dests.size() >= 3 && numCmps >= 6))) 2237 return false; 2238 2239 DEBUG(dbgs() << "Emitting bit tests\n"); 2240 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2241 2242 // Optimize the case where all the case values fit in a 2243 // word without having to subtract minValue. In this case, 2244 // we can optimize away the subtraction. 2245 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2246 cmpRange = maxValue; 2247 } else { 2248 lowBound = minValue; 2249 } 2250 2251 CaseBitsVector CasesBits; 2252 unsigned i, count = 0; 2253 2254 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2255 MachineBasicBlock* Dest = I->BB; 2256 for (i = 0; i < count; ++i) 2257 if (Dest == CasesBits[i].BB) 2258 break; 2259 2260 if (i == count) { 2261 assert((count < 3) && "Too much destinations to test!"); 2262 CasesBits.push_back(CaseBits(0, Dest, 0)); 2263 count++; 2264 } 2265 2266 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2267 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2268 2269 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2270 uint64_t hi = (highValue - lowBound).getZExtValue(); 2271 2272 for (uint64_t j = lo; j <= hi; j++) { 2273 CasesBits[i].Mask |= 1ULL << j; 2274 CasesBits[i].Bits++; 2275 } 2276 2277 } 2278 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2279 2280 BitTestInfo BTC; 2281 2282 // Figure out which block is immediately after the current one. 2283 MachineFunction::iterator BBI = CR.CaseBB; 2284 ++BBI; 2285 2286 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2287 2288 DEBUG(dbgs() << "Cases:\n"); 2289 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2290 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2291 << ", Bits: " << CasesBits[i].Bits 2292 << ", BB: " << CasesBits[i].BB << '\n'); 2293 2294 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2295 CurMF->insert(BBI, CaseBB); 2296 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2297 CaseBB, 2298 CasesBits[i].BB)); 2299 2300 // Put SV in a virtual register to make it available from the new blocks. 2301 ExportFromCurrentBlock(SV); 2302 } 2303 2304 BitTestBlock BTB(lowBound, cmpRange, SV, 2305 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2306 CR.CaseBB, Default, BTC); 2307 2308 if (CR.CaseBB == SwitchBB) 2309 visitBitTestHeader(BTB, SwitchBB); 2310 2311 BitTestCases.push_back(BTB); 2312 2313 return true; 2314} 2315 2316/// Clusterify - Transform simple list of Cases into list of CaseRange's 2317size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2318 const SwitchInst& SI) { 2319 size_t numCmps = 0; 2320 2321 // Start with "simple" cases 2322 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2323 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2324 Cases.push_back(Case(SI.getSuccessorValue(i), 2325 SI.getSuccessorValue(i), 2326 SMBB)); 2327 } 2328 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2329 2330 // Merge case into clusters 2331 if (Cases.size() >= 2) 2332 // Must recompute end() each iteration because it may be 2333 // invalidated by erase if we hold on to it 2334 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2335 J != Cases.end(); ) { 2336 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2337 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2338 MachineBasicBlock* nextBB = J->BB; 2339 MachineBasicBlock* currentBB = I->BB; 2340 2341 // If the two neighboring cases go to the same destination, merge them 2342 // into a single case. 2343 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2344 I->High = J->High; 2345 J = Cases.erase(J); 2346 } else { 2347 I = J++; 2348 } 2349 } 2350 2351 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2352 if (I->Low != I->High) 2353 // A range counts double, since it requires two compares. 2354 ++numCmps; 2355 } 2356 2357 return numCmps; 2358} 2359 2360void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2361 MachineBasicBlock *Last) { 2362 // Update JTCases. 2363 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2364 if (JTCases[i].first.HeaderBB == First) 2365 JTCases[i].first.HeaderBB = Last; 2366 2367 // Update BitTestCases. 2368 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2369 if (BitTestCases[i].Parent == First) 2370 BitTestCases[i].Parent = Last; 2371} 2372 2373void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2374 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2375 2376 // Figure out which block is immediately after the current one. 2377 MachineBasicBlock *NextBlock = 0; 2378 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2379 2380 // If there is only the default destination, branch to it if it is not the 2381 // next basic block. Otherwise, just fall through. 2382 if (SI.getNumOperands() == 2) { 2383 // Update machine-CFG edges. 2384 2385 // If this is not a fall-through branch, emit the branch. 2386 SwitchMBB->addSuccessor(Default); 2387 if (Default != NextBlock) 2388 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2389 MVT::Other, getControlRoot(), 2390 DAG.getBasicBlock(Default))); 2391 2392 return; 2393 } 2394 2395 // If there are any non-default case statements, create a vector of Cases 2396 // representing each one, and sort the vector so that we can efficiently 2397 // create a binary search tree from them. 2398 CaseVector Cases; 2399 size_t numCmps = Clusterify(Cases, SI); 2400 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2401 << ". Total compares: " << numCmps << '\n'); 2402 numCmps = 0; 2403 2404 // Get the Value to be switched on and default basic blocks, which will be 2405 // inserted into CaseBlock records, representing basic blocks in the binary 2406 // search tree. 2407 const Value *SV = SI.getOperand(0); 2408 2409 // Push the initial CaseRec onto the worklist 2410 CaseRecVector WorkList; 2411 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2412 CaseRange(Cases.begin(),Cases.end()))); 2413 2414 while (!WorkList.empty()) { 2415 // Grab a record representing a case range to process off the worklist 2416 CaseRec CR = WorkList.back(); 2417 WorkList.pop_back(); 2418 2419 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2420 continue; 2421 2422 // If the range has few cases (two or less) emit a series of specific 2423 // tests. 2424 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2425 continue; 2426 2427 // If the switch has more than 5 blocks, and at least 40% dense, and the 2428 // target supports indirect branches, then emit a jump table rather than 2429 // lowering the switch to a binary tree of conditional branches. 2430 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2431 continue; 2432 2433 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2434 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2435 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2436 } 2437} 2438 2439void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2440 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2441 2442 // Update machine-CFG edges with unique successors. 2443 SmallVector<BasicBlock*, 32> succs; 2444 succs.reserve(I.getNumSuccessors()); 2445 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2446 succs.push_back(I.getSuccessor(i)); 2447 array_pod_sort(succs.begin(), succs.end()); 2448 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2449 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2450 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2451 addSuccessorWithWeight(IndirectBrMBB, Succ); 2452 } 2453 2454 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2455 MVT::Other, getControlRoot(), 2456 getValue(I.getAddress()))); 2457} 2458 2459void SelectionDAGBuilder::visitFSub(const User &I) { 2460 // -0.0 - X --> fneg 2461 Type *Ty = I.getType(); 2462 if (isa<Constant>(I.getOperand(0)) && 2463 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2464 SDValue Op2 = getValue(I.getOperand(1)); 2465 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2466 Op2.getValueType(), Op2)); 2467 return; 2468 } 2469 2470 visitBinary(I, ISD::FSUB); 2471} 2472 2473void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2474 SDValue Op1 = getValue(I.getOperand(0)); 2475 SDValue Op2 = getValue(I.getOperand(1)); 2476 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2477 Op1.getValueType(), Op1, Op2)); 2478} 2479 2480void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2481 SDValue Op1 = getValue(I.getOperand(0)); 2482 SDValue Op2 = getValue(I.getOperand(1)); 2483 2484 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2485 2486 // Coerce the shift amount to the right type if we can. 2487 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2488 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2489 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2490 DebugLoc DL = getCurDebugLoc(); 2491 2492 // If the operand is smaller than the shift count type, promote it. 2493 if (ShiftSize > Op2Size) 2494 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2495 2496 // If the operand is larger than the shift count type but the shift 2497 // count type has enough bits to represent any shift value, truncate 2498 // it now. This is a common case and it exposes the truncate to 2499 // optimization early. 2500 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2501 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2502 // Otherwise we'll need to temporarily settle for some other convenient 2503 // type. Type legalization will make adjustments once the shiftee is split. 2504 else 2505 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2506 } 2507 2508 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2509 Op1.getValueType(), Op1, Op2)); 2510} 2511 2512void SelectionDAGBuilder::visitSDiv(const User &I) { 2513 SDValue Op1 = getValue(I.getOperand(0)); 2514 SDValue Op2 = getValue(I.getOperand(1)); 2515 2516 // Turn exact SDivs into multiplications. 2517 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2518 // exact bit. 2519 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2520 !isa<ConstantSDNode>(Op1) && 2521 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2522 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2523 else 2524 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2525 Op1, Op2)); 2526} 2527 2528void SelectionDAGBuilder::visitICmp(const User &I) { 2529 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2530 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2531 predicate = IC->getPredicate(); 2532 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2533 predicate = ICmpInst::Predicate(IC->getPredicate()); 2534 SDValue Op1 = getValue(I.getOperand(0)); 2535 SDValue Op2 = getValue(I.getOperand(1)); 2536 ISD::CondCode Opcode = getICmpCondCode(predicate); 2537 2538 EVT DestVT = TLI.getValueType(I.getType()); 2539 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2540} 2541 2542void SelectionDAGBuilder::visitFCmp(const User &I) { 2543 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2544 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2545 predicate = FC->getPredicate(); 2546 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2547 predicate = FCmpInst::Predicate(FC->getPredicate()); 2548 SDValue Op1 = getValue(I.getOperand(0)); 2549 SDValue Op2 = getValue(I.getOperand(1)); 2550 ISD::CondCode Condition = getFCmpCondCode(predicate); 2551 EVT DestVT = TLI.getValueType(I.getType()); 2552 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2553} 2554 2555void SelectionDAGBuilder::visitSelect(const User &I) { 2556 SmallVector<EVT, 4> ValueVTs; 2557 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2558 unsigned NumValues = ValueVTs.size(); 2559 if (NumValues == 0) return; 2560 2561 SmallVector<SDValue, 4> Values(NumValues); 2562 SDValue Cond = getValue(I.getOperand(0)); 2563 SDValue TrueVal = getValue(I.getOperand(1)); 2564 SDValue FalseVal = getValue(I.getOperand(2)); 2565 2566 for (unsigned i = 0; i != NumValues; ++i) 2567 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2568 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2569 Cond, 2570 SDValue(TrueVal.getNode(), 2571 TrueVal.getResNo() + i), 2572 SDValue(FalseVal.getNode(), 2573 FalseVal.getResNo() + i)); 2574 2575 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2576 DAG.getVTList(&ValueVTs[0], NumValues), 2577 &Values[0], NumValues)); 2578} 2579 2580void SelectionDAGBuilder::visitTrunc(const User &I) { 2581 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2582 SDValue N = getValue(I.getOperand(0)); 2583 EVT DestVT = TLI.getValueType(I.getType()); 2584 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2585} 2586 2587void SelectionDAGBuilder::visitZExt(const User &I) { 2588 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2589 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2590 SDValue N = getValue(I.getOperand(0)); 2591 EVT DestVT = TLI.getValueType(I.getType()); 2592 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2593} 2594 2595void SelectionDAGBuilder::visitSExt(const User &I) { 2596 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2597 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2598 SDValue N = getValue(I.getOperand(0)); 2599 EVT DestVT = TLI.getValueType(I.getType()); 2600 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2601} 2602 2603void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2604 // FPTrunc is never a no-op cast, no need to check 2605 SDValue N = getValue(I.getOperand(0)); 2606 EVT DestVT = TLI.getValueType(I.getType()); 2607 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2608 DestVT, N, DAG.getIntPtrConstant(0))); 2609} 2610 2611void SelectionDAGBuilder::visitFPExt(const User &I){ 2612 // FPTrunc is never a no-op cast, no need to check 2613 SDValue N = getValue(I.getOperand(0)); 2614 EVT DestVT = TLI.getValueType(I.getType()); 2615 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2616} 2617 2618void SelectionDAGBuilder::visitFPToUI(const User &I) { 2619 // FPToUI is never a no-op cast, no need to check 2620 SDValue N = getValue(I.getOperand(0)); 2621 EVT DestVT = TLI.getValueType(I.getType()); 2622 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2623} 2624 2625void SelectionDAGBuilder::visitFPToSI(const User &I) { 2626 // FPToSI is never a no-op cast, no need to check 2627 SDValue N = getValue(I.getOperand(0)); 2628 EVT DestVT = TLI.getValueType(I.getType()); 2629 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2630} 2631 2632void SelectionDAGBuilder::visitUIToFP(const User &I) { 2633 // UIToFP is never a no-op cast, no need to check 2634 SDValue N = getValue(I.getOperand(0)); 2635 EVT DestVT = TLI.getValueType(I.getType()); 2636 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2637} 2638 2639void SelectionDAGBuilder::visitSIToFP(const User &I){ 2640 // SIToFP is never a no-op cast, no need to check 2641 SDValue N = getValue(I.getOperand(0)); 2642 EVT DestVT = TLI.getValueType(I.getType()); 2643 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2644} 2645 2646void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2647 // What to do depends on the size of the integer and the size of the pointer. 2648 // We can either truncate, zero extend, or no-op, accordingly. 2649 SDValue N = getValue(I.getOperand(0)); 2650 EVT DestVT = TLI.getValueType(I.getType()); 2651 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2652} 2653 2654void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2655 // What to do depends on the size of the integer and the size of the pointer. 2656 // We can either truncate, zero extend, or no-op, accordingly. 2657 SDValue N = getValue(I.getOperand(0)); 2658 EVT DestVT = TLI.getValueType(I.getType()); 2659 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2660} 2661 2662void SelectionDAGBuilder::visitBitCast(const User &I) { 2663 SDValue N = getValue(I.getOperand(0)); 2664 EVT DestVT = TLI.getValueType(I.getType()); 2665 2666 // BitCast assures us that source and destination are the same size so this is 2667 // either a BITCAST or a no-op. 2668 if (DestVT != N.getValueType()) 2669 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2670 DestVT, N)); // convert types. 2671 else 2672 setValue(&I, N); // noop cast. 2673} 2674 2675void SelectionDAGBuilder::visitInsertElement(const User &I) { 2676 SDValue InVec = getValue(I.getOperand(0)); 2677 SDValue InVal = getValue(I.getOperand(1)); 2678 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2679 TLI.getPointerTy(), 2680 getValue(I.getOperand(2))); 2681 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2682 TLI.getValueType(I.getType()), 2683 InVec, InVal, InIdx)); 2684} 2685 2686void SelectionDAGBuilder::visitExtractElement(const User &I) { 2687 SDValue InVec = getValue(I.getOperand(0)); 2688 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2689 TLI.getPointerTy(), 2690 getValue(I.getOperand(1))); 2691 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2692 TLI.getValueType(I.getType()), InVec, InIdx)); 2693} 2694 2695// Utility for visitShuffleVector - Returns true if the mask is mask starting 2696// from SIndx and increasing to the element length (undefs are allowed). 2697static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2698 unsigned MaskNumElts = Mask.size(); 2699 for (unsigned i = 0; i != MaskNumElts; ++i) 2700 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2701 return false; 2702 return true; 2703} 2704 2705void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2706 SmallVector<int, 8> Mask; 2707 SDValue Src1 = getValue(I.getOperand(0)); 2708 SDValue Src2 = getValue(I.getOperand(1)); 2709 2710 // Convert the ConstantVector mask operand into an array of ints, with -1 2711 // representing undef values. 2712 SmallVector<Constant*, 8> MaskElts; 2713 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2714 unsigned MaskNumElts = MaskElts.size(); 2715 for (unsigned i = 0; i != MaskNumElts; ++i) { 2716 if (isa<UndefValue>(MaskElts[i])) 2717 Mask.push_back(-1); 2718 else 2719 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2720 } 2721 2722 EVT VT = TLI.getValueType(I.getType()); 2723 EVT SrcVT = Src1.getValueType(); 2724 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2725 2726 if (SrcNumElts == MaskNumElts) { 2727 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2728 &Mask[0])); 2729 return; 2730 } 2731 2732 // Normalize the shuffle vector since mask and vector length don't match. 2733 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2734 // Mask is longer than the source vectors and is a multiple of the source 2735 // vectors. We can use concatenate vector to make the mask and vectors 2736 // lengths match. 2737 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2738 // The shuffle is concatenating two vectors together. 2739 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2740 VT, Src1, Src2)); 2741 return; 2742 } 2743 2744 // Pad both vectors with undefs to make them the same length as the mask. 2745 unsigned NumConcat = MaskNumElts / SrcNumElts; 2746 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2747 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2748 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2749 2750 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2751 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2752 MOps1[0] = Src1; 2753 MOps2[0] = Src2; 2754 2755 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2756 getCurDebugLoc(), VT, 2757 &MOps1[0], NumConcat); 2758 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2759 getCurDebugLoc(), VT, 2760 &MOps2[0], NumConcat); 2761 2762 // Readjust mask for new input vector length. 2763 SmallVector<int, 8> MappedOps; 2764 for (unsigned i = 0; i != MaskNumElts; ++i) { 2765 int Idx = Mask[i]; 2766 if (Idx < (int)SrcNumElts) 2767 MappedOps.push_back(Idx); 2768 else 2769 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2770 } 2771 2772 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2773 &MappedOps[0])); 2774 return; 2775 } 2776 2777 if (SrcNumElts > MaskNumElts) { 2778 // Analyze the access pattern of the vector to see if we can extract 2779 // two subvectors and do the shuffle. The analysis is done by calculating 2780 // the range of elements the mask access on both vectors. 2781 int MinRange[2] = { static_cast<int>(SrcNumElts+1), 2782 static_cast<int>(SrcNumElts+1)}; 2783 int MaxRange[2] = {-1, -1}; 2784 2785 for (unsigned i = 0; i != MaskNumElts; ++i) { 2786 int Idx = Mask[i]; 2787 int Input = 0; 2788 if (Idx < 0) 2789 continue; 2790 2791 if (Idx >= (int)SrcNumElts) { 2792 Input = 1; 2793 Idx -= SrcNumElts; 2794 } 2795 if (Idx > MaxRange[Input]) 2796 MaxRange[Input] = Idx; 2797 if (Idx < MinRange[Input]) 2798 MinRange[Input] = Idx; 2799 } 2800 2801 // Check if the access is smaller than the vector size and can we find 2802 // a reasonable extract index. 2803 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2804 // Extract. 2805 int StartIdx[2]; // StartIdx to extract from 2806 for (int Input=0; Input < 2; ++Input) { 2807 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2808 RangeUse[Input] = 0; // Unused 2809 StartIdx[Input] = 0; 2810 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2811 // Fits within range but we should see if we can find a good 2812 // start index that is a multiple of the mask length. 2813 if (MaxRange[Input] < (int)MaskNumElts) { 2814 RangeUse[Input] = 1; // Extract from beginning of the vector 2815 StartIdx[Input] = 0; 2816 } else { 2817 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2818 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2819 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2820 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2821 } 2822 } 2823 } 2824 2825 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2826 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2827 return; 2828 } 2829 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2830 // Extract appropriate subvector and generate a vector shuffle 2831 for (int Input=0; Input < 2; ++Input) { 2832 SDValue &Src = Input == 0 ? Src1 : Src2; 2833 if (RangeUse[Input] == 0) 2834 Src = DAG.getUNDEF(VT); 2835 else 2836 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2837 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2838 } 2839 2840 // Calculate new mask. 2841 SmallVector<int, 8> MappedOps; 2842 for (unsigned i = 0; i != MaskNumElts; ++i) { 2843 int Idx = Mask[i]; 2844 if (Idx < 0) 2845 MappedOps.push_back(Idx); 2846 else if (Idx < (int)SrcNumElts) 2847 MappedOps.push_back(Idx - StartIdx[0]); 2848 else 2849 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2850 } 2851 2852 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2853 &MappedOps[0])); 2854 return; 2855 } 2856 } 2857 2858 // We can't use either concat vectors or extract subvectors so fall back to 2859 // replacing the shuffle with extract and build vector. 2860 // to insert and build vector. 2861 EVT EltVT = VT.getVectorElementType(); 2862 EVT PtrVT = TLI.getPointerTy(); 2863 SmallVector<SDValue,8> Ops; 2864 for (unsigned i = 0; i != MaskNumElts; ++i) { 2865 if (Mask[i] < 0) { 2866 Ops.push_back(DAG.getUNDEF(EltVT)); 2867 } else { 2868 int Idx = Mask[i]; 2869 SDValue Res; 2870 2871 if (Idx < (int)SrcNumElts) 2872 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2873 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2874 else 2875 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2876 EltVT, Src2, 2877 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2878 2879 Ops.push_back(Res); 2880 } 2881 } 2882 2883 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2884 VT, &Ops[0], Ops.size())); 2885} 2886 2887void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2888 const Value *Op0 = I.getOperand(0); 2889 const Value *Op1 = I.getOperand(1); 2890 Type *AggTy = I.getType(); 2891 Type *ValTy = Op1->getType(); 2892 bool IntoUndef = isa<UndefValue>(Op0); 2893 bool FromUndef = isa<UndefValue>(Op1); 2894 2895 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 2896 2897 SmallVector<EVT, 4> AggValueVTs; 2898 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2899 SmallVector<EVT, 4> ValValueVTs; 2900 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2901 2902 unsigned NumAggValues = AggValueVTs.size(); 2903 unsigned NumValValues = ValValueVTs.size(); 2904 SmallVector<SDValue, 4> Values(NumAggValues); 2905 2906 SDValue Agg = getValue(Op0); 2907 unsigned i = 0; 2908 // Copy the beginning value(s) from the original aggregate. 2909 for (; i != LinearIndex; ++i) 2910 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2911 SDValue(Agg.getNode(), Agg.getResNo() + i); 2912 // Copy values from the inserted value(s). 2913 if (NumValValues) { 2914 SDValue Val = getValue(Op1); 2915 for (; i != LinearIndex + NumValValues; ++i) 2916 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2917 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2918 } 2919 // Copy remaining value(s) from the original aggregate. 2920 for (; i != NumAggValues; ++i) 2921 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2922 SDValue(Agg.getNode(), Agg.getResNo() + i); 2923 2924 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2925 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2926 &Values[0], NumAggValues)); 2927} 2928 2929void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2930 const Value *Op0 = I.getOperand(0); 2931 Type *AggTy = Op0->getType(); 2932 Type *ValTy = I.getType(); 2933 bool OutOfUndef = isa<UndefValue>(Op0); 2934 2935 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 2936 2937 SmallVector<EVT, 4> ValValueVTs; 2938 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2939 2940 unsigned NumValValues = ValValueVTs.size(); 2941 2942 // Ignore a extractvalue that produces an empty object 2943 if (!NumValValues) { 2944 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 2945 return; 2946 } 2947 2948 SmallVector<SDValue, 4> Values(NumValValues); 2949 2950 SDValue Agg = getValue(Op0); 2951 // Copy out the selected value(s). 2952 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2953 Values[i - LinearIndex] = 2954 OutOfUndef ? 2955 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2956 SDValue(Agg.getNode(), Agg.getResNo() + i); 2957 2958 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2959 DAG.getVTList(&ValValueVTs[0], NumValValues), 2960 &Values[0], NumValValues)); 2961} 2962 2963void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2964 SDValue N = getValue(I.getOperand(0)); 2965 Type *Ty = I.getOperand(0)->getType(); 2966 2967 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2968 OI != E; ++OI) { 2969 const Value *Idx = *OI; 2970 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 2971 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2972 if (Field) { 2973 // N = N + Offset 2974 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2975 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2976 DAG.getIntPtrConstant(Offset)); 2977 } 2978 2979 Ty = StTy->getElementType(Field); 2980 } else { 2981 Ty = cast<SequentialType>(Ty)->getElementType(); 2982 2983 // If this is a constant subscript, handle it quickly. 2984 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2985 if (CI->isZero()) continue; 2986 uint64_t Offs = 2987 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2988 SDValue OffsVal; 2989 EVT PTy = TLI.getPointerTy(); 2990 unsigned PtrBits = PTy.getSizeInBits(); 2991 if (PtrBits < 64) 2992 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2993 TLI.getPointerTy(), 2994 DAG.getConstant(Offs, MVT::i64)); 2995 else 2996 OffsVal = DAG.getIntPtrConstant(Offs); 2997 2998 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2999 OffsVal); 3000 continue; 3001 } 3002 3003 // N = N + Idx * ElementSize; 3004 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3005 TD->getTypeAllocSize(Ty)); 3006 SDValue IdxN = getValue(Idx); 3007 3008 // If the index is smaller or larger than intptr_t, truncate or extend 3009 // it. 3010 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3011 3012 // If this is a multiply by a power of two, turn it into a shl 3013 // immediately. This is a very common case. 3014 if (ElementSize != 1) { 3015 if (ElementSize.isPowerOf2()) { 3016 unsigned Amt = ElementSize.logBase2(); 3017 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3018 N.getValueType(), IdxN, 3019 DAG.getConstant(Amt, TLI.getPointerTy())); 3020 } else { 3021 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3022 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3023 N.getValueType(), IdxN, Scale); 3024 } 3025 } 3026 3027 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3028 N.getValueType(), N, IdxN); 3029 } 3030 } 3031 3032 setValue(&I, N); 3033} 3034 3035void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3036 // If this is a fixed sized alloca in the entry block of the function, 3037 // allocate it statically on the stack. 3038 if (FuncInfo.StaticAllocaMap.count(&I)) 3039 return; // getValue will auto-populate this. 3040 3041 Type *Ty = I.getAllocatedType(); 3042 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3043 unsigned Align = 3044 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3045 I.getAlignment()); 3046 3047 SDValue AllocSize = getValue(I.getArraySize()); 3048 3049 EVT IntPtr = TLI.getPointerTy(); 3050 if (AllocSize.getValueType() != IntPtr) 3051 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3052 3053 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3054 AllocSize, 3055 DAG.getConstant(TySize, IntPtr)); 3056 3057 // Handle alignment. If the requested alignment is less than or equal to 3058 // the stack alignment, ignore it. If the size is greater than or equal to 3059 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3060 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3061 if (Align <= StackAlign) 3062 Align = 0; 3063 3064 // Round the size of the allocation up to the stack alignment size 3065 // by add SA-1 to the size. 3066 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3067 AllocSize.getValueType(), AllocSize, 3068 DAG.getIntPtrConstant(StackAlign-1)); 3069 3070 // Mask out the low bits for alignment purposes. 3071 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3072 AllocSize.getValueType(), AllocSize, 3073 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3074 3075 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3076 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3077 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3078 VTs, Ops, 3); 3079 setValue(&I, DSA); 3080 DAG.setRoot(DSA.getValue(1)); 3081 3082 // Inform the Frame Information that we have just allocated a variable-sized 3083 // object. 3084 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3085} 3086 3087void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3088 const Value *SV = I.getOperand(0); 3089 SDValue Ptr = getValue(SV); 3090 3091 Type *Ty = I.getType(); 3092 3093 bool isVolatile = I.isVolatile(); 3094 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3095 unsigned Alignment = I.getAlignment(); 3096 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3097 3098 SmallVector<EVT, 4> ValueVTs; 3099 SmallVector<uint64_t, 4> Offsets; 3100 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3101 unsigned NumValues = ValueVTs.size(); 3102 if (NumValues == 0) 3103 return; 3104 3105 SDValue Root; 3106 bool ConstantMemory = false; 3107 if (I.isVolatile() || NumValues > MaxParallelChains) 3108 // Serialize volatile loads with other side effects. 3109 Root = getRoot(); 3110 else if (AA->pointsToConstantMemory( 3111 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3112 // Do not serialize (non-volatile) loads of constant memory with anything. 3113 Root = DAG.getEntryNode(); 3114 ConstantMemory = true; 3115 } else { 3116 // Do not serialize non-volatile loads against each other. 3117 Root = DAG.getRoot(); 3118 } 3119 3120 SmallVector<SDValue, 4> Values(NumValues); 3121 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3122 NumValues)); 3123 EVT PtrVT = Ptr.getValueType(); 3124 unsigned ChainI = 0; 3125 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3126 // Serializing loads here may result in excessive register pressure, and 3127 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3128 // could recover a bit by hoisting nodes upward in the chain by recognizing 3129 // they are side-effect free or do not alias. The optimizer should really 3130 // avoid this case by converting large object/array copies to llvm.memcpy 3131 // (MaxParallelChains should always remain as failsafe). 3132 if (ChainI == MaxParallelChains) { 3133 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3134 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3135 MVT::Other, &Chains[0], ChainI); 3136 Root = Chain; 3137 ChainI = 0; 3138 } 3139 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3140 PtrVT, Ptr, 3141 DAG.getConstant(Offsets[i], PtrVT)); 3142 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3143 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3144 isNonTemporal, Alignment, TBAAInfo); 3145 3146 Values[i] = L; 3147 Chains[ChainI] = L.getValue(1); 3148 } 3149 3150 if (!ConstantMemory) { 3151 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3152 MVT::Other, &Chains[0], ChainI); 3153 if (isVolatile) 3154 DAG.setRoot(Chain); 3155 else 3156 PendingLoads.push_back(Chain); 3157 } 3158 3159 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3160 DAG.getVTList(&ValueVTs[0], NumValues), 3161 &Values[0], NumValues)); 3162} 3163 3164void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3165 const Value *SrcV = I.getOperand(0); 3166 const Value *PtrV = I.getOperand(1); 3167 3168 SmallVector<EVT, 4> ValueVTs; 3169 SmallVector<uint64_t, 4> Offsets; 3170 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3171 unsigned NumValues = ValueVTs.size(); 3172 if (NumValues == 0) 3173 return; 3174 3175 // Get the lowered operands. Note that we do this after 3176 // checking if NumResults is zero, because with zero results 3177 // the operands won't have values in the map. 3178 SDValue Src = getValue(SrcV); 3179 SDValue Ptr = getValue(PtrV); 3180 3181 SDValue Root = getRoot(); 3182 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3183 NumValues)); 3184 EVT PtrVT = Ptr.getValueType(); 3185 bool isVolatile = I.isVolatile(); 3186 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3187 unsigned Alignment = I.getAlignment(); 3188 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3189 3190 unsigned ChainI = 0; 3191 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3192 // See visitLoad comments. 3193 if (ChainI == MaxParallelChains) { 3194 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3195 MVT::Other, &Chains[0], ChainI); 3196 Root = Chain; 3197 ChainI = 0; 3198 } 3199 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3200 DAG.getConstant(Offsets[i], PtrVT)); 3201 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3202 SDValue(Src.getNode(), Src.getResNo() + i), 3203 Add, MachinePointerInfo(PtrV, Offsets[i]), 3204 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3205 Chains[ChainI] = St; 3206 } 3207 3208 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3209 MVT::Other, &Chains[0], ChainI); 3210 ++SDNodeOrder; 3211 AssignOrderingToNode(StoreNode.getNode()); 3212 DAG.setRoot(StoreNode); 3213} 3214 3215void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3216 llvm_unreachable("Not implemented yet"); 3217} 3218 3219/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3220/// node. 3221void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3222 unsigned Intrinsic) { 3223 bool HasChain = !I.doesNotAccessMemory(); 3224 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3225 3226 // Build the operand list. 3227 SmallVector<SDValue, 8> Ops; 3228 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3229 if (OnlyLoad) { 3230 // We don't need to serialize loads against other loads. 3231 Ops.push_back(DAG.getRoot()); 3232 } else { 3233 Ops.push_back(getRoot()); 3234 } 3235 } 3236 3237 // Info is set by getTgtMemInstrinsic 3238 TargetLowering::IntrinsicInfo Info; 3239 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3240 3241 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3242 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3243 Info.opc == ISD::INTRINSIC_W_CHAIN) 3244 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3245 3246 // Add all operands of the call to the operand list. 3247 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3248 SDValue Op = getValue(I.getArgOperand(i)); 3249 assert(TLI.isTypeLegal(Op.getValueType()) && 3250 "Intrinsic uses a non-legal type?"); 3251 Ops.push_back(Op); 3252 } 3253 3254 SmallVector<EVT, 4> ValueVTs; 3255 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3256#ifndef NDEBUG 3257 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3258 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3259 "Intrinsic uses a non-legal type?"); 3260 } 3261#endif // NDEBUG 3262 3263 if (HasChain) 3264 ValueVTs.push_back(MVT::Other); 3265 3266 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3267 3268 // Create the node. 3269 SDValue Result; 3270 if (IsTgtIntrinsic) { 3271 // This is target intrinsic that touches memory 3272 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3273 VTs, &Ops[0], Ops.size(), 3274 Info.memVT, 3275 MachinePointerInfo(Info.ptrVal, Info.offset), 3276 Info.align, Info.vol, 3277 Info.readMem, Info.writeMem); 3278 } else if (!HasChain) { 3279 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3280 VTs, &Ops[0], Ops.size()); 3281 } else if (!I.getType()->isVoidTy()) { 3282 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3283 VTs, &Ops[0], Ops.size()); 3284 } else { 3285 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3286 VTs, &Ops[0], Ops.size()); 3287 } 3288 3289 if (HasChain) { 3290 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3291 if (OnlyLoad) 3292 PendingLoads.push_back(Chain); 3293 else 3294 DAG.setRoot(Chain); 3295 } 3296 3297 if (!I.getType()->isVoidTy()) { 3298 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3299 EVT VT = TLI.getValueType(PTy); 3300 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3301 } 3302 3303 setValue(&I, Result); 3304 } 3305} 3306 3307/// GetSignificand - Get the significand and build it into a floating-point 3308/// number with exponent of 1: 3309/// 3310/// Op = (Op & 0x007fffff) | 0x3f800000; 3311/// 3312/// where Op is the hexidecimal representation of floating point value. 3313static SDValue 3314GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3315 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3316 DAG.getConstant(0x007fffff, MVT::i32)); 3317 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3318 DAG.getConstant(0x3f800000, MVT::i32)); 3319 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3320} 3321 3322/// GetExponent - Get the exponent: 3323/// 3324/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3325/// 3326/// where Op is the hexidecimal representation of floating point value. 3327static SDValue 3328GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3329 DebugLoc dl) { 3330 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3331 DAG.getConstant(0x7f800000, MVT::i32)); 3332 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3333 DAG.getConstant(23, TLI.getPointerTy())); 3334 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3335 DAG.getConstant(127, MVT::i32)); 3336 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3337} 3338 3339/// getF32Constant - Get 32-bit floating point constant. 3340static SDValue 3341getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3342 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3343} 3344 3345/// Inlined utility function to implement binary input atomic intrinsics for 3346/// visitIntrinsicCall: I is a call instruction 3347/// Op is the associated NodeType for I 3348const char * 3349SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3350 ISD::NodeType Op) { 3351 SDValue Root = getRoot(); 3352 SDValue L = 3353 DAG.getAtomic(Op, getCurDebugLoc(), 3354 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3355 Root, 3356 getValue(I.getArgOperand(0)), 3357 getValue(I.getArgOperand(1)), 3358 I.getArgOperand(0)); 3359 setValue(&I, L); 3360 DAG.setRoot(L.getValue(1)); 3361 return 0; 3362} 3363 3364// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3365const char * 3366SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3367 SDValue Op1 = getValue(I.getArgOperand(0)); 3368 SDValue Op2 = getValue(I.getArgOperand(1)); 3369 3370 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3371 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3372 return 0; 3373} 3374 3375/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3376/// limited-precision mode. 3377void 3378SelectionDAGBuilder::visitExp(const CallInst &I) { 3379 SDValue result; 3380 DebugLoc dl = getCurDebugLoc(); 3381 3382 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3383 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3384 SDValue Op = getValue(I.getArgOperand(0)); 3385 3386 // Put the exponent in the right bit position for later addition to the 3387 // final result: 3388 // 3389 // #define LOG2OFe 1.4426950f 3390 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3391 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3392 getF32Constant(DAG, 0x3fb8aa3b)); 3393 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3394 3395 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3396 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3397 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3398 3399 // IntegerPartOfX <<= 23; 3400 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3401 DAG.getConstant(23, TLI.getPointerTy())); 3402 3403 if (LimitFloatPrecision <= 6) { 3404 // For floating-point precision of 6: 3405 // 3406 // TwoToFractionalPartOfX = 3407 // 0.997535578f + 3408 // (0.735607626f + 0.252464424f * x) * x; 3409 // 3410 // error 0.0144103317, which is 6 bits 3411 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3412 getF32Constant(DAG, 0x3e814304)); 3413 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3414 getF32Constant(DAG, 0x3f3c50c8)); 3415 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3416 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3417 getF32Constant(DAG, 0x3f7f5e7e)); 3418 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3419 3420 // Add the exponent into the result in integer domain. 3421 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3422 TwoToFracPartOfX, IntegerPartOfX); 3423 3424 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3425 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3426 // For floating-point precision of 12: 3427 // 3428 // TwoToFractionalPartOfX = 3429 // 0.999892986f + 3430 // (0.696457318f + 3431 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3432 // 3433 // 0.000107046256 error, which is 13 to 14 bits 3434 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3435 getF32Constant(DAG, 0x3da235e3)); 3436 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3437 getF32Constant(DAG, 0x3e65b8f3)); 3438 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3439 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3440 getF32Constant(DAG, 0x3f324b07)); 3441 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3442 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3443 getF32Constant(DAG, 0x3f7ff8fd)); 3444 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3445 3446 // Add the exponent into the result in integer domain. 3447 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3448 TwoToFracPartOfX, IntegerPartOfX); 3449 3450 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3451 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3452 // For floating-point precision of 18: 3453 // 3454 // TwoToFractionalPartOfX = 3455 // 0.999999982f + 3456 // (0.693148872f + 3457 // (0.240227044f + 3458 // (0.554906021e-1f + 3459 // (0.961591928e-2f + 3460 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3461 // 3462 // error 2.47208000*10^(-7), which is better than 18 bits 3463 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3464 getF32Constant(DAG, 0x3924b03e)); 3465 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3466 getF32Constant(DAG, 0x3ab24b87)); 3467 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3468 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3469 getF32Constant(DAG, 0x3c1d8c17)); 3470 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3471 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3472 getF32Constant(DAG, 0x3d634a1d)); 3473 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3474 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3475 getF32Constant(DAG, 0x3e75fe14)); 3476 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3477 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3478 getF32Constant(DAG, 0x3f317234)); 3479 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3480 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3481 getF32Constant(DAG, 0x3f800000)); 3482 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3483 MVT::i32, t13); 3484 3485 // Add the exponent into the result in integer domain. 3486 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3487 TwoToFracPartOfX, IntegerPartOfX); 3488 3489 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3490 } 3491 } else { 3492 // No special expansion. 3493 result = DAG.getNode(ISD::FEXP, dl, 3494 getValue(I.getArgOperand(0)).getValueType(), 3495 getValue(I.getArgOperand(0))); 3496 } 3497 3498 setValue(&I, result); 3499} 3500 3501/// visitLog - Lower a log intrinsic. Handles the special sequences for 3502/// limited-precision mode. 3503void 3504SelectionDAGBuilder::visitLog(const CallInst &I) { 3505 SDValue result; 3506 DebugLoc dl = getCurDebugLoc(); 3507 3508 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3509 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3510 SDValue Op = getValue(I.getArgOperand(0)); 3511 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3512 3513 // Scale the exponent by log(2) [0.69314718f]. 3514 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3515 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3516 getF32Constant(DAG, 0x3f317218)); 3517 3518 // Get the significand and build it into a floating-point number with 3519 // exponent of 1. 3520 SDValue X = GetSignificand(DAG, Op1, dl); 3521 3522 if (LimitFloatPrecision <= 6) { 3523 // For floating-point precision of 6: 3524 // 3525 // LogofMantissa = 3526 // -1.1609546f + 3527 // (1.4034025f - 0.23903021f * x) * x; 3528 // 3529 // error 0.0034276066, which is better than 8 bits 3530 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3531 getF32Constant(DAG, 0xbe74c456)); 3532 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3533 getF32Constant(DAG, 0x3fb3a2b1)); 3534 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3535 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3536 getF32Constant(DAG, 0x3f949a29)); 3537 3538 result = DAG.getNode(ISD::FADD, dl, 3539 MVT::f32, LogOfExponent, LogOfMantissa); 3540 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3541 // For floating-point precision of 12: 3542 // 3543 // LogOfMantissa = 3544 // -1.7417939f + 3545 // (2.8212026f + 3546 // (-1.4699568f + 3547 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3548 // 3549 // error 0.000061011436, which is 14 bits 3550 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3551 getF32Constant(DAG, 0xbd67b6d6)); 3552 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3553 getF32Constant(DAG, 0x3ee4f4b8)); 3554 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3555 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3556 getF32Constant(DAG, 0x3fbc278b)); 3557 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3558 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3559 getF32Constant(DAG, 0x40348e95)); 3560 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3561 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3562 getF32Constant(DAG, 0x3fdef31a)); 3563 3564 result = DAG.getNode(ISD::FADD, dl, 3565 MVT::f32, LogOfExponent, LogOfMantissa); 3566 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3567 // For floating-point precision of 18: 3568 // 3569 // LogOfMantissa = 3570 // -2.1072184f + 3571 // (4.2372794f + 3572 // (-3.7029485f + 3573 // (2.2781945f + 3574 // (-0.87823314f + 3575 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3576 // 3577 // error 0.0000023660568, which is better than 18 bits 3578 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3579 getF32Constant(DAG, 0xbc91e5ac)); 3580 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3581 getF32Constant(DAG, 0x3e4350aa)); 3582 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3583 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3584 getF32Constant(DAG, 0x3f60d3e3)); 3585 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3586 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3587 getF32Constant(DAG, 0x4011cdf0)); 3588 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3589 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3590 getF32Constant(DAG, 0x406cfd1c)); 3591 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3592 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3593 getF32Constant(DAG, 0x408797cb)); 3594 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3595 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3596 getF32Constant(DAG, 0x4006dcab)); 3597 3598 result = DAG.getNode(ISD::FADD, dl, 3599 MVT::f32, LogOfExponent, LogOfMantissa); 3600 } 3601 } else { 3602 // No special expansion. 3603 result = DAG.getNode(ISD::FLOG, dl, 3604 getValue(I.getArgOperand(0)).getValueType(), 3605 getValue(I.getArgOperand(0))); 3606 } 3607 3608 setValue(&I, result); 3609} 3610 3611/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3612/// limited-precision mode. 3613void 3614SelectionDAGBuilder::visitLog2(const CallInst &I) { 3615 SDValue result; 3616 DebugLoc dl = getCurDebugLoc(); 3617 3618 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3619 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3620 SDValue Op = getValue(I.getArgOperand(0)); 3621 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3622 3623 // Get the exponent. 3624 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3625 3626 // Get the significand and build it into a floating-point number with 3627 // exponent of 1. 3628 SDValue X = GetSignificand(DAG, Op1, dl); 3629 3630 // Different possible minimax approximations of significand in 3631 // floating-point for various degrees of accuracy over [1,2]. 3632 if (LimitFloatPrecision <= 6) { 3633 // For floating-point precision of 6: 3634 // 3635 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3636 // 3637 // error 0.0049451742, which is more than 7 bits 3638 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3639 getF32Constant(DAG, 0xbeb08fe0)); 3640 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3641 getF32Constant(DAG, 0x40019463)); 3642 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3643 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3644 getF32Constant(DAG, 0x3fd6633d)); 3645 3646 result = DAG.getNode(ISD::FADD, dl, 3647 MVT::f32, LogOfExponent, Log2ofMantissa); 3648 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3649 // For floating-point precision of 12: 3650 // 3651 // Log2ofMantissa = 3652 // -2.51285454f + 3653 // (4.07009056f + 3654 // (-2.12067489f + 3655 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3656 // 3657 // error 0.0000876136000, which is better than 13 bits 3658 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3659 getF32Constant(DAG, 0xbda7262e)); 3660 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3661 getF32Constant(DAG, 0x3f25280b)); 3662 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3663 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3664 getF32Constant(DAG, 0x4007b923)); 3665 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3666 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3667 getF32Constant(DAG, 0x40823e2f)); 3668 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3669 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3670 getF32Constant(DAG, 0x4020d29c)); 3671 3672 result = DAG.getNode(ISD::FADD, dl, 3673 MVT::f32, LogOfExponent, Log2ofMantissa); 3674 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3675 // For floating-point precision of 18: 3676 // 3677 // Log2ofMantissa = 3678 // -3.0400495f + 3679 // (6.1129976f + 3680 // (-5.3420409f + 3681 // (3.2865683f + 3682 // (-1.2669343f + 3683 // (0.27515199f - 3684 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3685 // 3686 // error 0.0000018516, which is better than 18 bits 3687 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3688 getF32Constant(DAG, 0xbcd2769e)); 3689 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3690 getF32Constant(DAG, 0x3e8ce0b9)); 3691 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3692 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3693 getF32Constant(DAG, 0x3fa22ae7)); 3694 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3695 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3696 getF32Constant(DAG, 0x40525723)); 3697 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3698 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3699 getF32Constant(DAG, 0x40aaf200)); 3700 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3701 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3702 getF32Constant(DAG, 0x40c39dad)); 3703 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3704 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3705 getF32Constant(DAG, 0x4042902c)); 3706 3707 result = DAG.getNode(ISD::FADD, dl, 3708 MVT::f32, LogOfExponent, Log2ofMantissa); 3709 } 3710 } else { 3711 // No special expansion. 3712 result = DAG.getNode(ISD::FLOG2, dl, 3713 getValue(I.getArgOperand(0)).getValueType(), 3714 getValue(I.getArgOperand(0))); 3715 } 3716 3717 setValue(&I, result); 3718} 3719 3720/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3721/// limited-precision mode. 3722void 3723SelectionDAGBuilder::visitLog10(const CallInst &I) { 3724 SDValue result; 3725 DebugLoc dl = getCurDebugLoc(); 3726 3727 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3728 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3729 SDValue Op = getValue(I.getArgOperand(0)); 3730 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3731 3732 // Scale the exponent by log10(2) [0.30102999f]. 3733 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3734 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3735 getF32Constant(DAG, 0x3e9a209a)); 3736 3737 // Get the significand and build it into a floating-point number with 3738 // exponent of 1. 3739 SDValue X = GetSignificand(DAG, Op1, dl); 3740 3741 if (LimitFloatPrecision <= 6) { 3742 // For floating-point precision of 6: 3743 // 3744 // Log10ofMantissa = 3745 // -0.50419619f + 3746 // (0.60948995f - 0.10380950f * x) * x; 3747 // 3748 // error 0.0014886165, which is 6 bits 3749 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3750 getF32Constant(DAG, 0xbdd49a13)); 3751 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3752 getF32Constant(DAG, 0x3f1c0789)); 3753 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3754 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3755 getF32Constant(DAG, 0x3f011300)); 3756 3757 result = DAG.getNode(ISD::FADD, dl, 3758 MVT::f32, LogOfExponent, Log10ofMantissa); 3759 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3760 // For floating-point precision of 12: 3761 // 3762 // Log10ofMantissa = 3763 // -0.64831180f + 3764 // (0.91751397f + 3765 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3766 // 3767 // error 0.00019228036, which is better than 12 bits 3768 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3769 getF32Constant(DAG, 0x3d431f31)); 3770 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3771 getF32Constant(DAG, 0x3ea21fb2)); 3772 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3773 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3774 getF32Constant(DAG, 0x3f6ae232)); 3775 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3776 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3777 getF32Constant(DAG, 0x3f25f7c3)); 3778 3779 result = DAG.getNode(ISD::FADD, dl, 3780 MVT::f32, LogOfExponent, Log10ofMantissa); 3781 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3782 // For floating-point precision of 18: 3783 // 3784 // Log10ofMantissa = 3785 // -0.84299375f + 3786 // (1.5327582f + 3787 // (-1.0688956f + 3788 // (0.49102474f + 3789 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3790 // 3791 // error 0.0000037995730, which is better than 18 bits 3792 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3793 getF32Constant(DAG, 0x3c5d51ce)); 3794 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3795 getF32Constant(DAG, 0x3e00685a)); 3796 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3797 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3798 getF32Constant(DAG, 0x3efb6798)); 3799 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3800 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3801 getF32Constant(DAG, 0x3f88d192)); 3802 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3803 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3804 getF32Constant(DAG, 0x3fc4316c)); 3805 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3806 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3807 getF32Constant(DAG, 0x3f57ce70)); 3808 3809 result = DAG.getNode(ISD::FADD, dl, 3810 MVT::f32, LogOfExponent, Log10ofMantissa); 3811 } 3812 } else { 3813 // No special expansion. 3814 result = DAG.getNode(ISD::FLOG10, dl, 3815 getValue(I.getArgOperand(0)).getValueType(), 3816 getValue(I.getArgOperand(0))); 3817 } 3818 3819 setValue(&I, result); 3820} 3821 3822/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3823/// limited-precision mode. 3824void 3825SelectionDAGBuilder::visitExp2(const CallInst &I) { 3826 SDValue result; 3827 DebugLoc dl = getCurDebugLoc(); 3828 3829 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3830 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3831 SDValue Op = getValue(I.getArgOperand(0)); 3832 3833 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3834 3835 // FractionalPartOfX = x - (float)IntegerPartOfX; 3836 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3837 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3838 3839 // IntegerPartOfX <<= 23; 3840 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3841 DAG.getConstant(23, TLI.getPointerTy())); 3842 3843 if (LimitFloatPrecision <= 6) { 3844 // For floating-point precision of 6: 3845 // 3846 // TwoToFractionalPartOfX = 3847 // 0.997535578f + 3848 // (0.735607626f + 0.252464424f * x) * x; 3849 // 3850 // error 0.0144103317, which is 6 bits 3851 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3852 getF32Constant(DAG, 0x3e814304)); 3853 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3854 getF32Constant(DAG, 0x3f3c50c8)); 3855 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3856 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3857 getF32Constant(DAG, 0x3f7f5e7e)); 3858 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3859 SDValue TwoToFractionalPartOfX = 3860 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3861 3862 result = DAG.getNode(ISD::BITCAST, dl, 3863 MVT::f32, TwoToFractionalPartOfX); 3864 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3865 // For floating-point precision of 12: 3866 // 3867 // TwoToFractionalPartOfX = 3868 // 0.999892986f + 3869 // (0.696457318f + 3870 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3871 // 3872 // error 0.000107046256, which is 13 to 14 bits 3873 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3874 getF32Constant(DAG, 0x3da235e3)); 3875 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3876 getF32Constant(DAG, 0x3e65b8f3)); 3877 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3878 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3879 getF32Constant(DAG, 0x3f324b07)); 3880 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3881 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3882 getF32Constant(DAG, 0x3f7ff8fd)); 3883 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3884 SDValue TwoToFractionalPartOfX = 3885 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3886 3887 result = DAG.getNode(ISD::BITCAST, dl, 3888 MVT::f32, TwoToFractionalPartOfX); 3889 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3890 // For floating-point precision of 18: 3891 // 3892 // TwoToFractionalPartOfX = 3893 // 0.999999982f + 3894 // (0.693148872f + 3895 // (0.240227044f + 3896 // (0.554906021e-1f + 3897 // (0.961591928e-2f + 3898 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3899 // error 2.47208000*10^(-7), which is better than 18 bits 3900 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3901 getF32Constant(DAG, 0x3924b03e)); 3902 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3903 getF32Constant(DAG, 0x3ab24b87)); 3904 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3905 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3906 getF32Constant(DAG, 0x3c1d8c17)); 3907 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3908 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3909 getF32Constant(DAG, 0x3d634a1d)); 3910 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3911 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3912 getF32Constant(DAG, 0x3e75fe14)); 3913 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3914 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3915 getF32Constant(DAG, 0x3f317234)); 3916 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3917 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3918 getF32Constant(DAG, 0x3f800000)); 3919 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 3920 SDValue TwoToFractionalPartOfX = 3921 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3922 3923 result = DAG.getNode(ISD::BITCAST, dl, 3924 MVT::f32, TwoToFractionalPartOfX); 3925 } 3926 } else { 3927 // No special expansion. 3928 result = DAG.getNode(ISD::FEXP2, dl, 3929 getValue(I.getArgOperand(0)).getValueType(), 3930 getValue(I.getArgOperand(0))); 3931 } 3932 3933 setValue(&I, result); 3934} 3935 3936/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3937/// limited-precision mode with x == 10.0f. 3938void 3939SelectionDAGBuilder::visitPow(const CallInst &I) { 3940 SDValue result; 3941 const Value *Val = I.getArgOperand(0); 3942 DebugLoc dl = getCurDebugLoc(); 3943 bool IsExp10 = false; 3944 3945 if (getValue(Val).getValueType() == MVT::f32 && 3946 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 3947 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3948 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3949 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3950 APFloat Ten(10.0f); 3951 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3952 } 3953 } 3954 } 3955 3956 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3957 SDValue Op = getValue(I.getArgOperand(1)); 3958 3959 // Put the exponent in the right bit position for later addition to the 3960 // final result: 3961 // 3962 // #define LOG2OF10 3.3219281f 3963 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3964 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3965 getF32Constant(DAG, 0x40549a78)); 3966 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3967 3968 // FractionalPartOfX = x - (float)IntegerPartOfX; 3969 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3970 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3971 3972 // IntegerPartOfX <<= 23; 3973 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3974 DAG.getConstant(23, TLI.getPointerTy())); 3975 3976 if (LimitFloatPrecision <= 6) { 3977 // For floating-point precision of 6: 3978 // 3979 // twoToFractionalPartOfX = 3980 // 0.997535578f + 3981 // (0.735607626f + 0.252464424f * x) * x; 3982 // 3983 // error 0.0144103317, which is 6 bits 3984 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3985 getF32Constant(DAG, 0x3e814304)); 3986 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3987 getF32Constant(DAG, 0x3f3c50c8)); 3988 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3989 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3990 getF32Constant(DAG, 0x3f7f5e7e)); 3991 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3992 SDValue TwoToFractionalPartOfX = 3993 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3994 3995 result = DAG.getNode(ISD::BITCAST, dl, 3996 MVT::f32, TwoToFractionalPartOfX); 3997 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3998 // For floating-point precision of 12: 3999 // 4000 // TwoToFractionalPartOfX = 4001 // 0.999892986f + 4002 // (0.696457318f + 4003 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4004 // 4005 // error 0.000107046256, which is 13 to 14 bits 4006 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4007 getF32Constant(DAG, 0x3da235e3)); 4008 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4009 getF32Constant(DAG, 0x3e65b8f3)); 4010 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4011 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4012 getF32Constant(DAG, 0x3f324b07)); 4013 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4014 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4015 getF32Constant(DAG, 0x3f7ff8fd)); 4016 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4017 SDValue TwoToFractionalPartOfX = 4018 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4019 4020 result = DAG.getNode(ISD::BITCAST, dl, 4021 MVT::f32, TwoToFractionalPartOfX); 4022 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4023 // For floating-point precision of 18: 4024 // 4025 // TwoToFractionalPartOfX = 4026 // 0.999999982f + 4027 // (0.693148872f + 4028 // (0.240227044f + 4029 // (0.554906021e-1f + 4030 // (0.961591928e-2f + 4031 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4032 // error 2.47208000*10^(-7), which is better than 18 bits 4033 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4034 getF32Constant(DAG, 0x3924b03e)); 4035 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4036 getF32Constant(DAG, 0x3ab24b87)); 4037 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4038 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4039 getF32Constant(DAG, 0x3c1d8c17)); 4040 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4041 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4042 getF32Constant(DAG, 0x3d634a1d)); 4043 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4044 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4045 getF32Constant(DAG, 0x3e75fe14)); 4046 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4047 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4048 getF32Constant(DAG, 0x3f317234)); 4049 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4050 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4051 getF32Constant(DAG, 0x3f800000)); 4052 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4053 SDValue TwoToFractionalPartOfX = 4054 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4055 4056 result = DAG.getNode(ISD::BITCAST, dl, 4057 MVT::f32, TwoToFractionalPartOfX); 4058 } 4059 } else { 4060 // No special expansion. 4061 result = DAG.getNode(ISD::FPOW, dl, 4062 getValue(I.getArgOperand(0)).getValueType(), 4063 getValue(I.getArgOperand(0)), 4064 getValue(I.getArgOperand(1))); 4065 } 4066 4067 setValue(&I, result); 4068} 4069 4070 4071/// ExpandPowI - Expand a llvm.powi intrinsic. 4072static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4073 SelectionDAG &DAG) { 4074 // If RHS is a constant, we can expand this out to a multiplication tree, 4075 // otherwise we end up lowering to a call to __powidf2 (for example). When 4076 // optimizing for size, we only want to do this if the expansion would produce 4077 // a small number of multiplies, otherwise we do the full expansion. 4078 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4079 // Get the exponent as a positive value. 4080 unsigned Val = RHSC->getSExtValue(); 4081 if ((int)Val < 0) Val = -Val; 4082 4083 // powi(x, 0) -> 1.0 4084 if (Val == 0) 4085 return DAG.getConstantFP(1.0, LHS.getValueType()); 4086 4087 const Function *F = DAG.getMachineFunction().getFunction(); 4088 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4089 // If optimizing for size, don't insert too many multiplies. This 4090 // inserts up to 5 multiplies. 4091 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4092 // We use the simple binary decomposition method to generate the multiply 4093 // sequence. There are more optimal ways to do this (for example, 4094 // powi(x,15) generates one more multiply than it should), but this has 4095 // the benefit of being both really simple and much better than a libcall. 4096 SDValue Res; // Logically starts equal to 1.0 4097 SDValue CurSquare = LHS; 4098 while (Val) { 4099 if (Val & 1) { 4100 if (Res.getNode()) 4101 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4102 else 4103 Res = CurSquare; // 1.0*CurSquare. 4104 } 4105 4106 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4107 CurSquare, CurSquare); 4108 Val >>= 1; 4109 } 4110 4111 // If the original was negative, invert the result, producing 1/(x*x*x). 4112 if (RHSC->getSExtValue() < 0) 4113 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4114 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4115 return Res; 4116 } 4117 } 4118 4119 // Otherwise, expand to a libcall. 4120 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4121} 4122 4123// getTruncatedArgReg - Find underlying register used for an truncated 4124// argument. 4125static unsigned getTruncatedArgReg(const SDValue &N) { 4126 if (N.getOpcode() != ISD::TRUNCATE) 4127 return 0; 4128 4129 const SDValue &Ext = N.getOperand(0); 4130 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4131 const SDValue &CFR = Ext.getOperand(0); 4132 if (CFR.getOpcode() == ISD::CopyFromReg) 4133 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4134 else 4135 if (CFR.getOpcode() == ISD::TRUNCATE) 4136 return getTruncatedArgReg(CFR); 4137 } 4138 return 0; 4139} 4140 4141/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4142/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4143/// At the end of instruction selection, they will be inserted to the entry BB. 4144bool 4145SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4146 int64_t Offset, 4147 const SDValue &N) { 4148 const Argument *Arg = dyn_cast<Argument>(V); 4149 if (!Arg) 4150 return false; 4151 4152 MachineFunction &MF = DAG.getMachineFunction(); 4153 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4154 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4155 4156 // Ignore inlined function arguments here. 4157 DIVariable DV(Variable); 4158 if (DV.isInlinedFnArgument(MF.getFunction())) 4159 return false; 4160 4161 unsigned Reg = 0; 4162 if (Arg->hasByValAttr()) { 4163 // Byval arguments' frame index is recorded during argument lowering. 4164 // Use this info directly. 4165 Reg = TRI->getFrameRegister(MF); 4166 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 4167 // If byval argument ofset is not recorded then ignore this. 4168 if (!Offset) 4169 Reg = 0; 4170 } 4171 4172 if (N.getNode()) { 4173 if (N.getOpcode() == ISD::CopyFromReg) 4174 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4175 else 4176 Reg = getTruncatedArgReg(N); 4177 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4178 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4179 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4180 if (PR) 4181 Reg = PR; 4182 } 4183 } 4184 4185 if (!Reg) { 4186 // Check if ValueMap has reg number. 4187 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4188 if (VMI != FuncInfo.ValueMap.end()) 4189 Reg = VMI->second; 4190 } 4191 4192 if (!Reg && N.getNode()) { 4193 // Check if frame index is available. 4194 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4195 if (FrameIndexSDNode *FINode = 4196 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4197 Reg = TRI->getFrameRegister(MF); 4198 Offset = FINode->getIndex(); 4199 } 4200 } 4201 4202 if (!Reg) 4203 return false; 4204 4205 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4206 TII->get(TargetOpcode::DBG_VALUE)) 4207 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4208 FuncInfo.ArgDbgValues.push_back(&*MIB); 4209 return true; 4210} 4211 4212// VisualStudio defines setjmp as _setjmp 4213#if defined(_MSC_VER) && defined(setjmp) && \ 4214 !defined(setjmp_undefined_for_msvc) 4215# pragma push_macro("setjmp") 4216# undef setjmp 4217# define setjmp_undefined_for_msvc 4218#endif 4219 4220/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4221/// we want to emit this as a call to a named external function, return the name 4222/// otherwise lower it and return null. 4223const char * 4224SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4225 DebugLoc dl = getCurDebugLoc(); 4226 SDValue Res; 4227 4228 switch (Intrinsic) { 4229 default: 4230 // By default, turn this into a target intrinsic node. 4231 visitTargetIntrinsic(I, Intrinsic); 4232 return 0; 4233 case Intrinsic::vastart: visitVAStart(I); return 0; 4234 case Intrinsic::vaend: visitVAEnd(I); return 0; 4235 case Intrinsic::vacopy: visitVACopy(I); return 0; 4236 case Intrinsic::returnaddress: 4237 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4238 getValue(I.getArgOperand(0)))); 4239 return 0; 4240 case Intrinsic::frameaddress: 4241 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4242 getValue(I.getArgOperand(0)))); 4243 return 0; 4244 case Intrinsic::setjmp: 4245 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4246 case Intrinsic::longjmp: 4247 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4248 case Intrinsic::memcpy: { 4249 // Assert for address < 256 since we support only user defined address 4250 // spaces. 4251 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4252 < 256 && 4253 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4254 < 256 && 4255 "Unknown address space"); 4256 SDValue Op1 = getValue(I.getArgOperand(0)); 4257 SDValue Op2 = getValue(I.getArgOperand(1)); 4258 SDValue Op3 = getValue(I.getArgOperand(2)); 4259 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4260 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4261 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4262 MachinePointerInfo(I.getArgOperand(0)), 4263 MachinePointerInfo(I.getArgOperand(1)))); 4264 return 0; 4265 } 4266 case Intrinsic::memset: { 4267 // Assert for address < 256 since we support only user defined address 4268 // spaces. 4269 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4270 < 256 && 4271 "Unknown address space"); 4272 SDValue Op1 = getValue(I.getArgOperand(0)); 4273 SDValue Op2 = getValue(I.getArgOperand(1)); 4274 SDValue Op3 = getValue(I.getArgOperand(2)); 4275 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4276 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4277 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4278 MachinePointerInfo(I.getArgOperand(0)))); 4279 return 0; 4280 } 4281 case Intrinsic::memmove: { 4282 // Assert for address < 256 since we support only user defined address 4283 // spaces. 4284 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4285 < 256 && 4286 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4287 < 256 && 4288 "Unknown address space"); 4289 SDValue Op1 = getValue(I.getArgOperand(0)); 4290 SDValue Op2 = getValue(I.getArgOperand(1)); 4291 SDValue Op3 = getValue(I.getArgOperand(2)); 4292 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4293 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4294 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4295 MachinePointerInfo(I.getArgOperand(0)), 4296 MachinePointerInfo(I.getArgOperand(1)))); 4297 return 0; 4298 } 4299 case Intrinsic::dbg_declare: { 4300 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4301 MDNode *Variable = DI.getVariable(); 4302 const Value *Address = DI.getAddress(); 4303 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4304 return 0; 4305 4306 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4307 // but do not always have a corresponding SDNode built. The SDNodeOrder 4308 // absolute, but not relative, values are different depending on whether 4309 // debug info exists. 4310 ++SDNodeOrder; 4311 4312 // Check if address has undef value. 4313 if (isa<UndefValue>(Address) || 4314 (Address->use_empty() && !isa<Argument>(Address))) { 4315 DEBUG(dbgs() << "Dropping debug info for " << DI); 4316 return 0; 4317 } 4318 4319 SDValue &N = NodeMap[Address]; 4320 if (!N.getNode() && isa<Argument>(Address)) 4321 // Check unused arguments map. 4322 N = UnusedArgNodeMap[Address]; 4323 SDDbgValue *SDV; 4324 if (N.getNode()) { 4325 // Parameters are handled specially. 4326 bool isParameter = 4327 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4328 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4329 Address = BCI->getOperand(0); 4330 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4331 4332 if (isParameter && !AI) { 4333 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4334 if (FINode) 4335 // Byval parameter. We have a frame index at this point. 4336 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4337 0, dl, SDNodeOrder); 4338 else { 4339 // Address is an argument, so try to emit its dbg value using 4340 // virtual register info from the FuncInfo.ValueMap. 4341 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4342 return 0; 4343 } 4344 } else if (AI) 4345 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4346 0, dl, SDNodeOrder); 4347 else { 4348 // Can't do anything with other non-AI cases yet. 4349 DEBUG(dbgs() << "Dropping debug info for " << DI); 4350 return 0; 4351 } 4352 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4353 } else { 4354 // If Address is an argument then try to emit its dbg value using 4355 // virtual register info from the FuncInfo.ValueMap. 4356 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4357 // If variable is pinned by a alloca in dominating bb then 4358 // use StaticAllocaMap. 4359 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4360 if (AI->getParent() != DI.getParent()) { 4361 DenseMap<const AllocaInst*, int>::iterator SI = 4362 FuncInfo.StaticAllocaMap.find(AI); 4363 if (SI != FuncInfo.StaticAllocaMap.end()) { 4364 SDV = DAG.getDbgValue(Variable, SI->second, 4365 0, dl, SDNodeOrder); 4366 DAG.AddDbgValue(SDV, 0, false); 4367 return 0; 4368 } 4369 } 4370 } 4371 DEBUG(dbgs() << "Dropping debug info for " << DI); 4372 } 4373 } 4374 return 0; 4375 } 4376 case Intrinsic::dbg_value: { 4377 const DbgValueInst &DI = cast<DbgValueInst>(I); 4378 if (!DIVariable(DI.getVariable()).Verify()) 4379 return 0; 4380 4381 MDNode *Variable = DI.getVariable(); 4382 uint64_t Offset = DI.getOffset(); 4383 const Value *V = DI.getValue(); 4384 if (!V) 4385 return 0; 4386 4387 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4388 // but do not always have a corresponding SDNode built. The SDNodeOrder 4389 // absolute, but not relative, values are different depending on whether 4390 // debug info exists. 4391 ++SDNodeOrder; 4392 SDDbgValue *SDV; 4393 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4394 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4395 DAG.AddDbgValue(SDV, 0, false); 4396 } else { 4397 // Do not use getValue() in here; we don't want to generate code at 4398 // this point if it hasn't been done yet. 4399 SDValue N = NodeMap[V]; 4400 if (!N.getNode() && isa<Argument>(V)) 4401 // Check unused arguments map. 4402 N = UnusedArgNodeMap[V]; 4403 if (N.getNode()) { 4404 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4405 SDV = DAG.getDbgValue(Variable, N.getNode(), 4406 N.getResNo(), Offset, dl, SDNodeOrder); 4407 DAG.AddDbgValue(SDV, N.getNode(), false); 4408 } 4409 } else if (!V->use_empty() ) { 4410 // Do not call getValue(V) yet, as we don't want to generate code. 4411 // Remember it for later. 4412 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4413 DanglingDebugInfoMap[V] = DDI; 4414 } else { 4415 // We may expand this to cover more cases. One case where we have no 4416 // data available is an unreferenced parameter. 4417 DEBUG(dbgs() << "Dropping debug info for " << DI); 4418 } 4419 } 4420 4421 // Build a debug info table entry. 4422 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4423 V = BCI->getOperand(0); 4424 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4425 // Don't handle byval struct arguments or VLAs, for example. 4426 if (!AI) 4427 return 0; 4428 DenseMap<const AllocaInst*, int>::iterator SI = 4429 FuncInfo.StaticAllocaMap.find(AI); 4430 if (SI == FuncInfo.StaticAllocaMap.end()) 4431 return 0; // VLAs. 4432 int FI = SI->second; 4433 4434 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4435 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4436 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4437 return 0; 4438 } 4439 case Intrinsic::eh_exception: { 4440 // Insert the EXCEPTIONADDR instruction. 4441 assert(FuncInfo.MBB->isLandingPad() && 4442 "Call to eh.exception not in landing pad!"); 4443 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4444 SDValue Ops[1]; 4445 Ops[0] = DAG.getRoot(); 4446 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4447 setValue(&I, Op); 4448 DAG.setRoot(Op.getValue(1)); 4449 return 0; 4450 } 4451 4452 case Intrinsic::eh_selector: { 4453 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4454 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4455 if (CallMBB->isLandingPad()) 4456 AddCatchInfo(I, &MMI, CallMBB); 4457 else { 4458#ifndef NDEBUG 4459 FuncInfo.CatchInfoLost.insert(&I); 4460#endif 4461 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4462 unsigned Reg = TLI.getExceptionSelectorRegister(); 4463 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4464 } 4465 4466 // Insert the EHSELECTION instruction. 4467 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4468 SDValue Ops[2]; 4469 Ops[0] = getValue(I.getArgOperand(0)); 4470 Ops[1] = getRoot(); 4471 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4472 DAG.setRoot(Op.getValue(1)); 4473 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4474 return 0; 4475 } 4476 4477 case Intrinsic::eh_typeid_for: { 4478 // Find the type id for the given typeinfo. 4479 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4480 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4481 Res = DAG.getConstant(TypeID, MVT::i32); 4482 setValue(&I, Res); 4483 return 0; 4484 } 4485 4486 case Intrinsic::eh_return_i32: 4487 case Intrinsic::eh_return_i64: 4488 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4489 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4490 MVT::Other, 4491 getControlRoot(), 4492 getValue(I.getArgOperand(0)), 4493 getValue(I.getArgOperand(1)))); 4494 return 0; 4495 case Intrinsic::eh_unwind_init: 4496 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4497 return 0; 4498 case Intrinsic::eh_dwarf_cfa: { 4499 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4500 TLI.getPointerTy()); 4501 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4502 TLI.getPointerTy(), 4503 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4504 TLI.getPointerTy()), 4505 CfaArg); 4506 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4507 TLI.getPointerTy(), 4508 DAG.getConstant(0, TLI.getPointerTy())); 4509 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4510 FA, Offset)); 4511 return 0; 4512 } 4513 case Intrinsic::eh_sjlj_callsite: { 4514 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4515 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4516 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4517 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4518 4519 MMI.setCurrentCallSite(CI->getZExtValue()); 4520 return 0; 4521 } 4522 case Intrinsic::eh_sjlj_setjmp: { 4523 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4524 getValue(I.getArgOperand(0)))); 4525 return 0; 4526 } 4527 case Intrinsic::eh_sjlj_longjmp: { 4528 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4529 getRoot(), getValue(I.getArgOperand(0)))); 4530 return 0; 4531 } 4532 case Intrinsic::eh_sjlj_dispatch_setup: { 4533 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4534 getRoot(), getValue(I.getArgOperand(0)))); 4535 return 0; 4536 } 4537 4538 case Intrinsic::x86_mmx_pslli_w: 4539 case Intrinsic::x86_mmx_pslli_d: 4540 case Intrinsic::x86_mmx_pslli_q: 4541 case Intrinsic::x86_mmx_psrli_w: 4542 case Intrinsic::x86_mmx_psrli_d: 4543 case Intrinsic::x86_mmx_psrli_q: 4544 case Intrinsic::x86_mmx_psrai_w: 4545 case Intrinsic::x86_mmx_psrai_d: { 4546 SDValue ShAmt = getValue(I.getArgOperand(1)); 4547 if (isa<ConstantSDNode>(ShAmt)) { 4548 visitTargetIntrinsic(I, Intrinsic); 4549 return 0; 4550 } 4551 unsigned NewIntrinsic = 0; 4552 EVT ShAmtVT = MVT::v2i32; 4553 switch (Intrinsic) { 4554 case Intrinsic::x86_mmx_pslli_w: 4555 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4556 break; 4557 case Intrinsic::x86_mmx_pslli_d: 4558 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4559 break; 4560 case Intrinsic::x86_mmx_pslli_q: 4561 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4562 break; 4563 case Intrinsic::x86_mmx_psrli_w: 4564 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4565 break; 4566 case Intrinsic::x86_mmx_psrli_d: 4567 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4568 break; 4569 case Intrinsic::x86_mmx_psrli_q: 4570 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4571 break; 4572 case Intrinsic::x86_mmx_psrai_w: 4573 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4574 break; 4575 case Intrinsic::x86_mmx_psrai_d: 4576 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4577 break; 4578 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4579 } 4580 4581 // The vector shift intrinsics with scalars uses 32b shift amounts but 4582 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4583 // to be zero. 4584 // We must do this early because v2i32 is not a legal type. 4585 DebugLoc dl = getCurDebugLoc(); 4586 SDValue ShOps[2]; 4587 ShOps[0] = ShAmt; 4588 ShOps[1] = DAG.getConstant(0, MVT::i32); 4589 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4590 EVT DestVT = TLI.getValueType(I.getType()); 4591 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4592 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4593 DAG.getConstant(NewIntrinsic, MVT::i32), 4594 getValue(I.getArgOperand(0)), ShAmt); 4595 setValue(&I, Res); 4596 return 0; 4597 } 4598 case Intrinsic::convertff: 4599 case Intrinsic::convertfsi: 4600 case Intrinsic::convertfui: 4601 case Intrinsic::convertsif: 4602 case Intrinsic::convertuif: 4603 case Intrinsic::convertss: 4604 case Intrinsic::convertsu: 4605 case Intrinsic::convertus: 4606 case Intrinsic::convertuu: { 4607 ISD::CvtCode Code = ISD::CVT_INVALID; 4608 switch (Intrinsic) { 4609 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4610 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4611 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4612 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4613 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4614 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4615 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4616 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4617 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4618 } 4619 EVT DestVT = TLI.getValueType(I.getType()); 4620 const Value *Op1 = I.getArgOperand(0); 4621 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4622 DAG.getValueType(DestVT), 4623 DAG.getValueType(getValue(Op1).getValueType()), 4624 getValue(I.getArgOperand(1)), 4625 getValue(I.getArgOperand(2)), 4626 Code); 4627 setValue(&I, Res); 4628 return 0; 4629 } 4630 case Intrinsic::sqrt: 4631 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4632 getValue(I.getArgOperand(0)).getValueType(), 4633 getValue(I.getArgOperand(0)))); 4634 return 0; 4635 case Intrinsic::powi: 4636 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4637 getValue(I.getArgOperand(1)), DAG)); 4638 return 0; 4639 case Intrinsic::sin: 4640 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4641 getValue(I.getArgOperand(0)).getValueType(), 4642 getValue(I.getArgOperand(0)))); 4643 return 0; 4644 case Intrinsic::cos: 4645 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4646 getValue(I.getArgOperand(0)).getValueType(), 4647 getValue(I.getArgOperand(0)))); 4648 return 0; 4649 case Intrinsic::log: 4650 visitLog(I); 4651 return 0; 4652 case Intrinsic::log2: 4653 visitLog2(I); 4654 return 0; 4655 case Intrinsic::log10: 4656 visitLog10(I); 4657 return 0; 4658 case Intrinsic::exp: 4659 visitExp(I); 4660 return 0; 4661 case Intrinsic::exp2: 4662 visitExp2(I); 4663 return 0; 4664 case Intrinsic::pow: 4665 visitPow(I); 4666 return 0; 4667 case Intrinsic::fma: 4668 setValue(&I, DAG.getNode(ISD::FMA, dl, 4669 getValue(I.getArgOperand(0)).getValueType(), 4670 getValue(I.getArgOperand(0)), 4671 getValue(I.getArgOperand(1)), 4672 getValue(I.getArgOperand(2)))); 4673 return 0; 4674 case Intrinsic::convert_to_fp16: 4675 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4676 MVT::i16, getValue(I.getArgOperand(0)))); 4677 return 0; 4678 case Intrinsic::convert_from_fp16: 4679 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4680 MVT::f32, getValue(I.getArgOperand(0)))); 4681 return 0; 4682 case Intrinsic::pcmarker: { 4683 SDValue Tmp = getValue(I.getArgOperand(0)); 4684 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4685 return 0; 4686 } 4687 case Intrinsic::readcyclecounter: { 4688 SDValue Op = getRoot(); 4689 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4690 DAG.getVTList(MVT::i64, MVT::Other), 4691 &Op, 1); 4692 setValue(&I, Res); 4693 DAG.setRoot(Res.getValue(1)); 4694 return 0; 4695 } 4696 case Intrinsic::bswap: 4697 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4698 getValue(I.getArgOperand(0)).getValueType(), 4699 getValue(I.getArgOperand(0)))); 4700 return 0; 4701 case Intrinsic::cttz: { 4702 SDValue Arg = getValue(I.getArgOperand(0)); 4703 EVT Ty = Arg.getValueType(); 4704 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4705 return 0; 4706 } 4707 case Intrinsic::ctlz: { 4708 SDValue Arg = getValue(I.getArgOperand(0)); 4709 EVT Ty = Arg.getValueType(); 4710 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4711 return 0; 4712 } 4713 case Intrinsic::ctpop: { 4714 SDValue Arg = getValue(I.getArgOperand(0)); 4715 EVT Ty = Arg.getValueType(); 4716 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4717 return 0; 4718 } 4719 case Intrinsic::stacksave: { 4720 SDValue Op = getRoot(); 4721 Res = DAG.getNode(ISD::STACKSAVE, dl, 4722 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4723 setValue(&I, Res); 4724 DAG.setRoot(Res.getValue(1)); 4725 return 0; 4726 } 4727 case Intrinsic::stackrestore: { 4728 Res = getValue(I.getArgOperand(0)); 4729 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4730 return 0; 4731 } 4732 case Intrinsic::stackprotector: { 4733 // Emit code into the DAG to store the stack guard onto the stack. 4734 MachineFunction &MF = DAG.getMachineFunction(); 4735 MachineFrameInfo *MFI = MF.getFrameInfo(); 4736 EVT PtrTy = TLI.getPointerTy(); 4737 4738 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4739 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4740 4741 int FI = FuncInfo.StaticAllocaMap[Slot]; 4742 MFI->setStackProtectorIndex(FI); 4743 4744 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4745 4746 // Store the stack protector onto the stack. 4747 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4748 MachinePointerInfo::getFixedStack(FI), 4749 true, false, 0); 4750 setValue(&I, Res); 4751 DAG.setRoot(Res); 4752 return 0; 4753 } 4754 case Intrinsic::objectsize: { 4755 // If we don't know by now, we're never going to know. 4756 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4757 4758 assert(CI && "Non-constant type in __builtin_object_size?"); 4759 4760 SDValue Arg = getValue(I.getCalledValue()); 4761 EVT Ty = Arg.getValueType(); 4762 4763 if (CI->isZero()) 4764 Res = DAG.getConstant(-1ULL, Ty); 4765 else 4766 Res = DAG.getConstant(0, Ty); 4767 4768 setValue(&I, Res); 4769 return 0; 4770 } 4771 case Intrinsic::var_annotation: 4772 // Discard annotate attributes 4773 return 0; 4774 4775 case Intrinsic::init_trampoline: { 4776 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4777 4778 SDValue Ops[6]; 4779 Ops[0] = getRoot(); 4780 Ops[1] = getValue(I.getArgOperand(0)); 4781 Ops[2] = getValue(I.getArgOperand(1)); 4782 Ops[3] = getValue(I.getArgOperand(2)); 4783 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4784 Ops[5] = DAG.getSrcValue(F); 4785 4786 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4787 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4788 Ops, 6); 4789 4790 setValue(&I, Res); 4791 DAG.setRoot(Res.getValue(1)); 4792 return 0; 4793 } 4794 case Intrinsic::gcroot: 4795 if (GFI) { 4796 const Value *Alloca = I.getArgOperand(0); 4797 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4798 4799 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4800 GFI->addStackRoot(FI->getIndex(), TypeMap); 4801 } 4802 return 0; 4803 case Intrinsic::gcread: 4804 case Intrinsic::gcwrite: 4805 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4806 return 0; 4807 case Intrinsic::flt_rounds: 4808 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4809 return 0; 4810 4811 case Intrinsic::expect: { 4812 // Just replace __builtin_expect(exp, c) with EXP. 4813 setValue(&I, getValue(I.getArgOperand(0))); 4814 return 0; 4815 } 4816 4817 case Intrinsic::trap: { 4818 StringRef TrapFuncName = getTrapFunctionName(); 4819 if (TrapFuncName.empty()) { 4820 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4821 return 0; 4822 } 4823 TargetLowering::ArgListTy Args; 4824 std::pair<SDValue, SDValue> Result = 4825 TLI.LowerCallTo(getRoot(), I.getType(), 4826 false, false, false, false, 0, CallingConv::C, 4827 /*isTailCall=*/false, /*isReturnValueUsed=*/true, 4828 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 4829 Args, DAG, getCurDebugLoc()); 4830 DAG.setRoot(Result.second); 4831 return 0; 4832 } 4833 case Intrinsic::uadd_with_overflow: 4834 return implVisitAluOverflow(I, ISD::UADDO); 4835 case Intrinsic::sadd_with_overflow: 4836 return implVisitAluOverflow(I, ISD::SADDO); 4837 case Intrinsic::usub_with_overflow: 4838 return implVisitAluOverflow(I, ISD::USUBO); 4839 case Intrinsic::ssub_with_overflow: 4840 return implVisitAluOverflow(I, ISD::SSUBO); 4841 case Intrinsic::umul_with_overflow: 4842 return implVisitAluOverflow(I, ISD::UMULO); 4843 case Intrinsic::smul_with_overflow: 4844 return implVisitAluOverflow(I, ISD::SMULO); 4845 4846 case Intrinsic::prefetch: { 4847 SDValue Ops[5]; 4848 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 4849 Ops[0] = getRoot(); 4850 Ops[1] = getValue(I.getArgOperand(0)); 4851 Ops[2] = getValue(I.getArgOperand(1)); 4852 Ops[3] = getValue(I.getArgOperand(2)); 4853 Ops[4] = getValue(I.getArgOperand(3)); 4854 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 4855 DAG.getVTList(MVT::Other), 4856 &Ops[0], 5, 4857 EVT::getIntegerVT(*Context, 8), 4858 MachinePointerInfo(I.getArgOperand(0)), 4859 0, /* align */ 4860 false, /* volatile */ 4861 rw==0, /* read */ 4862 rw==1)); /* write */ 4863 return 0; 4864 } 4865 case Intrinsic::memory_barrier: { 4866 SDValue Ops[6]; 4867 Ops[0] = getRoot(); 4868 for (int x = 1; x < 6; ++x) 4869 Ops[x] = getValue(I.getArgOperand(x - 1)); 4870 4871 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4872 return 0; 4873 } 4874 case Intrinsic::atomic_cmp_swap: { 4875 SDValue Root = getRoot(); 4876 SDValue L = 4877 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4878 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 4879 Root, 4880 getValue(I.getArgOperand(0)), 4881 getValue(I.getArgOperand(1)), 4882 getValue(I.getArgOperand(2)), 4883 MachinePointerInfo(I.getArgOperand(0))); 4884 setValue(&I, L); 4885 DAG.setRoot(L.getValue(1)); 4886 return 0; 4887 } 4888 case Intrinsic::atomic_load_add: 4889 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4890 case Intrinsic::atomic_load_sub: 4891 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4892 case Intrinsic::atomic_load_or: 4893 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4894 case Intrinsic::atomic_load_xor: 4895 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4896 case Intrinsic::atomic_load_and: 4897 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4898 case Intrinsic::atomic_load_nand: 4899 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4900 case Intrinsic::atomic_load_max: 4901 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4902 case Intrinsic::atomic_load_min: 4903 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4904 case Intrinsic::atomic_load_umin: 4905 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4906 case Intrinsic::atomic_load_umax: 4907 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4908 case Intrinsic::atomic_swap: 4909 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4910 4911 case Intrinsic::invariant_start: 4912 case Intrinsic::lifetime_start: 4913 // Discard region information. 4914 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4915 return 0; 4916 case Intrinsic::invariant_end: 4917 case Intrinsic::lifetime_end: 4918 // Discard region information. 4919 return 0; 4920 } 4921} 4922 4923void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 4924 bool isTailCall, 4925 MachineBasicBlock *LandingPad) { 4926 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4927 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4928 Type *RetTy = FTy->getReturnType(); 4929 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4930 MCSymbol *BeginLabel = 0; 4931 4932 TargetLowering::ArgListTy Args; 4933 TargetLowering::ArgListEntry Entry; 4934 Args.reserve(CS.arg_size()); 4935 4936 // Check whether the function can return without sret-demotion. 4937 SmallVector<ISD::OutputArg, 4> Outs; 4938 SmallVector<uint64_t, 4> Offsets; 4939 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4940 Outs, TLI, &Offsets); 4941 4942 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4943 DAG.getMachineFunction(), 4944 FTy->isVarArg(), Outs, 4945 FTy->getContext()); 4946 4947 SDValue DemoteStackSlot; 4948 int DemoteStackIdx = -100; 4949 4950 if (!CanLowerReturn) { 4951 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4952 FTy->getReturnType()); 4953 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4954 FTy->getReturnType()); 4955 MachineFunction &MF = DAG.getMachineFunction(); 4956 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4957 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4958 4959 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 4960 Entry.Node = DemoteStackSlot; 4961 Entry.Ty = StackSlotPtrType; 4962 Entry.isSExt = false; 4963 Entry.isZExt = false; 4964 Entry.isInReg = false; 4965 Entry.isSRet = true; 4966 Entry.isNest = false; 4967 Entry.isByVal = false; 4968 Entry.Alignment = Align; 4969 Args.push_back(Entry); 4970 RetTy = Type::getVoidTy(FTy->getContext()); 4971 } 4972 4973 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4974 i != e; ++i) { 4975 const Value *V = *i; 4976 4977 // Skip empty types 4978 if (V->getType()->isEmptyTy()) 4979 continue; 4980 4981 SDValue ArgNode = getValue(V); 4982 Entry.Node = ArgNode; Entry.Ty = V->getType(); 4983 4984 unsigned attrInd = i - CS.arg_begin() + 1; 4985 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4986 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4987 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4988 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4989 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4990 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4991 Entry.Alignment = CS.getParamAlignment(attrInd); 4992 Args.push_back(Entry); 4993 } 4994 4995 if (LandingPad) { 4996 // Insert a label before the invoke call to mark the try range. This can be 4997 // used to detect deletion of the invoke via the MachineModuleInfo. 4998 BeginLabel = MMI.getContext().CreateTempSymbol(); 4999 5000 // For SjLj, keep track of which landing pads go with which invokes 5001 // so as to maintain the ordering of pads in the LSDA. 5002 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5003 if (CallSiteIndex) { 5004 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5005 // Now that the call site is handled, stop tracking it. 5006 MMI.setCurrentCallSite(0); 5007 } 5008 5009 // Both PendingLoads and PendingExports must be flushed here; 5010 // this call might not return. 5011 (void)getRoot(); 5012 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5013 } 5014 5015 // Check if target-independent constraints permit a tail call here. 5016 // Target-dependent constraints are checked within TLI.LowerCallTo. 5017 if (isTailCall && 5018 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5019 isTailCall = false; 5020 5021 // If there's a possibility that fast-isel has already selected some amount 5022 // of the current basic block, don't emit a tail call. 5023 if (isTailCall && EnableFastISel) 5024 isTailCall = false; 5025 5026 std::pair<SDValue,SDValue> Result = 5027 TLI.LowerCallTo(getRoot(), RetTy, 5028 CS.paramHasAttr(0, Attribute::SExt), 5029 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 5030 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 5031 CS.getCallingConv(), 5032 isTailCall, 5033 !CS.getInstruction()->use_empty(), 5034 Callee, Args, DAG, getCurDebugLoc()); 5035 assert((isTailCall || Result.second.getNode()) && 5036 "Non-null chain expected with non-tail call!"); 5037 assert((Result.second.getNode() || !Result.first.getNode()) && 5038 "Null value expected with tail call!"); 5039 if (Result.first.getNode()) { 5040 setValue(CS.getInstruction(), Result.first); 5041 } else if (!CanLowerReturn && Result.second.getNode()) { 5042 // The instruction result is the result of loading from the 5043 // hidden sret parameter. 5044 SmallVector<EVT, 1> PVTs; 5045 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5046 5047 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5048 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5049 EVT PtrVT = PVTs[0]; 5050 unsigned NumValues = Outs.size(); 5051 SmallVector<SDValue, 4> Values(NumValues); 5052 SmallVector<SDValue, 4> Chains(NumValues); 5053 5054 for (unsigned i = 0; i < NumValues; ++i) { 5055 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5056 DemoteStackSlot, 5057 DAG.getConstant(Offsets[i], PtrVT)); 5058 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 5059 Add, 5060 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5061 false, false, 1); 5062 Values[i] = L; 5063 Chains[i] = L.getValue(1); 5064 } 5065 5066 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5067 MVT::Other, &Chains[0], NumValues); 5068 PendingLoads.push_back(Chain); 5069 5070 // Collect the legal value parts into potentially illegal values 5071 // that correspond to the original function's return values. 5072 SmallVector<EVT, 4> RetTys; 5073 RetTy = FTy->getReturnType(); 5074 ComputeValueVTs(TLI, RetTy, RetTys); 5075 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5076 SmallVector<SDValue, 4> ReturnValues; 5077 unsigned CurReg = 0; 5078 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5079 EVT VT = RetTys[I]; 5080 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 5081 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 5082 5083 SDValue ReturnValue = 5084 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 5085 RegisterVT, VT, AssertOp); 5086 ReturnValues.push_back(ReturnValue); 5087 CurReg += NumRegs; 5088 } 5089 5090 setValue(CS.getInstruction(), 5091 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5092 DAG.getVTList(&RetTys[0], RetTys.size()), 5093 &ReturnValues[0], ReturnValues.size())); 5094 } 5095 5096 // Assign order to nodes here. If the call does not produce a result, it won't 5097 // be mapped to a SDNode and visit() will not assign it an order number. 5098 if (!Result.second.getNode()) { 5099 // As a special case, a null chain means that a tail call has been emitted and 5100 // the DAG root is already updated. 5101 HasTailCall = true; 5102 ++SDNodeOrder; 5103 AssignOrderingToNode(DAG.getRoot().getNode()); 5104 } else { 5105 DAG.setRoot(Result.second); 5106 ++SDNodeOrder; 5107 AssignOrderingToNode(Result.second.getNode()); 5108 } 5109 5110 if (LandingPad) { 5111 // Insert a label at the end of the invoke call to mark the try range. This 5112 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5113 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5114 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5115 5116 // Inform MachineModuleInfo of range. 5117 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5118 } 5119} 5120 5121/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5122/// value is equal or not-equal to zero. 5123static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5124 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5125 UI != E; ++UI) { 5126 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5127 if (IC->isEquality()) 5128 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5129 if (C->isNullValue()) 5130 continue; 5131 // Unknown instruction. 5132 return false; 5133 } 5134 return true; 5135} 5136 5137static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5138 Type *LoadTy, 5139 SelectionDAGBuilder &Builder) { 5140 5141 // Check to see if this load can be trivially constant folded, e.g. if the 5142 // input is from a string literal. 5143 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5144 // Cast pointer to the type we really want to load. 5145 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5146 PointerType::getUnqual(LoadTy)); 5147 5148 if (const Constant *LoadCst = 5149 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5150 Builder.TD)) 5151 return Builder.getValue(LoadCst); 5152 } 5153 5154 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5155 // still constant memory, the input chain can be the entry node. 5156 SDValue Root; 5157 bool ConstantMemory = false; 5158 5159 // Do not serialize (non-volatile) loads of constant memory with anything. 5160 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5161 Root = Builder.DAG.getEntryNode(); 5162 ConstantMemory = true; 5163 } else { 5164 // Do not serialize non-volatile loads against each other. 5165 Root = Builder.DAG.getRoot(); 5166 } 5167 5168 SDValue Ptr = Builder.getValue(PtrVal); 5169 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5170 Ptr, MachinePointerInfo(PtrVal), 5171 false /*volatile*/, 5172 false /*nontemporal*/, 1 /* align=1 */); 5173 5174 if (!ConstantMemory) 5175 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5176 return LoadVal; 5177} 5178 5179 5180/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5181/// If so, return true and lower it, otherwise return false and it will be 5182/// lowered like a normal call. 5183bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5184 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5185 if (I.getNumArgOperands() != 3) 5186 return false; 5187 5188 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5189 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5190 !I.getArgOperand(2)->getType()->isIntegerTy() || 5191 !I.getType()->isIntegerTy()) 5192 return false; 5193 5194 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5195 5196 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5197 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5198 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5199 bool ActuallyDoIt = true; 5200 MVT LoadVT; 5201 Type *LoadTy; 5202 switch (Size->getZExtValue()) { 5203 default: 5204 LoadVT = MVT::Other; 5205 LoadTy = 0; 5206 ActuallyDoIt = false; 5207 break; 5208 case 2: 5209 LoadVT = MVT::i16; 5210 LoadTy = Type::getInt16Ty(Size->getContext()); 5211 break; 5212 case 4: 5213 LoadVT = MVT::i32; 5214 LoadTy = Type::getInt32Ty(Size->getContext()); 5215 break; 5216 case 8: 5217 LoadVT = MVT::i64; 5218 LoadTy = Type::getInt64Ty(Size->getContext()); 5219 break; 5220 /* 5221 case 16: 5222 LoadVT = MVT::v4i32; 5223 LoadTy = Type::getInt32Ty(Size->getContext()); 5224 LoadTy = VectorType::get(LoadTy, 4); 5225 break; 5226 */ 5227 } 5228 5229 // This turns into unaligned loads. We only do this if the target natively 5230 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5231 // we'll only produce a small number of byte loads. 5232 5233 // Require that we can find a legal MVT, and only do this if the target 5234 // supports unaligned loads of that type. Expanding into byte loads would 5235 // bloat the code. 5236 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5237 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5238 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5239 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5240 ActuallyDoIt = false; 5241 } 5242 5243 if (ActuallyDoIt) { 5244 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5245 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5246 5247 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5248 ISD::SETNE); 5249 EVT CallVT = TLI.getValueType(I.getType(), true); 5250 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5251 return true; 5252 } 5253 } 5254 5255 5256 return false; 5257} 5258 5259 5260void SelectionDAGBuilder::visitCall(const CallInst &I) { 5261 // Handle inline assembly differently. 5262 if (isa<InlineAsm>(I.getCalledValue())) { 5263 visitInlineAsm(&I); 5264 return; 5265 } 5266 5267 // See if any floating point values are being passed to this function. This is 5268 // used to emit an undefined reference to fltused on Windows. 5269 FunctionType *FT = 5270 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5271 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5272 if (FT->isVarArg() && 5273 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5274 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5275 Type* T = I.getArgOperand(i)->getType(); 5276 for (po_iterator<Type*> i = po_begin(T), e = po_end(T); 5277 i != e; ++i) { 5278 if (!i->isFloatingPointTy()) continue; 5279 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5280 break; 5281 } 5282 } 5283 } 5284 5285 const char *RenameFn = 0; 5286 if (Function *F = I.getCalledFunction()) { 5287 if (F->isDeclaration()) { 5288 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5289 if (unsigned IID = II->getIntrinsicID(F)) { 5290 RenameFn = visitIntrinsicCall(I, IID); 5291 if (!RenameFn) 5292 return; 5293 } 5294 } 5295 if (unsigned IID = F->getIntrinsicID()) { 5296 RenameFn = visitIntrinsicCall(I, IID); 5297 if (!RenameFn) 5298 return; 5299 } 5300 } 5301 5302 // Check for well-known libc/libm calls. If the function is internal, it 5303 // can't be a library call. 5304 if (!F->hasLocalLinkage() && F->hasName()) { 5305 StringRef Name = F->getName(); 5306 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5307 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5308 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5309 I.getType() == I.getArgOperand(0)->getType() && 5310 I.getType() == I.getArgOperand(1)->getType()) { 5311 SDValue LHS = getValue(I.getArgOperand(0)); 5312 SDValue RHS = getValue(I.getArgOperand(1)); 5313 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5314 LHS.getValueType(), LHS, RHS)); 5315 return; 5316 } 5317 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5318 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5319 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5320 I.getType() == I.getArgOperand(0)->getType()) { 5321 SDValue Tmp = getValue(I.getArgOperand(0)); 5322 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5323 Tmp.getValueType(), Tmp)); 5324 return; 5325 } 5326 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5327 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5328 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5329 I.getType() == I.getArgOperand(0)->getType() && 5330 I.onlyReadsMemory()) { 5331 SDValue Tmp = getValue(I.getArgOperand(0)); 5332 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5333 Tmp.getValueType(), Tmp)); 5334 return; 5335 } 5336 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5337 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5338 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5339 I.getType() == I.getArgOperand(0)->getType() && 5340 I.onlyReadsMemory()) { 5341 SDValue Tmp = getValue(I.getArgOperand(0)); 5342 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5343 Tmp.getValueType(), Tmp)); 5344 return; 5345 } 5346 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5347 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5348 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5349 I.getType() == I.getArgOperand(0)->getType() && 5350 I.onlyReadsMemory()) { 5351 SDValue Tmp = getValue(I.getArgOperand(0)); 5352 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5353 Tmp.getValueType(), Tmp)); 5354 return; 5355 } 5356 } else if (Name == "memcmp") { 5357 if (visitMemCmpCall(I)) 5358 return; 5359 } 5360 } 5361 } 5362 5363 SDValue Callee; 5364 if (!RenameFn) 5365 Callee = getValue(I.getCalledValue()); 5366 else 5367 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5368 5369 // Check if we can potentially perform a tail call. More detailed checking is 5370 // be done within LowerCallTo, after more information about the call is known. 5371 LowerCallTo(&I, Callee, I.isTailCall()); 5372} 5373 5374namespace { 5375 5376/// AsmOperandInfo - This contains information for each constraint that we are 5377/// lowering. 5378class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5379public: 5380 /// CallOperand - If this is the result output operand or a clobber 5381 /// this is null, otherwise it is the incoming operand to the CallInst. 5382 /// This gets modified as the asm is processed. 5383 SDValue CallOperand; 5384 5385 /// AssignedRegs - If this is a register or register class operand, this 5386 /// contains the set of register corresponding to the operand. 5387 RegsForValue AssignedRegs; 5388 5389 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5390 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5391 } 5392 5393 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5394 /// busy in OutputRegs/InputRegs. 5395 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5396 std::set<unsigned> &OutputRegs, 5397 std::set<unsigned> &InputRegs, 5398 const TargetRegisterInfo &TRI) const { 5399 if (isOutReg) { 5400 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5401 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5402 } 5403 if (isInReg) { 5404 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5405 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5406 } 5407 } 5408 5409 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5410 /// corresponds to. If there is no Value* for this operand, it returns 5411 /// MVT::Other. 5412 EVT getCallOperandValEVT(LLVMContext &Context, 5413 const TargetLowering &TLI, 5414 const TargetData *TD) const { 5415 if (CallOperandVal == 0) return MVT::Other; 5416 5417 if (isa<BasicBlock>(CallOperandVal)) 5418 return TLI.getPointerTy(); 5419 5420 llvm::Type *OpTy = CallOperandVal->getType(); 5421 5422 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5423 // If this is an indirect operand, the operand is a pointer to the 5424 // accessed type. 5425 if (isIndirect) { 5426 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5427 if (!PtrTy) 5428 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5429 OpTy = PtrTy->getElementType(); 5430 } 5431 5432 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5433 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5434 if (STy->getNumElements() == 1) 5435 OpTy = STy->getElementType(0); 5436 5437 // If OpTy is not a single value, it may be a struct/union that we 5438 // can tile with integers. 5439 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5440 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5441 switch (BitSize) { 5442 default: break; 5443 case 1: 5444 case 8: 5445 case 16: 5446 case 32: 5447 case 64: 5448 case 128: 5449 OpTy = IntegerType::get(Context, BitSize); 5450 break; 5451 } 5452 } 5453 5454 return TLI.getValueType(OpTy, true); 5455 } 5456 5457private: 5458 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5459 /// specified set. 5460 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5461 const TargetRegisterInfo &TRI) { 5462 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5463 Regs.insert(Reg); 5464 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5465 for (; *Aliases; ++Aliases) 5466 Regs.insert(*Aliases); 5467 } 5468}; 5469 5470typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5471 5472} // end anonymous namespace 5473 5474/// GetRegistersForValue - Assign registers (virtual or physical) for the 5475/// specified operand. We prefer to assign virtual registers, to allow the 5476/// register allocator to handle the assignment process. However, if the asm 5477/// uses features that we can't model on machineinstrs, we have SDISel do the 5478/// allocation. This produces generally horrible, but correct, code. 5479/// 5480/// OpInfo describes the operand. 5481/// Input and OutputRegs are the set of already allocated physical registers. 5482/// 5483static void GetRegistersForValue(SelectionDAG &DAG, 5484 const TargetLowering &TLI, 5485 DebugLoc DL, 5486 SDISelAsmOperandInfo &OpInfo, 5487 std::set<unsigned> &OutputRegs, 5488 std::set<unsigned> &InputRegs) { 5489 LLVMContext &Context = *DAG.getContext(); 5490 5491 // Compute whether this value requires an input register, an output register, 5492 // or both. 5493 bool isOutReg = false; 5494 bool isInReg = false; 5495 switch (OpInfo.Type) { 5496 case InlineAsm::isOutput: 5497 isOutReg = true; 5498 5499 // If there is an input constraint that matches this, we need to reserve 5500 // the input register so no other inputs allocate to it. 5501 isInReg = OpInfo.hasMatchingInput(); 5502 break; 5503 case InlineAsm::isInput: 5504 isInReg = true; 5505 isOutReg = false; 5506 break; 5507 case InlineAsm::isClobber: 5508 isOutReg = true; 5509 isInReg = true; 5510 break; 5511 } 5512 5513 5514 MachineFunction &MF = DAG.getMachineFunction(); 5515 SmallVector<unsigned, 4> Regs; 5516 5517 // If this is a constraint for a single physreg, or a constraint for a 5518 // register class, find it. 5519 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5520 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5521 OpInfo.ConstraintVT); 5522 5523 unsigned NumRegs = 1; 5524 if (OpInfo.ConstraintVT != MVT::Other) { 5525 // If this is a FP input in an integer register (or visa versa) insert a bit 5526 // cast of the input value. More generally, handle any case where the input 5527 // value disagrees with the register class we plan to stick this in. 5528 if (OpInfo.Type == InlineAsm::isInput && 5529 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5530 // Try to convert to the first EVT that the reg class contains. If the 5531 // types are identical size, use a bitcast to convert (e.g. two differing 5532 // vector types). 5533 EVT RegVT = *PhysReg.second->vt_begin(); 5534 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5535 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5536 RegVT, OpInfo.CallOperand); 5537 OpInfo.ConstraintVT = RegVT; 5538 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5539 // If the input is a FP value and we want it in FP registers, do a 5540 // bitcast to the corresponding integer type. This turns an f64 value 5541 // into i64, which can be passed with two i32 values on a 32-bit 5542 // machine. 5543 RegVT = EVT::getIntegerVT(Context, 5544 OpInfo.ConstraintVT.getSizeInBits()); 5545 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5546 RegVT, OpInfo.CallOperand); 5547 OpInfo.ConstraintVT = RegVT; 5548 } 5549 } 5550 5551 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5552 } 5553 5554 EVT RegVT; 5555 EVT ValueVT = OpInfo.ConstraintVT; 5556 5557 // If this is a constraint for a specific physical register, like {r17}, 5558 // assign it now. 5559 if (unsigned AssignedReg = PhysReg.first) { 5560 const TargetRegisterClass *RC = PhysReg.second; 5561 if (OpInfo.ConstraintVT == MVT::Other) 5562 ValueVT = *RC->vt_begin(); 5563 5564 // Get the actual register value type. This is important, because the user 5565 // may have asked for (e.g.) the AX register in i32 type. We need to 5566 // remember that AX is actually i16 to get the right extension. 5567 RegVT = *RC->vt_begin(); 5568 5569 // This is a explicit reference to a physical register. 5570 Regs.push_back(AssignedReg); 5571 5572 // If this is an expanded reference, add the rest of the regs to Regs. 5573 if (NumRegs != 1) { 5574 TargetRegisterClass::iterator I = RC->begin(); 5575 for (; *I != AssignedReg; ++I) 5576 assert(I != RC->end() && "Didn't find reg!"); 5577 5578 // Already added the first reg. 5579 --NumRegs; ++I; 5580 for (; NumRegs; --NumRegs, ++I) { 5581 assert(I != RC->end() && "Ran out of registers to allocate!"); 5582 Regs.push_back(*I); 5583 } 5584 } 5585 5586 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5587 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5588 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5589 return; 5590 } 5591 5592 // Otherwise, if this was a reference to an LLVM register class, create vregs 5593 // for this reference. 5594 if (const TargetRegisterClass *RC = PhysReg.second) { 5595 RegVT = *RC->vt_begin(); 5596 if (OpInfo.ConstraintVT == MVT::Other) 5597 ValueVT = RegVT; 5598 5599 // Create the appropriate number of virtual registers. 5600 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5601 for (; NumRegs; --NumRegs) 5602 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5603 5604 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5605 return; 5606 } 5607 5608 // Otherwise, we couldn't allocate enough registers for this. 5609} 5610 5611/// visitInlineAsm - Handle a call to an InlineAsm object. 5612/// 5613void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5614 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5615 5616 /// ConstraintOperands - Information about all of the constraints. 5617 SDISelAsmOperandInfoVector ConstraintOperands; 5618 5619 std::set<unsigned> OutputRegs, InputRegs; 5620 5621 TargetLowering::AsmOperandInfoVector 5622 TargetConstraints = TLI.ParseConstraints(CS); 5623 5624 bool hasMemory = false; 5625 5626 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5627 unsigned ResNo = 0; // ResNo - The result number of the next output. 5628 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5629 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5630 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5631 5632 EVT OpVT = MVT::Other; 5633 5634 // Compute the value type for each operand. 5635 switch (OpInfo.Type) { 5636 case InlineAsm::isOutput: 5637 // Indirect outputs just consume an argument. 5638 if (OpInfo.isIndirect) { 5639 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5640 break; 5641 } 5642 5643 // The return value of the call is this value. As such, there is no 5644 // corresponding argument. 5645 assert(!CS.getType()->isVoidTy() && 5646 "Bad inline asm!"); 5647 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5648 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5649 } else { 5650 assert(ResNo == 0 && "Asm only has one result!"); 5651 OpVT = TLI.getValueType(CS.getType()); 5652 } 5653 ++ResNo; 5654 break; 5655 case InlineAsm::isInput: 5656 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5657 break; 5658 case InlineAsm::isClobber: 5659 // Nothing to do. 5660 break; 5661 } 5662 5663 // If this is an input or an indirect output, process the call argument. 5664 // BasicBlocks are labels, currently appearing only in asm's. 5665 if (OpInfo.CallOperandVal) { 5666 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5667 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5668 } else { 5669 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5670 } 5671 5672 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5673 } 5674 5675 OpInfo.ConstraintVT = OpVT; 5676 5677 // Indirect operand accesses access memory. 5678 if (OpInfo.isIndirect) 5679 hasMemory = true; 5680 else { 5681 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5682 TargetLowering::ConstraintType 5683 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5684 if (CType == TargetLowering::C_Memory) { 5685 hasMemory = true; 5686 break; 5687 } 5688 } 5689 } 5690 } 5691 5692 SDValue Chain, Flag; 5693 5694 // We won't need to flush pending loads if this asm doesn't touch 5695 // memory and is nonvolatile. 5696 if (hasMemory || IA->hasSideEffects()) 5697 Chain = getRoot(); 5698 else 5699 Chain = DAG.getRoot(); 5700 5701 // Second pass over the constraints: compute which constraint option to use 5702 // and assign registers to constraints that want a specific physreg. 5703 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5704 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5705 5706 // If this is an output operand with a matching input operand, look up the 5707 // matching input. If their types mismatch, e.g. one is an integer, the 5708 // other is floating point, or their sizes are different, flag it as an 5709 // error. 5710 if (OpInfo.hasMatchingInput()) { 5711 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5712 5713 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5714 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5715 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT); 5716 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5717 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT); 5718 if ((OpInfo.ConstraintVT.isInteger() != 5719 Input.ConstraintVT.isInteger()) || 5720 (MatchRC.second != InputRC.second)) { 5721 report_fatal_error("Unsupported asm: input constraint" 5722 " with a matching output constraint of" 5723 " incompatible type!"); 5724 } 5725 Input.ConstraintVT = OpInfo.ConstraintVT; 5726 } 5727 } 5728 5729 // Compute the constraint code and ConstraintType to use. 5730 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5731 5732 // If this is a memory input, and if the operand is not indirect, do what we 5733 // need to to provide an address for the memory input. 5734 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5735 !OpInfo.isIndirect) { 5736 assert((OpInfo.isMultipleAlternative || 5737 (OpInfo.Type == InlineAsm::isInput)) && 5738 "Can only indirectify direct input operands!"); 5739 5740 // Memory operands really want the address of the value. If we don't have 5741 // an indirect input, put it in the constpool if we can, otherwise spill 5742 // it to a stack slot. 5743 // TODO: This isn't quite right. We need to handle these according to 5744 // the addressing mode that the constraint wants. Also, this may take 5745 // an additional register for the computation and we don't want that 5746 // either. 5747 5748 // If the operand is a float, integer, or vector constant, spill to a 5749 // constant pool entry to get its address. 5750 const Value *OpVal = OpInfo.CallOperandVal; 5751 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5752 isa<ConstantVector>(OpVal)) { 5753 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5754 TLI.getPointerTy()); 5755 } else { 5756 // Otherwise, create a stack slot and emit a store to it before the 5757 // asm. 5758 Type *Ty = OpVal->getType(); 5759 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5760 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5761 MachineFunction &MF = DAG.getMachineFunction(); 5762 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5763 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5764 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5765 OpInfo.CallOperand, StackSlot, 5766 MachinePointerInfo::getFixedStack(SSFI), 5767 false, false, 0); 5768 OpInfo.CallOperand = StackSlot; 5769 } 5770 5771 // There is no longer a Value* corresponding to this operand. 5772 OpInfo.CallOperandVal = 0; 5773 5774 // It is now an indirect operand. 5775 OpInfo.isIndirect = true; 5776 } 5777 5778 // If this constraint is for a specific register, allocate it before 5779 // anything else. 5780 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5781 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5782 InputRegs); 5783 } 5784 5785 // Second pass - Loop over all of the operands, assigning virtual or physregs 5786 // to register class operands. 5787 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5788 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5789 5790 // C_Register operands have already been allocated, Other/Memory don't need 5791 // to be. 5792 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5793 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5794 InputRegs); 5795 } 5796 5797 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5798 std::vector<SDValue> AsmNodeOperands; 5799 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5800 AsmNodeOperands.push_back( 5801 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5802 TLI.getPointerTy())); 5803 5804 // If we have a !srcloc metadata node associated with it, we want to attach 5805 // this to the ultimately generated inline asm machineinstr. To do this, we 5806 // pass in the third operand as this (potentially null) inline asm MDNode. 5807 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5808 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5809 5810 // Remember the HasSideEffect and AlignStack bits as operand 3. 5811 unsigned ExtraInfo = 0; 5812 if (IA->hasSideEffects()) 5813 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 5814 if (IA->isAlignStack()) 5815 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 5816 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 5817 TLI.getPointerTy())); 5818 5819 // Loop over all of the inputs, copying the operand values into the 5820 // appropriate registers and processing the output regs. 5821 RegsForValue RetValRegs; 5822 5823 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5824 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5825 5826 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5827 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5828 5829 switch (OpInfo.Type) { 5830 case InlineAsm::isOutput: { 5831 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5832 OpInfo.ConstraintType != TargetLowering::C_Register) { 5833 // Memory output, or 'other' output (e.g. 'X' constraint). 5834 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5835 5836 // Add information to the INLINEASM node to know about this output. 5837 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5838 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5839 TLI.getPointerTy())); 5840 AsmNodeOperands.push_back(OpInfo.CallOperand); 5841 break; 5842 } 5843 5844 // Otherwise, this is a register or register class output. 5845 5846 // Copy the output from the appropriate register. Find a register that 5847 // we can use. 5848 if (OpInfo.AssignedRegs.Regs.empty()) 5849 report_fatal_error("Couldn't allocate output reg for constraint '" + 5850 Twine(OpInfo.ConstraintCode) + "'!"); 5851 5852 // If this is an indirect operand, store through the pointer after the 5853 // asm. 5854 if (OpInfo.isIndirect) { 5855 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5856 OpInfo.CallOperandVal)); 5857 } else { 5858 // This is the result value of the call. 5859 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5860 // Concatenate this output onto the outputs list. 5861 RetValRegs.append(OpInfo.AssignedRegs); 5862 } 5863 5864 // Add information to the INLINEASM node to know that this register is 5865 // set. 5866 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5867 InlineAsm::Kind_RegDefEarlyClobber : 5868 InlineAsm::Kind_RegDef, 5869 false, 5870 0, 5871 DAG, 5872 AsmNodeOperands); 5873 break; 5874 } 5875 case InlineAsm::isInput: { 5876 SDValue InOperandVal = OpInfo.CallOperand; 5877 5878 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5879 // If this is required to match an output register we have already set, 5880 // just use its register. 5881 unsigned OperandNo = OpInfo.getMatchedOperand(); 5882 5883 // Scan until we find the definition we already emitted of this operand. 5884 // When we find it, create a RegsForValue operand. 5885 unsigned CurOp = InlineAsm::Op_FirstOperand; 5886 for (; OperandNo; --OperandNo) { 5887 // Advance to the next operand. 5888 unsigned OpFlag = 5889 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5890 assert((InlineAsm::isRegDefKind(OpFlag) || 5891 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5892 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5893 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5894 } 5895 5896 unsigned OpFlag = 5897 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5898 if (InlineAsm::isRegDefKind(OpFlag) || 5899 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5900 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5901 if (OpInfo.isIndirect) { 5902 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5903 LLVMContext &Ctx = *DAG.getContext(); 5904 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5905 " don't know how to handle tied " 5906 "indirect register inputs"); 5907 } 5908 5909 RegsForValue MatchedRegs; 5910 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5911 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5912 MatchedRegs.RegVTs.push_back(RegVT); 5913 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5914 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5915 i != e; ++i) 5916 MatchedRegs.Regs.push_back 5917 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5918 5919 // Use the produced MatchedRegs object to 5920 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5921 Chain, &Flag); 5922 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 5923 true, OpInfo.getMatchedOperand(), 5924 DAG, AsmNodeOperands); 5925 break; 5926 } 5927 5928 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 5929 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 5930 "Unexpected number of operands"); 5931 // Add information to the INLINEASM node to know about this input. 5932 // See InlineAsm.h isUseOperandTiedToDef. 5933 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 5934 OpInfo.getMatchedOperand()); 5935 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5936 TLI.getPointerTy())); 5937 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5938 break; 5939 } 5940 5941 // Treat indirect 'X' constraint as memory. 5942 if (OpInfo.ConstraintType == TargetLowering::C_Other && 5943 OpInfo.isIndirect) 5944 OpInfo.ConstraintType = TargetLowering::C_Memory; 5945 5946 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5947 std::vector<SDValue> Ops; 5948 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 5949 Ops, DAG); 5950 if (Ops.empty()) 5951 report_fatal_error("Invalid operand for inline asm constraint '" + 5952 Twine(OpInfo.ConstraintCode) + "'!"); 5953 5954 // Add information to the INLINEASM node to know about this input. 5955 unsigned ResOpType = 5956 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 5957 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5958 TLI.getPointerTy())); 5959 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5960 break; 5961 } 5962 5963 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5964 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5965 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5966 "Memory operands expect pointer values"); 5967 5968 // Add information to the INLINEASM node to know about this input. 5969 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5970 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5971 TLI.getPointerTy())); 5972 AsmNodeOperands.push_back(InOperandVal); 5973 break; 5974 } 5975 5976 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5977 OpInfo.ConstraintType == TargetLowering::C_Register) && 5978 "Unknown constraint type!"); 5979 assert(!OpInfo.isIndirect && 5980 "Don't know how to handle indirect register inputs yet!"); 5981 5982 // Copy the input into the appropriate registers. 5983 if (OpInfo.AssignedRegs.Regs.empty()) 5984 report_fatal_error("Couldn't allocate input reg for constraint '" + 5985 Twine(OpInfo.ConstraintCode) + "'!"); 5986 5987 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5988 Chain, &Flag); 5989 5990 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 5991 DAG, AsmNodeOperands); 5992 break; 5993 } 5994 case InlineAsm::isClobber: { 5995 // Add the clobbered value to the operand list, so that the register 5996 // allocator is aware that the physreg got clobbered. 5997 if (!OpInfo.AssignedRegs.Regs.empty()) 5998 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 5999 false, 0, DAG, 6000 AsmNodeOperands); 6001 break; 6002 } 6003 } 6004 } 6005 6006 // Finish up input operands. Set the input chain and add the flag last. 6007 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6008 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6009 6010 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6011 DAG.getVTList(MVT::Other, MVT::Glue), 6012 &AsmNodeOperands[0], AsmNodeOperands.size()); 6013 Flag = Chain.getValue(1); 6014 6015 // If this asm returns a register value, copy the result from that register 6016 // and set it as the value of the call. 6017 if (!RetValRegs.Regs.empty()) { 6018 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6019 Chain, &Flag); 6020 6021 // FIXME: Why don't we do this for inline asms with MRVs? 6022 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6023 EVT ResultType = TLI.getValueType(CS.getType()); 6024 6025 // If any of the results of the inline asm is a vector, it may have the 6026 // wrong width/num elts. This can happen for register classes that can 6027 // contain multiple different value types. The preg or vreg allocated may 6028 // not have the same VT as was expected. Convert it to the right type 6029 // with bit_convert. 6030 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6031 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6032 ResultType, Val); 6033 6034 } else if (ResultType != Val.getValueType() && 6035 ResultType.isInteger() && Val.getValueType().isInteger()) { 6036 // If a result value was tied to an input value, the computed result may 6037 // have a wider width than the expected result. Extract the relevant 6038 // portion. 6039 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6040 } 6041 6042 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6043 } 6044 6045 setValue(CS.getInstruction(), Val); 6046 // Don't need to use this as a chain in this case. 6047 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6048 return; 6049 } 6050 6051 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6052 6053 // Process indirect outputs, first output all of the flagged copies out of 6054 // physregs. 6055 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6056 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6057 const Value *Ptr = IndirectStoresToEmit[i].second; 6058 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6059 Chain, &Flag); 6060 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6061 } 6062 6063 // Emit the non-flagged stores from the physregs. 6064 SmallVector<SDValue, 8> OutChains; 6065 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6066 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6067 StoresToEmit[i].first, 6068 getValue(StoresToEmit[i].second), 6069 MachinePointerInfo(StoresToEmit[i].second), 6070 false, false, 0); 6071 OutChains.push_back(Val); 6072 } 6073 6074 if (!OutChains.empty()) 6075 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6076 &OutChains[0], OutChains.size()); 6077 6078 DAG.setRoot(Chain); 6079} 6080 6081void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6082 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6083 MVT::Other, getRoot(), 6084 getValue(I.getArgOperand(0)), 6085 DAG.getSrcValue(I.getArgOperand(0)))); 6086} 6087 6088void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6089 const TargetData &TD = *TLI.getTargetData(); 6090 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6091 getRoot(), getValue(I.getOperand(0)), 6092 DAG.getSrcValue(I.getOperand(0)), 6093 TD.getABITypeAlignment(I.getType())); 6094 setValue(&I, V); 6095 DAG.setRoot(V.getValue(1)); 6096} 6097 6098void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6099 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6100 MVT::Other, getRoot(), 6101 getValue(I.getArgOperand(0)), 6102 DAG.getSrcValue(I.getArgOperand(0)))); 6103} 6104 6105void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6106 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6107 MVT::Other, getRoot(), 6108 getValue(I.getArgOperand(0)), 6109 getValue(I.getArgOperand(1)), 6110 DAG.getSrcValue(I.getArgOperand(0)), 6111 DAG.getSrcValue(I.getArgOperand(1)))); 6112} 6113 6114/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6115/// implementation, which just calls LowerCall. 6116/// FIXME: When all targets are 6117/// migrated to using LowerCall, this hook should be integrated into SDISel. 6118std::pair<SDValue, SDValue> 6119TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy, 6120 bool RetSExt, bool RetZExt, bool isVarArg, 6121 bool isInreg, unsigned NumFixedArgs, 6122 CallingConv::ID CallConv, bool isTailCall, 6123 bool isReturnValueUsed, 6124 SDValue Callee, 6125 ArgListTy &Args, SelectionDAG &DAG, 6126 DebugLoc dl) const { 6127 // Handle all of the outgoing arguments. 6128 SmallVector<ISD::OutputArg, 32> Outs; 6129 SmallVector<SDValue, 32> OutVals; 6130 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6131 SmallVector<EVT, 4> ValueVTs; 6132 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6133 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6134 Value != NumValues; ++Value) { 6135 EVT VT = ValueVTs[Value]; 6136 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6137 SDValue Op = SDValue(Args[i].Node.getNode(), 6138 Args[i].Node.getResNo() + Value); 6139 ISD::ArgFlagsTy Flags; 6140 unsigned OriginalAlignment = 6141 getTargetData()->getABITypeAlignment(ArgTy); 6142 6143 if (Args[i].isZExt) 6144 Flags.setZExt(); 6145 if (Args[i].isSExt) 6146 Flags.setSExt(); 6147 if (Args[i].isInReg) 6148 Flags.setInReg(); 6149 if (Args[i].isSRet) 6150 Flags.setSRet(); 6151 if (Args[i].isByVal) { 6152 Flags.setByVal(); 6153 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6154 Type *ElementTy = Ty->getElementType(); 6155 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6156 // For ByVal, alignment should come from FE. BE will guess if this 6157 // info is not there but there are cases it cannot get right. 6158 unsigned FrameAlign; 6159 if (Args[i].Alignment) 6160 FrameAlign = Args[i].Alignment; 6161 else 6162 FrameAlign = getByValTypeAlignment(ElementTy); 6163 Flags.setByValAlign(FrameAlign); 6164 } 6165 if (Args[i].isNest) 6166 Flags.setNest(); 6167 Flags.setOrigAlign(OriginalAlignment); 6168 6169 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6170 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6171 SmallVector<SDValue, 4> Parts(NumParts); 6172 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6173 6174 if (Args[i].isSExt) 6175 ExtendKind = ISD::SIGN_EXTEND; 6176 else if (Args[i].isZExt) 6177 ExtendKind = ISD::ZERO_EXTEND; 6178 6179 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6180 PartVT, ExtendKind); 6181 6182 for (unsigned j = 0; j != NumParts; ++j) { 6183 // if it isn't first piece, alignment must be 1 6184 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6185 i < NumFixedArgs); 6186 if (NumParts > 1 && j == 0) 6187 MyFlags.Flags.setSplit(); 6188 else if (j != 0) 6189 MyFlags.Flags.setOrigAlign(1); 6190 6191 Outs.push_back(MyFlags); 6192 OutVals.push_back(Parts[j]); 6193 } 6194 } 6195 } 6196 6197 // Handle the incoming return values from the call. 6198 SmallVector<ISD::InputArg, 32> Ins; 6199 SmallVector<EVT, 4> RetTys; 6200 ComputeValueVTs(*this, RetTy, RetTys); 6201 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6202 EVT VT = RetTys[I]; 6203 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6204 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6205 for (unsigned i = 0; i != NumRegs; ++i) { 6206 ISD::InputArg MyFlags; 6207 MyFlags.VT = RegisterVT.getSimpleVT(); 6208 MyFlags.Used = isReturnValueUsed; 6209 if (RetSExt) 6210 MyFlags.Flags.setSExt(); 6211 if (RetZExt) 6212 MyFlags.Flags.setZExt(); 6213 if (isInreg) 6214 MyFlags.Flags.setInReg(); 6215 Ins.push_back(MyFlags); 6216 } 6217 } 6218 6219 SmallVector<SDValue, 4> InVals; 6220 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6221 Outs, OutVals, Ins, dl, DAG, InVals); 6222 6223 // Verify that the target's LowerCall behaved as expected. 6224 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6225 "LowerCall didn't return a valid chain!"); 6226 assert((!isTailCall || InVals.empty()) && 6227 "LowerCall emitted a return value for a tail call!"); 6228 assert((isTailCall || InVals.size() == Ins.size()) && 6229 "LowerCall didn't emit the correct number of values!"); 6230 6231 // For a tail call, the return value is merely live-out and there aren't 6232 // any nodes in the DAG representing it. Return a special value to 6233 // indicate that a tail call has been emitted and no more Instructions 6234 // should be processed in the current block. 6235 if (isTailCall) { 6236 DAG.setRoot(Chain); 6237 return std::make_pair(SDValue(), SDValue()); 6238 } 6239 6240 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6241 assert(InVals[i].getNode() && 6242 "LowerCall emitted a null value!"); 6243 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6244 "LowerCall emitted a value with the wrong type!"); 6245 }); 6246 6247 // Collect the legal value parts into potentially illegal values 6248 // that correspond to the original function's return values. 6249 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6250 if (RetSExt) 6251 AssertOp = ISD::AssertSext; 6252 else if (RetZExt) 6253 AssertOp = ISD::AssertZext; 6254 SmallVector<SDValue, 4> ReturnValues; 6255 unsigned CurReg = 0; 6256 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6257 EVT VT = RetTys[I]; 6258 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6259 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6260 6261 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6262 NumRegs, RegisterVT, VT, 6263 AssertOp)); 6264 CurReg += NumRegs; 6265 } 6266 6267 // For a function returning void, there is no return value. We can't create 6268 // such a node, so we just return a null return value in that case. In 6269 // that case, nothing will actually look at the value. 6270 if (ReturnValues.empty()) 6271 return std::make_pair(SDValue(), Chain); 6272 6273 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6274 DAG.getVTList(&RetTys[0], RetTys.size()), 6275 &ReturnValues[0], ReturnValues.size()); 6276 return std::make_pair(Res, Chain); 6277} 6278 6279void TargetLowering::LowerOperationWrapper(SDNode *N, 6280 SmallVectorImpl<SDValue> &Results, 6281 SelectionDAG &DAG) const { 6282 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6283 if (Res.getNode()) 6284 Results.push_back(Res); 6285} 6286 6287SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6288 llvm_unreachable("LowerOperation not implemented for this target!"); 6289 return SDValue(); 6290} 6291 6292void 6293SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6294 SDValue Op = getNonRegisterValue(V); 6295 assert((Op.getOpcode() != ISD::CopyFromReg || 6296 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6297 "Copy from a reg to the same reg!"); 6298 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6299 6300 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6301 SDValue Chain = DAG.getEntryNode(); 6302 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6303 PendingExports.push_back(Chain); 6304} 6305 6306#include "llvm/CodeGen/SelectionDAGISel.h" 6307 6308/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6309/// entry block, return true. This includes arguments used by switches, since 6310/// the switch may expand into multiple basic blocks. 6311static bool isOnlyUsedInEntryBlock(const Argument *A) { 6312 // With FastISel active, we may be splitting blocks, so force creation 6313 // of virtual registers for all non-dead arguments. 6314 if (EnableFastISel) 6315 return A->use_empty(); 6316 6317 const BasicBlock *Entry = A->getParent()->begin(); 6318 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6319 UI != E; ++UI) { 6320 const User *U = *UI; 6321 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6322 return false; // Use not in entry block. 6323 } 6324 return true; 6325} 6326 6327void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6328 // If this is the entry block, emit arguments. 6329 const Function &F = *LLVMBB->getParent(); 6330 SelectionDAG &DAG = SDB->DAG; 6331 DebugLoc dl = SDB->getCurDebugLoc(); 6332 const TargetData *TD = TLI.getTargetData(); 6333 SmallVector<ISD::InputArg, 16> Ins; 6334 6335 // Check whether the function can return without sret-demotion. 6336 SmallVector<ISD::OutputArg, 4> Outs; 6337 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6338 Outs, TLI); 6339 6340 if (!FuncInfo->CanLowerReturn) { 6341 // Put in an sret pointer parameter before all the other parameters. 6342 SmallVector<EVT, 1> ValueVTs; 6343 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6344 6345 // NOTE: Assuming that a pointer will never break down to more than one VT 6346 // or one register. 6347 ISD::ArgFlagsTy Flags; 6348 Flags.setSRet(); 6349 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6350 ISD::InputArg RetArg(Flags, RegisterVT, true); 6351 Ins.push_back(RetArg); 6352 } 6353 6354 // Set up the incoming argument description vector. 6355 unsigned Idx = 1; 6356 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6357 I != E; ++I, ++Idx) { 6358 SmallVector<EVT, 4> ValueVTs; 6359 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6360 bool isArgValueUsed = !I->use_empty(); 6361 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6362 Value != NumValues; ++Value) { 6363 EVT VT = ValueVTs[Value]; 6364 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6365 ISD::ArgFlagsTy Flags; 6366 unsigned OriginalAlignment = 6367 TD->getABITypeAlignment(ArgTy); 6368 6369 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6370 Flags.setZExt(); 6371 if (F.paramHasAttr(Idx, Attribute::SExt)) 6372 Flags.setSExt(); 6373 if (F.paramHasAttr(Idx, Attribute::InReg)) 6374 Flags.setInReg(); 6375 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6376 Flags.setSRet(); 6377 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6378 Flags.setByVal(); 6379 PointerType *Ty = cast<PointerType>(I->getType()); 6380 Type *ElementTy = Ty->getElementType(); 6381 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6382 // For ByVal, alignment should be passed from FE. BE will guess if 6383 // this info is not there but there are cases it cannot get right. 6384 unsigned FrameAlign; 6385 if (F.getParamAlignment(Idx)) 6386 FrameAlign = F.getParamAlignment(Idx); 6387 else 6388 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6389 Flags.setByValAlign(FrameAlign); 6390 } 6391 if (F.paramHasAttr(Idx, Attribute::Nest)) 6392 Flags.setNest(); 6393 Flags.setOrigAlign(OriginalAlignment); 6394 6395 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6396 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6397 for (unsigned i = 0; i != NumRegs; ++i) { 6398 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6399 if (NumRegs > 1 && i == 0) 6400 MyFlags.Flags.setSplit(); 6401 // if it isn't first piece, alignment must be 1 6402 else if (i > 0) 6403 MyFlags.Flags.setOrigAlign(1); 6404 Ins.push_back(MyFlags); 6405 } 6406 } 6407 } 6408 6409 // Call the target to set up the argument values. 6410 SmallVector<SDValue, 8> InVals; 6411 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6412 F.isVarArg(), Ins, 6413 dl, DAG, InVals); 6414 6415 // Verify that the target's LowerFormalArguments behaved as expected. 6416 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6417 "LowerFormalArguments didn't return a valid chain!"); 6418 assert(InVals.size() == Ins.size() && 6419 "LowerFormalArguments didn't emit the correct number of values!"); 6420 DEBUG({ 6421 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6422 assert(InVals[i].getNode() && 6423 "LowerFormalArguments emitted a null value!"); 6424 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6425 "LowerFormalArguments emitted a value with the wrong type!"); 6426 } 6427 }); 6428 6429 // Update the DAG with the new chain value resulting from argument lowering. 6430 DAG.setRoot(NewRoot); 6431 6432 // Set up the argument values. 6433 unsigned i = 0; 6434 Idx = 1; 6435 if (!FuncInfo->CanLowerReturn) { 6436 // Create a virtual register for the sret pointer, and put in a copy 6437 // from the sret argument into it. 6438 SmallVector<EVT, 1> ValueVTs; 6439 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6440 EVT VT = ValueVTs[0]; 6441 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6442 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6443 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6444 RegVT, VT, AssertOp); 6445 6446 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6447 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6448 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6449 FuncInfo->DemoteRegister = SRetReg; 6450 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6451 SRetReg, ArgValue); 6452 DAG.setRoot(NewRoot); 6453 6454 // i indexes lowered arguments. Bump it past the hidden sret argument. 6455 // Idx indexes LLVM arguments. Don't touch it. 6456 ++i; 6457 } 6458 6459 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6460 ++I, ++Idx) { 6461 SmallVector<SDValue, 4> ArgValues; 6462 SmallVector<EVT, 4> ValueVTs; 6463 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6464 unsigned NumValues = ValueVTs.size(); 6465 6466 // If this argument is unused then remember its value. It is used to generate 6467 // debugging information. 6468 if (I->use_empty() && NumValues) 6469 SDB->setUnusedArgValue(I, InVals[i]); 6470 6471 for (unsigned Val = 0; Val != NumValues; ++Val) { 6472 EVT VT = ValueVTs[Val]; 6473 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6474 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6475 6476 if (!I->use_empty()) { 6477 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6478 if (F.paramHasAttr(Idx, Attribute::SExt)) 6479 AssertOp = ISD::AssertSext; 6480 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6481 AssertOp = ISD::AssertZext; 6482 6483 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6484 NumParts, PartVT, VT, 6485 AssertOp)); 6486 } 6487 6488 i += NumParts; 6489 } 6490 6491 // We don't need to do anything else for unused arguments. 6492 if (ArgValues.empty()) 6493 continue; 6494 6495 // Note down frame index for byval arguments. 6496 if (I->hasByValAttr()) 6497 if (FrameIndexSDNode *FI = 6498 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6499 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6500 6501 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6502 SDB->getCurDebugLoc()); 6503 SDB->setValue(I, Res); 6504 6505 // If this argument is live outside of the entry block, insert a copy from 6506 // wherever we got it to the vreg that other BB's will reference it as. 6507 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6508 // If we can, though, try to skip creating an unnecessary vreg. 6509 // FIXME: This isn't very clean... it would be nice to make this more 6510 // general. It's also subtly incompatible with the hacks FastISel 6511 // uses with vregs. 6512 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6513 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6514 FuncInfo->ValueMap[I] = Reg; 6515 continue; 6516 } 6517 } 6518 if (!isOnlyUsedInEntryBlock(I)) { 6519 FuncInfo->InitializeRegForValue(I); 6520 SDB->CopyToExportRegsIfNeeded(I); 6521 } 6522 } 6523 6524 assert(i == InVals.size() && "Argument register count mismatch!"); 6525 6526 // Finally, if the target has anything special to do, allow it to do so. 6527 // FIXME: this should insert code into the DAG! 6528 EmitFunctionEntryCode(); 6529} 6530 6531/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6532/// ensure constants are generated when needed. Remember the virtual registers 6533/// that need to be added to the Machine PHI nodes as input. We cannot just 6534/// directly add them, because expansion might result in multiple MBB's for one 6535/// BB. As such, the start of the BB might correspond to a different MBB than 6536/// the end. 6537/// 6538void 6539SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6540 const TerminatorInst *TI = LLVMBB->getTerminator(); 6541 6542 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6543 6544 // Check successor nodes' PHI nodes that expect a constant to be available 6545 // from this block. 6546 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6547 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6548 if (!isa<PHINode>(SuccBB->begin())) continue; 6549 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6550 6551 // If this terminator has multiple identical successors (common for 6552 // switches), only handle each succ once. 6553 if (!SuccsHandled.insert(SuccMBB)) continue; 6554 6555 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6556 6557 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6558 // nodes and Machine PHI nodes, but the incoming operands have not been 6559 // emitted yet. 6560 for (BasicBlock::const_iterator I = SuccBB->begin(); 6561 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6562 // Ignore dead phi's. 6563 if (PN->use_empty()) continue; 6564 6565 // Skip empty types 6566 if (PN->getType()->isEmptyTy()) 6567 continue; 6568 6569 unsigned Reg; 6570 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6571 6572 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6573 unsigned &RegOut = ConstantsOut[C]; 6574 if (RegOut == 0) { 6575 RegOut = FuncInfo.CreateRegs(C->getType()); 6576 CopyValueToVirtualRegister(C, RegOut); 6577 } 6578 Reg = RegOut; 6579 } else { 6580 DenseMap<const Value *, unsigned>::iterator I = 6581 FuncInfo.ValueMap.find(PHIOp); 6582 if (I != FuncInfo.ValueMap.end()) 6583 Reg = I->second; 6584 else { 6585 assert(isa<AllocaInst>(PHIOp) && 6586 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6587 "Didn't codegen value into a register!??"); 6588 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6589 CopyValueToVirtualRegister(PHIOp, Reg); 6590 } 6591 } 6592 6593 // Remember that this register needs to added to the machine PHI node as 6594 // the input for this MBB. 6595 SmallVector<EVT, 4> ValueVTs; 6596 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6597 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6598 EVT VT = ValueVTs[vti]; 6599 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6600 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6601 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6602 Reg += NumRegisters; 6603 } 6604 } 6605 } 6606 ConstantsOut.clear(); 6607} 6608