SelectionDAGBuilder.cpp revision ac6d9bec671252dd1e596fa71180ff6b39d06b5d
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SelectionDAGBuilder.h" 16#include "SDNodeDbgValue.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/SmallSet.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/BranchProbabilityInfo.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Analysis/ValueTracking.h" 23#include "llvm/CodeGen/Analysis.h" 24#include "llvm/CodeGen/FastISel.h" 25#include "llvm/CodeGen/FunctionLoweringInfo.h" 26#include "llvm/CodeGen/GCMetadata.h" 27#include "llvm/CodeGen/GCStrategy.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineJumpTableInfo.h" 32#include "llvm/CodeGen/MachineModuleInfo.h" 33#include "llvm/CodeGen/MachineRegisterInfo.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/DebugInfo.h" 36#include "llvm/IR/CallingConv.h" 37#include "llvm/IR/Constants.h" 38#include "llvm/IR/DataLayout.h" 39#include "llvm/IR/DerivedTypes.h" 40#include "llvm/IR/Function.h" 41#include "llvm/IR/GlobalVariable.h" 42#include "llvm/IR/InlineAsm.h" 43#include "llvm/IR/Instructions.h" 44#include "llvm/IR/IntrinsicInst.h" 45#include "llvm/IR/Intrinsics.h" 46#include "llvm/IR/LLVMContext.h" 47#include "llvm/IR/Module.h" 48#include "llvm/Support/CommandLine.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/ErrorHandling.h" 51#include "llvm/Support/IntegersSubsetMapping.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54#include "llvm/Target/TargetFrameLowering.h" 55#include "llvm/Target/TargetInstrInfo.h" 56#include "llvm/Target/TargetIntrinsicInfo.h" 57#include "llvm/Target/TargetLibraryInfo.h" 58#include "llvm/Target/TargetLowering.h" 59#include "llvm/Target/TargetOptions.h" 60#include <algorithm> 61using namespace llvm; 62 63/// LimitFloatPrecision - Generate low-precision inline sequences for 64/// some float libcalls (6, 8 or 12 bits). 65static unsigned LimitFloatPrecision; 66 67static cl::opt<unsigned, true> 68LimitFPPrecision("limit-float-precision", 69 cl::desc("Generate low-precision inline sequences " 70 "for some float libcalls"), 71 cl::location(LimitFloatPrecision), 72 cl::init(0)); 73 74// Limit the width of DAG chains. This is important in general to prevent 75// prevent DAG-based analysis from blowing up. For example, alias analysis and 76// load clustering may not complete in reasonable time. It is difficult to 77// recognize and avoid this situation within each individual analysis, and 78// future analyses are likely to have the same behavior. Limiting DAG width is 79// the safe approach, and will be especially important with global DAGs. 80// 81// MaxParallelChains default is arbitrarily high to avoid affecting 82// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 83// sequence over this should have been converted to llvm.memcpy by the 84// frontend. It easy to induce this behavior with .ll code such as: 85// %buffer = alloca [4096 x i8] 86// %data = load [4096 x i8]* %argPtr 87// store [4096 x i8] %data, [4096 x i8]* %buffer 88static const unsigned MaxParallelChains = 64; 89 90static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL, 91 const SDValue *Parts, unsigned NumParts, 92 MVT PartVT, EVT ValueVT, const Value *V); 93 94/// getCopyFromParts - Create a value that contains the specified legal parts 95/// combined into the value they represent. If the parts combine to a type 96/// larger then ValueVT then AssertOp can be used to specify whether the extra 97/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 98/// (ISD::AssertSext). 99static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL, 100 const SDValue *Parts, 101 unsigned NumParts, MVT PartVT, EVT ValueVT, 102 const Value *V, 103 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 104 if (ValueVT.isVector()) 105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, 106 PartVT, ValueVT, V); 107 108 assert(NumParts > 0 && "No parts to assemble!"); 109 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 110 SDValue Val = Parts[0]; 111 112 if (NumParts > 1) { 113 // Assemble the value from multiple parts. 114 if (ValueVT.isInteger()) { 115 unsigned PartBits = PartVT.getSizeInBits(); 116 unsigned ValueBits = ValueVT.getSizeInBits(); 117 118 // Assemble the power of 2 part. 119 unsigned RoundParts = NumParts & (NumParts - 1) ? 120 1 << Log2_32(NumParts) : NumParts; 121 unsigned RoundBits = PartBits * RoundParts; 122 EVT RoundVT = RoundBits == ValueBits ? 123 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 124 SDValue Lo, Hi; 125 126 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 127 128 if (RoundParts > 2) { 129 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 130 PartVT, HalfVT, V); 131 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 132 RoundParts / 2, PartVT, HalfVT, V); 133 } else { 134 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 135 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 136 } 137 138 if (TLI.isBigEndian()) 139 std::swap(Lo, Hi); 140 141 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 142 143 if (RoundParts < NumParts) { 144 // Assemble the trailing non-power-of-2 part. 145 unsigned OddParts = NumParts - RoundParts; 146 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 147 Hi = getCopyFromParts(DAG, DL, 148 Parts + RoundParts, OddParts, PartVT, OddVT, V); 149 150 // Combine the round and odd parts. 151 Lo = Val; 152 if (TLI.isBigEndian()) 153 std::swap(Lo, Hi); 154 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 155 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 156 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 157 DAG.getConstant(Lo.getValueType().getSizeInBits(), 158 TLI.getPointerTy())); 159 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 160 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 161 } 162 } else if (PartVT.isFloatingPoint()) { 163 // FP split into multiple FP parts (for ppcf128) 164 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && 165 "Unexpected split"); 166 SDValue Lo, Hi; 167 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 168 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 169 if (TLI.isBigEndian()) 170 std::swap(Lo, Hi); 171 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 172 } else { 173 // FP split into integer parts (soft fp) 174 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 175 !PartVT.isVector() && "Unexpected split"); 176 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 177 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V); 178 } 179 } 180 181 // There is now one part, held in Val. Correct it to match ValueVT. 182 EVT PartEVT = Val.getValueType(); 183 184 if (PartEVT == ValueVT) 185 return Val; 186 187 if (PartEVT.isInteger() && ValueVT.isInteger()) { 188 if (ValueVT.bitsLT(PartEVT)) { 189 // For a truncate, see if we have any information to 190 // indicate whether the truncated bits will always be 191 // zero or sign-extension. 192 if (AssertOp != ISD::DELETED_NODE) 193 Val = DAG.getNode(AssertOp, DL, PartEVT, Val, 194 DAG.getValueType(ValueVT)); 195 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 196 } 197 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 198 } 199 200 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 201 // FP_ROUND's are always exact here. 202 if (ValueVT.bitsLT(Val.getValueType())) 203 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 204 DAG.getTargetConstant(1, TLI.getPointerTy())); 205 206 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 207 } 208 209 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits()) 210 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 211 212 llvm_unreachable("Unknown mismatch!"); 213} 214 215/// getCopyFromPartsVector - Create a value that contains the specified legal 216/// parts combined into the value they represent. If the parts combine to a 217/// type larger then ValueVT then AssertOp can be used to specify whether the 218/// extra bits are known to be zero (ISD::AssertZext) or sign extended from 219/// ValueVT (ISD::AssertSext). 220static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL, 221 const SDValue *Parts, unsigned NumParts, 222 MVT PartVT, EVT ValueVT, const Value *V) { 223 assert(ValueVT.isVector() && "Not a vector value"); 224 assert(NumParts > 0 && "No parts to assemble!"); 225 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 226 SDValue Val = Parts[0]; 227 228 // Handle a multi-element vector. 229 if (NumParts > 1) { 230 EVT IntermediateVT; 231 MVT RegisterVT; 232 unsigned NumIntermediates; 233 unsigned NumRegs = 234 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 235 NumIntermediates, RegisterVT); 236 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 237 NumParts = NumRegs; // Silence a compiler warning. 238 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 239 assert(RegisterVT == Parts[0].getSimpleValueType() && 240 "Part type doesn't match part!"); 241 242 // Assemble the parts into intermediate operands. 243 SmallVector<SDValue, 8> Ops(NumIntermediates); 244 if (NumIntermediates == NumParts) { 245 // If the register was not expanded, truncate or copy the value, 246 // as appropriate. 247 for (unsigned i = 0; i != NumParts; ++i) 248 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 249 PartVT, IntermediateVT, V); 250 } else if (NumParts > 0) { 251 // If the intermediate type was expanded, build the intermediate 252 // operands from the parts. 253 assert(NumParts % NumIntermediates == 0 && 254 "Must expand into a divisible number of parts!"); 255 unsigned Factor = NumParts / NumIntermediates; 256 for (unsigned i = 0; i != NumIntermediates; ++i) 257 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 258 PartVT, IntermediateVT, V); 259 } 260 261 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 262 // intermediate operands. 263 Val = DAG.getNode(IntermediateVT.isVector() ? 264 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 265 ValueVT, &Ops[0], NumIntermediates); 266 } 267 268 // There is now one part, held in Val. Correct it to match ValueVT. 269 EVT PartEVT = Val.getValueType(); 270 271 if (PartEVT == ValueVT) 272 return Val; 273 274 if (PartEVT.isVector()) { 275 // If the element type of the source/dest vectors are the same, but the 276 // parts vector has more elements than the value vector, then we have a 277 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 278 // elements we want. 279 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) { 280 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 281 "Cannot narrow, it would be a lossy transformation"); 282 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 283 DAG.getIntPtrConstant(0)); 284 } 285 286 // Vector/Vector bitcast. 287 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) 288 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 289 290 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 291 "Cannot handle this kind of promotion"); 292 // Promoted vector extract 293 bool Smaller = ValueVT.bitsLE(PartEVT); 294 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 295 DL, ValueVT, Val); 296 297 } 298 299 // Trivial bitcast if the types are the same size and the destination 300 // vector type is legal. 301 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() && 302 TLI.isTypeLegal(ValueVT)) 303 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 304 305 // Handle cases such as i8 -> <1 x i1> 306 if (ValueVT.getVectorNumElements() != 1) { 307 LLVMContext &Ctx = *DAG.getContext(); 308 Twine ErrMsg("non-trivial scalar-to-vector conversion"); 309 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) { 310 if (const CallInst *CI = dyn_cast<CallInst>(I)) 311 if (isa<InlineAsm>(CI->getCalledValue())) 312 ErrMsg = ErrMsg + ", possible invalid constraint for vector type"; 313 Ctx.emitError(I, ErrMsg); 314 } else { 315 Ctx.emitError(ErrMsg); 316 } 317 return DAG.getUNDEF(ValueVT); 318 } 319 320 if (ValueVT.getVectorNumElements() == 1 && 321 ValueVT.getVectorElementType() != PartEVT) { 322 bool Smaller = ValueVT.bitsLE(PartEVT); 323 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 324 DL, ValueVT.getScalarType(), Val); 325 } 326 327 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 328} 329 330static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl, 331 SDValue Val, SDValue *Parts, unsigned NumParts, 332 MVT PartVT, const Value *V); 333 334/// getCopyToParts - Create a series of nodes that contain the specified value 335/// split into legal parts. If the parts contain more bits than Val, then, for 336/// integers, ExtendKind can be used to specify how to generate the extra bits. 337static void getCopyToParts(SelectionDAG &DAG, SDLoc DL, 338 SDValue Val, SDValue *Parts, unsigned NumParts, 339 MVT PartVT, const Value *V, 340 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 341 EVT ValueVT = Val.getValueType(); 342 343 // Handle the vector case separately. 344 if (ValueVT.isVector()) 345 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V); 346 347 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 348 unsigned PartBits = PartVT.getSizeInBits(); 349 unsigned OrigNumParts = NumParts; 350 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 351 352 if (NumParts == 0) 353 return; 354 355 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 356 EVT PartEVT = PartVT; 357 if (PartEVT == ValueVT) { 358 assert(NumParts == 1 && "No-op copy with multiple parts!"); 359 Parts[0] = Val; 360 return; 361 } 362 363 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 364 // If the parts cover more bits than the value has, promote the value. 365 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 366 assert(NumParts == 1 && "Do not know what to promote to!"); 367 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 368 } else { 369 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 370 ValueVT.isInteger() && 371 "Unknown mismatch!"); 372 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 373 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 374 if (PartVT == MVT::x86mmx) 375 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 376 } 377 } else if (PartBits == ValueVT.getSizeInBits()) { 378 // Different types of the same size. 379 assert(NumParts == 1 && PartEVT != ValueVT); 380 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 381 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 382 // If the parts cover less bits than value has, truncate the value. 383 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 384 ValueVT.isInteger() && 385 "Unknown mismatch!"); 386 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 387 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 388 if (PartVT == MVT::x86mmx) 389 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 390 } 391 392 // The value may have changed - recompute ValueVT. 393 ValueVT = Val.getValueType(); 394 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 395 "Failed to tile the value with PartVT!"); 396 397 if (NumParts == 1) { 398 if (PartEVT != ValueVT) { 399 LLVMContext &Ctx = *DAG.getContext(); 400 Twine ErrMsg("scalar-to-vector conversion failed"); 401 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) { 402 if (const CallInst *CI = dyn_cast<CallInst>(I)) 403 if (isa<InlineAsm>(CI->getCalledValue())) 404 ErrMsg = ErrMsg + ", possible invalid constraint for vector type"; 405 Ctx.emitError(I, ErrMsg); 406 } else { 407 Ctx.emitError(ErrMsg); 408 } 409 } 410 411 Parts[0] = Val; 412 return; 413 } 414 415 // Expand the value into multiple parts. 416 if (NumParts & (NumParts - 1)) { 417 // The number of parts is not a power of 2. Split off and copy the tail. 418 assert(PartVT.isInteger() && ValueVT.isInteger() && 419 "Do not know what to expand to!"); 420 unsigned RoundParts = 1 << Log2_32(NumParts); 421 unsigned RoundBits = RoundParts * PartBits; 422 unsigned OddParts = NumParts - RoundParts; 423 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 424 DAG.getIntPtrConstant(RoundBits)); 425 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V); 426 427 if (TLI.isBigEndian()) 428 // The odd parts were reversed by getCopyToParts - unreverse them. 429 std::reverse(Parts + RoundParts, Parts + NumParts); 430 431 NumParts = RoundParts; 432 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 433 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 434 } 435 436 // The number of parts is a power of 2. Repeatedly bisect the value using 437 // EXTRACT_ELEMENT. 438 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 439 EVT::getIntegerVT(*DAG.getContext(), 440 ValueVT.getSizeInBits()), 441 Val); 442 443 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 444 for (unsigned i = 0; i < NumParts; i += StepSize) { 445 unsigned ThisBits = StepSize * PartBits / 2; 446 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 447 SDValue &Part0 = Parts[i]; 448 SDValue &Part1 = Parts[i+StepSize/2]; 449 450 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 451 ThisVT, Part0, DAG.getIntPtrConstant(1)); 452 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 453 ThisVT, Part0, DAG.getIntPtrConstant(0)); 454 455 if (ThisBits == PartBits && ThisVT != PartVT) { 456 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 457 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 458 } 459 } 460 } 461 462 if (TLI.isBigEndian()) 463 std::reverse(Parts, Parts + OrigNumParts); 464} 465 466 467/// getCopyToPartsVector - Create a series of nodes that contain the specified 468/// value split into legal parts. 469static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL, 470 SDValue Val, SDValue *Parts, unsigned NumParts, 471 MVT PartVT, const Value *V) { 472 EVT ValueVT = Val.getValueType(); 473 assert(ValueVT.isVector() && "Not a vector"); 474 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 475 476 if (NumParts == 1) { 477 EVT PartEVT = PartVT; 478 if (PartEVT == ValueVT) { 479 // Nothing to do. 480 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 481 // Bitconvert vector->vector case. 482 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 483 } else if (PartVT.isVector() && 484 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() && 485 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 486 EVT ElementVT = PartVT.getVectorElementType(); 487 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 488 // undef elements. 489 SmallVector<SDValue, 16> Ops; 490 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 491 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 492 ElementVT, Val, DAG.getIntPtrConstant(i))); 493 494 for (unsigned i = ValueVT.getVectorNumElements(), 495 e = PartVT.getVectorNumElements(); i != e; ++i) 496 Ops.push_back(DAG.getUNDEF(ElementVT)); 497 498 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 499 500 // FIXME: Use CONCAT for 2x -> 4x. 501 502 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 503 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 504 } else if (PartVT.isVector() && 505 PartEVT.getVectorElementType().bitsGE( 506 ValueVT.getVectorElementType()) && 507 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 508 509 // Promoted vector extract 510 bool Smaller = PartEVT.bitsLE(ValueVT); 511 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 512 DL, PartVT, Val); 513 } else{ 514 // Vector -> scalar conversion. 515 assert(ValueVT.getVectorNumElements() == 1 && 516 "Only trivial vector-to-scalar conversions should get here!"); 517 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 518 PartVT, Val, DAG.getIntPtrConstant(0)); 519 520 bool Smaller = ValueVT.bitsLE(PartVT); 521 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 522 DL, PartVT, Val); 523 } 524 525 Parts[0] = Val; 526 return; 527 } 528 529 // Handle a multi-element vector. 530 EVT IntermediateVT; 531 MVT RegisterVT; 532 unsigned NumIntermediates; 533 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 534 IntermediateVT, 535 NumIntermediates, RegisterVT); 536 unsigned NumElements = ValueVT.getVectorNumElements(); 537 538 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 539 NumParts = NumRegs; // Silence a compiler warning. 540 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 541 542 // Split the vector into intermediate operands. 543 SmallVector<SDValue, 8> Ops(NumIntermediates); 544 for (unsigned i = 0; i != NumIntermediates; ++i) { 545 if (IntermediateVT.isVector()) 546 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 547 IntermediateVT, Val, 548 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 549 else 550 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 551 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 552 } 553 554 // Split the intermediate operands into legal parts. 555 if (NumParts == NumIntermediates) { 556 // If the register was not expanded, promote or copy the value, 557 // as appropriate. 558 for (unsigned i = 0; i != NumParts; ++i) 559 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V); 560 } else if (NumParts > 0) { 561 // If the intermediate type was expanded, split each the value into 562 // legal parts. 563 assert(NumParts % NumIntermediates == 0 && 564 "Must expand into a divisible number of parts!"); 565 unsigned Factor = NumParts / NumIntermediates; 566 for (unsigned i = 0; i != NumIntermediates; ++i) 567 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V); 568 } 569} 570 571namespace { 572 /// RegsForValue - This struct represents the registers (physical or virtual) 573 /// that a particular set of values is assigned, and the type information 574 /// about the value. The most common situation is to represent one value at a 575 /// time, but struct or array values are handled element-wise as multiple 576 /// values. The splitting of aggregates is performed recursively, so that we 577 /// never have aggregate-typed registers. The values at this point do not 578 /// necessarily have legal types, so each value may require one or more 579 /// registers of some legal type. 580 /// 581 struct RegsForValue { 582 /// ValueVTs - The value types of the values, which may not be legal, and 583 /// may need be promoted or synthesized from one or more registers. 584 /// 585 SmallVector<EVT, 4> ValueVTs; 586 587 /// RegVTs - The value types of the registers. This is the same size as 588 /// ValueVTs and it records, for each value, what the type of the assigned 589 /// register or registers are. (Individual values are never synthesized 590 /// from more than one type of register.) 591 /// 592 /// With virtual registers, the contents of RegVTs is redundant with TLI's 593 /// getRegisterType member function, however when with physical registers 594 /// it is necessary to have a separate record of the types. 595 /// 596 SmallVector<MVT, 4> RegVTs; 597 598 /// Regs - This list holds the registers assigned to the values. 599 /// Each legal or promoted value requires one register, and each 600 /// expanded value requires multiple registers. 601 /// 602 SmallVector<unsigned, 4> Regs; 603 604 RegsForValue() {} 605 606 RegsForValue(const SmallVector<unsigned, 4> ®s, 607 MVT regvt, EVT valuevt) 608 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 609 610 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 611 unsigned Reg, Type *Ty) { 612 ComputeValueVTs(tli, Ty, ValueVTs); 613 614 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 615 EVT ValueVT = ValueVTs[Value]; 616 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 617 MVT RegisterVT = tli.getRegisterType(Context, ValueVT); 618 for (unsigned i = 0; i != NumRegs; ++i) 619 Regs.push_back(Reg + i); 620 RegVTs.push_back(RegisterVT); 621 Reg += NumRegs; 622 } 623 } 624 625 /// areValueTypesLegal - Return true if types of all the values are legal. 626 bool areValueTypesLegal(const TargetLowering &TLI) { 627 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 628 MVT RegisterVT = RegVTs[Value]; 629 if (!TLI.isTypeLegal(RegisterVT)) 630 return false; 631 } 632 return true; 633 } 634 635 /// append - Add the specified values to this one. 636 void append(const RegsForValue &RHS) { 637 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 638 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 639 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 640 } 641 642 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 643 /// this value and returns the result as a ValueVTs value. This uses 644 /// Chain/Flag as the input and updates them for the output Chain/Flag. 645 /// If the Flag pointer is NULL, no flag is used. 646 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 647 SDLoc dl, 648 SDValue &Chain, SDValue *Flag, 649 const Value *V = 0) const; 650 651 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 652 /// specified value into the registers specified by this object. This uses 653 /// Chain/Flag as the input and updates them for the output Chain/Flag. 654 /// If the Flag pointer is NULL, no flag is used. 655 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, 656 SDValue &Chain, SDValue *Flag, const Value *V) const; 657 658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 659 /// operand list. This adds the code marker, matching input operand index 660 /// (if applicable), and includes the number of values added into it. 661 void AddInlineAsmOperands(unsigned Kind, 662 bool HasMatching, unsigned MatchingIdx, 663 SelectionDAG &DAG, 664 std::vector<SDValue> &Ops) const; 665 }; 666} 667 668/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 669/// this value and returns the result as a ValueVT value. This uses 670/// Chain/Flag as the input and updates them for the output Chain/Flag. 671/// If the Flag pointer is NULL, no flag is used. 672SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 673 FunctionLoweringInfo &FuncInfo, 674 SDLoc dl, 675 SDValue &Chain, SDValue *Flag, 676 const Value *V) const { 677 // A Value with type {} or [0 x %t] needs no registers. 678 if (ValueVTs.empty()) 679 return SDValue(); 680 681 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 682 683 // Assemble the legal parts into the final values. 684 SmallVector<SDValue, 4> Values(ValueVTs.size()); 685 SmallVector<SDValue, 8> Parts; 686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 687 // Copy the legal parts from the registers. 688 EVT ValueVT = ValueVTs[Value]; 689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 690 MVT RegisterVT = RegVTs[Value]; 691 692 Parts.resize(NumRegs); 693 for (unsigned i = 0; i != NumRegs; ++i) { 694 SDValue P; 695 if (Flag == 0) { 696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 697 } else { 698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 699 *Flag = P.getValue(2); 700 } 701 702 Chain = P.getValue(1); 703 Parts[i] = P; 704 705 // If the source register was virtual and if we know something about it, 706 // add an assert node. 707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 708 !RegisterVT.isInteger() || RegisterVT.isVector()) 709 continue; 710 711 const FunctionLoweringInfo::LiveOutInfo *LOI = 712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 713 if (!LOI) 714 continue; 715 716 unsigned RegSize = RegisterVT.getSizeInBits(); 717 unsigned NumSignBits = LOI->NumSignBits; 718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 719 720 // FIXME: We capture more information than the dag can represent. For 721 // now, just use the tightest assertzext/assertsext possible. 722 bool isSExt = true; 723 EVT FromVT(MVT::Other); 724 if (NumSignBits == RegSize) 725 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 726 else if (NumZeroBits >= RegSize-1) 727 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 728 else if (NumSignBits > RegSize-8) 729 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 730 else if (NumZeroBits >= RegSize-8) 731 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 732 else if (NumSignBits > RegSize-16) 733 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 734 else if (NumZeroBits >= RegSize-16) 735 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 736 else if (NumSignBits > RegSize-32) 737 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 738 else if (NumZeroBits >= RegSize-32) 739 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 740 else 741 continue; 742 743 // Add an assertion node. 744 assert(FromVT != MVT::Other); 745 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 746 RegisterVT, P, DAG.getValueType(FromVT)); 747 } 748 749 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 750 NumRegs, RegisterVT, ValueVT, V); 751 Part += NumRegs; 752 Parts.clear(); 753 } 754 755 return DAG.getNode(ISD::MERGE_VALUES, dl, 756 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 757 &Values[0], ValueVTs.size()); 758} 759 760/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 761/// specified value into the registers specified by this object. This uses 762/// Chain/Flag as the input and updates them for the output Chain/Flag. 763/// If the Flag pointer is NULL, no flag is used. 764void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, 765 SDValue &Chain, SDValue *Flag, 766 const Value *V) const { 767 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 768 769 // Get the list of the values's legal parts. 770 unsigned NumRegs = Regs.size(); 771 SmallVector<SDValue, 8> Parts(NumRegs); 772 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 773 EVT ValueVT = ValueVTs[Value]; 774 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 775 MVT RegisterVT = RegVTs[Value]; 776 ISD::NodeType ExtendKind = 777 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND; 778 779 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 780 &Parts[Part], NumParts, RegisterVT, V, ExtendKind); 781 Part += NumParts; 782 } 783 784 // Copy the parts into the registers. 785 SmallVector<SDValue, 8> Chains(NumRegs); 786 for (unsigned i = 0; i != NumRegs; ++i) { 787 SDValue Part; 788 if (Flag == 0) { 789 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 790 } else { 791 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 792 *Flag = Part.getValue(1); 793 } 794 795 Chains[i] = Part.getValue(0); 796 } 797 798 if (NumRegs == 1 || Flag) 799 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 800 // flagged to it. That is the CopyToReg nodes and the user are considered 801 // a single scheduling unit. If we create a TokenFactor and return it as 802 // chain, then the TokenFactor is both a predecessor (operand) of the 803 // user as well as a successor (the TF operands are flagged to the user). 804 // c1, f1 = CopyToReg 805 // c2, f2 = CopyToReg 806 // c3 = TokenFactor c1, c2 807 // ... 808 // = op c3, ..., f2 809 Chain = Chains[NumRegs-1]; 810 else 811 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 812} 813 814/// AddInlineAsmOperands - Add this value to the specified inlineasm node 815/// operand list. This adds the code marker and includes the number of 816/// values added into it. 817void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 818 unsigned MatchingIdx, 819 SelectionDAG &DAG, 820 std::vector<SDValue> &Ops) const { 821 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 822 823 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 824 if (HasMatching) 825 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 826 else if (!Regs.empty() && 827 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 828 // Put the register class of the virtual registers in the flag word. That 829 // way, later passes can recompute register class constraints for inline 830 // assembly as well as normal instructions. 831 // Don't do this for tied operands that can use the regclass information 832 // from the def. 833 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 834 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 835 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 836 } 837 838 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 839 Ops.push_back(Res); 840 841 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 842 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 843 MVT RegisterVT = RegVTs[Value]; 844 for (unsigned i = 0; i != NumRegs; ++i) { 845 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 846 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 847 } 848 } 849} 850 851void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 852 const TargetLibraryInfo *li) { 853 AA = &aa; 854 GFI = gfi; 855 LibInfo = li; 856 TD = DAG.getTarget().getDataLayout(); 857 Context = DAG.getContext(); 858 LPadToCallSiteMap.clear(); 859} 860 861/// clear - Clear out the current SelectionDAG and the associated 862/// state and prepare this SelectionDAGBuilder object to be used 863/// for a new block. This doesn't clear out information about 864/// additional blocks that are needed to complete switch lowering 865/// or PHI node updating; that information is cleared out as it is 866/// consumed. 867void SelectionDAGBuilder::clear() { 868 NodeMap.clear(); 869 UnusedArgNodeMap.clear(); 870 PendingLoads.clear(); 871 PendingExports.clear(); 872 CurInst = NULL; 873 HasTailCall = false; 874} 875 876/// clearDanglingDebugInfo - Clear the dangling debug information 877/// map. This function is separated from the clear so that debug 878/// information that is dangling in a basic block can be properly 879/// resolved in a different basic block. This allows the 880/// SelectionDAG to resolve dangling debug information attached 881/// to PHI nodes. 882void SelectionDAGBuilder::clearDanglingDebugInfo() { 883 DanglingDebugInfoMap.clear(); 884} 885 886/// getRoot - Return the current virtual root of the Selection DAG, 887/// flushing any PendingLoad items. This must be done before emitting 888/// a store or any other node that may need to be ordered after any 889/// prior load instructions. 890/// 891SDValue SelectionDAGBuilder::getRoot() { 892 if (PendingLoads.empty()) 893 return DAG.getRoot(); 894 895 if (PendingLoads.size() == 1) { 896 SDValue Root = PendingLoads[0]; 897 DAG.setRoot(Root); 898 PendingLoads.clear(); 899 return Root; 900 } 901 902 // Otherwise, we have to make a token factor node. 903 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, 904 &PendingLoads[0], PendingLoads.size()); 905 PendingLoads.clear(); 906 DAG.setRoot(Root); 907 return Root; 908} 909 910/// getControlRoot - Similar to getRoot, but instead of flushing all the 911/// PendingLoad items, flush all the PendingExports items. It is necessary 912/// to do this before emitting a terminator instruction. 913/// 914SDValue SelectionDAGBuilder::getControlRoot() { 915 SDValue Root = DAG.getRoot(); 916 917 if (PendingExports.empty()) 918 return Root; 919 920 // Turn all of the CopyToReg chains into one factored node. 921 if (Root.getOpcode() != ISD::EntryToken) { 922 unsigned i = 0, e = PendingExports.size(); 923 for (; i != e; ++i) { 924 assert(PendingExports[i].getNode()->getNumOperands() > 1); 925 if (PendingExports[i].getNode()->getOperand(0) == Root) 926 break; // Don't add the root if we already indirectly depend on it. 927 } 928 929 if (i == e) 930 PendingExports.push_back(Root); 931 } 932 933 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, 934 &PendingExports[0], 935 PendingExports.size()); 936 PendingExports.clear(); 937 DAG.setRoot(Root); 938 return Root; 939} 940 941void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 942 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 943 DAG.AssignOrdering(Node, SDNodeOrder); 944 945 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 946 AssignOrderingToNode(Node->getOperand(I).getNode()); 947} 948 949void SelectionDAGBuilder::visit(const Instruction &I) { 950 // Set up outgoing PHI node register values before emitting the terminator. 951 if (isa<TerminatorInst>(&I)) 952 HandlePHINodesInSuccessorBlocks(I.getParent()); 953 954 CurInst = &I; 955 956 visit(I.getOpcode(), I); 957 958 if (!isa<TerminatorInst>(&I) && !HasTailCall) 959 CopyToExportRegsIfNeeded(&I); 960 961 CurInst = NULL; 962} 963 964void SelectionDAGBuilder::visitPHI(const PHINode &) { 965 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 966} 967 968void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 969 // Note: this doesn't use InstVisitor, because it has to work with 970 // ConstantExpr's in addition to instructions. 971 switch (Opcode) { 972 default: llvm_unreachable("Unknown instruction type encountered!"); 973 // Build the switch statement using the Instruction.def file. 974#define HANDLE_INST(NUM, OPCODE, CLASS) \ 975 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break; 976#include "llvm/IR/Instruction.def" 977 } 978 979 // Assign the ordering to the freshly created DAG nodes. 980 if (NodeMap.count(&I)) { 981 ++SDNodeOrder; 982 AssignOrderingToNode(getValue(&I).getNode()); 983 } 984} 985 986// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 987// generate the debug data structures now that we've seen its definition. 988void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 989 SDValue Val) { 990 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 991 if (DDI.getDI()) { 992 const DbgValueInst *DI = DDI.getDI(); 993 DebugLoc dl = DDI.getdl(); 994 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 995 MDNode *Variable = DI->getVariable(); 996 uint64_t Offset = DI->getOffset(); 997 SDDbgValue *SDV; 998 if (Val.getNode()) { 999 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 1000 SDV = DAG.getDbgValue(Variable, Val.getNode(), 1001 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 1002 DAG.AddDbgValue(SDV, Val.getNode(), false); 1003 } 1004 } else 1005 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); 1006 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 1007 } 1008} 1009 1010/// getValue - Return an SDValue for the given Value. 1011SDValue SelectionDAGBuilder::getValue(const Value *V) { 1012 // If we already have an SDValue for this value, use it. It's important 1013 // to do this first, so that we don't create a CopyFromReg if we already 1014 // have a regular SDValue. 1015 SDValue &N = NodeMap[V]; 1016 if (N.getNode()) return N; 1017 1018 // If there's a virtual register allocated and initialized for this 1019 // value, use it. 1020 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 1021 if (It != FuncInfo.ValueMap.end()) { 1022 unsigned InReg = It->second; 1023 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 1024 SDValue Chain = DAG.getEntryNode(); 1025 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V); 1026 resolveDanglingDebugInfo(V, N); 1027 return N; 1028 } 1029 1030 // Otherwise create a new SDValue and remember it. 1031 SDValue Val = getValueImpl(V); 1032 NodeMap[V] = Val; 1033 resolveDanglingDebugInfo(V, Val); 1034 return Val; 1035} 1036 1037/// getNonRegisterValue - Return an SDValue for the given Value, but 1038/// don't look in FuncInfo.ValueMap for a virtual register. 1039SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1040 // If we already have an SDValue for this value, use it. 1041 SDValue &N = NodeMap[V]; 1042 if (N.getNode()) return N; 1043 1044 // Otherwise create a new SDValue and remember it. 1045 SDValue Val = getValueImpl(V); 1046 NodeMap[V] = Val; 1047 resolveDanglingDebugInfo(V, Val); 1048 return Val; 1049} 1050 1051/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1052/// Create an SDValue for the given value. 1053SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1054 if (const Constant *C = dyn_cast<Constant>(V)) { 1055 EVT VT = TLI.getValueType(V->getType(), true); 1056 1057 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1058 return DAG.getConstant(*CI, VT); 1059 1060 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1061 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT); 1062 1063 if (isa<ConstantPointerNull>(C)) 1064 return DAG.getConstant(0, TLI.getPointerTy()); 1065 1066 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1067 return DAG.getConstantFP(*CFP, VT); 1068 1069 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1070 return DAG.getUNDEF(VT); 1071 1072 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1073 visit(CE->getOpcode(), *CE); 1074 SDValue N1 = NodeMap[V]; 1075 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1076 return N1; 1077 } 1078 1079 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1080 SmallVector<SDValue, 4> Constants; 1081 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1082 OI != OE; ++OI) { 1083 SDNode *Val = getValue(*OI).getNode(); 1084 // If the operand is an empty aggregate, there are no values. 1085 if (!Val) continue; 1086 // Add each leaf value from the operand to the Constants list 1087 // to form a flattened list of all the values. 1088 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1089 Constants.push_back(SDValue(Val, i)); 1090 } 1091 1092 return DAG.getMergeValues(&Constants[0], Constants.size(), 1093 getCurSDLoc()); 1094 } 1095 1096 if (const ConstantDataSequential *CDS = 1097 dyn_cast<ConstantDataSequential>(C)) { 1098 SmallVector<SDValue, 4> Ops; 1099 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { 1100 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1101 // Add each leaf value from the operand to the Constants list 1102 // to form a flattened list of all the values. 1103 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1104 Ops.push_back(SDValue(Val, i)); 1105 } 1106 1107 if (isa<ArrayType>(CDS->getType())) 1108 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc()); 1109 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), 1110 VT, &Ops[0], Ops.size()); 1111 } 1112 1113 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1114 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1115 "Unknown struct or array constant!"); 1116 1117 SmallVector<EVT, 4> ValueVTs; 1118 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1119 unsigned NumElts = ValueVTs.size(); 1120 if (NumElts == 0) 1121 return SDValue(); // empty struct 1122 SmallVector<SDValue, 4> Constants(NumElts); 1123 for (unsigned i = 0; i != NumElts; ++i) { 1124 EVT EltVT = ValueVTs[i]; 1125 if (isa<UndefValue>(C)) 1126 Constants[i] = DAG.getUNDEF(EltVT); 1127 else if (EltVT.isFloatingPoint()) 1128 Constants[i] = DAG.getConstantFP(0, EltVT); 1129 else 1130 Constants[i] = DAG.getConstant(0, EltVT); 1131 } 1132 1133 return DAG.getMergeValues(&Constants[0], NumElts, 1134 getCurSDLoc()); 1135 } 1136 1137 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1138 return DAG.getBlockAddress(BA, VT); 1139 1140 VectorType *VecTy = cast<VectorType>(V->getType()); 1141 unsigned NumElements = VecTy->getNumElements(); 1142 1143 // Now that we know the number and type of the elements, get that number of 1144 // elements into the Ops array based on what kind of constant it is. 1145 SmallVector<SDValue, 16> Ops; 1146 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1147 for (unsigned i = 0; i != NumElements; ++i) 1148 Ops.push_back(getValue(CV->getOperand(i))); 1149 } else { 1150 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1151 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1152 1153 SDValue Op; 1154 if (EltVT.isFloatingPoint()) 1155 Op = DAG.getConstantFP(0, EltVT); 1156 else 1157 Op = DAG.getConstant(0, EltVT); 1158 Ops.assign(NumElements, Op); 1159 } 1160 1161 // Create a BUILD_VECTOR node. 1162 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), 1163 VT, &Ops[0], Ops.size()); 1164 } 1165 1166 // If this is a static alloca, generate it as the frameindex instead of 1167 // computation. 1168 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1169 DenseMap<const AllocaInst*, int>::iterator SI = 1170 FuncInfo.StaticAllocaMap.find(AI); 1171 if (SI != FuncInfo.StaticAllocaMap.end()) 1172 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1173 } 1174 1175 // If this is an instruction which fast-isel has deferred, select it now. 1176 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1177 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1178 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1179 SDValue Chain = DAG.getEntryNode(); 1180 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V); 1181 } 1182 1183 llvm_unreachable("Can't get register for value!"); 1184} 1185 1186void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1187 SDValue Chain = getControlRoot(); 1188 SmallVector<ISD::OutputArg, 8> Outs; 1189 SmallVector<SDValue, 8> OutVals; 1190 1191 if (!FuncInfo.CanLowerReturn) { 1192 unsigned DemoteReg = FuncInfo.DemoteRegister; 1193 const Function *F = I.getParent()->getParent(); 1194 1195 // Emit a store of the return value through the virtual register. 1196 // Leave Outs empty so that LowerReturn won't try to load return 1197 // registers the usual way. 1198 SmallVector<EVT, 1> PtrValueVTs; 1199 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1200 PtrValueVTs); 1201 1202 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1203 SDValue RetOp = getValue(I.getOperand(0)); 1204 1205 SmallVector<EVT, 4> ValueVTs; 1206 SmallVector<uint64_t, 4> Offsets; 1207 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1208 unsigned NumValues = ValueVTs.size(); 1209 1210 SmallVector<SDValue, 4> Chains(NumValues); 1211 for (unsigned i = 0; i != NumValues; ++i) { 1212 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), 1213 RetPtr.getValueType(), RetPtr, 1214 DAG.getIntPtrConstant(Offsets[i])); 1215 Chains[i] = 1216 DAG.getStore(Chain, getCurSDLoc(), 1217 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1218 // FIXME: better loc info would be nice. 1219 Add, MachinePointerInfo(), false, false, 0); 1220 } 1221 1222 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 1223 MVT::Other, &Chains[0], NumValues); 1224 } else if (I.getNumOperands() != 0) { 1225 SmallVector<EVT, 4> ValueVTs; 1226 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1227 unsigned NumValues = ValueVTs.size(); 1228 if (NumValues) { 1229 SDValue RetOp = getValue(I.getOperand(0)); 1230 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1231 EVT VT = ValueVTs[j]; 1232 1233 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1234 1235 const Function *F = I.getParent()->getParent(); 1236 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex, 1237 Attribute::SExt)) 1238 ExtendKind = ISD::SIGN_EXTEND; 1239 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex, 1240 Attribute::ZExt)) 1241 ExtendKind = ISD::ZERO_EXTEND; 1242 1243 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1244 VT = TLI.getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind); 1245 1246 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1247 MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1248 SmallVector<SDValue, 4> Parts(NumParts); 1249 getCopyToParts(DAG, getCurSDLoc(), 1250 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1251 &Parts[0], NumParts, PartVT, &I, ExtendKind); 1252 1253 // 'inreg' on function refers to return value 1254 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1255 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex, 1256 Attribute::InReg)) 1257 Flags.setInReg(); 1258 1259 // Propagate extension type if any 1260 if (ExtendKind == ISD::SIGN_EXTEND) 1261 Flags.setSExt(); 1262 else if (ExtendKind == ISD::ZERO_EXTEND) 1263 Flags.setZExt(); 1264 1265 for (unsigned i = 0; i < NumParts; ++i) { 1266 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1267 /*isfixed=*/true, 0, 0)); 1268 OutVals.push_back(Parts[i]); 1269 } 1270 } 1271 } 1272 } 1273 1274 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1275 CallingConv::ID CallConv = 1276 DAG.getMachineFunction().getFunction()->getCallingConv(); 1277 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1278 Outs, OutVals, getCurSDLoc(), DAG); 1279 1280 // Verify that the target's LowerReturn behaved as expected. 1281 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1282 "LowerReturn didn't return a valid chain!"); 1283 1284 // Update the DAG with the new chain value resulting from return lowering. 1285 DAG.setRoot(Chain); 1286} 1287 1288/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1289/// created for it, emit nodes to copy the value into the virtual 1290/// registers. 1291void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1292 // Skip empty types 1293 if (V->getType()->isEmptyTy()) 1294 return; 1295 1296 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1297 if (VMI != FuncInfo.ValueMap.end()) { 1298 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1299 CopyValueToVirtualRegister(V, VMI->second); 1300 } 1301} 1302 1303/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1304/// the current basic block, add it to ValueMap now so that we'll get a 1305/// CopyTo/FromReg. 1306void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1307 // No need to export constants. 1308 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1309 1310 // Already exported? 1311 if (FuncInfo.isExportedInst(V)) return; 1312 1313 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1314 CopyValueToVirtualRegister(V, Reg); 1315} 1316 1317bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1318 const BasicBlock *FromBB) { 1319 // The operands of the setcc have to be in this block. We don't know 1320 // how to export them from some other block. 1321 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1322 // Can export from current BB. 1323 if (VI->getParent() == FromBB) 1324 return true; 1325 1326 // Is already exported, noop. 1327 return FuncInfo.isExportedInst(V); 1328 } 1329 1330 // If this is an argument, we can export it if the BB is the entry block or 1331 // if it is already exported. 1332 if (isa<Argument>(V)) { 1333 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1334 return true; 1335 1336 // Otherwise, can only export this if it is already exported. 1337 return FuncInfo.isExportedInst(V); 1338 } 1339 1340 // Otherwise, constants can always be exported. 1341 return true; 1342} 1343 1344/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1345uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1346 const MachineBasicBlock *Dst) const { 1347 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1348 if (!BPI) 1349 return 0; 1350 const BasicBlock *SrcBB = Src->getBasicBlock(); 1351 const BasicBlock *DstBB = Dst->getBasicBlock(); 1352 return BPI->getEdgeWeight(SrcBB, DstBB); 1353} 1354 1355void SelectionDAGBuilder:: 1356addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1357 uint32_t Weight /* = 0 */) { 1358 if (!Weight) 1359 Weight = getEdgeWeight(Src, Dst); 1360 Src->addSuccessor(Dst, Weight); 1361} 1362 1363 1364static bool InBlock(const Value *V, const BasicBlock *BB) { 1365 if (const Instruction *I = dyn_cast<Instruction>(V)) 1366 return I->getParent() == BB; 1367 return true; 1368} 1369 1370/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1371/// This function emits a branch and is used at the leaves of an OR or an 1372/// AND operator tree. 1373/// 1374void 1375SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1376 MachineBasicBlock *TBB, 1377 MachineBasicBlock *FBB, 1378 MachineBasicBlock *CurBB, 1379 MachineBasicBlock *SwitchBB) { 1380 const BasicBlock *BB = CurBB->getBasicBlock(); 1381 1382 // If the leaf of the tree is a comparison, merge the condition into 1383 // the caseblock. 1384 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1385 // The operands of the cmp have to be in this block. We don't know 1386 // how to export them from some other block. If this is the first block 1387 // of the sequence, no exporting is needed. 1388 if (CurBB == SwitchBB || 1389 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1390 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1391 ISD::CondCode Condition; 1392 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1393 Condition = getICmpCondCode(IC->getPredicate()); 1394 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1395 Condition = getFCmpCondCode(FC->getPredicate()); 1396 if (TM.Options.NoNaNsFPMath) 1397 Condition = getFCmpCodeWithoutNaN(Condition); 1398 } else { 1399 Condition = ISD::SETEQ; // silence warning. 1400 llvm_unreachable("Unknown compare instruction"); 1401 } 1402 1403 CaseBlock CB(Condition, BOp->getOperand(0), 1404 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1405 SwitchCases.push_back(CB); 1406 return; 1407 } 1408 } 1409 1410 // Create a CaseBlock record representing this branch. 1411 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1412 NULL, TBB, FBB, CurBB); 1413 SwitchCases.push_back(CB); 1414} 1415 1416/// FindMergedConditions - If Cond is an expression like 1417void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1418 MachineBasicBlock *TBB, 1419 MachineBasicBlock *FBB, 1420 MachineBasicBlock *CurBB, 1421 MachineBasicBlock *SwitchBB, 1422 unsigned Opc) { 1423 // If this node is not part of the or/and tree, emit it as a branch. 1424 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1425 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1426 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1427 BOp->getParent() != CurBB->getBasicBlock() || 1428 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1429 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1430 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1431 return; 1432 } 1433 1434 // Create TmpBB after CurBB. 1435 MachineFunction::iterator BBI = CurBB; 1436 MachineFunction &MF = DAG.getMachineFunction(); 1437 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1438 CurBB->getParent()->insert(++BBI, TmpBB); 1439 1440 if (Opc == Instruction::Or) { 1441 // Codegen X | Y as: 1442 // jmp_if_X TBB 1443 // jmp TmpBB 1444 // TmpBB: 1445 // jmp_if_Y TBB 1446 // jmp FBB 1447 // 1448 1449 // Emit the LHS condition. 1450 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1451 1452 // Emit the RHS condition into TmpBB. 1453 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1454 } else { 1455 assert(Opc == Instruction::And && "Unknown merge op!"); 1456 // Codegen X & Y as: 1457 // jmp_if_X TmpBB 1458 // jmp FBB 1459 // TmpBB: 1460 // jmp_if_Y TBB 1461 // jmp FBB 1462 // 1463 // This requires creation of TmpBB after CurBB. 1464 1465 // Emit the LHS condition. 1466 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1467 1468 // Emit the RHS condition into TmpBB. 1469 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1470 } 1471} 1472 1473/// If the set of cases should be emitted as a series of branches, return true. 1474/// If we should emit this as a bunch of and/or'd together conditions, return 1475/// false. 1476bool 1477SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1478 if (Cases.size() != 2) return true; 1479 1480 // If this is two comparisons of the same values or'd or and'd together, they 1481 // will get folded into a single comparison, so don't emit two blocks. 1482 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1483 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1484 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1485 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1486 return false; 1487 } 1488 1489 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1490 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1491 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1492 Cases[0].CC == Cases[1].CC && 1493 isa<Constant>(Cases[0].CmpRHS) && 1494 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1495 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1496 return false; 1497 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1498 return false; 1499 } 1500 1501 return true; 1502} 1503 1504void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1505 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1506 1507 // Update machine-CFG edges. 1508 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1509 1510 // Figure out which block is immediately after the current one. 1511 MachineBasicBlock *NextBlock = 0; 1512 MachineFunction::iterator BBI = BrMBB; 1513 if (++BBI != FuncInfo.MF->end()) 1514 NextBlock = BBI; 1515 1516 if (I.isUnconditional()) { 1517 // Update machine-CFG edges. 1518 BrMBB->addSuccessor(Succ0MBB); 1519 1520 // If this is not a fall-through branch, emit the branch. 1521 if (Succ0MBB != NextBlock) 1522 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), 1523 MVT::Other, getControlRoot(), 1524 DAG.getBasicBlock(Succ0MBB))); 1525 1526 return; 1527 } 1528 1529 // If this condition is one of the special cases we handle, do special stuff 1530 // now. 1531 const Value *CondVal = I.getCondition(); 1532 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1533 1534 // If this is a series of conditions that are or'd or and'd together, emit 1535 // this as a sequence of branches instead of setcc's with and/or operations. 1536 // As long as jumps are not expensive, this should improve performance. 1537 // For example, instead of something like: 1538 // cmp A, B 1539 // C = seteq 1540 // cmp D, E 1541 // F = setle 1542 // or C, F 1543 // jnz foo 1544 // Emit: 1545 // cmp A, B 1546 // je foo 1547 // cmp D, E 1548 // jle foo 1549 // 1550 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1551 if (!TLI.isJumpExpensive() && 1552 BOp->hasOneUse() && 1553 (BOp->getOpcode() == Instruction::And || 1554 BOp->getOpcode() == Instruction::Or)) { 1555 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1556 BOp->getOpcode()); 1557 // If the compares in later blocks need to use values not currently 1558 // exported from this block, export them now. This block should always 1559 // be the first entry. 1560 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1561 1562 // Allow some cases to be rejected. 1563 if (ShouldEmitAsBranches(SwitchCases)) { 1564 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1565 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1566 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1567 } 1568 1569 // Emit the branch for this block. 1570 visitSwitchCase(SwitchCases[0], BrMBB); 1571 SwitchCases.erase(SwitchCases.begin()); 1572 return; 1573 } 1574 1575 // Okay, we decided not to do this, remove any inserted MBB's and clear 1576 // SwitchCases. 1577 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1578 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1579 1580 SwitchCases.clear(); 1581 } 1582 } 1583 1584 // Create a CaseBlock record representing this branch. 1585 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1586 NULL, Succ0MBB, Succ1MBB, BrMBB); 1587 1588 // Use visitSwitchCase to actually insert the fast branch sequence for this 1589 // cond branch. 1590 visitSwitchCase(CB, BrMBB); 1591} 1592 1593/// visitSwitchCase - Emits the necessary code to represent a single node in 1594/// the binary search tree resulting from lowering a switch instruction. 1595void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1596 MachineBasicBlock *SwitchBB) { 1597 SDValue Cond; 1598 SDValue CondLHS = getValue(CB.CmpLHS); 1599 SDLoc dl = getCurSDLoc(); 1600 1601 // Build the setcc now. 1602 if (CB.CmpMHS == NULL) { 1603 // Fold "(X == true)" to X and "(X == false)" to !X to 1604 // handle common cases produced by branch lowering. 1605 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1606 CB.CC == ISD::SETEQ) 1607 Cond = CondLHS; 1608 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1609 CB.CC == ISD::SETEQ) { 1610 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1611 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1612 } else 1613 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1614 } else { 1615 assert(CB.CC == ISD::SETCC_INVALID && 1616 "Condition is undefined for to-the-range belonging check."); 1617 1618 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1619 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1620 1621 SDValue CmpOp = getValue(CB.CmpMHS); 1622 EVT VT = CmpOp.getValueType(); 1623 1624 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) { 1625 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1626 ISD::SETULE); 1627 } else { 1628 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1629 VT, CmpOp, DAG.getConstant(Low, VT)); 1630 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1631 DAG.getConstant(High-Low, VT), ISD::SETULE); 1632 } 1633 } 1634 1635 // Update successor info 1636 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1637 // TrueBB and FalseBB are always different unless the incoming IR is 1638 // degenerate. This only happens when running llc on weird IR. 1639 if (CB.TrueBB != CB.FalseBB) 1640 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1641 1642 // Set NextBlock to be the MBB immediately after the current one, if any. 1643 // This is used to avoid emitting unnecessary branches to the next block. 1644 MachineBasicBlock *NextBlock = 0; 1645 MachineFunction::iterator BBI = SwitchBB; 1646 if (++BBI != FuncInfo.MF->end()) 1647 NextBlock = BBI; 1648 1649 // If the lhs block is the next block, invert the condition so that we can 1650 // fall through to the lhs instead of the rhs block. 1651 if (CB.TrueBB == NextBlock) { 1652 std::swap(CB.TrueBB, CB.FalseBB); 1653 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1654 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1655 } 1656 1657 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1658 MVT::Other, getControlRoot(), Cond, 1659 DAG.getBasicBlock(CB.TrueBB)); 1660 1661 // Insert the false branch. Do this even if it's a fall through branch, 1662 // this makes it easier to do DAG optimizations which require inverting 1663 // the branch condition. 1664 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1665 DAG.getBasicBlock(CB.FalseBB)); 1666 1667 DAG.setRoot(BrCond); 1668} 1669 1670/// visitJumpTable - Emit JumpTable node in the current MBB 1671void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1672 // Emit the code for the jump table 1673 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1674 EVT PTy = TLI.getPointerTy(); 1675 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(), 1676 JT.Reg, PTy); 1677 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1678 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(), 1679 MVT::Other, Index.getValue(1), 1680 Table, Index); 1681 DAG.setRoot(BrJumpTable); 1682} 1683 1684/// visitJumpTableHeader - This function emits necessary code to produce index 1685/// in the JumpTable from switch case. 1686void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1687 JumpTableHeader &JTH, 1688 MachineBasicBlock *SwitchBB) { 1689 // Subtract the lowest switch case value from the value being switched on and 1690 // conditional branch to default mbb if the result is greater than the 1691 // difference between smallest and largest cases. 1692 SDValue SwitchOp = getValue(JTH.SValue); 1693 EVT VT = SwitchOp.getValueType(); 1694 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp, 1695 DAG.getConstant(JTH.First, VT)); 1696 1697 // The SDNode we just created, which holds the value being switched on minus 1698 // the smallest case value, needs to be copied to a virtual register so it 1699 // can be used as an index into the jump table in a subsequent basic block. 1700 // This value may be smaller or larger than the target's pointer type, and 1701 // therefore require extension or truncating. 1702 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy()); 1703 1704 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1705 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(), 1706 JumpTableReg, SwitchOp); 1707 JT.Reg = JumpTableReg; 1708 1709 // Emit the range check for the jump table, and branch to the default block 1710 // for the switch statement if the value being switched on exceeds the largest 1711 // case in the switch. 1712 SDValue CMP = DAG.getSetCC(getCurSDLoc(), 1713 TLI.getSetCCResultType(*DAG.getContext(), 1714 Sub.getValueType()), 1715 Sub, 1716 DAG.getConstant(JTH.Last - JTH.First,VT), 1717 ISD::SETUGT); 1718 1719 // Set NextBlock to be the MBB immediately after the current one, if any. 1720 // This is used to avoid emitting unnecessary branches to the next block. 1721 MachineBasicBlock *NextBlock = 0; 1722 MachineFunction::iterator BBI = SwitchBB; 1723 1724 if (++BBI != FuncInfo.MF->end()) 1725 NextBlock = BBI; 1726 1727 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(), 1728 MVT::Other, CopyTo, CMP, 1729 DAG.getBasicBlock(JT.Default)); 1730 1731 if (JT.MBB != NextBlock) 1732 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond, 1733 DAG.getBasicBlock(JT.MBB)); 1734 1735 DAG.setRoot(BrCond); 1736} 1737 1738/// visitBitTestHeader - This function emits necessary code to produce value 1739/// suitable for "bit tests" 1740void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1741 MachineBasicBlock *SwitchBB) { 1742 // Subtract the minimum value 1743 SDValue SwitchOp = getValue(B.SValue); 1744 EVT VT = SwitchOp.getValueType(); 1745 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp, 1746 DAG.getConstant(B.First, VT)); 1747 1748 // Check range 1749 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(), 1750 TLI.getSetCCResultType(*DAG.getContext(), 1751 Sub.getValueType()), 1752 Sub, DAG.getConstant(B.Range, VT), 1753 ISD::SETUGT); 1754 1755 // Determine the type of the test operands. 1756 bool UsePtrType = false; 1757 if (!TLI.isTypeLegal(VT)) 1758 UsePtrType = true; 1759 else { 1760 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1761 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1762 // Switch table case range are encoded into series of masks. 1763 // Just use pointer type, it's guaranteed to fit. 1764 UsePtrType = true; 1765 break; 1766 } 1767 } 1768 if (UsePtrType) { 1769 VT = TLI.getPointerTy(); 1770 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT); 1771 } 1772 1773 B.RegVT = VT.getSimpleVT(); 1774 B.Reg = FuncInfo.CreateReg(B.RegVT); 1775 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(), 1776 B.Reg, Sub); 1777 1778 // Set NextBlock to be the MBB immediately after the current one, if any. 1779 // This is used to avoid emitting unnecessary branches to the next block. 1780 MachineBasicBlock *NextBlock = 0; 1781 MachineFunction::iterator BBI = SwitchBB; 1782 if (++BBI != FuncInfo.MF->end()) 1783 NextBlock = BBI; 1784 1785 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1786 1787 addSuccessorWithWeight(SwitchBB, B.Default); 1788 addSuccessorWithWeight(SwitchBB, MBB); 1789 1790 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(), 1791 MVT::Other, CopyTo, RangeCmp, 1792 DAG.getBasicBlock(B.Default)); 1793 1794 if (MBB != NextBlock) 1795 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo, 1796 DAG.getBasicBlock(MBB)); 1797 1798 DAG.setRoot(BrRange); 1799} 1800 1801/// visitBitTestCase - this function produces one "bit test" 1802void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1803 MachineBasicBlock* NextMBB, 1804 uint32_t BranchWeightToNext, 1805 unsigned Reg, 1806 BitTestCase &B, 1807 MachineBasicBlock *SwitchBB) { 1808 MVT VT = BB.RegVT; 1809 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(), 1810 Reg, VT); 1811 SDValue Cmp; 1812 unsigned PopCount = CountPopulation_64(B.Mask); 1813 if (PopCount == 1) { 1814 // Testing for a single bit; just compare the shift count with what it 1815 // would need to be to shift a 1 bit in that position. 1816 Cmp = DAG.getSetCC(getCurSDLoc(), 1817 TLI.getSetCCResultType(*DAG.getContext(), VT), 1818 ShiftOp, 1819 DAG.getConstant(countTrailingZeros(B.Mask), VT), 1820 ISD::SETEQ); 1821 } else if (PopCount == BB.Range) { 1822 // There is only one zero bit in the range, test for it directly. 1823 Cmp = DAG.getSetCC(getCurSDLoc(), 1824 TLI.getSetCCResultType(*DAG.getContext(), VT), 1825 ShiftOp, 1826 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1827 ISD::SETNE); 1828 } else { 1829 // Make desired shift 1830 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT, 1831 DAG.getConstant(1, VT), ShiftOp); 1832 1833 // Emit bit tests and jumps 1834 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(), 1835 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1836 Cmp = DAG.getSetCC(getCurSDLoc(), 1837 TLI.getSetCCResultType(*DAG.getContext(), VT), 1838 AndOp, DAG.getConstant(0, VT), 1839 ISD::SETNE); 1840 } 1841 1842 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight. 1843 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight); 1844 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext. 1845 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext); 1846 1847 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(), 1848 MVT::Other, getControlRoot(), 1849 Cmp, DAG.getBasicBlock(B.TargetBB)); 1850 1851 // Set NextBlock to be the MBB immediately after the current one, if any. 1852 // This is used to avoid emitting unnecessary branches to the next block. 1853 MachineBasicBlock *NextBlock = 0; 1854 MachineFunction::iterator BBI = SwitchBB; 1855 if (++BBI != FuncInfo.MF->end()) 1856 NextBlock = BBI; 1857 1858 if (NextMBB != NextBlock) 1859 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd, 1860 DAG.getBasicBlock(NextMBB)); 1861 1862 DAG.setRoot(BrAnd); 1863} 1864 1865void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1866 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1867 1868 // Retrieve successors. 1869 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1870 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1871 1872 const Value *Callee(I.getCalledValue()); 1873 const Function *Fn = dyn_cast<Function>(Callee); 1874 if (isa<InlineAsm>(Callee)) 1875 visitInlineAsm(&I); 1876 else if (Fn && Fn->isIntrinsic()) { 1877 assert(Fn->getIntrinsicID() == Intrinsic::donothing); 1878 // Ignore invokes to @llvm.donothing: jump directly to the next BB. 1879 } else 1880 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1881 1882 // If the value of the invoke is used outside of its defining block, make it 1883 // available as a virtual register. 1884 CopyToExportRegsIfNeeded(&I); 1885 1886 // Update successor info 1887 addSuccessorWithWeight(InvokeMBB, Return); 1888 addSuccessorWithWeight(InvokeMBB, LandingPad); 1889 1890 // Drop into normal successor. 1891 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), 1892 MVT::Other, getControlRoot(), 1893 DAG.getBasicBlock(Return))); 1894} 1895 1896void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1897 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1898} 1899 1900void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1901 assert(FuncInfo.MBB->isLandingPad() && 1902 "Call to landingpad not in landing pad!"); 1903 1904 MachineBasicBlock *MBB = FuncInfo.MBB; 1905 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1906 AddLandingPadInfo(LP, MMI, MBB); 1907 1908 // If there aren't registers to copy the values into (e.g., during SjLj 1909 // exceptions), then don't bother to create these DAG nodes. 1910 if (TLI.getExceptionPointerRegister() == 0 && 1911 TLI.getExceptionSelectorRegister() == 0) 1912 return; 1913 1914 SmallVector<EVT, 2> ValueVTs; 1915 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1916 1917 // Insert the EXCEPTIONADDR instruction. 1918 assert(FuncInfo.MBB->isLandingPad() && 1919 "Call to eh.exception not in landing pad!"); 1920 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1921 SDValue Ops[2]; 1922 Ops[0] = DAG.getRoot(); 1923 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurSDLoc(), VTs, Ops, 1); 1924 SDValue Chain = Op1.getValue(1); 1925 1926 // Insert the EHSELECTION instruction. 1927 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1928 Ops[0] = Op1; 1929 Ops[1] = Chain; 1930 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurSDLoc(), VTs, Ops, 2); 1931 Chain = Op2.getValue(1); 1932 Op2 = DAG.getSExtOrTrunc(Op2, getCurSDLoc(), MVT::i32); 1933 1934 Ops[0] = Op1; 1935 Ops[1] = Op2; 1936 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 1937 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1938 &Ops[0], 2); 1939 1940 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1941 setValue(&LP, RetPair.first); 1942 DAG.setRoot(RetPair.second); 1943} 1944 1945/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1946/// small case ranges). 1947bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1948 CaseRecVector& WorkList, 1949 const Value* SV, 1950 MachineBasicBlock *Default, 1951 MachineBasicBlock *SwitchBB) { 1952 // Size is the number of Cases represented by this range. 1953 size_t Size = CR.Range.second - CR.Range.first; 1954 if (Size > 3) 1955 return false; 1956 1957 // Get the MachineFunction which holds the current MBB. This is used when 1958 // inserting any additional MBBs necessary to represent the switch. 1959 MachineFunction *CurMF = FuncInfo.MF; 1960 1961 // Figure out which block is immediately after the current one. 1962 MachineBasicBlock *NextBlock = 0; 1963 MachineFunction::iterator BBI = CR.CaseBB; 1964 1965 if (++BBI != FuncInfo.MF->end()) 1966 NextBlock = BBI; 1967 1968 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1969 // If any two of the cases has the same destination, and if one value 1970 // is the same as the other, but has one bit unset that the other has set, 1971 // use bit manipulation to do two compares at once. For example: 1972 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1973 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1974 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1975 if (Size == 2 && CR.CaseBB == SwitchBB) { 1976 Case &Small = *CR.Range.first; 1977 Case &Big = *(CR.Range.second-1); 1978 1979 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1980 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1981 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1982 1983 // Check that there is only one bit different. 1984 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1985 (SmallValue | BigValue) == BigValue) { 1986 // Isolate the common bit. 1987 APInt CommonBit = BigValue & ~SmallValue; 1988 assert((SmallValue | CommonBit) == BigValue && 1989 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1990 1991 SDValue CondLHS = getValue(SV); 1992 EVT VT = CondLHS.getValueType(); 1993 SDLoc DL = getCurSDLoc(); 1994 1995 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1996 DAG.getConstant(CommonBit, VT)); 1997 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1998 Or, DAG.getConstant(BigValue, VT), 1999 ISD::SETEQ); 2000 2001 // Update successor info. 2002 // Both Small and Big will jump to Small.BB, so we sum up the weights. 2003 addSuccessorWithWeight(SwitchBB, Small.BB, 2004 Small.ExtraWeight + Big.ExtraWeight); 2005 addSuccessorWithWeight(SwitchBB, Default, 2006 // The default destination is the first successor in IR. 2007 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0); 2008 2009 // Insert the true branch. 2010 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 2011 getControlRoot(), Cond, 2012 DAG.getBasicBlock(Small.BB)); 2013 2014 // Insert the false branch. 2015 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 2016 DAG.getBasicBlock(Default)); 2017 2018 DAG.setRoot(BrCond); 2019 return true; 2020 } 2021 } 2022 } 2023 2024 // Order cases by weight so the most likely case will be checked first. 2025 uint32_t UnhandledWeights = 0; 2026 if (BPI) { 2027 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) { 2028 uint32_t IWeight = I->ExtraWeight; 2029 UnhandledWeights += IWeight; 2030 for (CaseItr J = CR.Range.first; J < I; ++J) { 2031 uint32_t JWeight = J->ExtraWeight; 2032 if (IWeight > JWeight) 2033 std::swap(*I, *J); 2034 } 2035 } 2036 } 2037 // Rearrange the case blocks so that the last one falls through if possible. 2038 Case &BackCase = *(CR.Range.second-1); 2039 if (Size > 1 && 2040 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 2041 // The last case block won't fall through into 'NextBlock' if we emit the 2042 // branches in this order. See if rearranging a case value would help. 2043 // We start at the bottom as it's the case with the least weight. 2044 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){ 2045 if (I->BB == NextBlock) { 2046 std::swap(*I, BackCase); 2047 break; 2048 } 2049 } 2050 } 2051 2052 // Create a CaseBlock record representing a conditional branch to 2053 // the Case's target mbb if the value being switched on SV is equal 2054 // to C. 2055 MachineBasicBlock *CurBlock = CR.CaseBB; 2056 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2057 MachineBasicBlock *FallThrough; 2058 if (I != E-1) { 2059 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 2060 CurMF->insert(BBI, FallThrough); 2061 2062 // Put SV in a virtual register to make it available from the new blocks. 2063 ExportFromCurrentBlock(SV); 2064 } else { 2065 // If the last case doesn't match, go to the default block. 2066 FallThrough = Default; 2067 } 2068 2069 const Value *RHS, *LHS, *MHS; 2070 ISD::CondCode CC; 2071 if (I->High == I->Low) { 2072 // This is just small small case range :) containing exactly 1 case 2073 CC = ISD::SETEQ; 2074 LHS = SV; RHS = I->High; MHS = NULL; 2075 } else { 2076 CC = ISD::SETCC_INVALID; 2077 LHS = I->Low; MHS = SV; RHS = I->High; 2078 } 2079 2080 // The false weight should be sum of all un-handled cases. 2081 UnhandledWeights -= I->ExtraWeight; 2082 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 2083 /* me */ CurBlock, 2084 /* trueweight */ I->ExtraWeight, 2085 /* falseweight */ UnhandledWeights); 2086 2087 // If emitting the first comparison, just call visitSwitchCase to emit the 2088 // code into the current block. Otherwise, push the CaseBlock onto the 2089 // vector to be later processed by SDISel, and insert the node's MBB 2090 // before the next MBB. 2091 if (CurBlock == SwitchBB) 2092 visitSwitchCase(CB, SwitchBB); 2093 else 2094 SwitchCases.push_back(CB); 2095 2096 CurBlock = FallThrough; 2097 } 2098 2099 return true; 2100} 2101 2102static inline bool areJTsAllowed(const TargetLowering &TLI) { 2103 return TLI.supportJumpTables() && 2104 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2105 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2106} 2107 2108static APInt ComputeRange(const APInt &First, const APInt &Last) { 2109 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2110 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth); 2111 return (LastExt - FirstExt + 1ULL); 2112} 2113 2114/// handleJTSwitchCase - Emit jumptable for current switch case range 2115bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2116 CaseRecVector &WorkList, 2117 const Value *SV, 2118 MachineBasicBlock *Default, 2119 MachineBasicBlock *SwitchBB) { 2120 Case& FrontCase = *CR.Range.first; 2121 Case& BackCase = *(CR.Range.second-1); 2122 2123 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2124 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2125 2126 APInt TSize(First.getBitWidth(), 0); 2127 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2128 TSize += I->size(); 2129 2130 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries())) 2131 return false; 2132 2133 APInt Range = ComputeRange(First, Last); 2134 // The density is TSize / Range. Require at least 40%. 2135 // It should not be possible for IntTSize to saturate for sane code, but make 2136 // sure we handle Range saturation correctly. 2137 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2138 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2139 if (IntTSize * 10 < IntRange * 4) 2140 return false; 2141 2142 DEBUG(dbgs() << "Lowering jump table\n" 2143 << "First entry: " << First << ". Last entry: " << Last << '\n' 2144 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2145 2146 // Get the MachineFunction which holds the current MBB. This is used when 2147 // inserting any additional MBBs necessary to represent the switch. 2148 MachineFunction *CurMF = FuncInfo.MF; 2149 2150 // Figure out which block is immediately after the current one. 2151 MachineFunction::iterator BBI = CR.CaseBB; 2152 ++BBI; 2153 2154 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2155 2156 // Create a new basic block to hold the code for loading the address 2157 // of the jump table, and jumping to it. Update successor information; 2158 // we will either branch to the default case for the switch, or the jump 2159 // table. 2160 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2161 CurMF->insert(BBI, JumpTableBB); 2162 2163 addSuccessorWithWeight(CR.CaseBB, Default); 2164 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2165 2166 // Build a vector of destination BBs, corresponding to each target 2167 // of the jump table. If the value of the jump table slot corresponds to 2168 // a case statement, push the case's BB onto the vector, otherwise, push 2169 // the default BB. 2170 std::vector<MachineBasicBlock*> DestBBs; 2171 APInt TEI = First; 2172 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2173 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2174 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2175 2176 if (Low.ule(TEI) && TEI.ule(High)) { 2177 DestBBs.push_back(I->BB); 2178 if (TEI==High) 2179 ++I; 2180 } else { 2181 DestBBs.push_back(Default); 2182 } 2183 } 2184 2185 // Calculate weight for each unique destination in CR. 2186 DenseMap<MachineBasicBlock*, uint32_t> DestWeights; 2187 if (FuncInfo.BPI) 2188 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2189 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr = 2190 DestWeights.find(I->BB); 2191 if (Itr != DestWeights.end()) 2192 Itr->second += I->ExtraWeight; 2193 else 2194 DestWeights[I->BB] = I->ExtraWeight; 2195 } 2196 2197 // Update successor info. Add one edge to each unique successor. 2198 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2199 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2200 E = DestBBs.end(); I != E; ++I) { 2201 if (!SuccsHandled[(*I)->getNumber()]) { 2202 SuccsHandled[(*I)->getNumber()] = true; 2203 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr = 2204 DestWeights.find(*I); 2205 addSuccessorWithWeight(JumpTableBB, *I, 2206 Itr != DestWeights.end() ? Itr->second : 0); 2207 } 2208 } 2209 2210 // Create a jump table index for this jump table. 2211 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2212 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2213 ->createJumpTableIndex(DestBBs); 2214 2215 // Set the jump table information so that we can codegen it as a second 2216 // MachineBasicBlock 2217 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2218 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2219 if (CR.CaseBB == SwitchBB) 2220 visitJumpTableHeader(JT, JTH, SwitchBB); 2221 2222 JTCases.push_back(JumpTableBlock(JTH, JT)); 2223 return true; 2224} 2225 2226/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2227/// 2 subtrees. 2228bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2229 CaseRecVector& WorkList, 2230 const Value* SV, 2231 MachineBasicBlock *Default, 2232 MachineBasicBlock *SwitchBB) { 2233 // Get the MachineFunction which holds the current MBB. This is used when 2234 // inserting any additional MBBs necessary to represent the switch. 2235 MachineFunction *CurMF = FuncInfo.MF; 2236 2237 // Figure out which block is immediately after the current one. 2238 MachineFunction::iterator BBI = CR.CaseBB; 2239 ++BBI; 2240 2241 Case& FrontCase = *CR.Range.first; 2242 Case& BackCase = *(CR.Range.second-1); 2243 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2244 2245 // Size is the number of Cases represented by this range. 2246 unsigned Size = CR.Range.second - CR.Range.first; 2247 2248 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2249 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2250 double FMetric = 0; 2251 CaseItr Pivot = CR.Range.first + Size/2; 2252 2253 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2254 // (heuristically) allow us to emit JumpTable's later. 2255 APInt TSize(First.getBitWidth(), 0); 2256 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2257 I!=E; ++I) 2258 TSize += I->size(); 2259 2260 APInt LSize = FrontCase.size(); 2261 APInt RSize = TSize-LSize; 2262 DEBUG(dbgs() << "Selecting best pivot: \n" 2263 << "First: " << First << ", Last: " << Last <<'\n' 2264 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2265 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2266 J!=E; ++I, ++J) { 2267 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2268 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2269 APInt Range = ComputeRange(LEnd, RBegin); 2270 assert((Range - 2ULL).isNonNegative() && 2271 "Invalid case distance"); 2272 // Use volatile double here to avoid excess precision issues on some hosts, 2273 // e.g. that use 80-bit X87 registers. 2274 volatile double LDensity = 2275 (double)LSize.roundToDouble() / 2276 (LEnd - First + 1ULL).roundToDouble(); 2277 volatile double RDensity = 2278 (double)RSize.roundToDouble() / 2279 (Last - RBegin + 1ULL).roundToDouble(); 2280 double Metric = Range.logBase2()*(LDensity+RDensity); 2281 // Should always split in some non-trivial place 2282 DEBUG(dbgs() <<"=>Step\n" 2283 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2284 << "LDensity: " << LDensity 2285 << ", RDensity: " << RDensity << '\n' 2286 << "Metric: " << Metric << '\n'); 2287 if (FMetric < Metric) { 2288 Pivot = J; 2289 FMetric = Metric; 2290 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2291 } 2292 2293 LSize += J->size(); 2294 RSize -= J->size(); 2295 } 2296 if (areJTsAllowed(TLI)) { 2297 // If our case is dense we *really* should handle it earlier! 2298 assert((FMetric > 0) && "Should handle dense range earlier!"); 2299 } else { 2300 Pivot = CR.Range.first + Size/2; 2301 } 2302 2303 CaseRange LHSR(CR.Range.first, Pivot); 2304 CaseRange RHSR(Pivot, CR.Range.second); 2305 const Constant *C = Pivot->Low; 2306 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2307 2308 // We know that we branch to the LHS if the Value being switched on is 2309 // less than the Pivot value, C. We use this to optimize our binary 2310 // tree a bit, by recognizing that if SV is greater than or equal to the 2311 // LHS's Case Value, and that Case Value is exactly one less than the 2312 // Pivot's Value, then we can branch directly to the LHS's Target, 2313 // rather than creating a leaf node for it. 2314 if ((LHSR.second - LHSR.first) == 1 && 2315 LHSR.first->High == CR.GE && 2316 cast<ConstantInt>(C)->getValue() == 2317 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2318 TrueBB = LHSR.first->BB; 2319 } else { 2320 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2321 CurMF->insert(BBI, TrueBB); 2322 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2323 2324 // Put SV in a virtual register to make it available from the new blocks. 2325 ExportFromCurrentBlock(SV); 2326 } 2327 2328 // Similar to the optimization above, if the Value being switched on is 2329 // known to be less than the Constant CR.LT, and the current Case Value 2330 // is CR.LT - 1, then we can branch directly to the target block for 2331 // the current Case Value, rather than emitting a RHS leaf node for it. 2332 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2333 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2334 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2335 FalseBB = RHSR.first->BB; 2336 } else { 2337 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2338 CurMF->insert(BBI, FalseBB); 2339 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2340 2341 // Put SV in a virtual register to make it available from the new blocks. 2342 ExportFromCurrentBlock(SV); 2343 } 2344 2345 // Create a CaseBlock record representing a conditional branch to 2346 // the LHS node if the value being switched on SV is less than C. 2347 // Otherwise, branch to LHS. 2348 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2349 2350 if (CR.CaseBB == SwitchBB) 2351 visitSwitchCase(CB, SwitchBB); 2352 else 2353 SwitchCases.push_back(CB); 2354 2355 return true; 2356} 2357 2358/// handleBitTestsSwitchCase - if current case range has few destination and 2359/// range span less, than machine word bitwidth, encode case range into series 2360/// of masks and emit bit tests with these masks. 2361bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2362 CaseRecVector& WorkList, 2363 const Value* SV, 2364 MachineBasicBlock* Default, 2365 MachineBasicBlock *SwitchBB){ 2366 EVT PTy = TLI.getPointerTy(); 2367 unsigned IntPtrBits = PTy.getSizeInBits(); 2368 2369 Case& FrontCase = *CR.Range.first; 2370 Case& BackCase = *(CR.Range.second-1); 2371 2372 // Get the MachineFunction which holds the current MBB. This is used when 2373 // inserting any additional MBBs necessary to represent the switch. 2374 MachineFunction *CurMF = FuncInfo.MF; 2375 2376 // If target does not have legal shift left, do not emit bit tests at all. 2377 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2378 return false; 2379 2380 size_t numCmps = 0; 2381 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2382 I!=E; ++I) { 2383 // Single case counts one, case range - two. 2384 numCmps += (I->Low == I->High ? 1 : 2); 2385 } 2386 2387 // Count unique destinations 2388 SmallSet<MachineBasicBlock*, 4> Dests; 2389 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2390 Dests.insert(I->BB); 2391 if (Dests.size() > 3) 2392 // Don't bother the code below, if there are too much unique destinations 2393 return false; 2394 } 2395 DEBUG(dbgs() << "Total number of unique destinations: " 2396 << Dests.size() << '\n' 2397 << "Total number of comparisons: " << numCmps << '\n'); 2398 2399 // Compute span of values. 2400 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2401 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2402 APInt cmpRange = maxValue - minValue; 2403 2404 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2405 << "Low bound: " << minValue << '\n' 2406 << "High bound: " << maxValue << '\n'); 2407 2408 if (cmpRange.uge(IntPtrBits) || 2409 (!(Dests.size() == 1 && numCmps >= 3) && 2410 !(Dests.size() == 2 && numCmps >= 5) && 2411 !(Dests.size() >= 3 && numCmps >= 6))) 2412 return false; 2413 2414 DEBUG(dbgs() << "Emitting bit tests\n"); 2415 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2416 2417 // Optimize the case where all the case values fit in a 2418 // word without having to subtract minValue. In this case, 2419 // we can optimize away the subtraction. 2420 if (maxValue.ult(IntPtrBits)) { 2421 cmpRange = maxValue; 2422 } else { 2423 lowBound = minValue; 2424 } 2425 2426 CaseBitsVector CasesBits; 2427 unsigned i, count = 0; 2428 2429 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2430 MachineBasicBlock* Dest = I->BB; 2431 for (i = 0; i < count; ++i) 2432 if (Dest == CasesBits[i].BB) 2433 break; 2434 2435 if (i == count) { 2436 assert((count < 3) && "Too much destinations to test!"); 2437 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/)); 2438 count++; 2439 } 2440 2441 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2442 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2443 2444 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2445 uint64_t hi = (highValue - lowBound).getZExtValue(); 2446 CasesBits[i].ExtraWeight += I->ExtraWeight; 2447 2448 for (uint64_t j = lo; j <= hi; j++) { 2449 CasesBits[i].Mask |= 1ULL << j; 2450 CasesBits[i].Bits++; 2451 } 2452 2453 } 2454 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2455 2456 BitTestInfo BTC; 2457 2458 // Figure out which block is immediately after the current one. 2459 MachineFunction::iterator BBI = CR.CaseBB; 2460 ++BBI; 2461 2462 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2463 2464 DEBUG(dbgs() << "Cases:\n"); 2465 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2466 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2467 << ", Bits: " << CasesBits[i].Bits 2468 << ", BB: " << CasesBits[i].BB << '\n'); 2469 2470 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2471 CurMF->insert(BBI, CaseBB); 2472 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2473 CaseBB, 2474 CasesBits[i].BB, CasesBits[i].ExtraWeight)); 2475 2476 // Put SV in a virtual register to make it available from the new blocks. 2477 ExportFromCurrentBlock(SV); 2478 } 2479 2480 BitTestBlock BTB(lowBound, cmpRange, SV, 2481 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2482 CR.CaseBB, Default, BTC); 2483 2484 if (CR.CaseBB == SwitchBB) 2485 visitBitTestHeader(BTB, SwitchBB); 2486 2487 BitTestCases.push_back(BTB); 2488 2489 return true; 2490} 2491 2492/// Clusterify - Transform simple list of Cases into list of CaseRange's 2493size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2494 const SwitchInst& SI) { 2495 2496 /// Use a shorter form of declaration, and also 2497 /// show the we want to use CRSBuilder as Clusterifier. 2498 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier; 2499 2500 Clusterifier TheClusterifier; 2501 2502 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2503 // Start with "simple" cases 2504 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end(); 2505 i != e; ++i) { 2506 const BasicBlock *SuccBB = i.getCaseSuccessor(); 2507 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2508 2509 TheClusterifier.add(i.getCaseValueEx(), SMBB, 2510 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0); 2511 } 2512 2513 TheClusterifier.optimize(); 2514 2515 size_t numCmps = 0; 2516 for (Clusterifier::RangeIterator i = TheClusterifier.begin(), 2517 e = TheClusterifier.end(); i != e; ++i, ++numCmps) { 2518 Clusterifier::Cluster &C = *i; 2519 // Update edge weight for the cluster. 2520 unsigned W = C.first.Weight; 2521 2522 // FIXME: Currently work with ConstantInt based numbers. 2523 // Changing it to APInt based is a pretty heavy for this commit. 2524 Cases.push_back(Case(C.first.getLow().toConstantInt(), 2525 C.first.getHigh().toConstantInt(), C.second, W)); 2526 2527 if (C.first.getLow() != C.first.getHigh()) 2528 // A range counts double, since it requires two compares. 2529 ++numCmps; 2530 } 2531 2532 return numCmps; 2533} 2534 2535void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2536 MachineBasicBlock *Last) { 2537 // Update JTCases. 2538 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2539 if (JTCases[i].first.HeaderBB == First) 2540 JTCases[i].first.HeaderBB = Last; 2541 2542 // Update BitTestCases. 2543 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2544 if (BitTestCases[i].Parent == First) 2545 BitTestCases[i].Parent = Last; 2546} 2547 2548void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2549 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2550 2551 // Figure out which block is immediately after the current one. 2552 MachineBasicBlock *NextBlock = 0; 2553 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2554 2555 // If there is only the default destination, branch to it if it is not the 2556 // next basic block. Otherwise, just fall through. 2557 if (!SI.getNumCases()) { 2558 // Update machine-CFG edges. 2559 2560 // If this is not a fall-through branch, emit the branch. 2561 SwitchMBB->addSuccessor(Default); 2562 if (Default != NextBlock) 2563 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), 2564 MVT::Other, getControlRoot(), 2565 DAG.getBasicBlock(Default))); 2566 2567 return; 2568 } 2569 2570 // If there are any non-default case statements, create a vector of Cases 2571 // representing each one, and sort the vector so that we can efficiently 2572 // create a binary search tree from them. 2573 CaseVector Cases; 2574 size_t numCmps = Clusterify(Cases, SI); 2575 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2576 << ". Total compares: " << numCmps << '\n'); 2577 (void)numCmps; 2578 2579 // Get the Value to be switched on and default basic blocks, which will be 2580 // inserted into CaseBlock records, representing basic blocks in the binary 2581 // search tree. 2582 const Value *SV = SI.getCondition(); 2583 2584 // Push the initial CaseRec onto the worklist 2585 CaseRecVector WorkList; 2586 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2587 CaseRange(Cases.begin(),Cases.end()))); 2588 2589 while (!WorkList.empty()) { 2590 // Grab a record representing a case range to process off the worklist 2591 CaseRec CR = WorkList.back(); 2592 WorkList.pop_back(); 2593 2594 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2595 continue; 2596 2597 // If the range has few cases (two or less) emit a series of specific 2598 // tests. 2599 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2600 continue; 2601 2602 // If the switch has more than N blocks, and is at least 40% dense, and the 2603 // target supports indirect branches, then emit a jump table rather than 2604 // lowering the switch to a binary tree of conditional branches. 2605 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries(). 2606 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2607 continue; 2608 2609 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2610 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2611 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2612 } 2613} 2614 2615void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2616 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2617 2618 // Update machine-CFG edges with unique successors. 2619 SmallSet<BasicBlock*, 32> Done; 2620 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) { 2621 BasicBlock *BB = I.getSuccessor(i); 2622 bool Inserted = Done.insert(BB); 2623 if (!Inserted) 2624 continue; 2625 2626 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB]; 2627 addSuccessorWithWeight(IndirectBrMBB, Succ); 2628 } 2629 2630 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(), 2631 MVT::Other, getControlRoot(), 2632 getValue(I.getAddress()))); 2633} 2634 2635void SelectionDAGBuilder::visitFSub(const User &I) { 2636 // -0.0 - X --> fneg 2637 Type *Ty = I.getType(); 2638 if (isa<Constant>(I.getOperand(0)) && 2639 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2640 SDValue Op2 = getValue(I.getOperand(1)); 2641 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(), 2642 Op2.getValueType(), Op2)); 2643 return; 2644 } 2645 2646 visitBinary(I, ISD::FSUB); 2647} 2648 2649void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2650 SDValue Op1 = getValue(I.getOperand(0)); 2651 SDValue Op2 = getValue(I.getOperand(1)); 2652 setValue(&I, DAG.getNode(OpCode, getCurSDLoc(), 2653 Op1.getValueType(), Op1, Op2)); 2654} 2655 2656void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2657 SDValue Op1 = getValue(I.getOperand(0)); 2658 SDValue Op2 = getValue(I.getOperand(1)); 2659 2660 EVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2661 2662 // Coerce the shift amount to the right type if we can. 2663 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2664 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2665 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2666 SDLoc DL = getCurSDLoc(); 2667 2668 // If the operand is smaller than the shift count type, promote it. 2669 if (ShiftSize > Op2Size) 2670 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2671 2672 // If the operand is larger than the shift count type but the shift 2673 // count type has enough bits to represent any shift value, truncate 2674 // it now. This is a common case and it exposes the truncate to 2675 // optimization early. 2676 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2677 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2678 // Otherwise we'll need to temporarily settle for some other convenient 2679 // type. Type legalization will make adjustments once the shiftee is split. 2680 else 2681 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2682 } 2683 2684 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), 2685 Op1.getValueType(), Op1, Op2)); 2686} 2687 2688void SelectionDAGBuilder::visitSDiv(const User &I) { 2689 SDValue Op1 = getValue(I.getOperand(0)); 2690 SDValue Op2 = getValue(I.getOperand(1)); 2691 2692 // Turn exact SDivs into multiplications. 2693 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2694 // exact bit. 2695 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2696 !isa<ConstantSDNode>(Op1) && 2697 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2698 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG)); 2699 else 2700 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), 2701 Op1, Op2)); 2702} 2703 2704void SelectionDAGBuilder::visitICmp(const User &I) { 2705 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2706 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2707 predicate = IC->getPredicate(); 2708 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2709 predicate = ICmpInst::Predicate(IC->getPredicate()); 2710 SDValue Op1 = getValue(I.getOperand(0)); 2711 SDValue Op2 = getValue(I.getOperand(1)); 2712 ISD::CondCode Opcode = getICmpCondCode(predicate); 2713 2714 EVT DestVT = TLI.getValueType(I.getType()); 2715 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); 2716} 2717 2718void SelectionDAGBuilder::visitFCmp(const User &I) { 2719 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2720 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2721 predicate = FC->getPredicate(); 2722 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2723 predicate = FCmpInst::Predicate(FC->getPredicate()); 2724 SDValue Op1 = getValue(I.getOperand(0)); 2725 SDValue Op2 = getValue(I.getOperand(1)); 2726 ISD::CondCode Condition = getFCmpCondCode(predicate); 2727 if (TM.Options.NoNaNsFPMath) 2728 Condition = getFCmpCodeWithoutNaN(Condition); 2729 EVT DestVT = TLI.getValueType(I.getType()); 2730 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); 2731} 2732 2733void SelectionDAGBuilder::visitSelect(const User &I) { 2734 SmallVector<EVT, 4> ValueVTs; 2735 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2736 unsigned NumValues = ValueVTs.size(); 2737 if (NumValues == 0) return; 2738 2739 SmallVector<SDValue, 4> Values(NumValues); 2740 SDValue Cond = getValue(I.getOperand(0)); 2741 SDValue TrueVal = getValue(I.getOperand(1)); 2742 SDValue FalseVal = getValue(I.getOperand(2)); 2743 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2744 ISD::VSELECT : ISD::SELECT; 2745 2746 for (unsigned i = 0; i != NumValues; ++i) 2747 Values[i] = DAG.getNode(OpCode, getCurSDLoc(), 2748 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2749 Cond, 2750 SDValue(TrueVal.getNode(), 2751 TrueVal.getResNo() + i), 2752 SDValue(FalseVal.getNode(), 2753 FalseVal.getResNo() + i)); 2754 2755 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 2756 DAG.getVTList(&ValueVTs[0], NumValues), 2757 &Values[0], NumValues)); 2758} 2759 2760void SelectionDAGBuilder::visitTrunc(const User &I) { 2761 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2762 SDValue N = getValue(I.getOperand(0)); 2763 EVT DestVT = TLI.getValueType(I.getType()); 2764 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); 2765} 2766 2767void SelectionDAGBuilder::visitZExt(const User &I) { 2768 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2769 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2770 SDValue N = getValue(I.getOperand(0)); 2771 EVT DestVT = TLI.getValueType(I.getType()); 2772 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N)); 2773} 2774 2775void SelectionDAGBuilder::visitSExt(const User &I) { 2776 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2777 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2778 SDValue N = getValue(I.getOperand(0)); 2779 EVT DestVT = TLI.getValueType(I.getType()); 2780 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N)); 2781} 2782 2783void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2784 // FPTrunc is never a no-op cast, no need to check 2785 SDValue N = getValue(I.getOperand(0)); 2786 EVT DestVT = TLI.getValueType(I.getType()); 2787 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), 2788 DestVT, N, 2789 DAG.getTargetConstant(0, TLI.getPointerTy()))); 2790} 2791 2792void SelectionDAGBuilder::visitFPExt(const User &I){ 2793 // FPExt is never a no-op cast, no need to check 2794 SDValue N = getValue(I.getOperand(0)); 2795 EVT DestVT = TLI.getValueType(I.getType()); 2796 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N)); 2797} 2798 2799void SelectionDAGBuilder::visitFPToUI(const User &I) { 2800 // FPToUI is never a no-op cast, no need to check 2801 SDValue N = getValue(I.getOperand(0)); 2802 EVT DestVT = TLI.getValueType(I.getType()); 2803 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N)); 2804} 2805 2806void SelectionDAGBuilder::visitFPToSI(const User &I) { 2807 // FPToSI is never a no-op cast, no need to check 2808 SDValue N = getValue(I.getOperand(0)); 2809 EVT DestVT = TLI.getValueType(I.getType()); 2810 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N)); 2811} 2812 2813void SelectionDAGBuilder::visitUIToFP(const User &I) { 2814 // UIToFP is never a no-op cast, no need to check 2815 SDValue N = getValue(I.getOperand(0)); 2816 EVT DestVT = TLI.getValueType(I.getType()); 2817 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N)); 2818} 2819 2820void SelectionDAGBuilder::visitSIToFP(const User &I){ 2821 // SIToFP is never a no-op cast, no need to check 2822 SDValue N = getValue(I.getOperand(0)); 2823 EVT DestVT = TLI.getValueType(I.getType()); 2824 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N)); 2825} 2826 2827void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2828 // What to do depends on the size of the integer and the size of the pointer. 2829 // We can either truncate, zero extend, or no-op, accordingly. 2830 SDValue N = getValue(I.getOperand(0)); 2831 EVT DestVT = TLI.getValueType(I.getType()); 2832 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT)); 2833} 2834 2835void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2836 // What to do depends on the size of the integer and the size of the pointer. 2837 // We can either truncate, zero extend, or no-op, accordingly. 2838 SDValue N = getValue(I.getOperand(0)); 2839 EVT DestVT = TLI.getValueType(I.getType()); 2840 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT)); 2841} 2842 2843void SelectionDAGBuilder::visitBitCast(const User &I) { 2844 SDValue N = getValue(I.getOperand(0)); 2845 EVT DestVT = TLI.getValueType(I.getType()); 2846 2847 // BitCast assures us that source and destination are the same size so this is 2848 // either a BITCAST or a no-op. 2849 if (DestVT != N.getValueType()) 2850 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(), 2851 DestVT, N)); // convert types. 2852 else 2853 setValue(&I, N); // noop cast. 2854} 2855 2856void SelectionDAGBuilder::visitInsertElement(const User &I) { 2857 SDValue InVec = getValue(I.getOperand(0)); 2858 SDValue InVal = getValue(I.getOperand(1)); 2859 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), 2860 TLI.getPointerTy(), 2861 getValue(I.getOperand(2))); 2862 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(), 2863 TLI.getValueType(I.getType()), 2864 InVec, InVal, InIdx)); 2865} 2866 2867void SelectionDAGBuilder::visitExtractElement(const User &I) { 2868 SDValue InVec = getValue(I.getOperand(0)); 2869 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), 2870 TLI.getPointerTy(), 2871 getValue(I.getOperand(1))); 2872 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(), 2873 TLI.getValueType(I.getType()), InVec, InIdx)); 2874} 2875 2876// Utility for visitShuffleVector - Return true if every element in Mask, 2877// beginning from position Pos and ending in Pos+Size, falls within the 2878// specified sequential range [L, L+Pos). or is undef. 2879static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2880 unsigned Pos, unsigned Size, int Low) { 2881 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2882 if (Mask[i] >= 0 && Mask[i] != Low) 2883 return false; 2884 return true; 2885} 2886 2887void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2888 SDValue Src1 = getValue(I.getOperand(0)); 2889 SDValue Src2 = getValue(I.getOperand(1)); 2890 2891 SmallVector<int, 8> Mask; 2892 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); 2893 unsigned MaskNumElts = Mask.size(); 2894 2895 EVT VT = TLI.getValueType(I.getType()); 2896 EVT SrcVT = Src1.getValueType(); 2897 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2898 2899 if (SrcNumElts == MaskNumElts) { 2900 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, 2901 &Mask[0])); 2902 return; 2903 } 2904 2905 // Normalize the shuffle vector since mask and vector length don't match. 2906 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2907 // Mask is longer than the source vectors and is a multiple of the source 2908 // vectors. We can use concatenate vector to make the mask and vectors 2909 // lengths match. 2910 if (SrcNumElts*2 == MaskNumElts) { 2911 // First check for Src1 in low and Src2 in high 2912 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 2913 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 2914 // The shuffle is concatenating two vectors together. 2915 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(), 2916 VT, Src1, Src2)); 2917 return; 2918 } 2919 // Then check for Src2 in low and Src1 in high 2920 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 2921 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 2922 // The shuffle is concatenating two vectors together. 2923 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(), 2924 VT, Src2, Src1)); 2925 return; 2926 } 2927 } 2928 2929 // Pad both vectors with undefs to make them the same length as the mask. 2930 unsigned NumConcat = MaskNumElts / SrcNumElts; 2931 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2932 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2933 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2934 2935 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2936 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2937 MOps1[0] = Src1; 2938 MOps2[0] = Src2; 2939 2940 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2941 getCurSDLoc(), VT, 2942 &MOps1[0], NumConcat); 2943 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2944 getCurSDLoc(), VT, 2945 &MOps2[0], NumConcat); 2946 2947 // Readjust mask for new input vector length. 2948 SmallVector<int, 8> MappedOps; 2949 for (unsigned i = 0; i != MaskNumElts; ++i) { 2950 int Idx = Mask[i]; 2951 if (Idx >= (int)SrcNumElts) 2952 Idx -= SrcNumElts - MaskNumElts; 2953 MappedOps.push_back(Idx); 2954 } 2955 2956 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, 2957 &MappedOps[0])); 2958 return; 2959 } 2960 2961 if (SrcNumElts > MaskNumElts) { 2962 // Analyze the access pattern of the vector to see if we can extract 2963 // two subvectors and do the shuffle. The analysis is done by calculating 2964 // the range of elements the mask access on both vectors. 2965 int MinRange[2] = { static_cast<int>(SrcNumElts), 2966 static_cast<int>(SrcNumElts)}; 2967 int MaxRange[2] = {-1, -1}; 2968 2969 for (unsigned i = 0; i != MaskNumElts; ++i) { 2970 int Idx = Mask[i]; 2971 unsigned Input = 0; 2972 if (Idx < 0) 2973 continue; 2974 2975 if (Idx >= (int)SrcNumElts) { 2976 Input = 1; 2977 Idx -= SrcNumElts; 2978 } 2979 if (Idx > MaxRange[Input]) 2980 MaxRange[Input] = Idx; 2981 if (Idx < MinRange[Input]) 2982 MinRange[Input] = Idx; 2983 } 2984 2985 // Check if the access is smaller than the vector size and can we find 2986 // a reasonable extract index. 2987 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not 2988 // Extract. 2989 int StartIdx[2]; // StartIdx to extract from 2990 for (unsigned Input = 0; Input < 2; ++Input) { 2991 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) { 2992 RangeUse[Input] = 0; // Unused 2993 StartIdx[Input] = 0; 2994 continue; 2995 } 2996 2997 // Find a good start index that is a multiple of the mask length. Then 2998 // see if the rest of the elements are in range. 2999 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 3000 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 3001 StartIdx[Input] + MaskNumElts <= SrcNumElts) 3002 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 3003 } 3004 3005 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 3006 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 3007 return; 3008 } 3009 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) { 3010 // Extract appropriate subvector and generate a vector shuffle 3011 for (unsigned Input = 0; Input < 2; ++Input) { 3012 SDValue &Src = Input == 0 ? Src1 : Src2; 3013 if (RangeUse[Input] == 0) 3014 Src = DAG.getUNDEF(VT); 3015 else 3016 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, 3017 Src, DAG.getIntPtrConstant(StartIdx[Input])); 3018 } 3019 3020 // Calculate new mask. 3021 SmallVector<int, 8> MappedOps; 3022 for (unsigned i = 0; i != MaskNumElts; ++i) { 3023 int Idx = Mask[i]; 3024 if (Idx >= 0) { 3025 if (Idx < (int)SrcNumElts) 3026 Idx -= StartIdx[0]; 3027 else 3028 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; 3029 } 3030 MappedOps.push_back(Idx); 3031 } 3032 3033 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, 3034 &MappedOps[0])); 3035 return; 3036 } 3037 } 3038 3039 // We can't use either concat vectors or extract subvectors so fall back to 3040 // replacing the shuffle with extract and build vector. 3041 // to insert and build vector. 3042 EVT EltVT = VT.getVectorElementType(); 3043 EVT PtrVT = TLI.getPointerTy(); 3044 SmallVector<SDValue,8> Ops; 3045 for (unsigned i = 0; i != MaskNumElts; ++i) { 3046 int Idx = Mask[i]; 3047 SDValue Res; 3048 3049 if (Idx < 0) { 3050 Res = DAG.getUNDEF(EltVT); 3051 } else { 3052 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; 3053 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; 3054 3055 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(), 3056 EltVT, Src, DAG.getConstant(Idx, PtrVT)); 3057 } 3058 3059 Ops.push_back(Res); 3060 } 3061 3062 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), 3063 VT, &Ops[0], Ops.size())); 3064} 3065 3066void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 3067 const Value *Op0 = I.getOperand(0); 3068 const Value *Op1 = I.getOperand(1); 3069 Type *AggTy = I.getType(); 3070 Type *ValTy = Op1->getType(); 3071 bool IntoUndef = isa<UndefValue>(Op0); 3072 bool FromUndef = isa<UndefValue>(Op1); 3073 3074 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3075 3076 SmallVector<EVT, 4> AggValueVTs; 3077 ComputeValueVTs(TLI, AggTy, AggValueVTs); 3078 SmallVector<EVT, 4> ValValueVTs; 3079 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3080 3081 unsigned NumAggValues = AggValueVTs.size(); 3082 unsigned NumValValues = ValValueVTs.size(); 3083 SmallVector<SDValue, 4> Values(NumAggValues); 3084 3085 SDValue Agg = getValue(Op0); 3086 unsigned i = 0; 3087 // Copy the beginning value(s) from the original aggregate. 3088 for (; i != LinearIndex; ++i) 3089 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3090 SDValue(Agg.getNode(), Agg.getResNo() + i); 3091 // Copy values from the inserted value(s). 3092 if (NumValValues) { 3093 SDValue Val = getValue(Op1); 3094 for (; i != LinearIndex + NumValValues; ++i) 3095 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3096 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3097 } 3098 // Copy remaining value(s) from the original aggregate. 3099 for (; i != NumAggValues; ++i) 3100 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3101 SDValue(Agg.getNode(), Agg.getResNo() + i); 3102 3103 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 3104 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3105 &Values[0], NumAggValues)); 3106} 3107 3108void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3109 const Value *Op0 = I.getOperand(0); 3110 Type *AggTy = Op0->getType(); 3111 Type *ValTy = I.getType(); 3112 bool OutOfUndef = isa<UndefValue>(Op0); 3113 3114 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3115 3116 SmallVector<EVT, 4> ValValueVTs; 3117 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3118 3119 unsigned NumValValues = ValValueVTs.size(); 3120 3121 // Ignore a extractvalue that produces an empty object 3122 if (!NumValValues) { 3123 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3124 return; 3125 } 3126 3127 SmallVector<SDValue, 4> Values(NumValValues); 3128 3129 SDValue Agg = getValue(Op0); 3130 // Copy out the selected value(s). 3131 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3132 Values[i - LinearIndex] = 3133 OutOfUndef ? 3134 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3135 SDValue(Agg.getNode(), Agg.getResNo() + i); 3136 3137 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 3138 DAG.getVTList(&ValValueVTs[0], NumValValues), 3139 &Values[0], NumValValues)); 3140} 3141 3142void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3143 SDValue N = getValue(I.getOperand(0)); 3144 // Note that the pointer operand may be a vector of pointers. Take the scalar 3145 // element which holds a pointer. 3146 Type *Ty = I.getOperand(0)->getType()->getScalarType(); 3147 3148 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3149 OI != E; ++OI) { 3150 const Value *Idx = *OI; 3151 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3152 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue(); 3153 if (Field) { 3154 // N = N + Offset 3155 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3156 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, 3157 DAG.getConstant(Offset, N.getValueType())); 3158 } 3159 3160 Ty = StTy->getElementType(Field); 3161 } else { 3162 Ty = cast<SequentialType>(Ty)->getElementType(); 3163 3164 // If this is a constant subscript, handle it quickly. 3165 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3166 if (CI->isZero()) continue; 3167 uint64_t Offs = 3168 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3169 SDValue OffsVal; 3170 EVT PTy = TLI.getPointerTy(); 3171 unsigned PtrBits = PTy.getSizeInBits(); 3172 if (PtrBits < 64) 3173 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), 3174 TLI.getPointerTy(), 3175 DAG.getConstant(Offs, MVT::i64)); 3176 else 3177 OffsVal = DAG.getIntPtrConstant(Offs); 3178 3179 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, 3180 OffsVal); 3181 continue; 3182 } 3183 3184 // N = N + Idx * ElementSize; 3185 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3186 TD->getTypeAllocSize(Ty)); 3187 SDValue IdxN = getValue(Idx); 3188 3189 // If the index is smaller or larger than intptr_t, truncate or extend 3190 // it. 3191 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType()); 3192 3193 // If this is a multiply by a power of two, turn it into a shl 3194 // immediately. This is a very common case. 3195 if (ElementSize != 1) { 3196 if (ElementSize.isPowerOf2()) { 3197 unsigned Amt = ElementSize.logBase2(); 3198 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(), 3199 N.getValueType(), IdxN, 3200 DAG.getConstant(Amt, IdxN.getValueType())); 3201 } else { 3202 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType()); 3203 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(), 3204 N.getValueType(), IdxN, Scale); 3205 } 3206 } 3207 3208 N = DAG.getNode(ISD::ADD, getCurSDLoc(), 3209 N.getValueType(), N, IdxN); 3210 } 3211 } 3212 3213 setValue(&I, N); 3214} 3215 3216void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3217 // If this is a fixed sized alloca in the entry block of the function, 3218 // allocate it statically on the stack. 3219 if (FuncInfo.StaticAllocaMap.count(&I)) 3220 return; // getValue will auto-populate this. 3221 3222 Type *Ty = I.getAllocatedType(); 3223 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty); 3224 unsigned Align = 3225 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty), 3226 I.getAlignment()); 3227 3228 SDValue AllocSize = getValue(I.getArraySize()); 3229 3230 EVT IntPtr = TLI.getPointerTy(); 3231 if (AllocSize.getValueType() != IntPtr) 3232 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr); 3233 3234 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr, 3235 AllocSize, 3236 DAG.getConstant(TySize, IntPtr)); 3237 3238 // Handle alignment. If the requested alignment is less than or equal to 3239 // the stack alignment, ignore it. If the size is greater than or equal to 3240 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3241 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3242 if (Align <= StackAlign) 3243 Align = 0; 3244 3245 // Round the size of the allocation up to the stack alignment size 3246 // by add SA-1 to the size. 3247 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(), 3248 AllocSize.getValueType(), AllocSize, 3249 DAG.getIntPtrConstant(StackAlign-1)); 3250 3251 // Mask out the low bits for alignment purposes. 3252 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(), 3253 AllocSize.getValueType(), AllocSize, 3254 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3255 3256 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3257 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3258 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), 3259 VTs, Ops, 3); 3260 setValue(&I, DSA); 3261 DAG.setRoot(DSA.getValue(1)); 3262 3263 // Inform the Frame Information that we have just allocated a variable-sized 3264 // object. 3265 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3266} 3267 3268void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3269 if (I.isAtomic()) 3270 return visitAtomicLoad(I); 3271 3272 const Value *SV = I.getOperand(0); 3273 SDValue Ptr = getValue(SV); 3274 3275 Type *Ty = I.getType(); 3276 3277 bool isVolatile = I.isVolatile(); 3278 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3279 bool isInvariant = I.getMetadata("invariant.load") != 0; 3280 unsigned Alignment = I.getAlignment(); 3281 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3282 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 3283 3284 SmallVector<EVT, 4> ValueVTs; 3285 SmallVector<uint64_t, 4> Offsets; 3286 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3287 unsigned NumValues = ValueVTs.size(); 3288 if (NumValues == 0) 3289 return; 3290 3291 SDValue Root; 3292 bool ConstantMemory = false; 3293 if (I.isVolatile() || NumValues > MaxParallelChains) 3294 // Serialize volatile loads with other side effects. 3295 Root = getRoot(); 3296 else if (AA->pointsToConstantMemory( 3297 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3298 // Do not serialize (non-volatile) loads of constant memory with anything. 3299 Root = DAG.getEntryNode(); 3300 ConstantMemory = true; 3301 } else { 3302 // Do not serialize non-volatile loads against each other. 3303 Root = DAG.getRoot(); 3304 } 3305 3306 SmallVector<SDValue, 4> Values(NumValues); 3307 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3308 NumValues)); 3309 EVT PtrVT = Ptr.getValueType(); 3310 unsigned ChainI = 0; 3311 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3312 // Serializing loads here may result in excessive register pressure, and 3313 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3314 // could recover a bit by hoisting nodes upward in the chain by recognizing 3315 // they are side-effect free or do not alias. The optimizer should really 3316 // avoid this case by converting large object/array copies to llvm.memcpy 3317 // (MaxParallelChains should always remain as failsafe). 3318 if (ChainI == MaxParallelChains) { 3319 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3320 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 3321 MVT::Other, &Chains[0], ChainI); 3322 Root = Chain; 3323 ChainI = 0; 3324 } 3325 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(), 3326 PtrVT, Ptr, 3327 DAG.getConstant(Offsets[i], PtrVT)); 3328 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root, 3329 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3330 isNonTemporal, isInvariant, Alignment, TBAAInfo, 3331 Ranges); 3332 3333 Values[i] = L; 3334 Chains[ChainI] = L.getValue(1); 3335 } 3336 3337 if (!ConstantMemory) { 3338 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 3339 MVT::Other, &Chains[0], ChainI); 3340 if (isVolatile) 3341 DAG.setRoot(Chain); 3342 else 3343 PendingLoads.push_back(Chain); 3344 } 3345 3346 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 3347 DAG.getVTList(&ValueVTs[0], NumValues), 3348 &Values[0], NumValues)); 3349} 3350 3351void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3352 if (I.isAtomic()) 3353 return visitAtomicStore(I); 3354 3355 const Value *SrcV = I.getOperand(0); 3356 const Value *PtrV = I.getOperand(1); 3357 3358 SmallVector<EVT, 4> ValueVTs; 3359 SmallVector<uint64_t, 4> Offsets; 3360 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3361 unsigned NumValues = ValueVTs.size(); 3362 if (NumValues == 0) 3363 return; 3364 3365 // Get the lowered operands. Note that we do this after 3366 // checking if NumResults is zero, because with zero results 3367 // the operands won't have values in the map. 3368 SDValue Src = getValue(SrcV); 3369 SDValue Ptr = getValue(PtrV); 3370 3371 SDValue Root = getRoot(); 3372 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3373 NumValues)); 3374 EVT PtrVT = Ptr.getValueType(); 3375 bool isVolatile = I.isVolatile(); 3376 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3377 unsigned Alignment = I.getAlignment(); 3378 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3379 3380 unsigned ChainI = 0; 3381 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3382 // See visitLoad comments. 3383 if (ChainI == MaxParallelChains) { 3384 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 3385 MVT::Other, &Chains[0], ChainI); 3386 Root = Chain; 3387 ChainI = 0; 3388 } 3389 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr, 3390 DAG.getConstant(Offsets[i], PtrVT)); 3391 SDValue St = DAG.getStore(Root, getCurSDLoc(), 3392 SDValue(Src.getNode(), Src.getResNo() + i), 3393 Add, MachinePointerInfo(PtrV, Offsets[i]), 3394 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3395 Chains[ChainI] = St; 3396 } 3397 3398 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 3399 MVT::Other, &Chains[0], ChainI); 3400 ++SDNodeOrder; 3401 AssignOrderingToNode(StoreNode.getNode()); 3402 DAG.setRoot(StoreNode); 3403} 3404 3405static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3406 SynchronizationScope Scope, 3407 bool Before, SDLoc dl, 3408 SelectionDAG &DAG, 3409 const TargetLowering &TLI) { 3410 // Fence, if necessary 3411 if (Before) { 3412 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3413 Order = Release; 3414 else if (Order == Acquire || Order == Monotonic) 3415 return Chain; 3416 } else { 3417 if (Order == AcquireRelease) 3418 Order = Acquire; 3419 else if (Order == Release || Order == Monotonic) 3420 return Chain; 3421 } 3422 SDValue Ops[3]; 3423 Ops[0] = Chain; 3424 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3425 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3426 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3427} 3428 3429void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3430 SDLoc dl = getCurSDLoc(); 3431 AtomicOrdering Order = I.getOrdering(); 3432 SynchronizationScope Scope = I.getSynchScope(); 3433 3434 SDValue InChain = getRoot(); 3435 3436 if (TLI.getInsertFencesForAtomic()) 3437 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3438 DAG, TLI); 3439 3440 SDValue L = 3441 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3442 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3443 InChain, 3444 getValue(I.getPointerOperand()), 3445 getValue(I.getCompareOperand()), 3446 getValue(I.getNewValOperand()), 3447 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3448 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3449 Scope); 3450 3451 SDValue OutChain = L.getValue(1); 3452 3453 if (TLI.getInsertFencesForAtomic()) 3454 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3455 DAG, TLI); 3456 3457 setValue(&I, L); 3458 DAG.setRoot(OutChain); 3459} 3460 3461void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3462 SDLoc dl = getCurSDLoc(); 3463 ISD::NodeType NT; 3464 switch (I.getOperation()) { 3465 default: llvm_unreachable("Unknown atomicrmw operation"); 3466 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3467 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3468 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3469 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3470 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3471 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3472 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3473 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3474 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3475 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3476 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3477 } 3478 AtomicOrdering Order = I.getOrdering(); 3479 SynchronizationScope Scope = I.getSynchScope(); 3480 3481 SDValue InChain = getRoot(); 3482 3483 if (TLI.getInsertFencesForAtomic()) 3484 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3485 DAG, TLI); 3486 3487 SDValue L = 3488 DAG.getAtomic(NT, dl, 3489 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3490 InChain, 3491 getValue(I.getPointerOperand()), 3492 getValue(I.getValOperand()), 3493 I.getPointerOperand(), 0 /* Alignment */, 3494 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3495 Scope); 3496 3497 SDValue OutChain = L.getValue(1); 3498 3499 if (TLI.getInsertFencesForAtomic()) 3500 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3501 DAG, TLI); 3502 3503 setValue(&I, L); 3504 DAG.setRoot(OutChain); 3505} 3506 3507void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3508 SDLoc dl = getCurSDLoc(); 3509 SDValue Ops[3]; 3510 Ops[0] = getRoot(); 3511 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3512 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3513 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3514} 3515 3516void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3517 SDLoc dl = getCurSDLoc(); 3518 AtomicOrdering Order = I.getOrdering(); 3519 SynchronizationScope Scope = I.getSynchScope(); 3520 3521 SDValue InChain = getRoot(); 3522 3523 EVT VT = TLI.getValueType(I.getType()); 3524 3525 if (I.getAlignment() < VT.getSizeInBits() / 8) 3526 report_fatal_error("Cannot generate unaligned atomic load"); 3527 3528 SDValue L = 3529 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3530 getValue(I.getPointerOperand()), 3531 I.getPointerOperand(), I.getAlignment(), 3532 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3533 Scope); 3534 3535 SDValue OutChain = L.getValue(1); 3536 3537 if (TLI.getInsertFencesForAtomic()) 3538 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3539 DAG, TLI); 3540 3541 setValue(&I, L); 3542 DAG.setRoot(OutChain); 3543} 3544 3545void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3546 SDLoc dl = getCurSDLoc(); 3547 3548 AtomicOrdering Order = I.getOrdering(); 3549 SynchronizationScope Scope = I.getSynchScope(); 3550 3551 SDValue InChain = getRoot(); 3552 3553 EVT VT = TLI.getValueType(I.getValueOperand()->getType()); 3554 3555 if (I.getAlignment() < VT.getSizeInBits() / 8) 3556 report_fatal_error("Cannot generate unaligned atomic store"); 3557 3558 if (TLI.getInsertFencesForAtomic()) 3559 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3560 DAG, TLI); 3561 3562 SDValue OutChain = 3563 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3564 InChain, 3565 getValue(I.getPointerOperand()), 3566 getValue(I.getValueOperand()), 3567 I.getPointerOperand(), I.getAlignment(), 3568 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3569 Scope); 3570 3571 if (TLI.getInsertFencesForAtomic()) 3572 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3573 DAG, TLI); 3574 3575 DAG.setRoot(OutChain); 3576} 3577 3578/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3579/// node. 3580void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3581 unsigned Intrinsic) { 3582 bool HasChain = !I.doesNotAccessMemory(); 3583 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3584 3585 // Build the operand list. 3586 SmallVector<SDValue, 8> Ops; 3587 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3588 if (OnlyLoad) { 3589 // We don't need to serialize loads against other loads. 3590 Ops.push_back(DAG.getRoot()); 3591 } else { 3592 Ops.push_back(getRoot()); 3593 } 3594 } 3595 3596 // Info is set by getTgtMemInstrinsic 3597 TargetLowering::IntrinsicInfo Info; 3598 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3599 3600 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3601 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3602 Info.opc == ISD::INTRINSIC_W_CHAIN) 3603 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy())); 3604 3605 // Add all operands of the call to the operand list. 3606 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3607 SDValue Op = getValue(I.getArgOperand(i)); 3608 Ops.push_back(Op); 3609 } 3610 3611 SmallVector<EVT, 4> ValueVTs; 3612 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3613 3614 if (HasChain) 3615 ValueVTs.push_back(MVT::Other); 3616 3617 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3618 3619 // Create the node. 3620 SDValue Result; 3621 if (IsTgtIntrinsic) { 3622 // This is target intrinsic that touches memory 3623 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), 3624 VTs, &Ops[0], Ops.size(), 3625 Info.memVT, 3626 MachinePointerInfo(Info.ptrVal, Info.offset), 3627 Info.align, Info.vol, 3628 Info.readMem, Info.writeMem); 3629 } else if (!HasChain) { 3630 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), 3631 VTs, &Ops[0], Ops.size()); 3632 } else if (!I.getType()->isVoidTy()) { 3633 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), 3634 VTs, &Ops[0], Ops.size()); 3635 } else { 3636 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), 3637 VTs, &Ops[0], Ops.size()); 3638 } 3639 3640 if (HasChain) { 3641 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3642 if (OnlyLoad) 3643 PendingLoads.push_back(Chain); 3644 else 3645 DAG.setRoot(Chain); 3646 } 3647 3648 if (!I.getType()->isVoidTy()) { 3649 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3650 EVT VT = TLI.getValueType(PTy); 3651 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result); 3652 } 3653 3654 setValue(&I, Result); 3655 } else { 3656 // Assign order to result here. If the intrinsic does not produce a result, 3657 // it won't be mapped to a SDNode and visit() will not assign it an order 3658 // number. 3659 ++SDNodeOrder; 3660 AssignOrderingToNode(Result.getNode()); 3661 } 3662} 3663 3664/// GetSignificand - Get the significand and build it into a floating-point 3665/// number with exponent of 1: 3666/// 3667/// Op = (Op & 0x007fffff) | 0x3f800000; 3668/// 3669/// where Op is the hexadecimal representation of floating point value. 3670static SDValue 3671GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) { 3672 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3673 DAG.getConstant(0x007fffff, MVT::i32)); 3674 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3675 DAG.getConstant(0x3f800000, MVT::i32)); 3676 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3677} 3678 3679/// GetExponent - Get the exponent: 3680/// 3681/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3682/// 3683/// where Op is the hexadecimal representation of floating point value. 3684static SDValue 3685GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3686 SDLoc dl) { 3687 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3688 DAG.getConstant(0x7f800000, MVT::i32)); 3689 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3690 DAG.getConstant(23, TLI.getPointerTy())); 3691 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3692 DAG.getConstant(127, MVT::i32)); 3693 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3694} 3695 3696/// getF32Constant - Get 32-bit floating point constant. 3697static SDValue 3698getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3699 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), 3700 MVT::f32); 3701} 3702 3703/// expandExp - Lower an exp intrinsic. Handles the special sequences for 3704/// limited-precision mode. 3705static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG, 3706 const TargetLowering &TLI) { 3707 if (Op.getValueType() == MVT::f32 && 3708 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3709 3710 // Put the exponent in the right bit position for later addition to the 3711 // final result: 3712 // 3713 // #define LOG2OFe 1.4426950f 3714 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3715 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3716 getF32Constant(DAG, 0x3fb8aa3b)); 3717 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3718 3719 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3720 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3721 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3722 3723 // IntegerPartOfX <<= 23; 3724 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3725 DAG.getConstant(23, TLI.getPointerTy())); 3726 3727 SDValue TwoToFracPartOfX; 3728 if (LimitFloatPrecision <= 6) { 3729 // For floating-point precision of 6: 3730 // 3731 // TwoToFractionalPartOfX = 3732 // 0.997535578f + 3733 // (0.735607626f + 0.252464424f * x) * x; 3734 // 3735 // error 0.0144103317, which is 6 bits 3736 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3737 getF32Constant(DAG, 0x3e814304)); 3738 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3739 getF32Constant(DAG, 0x3f3c50c8)); 3740 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3741 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3742 getF32Constant(DAG, 0x3f7f5e7e)); 3743 } else if (LimitFloatPrecision <= 12) { 3744 // For floating-point precision of 12: 3745 // 3746 // TwoToFractionalPartOfX = 3747 // 0.999892986f + 3748 // (0.696457318f + 3749 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3750 // 3751 // 0.000107046256 error, which is 13 to 14 bits 3752 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3753 getF32Constant(DAG, 0x3da235e3)); 3754 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3755 getF32Constant(DAG, 0x3e65b8f3)); 3756 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3757 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3758 getF32Constant(DAG, 0x3f324b07)); 3759 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3760 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3761 getF32Constant(DAG, 0x3f7ff8fd)); 3762 } else { // LimitFloatPrecision <= 18 3763 // For floating-point precision of 18: 3764 // 3765 // TwoToFractionalPartOfX = 3766 // 0.999999982f + 3767 // (0.693148872f + 3768 // (0.240227044f + 3769 // (0.554906021e-1f + 3770 // (0.961591928e-2f + 3771 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3772 // 3773 // error 2.47208000*10^(-7), which is better than 18 bits 3774 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3775 getF32Constant(DAG, 0x3924b03e)); 3776 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3777 getF32Constant(DAG, 0x3ab24b87)); 3778 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3779 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3780 getF32Constant(DAG, 0x3c1d8c17)); 3781 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3782 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3783 getF32Constant(DAG, 0x3d634a1d)); 3784 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3785 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3786 getF32Constant(DAG, 0x3e75fe14)); 3787 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3788 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3789 getF32Constant(DAG, 0x3f317234)); 3790 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3791 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3792 getF32Constant(DAG, 0x3f800000)); 3793 } 3794 3795 // Add the exponent into the result in integer domain. 3796 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX); 3797 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 3798 DAG.getNode(ISD::ADD, dl, MVT::i32, 3799 t13, IntegerPartOfX)); 3800 } 3801 3802 // No special expansion. 3803 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op); 3804} 3805 3806/// expandLog - Lower a log intrinsic. Handles the special sequences for 3807/// limited-precision mode. 3808static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG, 3809 const TargetLowering &TLI) { 3810 if (Op.getValueType() == MVT::f32 && 3811 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3812 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3813 3814 // Scale the exponent by log(2) [0.69314718f]. 3815 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3816 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3817 getF32Constant(DAG, 0x3f317218)); 3818 3819 // Get the significand and build it into a floating-point number with 3820 // exponent of 1. 3821 SDValue X = GetSignificand(DAG, Op1, dl); 3822 3823 SDValue LogOfMantissa; 3824 if (LimitFloatPrecision <= 6) { 3825 // For floating-point precision of 6: 3826 // 3827 // LogofMantissa = 3828 // -1.1609546f + 3829 // (1.4034025f - 0.23903021f * x) * x; 3830 // 3831 // error 0.0034276066, which is better than 8 bits 3832 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3833 getF32Constant(DAG, 0xbe74c456)); 3834 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3835 getF32Constant(DAG, 0x3fb3a2b1)); 3836 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3837 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3838 getF32Constant(DAG, 0x3f949a29)); 3839 } else if (LimitFloatPrecision <= 12) { 3840 // For floating-point precision of 12: 3841 // 3842 // LogOfMantissa = 3843 // -1.7417939f + 3844 // (2.8212026f + 3845 // (-1.4699568f + 3846 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3847 // 3848 // error 0.000061011436, which is 14 bits 3849 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3850 getF32Constant(DAG, 0xbd67b6d6)); 3851 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3852 getF32Constant(DAG, 0x3ee4f4b8)); 3853 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3854 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3855 getF32Constant(DAG, 0x3fbc278b)); 3856 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3857 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3858 getF32Constant(DAG, 0x40348e95)); 3859 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3860 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3861 getF32Constant(DAG, 0x3fdef31a)); 3862 } else { // LimitFloatPrecision <= 18 3863 // For floating-point precision of 18: 3864 // 3865 // LogOfMantissa = 3866 // -2.1072184f + 3867 // (4.2372794f + 3868 // (-3.7029485f + 3869 // (2.2781945f + 3870 // (-0.87823314f + 3871 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3872 // 3873 // error 0.0000023660568, which is better than 18 bits 3874 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3875 getF32Constant(DAG, 0xbc91e5ac)); 3876 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3877 getF32Constant(DAG, 0x3e4350aa)); 3878 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3879 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3880 getF32Constant(DAG, 0x3f60d3e3)); 3881 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3882 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3883 getF32Constant(DAG, 0x4011cdf0)); 3884 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3885 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3886 getF32Constant(DAG, 0x406cfd1c)); 3887 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3888 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3889 getF32Constant(DAG, 0x408797cb)); 3890 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3891 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3892 getF32Constant(DAG, 0x4006dcab)); 3893 } 3894 3895 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa); 3896 } 3897 3898 // No special expansion. 3899 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op); 3900} 3901 3902/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for 3903/// limited-precision mode. 3904static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG, 3905 const TargetLowering &TLI) { 3906 if (Op.getValueType() == MVT::f32 && 3907 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3908 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3909 3910 // Get the exponent. 3911 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3912 3913 // Get the significand and build it into a floating-point number with 3914 // exponent of 1. 3915 SDValue X = GetSignificand(DAG, Op1, dl); 3916 3917 // Different possible minimax approximations of significand in 3918 // floating-point for various degrees of accuracy over [1,2]. 3919 SDValue Log2ofMantissa; 3920 if (LimitFloatPrecision <= 6) { 3921 // For floating-point precision of 6: 3922 // 3923 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3924 // 3925 // error 0.0049451742, which is more than 7 bits 3926 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3927 getF32Constant(DAG, 0xbeb08fe0)); 3928 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3929 getF32Constant(DAG, 0x40019463)); 3930 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3931 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3932 getF32Constant(DAG, 0x3fd6633d)); 3933 } else if (LimitFloatPrecision <= 12) { 3934 // For floating-point precision of 12: 3935 // 3936 // Log2ofMantissa = 3937 // -2.51285454f + 3938 // (4.07009056f + 3939 // (-2.12067489f + 3940 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3941 // 3942 // error 0.0000876136000, which is better than 13 bits 3943 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3944 getF32Constant(DAG, 0xbda7262e)); 3945 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3946 getF32Constant(DAG, 0x3f25280b)); 3947 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3948 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3949 getF32Constant(DAG, 0x4007b923)); 3950 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3951 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3952 getF32Constant(DAG, 0x40823e2f)); 3953 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3954 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3955 getF32Constant(DAG, 0x4020d29c)); 3956 } else { // LimitFloatPrecision <= 18 3957 // For floating-point precision of 18: 3958 // 3959 // Log2ofMantissa = 3960 // -3.0400495f + 3961 // (6.1129976f + 3962 // (-5.3420409f + 3963 // (3.2865683f + 3964 // (-1.2669343f + 3965 // (0.27515199f - 3966 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3967 // 3968 // error 0.0000018516, which is better than 18 bits 3969 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3970 getF32Constant(DAG, 0xbcd2769e)); 3971 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3972 getF32Constant(DAG, 0x3e8ce0b9)); 3973 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3974 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3975 getF32Constant(DAG, 0x3fa22ae7)); 3976 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3977 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3978 getF32Constant(DAG, 0x40525723)); 3979 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3980 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3981 getF32Constant(DAG, 0x40aaf200)); 3982 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3983 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3984 getF32Constant(DAG, 0x40c39dad)); 3985 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3986 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3987 getF32Constant(DAG, 0x4042902c)); 3988 } 3989 3990 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa); 3991 } 3992 3993 // No special expansion. 3994 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op); 3995} 3996 3997/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for 3998/// limited-precision mode. 3999static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG, 4000 const TargetLowering &TLI) { 4001 if (Op.getValueType() == MVT::f32 && 4002 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4003 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 4004 4005 // Scale the exponent by log10(2) [0.30102999f]. 4006 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 4007 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 4008 getF32Constant(DAG, 0x3e9a209a)); 4009 4010 // Get the significand and build it into a floating-point number with 4011 // exponent of 1. 4012 SDValue X = GetSignificand(DAG, Op1, dl); 4013 4014 SDValue Log10ofMantissa; 4015 if (LimitFloatPrecision <= 6) { 4016 // For floating-point precision of 6: 4017 // 4018 // Log10ofMantissa = 4019 // -0.50419619f + 4020 // (0.60948995f - 0.10380950f * x) * x; 4021 // 4022 // error 0.0014886165, which is 6 bits 4023 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4024 getF32Constant(DAG, 0xbdd49a13)); 4025 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4026 getF32Constant(DAG, 0x3f1c0789)); 4027 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4028 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4029 getF32Constant(DAG, 0x3f011300)); 4030 } else if (LimitFloatPrecision <= 12) { 4031 // For floating-point precision of 12: 4032 // 4033 // Log10ofMantissa = 4034 // -0.64831180f + 4035 // (0.91751397f + 4036 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4037 // 4038 // error 0.00019228036, which is better than 12 bits 4039 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4040 getF32Constant(DAG, 0x3d431f31)); 4041 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4042 getF32Constant(DAG, 0x3ea21fb2)); 4043 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4044 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4045 getF32Constant(DAG, 0x3f6ae232)); 4046 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4047 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4048 getF32Constant(DAG, 0x3f25f7c3)); 4049 } else { // LimitFloatPrecision <= 18 4050 // For floating-point precision of 18: 4051 // 4052 // Log10ofMantissa = 4053 // -0.84299375f + 4054 // (1.5327582f + 4055 // (-1.0688956f + 4056 // (0.49102474f + 4057 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4058 // 4059 // error 0.0000037995730, which is better than 18 bits 4060 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4061 getF32Constant(DAG, 0x3c5d51ce)); 4062 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4063 getF32Constant(DAG, 0x3e00685a)); 4064 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4065 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4066 getF32Constant(DAG, 0x3efb6798)); 4067 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4068 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4069 getF32Constant(DAG, 0x3f88d192)); 4070 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4071 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4072 getF32Constant(DAG, 0x3fc4316c)); 4073 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4074 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4075 getF32Constant(DAG, 0x3f57ce70)); 4076 } 4077 4078 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa); 4079 } 4080 4081 // No special expansion. 4082 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op); 4083} 4084 4085/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4086/// limited-precision mode. 4087static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG, 4088 const TargetLowering &TLI) { 4089 if (Op.getValueType() == MVT::f32 && 4090 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4091 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4092 4093 // FractionalPartOfX = x - (float)IntegerPartOfX; 4094 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4095 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4096 4097 // IntegerPartOfX <<= 23; 4098 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4099 DAG.getConstant(23, TLI.getPointerTy())); 4100 4101 SDValue TwoToFractionalPartOfX; 4102 if (LimitFloatPrecision <= 6) { 4103 // For floating-point precision of 6: 4104 // 4105 // TwoToFractionalPartOfX = 4106 // 0.997535578f + 4107 // (0.735607626f + 0.252464424f * x) * x; 4108 // 4109 // error 0.0144103317, which is 6 bits 4110 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4111 getF32Constant(DAG, 0x3e814304)); 4112 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4113 getF32Constant(DAG, 0x3f3c50c8)); 4114 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4115 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4116 getF32Constant(DAG, 0x3f7f5e7e)); 4117 } else if (LimitFloatPrecision <= 12) { 4118 // For floating-point precision of 12: 4119 // 4120 // TwoToFractionalPartOfX = 4121 // 0.999892986f + 4122 // (0.696457318f + 4123 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4124 // 4125 // error 0.000107046256, which is 13 to 14 bits 4126 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4127 getF32Constant(DAG, 0x3da235e3)); 4128 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4129 getF32Constant(DAG, 0x3e65b8f3)); 4130 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4131 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4132 getF32Constant(DAG, 0x3f324b07)); 4133 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4134 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4135 getF32Constant(DAG, 0x3f7ff8fd)); 4136 } else { // LimitFloatPrecision <= 18 4137 // For floating-point precision of 18: 4138 // 4139 // TwoToFractionalPartOfX = 4140 // 0.999999982f + 4141 // (0.693148872f + 4142 // (0.240227044f + 4143 // (0.554906021e-1f + 4144 // (0.961591928e-2f + 4145 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4146 // error 2.47208000*10^(-7), which is better than 18 bits 4147 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4148 getF32Constant(DAG, 0x3924b03e)); 4149 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4150 getF32Constant(DAG, 0x3ab24b87)); 4151 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4152 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4153 getF32Constant(DAG, 0x3c1d8c17)); 4154 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4155 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4156 getF32Constant(DAG, 0x3d634a1d)); 4157 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4158 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4159 getF32Constant(DAG, 0x3e75fe14)); 4160 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4161 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4162 getF32Constant(DAG, 0x3f317234)); 4163 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4164 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4165 getF32Constant(DAG, 0x3f800000)); 4166 } 4167 4168 // Add the exponent into the result in integer domain. 4169 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, 4170 TwoToFractionalPartOfX); 4171 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 4172 DAG.getNode(ISD::ADD, dl, MVT::i32, 4173 t13, IntegerPartOfX)); 4174 } 4175 4176 // No special expansion. 4177 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op); 4178} 4179 4180/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4181/// limited-precision mode with x == 10.0f. 4182static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS, 4183 SelectionDAG &DAG, const TargetLowering &TLI) { 4184 bool IsExp10 = false; 4185 if (LHS.getValueType() == MVT::f32 && LHS.getValueType() == MVT::f32 && 4186 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4187 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) { 4188 APFloat Ten(10.0f); 4189 IsExp10 = LHSC->isExactlyValue(Ten); 4190 } 4191 } 4192 4193 if (IsExp10) { 4194 // Put the exponent in the right bit position for later addition to the 4195 // final result: 4196 // 4197 // #define LOG2OF10 3.3219281f 4198 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4199 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS, 4200 getF32Constant(DAG, 0x40549a78)); 4201 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4202 4203 // FractionalPartOfX = x - (float)IntegerPartOfX; 4204 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4205 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4206 4207 // IntegerPartOfX <<= 23; 4208 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4209 DAG.getConstant(23, TLI.getPointerTy())); 4210 4211 SDValue TwoToFractionalPartOfX; 4212 if (LimitFloatPrecision <= 6) { 4213 // For floating-point precision of 6: 4214 // 4215 // twoToFractionalPartOfX = 4216 // 0.997535578f + 4217 // (0.735607626f + 0.252464424f * x) * x; 4218 // 4219 // error 0.0144103317, which is 6 bits 4220 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4221 getF32Constant(DAG, 0x3e814304)); 4222 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4223 getF32Constant(DAG, 0x3f3c50c8)); 4224 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4225 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4226 getF32Constant(DAG, 0x3f7f5e7e)); 4227 } else if (LimitFloatPrecision <= 12) { 4228 // For floating-point precision of 12: 4229 // 4230 // TwoToFractionalPartOfX = 4231 // 0.999892986f + 4232 // (0.696457318f + 4233 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4234 // 4235 // error 0.000107046256, which is 13 to 14 bits 4236 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4237 getF32Constant(DAG, 0x3da235e3)); 4238 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4239 getF32Constant(DAG, 0x3e65b8f3)); 4240 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4241 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4242 getF32Constant(DAG, 0x3f324b07)); 4243 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4244 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4245 getF32Constant(DAG, 0x3f7ff8fd)); 4246 } else { // LimitFloatPrecision <= 18 4247 // For floating-point precision of 18: 4248 // 4249 // TwoToFractionalPartOfX = 4250 // 0.999999982f + 4251 // (0.693148872f + 4252 // (0.240227044f + 4253 // (0.554906021e-1f + 4254 // (0.961591928e-2f + 4255 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4256 // error 2.47208000*10^(-7), which is better than 18 bits 4257 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4258 getF32Constant(DAG, 0x3924b03e)); 4259 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4260 getF32Constant(DAG, 0x3ab24b87)); 4261 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4262 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4263 getF32Constant(DAG, 0x3c1d8c17)); 4264 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4265 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4266 getF32Constant(DAG, 0x3d634a1d)); 4267 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4268 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4269 getF32Constant(DAG, 0x3e75fe14)); 4270 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4271 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4272 getF32Constant(DAG, 0x3f317234)); 4273 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4274 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4275 getF32Constant(DAG, 0x3f800000)); 4276 } 4277 4278 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX); 4279 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 4280 DAG.getNode(ISD::ADD, dl, MVT::i32, 4281 t13, IntegerPartOfX)); 4282 } 4283 4284 // No special expansion. 4285 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS); 4286} 4287 4288 4289/// ExpandPowI - Expand a llvm.powi intrinsic. 4290static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS, 4291 SelectionDAG &DAG) { 4292 // If RHS is a constant, we can expand this out to a multiplication tree, 4293 // otherwise we end up lowering to a call to __powidf2 (for example). When 4294 // optimizing for size, we only want to do this if the expansion would produce 4295 // a small number of multiplies, otherwise we do the full expansion. 4296 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4297 // Get the exponent as a positive value. 4298 unsigned Val = RHSC->getSExtValue(); 4299 if ((int)Val < 0) Val = -Val; 4300 4301 // powi(x, 0) -> 1.0 4302 if (Val == 0) 4303 return DAG.getConstantFP(1.0, LHS.getValueType()); 4304 4305 const Function *F = DAG.getMachineFunction().getFunction(); 4306 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 4307 Attribute::OptimizeForSize) || 4308 // If optimizing for size, don't insert too many multiplies. This 4309 // inserts up to 5 multiplies. 4310 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4311 // We use the simple binary decomposition method to generate the multiply 4312 // sequence. There are more optimal ways to do this (for example, 4313 // powi(x,15) generates one more multiply than it should), but this has 4314 // the benefit of being both really simple and much better than a libcall. 4315 SDValue Res; // Logically starts equal to 1.0 4316 SDValue CurSquare = LHS; 4317 while (Val) { 4318 if (Val & 1) { 4319 if (Res.getNode()) 4320 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4321 else 4322 Res = CurSquare; // 1.0*CurSquare. 4323 } 4324 4325 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4326 CurSquare, CurSquare); 4327 Val >>= 1; 4328 } 4329 4330 // If the original was negative, invert the result, producing 1/(x*x*x). 4331 if (RHSC->getSExtValue() < 0) 4332 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4333 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4334 return Res; 4335 } 4336 } 4337 4338 // Otherwise, expand to a libcall. 4339 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4340} 4341 4342// getTruncatedArgReg - Find underlying register used for an truncated 4343// argument. 4344static unsigned getTruncatedArgReg(const SDValue &N) { 4345 if (N.getOpcode() != ISD::TRUNCATE) 4346 return 0; 4347 4348 const SDValue &Ext = N.getOperand(0); 4349 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4350 const SDValue &CFR = Ext.getOperand(0); 4351 if (CFR.getOpcode() == ISD::CopyFromReg) 4352 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4353 if (CFR.getOpcode() == ISD::TRUNCATE) 4354 return getTruncatedArgReg(CFR); 4355 } 4356 return 0; 4357} 4358 4359/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4360/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4361/// At the end of instruction selection, they will be inserted to the entry BB. 4362bool 4363SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4364 int64_t Offset, 4365 const SDValue &N) { 4366 const Argument *Arg = dyn_cast<Argument>(V); 4367 if (!Arg) 4368 return false; 4369 4370 MachineFunction &MF = DAG.getMachineFunction(); 4371 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4372 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4373 4374 // Ignore inlined function arguments here. 4375 DIVariable DV(Variable); 4376 if (DV.isInlinedFnArgument(MF.getFunction())) 4377 return false; 4378 4379 unsigned Reg = 0; 4380 // Some arguments' frame index is recorded during argument lowering. 4381 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4382 if (Offset) 4383 Reg = TRI->getFrameRegister(MF); 4384 4385 if (!Reg && N.getNode()) { 4386 if (N.getOpcode() == ISD::CopyFromReg) 4387 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4388 else 4389 Reg = getTruncatedArgReg(N); 4390 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4391 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4392 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4393 if (PR) 4394 Reg = PR; 4395 } 4396 } 4397 4398 if (!Reg) { 4399 // Check if ValueMap has reg number. 4400 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4401 if (VMI != FuncInfo.ValueMap.end()) 4402 Reg = VMI->second; 4403 } 4404 4405 if (!Reg && N.getNode()) { 4406 // Check if frame index is available. 4407 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4408 if (FrameIndexSDNode *FINode = 4409 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4410 Reg = TRI->getFrameRegister(MF); 4411 Offset = FINode->getIndex(); 4412 } 4413 } 4414 4415 if (!Reg) 4416 return false; 4417 4418 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4419 TII->get(TargetOpcode::DBG_VALUE)) 4420 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4421 FuncInfo.ArgDbgValues.push_back(&*MIB); 4422 return true; 4423} 4424 4425// VisualStudio defines setjmp as _setjmp 4426#if defined(_MSC_VER) && defined(setjmp) && \ 4427 !defined(setjmp_undefined_for_msvc) 4428# pragma push_macro("setjmp") 4429# undef setjmp 4430# define setjmp_undefined_for_msvc 4431#endif 4432 4433/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4434/// we want to emit this as a call to a named external function, return the name 4435/// otherwise lower it and return null. 4436const char * 4437SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4438 SDLoc sdl = getCurSDLoc(); 4439 DebugLoc dl = getCurDebugLoc(); 4440 SDValue Res; 4441 4442 switch (Intrinsic) { 4443 default: 4444 // By default, turn this into a target intrinsic node. 4445 visitTargetIntrinsic(I, Intrinsic); 4446 return 0; 4447 case Intrinsic::vastart: visitVAStart(I); return 0; 4448 case Intrinsic::vaend: visitVAEnd(I); return 0; 4449 case Intrinsic::vacopy: visitVACopy(I); return 0; 4450 case Intrinsic::returnaddress: 4451 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(), 4452 getValue(I.getArgOperand(0)))); 4453 return 0; 4454 case Intrinsic::frameaddress: 4455 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(), 4456 getValue(I.getArgOperand(0)))); 4457 return 0; 4458 case Intrinsic::setjmp: 4459 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()]; 4460 case Intrinsic::longjmp: 4461 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()]; 4462 case Intrinsic::memcpy: { 4463 // Assert for address < 256 since we support only user defined address 4464 // spaces. 4465 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4466 < 256 && 4467 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4468 < 256 && 4469 "Unknown address space"); 4470 SDValue Op1 = getValue(I.getArgOperand(0)); 4471 SDValue Op2 = getValue(I.getArgOperand(1)); 4472 SDValue Op3 = getValue(I.getArgOperand(2)); 4473 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4474 if (!Align) 4475 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment. 4476 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4477 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false, 4478 MachinePointerInfo(I.getArgOperand(0)), 4479 MachinePointerInfo(I.getArgOperand(1)))); 4480 return 0; 4481 } 4482 case Intrinsic::memset: { 4483 // Assert for address < 256 since we support only user defined address 4484 // spaces. 4485 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4486 < 256 && 4487 "Unknown address space"); 4488 SDValue Op1 = getValue(I.getArgOperand(0)); 4489 SDValue Op2 = getValue(I.getArgOperand(1)); 4490 SDValue Op3 = getValue(I.getArgOperand(2)); 4491 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4492 if (!Align) 4493 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment. 4494 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4495 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, 4496 MachinePointerInfo(I.getArgOperand(0)))); 4497 return 0; 4498 } 4499 case Intrinsic::memmove: { 4500 // Assert for address < 256 since we support only user defined address 4501 // spaces. 4502 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4503 < 256 && 4504 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4505 < 256 && 4506 "Unknown address space"); 4507 SDValue Op1 = getValue(I.getArgOperand(0)); 4508 SDValue Op2 = getValue(I.getArgOperand(1)); 4509 SDValue Op3 = getValue(I.getArgOperand(2)); 4510 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4511 if (!Align) 4512 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment. 4513 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4514 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, 4515 MachinePointerInfo(I.getArgOperand(0)), 4516 MachinePointerInfo(I.getArgOperand(1)))); 4517 return 0; 4518 } 4519 case Intrinsic::dbg_declare: { 4520 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4521 MDNode *Variable = DI.getVariable(); 4522 const Value *Address = DI.getAddress(); 4523 if (!Address || !DIVariable(Variable).Verify()) { 4524 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4525 return 0; 4526 } 4527 4528 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4529 // but do not always have a corresponding SDNode built. The SDNodeOrder 4530 // absolute, but not relative, values are different depending on whether 4531 // debug info exists. 4532 ++SDNodeOrder; 4533 4534 // Check if address has undef value. 4535 if (isa<UndefValue>(Address) || 4536 (Address->use_empty() && !isa<Argument>(Address))) { 4537 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4538 return 0; 4539 } 4540 4541 SDValue &N = NodeMap[Address]; 4542 if (!N.getNode() && isa<Argument>(Address)) 4543 // Check unused arguments map. 4544 N = UnusedArgNodeMap[Address]; 4545 SDDbgValue *SDV; 4546 if (N.getNode()) { 4547 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4548 Address = BCI->getOperand(0); 4549 // Parameters are handled specially. 4550 bool isParameter = 4551 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable || 4552 isa<Argument>(Address)); 4553 4554 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4555 4556 if (isParameter && !AI) { 4557 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4558 if (FINode) 4559 // Byval parameter. We have a frame index at this point. 4560 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4561 0, dl, SDNodeOrder); 4562 else { 4563 // Address is an argument, so try to emit its dbg value using 4564 // virtual register info from the FuncInfo.ValueMap. 4565 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4566 return 0; 4567 } 4568 } else if (AI) 4569 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4570 0, dl, SDNodeOrder); 4571 else { 4572 // Can't do anything with other non-AI cases yet. 4573 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4574 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t"); 4575 DEBUG(Address->dump()); 4576 return 0; 4577 } 4578 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4579 } else { 4580 // If Address is an argument then try to emit its dbg value using 4581 // virtual register info from the FuncInfo.ValueMap. 4582 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4583 // If variable is pinned by a alloca in dominating bb then 4584 // use StaticAllocaMap. 4585 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4586 if (AI->getParent() != DI.getParent()) { 4587 DenseMap<const AllocaInst*, int>::iterator SI = 4588 FuncInfo.StaticAllocaMap.find(AI); 4589 if (SI != FuncInfo.StaticAllocaMap.end()) { 4590 SDV = DAG.getDbgValue(Variable, SI->second, 4591 0, dl, SDNodeOrder); 4592 DAG.AddDbgValue(SDV, 0, false); 4593 return 0; 4594 } 4595 } 4596 } 4597 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4598 } 4599 } 4600 return 0; 4601 } 4602 case Intrinsic::dbg_value: { 4603 const DbgValueInst &DI = cast<DbgValueInst>(I); 4604 if (!DIVariable(DI.getVariable()).Verify()) 4605 return 0; 4606 4607 MDNode *Variable = DI.getVariable(); 4608 uint64_t Offset = DI.getOffset(); 4609 const Value *V = DI.getValue(); 4610 if (!V) 4611 return 0; 4612 4613 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4614 // but do not always have a corresponding SDNode built. The SDNodeOrder 4615 // absolute, but not relative, values are different depending on whether 4616 // debug info exists. 4617 ++SDNodeOrder; 4618 SDDbgValue *SDV; 4619 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4620 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4621 DAG.AddDbgValue(SDV, 0, false); 4622 } else { 4623 // Do not use getValue() in here; we don't want to generate code at 4624 // this point if it hasn't been done yet. 4625 SDValue N = NodeMap[V]; 4626 if (!N.getNode() && isa<Argument>(V)) 4627 // Check unused arguments map. 4628 N = UnusedArgNodeMap[V]; 4629 if (N.getNode()) { 4630 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4631 SDV = DAG.getDbgValue(Variable, N.getNode(), 4632 N.getResNo(), Offset, dl, SDNodeOrder); 4633 DAG.AddDbgValue(SDV, N.getNode(), false); 4634 } 4635 } else if (!V->use_empty() ) { 4636 // Do not call getValue(V) yet, as we don't want to generate code. 4637 // Remember it for later. 4638 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4639 DanglingDebugInfoMap[V] = DDI; 4640 } else { 4641 // We may expand this to cover more cases. One case where we have no 4642 // data available is an unreferenced parameter. 4643 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4644 } 4645 } 4646 4647 // Build a debug info table entry. 4648 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4649 V = BCI->getOperand(0); 4650 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4651 // Don't handle byval struct arguments or VLAs, for example. 4652 if (!AI) { 4653 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); 4654 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); 4655 return 0; 4656 } 4657 DenseMap<const AllocaInst*, int>::iterator SI = 4658 FuncInfo.StaticAllocaMap.find(AI); 4659 if (SI == FuncInfo.StaticAllocaMap.end()) 4660 return 0; // VLAs. 4661 int FI = SI->second; 4662 4663 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4664 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4665 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4666 return 0; 4667 } 4668 4669 case Intrinsic::eh_typeid_for: { 4670 // Find the type id for the given typeinfo. 4671 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4672 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4673 Res = DAG.getConstant(TypeID, MVT::i32); 4674 setValue(&I, Res); 4675 return 0; 4676 } 4677 4678 case Intrinsic::eh_return_i32: 4679 case Intrinsic::eh_return_i64: 4680 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4681 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl, 4682 MVT::Other, 4683 getControlRoot(), 4684 getValue(I.getArgOperand(0)), 4685 getValue(I.getArgOperand(1)))); 4686 return 0; 4687 case Intrinsic::eh_unwind_init: 4688 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4689 return 0; 4690 case Intrinsic::eh_dwarf_cfa: { 4691 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl, 4692 TLI.getPointerTy()); 4693 SDValue Offset = DAG.getNode(ISD::ADD, sdl, 4694 TLI.getPointerTy(), 4695 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl, 4696 TLI.getPointerTy()), 4697 CfaArg); 4698 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, 4699 TLI.getPointerTy(), 4700 DAG.getConstant(0, TLI.getPointerTy())); 4701 setValue(&I, DAG.getNode(ISD::ADD, sdl, TLI.getPointerTy(), 4702 FA, Offset)); 4703 return 0; 4704 } 4705 case Intrinsic::eh_sjlj_callsite: { 4706 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4707 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4708 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4709 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4710 4711 MMI.setCurrentCallSite(CI->getZExtValue()); 4712 return 0; 4713 } 4714 case Intrinsic::eh_sjlj_functioncontext: { 4715 // Get and store the index of the function context. 4716 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4717 AllocaInst *FnCtx = 4718 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4719 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4720 MFI->setFunctionContextIndex(FI); 4721 return 0; 4722 } 4723 case Intrinsic::eh_sjlj_setjmp: { 4724 SDValue Ops[2]; 4725 Ops[0] = getRoot(); 4726 Ops[1] = getValue(I.getArgOperand(0)); 4727 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl, 4728 DAG.getVTList(MVT::i32, MVT::Other), 4729 Ops, 2); 4730 setValue(&I, Op.getValue(0)); 4731 DAG.setRoot(Op.getValue(1)); 4732 return 0; 4733 } 4734 case Intrinsic::eh_sjlj_longjmp: { 4735 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other, 4736 getRoot(), getValue(I.getArgOperand(0)))); 4737 return 0; 4738 } 4739 4740 case Intrinsic::x86_mmx_pslli_w: 4741 case Intrinsic::x86_mmx_pslli_d: 4742 case Intrinsic::x86_mmx_pslli_q: 4743 case Intrinsic::x86_mmx_psrli_w: 4744 case Intrinsic::x86_mmx_psrli_d: 4745 case Intrinsic::x86_mmx_psrli_q: 4746 case Intrinsic::x86_mmx_psrai_w: 4747 case Intrinsic::x86_mmx_psrai_d: { 4748 SDValue ShAmt = getValue(I.getArgOperand(1)); 4749 if (isa<ConstantSDNode>(ShAmt)) { 4750 visitTargetIntrinsic(I, Intrinsic); 4751 return 0; 4752 } 4753 unsigned NewIntrinsic = 0; 4754 EVT ShAmtVT = MVT::v2i32; 4755 switch (Intrinsic) { 4756 case Intrinsic::x86_mmx_pslli_w: 4757 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4758 break; 4759 case Intrinsic::x86_mmx_pslli_d: 4760 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4761 break; 4762 case Intrinsic::x86_mmx_pslli_q: 4763 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4764 break; 4765 case Intrinsic::x86_mmx_psrli_w: 4766 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4767 break; 4768 case Intrinsic::x86_mmx_psrli_d: 4769 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4770 break; 4771 case Intrinsic::x86_mmx_psrli_q: 4772 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4773 break; 4774 case Intrinsic::x86_mmx_psrai_w: 4775 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4776 break; 4777 case Intrinsic::x86_mmx_psrai_d: 4778 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4779 break; 4780 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4781 } 4782 4783 // The vector shift intrinsics with scalars uses 32b shift amounts but 4784 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4785 // to be zero. 4786 // We must do this early because v2i32 is not a legal type. 4787 SDValue ShOps[2]; 4788 ShOps[0] = ShAmt; 4789 ShOps[1] = DAG.getConstant(0, MVT::i32); 4790 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, &ShOps[0], 2); 4791 EVT DestVT = TLI.getValueType(I.getType()); 4792 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt); 4793 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT, 4794 DAG.getConstant(NewIntrinsic, MVT::i32), 4795 getValue(I.getArgOperand(0)), ShAmt); 4796 setValue(&I, Res); 4797 return 0; 4798 } 4799 case Intrinsic::x86_avx_vinsertf128_pd_256: 4800 case Intrinsic::x86_avx_vinsertf128_ps_256: 4801 case Intrinsic::x86_avx_vinsertf128_si_256: 4802 case Intrinsic::x86_avx2_vinserti128: { 4803 EVT DestVT = TLI.getValueType(I.getType()); 4804 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType()); 4805 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) * 4806 ElVT.getVectorNumElements(); 4807 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT, 4808 getValue(I.getArgOperand(0)), 4809 getValue(I.getArgOperand(1)), 4810 DAG.getIntPtrConstant(Idx)); 4811 setValue(&I, Res); 4812 return 0; 4813 } 4814 case Intrinsic::x86_avx_vextractf128_pd_256: 4815 case Intrinsic::x86_avx_vextractf128_ps_256: 4816 case Intrinsic::x86_avx_vextractf128_si_256: 4817 case Intrinsic::x86_avx2_vextracti128: { 4818 EVT DestVT = TLI.getValueType(I.getType()); 4819 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) * 4820 DestVT.getVectorNumElements(); 4821 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT, 4822 getValue(I.getArgOperand(0)), 4823 DAG.getIntPtrConstant(Idx)); 4824 setValue(&I, Res); 4825 return 0; 4826 } 4827 case Intrinsic::convertff: 4828 case Intrinsic::convertfsi: 4829 case Intrinsic::convertfui: 4830 case Intrinsic::convertsif: 4831 case Intrinsic::convertuif: 4832 case Intrinsic::convertss: 4833 case Intrinsic::convertsu: 4834 case Intrinsic::convertus: 4835 case Intrinsic::convertuu: { 4836 ISD::CvtCode Code = ISD::CVT_INVALID; 4837 switch (Intrinsic) { 4838 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4839 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4840 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4841 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4842 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4843 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4844 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4845 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4846 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4847 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4848 } 4849 EVT DestVT = TLI.getValueType(I.getType()); 4850 const Value *Op1 = I.getArgOperand(0); 4851 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1), 4852 DAG.getValueType(DestVT), 4853 DAG.getValueType(getValue(Op1).getValueType()), 4854 getValue(I.getArgOperand(1)), 4855 getValue(I.getArgOperand(2)), 4856 Code); 4857 setValue(&I, Res); 4858 return 0; 4859 } 4860 case Intrinsic::powi: 4861 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)), 4862 getValue(I.getArgOperand(1)), DAG)); 4863 return 0; 4864 case Intrinsic::log: 4865 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI)); 4866 return 0; 4867 case Intrinsic::log2: 4868 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI)); 4869 return 0; 4870 case Intrinsic::log10: 4871 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI)); 4872 return 0; 4873 case Intrinsic::exp: 4874 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI)); 4875 return 0; 4876 case Intrinsic::exp2: 4877 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI)); 4878 return 0; 4879 case Intrinsic::pow: 4880 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)), 4881 getValue(I.getArgOperand(1)), DAG, TLI)); 4882 return 0; 4883 case Intrinsic::sqrt: 4884 case Intrinsic::fabs: 4885 case Intrinsic::sin: 4886 case Intrinsic::cos: 4887 case Intrinsic::floor: 4888 case Intrinsic::ceil: 4889 case Intrinsic::trunc: 4890 case Intrinsic::rint: 4891 case Intrinsic::nearbyint: { 4892 unsigned Opcode; 4893 switch (Intrinsic) { 4894 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4895 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; 4896 case Intrinsic::fabs: Opcode = ISD::FABS; break; 4897 case Intrinsic::sin: Opcode = ISD::FSIN; break; 4898 case Intrinsic::cos: Opcode = ISD::FCOS; break; 4899 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; 4900 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; 4901 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; 4902 case Intrinsic::rint: Opcode = ISD::FRINT; break; 4903 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; 4904 } 4905 4906 setValue(&I, DAG.getNode(Opcode, sdl, 4907 getValue(I.getArgOperand(0)).getValueType(), 4908 getValue(I.getArgOperand(0)))); 4909 return 0; 4910 } 4911 case Intrinsic::fma: 4912 setValue(&I, DAG.getNode(ISD::FMA, sdl, 4913 getValue(I.getArgOperand(0)).getValueType(), 4914 getValue(I.getArgOperand(0)), 4915 getValue(I.getArgOperand(1)), 4916 getValue(I.getArgOperand(2)))); 4917 return 0; 4918 case Intrinsic::fmuladd: { 4919 EVT VT = TLI.getValueType(I.getType()); 4920 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && 4921 TLI.isFMAFasterThanMulAndAdd(VT)){ 4922 setValue(&I, DAG.getNode(ISD::FMA, sdl, 4923 getValue(I.getArgOperand(0)).getValueType(), 4924 getValue(I.getArgOperand(0)), 4925 getValue(I.getArgOperand(1)), 4926 getValue(I.getArgOperand(2)))); 4927 } else { 4928 SDValue Mul = DAG.getNode(ISD::FMUL, sdl, 4929 getValue(I.getArgOperand(0)).getValueType(), 4930 getValue(I.getArgOperand(0)), 4931 getValue(I.getArgOperand(1))); 4932 SDValue Add = DAG.getNode(ISD::FADD, sdl, 4933 getValue(I.getArgOperand(0)).getValueType(), 4934 Mul, 4935 getValue(I.getArgOperand(2))); 4936 setValue(&I, Add); 4937 } 4938 return 0; 4939 } 4940 case Intrinsic::convert_to_fp16: 4941 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, sdl, 4942 MVT::i16, getValue(I.getArgOperand(0)))); 4943 return 0; 4944 case Intrinsic::convert_from_fp16: 4945 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, sdl, 4946 MVT::f32, getValue(I.getArgOperand(0)))); 4947 return 0; 4948 case Intrinsic::pcmarker: { 4949 SDValue Tmp = getValue(I.getArgOperand(0)); 4950 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp)); 4951 return 0; 4952 } 4953 case Intrinsic::readcyclecounter: { 4954 SDValue Op = getRoot(); 4955 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl, 4956 DAG.getVTList(MVT::i64, MVT::Other), 4957 &Op, 1); 4958 setValue(&I, Res); 4959 DAG.setRoot(Res.getValue(1)); 4960 return 0; 4961 } 4962 case Intrinsic::bswap: 4963 setValue(&I, DAG.getNode(ISD::BSWAP, sdl, 4964 getValue(I.getArgOperand(0)).getValueType(), 4965 getValue(I.getArgOperand(0)))); 4966 return 0; 4967 case Intrinsic::cttz: { 4968 SDValue Arg = getValue(I.getArgOperand(0)); 4969 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4970 EVT Ty = Arg.getValueType(); 4971 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 4972 sdl, Ty, Arg)); 4973 return 0; 4974 } 4975 case Intrinsic::ctlz: { 4976 SDValue Arg = getValue(I.getArgOperand(0)); 4977 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4978 EVT Ty = Arg.getValueType(); 4979 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 4980 sdl, Ty, Arg)); 4981 return 0; 4982 } 4983 case Intrinsic::ctpop: { 4984 SDValue Arg = getValue(I.getArgOperand(0)); 4985 EVT Ty = Arg.getValueType(); 4986 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg)); 4987 return 0; 4988 } 4989 case Intrinsic::stacksave: { 4990 SDValue Op = getRoot(); 4991 Res = DAG.getNode(ISD::STACKSAVE, sdl, 4992 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4993 setValue(&I, Res); 4994 DAG.setRoot(Res.getValue(1)); 4995 return 0; 4996 } 4997 case Intrinsic::stackrestore: { 4998 Res = getValue(I.getArgOperand(0)); 4999 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res)); 5000 return 0; 5001 } 5002 case Intrinsic::stackprotector: { 5003 // Emit code into the DAG to store the stack guard onto the stack. 5004 MachineFunction &MF = DAG.getMachineFunction(); 5005 MachineFrameInfo *MFI = MF.getFrameInfo(); 5006 EVT PtrTy = TLI.getPointerTy(); 5007 5008 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 5009 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 5010 5011 int FI = FuncInfo.StaticAllocaMap[Slot]; 5012 MFI->setStackProtectorIndex(FI); 5013 5014 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5015 5016 // Store the stack protector onto the stack. 5017 Res = DAG.getStore(getRoot(), sdl, Src, FIN, 5018 MachinePointerInfo::getFixedStack(FI), 5019 true, false, 0); 5020 setValue(&I, Res); 5021 DAG.setRoot(Res); 5022 return 0; 5023 } 5024 case Intrinsic::objectsize: { 5025 // If we don't know by now, we're never going to know. 5026 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5027 5028 assert(CI && "Non-constant type in __builtin_object_size?"); 5029 5030 SDValue Arg = getValue(I.getCalledValue()); 5031 EVT Ty = Arg.getValueType(); 5032 5033 if (CI->isZero()) 5034 Res = DAG.getConstant(-1ULL, Ty); 5035 else 5036 Res = DAG.getConstant(0, Ty); 5037 5038 setValue(&I, Res); 5039 return 0; 5040 } 5041 case Intrinsic::annotation: 5042 case Intrinsic::ptr_annotation: 5043 // Drop the intrinsic, but forward the value 5044 setValue(&I, getValue(I.getOperand(0))); 5045 return 0; 5046 case Intrinsic::var_annotation: 5047 // Discard annotate attributes 5048 return 0; 5049 5050 case Intrinsic::init_trampoline: { 5051 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5052 5053 SDValue Ops[6]; 5054 Ops[0] = getRoot(); 5055 Ops[1] = getValue(I.getArgOperand(0)); 5056 Ops[2] = getValue(I.getArgOperand(1)); 5057 Ops[3] = getValue(I.getArgOperand(2)); 5058 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5059 Ops[5] = DAG.getSrcValue(F); 5060 5061 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops, 6); 5062 5063 DAG.setRoot(Res); 5064 return 0; 5065 } 5066 case Intrinsic::adjust_trampoline: { 5067 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl, 5068 TLI.getPointerTy(), 5069 getValue(I.getArgOperand(0)))); 5070 return 0; 5071 } 5072 case Intrinsic::gcroot: 5073 if (GFI) { 5074 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); 5075 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5076 5077 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5078 GFI->addStackRoot(FI->getIndex(), TypeMap); 5079 } 5080 return 0; 5081 case Intrinsic::gcread: 5082 case Intrinsic::gcwrite: 5083 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5084 case Intrinsic::flt_rounds: 5085 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32)); 5086 return 0; 5087 5088 case Intrinsic::expect: { 5089 // Just replace __builtin_expect(exp, c) with EXP. 5090 setValue(&I, getValue(I.getArgOperand(0))); 5091 return 0; 5092 } 5093 5094 case Intrinsic::debugtrap: 5095 case Intrinsic::trap: { 5096 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5097 if (TrapFuncName.empty()) { 5098 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ? 5099 ISD::TRAP : ISD::DEBUGTRAP; 5100 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot())); 5101 return 0; 5102 } 5103 TargetLowering::ArgListTy Args; 5104 TargetLowering:: 5105 CallLoweringInfo CLI(getRoot(), I.getType(), 5106 false, false, false, false, 0, CallingConv::C, 5107 /*isTailCall=*/false, 5108 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 5109 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5110 Args, DAG, sdl); 5111 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI); 5112 DAG.setRoot(Result.second); 5113 return 0; 5114 } 5115 5116 case Intrinsic::uadd_with_overflow: 5117 case Intrinsic::sadd_with_overflow: 5118 case Intrinsic::usub_with_overflow: 5119 case Intrinsic::ssub_with_overflow: 5120 case Intrinsic::umul_with_overflow: 5121 case Intrinsic::smul_with_overflow: { 5122 ISD::NodeType Op; 5123 switch (Intrinsic) { 5124 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 5125 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; 5126 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; 5127 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; 5128 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; 5129 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; 5130 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; 5131 } 5132 SDValue Op1 = getValue(I.getArgOperand(0)); 5133 SDValue Op2 = getValue(I.getArgOperand(1)); 5134 5135 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 5136 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2)); 5137 return 0; 5138 } 5139 case Intrinsic::prefetch: { 5140 SDValue Ops[5]; 5141 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5142 Ops[0] = getRoot(); 5143 Ops[1] = getValue(I.getArgOperand(0)); 5144 Ops[2] = getValue(I.getArgOperand(1)); 5145 Ops[3] = getValue(I.getArgOperand(2)); 5146 Ops[4] = getValue(I.getArgOperand(3)); 5147 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl, 5148 DAG.getVTList(MVT::Other), 5149 &Ops[0], 5, 5150 EVT::getIntegerVT(*Context, 8), 5151 MachinePointerInfo(I.getArgOperand(0)), 5152 0, /* align */ 5153 false, /* volatile */ 5154 rw==0, /* read */ 5155 rw==1)); /* write */ 5156 return 0; 5157 } 5158 case Intrinsic::lifetime_start: 5159 case Intrinsic::lifetime_end: { 5160 bool IsStart = (Intrinsic == Intrinsic::lifetime_start); 5161 // Stack coloring is not enabled in O0, discard region information. 5162 if (TM.getOptLevel() == CodeGenOpt::None) 5163 return 0; 5164 5165 SmallVector<Value *, 4> Allocas; 5166 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD); 5167 5168 for (SmallVector<Value*, 4>::iterator Object = Allocas.begin(), 5169 E = Allocas.end(); Object != E; ++Object) { 5170 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object); 5171 5172 // Could not find an Alloca. 5173 if (!LifetimeObject) 5174 continue; 5175 5176 int FI = FuncInfo.StaticAllocaMap[LifetimeObject]; 5177 5178 SDValue Ops[2]; 5179 Ops[0] = getRoot(); 5180 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true); 5181 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END); 5182 5183 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2); 5184 DAG.setRoot(Res); 5185 } 5186 return 0; 5187 } 5188 case Intrinsic::invariant_start: 5189 // Discard region information. 5190 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5191 return 0; 5192 case Intrinsic::invariant_end: 5193 // Discard region information. 5194 return 0; 5195 case Intrinsic::donothing: 5196 // ignore 5197 return 0; 5198 } 5199} 5200 5201void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5202 bool isTailCall, 5203 MachineBasicBlock *LandingPad) { 5204 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5205 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5206 Type *RetTy = FTy->getReturnType(); 5207 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5208 MCSymbol *BeginLabel = 0; 5209 5210 TargetLowering::ArgListTy Args; 5211 TargetLowering::ArgListEntry Entry; 5212 Args.reserve(CS.arg_size()); 5213 5214 // Check whether the function can return without sret-demotion. 5215 SmallVector<ISD::OutputArg, 4> Outs; 5216 GetReturnInfo(RetTy, CS.getAttributes(), Outs, TLI); 5217 5218 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5219 DAG.getMachineFunction(), 5220 FTy->isVarArg(), Outs, 5221 FTy->getContext()); 5222 5223 SDValue DemoteStackSlot; 5224 int DemoteStackIdx = -100; 5225 5226 if (!CanLowerReturn) { 5227 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize( 5228 FTy->getReturnType()); 5229 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment( 5230 FTy->getReturnType()); 5231 MachineFunction &MF = DAG.getMachineFunction(); 5232 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5233 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5234 5235 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5236 Entry.Node = DemoteStackSlot; 5237 Entry.Ty = StackSlotPtrType; 5238 Entry.isSExt = false; 5239 Entry.isZExt = false; 5240 Entry.isInReg = false; 5241 Entry.isSRet = true; 5242 Entry.isNest = false; 5243 Entry.isByVal = false; 5244 Entry.isReturned = false; 5245 Entry.Alignment = Align; 5246 Args.push_back(Entry); 5247 RetTy = Type::getVoidTy(FTy->getContext()); 5248 } 5249 5250 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5251 i != e; ++i) { 5252 const Value *V = *i; 5253 5254 // Skip empty types 5255 if (V->getType()->isEmptyTy()) 5256 continue; 5257 5258 SDValue ArgNode = getValue(V); 5259 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5260 5261 unsigned attrInd = i - CS.arg_begin() + 1; 5262 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5263 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5264 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5265 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5266 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5267 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5268 Entry.isReturned = CS.paramHasAttr(attrInd, Attribute::Returned); 5269 Entry.Alignment = CS.getParamAlignment(attrInd); 5270 Args.push_back(Entry); 5271 } 5272 5273 if (LandingPad) { 5274 // Insert a label before the invoke call to mark the try range. This can be 5275 // used to detect deletion of the invoke via the MachineModuleInfo. 5276 BeginLabel = MMI.getContext().CreateTempSymbol(); 5277 5278 // For SjLj, keep track of which landing pads go with which invokes 5279 // so as to maintain the ordering of pads in the LSDA. 5280 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5281 if (CallSiteIndex) { 5282 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5283 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5284 5285 // Now that the call site is handled, stop tracking it. 5286 MMI.setCurrentCallSite(0); 5287 } 5288 5289 // Both PendingLoads and PendingExports must be flushed here; 5290 // this call might not return. 5291 (void)getRoot(); 5292 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel)); 5293 } 5294 5295 // Check if target-independent constraints permit a tail call here. 5296 // Target-dependent constraints are checked within TLI.LowerCallTo. 5297 if (isTailCall && !isInTailCallPosition(CS, TLI)) 5298 isTailCall = false; 5299 5300 TargetLowering:: 5301 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG, 5302 getCurSDLoc(), CS); 5303 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI); 5304 assert((isTailCall || Result.second.getNode()) && 5305 "Non-null chain expected with non-tail call!"); 5306 assert((Result.second.getNode() || !Result.first.getNode()) && 5307 "Null value expected with tail call!"); 5308 if (Result.first.getNode()) { 5309 setValue(CS.getInstruction(), Result.first); 5310 } else if (!CanLowerReturn && Result.second.getNode()) { 5311 // The instruction result is the result of loading from the 5312 // hidden sret parameter. 5313 SmallVector<EVT, 1> PVTs; 5314 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5315 5316 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5317 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5318 EVT PtrVT = PVTs[0]; 5319 5320 SmallVector<EVT, 4> RetTys; 5321 SmallVector<uint64_t, 4> Offsets; 5322 RetTy = FTy->getReturnType(); 5323 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets); 5324 5325 unsigned NumValues = RetTys.size(); 5326 SmallVector<SDValue, 4> Values(NumValues); 5327 SmallVector<SDValue, 4> Chains(NumValues); 5328 5329 for (unsigned i = 0; i < NumValues; ++i) { 5330 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, 5331 DemoteStackSlot, 5332 DAG.getConstant(Offsets[i], PtrVT)); 5333 SDValue L = DAG.getLoad(RetTys[i], getCurSDLoc(), Result.second, Add, 5334 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5335 false, false, false, 1); 5336 Values[i] = L; 5337 Chains[i] = L.getValue(1); 5338 } 5339 5340 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 5341 MVT::Other, &Chains[0], NumValues); 5342 PendingLoads.push_back(Chain); 5343 5344 setValue(CS.getInstruction(), 5345 DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 5346 DAG.getVTList(&RetTys[0], RetTys.size()), 5347 &Values[0], Values.size())); 5348 } 5349 5350 // Assign order to nodes here. If the call does not produce a result, it won't 5351 // be mapped to a SDNode and visit() will not assign it an order number. 5352 if (!Result.second.getNode()) { 5353 // As a special case, a null chain means that a tail call has been emitted and 5354 // the DAG root is already updated. 5355 HasTailCall = true; 5356 ++SDNodeOrder; 5357 AssignOrderingToNode(DAG.getRoot().getNode()); 5358 } else { 5359 DAG.setRoot(Result.second); 5360 ++SDNodeOrder; 5361 AssignOrderingToNode(Result.second.getNode()); 5362 } 5363 5364 if (LandingPad) { 5365 // Insert a label at the end of the invoke call to mark the try range. This 5366 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5367 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5368 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel)); 5369 5370 // Inform MachineModuleInfo of range. 5371 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5372 } 5373} 5374 5375/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5376/// value is equal or not-equal to zero. 5377static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5378 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5379 UI != E; ++UI) { 5380 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5381 if (IC->isEquality()) 5382 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5383 if (C->isNullValue()) 5384 continue; 5385 // Unknown instruction. 5386 return false; 5387 } 5388 return true; 5389} 5390 5391static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5392 Type *LoadTy, 5393 SelectionDAGBuilder &Builder) { 5394 5395 // Check to see if this load can be trivially constant folded, e.g. if the 5396 // input is from a string literal. 5397 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5398 // Cast pointer to the type we really want to load. 5399 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5400 PointerType::getUnqual(LoadTy)); 5401 5402 if (const Constant *LoadCst = 5403 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5404 Builder.TD)) 5405 return Builder.getValue(LoadCst); 5406 } 5407 5408 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5409 // still constant memory, the input chain can be the entry node. 5410 SDValue Root; 5411 bool ConstantMemory = false; 5412 5413 // Do not serialize (non-volatile) loads of constant memory with anything. 5414 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5415 Root = Builder.DAG.getEntryNode(); 5416 ConstantMemory = true; 5417 } else { 5418 // Do not serialize non-volatile loads against each other. 5419 Root = Builder.DAG.getRoot(); 5420 } 5421 5422 SDValue Ptr = Builder.getValue(PtrVal); 5423 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, 5424 Ptr, MachinePointerInfo(PtrVal), 5425 false /*volatile*/, 5426 false /*nontemporal*/, 5427 false /*isinvariant*/, 1 /* align=1 */); 5428 5429 if (!ConstantMemory) 5430 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5431 return LoadVal; 5432} 5433 5434 5435/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5436/// If so, return true and lower it, otherwise return false and it will be 5437/// lowered like a normal call. 5438bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5439 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5440 if (I.getNumArgOperands() != 3) 5441 return false; 5442 5443 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5444 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5445 !I.getArgOperand(2)->getType()->isIntegerTy() || 5446 !I.getType()->isIntegerTy()) 5447 return false; 5448 5449 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5450 5451 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5452 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5453 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5454 bool ActuallyDoIt = true; 5455 MVT LoadVT; 5456 Type *LoadTy; 5457 switch (Size->getZExtValue()) { 5458 default: 5459 LoadVT = MVT::Other; 5460 LoadTy = 0; 5461 ActuallyDoIt = false; 5462 break; 5463 case 2: 5464 LoadVT = MVT::i16; 5465 LoadTy = Type::getInt16Ty(Size->getContext()); 5466 break; 5467 case 4: 5468 LoadVT = MVT::i32; 5469 LoadTy = Type::getInt32Ty(Size->getContext()); 5470 break; 5471 case 8: 5472 LoadVT = MVT::i64; 5473 LoadTy = Type::getInt64Ty(Size->getContext()); 5474 break; 5475 /* 5476 case 16: 5477 LoadVT = MVT::v4i32; 5478 LoadTy = Type::getInt32Ty(Size->getContext()); 5479 LoadTy = VectorType::get(LoadTy, 4); 5480 break; 5481 */ 5482 } 5483 5484 // This turns into unaligned loads. We only do this if the target natively 5485 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5486 // we'll only produce a small number of byte loads. 5487 5488 // Require that we can find a legal MVT, and only do this if the target 5489 // supports unaligned loads of that type. Expanding into byte loads would 5490 // bloat the code. 5491 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5492 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5493 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5494 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5495 ActuallyDoIt = false; 5496 } 5497 5498 if (ActuallyDoIt) { 5499 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5500 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5501 5502 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal, 5503 ISD::SETNE); 5504 EVT CallVT = TLI.getValueType(I.getType(), true); 5505 setValue(&I, DAG.getZExtOrTrunc(Res, getCurSDLoc(), CallVT)); 5506 return true; 5507 } 5508 } 5509 5510 5511 return false; 5512} 5513 5514/// visitUnaryFloatCall - If a call instruction is a unary floating-point 5515/// operation (as expected), translate it to an SDNode with the specified opcode 5516/// and return true. 5517bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I, 5518 unsigned Opcode) { 5519 // Sanity check that it really is a unary floating-point call. 5520 if (I.getNumArgOperands() != 1 || 5521 !I.getArgOperand(0)->getType()->isFloatingPointTy() || 5522 I.getType() != I.getArgOperand(0)->getType() || 5523 !I.onlyReadsMemory()) 5524 return false; 5525 5526 SDValue Tmp = getValue(I.getArgOperand(0)); 5527 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp)); 5528 return true; 5529} 5530 5531void SelectionDAGBuilder::visitCall(const CallInst &I) { 5532 // Handle inline assembly differently. 5533 if (isa<InlineAsm>(I.getCalledValue())) { 5534 visitInlineAsm(&I); 5535 return; 5536 } 5537 5538 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5539 ComputeUsesVAFloatArgument(I, &MMI); 5540 5541 const char *RenameFn = 0; 5542 if (Function *F = I.getCalledFunction()) { 5543 if (F->isDeclaration()) { 5544 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5545 if (unsigned IID = II->getIntrinsicID(F)) { 5546 RenameFn = visitIntrinsicCall(I, IID); 5547 if (!RenameFn) 5548 return; 5549 } 5550 } 5551 if (unsigned IID = F->getIntrinsicID()) { 5552 RenameFn = visitIntrinsicCall(I, IID); 5553 if (!RenameFn) 5554 return; 5555 } 5556 } 5557 5558 // Check for well-known libc/libm calls. If the function is internal, it 5559 // can't be a library call. 5560 LibFunc::Func Func; 5561 if (!F->hasLocalLinkage() && F->hasName() && 5562 LibInfo->getLibFunc(F->getName(), Func) && 5563 LibInfo->hasOptimizedCodeGen(Func)) { 5564 switch (Func) { 5565 default: break; 5566 case LibFunc::copysign: 5567 case LibFunc::copysignf: 5568 case LibFunc::copysignl: 5569 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5570 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5571 I.getType() == I.getArgOperand(0)->getType() && 5572 I.getType() == I.getArgOperand(1)->getType() && 5573 I.onlyReadsMemory()) { 5574 SDValue LHS = getValue(I.getArgOperand(0)); 5575 SDValue RHS = getValue(I.getArgOperand(1)); 5576 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(), 5577 LHS.getValueType(), LHS, RHS)); 5578 return; 5579 } 5580 break; 5581 case LibFunc::fabs: 5582 case LibFunc::fabsf: 5583 case LibFunc::fabsl: 5584 if (visitUnaryFloatCall(I, ISD::FABS)) 5585 return; 5586 break; 5587 case LibFunc::sin: 5588 case LibFunc::sinf: 5589 case LibFunc::sinl: 5590 if (visitUnaryFloatCall(I, ISD::FSIN)) 5591 return; 5592 break; 5593 case LibFunc::cos: 5594 case LibFunc::cosf: 5595 case LibFunc::cosl: 5596 if (visitUnaryFloatCall(I, ISD::FCOS)) 5597 return; 5598 break; 5599 case LibFunc::sqrt: 5600 case LibFunc::sqrtf: 5601 case LibFunc::sqrtl: 5602 if (visitUnaryFloatCall(I, ISD::FSQRT)) 5603 return; 5604 break; 5605 case LibFunc::floor: 5606 case LibFunc::floorf: 5607 case LibFunc::floorl: 5608 if (visitUnaryFloatCall(I, ISD::FFLOOR)) 5609 return; 5610 break; 5611 case LibFunc::nearbyint: 5612 case LibFunc::nearbyintf: 5613 case LibFunc::nearbyintl: 5614 if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) 5615 return; 5616 break; 5617 case LibFunc::ceil: 5618 case LibFunc::ceilf: 5619 case LibFunc::ceill: 5620 if (visitUnaryFloatCall(I, ISD::FCEIL)) 5621 return; 5622 break; 5623 case LibFunc::rint: 5624 case LibFunc::rintf: 5625 case LibFunc::rintl: 5626 if (visitUnaryFloatCall(I, ISD::FRINT)) 5627 return; 5628 break; 5629 case LibFunc::trunc: 5630 case LibFunc::truncf: 5631 case LibFunc::truncl: 5632 if (visitUnaryFloatCall(I, ISD::FTRUNC)) 5633 return; 5634 break; 5635 case LibFunc::log2: 5636 case LibFunc::log2f: 5637 case LibFunc::log2l: 5638 if (visitUnaryFloatCall(I, ISD::FLOG2)) 5639 return; 5640 break; 5641 case LibFunc::exp2: 5642 case LibFunc::exp2f: 5643 case LibFunc::exp2l: 5644 if (visitUnaryFloatCall(I, ISD::FEXP2)) 5645 return; 5646 break; 5647 case LibFunc::memcmp: 5648 if (visitMemCmpCall(I)) 5649 return; 5650 break; 5651 } 5652 } 5653 } 5654 5655 SDValue Callee; 5656 if (!RenameFn) 5657 Callee = getValue(I.getCalledValue()); 5658 else 5659 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5660 5661 // Check if we can potentially perform a tail call. More detailed checking is 5662 // be done within LowerCallTo, after more information about the call is known. 5663 LowerCallTo(&I, Callee, I.isTailCall()); 5664} 5665 5666namespace { 5667 5668/// AsmOperandInfo - This contains information for each constraint that we are 5669/// lowering. 5670class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5671public: 5672 /// CallOperand - If this is the result output operand or a clobber 5673 /// this is null, otherwise it is the incoming operand to the CallInst. 5674 /// This gets modified as the asm is processed. 5675 SDValue CallOperand; 5676 5677 /// AssignedRegs - If this is a register or register class operand, this 5678 /// contains the set of register corresponding to the operand. 5679 RegsForValue AssignedRegs; 5680 5681 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5682 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5683 } 5684 5685 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5686 /// corresponds to. If there is no Value* for this operand, it returns 5687 /// MVT::Other. 5688 EVT getCallOperandValEVT(LLVMContext &Context, 5689 const TargetLowering &TLI, 5690 const DataLayout *TD) const { 5691 if (CallOperandVal == 0) return MVT::Other; 5692 5693 if (isa<BasicBlock>(CallOperandVal)) 5694 return TLI.getPointerTy(); 5695 5696 llvm::Type *OpTy = CallOperandVal->getType(); 5697 5698 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5699 // If this is an indirect operand, the operand is a pointer to the 5700 // accessed type. 5701 if (isIndirect) { 5702 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5703 if (!PtrTy) 5704 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5705 OpTy = PtrTy->getElementType(); 5706 } 5707 5708 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5709 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5710 if (STy->getNumElements() == 1) 5711 OpTy = STy->getElementType(0); 5712 5713 // If OpTy is not a single value, it may be a struct/union that we 5714 // can tile with integers. 5715 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5716 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5717 switch (BitSize) { 5718 default: break; 5719 case 1: 5720 case 8: 5721 case 16: 5722 case 32: 5723 case 64: 5724 case 128: 5725 OpTy = IntegerType::get(Context, BitSize); 5726 break; 5727 } 5728 } 5729 5730 return TLI.getValueType(OpTy, true); 5731 } 5732}; 5733 5734typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5735 5736} // end anonymous namespace 5737 5738/// GetRegistersForValue - Assign registers (virtual or physical) for the 5739/// specified operand. We prefer to assign virtual registers, to allow the 5740/// register allocator to handle the assignment process. However, if the asm 5741/// uses features that we can't model on machineinstrs, we have SDISel do the 5742/// allocation. This produces generally horrible, but correct, code. 5743/// 5744/// OpInfo describes the operand. 5745/// 5746static void GetRegistersForValue(SelectionDAG &DAG, 5747 const TargetLowering &TLI, 5748 SDLoc DL, 5749 SDISelAsmOperandInfo &OpInfo) { 5750 LLVMContext &Context = *DAG.getContext(); 5751 5752 MachineFunction &MF = DAG.getMachineFunction(); 5753 SmallVector<unsigned, 4> Regs; 5754 5755 // If this is a constraint for a single physreg, or a constraint for a 5756 // register class, find it. 5757 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5758 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5759 OpInfo.ConstraintVT); 5760 5761 unsigned NumRegs = 1; 5762 if (OpInfo.ConstraintVT != MVT::Other) { 5763 // If this is a FP input in an integer register (or visa versa) insert a bit 5764 // cast of the input value. More generally, handle any case where the input 5765 // value disagrees with the register class we plan to stick this in. 5766 if (OpInfo.Type == InlineAsm::isInput && 5767 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5768 // Try to convert to the first EVT that the reg class contains. If the 5769 // types are identical size, use a bitcast to convert (e.g. two differing 5770 // vector types). 5771 MVT RegVT = *PhysReg.second->vt_begin(); 5772 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5773 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5774 RegVT, OpInfo.CallOperand); 5775 OpInfo.ConstraintVT = RegVT; 5776 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5777 // If the input is a FP value and we want it in FP registers, do a 5778 // bitcast to the corresponding integer type. This turns an f64 value 5779 // into i64, which can be passed with two i32 values on a 32-bit 5780 // machine. 5781 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); 5782 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5783 RegVT, OpInfo.CallOperand); 5784 OpInfo.ConstraintVT = RegVT; 5785 } 5786 } 5787 5788 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5789 } 5790 5791 MVT RegVT; 5792 EVT ValueVT = OpInfo.ConstraintVT; 5793 5794 // If this is a constraint for a specific physical register, like {r17}, 5795 // assign it now. 5796 if (unsigned AssignedReg = PhysReg.first) { 5797 const TargetRegisterClass *RC = PhysReg.second; 5798 if (OpInfo.ConstraintVT == MVT::Other) 5799 ValueVT = *RC->vt_begin(); 5800 5801 // Get the actual register value type. This is important, because the user 5802 // may have asked for (e.g.) the AX register in i32 type. We need to 5803 // remember that AX is actually i16 to get the right extension. 5804 RegVT = *RC->vt_begin(); 5805 5806 // This is a explicit reference to a physical register. 5807 Regs.push_back(AssignedReg); 5808 5809 // If this is an expanded reference, add the rest of the regs to Regs. 5810 if (NumRegs != 1) { 5811 TargetRegisterClass::iterator I = RC->begin(); 5812 for (; *I != AssignedReg; ++I) 5813 assert(I != RC->end() && "Didn't find reg!"); 5814 5815 // Already added the first reg. 5816 --NumRegs; ++I; 5817 for (; NumRegs; --NumRegs, ++I) { 5818 assert(I != RC->end() && "Ran out of registers to allocate!"); 5819 Regs.push_back(*I); 5820 } 5821 } 5822 5823 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5824 return; 5825 } 5826 5827 // Otherwise, if this was a reference to an LLVM register class, create vregs 5828 // for this reference. 5829 if (const TargetRegisterClass *RC = PhysReg.second) { 5830 RegVT = *RC->vt_begin(); 5831 if (OpInfo.ConstraintVT == MVT::Other) 5832 ValueVT = RegVT; 5833 5834 // Create the appropriate number of virtual registers. 5835 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5836 for (; NumRegs; --NumRegs) 5837 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5838 5839 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5840 return; 5841 } 5842 5843 // Otherwise, we couldn't allocate enough registers for this. 5844} 5845 5846/// visitInlineAsm - Handle a call to an InlineAsm object. 5847/// 5848void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5849 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5850 5851 /// ConstraintOperands - Information about all of the constraints. 5852 SDISelAsmOperandInfoVector ConstraintOperands; 5853 5854 TargetLowering::AsmOperandInfoVector 5855 TargetConstraints = TLI.ParseConstraints(CS); 5856 5857 bool hasMemory = false; 5858 5859 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5860 unsigned ResNo = 0; // ResNo - The result number of the next output. 5861 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5862 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5863 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5864 5865 MVT OpVT = MVT::Other; 5866 5867 // Compute the value type for each operand. 5868 switch (OpInfo.Type) { 5869 case InlineAsm::isOutput: 5870 // Indirect outputs just consume an argument. 5871 if (OpInfo.isIndirect) { 5872 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5873 break; 5874 } 5875 5876 // The return value of the call is this value. As such, there is no 5877 // corresponding argument. 5878 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5879 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5880 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo)); 5881 } else { 5882 assert(ResNo == 0 && "Asm only has one result!"); 5883 OpVT = TLI.getSimpleValueType(CS.getType()); 5884 } 5885 ++ResNo; 5886 break; 5887 case InlineAsm::isInput: 5888 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5889 break; 5890 case InlineAsm::isClobber: 5891 // Nothing to do. 5892 break; 5893 } 5894 5895 // If this is an input or an indirect output, process the call argument. 5896 // BasicBlocks are labels, currently appearing only in asm's. 5897 if (OpInfo.CallOperandVal) { 5898 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5899 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5900 } else { 5901 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5902 } 5903 5904 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD). 5905 getSimpleVT(); 5906 } 5907 5908 OpInfo.ConstraintVT = OpVT; 5909 5910 // Indirect operand accesses access memory. 5911 if (OpInfo.isIndirect) 5912 hasMemory = true; 5913 else { 5914 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5915 TargetLowering::ConstraintType 5916 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5917 if (CType == TargetLowering::C_Memory) { 5918 hasMemory = true; 5919 break; 5920 } 5921 } 5922 } 5923 } 5924 5925 SDValue Chain, Flag; 5926 5927 // We won't need to flush pending loads if this asm doesn't touch 5928 // memory and is nonvolatile. 5929 if (hasMemory || IA->hasSideEffects()) 5930 Chain = getRoot(); 5931 else 5932 Chain = DAG.getRoot(); 5933 5934 // Second pass over the constraints: compute which constraint option to use 5935 // and assign registers to constraints that want a specific physreg. 5936 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5937 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5938 5939 // If this is an output operand with a matching input operand, look up the 5940 // matching input. If their types mismatch, e.g. one is an integer, the 5941 // other is floating point, or their sizes are different, flag it as an 5942 // error. 5943 if (OpInfo.hasMatchingInput()) { 5944 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5945 5946 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5947 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5948 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5949 OpInfo.ConstraintVT); 5950 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5951 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 5952 Input.ConstraintVT); 5953 if ((OpInfo.ConstraintVT.isInteger() != 5954 Input.ConstraintVT.isInteger()) || 5955 (MatchRC.second != InputRC.second)) { 5956 report_fatal_error("Unsupported asm: input constraint" 5957 " with a matching output constraint of" 5958 " incompatible type!"); 5959 } 5960 Input.ConstraintVT = OpInfo.ConstraintVT; 5961 } 5962 } 5963 5964 // Compute the constraint code and ConstraintType to use. 5965 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5966 5967 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5968 OpInfo.Type == InlineAsm::isClobber) 5969 continue; 5970 5971 // If this is a memory input, and if the operand is not indirect, do what we 5972 // need to to provide an address for the memory input. 5973 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5974 !OpInfo.isIndirect) { 5975 assert((OpInfo.isMultipleAlternative || 5976 (OpInfo.Type == InlineAsm::isInput)) && 5977 "Can only indirectify direct input operands!"); 5978 5979 // Memory operands really want the address of the value. If we don't have 5980 // an indirect input, put it in the constpool if we can, otherwise spill 5981 // it to a stack slot. 5982 // TODO: This isn't quite right. We need to handle these according to 5983 // the addressing mode that the constraint wants. Also, this may take 5984 // an additional register for the computation and we don't want that 5985 // either. 5986 5987 // If the operand is a float, integer, or vector constant, spill to a 5988 // constant pool entry to get its address. 5989 const Value *OpVal = OpInfo.CallOperandVal; 5990 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5991 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { 5992 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5993 TLI.getPointerTy()); 5994 } else { 5995 // Otherwise, create a stack slot and emit a store to it before the 5996 // asm. 5997 Type *Ty = OpVal->getType(); 5998 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty); 5999 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty); 6000 MachineFunction &MF = DAG.getMachineFunction(); 6001 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 6002 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 6003 Chain = DAG.getStore(Chain, getCurSDLoc(), 6004 OpInfo.CallOperand, StackSlot, 6005 MachinePointerInfo::getFixedStack(SSFI), 6006 false, false, 0); 6007 OpInfo.CallOperand = StackSlot; 6008 } 6009 6010 // There is no longer a Value* corresponding to this operand. 6011 OpInfo.CallOperandVal = 0; 6012 6013 // It is now an indirect operand. 6014 OpInfo.isIndirect = true; 6015 } 6016 6017 // If this constraint is for a specific register, allocate it before 6018 // anything else. 6019 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6020 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo); 6021 } 6022 6023 // Second pass - Loop over all of the operands, assigning virtual or physregs 6024 // to register class operands. 6025 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6026 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6027 6028 // C_Register operands have already been allocated, Other/Memory don't need 6029 // to be. 6030 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6031 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo); 6032 } 6033 6034 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6035 std::vector<SDValue> AsmNodeOperands; 6036 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6037 AsmNodeOperands.push_back( 6038 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6039 TLI.getPointerTy())); 6040 6041 // If we have a !srcloc metadata node associated with it, we want to attach 6042 // this to the ultimately generated inline asm machineinstr. To do this, we 6043 // pass in the third operand as this (potentially null) inline asm MDNode. 6044 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6045 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6046 6047 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore 6048 // bits as operand 3. 6049 unsigned ExtraInfo = 0; 6050 if (IA->hasSideEffects()) 6051 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6052 if (IA->isAlignStack()) 6053 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6054 // Set the asm dialect. 6055 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect; 6056 6057 // Determine if this InlineAsm MayLoad or MayStore based on the constraints. 6058 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 6059 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i]; 6060 6061 // Compute the constraint code and ConstraintType to use. 6062 TLI.ComputeConstraintToUse(OpInfo, SDValue()); 6063 6064 // Ideally, we would only check against memory constraints. However, the 6065 // meaning of an other constraint can be target-specific and we can't easily 6066 // reason about it. Therefore, be conservative and set MayLoad/MayStore 6067 // for other constriants as well. 6068 if (OpInfo.ConstraintType == TargetLowering::C_Memory || 6069 OpInfo.ConstraintType == TargetLowering::C_Other) { 6070 if (OpInfo.Type == InlineAsm::isInput) 6071 ExtraInfo |= InlineAsm::Extra_MayLoad; 6072 else if (OpInfo.Type == InlineAsm::isOutput) 6073 ExtraInfo |= InlineAsm::Extra_MayStore; 6074 else if (OpInfo.Type == InlineAsm::isClobber) 6075 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore); 6076 } 6077 } 6078 6079 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6080 TLI.getPointerTy())); 6081 6082 // Loop over all of the inputs, copying the operand values into the 6083 // appropriate registers and processing the output regs. 6084 RegsForValue RetValRegs; 6085 6086 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6087 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6088 6089 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6090 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6091 6092 switch (OpInfo.Type) { 6093 case InlineAsm::isOutput: { 6094 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6095 OpInfo.ConstraintType != TargetLowering::C_Register) { 6096 // Memory output, or 'other' output (e.g. 'X' constraint). 6097 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6098 6099 // Add information to the INLINEASM node to know about this output. 6100 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6101 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6102 TLI.getPointerTy())); 6103 AsmNodeOperands.push_back(OpInfo.CallOperand); 6104 break; 6105 } 6106 6107 // Otherwise, this is a register or register class output. 6108 6109 // Copy the output from the appropriate register. Find a register that 6110 // we can use. 6111 if (OpInfo.AssignedRegs.Regs.empty()) { 6112 LLVMContext &Ctx = *DAG.getContext(); 6113 Ctx.emitError(CS.getInstruction(), 6114 "couldn't allocate output register for constraint '" + 6115 Twine(OpInfo.ConstraintCode) + "'"); 6116 break; 6117 } 6118 6119 // If this is an indirect operand, store through the pointer after the 6120 // asm. 6121 if (OpInfo.isIndirect) { 6122 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6123 OpInfo.CallOperandVal)); 6124 } else { 6125 // This is the result value of the call. 6126 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6127 // Concatenate this output onto the outputs list. 6128 RetValRegs.append(OpInfo.AssignedRegs); 6129 } 6130 6131 // Add information to the INLINEASM node to know that this register is 6132 // set. 6133 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6134 InlineAsm::Kind_RegDefEarlyClobber : 6135 InlineAsm::Kind_RegDef, 6136 false, 6137 0, 6138 DAG, 6139 AsmNodeOperands); 6140 break; 6141 } 6142 case InlineAsm::isInput: { 6143 SDValue InOperandVal = OpInfo.CallOperand; 6144 6145 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6146 // If this is required to match an output register we have already set, 6147 // just use its register. 6148 unsigned OperandNo = OpInfo.getMatchedOperand(); 6149 6150 // Scan until we find the definition we already emitted of this operand. 6151 // When we find it, create a RegsForValue operand. 6152 unsigned CurOp = InlineAsm::Op_FirstOperand; 6153 for (; OperandNo; --OperandNo) { 6154 // Advance to the next operand. 6155 unsigned OpFlag = 6156 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6157 assert((InlineAsm::isRegDefKind(OpFlag) || 6158 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6159 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6160 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6161 } 6162 6163 unsigned OpFlag = 6164 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6165 if (InlineAsm::isRegDefKind(OpFlag) || 6166 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6167 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6168 if (OpInfo.isIndirect) { 6169 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6170 LLVMContext &Ctx = *DAG.getContext(); 6171 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6172 " don't know how to handle tied " 6173 "indirect register inputs"); 6174 report_fatal_error("Cannot handle indirect register inputs!"); 6175 } 6176 6177 RegsForValue MatchedRegs; 6178 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6179 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType(); 6180 MatchedRegs.RegVTs.push_back(RegVT); 6181 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6182 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6183 i != e; ++i) { 6184 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT)) 6185 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC)); 6186 else { 6187 LLVMContext &Ctx = *DAG.getContext(); 6188 Ctx.emitError(CS.getInstruction(), "inline asm error: This value" 6189 " type register class is not natively supported!"); 6190 report_fatal_error("inline asm error: This value type register " 6191 "class is not natively supported!"); 6192 } 6193 } 6194 // Use the produced MatchedRegs object to 6195 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(), 6196 Chain, &Flag, CS.getInstruction()); 6197 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6198 true, OpInfo.getMatchedOperand(), 6199 DAG, AsmNodeOperands); 6200 break; 6201 } 6202 6203 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6204 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6205 "Unexpected number of operands"); 6206 // Add information to the INLINEASM node to know about this input. 6207 // See InlineAsm.h isUseOperandTiedToDef. 6208 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6209 OpInfo.getMatchedOperand()); 6210 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6211 TLI.getPointerTy())); 6212 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6213 break; 6214 } 6215 6216 // Treat indirect 'X' constraint as memory. 6217 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6218 OpInfo.isIndirect) 6219 OpInfo.ConstraintType = TargetLowering::C_Memory; 6220 6221 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6222 std::vector<SDValue> Ops; 6223 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6224 Ops, DAG); 6225 if (Ops.empty()) { 6226 LLVMContext &Ctx = *DAG.getContext(); 6227 Ctx.emitError(CS.getInstruction(), 6228 "invalid operand for inline asm constraint '" + 6229 Twine(OpInfo.ConstraintCode) + "'"); 6230 break; 6231 } 6232 6233 // Add information to the INLINEASM node to know about this input. 6234 unsigned ResOpType = 6235 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6236 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6237 TLI.getPointerTy())); 6238 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6239 break; 6240 } 6241 6242 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6243 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6244 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6245 "Memory operands expect pointer values"); 6246 6247 // Add information to the INLINEASM node to know about this input. 6248 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6249 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6250 TLI.getPointerTy())); 6251 AsmNodeOperands.push_back(InOperandVal); 6252 break; 6253 } 6254 6255 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6256 OpInfo.ConstraintType == TargetLowering::C_Register) && 6257 "Unknown constraint type!"); 6258 6259 // TODO: Support this. 6260 if (OpInfo.isIndirect) { 6261 LLVMContext &Ctx = *DAG.getContext(); 6262 Ctx.emitError(CS.getInstruction(), 6263 "Don't know how to handle indirect register inputs yet " 6264 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'"); 6265 break; 6266 } 6267 6268 // Copy the input into the appropriate registers. 6269 if (OpInfo.AssignedRegs.Regs.empty()) { 6270 LLVMContext &Ctx = *DAG.getContext(); 6271 Ctx.emitError(CS.getInstruction(), 6272 "couldn't allocate input reg for constraint '" + 6273 Twine(OpInfo.ConstraintCode) + "'"); 6274 break; 6275 } 6276 6277 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(), 6278 Chain, &Flag, CS.getInstruction()); 6279 6280 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6281 DAG, AsmNodeOperands); 6282 break; 6283 } 6284 case InlineAsm::isClobber: { 6285 // Add the clobbered value to the operand list, so that the register 6286 // allocator is aware that the physreg got clobbered. 6287 if (!OpInfo.AssignedRegs.Regs.empty()) 6288 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6289 false, 0, DAG, 6290 AsmNodeOperands); 6291 break; 6292 } 6293 } 6294 } 6295 6296 // Finish up input operands. Set the input chain and add the flag last. 6297 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6298 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6299 6300 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(), 6301 DAG.getVTList(MVT::Other, MVT::Glue), 6302 &AsmNodeOperands[0], AsmNodeOperands.size()); 6303 Flag = Chain.getValue(1); 6304 6305 // If this asm returns a register value, copy the result from that register 6306 // and set it as the value of the call. 6307 if (!RetValRegs.Regs.empty()) { 6308 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), 6309 Chain, &Flag, CS.getInstruction()); 6310 6311 // FIXME: Why don't we do this for inline asms with MRVs? 6312 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6313 EVT ResultType = TLI.getValueType(CS.getType()); 6314 6315 // If any of the results of the inline asm is a vector, it may have the 6316 // wrong width/num elts. This can happen for register classes that can 6317 // contain multiple different value types. The preg or vreg allocated may 6318 // not have the same VT as was expected. Convert it to the right type 6319 // with bit_convert. 6320 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6321 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(), 6322 ResultType, Val); 6323 6324 } else if (ResultType != Val.getValueType() && 6325 ResultType.isInteger() && Val.getValueType().isInteger()) { 6326 // If a result value was tied to an input value, the computed result may 6327 // have a wider width than the expected result. Extract the relevant 6328 // portion. 6329 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val); 6330 } 6331 6332 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6333 } 6334 6335 setValue(CS.getInstruction(), Val); 6336 // Don't need to use this as a chain in this case. 6337 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6338 return; 6339 } 6340 6341 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6342 6343 // Process indirect outputs, first output all of the flagged copies out of 6344 // physregs. 6345 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6346 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6347 const Value *Ptr = IndirectStoresToEmit[i].second; 6348 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), 6349 Chain, &Flag, IA); 6350 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6351 } 6352 6353 // Emit the non-flagged stores from the physregs. 6354 SmallVector<SDValue, 8> OutChains; 6355 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6356 SDValue Val = DAG.getStore(Chain, getCurSDLoc(), 6357 StoresToEmit[i].first, 6358 getValue(StoresToEmit[i].second), 6359 MachinePointerInfo(StoresToEmit[i].second), 6360 false, false, 0); 6361 OutChains.push_back(Val); 6362 } 6363 6364 if (!OutChains.empty()) 6365 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, 6366 &OutChains[0], OutChains.size()); 6367 6368 DAG.setRoot(Chain); 6369} 6370 6371void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6372 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(), 6373 MVT::Other, getRoot(), 6374 getValue(I.getArgOperand(0)), 6375 DAG.getSrcValue(I.getArgOperand(0)))); 6376} 6377 6378void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6379 const DataLayout &TD = *TLI.getDataLayout(); 6380 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(), 6381 getRoot(), getValue(I.getOperand(0)), 6382 DAG.getSrcValue(I.getOperand(0)), 6383 TD.getABITypeAlignment(I.getType())); 6384 setValue(&I, V); 6385 DAG.setRoot(V.getValue(1)); 6386} 6387 6388void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6389 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(), 6390 MVT::Other, getRoot(), 6391 getValue(I.getArgOperand(0)), 6392 DAG.getSrcValue(I.getArgOperand(0)))); 6393} 6394 6395void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6396 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(), 6397 MVT::Other, getRoot(), 6398 getValue(I.getArgOperand(0)), 6399 getValue(I.getArgOperand(1)), 6400 DAG.getSrcValue(I.getArgOperand(0)), 6401 DAG.getSrcValue(I.getArgOperand(1)))); 6402} 6403 6404/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6405/// implementation, which just calls LowerCall. 6406/// FIXME: When all targets are 6407/// migrated to using LowerCall, this hook should be integrated into SDISel. 6408std::pair<SDValue, SDValue> 6409TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { 6410 // Handle the incoming return values from the call. 6411 CLI.Ins.clear(); 6412 SmallVector<EVT, 4> RetTys; 6413 ComputeValueVTs(*this, CLI.RetTy, RetTys); 6414 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6415 EVT VT = RetTys[I]; 6416 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6417 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6418 for (unsigned i = 0; i != NumRegs; ++i) { 6419 ISD::InputArg MyFlags; 6420 MyFlags.VT = RegisterVT; 6421 MyFlags.Used = CLI.IsReturnValueUsed; 6422 if (CLI.RetSExt) 6423 MyFlags.Flags.setSExt(); 6424 if (CLI.RetZExt) 6425 MyFlags.Flags.setZExt(); 6426 if (CLI.IsInReg) 6427 MyFlags.Flags.setInReg(); 6428 CLI.Ins.push_back(MyFlags); 6429 } 6430 } 6431 6432 // Handle all of the outgoing arguments. 6433 CLI.Outs.clear(); 6434 CLI.OutVals.clear(); 6435 ArgListTy &Args = CLI.Args; 6436 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6437 SmallVector<EVT, 4> ValueVTs; 6438 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6439 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6440 Value != NumValues; ++Value) { 6441 EVT VT = ValueVTs[Value]; 6442 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); 6443 SDValue Op = SDValue(Args[i].Node.getNode(), 6444 Args[i].Node.getResNo() + Value); 6445 ISD::ArgFlagsTy Flags; 6446 unsigned OriginalAlignment = 6447 getDataLayout()->getABITypeAlignment(ArgTy); 6448 6449 if (Args[i].isZExt) 6450 Flags.setZExt(); 6451 if (Args[i].isSExt) 6452 Flags.setSExt(); 6453 if (Args[i].isInReg) 6454 Flags.setInReg(); 6455 if (Args[i].isSRet) 6456 Flags.setSRet(); 6457 if (Args[i].isByVal) { 6458 Flags.setByVal(); 6459 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6460 Type *ElementTy = Ty->getElementType(); 6461 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy)); 6462 // For ByVal, alignment should come from FE. BE will guess if this 6463 // info is not there but there are cases it cannot get right. 6464 unsigned FrameAlign; 6465 if (Args[i].Alignment) 6466 FrameAlign = Args[i].Alignment; 6467 else 6468 FrameAlign = getByValTypeAlignment(ElementTy); 6469 Flags.setByValAlign(FrameAlign); 6470 } 6471 if (Args[i].isNest) 6472 Flags.setNest(); 6473 Flags.setOrigAlign(OriginalAlignment); 6474 6475 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT); 6476 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT); 6477 SmallVector<SDValue, 4> Parts(NumParts); 6478 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6479 6480 if (Args[i].isSExt) 6481 ExtendKind = ISD::SIGN_EXTEND; 6482 else if (Args[i].isZExt) 6483 ExtendKind = ISD::ZERO_EXTEND; 6484 6485 // Conservatively only handle 'returned' on non-vectors for now 6486 if (Args[i].isReturned && !Op.getValueType().isVector()) { 6487 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues && 6488 "unexpected use of 'returned'"); 6489 // Before passing 'returned' to the target lowering code, ensure that 6490 // either the register MVT and the actual EVT are the same size or that 6491 // the return value and argument are extended in the same way; in these 6492 // cases it's safe to pass the argument register value unchanged as the 6493 // return register value (although it's at the target's option whether 6494 // to do so) 6495 // TODO: allow code generation to take advantage of partially preserved 6496 // registers rather than clobbering the entire register when the 6497 // parameter extension method is not compatible with the return 6498 // extension method 6499 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) || 6500 (ExtendKind != ISD::ANY_EXTEND && 6501 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt)) 6502 Flags.setReturned(); 6503 } 6504 6505 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, 6506 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind); 6507 6508 for (unsigned j = 0; j != NumParts; ++j) { 6509 // if it isn't first piece, alignment must be 1 6510 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6511 i < CLI.NumFixedArgs, 6512 i, j*Parts[j].getValueType().getStoreSize()); 6513 if (NumParts > 1 && j == 0) 6514 MyFlags.Flags.setSplit(); 6515 else if (j != 0) 6516 MyFlags.Flags.setOrigAlign(1); 6517 6518 CLI.Outs.push_back(MyFlags); 6519 CLI.OutVals.push_back(Parts[j]); 6520 } 6521 } 6522 } 6523 6524 SmallVector<SDValue, 4> InVals; 6525 CLI.Chain = LowerCall(CLI, InVals); 6526 6527 // Verify that the target's LowerCall behaved as expected. 6528 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && 6529 "LowerCall didn't return a valid chain!"); 6530 assert((!CLI.IsTailCall || InVals.empty()) && 6531 "LowerCall emitted a return value for a tail call!"); 6532 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && 6533 "LowerCall didn't emit the correct number of values!"); 6534 6535 // For a tail call, the return value is merely live-out and there aren't 6536 // any nodes in the DAG representing it. Return a special value to 6537 // indicate that a tail call has been emitted and no more Instructions 6538 // should be processed in the current block. 6539 if (CLI.IsTailCall) { 6540 CLI.DAG.setRoot(CLI.Chain); 6541 return std::make_pair(SDValue(), SDValue()); 6542 } 6543 6544 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { 6545 assert(InVals[i].getNode() && 6546 "LowerCall emitted a null value!"); 6547 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && 6548 "LowerCall emitted a value with the wrong type!"); 6549 }); 6550 6551 // Collect the legal value parts into potentially illegal values 6552 // that correspond to the original function's return values. 6553 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6554 if (CLI.RetSExt) 6555 AssertOp = ISD::AssertSext; 6556 else if (CLI.RetZExt) 6557 AssertOp = ISD::AssertZext; 6558 SmallVector<SDValue, 4> ReturnValues; 6559 unsigned CurReg = 0; 6560 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6561 EVT VT = RetTys[I]; 6562 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6563 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6564 6565 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], 6566 NumRegs, RegisterVT, VT, NULL, 6567 AssertOp)); 6568 CurReg += NumRegs; 6569 } 6570 6571 // For a function returning void, there is no return value. We can't create 6572 // such a node, so we just return a null return value in that case. In 6573 // that case, nothing will actually look at the value. 6574 if (ReturnValues.empty()) 6575 return std::make_pair(SDValue(), CLI.Chain); 6576 6577 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, 6578 CLI.DAG.getVTList(&RetTys[0], RetTys.size()), 6579 &ReturnValues[0], ReturnValues.size()); 6580 return std::make_pair(Res, CLI.Chain); 6581} 6582 6583void TargetLowering::LowerOperationWrapper(SDNode *N, 6584 SmallVectorImpl<SDValue> &Results, 6585 SelectionDAG &DAG) const { 6586 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6587 if (Res.getNode()) 6588 Results.push_back(Res); 6589} 6590 6591SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6592 llvm_unreachable("LowerOperation not implemented for this target!"); 6593} 6594 6595void 6596SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6597 SDValue Op = getNonRegisterValue(V); 6598 assert((Op.getOpcode() != ISD::CopyFromReg || 6599 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6600 "Copy from a reg to the same reg!"); 6601 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6602 6603 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6604 SDValue Chain = DAG.getEntryNode(); 6605 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, 0, V); 6606 PendingExports.push_back(Chain); 6607} 6608 6609#include "llvm/CodeGen/SelectionDAGISel.h" 6610 6611/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6612/// entry block, return true. This includes arguments used by switches, since 6613/// the switch may expand into multiple basic blocks. 6614static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 6615 // With FastISel active, we may be splitting blocks, so force creation 6616 // of virtual registers for all non-dead arguments. 6617 if (FastISel) 6618 return A->use_empty(); 6619 6620 const BasicBlock *Entry = A->getParent()->begin(); 6621 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6622 UI != E; ++UI) { 6623 const User *U = *UI; 6624 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6625 return false; // Use not in entry block. 6626 } 6627 return true; 6628} 6629 6630void SelectionDAGISel::LowerArguments(const Function &F) { 6631 SelectionDAG &DAG = SDB->DAG; 6632 SDLoc dl = SDB->getCurSDLoc(); 6633 const DataLayout *TD = TLI.getDataLayout(); 6634 SmallVector<ISD::InputArg, 16> Ins; 6635 6636 if (!FuncInfo->CanLowerReturn) { 6637 // Put in an sret pointer parameter before all the other parameters. 6638 SmallVector<EVT, 1> ValueVTs; 6639 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6640 6641 // NOTE: Assuming that a pointer will never break down to more than one VT 6642 // or one register. 6643 ISD::ArgFlagsTy Flags; 6644 Flags.setSRet(); 6645 MVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6646 ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0); 6647 Ins.push_back(RetArg); 6648 } 6649 6650 // Set up the incoming argument description vector. 6651 unsigned Idx = 1; 6652 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6653 I != E; ++I, ++Idx) { 6654 SmallVector<EVT, 4> ValueVTs; 6655 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6656 bool isArgValueUsed = !I->use_empty(); 6657 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6658 Value != NumValues; ++Value) { 6659 EVT VT = ValueVTs[Value]; 6660 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6661 ISD::ArgFlagsTy Flags; 6662 unsigned OriginalAlignment = 6663 TD->getABITypeAlignment(ArgTy); 6664 6665 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt)) 6666 Flags.setZExt(); 6667 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt)) 6668 Flags.setSExt(); 6669 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg)) 6670 Flags.setInReg(); 6671 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet)) 6672 Flags.setSRet(); 6673 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal)) { 6674 Flags.setByVal(); 6675 PointerType *Ty = cast<PointerType>(I->getType()); 6676 Type *ElementTy = Ty->getElementType(); 6677 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6678 // For ByVal, alignment should be passed from FE. BE will guess if 6679 // this info is not there but there are cases it cannot get right. 6680 unsigned FrameAlign; 6681 if (F.getParamAlignment(Idx)) 6682 FrameAlign = F.getParamAlignment(Idx); 6683 else 6684 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6685 Flags.setByValAlign(FrameAlign); 6686 } 6687 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest)) 6688 Flags.setNest(); 6689 Flags.setOrigAlign(OriginalAlignment); 6690 6691 MVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6692 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6693 for (unsigned i = 0; i != NumRegs; ++i) { 6694 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed, 6695 Idx-1, i*RegisterVT.getStoreSize()); 6696 if (NumRegs > 1 && i == 0) 6697 MyFlags.Flags.setSplit(); 6698 // if it isn't first piece, alignment must be 1 6699 else if (i > 0) 6700 MyFlags.Flags.setOrigAlign(1); 6701 Ins.push_back(MyFlags); 6702 } 6703 } 6704 } 6705 6706 // Call the target to set up the argument values. 6707 SmallVector<SDValue, 8> InVals; 6708 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6709 F.isVarArg(), Ins, 6710 dl, DAG, InVals); 6711 6712 // Verify that the target's LowerFormalArguments behaved as expected. 6713 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6714 "LowerFormalArguments didn't return a valid chain!"); 6715 assert(InVals.size() == Ins.size() && 6716 "LowerFormalArguments didn't emit the correct number of values!"); 6717 DEBUG({ 6718 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6719 assert(InVals[i].getNode() && 6720 "LowerFormalArguments emitted a null value!"); 6721 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6722 "LowerFormalArguments emitted a value with the wrong type!"); 6723 } 6724 }); 6725 6726 // Update the DAG with the new chain value resulting from argument lowering. 6727 DAG.setRoot(NewRoot); 6728 6729 // Set up the argument values. 6730 unsigned i = 0; 6731 Idx = 1; 6732 if (!FuncInfo->CanLowerReturn) { 6733 // Create a virtual register for the sret pointer, and put in a copy 6734 // from the sret argument into it. 6735 SmallVector<EVT, 1> ValueVTs; 6736 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6737 MVT VT = ValueVTs[0].getSimpleVT(); 6738 MVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6739 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6740 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6741 RegVT, VT, NULL, AssertOp); 6742 6743 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6744 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6745 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6746 FuncInfo->DemoteRegister = SRetReg; 6747 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), 6748 SRetReg, ArgValue); 6749 DAG.setRoot(NewRoot); 6750 6751 // i indexes lowered arguments. Bump it past the hidden sret argument. 6752 // Idx indexes LLVM arguments. Don't touch it. 6753 ++i; 6754 } 6755 6756 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6757 ++I, ++Idx) { 6758 SmallVector<SDValue, 4> ArgValues; 6759 SmallVector<EVT, 4> ValueVTs; 6760 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6761 unsigned NumValues = ValueVTs.size(); 6762 6763 // If this argument is unused then remember its value. It is used to generate 6764 // debugging information. 6765 if (I->use_empty() && NumValues) { 6766 SDB->setUnusedArgValue(I, InVals[i]); 6767 6768 // Also remember any frame index for use in FastISel. 6769 if (FrameIndexSDNode *FI = 6770 dyn_cast<FrameIndexSDNode>(InVals[i].getNode())) 6771 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6772 } 6773 6774 for (unsigned Val = 0; Val != NumValues; ++Val) { 6775 EVT VT = ValueVTs[Val]; 6776 MVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6777 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6778 6779 if (!I->use_empty()) { 6780 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6781 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt)) 6782 AssertOp = ISD::AssertSext; 6783 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt)) 6784 AssertOp = ISD::AssertZext; 6785 6786 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6787 NumParts, PartVT, VT, 6788 NULL, AssertOp)); 6789 } 6790 6791 i += NumParts; 6792 } 6793 6794 // We don't need to do anything else for unused arguments. 6795 if (ArgValues.empty()) 6796 continue; 6797 6798 // Note down frame index. 6799 if (FrameIndexSDNode *FI = 6800 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6801 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6802 6803 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6804 SDB->getCurSDLoc()); 6805 6806 SDB->setValue(I, Res); 6807 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6808 if (LoadSDNode *LNode = 6809 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6810 if (FrameIndexSDNode *FI = 6811 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6812 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6813 } 6814 6815 // If this argument is live outside of the entry block, insert a copy from 6816 // wherever we got it to the vreg that other BB's will reference it as. 6817 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6818 // If we can, though, try to skip creating an unnecessary vreg. 6819 // FIXME: This isn't very clean... it would be nice to make this more 6820 // general. It's also subtly incompatible with the hacks FastISel 6821 // uses with vregs. 6822 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6823 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6824 FuncInfo->ValueMap[I] = Reg; 6825 continue; 6826 } 6827 } 6828 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 6829 FuncInfo->InitializeRegForValue(I); 6830 SDB->CopyToExportRegsIfNeeded(I); 6831 } 6832 } 6833 6834 assert(i == InVals.size() && "Argument register count mismatch!"); 6835 6836 // Finally, if the target has anything special to do, allow it to do so. 6837 // FIXME: this should insert code into the DAG! 6838 EmitFunctionEntryCode(); 6839} 6840 6841/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6842/// ensure constants are generated when needed. Remember the virtual registers 6843/// that need to be added to the Machine PHI nodes as input. We cannot just 6844/// directly add them, because expansion might result in multiple MBB's for one 6845/// BB. As such, the start of the BB might correspond to a different MBB than 6846/// the end. 6847/// 6848void 6849SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6850 const TerminatorInst *TI = LLVMBB->getTerminator(); 6851 6852 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6853 6854 // Check successor nodes' PHI nodes that expect a constant to be available 6855 // from this block. 6856 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6857 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6858 if (!isa<PHINode>(SuccBB->begin())) continue; 6859 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6860 6861 // If this terminator has multiple identical successors (common for 6862 // switches), only handle each succ once. 6863 if (!SuccsHandled.insert(SuccMBB)) continue; 6864 6865 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6866 6867 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6868 // nodes and Machine PHI nodes, but the incoming operands have not been 6869 // emitted yet. 6870 for (BasicBlock::const_iterator I = SuccBB->begin(); 6871 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6872 // Ignore dead phi's. 6873 if (PN->use_empty()) continue; 6874 6875 // Skip empty types 6876 if (PN->getType()->isEmptyTy()) 6877 continue; 6878 6879 unsigned Reg; 6880 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6881 6882 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6883 unsigned &RegOut = ConstantsOut[C]; 6884 if (RegOut == 0) { 6885 RegOut = FuncInfo.CreateRegs(C->getType()); 6886 CopyValueToVirtualRegister(C, RegOut); 6887 } 6888 Reg = RegOut; 6889 } else { 6890 DenseMap<const Value *, unsigned>::iterator I = 6891 FuncInfo.ValueMap.find(PHIOp); 6892 if (I != FuncInfo.ValueMap.end()) 6893 Reg = I->second; 6894 else { 6895 assert(isa<AllocaInst>(PHIOp) && 6896 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6897 "Didn't codegen value into a register!??"); 6898 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6899 CopyValueToVirtualRegister(PHIOp, Reg); 6900 } 6901 } 6902 6903 // Remember that this register needs to added to the machine PHI node as 6904 // the input for this MBB. 6905 SmallVector<EVT, 4> ValueVTs; 6906 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6907 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6908 EVT VT = ValueVTs[vti]; 6909 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6910 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6911 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6912 Reg += NumRegisters; 6913 } 6914 } 6915 } 6916 ConstantsOut.clear(); 6917} 6918