SelectionDAGBuilder.cpp revision adbf7b2c567d42fcb12cfd69c2692da03d34d384
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/PseudoSourceValue.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Analysis/DebugInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameLowering.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72// Limit the width of DAG chains. This is important in general to prevent 73// prevent DAG-based analysis from blowing up. For example, alias analysis and 74// load clustering may not complete in reasonable time. It is difficult to 75// recognize and avoid this situation within each individual analysis, and 76// future analyses are likely to have the same behavior. Limiting DAG width is 77// the safe approach, and will be especially important with global DAGs. 78// 79// MaxParallelChains default is arbitrarily high to avoid affecting 80// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81// sequence over this should have been converted to llvm.memcpy by the 82// frontend. It easy to induce this behavior with .ll code such as: 83// %buffer = alloca [4096 x i8] 84// %data = load [4096 x i8]* %argPtr 85// store [4096 x i8] %data, [4096 x i8]* %buffer 86static const unsigned MaxParallelChains = 64; 87 88static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92/// getCopyFromParts - Create a value that contains the specified legal parts 93/// combined into the value they represent. If the parts combine to a type 94/// larger then ValueVT then AssertOp can be used to specify whether the extra 95/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96/// (ISD::AssertSext). 97static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getIntPtrConstant(1)); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209 return SDValue(); 210} 211 212/// getCopyFromParts - Create a value that contains the specified legal parts 213/// combined into the value they represent. If the parts combine to a type 214/// larger then ValueVT then AssertOp can be used to specify whether the extra 215/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216/// (ISD::AssertSext). 217static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 287 "Cannot handle this kind of promotion"); 288 // Promoted vector extract 289 bool Smaller = ValueVT.bitsLE(PartVT); 290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 291 DL, ValueVT, Val); 292 293 } 294 295 // Trivial bitcast if the types are the same size and the destination 296 // vector type is legal. 297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 298 TLI.isTypeLegal(ValueVT)) 299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 300 301 // Handle cases such as i8 -> <1 x i1> 302 assert(ValueVT.getVectorNumElements() == 1 && 303 "Only trivial scalar-to-vector conversions should get here!"); 304 305 if (ValueVT.getVectorNumElements() == 1 && 306 ValueVT.getVectorElementType() != PartVT) { 307 bool Smaller = ValueVT.bitsLE(PartVT); 308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 309 DL, ValueVT.getScalarType(), Val); 310 } 311 312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 313} 314 315 316 317 318static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 319 SDValue Val, SDValue *Parts, unsigned NumParts, 320 EVT PartVT); 321 322/// getCopyToParts - Create a series of nodes that contain the specified value 323/// split into legal parts. If the parts contain more bits than Val, then, for 324/// integers, ExtendKind can be used to specify how to generate the extra bits. 325static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 326 SDValue Val, SDValue *Parts, unsigned NumParts, 327 EVT PartVT, 328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 329 EVT ValueVT = Val.getValueType(); 330 331 // Handle the vector case separately. 332 if (ValueVT.isVector()) 333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 334 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 336 unsigned PartBits = PartVT.getSizeInBits(); 337 unsigned OrigNumParts = NumParts; 338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 339 340 if (NumParts == 0) 341 return; 342 343 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 344 if (PartVT == ValueVT) { 345 assert(NumParts == 1 && "No-op copy with multiple parts!"); 346 Parts[0] = Val; 347 return; 348 } 349 350 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 351 // If the parts cover more bits than the value has, promote the value. 352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 353 assert(NumParts == 1 && "Do not know what to promote to!"); 354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 355 } else { 356 assert(PartVT.isInteger() && ValueVT.isInteger() && 357 "Unknown mismatch!"); 358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 360 } 361 } else if (PartBits == ValueVT.getSizeInBits()) { 362 // Different types of the same size. 363 assert(NumParts == 1 && PartVT != ValueVT); 364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 366 // If the parts cover less bits than value has, truncate the value. 367 assert(PartVT.isInteger() && ValueVT.isInteger() && 368 "Unknown mismatch!"); 369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 371 } 372 373 // The value may have changed - recompute ValueVT. 374 ValueVT = Val.getValueType(); 375 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 376 "Failed to tile the value with PartVT!"); 377 378 if (NumParts == 1) { 379 assert(PartVT == ValueVT && "Type conversion failed!"); 380 Parts[0] = Val; 381 return; 382 } 383 384 // Expand the value into multiple parts. 385 if (NumParts & (NumParts - 1)) { 386 // The number of parts is not a power of 2. Split off and copy the tail. 387 assert(PartVT.isInteger() && ValueVT.isInteger() && 388 "Do not know what to expand to!"); 389 unsigned RoundParts = 1 << Log2_32(NumParts); 390 unsigned RoundBits = RoundParts * PartBits; 391 unsigned OddParts = NumParts - RoundParts; 392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 393 DAG.getIntPtrConstant(RoundBits)); 394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 395 396 if (TLI.isBigEndian()) 397 // The odd parts were reversed by getCopyToParts - unreverse them. 398 std::reverse(Parts + RoundParts, Parts + NumParts); 399 400 NumParts = RoundParts; 401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 403 } 404 405 // The number of parts is a power of 2. Repeatedly bisect the value using 406 // EXTRACT_ELEMENT. 407 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 408 EVT::getIntegerVT(*DAG.getContext(), 409 ValueVT.getSizeInBits()), 410 Val); 411 412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 413 for (unsigned i = 0; i < NumParts; i += StepSize) { 414 unsigned ThisBits = StepSize * PartBits / 2; 415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 416 SDValue &Part0 = Parts[i]; 417 SDValue &Part1 = Parts[i+StepSize/2]; 418 419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 420 ThisVT, Part0, DAG.getIntPtrConstant(1)); 421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 422 ThisVT, Part0, DAG.getIntPtrConstant(0)); 423 424 if (ThisBits == PartBits && ThisVT != PartVT) { 425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 427 } 428 } 429 } 430 431 if (TLI.isBigEndian()) 432 std::reverse(Parts, Parts + OrigNumParts); 433} 434 435 436/// getCopyToPartsVector - Create a series of nodes that contain the specified 437/// value split into legal parts. 438static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 439 SDValue Val, SDValue *Parts, unsigned NumParts, 440 EVT PartVT) { 441 EVT ValueVT = Val.getValueType(); 442 assert(ValueVT.isVector() && "Not a vector"); 443 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 444 445 if (NumParts == 1) { 446 if (PartVT == ValueVT) { 447 // Nothing to do. 448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 449 // Bitconvert vector->vector case. 450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 451 } else if (PartVT.isVector() && 452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 454 EVT ElementVT = PartVT.getVectorElementType(); 455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 456 // undef elements. 457 SmallVector<SDValue, 16> Ops; 458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 460 ElementVT, Val, DAG.getIntPtrConstant(i))); 461 462 for (unsigned i = ValueVT.getVectorNumElements(), 463 e = PartVT.getVectorNumElements(); i != e; ++i) 464 Ops.push_back(DAG.getUNDEF(ElementVT)); 465 466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 467 468 // FIXME: Use CONCAT for 2x -> 4x. 469 470 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 472 } else if (PartVT.isVector() && 473 PartVT.getVectorElementType().bitsGE( 474 ValueVT.getVectorElementType()) && 475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 476 477 // Promoted vector extract 478 bool Smaller = PartVT.bitsLE(ValueVT); 479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 480 DL, PartVT, Val); 481 } else{ 482 // Vector -> scalar conversion. 483 assert(ValueVT.getVectorNumElements() == 1 && 484 "Only trivial vector-to-scalar conversions should get here!"); 485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 486 PartVT, Val, DAG.getIntPtrConstant(0)); 487 488 bool Smaller = ValueVT.bitsLE(PartVT); 489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 490 DL, PartVT, Val); 491 } 492 493 Parts[0] = Val; 494 return; 495 } 496 497 // Handle a multi-element vector. 498 EVT IntermediateVT, RegisterVT; 499 unsigned NumIntermediates; 500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 501 IntermediateVT, 502 NumIntermediates, RegisterVT); 503 unsigned NumElements = ValueVT.getVectorNumElements(); 504 505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 506 NumParts = NumRegs; // Silence a compiler warning. 507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 508 509 // Split the vector into intermediate operands. 510 SmallVector<SDValue, 8> Ops(NumIntermediates); 511 for (unsigned i = 0; i != NumIntermediates; ++i) { 512 if (IntermediateVT.isVector()) 513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 514 IntermediateVT, Val, 515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 516 else 517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 518 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 519 } 520 521 // Split the intermediate operands into legal parts. 522 if (NumParts == NumIntermediates) { 523 // If the register was not expanded, promote or copy the value, 524 // as appropriate. 525 for (unsigned i = 0; i != NumParts; ++i) 526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 527 } else if (NumParts > 0) { 528 // If the intermediate type was expanded, split each the value into 529 // legal parts. 530 assert(NumParts % NumIntermediates == 0 && 531 "Must expand into a divisible number of parts!"); 532 unsigned Factor = NumParts / NumIntermediates; 533 for (unsigned i = 0; i != NumIntermediates; ++i) 534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 535 } 536} 537 538 539 540 541namespace { 542 /// RegsForValue - This struct represents the registers (physical or virtual) 543 /// that a particular set of values is assigned, and the type information 544 /// about the value. The most common situation is to represent one value at a 545 /// time, but struct or array values are handled element-wise as multiple 546 /// values. The splitting of aggregates is performed recursively, so that we 547 /// never have aggregate-typed registers. The values at this point do not 548 /// necessarily have legal types, so each value may require one or more 549 /// registers of some legal type. 550 /// 551 struct RegsForValue { 552 /// ValueVTs - The value types of the values, which may not be legal, and 553 /// may need be promoted or synthesized from one or more registers. 554 /// 555 SmallVector<EVT, 4> ValueVTs; 556 557 /// RegVTs - The value types of the registers. This is the same size as 558 /// ValueVTs and it records, for each value, what the type of the assigned 559 /// register or registers are. (Individual values are never synthesized 560 /// from more than one type of register.) 561 /// 562 /// With virtual registers, the contents of RegVTs is redundant with TLI's 563 /// getRegisterType member function, however when with physical registers 564 /// it is necessary to have a separate record of the types. 565 /// 566 SmallVector<EVT, 4> RegVTs; 567 568 /// Regs - This list holds the registers assigned to the values. 569 /// Each legal or promoted value requires one register, and each 570 /// expanded value requires multiple registers. 571 /// 572 SmallVector<unsigned, 4> Regs; 573 574 RegsForValue() {} 575 576 RegsForValue(const SmallVector<unsigned, 4> ®s, 577 EVT regvt, EVT valuevt) 578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 579 580 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 581 unsigned Reg, Type *Ty) { 582 ComputeValueVTs(tli, Ty, ValueVTs); 583 584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 585 EVT ValueVT = ValueVTs[Value]; 586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 588 for (unsigned i = 0; i != NumRegs; ++i) 589 Regs.push_back(Reg + i); 590 RegVTs.push_back(RegisterVT); 591 Reg += NumRegs; 592 } 593 } 594 595 /// areValueTypesLegal - Return true if types of all the values are legal. 596 bool areValueTypesLegal(const TargetLowering &TLI) { 597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 598 EVT RegisterVT = RegVTs[Value]; 599 if (!TLI.isTypeLegal(RegisterVT)) 600 return false; 601 } 602 return true; 603 } 604 605 /// append - Add the specified values to this one. 606 void append(const RegsForValue &RHS) { 607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 609 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 610 } 611 612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 613 /// this value and returns the result as a ValueVTs value. This uses 614 /// Chain/Flag as the input and updates them for the output Chain/Flag. 615 /// If the Flag pointer is NULL, no flag is used. 616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 617 DebugLoc dl, 618 SDValue &Chain, SDValue *Flag) const; 619 620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 621 /// specified value into the registers specified by this object. This uses 622 /// Chain/Flag as the input and updates them for the output Chain/Flag. 623 /// If the Flag pointer is NULL, no flag is used. 624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 625 SDValue &Chain, SDValue *Flag) const; 626 627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 628 /// operand list. This adds the code marker, matching input operand index 629 /// (if applicable), and includes the number of values added into it. 630 void AddInlineAsmOperands(unsigned Kind, 631 bool HasMatching, unsigned MatchingIdx, 632 SelectionDAG &DAG, 633 std::vector<SDValue> &Ops) const; 634 }; 635} 636 637/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 638/// this value and returns the result as a ValueVT value. This uses 639/// Chain/Flag as the input and updates them for the output Chain/Flag. 640/// If the Flag pointer is NULL, no flag is used. 641SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 642 FunctionLoweringInfo &FuncInfo, 643 DebugLoc dl, 644 SDValue &Chain, SDValue *Flag) const { 645 // A Value with type {} or [0 x %t] needs no registers. 646 if (ValueVTs.empty()) 647 return SDValue(); 648 649 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 650 651 // Assemble the legal parts into the final values. 652 SmallVector<SDValue, 4> Values(ValueVTs.size()); 653 SmallVector<SDValue, 8> Parts; 654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 655 // Copy the legal parts from the registers. 656 EVT ValueVT = ValueVTs[Value]; 657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 658 EVT RegisterVT = RegVTs[Value]; 659 660 Parts.resize(NumRegs); 661 for (unsigned i = 0; i != NumRegs; ++i) { 662 SDValue P; 663 if (Flag == 0) { 664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 665 } else { 666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 667 *Flag = P.getValue(2); 668 } 669 670 Chain = P.getValue(1); 671 Parts[i] = P; 672 673 // If the source register was virtual and if we know something about it, 674 // add an assert node. 675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 676 !RegisterVT.isInteger() || RegisterVT.isVector()) 677 continue; 678 679 const FunctionLoweringInfo::LiveOutInfo *LOI = 680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 681 if (!LOI) 682 continue; 683 684 unsigned RegSize = RegisterVT.getSizeInBits(); 685 unsigned NumSignBits = LOI->NumSignBits; 686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 687 688 // FIXME: We capture more information than the dag can represent. For 689 // now, just use the tightest assertzext/assertsext possible. 690 bool isSExt = true; 691 EVT FromVT(MVT::Other); 692 if (NumSignBits == RegSize) 693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 694 else if (NumZeroBits >= RegSize-1) 695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 696 else if (NumSignBits > RegSize-8) 697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 698 else if (NumZeroBits >= RegSize-8) 699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 700 else if (NumSignBits > RegSize-16) 701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 702 else if (NumZeroBits >= RegSize-16) 703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 704 else if (NumSignBits > RegSize-32) 705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 706 else if (NumZeroBits >= RegSize-32) 707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 708 else 709 continue; 710 711 // Add an assertion node. 712 assert(FromVT != MVT::Other); 713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 714 RegisterVT, P, DAG.getValueType(FromVT)); 715 } 716 717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 718 NumRegs, RegisterVT, ValueVT); 719 Part += NumRegs; 720 Parts.clear(); 721 } 722 723 return DAG.getNode(ISD::MERGE_VALUES, dl, 724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 725 &Values[0], ValueVTs.size()); 726} 727 728/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 729/// specified value into the registers specified by this object. This uses 730/// Chain/Flag as the input and updates them for the output Chain/Flag. 731/// If the Flag pointer is NULL, no flag is used. 732void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 733 SDValue &Chain, SDValue *Flag) const { 734 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 735 736 // Get the list of the values's legal parts. 737 unsigned NumRegs = Regs.size(); 738 SmallVector<SDValue, 8> Parts(NumRegs); 739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 740 EVT ValueVT = ValueVTs[Value]; 741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 742 EVT RegisterVT = RegVTs[Value]; 743 744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 745 &Parts[Part], NumParts, RegisterVT); 746 Part += NumParts; 747 } 748 749 // Copy the parts into the registers. 750 SmallVector<SDValue, 8> Chains(NumRegs); 751 for (unsigned i = 0; i != NumRegs; ++i) { 752 SDValue Part; 753 if (Flag == 0) { 754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 755 } else { 756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 757 *Flag = Part.getValue(1); 758 } 759 760 Chains[i] = Part.getValue(0); 761 } 762 763 if (NumRegs == 1 || Flag) 764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 765 // flagged to it. That is the CopyToReg nodes and the user are considered 766 // a single scheduling unit. If we create a TokenFactor and return it as 767 // chain, then the TokenFactor is both a predecessor (operand) of the 768 // user as well as a successor (the TF operands are flagged to the user). 769 // c1, f1 = CopyToReg 770 // c2, f2 = CopyToReg 771 // c3 = TokenFactor c1, c2 772 // ... 773 // = op c3, ..., f2 774 Chain = Chains[NumRegs-1]; 775 else 776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 777} 778 779/// AddInlineAsmOperands - Add this value to the specified inlineasm node 780/// operand list. This adds the code marker and includes the number of 781/// values added into it. 782void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 783 unsigned MatchingIdx, 784 SelectionDAG &DAG, 785 std::vector<SDValue> &Ops) const { 786 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 787 788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 789 if (HasMatching) 790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 791 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 792 Ops.push_back(Res); 793 794 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 795 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 796 EVT RegisterVT = RegVTs[Value]; 797 for (unsigned i = 0; i != NumRegs; ++i) { 798 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 799 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 800 } 801 } 802} 803 804void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 805 AA = &aa; 806 GFI = gfi; 807 TD = DAG.getTarget().getTargetData(); 808} 809 810/// clear - Clear out the current SelectionDAG and the associated 811/// state and prepare this SelectionDAGBuilder object to be used 812/// for a new block. This doesn't clear out information about 813/// additional blocks that are needed to complete switch lowering 814/// or PHI node updating; that information is cleared out as it is 815/// consumed. 816void SelectionDAGBuilder::clear() { 817 NodeMap.clear(); 818 UnusedArgNodeMap.clear(); 819 PendingLoads.clear(); 820 PendingExports.clear(); 821 CurDebugLoc = DebugLoc(); 822 HasTailCall = false; 823} 824 825/// clearDanglingDebugInfo - Clear the dangling debug information 826/// map. This function is seperated from the clear so that debug 827/// information that is dangling in a basic block can be properly 828/// resolved in a different basic block. This allows the 829/// SelectionDAG to resolve dangling debug information attached 830/// to PHI nodes. 831void SelectionDAGBuilder::clearDanglingDebugInfo() { 832 DanglingDebugInfoMap.clear(); 833} 834 835/// getRoot - Return the current virtual root of the Selection DAG, 836/// flushing any PendingLoad items. This must be done before emitting 837/// a store or any other node that may need to be ordered after any 838/// prior load instructions. 839/// 840SDValue SelectionDAGBuilder::getRoot() { 841 if (PendingLoads.empty()) 842 return DAG.getRoot(); 843 844 if (PendingLoads.size() == 1) { 845 SDValue Root = PendingLoads[0]; 846 DAG.setRoot(Root); 847 PendingLoads.clear(); 848 return Root; 849 } 850 851 // Otherwise, we have to make a token factor node. 852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 853 &PendingLoads[0], PendingLoads.size()); 854 PendingLoads.clear(); 855 DAG.setRoot(Root); 856 return Root; 857} 858 859/// getControlRoot - Similar to getRoot, but instead of flushing all the 860/// PendingLoad items, flush all the PendingExports items. It is necessary 861/// to do this before emitting a terminator instruction. 862/// 863SDValue SelectionDAGBuilder::getControlRoot() { 864 SDValue Root = DAG.getRoot(); 865 866 if (PendingExports.empty()) 867 return Root; 868 869 // Turn all of the CopyToReg chains into one factored node. 870 if (Root.getOpcode() != ISD::EntryToken) { 871 unsigned i = 0, e = PendingExports.size(); 872 for (; i != e; ++i) { 873 assert(PendingExports[i].getNode()->getNumOperands() > 1); 874 if (PendingExports[i].getNode()->getOperand(0) == Root) 875 break; // Don't add the root if we already indirectly depend on it. 876 } 877 878 if (i == e) 879 PendingExports.push_back(Root); 880 } 881 882 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 883 &PendingExports[0], 884 PendingExports.size()); 885 PendingExports.clear(); 886 DAG.setRoot(Root); 887 return Root; 888} 889 890void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 891 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 892 DAG.AssignOrdering(Node, SDNodeOrder); 893 894 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 895 AssignOrderingToNode(Node->getOperand(I).getNode()); 896} 897 898void SelectionDAGBuilder::visit(const Instruction &I) { 899 // Set up outgoing PHI node register values before emitting the terminator. 900 if (isa<TerminatorInst>(&I)) 901 HandlePHINodesInSuccessorBlocks(I.getParent()); 902 903 CurDebugLoc = I.getDebugLoc(); 904 905 visit(I.getOpcode(), I); 906 907 if (!isa<TerminatorInst>(&I) && !HasTailCall) 908 CopyToExportRegsIfNeeded(&I); 909 910 CurDebugLoc = DebugLoc(); 911} 912 913void SelectionDAGBuilder::visitPHI(const PHINode &) { 914 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 915} 916 917void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 918 // Note: this doesn't use InstVisitor, because it has to work with 919 // ConstantExpr's in addition to instructions. 920 switch (Opcode) { 921 default: llvm_unreachable("Unknown instruction type encountered!"); 922 // Build the switch statement using the Instruction.def file. 923#define HANDLE_INST(NUM, OPCODE, CLASS) \ 924 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 925#include "llvm/Instruction.def" 926 } 927 928 // Assign the ordering to the freshly created DAG nodes. 929 if (NodeMap.count(&I)) { 930 ++SDNodeOrder; 931 AssignOrderingToNode(getValue(&I).getNode()); 932 } 933} 934 935// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 936// generate the debug data structures now that we've seen its definition. 937void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 938 SDValue Val) { 939 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 940 if (DDI.getDI()) { 941 const DbgValueInst *DI = DDI.getDI(); 942 DebugLoc dl = DDI.getdl(); 943 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 944 MDNode *Variable = DI->getVariable(); 945 uint64_t Offset = DI->getOffset(); 946 SDDbgValue *SDV; 947 if (Val.getNode()) { 948 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 949 SDV = DAG.getDbgValue(Variable, Val.getNode(), 950 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 951 DAG.AddDbgValue(SDV, Val.getNode(), false); 952 } 953 } else 954 DEBUG(dbgs() << "Dropping debug info for " << DI); 955 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 956 } 957} 958 959// getValue - Return an SDValue for the given Value. 960SDValue SelectionDAGBuilder::getValue(const Value *V) { 961 // If we already have an SDValue for this value, use it. It's important 962 // to do this first, so that we don't create a CopyFromReg if we already 963 // have a regular SDValue. 964 SDValue &N = NodeMap[V]; 965 if (N.getNode()) return N; 966 967 // If there's a virtual register allocated and initialized for this 968 // value, use it. 969 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 970 if (It != FuncInfo.ValueMap.end()) { 971 unsigned InReg = It->second; 972 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 973 SDValue Chain = DAG.getEntryNode(); 974 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 975 resolveDanglingDebugInfo(V, N); 976 return N; 977 } 978 979 // Otherwise create a new SDValue and remember it. 980 SDValue Val = getValueImpl(V); 981 NodeMap[V] = Val; 982 resolveDanglingDebugInfo(V, Val); 983 return Val; 984} 985 986/// getNonRegisterValue - Return an SDValue for the given Value, but 987/// don't look in FuncInfo.ValueMap for a virtual register. 988SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 989 // If we already have an SDValue for this value, use it. 990 SDValue &N = NodeMap[V]; 991 if (N.getNode()) return N; 992 993 // Otherwise create a new SDValue and remember it. 994 SDValue Val = getValueImpl(V); 995 NodeMap[V] = Val; 996 resolveDanglingDebugInfo(V, Val); 997 return Val; 998} 999 1000/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1001/// Create an SDValue for the given value. 1002SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1003 if (const Constant *C = dyn_cast<Constant>(V)) { 1004 EVT VT = TLI.getValueType(V->getType(), true); 1005 1006 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1007 return DAG.getConstant(*CI, VT); 1008 1009 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1010 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1011 1012 if (isa<ConstantPointerNull>(C)) 1013 return DAG.getConstant(0, TLI.getPointerTy()); 1014 1015 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1016 return DAG.getConstantFP(*CFP, VT); 1017 1018 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1019 return DAG.getUNDEF(VT); 1020 1021 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1022 visit(CE->getOpcode(), *CE); 1023 SDValue N1 = NodeMap[V]; 1024 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1025 return N1; 1026 } 1027 1028 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1029 SmallVector<SDValue, 4> Constants; 1030 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1031 OI != OE; ++OI) { 1032 SDNode *Val = getValue(*OI).getNode(); 1033 // If the operand is an empty aggregate, there are no values. 1034 if (!Val) continue; 1035 // Add each leaf value from the operand to the Constants list 1036 // to form a flattened list of all the values. 1037 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1038 Constants.push_back(SDValue(Val, i)); 1039 } 1040 1041 return DAG.getMergeValues(&Constants[0], Constants.size(), 1042 getCurDebugLoc()); 1043 } 1044 1045 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1046 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1047 "Unknown struct or array constant!"); 1048 1049 SmallVector<EVT, 4> ValueVTs; 1050 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1051 unsigned NumElts = ValueVTs.size(); 1052 if (NumElts == 0) 1053 return SDValue(); // empty struct 1054 SmallVector<SDValue, 4> Constants(NumElts); 1055 for (unsigned i = 0; i != NumElts; ++i) { 1056 EVT EltVT = ValueVTs[i]; 1057 if (isa<UndefValue>(C)) 1058 Constants[i] = DAG.getUNDEF(EltVT); 1059 else if (EltVT.isFloatingPoint()) 1060 Constants[i] = DAG.getConstantFP(0, EltVT); 1061 else 1062 Constants[i] = DAG.getConstant(0, EltVT); 1063 } 1064 1065 return DAG.getMergeValues(&Constants[0], NumElts, 1066 getCurDebugLoc()); 1067 } 1068 1069 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1070 return DAG.getBlockAddress(BA, VT); 1071 1072 VectorType *VecTy = cast<VectorType>(V->getType()); 1073 unsigned NumElements = VecTy->getNumElements(); 1074 1075 // Now that we know the number and type of the elements, get that number of 1076 // elements into the Ops array based on what kind of constant it is. 1077 SmallVector<SDValue, 16> Ops; 1078 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1079 for (unsigned i = 0; i != NumElements; ++i) 1080 Ops.push_back(getValue(CP->getOperand(i))); 1081 } else { 1082 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1083 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1084 1085 SDValue Op; 1086 if (EltVT.isFloatingPoint()) 1087 Op = DAG.getConstantFP(0, EltVT); 1088 else 1089 Op = DAG.getConstant(0, EltVT); 1090 Ops.assign(NumElements, Op); 1091 } 1092 1093 // Create a BUILD_VECTOR node. 1094 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1095 VT, &Ops[0], Ops.size()); 1096 } 1097 1098 // If this is a static alloca, generate it as the frameindex instead of 1099 // computation. 1100 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1101 DenseMap<const AllocaInst*, int>::iterator SI = 1102 FuncInfo.StaticAllocaMap.find(AI); 1103 if (SI != FuncInfo.StaticAllocaMap.end()) 1104 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1105 } 1106 1107 // If this is an instruction which fast-isel has deferred, select it now. 1108 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1109 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1110 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1111 SDValue Chain = DAG.getEntryNode(); 1112 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1113 } 1114 1115 llvm_unreachable("Can't get register for value!"); 1116 return SDValue(); 1117} 1118 1119void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1120 SDValue Chain = getControlRoot(); 1121 SmallVector<ISD::OutputArg, 8> Outs; 1122 SmallVector<SDValue, 8> OutVals; 1123 1124 if (!FuncInfo.CanLowerReturn) { 1125 unsigned DemoteReg = FuncInfo.DemoteRegister; 1126 const Function *F = I.getParent()->getParent(); 1127 1128 // Emit a store of the return value through the virtual register. 1129 // Leave Outs empty so that LowerReturn won't try to load return 1130 // registers the usual way. 1131 SmallVector<EVT, 1> PtrValueVTs; 1132 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1133 PtrValueVTs); 1134 1135 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1136 SDValue RetOp = getValue(I.getOperand(0)); 1137 1138 SmallVector<EVT, 4> ValueVTs; 1139 SmallVector<uint64_t, 4> Offsets; 1140 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1141 unsigned NumValues = ValueVTs.size(); 1142 1143 SmallVector<SDValue, 4> Chains(NumValues); 1144 for (unsigned i = 0; i != NumValues; ++i) { 1145 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1146 RetPtr.getValueType(), RetPtr, 1147 DAG.getIntPtrConstant(Offsets[i])); 1148 Chains[i] = 1149 DAG.getStore(Chain, getCurDebugLoc(), 1150 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1151 // FIXME: better loc info would be nice. 1152 Add, MachinePointerInfo(), false, false, 0); 1153 } 1154 1155 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1156 MVT::Other, &Chains[0], NumValues); 1157 } else if (I.getNumOperands() != 0) { 1158 SmallVector<EVT, 4> ValueVTs; 1159 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1160 unsigned NumValues = ValueVTs.size(); 1161 if (NumValues) { 1162 SDValue RetOp = getValue(I.getOperand(0)); 1163 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1164 EVT VT = ValueVTs[j]; 1165 1166 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1167 1168 const Function *F = I.getParent()->getParent(); 1169 if (F->paramHasAttr(0, Attribute::SExt)) 1170 ExtendKind = ISD::SIGN_EXTEND; 1171 else if (F->paramHasAttr(0, Attribute::ZExt)) 1172 ExtendKind = ISD::ZERO_EXTEND; 1173 1174 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1175 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1176 1177 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1178 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1179 SmallVector<SDValue, 4> Parts(NumParts); 1180 getCopyToParts(DAG, getCurDebugLoc(), 1181 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1182 &Parts[0], NumParts, PartVT, ExtendKind); 1183 1184 // 'inreg' on function refers to return value 1185 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1186 if (F->paramHasAttr(0, Attribute::InReg)) 1187 Flags.setInReg(); 1188 1189 // Propagate extension type if any 1190 if (ExtendKind == ISD::SIGN_EXTEND) 1191 Flags.setSExt(); 1192 else if (ExtendKind == ISD::ZERO_EXTEND) 1193 Flags.setZExt(); 1194 1195 for (unsigned i = 0; i < NumParts; ++i) { 1196 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1197 /*isfixed=*/true)); 1198 OutVals.push_back(Parts[i]); 1199 } 1200 } 1201 } 1202 } 1203 1204 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1205 CallingConv::ID CallConv = 1206 DAG.getMachineFunction().getFunction()->getCallingConv(); 1207 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1208 Outs, OutVals, getCurDebugLoc(), DAG); 1209 1210 // Verify that the target's LowerReturn behaved as expected. 1211 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1212 "LowerReturn didn't return a valid chain!"); 1213 1214 // Update the DAG with the new chain value resulting from return lowering. 1215 DAG.setRoot(Chain); 1216} 1217 1218/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1219/// created for it, emit nodes to copy the value into the virtual 1220/// registers. 1221void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1222 // Skip empty types 1223 if (V->getType()->isEmptyTy()) 1224 return; 1225 1226 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1227 if (VMI != FuncInfo.ValueMap.end()) { 1228 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1229 CopyValueToVirtualRegister(V, VMI->second); 1230 } 1231} 1232 1233/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1234/// the current basic block, add it to ValueMap now so that we'll get a 1235/// CopyTo/FromReg. 1236void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1237 // No need to export constants. 1238 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1239 1240 // Already exported? 1241 if (FuncInfo.isExportedInst(V)) return; 1242 1243 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1244 CopyValueToVirtualRegister(V, Reg); 1245} 1246 1247bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1248 const BasicBlock *FromBB) { 1249 // The operands of the setcc have to be in this block. We don't know 1250 // how to export them from some other block. 1251 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1252 // Can export from current BB. 1253 if (VI->getParent() == FromBB) 1254 return true; 1255 1256 // Is already exported, noop. 1257 return FuncInfo.isExportedInst(V); 1258 } 1259 1260 // If this is an argument, we can export it if the BB is the entry block or 1261 // if it is already exported. 1262 if (isa<Argument>(V)) { 1263 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1264 return true; 1265 1266 // Otherwise, can only export this if it is already exported. 1267 return FuncInfo.isExportedInst(V); 1268 } 1269 1270 // Otherwise, constants can always be exported. 1271 return true; 1272} 1273 1274/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1275uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src, 1276 MachineBasicBlock *Dst) { 1277 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1278 if (!BPI) 1279 return 0; 1280 const BasicBlock *SrcBB = Src->getBasicBlock(); 1281 const BasicBlock *DstBB = Dst->getBasicBlock(); 1282 return BPI->getEdgeWeight(SrcBB, DstBB); 1283} 1284 1285void SelectionDAGBuilder:: 1286addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1287 uint32_t Weight /* = 0 */) { 1288 if (!Weight) 1289 Weight = getEdgeWeight(Src, Dst); 1290 Src->addSuccessor(Dst, Weight); 1291} 1292 1293 1294static bool InBlock(const Value *V, const BasicBlock *BB) { 1295 if (const Instruction *I = dyn_cast<Instruction>(V)) 1296 return I->getParent() == BB; 1297 return true; 1298} 1299 1300/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1301/// This function emits a branch and is used at the leaves of an OR or an 1302/// AND operator tree. 1303/// 1304void 1305SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1306 MachineBasicBlock *TBB, 1307 MachineBasicBlock *FBB, 1308 MachineBasicBlock *CurBB, 1309 MachineBasicBlock *SwitchBB) { 1310 const BasicBlock *BB = CurBB->getBasicBlock(); 1311 1312 // If the leaf of the tree is a comparison, merge the condition into 1313 // the caseblock. 1314 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1315 // The operands of the cmp have to be in this block. We don't know 1316 // how to export them from some other block. If this is the first block 1317 // of the sequence, no exporting is needed. 1318 if (CurBB == SwitchBB || 1319 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1320 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1321 ISD::CondCode Condition; 1322 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1323 Condition = getICmpCondCode(IC->getPredicate()); 1324 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1325 Condition = getFCmpCondCode(FC->getPredicate()); 1326 } else { 1327 Condition = ISD::SETEQ; // silence warning. 1328 llvm_unreachable("Unknown compare instruction"); 1329 } 1330 1331 CaseBlock CB(Condition, BOp->getOperand(0), 1332 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1333 SwitchCases.push_back(CB); 1334 return; 1335 } 1336 } 1337 1338 // Create a CaseBlock record representing this branch. 1339 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1340 NULL, TBB, FBB, CurBB); 1341 SwitchCases.push_back(CB); 1342} 1343 1344/// FindMergedConditions - If Cond is an expression like 1345void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1346 MachineBasicBlock *TBB, 1347 MachineBasicBlock *FBB, 1348 MachineBasicBlock *CurBB, 1349 MachineBasicBlock *SwitchBB, 1350 unsigned Opc) { 1351 // If this node is not part of the or/and tree, emit it as a branch. 1352 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1353 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1354 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1355 BOp->getParent() != CurBB->getBasicBlock() || 1356 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1357 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1358 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1359 return; 1360 } 1361 1362 // Create TmpBB after CurBB. 1363 MachineFunction::iterator BBI = CurBB; 1364 MachineFunction &MF = DAG.getMachineFunction(); 1365 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1366 CurBB->getParent()->insert(++BBI, TmpBB); 1367 1368 if (Opc == Instruction::Or) { 1369 // Codegen X | Y as: 1370 // jmp_if_X TBB 1371 // jmp TmpBB 1372 // TmpBB: 1373 // jmp_if_Y TBB 1374 // jmp FBB 1375 // 1376 1377 // Emit the LHS condition. 1378 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1379 1380 // Emit the RHS condition into TmpBB. 1381 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1382 } else { 1383 assert(Opc == Instruction::And && "Unknown merge op!"); 1384 // Codegen X & Y as: 1385 // jmp_if_X TmpBB 1386 // jmp FBB 1387 // TmpBB: 1388 // jmp_if_Y TBB 1389 // jmp FBB 1390 // 1391 // This requires creation of TmpBB after CurBB. 1392 1393 // Emit the LHS condition. 1394 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1395 1396 // Emit the RHS condition into TmpBB. 1397 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1398 } 1399} 1400 1401/// If the set of cases should be emitted as a series of branches, return true. 1402/// If we should emit this as a bunch of and/or'd together conditions, return 1403/// false. 1404bool 1405SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1406 if (Cases.size() != 2) return true; 1407 1408 // If this is two comparisons of the same values or'd or and'd together, they 1409 // will get folded into a single comparison, so don't emit two blocks. 1410 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1411 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1412 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1413 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1414 return false; 1415 } 1416 1417 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1418 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1419 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1420 Cases[0].CC == Cases[1].CC && 1421 isa<Constant>(Cases[0].CmpRHS) && 1422 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1423 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1424 return false; 1425 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1426 return false; 1427 } 1428 1429 return true; 1430} 1431 1432void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1433 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1434 1435 // Update machine-CFG edges. 1436 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1437 1438 // Figure out which block is immediately after the current one. 1439 MachineBasicBlock *NextBlock = 0; 1440 MachineFunction::iterator BBI = BrMBB; 1441 if (++BBI != FuncInfo.MF->end()) 1442 NextBlock = BBI; 1443 1444 if (I.isUnconditional()) { 1445 // Update machine-CFG edges. 1446 BrMBB->addSuccessor(Succ0MBB); 1447 1448 // If this is not a fall-through branch, emit the branch. 1449 if (Succ0MBB != NextBlock) 1450 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1451 MVT::Other, getControlRoot(), 1452 DAG.getBasicBlock(Succ0MBB))); 1453 1454 return; 1455 } 1456 1457 // If this condition is one of the special cases we handle, do special stuff 1458 // now. 1459 const Value *CondVal = I.getCondition(); 1460 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1461 1462 // If this is a series of conditions that are or'd or and'd together, emit 1463 // this as a sequence of branches instead of setcc's with and/or operations. 1464 // As long as jumps are not expensive, this should improve performance. 1465 // For example, instead of something like: 1466 // cmp A, B 1467 // C = seteq 1468 // cmp D, E 1469 // F = setle 1470 // or C, F 1471 // jnz foo 1472 // Emit: 1473 // cmp A, B 1474 // je foo 1475 // cmp D, E 1476 // jle foo 1477 // 1478 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1479 if (!TLI.isJumpExpensive() && 1480 BOp->hasOneUse() && 1481 (BOp->getOpcode() == Instruction::And || 1482 BOp->getOpcode() == Instruction::Or)) { 1483 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1484 BOp->getOpcode()); 1485 // If the compares in later blocks need to use values not currently 1486 // exported from this block, export them now. This block should always 1487 // be the first entry. 1488 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1489 1490 // Allow some cases to be rejected. 1491 if (ShouldEmitAsBranches(SwitchCases)) { 1492 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1493 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1494 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1495 } 1496 1497 // Emit the branch for this block. 1498 visitSwitchCase(SwitchCases[0], BrMBB); 1499 SwitchCases.erase(SwitchCases.begin()); 1500 return; 1501 } 1502 1503 // Okay, we decided not to do this, remove any inserted MBB's and clear 1504 // SwitchCases. 1505 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1506 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1507 1508 SwitchCases.clear(); 1509 } 1510 } 1511 1512 // Create a CaseBlock record representing this branch. 1513 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1514 NULL, Succ0MBB, Succ1MBB, BrMBB); 1515 1516 // Use visitSwitchCase to actually insert the fast branch sequence for this 1517 // cond branch. 1518 visitSwitchCase(CB, BrMBB); 1519} 1520 1521/// visitSwitchCase - Emits the necessary code to represent a single node in 1522/// the binary search tree resulting from lowering a switch instruction. 1523void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1524 MachineBasicBlock *SwitchBB) { 1525 SDValue Cond; 1526 SDValue CondLHS = getValue(CB.CmpLHS); 1527 DebugLoc dl = getCurDebugLoc(); 1528 1529 // Build the setcc now. 1530 if (CB.CmpMHS == NULL) { 1531 // Fold "(X == true)" to X and "(X == false)" to !X to 1532 // handle common cases produced by branch lowering. 1533 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1534 CB.CC == ISD::SETEQ) 1535 Cond = CondLHS; 1536 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1537 CB.CC == ISD::SETEQ) { 1538 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1539 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1540 } else 1541 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1542 } else { 1543 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1544 1545 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1546 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1547 1548 SDValue CmpOp = getValue(CB.CmpMHS); 1549 EVT VT = CmpOp.getValueType(); 1550 1551 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1552 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1553 ISD::SETLE); 1554 } else { 1555 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1556 VT, CmpOp, DAG.getConstant(Low, VT)); 1557 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1558 DAG.getConstant(High-Low, VT), ISD::SETULE); 1559 } 1560 } 1561 1562 // Update successor info 1563 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1564 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1565 1566 // Set NextBlock to be the MBB immediately after the current one, if any. 1567 // This is used to avoid emitting unnecessary branches to the next block. 1568 MachineBasicBlock *NextBlock = 0; 1569 MachineFunction::iterator BBI = SwitchBB; 1570 if (++BBI != FuncInfo.MF->end()) 1571 NextBlock = BBI; 1572 1573 // If the lhs block is the next block, invert the condition so that we can 1574 // fall through to the lhs instead of the rhs block. 1575 if (CB.TrueBB == NextBlock) { 1576 std::swap(CB.TrueBB, CB.FalseBB); 1577 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1578 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1579 } 1580 1581 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1582 MVT::Other, getControlRoot(), Cond, 1583 DAG.getBasicBlock(CB.TrueBB)); 1584 1585 // Insert the false branch. Do this even if it's a fall through branch, 1586 // this makes it easier to do DAG optimizations which require inverting 1587 // the branch condition. 1588 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1589 DAG.getBasicBlock(CB.FalseBB)); 1590 1591 DAG.setRoot(BrCond); 1592} 1593 1594/// visitJumpTable - Emit JumpTable node in the current MBB 1595void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1596 // Emit the code for the jump table 1597 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1598 EVT PTy = TLI.getPointerTy(); 1599 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1600 JT.Reg, PTy); 1601 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1602 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1603 MVT::Other, Index.getValue(1), 1604 Table, Index); 1605 DAG.setRoot(BrJumpTable); 1606} 1607 1608/// visitJumpTableHeader - This function emits necessary code to produce index 1609/// in the JumpTable from switch case. 1610void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1611 JumpTableHeader &JTH, 1612 MachineBasicBlock *SwitchBB) { 1613 // Subtract the lowest switch case value from the value being switched on and 1614 // conditional branch to default mbb if the result is greater than the 1615 // difference between smallest and largest cases. 1616 SDValue SwitchOp = getValue(JTH.SValue); 1617 EVT VT = SwitchOp.getValueType(); 1618 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1619 DAG.getConstant(JTH.First, VT)); 1620 1621 // The SDNode we just created, which holds the value being switched on minus 1622 // the smallest case value, needs to be copied to a virtual register so it 1623 // can be used as an index into the jump table in a subsequent basic block. 1624 // This value may be smaller or larger than the target's pointer type, and 1625 // therefore require extension or truncating. 1626 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1627 1628 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1629 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1630 JumpTableReg, SwitchOp); 1631 JT.Reg = JumpTableReg; 1632 1633 // Emit the range check for the jump table, and branch to the default block 1634 // for the switch statement if the value being switched on exceeds the largest 1635 // case in the switch. 1636 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1637 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1638 DAG.getConstant(JTH.Last-JTH.First,VT), 1639 ISD::SETUGT); 1640 1641 // Set NextBlock to be the MBB immediately after the current one, if any. 1642 // This is used to avoid emitting unnecessary branches to the next block. 1643 MachineBasicBlock *NextBlock = 0; 1644 MachineFunction::iterator BBI = SwitchBB; 1645 1646 if (++BBI != FuncInfo.MF->end()) 1647 NextBlock = BBI; 1648 1649 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1650 MVT::Other, CopyTo, CMP, 1651 DAG.getBasicBlock(JT.Default)); 1652 1653 if (JT.MBB != NextBlock) 1654 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1655 DAG.getBasicBlock(JT.MBB)); 1656 1657 DAG.setRoot(BrCond); 1658} 1659 1660/// visitBitTestHeader - This function emits necessary code to produce value 1661/// suitable for "bit tests" 1662void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1663 MachineBasicBlock *SwitchBB) { 1664 // Subtract the minimum value 1665 SDValue SwitchOp = getValue(B.SValue); 1666 EVT VT = SwitchOp.getValueType(); 1667 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1668 DAG.getConstant(B.First, VT)); 1669 1670 // Check range 1671 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1672 TLI.getSetCCResultType(Sub.getValueType()), 1673 Sub, DAG.getConstant(B.Range, VT), 1674 ISD::SETUGT); 1675 1676 // Determine the type of the test operands. 1677 bool UsePtrType = false; 1678 if (!TLI.isTypeLegal(VT)) 1679 UsePtrType = true; 1680 else { 1681 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1682 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) { 1683 // Switch table case range are encoded into series of masks. 1684 // Just use pointer type, it's guaranteed to fit. 1685 UsePtrType = true; 1686 break; 1687 } 1688 } 1689 if (UsePtrType) { 1690 VT = TLI.getPointerTy(); 1691 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1692 } 1693 1694 B.RegVT = VT; 1695 B.Reg = FuncInfo.CreateReg(VT); 1696 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1697 B.Reg, Sub); 1698 1699 // Set NextBlock to be the MBB immediately after the current one, if any. 1700 // This is used to avoid emitting unnecessary branches to the next block. 1701 MachineBasicBlock *NextBlock = 0; 1702 MachineFunction::iterator BBI = SwitchBB; 1703 if (++BBI != FuncInfo.MF->end()) 1704 NextBlock = BBI; 1705 1706 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1707 1708 addSuccessorWithWeight(SwitchBB, B.Default); 1709 addSuccessorWithWeight(SwitchBB, MBB); 1710 1711 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1712 MVT::Other, CopyTo, RangeCmp, 1713 DAG.getBasicBlock(B.Default)); 1714 1715 if (MBB != NextBlock) 1716 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1717 DAG.getBasicBlock(MBB)); 1718 1719 DAG.setRoot(BrRange); 1720} 1721 1722/// visitBitTestCase - this function produces one "bit test" 1723void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1724 MachineBasicBlock* NextMBB, 1725 unsigned Reg, 1726 BitTestCase &B, 1727 MachineBasicBlock *SwitchBB) { 1728 EVT VT = BB.RegVT; 1729 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1730 Reg, VT); 1731 SDValue Cmp; 1732 unsigned PopCount = CountPopulation_64(B.Mask); 1733 if (PopCount == 1) { 1734 // Testing for a single bit; just compare the shift count with what it 1735 // would need to be to shift a 1 bit in that position. 1736 Cmp = DAG.getSetCC(getCurDebugLoc(), 1737 TLI.getSetCCResultType(VT), 1738 ShiftOp, 1739 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1740 ISD::SETEQ); 1741 } else if (PopCount == BB.Range) { 1742 // There is only one zero bit in the range, test for it directly. 1743 Cmp = DAG.getSetCC(getCurDebugLoc(), 1744 TLI.getSetCCResultType(VT), 1745 ShiftOp, 1746 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1747 ISD::SETNE); 1748 } else { 1749 // Make desired shift 1750 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1751 DAG.getConstant(1, VT), ShiftOp); 1752 1753 // Emit bit tests and jumps 1754 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1755 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1756 Cmp = DAG.getSetCC(getCurDebugLoc(), 1757 TLI.getSetCCResultType(VT), 1758 AndOp, DAG.getConstant(0, VT), 1759 ISD::SETNE); 1760 } 1761 1762 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1763 addSuccessorWithWeight(SwitchBB, NextMBB); 1764 1765 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1766 MVT::Other, getControlRoot(), 1767 Cmp, DAG.getBasicBlock(B.TargetBB)); 1768 1769 // Set NextBlock to be the MBB immediately after the current one, if any. 1770 // This is used to avoid emitting unnecessary branches to the next block. 1771 MachineBasicBlock *NextBlock = 0; 1772 MachineFunction::iterator BBI = SwitchBB; 1773 if (++BBI != FuncInfo.MF->end()) 1774 NextBlock = BBI; 1775 1776 if (NextMBB != NextBlock) 1777 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1778 DAG.getBasicBlock(NextMBB)); 1779 1780 DAG.setRoot(BrAnd); 1781} 1782 1783void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1784 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1785 1786 // Retrieve successors. 1787 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1788 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1789 1790 const Value *Callee(I.getCalledValue()); 1791 if (isa<InlineAsm>(Callee)) 1792 visitInlineAsm(&I); 1793 else 1794 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1795 1796 // If the value of the invoke is used outside of its defining block, make it 1797 // available as a virtual register. 1798 CopyToExportRegsIfNeeded(&I); 1799 1800 // Update successor info 1801 InvokeMBB->addSuccessor(Return); 1802 InvokeMBB->addSuccessor(LandingPad); 1803 1804 // Drop into normal successor. 1805 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1806 MVT::Other, getControlRoot(), 1807 DAG.getBasicBlock(Return))); 1808} 1809 1810void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1811} 1812 1813void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1814 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1815} 1816 1817void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1818 assert(FuncInfo.MBB->isLandingPad() && 1819 "Call to landingpad not in landing pad!"); 1820 1821 MachineBasicBlock *MBB = FuncInfo.MBB; 1822 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1823 AddLandingPadInfo(LP, MMI, MBB); 1824 1825 SmallVector<EVT, 2> ValueVTs; 1826 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1827 1828 // Insert the EXCEPTIONADDR instruction. 1829 assert(FuncInfo.MBB->isLandingPad() && 1830 "Call to eh.exception not in landing pad!"); 1831 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1832 SDValue Ops[2]; 1833 Ops[0] = DAG.getRoot(); 1834 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1835 SDValue Chain = Op1.getValue(1); 1836 1837 // Insert the EHSELECTION instruction. 1838 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1839 Ops[0] = Op1; 1840 Ops[1] = Chain; 1841 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1842 Chain = Op2.getValue(1); 1843 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1844 1845 Ops[0] = Op1; 1846 Ops[1] = Op2; 1847 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1848 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1849 &Ops[0], 2); 1850 1851 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1852 setValue(&LP, RetPair.first); 1853 DAG.setRoot(RetPair.second); 1854} 1855 1856/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1857/// small case ranges). 1858bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1859 CaseRecVector& WorkList, 1860 const Value* SV, 1861 MachineBasicBlock *Default, 1862 MachineBasicBlock *SwitchBB) { 1863 Case& BackCase = *(CR.Range.second-1); 1864 1865 // Size is the number of Cases represented by this range. 1866 size_t Size = CR.Range.second - CR.Range.first; 1867 if (Size > 3) 1868 return false; 1869 1870 // Get the MachineFunction which holds the current MBB. This is used when 1871 // inserting any additional MBBs necessary to represent the switch. 1872 MachineFunction *CurMF = FuncInfo.MF; 1873 1874 // Figure out which block is immediately after the current one. 1875 MachineBasicBlock *NextBlock = 0; 1876 MachineFunction::iterator BBI = CR.CaseBB; 1877 1878 if (++BBI != FuncInfo.MF->end()) 1879 NextBlock = BBI; 1880 1881 // If any two of the cases has the same destination, and if one value 1882 // is the same as the other, but has one bit unset that the other has set, 1883 // use bit manipulation to do two compares at once. For example: 1884 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1885 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1886 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1887 if (Size == 2 && CR.CaseBB == SwitchBB) { 1888 Case &Small = *CR.Range.first; 1889 Case &Big = *(CR.Range.second-1); 1890 1891 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1892 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1893 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1894 1895 // Check that there is only one bit different. 1896 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1897 (SmallValue | BigValue) == BigValue) { 1898 // Isolate the common bit. 1899 APInt CommonBit = BigValue & ~SmallValue; 1900 assert((SmallValue | CommonBit) == BigValue && 1901 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1902 1903 SDValue CondLHS = getValue(SV); 1904 EVT VT = CondLHS.getValueType(); 1905 DebugLoc DL = getCurDebugLoc(); 1906 1907 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1908 DAG.getConstant(CommonBit, VT)); 1909 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1910 Or, DAG.getConstant(BigValue, VT), 1911 ISD::SETEQ); 1912 1913 // Update successor info. 1914 addSuccessorWithWeight(SwitchBB, Small.BB); 1915 addSuccessorWithWeight(SwitchBB, Default); 1916 1917 // Insert the true branch. 1918 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1919 getControlRoot(), Cond, 1920 DAG.getBasicBlock(Small.BB)); 1921 1922 // Insert the false branch. 1923 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1924 DAG.getBasicBlock(Default)); 1925 1926 DAG.setRoot(BrCond); 1927 return true; 1928 } 1929 } 1930 } 1931 1932 // Rearrange the case blocks so that the last one falls through if possible. 1933 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1934 // The last case block won't fall through into 'NextBlock' if we emit the 1935 // branches in this order. See if rearranging a case value would help. 1936 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1937 if (I->BB == NextBlock) { 1938 std::swap(*I, BackCase); 1939 break; 1940 } 1941 } 1942 } 1943 1944 // Create a CaseBlock record representing a conditional branch to 1945 // the Case's target mbb if the value being switched on SV is equal 1946 // to C. 1947 MachineBasicBlock *CurBlock = CR.CaseBB; 1948 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1949 MachineBasicBlock *FallThrough; 1950 if (I != E-1) { 1951 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1952 CurMF->insert(BBI, FallThrough); 1953 1954 // Put SV in a virtual register to make it available from the new blocks. 1955 ExportFromCurrentBlock(SV); 1956 } else { 1957 // If the last case doesn't match, go to the default block. 1958 FallThrough = Default; 1959 } 1960 1961 const Value *RHS, *LHS, *MHS; 1962 ISD::CondCode CC; 1963 if (I->High == I->Low) { 1964 // This is just small small case range :) containing exactly 1 case 1965 CC = ISD::SETEQ; 1966 LHS = SV; RHS = I->High; MHS = NULL; 1967 } else { 1968 CC = ISD::SETLE; 1969 LHS = I->Low; MHS = SV; RHS = I->High; 1970 } 1971 1972 uint32_t ExtraWeight = I->ExtraWeight; 1973 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 1974 /* me */ CurBlock, 1975 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2); 1976 1977 // If emitting the first comparison, just call visitSwitchCase to emit the 1978 // code into the current block. Otherwise, push the CaseBlock onto the 1979 // vector to be later processed by SDISel, and insert the node's MBB 1980 // before the next MBB. 1981 if (CurBlock == SwitchBB) 1982 visitSwitchCase(CB, SwitchBB); 1983 else 1984 SwitchCases.push_back(CB); 1985 1986 CurBlock = FallThrough; 1987 } 1988 1989 return true; 1990} 1991 1992static inline bool areJTsAllowed(const TargetLowering &TLI) { 1993 return !DisableJumpTables && 1994 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1995 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1996} 1997 1998static APInt ComputeRange(const APInt &First, const APInt &Last) { 1999 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2000 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 2001 return (LastExt - FirstExt + 1ULL); 2002} 2003 2004/// handleJTSwitchCase - Emit jumptable for current switch case range 2005bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2006 CaseRecVector &WorkList, 2007 const Value *SV, 2008 MachineBasicBlock *Default, 2009 MachineBasicBlock *SwitchBB) { 2010 Case& FrontCase = *CR.Range.first; 2011 Case& BackCase = *(CR.Range.second-1); 2012 2013 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2014 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2015 2016 APInt TSize(First.getBitWidth(), 0); 2017 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2018 TSize += I->size(); 2019 2020 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2021 return false; 2022 2023 APInt Range = ComputeRange(First, Last); 2024 double Density = TSize.roundToDouble() / Range.roundToDouble(); 2025 if (Density < 0.4) 2026 return false; 2027 2028 DEBUG(dbgs() << "Lowering jump table\n" 2029 << "First entry: " << First << ". Last entry: " << Last << '\n' 2030 << "Range: " << Range 2031 << ". Size: " << TSize << ". Density: " << Density << "\n\n"); 2032 2033 // Get the MachineFunction which holds the current MBB. This is used when 2034 // inserting any additional MBBs necessary to represent the switch. 2035 MachineFunction *CurMF = FuncInfo.MF; 2036 2037 // Figure out which block is immediately after the current one. 2038 MachineFunction::iterator BBI = CR.CaseBB; 2039 ++BBI; 2040 2041 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2042 2043 // Create a new basic block to hold the code for loading the address 2044 // of the jump table, and jumping to it. Update successor information; 2045 // we will either branch to the default case for the switch, or the jump 2046 // table. 2047 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2048 CurMF->insert(BBI, JumpTableBB); 2049 2050 addSuccessorWithWeight(CR.CaseBB, Default); 2051 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2052 2053 // Build a vector of destination BBs, corresponding to each target 2054 // of the jump table. If the value of the jump table slot corresponds to 2055 // a case statement, push the case's BB onto the vector, otherwise, push 2056 // the default BB. 2057 std::vector<MachineBasicBlock*> DestBBs; 2058 APInt TEI = First; 2059 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2060 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2061 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2062 2063 if (Low.sle(TEI) && TEI.sle(High)) { 2064 DestBBs.push_back(I->BB); 2065 if (TEI==High) 2066 ++I; 2067 } else { 2068 DestBBs.push_back(Default); 2069 } 2070 } 2071 2072 // Update successor info. Add one edge to each unique successor. 2073 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2074 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2075 E = DestBBs.end(); I != E; ++I) { 2076 if (!SuccsHandled[(*I)->getNumber()]) { 2077 SuccsHandled[(*I)->getNumber()] = true; 2078 addSuccessorWithWeight(JumpTableBB, *I); 2079 } 2080 } 2081 2082 // Create a jump table index for this jump table. 2083 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2084 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2085 ->createJumpTableIndex(DestBBs); 2086 2087 // Set the jump table information so that we can codegen it as a second 2088 // MachineBasicBlock 2089 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2090 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2091 if (CR.CaseBB == SwitchBB) 2092 visitJumpTableHeader(JT, JTH, SwitchBB); 2093 2094 JTCases.push_back(JumpTableBlock(JTH, JT)); 2095 return true; 2096} 2097 2098/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2099/// 2 subtrees. 2100bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2101 CaseRecVector& WorkList, 2102 const Value* SV, 2103 MachineBasicBlock *Default, 2104 MachineBasicBlock *SwitchBB) { 2105 // Get the MachineFunction which holds the current MBB. This is used when 2106 // inserting any additional MBBs necessary to represent the switch. 2107 MachineFunction *CurMF = FuncInfo.MF; 2108 2109 // Figure out which block is immediately after the current one. 2110 MachineFunction::iterator BBI = CR.CaseBB; 2111 ++BBI; 2112 2113 Case& FrontCase = *CR.Range.first; 2114 Case& BackCase = *(CR.Range.second-1); 2115 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2116 2117 // Size is the number of Cases represented by this range. 2118 unsigned Size = CR.Range.second - CR.Range.first; 2119 2120 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2121 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2122 double FMetric = 0; 2123 CaseItr Pivot = CR.Range.first + Size/2; 2124 2125 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2126 // (heuristically) allow us to emit JumpTable's later. 2127 APInt TSize(First.getBitWidth(), 0); 2128 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2129 I!=E; ++I) 2130 TSize += I->size(); 2131 2132 APInt LSize = FrontCase.size(); 2133 APInt RSize = TSize-LSize; 2134 DEBUG(dbgs() << "Selecting best pivot: \n" 2135 << "First: " << First << ", Last: " << Last <<'\n' 2136 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2137 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2138 J!=E; ++I, ++J) { 2139 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2140 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2141 APInt Range = ComputeRange(LEnd, RBegin); 2142 assert((Range - 2ULL).isNonNegative() && 2143 "Invalid case distance"); 2144 // Use volatile double here to avoid excess precision issues on some hosts, 2145 // e.g. that use 80-bit X87 registers. 2146 volatile double LDensity = 2147 (double)LSize.roundToDouble() / 2148 (LEnd - First + 1ULL).roundToDouble(); 2149 volatile double RDensity = 2150 (double)RSize.roundToDouble() / 2151 (Last - RBegin + 1ULL).roundToDouble(); 2152 double Metric = Range.logBase2()*(LDensity+RDensity); 2153 // Should always split in some non-trivial place 2154 DEBUG(dbgs() <<"=>Step\n" 2155 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2156 << "LDensity: " << LDensity 2157 << ", RDensity: " << RDensity << '\n' 2158 << "Metric: " << Metric << '\n'); 2159 if (FMetric < Metric) { 2160 Pivot = J; 2161 FMetric = Metric; 2162 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2163 } 2164 2165 LSize += J->size(); 2166 RSize -= J->size(); 2167 } 2168 if (areJTsAllowed(TLI)) { 2169 // If our case is dense we *really* should handle it earlier! 2170 assert((FMetric > 0) && "Should handle dense range earlier!"); 2171 } else { 2172 Pivot = CR.Range.first + Size/2; 2173 } 2174 2175 CaseRange LHSR(CR.Range.first, Pivot); 2176 CaseRange RHSR(Pivot, CR.Range.second); 2177 Constant *C = Pivot->Low; 2178 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2179 2180 // We know that we branch to the LHS if the Value being switched on is 2181 // less than the Pivot value, C. We use this to optimize our binary 2182 // tree a bit, by recognizing that if SV is greater than or equal to the 2183 // LHS's Case Value, and that Case Value is exactly one less than the 2184 // Pivot's Value, then we can branch directly to the LHS's Target, 2185 // rather than creating a leaf node for it. 2186 if ((LHSR.second - LHSR.first) == 1 && 2187 LHSR.first->High == CR.GE && 2188 cast<ConstantInt>(C)->getValue() == 2189 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2190 TrueBB = LHSR.first->BB; 2191 } else { 2192 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2193 CurMF->insert(BBI, TrueBB); 2194 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2195 2196 // Put SV in a virtual register to make it available from the new blocks. 2197 ExportFromCurrentBlock(SV); 2198 } 2199 2200 // Similar to the optimization above, if the Value being switched on is 2201 // known to be less than the Constant CR.LT, and the current Case Value 2202 // is CR.LT - 1, then we can branch directly to the target block for 2203 // the current Case Value, rather than emitting a RHS leaf node for it. 2204 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2205 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2206 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2207 FalseBB = RHSR.first->BB; 2208 } else { 2209 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2210 CurMF->insert(BBI, FalseBB); 2211 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2212 2213 // Put SV in a virtual register to make it available from the new blocks. 2214 ExportFromCurrentBlock(SV); 2215 } 2216 2217 // Create a CaseBlock record representing a conditional branch to 2218 // the LHS node if the value being switched on SV is less than C. 2219 // Otherwise, branch to LHS. 2220 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2221 2222 if (CR.CaseBB == SwitchBB) 2223 visitSwitchCase(CB, SwitchBB); 2224 else 2225 SwitchCases.push_back(CB); 2226 2227 return true; 2228} 2229 2230/// handleBitTestsSwitchCase - if current case range has few destination and 2231/// range span less, than machine word bitwidth, encode case range into series 2232/// of masks and emit bit tests with these masks. 2233bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2234 CaseRecVector& WorkList, 2235 const Value* SV, 2236 MachineBasicBlock* Default, 2237 MachineBasicBlock *SwitchBB){ 2238 EVT PTy = TLI.getPointerTy(); 2239 unsigned IntPtrBits = PTy.getSizeInBits(); 2240 2241 Case& FrontCase = *CR.Range.first; 2242 Case& BackCase = *(CR.Range.second-1); 2243 2244 // Get the MachineFunction which holds the current MBB. This is used when 2245 // inserting any additional MBBs necessary to represent the switch. 2246 MachineFunction *CurMF = FuncInfo.MF; 2247 2248 // If target does not have legal shift left, do not emit bit tests at all. 2249 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2250 return false; 2251 2252 size_t numCmps = 0; 2253 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2254 I!=E; ++I) { 2255 // Single case counts one, case range - two. 2256 numCmps += (I->Low == I->High ? 1 : 2); 2257 } 2258 2259 // Count unique destinations 2260 SmallSet<MachineBasicBlock*, 4> Dests; 2261 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2262 Dests.insert(I->BB); 2263 if (Dests.size() > 3) 2264 // Don't bother the code below, if there are too much unique destinations 2265 return false; 2266 } 2267 DEBUG(dbgs() << "Total number of unique destinations: " 2268 << Dests.size() << '\n' 2269 << "Total number of comparisons: " << numCmps << '\n'); 2270 2271 // Compute span of values. 2272 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2273 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2274 APInt cmpRange = maxValue - minValue; 2275 2276 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2277 << "Low bound: " << minValue << '\n' 2278 << "High bound: " << maxValue << '\n'); 2279 2280 if (cmpRange.uge(IntPtrBits) || 2281 (!(Dests.size() == 1 && numCmps >= 3) && 2282 !(Dests.size() == 2 && numCmps >= 5) && 2283 !(Dests.size() >= 3 && numCmps >= 6))) 2284 return false; 2285 2286 DEBUG(dbgs() << "Emitting bit tests\n"); 2287 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2288 2289 // Optimize the case where all the case values fit in a 2290 // word without having to subtract minValue. In this case, 2291 // we can optimize away the subtraction. 2292 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2293 cmpRange = maxValue; 2294 } else { 2295 lowBound = minValue; 2296 } 2297 2298 CaseBitsVector CasesBits; 2299 unsigned i, count = 0; 2300 2301 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2302 MachineBasicBlock* Dest = I->BB; 2303 for (i = 0; i < count; ++i) 2304 if (Dest == CasesBits[i].BB) 2305 break; 2306 2307 if (i == count) { 2308 assert((count < 3) && "Too much destinations to test!"); 2309 CasesBits.push_back(CaseBits(0, Dest, 0)); 2310 count++; 2311 } 2312 2313 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2314 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2315 2316 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2317 uint64_t hi = (highValue - lowBound).getZExtValue(); 2318 2319 for (uint64_t j = lo; j <= hi; j++) { 2320 CasesBits[i].Mask |= 1ULL << j; 2321 CasesBits[i].Bits++; 2322 } 2323 2324 } 2325 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2326 2327 BitTestInfo BTC; 2328 2329 // Figure out which block is immediately after the current one. 2330 MachineFunction::iterator BBI = CR.CaseBB; 2331 ++BBI; 2332 2333 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2334 2335 DEBUG(dbgs() << "Cases:\n"); 2336 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2337 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2338 << ", Bits: " << CasesBits[i].Bits 2339 << ", BB: " << CasesBits[i].BB << '\n'); 2340 2341 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2342 CurMF->insert(BBI, CaseBB); 2343 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2344 CaseBB, 2345 CasesBits[i].BB)); 2346 2347 // Put SV in a virtual register to make it available from the new blocks. 2348 ExportFromCurrentBlock(SV); 2349 } 2350 2351 BitTestBlock BTB(lowBound, cmpRange, SV, 2352 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2353 CR.CaseBB, Default, BTC); 2354 2355 if (CR.CaseBB == SwitchBB) 2356 visitBitTestHeader(BTB, SwitchBB); 2357 2358 BitTestCases.push_back(BTB); 2359 2360 return true; 2361} 2362 2363/// Clusterify - Transform simple list of Cases into list of CaseRange's 2364size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2365 const SwitchInst& SI) { 2366 size_t numCmps = 0; 2367 2368 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2369 // Start with "simple" cases 2370 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2371 BasicBlock *SuccBB = SI.getSuccessor(i); 2372 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2373 2374 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0; 2375 2376 Cases.push_back(Case(SI.getSuccessorValue(i), 2377 SI.getSuccessorValue(i), 2378 SMBB, ExtraWeight)); 2379 } 2380 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2381 2382 // Merge case into clusters 2383 if (Cases.size() >= 2) 2384 // Must recompute end() each iteration because it may be 2385 // invalidated by erase if we hold on to it 2386 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2387 J != Cases.end(); ) { 2388 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2389 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2390 MachineBasicBlock* nextBB = J->BB; 2391 MachineBasicBlock* currentBB = I->BB; 2392 2393 // If the two neighboring cases go to the same destination, merge them 2394 // into a single case. 2395 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2396 I->High = J->High; 2397 J = Cases.erase(J); 2398 2399 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) { 2400 uint32_t CurWeight = currentBB->getBasicBlock() ? 2401 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16; 2402 uint32_t NextWeight = nextBB->getBasicBlock() ? 2403 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16; 2404 2405 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(), 2406 CurWeight + NextWeight); 2407 } 2408 } else { 2409 I = J++; 2410 } 2411 } 2412 2413 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2414 if (I->Low != I->High) 2415 // A range counts double, since it requires two compares. 2416 ++numCmps; 2417 } 2418 2419 return numCmps; 2420} 2421 2422void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2423 MachineBasicBlock *Last) { 2424 // Update JTCases. 2425 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2426 if (JTCases[i].first.HeaderBB == First) 2427 JTCases[i].first.HeaderBB = Last; 2428 2429 // Update BitTestCases. 2430 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2431 if (BitTestCases[i].Parent == First) 2432 BitTestCases[i].Parent = Last; 2433} 2434 2435void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2436 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2437 2438 // Figure out which block is immediately after the current one. 2439 MachineBasicBlock *NextBlock = 0; 2440 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2441 2442 // If there is only the default destination, branch to it if it is not the 2443 // next basic block. Otherwise, just fall through. 2444 if (SI.getNumOperands() == 2) { 2445 // Update machine-CFG edges. 2446 2447 // If this is not a fall-through branch, emit the branch. 2448 SwitchMBB->addSuccessor(Default); 2449 if (Default != NextBlock) 2450 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2451 MVT::Other, getControlRoot(), 2452 DAG.getBasicBlock(Default))); 2453 2454 return; 2455 } 2456 2457 // If there are any non-default case statements, create a vector of Cases 2458 // representing each one, and sort the vector so that we can efficiently 2459 // create a binary search tree from them. 2460 CaseVector Cases; 2461 size_t numCmps = Clusterify(Cases, SI); 2462 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2463 << ". Total compares: " << numCmps << '\n'); 2464 numCmps = 0; 2465 2466 // Get the Value to be switched on and default basic blocks, which will be 2467 // inserted into CaseBlock records, representing basic blocks in the binary 2468 // search tree. 2469 const Value *SV = SI.getOperand(0); 2470 2471 // Push the initial CaseRec onto the worklist 2472 CaseRecVector WorkList; 2473 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2474 CaseRange(Cases.begin(),Cases.end()))); 2475 2476 while (!WorkList.empty()) { 2477 // Grab a record representing a case range to process off the worklist 2478 CaseRec CR = WorkList.back(); 2479 WorkList.pop_back(); 2480 2481 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2482 continue; 2483 2484 // If the range has few cases (two or less) emit a series of specific 2485 // tests. 2486 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2487 continue; 2488 2489 // If the switch has more than 5 blocks, and at least 40% dense, and the 2490 // target supports indirect branches, then emit a jump table rather than 2491 // lowering the switch to a binary tree of conditional branches. 2492 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2493 continue; 2494 2495 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2496 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2497 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2498 } 2499} 2500 2501void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2502 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2503 2504 // Update machine-CFG edges with unique successors. 2505 SmallVector<BasicBlock*, 32> succs; 2506 succs.reserve(I.getNumSuccessors()); 2507 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2508 succs.push_back(I.getSuccessor(i)); 2509 array_pod_sort(succs.begin(), succs.end()); 2510 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2511 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2512 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2513 addSuccessorWithWeight(IndirectBrMBB, Succ); 2514 } 2515 2516 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2517 MVT::Other, getControlRoot(), 2518 getValue(I.getAddress()))); 2519} 2520 2521void SelectionDAGBuilder::visitFSub(const User &I) { 2522 // -0.0 - X --> fneg 2523 Type *Ty = I.getType(); 2524 if (isa<Constant>(I.getOperand(0)) && 2525 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2526 SDValue Op2 = getValue(I.getOperand(1)); 2527 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2528 Op2.getValueType(), Op2)); 2529 return; 2530 } 2531 2532 visitBinary(I, ISD::FSUB); 2533} 2534 2535void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2536 SDValue Op1 = getValue(I.getOperand(0)); 2537 SDValue Op2 = getValue(I.getOperand(1)); 2538 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2539 Op1.getValueType(), Op1, Op2)); 2540} 2541 2542void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2543 SDValue Op1 = getValue(I.getOperand(0)); 2544 SDValue Op2 = getValue(I.getOperand(1)); 2545 2546 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2547 2548 // Coerce the shift amount to the right type if we can. 2549 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2550 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2551 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2552 DebugLoc DL = getCurDebugLoc(); 2553 2554 // If the operand is smaller than the shift count type, promote it. 2555 if (ShiftSize > Op2Size) 2556 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2557 2558 // If the operand is larger than the shift count type but the shift 2559 // count type has enough bits to represent any shift value, truncate 2560 // it now. This is a common case and it exposes the truncate to 2561 // optimization early. 2562 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2563 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2564 // Otherwise we'll need to temporarily settle for some other convenient 2565 // type. Type legalization will make adjustments once the shiftee is split. 2566 else 2567 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2568 } 2569 2570 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2571 Op1.getValueType(), Op1, Op2)); 2572} 2573 2574void SelectionDAGBuilder::visitSDiv(const User &I) { 2575 SDValue Op1 = getValue(I.getOperand(0)); 2576 SDValue Op2 = getValue(I.getOperand(1)); 2577 2578 // Turn exact SDivs into multiplications. 2579 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2580 // exact bit. 2581 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2582 !isa<ConstantSDNode>(Op1) && 2583 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2584 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2585 else 2586 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2587 Op1, Op2)); 2588} 2589 2590void SelectionDAGBuilder::visitICmp(const User &I) { 2591 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2592 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2593 predicate = IC->getPredicate(); 2594 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2595 predicate = ICmpInst::Predicate(IC->getPredicate()); 2596 SDValue Op1 = getValue(I.getOperand(0)); 2597 SDValue Op2 = getValue(I.getOperand(1)); 2598 ISD::CondCode Opcode = getICmpCondCode(predicate); 2599 2600 EVT DestVT = TLI.getValueType(I.getType()); 2601 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2602} 2603 2604void SelectionDAGBuilder::visitFCmp(const User &I) { 2605 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2606 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2607 predicate = FC->getPredicate(); 2608 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2609 predicate = FCmpInst::Predicate(FC->getPredicate()); 2610 SDValue Op1 = getValue(I.getOperand(0)); 2611 SDValue Op2 = getValue(I.getOperand(1)); 2612 ISD::CondCode Condition = getFCmpCondCode(predicate); 2613 EVT DestVT = TLI.getValueType(I.getType()); 2614 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2615} 2616 2617void SelectionDAGBuilder::visitSelect(const User &I) { 2618 SmallVector<EVT, 4> ValueVTs; 2619 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2620 unsigned NumValues = ValueVTs.size(); 2621 if (NumValues == 0) return; 2622 2623 SmallVector<SDValue, 4> Values(NumValues); 2624 SDValue Cond = getValue(I.getOperand(0)); 2625 SDValue TrueVal = getValue(I.getOperand(1)); 2626 SDValue FalseVal = getValue(I.getOperand(2)); 2627 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2628 ISD::VSELECT : ISD::SELECT; 2629 2630 for (unsigned i = 0; i != NumValues; ++i) 2631 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2632 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2633 Cond, 2634 SDValue(TrueVal.getNode(), 2635 TrueVal.getResNo() + i), 2636 SDValue(FalseVal.getNode(), 2637 FalseVal.getResNo() + i)); 2638 2639 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2640 DAG.getVTList(&ValueVTs[0], NumValues), 2641 &Values[0], NumValues)); 2642} 2643 2644void SelectionDAGBuilder::visitTrunc(const User &I) { 2645 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2646 SDValue N = getValue(I.getOperand(0)); 2647 EVT DestVT = TLI.getValueType(I.getType()); 2648 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2649} 2650 2651void SelectionDAGBuilder::visitZExt(const User &I) { 2652 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2653 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2654 SDValue N = getValue(I.getOperand(0)); 2655 EVT DestVT = TLI.getValueType(I.getType()); 2656 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2657} 2658 2659void SelectionDAGBuilder::visitSExt(const User &I) { 2660 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2661 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2662 SDValue N = getValue(I.getOperand(0)); 2663 EVT DestVT = TLI.getValueType(I.getType()); 2664 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2665} 2666 2667void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2668 // FPTrunc is never a no-op cast, no need to check 2669 SDValue N = getValue(I.getOperand(0)); 2670 EVT DestVT = TLI.getValueType(I.getType()); 2671 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2672 DestVT, N, DAG.getIntPtrConstant(0))); 2673} 2674 2675void SelectionDAGBuilder::visitFPExt(const User &I){ 2676 // FPTrunc is never a no-op cast, no need to check 2677 SDValue N = getValue(I.getOperand(0)); 2678 EVT DestVT = TLI.getValueType(I.getType()); 2679 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2680} 2681 2682void SelectionDAGBuilder::visitFPToUI(const User &I) { 2683 // FPToUI is never a no-op cast, no need to check 2684 SDValue N = getValue(I.getOperand(0)); 2685 EVT DestVT = TLI.getValueType(I.getType()); 2686 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2687} 2688 2689void SelectionDAGBuilder::visitFPToSI(const User &I) { 2690 // FPToSI is never a no-op cast, no need to check 2691 SDValue N = getValue(I.getOperand(0)); 2692 EVT DestVT = TLI.getValueType(I.getType()); 2693 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2694} 2695 2696void SelectionDAGBuilder::visitUIToFP(const User &I) { 2697 // UIToFP is never a no-op cast, no need to check 2698 SDValue N = getValue(I.getOperand(0)); 2699 EVT DestVT = TLI.getValueType(I.getType()); 2700 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2701} 2702 2703void SelectionDAGBuilder::visitSIToFP(const User &I){ 2704 // SIToFP is never a no-op cast, no need to check 2705 SDValue N = getValue(I.getOperand(0)); 2706 EVT DestVT = TLI.getValueType(I.getType()); 2707 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2708} 2709 2710void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2711 // What to do depends on the size of the integer and the size of the pointer. 2712 // We can either truncate, zero extend, or no-op, accordingly. 2713 SDValue N = getValue(I.getOperand(0)); 2714 EVT DestVT = TLI.getValueType(I.getType()); 2715 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2716} 2717 2718void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2719 // What to do depends on the size of the integer and the size of the pointer. 2720 // We can either truncate, zero extend, or no-op, accordingly. 2721 SDValue N = getValue(I.getOperand(0)); 2722 EVT DestVT = TLI.getValueType(I.getType()); 2723 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2724} 2725 2726void SelectionDAGBuilder::visitBitCast(const User &I) { 2727 SDValue N = getValue(I.getOperand(0)); 2728 EVT DestVT = TLI.getValueType(I.getType()); 2729 2730 // BitCast assures us that source and destination are the same size so this is 2731 // either a BITCAST or a no-op. 2732 if (DestVT != N.getValueType()) 2733 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2734 DestVT, N)); // convert types. 2735 else 2736 setValue(&I, N); // noop cast. 2737} 2738 2739void SelectionDAGBuilder::visitInsertElement(const User &I) { 2740 SDValue InVec = getValue(I.getOperand(0)); 2741 SDValue InVal = getValue(I.getOperand(1)); 2742 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2743 TLI.getPointerTy(), 2744 getValue(I.getOperand(2))); 2745 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2746 TLI.getValueType(I.getType()), 2747 InVec, InVal, InIdx)); 2748} 2749 2750void SelectionDAGBuilder::visitExtractElement(const User &I) { 2751 SDValue InVec = getValue(I.getOperand(0)); 2752 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2753 TLI.getPointerTy(), 2754 getValue(I.getOperand(1))); 2755 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2756 TLI.getValueType(I.getType()), InVec, InIdx)); 2757} 2758 2759// Utility for visitShuffleVector - Returns true if the mask is mask starting 2760// from SIndx and increasing to the element length (undefs are allowed). 2761static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2762 unsigned MaskNumElts = Mask.size(); 2763 for (unsigned i = 0; i != MaskNumElts; ++i) 2764 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2765 return false; 2766 return true; 2767} 2768 2769void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2770 SmallVector<int, 8> Mask; 2771 SDValue Src1 = getValue(I.getOperand(0)); 2772 SDValue Src2 = getValue(I.getOperand(1)); 2773 2774 // Convert the ConstantVector mask operand into an array of ints, with -1 2775 // representing undef values. 2776 SmallVector<Constant*, 8> MaskElts; 2777 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2778 unsigned MaskNumElts = MaskElts.size(); 2779 for (unsigned i = 0; i != MaskNumElts; ++i) { 2780 if (isa<UndefValue>(MaskElts[i])) 2781 Mask.push_back(-1); 2782 else 2783 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2784 } 2785 2786 EVT VT = TLI.getValueType(I.getType()); 2787 EVT SrcVT = Src1.getValueType(); 2788 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2789 2790 if (SrcNumElts == MaskNumElts) { 2791 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2792 &Mask[0])); 2793 return; 2794 } 2795 2796 // Normalize the shuffle vector since mask and vector length don't match. 2797 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2798 // Mask is longer than the source vectors and is a multiple of the source 2799 // vectors. We can use concatenate vector to make the mask and vectors 2800 // lengths match. 2801 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2802 // The shuffle is concatenating two vectors together. 2803 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2804 VT, Src1, Src2)); 2805 return; 2806 } 2807 2808 // Pad both vectors with undefs to make them the same length as the mask. 2809 unsigned NumConcat = MaskNumElts / SrcNumElts; 2810 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2811 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2812 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2813 2814 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2815 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2816 MOps1[0] = Src1; 2817 MOps2[0] = Src2; 2818 2819 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2820 getCurDebugLoc(), VT, 2821 &MOps1[0], NumConcat); 2822 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2823 getCurDebugLoc(), VT, 2824 &MOps2[0], NumConcat); 2825 2826 // Readjust mask for new input vector length. 2827 SmallVector<int, 8> MappedOps; 2828 for (unsigned i = 0; i != MaskNumElts; ++i) { 2829 int Idx = Mask[i]; 2830 if (Idx < (int)SrcNumElts) 2831 MappedOps.push_back(Idx); 2832 else 2833 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2834 } 2835 2836 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2837 &MappedOps[0])); 2838 return; 2839 } 2840 2841 if (SrcNumElts > MaskNumElts) { 2842 // Analyze the access pattern of the vector to see if we can extract 2843 // two subvectors and do the shuffle. The analysis is done by calculating 2844 // the range of elements the mask access on both vectors. 2845 int MinRange[2] = { static_cast<int>(SrcNumElts+1), 2846 static_cast<int>(SrcNumElts+1)}; 2847 int MaxRange[2] = {-1, -1}; 2848 2849 for (unsigned i = 0; i != MaskNumElts; ++i) { 2850 int Idx = Mask[i]; 2851 int Input = 0; 2852 if (Idx < 0) 2853 continue; 2854 2855 if (Idx >= (int)SrcNumElts) { 2856 Input = 1; 2857 Idx -= SrcNumElts; 2858 } 2859 if (Idx > MaxRange[Input]) 2860 MaxRange[Input] = Idx; 2861 if (Idx < MinRange[Input]) 2862 MinRange[Input] = Idx; 2863 } 2864 2865 // Check if the access is smaller than the vector size and can we find 2866 // a reasonable extract index. 2867 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2868 // Extract. 2869 int StartIdx[2]; // StartIdx to extract from 2870 for (int Input=0; Input < 2; ++Input) { 2871 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2872 RangeUse[Input] = 0; // Unused 2873 StartIdx[Input] = 0; 2874 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2875 // Fits within range but we should see if we can find a good 2876 // start index that is a multiple of the mask length. 2877 if (MaxRange[Input] < (int)MaskNumElts) { 2878 RangeUse[Input] = 1; // Extract from beginning of the vector 2879 StartIdx[Input] = 0; 2880 } else { 2881 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2882 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2883 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2884 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2885 } 2886 } 2887 } 2888 2889 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2890 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2891 return; 2892 } 2893 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2894 // Extract appropriate subvector and generate a vector shuffle 2895 for (int Input=0; Input < 2; ++Input) { 2896 SDValue &Src = Input == 0 ? Src1 : Src2; 2897 if (RangeUse[Input] == 0) 2898 Src = DAG.getUNDEF(VT); 2899 else 2900 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2901 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2902 } 2903 2904 // Calculate new mask. 2905 SmallVector<int, 8> MappedOps; 2906 for (unsigned i = 0; i != MaskNumElts; ++i) { 2907 int Idx = Mask[i]; 2908 if (Idx < 0) 2909 MappedOps.push_back(Idx); 2910 else if (Idx < (int)SrcNumElts) 2911 MappedOps.push_back(Idx - StartIdx[0]); 2912 else 2913 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2914 } 2915 2916 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2917 &MappedOps[0])); 2918 return; 2919 } 2920 } 2921 2922 // We can't use either concat vectors or extract subvectors so fall back to 2923 // replacing the shuffle with extract and build vector. 2924 // to insert and build vector. 2925 EVT EltVT = VT.getVectorElementType(); 2926 EVT PtrVT = TLI.getPointerTy(); 2927 SmallVector<SDValue,8> Ops; 2928 for (unsigned i = 0; i != MaskNumElts; ++i) { 2929 if (Mask[i] < 0) { 2930 Ops.push_back(DAG.getUNDEF(EltVT)); 2931 } else { 2932 int Idx = Mask[i]; 2933 SDValue Res; 2934 2935 if (Idx < (int)SrcNumElts) 2936 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2937 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2938 else 2939 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2940 EltVT, Src2, 2941 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2942 2943 Ops.push_back(Res); 2944 } 2945 } 2946 2947 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2948 VT, &Ops[0], Ops.size())); 2949} 2950 2951void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2952 const Value *Op0 = I.getOperand(0); 2953 const Value *Op1 = I.getOperand(1); 2954 Type *AggTy = I.getType(); 2955 Type *ValTy = Op1->getType(); 2956 bool IntoUndef = isa<UndefValue>(Op0); 2957 bool FromUndef = isa<UndefValue>(Op1); 2958 2959 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 2960 2961 SmallVector<EVT, 4> AggValueVTs; 2962 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2963 SmallVector<EVT, 4> ValValueVTs; 2964 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2965 2966 unsigned NumAggValues = AggValueVTs.size(); 2967 unsigned NumValValues = ValValueVTs.size(); 2968 SmallVector<SDValue, 4> Values(NumAggValues); 2969 2970 SDValue Agg = getValue(Op0); 2971 unsigned i = 0; 2972 // Copy the beginning value(s) from the original aggregate. 2973 for (; i != LinearIndex; ++i) 2974 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2975 SDValue(Agg.getNode(), Agg.getResNo() + i); 2976 // Copy values from the inserted value(s). 2977 if (NumValValues) { 2978 SDValue Val = getValue(Op1); 2979 for (; i != LinearIndex + NumValValues; ++i) 2980 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2981 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2982 } 2983 // Copy remaining value(s) from the original aggregate. 2984 for (; i != NumAggValues; ++i) 2985 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2986 SDValue(Agg.getNode(), Agg.getResNo() + i); 2987 2988 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2989 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2990 &Values[0], NumAggValues)); 2991} 2992 2993void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2994 const Value *Op0 = I.getOperand(0); 2995 Type *AggTy = Op0->getType(); 2996 Type *ValTy = I.getType(); 2997 bool OutOfUndef = isa<UndefValue>(Op0); 2998 2999 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3000 3001 SmallVector<EVT, 4> ValValueVTs; 3002 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3003 3004 unsigned NumValValues = ValValueVTs.size(); 3005 3006 // Ignore a extractvalue that produces an empty object 3007 if (!NumValValues) { 3008 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3009 return; 3010 } 3011 3012 SmallVector<SDValue, 4> Values(NumValValues); 3013 3014 SDValue Agg = getValue(Op0); 3015 // Copy out the selected value(s). 3016 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3017 Values[i - LinearIndex] = 3018 OutOfUndef ? 3019 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3020 SDValue(Agg.getNode(), Agg.getResNo() + i); 3021 3022 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3023 DAG.getVTList(&ValValueVTs[0], NumValValues), 3024 &Values[0], NumValValues)); 3025} 3026 3027void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3028 SDValue N = getValue(I.getOperand(0)); 3029 Type *Ty = I.getOperand(0)->getType(); 3030 3031 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3032 OI != E; ++OI) { 3033 const Value *Idx = *OI; 3034 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3035 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3036 if (Field) { 3037 // N = N + Offset 3038 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3039 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3040 DAG.getIntPtrConstant(Offset)); 3041 } 3042 3043 Ty = StTy->getElementType(Field); 3044 } else { 3045 Ty = cast<SequentialType>(Ty)->getElementType(); 3046 3047 // If this is a constant subscript, handle it quickly. 3048 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3049 if (CI->isZero()) continue; 3050 uint64_t Offs = 3051 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3052 SDValue OffsVal; 3053 EVT PTy = TLI.getPointerTy(); 3054 unsigned PtrBits = PTy.getSizeInBits(); 3055 if (PtrBits < 64) 3056 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3057 TLI.getPointerTy(), 3058 DAG.getConstant(Offs, MVT::i64)); 3059 else 3060 OffsVal = DAG.getIntPtrConstant(Offs); 3061 3062 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3063 OffsVal); 3064 continue; 3065 } 3066 3067 // N = N + Idx * ElementSize; 3068 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3069 TD->getTypeAllocSize(Ty)); 3070 SDValue IdxN = getValue(Idx); 3071 3072 // If the index is smaller or larger than intptr_t, truncate or extend 3073 // it. 3074 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3075 3076 // If this is a multiply by a power of two, turn it into a shl 3077 // immediately. This is a very common case. 3078 if (ElementSize != 1) { 3079 if (ElementSize.isPowerOf2()) { 3080 unsigned Amt = ElementSize.logBase2(); 3081 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3082 N.getValueType(), IdxN, 3083 DAG.getConstant(Amt, TLI.getPointerTy())); 3084 } else { 3085 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3086 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3087 N.getValueType(), IdxN, Scale); 3088 } 3089 } 3090 3091 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3092 N.getValueType(), N, IdxN); 3093 } 3094 } 3095 3096 setValue(&I, N); 3097} 3098 3099void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3100 // If this is a fixed sized alloca in the entry block of the function, 3101 // allocate it statically on the stack. 3102 if (FuncInfo.StaticAllocaMap.count(&I)) 3103 return; // getValue will auto-populate this. 3104 3105 Type *Ty = I.getAllocatedType(); 3106 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3107 unsigned Align = 3108 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3109 I.getAlignment()); 3110 3111 SDValue AllocSize = getValue(I.getArraySize()); 3112 3113 EVT IntPtr = TLI.getPointerTy(); 3114 if (AllocSize.getValueType() != IntPtr) 3115 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3116 3117 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3118 AllocSize, 3119 DAG.getConstant(TySize, IntPtr)); 3120 3121 // Handle alignment. If the requested alignment is less than or equal to 3122 // the stack alignment, ignore it. If the size is greater than or equal to 3123 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3124 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3125 if (Align <= StackAlign) 3126 Align = 0; 3127 3128 // Round the size of the allocation up to the stack alignment size 3129 // by add SA-1 to the size. 3130 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3131 AllocSize.getValueType(), AllocSize, 3132 DAG.getIntPtrConstant(StackAlign-1)); 3133 3134 // Mask out the low bits for alignment purposes. 3135 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3136 AllocSize.getValueType(), AllocSize, 3137 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3138 3139 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3140 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3141 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3142 VTs, Ops, 3); 3143 setValue(&I, DSA); 3144 DAG.setRoot(DSA.getValue(1)); 3145 3146 // Inform the Frame Information that we have just allocated a variable-sized 3147 // object. 3148 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3149} 3150 3151void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3152 if (I.isAtomic()) 3153 return visitAtomicLoad(I); 3154 3155 const Value *SV = I.getOperand(0); 3156 SDValue Ptr = getValue(SV); 3157 3158 Type *Ty = I.getType(); 3159 3160 bool isVolatile = I.isVolatile(); 3161 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3162 unsigned Alignment = I.getAlignment(); 3163 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3164 3165 SmallVector<EVT, 4> ValueVTs; 3166 SmallVector<uint64_t, 4> Offsets; 3167 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3168 unsigned NumValues = ValueVTs.size(); 3169 if (NumValues == 0) 3170 return; 3171 3172 SDValue Root; 3173 bool ConstantMemory = false; 3174 if (I.isVolatile() || NumValues > MaxParallelChains) 3175 // Serialize volatile loads with other side effects. 3176 Root = getRoot(); 3177 else if (AA->pointsToConstantMemory( 3178 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3179 // Do not serialize (non-volatile) loads of constant memory with anything. 3180 Root = DAG.getEntryNode(); 3181 ConstantMemory = true; 3182 } else { 3183 // Do not serialize non-volatile loads against each other. 3184 Root = DAG.getRoot(); 3185 } 3186 3187 SmallVector<SDValue, 4> Values(NumValues); 3188 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3189 NumValues)); 3190 EVT PtrVT = Ptr.getValueType(); 3191 unsigned ChainI = 0; 3192 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3193 // Serializing loads here may result in excessive register pressure, and 3194 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3195 // could recover a bit by hoisting nodes upward in the chain by recognizing 3196 // they are side-effect free or do not alias. The optimizer should really 3197 // avoid this case by converting large object/array copies to llvm.memcpy 3198 // (MaxParallelChains should always remain as failsafe). 3199 if (ChainI == MaxParallelChains) { 3200 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3201 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3202 MVT::Other, &Chains[0], ChainI); 3203 Root = Chain; 3204 ChainI = 0; 3205 } 3206 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3207 PtrVT, Ptr, 3208 DAG.getConstant(Offsets[i], PtrVT)); 3209 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3210 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3211 isNonTemporal, Alignment, TBAAInfo); 3212 3213 Values[i] = L; 3214 Chains[ChainI] = L.getValue(1); 3215 } 3216 3217 if (!ConstantMemory) { 3218 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3219 MVT::Other, &Chains[0], ChainI); 3220 if (isVolatile) 3221 DAG.setRoot(Chain); 3222 else 3223 PendingLoads.push_back(Chain); 3224 } 3225 3226 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3227 DAG.getVTList(&ValueVTs[0], NumValues), 3228 &Values[0], NumValues)); 3229} 3230 3231void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3232 if (I.isAtomic()) 3233 return visitAtomicStore(I); 3234 3235 const Value *SrcV = I.getOperand(0); 3236 const Value *PtrV = I.getOperand(1); 3237 3238 SmallVector<EVT, 4> ValueVTs; 3239 SmallVector<uint64_t, 4> Offsets; 3240 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3241 unsigned NumValues = ValueVTs.size(); 3242 if (NumValues == 0) 3243 return; 3244 3245 // Get the lowered operands. Note that we do this after 3246 // checking if NumResults is zero, because with zero results 3247 // the operands won't have values in the map. 3248 SDValue Src = getValue(SrcV); 3249 SDValue Ptr = getValue(PtrV); 3250 3251 SDValue Root = getRoot(); 3252 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3253 NumValues)); 3254 EVT PtrVT = Ptr.getValueType(); 3255 bool isVolatile = I.isVolatile(); 3256 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3257 unsigned Alignment = I.getAlignment(); 3258 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3259 3260 unsigned ChainI = 0; 3261 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3262 // See visitLoad comments. 3263 if (ChainI == MaxParallelChains) { 3264 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3265 MVT::Other, &Chains[0], ChainI); 3266 Root = Chain; 3267 ChainI = 0; 3268 } 3269 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3270 DAG.getConstant(Offsets[i], PtrVT)); 3271 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3272 SDValue(Src.getNode(), Src.getResNo() + i), 3273 Add, MachinePointerInfo(PtrV, Offsets[i]), 3274 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3275 Chains[ChainI] = St; 3276 } 3277 3278 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3279 MVT::Other, &Chains[0], ChainI); 3280 ++SDNodeOrder; 3281 AssignOrderingToNode(StoreNode.getNode()); 3282 DAG.setRoot(StoreNode); 3283} 3284 3285static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3286 SynchronizationScope Scope, 3287 bool Before, DebugLoc dl, 3288 SelectionDAG &DAG, 3289 const TargetLowering &TLI) { 3290 // Fence, if necessary 3291 if (Before) { 3292 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3293 Order = Release; 3294 else if (Order == Acquire || Order == Monotonic) 3295 return Chain; 3296 } else { 3297 if (Order == AcquireRelease) 3298 Order = Acquire; 3299 else if (Order == Release || Order == Monotonic) 3300 return Chain; 3301 } 3302 SDValue Ops[3]; 3303 Ops[0] = Chain; 3304 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3305 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3306 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3307} 3308 3309void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3310 DebugLoc dl = getCurDebugLoc(); 3311 AtomicOrdering Order = I.getOrdering(); 3312 SynchronizationScope Scope = I.getSynchScope(); 3313 3314 SDValue InChain = getRoot(); 3315 3316 if (TLI.getInsertFencesForAtomic()) 3317 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3318 DAG, TLI); 3319 3320 SDValue L = 3321 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3322 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3323 InChain, 3324 getValue(I.getPointerOperand()), 3325 getValue(I.getCompareOperand()), 3326 getValue(I.getNewValOperand()), 3327 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3328 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3329 Scope); 3330 3331 SDValue OutChain = L.getValue(1); 3332 3333 if (TLI.getInsertFencesForAtomic()) 3334 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3335 DAG, TLI); 3336 3337 setValue(&I, L); 3338 DAG.setRoot(OutChain); 3339} 3340 3341void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3342 DebugLoc dl = getCurDebugLoc(); 3343 ISD::NodeType NT; 3344 switch (I.getOperation()) { 3345 default: llvm_unreachable("Unknown atomicrmw operation"); return; 3346 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3347 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3348 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3349 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3350 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3351 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3352 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3353 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3354 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3355 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3356 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3357 } 3358 AtomicOrdering Order = I.getOrdering(); 3359 SynchronizationScope Scope = I.getSynchScope(); 3360 3361 SDValue InChain = getRoot(); 3362 3363 if (TLI.getInsertFencesForAtomic()) 3364 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3365 DAG, TLI); 3366 3367 SDValue L = 3368 DAG.getAtomic(NT, dl, 3369 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3370 InChain, 3371 getValue(I.getPointerOperand()), 3372 getValue(I.getValOperand()), 3373 I.getPointerOperand(), 0 /* Alignment */, 3374 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3375 Scope); 3376 3377 SDValue OutChain = L.getValue(1); 3378 3379 if (TLI.getInsertFencesForAtomic()) 3380 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3381 DAG, TLI); 3382 3383 setValue(&I, L); 3384 DAG.setRoot(OutChain); 3385} 3386 3387void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3388 DebugLoc dl = getCurDebugLoc(); 3389 SDValue Ops[3]; 3390 Ops[0] = getRoot(); 3391 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3392 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3393 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3394} 3395 3396void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3397 DebugLoc dl = getCurDebugLoc(); 3398 AtomicOrdering Order = I.getOrdering(); 3399 SynchronizationScope Scope = I.getSynchScope(); 3400 3401 SDValue InChain = getRoot(); 3402 3403 EVT VT = EVT::getEVT(I.getType()); 3404 3405 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3406 report_fatal_error("Cannot generate unaligned atomic load"); 3407 3408 SDValue L = 3409 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3410 getValue(I.getPointerOperand()), 3411 I.getPointerOperand(), I.getAlignment(), 3412 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3413 Scope); 3414 3415 SDValue OutChain = L.getValue(1); 3416 3417 if (TLI.getInsertFencesForAtomic()) 3418 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3419 DAG, TLI); 3420 3421 setValue(&I, L); 3422 DAG.setRoot(OutChain); 3423} 3424 3425void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3426 DebugLoc dl = getCurDebugLoc(); 3427 3428 AtomicOrdering Order = I.getOrdering(); 3429 SynchronizationScope Scope = I.getSynchScope(); 3430 3431 SDValue InChain = getRoot(); 3432 3433 EVT VT = EVT::getEVT(I.getValueOperand()->getType()); 3434 3435 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3436 report_fatal_error("Cannot generate unaligned atomic store"); 3437 3438 if (TLI.getInsertFencesForAtomic()) 3439 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3440 DAG, TLI); 3441 3442 SDValue OutChain = 3443 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3444 InChain, 3445 getValue(I.getPointerOperand()), 3446 getValue(I.getValueOperand()), 3447 I.getPointerOperand(), I.getAlignment(), 3448 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3449 Scope); 3450 3451 if (TLI.getInsertFencesForAtomic()) 3452 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3453 DAG, TLI); 3454 3455 DAG.setRoot(OutChain); 3456} 3457 3458/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3459/// node. 3460void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3461 unsigned Intrinsic) { 3462 bool HasChain = !I.doesNotAccessMemory(); 3463 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3464 3465 // Build the operand list. 3466 SmallVector<SDValue, 8> Ops; 3467 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3468 if (OnlyLoad) { 3469 // We don't need to serialize loads against other loads. 3470 Ops.push_back(DAG.getRoot()); 3471 } else { 3472 Ops.push_back(getRoot()); 3473 } 3474 } 3475 3476 // Info is set by getTgtMemInstrinsic 3477 TargetLowering::IntrinsicInfo Info; 3478 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3479 3480 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3481 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3482 Info.opc == ISD::INTRINSIC_W_CHAIN) 3483 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3484 3485 // Add all operands of the call to the operand list. 3486 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3487 SDValue Op = getValue(I.getArgOperand(i)); 3488 assert(TLI.isTypeLegal(Op.getValueType()) && 3489 "Intrinsic uses a non-legal type?"); 3490 Ops.push_back(Op); 3491 } 3492 3493 SmallVector<EVT, 4> ValueVTs; 3494 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3495#ifndef NDEBUG 3496 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3497 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3498 "Intrinsic uses a non-legal type?"); 3499 } 3500#endif // NDEBUG 3501 3502 if (HasChain) 3503 ValueVTs.push_back(MVT::Other); 3504 3505 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3506 3507 // Create the node. 3508 SDValue Result; 3509 if (IsTgtIntrinsic) { 3510 // This is target intrinsic that touches memory 3511 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3512 VTs, &Ops[0], Ops.size(), 3513 Info.memVT, 3514 MachinePointerInfo(Info.ptrVal, Info.offset), 3515 Info.align, Info.vol, 3516 Info.readMem, Info.writeMem); 3517 } else if (!HasChain) { 3518 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3519 VTs, &Ops[0], Ops.size()); 3520 } else if (!I.getType()->isVoidTy()) { 3521 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3522 VTs, &Ops[0], Ops.size()); 3523 } else { 3524 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3525 VTs, &Ops[0], Ops.size()); 3526 } 3527 3528 if (HasChain) { 3529 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3530 if (OnlyLoad) 3531 PendingLoads.push_back(Chain); 3532 else 3533 DAG.setRoot(Chain); 3534 } 3535 3536 if (!I.getType()->isVoidTy()) { 3537 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3538 EVT VT = TLI.getValueType(PTy); 3539 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3540 } 3541 3542 setValue(&I, Result); 3543 } 3544} 3545 3546/// GetSignificand - Get the significand and build it into a floating-point 3547/// number with exponent of 1: 3548/// 3549/// Op = (Op & 0x007fffff) | 0x3f800000; 3550/// 3551/// where Op is the hexidecimal representation of floating point value. 3552static SDValue 3553GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3554 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3555 DAG.getConstant(0x007fffff, MVT::i32)); 3556 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3557 DAG.getConstant(0x3f800000, MVT::i32)); 3558 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3559} 3560 3561/// GetExponent - Get the exponent: 3562/// 3563/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3564/// 3565/// where Op is the hexidecimal representation of floating point value. 3566static SDValue 3567GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3568 DebugLoc dl) { 3569 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3570 DAG.getConstant(0x7f800000, MVT::i32)); 3571 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3572 DAG.getConstant(23, TLI.getPointerTy())); 3573 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3574 DAG.getConstant(127, MVT::i32)); 3575 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3576} 3577 3578/// getF32Constant - Get 32-bit floating point constant. 3579static SDValue 3580getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3581 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3582} 3583 3584/// Inlined utility function to implement binary input atomic intrinsics for 3585/// visitIntrinsicCall: I is a call instruction 3586/// Op is the associated NodeType for I 3587const char * 3588SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3589 ISD::NodeType Op) { 3590 SDValue Root = getRoot(); 3591 SDValue L = 3592 DAG.getAtomic(Op, getCurDebugLoc(), 3593 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3594 Root, 3595 getValue(I.getArgOperand(0)), 3596 getValue(I.getArgOperand(1)), 3597 I.getArgOperand(0), 0 /* Alignment */, 3598 Monotonic, CrossThread); 3599 setValue(&I, L); 3600 DAG.setRoot(L.getValue(1)); 3601 return 0; 3602} 3603 3604// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3605const char * 3606SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3607 SDValue Op1 = getValue(I.getArgOperand(0)); 3608 SDValue Op2 = getValue(I.getArgOperand(1)); 3609 3610 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3611 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3612 return 0; 3613} 3614 3615/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3616/// limited-precision mode. 3617void 3618SelectionDAGBuilder::visitExp(const CallInst &I) { 3619 SDValue result; 3620 DebugLoc dl = getCurDebugLoc(); 3621 3622 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3623 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3624 SDValue Op = getValue(I.getArgOperand(0)); 3625 3626 // Put the exponent in the right bit position for later addition to the 3627 // final result: 3628 // 3629 // #define LOG2OFe 1.4426950f 3630 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3631 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3632 getF32Constant(DAG, 0x3fb8aa3b)); 3633 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3634 3635 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3636 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3637 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3638 3639 // IntegerPartOfX <<= 23; 3640 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3641 DAG.getConstant(23, TLI.getPointerTy())); 3642 3643 if (LimitFloatPrecision <= 6) { 3644 // For floating-point precision of 6: 3645 // 3646 // TwoToFractionalPartOfX = 3647 // 0.997535578f + 3648 // (0.735607626f + 0.252464424f * x) * x; 3649 // 3650 // error 0.0144103317, which is 6 bits 3651 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3652 getF32Constant(DAG, 0x3e814304)); 3653 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3654 getF32Constant(DAG, 0x3f3c50c8)); 3655 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3656 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3657 getF32Constant(DAG, 0x3f7f5e7e)); 3658 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3659 3660 // Add the exponent into the result in integer domain. 3661 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3662 TwoToFracPartOfX, IntegerPartOfX); 3663 3664 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3665 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3666 // For floating-point precision of 12: 3667 // 3668 // TwoToFractionalPartOfX = 3669 // 0.999892986f + 3670 // (0.696457318f + 3671 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3672 // 3673 // 0.000107046256 error, which is 13 to 14 bits 3674 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3675 getF32Constant(DAG, 0x3da235e3)); 3676 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3677 getF32Constant(DAG, 0x3e65b8f3)); 3678 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3679 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3680 getF32Constant(DAG, 0x3f324b07)); 3681 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3682 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3683 getF32Constant(DAG, 0x3f7ff8fd)); 3684 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3685 3686 // Add the exponent into the result in integer domain. 3687 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3688 TwoToFracPartOfX, IntegerPartOfX); 3689 3690 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3691 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3692 // For floating-point precision of 18: 3693 // 3694 // TwoToFractionalPartOfX = 3695 // 0.999999982f + 3696 // (0.693148872f + 3697 // (0.240227044f + 3698 // (0.554906021e-1f + 3699 // (0.961591928e-2f + 3700 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3701 // 3702 // error 2.47208000*10^(-7), which is better than 18 bits 3703 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3704 getF32Constant(DAG, 0x3924b03e)); 3705 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3706 getF32Constant(DAG, 0x3ab24b87)); 3707 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3708 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3709 getF32Constant(DAG, 0x3c1d8c17)); 3710 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3711 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3712 getF32Constant(DAG, 0x3d634a1d)); 3713 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3714 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3715 getF32Constant(DAG, 0x3e75fe14)); 3716 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3717 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3718 getF32Constant(DAG, 0x3f317234)); 3719 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3720 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3721 getF32Constant(DAG, 0x3f800000)); 3722 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3723 MVT::i32, t13); 3724 3725 // Add the exponent into the result in integer domain. 3726 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3727 TwoToFracPartOfX, IntegerPartOfX); 3728 3729 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3730 } 3731 } else { 3732 // No special expansion. 3733 result = DAG.getNode(ISD::FEXP, dl, 3734 getValue(I.getArgOperand(0)).getValueType(), 3735 getValue(I.getArgOperand(0))); 3736 } 3737 3738 setValue(&I, result); 3739} 3740 3741/// visitLog - Lower a log intrinsic. Handles the special sequences for 3742/// limited-precision mode. 3743void 3744SelectionDAGBuilder::visitLog(const CallInst &I) { 3745 SDValue result; 3746 DebugLoc dl = getCurDebugLoc(); 3747 3748 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3749 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3750 SDValue Op = getValue(I.getArgOperand(0)); 3751 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3752 3753 // Scale the exponent by log(2) [0.69314718f]. 3754 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3755 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3756 getF32Constant(DAG, 0x3f317218)); 3757 3758 // Get the significand and build it into a floating-point number with 3759 // exponent of 1. 3760 SDValue X = GetSignificand(DAG, Op1, dl); 3761 3762 if (LimitFloatPrecision <= 6) { 3763 // For floating-point precision of 6: 3764 // 3765 // LogofMantissa = 3766 // -1.1609546f + 3767 // (1.4034025f - 0.23903021f * x) * x; 3768 // 3769 // error 0.0034276066, which is better than 8 bits 3770 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3771 getF32Constant(DAG, 0xbe74c456)); 3772 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3773 getF32Constant(DAG, 0x3fb3a2b1)); 3774 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3775 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3776 getF32Constant(DAG, 0x3f949a29)); 3777 3778 result = DAG.getNode(ISD::FADD, dl, 3779 MVT::f32, LogOfExponent, LogOfMantissa); 3780 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3781 // For floating-point precision of 12: 3782 // 3783 // LogOfMantissa = 3784 // -1.7417939f + 3785 // (2.8212026f + 3786 // (-1.4699568f + 3787 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3788 // 3789 // error 0.000061011436, which is 14 bits 3790 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3791 getF32Constant(DAG, 0xbd67b6d6)); 3792 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3793 getF32Constant(DAG, 0x3ee4f4b8)); 3794 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3795 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3796 getF32Constant(DAG, 0x3fbc278b)); 3797 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3798 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3799 getF32Constant(DAG, 0x40348e95)); 3800 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3801 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3802 getF32Constant(DAG, 0x3fdef31a)); 3803 3804 result = DAG.getNode(ISD::FADD, dl, 3805 MVT::f32, LogOfExponent, LogOfMantissa); 3806 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3807 // For floating-point precision of 18: 3808 // 3809 // LogOfMantissa = 3810 // -2.1072184f + 3811 // (4.2372794f + 3812 // (-3.7029485f + 3813 // (2.2781945f + 3814 // (-0.87823314f + 3815 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3816 // 3817 // error 0.0000023660568, which is better than 18 bits 3818 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3819 getF32Constant(DAG, 0xbc91e5ac)); 3820 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3821 getF32Constant(DAG, 0x3e4350aa)); 3822 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3823 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3824 getF32Constant(DAG, 0x3f60d3e3)); 3825 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3826 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3827 getF32Constant(DAG, 0x4011cdf0)); 3828 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3829 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3830 getF32Constant(DAG, 0x406cfd1c)); 3831 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3832 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3833 getF32Constant(DAG, 0x408797cb)); 3834 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3835 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3836 getF32Constant(DAG, 0x4006dcab)); 3837 3838 result = DAG.getNode(ISD::FADD, dl, 3839 MVT::f32, LogOfExponent, LogOfMantissa); 3840 } 3841 } else { 3842 // No special expansion. 3843 result = DAG.getNode(ISD::FLOG, dl, 3844 getValue(I.getArgOperand(0)).getValueType(), 3845 getValue(I.getArgOperand(0))); 3846 } 3847 3848 setValue(&I, result); 3849} 3850 3851/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3852/// limited-precision mode. 3853void 3854SelectionDAGBuilder::visitLog2(const CallInst &I) { 3855 SDValue result; 3856 DebugLoc dl = getCurDebugLoc(); 3857 3858 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3859 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3860 SDValue Op = getValue(I.getArgOperand(0)); 3861 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3862 3863 // Get the exponent. 3864 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3865 3866 // Get the significand and build it into a floating-point number with 3867 // exponent of 1. 3868 SDValue X = GetSignificand(DAG, Op1, dl); 3869 3870 // Different possible minimax approximations of significand in 3871 // floating-point for various degrees of accuracy over [1,2]. 3872 if (LimitFloatPrecision <= 6) { 3873 // For floating-point precision of 6: 3874 // 3875 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3876 // 3877 // error 0.0049451742, which is more than 7 bits 3878 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3879 getF32Constant(DAG, 0xbeb08fe0)); 3880 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3881 getF32Constant(DAG, 0x40019463)); 3882 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3883 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3884 getF32Constant(DAG, 0x3fd6633d)); 3885 3886 result = DAG.getNode(ISD::FADD, dl, 3887 MVT::f32, LogOfExponent, Log2ofMantissa); 3888 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3889 // For floating-point precision of 12: 3890 // 3891 // Log2ofMantissa = 3892 // -2.51285454f + 3893 // (4.07009056f + 3894 // (-2.12067489f + 3895 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3896 // 3897 // error 0.0000876136000, which is better than 13 bits 3898 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3899 getF32Constant(DAG, 0xbda7262e)); 3900 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3901 getF32Constant(DAG, 0x3f25280b)); 3902 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3903 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3904 getF32Constant(DAG, 0x4007b923)); 3905 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3906 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3907 getF32Constant(DAG, 0x40823e2f)); 3908 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3909 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3910 getF32Constant(DAG, 0x4020d29c)); 3911 3912 result = DAG.getNode(ISD::FADD, dl, 3913 MVT::f32, LogOfExponent, Log2ofMantissa); 3914 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3915 // For floating-point precision of 18: 3916 // 3917 // Log2ofMantissa = 3918 // -3.0400495f + 3919 // (6.1129976f + 3920 // (-5.3420409f + 3921 // (3.2865683f + 3922 // (-1.2669343f + 3923 // (0.27515199f - 3924 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3925 // 3926 // error 0.0000018516, which is better than 18 bits 3927 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3928 getF32Constant(DAG, 0xbcd2769e)); 3929 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3930 getF32Constant(DAG, 0x3e8ce0b9)); 3931 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3932 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3933 getF32Constant(DAG, 0x3fa22ae7)); 3934 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3935 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3936 getF32Constant(DAG, 0x40525723)); 3937 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3938 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3939 getF32Constant(DAG, 0x40aaf200)); 3940 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3941 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3942 getF32Constant(DAG, 0x40c39dad)); 3943 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3944 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3945 getF32Constant(DAG, 0x4042902c)); 3946 3947 result = DAG.getNode(ISD::FADD, dl, 3948 MVT::f32, LogOfExponent, Log2ofMantissa); 3949 } 3950 } else { 3951 // No special expansion. 3952 result = DAG.getNode(ISD::FLOG2, dl, 3953 getValue(I.getArgOperand(0)).getValueType(), 3954 getValue(I.getArgOperand(0))); 3955 } 3956 3957 setValue(&I, result); 3958} 3959 3960/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3961/// limited-precision mode. 3962void 3963SelectionDAGBuilder::visitLog10(const CallInst &I) { 3964 SDValue result; 3965 DebugLoc dl = getCurDebugLoc(); 3966 3967 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3968 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3969 SDValue Op = getValue(I.getArgOperand(0)); 3970 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3971 3972 // Scale the exponent by log10(2) [0.30102999f]. 3973 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3974 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3975 getF32Constant(DAG, 0x3e9a209a)); 3976 3977 // Get the significand and build it into a floating-point number with 3978 // exponent of 1. 3979 SDValue X = GetSignificand(DAG, Op1, dl); 3980 3981 if (LimitFloatPrecision <= 6) { 3982 // For floating-point precision of 6: 3983 // 3984 // Log10ofMantissa = 3985 // -0.50419619f + 3986 // (0.60948995f - 0.10380950f * x) * x; 3987 // 3988 // error 0.0014886165, which is 6 bits 3989 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3990 getF32Constant(DAG, 0xbdd49a13)); 3991 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3992 getF32Constant(DAG, 0x3f1c0789)); 3993 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3994 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3995 getF32Constant(DAG, 0x3f011300)); 3996 3997 result = DAG.getNode(ISD::FADD, dl, 3998 MVT::f32, LogOfExponent, Log10ofMantissa); 3999 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4000 // For floating-point precision of 12: 4001 // 4002 // Log10ofMantissa = 4003 // -0.64831180f + 4004 // (0.91751397f + 4005 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4006 // 4007 // error 0.00019228036, which is better than 12 bits 4008 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4009 getF32Constant(DAG, 0x3d431f31)); 4010 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4011 getF32Constant(DAG, 0x3ea21fb2)); 4012 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4013 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4014 getF32Constant(DAG, 0x3f6ae232)); 4015 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4016 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4017 getF32Constant(DAG, 0x3f25f7c3)); 4018 4019 result = DAG.getNode(ISD::FADD, dl, 4020 MVT::f32, LogOfExponent, Log10ofMantissa); 4021 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4022 // For floating-point precision of 18: 4023 // 4024 // Log10ofMantissa = 4025 // -0.84299375f + 4026 // (1.5327582f + 4027 // (-1.0688956f + 4028 // (0.49102474f + 4029 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4030 // 4031 // error 0.0000037995730, which is better than 18 bits 4032 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4033 getF32Constant(DAG, 0x3c5d51ce)); 4034 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4035 getF32Constant(DAG, 0x3e00685a)); 4036 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4037 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4038 getF32Constant(DAG, 0x3efb6798)); 4039 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4040 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4041 getF32Constant(DAG, 0x3f88d192)); 4042 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4043 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4044 getF32Constant(DAG, 0x3fc4316c)); 4045 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4046 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4047 getF32Constant(DAG, 0x3f57ce70)); 4048 4049 result = DAG.getNode(ISD::FADD, dl, 4050 MVT::f32, LogOfExponent, Log10ofMantissa); 4051 } 4052 } else { 4053 // No special expansion. 4054 result = DAG.getNode(ISD::FLOG10, dl, 4055 getValue(I.getArgOperand(0)).getValueType(), 4056 getValue(I.getArgOperand(0))); 4057 } 4058 4059 setValue(&I, result); 4060} 4061 4062/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4063/// limited-precision mode. 4064void 4065SelectionDAGBuilder::visitExp2(const CallInst &I) { 4066 SDValue result; 4067 DebugLoc dl = getCurDebugLoc(); 4068 4069 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 4070 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4071 SDValue Op = getValue(I.getArgOperand(0)); 4072 4073 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4074 4075 // FractionalPartOfX = x - (float)IntegerPartOfX; 4076 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4077 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4078 4079 // IntegerPartOfX <<= 23; 4080 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4081 DAG.getConstant(23, TLI.getPointerTy())); 4082 4083 if (LimitFloatPrecision <= 6) { 4084 // For floating-point precision of 6: 4085 // 4086 // TwoToFractionalPartOfX = 4087 // 0.997535578f + 4088 // (0.735607626f + 0.252464424f * x) * x; 4089 // 4090 // error 0.0144103317, which is 6 bits 4091 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4092 getF32Constant(DAG, 0x3e814304)); 4093 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4094 getF32Constant(DAG, 0x3f3c50c8)); 4095 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4096 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4097 getF32Constant(DAG, 0x3f7f5e7e)); 4098 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4099 SDValue TwoToFractionalPartOfX = 4100 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4101 4102 result = DAG.getNode(ISD::BITCAST, dl, 4103 MVT::f32, TwoToFractionalPartOfX); 4104 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4105 // For floating-point precision of 12: 4106 // 4107 // TwoToFractionalPartOfX = 4108 // 0.999892986f + 4109 // (0.696457318f + 4110 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4111 // 4112 // error 0.000107046256, which is 13 to 14 bits 4113 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4114 getF32Constant(DAG, 0x3da235e3)); 4115 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4116 getF32Constant(DAG, 0x3e65b8f3)); 4117 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4118 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4119 getF32Constant(DAG, 0x3f324b07)); 4120 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4121 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4122 getF32Constant(DAG, 0x3f7ff8fd)); 4123 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4124 SDValue TwoToFractionalPartOfX = 4125 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4126 4127 result = DAG.getNode(ISD::BITCAST, dl, 4128 MVT::f32, TwoToFractionalPartOfX); 4129 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4130 // For floating-point precision of 18: 4131 // 4132 // TwoToFractionalPartOfX = 4133 // 0.999999982f + 4134 // (0.693148872f + 4135 // (0.240227044f + 4136 // (0.554906021e-1f + 4137 // (0.961591928e-2f + 4138 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4139 // error 2.47208000*10^(-7), which is better than 18 bits 4140 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4141 getF32Constant(DAG, 0x3924b03e)); 4142 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4143 getF32Constant(DAG, 0x3ab24b87)); 4144 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4145 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4146 getF32Constant(DAG, 0x3c1d8c17)); 4147 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4148 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4149 getF32Constant(DAG, 0x3d634a1d)); 4150 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4151 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4152 getF32Constant(DAG, 0x3e75fe14)); 4153 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4154 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4155 getF32Constant(DAG, 0x3f317234)); 4156 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4157 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4158 getF32Constant(DAG, 0x3f800000)); 4159 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4160 SDValue TwoToFractionalPartOfX = 4161 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4162 4163 result = DAG.getNode(ISD::BITCAST, dl, 4164 MVT::f32, TwoToFractionalPartOfX); 4165 } 4166 } else { 4167 // No special expansion. 4168 result = DAG.getNode(ISD::FEXP2, dl, 4169 getValue(I.getArgOperand(0)).getValueType(), 4170 getValue(I.getArgOperand(0))); 4171 } 4172 4173 setValue(&I, result); 4174} 4175 4176/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4177/// limited-precision mode with x == 10.0f. 4178void 4179SelectionDAGBuilder::visitPow(const CallInst &I) { 4180 SDValue result; 4181 const Value *Val = I.getArgOperand(0); 4182 DebugLoc dl = getCurDebugLoc(); 4183 bool IsExp10 = false; 4184 4185 if (getValue(Val).getValueType() == MVT::f32 && 4186 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4187 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4188 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4189 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4190 APFloat Ten(10.0f); 4191 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4192 } 4193 } 4194 } 4195 4196 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4197 SDValue Op = getValue(I.getArgOperand(1)); 4198 4199 // Put the exponent in the right bit position for later addition to the 4200 // final result: 4201 // 4202 // #define LOG2OF10 3.3219281f 4203 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4204 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4205 getF32Constant(DAG, 0x40549a78)); 4206 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4207 4208 // FractionalPartOfX = x - (float)IntegerPartOfX; 4209 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4210 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4211 4212 // IntegerPartOfX <<= 23; 4213 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4214 DAG.getConstant(23, TLI.getPointerTy())); 4215 4216 if (LimitFloatPrecision <= 6) { 4217 // For floating-point precision of 6: 4218 // 4219 // twoToFractionalPartOfX = 4220 // 0.997535578f + 4221 // (0.735607626f + 0.252464424f * x) * x; 4222 // 4223 // error 0.0144103317, which is 6 bits 4224 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4225 getF32Constant(DAG, 0x3e814304)); 4226 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4227 getF32Constant(DAG, 0x3f3c50c8)); 4228 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4229 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4230 getF32Constant(DAG, 0x3f7f5e7e)); 4231 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4232 SDValue TwoToFractionalPartOfX = 4233 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4234 4235 result = DAG.getNode(ISD::BITCAST, dl, 4236 MVT::f32, TwoToFractionalPartOfX); 4237 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4238 // For floating-point precision of 12: 4239 // 4240 // TwoToFractionalPartOfX = 4241 // 0.999892986f + 4242 // (0.696457318f + 4243 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4244 // 4245 // error 0.000107046256, which is 13 to 14 bits 4246 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4247 getF32Constant(DAG, 0x3da235e3)); 4248 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4249 getF32Constant(DAG, 0x3e65b8f3)); 4250 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4251 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4252 getF32Constant(DAG, 0x3f324b07)); 4253 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4254 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4255 getF32Constant(DAG, 0x3f7ff8fd)); 4256 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4257 SDValue TwoToFractionalPartOfX = 4258 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4259 4260 result = DAG.getNode(ISD::BITCAST, dl, 4261 MVT::f32, TwoToFractionalPartOfX); 4262 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4263 // For floating-point precision of 18: 4264 // 4265 // TwoToFractionalPartOfX = 4266 // 0.999999982f + 4267 // (0.693148872f + 4268 // (0.240227044f + 4269 // (0.554906021e-1f + 4270 // (0.961591928e-2f + 4271 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4272 // error 2.47208000*10^(-7), which is better than 18 bits 4273 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4274 getF32Constant(DAG, 0x3924b03e)); 4275 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4276 getF32Constant(DAG, 0x3ab24b87)); 4277 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4278 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4279 getF32Constant(DAG, 0x3c1d8c17)); 4280 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4281 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4282 getF32Constant(DAG, 0x3d634a1d)); 4283 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4284 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4285 getF32Constant(DAG, 0x3e75fe14)); 4286 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4287 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4288 getF32Constant(DAG, 0x3f317234)); 4289 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4290 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4291 getF32Constant(DAG, 0x3f800000)); 4292 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4293 SDValue TwoToFractionalPartOfX = 4294 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4295 4296 result = DAG.getNode(ISD::BITCAST, dl, 4297 MVT::f32, TwoToFractionalPartOfX); 4298 } 4299 } else { 4300 // No special expansion. 4301 result = DAG.getNode(ISD::FPOW, dl, 4302 getValue(I.getArgOperand(0)).getValueType(), 4303 getValue(I.getArgOperand(0)), 4304 getValue(I.getArgOperand(1))); 4305 } 4306 4307 setValue(&I, result); 4308} 4309 4310 4311/// ExpandPowI - Expand a llvm.powi intrinsic. 4312static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4313 SelectionDAG &DAG) { 4314 // If RHS is a constant, we can expand this out to a multiplication tree, 4315 // otherwise we end up lowering to a call to __powidf2 (for example). When 4316 // optimizing for size, we only want to do this if the expansion would produce 4317 // a small number of multiplies, otherwise we do the full expansion. 4318 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4319 // Get the exponent as a positive value. 4320 unsigned Val = RHSC->getSExtValue(); 4321 if ((int)Val < 0) Val = -Val; 4322 4323 // powi(x, 0) -> 1.0 4324 if (Val == 0) 4325 return DAG.getConstantFP(1.0, LHS.getValueType()); 4326 4327 const Function *F = DAG.getMachineFunction().getFunction(); 4328 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4329 // If optimizing for size, don't insert too many multiplies. This 4330 // inserts up to 5 multiplies. 4331 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4332 // We use the simple binary decomposition method to generate the multiply 4333 // sequence. There are more optimal ways to do this (for example, 4334 // powi(x,15) generates one more multiply than it should), but this has 4335 // the benefit of being both really simple and much better than a libcall. 4336 SDValue Res; // Logically starts equal to 1.0 4337 SDValue CurSquare = LHS; 4338 while (Val) { 4339 if (Val & 1) { 4340 if (Res.getNode()) 4341 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4342 else 4343 Res = CurSquare; // 1.0*CurSquare. 4344 } 4345 4346 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4347 CurSquare, CurSquare); 4348 Val >>= 1; 4349 } 4350 4351 // If the original was negative, invert the result, producing 1/(x*x*x). 4352 if (RHSC->getSExtValue() < 0) 4353 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4354 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4355 return Res; 4356 } 4357 } 4358 4359 // Otherwise, expand to a libcall. 4360 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4361} 4362 4363// getTruncatedArgReg - Find underlying register used for an truncated 4364// argument. 4365static unsigned getTruncatedArgReg(const SDValue &N) { 4366 if (N.getOpcode() != ISD::TRUNCATE) 4367 return 0; 4368 4369 const SDValue &Ext = N.getOperand(0); 4370 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4371 const SDValue &CFR = Ext.getOperand(0); 4372 if (CFR.getOpcode() == ISD::CopyFromReg) 4373 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4374 else 4375 if (CFR.getOpcode() == ISD::TRUNCATE) 4376 return getTruncatedArgReg(CFR); 4377 } 4378 return 0; 4379} 4380 4381/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4382/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4383/// At the end of instruction selection, they will be inserted to the entry BB. 4384bool 4385SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4386 int64_t Offset, 4387 const SDValue &N) { 4388 const Argument *Arg = dyn_cast<Argument>(V); 4389 if (!Arg) 4390 return false; 4391 4392 MachineFunction &MF = DAG.getMachineFunction(); 4393 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4394 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4395 4396 // Ignore inlined function arguments here. 4397 DIVariable DV(Variable); 4398 if (DV.isInlinedFnArgument(MF.getFunction())) 4399 return false; 4400 4401 unsigned Reg = 0; 4402 // Some arguments' frame index is recorded during argument lowering. 4403 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4404 if (Offset) 4405 Reg = TRI->getFrameRegister(MF); 4406 4407 if (!Reg && N.getNode()) { 4408 if (N.getOpcode() == ISD::CopyFromReg) 4409 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4410 else 4411 Reg = getTruncatedArgReg(N); 4412 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4413 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4414 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4415 if (PR) 4416 Reg = PR; 4417 } 4418 } 4419 4420 if (!Reg) { 4421 // Check if ValueMap has reg number. 4422 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4423 if (VMI != FuncInfo.ValueMap.end()) 4424 Reg = VMI->second; 4425 } 4426 4427 if (!Reg && N.getNode()) { 4428 // Check if frame index is available. 4429 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4430 if (FrameIndexSDNode *FINode = 4431 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4432 Reg = TRI->getFrameRegister(MF); 4433 Offset = FINode->getIndex(); 4434 } 4435 } 4436 4437 if (!Reg) 4438 return false; 4439 4440 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4441 TII->get(TargetOpcode::DBG_VALUE)) 4442 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4443 FuncInfo.ArgDbgValues.push_back(&*MIB); 4444 return true; 4445} 4446 4447// VisualStudio defines setjmp as _setjmp 4448#if defined(_MSC_VER) && defined(setjmp) && \ 4449 !defined(setjmp_undefined_for_msvc) 4450# pragma push_macro("setjmp") 4451# undef setjmp 4452# define setjmp_undefined_for_msvc 4453#endif 4454 4455/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4456/// we want to emit this as a call to a named external function, return the name 4457/// otherwise lower it and return null. 4458const char * 4459SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4460 DebugLoc dl = getCurDebugLoc(); 4461 SDValue Res; 4462 4463 switch (Intrinsic) { 4464 default: 4465 // By default, turn this into a target intrinsic node. 4466 visitTargetIntrinsic(I, Intrinsic); 4467 return 0; 4468 case Intrinsic::vastart: visitVAStart(I); return 0; 4469 case Intrinsic::vaend: visitVAEnd(I); return 0; 4470 case Intrinsic::vacopy: visitVACopy(I); return 0; 4471 case Intrinsic::returnaddress: 4472 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4473 getValue(I.getArgOperand(0)))); 4474 return 0; 4475 case Intrinsic::frameaddress: 4476 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4477 getValue(I.getArgOperand(0)))); 4478 return 0; 4479 case Intrinsic::setjmp: 4480 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4481 case Intrinsic::longjmp: 4482 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4483 case Intrinsic::memcpy: { 4484 // Assert for address < 256 since we support only user defined address 4485 // spaces. 4486 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4487 < 256 && 4488 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4489 < 256 && 4490 "Unknown address space"); 4491 SDValue Op1 = getValue(I.getArgOperand(0)); 4492 SDValue Op2 = getValue(I.getArgOperand(1)); 4493 SDValue Op3 = getValue(I.getArgOperand(2)); 4494 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4495 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4496 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4497 MachinePointerInfo(I.getArgOperand(0)), 4498 MachinePointerInfo(I.getArgOperand(1)))); 4499 return 0; 4500 } 4501 case Intrinsic::memset: { 4502 // Assert for address < 256 since we support only user defined address 4503 // spaces. 4504 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4505 < 256 && 4506 "Unknown address space"); 4507 SDValue Op1 = getValue(I.getArgOperand(0)); 4508 SDValue Op2 = getValue(I.getArgOperand(1)); 4509 SDValue Op3 = getValue(I.getArgOperand(2)); 4510 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4511 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4512 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4513 MachinePointerInfo(I.getArgOperand(0)))); 4514 return 0; 4515 } 4516 case Intrinsic::memmove: { 4517 // Assert for address < 256 since we support only user defined address 4518 // spaces. 4519 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4520 < 256 && 4521 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4522 < 256 && 4523 "Unknown address space"); 4524 SDValue Op1 = getValue(I.getArgOperand(0)); 4525 SDValue Op2 = getValue(I.getArgOperand(1)); 4526 SDValue Op3 = getValue(I.getArgOperand(2)); 4527 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4528 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4529 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4530 MachinePointerInfo(I.getArgOperand(0)), 4531 MachinePointerInfo(I.getArgOperand(1)))); 4532 return 0; 4533 } 4534 case Intrinsic::dbg_declare: { 4535 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4536 MDNode *Variable = DI.getVariable(); 4537 const Value *Address = DI.getAddress(); 4538 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4539 return 0; 4540 4541 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4542 // but do not always have a corresponding SDNode built. The SDNodeOrder 4543 // absolute, but not relative, values are different depending on whether 4544 // debug info exists. 4545 ++SDNodeOrder; 4546 4547 // Check if address has undef value. 4548 if (isa<UndefValue>(Address) || 4549 (Address->use_empty() && !isa<Argument>(Address))) { 4550 DEBUG(dbgs() << "Dropping debug info for " << DI); 4551 return 0; 4552 } 4553 4554 SDValue &N = NodeMap[Address]; 4555 if (!N.getNode() && isa<Argument>(Address)) 4556 // Check unused arguments map. 4557 N = UnusedArgNodeMap[Address]; 4558 SDDbgValue *SDV; 4559 if (N.getNode()) { 4560 // Parameters are handled specially. 4561 bool isParameter = 4562 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4563 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4564 Address = BCI->getOperand(0); 4565 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4566 4567 if (isParameter && !AI) { 4568 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4569 if (FINode) 4570 // Byval parameter. We have a frame index at this point. 4571 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4572 0, dl, SDNodeOrder); 4573 else { 4574 // Address is an argument, so try to emit its dbg value using 4575 // virtual register info from the FuncInfo.ValueMap. 4576 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4577 return 0; 4578 } 4579 } else if (AI) 4580 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4581 0, dl, SDNodeOrder); 4582 else { 4583 // Can't do anything with other non-AI cases yet. 4584 DEBUG(dbgs() << "Dropping debug info for " << DI); 4585 return 0; 4586 } 4587 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4588 } else { 4589 // If Address is an argument then try to emit its dbg value using 4590 // virtual register info from the FuncInfo.ValueMap. 4591 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4592 // If variable is pinned by a alloca in dominating bb then 4593 // use StaticAllocaMap. 4594 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4595 if (AI->getParent() != DI.getParent()) { 4596 DenseMap<const AllocaInst*, int>::iterator SI = 4597 FuncInfo.StaticAllocaMap.find(AI); 4598 if (SI != FuncInfo.StaticAllocaMap.end()) { 4599 SDV = DAG.getDbgValue(Variable, SI->second, 4600 0, dl, SDNodeOrder); 4601 DAG.AddDbgValue(SDV, 0, false); 4602 return 0; 4603 } 4604 } 4605 } 4606 DEBUG(dbgs() << "Dropping debug info for " << DI); 4607 } 4608 } 4609 return 0; 4610 } 4611 case Intrinsic::dbg_value: { 4612 const DbgValueInst &DI = cast<DbgValueInst>(I); 4613 if (!DIVariable(DI.getVariable()).Verify()) 4614 return 0; 4615 4616 MDNode *Variable = DI.getVariable(); 4617 uint64_t Offset = DI.getOffset(); 4618 const Value *V = DI.getValue(); 4619 if (!V) 4620 return 0; 4621 4622 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4623 // but do not always have a corresponding SDNode built. The SDNodeOrder 4624 // absolute, but not relative, values are different depending on whether 4625 // debug info exists. 4626 ++SDNodeOrder; 4627 SDDbgValue *SDV; 4628 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4629 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4630 DAG.AddDbgValue(SDV, 0, false); 4631 } else { 4632 // Do not use getValue() in here; we don't want to generate code at 4633 // this point if it hasn't been done yet. 4634 SDValue N = NodeMap[V]; 4635 if (!N.getNode() && isa<Argument>(V)) 4636 // Check unused arguments map. 4637 N = UnusedArgNodeMap[V]; 4638 if (N.getNode()) { 4639 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4640 SDV = DAG.getDbgValue(Variable, N.getNode(), 4641 N.getResNo(), Offset, dl, SDNodeOrder); 4642 DAG.AddDbgValue(SDV, N.getNode(), false); 4643 } 4644 } else if (!V->use_empty() ) { 4645 // Do not call getValue(V) yet, as we don't want to generate code. 4646 // Remember it for later. 4647 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4648 DanglingDebugInfoMap[V] = DDI; 4649 } else { 4650 // We may expand this to cover more cases. One case where we have no 4651 // data available is an unreferenced parameter. 4652 DEBUG(dbgs() << "Dropping debug info for " << DI); 4653 } 4654 } 4655 4656 // Build a debug info table entry. 4657 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4658 V = BCI->getOperand(0); 4659 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4660 // Don't handle byval struct arguments or VLAs, for example. 4661 if (!AI) 4662 return 0; 4663 DenseMap<const AllocaInst*, int>::iterator SI = 4664 FuncInfo.StaticAllocaMap.find(AI); 4665 if (SI == FuncInfo.StaticAllocaMap.end()) 4666 return 0; // VLAs. 4667 int FI = SI->second; 4668 4669 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4670 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4671 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4672 return 0; 4673 } 4674 case Intrinsic::eh_exception: { 4675 // Insert the EXCEPTIONADDR instruction. 4676 assert(FuncInfo.MBB->isLandingPad() && 4677 "Call to eh.exception not in landing pad!"); 4678 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4679 SDValue Ops[1]; 4680 Ops[0] = DAG.getRoot(); 4681 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4682 setValue(&I, Op); 4683 DAG.setRoot(Op.getValue(1)); 4684 return 0; 4685 } 4686 4687 case Intrinsic::eh_selector: { 4688 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4689 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4690 if (CallMBB->isLandingPad()) 4691 AddCatchInfo(I, &MMI, CallMBB); 4692 else { 4693#ifndef NDEBUG 4694 FuncInfo.CatchInfoLost.insert(&I); 4695#endif 4696 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4697 unsigned Reg = TLI.getExceptionSelectorRegister(); 4698 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4699 } 4700 4701 // Insert the EHSELECTION instruction. 4702 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4703 SDValue Ops[2]; 4704 Ops[0] = getValue(I.getArgOperand(0)); 4705 Ops[1] = getRoot(); 4706 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4707 DAG.setRoot(Op.getValue(1)); 4708 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4709 return 0; 4710 } 4711 4712 case Intrinsic::eh_typeid_for: { 4713 // Find the type id for the given typeinfo. 4714 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4715 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4716 Res = DAG.getConstant(TypeID, MVT::i32); 4717 setValue(&I, Res); 4718 return 0; 4719 } 4720 4721 case Intrinsic::eh_return_i32: 4722 case Intrinsic::eh_return_i64: 4723 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4724 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4725 MVT::Other, 4726 getControlRoot(), 4727 getValue(I.getArgOperand(0)), 4728 getValue(I.getArgOperand(1)))); 4729 return 0; 4730 case Intrinsic::eh_unwind_init: 4731 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4732 return 0; 4733 case Intrinsic::eh_dwarf_cfa: { 4734 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4735 TLI.getPointerTy()); 4736 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4737 TLI.getPointerTy(), 4738 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4739 TLI.getPointerTy()), 4740 CfaArg); 4741 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4742 TLI.getPointerTy(), 4743 DAG.getConstant(0, TLI.getPointerTy())); 4744 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4745 FA, Offset)); 4746 return 0; 4747 } 4748 case Intrinsic::eh_sjlj_callsite: { 4749 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4750 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4751 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4752 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4753 4754 MMI.setCurrentCallSite(CI->getZExtValue()); 4755 return 0; 4756 } 4757 case Intrinsic::eh_sjlj_functioncontext: { 4758 // Get and store the index of the function context. 4759 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4760 AllocaInst *FnCtx = 4761 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4762 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4763 MFI->setFunctionContextIndex(FI); 4764 return 0; 4765 } 4766 case Intrinsic::eh_sjlj_setjmp: { 4767 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4768 getValue(I.getArgOperand(0)))); 4769 return 0; 4770 } 4771 case Intrinsic::eh_sjlj_longjmp: { 4772 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4773 getRoot(), getValue(I.getArgOperand(0)))); 4774 return 0; 4775 } 4776 case Intrinsic::eh_sjlj_dispatch_setup: { 4777 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4778 getRoot(), getValue(I.getArgOperand(0)))); 4779 return 0; 4780 } 4781 4782 case Intrinsic::x86_mmx_pslli_w: 4783 case Intrinsic::x86_mmx_pslli_d: 4784 case Intrinsic::x86_mmx_pslli_q: 4785 case Intrinsic::x86_mmx_psrli_w: 4786 case Intrinsic::x86_mmx_psrli_d: 4787 case Intrinsic::x86_mmx_psrli_q: 4788 case Intrinsic::x86_mmx_psrai_w: 4789 case Intrinsic::x86_mmx_psrai_d: { 4790 SDValue ShAmt = getValue(I.getArgOperand(1)); 4791 if (isa<ConstantSDNode>(ShAmt)) { 4792 visitTargetIntrinsic(I, Intrinsic); 4793 return 0; 4794 } 4795 unsigned NewIntrinsic = 0; 4796 EVT ShAmtVT = MVT::v2i32; 4797 switch (Intrinsic) { 4798 case Intrinsic::x86_mmx_pslli_w: 4799 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4800 break; 4801 case Intrinsic::x86_mmx_pslli_d: 4802 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4803 break; 4804 case Intrinsic::x86_mmx_pslli_q: 4805 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4806 break; 4807 case Intrinsic::x86_mmx_psrli_w: 4808 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4809 break; 4810 case Intrinsic::x86_mmx_psrli_d: 4811 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4812 break; 4813 case Intrinsic::x86_mmx_psrli_q: 4814 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4815 break; 4816 case Intrinsic::x86_mmx_psrai_w: 4817 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4818 break; 4819 case Intrinsic::x86_mmx_psrai_d: 4820 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4821 break; 4822 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4823 } 4824 4825 // The vector shift intrinsics with scalars uses 32b shift amounts but 4826 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4827 // to be zero. 4828 // We must do this early because v2i32 is not a legal type. 4829 DebugLoc dl = getCurDebugLoc(); 4830 SDValue ShOps[2]; 4831 ShOps[0] = ShAmt; 4832 ShOps[1] = DAG.getConstant(0, MVT::i32); 4833 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4834 EVT DestVT = TLI.getValueType(I.getType()); 4835 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4836 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4837 DAG.getConstant(NewIntrinsic, MVT::i32), 4838 getValue(I.getArgOperand(0)), ShAmt); 4839 setValue(&I, Res); 4840 return 0; 4841 } 4842 case Intrinsic::convertff: 4843 case Intrinsic::convertfsi: 4844 case Intrinsic::convertfui: 4845 case Intrinsic::convertsif: 4846 case Intrinsic::convertuif: 4847 case Intrinsic::convertss: 4848 case Intrinsic::convertsu: 4849 case Intrinsic::convertus: 4850 case Intrinsic::convertuu: { 4851 ISD::CvtCode Code = ISD::CVT_INVALID; 4852 switch (Intrinsic) { 4853 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4854 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4855 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4856 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4857 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4858 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4859 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4860 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4861 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4862 } 4863 EVT DestVT = TLI.getValueType(I.getType()); 4864 const Value *Op1 = I.getArgOperand(0); 4865 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4866 DAG.getValueType(DestVT), 4867 DAG.getValueType(getValue(Op1).getValueType()), 4868 getValue(I.getArgOperand(1)), 4869 getValue(I.getArgOperand(2)), 4870 Code); 4871 setValue(&I, Res); 4872 return 0; 4873 } 4874 case Intrinsic::sqrt: 4875 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4876 getValue(I.getArgOperand(0)).getValueType(), 4877 getValue(I.getArgOperand(0)))); 4878 return 0; 4879 case Intrinsic::powi: 4880 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4881 getValue(I.getArgOperand(1)), DAG)); 4882 return 0; 4883 case Intrinsic::sin: 4884 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4885 getValue(I.getArgOperand(0)).getValueType(), 4886 getValue(I.getArgOperand(0)))); 4887 return 0; 4888 case Intrinsic::cos: 4889 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4890 getValue(I.getArgOperand(0)).getValueType(), 4891 getValue(I.getArgOperand(0)))); 4892 return 0; 4893 case Intrinsic::log: 4894 visitLog(I); 4895 return 0; 4896 case Intrinsic::log2: 4897 visitLog2(I); 4898 return 0; 4899 case Intrinsic::log10: 4900 visitLog10(I); 4901 return 0; 4902 case Intrinsic::exp: 4903 visitExp(I); 4904 return 0; 4905 case Intrinsic::exp2: 4906 visitExp2(I); 4907 return 0; 4908 case Intrinsic::pow: 4909 visitPow(I); 4910 return 0; 4911 case Intrinsic::fma: 4912 setValue(&I, DAG.getNode(ISD::FMA, dl, 4913 getValue(I.getArgOperand(0)).getValueType(), 4914 getValue(I.getArgOperand(0)), 4915 getValue(I.getArgOperand(1)), 4916 getValue(I.getArgOperand(2)))); 4917 return 0; 4918 case Intrinsic::convert_to_fp16: 4919 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4920 MVT::i16, getValue(I.getArgOperand(0)))); 4921 return 0; 4922 case Intrinsic::convert_from_fp16: 4923 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4924 MVT::f32, getValue(I.getArgOperand(0)))); 4925 return 0; 4926 case Intrinsic::pcmarker: { 4927 SDValue Tmp = getValue(I.getArgOperand(0)); 4928 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4929 return 0; 4930 } 4931 case Intrinsic::readcyclecounter: { 4932 SDValue Op = getRoot(); 4933 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4934 DAG.getVTList(MVT::i64, MVT::Other), 4935 &Op, 1); 4936 setValue(&I, Res); 4937 DAG.setRoot(Res.getValue(1)); 4938 return 0; 4939 } 4940 case Intrinsic::bswap: 4941 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4942 getValue(I.getArgOperand(0)).getValueType(), 4943 getValue(I.getArgOperand(0)))); 4944 return 0; 4945 case Intrinsic::cttz: { 4946 SDValue Arg = getValue(I.getArgOperand(0)); 4947 EVT Ty = Arg.getValueType(); 4948 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4949 return 0; 4950 } 4951 case Intrinsic::ctlz: { 4952 SDValue Arg = getValue(I.getArgOperand(0)); 4953 EVT Ty = Arg.getValueType(); 4954 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4955 return 0; 4956 } 4957 case Intrinsic::ctpop: { 4958 SDValue Arg = getValue(I.getArgOperand(0)); 4959 EVT Ty = Arg.getValueType(); 4960 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4961 return 0; 4962 } 4963 case Intrinsic::stacksave: { 4964 SDValue Op = getRoot(); 4965 Res = DAG.getNode(ISD::STACKSAVE, dl, 4966 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4967 setValue(&I, Res); 4968 DAG.setRoot(Res.getValue(1)); 4969 return 0; 4970 } 4971 case Intrinsic::stackrestore: { 4972 Res = getValue(I.getArgOperand(0)); 4973 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4974 return 0; 4975 } 4976 case Intrinsic::stackprotector: { 4977 // Emit code into the DAG to store the stack guard onto the stack. 4978 MachineFunction &MF = DAG.getMachineFunction(); 4979 MachineFrameInfo *MFI = MF.getFrameInfo(); 4980 EVT PtrTy = TLI.getPointerTy(); 4981 4982 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4983 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4984 4985 int FI = FuncInfo.StaticAllocaMap[Slot]; 4986 MFI->setStackProtectorIndex(FI); 4987 4988 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4989 4990 // Store the stack protector onto the stack. 4991 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4992 MachinePointerInfo::getFixedStack(FI), 4993 true, false, 0); 4994 setValue(&I, Res); 4995 DAG.setRoot(Res); 4996 return 0; 4997 } 4998 case Intrinsic::objectsize: { 4999 // If we don't know by now, we're never going to know. 5000 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5001 5002 assert(CI && "Non-constant type in __builtin_object_size?"); 5003 5004 SDValue Arg = getValue(I.getCalledValue()); 5005 EVT Ty = Arg.getValueType(); 5006 5007 if (CI->isZero()) 5008 Res = DAG.getConstant(-1ULL, Ty); 5009 else 5010 Res = DAG.getConstant(0, Ty); 5011 5012 setValue(&I, Res); 5013 return 0; 5014 } 5015 case Intrinsic::var_annotation: 5016 // Discard annotate attributes 5017 return 0; 5018 5019 case Intrinsic::init_trampoline: { 5020 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5021 5022 SDValue Ops[6]; 5023 Ops[0] = getRoot(); 5024 Ops[1] = getValue(I.getArgOperand(0)); 5025 Ops[2] = getValue(I.getArgOperand(1)); 5026 Ops[3] = getValue(I.getArgOperand(2)); 5027 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5028 Ops[5] = DAG.getSrcValue(F); 5029 5030 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5031 5032 DAG.setRoot(Res); 5033 return 0; 5034 } 5035 case Intrinsic::adjust_trampoline: { 5036 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5037 TLI.getPointerTy(), 5038 getValue(I.getArgOperand(0)))); 5039 return 0; 5040 } 5041 case Intrinsic::gcroot: 5042 if (GFI) { 5043 const Value *Alloca = I.getArgOperand(0); 5044 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5045 5046 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5047 GFI->addStackRoot(FI->getIndex(), TypeMap); 5048 } 5049 return 0; 5050 case Intrinsic::gcread: 5051 case Intrinsic::gcwrite: 5052 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5053 return 0; 5054 case Intrinsic::flt_rounds: 5055 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5056 return 0; 5057 5058 case Intrinsic::expect: { 5059 // Just replace __builtin_expect(exp, c) with EXP. 5060 setValue(&I, getValue(I.getArgOperand(0))); 5061 return 0; 5062 } 5063 5064 case Intrinsic::trap: { 5065 StringRef TrapFuncName = getTrapFunctionName(); 5066 if (TrapFuncName.empty()) { 5067 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 5068 return 0; 5069 } 5070 TargetLowering::ArgListTy Args; 5071 std::pair<SDValue, SDValue> Result = 5072 TLI.LowerCallTo(getRoot(), I.getType(), 5073 false, false, false, false, 0, CallingConv::C, 5074 /*isTailCall=*/false, /*isReturnValueUsed=*/true, 5075 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5076 Args, DAG, getCurDebugLoc()); 5077 DAG.setRoot(Result.second); 5078 return 0; 5079 } 5080 case Intrinsic::uadd_with_overflow: 5081 return implVisitAluOverflow(I, ISD::UADDO); 5082 case Intrinsic::sadd_with_overflow: 5083 return implVisitAluOverflow(I, ISD::SADDO); 5084 case Intrinsic::usub_with_overflow: 5085 return implVisitAluOverflow(I, ISD::USUBO); 5086 case Intrinsic::ssub_with_overflow: 5087 return implVisitAluOverflow(I, ISD::SSUBO); 5088 case Intrinsic::umul_with_overflow: 5089 return implVisitAluOverflow(I, ISD::UMULO); 5090 case Intrinsic::smul_with_overflow: 5091 return implVisitAluOverflow(I, ISD::SMULO); 5092 5093 case Intrinsic::prefetch: { 5094 SDValue Ops[5]; 5095 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5096 Ops[0] = getRoot(); 5097 Ops[1] = getValue(I.getArgOperand(0)); 5098 Ops[2] = getValue(I.getArgOperand(1)); 5099 Ops[3] = getValue(I.getArgOperand(2)); 5100 Ops[4] = getValue(I.getArgOperand(3)); 5101 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5102 DAG.getVTList(MVT::Other), 5103 &Ops[0], 5, 5104 EVT::getIntegerVT(*Context, 8), 5105 MachinePointerInfo(I.getArgOperand(0)), 5106 0, /* align */ 5107 false, /* volatile */ 5108 rw==0, /* read */ 5109 rw==1)); /* write */ 5110 return 0; 5111 } 5112 case Intrinsic::memory_barrier: { 5113 SDValue Ops[6]; 5114 Ops[0] = getRoot(); 5115 for (int x = 1; x < 6; ++x) 5116 Ops[x] = getValue(I.getArgOperand(x - 1)); 5117 5118 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 5119 return 0; 5120 } 5121 case Intrinsic::atomic_cmp_swap: { 5122 SDValue Root = getRoot(); 5123 SDValue L = 5124 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 5125 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 5126 Root, 5127 getValue(I.getArgOperand(0)), 5128 getValue(I.getArgOperand(1)), 5129 getValue(I.getArgOperand(2)), 5130 MachinePointerInfo(I.getArgOperand(0)), 0 /* Alignment */, 5131 Monotonic, CrossThread); 5132 setValue(&I, L); 5133 DAG.setRoot(L.getValue(1)); 5134 return 0; 5135 } 5136 case Intrinsic::atomic_load_add: 5137 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 5138 case Intrinsic::atomic_load_sub: 5139 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 5140 case Intrinsic::atomic_load_or: 5141 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 5142 case Intrinsic::atomic_load_xor: 5143 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 5144 case Intrinsic::atomic_load_and: 5145 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 5146 case Intrinsic::atomic_load_nand: 5147 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 5148 case Intrinsic::atomic_load_max: 5149 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 5150 case Intrinsic::atomic_load_min: 5151 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 5152 case Intrinsic::atomic_load_umin: 5153 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 5154 case Intrinsic::atomic_load_umax: 5155 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 5156 case Intrinsic::atomic_swap: 5157 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 5158 5159 case Intrinsic::invariant_start: 5160 case Intrinsic::lifetime_start: 5161 // Discard region information. 5162 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5163 return 0; 5164 case Intrinsic::invariant_end: 5165 case Intrinsic::lifetime_end: 5166 // Discard region information. 5167 return 0; 5168 } 5169} 5170 5171void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5172 bool isTailCall, 5173 MachineBasicBlock *LandingPad) { 5174 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5175 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5176 Type *RetTy = FTy->getReturnType(); 5177 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5178 MCSymbol *BeginLabel = 0; 5179 5180 TargetLowering::ArgListTy Args; 5181 TargetLowering::ArgListEntry Entry; 5182 Args.reserve(CS.arg_size()); 5183 5184 // Check whether the function can return without sret-demotion. 5185 SmallVector<ISD::OutputArg, 4> Outs; 5186 SmallVector<uint64_t, 4> Offsets; 5187 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5188 Outs, TLI, &Offsets); 5189 5190 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5191 DAG.getMachineFunction(), 5192 FTy->isVarArg(), Outs, 5193 FTy->getContext()); 5194 5195 SDValue DemoteStackSlot; 5196 int DemoteStackIdx = -100; 5197 5198 if (!CanLowerReturn) { 5199 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5200 FTy->getReturnType()); 5201 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5202 FTy->getReturnType()); 5203 MachineFunction &MF = DAG.getMachineFunction(); 5204 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5205 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5206 5207 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5208 Entry.Node = DemoteStackSlot; 5209 Entry.Ty = StackSlotPtrType; 5210 Entry.isSExt = false; 5211 Entry.isZExt = false; 5212 Entry.isInReg = false; 5213 Entry.isSRet = true; 5214 Entry.isNest = false; 5215 Entry.isByVal = false; 5216 Entry.Alignment = Align; 5217 Args.push_back(Entry); 5218 RetTy = Type::getVoidTy(FTy->getContext()); 5219 } 5220 5221 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5222 i != e; ++i) { 5223 const Value *V = *i; 5224 5225 // Skip empty types 5226 if (V->getType()->isEmptyTy()) 5227 continue; 5228 5229 SDValue ArgNode = getValue(V); 5230 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5231 5232 unsigned attrInd = i - CS.arg_begin() + 1; 5233 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5234 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5235 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5236 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5237 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5238 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5239 Entry.Alignment = CS.getParamAlignment(attrInd); 5240 Args.push_back(Entry); 5241 } 5242 5243 if (LandingPad) { 5244 // Insert a label before the invoke call to mark the try range. This can be 5245 // used to detect deletion of the invoke via the MachineModuleInfo. 5246 BeginLabel = MMI.getContext().CreateTempSymbol(); 5247 5248 // For SjLj, keep track of which landing pads go with which invokes 5249 // so as to maintain the ordering of pads in the LSDA. 5250 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5251 if (CallSiteIndex) { 5252 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5253 // Now that the call site is handled, stop tracking it. 5254 MMI.setCurrentCallSite(0); 5255 } 5256 5257 // Both PendingLoads and PendingExports must be flushed here; 5258 // this call might not return. 5259 (void)getRoot(); 5260 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5261 } 5262 5263 // Check if target-independent constraints permit a tail call here. 5264 // Target-dependent constraints are checked within TLI.LowerCallTo. 5265 if (isTailCall && 5266 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5267 isTailCall = false; 5268 5269 // If there's a possibility that fast-isel has already selected some amount 5270 // of the current basic block, don't emit a tail call. 5271 if (isTailCall && EnableFastISel) 5272 isTailCall = false; 5273 5274 std::pair<SDValue,SDValue> Result = 5275 TLI.LowerCallTo(getRoot(), RetTy, 5276 CS.paramHasAttr(0, Attribute::SExt), 5277 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 5278 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 5279 CS.getCallingConv(), 5280 isTailCall, 5281 !CS.getInstruction()->use_empty(), 5282 Callee, Args, DAG, getCurDebugLoc()); 5283 assert((isTailCall || Result.second.getNode()) && 5284 "Non-null chain expected with non-tail call!"); 5285 assert((Result.second.getNode() || !Result.first.getNode()) && 5286 "Null value expected with tail call!"); 5287 if (Result.first.getNode()) { 5288 setValue(CS.getInstruction(), Result.first); 5289 } else if (!CanLowerReturn && Result.second.getNode()) { 5290 // The instruction result is the result of loading from the 5291 // hidden sret parameter. 5292 SmallVector<EVT, 1> PVTs; 5293 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5294 5295 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5296 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5297 EVT PtrVT = PVTs[0]; 5298 unsigned NumValues = Outs.size(); 5299 SmallVector<SDValue, 4> Values(NumValues); 5300 SmallVector<SDValue, 4> Chains(NumValues); 5301 5302 for (unsigned i = 0; i < NumValues; ++i) { 5303 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5304 DemoteStackSlot, 5305 DAG.getConstant(Offsets[i], PtrVT)); 5306 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 5307 Add, 5308 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5309 false, false, 1); 5310 Values[i] = L; 5311 Chains[i] = L.getValue(1); 5312 } 5313 5314 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5315 MVT::Other, &Chains[0], NumValues); 5316 PendingLoads.push_back(Chain); 5317 5318 // Collect the legal value parts into potentially illegal values 5319 // that correspond to the original function's return values. 5320 SmallVector<EVT, 4> RetTys; 5321 RetTy = FTy->getReturnType(); 5322 ComputeValueVTs(TLI, RetTy, RetTys); 5323 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5324 SmallVector<SDValue, 4> ReturnValues; 5325 unsigned CurReg = 0; 5326 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5327 EVT VT = RetTys[I]; 5328 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 5329 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 5330 5331 SDValue ReturnValue = 5332 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 5333 RegisterVT, VT, AssertOp); 5334 ReturnValues.push_back(ReturnValue); 5335 CurReg += NumRegs; 5336 } 5337 5338 setValue(CS.getInstruction(), 5339 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5340 DAG.getVTList(&RetTys[0], RetTys.size()), 5341 &ReturnValues[0], ReturnValues.size())); 5342 } 5343 5344 // Assign order to nodes here. If the call does not produce a result, it won't 5345 // be mapped to a SDNode and visit() will not assign it an order number. 5346 if (!Result.second.getNode()) { 5347 // As a special case, a null chain means that a tail call has been emitted and 5348 // the DAG root is already updated. 5349 HasTailCall = true; 5350 ++SDNodeOrder; 5351 AssignOrderingToNode(DAG.getRoot().getNode()); 5352 } else { 5353 DAG.setRoot(Result.second); 5354 ++SDNodeOrder; 5355 AssignOrderingToNode(Result.second.getNode()); 5356 } 5357 5358 if (LandingPad) { 5359 // Insert a label at the end of the invoke call to mark the try range. This 5360 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5361 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5362 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5363 5364 // Inform MachineModuleInfo of range. 5365 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5366 } 5367} 5368 5369/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5370/// value is equal or not-equal to zero. 5371static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5372 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5373 UI != E; ++UI) { 5374 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5375 if (IC->isEquality()) 5376 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5377 if (C->isNullValue()) 5378 continue; 5379 // Unknown instruction. 5380 return false; 5381 } 5382 return true; 5383} 5384 5385static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5386 Type *LoadTy, 5387 SelectionDAGBuilder &Builder) { 5388 5389 // Check to see if this load can be trivially constant folded, e.g. if the 5390 // input is from a string literal. 5391 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5392 // Cast pointer to the type we really want to load. 5393 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5394 PointerType::getUnqual(LoadTy)); 5395 5396 if (const Constant *LoadCst = 5397 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5398 Builder.TD)) 5399 return Builder.getValue(LoadCst); 5400 } 5401 5402 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5403 // still constant memory, the input chain can be the entry node. 5404 SDValue Root; 5405 bool ConstantMemory = false; 5406 5407 // Do not serialize (non-volatile) loads of constant memory with anything. 5408 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5409 Root = Builder.DAG.getEntryNode(); 5410 ConstantMemory = true; 5411 } else { 5412 // Do not serialize non-volatile loads against each other. 5413 Root = Builder.DAG.getRoot(); 5414 } 5415 5416 SDValue Ptr = Builder.getValue(PtrVal); 5417 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5418 Ptr, MachinePointerInfo(PtrVal), 5419 false /*volatile*/, 5420 false /*nontemporal*/, 1 /* align=1 */); 5421 5422 if (!ConstantMemory) 5423 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5424 return LoadVal; 5425} 5426 5427 5428/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5429/// If so, return true and lower it, otherwise return false and it will be 5430/// lowered like a normal call. 5431bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5432 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5433 if (I.getNumArgOperands() != 3) 5434 return false; 5435 5436 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5437 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5438 !I.getArgOperand(2)->getType()->isIntegerTy() || 5439 !I.getType()->isIntegerTy()) 5440 return false; 5441 5442 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5443 5444 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5445 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5446 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5447 bool ActuallyDoIt = true; 5448 MVT LoadVT; 5449 Type *LoadTy; 5450 switch (Size->getZExtValue()) { 5451 default: 5452 LoadVT = MVT::Other; 5453 LoadTy = 0; 5454 ActuallyDoIt = false; 5455 break; 5456 case 2: 5457 LoadVT = MVT::i16; 5458 LoadTy = Type::getInt16Ty(Size->getContext()); 5459 break; 5460 case 4: 5461 LoadVT = MVT::i32; 5462 LoadTy = Type::getInt32Ty(Size->getContext()); 5463 break; 5464 case 8: 5465 LoadVT = MVT::i64; 5466 LoadTy = Type::getInt64Ty(Size->getContext()); 5467 break; 5468 /* 5469 case 16: 5470 LoadVT = MVT::v4i32; 5471 LoadTy = Type::getInt32Ty(Size->getContext()); 5472 LoadTy = VectorType::get(LoadTy, 4); 5473 break; 5474 */ 5475 } 5476 5477 // This turns into unaligned loads. We only do this if the target natively 5478 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5479 // we'll only produce a small number of byte loads. 5480 5481 // Require that we can find a legal MVT, and only do this if the target 5482 // supports unaligned loads of that type. Expanding into byte loads would 5483 // bloat the code. 5484 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5485 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5486 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5487 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5488 ActuallyDoIt = false; 5489 } 5490 5491 if (ActuallyDoIt) { 5492 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5493 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5494 5495 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5496 ISD::SETNE); 5497 EVT CallVT = TLI.getValueType(I.getType(), true); 5498 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5499 return true; 5500 } 5501 } 5502 5503 5504 return false; 5505} 5506 5507 5508void SelectionDAGBuilder::visitCall(const CallInst &I) { 5509 // Handle inline assembly differently. 5510 if (isa<InlineAsm>(I.getCalledValue())) { 5511 visitInlineAsm(&I); 5512 return; 5513 } 5514 5515 // See if any floating point values are being passed to this function. This is 5516 // used to emit an undefined reference to fltused on Windows. 5517 FunctionType *FT = 5518 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5519 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5520 if (FT->isVarArg() && 5521 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5522 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5523 Type* T = I.getArgOperand(i)->getType(); 5524 for (po_iterator<Type*> i = po_begin(T), e = po_end(T); 5525 i != e; ++i) { 5526 if (!i->isFloatingPointTy()) continue; 5527 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5528 break; 5529 } 5530 } 5531 } 5532 5533 const char *RenameFn = 0; 5534 if (Function *F = I.getCalledFunction()) { 5535 if (F->isDeclaration()) { 5536 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5537 if (unsigned IID = II->getIntrinsicID(F)) { 5538 RenameFn = visitIntrinsicCall(I, IID); 5539 if (!RenameFn) 5540 return; 5541 } 5542 } 5543 if (unsigned IID = F->getIntrinsicID()) { 5544 RenameFn = visitIntrinsicCall(I, IID); 5545 if (!RenameFn) 5546 return; 5547 } 5548 } 5549 5550 // Check for well-known libc/libm calls. If the function is internal, it 5551 // can't be a library call. 5552 if (!F->hasLocalLinkage() && F->hasName()) { 5553 StringRef Name = F->getName(); 5554 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5555 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5556 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5557 I.getType() == I.getArgOperand(0)->getType() && 5558 I.getType() == I.getArgOperand(1)->getType()) { 5559 SDValue LHS = getValue(I.getArgOperand(0)); 5560 SDValue RHS = getValue(I.getArgOperand(1)); 5561 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5562 LHS.getValueType(), LHS, RHS)); 5563 return; 5564 } 5565 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5566 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5567 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5568 I.getType() == I.getArgOperand(0)->getType()) { 5569 SDValue Tmp = getValue(I.getArgOperand(0)); 5570 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5571 Tmp.getValueType(), Tmp)); 5572 return; 5573 } 5574 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5575 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5576 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5577 I.getType() == I.getArgOperand(0)->getType() && 5578 I.onlyReadsMemory()) { 5579 SDValue Tmp = getValue(I.getArgOperand(0)); 5580 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5581 Tmp.getValueType(), Tmp)); 5582 return; 5583 } 5584 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5585 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5586 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5587 I.getType() == I.getArgOperand(0)->getType() && 5588 I.onlyReadsMemory()) { 5589 SDValue Tmp = getValue(I.getArgOperand(0)); 5590 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5591 Tmp.getValueType(), Tmp)); 5592 return; 5593 } 5594 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5595 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5596 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5597 I.getType() == I.getArgOperand(0)->getType() && 5598 I.onlyReadsMemory()) { 5599 SDValue Tmp = getValue(I.getArgOperand(0)); 5600 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5601 Tmp.getValueType(), Tmp)); 5602 return; 5603 } 5604 } else if (Name == "memcmp") { 5605 if (visitMemCmpCall(I)) 5606 return; 5607 } 5608 } 5609 } 5610 5611 SDValue Callee; 5612 if (!RenameFn) 5613 Callee = getValue(I.getCalledValue()); 5614 else 5615 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5616 5617 // Check if we can potentially perform a tail call. More detailed checking is 5618 // be done within LowerCallTo, after more information about the call is known. 5619 LowerCallTo(&I, Callee, I.isTailCall()); 5620} 5621 5622namespace { 5623 5624/// AsmOperandInfo - This contains information for each constraint that we are 5625/// lowering. 5626class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5627public: 5628 /// CallOperand - If this is the result output operand or a clobber 5629 /// this is null, otherwise it is the incoming operand to the CallInst. 5630 /// This gets modified as the asm is processed. 5631 SDValue CallOperand; 5632 5633 /// AssignedRegs - If this is a register or register class operand, this 5634 /// contains the set of register corresponding to the operand. 5635 RegsForValue AssignedRegs; 5636 5637 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5638 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5639 } 5640 5641 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5642 /// busy in OutputRegs/InputRegs. 5643 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5644 std::set<unsigned> &OutputRegs, 5645 std::set<unsigned> &InputRegs, 5646 const TargetRegisterInfo &TRI) const { 5647 if (isOutReg) { 5648 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5649 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5650 } 5651 if (isInReg) { 5652 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5653 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5654 } 5655 } 5656 5657 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5658 /// corresponds to. If there is no Value* for this operand, it returns 5659 /// MVT::Other. 5660 EVT getCallOperandValEVT(LLVMContext &Context, 5661 const TargetLowering &TLI, 5662 const TargetData *TD) const { 5663 if (CallOperandVal == 0) return MVT::Other; 5664 5665 if (isa<BasicBlock>(CallOperandVal)) 5666 return TLI.getPointerTy(); 5667 5668 llvm::Type *OpTy = CallOperandVal->getType(); 5669 5670 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5671 // If this is an indirect operand, the operand is a pointer to the 5672 // accessed type. 5673 if (isIndirect) { 5674 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5675 if (!PtrTy) 5676 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5677 OpTy = PtrTy->getElementType(); 5678 } 5679 5680 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5681 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5682 if (STy->getNumElements() == 1) 5683 OpTy = STy->getElementType(0); 5684 5685 // If OpTy is not a single value, it may be a struct/union that we 5686 // can tile with integers. 5687 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5688 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5689 switch (BitSize) { 5690 default: break; 5691 case 1: 5692 case 8: 5693 case 16: 5694 case 32: 5695 case 64: 5696 case 128: 5697 OpTy = IntegerType::get(Context, BitSize); 5698 break; 5699 } 5700 } 5701 5702 return TLI.getValueType(OpTy, true); 5703 } 5704 5705private: 5706 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5707 /// specified set. 5708 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5709 const TargetRegisterInfo &TRI) { 5710 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5711 Regs.insert(Reg); 5712 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5713 for (; *Aliases; ++Aliases) 5714 Regs.insert(*Aliases); 5715 } 5716}; 5717 5718typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5719 5720} // end anonymous namespace 5721 5722/// GetRegistersForValue - Assign registers (virtual or physical) for the 5723/// specified operand. We prefer to assign virtual registers, to allow the 5724/// register allocator to handle the assignment process. However, if the asm 5725/// uses features that we can't model on machineinstrs, we have SDISel do the 5726/// allocation. This produces generally horrible, but correct, code. 5727/// 5728/// OpInfo describes the operand. 5729/// Input and OutputRegs are the set of already allocated physical registers. 5730/// 5731static void GetRegistersForValue(SelectionDAG &DAG, 5732 const TargetLowering &TLI, 5733 DebugLoc DL, 5734 SDISelAsmOperandInfo &OpInfo, 5735 std::set<unsigned> &OutputRegs, 5736 std::set<unsigned> &InputRegs) { 5737 LLVMContext &Context = *DAG.getContext(); 5738 5739 // Compute whether this value requires an input register, an output register, 5740 // or both. 5741 bool isOutReg = false; 5742 bool isInReg = false; 5743 switch (OpInfo.Type) { 5744 case InlineAsm::isOutput: 5745 isOutReg = true; 5746 5747 // If there is an input constraint that matches this, we need to reserve 5748 // the input register so no other inputs allocate to it. 5749 isInReg = OpInfo.hasMatchingInput(); 5750 break; 5751 case InlineAsm::isInput: 5752 isInReg = true; 5753 isOutReg = false; 5754 break; 5755 case InlineAsm::isClobber: 5756 isOutReg = true; 5757 isInReg = true; 5758 break; 5759 } 5760 5761 5762 MachineFunction &MF = DAG.getMachineFunction(); 5763 SmallVector<unsigned, 4> Regs; 5764 5765 // If this is a constraint for a single physreg, or a constraint for a 5766 // register class, find it. 5767 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5768 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5769 OpInfo.ConstraintVT); 5770 5771 unsigned NumRegs = 1; 5772 if (OpInfo.ConstraintVT != MVT::Other) { 5773 // If this is a FP input in an integer register (or visa versa) insert a bit 5774 // cast of the input value. More generally, handle any case where the input 5775 // value disagrees with the register class we plan to stick this in. 5776 if (OpInfo.Type == InlineAsm::isInput && 5777 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5778 // Try to convert to the first EVT that the reg class contains. If the 5779 // types are identical size, use a bitcast to convert (e.g. two differing 5780 // vector types). 5781 EVT RegVT = *PhysReg.second->vt_begin(); 5782 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5783 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5784 RegVT, OpInfo.CallOperand); 5785 OpInfo.ConstraintVT = RegVT; 5786 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5787 // If the input is a FP value and we want it in FP registers, do a 5788 // bitcast to the corresponding integer type. This turns an f64 value 5789 // into i64, which can be passed with two i32 values on a 32-bit 5790 // machine. 5791 RegVT = EVT::getIntegerVT(Context, 5792 OpInfo.ConstraintVT.getSizeInBits()); 5793 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5794 RegVT, OpInfo.CallOperand); 5795 OpInfo.ConstraintVT = RegVT; 5796 } 5797 } 5798 5799 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5800 } 5801 5802 EVT RegVT; 5803 EVT ValueVT = OpInfo.ConstraintVT; 5804 5805 // If this is a constraint for a specific physical register, like {r17}, 5806 // assign it now. 5807 if (unsigned AssignedReg = PhysReg.first) { 5808 const TargetRegisterClass *RC = PhysReg.second; 5809 if (OpInfo.ConstraintVT == MVT::Other) 5810 ValueVT = *RC->vt_begin(); 5811 5812 // Get the actual register value type. This is important, because the user 5813 // may have asked for (e.g.) the AX register in i32 type. We need to 5814 // remember that AX is actually i16 to get the right extension. 5815 RegVT = *RC->vt_begin(); 5816 5817 // This is a explicit reference to a physical register. 5818 Regs.push_back(AssignedReg); 5819 5820 // If this is an expanded reference, add the rest of the regs to Regs. 5821 if (NumRegs != 1) { 5822 TargetRegisterClass::iterator I = RC->begin(); 5823 for (; *I != AssignedReg; ++I) 5824 assert(I != RC->end() && "Didn't find reg!"); 5825 5826 // Already added the first reg. 5827 --NumRegs; ++I; 5828 for (; NumRegs; --NumRegs, ++I) { 5829 assert(I != RC->end() && "Ran out of registers to allocate!"); 5830 Regs.push_back(*I); 5831 } 5832 } 5833 5834 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5835 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5836 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5837 return; 5838 } 5839 5840 // Otherwise, if this was a reference to an LLVM register class, create vregs 5841 // for this reference. 5842 if (const TargetRegisterClass *RC = PhysReg.second) { 5843 RegVT = *RC->vt_begin(); 5844 if (OpInfo.ConstraintVT == MVT::Other) 5845 ValueVT = RegVT; 5846 5847 // Create the appropriate number of virtual registers. 5848 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5849 for (; NumRegs; --NumRegs) 5850 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5851 5852 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5853 return; 5854 } 5855 5856 // Otherwise, we couldn't allocate enough registers for this. 5857} 5858 5859/// visitInlineAsm - Handle a call to an InlineAsm object. 5860/// 5861void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5862 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5863 5864 /// ConstraintOperands - Information about all of the constraints. 5865 SDISelAsmOperandInfoVector ConstraintOperands; 5866 5867 std::set<unsigned> OutputRegs, InputRegs; 5868 5869 TargetLowering::AsmOperandInfoVector 5870 TargetConstraints = TLI.ParseConstraints(CS); 5871 5872 bool hasMemory = false; 5873 5874 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5875 unsigned ResNo = 0; // ResNo - The result number of the next output. 5876 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5877 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5878 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5879 5880 EVT OpVT = MVT::Other; 5881 5882 // Compute the value type for each operand. 5883 switch (OpInfo.Type) { 5884 case InlineAsm::isOutput: 5885 // Indirect outputs just consume an argument. 5886 if (OpInfo.isIndirect) { 5887 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5888 break; 5889 } 5890 5891 // The return value of the call is this value. As such, there is no 5892 // corresponding argument. 5893 assert(!CS.getType()->isVoidTy() && 5894 "Bad inline asm!"); 5895 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5896 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5897 } else { 5898 assert(ResNo == 0 && "Asm only has one result!"); 5899 OpVT = TLI.getValueType(CS.getType()); 5900 } 5901 ++ResNo; 5902 break; 5903 case InlineAsm::isInput: 5904 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5905 break; 5906 case InlineAsm::isClobber: 5907 // Nothing to do. 5908 break; 5909 } 5910 5911 // If this is an input or an indirect output, process the call argument. 5912 // BasicBlocks are labels, currently appearing only in asm's. 5913 if (OpInfo.CallOperandVal) { 5914 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5915 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5916 } else { 5917 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5918 } 5919 5920 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5921 } 5922 5923 OpInfo.ConstraintVT = OpVT; 5924 5925 // Indirect operand accesses access memory. 5926 if (OpInfo.isIndirect) 5927 hasMemory = true; 5928 else { 5929 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5930 TargetLowering::ConstraintType 5931 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5932 if (CType == TargetLowering::C_Memory) { 5933 hasMemory = true; 5934 break; 5935 } 5936 } 5937 } 5938 } 5939 5940 SDValue Chain, Flag; 5941 5942 // We won't need to flush pending loads if this asm doesn't touch 5943 // memory and is nonvolatile. 5944 if (hasMemory || IA->hasSideEffects()) 5945 Chain = getRoot(); 5946 else 5947 Chain = DAG.getRoot(); 5948 5949 // Second pass over the constraints: compute which constraint option to use 5950 // and assign registers to constraints that want a specific physreg. 5951 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5952 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5953 5954 // If this is an output operand with a matching input operand, look up the 5955 // matching input. If their types mismatch, e.g. one is an integer, the 5956 // other is floating point, or their sizes are different, flag it as an 5957 // error. 5958 if (OpInfo.hasMatchingInput()) { 5959 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5960 5961 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5962 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5963 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5964 OpInfo.ConstraintVT); 5965 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5966 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 5967 Input.ConstraintVT); 5968 if ((OpInfo.ConstraintVT.isInteger() != 5969 Input.ConstraintVT.isInteger()) || 5970 (MatchRC.second != InputRC.second)) { 5971 report_fatal_error("Unsupported asm: input constraint" 5972 " with a matching output constraint of" 5973 " incompatible type!"); 5974 } 5975 Input.ConstraintVT = OpInfo.ConstraintVT; 5976 } 5977 } 5978 5979 // Compute the constraint code and ConstraintType to use. 5980 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5981 5982 // If this is a memory input, and if the operand is not indirect, do what we 5983 // need to to provide an address for the memory input. 5984 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5985 !OpInfo.isIndirect) { 5986 assert((OpInfo.isMultipleAlternative || 5987 (OpInfo.Type == InlineAsm::isInput)) && 5988 "Can only indirectify direct input operands!"); 5989 5990 // Memory operands really want the address of the value. If we don't have 5991 // an indirect input, put it in the constpool if we can, otherwise spill 5992 // it to a stack slot. 5993 // TODO: This isn't quite right. We need to handle these according to 5994 // the addressing mode that the constraint wants. Also, this may take 5995 // an additional register for the computation and we don't want that 5996 // either. 5997 5998 // If the operand is a float, integer, or vector constant, spill to a 5999 // constant pool entry to get its address. 6000 const Value *OpVal = OpInfo.CallOperandVal; 6001 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 6002 isa<ConstantVector>(OpVal)) { 6003 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 6004 TLI.getPointerTy()); 6005 } else { 6006 // Otherwise, create a stack slot and emit a store to it before the 6007 // asm. 6008 Type *Ty = OpVal->getType(); 6009 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 6010 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 6011 MachineFunction &MF = DAG.getMachineFunction(); 6012 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 6013 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 6014 Chain = DAG.getStore(Chain, getCurDebugLoc(), 6015 OpInfo.CallOperand, StackSlot, 6016 MachinePointerInfo::getFixedStack(SSFI), 6017 false, false, 0); 6018 OpInfo.CallOperand = StackSlot; 6019 } 6020 6021 // There is no longer a Value* corresponding to this operand. 6022 OpInfo.CallOperandVal = 0; 6023 6024 // It is now an indirect operand. 6025 OpInfo.isIndirect = true; 6026 } 6027 6028 // If this constraint is for a specific register, allocate it before 6029 // anything else. 6030 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6031 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 6032 InputRegs); 6033 } 6034 6035 // Second pass - Loop over all of the operands, assigning virtual or physregs 6036 // to register class operands. 6037 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6038 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6039 6040 // C_Register operands have already been allocated, Other/Memory don't need 6041 // to be. 6042 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6043 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 6044 InputRegs); 6045 } 6046 6047 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6048 std::vector<SDValue> AsmNodeOperands; 6049 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6050 AsmNodeOperands.push_back( 6051 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6052 TLI.getPointerTy())); 6053 6054 // If we have a !srcloc metadata node associated with it, we want to attach 6055 // this to the ultimately generated inline asm machineinstr. To do this, we 6056 // pass in the third operand as this (potentially null) inline asm MDNode. 6057 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6058 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6059 6060 // Remember the HasSideEffect and AlignStack bits as operand 3. 6061 unsigned ExtraInfo = 0; 6062 if (IA->hasSideEffects()) 6063 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6064 if (IA->isAlignStack()) 6065 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6066 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6067 TLI.getPointerTy())); 6068 6069 // Loop over all of the inputs, copying the operand values into the 6070 // appropriate registers and processing the output regs. 6071 RegsForValue RetValRegs; 6072 6073 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6074 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6075 6076 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6077 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6078 6079 switch (OpInfo.Type) { 6080 case InlineAsm::isOutput: { 6081 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6082 OpInfo.ConstraintType != TargetLowering::C_Register) { 6083 // Memory output, or 'other' output (e.g. 'X' constraint). 6084 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6085 6086 // Add information to the INLINEASM node to know about this output. 6087 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6088 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6089 TLI.getPointerTy())); 6090 AsmNodeOperands.push_back(OpInfo.CallOperand); 6091 break; 6092 } 6093 6094 // Otherwise, this is a register or register class output. 6095 6096 // Copy the output from the appropriate register. Find a register that 6097 // we can use. 6098 if (OpInfo.AssignedRegs.Regs.empty()) 6099 report_fatal_error("Couldn't allocate output reg for constraint '" + 6100 Twine(OpInfo.ConstraintCode) + "'!"); 6101 6102 // If this is an indirect operand, store through the pointer after the 6103 // asm. 6104 if (OpInfo.isIndirect) { 6105 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6106 OpInfo.CallOperandVal)); 6107 } else { 6108 // This is the result value of the call. 6109 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6110 // Concatenate this output onto the outputs list. 6111 RetValRegs.append(OpInfo.AssignedRegs); 6112 } 6113 6114 // Add information to the INLINEASM node to know that this register is 6115 // set. 6116 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6117 InlineAsm::Kind_RegDefEarlyClobber : 6118 InlineAsm::Kind_RegDef, 6119 false, 6120 0, 6121 DAG, 6122 AsmNodeOperands); 6123 break; 6124 } 6125 case InlineAsm::isInput: { 6126 SDValue InOperandVal = OpInfo.CallOperand; 6127 6128 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6129 // If this is required to match an output register we have already set, 6130 // just use its register. 6131 unsigned OperandNo = OpInfo.getMatchedOperand(); 6132 6133 // Scan until we find the definition we already emitted of this operand. 6134 // When we find it, create a RegsForValue operand. 6135 unsigned CurOp = InlineAsm::Op_FirstOperand; 6136 for (; OperandNo; --OperandNo) { 6137 // Advance to the next operand. 6138 unsigned OpFlag = 6139 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6140 assert((InlineAsm::isRegDefKind(OpFlag) || 6141 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6142 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6143 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6144 } 6145 6146 unsigned OpFlag = 6147 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6148 if (InlineAsm::isRegDefKind(OpFlag) || 6149 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6150 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6151 if (OpInfo.isIndirect) { 6152 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6153 LLVMContext &Ctx = *DAG.getContext(); 6154 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6155 " don't know how to handle tied " 6156 "indirect register inputs"); 6157 } 6158 6159 RegsForValue MatchedRegs; 6160 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6161 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6162 MatchedRegs.RegVTs.push_back(RegVT); 6163 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6164 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6165 i != e; ++i) 6166 MatchedRegs.Regs.push_back 6167 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6168 6169 // Use the produced MatchedRegs object to 6170 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6171 Chain, &Flag); 6172 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6173 true, OpInfo.getMatchedOperand(), 6174 DAG, AsmNodeOperands); 6175 break; 6176 } 6177 6178 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6179 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6180 "Unexpected number of operands"); 6181 // Add information to the INLINEASM node to know about this input. 6182 // See InlineAsm.h isUseOperandTiedToDef. 6183 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6184 OpInfo.getMatchedOperand()); 6185 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6186 TLI.getPointerTy())); 6187 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6188 break; 6189 } 6190 6191 // Treat indirect 'X' constraint as memory. 6192 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6193 OpInfo.isIndirect) 6194 OpInfo.ConstraintType = TargetLowering::C_Memory; 6195 6196 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6197 std::vector<SDValue> Ops; 6198 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6199 Ops, DAG); 6200 if (Ops.empty()) 6201 report_fatal_error("Invalid operand for inline asm constraint '" + 6202 Twine(OpInfo.ConstraintCode) + "'!"); 6203 6204 // Add information to the INLINEASM node to know about this input. 6205 unsigned ResOpType = 6206 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6207 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6208 TLI.getPointerTy())); 6209 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6210 break; 6211 } 6212 6213 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6214 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6215 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6216 "Memory operands expect pointer values"); 6217 6218 // Add information to the INLINEASM node to know about this input. 6219 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6220 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6221 TLI.getPointerTy())); 6222 AsmNodeOperands.push_back(InOperandVal); 6223 break; 6224 } 6225 6226 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6227 OpInfo.ConstraintType == TargetLowering::C_Register) && 6228 "Unknown constraint type!"); 6229 assert(!OpInfo.isIndirect && 6230 "Don't know how to handle indirect register inputs yet!"); 6231 6232 // Copy the input into the appropriate registers. 6233 if (OpInfo.AssignedRegs.Regs.empty()) 6234 report_fatal_error("Couldn't allocate input reg for constraint '" + 6235 Twine(OpInfo.ConstraintCode) + "'!"); 6236 6237 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6238 Chain, &Flag); 6239 6240 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6241 DAG, AsmNodeOperands); 6242 break; 6243 } 6244 case InlineAsm::isClobber: { 6245 // Add the clobbered value to the operand list, so that the register 6246 // allocator is aware that the physreg got clobbered. 6247 if (!OpInfo.AssignedRegs.Regs.empty()) 6248 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6249 false, 0, DAG, 6250 AsmNodeOperands); 6251 break; 6252 } 6253 } 6254 } 6255 6256 // Finish up input operands. Set the input chain and add the flag last. 6257 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6258 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6259 6260 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6261 DAG.getVTList(MVT::Other, MVT::Glue), 6262 &AsmNodeOperands[0], AsmNodeOperands.size()); 6263 Flag = Chain.getValue(1); 6264 6265 // If this asm returns a register value, copy the result from that register 6266 // and set it as the value of the call. 6267 if (!RetValRegs.Regs.empty()) { 6268 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6269 Chain, &Flag); 6270 6271 // FIXME: Why don't we do this for inline asms with MRVs? 6272 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6273 EVT ResultType = TLI.getValueType(CS.getType()); 6274 6275 // If any of the results of the inline asm is a vector, it may have the 6276 // wrong width/num elts. This can happen for register classes that can 6277 // contain multiple different value types. The preg or vreg allocated may 6278 // not have the same VT as was expected. Convert it to the right type 6279 // with bit_convert. 6280 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6281 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6282 ResultType, Val); 6283 6284 } else if (ResultType != Val.getValueType() && 6285 ResultType.isInteger() && Val.getValueType().isInteger()) { 6286 // If a result value was tied to an input value, the computed result may 6287 // have a wider width than the expected result. Extract the relevant 6288 // portion. 6289 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6290 } 6291 6292 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6293 } 6294 6295 setValue(CS.getInstruction(), Val); 6296 // Don't need to use this as a chain in this case. 6297 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6298 return; 6299 } 6300 6301 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6302 6303 // Process indirect outputs, first output all of the flagged copies out of 6304 // physregs. 6305 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6306 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6307 const Value *Ptr = IndirectStoresToEmit[i].second; 6308 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6309 Chain, &Flag); 6310 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6311 } 6312 6313 // Emit the non-flagged stores from the physregs. 6314 SmallVector<SDValue, 8> OutChains; 6315 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6316 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6317 StoresToEmit[i].first, 6318 getValue(StoresToEmit[i].second), 6319 MachinePointerInfo(StoresToEmit[i].second), 6320 false, false, 0); 6321 OutChains.push_back(Val); 6322 } 6323 6324 if (!OutChains.empty()) 6325 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6326 &OutChains[0], OutChains.size()); 6327 6328 DAG.setRoot(Chain); 6329} 6330 6331void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6332 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6333 MVT::Other, getRoot(), 6334 getValue(I.getArgOperand(0)), 6335 DAG.getSrcValue(I.getArgOperand(0)))); 6336} 6337 6338void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6339 const TargetData &TD = *TLI.getTargetData(); 6340 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6341 getRoot(), getValue(I.getOperand(0)), 6342 DAG.getSrcValue(I.getOperand(0)), 6343 TD.getABITypeAlignment(I.getType())); 6344 setValue(&I, V); 6345 DAG.setRoot(V.getValue(1)); 6346} 6347 6348void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6349 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6350 MVT::Other, getRoot(), 6351 getValue(I.getArgOperand(0)), 6352 DAG.getSrcValue(I.getArgOperand(0)))); 6353} 6354 6355void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6356 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6357 MVT::Other, getRoot(), 6358 getValue(I.getArgOperand(0)), 6359 getValue(I.getArgOperand(1)), 6360 DAG.getSrcValue(I.getArgOperand(0)), 6361 DAG.getSrcValue(I.getArgOperand(1)))); 6362} 6363 6364/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6365/// implementation, which just calls LowerCall. 6366/// FIXME: When all targets are 6367/// migrated to using LowerCall, this hook should be integrated into SDISel. 6368std::pair<SDValue, SDValue> 6369TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy, 6370 bool RetSExt, bool RetZExt, bool isVarArg, 6371 bool isInreg, unsigned NumFixedArgs, 6372 CallingConv::ID CallConv, bool isTailCall, 6373 bool isReturnValueUsed, 6374 SDValue Callee, 6375 ArgListTy &Args, SelectionDAG &DAG, 6376 DebugLoc dl) const { 6377 // Handle all of the outgoing arguments. 6378 SmallVector<ISD::OutputArg, 32> Outs; 6379 SmallVector<SDValue, 32> OutVals; 6380 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6381 SmallVector<EVT, 4> ValueVTs; 6382 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6383 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6384 Value != NumValues; ++Value) { 6385 EVT VT = ValueVTs[Value]; 6386 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6387 SDValue Op = SDValue(Args[i].Node.getNode(), 6388 Args[i].Node.getResNo() + Value); 6389 ISD::ArgFlagsTy Flags; 6390 unsigned OriginalAlignment = 6391 getTargetData()->getABITypeAlignment(ArgTy); 6392 6393 if (Args[i].isZExt) 6394 Flags.setZExt(); 6395 if (Args[i].isSExt) 6396 Flags.setSExt(); 6397 if (Args[i].isInReg) 6398 Flags.setInReg(); 6399 if (Args[i].isSRet) 6400 Flags.setSRet(); 6401 if (Args[i].isByVal) { 6402 Flags.setByVal(); 6403 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6404 Type *ElementTy = Ty->getElementType(); 6405 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6406 // For ByVal, alignment should come from FE. BE will guess if this 6407 // info is not there but there are cases it cannot get right. 6408 unsigned FrameAlign; 6409 if (Args[i].Alignment) 6410 FrameAlign = Args[i].Alignment; 6411 else 6412 FrameAlign = getByValTypeAlignment(ElementTy); 6413 Flags.setByValAlign(FrameAlign); 6414 } 6415 if (Args[i].isNest) 6416 Flags.setNest(); 6417 Flags.setOrigAlign(OriginalAlignment); 6418 6419 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6420 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6421 SmallVector<SDValue, 4> Parts(NumParts); 6422 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6423 6424 if (Args[i].isSExt) 6425 ExtendKind = ISD::SIGN_EXTEND; 6426 else if (Args[i].isZExt) 6427 ExtendKind = ISD::ZERO_EXTEND; 6428 6429 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6430 PartVT, ExtendKind); 6431 6432 for (unsigned j = 0; j != NumParts; ++j) { 6433 // if it isn't first piece, alignment must be 1 6434 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6435 i < NumFixedArgs); 6436 if (NumParts > 1 && j == 0) 6437 MyFlags.Flags.setSplit(); 6438 else if (j != 0) 6439 MyFlags.Flags.setOrigAlign(1); 6440 6441 Outs.push_back(MyFlags); 6442 OutVals.push_back(Parts[j]); 6443 } 6444 } 6445 } 6446 6447 // Handle the incoming return values from the call. 6448 SmallVector<ISD::InputArg, 32> Ins; 6449 SmallVector<EVT, 4> RetTys; 6450 ComputeValueVTs(*this, RetTy, RetTys); 6451 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6452 EVT VT = RetTys[I]; 6453 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6454 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6455 for (unsigned i = 0; i != NumRegs; ++i) { 6456 ISD::InputArg MyFlags; 6457 MyFlags.VT = RegisterVT.getSimpleVT(); 6458 MyFlags.Used = isReturnValueUsed; 6459 if (RetSExt) 6460 MyFlags.Flags.setSExt(); 6461 if (RetZExt) 6462 MyFlags.Flags.setZExt(); 6463 if (isInreg) 6464 MyFlags.Flags.setInReg(); 6465 Ins.push_back(MyFlags); 6466 } 6467 } 6468 6469 SmallVector<SDValue, 4> InVals; 6470 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6471 Outs, OutVals, Ins, dl, DAG, InVals); 6472 6473 // Verify that the target's LowerCall behaved as expected. 6474 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6475 "LowerCall didn't return a valid chain!"); 6476 assert((!isTailCall || InVals.empty()) && 6477 "LowerCall emitted a return value for a tail call!"); 6478 assert((isTailCall || InVals.size() == Ins.size()) && 6479 "LowerCall didn't emit the correct number of values!"); 6480 6481 // For a tail call, the return value is merely live-out and there aren't 6482 // any nodes in the DAG representing it. Return a special value to 6483 // indicate that a tail call has been emitted and no more Instructions 6484 // should be processed in the current block. 6485 if (isTailCall) { 6486 DAG.setRoot(Chain); 6487 return std::make_pair(SDValue(), SDValue()); 6488 } 6489 6490 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6491 assert(InVals[i].getNode() && 6492 "LowerCall emitted a null value!"); 6493 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6494 "LowerCall emitted a value with the wrong type!"); 6495 }); 6496 6497 // Collect the legal value parts into potentially illegal values 6498 // that correspond to the original function's return values. 6499 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6500 if (RetSExt) 6501 AssertOp = ISD::AssertSext; 6502 else if (RetZExt) 6503 AssertOp = ISD::AssertZext; 6504 SmallVector<SDValue, 4> ReturnValues; 6505 unsigned CurReg = 0; 6506 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6507 EVT VT = RetTys[I]; 6508 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6509 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6510 6511 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6512 NumRegs, RegisterVT, VT, 6513 AssertOp)); 6514 CurReg += NumRegs; 6515 } 6516 6517 // For a function returning void, there is no return value. We can't create 6518 // such a node, so we just return a null return value in that case. In 6519 // that case, nothing will actually look at the value. 6520 if (ReturnValues.empty()) 6521 return std::make_pair(SDValue(), Chain); 6522 6523 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6524 DAG.getVTList(&RetTys[0], RetTys.size()), 6525 &ReturnValues[0], ReturnValues.size()); 6526 return std::make_pair(Res, Chain); 6527} 6528 6529void TargetLowering::LowerOperationWrapper(SDNode *N, 6530 SmallVectorImpl<SDValue> &Results, 6531 SelectionDAG &DAG) const { 6532 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6533 if (Res.getNode()) 6534 Results.push_back(Res); 6535} 6536 6537SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6538 llvm_unreachable("LowerOperation not implemented for this target!"); 6539 return SDValue(); 6540} 6541 6542void 6543SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6544 SDValue Op = getNonRegisterValue(V); 6545 assert((Op.getOpcode() != ISD::CopyFromReg || 6546 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6547 "Copy from a reg to the same reg!"); 6548 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6549 6550 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6551 SDValue Chain = DAG.getEntryNode(); 6552 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6553 PendingExports.push_back(Chain); 6554} 6555 6556#include "llvm/CodeGen/SelectionDAGISel.h" 6557 6558/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6559/// entry block, return true. This includes arguments used by switches, since 6560/// the switch may expand into multiple basic blocks. 6561static bool isOnlyUsedInEntryBlock(const Argument *A) { 6562 // With FastISel active, we may be splitting blocks, so force creation 6563 // of virtual registers for all non-dead arguments. 6564 if (EnableFastISel) 6565 return A->use_empty(); 6566 6567 const BasicBlock *Entry = A->getParent()->begin(); 6568 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6569 UI != E; ++UI) { 6570 const User *U = *UI; 6571 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6572 return false; // Use not in entry block. 6573 } 6574 return true; 6575} 6576 6577void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6578 // If this is the entry block, emit arguments. 6579 const Function &F = *LLVMBB->getParent(); 6580 SelectionDAG &DAG = SDB->DAG; 6581 DebugLoc dl = SDB->getCurDebugLoc(); 6582 const TargetData *TD = TLI.getTargetData(); 6583 SmallVector<ISD::InputArg, 16> Ins; 6584 6585 // Check whether the function can return without sret-demotion. 6586 SmallVector<ISD::OutputArg, 4> Outs; 6587 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6588 Outs, TLI); 6589 6590 if (!FuncInfo->CanLowerReturn) { 6591 // Put in an sret pointer parameter before all the other parameters. 6592 SmallVector<EVT, 1> ValueVTs; 6593 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6594 6595 // NOTE: Assuming that a pointer will never break down to more than one VT 6596 // or one register. 6597 ISD::ArgFlagsTy Flags; 6598 Flags.setSRet(); 6599 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6600 ISD::InputArg RetArg(Flags, RegisterVT, true); 6601 Ins.push_back(RetArg); 6602 } 6603 6604 // Set up the incoming argument description vector. 6605 unsigned Idx = 1; 6606 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6607 I != E; ++I, ++Idx) { 6608 SmallVector<EVT, 4> ValueVTs; 6609 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6610 bool isArgValueUsed = !I->use_empty(); 6611 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6612 Value != NumValues; ++Value) { 6613 EVT VT = ValueVTs[Value]; 6614 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6615 ISD::ArgFlagsTy Flags; 6616 unsigned OriginalAlignment = 6617 TD->getABITypeAlignment(ArgTy); 6618 6619 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6620 Flags.setZExt(); 6621 if (F.paramHasAttr(Idx, Attribute::SExt)) 6622 Flags.setSExt(); 6623 if (F.paramHasAttr(Idx, Attribute::InReg)) 6624 Flags.setInReg(); 6625 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6626 Flags.setSRet(); 6627 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6628 Flags.setByVal(); 6629 PointerType *Ty = cast<PointerType>(I->getType()); 6630 Type *ElementTy = Ty->getElementType(); 6631 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6632 // For ByVal, alignment should be passed from FE. BE will guess if 6633 // this info is not there but there are cases it cannot get right. 6634 unsigned FrameAlign; 6635 if (F.getParamAlignment(Idx)) 6636 FrameAlign = F.getParamAlignment(Idx); 6637 else 6638 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6639 Flags.setByValAlign(FrameAlign); 6640 } 6641 if (F.paramHasAttr(Idx, Attribute::Nest)) 6642 Flags.setNest(); 6643 Flags.setOrigAlign(OriginalAlignment); 6644 6645 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6646 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6647 for (unsigned i = 0; i != NumRegs; ++i) { 6648 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6649 if (NumRegs > 1 && i == 0) 6650 MyFlags.Flags.setSplit(); 6651 // if it isn't first piece, alignment must be 1 6652 else if (i > 0) 6653 MyFlags.Flags.setOrigAlign(1); 6654 Ins.push_back(MyFlags); 6655 } 6656 } 6657 } 6658 6659 // Call the target to set up the argument values. 6660 SmallVector<SDValue, 8> InVals; 6661 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6662 F.isVarArg(), Ins, 6663 dl, DAG, InVals); 6664 6665 // Verify that the target's LowerFormalArguments behaved as expected. 6666 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6667 "LowerFormalArguments didn't return a valid chain!"); 6668 assert(InVals.size() == Ins.size() && 6669 "LowerFormalArguments didn't emit the correct number of values!"); 6670 DEBUG({ 6671 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6672 assert(InVals[i].getNode() && 6673 "LowerFormalArguments emitted a null value!"); 6674 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6675 "LowerFormalArguments emitted a value with the wrong type!"); 6676 } 6677 }); 6678 6679 // Update the DAG with the new chain value resulting from argument lowering. 6680 DAG.setRoot(NewRoot); 6681 6682 // Set up the argument values. 6683 unsigned i = 0; 6684 Idx = 1; 6685 if (!FuncInfo->CanLowerReturn) { 6686 // Create a virtual register for the sret pointer, and put in a copy 6687 // from the sret argument into it. 6688 SmallVector<EVT, 1> ValueVTs; 6689 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6690 EVT VT = ValueVTs[0]; 6691 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6692 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6693 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6694 RegVT, VT, AssertOp); 6695 6696 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6697 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6698 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6699 FuncInfo->DemoteRegister = SRetReg; 6700 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6701 SRetReg, ArgValue); 6702 DAG.setRoot(NewRoot); 6703 6704 // i indexes lowered arguments. Bump it past the hidden sret argument. 6705 // Idx indexes LLVM arguments. Don't touch it. 6706 ++i; 6707 } 6708 6709 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6710 ++I, ++Idx) { 6711 SmallVector<SDValue, 4> ArgValues; 6712 SmallVector<EVT, 4> ValueVTs; 6713 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6714 unsigned NumValues = ValueVTs.size(); 6715 6716 // If this argument is unused then remember its value. It is used to generate 6717 // debugging information. 6718 if (I->use_empty() && NumValues) 6719 SDB->setUnusedArgValue(I, InVals[i]); 6720 6721 for (unsigned Val = 0; Val != NumValues; ++Val) { 6722 EVT VT = ValueVTs[Val]; 6723 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6724 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6725 6726 if (!I->use_empty()) { 6727 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6728 if (F.paramHasAttr(Idx, Attribute::SExt)) 6729 AssertOp = ISD::AssertSext; 6730 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6731 AssertOp = ISD::AssertZext; 6732 6733 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6734 NumParts, PartVT, VT, 6735 AssertOp)); 6736 } 6737 6738 i += NumParts; 6739 } 6740 6741 // We don't need to do anything else for unused arguments. 6742 if (ArgValues.empty()) 6743 continue; 6744 6745 // Note down frame index. 6746 if (FrameIndexSDNode *FI = 6747 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6748 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6749 6750 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6751 SDB->getCurDebugLoc()); 6752 6753 SDB->setValue(I, Res); 6754 if (!EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6755 if (LoadSDNode *LNode = 6756 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6757 if (FrameIndexSDNode *FI = 6758 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6759 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6760 } 6761 6762 // If this argument is live outside of the entry block, insert a copy from 6763 // wherever we got it to the vreg that other BB's will reference it as. 6764 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6765 // If we can, though, try to skip creating an unnecessary vreg. 6766 // FIXME: This isn't very clean... it would be nice to make this more 6767 // general. It's also subtly incompatible with the hacks FastISel 6768 // uses with vregs. 6769 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6770 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6771 FuncInfo->ValueMap[I] = Reg; 6772 continue; 6773 } 6774 } 6775 if (!isOnlyUsedInEntryBlock(I)) { 6776 FuncInfo->InitializeRegForValue(I); 6777 SDB->CopyToExportRegsIfNeeded(I); 6778 } 6779 } 6780 6781 assert(i == InVals.size() && "Argument register count mismatch!"); 6782 6783 // Finally, if the target has anything special to do, allow it to do so. 6784 // FIXME: this should insert code into the DAG! 6785 EmitFunctionEntryCode(); 6786} 6787 6788/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6789/// ensure constants are generated when needed. Remember the virtual registers 6790/// that need to be added to the Machine PHI nodes as input. We cannot just 6791/// directly add them, because expansion might result in multiple MBB's for one 6792/// BB. As such, the start of the BB might correspond to a different MBB than 6793/// the end. 6794/// 6795void 6796SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6797 const TerminatorInst *TI = LLVMBB->getTerminator(); 6798 6799 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6800 6801 // Check successor nodes' PHI nodes that expect a constant to be available 6802 // from this block. 6803 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6804 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6805 if (!isa<PHINode>(SuccBB->begin())) continue; 6806 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6807 6808 // If this terminator has multiple identical successors (common for 6809 // switches), only handle each succ once. 6810 if (!SuccsHandled.insert(SuccMBB)) continue; 6811 6812 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6813 6814 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6815 // nodes and Machine PHI nodes, but the incoming operands have not been 6816 // emitted yet. 6817 for (BasicBlock::const_iterator I = SuccBB->begin(); 6818 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6819 // Ignore dead phi's. 6820 if (PN->use_empty()) continue; 6821 6822 // Skip empty types 6823 if (PN->getType()->isEmptyTy()) 6824 continue; 6825 6826 unsigned Reg; 6827 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6828 6829 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6830 unsigned &RegOut = ConstantsOut[C]; 6831 if (RegOut == 0) { 6832 RegOut = FuncInfo.CreateRegs(C->getType()); 6833 CopyValueToVirtualRegister(C, RegOut); 6834 } 6835 Reg = RegOut; 6836 } else { 6837 DenseMap<const Value *, unsigned>::iterator I = 6838 FuncInfo.ValueMap.find(PHIOp); 6839 if (I != FuncInfo.ValueMap.end()) 6840 Reg = I->second; 6841 else { 6842 assert(isa<AllocaInst>(PHIOp) && 6843 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6844 "Didn't codegen value into a register!??"); 6845 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6846 CopyValueToVirtualRegister(PHIOp, Reg); 6847 } 6848 } 6849 6850 // Remember that this register needs to added to the machine PHI node as 6851 // the input for this MBB. 6852 SmallVector<EVT, 4> ValueVTs; 6853 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6854 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6855 EVT VT = ValueVTs[vti]; 6856 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6857 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6858 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6859 Reg += NumRegisters; 6860 } 6861 } 6862 } 6863 ConstantsOut.clear(); 6864} 6865