SelectionDAGBuilder.cpp revision b45c96995924d1b74f2a91e85e21be98709285cd
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Analysis/DebugInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameLowering.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetIntrinsicInfo.h" 50#include "llvm/Target/TargetLibraryInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72// Limit the width of DAG chains. This is important in general to prevent 73// prevent DAG-based analysis from blowing up. For example, alias analysis and 74// load clustering may not complete in reasonable time. It is difficult to 75// recognize and avoid this situation within each individual analysis, and 76// future analyses are likely to have the same behavior. Limiting DAG width is 77// the safe approach, and will be especially important with global DAGs. 78// 79// MaxParallelChains default is arbitrarily high to avoid affecting 80// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81// sequence over this should have been converted to llvm.memcpy by the 82// frontend. It easy to induce this behavior with .ll code such as: 83// %buffer = alloca [4096 x i8] 84// %data = load [4096 x i8]* %argPtr 85// store [4096 x i8] %data, [4096 x i8]* %buffer 86static const unsigned MaxParallelChains = 64; 87 88static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92/// getCopyFromParts - Create a value that contains the specified legal parts 93/// combined into the value they represent. If the parts combine to a type 94/// larger then ValueVT then AssertOp can be used to specify whether the extra 95/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96/// (ISD::AssertSext). 97static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getTargetConstant(1, TLI.getPointerTy())); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209} 210 211/// getCopyFromParts - Create a value that contains the specified legal parts 212/// combined into the value they represent. If the parts combine to a type 213/// larger then ValueVT then AssertOp can be used to specify whether the extra 214/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 215/// (ISD::AssertSext). 216static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 217 const SDValue *Parts, unsigned NumParts, 218 EVT PartVT, EVT ValueVT) { 219 assert(ValueVT.isVector() && "Not a vector value"); 220 assert(NumParts > 0 && "No parts to assemble!"); 221 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 222 SDValue Val = Parts[0]; 223 224 // Handle a multi-element vector. 225 if (NumParts > 1) { 226 EVT IntermediateVT, RegisterVT; 227 unsigned NumIntermediates; 228 unsigned NumRegs = 229 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 230 NumIntermediates, RegisterVT); 231 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 232 NumParts = NumRegs; // Silence a compiler warning. 233 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 234 assert(RegisterVT == Parts[0].getValueType() && 235 "Part type doesn't match part!"); 236 237 // Assemble the parts into intermediate operands. 238 SmallVector<SDValue, 8> Ops(NumIntermediates); 239 if (NumIntermediates == NumParts) { 240 // If the register was not expanded, truncate or copy the value, 241 // as appropriate. 242 for (unsigned i = 0; i != NumParts; ++i) 243 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 244 PartVT, IntermediateVT); 245 } else if (NumParts > 0) { 246 // If the intermediate type was expanded, build the intermediate 247 // operands from the parts. 248 assert(NumParts % NumIntermediates == 0 && 249 "Must expand into a divisible number of parts!"); 250 unsigned Factor = NumParts / NumIntermediates; 251 for (unsigned i = 0; i != NumIntermediates; ++i) 252 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 253 PartVT, IntermediateVT); 254 } 255 256 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 257 // intermediate operands. 258 Val = DAG.getNode(IntermediateVT.isVector() ? 259 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 260 ValueVT, &Ops[0], NumIntermediates); 261 } 262 263 // There is now one part, held in Val. Correct it to match ValueVT. 264 PartVT = Val.getValueType(); 265 266 if (PartVT == ValueVT) 267 return Val; 268 269 if (PartVT.isVector()) { 270 // If the element type of the source/dest vectors are the same, but the 271 // parts vector has more elements than the value vector, then we have a 272 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 273 // elements we want. 274 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 275 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 276 "Cannot narrow, it would be a lossy transformation"); 277 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 278 DAG.getIntPtrConstant(0)); 279 } 280 281 // Vector/Vector bitcast. 282 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 283 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 284 285 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 286 "Cannot handle this kind of promotion"); 287 // Promoted vector extract 288 bool Smaller = ValueVT.bitsLE(PartVT); 289 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 290 DL, ValueVT, Val); 291 292 } 293 294 // Trivial bitcast if the types are the same size and the destination 295 // vector type is legal. 296 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 297 TLI.isTypeLegal(ValueVT)) 298 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 299 300 // Handle cases such as i8 -> <1 x i1> 301 assert(ValueVT.getVectorNumElements() == 1 && 302 "Only trivial scalar-to-vector conversions should get here!"); 303 304 if (ValueVT.getVectorNumElements() == 1 && 305 ValueVT.getVectorElementType() != PartVT) { 306 bool Smaller = ValueVT.bitsLE(PartVT); 307 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 308 DL, ValueVT.getScalarType(), Val); 309 } 310 311 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 312} 313 314 315 316 317static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 318 SDValue Val, SDValue *Parts, unsigned NumParts, 319 EVT PartVT); 320 321/// getCopyToParts - Create a series of nodes that contain the specified value 322/// split into legal parts. If the parts contain more bits than Val, then, for 323/// integers, ExtendKind can be used to specify how to generate the extra bits. 324static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 325 SDValue Val, SDValue *Parts, unsigned NumParts, 326 EVT PartVT, 327 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 328 EVT ValueVT = Val.getValueType(); 329 330 // Handle the vector case separately. 331 if (ValueVT.isVector()) 332 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 333 334 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 335 unsigned PartBits = PartVT.getSizeInBits(); 336 unsigned OrigNumParts = NumParts; 337 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 338 339 if (NumParts == 0) 340 return; 341 342 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 343 if (PartVT == ValueVT) { 344 assert(NumParts == 1 && "No-op copy with multiple parts!"); 345 Parts[0] = Val; 346 return; 347 } 348 349 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 350 // If the parts cover more bits than the value has, promote the value. 351 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 352 assert(NumParts == 1 && "Do not know what to promote to!"); 353 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 354 } else { 355 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 356 ValueVT.isInteger() && 357 "Unknown mismatch!"); 358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 360 if (PartVT == MVT::x86mmx) 361 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 362 } 363 } else if (PartBits == ValueVT.getSizeInBits()) { 364 // Different types of the same size. 365 assert(NumParts == 1 && PartVT != ValueVT); 366 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 367 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 368 // If the parts cover less bits than value has, truncate the value. 369 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 370 ValueVT.isInteger() && 371 "Unknown mismatch!"); 372 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 373 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 374 if (PartVT == MVT::x86mmx) 375 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 376 } 377 378 // The value may have changed - recompute ValueVT. 379 ValueVT = Val.getValueType(); 380 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 381 "Failed to tile the value with PartVT!"); 382 383 if (NumParts == 1) { 384 assert(PartVT == ValueVT && "Type conversion failed!"); 385 Parts[0] = Val; 386 return; 387 } 388 389 // Expand the value into multiple parts. 390 if (NumParts & (NumParts - 1)) { 391 // The number of parts is not a power of 2. Split off and copy the tail. 392 assert(PartVT.isInteger() && ValueVT.isInteger() && 393 "Do not know what to expand to!"); 394 unsigned RoundParts = 1 << Log2_32(NumParts); 395 unsigned RoundBits = RoundParts * PartBits; 396 unsigned OddParts = NumParts - RoundParts; 397 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 398 DAG.getIntPtrConstant(RoundBits)); 399 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 400 401 if (TLI.isBigEndian()) 402 // The odd parts were reversed by getCopyToParts - unreverse them. 403 std::reverse(Parts + RoundParts, Parts + NumParts); 404 405 NumParts = RoundParts; 406 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 407 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 408 } 409 410 // The number of parts is a power of 2. Repeatedly bisect the value using 411 // EXTRACT_ELEMENT. 412 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 413 EVT::getIntegerVT(*DAG.getContext(), 414 ValueVT.getSizeInBits()), 415 Val); 416 417 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 418 for (unsigned i = 0; i < NumParts; i += StepSize) { 419 unsigned ThisBits = StepSize * PartBits / 2; 420 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 421 SDValue &Part0 = Parts[i]; 422 SDValue &Part1 = Parts[i+StepSize/2]; 423 424 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 425 ThisVT, Part0, DAG.getIntPtrConstant(1)); 426 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 427 ThisVT, Part0, DAG.getIntPtrConstant(0)); 428 429 if (ThisBits == PartBits && ThisVT != PartVT) { 430 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 431 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 432 } 433 } 434 } 435 436 if (TLI.isBigEndian()) 437 std::reverse(Parts, Parts + OrigNumParts); 438} 439 440 441/// getCopyToPartsVector - Create a series of nodes that contain the specified 442/// value split into legal parts. 443static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 444 SDValue Val, SDValue *Parts, unsigned NumParts, 445 EVT PartVT) { 446 EVT ValueVT = Val.getValueType(); 447 assert(ValueVT.isVector() && "Not a vector"); 448 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 449 450 if (NumParts == 1) { 451 if (PartVT == ValueVT) { 452 // Nothing to do. 453 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 454 // Bitconvert vector->vector case. 455 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 456 } else if (PartVT.isVector() && 457 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 458 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 459 EVT ElementVT = PartVT.getVectorElementType(); 460 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 461 // undef elements. 462 SmallVector<SDValue, 16> Ops; 463 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 464 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 465 ElementVT, Val, DAG.getIntPtrConstant(i))); 466 467 for (unsigned i = ValueVT.getVectorNumElements(), 468 e = PartVT.getVectorNumElements(); i != e; ++i) 469 Ops.push_back(DAG.getUNDEF(ElementVT)); 470 471 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 472 473 // FIXME: Use CONCAT for 2x -> 4x. 474 475 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 476 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 477 } else if (PartVT.isVector() && 478 PartVT.getVectorElementType().bitsGE( 479 ValueVT.getVectorElementType()) && 480 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 481 482 // Promoted vector extract 483 bool Smaller = PartVT.bitsLE(ValueVT); 484 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 485 DL, PartVT, Val); 486 } else{ 487 // Vector -> scalar conversion. 488 assert(ValueVT.getVectorNumElements() == 1 && 489 "Only trivial vector-to-scalar conversions should get here!"); 490 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 491 PartVT, Val, DAG.getIntPtrConstant(0)); 492 493 bool Smaller = ValueVT.bitsLE(PartVT); 494 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 495 DL, PartVT, Val); 496 } 497 498 Parts[0] = Val; 499 return; 500 } 501 502 // Handle a multi-element vector. 503 EVT IntermediateVT, RegisterVT; 504 unsigned NumIntermediates; 505 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 506 IntermediateVT, 507 NumIntermediates, RegisterVT); 508 unsigned NumElements = ValueVT.getVectorNumElements(); 509 510 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 511 NumParts = NumRegs; // Silence a compiler warning. 512 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 513 514 // Split the vector into intermediate operands. 515 SmallVector<SDValue, 8> Ops(NumIntermediates); 516 for (unsigned i = 0; i != NumIntermediates; ++i) { 517 if (IntermediateVT.isVector()) 518 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 519 IntermediateVT, Val, 520 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 521 else 522 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 523 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 524 } 525 526 // Split the intermediate operands into legal parts. 527 if (NumParts == NumIntermediates) { 528 // If the register was not expanded, promote or copy the value, 529 // as appropriate. 530 for (unsigned i = 0; i != NumParts; ++i) 531 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 532 } else if (NumParts > 0) { 533 // If the intermediate type was expanded, split each the value into 534 // legal parts. 535 assert(NumParts % NumIntermediates == 0 && 536 "Must expand into a divisible number of parts!"); 537 unsigned Factor = NumParts / NumIntermediates; 538 for (unsigned i = 0; i != NumIntermediates; ++i) 539 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 540 } 541} 542 543 544 545 546namespace { 547 /// RegsForValue - This struct represents the registers (physical or virtual) 548 /// that a particular set of values is assigned, and the type information 549 /// about the value. The most common situation is to represent one value at a 550 /// time, but struct or array values are handled element-wise as multiple 551 /// values. The splitting of aggregates is performed recursively, so that we 552 /// never have aggregate-typed registers. The values at this point do not 553 /// necessarily have legal types, so each value may require one or more 554 /// registers of some legal type. 555 /// 556 struct RegsForValue { 557 /// ValueVTs - The value types of the values, which may not be legal, and 558 /// may need be promoted or synthesized from one or more registers. 559 /// 560 SmallVector<EVT, 4> ValueVTs; 561 562 /// RegVTs - The value types of the registers. This is the same size as 563 /// ValueVTs and it records, for each value, what the type of the assigned 564 /// register or registers are. (Individual values are never synthesized 565 /// from more than one type of register.) 566 /// 567 /// With virtual registers, the contents of RegVTs is redundant with TLI's 568 /// getRegisterType member function, however when with physical registers 569 /// it is necessary to have a separate record of the types. 570 /// 571 SmallVector<EVT, 4> RegVTs; 572 573 /// Regs - This list holds the registers assigned to the values. 574 /// Each legal or promoted value requires one register, and each 575 /// expanded value requires multiple registers. 576 /// 577 SmallVector<unsigned, 4> Regs; 578 579 RegsForValue() {} 580 581 RegsForValue(const SmallVector<unsigned, 4> ®s, 582 EVT regvt, EVT valuevt) 583 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 584 585 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 586 unsigned Reg, Type *Ty) { 587 ComputeValueVTs(tli, Ty, ValueVTs); 588 589 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 590 EVT ValueVT = ValueVTs[Value]; 591 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 592 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 593 for (unsigned i = 0; i != NumRegs; ++i) 594 Regs.push_back(Reg + i); 595 RegVTs.push_back(RegisterVT); 596 Reg += NumRegs; 597 } 598 } 599 600 /// areValueTypesLegal - Return true if types of all the values are legal. 601 bool areValueTypesLegal(const TargetLowering &TLI) { 602 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 603 EVT RegisterVT = RegVTs[Value]; 604 if (!TLI.isTypeLegal(RegisterVT)) 605 return false; 606 } 607 return true; 608 } 609 610 /// append - Add the specified values to this one. 611 void append(const RegsForValue &RHS) { 612 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 613 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 614 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 615 } 616 617 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 618 /// this value and returns the result as a ValueVTs value. This uses 619 /// Chain/Flag as the input and updates them for the output Chain/Flag. 620 /// If the Flag pointer is NULL, no flag is used. 621 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 622 DebugLoc dl, 623 SDValue &Chain, SDValue *Flag) const; 624 625 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 626 /// specified value into the registers specified by this object. This uses 627 /// Chain/Flag as the input and updates them for the output Chain/Flag. 628 /// If the Flag pointer is NULL, no flag is used. 629 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 630 SDValue &Chain, SDValue *Flag) const; 631 632 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 633 /// operand list. This adds the code marker, matching input operand index 634 /// (if applicable), and includes the number of values added into it. 635 void AddInlineAsmOperands(unsigned Kind, 636 bool HasMatching, unsigned MatchingIdx, 637 SelectionDAG &DAG, 638 std::vector<SDValue> &Ops) const; 639 }; 640} 641 642/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 643/// this value and returns the result as a ValueVT value. This uses 644/// Chain/Flag as the input and updates them for the output Chain/Flag. 645/// If the Flag pointer is NULL, no flag is used. 646SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 647 FunctionLoweringInfo &FuncInfo, 648 DebugLoc dl, 649 SDValue &Chain, SDValue *Flag) const { 650 // A Value with type {} or [0 x %t] needs no registers. 651 if (ValueVTs.empty()) 652 return SDValue(); 653 654 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 655 656 // Assemble the legal parts into the final values. 657 SmallVector<SDValue, 4> Values(ValueVTs.size()); 658 SmallVector<SDValue, 8> Parts; 659 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 660 // Copy the legal parts from the registers. 661 EVT ValueVT = ValueVTs[Value]; 662 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 663 EVT RegisterVT = RegVTs[Value]; 664 665 Parts.resize(NumRegs); 666 for (unsigned i = 0; i != NumRegs; ++i) { 667 SDValue P; 668 if (Flag == 0) { 669 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 670 } else { 671 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 672 *Flag = P.getValue(2); 673 } 674 675 Chain = P.getValue(1); 676 Parts[i] = P; 677 678 // If the source register was virtual and if we know something about it, 679 // add an assert node. 680 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 681 !RegisterVT.isInteger() || RegisterVT.isVector()) 682 continue; 683 684 const FunctionLoweringInfo::LiveOutInfo *LOI = 685 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 686 if (!LOI) 687 continue; 688 689 unsigned RegSize = RegisterVT.getSizeInBits(); 690 unsigned NumSignBits = LOI->NumSignBits; 691 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 692 693 // FIXME: We capture more information than the dag can represent. For 694 // now, just use the tightest assertzext/assertsext possible. 695 bool isSExt = true; 696 EVT FromVT(MVT::Other); 697 if (NumSignBits == RegSize) 698 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 699 else if (NumZeroBits >= RegSize-1) 700 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 701 else if (NumSignBits > RegSize-8) 702 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 703 else if (NumZeroBits >= RegSize-8) 704 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 705 else if (NumSignBits > RegSize-16) 706 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 707 else if (NumZeroBits >= RegSize-16) 708 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 709 else if (NumSignBits > RegSize-32) 710 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 711 else if (NumZeroBits >= RegSize-32) 712 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 713 else 714 continue; 715 716 // Add an assertion node. 717 assert(FromVT != MVT::Other); 718 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 719 RegisterVT, P, DAG.getValueType(FromVT)); 720 } 721 722 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 723 NumRegs, RegisterVT, ValueVT); 724 Part += NumRegs; 725 Parts.clear(); 726 } 727 728 return DAG.getNode(ISD::MERGE_VALUES, dl, 729 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 730 &Values[0], ValueVTs.size()); 731} 732 733/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 734/// specified value into the registers specified by this object. This uses 735/// Chain/Flag as the input and updates them for the output Chain/Flag. 736/// If the Flag pointer is NULL, no flag is used. 737void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 738 SDValue &Chain, SDValue *Flag) const { 739 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 740 741 // Get the list of the values's legal parts. 742 unsigned NumRegs = Regs.size(); 743 SmallVector<SDValue, 8> Parts(NumRegs); 744 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 745 EVT ValueVT = ValueVTs[Value]; 746 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 747 EVT RegisterVT = RegVTs[Value]; 748 749 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 750 &Parts[Part], NumParts, RegisterVT); 751 Part += NumParts; 752 } 753 754 // Copy the parts into the registers. 755 SmallVector<SDValue, 8> Chains(NumRegs); 756 for (unsigned i = 0; i != NumRegs; ++i) { 757 SDValue Part; 758 if (Flag == 0) { 759 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 760 } else { 761 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 762 *Flag = Part.getValue(1); 763 } 764 765 Chains[i] = Part.getValue(0); 766 } 767 768 if (NumRegs == 1 || Flag) 769 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 770 // flagged to it. That is the CopyToReg nodes and the user are considered 771 // a single scheduling unit. If we create a TokenFactor and return it as 772 // chain, then the TokenFactor is both a predecessor (operand) of the 773 // user as well as a successor (the TF operands are flagged to the user). 774 // c1, f1 = CopyToReg 775 // c2, f2 = CopyToReg 776 // c3 = TokenFactor c1, c2 777 // ... 778 // = op c3, ..., f2 779 Chain = Chains[NumRegs-1]; 780 else 781 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 782} 783 784/// AddInlineAsmOperands - Add this value to the specified inlineasm node 785/// operand list. This adds the code marker and includes the number of 786/// values added into it. 787void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 788 unsigned MatchingIdx, 789 SelectionDAG &DAG, 790 std::vector<SDValue> &Ops) const { 791 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 792 793 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 794 if (HasMatching) 795 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 796 else if (!Regs.empty() && 797 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 798 // Put the register class of the virtual registers in the flag word. That 799 // way, later passes can recompute register class constraints for inline 800 // assembly as well as normal instructions. 801 // Don't do this for tied operands that can use the regclass information 802 // from the def. 803 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 804 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 805 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 806 } 807 808 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 809 Ops.push_back(Res); 810 811 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 812 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 813 EVT RegisterVT = RegVTs[Value]; 814 for (unsigned i = 0; i != NumRegs; ++i) { 815 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 816 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 817 } 818 } 819} 820 821void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 822 const TargetLibraryInfo *li) { 823 AA = &aa; 824 GFI = gfi; 825 LibInfo = li; 826 TD = DAG.getTarget().getTargetData(); 827 LPadToCallSiteMap.clear(); 828} 829 830/// clear - Clear out the current SelectionDAG and the associated 831/// state and prepare this SelectionDAGBuilder object to be used 832/// for a new block. This doesn't clear out information about 833/// additional blocks that are needed to complete switch lowering 834/// or PHI node updating; that information is cleared out as it is 835/// consumed. 836void SelectionDAGBuilder::clear() { 837 NodeMap.clear(); 838 UnusedArgNodeMap.clear(); 839 PendingLoads.clear(); 840 PendingExports.clear(); 841 CurDebugLoc = DebugLoc(); 842 HasTailCall = false; 843} 844 845/// clearDanglingDebugInfo - Clear the dangling debug information 846/// map. This function is seperated from the clear so that debug 847/// information that is dangling in a basic block can be properly 848/// resolved in a different basic block. This allows the 849/// SelectionDAG to resolve dangling debug information attached 850/// to PHI nodes. 851void SelectionDAGBuilder::clearDanglingDebugInfo() { 852 DanglingDebugInfoMap.clear(); 853} 854 855/// getRoot - Return the current virtual root of the Selection DAG, 856/// flushing any PendingLoad items. This must be done before emitting 857/// a store or any other node that may need to be ordered after any 858/// prior load instructions. 859/// 860SDValue SelectionDAGBuilder::getRoot() { 861 if (PendingLoads.empty()) 862 return DAG.getRoot(); 863 864 if (PendingLoads.size() == 1) { 865 SDValue Root = PendingLoads[0]; 866 DAG.setRoot(Root); 867 PendingLoads.clear(); 868 return Root; 869 } 870 871 // Otherwise, we have to make a token factor node. 872 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 873 &PendingLoads[0], PendingLoads.size()); 874 PendingLoads.clear(); 875 DAG.setRoot(Root); 876 return Root; 877} 878 879/// getControlRoot - Similar to getRoot, but instead of flushing all the 880/// PendingLoad items, flush all the PendingExports items. It is necessary 881/// to do this before emitting a terminator instruction. 882/// 883SDValue SelectionDAGBuilder::getControlRoot() { 884 SDValue Root = DAG.getRoot(); 885 886 if (PendingExports.empty()) 887 return Root; 888 889 // Turn all of the CopyToReg chains into one factored node. 890 if (Root.getOpcode() != ISD::EntryToken) { 891 unsigned i = 0, e = PendingExports.size(); 892 for (; i != e; ++i) { 893 assert(PendingExports[i].getNode()->getNumOperands() > 1); 894 if (PendingExports[i].getNode()->getOperand(0) == Root) 895 break; // Don't add the root if we already indirectly depend on it. 896 } 897 898 if (i == e) 899 PendingExports.push_back(Root); 900 } 901 902 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 903 &PendingExports[0], 904 PendingExports.size()); 905 PendingExports.clear(); 906 DAG.setRoot(Root); 907 return Root; 908} 909 910void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 911 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 912 DAG.AssignOrdering(Node, SDNodeOrder); 913 914 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 915 AssignOrderingToNode(Node->getOperand(I).getNode()); 916} 917 918void SelectionDAGBuilder::visit(const Instruction &I) { 919 // Set up outgoing PHI node register values before emitting the terminator. 920 if (isa<TerminatorInst>(&I)) 921 HandlePHINodesInSuccessorBlocks(I.getParent()); 922 923 CurDebugLoc = I.getDebugLoc(); 924 925 visit(I.getOpcode(), I); 926 927 if (!isa<TerminatorInst>(&I) && !HasTailCall) 928 CopyToExportRegsIfNeeded(&I); 929 930 CurDebugLoc = DebugLoc(); 931} 932 933void SelectionDAGBuilder::visitPHI(const PHINode &) { 934 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 935} 936 937void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 938 // Note: this doesn't use InstVisitor, because it has to work with 939 // ConstantExpr's in addition to instructions. 940 switch (Opcode) { 941 default: llvm_unreachable("Unknown instruction type encountered!"); 942 // Build the switch statement using the Instruction.def file. 943#define HANDLE_INST(NUM, OPCODE, CLASS) \ 944 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 945#include "llvm/Instruction.def" 946 } 947 948 // Assign the ordering to the freshly created DAG nodes. 949 if (NodeMap.count(&I)) { 950 ++SDNodeOrder; 951 AssignOrderingToNode(getValue(&I).getNode()); 952 } 953} 954 955// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 956// generate the debug data structures now that we've seen its definition. 957void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 958 SDValue Val) { 959 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 960 if (DDI.getDI()) { 961 const DbgValueInst *DI = DDI.getDI(); 962 DebugLoc dl = DDI.getdl(); 963 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 964 MDNode *Variable = DI->getVariable(); 965 uint64_t Offset = DI->getOffset(); 966 SDDbgValue *SDV; 967 if (Val.getNode()) { 968 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 969 SDV = DAG.getDbgValue(Variable, Val.getNode(), 970 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 971 DAG.AddDbgValue(SDV, Val.getNode(), false); 972 } 973 } else 974 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 975 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 976 } 977} 978 979/// getValue - Return an SDValue for the given Value. 980SDValue SelectionDAGBuilder::getValue(const Value *V) { 981 // If we already have an SDValue for this value, use it. It's important 982 // to do this first, so that we don't create a CopyFromReg if we already 983 // have a regular SDValue. 984 SDValue &N = NodeMap[V]; 985 if (N.getNode()) return N; 986 987 // If there's a virtual register allocated and initialized for this 988 // value, use it. 989 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 990 if (It != FuncInfo.ValueMap.end()) { 991 unsigned InReg = It->second; 992 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 993 SDValue Chain = DAG.getEntryNode(); 994 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 995 resolveDanglingDebugInfo(V, N); 996 return N; 997 } 998 999 // Otherwise create a new SDValue and remember it. 1000 SDValue Val = getValueImpl(V); 1001 NodeMap[V] = Val; 1002 resolveDanglingDebugInfo(V, Val); 1003 return Val; 1004} 1005 1006/// getNonRegisterValue - Return an SDValue for the given Value, but 1007/// don't look in FuncInfo.ValueMap for a virtual register. 1008SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1009 // If we already have an SDValue for this value, use it. 1010 SDValue &N = NodeMap[V]; 1011 if (N.getNode()) return N; 1012 1013 // Otherwise create a new SDValue and remember it. 1014 SDValue Val = getValueImpl(V); 1015 NodeMap[V] = Val; 1016 resolveDanglingDebugInfo(V, Val); 1017 return Val; 1018} 1019 1020/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1021/// Create an SDValue for the given value. 1022SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1023 if (const Constant *C = dyn_cast<Constant>(V)) { 1024 EVT VT = TLI.getValueType(V->getType(), true); 1025 1026 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1027 return DAG.getConstant(*CI, VT); 1028 1029 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1030 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1031 1032 if (isa<ConstantPointerNull>(C)) 1033 return DAG.getConstant(0, TLI.getPointerTy()); 1034 1035 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1036 return DAG.getConstantFP(*CFP, VT); 1037 1038 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1039 return DAG.getUNDEF(VT); 1040 1041 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1042 visit(CE->getOpcode(), *CE); 1043 SDValue N1 = NodeMap[V]; 1044 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1045 return N1; 1046 } 1047 1048 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1049 SmallVector<SDValue, 4> Constants; 1050 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1051 OI != OE; ++OI) { 1052 SDNode *Val = getValue(*OI).getNode(); 1053 // If the operand is an empty aggregate, there are no values. 1054 if (!Val) continue; 1055 // Add each leaf value from the operand to the Constants list 1056 // to form a flattened list of all the values. 1057 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1058 Constants.push_back(SDValue(Val, i)); 1059 } 1060 1061 return DAG.getMergeValues(&Constants[0], Constants.size(), 1062 getCurDebugLoc()); 1063 } 1064 1065 if (const ConstantDataSequential *CDS = 1066 dyn_cast<ConstantDataSequential>(C)) { 1067 SmallVector<SDValue, 4> Ops; 1068 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { 1069 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1070 // Add each leaf value from the operand to the Constants list 1071 // to form a flattened list of all the values. 1072 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1073 Ops.push_back(SDValue(Val, i)); 1074 } 1075 1076 if (isa<ArrayType>(CDS->getType())) 1077 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc()); 1078 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1079 VT, &Ops[0], Ops.size()); 1080 } 1081 1082 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1083 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1084 "Unknown struct or array constant!"); 1085 1086 SmallVector<EVT, 4> ValueVTs; 1087 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1088 unsigned NumElts = ValueVTs.size(); 1089 if (NumElts == 0) 1090 return SDValue(); // empty struct 1091 SmallVector<SDValue, 4> Constants(NumElts); 1092 for (unsigned i = 0; i != NumElts; ++i) { 1093 EVT EltVT = ValueVTs[i]; 1094 if (isa<UndefValue>(C)) 1095 Constants[i] = DAG.getUNDEF(EltVT); 1096 else if (EltVT.isFloatingPoint()) 1097 Constants[i] = DAG.getConstantFP(0, EltVT); 1098 else 1099 Constants[i] = DAG.getConstant(0, EltVT); 1100 } 1101 1102 return DAG.getMergeValues(&Constants[0], NumElts, 1103 getCurDebugLoc()); 1104 } 1105 1106 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1107 return DAG.getBlockAddress(BA, VT); 1108 1109 VectorType *VecTy = cast<VectorType>(V->getType()); 1110 unsigned NumElements = VecTy->getNumElements(); 1111 1112 // Now that we know the number and type of the elements, get that number of 1113 // elements into the Ops array based on what kind of constant it is. 1114 SmallVector<SDValue, 16> Ops; 1115 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1116 for (unsigned i = 0; i != NumElements; ++i) 1117 Ops.push_back(getValue(CV->getOperand(i))); 1118 } else { 1119 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1120 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1121 1122 SDValue Op; 1123 if (EltVT.isFloatingPoint()) 1124 Op = DAG.getConstantFP(0, EltVT); 1125 else 1126 Op = DAG.getConstant(0, EltVT); 1127 Ops.assign(NumElements, Op); 1128 } 1129 1130 // Create a BUILD_VECTOR node. 1131 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1132 VT, &Ops[0], Ops.size()); 1133 } 1134 1135 // If this is a static alloca, generate it as the frameindex instead of 1136 // computation. 1137 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1138 DenseMap<const AllocaInst*, int>::iterator SI = 1139 FuncInfo.StaticAllocaMap.find(AI); 1140 if (SI != FuncInfo.StaticAllocaMap.end()) 1141 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1142 } 1143 1144 // If this is an instruction which fast-isel has deferred, select it now. 1145 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1146 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1147 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1148 SDValue Chain = DAG.getEntryNode(); 1149 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1150 } 1151 1152 llvm_unreachable("Can't get register for value!"); 1153} 1154 1155void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1156 SDValue Chain = getControlRoot(); 1157 SmallVector<ISD::OutputArg, 8> Outs; 1158 SmallVector<SDValue, 8> OutVals; 1159 1160 if (!FuncInfo.CanLowerReturn) { 1161 unsigned DemoteReg = FuncInfo.DemoteRegister; 1162 const Function *F = I.getParent()->getParent(); 1163 1164 // Emit a store of the return value through the virtual register. 1165 // Leave Outs empty so that LowerReturn won't try to load return 1166 // registers the usual way. 1167 SmallVector<EVT, 1> PtrValueVTs; 1168 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1169 PtrValueVTs); 1170 1171 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1172 SDValue RetOp = getValue(I.getOperand(0)); 1173 1174 SmallVector<EVT, 4> ValueVTs; 1175 SmallVector<uint64_t, 4> Offsets; 1176 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1177 unsigned NumValues = ValueVTs.size(); 1178 1179 SmallVector<SDValue, 4> Chains(NumValues); 1180 for (unsigned i = 0; i != NumValues; ++i) { 1181 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1182 RetPtr.getValueType(), RetPtr, 1183 DAG.getIntPtrConstant(Offsets[i])); 1184 Chains[i] = 1185 DAG.getStore(Chain, getCurDebugLoc(), 1186 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1187 // FIXME: better loc info would be nice. 1188 Add, MachinePointerInfo(), false, false, 0); 1189 } 1190 1191 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1192 MVT::Other, &Chains[0], NumValues); 1193 } else if (I.getNumOperands() != 0) { 1194 SmallVector<EVT, 4> ValueVTs; 1195 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1196 unsigned NumValues = ValueVTs.size(); 1197 if (NumValues) { 1198 SDValue RetOp = getValue(I.getOperand(0)); 1199 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1200 EVT VT = ValueVTs[j]; 1201 1202 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1203 1204 const Function *F = I.getParent()->getParent(); 1205 if (F->paramHasAttr(0, Attribute::SExt)) 1206 ExtendKind = ISD::SIGN_EXTEND; 1207 else if (F->paramHasAttr(0, Attribute::ZExt)) 1208 ExtendKind = ISD::ZERO_EXTEND; 1209 1210 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1211 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1212 1213 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1214 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1215 SmallVector<SDValue, 4> Parts(NumParts); 1216 getCopyToParts(DAG, getCurDebugLoc(), 1217 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1218 &Parts[0], NumParts, PartVT, ExtendKind); 1219 1220 // 'inreg' on function refers to return value 1221 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1222 if (F->paramHasAttr(0, Attribute::InReg)) 1223 Flags.setInReg(); 1224 1225 // Propagate extension type if any 1226 if (ExtendKind == ISD::SIGN_EXTEND) 1227 Flags.setSExt(); 1228 else if (ExtendKind == ISD::ZERO_EXTEND) 1229 Flags.setZExt(); 1230 1231 for (unsigned i = 0; i < NumParts; ++i) { 1232 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1233 /*isfixed=*/true)); 1234 OutVals.push_back(Parts[i]); 1235 } 1236 } 1237 } 1238 } 1239 1240 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1241 CallingConv::ID CallConv = 1242 DAG.getMachineFunction().getFunction()->getCallingConv(); 1243 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1244 Outs, OutVals, getCurDebugLoc(), DAG); 1245 1246 // Verify that the target's LowerReturn behaved as expected. 1247 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1248 "LowerReturn didn't return a valid chain!"); 1249 1250 // Update the DAG with the new chain value resulting from return lowering. 1251 DAG.setRoot(Chain); 1252} 1253 1254/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1255/// created for it, emit nodes to copy the value into the virtual 1256/// registers. 1257void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1258 // Skip empty types 1259 if (V->getType()->isEmptyTy()) 1260 return; 1261 1262 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1263 if (VMI != FuncInfo.ValueMap.end()) { 1264 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1265 CopyValueToVirtualRegister(V, VMI->second); 1266 } 1267} 1268 1269/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1270/// the current basic block, add it to ValueMap now so that we'll get a 1271/// CopyTo/FromReg. 1272void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1273 // No need to export constants. 1274 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1275 1276 // Already exported? 1277 if (FuncInfo.isExportedInst(V)) return; 1278 1279 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1280 CopyValueToVirtualRegister(V, Reg); 1281} 1282 1283bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1284 const BasicBlock *FromBB) { 1285 // The operands of the setcc have to be in this block. We don't know 1286 // how to export them from some other block. 1287 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1288 // Can export from current BB. 1289 if (VI->getParent() == FromBB) 1290 return true; 1291 1292 // Is already exported, noop. 1293 return FuncInfo.isExportedInst(V); 1294 } 1295 1296 // If this is an argument, we can export it if the BB is the entry block or 1297 // if it is already exported. 1298 if (isa<Argument>(V)) { 1299 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1300 return true; 1301 1302 // Otherwise, can only export this if it is already exported. 1303 return FuncInfo.isExportedInst(V); 1304 } 1305 1306 // Otherwise, constants can always be exported. 1307 return true; 1308} 1309 1310/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1311uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1312 const MachineBasicBlock *Dst) const { 1313 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1314 if (!BPI) 1315 return 0; 1316 const BasicBlock *SrcBB = Src->getBasicBlock(); 1317 const BasicBlock *DstBB = Dst->getBasicBlock(); 1318 return BPI->getEdgeWeight(SrcBB, DstBB); 1319} 1320 1321void SelectionDAGBuilder:: 1322addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1323 uint32_t Weight /* = 0 */) { 1324 if (!Weight) 1325 Weight = getEdgeWeight(Src, Dst); 1326 Src->addSuccessor(Dst, Weight); 1327} 1328 1329 1330static bool InBlock(const Value *V, const BasicBlock *BB) { 1331 if (const Instruction *I = dyn_cast<Instruction>(V)) 1332 return I->getParent() == BB; 1333 return true; 1334} 1335 1336/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1337/// This function emits a branch and is used at the leaves of an OR or an 1338/// AND operator tree. 1339/// 1340void 1341SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1342 MachineBasicBlock *TBB, 1343 MachineBasicBlock *FBB, 1344 MachineBasicBlock *CurBB, 1345 MachineBasicBlock *SwitchBB) { 1346 const BasicBlock *BB = CurBB->getBasicBlock(); 1347 1348 // If the leaf of the tree is a comparison, merge the condition into 1349 // the caseblock. 1350 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1351 // The operands of the cmp have to be in this block. We don't know 1352 // how to export them from some other block. If this is the first block 1353 // of the sequence, no exporting is needed. 1354 if (CurBB == SwitchBB || 1355 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1356 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1357 ISD::CondCode Condition; 1358 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1359 Condition = getICmpCondCode(IC->getPredicate()); 1360 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1361 Condition = getFCmpCondCode(FC->getPredicate()); 1362 if (TM.Options.NoNaNsFPMath) 1363 Condition = getFCmpCodeWithoutNaN(Condition); 1364 } else { 1365 Condition = ISD::SETEQ; // silence warning. 1366 llvm_unreachable("Unknown compare instruction"); 1367 } 1368 1369 CaseBlock CB(Condition, BOp->getOperand(0), 1370 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1371 SwitchCases.push_back(CB); 1372 return; 1373 } 1374 } 1375 1376 // Create a CaseBlock record representing this branch. 1377 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1378 NULL, TBB, FBB, CurBB); 1379 SwitchCases.push_back(CB); 1380} 1381 1382/// FindMergedConditions - If Cond is an expression like 1383void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1384 MachineBasicBlock *TBB, 1385 MachineBasicBlock *FBB, 1386 MachineBasicBlock *CurBB, 1387 MachineBasicBlock *SwitchBB, 1388 unsigned Opc) { 1389 // If this node is not part of the or/and tree, emit it as a branch. 1390 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1391 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1392 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1393 BOp->getParent() != CurBB->getBasicBlock() || 1394 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1395 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1396 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1397 return; 1398 } 1399 1400 // Create TmpBB after CurBB. 1401 MachineFunction::iterator BBI = CurBB; 1402 MachineFunction &MF = DAG.getMachineFunction(); 1403 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1404 CurBB->getParent()->insert(++BBI, TmpBB); 1405 1406 if (Opc == Instruction::Or) { 1407 // Codegen X | Y as: 1408 // jmp_if_X TBB 1409 // jmp TmpBB 1410 // TmpBB: 1411 // jmp_if_Y TBB 1412 // jmp FBB 1413 // 1414 1415 // Emit the LHS condition. 1416 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1417 1418 // Emit the RHS condition into TmpBB. 1419 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1420 } else { 1421 assert(Opc == Instruction::And && "Unknown merge op!"); 1422 // Codegen X & Y as: 1423 // jmp_if_X TmpBB 1424 // jmp FBB 1425 // TmpBB: 1426 // jmp_if_Y TBB 1427 // jmp FBB 1428 // 1429 // This requires creation of TmpBB after CurBB. 1430 1431 // Emit the LHS condition. 1432 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1433 1434 // Emit the RHS condition into TmpBB. 1435 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1436 } 1437} 1438 1439/// If the set of cases should be emitted as a series of branches, return true. 1440/// If we should emit this as a bunch of and/or'd together conditions, return 1441/// false. 1442bool 1443SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1444 if (Cases.size() != 2) return true; 1445 1446 // If this is two comparisons of the same values or'd or and'd together, they 1447 // will get folded into a single comparison, so don't emit two blocks. 1448 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1449 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1450 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1451 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1452 return false; 1453 } 1454 1455 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1456 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1457 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1458 Cases[0].CC == Cases[1].CC && 1459 isa<Constant>(Cases[0].CmpRHS) && 1460 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1461 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1462 return false; 1463 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1464 return false; 1465 } 1466 1467 return true; 1468} 1469 1470void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1471 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1472 1473 // Update machine-CFG edges. 1474 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1475 1476 // Figure out which block is immediately after the current one. 1477 MachineBasicBlock *NextBlock = 0; 1478 MachineFunction::iterator BBI = BrMBB; 1479 if (++BBI != FuncInfo.MF->end()) 1480 NextBlock = BBI; 1481 1482 if (I.isUnconditional()) { 1483 // Update machine-CFG edges. 1484 BrMBB->addSuccessor(Succ0MBB); 1485 1486 // If this is not a fall-through branch, emit the branch. 1487 if (Succ0MBB != NextBlock) 1488 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1489 MVT::Other, getControlRoot(), 1490 DAG.getBasicBlock(Succ0MBB))); 1491 1492 return; 1493 } 1494 1495 // If this condition is one of the special cases we handle, do special stuff 1496 // now. 1497 const Value *CondVal = I.getCondition(); 1498 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1499 1500 // If this is a series of conditions that are or'd or and'd together, emit 1501 // this as a sequence of branches instead of setcc's with and/or operations. 1502 // As long as jumps are not expensive, this should improve performance. 1503 // For example, instead of something like: 1504 // cmp A, B 1505 // C = seteq 1506 // cmp D, E 1507 // F = setle 1508 // or C, F 1509 // jnz foo 1510 // Emit: 1511 // cmp A, B 1512 // je foo 1513 // cmp D, E 1514 // jle foo 1515 // 1516 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1517 if (!TLI.isJumpExpensive() && 1518 BOp->hasOneUse() && 1519 (BOp->getOpcode() == Instruction::And || 1520 BOp->getOpcode() == Instruction::Or)) { 1521 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1522 BOp->getOpcode()); 1523 // If the compares in later blocks need to use values not currently 1524 // exported from this block, export them now. This block should always 1525 // be the first entry. 1526 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1527 1528 // Allow some cases to be rejected. 1529 if (ShouldEmitAsBranches(SwitchCases)) { 1530 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1531 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1532 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1533 } 1534 1535 // Emit the branch for this block. 1536 visitSwitchCase(SwitchCases[0], BrMBB); 1537 SwitchCases.erase(SwitchCases.begin()); 1538 return; 1539 } 1540 1541 // Okay, we decided not to do this, remove any inserted MBB's and clear 1542 // SwitchCases. 1543 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1544 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1545 1546 SwitchCases.clear(); 1547 } 1548 } 1549 1550 // Create a CaseBlock record representing this branch. 1551 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1552 NULL, Succ0MBB, Succ1MBB, BrMBB); 1553 1554 // Use visitSwitchCase to actually insert the fast branch sequence for this 1555 // cond branch. 1556 visitSwitchCase(CB, BrMBB); 1557} 1558 1559/// visitSwitchCase - Emits the necessary code to represent a single node in 1560/// the binary search tree resulting from lowering a switch instruction. 1561void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1562 MachineBasicBlock *SwitchBB) { 1563 SDValue Cond; 1564 SDValue CondLHS = getValue(CB.CmpLHS); 1565 DebugLoc dl = getCurDebugLoc(); 1566 1567 // Build the setcc now. 1568 if (CB.CmpMHS == NULL) { 1569 // Fold "(X == true)" to X and "(X == false)" to !X to 1570 // handle common cases produced by branch lowering. 1571 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1572 CB.CC == ISD::SETEQ) 1573 Cond = CondLHS; 1574 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1575 CB.CC == ISD::SETEQ) { 1576 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1577 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1578 } else 1579 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1580 } else { 1581 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1582 1583 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1584 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1585 1586 SDValue CmpOp = getValue(CB.CmpMHS); 1587 EVT VT = CmpOp.getValueType(); 1588 1589 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1590 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1591 ISD::SETLE); 1592 } else { 1593 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1594 VT, CmpOp, DAG.getConstant(Low, VT)); 1595 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1596 DAG.getConstant(High-Low, VT), ISD::SETULE); 1597 } 1598 } 1599 1600 // Update successor info 1601 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1602 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1603 1604 // Set NextBlock to be the MBB immediately after the current one, if any. 1605 // This is used to avoid emitting unnecessary branches to the next block. 1606 MachineBasicBlock *NextBlock = 0; 1607 MachineFunction::iterator BBI = SwitchBB; 1608 if (++BBI != FuncInfo.MF->end()) 1609 NextBlock = BBI; 1610 1611 // If the lhs block is the next block, invert the condition so that we can 1612 // fall through to the lhs instead of the rhs block. 1613 if (CB.TrueBB == NextBlock) { 1614 std::swap(CB.TrueBB, CB.FalseBB); 1615 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1616 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1617 } 1618 1619 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1620 MVT::Other, getControlRoot(), Cond, 1621 DAG.getBasicBlock(CB.TrueBB)); 1622 1623 // Insert the false branch. Do this even if it's a fall through branch, 1624 // this makes it easier to do DAG optimizations which require inverting 1625 // the branch condition. 1626 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1627 DAG.getBasicBlock(CB.FalseBB)); 1628 1629 DAG.setRoot(BrCond); 1630} 1631 1632/// visitJumpTable - Emit JumpTable node in the current MBB 1633void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1634 // Emit the code for the jump table 1635 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1636 EVT PTy = TLI.getPointerTy(); 1637 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1638 JT.Reg, PTy); 1639 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1640 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1641 MVT::Other, Index.getValue(1), 1642 Table, Index); 1643 DAG.setRoot(BrJumpTable); 1644} 1645 1646/// visitJumpTableHeader - This function emits necessary code to produce index 1647/// in the JumpTable from switch case. 1648void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1649 JumpTableHeader &JTH, 1650 MachineBasicBlock *SwitchBB) { 1651 // Subtract the lowest switch case value from the value being switched on and 1652 // conditional branch to default mbb if the result is greater than the 1653 // difference between smallest and largest cases. 1654 SDValue SwitchOp = getValue(JTH.SValue); 1655 EVT VT = SwitchOp.getValueType(); 1656 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1657 DAG.getConstant(JTH.First, VT)); 1658 1659 // The SDNode we just created, which holds the value being switched on minus 1660 // the smallest case value, needs to be copied to a virtual register so it 1661 // can be used as an index into the jump table in a subsequent basic block. 1662 // This value may be smaller or larger than the target's pointer type, and 1663 // therefore require extension or truncating. 1664 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1665 1666 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1667 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1668 JumpTableReg, SwitchOp); 1669 JT.Reg = JumpTableReg; 1670 1671 // Emit the range check for the jump table, and branch to the default block 1672 // for the switch statement if the value being switched on exceeds the largest 1673 // case in the switch. 1674 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1675 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1676 DAG.getConstant(JTH.Last-JTH.First,VT), 1677 ISD::SETUGT); 1678 1679 // Set NextBlock to be the MBB immediately after the current one, if any. 1680 // This is used to avoid emitting unnecessary branches to the next block. 1681 MachineBasicBlock *NextBlock = 0; 1682 MachineFunction::iterator BBI = SwitchBB; 1683 1684 if (++BBI != FuncInfo.MF->end()) 1685 NextBlock = BBI; 1686 1687 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1688 MVT::Other, CopyTo, CMP, 1689 DAG.getBasicBlock(JT.Default)); 1690 1691 if (JT.MBB != NextBlock) 1692 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1693 DAG.getBasicBlock(JT.MBB)); 1694 1695 DAG.setRoot(BrCond); 1696} 1697 1698/// visitBitTestHeader - This function emits necessary code to produce value 1699/// suitable for "bit tests" 1700void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1701 MachineBasicBlock *SwitchBB) { 1702 // Subtract the minimum value 1703 SDValue SwitchOp = getValue(B.SValue); 1704 EVT VT = SwitchOp.getValueType(); 1705 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1706 DAG.getConstant(B.First, VT)); 1707 1708 // Check range 1709 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1710 TLI.getSetCCResultType(Sub.getValueType()), 1711 Sub, DAG.getConstant(B.Range, VT), 1712 ISD::SETUGT); 1713 1714 // Determine the type of the test operands. 1715 bool UsePtrType = false; 1716 if (!TLI.isTypeLegal(VT)) 1717 UsePtrType = true; 1718 else { 1719 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1720 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1721 // Switch table case range are encoded into series of masks. 1722 // Just use pointer type, it's guaranteed to fit. 1723 UsePtrType = true; 1724 break; 1725 } 1726 } 1727 if (UsePtrType) { 1728 VT = TLI.getPointerTy(); 1729 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1730 } 1731 1732 B.RegVT = VT; 1733 B.Reg = FuncInfo.CreateReg(VT); 1734 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1735 B.Reg, Sub); 1736 1737 // Set NextBlock to be the MBB immediately after the current one, if any. 1738 // This is used to avoid emitting unnecessary branches to the next block. 1739 MachineBasicBlock *NextBlock = 0; 1740 MachineFunction::iterator BBI = SwitchBB; 1741 if (++BBI != FuncInfo.MF->end()) 1742 NextBlock = BBI; 1743 1744 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1745 1746 addSuccessorWithWeight(SwitchBB, B.Default); 1747 addSuccessorWithWeight(SwitchBB, MBB); 1748 1749 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1750 MVT::Other, CopyTo, RangeCmp, 1751 DAG.getBasicBlock(B.Default)); 1752 1753 if (MBB != NextBlock) 1754 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1755 DAG.getBasicBlock(MBB)); 1756 1757 DAG.setRoot(BrRange); 1758} 1759 1760/// visitBitTestCase - this function produces one "bit test" 1761void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1762 MachineBasicBlock* NextMBB, 1763 unsigned Reg, 1764 BitTestCase &B, 1765 MachineBasicBlock *SwitchBB) { 1766 EVT VT = BB.RegVT; 1767 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1768 Reg, VT); 1769 SDValue Cmp; 1770 unsigned PopCount = CountPopulation_64(B.Mask); 1771 if (PopCount == 1) { 1772 // Testing for a single bit; just compare the shift count with what it 1773 // would need to be to shift a 1 bit in that position. 1774 Cmp = DAG.getSetCC(getCurDebugLoc(), 1775 TLI.getSetCCResultType(VT), 1776 ShiftOp, 1777 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1778 ISD::SETEQ); 1779 } else if (PopCount == BB.Range) { 1780 // There is only one zero bit in the range, test for it directly. 1781 Cmp = DAG.getSetCC(getCurDebugLoc(), 1782 TLI.getSetCCResultType(VT), 1783 ShiftOp, 1784 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1785 ISD::SETNE); 1786 } else { 1787 // Make desired shift 1788 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1789 DAG.getConstant(1, VT), ShiftOp); 1790 1791 // Emit bit tests and jumps 1792 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1793 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1794 Cmp = DAG.getSetCC(getCurDebugLoc(), 1795 TLI.getSetCCResultType(VT), 1796 AndOp, DAG.getConstant(0, VT), 1797 ISD::SETNE); 1798 } 1799 1800 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1801 addSuccessorWithWeight(SwitchBB, NextMBB); 1802 1803 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1804 MVT::Other, getControlRoot(), 1805 Cmp, DAG.getBasicBlock(B.TargetBB)); 1806 1807 // Set NextBlock to be the MBB immediately after the current one, if any. 1808 // This is used to avoid emitting unnecessary branches to the next block. 1809 MachineBasicBlock *NextBlock = 0; 1810 MachineFunction::iterator BBI = SwitchBB; 1811 if (++BBI != FuncInfo.MF->end()) 1812 NextBlock = BBI; 1813 1814 if (NextMBB != NextBlock) 1815 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1816 DAG.getBasicBlock(NextMBB)); 1817 1818 DAG.setRoot(BrAnd); 1819} 1820 1821void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1822 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1823 1824 // Retrieve successors. 1825 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1826 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1827 1828 const Value *Callee(I.getCalledValue()); 1829 if (isa<InlineAsm>(Callee)) 1830 visitInlineAsm(&I); 1831 else 1832 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1833 1834 // If the value of the invoke is used outside of its defining block, make it 1835 // available as a virtual register. 1836 CopyToExportRegsIfNeeded(&I); 1837 1838 // Update successor info 1839 addSuccessorWithWeight(InvokeMBB, Return); 1840 addSuccessorWithWeight(InvokeMBB, LandingPad); 1841 1842 // Drop into normal successor. 1843 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1844 MVT::Other, getControlRoot(), 1845 DAG.getBasicBlock(Return))); 1846} 1847 1848void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1849 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1850} 1851 1852void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1853 assert(FuncInfo.MBB->isLandingPad() && 1854 "Call to landingpad not in landing pad!"); 1855 1856 MachineBasicBlock *MBB = FuncInfo.MBB; 1857 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1858 AddLandingPadInfo(LP, MMI, MBB); 1859 1860 // If there aren't registers to copy the values into (e.g., during SjLj 1861 // exceptions), then don't bother to create these DAG nodes. 1862 if (TLI.getExceptionPointerRegister() == 0 && 1863 TLI.getExceptionSelectorRegister() == 0) 1864 return; 1865 1866 SmallVector<EVT, 2> ValueVTs; 1867 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1868 1869 // Insert the EXCEPTIONADDR instruction. 1870 assert(FuncInfo.MBB->isLandingPad() && 1871 "Call to eh.exception not in landing pad!"); 1872 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1873 SDValue Ops[2]; 1874 Ops[0] = DAG.getRoot(); 1875 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1876 SDValue Chain = Op1.getValue(1); 1877 1878 // Insert the EHSELECTION instruction. 1879 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1880 Ops[0] = Op1; 1881 Ops[1] = Chain; 1882 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1883 Chain = Op2.getValue(1); 1884 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1885 1886 Ops[0] = Op1; 1887 Ops[1] = Op2; 1888 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1889 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1890 &Ops[0], 2); 1891 1892 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1893 setValue(&LP, RetPair.first); 1894 DAG.setRoot(RetPair.second); 1895} 1896 1897/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1898/// small case ranges). 1899bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1900 CaseRecVector& WorkList, 1901 const Value* SV, 1902 MachineBasicBlock *Default, 1903 MachineBasicBlock *SwitchBB) { 1904 Case& BackCase = *(CR.Range.second-1); 1905 1906 // Size is the number of Cases represented by this range. 1907 size_t Size = CR.Range.second - CR.Range.first; 1908 if (Size > 3) 1909 return false; 1910 1911 // Get the MachineFunction which holds the current MBB. This is used when 1912 // inserting any additional MBBs necessary to represent the switch. 1913 MachineFunction *CurMF = FuncInfo.MF; 1914 1915 // Figure out which block is immediately after the current one. 1916 MachineBasicBlock *NextBlock = 0; 1917 MachineFunction::iterator BBI = CR.CaseBB; 1918 1919 if (++BBI != FuncInfo.MF->end()) 1920 NextBlock = BBI; 1921 1922 // If any two of the cases has the same destination, and if one value 1923 // is the same as the other, but has one bit unset that the other has set, 1924 // use bit manipulation to do two compares at once. For example: 1925 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1926 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1927 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1928 if (Size == 2 && CR.CaseBB == SwitchBB) { 1929 Case &Small = *CR.Range.first; 1930 Case &Big = *(CR.Range.second-1); 1931 1932 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1933 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1934 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1935 1936 // Check that there is only one bit different. 1937 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1938 (SmallValue | BigValue) == BigValue) { 1939 // Isolate the common bit. 1940 APInt CommonBit = BigValue & ~SmallValue; 1941 assert((SmallValue | CommonBit) == BigValue && 1942 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1943 1944 SDValue CondLHS = getValue(SV); 1945 EVT VT = CondLHS.getValueType(); 1946 DebugLoc DL = getCurDebugLoc(); 1947 1948 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1949 DAG.getConstant(CommonBit, VT)); 1950 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1951 Or, DAG.getConstant(BigValue, VT), 1952 ISD::SETEQ); 1953 1954 // Update successor info. 1955 addSuccessorWithWeight(SwitchBB, Small.BB); 1956 addSuccessorWithWeight(SwitchBB, Default); 1957 1958 // Insert the true branch. 1959 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1960 getControlRoot(), Cond, 1961 DAG.getBasicBlock(Small.BB)); 1962 1963 // Insert the false branch. 1964 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1965 DAG.getBasicBlock(Default)); 1966 1967 DAG.setRoot(BrCond); 1968 return true; 1969 } 1970 } 1971 } 1972 1973 // Rearrange the case blocks so that the last one falls through if possible. 1974 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1975 // The last case block won't fall through into 'NextBlock' if we emit the 1976 // branches in this order. See if rearranging a case value would help. 1977 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1978 if (I->BB == NextBlock) { 1979 std::swap(*I, BackCase); 1980 break; 1981 } 1982 } 1983 } 1984 1985 // Create a CaseBlock record representing a conditional branch to 1986 // the Case's target mbb if the value being switched on SV is equal 1987 // to C. 1988 MachineBasicBlock *CurBlock = CR.CaseBB; 1989 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1990 MachineBasicBlock *FallThrough; 1991 if (I != E-1) { 1992 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1993 CurMF->insert(BBI, FallThrough); 1994 1995 // Put SV in a virtual register to make it available from the new blocks. 1996 ExportFromCurrentBlock(SV); 1997 } else { 1998 // If the last case doesn't match, go to the default block. 1999 FallThrough = Default; 2000 } 2001 2002 const Value *RHS, *LHS, *MHS; 2003 ISD::CondCode CC; 2004 if (I->High == I->Low) { 2005 // This is just small small case range :) containing exactly 1 case 2006 CC = ISD::SETEQ; 2007 LHS = SV; RHS = I->High; MHS = NULL; 2008 } else { 2009 CC = ISD::SETLE; 2010 LHS = I->Low; MHS = SV; RHS = I->High; 2011 } 2012 2013 uint32_t ExtraWeight = I->ExtraWeight; 2014 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 2015 /* me */ CurBlock, 2016 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2); 2017 2018 // If emitting the first comparison, just call visitSwitchCase to emit the 2019 // code into the current block. Otherwise, push the CaseBlock onto the 2020 // vector to be later processed by SDISel, and insert the node's MBB 2021 // before the next MBB. 2022 if (CurBlock == SwitchBB) 2023 visitSwitchCase(CB, SwitchBB); 2024 else 2025 SwitchCases.push_back(CB); 2026 2027 CurBlock = FallThrough; 2028 } 2029 2030 return true; 2031} 2032 2033static inline bool areJTsAllowed(const TargetLowering &TLI) { 2034 return !TLI.getTargetMachine().Options.DisableJumpTables && 2035 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2036 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2037} 2038 2039static APInt ComputeRange(const APInt &First, const APInt &Last) { 2040 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2041 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 2042 return (LastExt - FirstExt + 1ULL); 2043} 2044 2045/// handleJTSwitchCase - Emit jumptable for current switch case range 2046bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2047 CaseRecVector &WorkList, 2048 const Value *SV, 2049 MachineBasicBlock *Default, 2050 MachineBasicBlock *SwitchBB) { 2051 Case& FrontCase = *CR.Range.first; 2052 Case& BackCase = *(CR.Range.second-1); 2053 2054 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2055 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2056 2057 APInt TSize(First.getBitWidth(), 0); 2058 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2059 TSize += I->size(); 2060 2061 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2062 return false; 2063 2064 APInt Range = ComputeRange(First, Last); 2065 // The density is TSize / Range. Require at least 40%. 2066 // It should not be possible for IntTSize to saturate for sane code, but make 2067 // sure we handle Range saturation correctly. 2068 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2069 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2070 if (IntTSize * 10 < IntRange * 4) 2071 return false; 2072 2073 DEBUG(dbgs() << "Lowering jump table\n" 2074 << "First entry: " << First << ". Last entry: " << Last << '\n' 2075 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2076 2077 // Get the MachineFunction which holds the current MBB. This is used when 2078 // inserting any additional MBBs necessary to represent the switch. 2079 MachineFunction *CurMF = FuncInfo.MF; 2080 2081 // Figure out which block is immediately after the current one. 2082 MachineFunction::iterator BBI = CR.CaseBB; 2083 ++BBI; 2084 2085 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2086 2087 // Create a new basic block to hold the code for loading the address 2088 // of the jump table, and jumping to it. Update successor information; 2089 // we will either branch to the default case for the switch, or the jump 2090 // table. 2091 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2092 CurMF->insert(BBI, JumpTableBB); 2093 2094 addSuccessorWithWeight(CR.CaseBB, Default); 2095 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2096 2097 // Build a vector of destination BBs, corresponding to each target 2098 // of the jump table. If the value of the jump table slot corresponds to 2099 // a case statement, push the case's BB onto the vector, otherwise, push 2100 // the default BB. 2101 std::vector<MachineBasicBlock*> DestBBs; 2102 APInt TEI = First; 2103 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2104 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2105 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2106 2107 if (Low.sle(TEI) && TEI.sle(High)) { 2108 DestBBs.push_back(I->BB); 2109 if (TEI==High) 2110 ++I; 2111 } else { 2112 DestBBs.push_back(Default); 2113 } 2114 } 2115 2116 // Update successor info. Add one edge to each unique successor. 2117 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2118 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2119 E = DestBBs.end(); I != E; ++I) { 2120 if (!SuccsHandled[(*I)->getNumber()]) { 2121 SuccsHandled[(*I)->getNumber()] = true; 2122 addSuccessorWithWeight(JumpTableBB, *I); 2123 } 2124 } 2125 2126 // Create a jump table index for this jump table. 2127 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2128 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2129 ->createJumpTableIndex(DestBBs); 2130 2131 // Set the jump table information so that we can codegen it as a second 2132 // MachineBasicBlock 2133 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2134 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2135 if (CR.CaseBB == SwitchBB) 2136 visitJumpTableHeader(JT, JTH, SwitchBB); 2137 2138 JTCases.push_back(JumpTableBlock(JTH, JT)); 2139 return true; 2140} 2141 2142/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2143/// 2 subtrees. 2144bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2145 CaseRecVector& WorkList, 2146 const Value* SV, 2147 MachineBasicBlock *Default, 2148 MachineBasicBlock *SwitchBB) { 2149 // Get the MachineFunction which holds the current MBB. This is used when 2150 // inserting any additional MBBs necessary to represent the switch. 2151 MachineFunction *CurMF = FuncInfo.MF; 2152 2153 // Figure out which block is immediately after the current one. 2154 MachineFunction::iterator BBI = CR.CaseBB; 2155 ++BBI; 2156 2157 Case& FrontCase = *CR.Range.first; 2158 Case& BackCase = *(CR.Range.second-1); 2159 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2160 2161 // Size is the number of Cases represented by this range. 2162 unsigned Size = CR.Range.second - CR.Range.first; 2163 2164 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2165 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2166 double FMetric = 0; 2167 CaseItr Pivot = CR.Range.first + Size/2; 2168 2169 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2170 // (heuristically) allow us to emit JumpTable's later. 2171 APInt TSize(First.getBitWidth(), 0); 2172 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2173 I!=E; ++I) 2174 TSize += I->size(); 2175 2176 APInt LSize = FrontCase.size(); 2177 APInt RSize = TSize-LSize; 2178 DEBUG(dbgs() << "Selecting best pivot: \n" 2179 << "First: " << First << ", Last: " << Last <<'\n' 2180 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2181 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2182 J!=E; ++I, ++J) { 2183 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2184 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2185 APInt Range = ComputeRange(LEnd, RBegin); 2186 assert((Range - 2ULL).isNonNegative() && 2187 "Invalid case distance"); 2188 // Use volatile double here to avoid excess precision issues on some hosts, 2189 // e.g. that use 80-bit X87 registers. 2190 volatile double LDensity = 2191 (double)LSize.roundToDouble() / 2192 (LEnd - First + 1ULL).roundToDouble(); 2193 volatile double RDensity = 2194 (double)RSize.roundToDouble() / 2195 (Last - RBegin + 1ULL).roundToDouble(); 2196 double Metric = Range.logBase2()*(LDensity+RDensity); 2197 // Should always split in some non-trivial place 2198 DEBUG(dbgs() <<"=>Step\n" 2199 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2200 << "LDensity: " << LDensity 2201 << ", RDensity: " << RDensity << '\n' 2202 << "Metric: " << Metric << '\n'); 2203 if (FMetric < Metric) { 2204 Pivot = J; 2205 FMetric = Metric; 2206 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2207 } 2208 2209 LSize += J->size(); 2210 RSize -= J->size(); 2211 } 2212 if (areJTsAllowed(TLI)) { 2213 // If our case is dense we *really* should handle it earlier! 2214 assert((FMetric > 0) && "Should handle dense range earlier!"); 2215 } else { 2216 Pivot = CR.Range.first + Size/2; 2217 } 2218 2219 CaseRange LHSR(CR.Range.first, Pivot); 2220 CaseRange RHSR(Pivot, CR.Range.second); 2221 const Constant *C = Pivot->Low; 2222 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2223 2224 // We know that we branch to the LHS if the Value being switched on is 2225 // less than the Pivot value, C. We use this to optimize our binary 2226 // tree a bit, by recognizing that if SV is greater than or equal to the 2227 // LHS's Case Value, and that Case Value is exactly one less than the 2228 // Pivot's Value, then we can branch directly to the LHS's Target, 2229 // rather than creating a leaf node for it. 2230 if ((LHSR.second - LHSR.first) == 1 && 2231 LHSR.first->High == CR.GE && 2232 cast<ConstantInt>(C)->getValue() == 2233 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2234 TrueBB = LHSR.first->BB; 2235 } else { 2236 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2237 CurMF->insert(BBI, TrueBB); 2238 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2239 2240 // Put SV in a virtual register to make it available from the new blocks. 2241 ExportFromCurrentBlock(SV); 2242 } 2243 2244 // Similar to the optimization above, if the Value being switched on is 2245 // known to be less than the Constant CR.LT, and the current Case Value 2246 // is CR.LT - 1, then we can branch directly to the target block for 2247 // the current Case Value, rather than emitting a RHS leaf node for it. 2248 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2249 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2250 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2251 FalseBB = RHSR.first->BB; 2252 } else { 2253 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2254 CurMF->insert(BBI, FalseBB); 2255 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2256 2257 // Put SV in a virtual register to make it available from the new blocks. 2258 ExportFromCurrentBlock(SV); 2259 } 2260 2261 // Create a CaseBlock record representing a conditional branch to 2262 // the LHS node if the value being switched on SV is less than C. 2263 // Otherwise, branch to LHS. 2264 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2265 2266 if (CR.CaseBB == SwitchBB) 2267 visitSwitchCase(CB, SwitchBB); 2268 else 2269 SwitchCases.push_back(CB); 2270 2271 return true; 2272} 2273 2274/// handleBitTestsSwitchCase - if current case range has few destination and 2275/// range span less, than machine word bitwidth, encode case range into series 2276/// of masks and emit bit tests with these masks. 2277bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2278 CaseRecVector& WorkList, 2279 const Value* SV, 2280 MachineBasicBlock* Default, 2281 MachineBasicBlock *SwitchBB){ 2282 EVT PTy = TLI.getPointerTy(); 2283 unsigned IntPtrBits = PTy.getSizeInBits(); 2284 2285 Case& FrontCase = *CR.Range.first; 2286 Case& BackCase = *(CR.Range.second-1); 2287 2288 // Get the MachineFunction which holds the current MBB. This is used when 2289 // inserting any additional MBBs necessary to represent the switch. 2290 MachineFunction *CurMF = FuncInfo.MF; 2291 2292 // If target does not have legal shift left, do not emit bit tests at all. 2293 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2294 return false; 2295 2296 size_t numCmps = 0; 2297 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2298 I!=E; ++I) { 2299 // Single case counts one, case range - two. 2300 numCmps += (I->Low == I->High ? 1 : 2); 2301 } 2302 2303 // Count unique destinations 2304 SmallSet<MachineBasicBlock*, 4> Dests; 2305 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2306 Dests.insert(I->BB); 2307 if (Dests.size() > 3) 2308 // Don't bother the code below, if there are too much unique destinations 2309 return false; 2310 } 2311 DEBUG(dbgs() << "Total number of unique destinations: " 2312 << Dests.size() << '\n' 2313 << "Total number of comparisons: " << numCmps << '\n'); 2314 2315 // Compute span of values. 2316 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2317 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2318 APInt cmpRange = maxValue - minValue; 2319 2320 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2321 << "Low bound: " << minValue << '\n' 2322 << "High bound: " << maxValue << '\n'); 2323 2324 if (cmpRange.uge(IntPtrBits) || 2325 (!(Dests.size() == 1 && numCmps >= 3) && 2326 !(Dests.size() == 2 && numCmps >= 5) && 2327 !(Dests.size() >= 3 && numCmps >= 6))) 2328 return false; 2329 2330 DEBUG(dbgs() << "Emitting bit tests\n"); 2331 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2332 2333 // Optimize the case where all the case values fit in a 2334 // word without having to subtract minValue. In this case, 2335 // we can optimize away the subtraction. 2336 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2337 cmpRange = maxValue; 2338 } else { 2339 lowBound = minValue; 2340 } 2341 2342 CaseBitsVector CasesBits; 2343 unsigned i, count = 0; 2344 2345 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2346 MachineBasicBlock* Dest = I->BB; 2347 for (i = 0; i < count; ++i) 2348 if (Dest == CasesBits[i].BB) 2349 break; 2350 2351 if (i == count) { 2352 assert((count < 3) && "Too much destinations to test!"); 2353 CasesBits.push_back(CaseBits(0, Dest, 0)); 2354 count++; 2355 } 2356 2357 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2358 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2359 2360 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2361 uint64_t hi = (highValue - lowBound).getZExtValue(); 2362 2363 for (uint64_t j = lo; j <= hi; j++) { 2364 CasesBits[i].Mask |= 1ULL << j; 2365 CasesBits[i].Bits++; 2366 } 2367 2368 } 2369 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2370 2371 BitTestInfo BTC; 2372 2373 // Figure out which block is immediately after the current one. 2374 MachineFunction::iterator BBI = CR.CaseBB; 2375 ++BBI; 2376 2377 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2378 2379 DEBUG(dbgs() << "Cases:\n"); 2380 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2381 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2382 << ", Bits: " << CasesBits[i].Bits 2383 << ", BB: " << CasesBits[i].BB << '\n'); 2384 2385 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2386 CurMF->insert(BBI, CaseBB); 2387 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2388 CaseBB, 2389 CasesBits[i].BB)); 2390 2391 // Put SV in a virtual register to make it available from the new blocks. 2392 ExportFromCurrentBlock(SV); 2393 } 2394 2395 BitTestBlock BTB(lowBound, cmpRange, SV, 2396 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2397 CR.CaseBB, Default, BTC); 2398 2399 if (CR.CaseBB == SwitchBB) 2400 visitBitTestHeader(BTB, SwitchBB); 2401 2402 BitTestCases.push_back(BTB); 2403 2404 return true; 2405} 2406 2407/// Clusterify - Transform simple list of Cases into list of CaseRange's 2408size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2409 const SwitchInst& SI) { 2410 size_t numCmps = 0; 2411 2412 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2413 // Start with "simple" cases 2414 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end(); 2415 i != e; ++i) { 2416 const BasicBlock *SuccBB = i.getCaseSuccessor(); 2417 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2418 2419 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0; 2420 2421 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(), 2422 SMBB, ExtraWeight)); 2423 } 2424 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2425 2426 // Merge case into clusters 2427 if (Cases.size() >= 2) 2428 // Must recompute end() each iteration because it may be 2429 // invalidated by erase if we hold on to it 2430 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2431 J != Cases.end(); ) { 2432 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2433 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2434 MachineBasicBlock* nextBB = J->BB; 2435 MachineBasicBlock* currentBB = I->BB; 2436 2437 // If the two neighboring cases go to the same destination, merge them 2438 // into a single case. 2439 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2440 I->High = J->High; 2441 J = Cases.erase(J); 2442 2443 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) { 2444 uint32_t CurWeight = currentBB->getBasicBlock() ? 2445 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16; 2446 uint32_t NextWeight = nextBB->getBasicBlock() ? 2447 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16; 2448 2449 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(), 2450 CurWeight + NextWeight); 2451 } 2452 } else { 2453 I = J++; 2454 } 2455 } 2456 2457 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2458 if (I->Low != I->High) 2459 // A range counts double, since it requires two compares. 2460 ++numCmps; 2461 } 2462 2463 return numCmps; 2464} 2465 2466void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2467 MachineBasicBlock *Last) { 2468 // Update JTCases. 2469 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2470 if (JTCases[i].first.HeaderBB == First) 2471 JTCases[i].first.HeaderBB = Last; 2472 2473 // Update BitTestCases. 2474 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2475 if (BitTestCases[i].Parent == First) 2476 BitTestCases[i].Parent = Last; 2477} 2478 2479void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2480 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2481 2482 // Figure out which block is immediately after the current one. 2483 MachineBasicBlock *NextBlock = 0; 2484 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2485 2486 // If there is only the default destination, branch to it if it is not the 2487 // next basic block. Otherwise, just fall through. 2488 if (!SI.getNumCases()) { 2489 // Update machine-CFG edges. 2490 2491 // If this is not a fall-through branch, emit the branch. 2492 SwitchMBB->addSuccessor(Default); 2493 if (Default != NextBlock) 2494 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2495 MVT::Other, getControlRoot(), 2496 DAG.getBasicBlock(Default))); 2497 2498 return; 2499 } 2500 2501 // If there are any non-default case statements, create a vector of Cases 2502 // representing each one, and sort the vector so that we can efficiently 2503 // create a binary search tree from them. 2504 CaseVector Cases; 2505 size_t numCmps = Clusterify(Cases, SI); 2506 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2507 << ". Total compares: " << numCmps << '\n'); 2508 (void)numCmps; 2509 2510 // Get the Value to be switched on and default basic blocks, which will be 2511 // inserted into CaseBlock records, representing basic blocks in the binary 2512 // search tree. 2513 const Value *SV = SI.getCondition(); 2514 2515 // Push the initial CaseRec onto the worklist 2516 CaseRecVector WorkList; 2517 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2518 CaseRange(Cases.begin(),Cases.end()))); 2519 2520 while (!WorkList.empty()) { 2521 // Grab a record representing a case range to process off the worklist 2522 CaseRec CR = WorkList.back(); 2523 WorkList.pop_back(); 2524 2525 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2526 continue; 2527 2528 // If the range has few cases (two or less) emit a series of specific 2529 // tests. 2530 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2531 continue; 2532 2533 // If the switch has more than 5 blocks, and at least 40% dense, and the 2534 // target supports indirect branches, then emit a jump table rather than 2535 // lowering the switch to a binary tree of conditional branches. 2536 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2537 continue; 2538 2539 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2540 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2541 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2542 } 2543} 2544 2545void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2546 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2547 2548 // Update machine-CFG edges with unique successors. 2549 SmallVector<BasicBlock*, 32> succs; 2550 succs.reserve(I.getNumSuccessors()); 2551 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2552 succs.push_back(I.getSuccessor(i)); 2553 array_pod_sort(succs.begin(), succs.end()); 2554 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2555 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2556 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2557 addSuccessorWithWeight(IndirectBrMBB, Succ); 2558 } 2559 2560 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2561 MVT::Other, getControlRoot(), 2562 getValue(I.getAddress()))); 2563} 2564 2565void SelectionDAGBuilder::visitFSub(const User &I) { 2566 // -0.0 - X --> fneg 2567 Type *Ty = I.getType(); 2568 if (isa<Constant>(I.getOperand(0)) && 2569 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2570 SDValue Op2 = getValue(I.getOperand(1)); 2571 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2572 Op2.getValueType(), Op2)); 2573 return; 2574 } 2575 2576 visitBinary(I, ISD::FSUB); 2577} 2578 2579void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2580 SDValue Op1 = getValue(I.getOperand(0)); 2581 SDValue Op2 = getValue(I.getOperand(1)); 2582 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2583 Op1.getValueType(), Op1, Op2)); 2584} 2585 2586void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2587 SDValue Op1 = getValue(I.getOperand(0)); 2588 SDValue Op2 = getValue(I.getOperand(1)); 2589 2590 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2591 2592 // Coerce the shift amount to the right type if we can. 2593 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2594 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2595 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2596 DebugLoc DL = getCurDebugLoc(); 2597 2598 // If the operand is smaller than the shift count type, promote it. 2599 if (ShiftSize > Op2Size) 2600 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2601 2602 // If the operand is larger than the shift count type but the shift 2603 // count type has enough bits to represent any shift value, truncate 2604 // it now. This is a common case and it exposes the truncate to 2605 // optimization early. 2606 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2607 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2608 // Otherwise we'll need to temporarily settle for some other convenient 2609 // type. Type legalization will make adjustments once the shiftee is split. 2610 else 2611 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2612 } 2613 2614 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2615 Op1.getValueType(), Op1, Op2)); 2616} 2617 2618void SelectionDAGBuilder::visitSDiv(const User &I) { 2619 SDValue Op1 = getValue(I.getOperand(0)); 2620 SDValue Op2 = getValue(I.getOperand(1)); 2621 2622 // Turn exact SDivs into multiplications. 2623 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2624 // exact bit. 2625 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2626 !isa<ConstantSDNode>(Op1) && 2627 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2628 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2629 else 2630 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2631 Op1, Op2)); 2632} 2633 2634void SelectionDAGBuilder::visitICmp(const User &I) { 2635 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2636 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2637 predicate = IC->getPredicate(); 2638 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2639 predicate = ICmpInst::Predicate(IC->getPredicate()); 2640 SDValue Op1 = getValue(I.getOperand(0)); 2641 SDValue Op2 = getValue(I.getOperand(1)); 2642 ISD::CondCode Opcode = getICmpCondCode(predicate); 2643 2644 EVT DestVT = TLI.getValueType(I.getType()); 2645 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2646} 2647 2648void SelectionDAGBuilder::visitFCmp(const User &I) { 2649 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2650 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2651 predicate = FC->getPredicate(); 2652 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2653 predicate = FCmpInst::Predicate(FC->getPredicate()); 2654 SDValue Op1 = getValue(I.getOperand(0)); 2655 SDValue Op2 = getValue(I.getOperand(1)); 2656 ISD::CondCode Condition = getFCmpCondCode(predicate); 2657 if (TM.Options.NoNaNsFPMath) 2658 Condition = getFCmpCodeWithoutNaN(Condition); 2659 EVT DestVT = TLI.getValueType(I.getType()); 2660 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2661} 2662 2663void SelectionDAGBuilder::visitSelect(const User &I) { 2664 SmallVector<EVT, 4> ValueVTs; 2665 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2666 unsigned NumValues = ValueVTs.size(); 2667 if (NumValues == 0) return; 2668 2669 SmallVector<SDValue, 4> Values(NumValues); 2670 SDValue Cond = getValue(I.getOperand(0)); 2671 SDValue TrueVal = getValue(I.getOperand(1)); 2672 SDValue FalseVal = getValue(I.getOperand(2)); 2673 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2674 ISD::VSELECT : ISD::SELECT; 2675 2676 for (unsigned i = 0; i != NumValues; ++i) 2677 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2678 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2679 Cond, 2680 SDValue(TrueVal.getNode(), 2681 TrueVal.getResNo() + i), 2682 SDValue(FalseVal.getNode(), 2683 FalseVal.getResNo() + i)); 2684 2685 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2686 DAG.getVTList(&ValueVTs[0], NumValues), 2687 &Values[0], NumValues)); 2688} 2689 2690void SelectionDAGBuilder::visitTrunc(const User &I) { 2691 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2692 SDValue N = getValue(I.getOperand(0)); 2693 EVT DestVT = TLI.getValueType(I.getType()); 2694 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2695} 2696 2697void SelectionDAGBuilder::visitZExt(const User &I) { 2698 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2699 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2700 SDValue N = getValue(I.getOperand(0)); 2701 EVT DestVT = TLI.getValueType(I.getType()); 2702 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2703} 2704 2705void SelectionDAGBuilder::visitSExt(const User &I) { 2706 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2707 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2708 SDValue N = getValue(I.getOperand(0)); 2709 EVT DestVT = TLI.getValueType(I.getType()); 2710 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2711} 2712 2713void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2714 // FPTrunc is never a no-op cast, no need to check 2715 SDValue N = getValue(I.getOperand(0)); 2716 EVT DestVT = TLI.getValueType(I.getType()); 2717 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2718 DestVT, N, 2719 DAG.getTargetConstant(0, TLI.getPointerTy()))); 2720} 2721 2722void SelectionDAGBuilder::visitFPExt(const User &I){ 2723 // FPExt is never a no-op cast, no need to check 2724 SDValue N = getValue(I.getOperand(0)); 2725 EVT DestVT = TLI.getValueType(I.getType()); 2726 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2727} 2728 2729void SelectionDAGBuilder::visitFPToUI(const User &I) { 2730 // FPToUI is never a no-op cast, no need to check 2731 SDValue N = getValue(I.getOperand(0)); 2732 EVT DestVT = TLI.getValueType(I.getType()); 2733 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2734} 2735 2736void SelectionDAGBuilder::visitFPToSI(const User &I) { 2737 // FPToSI is never a no-op cast, no need to check 2738 SDValue N = getValue(I.getOperand(0)); 2739 EVT DestVT = TLI.getValueType(I.getType()); 2740 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2741} 2742 2743void SelectionDAGBuilder::visitUIToFP(const User &I) { 2744 // UIToFP is never a no-op cast, no need to check 2745 SDValue N = getValue(I.getOperand(0)); 2746 EVT DestVT = TLI.getValueType(I.getType()); 2747 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2748} 2749 2750void SelectionDAGBuilder::visitSIToFP(const User &I){ 2751 // SIToFP is never a no-op cast, no need to check 2752 SDValue N = getValue(I.getOperand(0)); 2753 EVT DestVT = TLI.getValueType(I.getType()); 2754 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2755} 2756 2757void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2758 // What to do depends on the size of the integer and the size of the pointer. 2759 // We can either truncate, zero extend, or no-op, accordingly. 2760 SDValue N = getValue(I.getOperand(0)); 2761 EVT DestVT = TLI.getValueType(I.getType()); 2762 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2763} 2764 2765void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2766 // What to do depends on the size of the integer and the size of the pointer. 2767 // We can either truncate, zero extend, or no-op, accordingly. 2768 SDValue N = getValue(I.getOperand(0)); 2769 EVT DestVT = TLI.getValueType(I.getType()); 2770 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2771} 2772 2773void SelectionDAGBuilder::visitBitCast(const User &I) { 2774 SDValue N = getValue(I.getOperand(0)); 2775 EVT DestVT = TLI.getValueType(I.getType()); 2776 2777 // BitCast assures us that source and destination are the same size so this is 2778 // either a BITCAST or a no-op. 2779 if (DestVT != N.getValueType()) 2780 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2781 DestVT, N)); // convert types. 2782 else 2783 setValue(&I, N); // noop cast. 2784} 2785 2786void SelectionDAGBuilder::visitInsertElement(const User &I) { 2787 SDValue InVec = getValue(I.getOperand(0)); 2788 SDValue InVal = getValue(I.getOperand(1)); 2789 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2790 TLI.getPointerTy(), 2791 getValue(I.getOperand(2))); 2792 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2793 TLI.getValueType(I.getType()), 2794 InVec, InVal, InIdx)); 2795} 2796 2797void SelectionDAGBuilder::visitExtractElement(const User &I) { 2798 SDValue InVec = getValue(I.getOperand(0)); 2799 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2800 TLI.getPointerTy(), 2801 getValue(I.getOperand(1))); 2802 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2803 TLI.getValueType(I.getType()), InVec, InIdx)); 2804} 2805 2806// Utility for visitShuffleVector - Return true if every element in Mask, 2807// begining // from position Pos and ending in Pos+Size, falls within the 2808// specified sequential range [L, L+Pos). or is undef. 2809static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2810 int Pos, int Size, int Low) { 2811 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2812 if (Mask[i] >= 0 && Mask[i] != Low) 2813 return false; 2814 return true; 2815} 2816 2817void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2818 SDValue Src1 = getValue(I.getOperand(0)); 2819 SDValue Src2 = getValue(I.getOperand(1)); 2820 2821 SmallVector<int, 8> Mask; 2822 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); 2823 unsigned MaskNumElts = Mask.size(); 2824 2825 EVT VT = TLI.getValueType(I.getType()); 2826 EVT SrcVT = Src1.getValueType(); 2827 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2828 2829 if (SrcNumElts == MaskNumElts) { 2830 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2831 &Mask[0])); 2832 return; 2833 } 2834 2835 // Normalize the shuffle vector since mask and vector length don't match. 2836 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2837 // Mask is longer than the source vectors and is a multiple of the source 2838 // vectors. We can use concatenate vector to make the mask and vectors 2839 // lengths match. 2840 if (SrcNumElts*2 == MaskNumElts) { 2841 // First check for Src1 in low and Src2 in high 2842 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 2843 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 2844 // The shuffle is concatenating two vectors together. 2845 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2846 VT, Src1, Src2)); 2847 return; 2848 } 2849 // Then check for Src2 in low and Src1 in high 2850 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 2851 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 2852 // The shuffle is concatenating two vectors together. 2853 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2854 VT, Src2, Src1)); 2855 return; 2856 } 2857 } 2858 2859 // Pad both vectors with undefs to make them the same length as the mask. 2860 unsigned NumConcat = MaskNumElts / SrcNumElts; 2861 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2862 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2863 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2864 2865 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2866 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2867 MOps1[0] = Src1; 2868 MOps2[0] = Src2; 2869 2870 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2871 getCurDebugLoc(), VT, 2872 &MOps1[0], NumConcat); 2873 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2874 getCurDebugLoc(), VT, 2875 &MOps2[0], NumConcat); 2876 2877 // Readjust mask for new input vector length. 2878 SmallVector<int, 8> MappedOps; 2879 for (unsigned i = 0; i != MaskNumElts; ++i) { 2880 int Idx = Mask[i]; 2881 if (Idx < (int)SrcNumElts) 2882 MappedOps.push_back(Idx); 2883 else 2884 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2885 } 2886 2887 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2888 &MappedOps[0])); 2889 return; 2890 } 2891 2892 if (SrcNumElts > MaskNumElts) { 2893 // Analyze the access pattern of the vector to see if we can extract 2894 // two subvectors and do the shuffle. The analysis is done by calculating 2895 // the range of elements the mask access on both vectors. 2896 int MinRange[2] = { static_cast<int>(SrcNumElts+1), 2897 static_cast<int>(SrcNumElts+1)}; 2898 int MaxRange[2] = {-1, -1}; 2899 2900 for (unsigned i = 0; i != MaskNumElts; ++i) { 2901 int Idx = Mask[i]; 2902 int Input = 0; 2903 if (Idx < 0) 2904 continue; 2905 2906 if (Idx >= (int)SrcNumElts) { 2907 Input = 1; 2908 Idx -= SrcNumElts; 2909 } 2910 if (Idx > MaxRange[Input]) 2911 MaxRange[Input] = Idx; 2912 if (Idx < MinRange[Input]) 2913 MinRange[Input] = Idx; 2914 } 2915 2916 // Check if the access is smaller than the vector size and can we find 2917 // a reasonable extract index. 2918 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2919 // Extract. 2920 int StartIdx[2]; // StartIdx to extract from 2921 for (int Input=0; Input < 2; ++Input) { 2922 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2923 RangeUse[Input] = 0; // Unused 2924 StartIdx[Input] = 0; 2925 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2926 // Fits within range but we should see if we can find a good 2927 // start index that is a multiple of the mask length. 2928 if (MaxRange[Input] < (int)MaskNumElts) { 2929 RangeUse[Input] = 1; // Extract from beginning of the vector 2930 StartIdx[Input] = 0; 2931 } else { 2932 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2933 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2934 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2935 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2936 } 2937 } 2938 } 2939 2940 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2941 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2942 return; 2943 } 2944 if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2945 // Extract appropriate subvector and generate a vector shuffle 2946 for (int Input=0; Input < 2; ++Input) { 2947 SDValue &Src = Input == 0 ? Src1 : Src2; 2948 if (RangeUse[Input] == 0) 2949 Src = DAG.getUNDEF(VT); 2950 else 2951 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2952 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2953 } 2954 2955 // Calculate new mask. 2956 SmallVector<int, 8> MappedOps; 2957 for (unsigned i = 0; i != MaskNumElts; ++i) { 2958 int Idx = Mask[i]; 2959 if (Idx < 0) 2960 MappedOps.push_back(Idx); 2961 else if (Idx < (int)SrcNumElts) 2962 MappedOps.push_back(Idx - StartIdx[0]); 2963 else 2964 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2965 } 2966 2967 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2968 &MappedOps[0])); 2969 return; 2970 } 2971 } 2972 2973 // We can't use either concat vectors or extract subvectors so fall back to 2974 // replacing the shuffle with extract and build vector. 2975 // to insert and build vector. 2976 EVT EltVT = VT.getVectorElementType(); 2977 EVT PtrVT = TLI.getPointerTy(); 2978 SmallVector<SDValue,8> Ops; 2979 for (unsigned i = 0; i != MaskNumElts; ++i) { 2980 if (Mask[i] < 0) { 2981 Ops.push_back(DAG.getUNDEF(EltVT)); 2982 } else { 2983 int Idx = Mask[i]; 2984 SDValue Res; 2985 2986 if (Idx < (int)SrcNumElts) 2987 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2988 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2989 else 2990 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2991 EltVT, Src2, 2992 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2993 2994 Ops.push_back(Res); 2995 } 2996 } 2997 2998 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2999 VT, &Ops[0], Ops.size())); 3000} 3001 3002void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 3003 const Value *Op0 = I.getOperand(0); 3004 const Value *Op1 = I.getOperand(1); 3005 Type *AggTy = I.getType(); 3006 Type *ValTy = Op1->getType(); 3007 bool IntoUndef = isa<UndefValue>(Op0); 3008 bool FromUndef = isa<UndefValue>(Op1); 3009 3010 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3011 3012 SmallVector<EVT, 4> AggValueVTs; 3013 ComputeValueVTs(TLI, AggTy, AggValueVTs); 3014 SmallVector<EVT, 4> ValValueVTs; 3015 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3016 3017 unsigned NumAggValues = AggValueVTs.size(); 3018 unsigned NumValValues = ValValueVTs.size(); 3019 SmallVector<SDValue, 4> Values(NumAggValues); 3020 3021 SDValue Agg = getValue(Op0); 3022 unsigned i = 0; 3023 // Copy the beginning value(s) from the original aggregate. 3024 for (; i != LinearIndex; ++i) 3025 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3026 SDValue(Agg.getNode(), Agg.getResNo() + i); 3027 // Copy values from the inserted value(s). 3028 if (NumValValues) { 3029 SDValue Val = getValue(Op1); 3030 for (; i != LinearIndex + NumValValues; ++i) 3031 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3032 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3033 } 3034 // Copy remaining value(s) from the original aggregate. 3035 for (; i != NumAggValues; ++i) 3036 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3037 SDValue(Agg.getNode(), Agg.getResNo() + i); 3038 3039 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3040 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3041 &Values[0], NumAggValues)); 3042} 3043 3044void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3045 const Value *Op0 = I.getOperand(0); 3046 Type *AggTy = Op0->getType(); 3047 Type *ValTy = I.getType(); 3048 bool OutOfUndef = isa<UndefValue>(Op0); 3049 3050 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3051 3052 SmallVector<EVT, 4> ValValueVTs; 3053 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3054 3055 unsigned NumValValues = ValValueVTs.size(); 3056 3057 // Ignore a extractvalue that produces an empty object 3058 if (!NumValValues) { 3059 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3060 return; 3061 } 3062 3063 SmallVector<SDValue, 4> Values(NumValValues); 3064 3065 SDValue Agg = getValue(Op0); 3066 // Copy out the selected value(s). 3067 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3068 Values[i - LinearIndex] = 3069 OutOfUndef ? 3070 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3071 SDValue(Agg.getNode(), Agg.getResNo() + i); 3072 3073 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3074 DAG.getVTList(&ValValueVTs[0], NumValValues), 3075 &Values[0], NumValValues)); 3076} 3077 3078void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3079 SDValue N = getValue(I.getOperand(0)); 3080 // Note that the pointer operand may be a vector of pointers. Take the scalar 3081 // element which holds a pointer. 3082 Type *Ty = I.getOperand(0)->getType()->getScalarType(); 3083 3084 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3085 OI != E; ++OI) { 3086 const Value *Idx = *OI; 3087 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3088 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3089 if (Field) { 3090 // N = N + Offset 3091 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3092 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3093 DAG.getIntPtrConstant(Offset)); 3094 } 3095 3096 Ty = StTy->getElementType(Field); 3097 } else { 3098 Ty = cast<SequentialType>(Ty)->getElementType(); 3099 3100 // If this is a constant subscript, handle it quickly. 3101 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3102 if (CI->isZero()) continue; 3103 uint64_t Offs = 3104 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3105 SDValue OffsVal; 3106 EVT PTy = TLI.getPointerTy(); 3107 unsigned PtrBits = PTy.getSizeInBits(); 3108 if (PtrBits < 64) 3109 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3110 TLI.getPointerTy(), 3111 DAG.getConstant(Offs, MVT::i64)); 3112 else 3113 OffsVal = DAG.getIntPtrConstant(Offs); 3114 3115 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3116 OffsVal); 3117 continue; 3118 } 3119 3120 // N = N + Idx * ElementSize; 3121 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3122 TD->getTypeAllocSize(Ty)); 3123 SDValue IdxN = getValue(Idx); 3124 3125 // If the index is smaller or larger than intptr_t, truncate or extend 3126 // it. 3127 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3128 3129 // If this is a multiply by a power of two, turn it into a shl 3130 // immediately. This is a very common case. 3131 if (ElementSize != 1) { 3132 if (ElementSize.isPowerOf2()) { 3133 unsigned Amt = ElementSize.logBase2(); 3134 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3135 N.getValueType(), IdxN, 3136 DAG.getConstant(Amt, IdxN.getValueType())); 3137 } else { 3138 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3139 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3140 N.getValueType(), IdxN, Scale); 3141 } 3142 } 3143 3144 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3145 N.getValueType(), N, IdxN); 3146 } 3147 } 3148 3149 setValue(&I, N); 3150} 3151 3152void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3153 // If this is a fixed sized alloca in the entry block of the function, 3154 // allocate it statically on the stack. 3155 if (FuncInfo.StaticAllocaMap.count(&I)) 3156 return; // getValue will auto-populate this. 3157 3158 Type *Ty = I.getAllocatedType(); 3159 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3160 unsigned Align = 3161 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3162 I.getAlignment()); 3163 3164 SDValue AllocSize = getValue(I.getArraySize()); 3165 3166 EVT IntPtr = TLI.getPointerTy(); 3167 if (AllocSize.getValueType() != IntPtr) 3168 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3169 3170 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3171 AllocSize, 3172 DAG.getConstant(TySize, IntPtr)); 3173 3174 // Handle alignment. If the requested alignment is less than or equal to 3175 // the stack alignment, ignore it. If the size is greater than or equal to 3176 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3177 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3178 if (Align <= StackAlign) 3179 Align = 0; 3180 3181 // Round the size of the allocation up to the stack alignment size 3182 // by add SA-1 to the size. 3183 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3184 AllocSize.getValueType(), AllocSize, 3185 DAG.getIntPtrConstant(StackAlign-1)); 3186 3187 // Mask out the low bits for alignment purposes. 3188 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3189 AllocSize.getValueType(), AllocSize, 3190 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3191 3192 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3193 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3194 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3195 VTs, Ops, 3); 3196 setValue(&I, DSA); 3197 DAG.setRoot(DSA.getValue(1)); 3198 3199 // Inform the Frame Information that we have just allocated a variable-sized 3200 // object. 3201 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3202} 3203 3204void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3205 if (I.isAtomic()) 3206 return visitAtomicLoad(I); 3207 3208 const Value *SV = I.getOperand(0); 3209 SDValue Ptr = getValue(SV); 3210 3211 Type *Ty = I.getType(); 3212 3213 bool isVolatile = I.isVolatile(); 3214 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3215 bool isInvariant = I.getMetadata("invariant.load") != 0; 3216 unsigned Alignment = I.getAlignment(); 3217 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3218 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 3219 3220 SmallVector<EVT, 4> ValueVTs; 3221 SmallVector<uint64_t, 4> Offsets; 3222 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3223 unsigned NumValues = ValueVTs.size(); 3224 if (NumValues == 0) 3225 return; 3226 3227 SDValue Root; 3228 bool ConstantMemory = false; 3229 if (I.isVolatile() || NumValues > MaxParallelChains) 3230 // Serialize volatile loads with other side effects. 3231 Root = getRoot(); 3232 else if (AA->pointsToConstantMemory( 3233 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3234 // Do not serialize (non-volatile) loads of constant memory with anything. 3235 Root = DAG.getEntryNode(); 3236 ConstantMemory = true; 3237 } else { 3238 // Do not serialize non-volatile loads against each other. 3239 Root = DAG.getRoot(); 3240 } 3241 3242 SmallVector<SDValue, 4> Values(NumValues); 3243 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3244 NumValues)); 3245 EVT PtrVT = Ptr.getValueType(); 3246 unsigned ChainI = 0; 3247 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3248 // Serializing loads here may result in excessive register pressure, and 3249 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3250 // could recover a bit by hoisting nodes upward in the chain by recognizing 3251 // they are side-effect free or do not alias. The optimizer should really 3252 // avoid this case by converting large object/array copies to llvm.memcpy 3253 // (MaxParallelChains should always remain as failsafe). 3254 if (ChainI == MaxParallelChains) { 3255 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3256 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3257 MVT::Other, &Chains[0], ChainI); 3258 Root = Chain; 3259 ChainI = 0; 3260 } 3261 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3262 PtrVT, Ptr, 3263 DAG.getConstant(Offsets[i], PtrVT)); 3264 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3265 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3266 isNonTemporal, isInvariant, Alignment, TBAAInfo, 3267 Ranges); 3268 3269 Values[i] = L; 3270 Chains[ChainI] = L.getValue(1); 3271 } 3272 3273 if (!ConstantMemory) { 3274 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3275 MVT::Other, &Chains[0], ChainI); 3276 if (isVolatile) 3277 DAG.setRoot(Chain); 3278 else 3279 PendingLoads.push_back(Chain); 3280 } 3281 3282 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3283 DAG.getVTList(&ValueVTs[0], NumValues), 3284 &Values[0], NumValues)); 3285} 3286 3287void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3288 if (I.isAtomic()) 3289 return visitAtomicStore(I); 3290 3291 const Value *SrcV = I.getOperand(0); 3292 const Value *PtrV = I.getOperand(1); 3293 3294 SmallVector<EVT, 4> ValueVTs; 3295 SmallVector<uint64_t, 4> Offsets; 3296 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3297 unsigned NumValues = ValueVTs.size(); 3298 if (NumValues == 0) 3299 return; 3300 3301 // Get the lowered operands. Note that we do this after 3302 // checking if NumResults is zero, because with zero results 3303 // the operands won't have values in the map. 3304 SDValue Src = getValue(SrcV); 3305 SDValue Ptr = getValue(PtrV); 3306 3307 SDValue Root = getRoot(); 3308 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3309 NumValues)); 3310 EVT PtrVT = Ptr.getValueType(); 3311 bool isVolatile = I.isVolatile(); 3312 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3313 unsigned Alignment = I.getAlignment(); 3314 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3315 3316 unsigned ChainI = 0; 3317 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3318 // See visitLoad comments. 3319 if (ChainI == MaxParallelChains) { 3320 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3321 MVT::Other, &Chains[0], ChainI); 3322 Root = Chain; 3323 ChainI = 0; 3324 } 3325 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3326 DAG.getConstant(Offsets[i], PtrVT)); 3327 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3328 SDValue(Src.getNode(), Src.getResNo() + i), 3329 Add, MachinePointerInfo(PtrV, Offsets[i]), 3330 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3331 Chains[ChainI] = St; 3332 } 3333 3334 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3335 MVT::Other, &Chains[0], ChainI); 3336 ++SDNodeOrder; 3337 AssignOrderingToNode(StoreNode.getNode()); 3338 DAG.setRoot(StoreNode); 3339} 3340 3341static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3342 SynchronizationScope Scope, 3343 bool Before, DebugLoc dl, 3344 SelectionDAG &DAG, 3345 const TargetLowering &TLI) { 3346 // Fence, if necessary 3347 if (Before) { 3348 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3349 Order = Release; 3350 else if (Order == Acquire || Order == Monotonic) 3351 return Chain; 3352 } else { 3353 if (Order == AcquireRelease) 3354 Order = Acquire; 3355 else if (Order == Release || Order == Monotonic) 3356 return Chain; 3357 } 3358 SDValue Ops[3]; 3359 Ops[0] = Chain; 3360 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3361 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3362 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3363} 3364 3365void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3366 DebugLoc dl = getCurDebugLoc(); 3367 AtomicOrdering Order = I.getOrdering(); 3368 SynchronizationScope Scope = I.getSynchScope(); 3369 3370 SDValue InChain = getRoot(); 3371 3372 if (TLI.getInsertFencesForAtomic()) 3373 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3374 DAG, TLI); 3375 3376 SDValue L = 3377 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3378 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3379 InChain, 3380 getValue(I.getPointerOperand()), 3381 getValue(I.getCompareOperand()), 3382 getValue(I.getNewValOperand()), 3383 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3384 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3385 Scope); 3386 3387 SDValue OutChain = L.getValue(1); 3388 3389 if (TLI.getInsertFencesForAtomic()) 3390 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3391 DAG, TLI); 3392 3393 setValue(&I, L); 3394 DAG.setRoot(OutChain); 3395} 3396 3397void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3398 DebugLoc dl = getCurDebugLoc(); 3399 ISD::NodeType NT; 3400 switch (I.getOperation()) { 3401 default: llvm_unreachable("Unknown atomicrmw operation"); 3402 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3403 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3404 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3405 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3406 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3407 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3408 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3409 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3410 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3411 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3412 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3413 } 3414 AtomicOrdering Order = I.getOrdering(); 3415 SynchronizationScope Scope = I.getSynchScope(); 3416 3417 SDValue InChain = getRoot(); 3418 3419 if (TLI.getInsertFencesForAtomic()) 3420 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3421 DAG, TLI); 3422 3423 SDValue L = 3424 DAG.getAtomic(NT, dl, 3425 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3426 InChain, 3427 getValue(I.getPointerOperand()), 3428 getValue(I.getValOperand()), 3429 I.getPointerOperand(), 0 /* Alignment */, 3430 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3431 Scope); 3432 3433 SDValue OutChain = L.getValue(1); 3434 3435 if (TLI.getInsertFencesForAtomic()) 3436 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3437 DAG, TLI); 3438 3439 setValue(&I, L); 3440 DAG.setRoot(OutChain); 3441} 3442 3443void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3444 DebugLoc dl = getCurDebugLoc(); 3445 SDValue Ops[3]; 3446 Ops[0] = getRoot(); 3447 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3448 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3449 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3450} 3451 3452void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3453 DebugLoc dl = getCurDebugLoc(); 3454 AtomicOrdering Order = I.getOrdering(); 3455 SynchronizationScope Scope = I.getSynchScope(); 3456 3457 SDValue InChain = getRoot(); 3458 3459 EVT VT = EVT::getEVT(I.getType()); 3460 3461 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3462 report_fatal_error("Cannot generate unaligned atomic load"); 3463 3464 SDValue L = 3465 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3466 getValue(I.getPointerOperand()), 3467 I.getPointerOperand(), I.getAlignment(), 3468 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3469 Scope); 3470 3471 SDValue OutChain = L.getValue(1); 3472 3473 if (TLI.getInsertFencesForAtomic()) 3474 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3475 DAG, TLI); 3476 3477 setValue(&I, L); 3478 DAG.setRoot(OutChain); 3479} 3480 3481void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3482 DebugLoc dl = getCurDebugLoc(); 3483 3484 AtomicOrdering Order = I.getOrdering(); 3485 SynchronizationScope Scope = I.getSynchScope(); 3486 3487 SDValue InChain = getRoot(); 3488 3489 EVT VT = EVT::getEVT(I.getValueOperand()->getType()); 3490 3491 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3492 report_fatal_error("Cannot generate unaligned atomic store"); 3493 3494 if (TLI.getInsertFencesForAtomic()) 3495 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3496 DAG, TLI); 3497 3498 SDValue OutChain = 3499 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3500 InChain, 3501 getValue(I.getPointerOperand()), 3502 getValue(I.getValueOperand()), 3503 I.getPointerOperand(), I.getAlignment(), 3504 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3505 Scope); 3506 3507 if (TLI.getInsertFencesForAtomic()) 3508 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3509 DAG, TLI); 3510 3511 DAG.setRoot(OutChain); 3512} 3513 3514/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3515/// node. 3516void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3517 unsigned Intrinsic) { 3518 bool HasChain = !I.doesNotAccessMemory(); 3519 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3520 3521 // Build the operand list. 3522 SmallVector<SDValue, 8> Ops; 3523 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3524 if (OnlyLoad) { 3525 // We don't need to serialize loads against other loads. 3526 Ops.push_back(DAG.getRoot()); 3527 } else { 3528 Ops.push_back(getRoot()); 3529 } 3530 } 3531 3532 // Info is set by getTgtMemInstrinsic 3533 TargetLowering::IntrinsicInfo Info; 3534 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3535 3536 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3537 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3538 Info.opc == ISD::INTRINSIC_W_CHAIN) 3539 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy())); 3540 3541 // Add all operands of the call to the operand list. 3542 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3543 SDValue Op = getValue(I.getArgOperand(i)); 3544 Ops.push_back(Op); 3545 } 3546 3547 SmallVector<EVT, 4> ValueVTs; 3548 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3549 3550 if (HasChain) 3551 ValueVTs.push_back(MVT::Other); 3552 3553 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3554 3555 // Create the node. 3556 SDValue Result; 3557 if (IsTgtIntrinsic) { 3558 // This is target intrinsic that touches memory 3559 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3560 VTs, &Ops[0], Ops.size(), 3561 Info.memVT, 3562 MachinePointerInfo(Info.ptrVal, Info.offset), 3563 Info.align, Info.vol, 3564 Info.readMem, Info.writeMem); 3565 } else if (!HasChain) { 3566 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3567 VTs, &Ops[0], Ops.size()); 3568 } else if (!I.getType()->isVoidTy()) { 3569 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3570 VTs, &Ops[0], Ops.size()); 3571 } else { 3572 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3573 VTs, &Ops[0], Ops.size()); 3574 } 3575 3576 if (HasChain) { 3577 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3578 if (OnlyLoad) 3579 PendingLoads.push_back(Chain); 3580 else 3581 DAG.setRoot(Chain); 3582 } 3583 3584 if (!I.getType()->isVoidTy()) { 3585 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3586 EVT VT = TLI.getValueType(PTy); 3587 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3588 } 3589 3590 setValue(&I, Result); 3591 } else { 3592 // Assign order to result here. If the intrinsic does not produce a result, 3593 // it won't be mapped to a SDNode and visit() will not assign it an order 3594 // number. 3595 ++SDNodeOrder; 3596 AssignOrderingToNode(Result.getNode()); 3597 } 3598} 3599 3600/// GetSignificand - Get the significand and build it into a floating-point 3601/// number with exponent of 1: 3602/// 3603/// Op = (Op & 0x007fffff) | 0x3f800000; 3604/// 3605/// where Op is the hexidecimal representation of floating point value. 3606static SDValue 3607GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3608 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3609 DAG.getConstant(0x007fffff, MVT::i32)); 3610 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3611 DAG.getConstant(0x3f800000, MVT::i32)); 3612 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3613} 3614 3615/// GetExponent - Get the exponent: 3616/// 3617/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3618/// 3619/// where Op is the hexidecimal representation of floating point value. 3620static SDValue 3621GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3622 DebugLoc dl) { 3623 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3624 DAG.getConstant(0x7f800000, MVT::i32)); 3625 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3626 DAG.getConstant(23, TLI.getPointerTy())); 3627 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3628 DAG.getConstant(127, MVT::i32)); 3629 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3630} 3631 3632/// getF32Constant - Get 32-bit floating point constant. 3633static SDValue 3634getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3635 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3636} 3637 3638// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3639const char * 3640SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3641 SDValue Op1 = getValue(I.getArgOperand(0)); 3642 SDValue Op2 = getValue(I.getArgOperand(1)); 3643 3644 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3645 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3646 return 0; 3647} 3648 3649/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3650/// limited-precision mode. 3651void 3652SelectionDAGBuilder::visitExp(const CallInst &I) { 3653 SDValue result; 3654 DebugLoc dl = getCurDebugLoc(); 3655 3656 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3657 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3658 SDValue Op = getValue(I.getArgOperand(0)); 3659 3660 // Put the exponent in the right bit position for later addition to the 3661 // final result: 3662 // 3663 // #define LOG2OFe 1.4426950f 3664 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3665 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3666 getF32Constant(DAG, 0x3fb8aa3b)); 3667 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3668 3669 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3670 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3671 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3672 3673 // IntegerPartOfX <<= 23; 3674 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3675 DAG.getConstant(23, TLI.getPointerTy())); 3676 3677 if (LimitFloatPrecision <= 6) { 3678 // For floating-point precision of 6: 3679 // 3680 // TwoToFractionalPartOfX = 3681 // 0.997535578f + 3682 // (0.735607626f + 0.252464424f * x) * x; 3683 // 3684 // error 0.0144103317, which is 6 bits 3685 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3686 getF32Constant(DAG, 0x3e814304)); 3687 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3688 getF32Constant(DAG, 0x3f3c50c8)); 3689 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3690 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3691 getF32Constant(DAG, 0x3f7f5e7e)); 3692 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3693 3694 // Add the exponent into the result in integer domain. 3695 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3696 TwoToFracPartOfX, IntegerPartOfX); 3697 3698 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3699 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3700 // For floating-point precision of 12: 3701 // 3702 // TwoToFractionalPartOfX = 3703 // 0.999892986f + 3704 // (0.696457318f + 3705 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3706 // 3707 // 0.000107046256 error, which is 13 to 14 bits 3708 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3709 getF32Constant(DAG, 0x3da235e3)); 3710 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3711 getF32Constant(DAG, 0x3e65b8f3)); 3712 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3713 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3714 getF32Constant(DAG, 0x3f324b07)); 3715 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3716 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3717 getF32Constant(DAG, 0x3f7ff8fd)); 3718 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3719 3720 // Add the exponent into the result in integer domain. 3721 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3722 TwoToFracPartOfX, IntegerPartOfX); 3723 3724 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3725 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3726 // For floating-point precision of 18: 3727 // 3728 // TwoToFractionalPartOfX = 3729 // 0.999999982f + 3730 // (0.693148872f + 3731 // (0.240227044f + 3732 // (0.554906021e-1f + 3733 // (0.961591928e-2f + 3734 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3735 // 3736 // error 2.47208000*10^(-7), which is better than 18 bits 3737 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3738 getF32Constant(DAG, 0x3924b03e)); 3739 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3740 getF32Constant(DAG, 0x3ab24b87)); 3741 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3742 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3743 getF32Constant(DAG, 0x3c1d8c17)); 3744 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3745 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3746 getF32Constant(DAG, 0x3d634a1d)); 3747 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3748 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3749 getF32Constant(DAG, 0x3e75fe14)); 3750 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3751 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3752 getF32Constant(DAG, 0x3f317234)); 3753 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3754 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3755 getF32Constant(DAG, 0x3f800000)); 3756 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3757 MVT::i32, t13); 3758 3759 // Add the exponent into the result in integer domain. 3760 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3761 TwoToFracPartOfX, IntegerPartOfX); 3762 3763 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3764 } 3765 } else { 3766 // No special expansion. 3767 result = DAG.getNode(ISD::FEXP, dl, 3768 getValue(I.getArgOperand(0)).getValueType(), 3769 getValue(I.getArgOperand(0))); 3770 } 3771 3772 setValue(&I, result); 3773} 3774 3775/// visitLog - Lower a log intrinsic. Handles the special sequences for 3776/// limited-precision mode. 3777void 3778SelectionDAGBuilder::visitLog(const CallInst &I) { 3779 SDValue result; 3780 DebugLoc dl = getCurDebugLoc(); 3781 3782 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3783 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3784 SDValue Op = getValue(I.getArgOperand(0)); 3785 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3786 3787 // Scale the exponent by log(2) [0.69314718f]. 3788 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3789 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3790 getF32Constant(DAG, 0x3f317218)); 3791 3792 // Get the significand and build it into a floating-point number with 3793 // exponent of 1. 3794 SDValue X = GetSignificand(DAG, Op1, dl); 3795 3796 if (LimitFloatPrecision <= 6) { 3797 // For floating-point precision of 6: 3798 // 3799 // LogofMantissa = 3800 // -1.1609546f + 3801 // (1.4034025f - 0.23903021f * x) * x; 3802 // 3803 // error 0.0034276066, which is better than 8 bits 3804 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3805 getF32Constant(DAG, 0xbe74c456)); 3806 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3807 getF32Constant(DAG, 0x3fb3a2b1)); 3808 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3809 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3810 getF32Constant(DAG, 0x3f949a29)); 3811 3812 result = DAG.getNode(ISD::FADD, dl, 3813 MVT::f32, LogOfExponent, LogOfMantissa); 3814 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3815 // For floating-point precision of 12: 3816 // 3817 // LogOfMantissa = 3818 // -1.7417939f + 3819 // (2.8212026f + 3820 // (-1.4699568f + 3821 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3822 // 3823 // error 0.000061011436, which is 14 bits 3824 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3825 getF32Constant(DAG, 0xbd67b6d6)); 3826 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3827 getF32Constant(DAG, 0x3ee4f4b8)); 3828 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3829 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3830 getF32Constant(DAG, 0x3fbc278b)); 3831 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3832 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3833 getF32Constant(DAG, 0x40348e95)); 3834 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3835 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3836 getF32Constant(DAG, 0x3fdef31a)); 3837 3838 result = DAG.getNode(ISD::FADD, dl, 3839 MVT::f32, LogOfExponent, LogOfMantissa); 3840 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3841 // For floating-point precision of 18: 3842 // 3843 // LogOfMantissa = 3844 // -2.1072184f + 3845 // (4.2372794f + 3846 // (-3.7029485f + 3847 // (2.2781945f + 3848 // (-0.87823314f + 3849 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3850 // 3851 // error 0.0000023660568, which is better than 18 bits 3852 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3853 getF32Constant(DAG, 0xbc91e5ac)); 3854 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3855 getF32Constant(DAG, 0x3e4350aa)); 3856 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3857 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3858 getF32Constant(DAG, 0x3f60d3e3)); 3859 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3860 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3861 getF32Constant(DAG, 0x4011cdf0)); 3862 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3863 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3864 getF32Constant(DAG, 0x406cfd1c)); 3865 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3866 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3867 getF32Constant(DAG, 0x408797cb)); 3868 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3869 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3870 getF32Constant(DAG, 0x4006dcab)); 3871 3872 result = DAG.getNode(ISD::FADD, dl, 3873 MVT::f32, LogOfExponent, LogOfMantissa); 3874 } 3875 } else { 3876 // No special expansion. 3877 result = DAG.getNode(ISD::FLOG, dl, 3878 getValue(I.getArgOperand(0)).getValueType(), 3879 getValue(I.getArgOperand(0))); 3880 } 3881 3882 setValue(&I, result); 3883} 3884 3885/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3886/// limited-precision mode. 3887void 3888SelectionDAGBuilder::visitLog2(const CallInst &I) { 3889 SDValue result; 3890 DebugLoc dl = getCurDebugLoc(); 3891 3892 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3893 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3894 SDValue Op = getValue(I.getArgOperand(0)); 3895 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3896 3897 // Get the exponent. 3898 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3899 3900 // Get the significand and build it into a floating-point number with 3901 // exponent of 1. 3902 SDValue X = GetSignificand(DAG, Op1, dl); 3903 3904 // Different possible minimax approximations of significand in 3905 // floating-point for various degrees of accuracy over [1,2]. 3906 if (LimitFloatPrecision <= 6) { 3907 // For floating-point precision of 6: 3908 // 3909 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3910 // 3911 // error 0.0049451742, which is more than 7 bits 3912 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3913 getF32Constant(DAG, 0xbeb08fe0)); 3914 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3915 getF32Constant(DAG, 0x40019463)); 3916 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3917 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3918 getF32Constant(DAG, 0x3fd6633d)); 3919 3920 result = DAG.getNode(ISD::FADD, dl, 3921 MVT::f32, LogOfExponent, Log2ofMantissa); 3922 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3923 // For floating-point precision of 12: 3924 // 3925 // Log2ofMantissa = 3926 // -2.51285454f + 3927 // (4.07009056f + 3928 // (-2.12067489f + 3929 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3930 // 3931 // error 0.0000876136000, which is better than 13 bits 3932 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3933 getF32Constant(DAG, 0xbda7262e)); 3934 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3935 getF32Constant(DAG, 0x3f25280b)); 3936 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3937 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3938 getF32Constant(DAG, 0x4007b923)); 3939 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3940 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3941 getF32Constant(DAG, 0x40823e2f)); 3942 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3943 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3944 getF32Constant(DAG, 0x4020d29c)); 3945 3946 result = DAG.getNode(ISD::FADD, dl, 3947 MVT::f32, LogOfExponent, Log2ofMantissa); 3948 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3949 // For floating-point precision of 18: 3950 // 3951 // Log2ofMantissa = 3952 // -3.0400495f + 3953 // (6.1129976f + 3954 // (-5.3420409f + 3955 // (3.2865683f + 3956 // (-1.2669343f + 3957 // (0.27515199f - 3958 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3959 // 3960 // error 0.0000018516, which is better than 18 bits 3961 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3962 getF32Constant(DAG, 0xbcd2769e)); 3963 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3964 getF32Constant(DAG, 0x3e8ce0b9)); 3965 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3966 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3967 getF32Constant(DAG, 0x3fa22ae7)); 3968 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3969 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3970 getF32Constant(DAG, 0x40525723)); 3971 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3972 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3973 getF32Constant(DAG, 0x40aaf200)); 3974 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3975 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3976 getF32Constant(DAG, 0x40c39dad)); 3977 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3978 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3979 getF32Constant(DAG, 0x4042902c)); 3980 3981 result = DAG.getNode(ISD::FADD, dl, 3982 MVT::f32, LogOfExponent, Log2ofMantissa); 3983 } 3984 } else { 3985 // No special expansion. 3986 result = DAG.getNode(ISD::FLOG2, dl, 3987 getValue(I.getArgOperand(0)).getValueType(), 3988 getValue(I.getArgOperand(0))); 3989 } 3990 3991 setValue(&I, result); 3992} 3993 3994/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3995/// limited-precision mode. 3996void 3997SelectionDAGBuilder::visitLog10(const CallInst &I) { 3998 SDValue result; 3999 DebugLoc dl = getCurDebugLoc(); 4000 4001 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 4002 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4003 SDValue Op = getValue(I.getArgOperand(0)); 4004 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 4005 4006 // Scale the exponent by log10(2) [0.30102999f]. 4007 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 4008 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 4009 getF32Constant(DAG, 0x3e9a209a)); 4010 4011 // Get the significand and build it into a floating-point number with 4012 // exponent of 1. 4013 SDValue X = GetSignificand(DAG, Op1, dl); 4014 4015 if (LimitFloatPrecision <= 6) { 4016 // For floating-point precision of 6: 4017 // 4018 // Log10ofMantissa = 4019 // -0.50419619f + 4020 // (0.60948995f - 0.10380950f * x) * x; 4021 // 4022 // error 0.0014886165, which is 6 bits 4023 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4024 getF32Constant(DAG, 0xbdd49a13)); 4025 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4026 getF32Constant(DAG, 0x3f1c0789)); 4027 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4028 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4029 getF32Constant(DAG, 0x3f011300)); 4030 4031 result = DAG.getNode(ISD::FADD, dl, 4032 MVT::f32, LogOfExponent, Log10ofMantissa); 4033 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4034 // For floating-point precision of 12: 4035 // 4036 // Log10ofMantissa = 4037 // -0.64831180f + 4038 // (0.91751397f + 4039 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4040 // 4041 // error 0.00019228036, which is better than 12 bits 4042 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4043 getF32Constant(DAG, 0x3d431f31)); 4044 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4045 getF32Constant(DAG, 0x3ea21fb2)); 4046 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4047 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4048 getF32Constant(DAG, 0x3f6ae232)); 4049 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4050 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4051 getF32Constant(DAG, 0x3f25f7c3)); 4052 4053 result = DAG.getNode(ISD::FADD, dl, 4054 MVT::f32, LogOfExponent, Log10ofMantissa); 4055 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4056 // For floating-point precision of 18: 4057 // 4058 // Log10ofMantissa = 4059 // -0.84299375f + 4060 // (1.5327582f + 4061 // (-1.0688956f + 4062 // (0.49102474f + 4063 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4064 // 4065 // error 0.0000037995730, which is better than 18 bits 4066 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4067 getF32Constant(DAG, 0x3c5d51ce)); 4068 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4069 getF32Constant(DAG, 0x3e00685a)); 4070 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4071 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4072 getF32Constant(DAG, 0x3efb6798)); 4073 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4074 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4075 getF32Constant(DAG, 0x3f88d192)); 4076 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4077 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4078 getF32Constant(DAG, 0x3fc4316c)); 4079 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4080 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4081 getF32Constant(DAG, 0x3f57ce70)); 4082 4083 result = DAG.getNode(ISD::FADD, dl, 4084 MVT::f32, LogOfExponent, Log10ofMantissa); 4085 } 4086 } else { 4087 // No special expansion. 4088 result = DAG.getNode(ISD::FLOG10, dl, 4089 getValue(I.getArgOperand(0)).getValueType(), 4090 getValue(I.getArgOperand(0))); 4091 } 4092 4093 setValue(&I, result); 4094} 4095 4096/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4097/// limited-precision mode. 4098void 4099SelectionDAGBuilder::visitExp2(const CallInst &I) { 4100 SDValue result; 4101 DebugLoc dl = getCurDebugLoc(); 4102 4103 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 4104 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4105 SDValue Op = getValue(I.getArgOperand(0)); 4106 4107 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4108 4109 // FractionalPartOfX = x - (float)IntegerPartOfX; 4110 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4111 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4112 4113 // IntegerPartOfX <<= 23; 4114 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4115 DAG.getConstant(23, TLI.getPointerTy())); 4116 4117 if (LimitFloatPrecision <= 6) { 4118 // For floating-point precision of 6: 4119 // 4120 // TwoToFractionalPartOfX = 4121 // 0.997535578f + 4122 // (0.735607626f + 0.252464424f * x) * x; 4123 // 4124 // error 0.0144103317, which is 6 bits 4125 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4126 getF32Constant(DAG, 0x3e814304)); 4127 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4128 getF32Constant(DAG, 0x3f3c50c8)); 4129 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4130 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4131 getF32Constant(DAG, 0x3f7f5e7e)); 4132 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4133 SDValue TwoToFractionalPartOfX = 4134 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4135 4136 result = DAG.getNode(ISD::BITCAST, dl, 4137 MVT::f32, TwoToFractionalPartOfX); 4138 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4139 // For floating-point precision of 12: 4140 // 4141 // TwoToFractionalPartOfX = 4142 // 0.999892986f + 4143 // (0.696457318f + 4144 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4145 // 4146 // error 0.000107046256, which is 13 to 14 bits 4147 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4148 getF32Constant(DAG, 0x3da235e3)); 4149 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4150 getF32Constant(DAG, 0x3e65b8f3)); 4151 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4152 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4153 getF32Constant(DAG, 0x3f324b07)); 4154 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4155 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4156 getF32Constant(DAG, 0x3f7ff8fd)); 4157 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4158 SDValue TwoToFractionalPartOfX = 4159 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4160 4161 result = DAG.getNode(ISD::BITCAST, dl, 4162 MVT::f32, TwoToFractionalPartOfX); 4163 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4164 // For floating-point precision of 18: 4165 // 4166 // TwoToFractionalPartOfX = 4167 // 0.999999982f + 4168 // (0.693148872f + 4169 // (0.240227044f + 4170 // (0.554906021e-1f + 4171 // (0.961591928e-2f + 4172 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4173 // error 2.47208000*10^(-7), which is better than 18 bits 4174 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4175 getF32Constant(DAG, 0x3924b03e)); 4176 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4177 getF32Constant(DAG, 0x3ab24b87)); 4178 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4179 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4180 getF32Constant(DAG, 0x3c1d8c17)); 4181 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4182 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4183 getF32Constant(DAG, 0x3d634a1d)); 4184 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4185 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4186 getF32Constant(DAG, 0x3e75fe14)); 4187 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4188 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4189 getF32Constant(DAG, 0x3f317234)); 4190 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4191 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4192 getF32Constant(DAG, 0x3f800000)); 4193 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4194 SDValue TwoToFractionalPartOfX = 4195 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4196 4197 result = DAG.getNode(ISD::BITCAST, dl, 4198 MVT::f32, TwoToFractionalPartOfX); 4199 } 4200 } else { 4201 // No special expansion. 4202 result = DAG.getNode(ISD::FEXP2, dl, 4203 getValue(I.getArgOperand(0)).getValueType(), 4204 getValue(I.getArgOperand(0))); 4205 } 4206 4207 setValue(&I, result); 4208} 4209 4210/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4211/// limited-precision mode with x == 10.0f. 4212void 4213SelectionDAGBuilder::visitPow(const CallInst &I) { 4214 SDValue result; 4215 const Value *Val = I.getArgOperand(0); 4216 DebugLoc dl = getCurDebugLoc(); 4217 bool IsExp10 = false; 4218 4219 if (getValue(Val).getValueType() == MVT::f32 && 4220 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4221 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4222 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4223 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4224 APFloat Ten(10.0f); 4225 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4226 } 4227 } 4228 } 4229 4230 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4231 SDValue Op = getValue(I.getArgOperand(1)); 4232 4233 // Put the exponent in the right bit position for later addition to the 4234 // final result: 4235 // 4236 // #define LOG2OF10 3.3219281f 4237 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4238 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4239 getF32Constant(DAG, 0x40549a78)); 4240 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4241 4242 // FractionalPartOfX = x - (float)IntegerPartOfX; 4243 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4244 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4245 4246 // IntegerPartOfX <<= 23; 4247 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4248 DAG.getConstant(23, TLI.getPointerTy())); 4249 4250 if (LimitFloatPrecision <= 6) { 4251 // For floating-point precision of 6: 4252 // 4253 // twoToFractionalPartOfX = 4254 // 0.997535578f + 4255 // (0.735607626f + 0.252464424f * x) * x; 4256 // 4257 // error 0.0144103317, which is 6 bits 4258 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4259 getF32Constant(DAG, 0x3e814304)); 4260 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4261 getF32Constant(DAG, 0x3f3c50c8)); 4262 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4263 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4264 getF32Constant(DAG, 0x3f7f5e7e)); 4265 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4266 SDValue TwoToFractionalPartOfX = 4267 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4268 4269 result = DAG.getNode(ISD::BITCAST, dl, 4270 MVT::f32, TwoToFractionalPartOfX); 4271 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4272 // For floating-point precision of 12: 4273 // 4274 // TwoToFractionalPartOfX = 4275 // 0.999892986f + 4276 // (0.696457318f + 4277 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4278 // 4279 // error 0.000107046256, which is 13 to 14 bits 4280 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4281 getF32Constant(DAG, 0x3da235e3)); 4282 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4283 getF32Constant(DAG, 0x3e65b8f3)); 4284 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4285 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4286 getF32Constant(DAG, 0x3f324b07)); 4287 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4288 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4289 getF32Constant(DAG, 0x3f7ff8fd)); 4290 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4291 SDValue TwoToFractionalPartOfX = 4292 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4293 4294 result = DAG.getNode(ISD::BITCAST, dl, 4295 MVT::f32, TwoToFractionalPartOfX); 4296 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4297 // For floating-point precision of 18: 4298 // 4299 // TwoToFractionalPartOfX = 4300 // 0.999999982f + 4301 // (0.693148872f + 4302 // (0.240227044f + 4303 // (0.554906021e-1f + 4304 // (0.961591928e-2f + 4305 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4306 // error 2.47208000*10^(-7), which is better than 18 bits 4307 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4308 getF32Constant(DAG, 0x3924b03e)); 4309 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4310 getF32Constant(DAG, 0x3ab24b87)); 4311 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4312 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4313 getF32Constant(DAG, 0x3c1d8c17)); 4314 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4315 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4316 getF32Constant(DAG, 0x3d634a1d)); 4317 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4318 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4319 getF32Constant(DAG, 0x3e75fe14)); 4320 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4321 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4322 getF32Constant(DAG, 0x3f317234)); 4323 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4324 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4325 getF32Constant(DAG, 0x3f800000)); 4326 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4327 SDValue TwoToFractionalPartOfX = 4328 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4329 4330 result = DAG.getNode(ISD::BITCAST, dl, 4331 MVT::f32, TwoToFractionalPartOfX); 4332 } 4333 } else { 4334 // No special expansion. 4335 result = DAG.getNode(ISD::FPOW, dl, 4336 getValue(I.getArgOperand(0)).getValueType(), 4337 getValue(I.getArgOperand(0)), 4338 getValue(I.getArgOperand(1))); 4339 } 4340 4341 setValue(&I, result); 4342} 4343 4344 4345/// ExpandPowI - Expand a llvm.powi intrinsic. 4346static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4347 SelectionDAG &DAG) { 4348 // If RHS is a constant, we can expand this out to a multiplication tree, 4349 // otherwise we end up lowering to a call to __powidf2 (for example). When 4350 // optimizing for size, we only want to do this if the expansion would produce 4351 // a small number of multiplies, otherwise we do the full expansion. 4352 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4353 // Get the exponent as a positive value. 4354 unsigned Val = RHSC->getSExtValue(); 4355 if ((int)Val < 0) Val = -Val; 4356 4357 // powi(x, 0) -> 1.0 4358 if (Val == 0) 4359 return DAG.getConstantFP(1.0, LHS.getValueType()); 4360 4361 const Function *F = DAG.getMachineFunction().getFunction(); 4362 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4363 // If optimizing for size, don't insert too many multiplies. This 4364 // inserts up to 5 multiplies. 4365 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4366 // We use the simple binary decomposition method to generate the multiply 4367 // sequence. There are more optimal ways to do this (for example, 4368 // powi(x,15) generates one more multiply than it should), but this has 4369 // the benefit of being both really simple and much better than a libcall. 4370 SDValue Res; // Logically starts equal to 1.0 4371 SDValue CurSquare = LHS; 4372 while (Val) { 4373 if (Val & 1) { 4374 if (Res.getNode()) 4375 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4376 else 4377 Res = CurSquare; // 1.0*CurSquare. 4378 } 4379 4380 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4381 CurSquare, CurSquare); 4382 Val >>= 1; 4383 } 4384 4385 // If the original was negative, invert the result, producing 1/(x*x*x). 4386 if (RHSC->getSExtValue() < 0) 4387 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4388 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4389 return Res; 4390 } 4391 } 4392 4393 // Otherwise, expand to a libcall. 4394 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4395} 4396 4397// getTruncatedArgReg - Find underlying register used for an truncated 4398// argument. 4399static unsigned getTruncatedArgReg(const SDValue &N) { 4400 if (N.getOpcode() != ISD::TRUNCATE) 4401 return 0; 4402 4403 const SDValue &Ext = N.getOperand(0); 4404 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4405 const SDValue &CFR = Ext.getOperand(0); 4406 if (CFR.getOpcode() == ISD::CopyFromReg) 4407 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4408 else 4409 if (CFR.getOpcode() == ISD::TRUNCATE) 4410 return getTruncatedArgReg(CFR); 4411 } 4412 return 0; 4413} 4414 4415/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4416/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4417/// At the end of instruction selection, they will be inserted to the entry BB. 4418bool 4419SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4420 int64_t Offset, 4421 const SDValue &N) { 4422 const Argument *Arg = dyn_cast<Argument>(V); 4423 if (!Arg) 4424 return false; 4425 4426 MachineFunction &MF = DAG.getMachineFunction(); 4427 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4428 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4429 4430 // Ignore inlined function arguments here. 4431 DIVariable DV(Variable); 4432 if (DV.isInlinedFnArgument(MF.getFunction())) 4433 return false; 4434 4435 unsigned Reg = 0; 4436 // Some arguments' frame index is recorded during argument lowering. 4437 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4438 if (Offset) 4439 Reg = TRI->getFrameRegister(MF); 4440 4441 if (!Reg && N.getNode()) { 4442 if (N.getOpcode() == ISD::CopyFromReg) 4443 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4444 else 4445 Reg = getTruncatedArgReg(N); 4446 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4447 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4448 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4449 if (PR) 4450 Reg = PR; 4451 } 4452 } 4453 4454 if (!Reg) { 4455 // Check if ValueMap has reg number. 4456 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4457 if (VMI != FuncInfo.ValueMap.end()) 4458 Reg = VMI->second; 4459 } 4460 4461 if (!Reg && N.getNode()) { 4462 // Check if frame index is available. 4463 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4464 if (FrameIndexSDNode *FINode = 4465 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4466 Reg = TRI->getFrameRegister(MF); 4467 Offset = FINode->getIndex(); 4468 } 4469 } 4470 4471 if (!Reg) 4472 return false; 4473 4474 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4475 TII->get(TargetOpcode::DBG_VALUE)) 4476 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4477 FuncInfo.ArgDbgValues.push_back(&*MIB); 4478 return true; 4479} 4480 4481// VisualStudio defines setjmp as _setjmp 4482#if defined(_MSC_VER) && defined(setjmp) && \ 4483 !defined(setjmp_undefined_for_msvc) 4484# pragma push_macro("setjmp") 4485# undef setjmp 4486# define setjmp_undefined_for_msvc 4487#endif 4488 4489/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4490/// we want to emit this as a call to a named external function, return the name 4491/// otherwise lower it and return null. 4492const char * 4493SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4494 DebugLoc dl = getCurDebugLoc(); 4495 SDValue Res; 4496 4497 switch (Intrinsic) { 4498 default: 4499 // By default, turn this into a target intrinsic node. 4500 visitTargetIntrinsic(I, Intrinsic); 4501 return 0; 4502 case Intrinsic::vastart: visitVAStart(I); return 0; 4503 case Intrinsic::vaend: visitVAEnd(I); return 0; 4504 case Intrinsic::vacopy: visitVACopy(I); return 0; 4505 case Intrinsic::returnaddress: 4506 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4507 getValue(I.getArgOperand(0)))); 4508 return 0; 4509 case Intrinsic::frameaddress: 4510 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4511 getValue(I.getArgOperand(0)))); 4512 return 0; 4513 case Intrinsic::setjmp: 4514 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()]; 4515 case Intrinsic::longjmp: 4516 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()]; 4517 case Intrinsic::memcpy: { 4518 // Assert for address < 256 since we support only user defined address 4519 // spaces. 4520 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4521 < 256 && 4522 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4523 < 256 && 4524 "Unknown address space"); 4525 SDValue Op1 = getValue(I.getArgOperand(0)); 4526 SDValue Op2 = getValue(I.getArgOperand(1)); 4527 SDValue Op3 = getValue(I.getArgOperand(2)); 4528 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4529 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4530 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4531 MachinePointerInfo(I.getArgOperand(0)), 4532 MachinePointerInfo(I.getArgOperand(1)))); 4533 return 0; 4534 } 4535 case Intrinsic::memset: { 4536 // Assert for address < 256 since we support only user defined address 4537 // spaces. 4538 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4539 < 256 && 4540 "Unknown address space"); 4541 SDValue Op1 = getValue(I.getArgOperand(0)); 4542 SDValue Op2 = getValue(I.getArgOperand(1)); 4543 SDValue Op3 = getValue(I.getArgOperand(2)); 4544 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4545 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4546 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4547 MachinePointerInfo(I.getArgOperand(0)))); 4548 return 0; 4549 } 4550 case Intrinsic::memmove: { 4551 // Assert for address < 256 since we support only user defined address 4552 // spaces. 4553 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4554 < 256 && 4555 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4556 < 256 && 4557 "Unknown address space"); 4558 SDValue Op1 = getValue(I.getArgOperand(0)); 4559 SDValue Op2 = getValue(I.getArgOperand(1)); 4560 SDValue Op3 = getValue(I.getArgOperand(2)); 4561 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4562 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4563 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4564 MachinePointerInfo(I.getArgOperand(0)), 4565 MachinePointerInfo(I.getArgOperand(1)))); 4566 return 0; 4567 } 4568 case Intrinsic::dbg_declare: { 4569 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4570 MDNode *Variable = DI.getVariable(); 4571 const Value *Address = DI.getAddress(); 4572 if (!Address || !DIVariable(Variable).Verify()) { 4573 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4574 return 0; 4575 } 4576 4577 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4578 // but do not always have a corresponding SDNode built. The SDNodeOrder 4579 // absolute, but not relative, values are different depending on whether 4580 // debug info exists. 4581 ++SDNodeOrder; 4582 4583 // Check if address has undef value. 4584 if (isa<UndefValue>(Address) || 4585 (Address->use_empty() && !isa<Argument>(Address))) { 4586 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4587 return 0; 4588 } 4589 4590 SDValue &N = NodeMap[Address]; 4591 if (!N.getNode() && isa<Argument>(Address)) 4592 // Check unused arguments map. 4593 N = UnusedArgNodeMap[Address]; 4594 SDDbgValue *SDV; 4595 if (N.getNode()) { 4596 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4597 Address = BCI->getOperand(0); 4598 // Parameters are handled specially. 4599 bool isParameter = 4600 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable || 4601 isa<Argument>(Address)); 4602 4603 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4604 4605 if (isParameter && !AI) { 4606 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4607 if (FINode) 4608 // Byval parameter. We have a frame index at this point. 4609 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4610 0, dl, SDNodeOrder); 4611 else { 4612 // Address is an argument, so try to emit its dbg value using 4613 // virtual register info from the FuncInfo.ValueMap. 4614 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4615 return 0; 4616 } 4617 } else if (AI) 4618 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4619 0, dl, SDNodeOrder); 4620 else { 4621 // Can't do anything with other non-AI cases yet. 4622 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4623 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t"); 4624 DEBUG(Address->dump()); 4625 return 0; 4626 } 4627 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4628 } else { 4629 // If Address is an argument then try to emit its dbg value using 4630 // virtual register info from the FuncInfo.ValueMap. 4631 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4632 // If variable is pinned by a alloca in dominating bb then 4633 // use StaticAllocaMap. 4634 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4635 if (AI->getParent() != DI.getParent()) { 4636 DenseMap<const AllocaInst*, int>::iterator SI = 4637 FuncInfo.StaticAllocaMap.find(AI); 4638 if (SI != FuncInfo.StaticAllocaMap.end()) { 4639 SDV = DAG.getDbgValue(Variable, SI->second, 4640 0, dl, SDNodeOrder); 4641 DAG.AddDbgValue(SDV, 0, false); 4642 return 0; 4643 } 4644 } 4645 } 4646 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4647 } 4648 } 4649 return 0; 4650 } 4651 case Intrinsic::dbg_value: { 4652 const DbgValueInst &DI = cast<DbgValueInst>(I); 4653 if (!DIVariable(DI.getVariable()).Verify()) 4654 return 0; 4655 4656 MDNode *Variable = DI.getVariable(); 4657 uint64_t Offset = DI.getOffset(); 4658 const Value *V = DI.getValue(); 4659 if (!V) 4660 return 0; 4661 4662 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4663 // but do not always have a corresponding SDNode built. The SDNodeOrder 4664 // absolute, but not relative, values are different depending on whether 4665 // debug info exists. 4666 ++SDNodeOrder; 4667 SDDbgValue *SDV; 4668 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4669 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4670 DAG.AddDbgValue(SDV, 0, false); 4671 } else { 4672 // Do not use getValue() in here; we don't want to generate code at 4673 // this point if it hasn't been done yet. 4674 SDValue N = NodeMap[V]; 4675 if (!N.getNode() && isa<Argument>(V)) 4676 // Check unused arguments map. 4677 N = UnusedArgNodeMap[V]; 4678 if (N.getNode()) { 4679 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4680 SDV = DAG.getDbgValue(Variable, N.getNode(), 4681 N.getResNo(), Offset, dl, SDNodeOrder); 4682 DAG.AddDbgValue(SDV, N.getNode(), false); 4683 } 4684 } else if (!V->use_empty() ) { 4685 // Do not call getValue(V) yet, as we don't want to generate code. 4686 // Remember it for later. 4687 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4688 DanglingDebugInfoMap[V] = DDI; 4689 } else { 4690 // We may expand this to cover more cases. One case where we have no 4691 // data available is an unreferenced parameter. 4692 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4693 } 4694 } 4695 4696 // Build a debug info table entry. 4697 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4698 V = BCI->getOperand(0); 4699 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4700 // Don't handle byval struct arguments or VLAs, for example. 4701 if (!AI) { 4702 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); 4703 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); 4704 return 0; 4705 } 4706 DenseMap<const AllocaInst*, int>::iterator SI = 4707 FuncInfo.StaticAllocaMap.find(AI); 4708 if (SI == FuncInfo.StaticAllocaMap.end()) 4709 return 0; // VLAs. 4710 int FI = SI->second; 4711 4712 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4713 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4714 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4715 return 0; 4716 } 4717 4718 case Intrinsic::eh_typeid_for: { 4719 // Find the type id for the given typeinfo. 4720 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4721 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4722 Res = DAG.getConstant(TypeID, MVT::i32); 4723 setValue(&I, Res); 4724 return 0; 4725 } 4726 4727 case Intrinsic::eh_return_i32: 4728 case Intrinsic::eh_return_i64: 4729 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4730 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4731 MVT::Other, 4732 getControlRoot(), 4733 getValue(I.getArgOperand(0)), 4734 getValue(I.getArgOperand(1)))); 4735 return 0; 4736 case Intrinsic::eh_unwind_init: 4737 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4738 return 0; 4739 case Intrinsic::eh_dwarf_cfa: { 4740 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4741 TLI.getPointerTy()); 4742 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4743 TLI.getPointerTy(), 4744 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4745 TLI.getPointerTy()), 4746 CfaArg); 4747 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4748 TLI.getPointerTy(), 4749 DAG.getConstant(0, TLI.getPointerTy())); 4750 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4751 FA, Offset)); 4752 return 0; 4753 } 4754 case Intrinsic::eh_sjlj_callsite: { 4755 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4756 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4757 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4758 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4759 4760 MMI.setCurrentCallSite(CI->getZExtValue()); 4761 return 0; 4762 } 4763 case Intrinsic::eh_sjlj_functioncontext: { 4764 // Get and store the index of the function context. 4765 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4766 AllocaInst *FnCtx = 4767 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4768 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4769 MFI->setFunctionContextIndex(FI); 4770 return 0; 4771 } 4772 case Intrinsic::eh_sjlj_setjmp: { 4773 SDValue Ops[2]; 4774 Ops[0] = getRoot(); 4775 Ops[1] = getValue(I.getArgOperand(0)); 4776 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, 4777 DAG.getVTList(MVT::i32, MVT::Other), 4778 Ops, 2); 4779 setValue(&I, Op.getValue(0)); 4780 DAG.setRoot(Op.getValue(1)); 4781 return 0; 4782 } 4783 case Intrinsic::eh_sjlj_longjmp: { 4784 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4785 getRoot(), getValue(I.getArgOperand(0)))); 4786 return 0; 4787 } 4788 4789 case Intrinsic::x86_mmx_pslli_w: 4790 case Intrinsic::x86_mmx_pslli_d: 4791 case Intrinsic::x86_mmx_pslli_q: 4792 case Intrinsic::x86_mmx_psrli_w: 4793 case Intrinsic::x86_mmx_psrli_d: 4794 case Intrinsic::x86_mmx_psrli_q: 4795 case Intrinsic::x86_mmx_psrai_w: 4796 case Intrinsic::x86_mmx_psrai_d: { 4797 SDValue ShAmt = getValue(I.getArgOperand(1)); 4798 if (isa<ConstantSDNode>(ShAmt)) { 4799 visitTargetIntrinsic(I, Intrinsic); 4800 return 0; 4801 } 4802 unsigned NewIntrinsic = 0; 4803 EVT ShAmtVT = MVT::v2i32; 4804 switch (Intrinsic) { 4805 case Intrinsic::x86_mmx_pslli_w: 4806 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4807 break; 4808 case Intrinsic::x86_mmx_pslli_d: 4809 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4810 break; 4811 case Intrinsic::x86_mmx_pslli_q: 4812 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4813 break; 4814 case Intrinsic::x86_mmx_psrli_w: 4815 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4816 break; 4817 case Intrinsic::x86_mmx_psrli_d: 4818 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4819 break; 4820 case Intrinsic::x86_mmx_psrli_q: 4821 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4822 break; 4823 case Intrinsic::x86_mmx_psrai_w: 4824 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4825 break; 4826 case Intrinsic::x86_mmx_psrai_d: 4827 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4828 break; 4829 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4830 } 4831 4832 // The vector shift intrinsics with scalars uses 32b shift amounts but 4833 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4834 // to be zero. 4835 // We must do this early because v2i32 is not a legal type. 4836 DebugLoc dl = getCurDebugLoc(); 4837 SDValue ShOps[2]; 4838 ShOps[0] = ShAmt; 4839 ShOps[1] = DAG.getConstant(0, MVT::i32); 4840 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4841 EVT DestVT = TLI.getValueType(I.getType()); 4842 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4843 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4844 DAG.getConstant(NewIntrinsic, MVT::i32), 4845 getValue(I.getArgOperand(0)), ShAmt); 4846 setValue(&I, Res); 4847 return 0; 4848 } 4849 case Intrinsic::x86_avx_vinsertf128_pd_256: 4850 case Intrinsic::x86_avx_vinsertf128_ps_256: 4851 case Intrinsic::x86_avx_vinsertf128_si_256: 4852 case Intrinsic::x86_avx2_vinserti128: { 4853 DebugLoc dl = getCurDebugLoc(); 4854 EVT DestVT = TLI.getValueType(I.getType()); 4855 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType()); 4856 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) * 4857 ElVT.getVectorNumElements(); 4858 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT, 4859 getValue(I.getArgOperand(0)), 4860 getValue(I.getArgOperand(1)), 4861 DAG.getConstant(Idx, MVT::i32)); 4862 setValue(&I, Res); 4863 return 0; 4864 } 4865 case Intrinsic::convertff: 4866 case Intrinsic::convertfsi: 4867 case Intrinsic::convertfui: 4868 case Intrinsic::convertsif: 4869 case Intrinsic::convertuif: 4870 case Intrinsic::convertss: 4871 case Intrinsic::convertsu: 4872 case Intrinsic::convertus: 4873 case Intrinsic::convertuu: { 4874 ISD::CvtCode Code = ISD::CVT_INVALID; 4875 switch (Intrinsic) { 4876 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4877 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4878 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4879 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4880 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4881 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4882 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4883 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4884 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4885 } 4886 EVT DestVT = TLI.getValueType(I.getType()); 4887 const Value *Op1 = I.getArgOperand(0); 4888 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4889 DAG.getValueType(DestVT), 4890 DAG.getValueType(getValue(Op1).getValueType()), 4891 getValue(I.getArgOperand(1)), 4892 getValue(I.getArgOperand(2)), 4893 Code); 4894 setValue(&I, Res); 4895 return 0; 4896 } 4897 case Intrinsic::sqrt: 4898 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4899 getValue(I.getArgOperand(0)).getValueType(), 4900 getValue(I.getArgOperand(0)))); 4901 return 0; 4902 case Intrinsic::powi: 4903 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4904 getValue(I.getArgOperand(1)), DAG)); 4905 return 0; 4906 case Intrinsic::sin: 4907 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4908 getValue(I.getArgOperand(0)).getValueType(), 4909 getValue(I.getArgOperand(0)))); 4910 return 0; 4911 case Intrinsic::cos: 4912 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4913 getValue(I.getArgOperand(0)).getValueType(), 4914 getValue(I.getArgOperand(0)))); 4915 return 0; 4916 case Intrinsic::log: 4917 visitLog(I); 4918 return 0; 4919 case Intrinsic::log2: 4920 visitLog2(I); 4921 return 0; 4922 case Intrinsic::log10: 4923 visitLog10(I); 4924 return 0; 4925 case Intrinsic::exp: 4926 visitExp(I); 4927 return 0; 4928 case Intrinsic::exp2: 4929 visitExp2(I); 4930 return 0; 4931 case Intrinsic::pow: 4932 visitPow(I); 4933 return 0; 4934 case Intrinsic::fma: 4935 setValue(&I, DAG.getNode(ISD::FMA, dl, 4936 getValue(I.getArgOperand(0)).getValueType(), 4937 getValue(I.getArgOperand(0)), 4938 getValue(I.getArgOperand(1)), 4939 getValue(I.getArgOperand(2)))); 4940 return 0; 4941 case Intrinsic::convert_to_fp16: 4942 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4943 MVT::i16, getValue(I.getArgOperand(0)))); 4944 return 0; 4945 case Intrinsic::convert_from_fp16: 4946 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4947 MVT::f32, getValue(I.getArgOperand(0)))); 4948 return 0; 4949 case Intrinsic::pcmarker: { 4950 SDValue Tmp = getValue(I.getArgOperand(0)); 4951 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4952 return 0; 4953 } 4954 case Intrinsic::readcyclecounter: { 4955 SDValue Op = getRoot(); 4956 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4957 DAG.getVTList(MVT::i64, MVT::Other), 4958 &Op, 1); 4959 setValue(&I, Res); 4960 DAG.setRoot(Res.getValue(1)); 4961 return 0; 4962 } 4963 case Intrinsic::bswap: 4964 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4965 getValue(I.getArgOperand(0)).getValueType(), 4966 getValue(I.getArgOperand(0)))); 4967 return 0; 4968 case Intrinsic::cttz: { 4969 SDValue Arg = getValue(I.getArgOperand(0)); 4970 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4971 EVT Ty = Arg.getValueType(); 4972 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 4973 dl, Ty, Arg)); 4974 return 0; 4975 } 4976 case Intrinsic::ctlz: { 4977 SDValue Arg = getValue(I.getArgOperand(0)); 4978 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4979 EVT Ty = Arg.getValueType(); 4980 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 4981 dl, Ty, Arg)); 4982 return 0; 4983 } 4984 case Intrinsic::ctpop: { 4985 SDValue Arg = getValue(I.getArgOperand(0)); 4986 EVT Ty = Arg.getValueType(); 4987 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4988 return 0; 4989 } 4990 case Intrinsic::stacksave: { 4991 SDValue Op = getRoot(); 4992 Res = DAG.getNode(ISD::STACKSAVE, dl, 4993 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4994 setValue(&I, Res); 4995 DAG.setRoot(Res.getValue(1)); 4996 return 0; 4997 } 4998 case Intrinsic::stackrestore: { 4999 Res = getValue(I.getArgOperand(0)); 5000 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 5001 return 0; 5002 } 5003 case Intrinsic::stackprotector: { 5004 // Emit code into the DAG to store the stack guard onto the stack. 5005 MachineFunction &MF = DAG.getMachineFunction(); 5006 MachineFrameInfo *MFI = MF.getFrameInfo(); 5007 EVT PtrTy = TLI.getPointerTy(); 5008 5009 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 5010 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 5011 5012 int FI = FuncInfo.StaticAllocaMap[Slot]; 5013 MFI->setStackProtectorIndex(FI); 5014 5015 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5016 5017 // Store the stack protector onto the stack. 5018 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 5019 MachinePointerInfo::getFixedStack(FI), 5020 true, false, 0); 5021 setValue(&I, Res); 5022 DAG.setRoot(Res); 5023 return 0; 5024 } 5025 case Intrinsic::objectsize: { 5026 // If we don't know by now, we're never going to know. 5027 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5028 5029 assert(CI && "Non-constant type in __builtin_object_size?"); 5030 5031 SDValue Arg = getValue(I.getCalledValue()); 5032 EVT Ty = Arg.getValueType(); 5033 5034 if (CI->isZero()) 5035 Res = DAG.getConstant(-1ULL, Ty); 5036 else 5037 Res = DAG.getConstant(0, Ty); 5038 5039 setValue(&I, Res); 5040 return 0; 5041 } 5042 case Intrinsic::var_annotation: 5043 // Discard annotate attributes 5044 return 0; 5045 5046 case Intrinsic::init_trampoline: { 5047 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5048 5049 SDValue Ops[6]; 5050 Ops[0] = getRoot(); 5051 Ops[1] = getValue(I.getArgOperand(0)); 5052 Ops[2] = getValue(I.getArgOperand(1)); 5053 Ops[3] = getValue(I.getArgOperand(2)); 5054 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5055 Ops[5] = DAG.getSrcValue(F); 5056 5057 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5058 5059 DAG.setRoot(Res); 5060 return 0; 5061 } 5062 case Intrinsic::adjust_trampoline: { 5063 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5064 TLI.getPointerTy(), 5065 getValue(I.getArgOperand(0)))); 5066 return 0; 5067 } 5068 case Intrinsic::gcroot: 5069 if (GFI) { 5070 const Value *Alloca = I.getArgOperand(0); 5071 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5072 5073 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5074 GFI->addStackRoot(FI->getIndex(), TypeMap); 5075 } 5076 return 0; 5077 case Intrinsic::gcread: 5078 case Intrinsic::gcwrite: 5079 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5080 case Intrinsic::flt_rounds: 5081 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5082 return 0; 5083 5084 case Intrinsic::expect: { 5085 // Just replace __builtin_expect(exp, c) with EXP. 5086 setValue(&I, getValue(I.getArgOperand(0))); 5087 return 0; 5088 } 5089 5090 case Intrinsic::trap: { 5091 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5092 if (TrapFuncName.empty()) { 5093 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 5094 return 0; 5095 } 5096 TargetLowering::ArgListTy Args; 5097 std::pair<SDValue, SDValue> Result = 5098 TLI.LowerCallTo(getRoot(), I.getType(), 5099 false, false, false, false, 0, CallingConv::C, 5100 /*isTailCall=*/false, 5101 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 5102 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5103 Args, DAG, getCurDebugLoc()); 5104 DAG.setRoot(Result.second); 5105 return 0; 5106 } 5107 case Intrinsic::uadd_with_overflow: 5108 return implVisitAluOverflow(I, ISD::UADDO); 5109 case Intrinsic::sadd_with_overflow: 5110 return implVisitAluOverflow(I, ISD::SADDO); 5111 case Intrinsic::usub_with_overflow: 5112 return implVisitAluOverflow(I, ISD::USUBO); 5113 case Intrinsic::ssub_with_overflow: 5114 return implVisitAluOverflow(I, ISD::SSUBO); 5115 case Intrinsic::umul_with_overflow: 5116 return implVisitAluOverflow(I, ISD::UMULO); 5117 case Intrinsic::smul_with_overflow: 5118 return implVisitAluOverflow(I, ISD::SMULO); 5119 5120 case Intrinsic::prefetch: { 5121 SDValue Ops[5]; 5122 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5123 Ops[0] = getRoot(); 5124 Ops[1] = getValue(I.getArgOperand(0)); 5125 Ops[2] = getValue(I.getArgOperand(1)); 5126 Ops[3] = getValue(I.getArgOperand(2)); 5127 Ops[4] = getValue(I.getArgOperand(3)); 5128 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5129 DAG.getVTList(MVT::Other), 5130 &Ops[0], 5, 5131 EVT::getIntegerVT(*Context, 8), 5132 MachinePointerInfo(I.getArgOperand(0)), 5133 0, /* align */ 5134 false, /* volatile */ 5135 rw==0, /* read */ 5136 rw==1)); /* write */ 5137 return 0; 5138 } 5139 5140 case Intrinsic::invariant_start: 5141 case Intrinsic::lifetime_start: 5142 // Discard region information. 5143 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5144 return 0; 5145 case Intrinsic::invariant_end: 5146 case Intrinsic::lifetime_end: 5147 // Discard region information. 5148 return 0; 5149 } 5150} 5151 5152void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5153 bool isTailCall, 5154 MachineBasicBlock *LandingPad) { 5155 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5156 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5157 Type *RetTy = FTy->getReturnType(); 5158 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5159 MCSymbol *BeginLabel = 0; 5160 5161 TargetLowering::ArgListTy Args; 5162 TargetLowering::ArgListEntry Entry; 5163 Args.reserve(CS.arg_size()); 5164 5165 // Check whether the function can return without sret-demotion. 5166 SmallVector<ISD::OutputArg, 4> Outs; 5167 SmallVector<uint64_t, 4> Offsets; 5168 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5169 Outs, TLI, &Offsets); 5170 5171 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5172 DAG.getMachineFunction(), 5173 FTy->isVarArg(), Outs, 5174 FTy->getContext()); 5175 5176 SDValue DemoteStackSlot; 5177 int DemoteStackIdx = -100; 5178 5179 if (!CanLowerReturn) { 5180 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5181 FTy->getReturnType()); 5182 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5183 FTy->getReturnType()); 5184 MachineFunction &MF = DAG.getMachineFunction(); 5185 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5186 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5187 5188 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5189 Entry.Node = DemoteStackSlot; 5190 Entry.Ty = StackSlotPtrType; 5191 Entry.isSExt = false; 5192 Entry.isZExt = false; 5193 Entry.isInReg = false; 5194 Entry.isSRet = true; 5195 Entry.isNest = false; 5196 Entry.isByVal = false; 5197 Entry.Alignment = Align; 5198 Args.push_back(Entry); 5199 RetTy = Type::getVoidTy(FTy->getContext()); 5200 } 5201 5202 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5203 i != e; ++i) { 5204 const Value *V = *i; 5205 5206 // Skip empty types 5207 if (V->getType()->isEmptyTy()) 5208 continue; 5209 5210 SDValue ArgNode = getValue(V); 5211 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5212 5213 unsigned attrInd = i - CS.arg_begin() + 1; 5214 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5215 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5216 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5217 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5218 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5219 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5220 Entry.Alignment = CS.getParamAlignment(attrInd); 5221 Args.push_back(Entry); 5222 } 5223 5224 if (LandingPad) { 5225 // Insert a label before the invoke call to mark the try range. This can be 5226 // used to detect deletion of the invoke via the MachineModuleInfo. 5227 BeginLabel = MMI.getContext().CreateTempSymbol(); 5228 5229 // For SjLj, keep track of which landing pads go with which invokes 5230 // so as to maintain the ordering of pads in the LSDA. 5231 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5232 if (CallSiteIndex) { 5233 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5234 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5235 5236 // Now that the call site is handled, stop tracking it. 5237 MMI.setCurrentCallSite(0); 5238 } 5239 5240 // Both PendingLoads and PendingExports must be flushed here; 5241 // this call might not return. 5242 (void)getRoot(); 5243 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5244 } 5245 5246 // Check if target-independent constraints permit a tail call here. 5247 // Target-dependent constraints are checked within TLI.LowerCallTo. 5248 if (isTailCall && 5249 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5250 isTailCall = false; 5251 5252 // If there's a possibility that fast-isel has already selected some amount 5253 // of the current basic block, don't emit a tail call. 5254 if (isTailCall && TM.Options.EnableFastISel) 5255 isTailCall = false; 5256 5257 std::pair<SDValue,SDValue> Result = 5258 TLI.LowerCallTo(getRoot(), RetTy, 5259 CS.paramHasAttr(0, Attribute::SExt), 5260 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 5261 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 5262 CS.getCallingConv(), 5263 isTailCall, 5264 CS.doesNotReturn(), 5265 !CS.getInstruction()->use_empty(), 5266 Callee, Args, DAG, getCurDebugLoc()); 5267 assert((isTailCall || Result.second.getNode()) && 5268 "Non-null chain expected with non-tail call!"); 5269 assert((Result.second.getNode() || !Result.first.getNode()) && 5270 "Null value expected with tail call!"); 5271 if (Result.first.getNode()) { 5272 setValue(CS.getInstruction(), Result.first); 5273 } else if (!CanLowerReturn && Result.second.getNode()) { 5274 // The instruction result is the result of loading from the 5275 // hidden sret parameter. 5276 SmallVector<EVT, 1> PVTs; 5277 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5278 5279 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5280 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5281 EVT PtrVT = PVTs[0]; 5282 unsigned NumValues = Outs.size(); 5283 SmallVector<SDValue, 4> Values(NumValues); 5284 SmallVector<SDValue, 4> Chains(NumValues); 5285 5286 for (unsigned i = 0; i < NumValues; ++i) { 5287 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5288 DemoteStackSlot, 5289 DAG.getConstant(Offsets[i], PtrVT)); 5290 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 5291 Add, 5292 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5293 false, false, false, 1); 5294 Values[i] = L; 5295 Chains[i] = L.getValue(1); 5296 } 5297 5298 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5299 MVT::Other, &Chains[0], NumValues); 5300 PendingLoads.push_back(Chain); 5301 5302 // Collect the legal value parts into potentially illegal values 5303 // that correspond to the original function's return values. 5304 SmallVector<EVT, 4> RetTys; 5305 RetTy = FTy->getReturnType(); 5306 ComputeValueVTs(TLI, RetTy, RetTys); 5307 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5308 SmallVector<SDValue, 4> ReturnValues; 5309 unsigned CurReg = 0; 5310 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5311 EVT VT = RetTys[I]; 5312 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 5313 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 5314 5315 SDValue ReturnValue = 5316 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 5317 RegisterVT, VT, AssertOp); 5318 ReturnValues.push_back(ReturnValue); 5319 CurReg += NumRegs; 5320 } 5321 5322 setValue(CS.getInstruction(), 5323 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5324 DAG.getVTList(&RetTys[0], RetTys.size()), 5325 &ReturnValues[0], ReturnValues.size())); 5326 } 5327 5328 // Assign order to nodes here. If the call does not produce a result, it won't 5329 // be mapped to a SDNode and visit() will not assign it an order number. 5330 if (!Result.second.getNode()) { 5331 // As a special case, a null chain means that a tail call has been emitted and 5332 // the DAG root is already updated. 5333 HasTailCall = true; 5334 ++SDNodeOrder; 5335 AssignOrderingToNode(DAG.getRoot().getNode()); 5336 } else { 5337 DAG.setRoot(Result.second); 5338 ++SDNodeOrder; 5339 AssignOrderingToNode(Result.second.getNode()); 5340 } 5341 5342 if (LandingPad) { 5343 // Insert a label at the end of the invoke call to mark the try range. This 5344 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5345 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5346 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5347 5348 // Inform MachineModuleInfo of range. 5349 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5350 } 5351} 5352 5353/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5354/// value is equal or not-equal to zero. 5355static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5356 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5357 UI != E; ++UI) { 5358 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5359 if (IC->isEquality()) 5360 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5361 if (C->isNullValue()) 5362 continue; 5363 // Unknown instruction. 5364 return false; 5365 } 5366 return true; 5367} 5368 5369static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5370 Type *LoadTy, 5371 SelectionDAGBuilder &Builder) { 5372 5373 // Check to see if this load can be trivially constant folded, e.g. if the 5374 // input is from a string literal. 5375 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5376 // Cast pointer to the type we really want to load. 5377 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5378 PointerType::getUnqual(LoadTy)); 5379 5380 if (const Constant *LoadCst = 5381 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5382 Builder.TD)) 5383 return Builder.getValue(LoadCst); 5384 } 5385 5386 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5387 // still constant memory, the input chain can be the entry node. 5388 SDValue Root; 5389 bool ConstantMemory = false; 5390 5391 // Do not serialize (non-volatile) loads of constant memory with anything. 5392 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5393 Root = Builder.DAG.getEntryNode(); 5394 ConstantMemory = true; 5395 } else { 5396 // Do not serialize non-volatile loads against each other. 5397 Root = Builder.DAG.getRoot(); 5398 } 5399 5400 SDValue Ptr = Builder.getValue(PtrVal); 5401 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5402 Ptr, MachinePointerInfo(PtrVal), 5403 false /*volatile*/, 5404 false /*nontemporal*/, 5405 false /*isinvariant*/, 1 /* align=1 */); 5406 5407 if (!ConstantMemory) 5408 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5409 return LoadVal; 5410} 5411 5412 5413/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5414/// If so, return true and lower it, otherwise return false and it will be 5415/// lowered like a normal call. 5416bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5417 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5418 if (I.getNumArgOperands() != 3) 5419 return false; 5420 5421 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5422 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5423 !I.getArgOperand(2)->getType()->isIntegerTy() || 5424 !I.getType()->isIntegerTy()) 5425 return false; 5426 5427 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5428 5429 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5430 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5431 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5432 bool ActuallyDoIt = true; 5433 MVT LoadVT; 5434 Type *LoadTy; 5435 switch (Size->getZExtValue()) { 5436 default: 5437 LoadVT = MVT::Other; 5438 LoadTy = 0; 5439 ActuallyDoIt = false; 5440 break; 5441 case 2: 5442 LoadVT = MVT::i16; 5443 LoadTy = Type::getInt16Ty(Size->getContext()); 5444 break; 5445 case 4: 5446 LoadVT = MVT::i32; 5447 LoadTy = Type::getInt32Ty(Size->getContext()); 5448 break; 5449 case 8: 5450 LoadVT = MVT::i64; 5451 LoadTy = Type::getInt64Ty(Size->getContext()); 5452 break; 5453 /* 5454 case 16: 5455 LoadVT = MVT::v4i32; 5456 LoadTy = Type::getInt32Ty(Size->getContext()); 5457 LoadTy = VectorType::get(LoadTy, 4); 5458 break; 5459 */ 5460 } 5461 5462 // This turns into unaligned loads. We only do this if the target natively 5463 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5464 // we'll only produce a small number of byte loads. 5465 5466 // Require that we can find a legal MVT, and only do this if the target 5467 // supports unaligned loads of that type. Expanding into byte loads would 5468 // bloat the code. 5469 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5470 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5471 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5472 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5473 ActuallyDoIt = false; 5474 } 5475 5476 if (ActuallyDoIt) { 5477 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5478 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5479 5480 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5481 ISD::SETNE); 5482 EVT CallVT = TLI.getValueType(I.getType(), true); 5483 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5484 return true; 5485 } 5486 } 5487 5488 5489 return false; 5490} 5491 5492 5493void SelectionDAGBuilder::visitCall(const CallInst &I) { 5494 // Handle inline assembly differently. 5495 if (isa<InlineAsm>(I.getCalledValue())) { 5496 visitInlineAsm(&I); 5497 return; 5498 } 5499 5500 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5501 ComputeUsesVAFloatArgument(I, &MMI); 5502 5503 const char *RenameFn = 0; 5504 if (Function *F = I.getCalledFunction()) { 5505 if (F->isDeclaration()) { 5506 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5507 if (unsigned IID = II->getIntrinsicID(F)) { 5508 RenameFn = visitIntrinsicCall(I, IID); 5509 if (!RenameFn) 5510 return; 5511 } 5512 } 5513 if (unsigned IID = F->getIntrinsicID()) { 5514 RenameFn = visitIntrinsicCall(I, IID); 5515 if (!RenameFn) 5516 return; 5517 } 5518 } 5519 5520 // Check for well-known libc/libm calls. If the function is internal, it 5521 // can't be a library call. 5522 if (!F->hasLocalLinkage() && F->hasName()) { 5523 StringRef Name = F->getName(); 5524 if ((LibInfo->has(LibFunc::copysign) && Name == "copysign") || 5525 (LibInfo->has(LibFunc::copysignf) && Name == "copysignf") || 5526 (LibInfo->has(LibFunc::copysignl) && Name == "copysignl")) { 5527 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5528 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5529 I.getType() == I.getArgOperand(0)->getType() && 5530 I.getType() == I.getArgOperand(1)->getType()) { 5531 SDValue LHS = getValue(I.getArgOperand(0)); 5532 SDValue RHS = getValue(I.getArgOperand(1)); 5533 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5534 LHS.getValueType(), LHS, RHS)); 5535 return; 5536 } 5537 } else if ((LibInfo->has(LibFunc::fabs) && Name == "fabs") || 5538 (LibInfo->has(LibFunc::fabsf) && Name == "fabsf") || 5539 (LibInfo->has(LibFunc::fabsl) && Name == "fabsl")) { 5540 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5541 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5542 I.getType() == I.getArgOperand(0)->getType()) { 5543 SDValue Tmp = getValue(I.getArgOperand(0)); 5544 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5545 Tmp.getValueType(), Tmp)); 5546 return; 5547 } 5548 } else if ((LibInfo->has(LibFunc::sin) && Name == "sin") || 5549 (LibInfo->has(LibFunc::sinf) && Name == "sinf") || 5550 (LibInfo->has(LibFunc::sinl) && Name == "sinl")) { 5551 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5552 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5553 I.getType() == I.getArgOperand(0)->getType() && 5554 I.onlyReadsMemory()) { 5555 SDValue Tmp = getValue(I.getArgOperand(0)); 5556 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5557 Tmp.getValueType(), Tmp)); 5558 return; 5559 } 5560 } else if ((LibInfo->has(LibFunc::cos) && Name == "cos") || 5561 (LibInfo->has(LibFunc::cosf) && Name == "cosf") || 5562 (LibInfo->has(LibFunc::cosl) && Name == "cosl")) { 5563 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5564 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5565 I.getType() == I.getArgOperand(0)->getType() && 5566 I.onlyReadsMemory()) { 5567 SDValue Tmp = getValue(I.getArgOperand(0)); 5568 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5569 Tmp.getValueType(), Tmp)); 5570 return; 5571 } 5572 } else if ((LibInfo->has(LibFunc::sqrt) && Name == "sqrt") || 5573 (LibInfo->has(LibFunc::sqrtf) && Name == "sqrtf") || 5574 (LibInfo->has(LibFunc::sqrtl) && Name == "sqrtl")) { 5575 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5576 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5577 I.getType() == I.getArgOperand(0)->getType() && 5578 I.onlyReadsMemory()) { 5579 SDValue Tmp = getValue(I.getArgOperand(0)); 5580 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5581 Tmp.getValueType(), Tmp)); 5582 return; 5583 } 5584 } else if ((LibInfo->has(LibFunc::floor) && Name == "floor") || 5585 (LibInfo->has(LibFunc::floorf) && Name == "floorf") || 5586 (LibInfo->has(LibFunc::floorl) && Name == "floorl")) { 5587 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5588 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5589 I.getType() == I.getArgOperand(0)->getType()) { 5590 SDValue Tmp = getValue(I.getArgOperand(0)); 5591 setValue(&I, DAG.getNode(ISD::FFLOOR, getCurDebugLoc(), 5592 Tmp.getValueType(), Tmp)); 5593 return; 5594 } 5595 } else if ((LibInfo->has(LibFunc::nearbyint) && Name == "nearbyint") || 5596 (LibInfo->has(LibFunc::nearbyintf) && Name == "nearbyintf") || 5597 (LibInfo->has(LibFunc::nearbyintl) && Name == "nearbyintl")) { 5598 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5599 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5600 I.getType() == I.getArgOperand(0)->getType()) { 5601 SDValue Tmp = getValue(I.getArgOperand(0)); 5602 setValue(&I, DAG.getNode(ISD::FNEARBYINT, getCurDebugLoc(), 5603 Tmp.getValueType(), Tmp)); 5604 return; 5605 } 5606 } else if ((LibInfo->has(LibFunc::ceil) && Name == "ceil") || 5607 (LibInfo->has(LibFunc::ceilf) && Name == "ceilf") || 5608 (LibInfo->has(LibFunc::ceill) && Name == "ceill")) { 5609 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5610 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5611 I.getType() == I.getArgOperand(0)->getType()) { 5612 SDValue Tmp = getValue(I.getArgOperand(0)); 5613 setValue(&I, DAG.getNode(ISD::FCEIL, getCurDebugLoc(), 5614 Tmp.getValueType(), Tmp)); 5615 return; 5616 } 5617 } else if ((LibInfo->has(LibFunc::rint) && Name == "rint") || 5618 (LibInfo->has(LibFunc::rintf) && Name == "rintf") || 5619 (LibInfo->has(LibFunc::rintl) && Name == "rintl")) { 5620 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5621 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5622 I.getType() == I.getArgOperand(0)->getType()) { 5623 SDValue Tmp = getValue(I.getArgOperand(0)); 5624 setValue(&I, DAG.getNode(ISD::FRINT, getCurDebugLoc(), 5625 Tmp.getValueType(), Tmp)); 5626 return; 5627 } 5628 } else if ((LibInfo->has(LibFunc::trunc) && Name == "trunc") || 5629 (LibInfo->has(LibFunc::truncf) && Name == "truncf") || 5630 (LibInfo->has(LibFunc::truncl) && Name == "truncl")) { 5631 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5632 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5633 I.getType() == I.getArgOperand(0)->getType()) { 5634 SDValue Tmp = getValue(I.getArgOperand(0)); 5635 setValue(&I, DAG.getNode(ISD::FTRUNC, getCurDebugLoc(), 5636 Tmp.getValueType(), Tmp)); 5637 return; 5638 } 5639 } else if ((LibInfo->has(LibFunc::log2) && Name == "log2") || 5640 (LibInfo->has(LibFunc::log2f) && Name == "log2f") || 5641 (LibInfo->has(LibFunc::log2l) && Name == "log2l")) { 5642 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5643 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5644 I.getType() == I.getArgOperand(0)->getType() && 5645 I.onlyReadsMemory()) { 5646 SDValue Tmp = getValue(I.getArgOperand(0)); 5647 setValue(&I, DAG.getNode(ISD::FLOG2, getCurDebugLoc(), 5648 Tmp.getValueType(), Tmp)); 5649 return; 5650 } 5651 } else if ((LibInfo->has(LibFunc::exp2) && Name == "exp2") || 5652 (LibInfo->has(LibFunc::exp2f) && Name == "exp2f") || 5653 (LibInfo->has(LibFunc::exp2l) && Name == "exp2l")) { 5654 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5655 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5656 I.getType() == I.getArgOperand(0)->getType() && 5657 I.onlyReadsMemory()) { 5658 SDValue Tmp = getValue(I.getArgOperand(0)); 5659 setValue(&I, DAG.getNode(ISD::FEXP2, getCurDebugLoc(), 5660 Tmp.getValueType(), Tmp)); 5661 return; 5662 } 5663 } else if (Name == "memcmp") { 5664 if (visitMemCmpCall(I)) 5665 return; 5666 } 5667 } 5668 } 5669 5670 SDValue Callee; 5671 if (!RenameFn) 5672 Callee = getValue(I.getCalledValue()); 5673 else 5674 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5675 5676 // Check if we can potentially perform a tail call. More detailed checking is 5677 // be done within LowerCallTo, after more information about the call is known. 5678 LowerCallTo(&I, Callee, I.isTailCall()); 5679} 5680 5681namespace { 5682 5683/// AsmOperandInfo - This contains information for each constraint that we are 5684/// lowering. 5685class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5686public: 5687 /// CallOperand - If this is the result output operand or a clobber 5688 /// this is null, otherwise it is the incoming operand to the CallInst. 5689 /// This gets modified as the asm is processed. 5690 SDValue CallOperand; 5691 5692 /// AssignedRegs - If this is a register or register class operand, this 5693 /// contains the set of register corresponding to the operand. 5694 RegsForValue AssignedRegs; 5695 5696 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5697 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5698 } 5699 5700 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5701 /// corresponds to. If there is no Value* for this operand, it returns 5702 /// MVT::Other. 5703 EVT getCallOperandValEVT(LLVMContext &Context, 5704 const TargetLowering &TLI, 5705 const TargetData *TD) const { 5706 if (CallOperandVal == 0) return MVT::Other; 5707 5708 if (isa<BasicBlock>(CallOperandVal)) 5709 return TLI.getPointerTy(); 5710 5711 llvm::Type *OpTy = CallOperandVal->getType(); 5712 5713 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5714 // If this is an indirect operand, the operand is a pointer to the 5715 // accessed type. 5716 if (isIndirect) { 5717 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5718 if (!PtrTy) 5719 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5720 OpTy = PtrTy->getElementType(); 5721 } 5722 5723 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5724 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5725 if (STy->getNumElements() == 1) 5726 OpTy = STy->getElementType(0); 5727 5728 // If OpTy is not a single value, it may be a struct/union that we 5729 // can tile with integers. 5730 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5731 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5732 switch (BitSize) { 5733 default: break; 5734 case 1: 5735 case 8: 5736 case 16: 5737 case 32: 5738 case 64: 5739 case 128: 5740 OpTy = IntegerType::get(Context, BitSize); 5741 break; 5742 } 5743 } 5744 5745 return TLI.getValueType(OpTy, true); 5746 } 5747}; 5748 5749typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5750 5751} // end anonymous namespace 5752 5753/// GetRegistersForValue - Assign registers (virtual or physical) for the 5754/// specified operand. We prefer to assign virtual registers, to allow the 5755/// register allocator to handle the assignment process. However, if the asm 5756/// uses features that we can't model on machineinstrs, we have SDISel do the 5757/// allocation. This produces generally horrible, but correct, code. 5758/// 5759/// OpInfo describes the operand. 5760/// 5761static void GetRegistersForValue(SelectionDAG &DAG, 5762 const TargetLowering &TLI, 5763 DebugLoc DL, 5764 SDISelAsmOperandInfo &OpInfo) { 5765 LLVMContext &Context = *DAG.getContext(); 5766 5767 MachineFunction &MF = DAG.getMachineFunction(); 5768 SmallVector<unsigned, 4> Regs; 5769 5770 // If this is a constraint for a single physreg, or a constraint for a 5771 // register class, find it. 5772 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5773 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5774 OpInfo.ConstraintVT); 5775 5776 unsigned NumRegs = 1; 5777 if (OpInfo.ConstraintVT != MVT::Other) { 5778 // If this is a FP input in an integer register (or visa versa) insert a bit 5779 // cast of the input value. More generally, handle any case where the input 5780 // value disagrees with the register class we plan to stick this in. 5781 if (OpInfo.Type == InlineAsm::isInput && 5782 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5783 // Try to convert to the first EVT that the reg class contains. If the 5784 // types are identical size, use a bitcast to convert (e.g. two differing 5785 // vector types). 5786 EVT RegVT = *PhysReg.second->vt_begin(); 5787 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5788 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5789 RegVT, OpInfo.CallOperand); 5790 OpInfo.ConstraintVT = RegVT; 5791 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5792 // If the input is a FP value and we want it in FP registers, do a 5793 // bitcast to the corresponding integer type. This turns an f64 value 5794 // into i64, which can be passed with two i32 values on a 32-bit 5795 // machine. 5796 RegVT = EVT::getIntegerVT(Context, 5797 OpInfo.ConstraintVT.getSizeInBits()); 5798 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5799 RegVT, OpInfo.CallOperand); 5800 OpInfo.ConstraintVT = RegVT; 5801 } 5802 } 5803 5804 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5805 } 5806 5807 EVT RegVT; 5808 EVT ValueVT = OpInfo.ConstraintVT; 5809 5810 // If this is a constraint for a specific physical register, like {r17}, 5811 // assign it now. 5812 if (unsigned AssignedReg = PhysReg.first) { 5813 const TargetRegisterClass *RC = PhysReg.second; 5814 if (OpInfo.ConstraintVT == MVT::Other) 5815 ValueVT = *RC->vt_begin(); 5816 5817 // Get the actual register value type. This is important, because the user 5818 // may have asked for (e.g.) the AX register in i32 type. We need to 5819 // remember that AX is actually i16 to get the right extension. 5820 RegVT = *RC->vt_begin(); 5821 5822 // This is a explicit reference to a physical register. 5823 Regs.push_back(AssignedReg); 5824 5825 // If this is an expanded reference, add the rest of the regs to Regs. 5826 if (NumRegs != 1) { 5827 TargetRegisterClass::iterator I = RC->begin(); 5828 for (; *I != AssignedReg; ++I) 5829 assert(I != RC->end() && "Didn't find reg!"); 5830 5831 // Already added the first reg. 5832 --NumRegs; ++I; 5833 for (; NumRegs; --NumRegs, ++I) { 5834 assert(I != RC->end() && "Ran out of registers to allocate!"); 5835 Regs.push_back(*I); 5836 } 5837 } 5838 5839 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5840 return; 5841 } 5842 5843 // Otherwise, if this was a reference to an LLVM register class, create vregs 5844 // for this reference. 5845 if (const TargetRegisterClass *RC = PhysReg.second) { 5846 RegVT = *RC->vt_begin(); 5847 if (OpInfo.ConstraintVT == MVT::Other) 5848 ValueVT = RegVT; 5849 5850 // Create the appropriate number of virtual registers. 5851 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5852 for (; NumRegs; --NumRegs) 5853 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5854 5855 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5856 return; 5857 } 5858 5859 // Otherwise, we couldn't allocate enough registers for this. 5860} 5861 5862/// visitInlineAsm - Handle a call to an InlineAsm object. 5863/// 5864void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5865 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5866 5867 /// ConstraintOperands - Information about all of the constraints. 5868 SDISelAsmOperandInfoVector ConstraintOperands; 5869 5870 TargetLowering::AsmOperandInfoVector 5871 TargetConstraints = TLI.ParseConstraints(CS); 5872 5873 bool hasMemory = false; 5874 5875 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5876 unsigned ResNo = 0; // ResNo - The result number of the next output. 5877 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5878 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5879 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5880 5881 EVT OpVT = MVT::Other; 5882 5883 // Compute the value type for each operand. 5884 switch (OpInfo.Type) { 5885 case InlineAsm::isOutput: 5886 // Indirect outputs just consume an argument. 5887 if (OpInfo.isIndirect) { 5888 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5889 break; 5890 } 5891 5892 // The return value of the call is this value. As such, there is no 5893 // corresponding argument. 5894 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5895 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5896 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5897 } else { 5898 assert(ResNo == 0 && "Asm only has one result!"); 5899 OpVT = TLI.getValueType(CS.getType()); 5900 } 5901 ++ResNo; 5902 break; 5903 case InlineAsm::isInput: 5904 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5905 break; 5906 case InlineAsm::isClobber: 5907 // Nothing to do. 5908 break; 5909 } 5910 5911 // If this is an input or an indirect output, process the call argument. 5912 // BasicBlocks are labels, currently appearing only in asm's. 5913 if (OpInfo.CallOperandVal) { 5914 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5915 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5916 } else { 5917 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5918 } 5919 5920 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5921 } 5922 5923 OpInfo.ConstraintVT = OpVT; 5924 5925 // Indirect operand accesses access memory. 5926 if (OpInfo.isIndirect) 5927 hasMemory = true; 5928 else { 5929 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5930 TargetLowering::ConstraintType 5931 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5932 if (CType == TargetLowering::C_Memory) { 5933 hasMemory = true; 5934 break; 5935 } 5936 } 5937 } 5938 } 5939 5940 SDValue Chain, Flag; 5941 5942 // We won't need to flush pending loads if this asm doesn't touch 5943 // memory and is nonvolatile. 5944 if (hasMemory || IA->hasSideEffects()) 5945 Chain = getRoot(); 5946 else 5947 Chain = DAG.getRoot(); 5948 5949 // Second pass over the constraints: compute which constraint option to use 5950 // and assign registers to constraints that want a specific physreg. 5951 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5952 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5953 5954 // If this is an output operand with a matching input operand, look up the 5955 // matching input. If their types mismatch, e.g. one is an integer, the 5956 // other is floating point, or their sizes are different, flag it as an 5957 // error. 5958 if (OpInfo.hasMatchingInput()) { 5959 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5960 5961 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5962 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5963 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5964 OpInfo.ConstraintVT); 5965 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5966 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 5967 Input.ConstraintVT); 5968 if ((OpInfo.ConstraintVT.isInteger() != 5969 Input.ConstraintVT.isInteger()) || 5970 (MatchRC.second != InputRC.second)) { 5971 report_fatal_error("Unsupported asm: input constraint" 5972 " with a matching output constraint of" 5973 " incompatible type!"); 5974 } 5975 Input.ConstraintVT = OpInfo.ConstraintVT; 5976 } 5977 } 5978 5979 // Compute the constraint code and ConstraintType to use. 5980 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5981 5982 // If this is a memory input, and if the operand is not indirect, do what we 5983 // need to to provide an address for the memory input. 5984 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5985 !OpInfo.isIndirect) { 5986 assert((OpInfo.isMultipleAlternative || 5987 (OpInfo.Type == InlineAsm::isInput)) && 5988 "Can only indirectify direct input operands!"); 5989 5990 // Memory operands really want the address of the value. If we don't have 5991 // an indirect input, put it in the constpool if we can, otherwise spill 5992 // it to a stack slot. 5993 // TODO: This isn't quite right. We need to handle these according to 5994 // the addressing mode that the constraint wants. Also, this may take 5995 // an additional register for the computation and we don't want that 5996 // either. 5997 5998 // If the operand is a float, integer, or vector constant, spill to a 5999 // constant pool entry to get its address. 6000 const Value *OpVal = OpInfo.CallOperandVal; 6001 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 6002 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { 6003 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 6004 TLI.getPointerTy()); 6005 } else { 6006 // Otherwise, create a stack slot and emit a store to it before the 6007 // asm. 6008 Type *Ty = OpVal->getType(); 6009 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 6010 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 6011 MachineFunction &MF = DAG.getMachineFunction(); 6012 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 6013 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 6014 Chain = DAG.getStore(Chain, getCurDebugLoc(), 6015 OpInfo.CallOperand, StackSlot, 6016 MachinePointerInfo::getFixedStack(SSFI), 6017 false, false, 0); 6018 OpInfo.CallOperand = StackSlot; 6019 } 6020 6021 // There is no longer a Value* corresponding to this operand. 6022 OpInfo.CallOperandVal = 0; 6023 6024 // It is now an indirect operand. 6025 OpInfo.isIndirect = true; 6026 } 6027 6028 // If this constraint is for a specific register, allocate it before 6029 // anything else. 6030 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6031 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6032 } 6033 6034 // Second pass - Loop over all of the operands, assigning virtual or physregs 6035 // to register class operands. 6036 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6037 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6038 6039 // C_Register operands have already been allocated, Other/Memory don't need 6040 // to be. 6041 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6042 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6043 } 6044 6045 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6046 std::vector<SDValue> AsmNodeOperands; 6047 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6048 AsmNodeOperands.push_back( 6049 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6050 TLI.getPointerTy())); 6051 6052 // If we have a !srcloc metadata node associated with it, we want to attach 6053 // this to the ultimately generated inline asm machineinstr. To do this, we 6054 // pass in the third operand as this (potentially null) inline asm MDNode. 6055 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6056 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6057 6058 // Remember the HasSideEffect and AlignStack bits as operand 3. 6059 unsigned ExtraInfo = 0; 6060 if (IA->hasSideEffects()) 6061 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6062 if (IA->isAlignStack()) 6063 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6064 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6065 TLI.getPointerTy())); 6066 6067 // Loop over all of the inputs, copying the operand values into the 6068 // appropriate registers and processing the output regs. 6069 RegsForValue RetValRegs; 6070 6071 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6072 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6073 6074 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6075 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6076 6077 switch (OpInfo.Type) { 6078 case InlineAsm::isOutput: { 6079 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6080 OpInfo.ConstraintType != TargetLowering::C_Register) { 6081 // Memory output, or 'other' output (e.g. 'X' constraint). 6082 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6083 6084 // Add information to the INLINEASM node to know about this output. 6085 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6086 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6087 TLI.getPointerTy())); 6088 AsmNodeOperands.push_back(OpInfo.CallOperand); 6089 break; 6090 } 6091 6092 // Otherwise, this is a register or register class output. 6093 6094 // Copy the output from the appropriate register. Find a register that 6095 // we can use. 6096 if (OpInfo.AssignedRegs.Regs.empty()) { 6097 LLVMContext &Ctx = *DAG.getContext(); 6098 Ctx.emitError(CS.getInstruction(), 6099 "couldn't allocate output register for constraint '" + 6100 Twine(OpInfo.ConstraintCode) + "'"); 6101 break; 6102 } 6103 6104 // If this is an indirect operand, store through the pointer after the 6105 // asm. 6106 if (OpInfo.isIndirect) { 6107 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6108 OpInfo.CallOperandVal)); 6109 } else { 6110 // This is the result value of the call. 6111 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6112 // Concatenate this output onto the outputs list. 6113 RetValRegs.append(OpInfo.AssignedRegs); 6114 } 6115 6116 // Add information to the INLINEASM node to know that this register is 6117 // set. 6118 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6119 InlineAsm::Kind_RegDefEarlyClobber : 6120 InlineAsm::Kind_RegDef, 6121 false, 6122 0, 6123 DAG, 6124 AsmNodeOperands); 6125 break; 6126 } 6127 case InlineAsm::isInput: { 6128 SDValue InOperandVal = OpInfo.CallOperand; 6129 6130 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6131 // If this is required to match an output register we have already set, 6132 // just use its register. 6133 unsigned OperandNo = OpInfo.getMatchedOperand(); 6134 6135 // Scan until we find the definition we already emitted of this operand. 6136 // When we find it, create a RegsForValue operand. 6137 unsigned CurOp = InlineAsm::Op_FirstOperand; 6138 for (; OperandNo; --OperandNo) { 6139 // Advance to the next operand. 6140 unsigned OpFlag = 6141 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6142 assert((InlineAsm::isRegDefKind(OpFlag) || 6143 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6144 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6145 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6146 } 6147 6148 unsigned OpFlag = 6149 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6150 if (InlineAsm::isRegDefKind(OpFlag) || 6151 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6152 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6153 if (OpInfo.isIndirect) { 6154 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6155 LLVMContext &Ctx = *DAG.getContext(); 6156 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6157 " don't know how to handle tied " 6158 "indirect register inputs"); 6159 } 6160 6161 RegsForValue MatchedRegs; 6162 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6163 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6164 MatchedRegs.RegVTs.push_back(RegVT); 6165 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6166 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6167 i != e; ++i) 6168 MatchedRegs.Regs.push_back 6169 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6170 6171 // Use the produced MatchedRegs object to 6172 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6173 Chain, &Flag); 6174 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6175 true, OpInfo.getMatchedOperand(), 6176 DAG, AsmNodeOperands); 6177 break; 6178 } 6179 6180 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6181 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6182 "Unexpected number of operands"); 6183 // Add information to the INLINEASM node to know about this input. 6184 // See InlineAsm.h isUseOperandTiedToDef. 6185 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6186 OpInfo.getMatchedOperand()); 6187 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6188 TLI.getPointerTy())); 6189 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6190 break; 6191 } 6192 6193 // Treat indirect 'X' constraint as memory. 6194 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6195 OpInfo.isIndirect) 6196 OpInfo.ConstraintType = TargetLowering::C_Memory; 6197 6198 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6199 std::vector<SDValue> Ops; 6200 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6201 Ops, DAG); 6202 if (Ops.empty()) { 6203 LLVMContext &Ctx = *DAG.getContext(); 6204 Ctx.emitError(CS.getInstruction(), 6205 "invalid operand for inline asm constraint '" + 6206 Twine(OpInfo.ConstraintCode) + "'"); 6207 break; 6208 } 6209 6210 // Add information to the INLINEASM node to know about this input. 6211 unsigned ResOpType = 6212 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6213 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6214 TLI.getPointerTy())); 6215 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6216 break; 6217 } 6218 6219 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6220 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6221 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6222 "Memory operands expect pointer values"); 6223 6224 // Add information to the INLINEASM node to know about this input. 6225 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6226 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6227 TLI.getPointerTy())); 6228 AsmNodeOperands.push_back(InOperandVal); 6229 break; 6230 } 6231 6232 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6233 OpInfo.ConstraintType == TargetLowering::C_Register) && 6234 "Unknown constraint type!"); 6235 assert(!OpInfo.isIndirect && 6236 "Don't know how to handle indirect register inputs yet!"); 6237 6238 // Copy the input into the appropriate registers. 6239 if (OpInfo.AssignedRegs.Regs.empty()) { 6240 LLVMContext &Ctx = *DAG.getContext(); 6241 Ctx.emitError(CS.getInstruction(), 6242 "couldn't allocate input reg for constraint '" + 6243 Twine(OpInfo.ConstraintCode) + "'"); 6244 break; 6245 } 6246 6247 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6248 Chain, &Flag); 6249 6250 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6251 DAG, AsmNodeOperands); 6252 break; 6253 } 6254 case InlineAsm::isClobber: { 6255 // Add the clobbered value to the operand list, so that the register 6256 // allocator is aware that the physreg got clobbered. 6257 if (!OpInfo.AssignedRegs.Regs.empty()) 6258 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6259 false, 0, DAG, 6260 AsmNodeOperands); 6261 break; 6262 } 6263 } 6264 } 6265 6266 // Finish up input operands. Set the input chain and add the flag last. 6267 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6268 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6269 6270 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6271 DAG.getVTList(MVT::Other, MVT::Glue), 6272 &AsmNodeOperands[0], AsmNodeOperands.size()); 6273 Flag = Chain.getValue(1); 6274 6275 // If this asm returns a register value, copy the result from that register 6276 // and set it as the value of the call. 6277 if (!RetValRegs.Regs.empty()) { 6278 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6279 Chain, &Flag); 6280 6281 // FIXME: Why don't we do this for inline asms with MRVs? 6282 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6283 EVT ResultType = TLI.getValueType(CS.getType()); 6284 6285 // If any of the results of the inline asm is a vector, it may have the 6286 // wrong width/num elts. This can happen for register classes that can 6287 // contain multiple different value types. The preg or vreg allocated may 6288 // not have the same VT as was expected. Convert it to the right type 6289 // with bit_convert. 6290 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6291 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6292 ResultType, Val); 6293 6294 } else if (ResultType != Val.getValueType() && 6295 ResultType.isInteger() && Val.getValueType().isInteger()) { 6296 // If a result value was tied to an input value, the computed result may 6297 // have a wider width than the expected result. Extract the relevant 6298 // portion. 6299 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6300 } 6301 6302 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6303 } 6304 6305 setValue(CS.getInstruction(), Val); 6306 // Don't need to use this as a chain in this case. 6307 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6308 return; 6309 } 6310 6311 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6312 6313 // Process indirect outputs, first output all of the flagged copies out of 6314 // physregs. 6315 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6316 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6317 const Value *Ptr = IndirectStoresToEmit[i].second; 6318 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6319 Chain, &Flag); 6320 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6321 } 6322 6323 // Emit the non-flagged stores from the physregs. 6324 SmallVector<SDValue, 8> OutChains; 6325 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6326 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6327 StoresToEmit[i].first, 6328 getValue(StoresToEmit[i].second), 6329 MachinePointerInfo(StoresToEmit[i].second), 6330 false, false, 0); 6331 OutChains.push_back(Val); 6332 } 6333 6334 if (!OutChains.empty()) 6335 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6336 &OutChains[0], OutChains.size()); 6337 6338 DAG.setRoot(Chain); 6339} 6340 6341void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6342 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6343 MVT::Other, getRoot(), 6344 getValue(I.getArgOperand(0)), 6345 DAG.getSrcValue(I.getArgOperand(0)))); 6346} 6347 6348void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6349 const TargetData &TD = *TLI.getTargetData(); 6350 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6351 getRoot(), getValue(I.getOperand(0)), 6352 DAG.getSrcValue(I.getOperand(0)), 6353 TD.getABITypeAlignment(I.getType())); 6354 setValue(&I, V); 6355 DAG.setRoot(V.getValue(1)); 6356} 6357 6358void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6359 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6360 MVT::Other, getRoot(), 6361 getValue(I.getArgOperand(0)), 6362 DAG.getSrcValue(I.getArgOperand(0)))); 6363} 6364 6365void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6366 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6367 MVT::Other, getRoot(), 6368 getValue(I.getArgOperand(0)), 6369 getValue(I.getArgOperand(1)), 6370 DAG.getSrcValue(I.getArgOperand(0)), 6371 DAG.getSrcValue(I.getArgOperand(1)))); 6372} 6373 6374/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6375/// implementation, which just calls LowerCall. 6376/// FIXME: When all targets are 6377/// migrated to using LowerCall, this hook should be integrated into SDISel. 6378std::pair<SDValue, SDValue> 6379TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy, 6380 bool RetSExt, bool RetZExt, bool isVarArg, 6381 bool isInreg, unsigned NumFixedArgs, 6382 CallingConv::ID CallConv, bool isTailCall, 6383 bool doesNotRet, bool isReturnValueUsed, 6384 SDValue Callee, 6385 ArgListTy &Args, SelectionDAG &DAG, 6386 DebugLoc dl) const { 6387 // Handle all of the outgoing arguments. 6388 SmallVector<ISD::OutputArg, 32> Outs; 6389 SmallVector<SDValue, 32> OutVals; 6390 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6391 SmallVector<EVT, 4> ValueVTs; 6392 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6393 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6394 Value != NumValues; ++Value) { 6395 EVT VT = ValueVTs[Value]; 6396 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6397 SDValue Op = SDValue(Args[i].Node.getNode(), 6398 Args[i].Node.getResNo() + Value); 6399 ISD::ArgFlagsTy Flags; 6400 unsigned OriginalAlignment = 6401 getTargetData()->getABITypeAlignment(ArgTy); 6402 6403 if (Args[i].isZExt) 6404 Flags.setZExt(); 6405 if (Args[i].isSExt) 6406 Flags.setSExt(); 6407 if (Args[i].isInReg) 6408 Flags.setInReg(); 6409 if (Args[i].isSRet) 6410 Flags.setSRet(); 6411 if (Args[i].isByVal) { 6412 Flags.setByVal(); 6413 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6414 Type *ElementTy = Ty->getElementType(); 6415 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6416 // For ByVal, alignment should come from FE. BE will guess if this 6417 // info is not there but there are cases it cannot get right. 6418 unsigned FrameAlign; 6419 if (Args[i].Alignment) 6420 FrameAlign = Args[i].Alignment; 6421 else 6422 FrameAlign = getByValTypeAlignment(ElementTy); 6423 Flags.setByValAlign(FrameAlign); 6424 } 6425 if (Args[i].isNest) 6426 Flags.setNest(); 6427 Flags.setOrigAlign(OriginalAlignment); 6428 6429 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6430 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6431 SmallVector<SDValue, 4> Parts(NumParts); 6432 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6433 6434 if (Args[i].isSExt) 6435 ExtendKind = ISD::SIGN_EXTEND; 6436 else if (Args[i].isZExt) 6437 ExtendKind = ISD::ZERO_EXTEND; 6438 6439 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6440 PartVT, ExtendKind); 6441 6442 for (unsigned j = 0; j != NumParts; ++j) { 6443 // if it isn't first piece, alignment must be 1 6444 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6445 i < NumFixedArgs); 6446 if (NumParts > 1 && j == 0) 6447 MyFlags.Flags.setSplit(); 6448 else if (j != 0) 6449 MyFlags.Flags.setOrigAlign(1); 6450 6451 Outs.push_back(MyFlags); 6452 OutVals.push_back(Parts[j]); 6453 } 6454 } 6455 } 6456 6457 // Handle the incoming return values from the call. 6458 SmallVector<ISD::InputArg, 32> Ins; 6459 SmallVector<EVT, 4> RetTys; 6460 ComputeValueVTs(*this, RetTy, RetTys); 6461 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6462 EVT VT = RetTys[I]; 6463 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6464 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6465 for (unsigned i = 0; i != NumRegs; ++i) { 6466 ISD::InputArg MyFlags; 6467 MyFlags.VT = RegisterVT.getSimpleVT(); 6468 MyFlags.Used = isReturnValueUsed; 6469 if (RetSExt) 6470 MyFlags.Flags.setSExt(); 6471 if (RetZExt) 6472 MyFlags.Flags.setZExt(); 6473 if (isInreg) 6474 MyFlags.Flags.setInReg(); 6475 Ins.push_back(MyFlags); 6476 } 6477 } 6478 6479 SmallVector<SDValue, 4> InVals; 6480 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, doesNotRet, isTailCall, 6481 Outs, OutVals, Ins, dl, DAG, InVals); 6482 6483 // Verify that the target's LowerCall behaved as expected. 6484 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6485 "LowerCall didn't return a valid chain!"); 6486 assert((!isTailCall || InVals.empty()) && 6487 "LowerCall emitted a return value for a tail call!"); 6488 assert((isTailCall || InVals.size() == Ins.size()) && 6489 "LowerCall didn't emit the correct number of values!"); 6490 6491 // For a tail call, the return value is merely live-out and there aren't 6492 // any nodes in the DAG representing it. Return a special value to 6493 // indicate that a tail call has been emitted and no more Instructions 6494 // should be processed in the current block. 6495 if (isTailCall) { 6496 DAG.setRoot(Chain); 6497 return std::make_pair(SDValue(), SDValue()); 6498 } 6499 6500 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6501 assert(InVals[i].getNode() && 6502 "LowerCall emitted a null value!"); 6503 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6504 "LowerCall emitted a value with the wrong type!"); 6505 }); 6506 6507 // Collect the legal value parts into potentially illegal values 6508 // that correspond to the original function's return values. 6509 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6510 if (RetSExt) 6511 AssertOp = ISD::AssertSext; 6512 else if (RetZExt) 6513 AssertOp = ISD::AssertZext; 6514 SmallVector<SDValue, 4> ReturnValues; 6515 unsigned CurReg = 0; 6516 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6517 EVT VT = RetTys[I]; 6518 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6519 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6520 6521 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6522 NumRegs, RegisterVT, VT, 6523 AssertOp)); 6524 CurReg += NumRegs; 6525 } 6526 6527 // For a function returning void, there is no return value. We can't create 6528 // such a node, so we just return a null return value in that case. In 6529 // that case, nothing will actually look at the value. 6530 if (ReturnValues.empty()) 6531 return std::make_pair(SDValue(), Chain); 6532 6533 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6534 DAG.getVTList(&RetTys[0], RetTys.size()), 6535 &ReturnValues[0], ReturnValues.size()); 6536 return std::make_pair(Res, Chain); 6537} 6538 6539void TargetLowering::LowerOperationWrapper(SDNode *N, 6540 SmallVectorImpl<SDValue> &Results, 6541 SelectionDAG &DAG) const { 6542 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6543 if (Res.getNode()) 6544 Results.push_back(Res); 6545} 6546 6547SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6548 llvm_unreachable("LowerOperation not implemented for this target!"); 6549} 6550 6551void 6552SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6553 SDValue Op = getNonRegisterValue(V); 6554 assert((Op.getOpcode() != ISD::CopyFromReg || 6555 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6556 "Copy from a reg to the same reg!"); 6557 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6558 6559 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6560 SDValue Chain = DAG.getEntryNode(); 6561 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6562 PendingExports.push_back(Chain); 6563} 6564 6565#include "llvm/CodeGen/SelectionDAGISel.h" 6566 6567/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6568/// entry block, return true. This includes arguments used by switches, since 6569/// the switch may expand into multiple basic blocks. 6570static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 6571 // With FastISel active, we may be splitting blocks, so force creation 6572 // of virtual registers for all non-dead arguments. 6573 if (FastISel) 6574 return A->use_empty(); 6575 6576 const BasicBlock *Entry = A->getParent()->begin(); 6577 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6578 UI != E; ++UI) { 6579 const User *U = *UI; 6580 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6581 return false; // Use not in entry block. 6582 } 6583 return true; 6584} 6585 6586void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6587 // If this is the entry block, emit arguments. 6588 const Function &F = *LLVMBB->getParent(); 6589 SelectionDAG &DAG = SDB->DAG; 6590 DebugLoc dl = SDB->getCurDebugLoc(); 6591 const TargetData *TD = TLI.getTargetData(); 6592 SmallVector<ISD::InputArg, 16> Ins; 6593 6594 // Check whether the function can return without sret-demotion. 6595 SmallVector<ISD::OutputArg, 4> Outs; 6596 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6597 Outs, TLI); 6598 6599 if (!FuncInfo->CanLowerReturn) { 6600 // Put in an sret pointer parameter before all the other parameters. 6601 SmallVector<EVT, 1> ValueVTs; 6602 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6603 6604 // NOTE: Assuming that a pointer will never break down to more than one VT 6605 // or one register. 6606 ISD::ArgFlagsTy Flags; 6607 Flags.setSRet(); 6608 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6609 ISD::InputArg RetArg(Flags, RegisterVT, true); 6610 Ins.push_back(RetArg); 6611 } 6612 6613 // Set up the incoming argument description vector. 6614 unsigned Idx = 1; 6615 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6616 I != E; ++I, ++Idx) { 6617 SmallVector<EVT, 4> ValueVTs; 6618 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6619 bool isArgValueUsed = !I->use_empty(); 6620 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6621 Value != NumValues; ++Value) { 6622 EVT VT = ValueVTs[Value]; 6623 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6624 ISD::ArgFlagsTy Flags; 6625 unsigned OriginalAlignment = 6626 TD->getABITypeAlignment(ArgTy); 6627 6628 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6629 Flags.setZExt(); 6630 if (F.paramHasAttr(Idx, Attribute::SExt)) 6631 Flags.setSExt(); 6632 if (F.paramHasAttr(Idx, Attribute::InReg)) 6633 Flags.setInReg(); 6634 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6635 Flags.setSRet(); 6636 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6637 Flags.setByVal(); 6638 PointerType *Ty = cast<PointerType>(I->getType()); 6639 Type *ElementTy = Ty->getElementType(); 6640 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6641 // For ByVal, alignment should be passed from FE. BE will guess if 6642 // this info is not there but there are cases it cannot get right. 6643 unsigned FrameAlign; 6644 if (F.getParamAlignment(Idx)) 6645 FrameAlign = F.getParamAlignment(Idx); 6646 else 6647 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6648 Flags.setByValAlign(FrameAlign); 6649 } 6650 if (F.paramHasAttr(Idx, Attribute::Nest)) 6651 Flags.setNest(); 6652 Flags.setOrigAlign(OriginalAlignment); 6653 6654 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6655 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6656 for (unsigned i = 0; i != NumRegs; ++i) { 6657 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6658 if (NumRegs > 1 && i == 0) 6659 MyFlags.Flags.setSplit(); 6660 // if it isn't first piece, alignment must be 1 6661 else if (i > 0) 6662 MyFlags.Flags.setOrigAlign(1); 6663 Ins.push_back(MyFlags); 6664 } 6665 } 6666 } 6667 6668 // Call the target to set up the argument values. 6669 SmallVector<SDValue, 8> InVals; 6670 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6671 F.isVarArg(), Ins, 6672 dl, DAG, InVals); 6673 6674 // Verify that the target's LowerFormalArguments behaved as expected. 6675 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6676 "LowerFormalArguments didn't return a valid chain!"); 6677 assert(InVals.size() == Ins.size() && 6678 "LowerFormalArguments didn't emit the correct number of values!"); 6679 DEBUG({ 6680 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6681 assert(InVals[i].getNode() && 6682 "LowerFormalArguments emitted a null value!"); 6683 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6684 "LowerFormalArguments emitted a value with the wrong type!"); 6685 } 6686 }); 6687 6688 // Update the DAG with the new chain value resulting from argument lowering. 6689 DAG.setRoot(NewRoot); 6690 6691 // Set up the argument values. 6692 unsigned i = 0; 6693 Idx = 1; 6694 if (!FuncInfo->CanLowerReturn) { 6695 // Create a virtual register for the sret pointer, and put in a copy 6696 // from the sret argument into it. 6697 SmallVector<EVT, 1> ValueVTs; 6698 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6699 EVT VT = ValueVTs[0]; 6700 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6701 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6702 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6703 RegVT, VT, AssertOp); 6704 6705 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6706 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6707 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6708 FuncInfo->DemoteRegister = SRetReg; 6709 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6710 SRetReg, ArgValue); 6711 DAG.setRoot(NewRoot); 6712 6713 // i indexes lowered arguments. Bump it past the hidden sret argument. 6714 // Idx indexes LLVM arguments. Don't touch it. 6715 ++i; 6716 } 6717 6718 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6719 ++I, ++Idx) { 6720 SmallVector<SDValue, 4> ArgValues; 6721 SmallVector<EVT, 4> ValueVTs; 6722 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6723 unsigned NumValues = ValueVTs.size(); 6724 6725 // If this argument is unused then remember its value. It is used to generate 6726 // debugging information. 6727 if (I->use_empty() && NumValues) 6728 SDB->setUnusedArgValue(I, InVals[i]); 6729 6730 for (unsigned Val = 0; Val != NumValues; ++Val) { 6731 EVT VT = ValueVTs[Val]; 6732 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6733 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6734 6735 if (!I->use_empty()) { 6736 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6737 if (F.paramHasAttr(Idx, Attribute::SExt)) 6738 AssertOp = ISD::AssertSext; 6739 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6740 AssertOp = ISD::AssertZext; 6741 6742 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6743 NumParts, PartVT, VT, 6744 AssertOp)); 6745 } 6746 6747 i += NumParts; 6748 } 6749 6750 // We don't need to do anything else for unused arguments. 6751 if (ArgValues.empty()) 6752 continue; 6753 6754 // Note down frame index. 6755 if (FrameIndexSDNode *FI = 6756 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6757 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6758 6759 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6760 SDB->getCurDebugLoc()); 6761 6762 SDB->setValue(I, Res); 6763 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6764 if (LoadSDNode *LNode = 6765 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6766 if (FrameIndexSDNode *FI = 6767 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6768 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6769 } 6770 6771 // If this argument is live outside of the entry block, insert a copy from 6772 // wherever we got it to the vreg that other BB's will reference it as. 6773 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6774 // If we can, though, try to skip creating an unnecessary vreg. 6775 // FIXME: This isn't very clean... it would be nice to make this more 6776 // general. It's also subtly incompatible with the hacks FastISel 6777 // uses with vregs. 6778 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6779 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6780 FuncInfo->ValueMap[I] = Reg; 6781 continue; 6782 } 6783 } 6784 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 6785 FuncInfo->InitializeRegForValue(I); 6786 SDB->CopyToExportRegsIfNeeded(I); 6787 } 6788 } 6789 6790 assert(i == InVals.size() && "Argument register count mismatch!"); 6791 6792 // Finally, if the target has anything special to do, allow it to do so. 6793 // FIXME: this should insert code into the DAG! 6794 EmitFunctionEntryCode(); 6795} 6796 6797/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6798/// ensure constants are generated when needed. Remember the virtual registers 6799/// that need to be added to the Machine PHI nodes as input. We cannot just 6800/// directly add them, because expansion might result in multiple MBB's for one 6801/// BB. As such, the start of the BB might correspond to a different MBB than 6802/// the end. 6803/// 6804void 6805SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6806 const TerminatorInst *TI = LLVMBB->getTerminator(); 6807 6808 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6809 6810 // Check successor nodes' PHI nodes that expect a constant to be available 6811 // from this block. 6812 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6813 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6814 if (!isa<PHINode>(SuccBB->begin())) continue; 6815 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6816 6817 // If this terminator has multiple identical successors (common for 6818 // switches), only handle each succ once. 6819 if (!SuccsHandled.insert(SuccMBB)) continue; 6820 6821 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6822 6823 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6824 // nodes and Machine PHI nodes, but the incoming operands have not been 6825 // emitted yet. 6826 for (BasicBlock::const_iterator I = SuccBB->begin(); 6827 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6828 // Ignore dead phi's. 6829 if (PN->use_empty()) continue; 6830 6831 // Skip empty types 6832 if (PN->getType()->isEmptyTy()) 6833 continue; 6834 6835 unsigned Reg; 6836 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6837 6838 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6839 unsigned &RegOut = ConstantsOut[C]; 6840 if (RegOut == 0) { 6841 RegOut = FuncInfo.CreateRegs(C->getType()); 6842 CopyValueToVirtualRegister(C, RegOut); 6843 } 6844 Reg = RegOut; 6845 } else { 6846 DenseMap<const Value *, unsigned>::iterator I = 6847 FuncInfo.ValueMap.find(PHIOp); 6848 if (I != FuncInfo.ValueMap.end()) 6849 Reg = I->second; 6850 else { 6851 assert(isa<AllocaInst>(PHIOp) && 6852 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6853 "Didn't codegen value into a register!??"); 6854 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6855 CopyValueToVirtualRegister(PHIOp, Reg); 6856 } 6857 } 6858 6859 // Remember that this register needs to added to the machine PHI node as 6860 // the input for this MBB. 6861 SmallVector<EVT, 4> ValueVTs; 6862 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6863 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6864 EVT VT = ValueVTs[vti]; 6865 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6866 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6867 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6868 Reg += NumRegisters; 6869 } 6870 } 6871 } 6872 ConstantsOut.clear(); 6873} 6874