SelectionDAGBuilder.cpp revision be5b032e4b06ae001098856c2dc4ebca41528132
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SelectionDAGBuilder.h" 16#include "FunctionLoweringInfo.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/SmallSet.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/ConstantFolding.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/Module.h" 31#include "llvm/CodeGen/FastISel.h" 32#include "llvm/CodeGen/GCStrategy.h" 33#include "llvm/CodeGen/GCMetadata.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineFrameInfo.h" 36#include "llvm/CodeGen/MachineInstrBuilder.h" 37#include "llvm/CodeGen/MachineJumpTableInfo.h" 38#include "llvm/CodeGen/MachineModuleInfo.h" 39#include "llvm/CodeGen/MachineRegisterInfo.h" 40#include "llvm/CodeGen/PseudoSourceValue.h" 41#include "llvm/CodeGen/SelectionDAG.h" 42#include "llvm/CodeGen/DwarfWriter.h" 43#include "llvm/Analysis/DebugInfo.h" 44#include "llvm/Target/TargetRegisterInfo.h" 45#include "llvm/Target/TargetData.h" 46#include "llvm/Target/TargetFrameInfo.h" 47#include "llvm/Target/TargetInstrInfo.h" 48#include "llvm/Target/TargetIntrinsicInfo.h" 49#include "llvm/Target/TargetLowering.h" 50#include "llvm/Target/TargetOptions.h" 51#include "llvm/Support/Compiler.h" 52#include "llvm/Support/CommandLine.h" 53#include "llvm/Support/Debug.h" 54#include "llvm/Support/ErrorHandling.h" 55#include "llvm/Support/MathExtras.h" 56#include "llvm/Support/raw_ostream.h" 57#include <algorithm> 58using namespace llvm; 59 60/// LimitFloatPrecision - Generate low-precision inline sequences for 61/// some float libcalls (6, 8 or 12 bits). 62static unsigned LimitFloatPrecision; 63 64static cl::opt<unsigned, true> 65LimitFPPrecision("limit-float-precision", 66 cl::desc("Generate low-precision inline sequences " 67 "for some float libcalls"), 68 cl::location(LimitFloatPrecision), 69 cl::init(0)); 70 71namespace { 72 /// RegsForValue - This struct represents the registers (physical or virtual) 73 /// that a particular set of values is assigned, and the type information 74 /// about the value. The most common situation is to represent one value at a 75 /// time, but struct or array values are handled element-wise as multiple 76 /// values. The splitting of aggregates is performed recursively, so that we 77 /// never have aggregate-typed registers. The values at this point do not 78 /// necessarily have legal types, so each value may require one or more 79 /// registers of some legal type. 80 /// 81 struct RegsForValue { 82 /// TLI - The TargetLowering object. 83 /// 84 const TargetLowering *TLI; 85 86 /// ValueVTs - The value types of the values, which may not be legal, and 87 /// may need be promoted or synthesized from one or more registers. 88 /// 89 SmallVector<EVT, 4> ValueVTs; 90 91 /// RegVTs - The value types of the registers. This is the same size as 92 /// ValueVTs and it records, for each value, what the type of the assigned 93 /// register or registers are. (Individual values are never synthesized 94 /// from more than one type of register.) 95 /// 96 /// With virtual registers, the contents of RegVTs is redundant with TLI's 97 /// getRegisterType member function, however when with physical registers 98 /// it is necessary to have a separate record of the types. 99 /// 100 SmallVector<EVT, 4> RegVTs; 101 102 /// Regs - This list holds the registers assigned to the values. 103 /// Each legal or promoted value requires one register, and each 104 /// expanded value requires multiple registers. 105 /// 106 SmallVector<unsigned, 4> Regs; 107 108 RegsForValue() : TLI(0) {} 109 110 RegsForValue(const TargetLowering &tli, 111 const SmallVector<unsigned, 4> ®s, 112 EVT regvt, EVT valuevt) 113 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 114 RegsForValue(const TargetLowering &tli, 115 const SmallVector<unsigned, 4> ®s, 116 const SmallVector<EVT, 4> ®vts, 117 const SmallVector<EVT, 4> &valuevts) 118 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {} 119 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 120 unsigned Reg, const Type *Ty) : TLI(&tli) { 121 ComputeValueVTs(tli, Ty, ValueVTs); 122 123 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 124 EVT ValueVT = ValueVTs[Value]; 125 unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT); 126 EVT RegisterVT = TLI->getRegisterType(Context, ValueVT); 127 for (unsigned i = 0; i != NumRegs; ++i) 128 Regs.push_back(Reg + i); 129 RegVTs.push_back(RegisterVT); 130 Reg += NumRegs; 131 } 132 } 133 134 /// areValueTypesLegal - Return true if types of all the values are legal. 135 bool areValueTypesLegal() { 136 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 137 EVT RegisterVT = RegVTs[Value]; 138 if (!TLI->isTypeLegal(RegisterVT)) 139 return false; 140 } 141 return true; 142 } 143 144 145 /// append - Add the specified values to this one. 146 void append(const RegsForValue &RHS) { 147 TLI = RHS.TLI; 148 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 149 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 150 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 151 } 152 153 154 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 155 /// this value and returns the result as a ValueVTs value. This uses 156 /// Chain/Flag as the input and updates them for the output Chain/Flag. 157 /// If the Flag pointer is NULL, no flag is used. 158 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, 159 SDValue &Chain, SDValue *Flag) const; 160 161 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 162 /// specified value into the registers specified by this object. This uses 163 /// Chain/Flag as the input and updates them for the output Chain/Flag. 164 /// If the Flag pointer is NULL, no flag is used. 165 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 166 SDValue &Chain, SDValue *Flag) const; 167 168 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 169 /// operand list. This adds the code marker, matching input operand index 170 /// (if applicable), and includes the number of values added into it. 171 void AddInlineAsmOperands(unsigned Code, 172 bool HasMatching, unsigned MatchingIdx, 173 SelectionDAG &DAG, 174 std::vector<SDValue> &Ops) const; 175 }; 176} 177 178/// getCopyFromParts - Create a value that contains the specified legal parts 179/// combined into the value they represent. If the parts combine to a type 180/// larger then ValueVT then AssertOp can be used to specify whether the extra 181/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 182/// (ISD::AssertSext). 183static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, 184 const SDValue *Parts, 185 unsigned NumParts, EVT PartVT, EVT ValueVT, 186 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 187 assert(NumParts > 0 && "No parts to assemble!"); 188 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 189 SDValue Val = Parts[0]; 190 191 if (NumParts > 1) { 192 // Assemble the value from multiple parts. 193 if (!ValueVT.isVector() && ValueVT.isInteger()) { 194 unsigned PartBits = PartVT.getSizeInBits(); 195 unsigned ValueBits = ValueVT.getSizeInBits(); 196 197 // Assemble the power of 2 part. 198 unsigned RoundParts = NumParts & (NumParts - 1) ? 199 1 << Log2_32(NumParts) : NumParts; 200 unsigned RoundBits = PartBits * RoundParts; 201 EVT RoundVT = RoundBits == ValueBits ? 202 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 203 SDValue Lo, Hi; 204 205 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 206 207 if (RoundParts > 2) { 208 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts / 2, 209 PartVT, HalfVT); 210 Hi = getCopyFromParts(DAG, dl, Parts + RoundParts / 2, 211 RoundParts / 2, PartVT, HalfVT); 212 } else { 213 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]); 214 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]); 215 } 216 217 if (TLI.isBigEndian()) 218 std::swap(Lo, Hi); 219 220 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi); 221 222 if (RoundParts < NumParts) { 223 // Assemble the trailing non-power-of-2 part. 224 unsigned OddParts = NumParts - RoundParts; 225 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 226 Hi = getCopyFromParts(DAG, dl, 227 Parts + RoundParts, OddParts, PartVT, OddVT); 228 229 // Combine the round and odd parts. 230 Lo = Val; 231 if (TLI.isBigEndian()) 232 std::swap(Lo, Hi); 233 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 234 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi); 235 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi, 236 DAG.getConstant(Lo.getValueType().getSizeInBits(), 237 TLI.getPointerTy())); 238 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo); 239 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi); 240 } 241 } else if (ValueVT.isVector()) { 242 // Handle a multi-element vector. 243 EVT IntermediateVT, RegisterVT; 244 unsigned NumIntermediates; 245 unsigned NumRegs = 246 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 247 NumIntermediates, RegisterVT); 248 assert(NumRegs == NumParts 249 && "Part count doesn't match vector breakdown!"); 250 NumParts = NumRegs; // Silence a compiler warning. 251 assert(RegisterVT == PartVT 252 && "Part type doesn't match vector breakdown!"); 253 assert(RegisterVT == Parts[0].getValueType() && 254 "Part type doesn't match part!"); 255 256 // Assemble the parts into intermediate operands. 257 SmallVector<SDValue, 8> Ops(NumIntermediates); 258 if (NumIntermediates == NumParts) { 259 // If the register was not expanded, truncate or copy the value, 260 // as appropriate. 261 for (unsigned i = 0; i != NumParts; ++i) 262 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1, 263 PartVT, IntermediateVT); 264 } else if (NumParts > 0) { 265 // If the intermediate type was expanded, build the intermediate 266 // operands from the parts. 267 assert(NumParts % NumIntermediates == 0 && 268 "Must expand into a divisible number of parts!"); 269 unsigned Factor = NumParts / NumIntermediates; 270 for (unsigned i = 0; i != NumIntermediates; ++i) 271 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor, 272 PartVT, IntermediateVT); 273 } 274 275 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 276 // intermediate operands. 277 Val = DAG.getNode(IntermediateVT.isVector() ? 278 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl, 279 ValueVT, &Ops[0], NumIntermediates); 280 } else if (PartVT.isFloatingPoint()) { 281 // FP split into multiple FP parts (for ppcf128) 282 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 283 "Unexpected split"); 284 SDValue Lo, Hi; 285 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]); 286 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]); 287 if (TLI.isBigEndian()) 288 std::swap(Lo, Hi); 289 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi); 290 } else { 291 // FP split into integer parts (soft fp) 292 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 293 !PartVT.isVector() && "Unexpected split"); 294 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 295 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT); 296 } 297 } 298 299 // There is now one part, held in Val. Correct it to match ValueVT. 300 PartVT = Val.getValueType(); 301 302 if (PartVT == ValueVT) 303 return Val; 304 305 if (PartVT.isVector()) { 306 assert(ValueVT.isVector() && "Unknown vector conversion!"); 307 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); 308 } 309 310 if (ValueVT.isVector()) { 311 assert(ValueVT.getVectorElementType() == PartVT && 312 ValueVT.getVectorNumElements() == 1 && 313 "Only trivial scalar-to-vector conversions should get here!"); 314 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val); 315 } 316 317 if (PartVT.isInteger() && 318 ValueVT.isInteger()) { 319 if (ValueVT.bitsLT(PartVT)) { 320 // For a truncate, see if we have any information to 321 // indicate whether the truncated bits will always be 322 // zero or sign-extension. 323 if (AssertOp != ISD::DELETED_NODE) 324 Val = DAG.getNode(AssertOp, dl, PartVT, Val, 325 DAG.getValueType(ValueVT)); 326 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); 327 } else { 328 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val); 329 } 330 } 331 332 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 333 if (ValueVT.bitsLT(Val.getValueType())) { 334 // FP_ROUND's are always exact here. 335 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val, 336 DAG.getIntPtrConstant(1)); 337 } 338 339 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val); 340 } 341 342 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 343 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); 344 345 llvm_unreachable("Unknown mismatch!"); 346 return SDValue(); 347} 348 349/// getCopyToParts - Create a series of nodes that contain the specified value 350/// split into legal parts. If the parts contain more bits than Val, then, for 351/// integers, ExtendKind can be used to specify how to generate the extra bits. 352static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, 353 SDValue Val, SDValue *Parts, unsigned NumParts, 354 EVT PartVT, 355 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 356 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 357 EVT PtrVT = TLI.getPointerTy(); 358 EVT ValueVT = Val.getValueType(); 359 unsigned PartBits = PartVT.getSizeInBits(); 360 unsigned OrigNumParts = NumParts; 361 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 362 363 if (!NumParts) 364 return; 365 366 if (!ValueVT.isVector()) { 367 if (PartVT == ValueVT) { 368 assert(NumParts == 1 && "No-op copy with multiple parts!"); 369 Parts[0] = Val; 370 return; 371 } 372 373 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 374 // If the parts cover more bits than the value has, promote the value. 375 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 376 assert(NumParts == 1 && "Do not know what to promote to!"); 377 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val); 378 } else if (PartVT.isInteger() && ValueVT.isInteger()) { 379 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 380 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val); 381 } else { 382 llvm_unreachable("Unknown mismatch!"); 383 } 384 } else if (PartBits == ValueVT.getSizeInBits()) { 385 // Different types of the same size. 386 assert(NumParts == 1 && PartVT != ValueVT); 387 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val); 388 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 389 // If the parts cover less bits than value has, truncate the value. 390 if (PartVT.isInteger() && ValueVT.isInteger()) { 391 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 392 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); 393 } else { 394 llvm_unreachable("Unknown mismatch!"); 395 } 396 } 397 398 // The value may have changed - recompute ValueVT. 399 ValueVT = Val.getValueType(); 400 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 401 "Failed to tile the value with PartVT!"); 402 403 if (NumParts == 1) { 404 assert(PartVT == ValueVT && "Type conversion failed!"); 405 Parts[0] = Val; 406 return; 407 } 408 409 // Expand the value into multiple parts. 410 if (NumParts & (NumParts - 1)) { 411 // The number of parts is not a power of 2. Split off and copy the tail. 412 assert(PartVT.isInteger() && ValueVT.isInteger() && 413 "Do not know what to expand to!"); 414 unsigned RoundParts = 1 << Log2_32(NumParts); 415 unsigned RoundBits = RoundParts * PartBits; 416 unsigned OddParts = NumParts - RoundParts; 417 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val, 418 DAG.getConstant(RoundBits, 419 TLI.getPointerTy())); 420 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, 421 OddParts, PartVT); 422 423 if (TLI.isBigEndian()) 424 // The odd parts were reversed by getCopyToParts - unreverse them. 425 std::reverse(Parts + RoundParts, Parts + NumParts); 426 427 NumParts = RoundParts; 428 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 429 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); 430 } 431 432 // The number of parts is a power of 2. Repeatedly bisect the value using 433 // EXTRACT_ELEMENT. 434 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl, 435 EVT::getIntegerVT(*DAG.getContext(), 436 ValueVT.getSizeInBits()), 437 Val); 438 439 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 440 for (unsigned i = 0; i < NumParts; i += StepSize) { 441 unsigned ThisBits = StepSize * PartBits / 2; 442 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 443 SDValue &Part0 = Parts[i]; 444 SDValue &Part1 = Parts[i+StepSize/2]; 445 446 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 447 ThisVT, Part0, 448 DAG.getConstant(1, PtrVT)); 449 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 450 ThisVT, Part0, 451 DAG.getConstant(0, PtrVT)); 452 453 if (ThisBits == PartBits && ThisVT != PartVT) { 454 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl, 455 PartVT, Part0); 456 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl, 457 PartVT, Part1); 458 } 459 } 460 } 461 462 if (TLI.isBigEndian()) 463 std::reverse(Parts, Parts + OrigNumParts); 464 465 return; 466 } 467 468 // Vector ValueVT. 469 if (NumParts == 1) { 470 if (PartVT != ValueVT) { 471 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 472 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val); 473 } else { 474 assert(ValueVT.getVectorElementType() == PartVT && 475 ValueVT.getVectorNumElements() == 1 && 476 "Only trivial vector-to-scalar conversions should get here!"); 477 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 478 PartVT, Val, 479 DAG.getConstant(0, PtrVT)); 480 } 481 } 482 483 Parts[0] = Val; 484 return; 485 } 486 487 // Handle a multi-element vector. 488 EVT IntermediateVT, RegisterVT; 489 unsigned NumIntermediates; 490 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 491 IntermediateVT, NumIntermediates, RegisterVT); 492 unsigned NumElements = ValueVT.getVectorNumElements(); 493 494 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 495 NumParts = NumRegs; // Silence a compiler warning. 496 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 497 498 // Split the vector into intermediate operands. 499 SmallVector<SDValue, 8> Ops(NumIntermediates); 500 for (unsigned i = 0; i != NumIntermediates; ++i) { 501 if (IntermediateVT.isVector()) 502 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, 503 IntermediateVT, Val, 504 DAG.getConstant(i * (NumElements / NumIntermediates), 505 PtrVT)); 506 else 507 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 508 IntermediateVT, Val, 509 DAG.getConstant(i, PtrVT)); 510 } 511 512 // Split the intermediate operands into legal parts. 513 if (NumParts == NumIntermediates) { 514 // If the register was not expanded, promote or copy the value, 515 // as appropriate. 516 for (unsigned i = 0; i != NumParts; ++i) 517 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT); 518 } else if (NumParts > 0) { 519 // If the intermediate type was expanded, split each the value into 520 // legal parts. 521 assert(NumParts % NumIntermediates == 0 && 522 "Must expand into a divisible number of parts!"); 523 unsigned Factor = NumParts / NumIntermediates; 524 for (unsigned i = 0; i != NumIntermediates; ++i) 525 getCopyToParts(DAG, dl, Ops[i], &Parts[i*Factor], Factor, PartVT); 526 } 527} 528 529 530void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 531 AA = &aa; 532 GFI = gfi; 533 TD = DAG.getTarget().getTargetData(); 534} 535 536/// clear - Clear out the curret SelectionDAG and the associated 537/// state and prepare this SelectionDAGBuilder object to be used 538/// for a new block. This doesn't clear out information about 539/// additional blocks that are needed to complete switch lowering 540/// or PHI node updating; that information is cleared out as it is 541/// consumed. 542void SelectionDAGBuilder::clear() { 543 NodeMap.clear(); 544 PendingLoads.clear(); 545 PendingExports.clear(); 546 EdgeMapping.clear(); 547 DAG.clear(); 548 CurDebugLoc = DebugLoc::getUnknownLoc(); 549 HasTailCall = false; 550} 551 552/// getRoot - Return the current virtual root of the Selection DAG, 553/// flushing any PendingLoad items. This must be done before emitting 554/// a store or any other node that may need to be ordered after any 555/// prior load instructions. 556/// 557SDValue SelectionDAGBuilder::getRoot() { 558 if (PendingLoads.empty()) 559 return DAG.getRoot(); 560 561 if (PendingLoads.size() == 1) { 562 SDValue Root = PendingLoads[0]; 563 DAG.setRoot(Root); 564 PendingLoads.clear(); 565 return Root; 566 } 567 568 // Otherwise, we have to make a token factor node. 569 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 570 &PendingLoads[0], PendingLoads.size()); 571 PendingLoads.clear(); 572 DAG.setRoot(Root); 573 return Root; 574} 575 576/// getControlRoot - Similar to getRoot, but instead of flushing all the 577/// PendingLoad items, flush all the PendingExports items. It is necessary 578/// to do this before emitting a terminator instruction. 579/// 580SDValue SelectionDAGBuilder::getControlRoot() { 581 SDValue Root = DAG.getRoot(); 582 583 if (PendingExports.empty()) 584 return Root; 585 586 // Turn all of the CopyToReg chains into one factored node. 587 if (Root.getOpcode() != ISD::EntryToken) { 588 unsigned i = 0, e = PendingExports.size(); 589 for (; i != e; ++i) { 590 assert(PendingExports[i].getNode()->getNumOperands() > 1); 591 if (PendingExports[i].getNode()->getOperand(0) == Root) 592 break; // Don't add the root if we already indirectly depend on it. 593 } 594 595 if (i == e) 596 PendingExports.push_back(Root); 597 } 598 599 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 600 &PendingExports[0], 601 PendingExports.size()); 602 PendingExports.clear(); 603 DAG.setRoot(Root); 604 return Root; 605} 606 607void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 608 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 609 DAG.AssignOrdering(Node, SDNodeOrder); 610 611 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 612 AssignOrderingToNode(Node->getOperand(I).getNode()); 613} 614 615void SelectionDAGBuilder::visit(Instruction &I) { 616 visit(I.getOpcode(), I); 617} 618 619void SelectionDAGBuilder::visit(unsigned Opcode, User &I) { 620 // Note: this doesn't use InstVisitor, because it has to work with 621 // ConstantExpr's in addition to instructions. 622 switch (Opcode) { 623 default: llvm_unreachable("Unknown instruction type encountered!"); 624 // Build the switch statement using the Instruction.def file. 625#define HANDLE_INST(NUM, OPCODE, CLASS) \ 626 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 627#include "llvm/Instruction.def" 628 } 629 630 // Assign the ordering to the freshly created DAG nodes. 631 if (NodeMap.count(&I)) { 632 ++SDNodeOrder; 633 AssignOrderingToNode(getValue(&I).getNode()); 634 } 635} 636 637SDValue SelectionDAGBuilder::getValue(const Value *V) { 638 SDValue &N = NodeMap[V]; 639 if (N.getNode()) return N; 640 641 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 642 EVT VT = TLI.getValueType(V->getType(), true); 643 644 if (ConstantInt *CI = dyn_cast<ConstantInt>(C)) 645 return N = DAG.getConstant(*CI, VT); 646 647 if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) 648 return N = DAG.getGlobalAddress(GV, VT); 649 650 if (isa<ConstantPointerNull>(C)) 651 return N = DAG.getConstant(0, TLI.getPointerTy()); 652 653 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 654 return N = DAG.getConstantFP(*CFP, VT); 655 656 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 657 return N = DAG.getUNDEF(VT); 658 659 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 660 visit(CE->getOpcode(), *CE); 661 SDValue N1 = NodeMap[V]; 662 assert(N1.getNode() && "visit didn't populate the ValueMap!"); 663 return N1; 664 } 665 666 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 667 SmallVector<SDValue, 4> Constants; 668 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 669 OI != OE; ++OI) { 670 SDNode *Val = getValue(*OI).getNode(); 671 // If the operand is an empty aggregate, there are no values. 672 if (!Val) continue; 673 // Add each leaf value from the operand to the Constants list 674 // to form a flattened list of all the values. 675 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 676 Constants.push_back(SDValue(Val, i)); 677 } 678 679 return DAG.getMergeValues(&Constants[0], Constants.size(), 680 getCurDebugLoc()); 681 } 682 683 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 684 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 685 "Unknown struct or array constant!"); 686 687 SmallVector<EVT, 4> ValueVTs; 688 ComputeValueVTs(TLI, C->getType(), ValueVTs); 689 unsigned NumElts = ValueVTs.size(); 690 if (NumElts == 0) 691 return SDValue(); // empty struct 692 SmallVector<SDValue, 4> Constants(NumElts); 693 for (unsigned i = 0; i != NumElts; ++i) { 694 EVT EltVT = ValueVTs[i]; 695 if (isa<UndefValue>(C)) 696 Constants[i] = DAG.getUNDEF(EltVT); 697 else if (EltVT.isFloatingPoint()) 698 Constants[i] = DAG.getConstantFP(0, EltVT); 699 else 700 Constants[i] = DAG.getConstant(0, EltVT); 701 } 702 703 return DAG.getMergeValues(&Constants[0], NumElts, 704 getCurDebugLoc()); 705 } 706 707 if (BlockAddress *BA = dyn_cast<BlockAddress>(C)) 708 return DAG.getBlockAddress(BA, VT); 709 710 const VectorType *VecTy = cast<VectorType>(V->getType()); 711 unsigned NumElements = VecTy->getNumElements(); 712 713 // Now that we know the number and type of the elements, get that number of 714 // elements into the Ops array based on what kind of constant it is. 715 SmallVector<SDValue, 16> Ops; 716 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 717 for (unsigned i = 0; i != NumElements; ++i) 718 Ops.push_back(getValue(CP->getOperand(i))); 719 } else { 720 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 721 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 722 723 SDValue Op; 724 if (EltVT.isFloatingPoint()) 725 Op = DAG.getConstantFP(0, EltVT); 726 else 727 Op = DAG.getConstant(0, EltVT); 728 Ops.assign(NumElements, Op); 729 } 730 731 // Create a BUILD_VECTOR node. 732 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 733 VT, &Ops[0], Ops.size()); 734 } 735 736 // If this is a static alloca, generate it as the frameindex instead of 737 // computation. 738 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 739 DenseMap<const AllocaInst*, int>::iterator SI = 740 FuncInfo.StaticAllocaMap.find(AI); 741 if (SI != FuncInfo.StaticAllocaMap.end()) 742 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 743 } 744 745 unsigned InReg = FuncInfo.ValueMap[V]; 746 assert(InReg && "Value not in map!"); 747 748 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 749 SDValue Chain = DAG.getEntryNode(); 750 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL); 751} 752 753/// Get the EVTs and ArgFlags collections that represent the legalized return 754/// type of the given function. This does not require a DAG or a return value, 755/// and is suitable for use before any DAGs for the function are constructed. 756static void getReturnInfo(const Type* ReturnType, 757 Attributes attr, SmallVectorImpl<EVT> &OutVTs, 758 SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags, 759 TargetLowering &TLI, 760 SmallVectorImpl<uint64_t> *Offsets = 0) { 761 SmallVector<EVT, 4> ValueVTs; 762 ComputeValueVTs(TLI, ReturnType, ValueVTs); 763 unsigned NumValues = ValueVTs.size(); 764 if (NumValues == 0) return; 765 unsigned Offset = 0; 766 767 for (unsigned j = 0, f = NumValues; j != f; ++j) { 768 EVT VT = ValueVTs[j]; 769 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 770 771 if (attr & Attribute::SExt) 772 ExtendKind = ISD::SIGN_EXTEND; 773 else if (attr & Attribute::ZExt) 774 ExtendKind = ISD::ZERO_EXTEND; 775 776 // FIXME: C calling convention requires the return type to be promoted to 777 // at least 32-bit. But this is not necessary for non-C calling 778 // conventions. The frontend should mark functions whose return values 779 // require promoting with signext or zeroext attributes. 780 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 781 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 782 if (VT.bitsLT(MinVT)) 783 VT = MinVT; 784 } 785 786 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 787 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 788 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 789 PartVT.getTypeForEVT(ReturnType->getContext())); 790 791 // 'inreg' on function refers to return value 792 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 793 if (attr & Attribute::InReg) 794 Flags.setInReg(); 795 796 // Propagate extension type if any 797 if (attr & Attribute::SExt) 798 Flags.setSExt(); 799 else if (attr & Attribute::ZExt) 800 Flags.setZExt(); 801 802 for (unsigned i = 0; i < NumParts; ++i) { 803 OutVTs.push_back(PartVT); 804 OutFlags.push_back(Flags); 805 if (Offsets) 806 { 807 Offsets->push_back(Offset); 808 Offset += PartSize; 809 } 810 } 811 } 812} 813 814void SelectionDAGBuilder::visitRet(ReturnInst &I) { 815 SDValue Chain = getControlRoot(); 816 SmallVector<ISD::OutputArg, 8> Outs; 817 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 818 819 if (!FLI.CanLowerReturn) { 820 unsigned DemoteReg = FLI.DemoteRegister; 821 const Function *F = I.getParent()->getParent(); 822 823 // Emit a store of the return value through the virtual register. 824 // Leave Outs empty so that LowerReturn won't try to load return 825 // registers the usual way. 826 SmallVector<EVT, 1> PtrValueVTs; 827 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 828 PtrValueVTs); 829 830 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 831 SDValue RetOp = getValue(I.getOperand(0)); 832 833 SmallVector<EVT, 4> ValueVTs; 834 SmallVector<uint64_t, 4> Offsets; 835 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 836 unsigned NumValues = ValueVTs.size(); 837 838 SmallVector<SDValue, 4> Chains(NumValues); 839 EVT PtrVT = PtrValueVTs[0]; 840 for (unsigned i = 0; i != NumValues; ++i) { 841 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, RetPtr, 842 DAG.getConstant(Offsets[i], PtrVT)); 843 Chains[i] = 844 DAG.getStore(Chain, getCurDebugLoc(), 845 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 846 Add, NULL, Offsets[i], false, false, 0); 847 } 848 849 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 850 MVT::Other, &Chains[0], NumValues); 851 } else if (I.getNumOperands() != 0) { 852 SmallVector<EVT, 4> ValueVTs; 853 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 854 unsigned NumValues = ValueVTs.size(); 855 if (NumValues) { 856 SDValue RetOp = getValue(I.getOperand(0)); 857 for (unsigned j = 0, f = NumValues; j != f; ++j) { 858 EVT VT = ValueVTs[j]; 859 860 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 861 862 const Function *F = I.getParent()->getParent(); 863 if (F->paramHasAttr(0, Attribute::SExt)) 864 ExtendKind = ISD::SIGN_EXTEND; 865 else if (F->paramHasAttr(0, Attribute::ZExt)) 866 ExtendKind = ISD::ZERO_EXTEND; 867 868 // FIXME: C calling convention requires the return type to be promoted 869 // to at least 32-bit. But this is not necessary for non-C calling 870 // conventions. The frontend should mark functions whose return values 871 // require promoting with signext or zeroext attributes. 872 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 873 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32); 874 if (VT.bitsLT(MinVT)) 875 VT = MinVT; 876 } 877 878 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 879 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 880 SmallVector<SDValue, 4> Parts(NumParts); 881 getCopyToParts(DAG, getCurDebugLoc(), 882 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 883 &Parts[0], NumParts, PartVT, ExtendKind); 884 885 // 'inreg' on function refers to return value 886 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 887 if (F->paramHasAttr(0, Attribute::InReg)) 888 Flags.setInReg(); 889 890 // Propagate extension type if any 891 if (F->paramHasAttr(0, Attribute::SExt)) 892 Flags.setSExt(); 893 else if (F->paramHasAttr(0, Attribute::ZExt)) 894 Flags.setZExt(); 895 896 for (unsigned i = 0; i < NumParts; ++i) 897 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true)); 898 } 899 } 900 } 901 902 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 903 CallingConv::ID CallConv = 904 DAG.getMachineFunction().getFunction()->getCallingConv(); 905 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 906 Outs, getCurDebugLoc(), DAG); 907 908 // Verify that the target's LowerReturn behaved as expected. 909 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 910 "LowerReturn didn't return a valid chain!"); 911 912 // Update the DAG with the new chain value resulting from return lowering. 913 DAG.setRoot(Chain); 914} 915 916/// CopyToExportRegsIfNeeded - If the given value has virtual registers 917/// created for it, emit nodes to copy the value into the virtual 918/// registers. 919void SelectionDAGBuilder::CopyToExportRegsIfNeeded(Value *V) { 920 if (!V->use_empty()) { 921 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 922 if (VMI != FuncInfo.ValueMap.end()) 923 CopyValueToVirtualRegister(V, VMI->second); 924 } 925} 926 927/// ExportFromCurrentBlock - If this condition isn't known to be exported from 928/// the current basic block, add it to ValueMap now so that we'll get a 929/// CopyTo/FromReg. 930void SelectionDAGBuilder::ExportFromCurrentBlock(Value *V) { 931 // No need to export constants. 932 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 933 934 // Already exported? 935 if (FuncInfo.isExportedInst(V)) return; 936 937 unsigned Reg = FuncInfo.InitializeRegForValue(V); 938 CopyValueToVirtualRegister(V, Reg); 939} 940 941bool SelectionDAGBuilder::isExportableFromCurrentBlock(Value *V, 942 const BasicBlock *FromBB) { 943 // The operands of the setcc have to be in this block. We don't know 944 // how to export them from some other block. 945 if (Instruction *VI = dyn_cast<Instruction>(V)) { 946 // Can export from current BB. 947 if (VI->getParent() == FromBB) 948 return true; 949 950 // Is already exported, noop. 951 return FuncInfo.isExportedInst(V); 952 } 953 954 // If this is an argument, we can export it if the BB is the entry block or 955 // if it is already exported. 956 if (isa<Argument>(V)) { 957 if (FromBB == &FromBB->getParent()->getEntryBlock()) 958 return true; 959 960 // Otherwise, can only export this if it is already exported. 961 return FuncInfo.isExportedInst(V); 962 } 963 964 // Otherwise, constants can always be exported. 965 return true; 966} 967 968static bool InBlock(const Value *V, const BasicBlock *BB) { 969 if (const Instruction *I = dyn_cast<Instruction>(V)) 970 return I->getParent() == BB; 971 return true; 972} 973 974/// getFCmpCondCode - Return the ISD condition code corresponding to 975/// the given LLVM IR floating-point condition code. This includes 976/// consideration of global floating-point math flags. 977/// 978static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) { 979 ISD::CondCode FPC, FOC; 980 switch (Pred) { 981 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 982 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 983 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 984 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 985 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 986 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 987 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 988 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 989 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 990 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 991 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 992 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 993 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 994 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 995 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 996 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 997 default: 998 llvm_unreachable("Invalid FCmp predicate opcode!"); 999 FOC = FPC = ISD::SETFALSE; 1000 break; 1001 } 1002 if (FiniteOnlyFPMath()) 1003 return FOC; 1004 else 1005 return FPC; 1006} 1007 1008/// getICmpCondCode - Return the ISD condition code corresponding to 1009/// the given LLVM IR integer condition code. 1010/// 1011static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) { 1012 switch (Pred) { 1013 case ICmpInst::ICMP_EQ: return ISD::SETEQ; 1014 case ICmpInst::ICMP_NE: return ISD::SETNE; 1015 case ICmpInst::ICMP_SLE: return ISD::SETLE; 1016 case ICmpInst::ICMP_ULE: return ISD::SETULE; 1017 case ICmpInst::ICMP_SGE: return ISD::SETGE; 1018 case ICmpInst::ICMP_UGE: return ISD::SETUGE; 1019 case ICmpInst::ICMP_SLT: return ISD::SETLT; 1020 case ICmpInst::ICMP_ULT: return ISD::SETULT; 1021 case ICmpInst::ICMP_SGT: return ISD::SETGT; 1022 case ICmpInst::ICMP_UGT: return ISD::SETUGT; 1023 default: 1024 llvm_unreachable("Invalid ICmp predicate opcode!"); 1025 return ISD::SETNE; 1026 } 1027} 1028 1029/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1030/// This function emits a branch and is used at the leaves of an OR or an 1031/// AND operator tree. 1032/// 1033void 1034SelectionDAGBuilder::EmitBranchForMergedCondition(Value *Cond, 1035 MachineBasicBlock *TBB, 1036 MachineBasicBlock *FBB, 1037 MachineBasicBlock *CurBB) { 1038 const BasicBlock *BB = CurBB->getBasicBlock(); 1039 1040 // If the leaf of the tree is a comparison, merge the condition into 1041 // the caseblock. 1042 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1043 // The operands of the cmp have to be in this block. We don't know 1044 // how to export them from some other block. If this is the first block 1045 // of the sequence, no exporting is needed. 1046 if (CurBB == CurMBB || 1047 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1048 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1049 ISD::CondCode Condition; 1050 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1051 Condition = getICmpCondCode(IC->getPredicate()); 1052 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1053 Condition = getFCmpCondCode(FC->getPredicate()); 1054 } else { 1055 Condition = ISD::SETEQ; // silence warning. 1056 llvm_unreachable("Unknown compare instruction"); 1057 } 1058 1059 CaseBlock CB(Condition, BOp->getOperand(0), 1060 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1061 SwitchCases.push_back(CB); 1062 return; 1063 } 1064 } 1065 1066 // Create a CaseBlock record representing this branch. 1067 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1068 NULL, TBB, FBB, CurBB); 1069 SwitchCases.push_back(CB); 1070} 1071 1072/// FindMergedConditions - If Cond is an expression like 1073void SelectionDAGBuilder::FindMergedConditions(Value *Cond, 1074 MachineBasicBlock *TBB, 1075 MachineBasicBlock *FBB, 1076 MachineBasicBlock *CurBB, 1077 unsigned Opc) { 1078 // If this node is not part of the or/and tree, emit it as a branch. 1079 Instruction *BOp = dyn_cast<Instruction>(Cond); 1080 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1081 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1082 BOp->getParent() != CurBB->getBasicBlock() || 1083 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1084 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1085 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB); 1086 return; 1087 } 1088 1089 // Create TmpBB after CurBB. 1090 MachineFunction::iterator BBI = CurBB; 1091 MachineFunction &MF = DAG.getMachineFunction(); 1092 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1093 CurBB->getParent()->insert(++BBI, TmpBB); 1094 1095 if (Opc == Instruction::Or) { 1096 // Codegen X | Y as: 1097 // jmp_if_X TBB 1098 // jmp TmpBB 1099 // TmpBB: 1100 // jmp_if_Y TBB 1101 // jmp FBB 1102 // 1103 1104 // Emit the LHS condition. 1105 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1106 1107 // Emit the RHS condition into TmpBB. 1108 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1109 } else { 1110 assert(Opc == Instruction::And && "Unknown merge op!"); 1111 // Codegen X & Y as: 1112 // jmp_if_X TmpBB 1113 // jmp FBB 1114 // TmpBB: 1115 // jmp_if_Y TBB 1116 // jmp FBB 1117 // 1118 // This requires creation of TmpBB after CurBB. 1119 1120 // Emit the LHS condition. 1121 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1122 1123 // Emit the RHS condition into TmpBB. 1124 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1125 } 1126} 1127 1128/// If the set of cases should be emitted as a series of branches, return true. 1129/// If we should emit this as a bunch of and/or'd together conditions, return 1130/// false. 1131bool 1132SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1133 if (Cases.size() != 2) return true; 1134 1135 // If this is two comparisons of the same values or'd or and'd together, they 1136 // will get folded into a single comparison, so don't emit two blocks. 1137 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1138 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1139 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1140 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1141 return false; 1142 } 1143 1144 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1145 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1146 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1147 Cases[0].CC == Cases[1].CC && 1148 isa<Constant>(Cases[0].CmpRHS) && 1149 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1150 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1151 return false; 1152 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1153 return false; 1154 } 1155 1156 return true; 1157} 1158 1159void SelectionDAGBuilder::visitBr(BranchInst &I) { 1160 // Update machine-CFG edges. 1161 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1162 1163 // Figure out which block is immediately after the current one. 1164 MachineBasicBlock *NextBlock = 0; 1165 MachineFunction::iterator BBI = CurMBB; 1166 if (++BBI != FuncInfo.MF->end()) 1167 NextBlock = BBI; 1168 1169 if (I.isUnconditional()) { 1170 // Update machine-CFG edges. 1171 CurMBB->addSuccessor(Succ0MBB); 1172 1173 // If this is not a fall-through branch, emit the branch. 1174 if (Succ0MBB != NextBlock) 1175 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1176 MVT::Other, getControlRoot(), 1177 DAG.getBasicBlock(Succ0MBB))); 1178 1179 return; 1180 } 1181 1182 // If this condition is one of the special cases we handle, do special stuff 1183 // now. 1184 Value *CondVal = I.getCondition(); 1185 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1186 1187 // If this is a series of conditions that are or'd or and'd together, emit 1188 // this as a sequence of branches instead of setcc's with and/or operations. 1189 // For example, instead of something like: 1190 // cmp A, B 1191 // C = seteq 1192 // cmp D, E 1193 // F = setle 1194 // or C, F 1195 // jnz foo 1196 // Emit: 1197 // cmp A, B 1198 // je foo 1199 // cmp D, E 1200 // jle foo 1201 // 1202 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1203 if (BOp->hasOneUse() && 1204 (BOp->getOpcode() == Instruction::And || 1205 BOp->getOpcode() == Instruction::Or)) { 1206 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1207 // If the compares in later blocks need to use values not currently 1208 // exported from this block, export them now. This block should always 1209 // be the first entry. 1210 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1211 1212 // Allow some cases to be rejected. 1213 if (ShouldEmitAsBranches(SwitchCases)) { 1214 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1215 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1216 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1217 } 1218 1219 // Emit the branch for this block. 1220 visitSwitchCase(SwitchCases[0]); 1221 SwitchCases.erase(SwitchCases.begin()); 1222 return; 1223 } 1224 1225 // Okay, we decided not to do this, remove any inserted MBB's and clear 1226 // SwitchCases. 1227 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1228 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1229 1230 SwitchCases.clear(); 1231 } 1232 } 1233 1234 // Create a CaseBlock record representing this branch. 1235 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1236 NULL, Succ0MBB, Succ1MBB, CurMBB); 1237 1238 // Use visitSwitchCase to actually insert the fast branch sequence for this 1239 // cond branch. 1240 visitSwitchCase(CB); 1241} 1242 1243/// visitSwitchCase - Emits the necessary code to represent a single node in 1244/// the binary search tree resulting from lowering a switch instruction. 1245void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) { 1246 SDValue Cond; 1247 SDValue CondLHS = getValue(CB.CmpLHS); 1248 DebugLoc dl = getCurDebugLoc(); 1249 1250 // Build the setcc now. 1251 if (CB.CmpMHS == NULL) { 1252 // Fold "(X == true)" to X and "(X == false)" to !X to 1253 // handle common cases produced by branch lowering. 1254 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1255 CB.CC == ISD::SETEQ) 1256 Cond = CondLHS; 1257 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1258 CB.CC == ISD::SETEQ) { 1259 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1260 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1261 } else 1262 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1263 } else { 1264 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1265 1266 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1267 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1268 1269 SDValue CmpOp = getValue(CB.CmpMHS); 1270 EVT VT = CmpOp.getValueType(); 1271 1272 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1273 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1274 ISD::SETLE); 1275 } else { 1276 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1277 VT, CmpOp, DAG.getConstant(Low, VT)); 1278 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1279 DAG.getConstant(High-Low, VT), ISD::SETULE); 1280 } 1281 } 1282 1283 // Update successor info 1284 CurMBB->addSuccessor(CB.TrueBB); 1285 CurMBB->addSuccessor(CB.FalseBB); 1286 1287 // Set NextBlock to be the MBB immediately after the current one, if any. 1288 // This is used to avoid emitting unnecessary branches to the next block. 1289 MachineBasicBlock *NextBlock = 0; 1290 MachineFunction::iterator BBI = CurMBB; 1291 if (++BBI != FuncInfo.MF->end()) 1292 NextBlock = BBI; 1293 1294 // If the lhs block is the next block, invert the condition so that we can 1295 // fall through to the lhs instead of the rhs block. 1296 if (CB.TrueBB == NextBlock) { 1297 std::swap(CB.TrueBB, CB.FalseBB); 1298 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1299 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1300 } 1301 1302 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1303 MVT::Other, getControlRoot(), Cond, 1304 DAG.getBasicBlock(CB.TrueBB)); 1305 1306 // If the branch was constant folded, fix up the CFG. 1307 if (BrCond.getOpcode() == ISD::BR) { 1308 CurMBB->removeSuccessor(CB.FalseBB); 1309 } else { 1310 // Otherwise, go ahead and insert the false branch. 1311 if (BrCond == getControlRoot()) 1312 CurMBB->removeSuccessor(CB.TrueBB); 1313 1314 if (CB.FalseBB != NextBlock) 1315 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1316 DAG.getBasicBlock(CB.FalseBB)); 1317 } 1318 1319 DAG.setRoot(BrCond); 1320} 1321 1322/// visitJumpTable - Emit JumpTable node in the current MBB 1323void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1324 // Emit the code for the jump table 1325 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1326 EVT PTy = TLI.getPointerTy(); 1327 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1328 JT.Reg, PTy); 1329 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1330 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1331 MVT::Other, Index.getValue(1), 1332 Table, Index); 1333 DAG.setRoot(BrJumpTable); 1334} 1335 1336/// visitJumpTableHeader - This function emits necessary code to produce index 1337/// in the JumpTable from switch case. 1338void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1339 JumpTableHeader &JTH) { 1340 // Subtract the lowest switch case value from the value being switched on and 1341 // conditional branch to default mbb if the result is greater than the 1342 // difference between smallest and largest cases. 1343 SDValue SwitchOp = getValue(JTH.SValue); 1344 EVT VT = SwitchOp.getValueType(); 1345 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1346 DAG.getConstant(JTH.First, VT)); 1347 1348 // The SDNode we just created, which holds the value being switched on minus 1349 // the smallest case value, needs to be copied to a virtual register so it 1350 // can be used as an index into the jump table in a subsequent basic block. 1351 // This value may be smaller or larger than the target's pointer type, and 1352 // therefore require extension or truncating. 1353 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1354 1355 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1356 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1357 JumpTableReg, SwitchOp); 1358 JT.Reg = JumpTableReg; 1359 1360 // Emit the range check for the jump table, and branch to the default block 1361 // for the switch statement if the value being switched on exceeds the largest 1362 // case in the switch. 1363 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1364 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1365 DAG.getConstant(JTH.Last-JTH.First,VT), 1366 ISD::SETUGT); 1367 1368 // Set NextBlock to be the MBB immediately after the current one, if any. 1369 // This is used to avoid emitting unnecessary branches to the next block. 1370 MachineBasicBlock *NextBlock = 0; 1371 MachineFunction::iterator BBI = CurMBB; 1372 1373 if (++BBI != FuncInfo.MF->end()) 1374 NextBlock = BBI; 1375 1376 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1377 MVT::Other, CopyTo, CMP, 1378 DAG.getBasicBlock(JT.Default)); 1379 1380 if (JT.MBB != NextBlock) 1381 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1382 DAG.getBasicBlock(JT.MBB)); 1383 1384 DAG.setRoot(BrCond); 1385} 1386 1387/// visitBitTestHeader - This function emits necessary code to produce value 1388/// suitable for "bit tests" 1389void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) { 1390 // Subtract the minimum value 1391 SDValue SwitchOp = getValue(B.SValue); 1392 EVT VT = SwitchOp.getValueType(); 1393 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1394 DAG.getConstant(B.First, VT)); 1395 1396 // Check range 1397 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1398 TLI.getSetCCResultType(Sub.getValueType()), 1399 Sub, DAG.getConstant(B.Range, VT), 1400 ISD::SETUGT); 1401 1402 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), 1403 TLI.getPointerTy()); 1404 1405 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy()); 1406 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1407 B.Reg, ShiftOp); 1408 1409 // Set NextBlock to be the MBB immediately after the current one, if any. 1410 // This is used to avoid emitting unnecessary branches to the next block. 1411 MachineBasicBlock *NextBlock = 0; 1412 MachineFunction::iterator BBI = CurMBB; 1413 if (++BBI != FuncInfo.MF->end()) 1414 NextBlock = BBI; 1415 1416 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1417 1418 CurMBB->addSuccessor(B.Default); 1419 CurMBB->addSuccessor(MBB); 1420 1421 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1422 MVT::Other, CopyTo, RangeCmp, 1423 DAG.getBasicBlock(B.Default)); 1424 1425 if (MBB != NextBlock) 1426 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1427 DAG.getBasicBlock(MBB)); 1428 1429 DAG.setRoot(BrRange); 1430} 1431 1432/// visitBitTestCase - this function produces one "bit test" 1433void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB, 1434 unsigned Reg, 1435 BitTestCase &B) { 1436 // Make desired shift 1437 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg, 1438 TLI.getPointerTy()); 1439 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), 1440 TLI.getPointerTy(), 1441 DAG.getConstant(1, TLI.getPointerTy()), 1442 ShiftOp); 1443 1444 // Emit bit tests and jumps 1445 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1446 TLI.getPointerTy(), SwitchVal, 1447 DAG.getConstant(B.Mask, TLI.getPointerTy())); 1448 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(), 1449 TLI.getSetCCResultType(AndOp.getValueType()), 1450 AndOp, DAG.getConstant(0, TLI.getPointerTy()), 1451 ISD::SETNE); 1452 1453 CurMBB->addSuccessor(B.TargetBB); 1454 CurMBB->addSuccessor(NextMBB); 1455 1456 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1457 MVT::Other, getControlRoot(), 1458 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1459 1460 // Set NextBlock to be the MBB immediately after the current one, if any. 1461 // This is used to avoid emitting unnecessary branches to the next block. 1462 MachineBasicBlock *NextBlock = 0; 1463 MachineFunction::iterator BBI = CurMBB; 1464 if (++BBI != FuncInfo.MF->end()) 1465 NextBlock = BBI; 1466 1467 if (NextMBB != NextBlock) 1468 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1469 DAG.getBasicBlock(NextMBB)); 1470 1471 DAG.setRoot(BrAnd); 1472} 1473 1474void SelectionDAGBuilder::visitInvoke(InvokeInst &I) { 1475 // Retrieve successors. 1476 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1477 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1478 1479 const Value *Callee(I.getCalledValue()); 1480 if (isa<InlineAsm>(Callee)) 1481 visitInlineAsm(&I); 1482 else 1483 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1484 1485 // If the value of the invoke is used outside of its defining block, make it 1486 // available as a virtual register. 1487 CopyToExportRegsIfNeeded(&I); 1488 1489 // Update successor info 1490 CurMBB->addSuccessor(Return); 1491 CurMBB->addSuccessor(LandingPad); 1492 1493 // Drop into normal successor. 1494 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1495 MVT::Other, getControlRoot(), 1496 DAG.getBasicBlock(Return))); 1497} 1498 1499void SelectionDAGBuilder::visitUnwind(UnwindInst &I) { 1500} 1501 1502/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1503/// small case ranges). 1504bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1505 CaseRecVector& WorkList, 1506 Value* SV, 1507 MachineBasicBlock* Default) { 1508 Case& BackCase = *(CR.Range.second-1); 1509 1510 // Size is the number of Cases represented by this range. 1511 size_t Size = CR.Range.second - CR.Range.first; 1512 if (Size > 3) 1513 return false; 1514 1515 // Get the MachineFunction which holds the current MBB. This is used when 1516 // inserting any additional MBBs necessary to represent the switch. 1517 MachineFunction *CurMF = FuncInfo.MF; 1518 1519 // Figure out which block is immediately after the current one. 1520 MachineBasicBlock *NextBlock = 0; 1521 MachineFunction::iterator BBI = CR.CaseBB; 1522 1523 if (++BBI != FuncInfo.MF->end()) 1524 NextBlock = BBI; 1525 1526 // TODO: If any two of the cases has the same destination, and if one value 1527 // is the same as the other, but has one bit unset that the other has set, 1528 // use bit manipulation to do two compares at once. For example: 1529 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1530 1531 // Rearrange the case blocks so that the last one falls through if possible. 1532 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1533 // The last case block won't fall through into 'NextBlock' if we emit the 1534 // branches in this order. See if rearranging a case value would help. 1535 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1536 if (I->BB == NextBlock) { 1537 std::swap(*I, BackCase); 1538 break; 1539 } 1540 } 1541 } 1542 1543 // Create a CaseBlock record representing a conditional branch to 1544 // the Case's target mbb if the value being switched on SV is equal 1545 // to C. 1546 MachineBasicBlock *CurBlock = CR.CaseBB; 1547 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1548 MachineBasicBlock *FallThrough; 1549 if (I != E-1) { 1550 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1551 CurMF->insert(BBI, FallThrough); 1552 1553 // Put SV in a virtual register to make it available from the new blocks. 1554 ExportFromCurrentBlock(SV); 1555 } else { 1556 // If the last case doesn't match, go to the default block. 1557 FallThrough = Default; 1558 } 1559 1560 Value *RHS, *LHS, *MHS; 1561 ISD::CondCode CC; 1562 if (I->High == I->Low) { 1563 // This is just small small case range :) containing exactly 1 case 1564 CC = ISD::SETEQ; 1565 LHS = SV; RHS = I->High; MHS = NULL; 1566 } else { 1567 CC = ISD::SETLE; 1568 LHS = I->Low; MHS = SV; RHS = I->High; 1569 } 1570 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1571 1572 // If emitting the first comparison, just call visitSwitchCase to emit the 1573 // code into the current block. Otherwise, push the CaseBlock onto the 1574 // vector to be later processed by SDISel, and insert the node's MBB 1575 // before the next MBB. 1576 if (CurBlock == CurMBB) 1577 visitSwitchCase(CB); 1578 else 1579 SwitchCases.push_back(CB); 1580 1581 CurBlock = FallThrough; 1582 } 1583 1584 return true; 1585} 1586 1587static inline bool areJTsAllowed(const TargetLowering &TLI) { 1588 return !DisableJumpTables && 1589 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1590 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1591} 1592 1593static APInt ComputeRange(const APInt &First, const APInt &Last) { 1594 APInt LastExt(Last), FirstExt(First); 1595 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1596 LastExt.sext(BitWidth); FirstExt.sext(BitWidth); 1597 return (LastExt - FirstExt + 1ULL); 1598} 1599 1600/// handleJTSwitchCase - Emit jumptable for current switch case range 1601bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1602 CaseRecVector& WorkList, 1603 Value* SV, 1604 MachineBasicBlock* Default) { 1605 Case& FrontCase = *CR.Range.first; 1606 Case& BackCase = *(CR.Range.second-1); 1607 1608 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1609 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1610 1611 APInt TSize(First.getBitWidth(), 0); 1612 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1613 I!=E; ++I) 1614 TSize += I->size(); 1615 1616 if (!areJTsAllowed(TLI) || TSize.ult(APInt(First.getBitWidth(), 4))) 1617 return false; 1618 1619 APInt Range = ComputeRange(First, Last); 1620 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1621 if (Density < 0.4) 1622 return false; 1623 1624 DEBUG(dbgs() << "Lowering jump table\n" 1625 << "First entry: " << First << ". Last entry: " << Last << '\n' 1626 << "Range: " << Range 1627 << "Size: " << TSize << ". Density: " << Density << "\n\n"); 1628 1629 // Get the MachineFunction which holds the current MBB. This is used when 1630 // inserting any additional MBBs necessary to represent the switch. 1631 MachineFunction *CurMF = FuncInfo.MF; 1632 1633 // Figure out which block is immediately after the current one. 1634 MachineFunction::iterator BBI = CR.CaseBB; 1635 ++BBI; 1636 1637 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1638 1639 // Create a new basic block to hold the code for loading the address 1640 // of the jump table, and jumping to it. Update successor information; 1641 // we will either branch to the default case for the switch, or the jump 1642 // table. 1643 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1644 CurMF->insert(BBI, JumpTableBB); 1645 CR.CaseBB->addSuccessor(Default); 1646 CR.CaseBB->addSuccessor(JumpTableBB); 1647 1648 // Build a vector of destination BBs, corresponding to each target 1649 // of the jump table. If the value of the jump table slot corresponds to 1650 // a case statement, push the case's BB onto the vector, otherwise, push 1651 // the default BB. 1652 std::vector<MachineBasicBlock*> DestBBs; 1653 APInt TEI = First; 1654 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1655 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 1656 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 1657 1658 if (Low.sle(TEI) && TEI.sle(High)) { 1659 DestBBs.push_back(I->BB); 1660 if (TEI==High) 1661 ++I; 1662 } else { 1663 DestBBs.push_back(Default); 1664 } 1665 } 1666 1667 // Update successor info. Add one edge to each unique successor. 1668 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1669 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1670 E = DestBBs.end(); I != E; ++I) { 1671 if (!SuccsHandled[(*I)->getNumber()]) { 1672 SuccsHandled[(*I)->getNumber()] = true; 1673 JumpTableBB->addSuccessor(*I); 1674 } 1675 } 1676 1677 // Create a jump table index for this jump table, or return an existing 1678 // one. 1679 unsigned JTEncoding = TLI.getJumpTableEncoding(); 1680 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 1681 ->getJumpTableIndex(DestBBs); 1682 1683 // Set the jump table information so that we can codegen it as a second 1684 // MachineBasicBlock 1685 JumpTable JT(-1U, JTI, JumpTableBB, Default); 1686 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB)); 1687 if (CR.CaseBB == CurMBB) 1688 visitJumpTableHeader(JT, JTH); 1689 1690 JTCases.push_back(JumpTableBlock(JTH, JT)); 1691 1692 return true; 1693} 1694 1695/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1696/// 2 subtrees. 1697bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 1698 CaseRecVector& WorkList, 1699 Value* SV, 1700 MachineBasicBlock* Default) { 1701 // Get the MachineFunction which holds the current MBB. This is used when 1702 // inserting any additional MBBs necessary to represent the switch. 1703 MachineFunction *CurMF = FuncInfo.MF; 1704 1705 // Figure out which block is immediately after the current one. 1706 MachineFunction::iterator BBI = CR.CaseBB; 1707 ++BBI; 1708 1709 Case& FrontCase = *CR.Range.first; 1710 Case& BackCase = *(CR.Range.second-1); 1711 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1712 1713 // Size is the number of Cases represented by this range. 1714 unsigned Size = CR.Range.second - CR.Range.first; 1715 1716 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1717 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1718 double FMetric = 0; 1719 CaseItr Pivot = CR.Range.first + Size/2; 1720 1721 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1722 // (heuristically) allow us to emit JumpTable's later. 1723 APInt TSize(First.getBitWidth(), 0); 1724 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1725 I!=E; ++I) 1726 TSize += I->size(); 1727 1728 APInt LSize = FrontCase.size(); 1729 APInt RSize = TSize-LSize; 1730 DEBUG(dbgs() << "Selecting best pivot: \n" 1731 << "First: " << First << ", Last: " << Last <<'\n' 1732 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 1733 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1734 J!=E; ++I, ++J) { 1735 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 1736 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 1737 APInt Range = ComputeRange(LEnd, RBegin); 1738 assert((Range - 2ULL).isNonNegative() && 1739 "Invalid case distance"); 1740 double LDensity = (double)LSize.roundToDouble() / 1741 (LEnd - First + 1ULL).roundToDouble(); 1742 double RDensity = (double)RSize.roundToDouble() / 1743 (Last - RBegin + 1ULL).roundToDouble(); 1744 double Metric = Range.logBase2()*(LDensity+RDensity); 1745 // Should always split in some non-trivial place 1746 DEBUG(dbgs() <<"=>Step\n" 1747 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 1748 << "LDensity: " << LDensity 1749 << ", RDensity: " << RDensity << '\n' 1750 << "Metric: " << Metric << '\n'); 1751 if (FMetric < Metric) { 1752 Pivot = J; 1753 FMetric = Metric; 1754 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 1755 } 1756 1757 LSize += J->size(); 1758 RSize -= J->size(); 1759 } 1760 if (areJTsAllowed(TLI)) { 1761 // If our case is dense we *really* should handle it earlier! 1762 assert((FMetric > 0) && "Should handle dense range earlier!"); 1763 } else { 1764 Pivot = CR.Range.first + Size/2; 1765 } 1766 1767 CaseRange LHSR(CR.Range.first, Pivot); 1768 CaseRange RHSR(Pivot, CR.Range.second); 1769 Constant *C = Pivot->Low; 1770 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1771 1772 // We know that we branch to the LHS if the Value being switched on is 1773 // less than the Pivot value, C. We use this to optimize our binary 1774 // tree a bit, by recognizing that if SV is greater than or equal to the 1775 // LHS's Case Value, and that Case Value is exactly one less than the 1776 // Pivot's Value, then we can branch directly to the LHS's Target, 1777 // rather than creating a leaf node for it. 1778 if ((LHSR.second - LHSR.first) == 1 && 1779 LHSR.first->High == CR.GE && 1780 cast<ConstantInt>(C)->getValue() == 1781 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 1782 TrueBB = LHSR.first->BB; 1783 } else { 1784 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1785 CurMF->insert(BBI, TrueBB); 1786 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1787 1788 // Put SV in a virtual register to make it available from the new blocks. 1789 ExportFromCurrentBlock(SV); 1790 } 1791 1792 // Similar to the optimization above, if the Value being switched on is 1793 // known to be less than the Constant CR.LT, and the current Case Value 1794 // is CR.LT - 1, then we can branch directly to the target block for 1795 // the current Case Value, rather than emitting a RHS leaf node for it. 1796 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1797 cast<ConstantInt>(RHSR.first->Low)->getValue() == 1798 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 1799 FalseBB = RHSR.first->BB; 1800 } else { 1801 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1802 CurMF->insert(BBI, FalseBB); 1803 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1804 1805 // Put SV in a virtual register to make it available from the new blocks. 1806 ExportFromCurrentBlock(SV); 1807 } 1808 1809 // Create a CaseBlock record representing a conditional branch to 1810 // the LHS node if the value being switched on SV is less than C. 1811 // Otherwise, branch to LHS. 1812 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 1813 1814 if (CR.CaseBB == CurMBB) 1815 visitSwitchCase(CB); 1816 else 1817 SwitchCases.push_back(CB); 1818 1819 return true; 1820} 1821 1822/// handleBitTestsSwitchCase - if current case range has few destination and 1823/// range span less, than machine word bitwidth, encode case range into series 1824/// of masks and emit bit tests with these masks. 1825bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 1826 CaseRecVector& WorkList, 1827 Value* SV, 1828 MachineBasicBlock* Default){ 1829 EVT PTy = TLI.getPointerTy(); 1830 unsigned IntPtrBits = PTy.getSizeInBits(); 1831 1832 Case& FrontCase = *CR.Range.first; 1833 Case& BackCase = *(CR.Range.second-1); 1834 1835 // Get the MachineFunction which holds the current MBB. This is used when 1836 // inserting any additional MBBs necessary to represent the switch. 1837 MachineFunction *CurMF = FuncInfo.MF; 1838 1839 // If target does not have legal shift left, do not emit bit tests at all. 1840 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 1841 return false; 1842 1843 size_t numCmps = 0; 1844 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1845 I!=E; ++I) { 1846 // Single case counts one, case range - two. 1847 numCmps += (I->Low == I->High ? 1 : 2); 1848 } 1849 1850 // Count unique destinations 1851 SmallSet<MachineBasicBlock*, 4> Dests; 1852 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1853 Dests.insert(I->BB); 1854 if (Dests.size() > 3) 1855 // Don't bother the code below, if there are too much unique destinations 1856 return false; 1857 } 1858 DEBUG(dbgs() << "Total number of unique destinations: " 1859 << Dests.size() << '\n' 1860 << "Total number of comparisons: " << numCmps << '\n'); 1861 1862 // Compute span of values. 1863 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 1864 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 1865 APInt cmpRange = maxValue - minValue; 1866 1867 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 1868 << "Low bound: " << minValue << '\n' 1869 << "High bound: " << maxValue << '\n'); 1870 1871 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) || 1872 (!(Dests.size() == 1 && numCmps >= 3) && 1873 !(Dests.size() == 2 && numCmps >= 5) && 1874 !(Dests.size() >= 3 && numCmps >= 6))) 1875 return false; 1876 1877 DEBUG(dbgs() << "Emitting bit tests\n"); 1878 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 1879 1880 // Optimize the case where all the case values fit in a 1881 // word without having to subtract minValue. In this case, 1882 // we can optimize away the subtraction. 1883 if (minValue.isNonNegative() && 1884 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) { 1885 cmpRange = maxValue; 1886 } else { 1887 lowBound = minValue; 1888 } 1889 1890 CaseBitsVector CasesBits; 1891 unsigned i, count = 0; 1892 1893 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1894 MachineBasicBlock* Dest = I->BB; 1895 for (i = 0; i < count; ++i) 1896 if (Dest == CasesBits[i].BB) 1897 break; 1898 1899 if (i == count) { 1900 assert((count < 3) && "Too much destinations to test!"); 1901 CasesBits.push_back(CaseBits(0, Dest, 0)); 1902 count++; 1903 } 1904 1905 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 1906 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 1907 1908 uint64_t lo = (lowValue - lowBound).getZExtValue(); 1909 uint64_t hi = (highValue - lowBound).getZExtValue(); 1910 1911 for (uint64_t j = lo; j <= hi; j++) { 1912 CasesBits[i].Mask |= 1ULL << j; 1913 CasesBits[i].Bits++; 1914 } 1915 1916 } 1917 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1918 1919 BitTestInfo BTC; 1920 1921 // Figure out which block is immediately after the current one. 1922 MachineFunction::iterator BBI = CR.CaseBB; 1923 ++BBI; 1924 1925 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1926 1927 DEBUG(dbgs() << "Cases:\n"); 1928 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1929 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 1930 << ", Bits: " << CasesBits[i].Bits 1931 << ", BB: " << CasesBits[i].BB << '\n'); 1932 1933 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1934 CurMF->insert(BBI, CaseBB); 1935 BTC.push_back(BitTestCase(CasesBits[i].Mask, 1936 CaseBB, 1937 CasesBits[i].BB)); 1938 1939 // Put SV in a virtual register to make it available from the new blocks. 1940 ExportFromCurrentBlock(SV); 1941 } 1942 1943 BitTestBlock BTB(lowBound, cmpRange, SV, 1944 -1U, (CR.CaseBB == CurMBB), 1945 CR.CaseBB, Default, BTC); 1946 1947 if (CR.CaseBB == CurMBB) 1948 visitBitTestHeader(BTB); 1949 1950 BitTestCases.push_back(BTB); 1951 1952 return true; 1953} 1954 1955/// Clusterify - Transform simple list of Cases into list of CaseRange's 1956size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 1957 const SwitchInst& SI) { 1958 size_t numCmps = 0; 1959 1960 // Start with "simple" cases 1961 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 1962 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1963 Cases.push_back(Case(SI.getSuccessorValue(i), 1964 SI.getSuccessorValue(i), 1965 SMBB)); 1966 } 1967 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 1968 1969 // Merge case into clusters 1970 if (Cases.size() >= 2) 1971 // Must recompute end() each iteration because it may be 1972 // invalidated by erase if we hold on to it 1973 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) { 1974 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 1975 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 1976 MachineBasicBlock* nextBB = J->BB; 1977 MachineBasicBlock* currentBB = I->BB; 1978 1979 // If the two neighboring cases go to the same destination, merge them 1980 // into a single case. 1981 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 1982 I->High = J->High; 1983 J = Cases.erase(J); 1984 } else { 1985 I = J++; 1986 } 1987 } 1988 1989 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1990 if (I->Low != I->High) 1991 // A range counts double, since it requires two compares. 1992 ++numCmps; 1993 } 1994 1995 return numCmps; 1996} 1997 1998void SelectionDAGBuilder::visitSwitch(SwitchInst &SI) { 1999 // Figure out which block is immediately after the current one. 2000 MachineBasicBlock *NextBlock = 0; 2001 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2002 2003 // If there is only the default destination, branch to it if it is not the 2004 // next basic block. Otherwise, just fall through. 2005 if (SI.getNumOperands() == 2) { 2006 // Update machine-CFG edges. 2007 2008 // If this is not a fall-through branch, emit the branch. 2009 CurMBB->addSuccessor(Default); 2010 if (Default != NextBlock) 2011 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2012 MVT::Other, getControlRoot(), 2013 DAG.getBasicBlock(Default))); 2014 2015 return; 2016 } 2017 2018 // If there are any non-default case statements, create a vector of Cases 2019 // representing each one, and sort the vector so that we can efficiently 2020 // create a binary search tree from them. 2021 CaseVector Cases; 2022 size_t numCmps = Clusterify(Cases, SI); 2023 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2024 << ". Total compares: " << numCmps << '\n'); 2025 numCmps = 0; 2026 2027 // Get the Value to be switched on and default basic blocks, which will be 2028 // inserted into CaseBlock records, representing basic blocks in the binary 2029 // search tree. 2030 Value *SV = SI.getOperand(0); 2031 2032 // Push the initial CaseRec onto the worklist 2033 CaseRecVector WorkList; 2034 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 2035 2036 while (!WorkList.empty()) { 2037 // Grab a record representing a case range to process off the worklist 2038 CaseRec CR = WorkList.back(); 2039 WorkList.pop_back(); 2040 2041 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 2042 continue; 2043 2044 // If the range has few cases (two or less) emit a series of specific 2045 // tests. 2046 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 2047 continue; 2048 2049 // If the switch has more than 5 blocks, and at least 40% dense, and the 2050 // target supports indirect branches, then emit a jump table rather than 2051 // lowering the switch to a binary tree of conditional branches. 2052 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 2053 continue; 2054 2055 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2056 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2057 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 2058 } 2059} 2060 2061void SelectionDAGBuilder::visitIndirectBr(IndirectBrInst &I) { 2062 // Update machine-CFG edges with unique successors. 2063 SmallVector<BasicBlock*, 32> succs; 2064 succs.reserve(I.getNumSuccessors()); 2065 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2066 succs.push_back(I.getSuccessor(i)); 2067 array_pod_sort(succs.begin(), succs.end()); 2068 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2069 for (unsigned i = 0, e = succs.size(); i != e; ++i) 2070 CurMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]); 2071 2072 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2073 MVT::Other, getControlRoot(), 2074 getValue(I.getAddress()))); 2075} 2076 2077void SelectionDAGBuilder::visitFSub(User &I) { 2078 // -0.0 - X --> fneg 2079 const Type *Ty = I.getType(); 2080 if (Ty->isVectorTy()) { 2081 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2082 const VectorType *DestTy = cast<VectorType>(I.getType()); 2083 const Type *ElTy = DestTy->getElementType(); 2084 unsigned VL = DestTy->getNumElements(); 2085 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2086 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2087 if (CV == CNZ) { 2088 SDValue Op2 = getValue(I.getOperand(1)); 2089 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2090 Op2.getValueType(), Op2)); 2091 return; 2092 } 2093 } 2094 } 2095 2096 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2097 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2098 SDValue Op2 = getValue(I.getOperand(1)); 2099 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2100 Op2.getValueType(), Op2)); 2101 return; 2102 } 2103 2104 visitBinary(I, ISD::FSUB); 2105} 2106 2107void SelectionDAGBuilder::visitBinary(User &I, unsigned OpCode) { 2108 SDValue Op1 = getValue(I.getOperand(0)); 2109 SDValue Op2 = getValue(I.getOperand(1)); 2110 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2111 Op1.getValueType(), Op1, Op2)); 2112} 2113 2114void SelectionDAGBuilder::visitShift(User &I, unsigned Opcode) { 2115 SDValue Op1 = getValue(I.getOperand(0)); 2116 SDValue Op2 = getValue(I.getOperand(1)); 2117 if (!I.getType()->isVectorTy() && 2118 Op2.getValueType() != TLI.getShiftAmountTy()) { 2119 // If the operand is smaller than the shift count type, promote it. 2120 EVT PTy = TLI.getPointerTy(); 2121 EVT STy = TLI.getShiftAmountTy(); 2122 if (STy.bitsGT(Op2.getValueType())) 2123 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2124 TLI.getShiftAmountTy(), Op2); 2125 // If the operand is larger than the shift count type but the shift 2126 // count type has enough bits to represent any shift value, truncate 2127 // it now. This is a common case and it exposes the truncate to 2128 // optimization early. 2129 else if (STy.getSizeInBits() >= 2130 Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2131 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2132 TLI.getShiftAmountTy(), Op2); 2133 // Otherwise we'll need to temporarily settle for some other 2134 // convenient type; type legalization will make adjustments as 2135 // needed. 2136 else if (PTy.bitsLT(Op2.getValueType())) 2137 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2138 TLI.getPointerTy(), Op2); 2139 else if (PTy.bitsGT(Op2.getValueType())) 2140 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2141 TLI.getPointerTy(), Op2); 2142 } 2143 2144 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2145 Op1.getValueType(), Op1, Op2)); 2146} 2147 2148void SelectionDAGBuilder::visitICmp(User &I) { 2149 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2150 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2151 predicate = IC->getPredicate(); 2152 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2153 predicate = ICmpInst::Predicate(IC->getPredicate()); 2154 SDValue Op1 = getValue(I.getOperand(0)); 2155 SDValue Op2 = getValue(I.getOperand(1)); 2156 ISD::CondCode Opcode = getICmpCondCode(predicate); 2157 2158 EVT DestVT = TLI.getValueType(I.getType()); 2159 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2160} 2161 2162void SelectionDAGBuilder::visitFCmp(User &I) { 2163 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2164 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2165 predicate = FC->getPredicate(); 2166 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2167 predicate = FCmpInst::Predicate(FC->getPredicate()); 2168 SDValue Op1 = getValue(I.getOperand(0)); 2169 SDValue Op2 = getValue(I.getOperand(1)); 2170 ISD::CondCode Condition = getFCmpCondCode(predicate); 2171 EVT DestVT = TLI.getValueType(I.getType()); 2172 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2173} 2174 2175void SelectionDAGBuilder::visitSelect(User &I) { 2176 SmallVector<EVT, 4> ValueVTs; 2177 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2178 unsigned NumValues = ValueVTs.size(); 2179 if (NumValues == 0) return; 2180 2181 SmallVector<SDValue, 4> Values(NumValues); 2182 SDValue Cond = getValue(I.getOperand(0)); 2183 SDValue TrueVal = getValue(I.getOperand(1)); 2184 SDValue FalseVal = getValue(I.getOperand(2)); 2185 2186 for (unsigned i = 0; i != NumValues; ++i) 2187 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2188 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2189 Cond, 2190 SDValue(TrueVal.getNode(), 2191 TrueVal.getResNo() + i), 2192 SDValue(FalseVal.getNode(), 2193 FalseVal.getResNo() + i)); 2194 2195 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2196 DAG.getVTList(&ValueVTs[0], NumValues), 2197 &Values[0], NumValues)); 2198} 2199 2200void SelectionDAGBuilder::visitTrunc(User &I) { 2201 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2202 SDValue N = getValue(I.getOperand(0)); 2203 EVT DestVT = TLI.getValueType(I.getType()); 2204 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2205} 2206 2207void SelectionDAGBuilder::visitZExt(User &I) { 2208 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2209 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2210 SDValue N = getValue(I.getOperand(0)); 2211 EVT DestVT = TLI.getValueType(I.getType()); 2212 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2213} 2214 2215void SelectionDAGBuilder::visitSExt(User &I) { 2216 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2217 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2218 SDValue N = getValue(I.getOperand(0)); 2219 EVT DestVT = TLI.getValueType(I.getType()); 2220 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2221} 2222 2223void SelectionDAGBuilder::visitFPTrunc(User &I) { 2224 // FPTrunc is never a no-op cast, no need to check 2225 SDValue N = getValue(I.getOperand(0)); 2226 EVT DestVT = TLI.getValueType(I.getType()); 2227 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2228 DestVT, N, DAG.getIntPtrConstant(0))); 2229} 2230 2231void SelectionDAGBuilder::visitFPExt(User &I){ 2232 // FPTrunc is never a no-op cast, no need to check 2233 SDValue N = getValue(I.getOperand(0)); 2234 EVT DestVT = TLI.getValueType(I.getType()); 2235 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2236} 2237 2238void SelectionDAGBuilder::visitFPToUI(User &I) { 2239 // FPToUI is never a no-op cast, no need to check 2240 SDValue N = getValue(I.getOperand(0)); 2241 EVT DestVT = TLI.getValueType(I.getType()); 2242 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2243} 2244 2245void SelectionDAGBuilder::visitFPToSI(User &I) { 2246 // FPToSI is never a no-op cast, no need to check 2247 SDValue N = getValue(I.getOperand(0)); 2248 EVT DestVT = TLI.getValueType(I.getType()); 2249 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2250} 2251 2252void SelectionDAGBuilder::visitUIToFP(User &I) { 2253 // UIToFP is never a no-op cast, no need to check 2254 SDValue N = getValue(I.getOperand(0)); 2255 EVT DestVT = TLI.getValueType(I.getType()); 2256 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2257} 2258 2259void SelectionDAGBuilder::visitSIToFP(User &I){ 2260 // SIToFP is never a no-op cast, no need to check 2261 SDValue N = getValue(I.getOperand(0)); 2262 EVT DestVT = TLI.getValueType(I.getType()); 2263 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2264} 2265 2266void SelectionDAGBuilder::visitPtrToInt(User &I) { 2267 // What to do depends on the size of the integer and the size of the pointer. 2268 // We can either truncate, zero extend, or no-op, accordingly. 2269 SDValue N = getValue(I.getOperand(0)); 2270 EVT SrcVT = N.getValueType(); 2271 EVT DestVT = TLI.getValueType(I.getType()); 2272 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2273} 2274 2275void SelectionDAGBuilder::visitIntToPtr(User &I) { 2276 // What to do depends on the size of the integer and the size of the pointer. 2277 // We can either truncate, zero extend, or no-op, accordingly. 2278 SDValue N = getValue(I.getOperand(0)); 2279 EVT SrcVT = N.getValueType(); 2280 EVT DestVT = TLI.getValueType(I.getType()); 2281 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2282} 2283 2284void SelectionDAGBuilder::visitBitCast(User &I) { 2285 SDValue N = getValue(I.getOperand(0)); 2286 EVT DestVT = TLI.getValueType(I.getType()); 2287 2288 // BitCast assures us that source and destination are the same size so this is 2289 // either a BIT_CONVERT or a no-op. 2290 if (DestVT != N.getValueType()) 2291 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 2292 DestVT, N)); // convert types. 2293 else 2294 setValue(&I, N); // noop cast. 2295} 2296 2297void SelectionDAGBuilder::visitInsertElement(User &I) { 2298 SDValue InVec = getValue(I.getOperand(0)); 2299 SDValue InVal = getValue(I.getOperand(1)); 2300 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2301 TLI.getPointerTy(), 2302 getValue(I.getOperand(2))); 2303 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2304 TLI.getValueType(I.getType()), 2305 InVec, InVal, InIdx)); 2306} 2307 2308void SelectionDAGBuilder::visitExtractElement(User &I) { 2309 SDValue InVec = getValue(I.getOperand(0)); 2310 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2311 TLI.getPointerTy(), 2312 getValue(I.getOperand(1))); 2313 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2314 TLI.getValueType(I.getType()), InVec, InIdx)); 2315} 2316 2317// Utility for visitShuffleVector - Returns true if the mask is mask starting 2318// from SIndx and increasing to the element length (undefs are allowed). 2319static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2320 unsigned MaskNumElts = Mask.size(); 2321 for (unsigned i = 0; i != MaskNumElts; ++i) 2322 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2323 return false; 2324 return true; 2325} 2326 2327void SelectionDAGBuilder::visitShuffleVector(User &I) { 2328 SmallVector<int, 8> Mask; 2329 SDValue Src1 = getValue(I.getOperand(0)); 2330 SDValue Src2 = getValue(I.getOperand(1)); 2331 2332 // Convert the ConstantVector mask operand into an array of ints, with -1 2333 // representing undef values. 2334 SmallVector<Constant*, 8> MaskElts; 2335 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2336 unsigned MaskNumElts = MaskElts.size(); 2337 for (unsigned i = 0; i != MaskNumElts; ++i) { 2338 if (isa<UndefValue>(MaskElts[i])) 2339 Mask.push_back(-1); 2340 else 2341 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2342 } 2343 2344 EVT VT = TLI.getValueType(I.getType()); 2345 EVT SrcVT = Src1.getValueType(); 2346 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2347 2348 if (SrcNumElts == MaskNumElts) { 2349 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2350 &Mask[0])); 2351 return; 2352 } 2353 2354 // Normalize the shuffle vector since mask and vector length don't match. 2355 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2356 // Mask is longer than the source vectors and is a multiple of the source 2357 // vectors. We can use concatenate vector to make the mask and vectors 2358 // lengths match. 2359 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2360 // The shuffle is concatenating two vectors together. 2361 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2362 VT, Src1, Src2)); 2363 return; 2364 } 2365 2366 // Pad both vectors with undefs to make them the same length as the mask. 2367 unsigned NumConcat = MaskNumElts / SrcNumElts; 2368 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2369 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2370 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2371 2372 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2373 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2374 MOps1[0] = Src1; 2375 MOps2[0] = Src2; 2376 2377 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2378 getCurDebugLoc(), VT, 2379 &MOps1[0], NumConcat); 2380 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2381 getCurDebugLoc(), VT, 2382 &MOps2[0], NumConcat); 2383 2384 // Readjust mask for new input vector length. 2385 SmallVector<int, 8> MappedOps; 2386 for (unsigned i = 0; i != MaskNumElts; ++i) { 2387 int Idx = Mask[i]; 2388 if (Idx < (int)SrcNumElts) 2389 MappedOps.push_back(Idx); 2390 else 2391 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2392 } 2393 2394 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2395 &MappedOps[0])); 2396 return; 2397 } 2398 2399 if (SrcNumElts > MaskNumElts) { 2400 // Analyze the access pattern of the vector to see if we can extract 2401 // two subvectors and do the shuffle. The analysis is done by calculating 2402 // the range of elements the mask access on both vectors. 2403 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2404 int MaxRange[2] = {-1, -1}; 2405 2406 for (unsigned i = 0; i != MaskNumElts; ++i) { 2407 int Idx = Mask[i]; 2408 int Input = 0; 2409 if (Idx < 0) 2410 continue; 2411 2412 if (Idx >= (int)SrcNumElts) { 2413 Input = 1; 2414 Idx -= SrcNumElts; 2415 } 2416 if (Idx > MaxRange[Input]) 2417 MaxRange[Input] = Idx; 2418 if (Idx < MinRange[Input]) 2419 MinRange[Input] = Idx; 2420 } 2421 2422 // Check if the access is smaller than the vector size and can we find 2423 // a reasonable extract index. 2424 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2425 // Extract. 2426 int StartIdx[2]; // StartIdx to extract from 2427 for (int Input=0; Input < 2; ++Input) { 2428 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2429 RangeUse[Input] = 0; // Unused 2430 StartIdx[Input] = 0; 2431 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2432 // Fits within range but we should see if we can find a good 2433 // start index that is a multiple of the mask length. 2434 if (MaxRange[Input] < (int)MaskNumElts) { 2435 RangeUse[Input] = 1; // Extract from beginning of the vector 2436 StartIdx[Input] = 0; 2437 } else { 2438 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2439 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2440 StartIdx[Input] + MaskNumElts < SrcNumElts) 2441 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2442 } 2443 } 2444 } 2445 2446 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2447 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2448 return; 2449 } 2450 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2451 // Extract appropriate subvector and generate a vector shuffle 2452 for (int Input=0; Input < 2; ++Input) { 2453 SDValue &Src = Input == 0 ? Src1 : Src2; 2454 if (RangeUse[Input] == 0) 2455 Src = DAG.getUNDEF(VT); 2456 else 2457 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2458 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2459 } 2460 2461 // Calculate new mask. 2462 SmallVector<int, 8> MappedOps; 2463 for (unsigned i = 0; i != MaskNumElts; ++i) { 2464 int Idx = Mask[i]; 2465 if (Idx < 0) 2466 MappedOps.push_back(Idx); 2467 else if (Idx < (int)SrcNumElts) 2468 MappedOps.push_back(Idx - StartIdx[0]); 2469 else 2470 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2471 } 2472 2473 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2474 &MappedOps[0])); 2475 return; 2476 } 2477 } 2478 2479 // We can't use either concat vectors or extract subvectors so fall back to 2480 // replacing the shuffle with extract and build vector. 2481 // to insert and build vector. 2482 EVT EltVT = VT.getVectorElementType(); 2483 EVT PtrVT = TLI.getPointerTy(); 2484 SmallVector<SDValue,8> Ops; 2485 for (unsigned i = 0; i != MaskNumElts; ++i) { 2486 if (Mask[i] < 0) { 2487 Ops.push_back(DAG.getUNDEF(EltVT)); 2488 } else { 2489 int Idx = Mask[i]; 2490 SDValue Res; 2491 2492 if (Idx < (int)SrcNumElts) 2493 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2494 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2495 else 2496 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2497 EltVT, Src2, 2498 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2499 2500 Ops.push_back(Res); 2501 } 2502 } 2503 2504 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2505 VT, &Ops[0], Ops.size())); 2506} 2507 2508void SelectionDAGBuilder::visitInsertValue(InsertValueInst &I) { 2509 const Value *Op0 = I.getOperand(0); 2510 const Value *Op1 = I.getOperand(1); 2511 const Type *AggTy = I.getType(); 2512 const Type *ValTy = Op1->getType(); 2513 bool IntoUndef = isa<UndefValue>(Op0); 2514 bool FromUndef = isa<UndefValue>(Op1); 2515 2516 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2517 I.idx_begin(), I.idx_end()); 2518 2519 SmallVector<EVT, 4> AggValueVTs; 2520 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2521 SmallVector<EVT, 4> ValValueVTs; 2522 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2523 2524 unsigned NumAggValues = AggValueVTs.size(); 2525 unsigned NumValValues = ValValueVTs.size(); 2526 SmallVector<SDValue, 4> Values(NumAggValues); 2527 2528 SDValue Agg = getValue(Op0); 2529 SDValue Val = getValue(Op1); 2530 unsigned i = 0; 2531 // Copy the beginning value(s) from the original aggregate. 2532 for (; i != LinearIndex; ++i) 2533 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2534 SDValue(Agg.getNode(), Agg.getResNo() + i); 2535 // Copy values from the inserted value(s). 2536 for (; i != LinearIndex + NumValValues; ++i) 2537 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2538 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2539 // Copy remaining value(s) from the original aggregate. 2540 for (; i != NumAggValues; ++i) 2541 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2542 SDValue(Agg.getNode(), Agg.getResNo() + i); 2543 2544 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2545 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2546 &Values[0], NumAggValues)); 2547} 2548 2549void SelectionDAGBuilder::visitExtractValue(ExtractValueInst &I) { 2550 const Value *Op0 = I.getOperand(0); 2551 const Type *AggTy = Op0->getType(); 2552 const Type *ValTy = I.getType(); 2553 bool OutOfUndef = isa<UndefValue>(Op0); 2554 2555 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2556 I.idx_begin(), I.idx_end()); 2557 2558 SmallVector<EVT, 4> ValValueVTs; 2559 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2560 2561 unsigned NumValValues = ValValueVTs.size(); 2562 SmallVector<SDValue, 4> Values(NumValValues); 2563 2564 SDValue Agg = getValue(Op0); 2565 // Copy out the selected value(s). 2566 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2567 Values[i - LinearIndex] = 2568 OutOfUndef ? 2569 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2570 SDValue(Agg.getNode(), Agg.getResNo() + i); 2571 2572 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2573 DAG.getVTList(&ValValueVTs[0], NumValValues), 2574 &Values[0], NumValValues)); 2575} 2576 2577void SelectionDAGBuilder::visitGetElementPtr(User &I) { 2578 SDValue N = getValue(I.getOperand(0)); 2579 const Type *Ty = I.getOperand(0)->getType(); 2580 2581 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2582 OI != E; ++OI) { 2583 Value *Idx = *OI; 2584 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2585 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2586 if (Field) { 2587 // N = N + Offset 2588 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2589 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2590 DAG.getIntPtrConstant(Offset)); 2591 } 2592 2593 Ty = StTy->getElementType(Field); 2594 } else { 2595 Ty = cast<SequentialType>(Ty)->getElementType(); 2596 2597 // If this is a constant subscript, handle it quickly. 2598 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2599 if (CI->getZExtValue() == 0) continue; 2600 uint64_t Offs = 2601 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2602 SDValue OffsVal; 2603 EVT PTy = TLI.getPointerTy(); 2604 unsigned PtrBits = PTy.getSizeInBits(); 2605 if (PtrBits < 64) 2606 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2607 TLI.getPointerTy(), 2608 DAG.getConstant(Offs, MVT::i64)); 2609 else 2610 OffsVal = DAG.getIntPtrConstant(Offs); 2611 2612 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2613 OffsVal); 2614 continue; 2615 } 2616 2617 // N = N + Idx * ElementSize; 2618 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2619 TD->getTypeAllocSize(Ty)); 2620 SDValue IdxN = getValue(Idx); 2621 2622 // If the index is smaller or larger than intptr_t, truncate or extend 2623 // it. 2624 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2625 2626 // If this is a multiply by a power of two, turn it into a shl 2627 // immediately. This is a very common case. 2628 if (ElementSize != 1) { 2629 if (ElementSize.isPowerOf2()) { 2630 unsigned Amt = ElementSize.logBase2(); 2631 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2632 N.getValueType(), IdxN, 2633 DAG.getConstant(Amt, TLI.getPointerTy())); 2634 } else { 2635 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2636 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2637 N.getValueType(), IdxN, Scale); 2638 } 2639 } 2640 2641 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2642 N.getValueType(), N, IdxN); 2643 } 2644 } 2645 2646 setValue(&I, N); 2647} 2648 2649void SelectionDAGBuilder::visitAlloca(AllocaInst &I) { 2650 // If this is a fixed sized alloca in the entry block of the function, 2651 // allocate it statically on the stack. 2652 if (FuncInfo.StaticAllocaMap.count(&I)) 2653 return; // getValue will auto-populate this. 2654 2655 const Type *Ty = I.getAllocatedType(); 2656 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 2657 unsigned Align = 2658 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2659 I.getAlignment()); 2660 2661 SDValue AllocSize = getValue(I.getArraySize()); 2662 2663 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(), 2664 AllocSize, 2665 DAG.getConstant(TySize, AllocSize.getValueType())); 2666 2667 EVT IntPtr = TLI.getPointerTy(); 2668 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 2669 2670 // Handle alignment. If the requested alignment is less than or equal to 2671 // the stack alignment, ignore it. If the size is greater than or equal to 2672 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2673 unsigned StackAlign = 2674 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2675 if (Align <= StackAlign) 2676 Align = 0; 2677 2678 // Round the size of the allocation up to the stack alignment size 2679 // by add SA-1 to the size. 2680 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2681 AllocSize.getValueType(), AllocSize, 2682 DAG.getIntPtrConstant(StackAlign-1)); 2683 2684 // Mask out the low bits for alignment purposes. 2685 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 2686 AllocSize.getValueType(), AllocSize, 2687 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2688 2689 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2690 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 2691 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 2692 VTs, Ops, 3); 2693 setValue(&I, DSA); 2694 DAG.setRoot(DSA.getValue(1)); 2695 2696 // Inform the Frame Information that we have just allocated a variable-sized 2697 // object. 2698 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(); 2699} 2700 2701void SelectionDAGBuilder::visitLoad(LoadInst &I) { 2702 const Value *SV = I.getOperand(0); 2703 SDValue Ptr = getValue(SV); 2704 2705 const Type *Ty = I.getType(); 2706 2707 bool isVolatile = I.isVolatile(); 2708 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2709 unsigned Alignment = I.getAlignment(); 2710 2711 SmallVector<EVT, 4> ValueVTs; 2712 SmallVector<uint64_t, 4> Offsets; 2713 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2714 unsigned NumValues = ValueVTs.size(); 2715 if (NumValues == 0) 2716 return; 2717 2718 SDValue Root; 2719 bool ConstantMemory = false; 2720 if (I.isVolatile()) 2721 // Serialize volatile loads with other side effects. 2722 Root = getRoot(); 2723 else if (AA->pointsToConstantMemory(SV)) { 2724 // Do not serialize (non-volatile) loads of constant memory with anything. 2725 Root = DAG.getEntryNode(); 2726 ConstantMemory = true; 2727 } else { 2728 // Do not serialize non-volatile loads against each other. 2729 Root = DAG.getRoot(); 2730 } 2731 2732 SmallVector<SDValue, 4> Values(NumValues); 2733 SmallVector<SDValue, 4> Chains(NumValues); 2734 EVT PtrVT = Ptr.getValueType(); 2735 for (unsigned i = 0; i != NumValues; ++i) { 2736 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2737 PtrVT, Ptr, 2738 DAG.getConstant(Offsets[i], PtrVT)); 2739 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 2740 A, SV, Offsets[i], isVolatile, 2741 isNonTemporal, Alignment); 2742 2743 Values[i] = L; 2744 Chains[i] = L.getValue(1); 2745 } 2746 2747 if (!ConstantMemory) { 2748 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 2749 MVT::Other, &Chains[0], NumValues); 2750 if (isVolatile) 2751 DAG.setRoot(Chain); 2752 else 2753 PendingLoads.push_back(Chain); 2754 } 2755 2756 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2757 DAG.getVTList(&ValueVTs[0], NumValues), 2758 &Values[0], NumValues)); 2759} 2760 2761void SelectionDAGBuilder::visitStore(StoreInst &I) { 2762 Value *SrcV = I.getOperand(0); 2763 Value *PtrV = I.getOperand(1); 2764 2765 SmallVector<EVT, 4> ValueVTs; 2766 SmallVector<uint64_t, 4> Offsets; 2767 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 2768 unsigned NumValues = ValueVTs.size(); 2769 if (NumValues == 0) 2770 return; 2771 2772 // Get the lowered operands. Note that we do this after 2773 // checking if NumResults is zero, because with zero results 2774 // the operands won't have values in the map. 2775 SDValue Src = getValue(SrcV); 2776 SDValue Ptr = getValue(PtrV); 2777 2778 SDValue Root = getRoot(); 2779 SmallVector<SDValue, 4> Chains(NumValues); 2780 EVT PtrVT = Ptr.getValueType(); 2781 bool isVolatile = I.isVolatile(); 2782 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2783 unsigned Alignment = I.getAlignment(); 2784 2785 for (unsigned i = 0; i != NumValues; ++i) { 2786 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 2787 DAG.getConstant(Offsets[i], PtrVT)); 2788 Chains[i] = DAG.getStore(Root, getCurDebugLoc(), 2789 SDValue(Src.getNode(), Src.getResNo() + i), 2790 Add, PtrV, Offsets[i], isVolatile, 2791 isNonTemporal, Alignment); 2792 } 2793 2794 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 2795 MVT::Other, &Chains[0], NumValues)); 2796} 2797 2798/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2799/// node. 2800void SelectionDAGBuilder::visitTargetIntrinsic(CallInst &I, 2801 unsigned Intrinsic) { 2802 bool HasChain = !I.doesNotAccessMemory(); 2803 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 2804 2805 // Build the operand list. 2806 SmallVector<SDValue, 8> Ops; 2807 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2808 if (OnlyLoad) { 2809 // We don't need to serialize loads against other loads. 2810 Ops.push_back(DAG.getRoot()); 2811 } else { 2812 Ops.push_back(getRoot()); 2813 } 2814 } 2815 2816 // Info is set by getTgtMemInstrinsic 2817 TargetLowering::IntrinsicInfo Info; 2818 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 2819 2820 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 2821 if (!IsTgtIntrinsic) 2822 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2823 2824 // Add all operands of the call to the operand list. 2825 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2826 SDValue Op = getValue(I.getOperand(i)); 2827 assert(TLI.isTypeLegal(Op.getValueType()) && 2828 "Intrinsic uses a non-legal type?"); 2829 Ops.push_back(Op); 2830 } 2831 2832 SmallVector<EVT, 4> ValueVTs; 2833 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2834#ifndef NDEBUG 2835 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 2836 assert(TLI.isTypeLegal(ValueVTs[Val]) && 2837 "Intrinsic uses a non-legal type?"); 2838 } 2839#endif // NDEBUG 2840 2841 if (HasChain) 2842 ValueVTs.push_back(MVT::Other); 2843 2844 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 2845 2846 // Create the node. 2847 SDValue Result; 2848 if (IsTgtIntrinsic) { 2849 // This is target intrinsic that touches memory 2850 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 2851 VTs, &Ops[0], Ops.size(), 2852 Info.memVT, Info.ptrVal, Info.offset, 2853 Info.align, Info.vol, 2854 Info.readMem, Info.writeMem); 2855 } else if (!HasChain) { 2856 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 2857 VTs, &Ops[0], Ops.size()); 2858 } else if (!I.getType()->isVoidTy()) { 2859 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 2860 VTs, &Ops[0], Ops.size()); 2861 } else { 2862 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 2863 VTs, &Ops[0], Ops.size()); 2864 } 2865 2866 if (HasChain) { 2867 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 2868 if (OnlyLoad) 2869 PendingLoads.push_back(Chain); 2870 else 2871 DAG.setRoot(Chain); 2872 } 2873 2874 if (!I.getType()->isVoidTy()) { 2875 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2876 EVT VT = TLI.getValueType(PTy); 2877 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result); 2878 } 2879 2880 setValue(&I, Result); 2881 } 2882} 2883 2884/// GetSignificand - Get the significand and build it into a floating-point 2885/// number with exponent of 1: 2886/// 2887/// Op = (Op & 0x007fffff) | 0x3f800000; 2888/// 2889/// where Op is the hexidecimal representation of floating point value. 2890static SDValue 2891GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 2892 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 2893 DAG.getConstant(0x007fffff, MVT::i32)); 2894 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 2895 DAG.getConstant(0x3f800000, MVT::i32)); 2896 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2); 2897} 2898 2899/// GetExponent - Get the exponent: 2900/// 2901/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 2902/// 2903/// where Op is the hexidecimal representation of floating point value. 2904static SDValue 2905GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 2906 DebugLoc dl) { 2907 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 2908 DAG.getConstant(0x7f800000, MVT::i32)); 2909 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 2910 DAG.getConstant(23, TLI.getPointerTy())); 2911 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 2912 DAG.getConstant(127, MVT::i32)); 2913 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 2914} 2915 2916/// getF32Constant - Get 32-bit floating point constant. 2917static SDValue 2918getF32Constant(SelectionDAG &DAG, unsigned Flt) { 2919 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 2920} 2921 2922/// Inlined utility function to implement binary input atomic intrinsics for 2923/// visitIntrinsicCall: I is a call instruction 2924/// Op is the associated NodeType for I 2925const char * 2926SelectionDAGBuilder::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) { 2927 SDValue Root = getRoot(); 2928 SDValue L = 2929 DAG.getAtomic(Op, getCurDebugLoc(), 2930 getValue(I.getOperand(2)).getValueType().getSimpleVT(), 2931 Root, 2932 getValue(I.getOperand(1)), 2933 getValue(I.getOperand(2)), 2934 I.getOperand(1)); 2935 setValue(&I, L); 2936 DAG.setRoot(L.getValue(1)); 2937 return 0; 2938} 2939 2940// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 2941const char * 2942SelectionDAGBuilder::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) { 2943 SDValue Op1 = getValue(I.getOperand(1)); 2944 SDValue Op2 = getValue(I.getOperand(2)); 2945 2946 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 2947 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 2948 return 0; 2949} 2950 2951/// visitExp - Lower an exp intrinsic. Handles the special sequences for 2952/// limited-precision mode. 2953void 2954SelectionDAGBuilder::visitExp(CallInst &I) { 2955 SDValue result; 2956 DebugLoc dl = getCurDebugLoc(); 2957 2958 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 2959 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 2960 SDValue Op = getValue(I.getOperand(1)); 2961 2962 // Put the exponent in the right bit position for later addition to the 2963 // final result: 2964 // 2965 // #define LOG2OFe 1.4426950f 2966 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 2967 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 2968 getF32Constant(DAG, 0x3fb8aa3b)); 2969 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 2970 2971 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 2972 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 2973 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 2974 2975 // IntegerPartOfX <<= 23; 2976 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 2977 DAG.getConstant(23, TLI.getPointerTy())); 2978 2979 if (LimitFloatPrecision <= 6) { 2980 // For floating-point precision of 6: 2981 // 2982 // TwoToFractionalPartOfX = 2983 // 0.997535578f + 2984 // (0.735607626f + 0.252464424f * x) * x; 2985 // 2986 // error 0.0144103317, which is 6 bits 2987 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 2988 getF32Constant(DAG, 0x3e814304)); 2989 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 2990 getF32Constant(DAG, 0x3f3c50c8)); 2991 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 2992 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 2993 getF32Constant(DAG, 0x3f7f5e7e)); 2994 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5); 2995 2996 // Add the exponent into the result in integer domain. 2997 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 2998 TwoToFracPartOfX, IntegerPartOfX); 2999 3000 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6); 3001 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3002 // For floating-point precision of 12: 3003 // 3004 // TwoToFractionalPartOfX = 3005 // 0.999892986f + 3006 // (0.696457318f + 3007 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3008 // 3009 // 0.000107046256 error, which is 13 to 14 bits 3010 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3011 getF32Constant(DAG, 0x3da235e3)); 3012 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3013 getF32Constant(DAG, 0x3e65b8f3)); 3014 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3015 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3016 getF32Constant(DAG, 0x3f324b07)); 3017 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3018 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3019 getF32Constant(DAG, 0x3f7ff8fd)); 3020 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7); 3021 3022 // Add the exponent into the result in integer domain. 3023 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3024 TwoToFracPartOfX, IntegerPartOfX); 3025 3026 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8); 3027 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3028 // For floating-point precision of 18: 3029 // 3030 // TwoToFractionalPartOfX = 3031 // 0.999999982f + 3032 // (0.693148872f + 3033 // (0.240227044f + 3034 // (0.554906021e-1f + 3035 // (0.961591928e-2f + 3036 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3037 // 3038 // error 2.47208000*10^(-7), which is better than 18 bits 3039 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3040 getF32Constant(DAG, 0x3924b03e)); 3041 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3042 getF32Constant(DAG, 0x3ab24b87)); 3043 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3044 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3045 getF32Constant(DAG, 0x3c1d8c17)); 3046 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3047 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3048 getF32Constant(DAG, 0x3d634a1d)); 3049 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3050 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3051 getF32Constant(DAG, 0x3e75fe14)); 3052 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3053 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3054 getF32Constant(DAG, 0x3f317234)); 3055 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3056 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3057 getF32Constant(DAG, 0x3f800000)); 3058 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl, 3059 MVT::i32, t13); 3060 3061 // Add the exponent into the result in integer domain. 3062 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3063 TwoToFracPartOfX, IntegerPartOfX); 3064 3065 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14); 3066 } 3067 } else { 3068 // No special expansion. 3069 result = DAG.getNode(ISD::FEXP, dl, 3070 getValue(I.getOperand(1)).getValueType(), 3071 getValue(I.getOperand(1))); 3072 } 3073 3074 setValue(&I, result); 3075} 3076 3077/// visitLog - Lower a log intrinsic. Handles the special sequences for 3078/// limited-precision mode. 3079void 3080SelectionDAGBuilder::visitLog(CallInst &I) { 3081 SDValue result; 3082 DebugLoc dl = getCurDebugLoc(); 3083 3084 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3085 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3086 SDValue Op = getValue(I.getOperand(1)); 3087 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3088 3089 // Scale the exponent by log(2) [0.69314718f]. 3090 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3091 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3092 getF32Constant(DAG, 0x3f317218)); 3093 3094 // Get the significand and build it into a floating-point number with 3095 // exponent of 1. 3096 SDValue X = GetSignificand(DAG, Op1, dl); 3097 3098 if (LimitFloatPrecision <= 6) { 3099 // For floating-point precision of 6: 3100 // 3101 // LogofMantissa = 3102 // -1.1609546f + 3103 // (1.4034025f - 0.23903021f * x) * x; 3104 // 3105 // error 0.0034276066, which is better than 8 bits 3106 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3107 getF32Constant(DAG, 0xbe74c456)); 3108 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3109 getF32Constant(DAG, 0x3fb3a2b1)); 3110 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3111 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3112 getF32Constant(DAG, 0x3f949a29)); 3113 3114 result = DAG.getNode(ISD::FADD, dl, 3115 MVT::f32, LogOfExponent, LogOfMantissa); 3116 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3117 // For floating-point precision of 12: 3118 // 3119 // LogOfMantissa = 3120 // -1.7417939f + 3121 // (2.8212026f + 3122 // (-1.4699568f + 3123 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3124 // 3125 // error 0.000061011436, which is 14 bits 3126 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3127 getF32Constant(DAG, 0xbd67b6d6)); 3128 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3129 getF32Constant(DAG, 0x3ee4f4b8)); 3130 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3131 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3132 getF32Constant(DAG, 0x3fbc278b)); 3133 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3134 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3135 getF32Constant(DAG, 0x40348e95)); 3136 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3137 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3138 getF32Constant(DAG, 0x3fdef31a)); 3139 3140 result = DAG.getNode(ISD::FADD, dl, 3141 MVT::f32, LogOfExponent, LogOfMantissa); 3142 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3143 // For floating-point precision of 18: 3144 // 3145 // LogOfMantissa = 3146 // -2.1072184f + 3147 // (4.2372794f + 3148 // (-3.7029485f + 3149 // (2.2781945f + 3150 // (-0.87823314f + 3151 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3152 // 3153 // error 0.0000023660568, which is better than 18 bits 3154 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3155 getF32Constant(DAG, 0xbc91e5ac)); 3156 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3157 getF32Constant(DAG, 0x3e4350aa)); 3158 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3159 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3160 getF32Constant(DAG, 0x3f60d3e3)); 3161 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3162 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3163 getF32Constant(DAG, 0x4011cdf0)); 3164 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3165 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3166 getF32Constant(DAG, 0x406cfd1c)); 3167 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3168 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3169 getF32Constant(DAG, 0x408797cb)); 3170 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3171 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3172 getF32Constant(DAG, 0x4006dcab)); 3173 3174 result = DAG.getNode(ISD::FADD, dl, 3175 MVT::f32, LogOfExponent, LogOfMantissa); 3176 } 3177 } else { 3178 // No special expansion. 3179 result = DAG.getNode(ISD::FLOG, dl, 3180 getValue(I.getOperand(1)).getValueType(), 3181 getValue(I.getOperand(1))); 3182 } 3183 3184 setValue(&I, result); 3185} 3186 3187/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3188/// limited-precision mode. 3189void 3190SelectionDAGBuilder::visitLog2(CallInst &I) { 3191 SDValue result; 3192 DebugLoc dl = getCurDebugLoc(); 3193 3194 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3195 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3196 SDValue Op = getValue(I.getOperand(1)); 3197 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3198 3199 // Get the exponent. 3200 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3201 3202 // Get the significand and build it into a floating-point number with 3203 // exponent of 1. 3204 SDValue X = GetSignificand(DAG, Op1, dl); 3205 3206 // Different possible minimax approximations of significand in 3207 // floating-point for various degrees of accuracy over [1,2]. 3208 if (LimitFloatPrecision <= 6) { 3209 // For floating-point precision of 6: 3210 // 3211 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3212 // 3213 // error 0.0049451742, which is more than 7 bits 3214 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3215 getF32Constant(DAG, 0xbeb08fe0)); 3216 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3217 getF32Constant(DAG, 0x40019463)); 3218 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3219 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3220 getF32Constant(DAG, 0x3fd6633d)); 3221 3222 result = DAG.getNode(ISD::FADD, dl, 3223 MVT::f32, LogOfExponent, Log2ofMantissa); 3224 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3225 // For floating-point precision of 12: 3226 // 3227 // Log2ofMantissa = 3228 // -2.51285454f + 3229 // (4.07009056f + 3230 // (-2.12067489f + 3231 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3232 // 3233 // error 0.0000876136000, which is better than 13 bits 3234 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3235 getF32Constant(DAG, 0xbda7262e)); 3236 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3237 getF32Constant(DAG, 0x3f25280b)); 3238 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3239 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3240 getF32Constant(DAG, 0x4007b923)); 3241 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3242 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3243 getF32Constant(DAG, 0x40823e2f)); 3244 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3245 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3246 getF32Constant(DAG, 0x4020d29c)); 3247 3248 result = DAG.getNode(ISD::FADD, dl, 3249 MVT::f32, LogOfExponent, Log2ofMantissa); 3250 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3251 // For floating-point precision of 18: 3252 // 3253 // Log2ofMantissa = 3254 // -3.0400495f + 3255 // (6.1129976f + 3256 // (-5.3420409f + 3257 // (3.2865683f + 3258 // (-1.2669343f + 3259 // (0.27515199f - 3260 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3261 // 3262 // error 0.0000018516, which is better than 18 bits 3263 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3264 getF32Constant(DAG, 0xbcd2769e)); 3265 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3266 getF32Constant(DAG, 0x3e8ce0b9)); 3267 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3268 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3269 getF32Constant(DAG, 0x3fa22ae7)); 3270 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3271 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3272 getF32Constant(DAG, 0x40525723)); 3273 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3274 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3275 getF32Constant(DAG, 0x40aaf200)); 3276 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3277 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3278 getF32Constant(DAG, 0x40c39dad)); 3279 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3280 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3281 getF32Constant(DAG, 0x4042902c)); 3282 3283 result = DAG.getNode(ISD::FADD, dl, 3284 MVT::f32, LogOfExponent, Log2ofMantissa); 3285 } 3286 } else { 3287 // No special expansion. 3288 result = DAG.getNode(ISD::FLOG2, dl, 3289 getValue(I.getOperand(1)).getValueType(), 3290 getValue(I.getOperand(1))); 3291 } 3292 3293 setValue(&I, result); 3294} 3295 3296/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3297/// limited-precision mode. 3298void 3299SelectionDAGBuilder::visitLog10(CallInst &I) { 3300 SDValue result; 3301 DebugLoc dl = getCurDebugLoc(); 3302 3303 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3304 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3305 SDValue Op = getValue(I.getOperand(1)); 3306 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3307 3308 // Scale the exponent by log10(2) [0.30102999f]. 3309 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3310 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3311 getF32Constant(DAG, 0x3e9a209a)); 3312 3313 // Get the significand and build it into a floating-point number with 3314 // exponent of 1. 3315 SDValue X = GetSignificand(DAG, Op1, dl); 3316 3317 if (LimitFloatPrecision <= 6) { 3318 // For floating-point precision of 6: 3319 // 3320 // Log10ofMantissa = 3321 // -0.50419619f + 3322 // (0.60948995f - 0.10380950f * x) * x; 3323 // 3324 // error 0.0014886165, which is 6 bits 3325 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3326 getF32Constant(DAG, 0xbdd49a13)); 3327 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3328 getF32Constant(DAG, 0x3f1c0789)); 3329 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3330 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3331 getF32Constant(DAG, 0x3f011300)); 3332 3333 result = DAG.getNode(ISD::FADD, dl, 3334 MVT::f32, LogOfExponent, Log10ofMantissa); 3335 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3336 // For floating-point precision of 12: 3337 // 3338 // Log10ofMantissa = 3339 // -0.64831180f + 3340 // (0.91751397f + 3341 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3342 // 3343 // error 0.00019228036, which is better than 12 bits 3344 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3345 getF32Constant(DAG, 0x3d431f31)); 3346 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3347 getF32Constant(DAG, 0x3ea21fb2)); 3348 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3349 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3350 getF32Constant(DAG, 0x3f6ae232)); 3351 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3352 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3353 getF32Constant(DAG, 0x3f25f7c3)); 3354 3355 result = DAG.getNode(ISD::FADD, dl, 3356 MVT::f32, LogOfExponent, Log10ofMantissa); 3357 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3358 // For floating-point precision of 18: 3359 // 3360 // Log10ofMantissa = 3361 // -0.84299375f + 3362 // (1.5327582f + 3363 // (-1.0688956f + 3364 // (0.49102474f + 3365 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3366 // 3367 // error 0.0000037995730, which is better than 18 bits 3368 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3369 getF32Constant(DAG, 0x3c5d51ce)); 3370 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3371 getF32Constant(DAG, 0x3e00685a)); 3372 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3373 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3374 getF32Constant(DAG, 0x3efb6798)); 3375 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3376 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3377 getF32Constant(DAG, 0x3f88d192)); 3378 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3379 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3380 getF32Constant(DAG, 0x3fc4316c)); 3381 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3382 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3383 getF32Constant(DAG, 0x3f57ce70)); 3384 3385 result = DAG.getNode(ISD::FADD, dl, 3386 MVT::f32, LogOfExponent, Log10ofMantissa); 3387 } 3388 } else { 3389 // No special expansion. 3390 result = DAG.getNode(ISD::FLOG10, dl, 3391 getValue(I.getOperand(1)).getValueType(), 3392 getValue(I.getOperand(1))); 3393 } 3394 3395 setValue(&I, result); 3396} 3397 3398/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3399/// limited-precision mode. 3400void 3401SelectionDAGBuilder::visitExp2(CallInst &I) { 3402 SDValue result; 3403 DebugLoc dl = getCurDebugLoc(); 3404 3405 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3406 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3407 SDValue Op = getValue(I.getOperand(1)); 3408 3409 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3410 3411 // FractionalPartOfX = x - (float)IntegerPartOfX; 3412 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3413 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3414 3415 // IntegerPartOfX <<= 23; 3416 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3417 DAG.getConstant(23, TLI.getPointerTy())); 3418 3419 if (LimitFloatPrecision <= 6) { 3420 // For floating-point precision of 6: 3421 // 3422 // TwoToFractionalPartOfX = 3423 // 0.997535578f + 3424 // (0.735607626f + 0.252464424f * x) * x; 3425 // 3426 // error 0.0144103317, which is 6 bits 3427 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3428 getF32Constant(DAG, 0x3e814304)); 3429 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3430 getF32Constant(DAG, 0x3f3c50c8)); 3431 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3432 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3433 getF32Constant(DAG, 0x3f7f5e7e)); 3434 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3435 SDValue TwoToFractionalPartOfX = 3436 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3437 3438 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3439 MVT::f32, TwoToFractionalPartOfX); 3440 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3441 // For floating-point precision of 12: 3442 // 3443 // TwoToFractionalPartOfX = 3444 // 0.999892986f + 3445 // (0.696457318f + 3446 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3447 // 3448 // error 0.000107046256, which is 13 to 14 bits 3449 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3450 getF32Constant(DAG, 0x3da235e3)); 3451 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3452 getF32Constant(DAG, 0x3e65b8f3)); 3453 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3454 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3455 getF32Constant(DAG, 0x3f324b07)); 3456 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3457 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3458 getF32Constant(DAG, 0x3f7ff8fd)); 3459 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3460 SDValue TwoToFractionalPartOfX = 3461 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3462 3463 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3464 MVT::f32, TwoToFractionalPartOfX); 3465 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3466 // For floating-point precision of 18: 3467 // 3468 // TwoToFractionalPartOfX = 3469 // 0.999999982f + 3470 // (0.693148872f + 3471 // (0.240227044f + 3472 // (0.554906021e-1f + 3473 // (0.961591928e-2f + 3474 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3475 // error 2.47208000*10^(-7), which is better than 18 bits 3476 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3477 getF32Constant(DAG, 0x3924b03e)); 3478 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3479 getF32Constant(DAG, 0x3ab24b87)); 3480 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3481 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3482 getF32Constant(DAG, 0x3c1d8c17)); 3483 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3484 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3485 getF32Constant(DAG, 0x3d634a1d)); 3486 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3487 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3488 getF32Constant(DAG, 0x3e75fe14)); 3489 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3490 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3491 getF32Constant(DAG, 0x3f317234)); 3492 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3493 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3494 getF32Constant(DAG, 0x3f800000)); 3495 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3496 SDValue TwoToFractionalPartOfX = 3497 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3498 3499 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3500 MVT::f32, TwoToFractionalPartOfX); 3501 } 3502 } else { 3503 // No special expansion. 3504 result = DAG.getNode(ISD::FEXP2, dl, 3505 getValue(I.getOperand(1)).getValueType(), 3506 getValue(I.getOperand(1))); 3507 } 3508 3509 setValue(&I, result); 3510} 3511 3512/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3513/// limited-precision mode with x == 10.0f. 3514void 3515SelectionDAGBuilder::visitPow(CallInst &I) { 3516 SDValue result; 3517 Value *Val = I.getOperand(1); 3518 DebugLoc dl = getCurDebugLoc(); 3519 bool IsExp10 = false; 3520 3521 if (getValue(Val).getValueType() == MVT::f32 && 3522 getValue(I.getOperand(2)).getValueType() == MVT::f32 && 3523 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3524 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3525 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3526 APFloat Ten(10.0f); 3527 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3528 } 3529 } 3530 } 3531 3532 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3533 SDValue Op = getValue(I.getOperand(2)); 3534 3535 // Put the exponent in the right bit position for later addition to the 3536 // final result: 3537 // 3538 // #define LOG2OF10 3.3219281f 3539 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3540 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3541 getF32Constant(DAG, 0x40549a78)); 3542 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3543 3544 // FractionalPartOfX = x - (float)IntegerPartOfX; 3545 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3546 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3547 3548 // IntegerPartOfX <<= 23; 3549 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3550 DAG.getConstant(23, TLI.getPointerTy())); 3551 3552 if (LimitFloatPrecision <= 6) { 3553 // For floating-point precision of 6: 3554 // 3555 // twoToFractionalPartOfX = 3556 // 0.997535578f + 3557 // (0.735607626f + 0.252464424f * x) * x; 3558 // 3559 // error 0.0144103317, which is 6 bits 3560 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3561 getF32Constant(DAG, 0x3e814304)); 3562 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3563 getF32Constant(DAG, 0x3f3c50c8)); 3564 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3565 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3566 getF32Constant(DAG, 0x3f7f5e7e)); 3567 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3568 SDValue TwoToFractionalPartOfX = 3569 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3570 3571 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3572 MVT::f32, TwoToFractionalPartOfX); 3573 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3574 // For floating-point precision of 12: 3575 // 3576 // TwoToFractionalPartOfX = 3577 // 0.999892986f + 3578 // (0.696457318f + 3579 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3580 // 3581 // error 0.000107046256, which is 13 to 14 bits 3582 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3583 getF32Constant(DAG, 0x3da235e3)); 3584 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3585 getF32Constant(DAG, 0x3e65b8f3)); 3586 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3587 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3588 getF32Constant(DAG, 0x3f324b07)); 3589 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3590 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3591 getF32Constant(DAG, 0x3f7ff8fd)); 3592 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3593 SDValue TwoToFractionalPartOfX = 3594 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3595 3596 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3597 MVT::f32, TwoToFractionalPartOfX); 3598 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3599 // For floating-point precision of 18: 3600 // 3601 // TwoToFractionalPartOfX = 3602 // 0.999999982f + 3603 // (0.693148872f + 3604 // (0.240227044f + 3605 // (0.554906021e-1f + 3606 // (0.961591928e-2f + 3607 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3608 // error 2.47208000*10^(-7), which is better than 18 bits 3609 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3610 getF32Constant(DAG, 0x3924b03e)); 3611 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3612 getF32Constant(DAG, 0x3ab24b87)); 3613 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3614 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3615 getF32Constant(DAG, 0x3c1d8c17)); 3616 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3617 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3618 getF32Constant(DAG, 0x3d634a1d)); 3619 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3620 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3621 getF32Constant(DAG, 0x3e75fe14)); 3622 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3623 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3624 getF32Constant(DAG, 0x3f317234)); 3625 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3626 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3627 getF32Constant(DAG, 0x3f800000)); 3628 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3629 SDValue TwoToFractionalPartOfX = 3630 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3631 3632 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3633 MVT::f32, TwoToFractionalPartOfX); 3634 } 3635 } else { 3636 // No special expansion. 3637 result = DAG.getNode(ISD::FPOW, dl, 3638 getValue(I.getOperand(1)).getValueType(), 3639 getValue(I.getOperand(1)), 3640 getValue(I.getOperand(2))); 3641 } 3642 3643 setValue(&I, result); 3644} 3645 3646 3647/// ExpandPowI - Expand a llvm.powi intrinsic. 3648static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 3649 SelectionDAG &DAG) { 3650 // If RHS is a constant, we can expand this out to a multiplication tree, 3651 // otherwise we end up lowering to a call to __powidf2 (for example). When 3652 // optimizing for size, we only want to do this if the expansion would produce 3653 // a small number of multiplies, otherwise we do the full expansion. 3654 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3655 // Get the exponent as a positive value. 3656 unsigned Val = RHSC->getSExtValue(); 3657 if ((int)Val < 0) Val = -Val; 3658 3659 // powi(x, 0) -> 1.0 3660 if (Val == 0) 3661 return DAG.getConstantFP(1.0, LHS.getValueType()); 3662 3663 Function *F = DAG.getMachineFunction().getFunction(); 3664 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 3665 // If optimizing for size, don't insert too many multiplies. This 3666 // inserts up to 5 multiplies. 3667 CountPopulation_32(Val)+Log2_32(Val) < 7) { 3668 // We use the simple binary decomposition method to generate the multiply 3669 // sequence. There are more optimal ways to do this (for example, 3670 // powi(x,15) generates one more multiply than it should), but this has 3671 // the benefit of being both really simple and much better than a libcall. 3672 SDValue Res; // Logically starts equal to 1.0 3673 SDValue CurSquare = LHS; 3674 while (Val) { 3675 if (Val & 1) { 3676 if (Res.getNode()) 3677 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 3678 else 3679 Res = CurSquare; // 1.0*CurSquare. 3680 } 3681 3682 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 3683 CurSquare, CurSquare); 3684 Val >>= 1; 3685 } 3686 3687 // If the original was negative, invert the result, producing 1/(x*x*x). 3688 if (RHSC->getSExtValue() < 0) 3689 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 3690 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 3691 return Res; 3692 } 3693 } 3694 3695 // Otherwise, expand to a libcall. 3696 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 3697} 3698 3699 3700/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 3701/// we want to emit this as a call to a named external function, return the name 3702/// otherwise lower it and return null. 3703const char * 3704SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 3705 DebugLoc dl = getCurDebugLoc(); 3706 SDValue Res; 3707 3708 switch (Intrinsic) { 3709 default: 3710 // By default, turn this into a target intrinsic node. 3711 visitTargetIntrinsic(I, Intrinsic); 3712 return 0; 3713 case Intrinsic::vastart: visitVAStart(I); return 0; 3714 case Intrinsic::vaend: visitVAEnd(I); return 0; 3715 case Intrinsic::vacopy: visitVACopy(I); return 0; 3716 case Intrinsic::returnaddress: 3717 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 3718 getValue(I.getOperand(1)))); 3719 return 0; 3720 case Intrinsic::frameaddress: 3721 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 3722 getValue(I.getOperand(1)))); 3723 return 0; 3724 case Intrinsic::setjmp: 3725 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 3726 case Intrinsic::longjmp: 3727 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 3728 case Intrinsic::memcpy: { 3729 SDValue Op1 = getValue(I.getOperand(1)); 3730 SDValue Op2 = getValue(I.getOperand(2)); 3731 SDValue Op3 = getValue(I.getOperand(3)); 3732 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3733 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false, 3734 I.getOperand(1), 0, I.getOperand(2), 0)); 3735 return 0; 3736 } 3737 case Intrinsic::memset: { 3738 SDValue Op1 = getValue(I.getOperand(1)); 3739 SDValue Op2 = getValue(I.getOperand(2)); 3740 SDValue Op3 = getValue(I.getOperand(3)); 3741 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3742 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, 3743 I.getOperand(1), 0)); 3744 return 0; 3745 } 3746 case Intrinsic::memmove: { 3747 SDValue Op1 = getValue(I.getOperand(1)); 3748 SDValue Op2 = getValue(I.getOperand(2)); 3749 SDValue Op3 = getValue(I.getOperand(3)); 3750 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3751 3752 // If the source and destination are known to not be aliases, we can 3753 // lower memmove as memcpy. 3754 uint64_t Size = -1ULL; 3755 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 3756 Size = C->getZExtValue(); 3757 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) == 3758 AliasAnalysis::NoAlias) { 3759 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false, 3760 I.getOperand(1), 0, I.getOperand(2), 0)); 3761 return 0; 3762 } 3763 3764 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, 3765 I.getOperand(1), 0, I.getOperand(2), 0)); 3766 return 0; 3767 } 3768 case Intrinsic::dbg_declare: { 3769 // FIXME: currently, we get here only if OptLevel != CodeGenOpt::None. 3770 // The real handling of this intrinsic is in FastISel. 3771 if (OptLevel != CodeGenOpt::None) 3772 // FIXME: Variable debug info is not supported here. 3773 return 0; 3774 DwarfWriter *DW = DAG.getDwarfWriter(); 3775 if (!DW) 3776 return 0; 3777 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 3778 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None)) 3779 return 0; 3780 3781 MDNode *Variable = DI.getVariable(); 3782 Value *Address = DI.getAddress(); 3783 if (!Address) 3784 return 0; 3785 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 3786 Address = BCI->getOperand(0); 3787 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 3788 // Don't handle byval struct arguments or VLAs, for example. 3789 if (!AI) 3790 return 0; 3791 DenseMap<const AllocaInst*, int>::iterator SI = 3792 FuncInfo.StaticAllocaMap.find(AI); 3793 if (SI == FuncInfo.StaticAllocaMap.end()) 3794 return 0; // VLAs. 3795 int FI = SI->second; 3796 3797 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) 3798 if (MDNode *Dbg = DI.getMetadata("dbg")) 3799 MMI->setVariableDbgInfo(Variable, FI, Dbg); 3800 return 0; 3801 } 3802 case Intrinsic::dbg_value: { 3803 // FIXME: currently, we get here only if OptLevel != CodeGenOpt::None. 3804 // The real handling of this intrinsic is in FastISel. 3805 if (OptLevel != CodeGenOpt::None) 3806 // FIXME: Variable debug info is not supported here. 3807 return 0; 3808 DwarfWriter *DW = DAG.getDwarfWriter(); 3809 if (!DW) 3810 return 0; 3811 DbgValueInst &DI = cast<DbgValueInst>(I); 3812 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None)) 3813 return 0; 3814 3815 MDNode *Variable = DI.getVariable(); 3816 Value *V = DI.getValue(); 3817 if (!V) 3818 return 0; 3819 if (BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 3820 V = BCI->getOperand(0); 3821 AllocaInst *AI = dyn_cast<AllocaInst>(V); 3822 // Don't handle byval struct arguments or VLAs, for example. 3823 if (!AI) 3824 return 0; 3825 DenseMap<const AllocaInst*, int>::iterator SI = 3826 FuncInfo.StaticAllocaMap.find(AI); 3827 if (SI == FuncInfo.StaticAllocaMap.end()) 3828 return 0; // VLAs. 3829 int FI = SI->second; 3830 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) 3831 if (MDNode *Dbg = DI.getMetadata("dbg")) 3832 MMI->setVariableDbgInfo(Variable, FI, Dbg); 3833 return 0; 3834 } 3835 case Intrinsic::eh_exception: { 3836 // Insert the EXCEPTIONADDR instruction. 3837 assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!"); 3838 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 3839 SDValue Ops[1]; 3840 Ops[0] = DAG.getRoot(); 3841 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 3842 setValue(&I, Op); 3843 DAG.setRoot(Op.getValue(1)); 3844 return 0; 3845 } 3846 3847 case Intrinsic::eh_selector: { 3848 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3849 3850 if (CurMBB->isLandingPad()) 3851 AddCatchInfo(I, MMI, CurMBB); 3852 else { 3853#ifndef NDEBUG 3854 FuncInfo.CatchInfoLost.insert(&I); 3855#endif 3856 // FIXME: Mark exception selector register as live in. Hack for PR1508. 3857 unsigned Reg = TLI.getExceptionSelectorRegister(); 3858 if (Reg) CurMBB->addLiveIn(Reg); 3859 } 3860 3861 // Insert the EHSELECTION instruction. 3862 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 3863 SDValue Ops[2]; 3864 Ops[0] = getValue(I.getOperand(1)); 3865 Ops[1] = getRoot(); 3866 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 3867 DAG.setRoot(Op.getValue(1)); 3868 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 3869 return 0; 3870 } 3871 3872 case Intrinsic::eh_typeid_for: { 3873 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3874 3875 if (MMI) { 3876 // Find the type id for the given typeinfo. 3877 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 3878 unsigned TypeID = MMI->getTypeIDFor(GV); 3879 Res = DAG.getConstant(TypeID, MVT::i32); 3880 } else { 3881 // Return something different to eh_selector. 3882 Res = DAG.getConstant(1, MVT::i32); 3883 } 3884 3885 setValue(&I, Res); 3886 return 0; 3887 } 3888 3889 case Intrinsic::eh_return_i32: 3890 case Intrinsic::eh_return_i64: 3891 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 3892 MMI->setCallsEHReturn(true); 3893 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 3894 MVT::Other, 3895 getControlRoot(), 3896 getValue(I.getOperand(1)), 3897 getValue(I.getOperand(2)))); 3898 } else { 3899 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 3900 } 3901 3902 return 0; 3903 case Intrinsic::eh_unwind_init: 3904 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 3905 MMI->setCallsUnwindInit(true); 3906 } 3907 return 0; 3908 case Intrinsic::eh_dwarf_cfa: { 3909 EVT VT = getValue(I.getOperand(1)).getValueType(); 3910 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), dl, 3911 TLI.getPointerTy()); 3912 SDValue Offset = DAG.getNode(ISD::ADD, dl, 3913 TLI.getPointerTy(), 3914 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 3915 TLI.getPointerTy()), 3916 CfaArg); 3917 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 3918 TLI.getPointerTy(), 3919 DAG.getConstant(0, TLI.getPointerTy())); 3920 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 3921 FA, Offset)); 3922 return 0; 3923 } 3924 case Intrinsic::eh_sjlj_callsite: { 3925 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3926 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1)); 3927 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 3928 assert(MMI->getCurrentCallSite() == 0 && "Overlapping call sites!"); 3929 3930 MMI->setCurrentCallSite(CI->getZExtValue()); 3931 return 0; 3932 } 3933 3934 case Intrinsic::convertff: 3935 case Intrinsic::convertfsi: 3936 case Intrinsic::convertfui: 3937 case Intrinsic::convertsif: 3938 case Intrinsic::convertuif: 3939 case Intrinsic::convertss: 3940 case Intrinsic::convertsu: 3941 case Intrinsic::convertus: 3942 case Intrinsic::convertuu: { 3943 ISD::CvtCode Code = ISD::CVT_INVALID; 3944 switch (Intrinsic) { 3945 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 3946 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 3947 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 3948 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 3949 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 3950 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 3951 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 3952 case Intrinsic::convertus: Code = ISD::CVT_US; break; 3953 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 3954 } 3955 EVT DestVT = TLI.getValueType(I.getType()); 3956 Value *Op1 = I.getOperand(1); 3957 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 3958 DAG.getValueType(DestVT), 3959 DAG.getValueType(getValue(Op1).getValueType()), 3960 getValue(I.getOperand(2)), 3961 getValue(I.getOperand(3)), 3962 Code); 3963 setValue(&I, Res); 3964 return 0; 3965 } 3966 case Intrinsic::sqrt: 3967 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 3968 getValue(I.getOperand(1)).getValueType(), 3969 getValue(I.getOperand(1)))); 3970 return 0; 3971 case Intrinsic::powi: 3972 setValue(&I, ExpandPowI(dl, getValue(I.getOperand(1)), 3973 getValue(I.getOperand(2)), DAG)); 3974 return 0; 3975 case Intrinsic::sin: 3976 setValue(&I, DAG.getNode(ISD::FSIN, dl, 3977 getValue(I.getOperand(1)).getValueType(), 3978 getValue(I.getOperand(1)))); 3979 return 0; 3980 case Intrinsic::cos: 3981 setValue(&I, DAG.getNode(ISD::FCOS, dl, 3982 getValue(I.getOperand(1)).getValueType(), 3983 getValue(I.getOperand(1)))); 3984 return 0; 3985 case Intrinsic::log: 3986 visitLog(I); 3987 return 0; 3988 case Intrinsic::log2: 3989 visitLog2(I); 3990 return 0; 3991 case Intrinsic::log10: 3992 visitLog10(I); 3993 return 0; 3994 case Intrinsic::exp: 3995 visitExp(I); 3996 return 0; 3997 case Intrinsic::exp2: 3998 visitExp2(I); 3999 return 0; 4000 case Intrinsic::pow: 4001 visitPow(I); 4002 return 0; 4003 case Intrinsic::convert_to_fp16: 4004 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4005 MVT::i16, getValue(I.getOperand(1)))); 4006 return 0; 4007 case Intrinsic::convert_from_fp16: 4008 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4009 MVT::f32, getValue(I.getOperand(1)))); 4010 return 0; 4011 case Intrinsic::pcmarker: { 4012 SDValue Tmp = getValue(I.getOperand(1)); 4013 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4014 return 0; 4015 } 4016 case Intrinsic::readcyclecounter: { 4017 SDValue Op = getRoot(); 4018 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4019 DAG.getVTList(MVT::i64, MVT::Other), 4020 &Op, 1); 4021 setValue(&I, Res); 4022 DAG.setRoot(Res.getValue(1)); 4023 return 0; 4024 } 4025 case Intrinsic::bswap: 4026 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4027 getValue(I.getOperand(1)).getValueType(), 4028 getValue(I.getOperand(1)))); 4029 return 0; 4030 case Intrinsic::cttz: { 4031 SDValue Arg = getValue(I.getOperand(1)); 4032 EVT Ty = Arg.getValueType(); 4033 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4034 return 0; 4035 } 4036 case Intrinsic::ctlz: { 4037 SDValue Arg = getValue(I.getOperand(1)); 4038 EVT Ty = Arg.getValueType(); 4039 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4040 return 0; 4041 } 4042 case Intrinsic::ctpop: { 4043 SDValue Arg = getValue(I.getOperand(1)); 4044 EVT Ty = Arg.getValueType(); 4045 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4046 return 0; 4047 } 4048 case Intrinsic::stacksave: { 4049 SDValue Op = getRoot(); 4050 Res = DAG.getNode(ISD::STACKSAVE, dl, 4051 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4052 setValue(&I, Res); 4053 DAG.setRoot(Res.getValue(1)); 4054 return 0; 4055 } 4056 case Intrinsic::stackrestore: { 4057 Res = getValue(I.getOperand(1)); 4058 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4059 return 0; 4060 } 4061 case Intrinsic::stackprotector: { 4062 // Emit code into the DAG to store the stack guard onto the stack. 4063 MachineFunction &MF = DAG.getMachineFunction(); 4064 MachineFrameInfo *MFI = MF.getFrameInfo(); 4065 EVT PtrTy = TLI.getPointerTy(); 4066 4067 SDValue Src = getValue(I.getOperand(1)); // The guard's value. 4068 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2)); 4069 4070 int FI = FuncInfo.StaticAllocaMap[Slot]; 4071 MFI->setStackProtectorIndex(FI); 4072 4073 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4074 4075 // Store the stack protector onto the stack. 4076 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4077 PseudoSourceValue::getFixedStack(FI), 4078 0, true, false, 0); 4079 setValue(&I, Res); 4080 DAG.setRoot(Res); 4081 return 0; 4082 } 4083 case Intrinsic::objectsize: { 4084 // If we don't know by now, we're never going to know. 4085 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2)); 4086 4087 assert(CI && "Non-constant type in __builtin_object_size?"); 4088 4089 SDValue Arg = getValue(I.getOperand(0)); 4090 EVT Ty = Arg.getValueType(); 4091 4092 if (CI->getZExtValue() == 0) 4093 Res = DAG.getConstant(-1ULL, Ty); 4094 else 4095 Res = DAG.getConstant(0, Ty); 4096 4097 setValue(&I, Res); 4098 return 0; 4099 } 4100 case Intrinsic::var_annotation: 4101 // Discard annotate attributes 4102 return 0; 4103 4104 case Intrinsic::init_trampoline: { 4105 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts()); 4106 4107 SDValue Ops[6]; 4108 Ops[0] = getRoot(); 4109 Ops[1] = getValue(I.getOperand(1)); 4110 Ops[2] = getValue(I.getOperand(2)); 4111 Ops[3] = getValue(I.getOperand(3)); 4112 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 4113 Ops[5] = DAG.getSrcValue(F); 4114 4115 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4116 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4117 Ops, 6); 4118 4119 setValue(&I, Res); 4120 DAG.setRoot(Res.getValue(1)); 4121 return 0; 4122 } 4123 case Intrinsic::gcroot: 4124 if (GFI) { 4125 Value *Alloca = I.getOperand(1); 4126 Constant *TypeMap = cast<Constant>(I.getOperand(2)); 4127 4128 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4129 GFI->addStackRoot(FI->getIndex(), TypeMap); 4130 } 4131 return 0; 4132 case Intrinsic::gcread: 4133 case Intrinsic::gcwrite: 4134 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4135 return 0; 4136 case Intrinsic::flt_rounds: 4137 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4138 return 0; 4139 case Intrinsic::trap: 4140 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4141 return 0; 4142 case Intrinsic::uadd_with_overflow: 4143 return implVisitAluOverflow(I, ISD::UADDO); 4144 case Intrinsic::sadd_with_overflow: 4145 return implVisitAluOverflow(I, ISD::SADDO); 4146 case Intrinsic::usub_with_overflow: 4147 return implVisitAluOverflow(I, ISD::USUBO); 4148 case Intrinsic::ssub_with_overflow: 4149 return implVisitAluOverflow(I, ISD::SSUBO); 4150 case Intrinsic::umul_with_overflow: 4151 return implVisitAluOverflow(I, ISD::UMULO); 4152 case Intrinsic::smul_with_overflow: 4153 return implVisitAluOverflow(I, ISD::SMULO); 4154 4155 case Intrinsic::prefetch: { 4156 SDValue Ops[4]; 4157 Ops[0] = getRoot(); 4158 Ops[1] = getValue(I.getOperand(1)); 4159 Ops[2] = getValue(I.getOperand(2)); 4160 Ops[3] = getValue(I.getOperand(3)); 4161 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4)); 4162 return 0; 4163 } 4164 4165 case Intrinsic::memory_barrier: { 4166 SDValue Ops[6]; 4167 Ops[0] = getRoot(); 4168 for (int x = 1; x < 6; ++x) 4169 Ops[x] = getValue(I.getOperand(x)); 4170 4171 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4172 return 0; 4173 } 4174 case Intrinsic::atomic_cmp_swap: { 4175 SDValue Root = getRoot(); 4176 SDValue L = 4177 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4178 getValue(I.getOperand(2)).getValueType().getSimpleVT(), 4179 Root, 4180 getValue(I.getOperand(1)), 4181 getValue(I.getOperand(2)), 4182 getValue(I.getOperand(3)), 4183 I.getOperand(1)); 4184 setValue(&I, L); 4185 DAG.setRoot(L.getValue(1)); 4186 return 0; 4187 } 4188 case Intrinsic::atomic_load_add: 4189 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4190 case Intrinsic::atomic_load_sub: 4191 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4192 case Intrinsic::atomic_load_or: 4193 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4194 case Intrinsic::atomic_load_xor: 4195 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4196 case Intrinsic::atomic_load_and: 4197 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4198 case Intrinsic::atomic_load_nand: 4199 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4200 case Intrinsic::atomic_load_max: 4201 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4202 case Intrinsic::atomic_load_min: 4203 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4204 case Intrinsic::atomic_load_umin: 4205 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4206 case Intrinsic::atomic_load_umax: 4207 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4208 case Intrinsic::atomic_swap: 4209 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4210 4211 case Intrinsic::invariant_start: 4212 case Intrinsic::lifetime_start: 4213 // Discard region information. 4214 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4215 return 0; 4216 case Intrinsic::invariant_end: 4217 case Intrinsic::lifetime_end: 4218 // Discard region information. 4219 return 0; 4220 } 4221} 4222 4223/// Test if the given instruction is in a position to be optimized 4224/// with a tail-call. This roughly means that it's in a block with 4225/// a return and there's nothing that needs to be scheduled 4226/// between it and the return. 4227/// 4228/// This function only tests target-independent requirements. 4229static bool 4230isInTailCallPosition(CallSite CS, Attributes CalleeRetAttr, 4231 const TargetLowering &TLI) { 4232 const Instruction *I = CS.getInstruction(); 4233 const BasicBlock *ExitBB = I->getParent(); 4234 const TerminatorInst *Term = ExitBB->getTerminator(); 4235 const ReturnInst *Ret = dyn_cast<ReturnInst>(Term); 4236 const Function *F = ExitBB->getParent(); 4237 4238 // The block must end in a return statement or unreachable. 4239 // 4240 // FIXME: Decline tailcall if it's not guaranteed and if the block ends in 4241 // an unreachable, for now. The way tailcall optimization is currently 4242 // implemented means it will add an epilogue followed by a jump. That is 4243 // not profitable. Also, if the callee is a special function (e.g. 4244 // longjmp on x86), it can end up causing miscompilation that has not 4245 // been fully understood. 4246 if (!Ret && 4247 (!GuaranteedTailCallOpt || !isa<UnreachableInst>(Term))) return false; 4248 4249 // If I will have a chain, make sure no other instruction that will have a 4250 // chain interposes between I and the return. 4251 if (I->mayHaveSideEffects() || I->mayReadFromMemory() || 4252 !I->isSafeToSpeculativelyExecute()) 4253 for (BasicBlock::const_iterator BBI = prior(prior(ExitBB->end())); ; 4254 --BBI) { 4255 if (&*BBI == I) 4256 break; 4257 if (BBI->mayHaveSideEffects() || BBI->mayReadFromMemory() || 4258 !BBI->isSafeToSpeculativelyExecute()) 4259 return false; 4260 } 4261 4262 // If the block ends with a void return or unreachable, it doesn't matter 4263 // what the call's return type is. 4264 if (!Ret || Ret->getNumOperands() == 0) return true; 4265 4266 // If the return value is undef, it doesn't matter what the call's 4267 // return type is. 4268 if (isa<UndefValue>(Ret->getOperand(0))) return true; 4269 4270 // Conservatively require the attributes of the call to match those of 4271 // the return. Ignore noalias because it doesn't affect the call sequence. 4272 unsigned CallerRetAttr = F->getAttributes().getRetAttributes(); 4273 if ((CalleeRetAttr ^ CallerRetAttr) & ~Attribute::NoAlias) 4274 return false; 4275 4276 // It's not safe to eliminate the sign / zero extension of the return value. 4277 if ((CallerRetAttr & Attribute::ZExt) || (CallerRetAttr & Attribute::SExt)) 4278 return false; 4279 4280 // Otherwise, make sure the unmodified return value of I is the return value. 4281 for (const Instruction *U = dyn_cast<Instruction>(Ret->getOperand(0)); ; 4282 U = dyn_cast<Instruction>(U->getOperand(0))) { 4283 if (!U) 4284 return false; 4285 if (!U->hasOneUse()) 4286 return false; 4287 if (U == I) 4288 break; 4289 // Check for a truly no-op truncate. 4290 if (isa<TruncInst>(U) && 4291 TLI.isTruncateFree(U->getOperand(0)->getType(), U->getType())) 4292 continue; 4293 // Check for a truly no-op bitcast. 4294 if (isa<BitCastInst>(U) && 4295 (U->getOperand(0)->getType() == U->getType() || 4296 (U->getOperand(0)->getType()->isPointerTy() && 4297 U->getType()->isPointerTy()))) 4298 continue; 4299 // Otherwise it's not a true no-op. 4300 return false; 4301 } 4302 4303 return true; 4304} 4305 4306void SelectionDAGBuilder::LowerCallTo(CallSite CS, SDValue Callee, 4307 bool isTailCall, 4308 MachineBasicBlock *LandingPad) { 4309 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4310 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4311 const Type *RetTy = FTy->getReturnType(); 4312 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4313 MCSymbol *BeginLabel = 0; 4314 4315 TargetLowering::ArgListTy Args; 4316 TargetLowering::ArgListEntry Entry; 4317 Args.reserve(CS.arg_size()); 4318 4319 // Check whether the function can return without sret-demotion. 4320 SmallVector<EVT, 4> OutVTs; 4321 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags; 4322 SmallVector<uint64_t, 4> Offsets; 4323 getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4324 OutVTs, OutsFlags, TLI, &Offsets); 4325 4326 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4327 FTy->isVarArg(), OutVTs, OutsFlags, DAG); 4328 4329 SDValue DemoteStackSlot; 4330 4331 if (!CanLowerReturn) { 4332 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4333 FTy->getReturnType()); 4334 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4335 FTy->getReturnType()); 4336 MachineFunction &MF = DAG.getMachineFunction(); 4337 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4338 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4339 4340 DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4341 Entry.Node = DemoteStackSlot; 4342 Entry.Ty = StackSlotPtrType; 4343 Entry.isSExt = false; 4344 Entry.isZExt = false; 4345 Entry.isInReg = false; 4346 Entry.isSRet = true; 4347 Entry.isNest = false; 4348 Entry.isByVal = false; 4349 Entry.Alignment = Align; 4350 Args.push_back(Entry); 4351 RetTy = Type::getVoidTy(FTy->getContext()); 4352 } 4353 4354 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4355 i != e; ++i) { 4356 SDValue ArgNode = getValue(*i); 4357 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 4358 4359 unsigned attrInd = i - CS.arg_begin() + 1; 4360 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4361 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4362 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4363 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4364 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4365 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4366 Entry.Alignment = CS.getParamAlignment(attrInd); 4367 Args.push_back(Entry); 4368 } 4369 4370 if (LandingPad && MMI) { 4371 // Insert a label before the invoke call to mark the try range. This can be 4372 // used to detect deletion of the invoke via the MachineModuleInfo. 4373 BeginLabel = MMI->getContext().CreateTempSymbol(); 4374 4375 // For SjLj, keep track of which landing pads go with which invokes 4376 // so as to maintain the ordering of pads in the LSDA. 4377 unsigned CallSiteIndex = MMI->getCurrentCallSite(); 4378 if (CallSiteIndex) { 4379 MMI->setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4380 // Now that the call site is handled, stop tracking it. 4381 MMI->setCurrentCallSite(0); 4382 } 4383 4384 // Both PendingLoads and PendingExports must be flushed here; 4385 // this call might not return. 4386 (void)getRoot(); 4387 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4388 } 4389 4390 // Check if target-independent constraints permit a tail call here. 4391 // Target-dependent constraints are checked within TLI.LowerCallTo. 4392 if (isTailCall && 4393 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4394 isTailCall = false; 4395 4396 std::pair<SDValue,SDValue> Result = 4397 TLI.LowerCallTo(getRoot(), RetTy, 4398 CS.paramHasAttr(0, Attribute::SExt), 4399 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4400 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4401 CS.getCallingConv(), 4402 isTailCall, 4403 !CS.getInstruction()->use_empty(), 4404 Callee, Args, DAG, getCurDebugLoc()); 4405 assert((isTailCall || Result.second.getNode()) && 4406 "Non-null chain expected with non-tail call!"); 4407 assert((Result.second.getNode() || !Result.first.getNode()) && 4408 "Null value expected with tail call!"); 4409 if (Result.first.getNode()) { 4410 setValue(CS.getInstruction(), Result.first); 4411 } else if (!CanLowerReturn && Result.second.getNode()) { 4412 // The instruction result is the result of loading from the 4413 // hidden sret parameter. 4414 SmallVector<EVT, 1> PVTs; 4415 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 4416 4417 ComputeValueVTs(TLI, PtrRetTy, PVTs); 4418 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 4419 EVT PtrVT = PVTs[0]; 4420 unsigned NumValues = OutVTs.size(); 4421 SmallVector<SDValue, 4> Values(NumValues); 4422 SmallVector<SDValue, 4> Chains(NumValues); 4423 4424 for (unsigned i = 0; i < NumValues; ++i) { 4425 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 4426 DemoteStackSlot, 4427 DAG.getConstant(Offsets[i], PtrVT)); 4428 SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second, 4429 Add, NULL, Offsets[i], false, false, 1); 4430 Values[i] = L; 4431 Chains[i] = L.getValue(1); 4432 } 4433 4434 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 4435 MVT::Other, &Chains[0], NumValues); 4436 PendingLoads.push_back(Chain); 4437 4438 // Collect the legal value parts into potentially illegal values 4439 // that correspond to the original function's return values. 4440 SmallVector<EVT, 4> RetTys; 4441 RetTy = FTy->getReturnType(); 4442 ComputeValueVTs(TLI, RetTy, RetTys); 4443 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4444 SmallVector<SDValue, 4> ReturnValues; 4445 unsigned CurReg = 0; 4446 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4447 EVT VT = RetTys[I]; 4448 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 4449 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 4450 4451 SDValue ReturnValue = 4452 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 4453 RegisterVT, VT, AssertOp); 4454 ReturnValues.push_back(ReturnValue); 4455 CurReg += NumRegs; 4456 } 4457 4458 setValue(CS.getInstruction(), 4459 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 4460 DAG.getVTList(&RetTys[0], RetTys.size()), 4461 &ReturnValues[0], ReturnValues.size())); 4462 4463 } 4464 4465 // As a special case, a null chain means that a tail call has been emitted and 4466 // the DAG root is already updated. 4467 if (Result.second.getNode()) 4468 DAG.setRoot(Result.second); 4469 else 4470 HasTailCall = true; 4471 4472 if (LandingPad && MMI) { 4473 // Insert a label at the end of the invoke call to mark the try range. This 4474 // can be used to detect deletion of the invoke via the MachineModuleInfo. 4475 MCSymbol *EndLabel = MMI->getContext().CreateTempSymbol(); 4476 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 4477 4478 // Inform MachineModuleInfo of range. 4479 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 4480 } 4481} 4482 4483/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 4484/// value is equal or not-equal to zero. 4485static bool IsOnlyUsedInZeroEqualityComparison(Value *V) { 4486 for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); 4487 UI != E; ++UI) { 4488 if (ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 4489 if (IC->isEquality()) 4490 if (Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 4491 if (C->isNullValue()) 4492 continue; 4493 // Unknown instruction. 4494 return false; 4495 } 4496 return true; 4497} 4498 4499static SDValue getMemCmpLoad(Value *PtrVal, MVT LoadVT, const Type *LoadTy, 4500 SelectionDAGBuilder &Builder) { 4501 4502 // Check to see if this load can be trivially constant folded, e.g. if the 4503 // input is from a string literal. 4504 if (Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 4505 // Cast pointer to the type we really want to load. 4506 LoadInput = ConstantExpr::getBitCast(LoadInput, 4507 PointerType::getUnqual(LoadTy)); 4508 4509 if (Constant *LoadCst = ConstantFoldLoadFromConstPtr(LoadInput, Builder.TD)) 4510 return Builder.getValue(LoadCst); 4511 } 4512 4513 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 4514 // still constant memory, the input chain can be the entry node. 4515 SDValue Root; 4516 bool ConstantMemory = false; 4517 4518 // Do not serialize (non-volatile) loads of constant memory with anything. 4519 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 4520 Root = Builder.DAG.getEntryNode(); 4521 ConstantMemory = true; 4522 } else { 4523 // Do not serialize non-volatile loads against each other. 4524 Root = Builder.DAG.getRoot(); 4525 } 4526 4527 SDValue Ptr = Builder.getValue(PtrVal); 4528 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 4529 Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/, 4530 false /*volatile*/, 4531 false /*nontemporal*/, 1 /* align=1 */); 4532 4533 if (!ConstantMemory) 4534 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 4535 return LoadVal; 4536} 4537 4538 4539/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 4540/// If so, return true and lower it, otherwise return false and it will be 4541/// lowered like a normal call. 4542bool SelectionDAGBuilder::visitMemCmpCall(CallInst &I) { 4543 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 4544 if (I.getNumOperands() != 4) 4545 return false; 4546 4547 Value *LHS = I.getOperand(1), *RHS = I.getOperand(2); 4548 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 4549 !I.getOperand(3)->getType()->isIntegerTy() || 4550 !I.getType()->isIntegerTy()) 4551 return false; 4552 4553 ConstantInt *Size = dyn_cast<ConstantInt>(I.getOperand(3)); 4554 4555 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 4556 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 4557 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 4558 bool ActuallyDoIt = true; 4559 MVT LoadVT; 4560 const Type *LoadTy; 4561 switch (Size->getZExtValue()) { 4562 default: 4563 LoadVT = MVT::Other; 4564 LoadTy = 0; 4565 ActuallyDoIt = false; 4566 break; 4567 case 2: 4568 LoadVT = MVT::i16; 4569 LoadTy = Type::getInt16Ty(Size->getContext()); 4570 break; 4571 case 4: 4572 LoadVT = MVT::i32; 4573 LoadTy = Type::getInt32Ty(Size->getContext()); 4574 break; 4575 case 8: 4576 LoadVT = MVT::i64; 4577 LoadTy = Type::getInt64Ty(Size->getContext()); 4578 break; 4579 /* 4580 case 16: 4581 LoadVT = MVT::v4i32; 4582 LoadTy = Type::getInt32Ty(Size->getContext()); 4583 LoadTy = VectorType::get(LoadTy, 4); 4584 break; 4585 */ 4586 } 4587 4588 // This turns into unaligned loads. We only do this if the target natively 4589 // supports the MVT we'll be loading or if it is small enough (<= 4) that 4590 // we'll only produce a small number of byte loads. 4591 4592 // Require that we can find a legal MVT, and only do this if the target 4593 // supports unaligned loads of that type. Expanding into byte loads would 4594 // bloat the code. 4595 if (ActuallyDoIt && Size->getZExtValue() > 4) { 4596 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 4597 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 4598 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 4599 ActuallyDoIt = false; 4600 } 4601 4602 if (ActuallyDoIt) { 4603 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 4604 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 4605 4606 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 4607 ISD::SETNE); 4608 EVT CallVT = TLI.getValueType(I.getType(), true); 4609 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 4610 return true; 4611 } 4612 } 4613 4614 4615 return false; 4616} 4617 4618 4619void SelectionDAGBuilder::visitCall(CallInst &I) { 4620 const char *RenameFn = 0; 4621 if (Function *F = I.getCalledFunction()) { 4622 if (F->isDeclaration()) { 4623 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo(); 4624 if (II) { 4625 if (unsigned IID = II->getIntrinsicID(F)) { 4626 RenameFn = visitIntrinsicCall(I, IID); 4627 if (!RenameFn) 4628 return; 4629 } 4630 } 4631 if (unsigned IID = F->getIntrinsicID()) { 4632 RenameFn = visitIntrinsicCall(I, IID); 4633 if (!RenameFn) 4634 return; 4635 } 4636 } 4637 4638 // Check for well-known libc/libm calls. If the function is internal, it 4639 // can't be a library call. 4640 if (!F->hasLocalLinkage() && F->hasName()) { 4641 StringRef Name = F->getName(); 4642 if (Name == "copysign" || Name == "copysignf") { 4643 if (I.getNumOperands() == 3 && // Basic sanity checks. 4644 I.getOperand(1)->getType()->isFloatingPointTy() && 4645 I.getType() == I.getOperand(1)->getType() && 4646 I.getType() == I.getOperand(2)->getType()) { 4647 SDValue LHS = getValue(I.getOperand(1)); 4648 SDValue RHS = getValue(I.getOperand(2)); 4649 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 4650 LHS.getValueType(), LHS, RHS)); 4651 return; 4652 } 4653 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 4654 if (I.getNumOperands() == 2 && // Basic sanity checks. 4655 I.getOperand(1)->getType()->isFloatingPointTy() && 4656 I.getType() == I.getOperand(1)->getType()) { 4657 SDValue Tmp = getValue(I.getOperand(1)); 4658 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 4659 Tmp.getValueType(), Tmp)); 4660 return; 4661 } 4662 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 4663 if (I.getNumOperands() == 2 && // Basic sanity checks. 4664 I.getOperand(1)->getType()->isFloatingPointTy() && 4665 I.getType() == I.getOperand(1)->getType() && 4666 I.onlyReadsMemory()) { 4667 SDValue Tmp = getValue(I.getOperand(1)); 4668 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 4669 Tmp.getValueType(), Tmp)); 4670 return; 4671 } 4672 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 4673 if (I.getNumOperands() == 2 && // Basic sanity checks. 4674 I.getOperand(1)->getType()->isFloatingPointTy() && 4675 I.getType() == I.getOperand(1)->getType() && 4676 I.onlyReadsMemory()) { 4677 SDValue Tmp = getValue(I.getOperand(1)); 4678 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 4679 Tmp.getValueType(), Tmp)); 4680 return; 4681 } 4682 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 4683 if (I.getNumOperands() == 2 && // Basic sanity checks. 4684 I.getOperand(1)->getType()->isFloatingPointTy() && 4685 I.getType() == I.getOperand(1)->getType() && 4686 I.onlyReadsMemory()) { 4687 SDValue Tmp = getValue(I.getOperand(1)); 4688 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 4689 Tmp.getValueType(), Tmp)); 4690 return; 4691 } 4692 } else if (Name == "memcmp") { 4693 if (visitMemCmpCall(I)) 4694 return; 4695 } 4696 } 4697 } else if (isa<InlineAsm>(I.getOperand(0))) { 4698 visitInlineAsm(&I); 4699 return; 4700 } 4701 4702 SDValue Callee; 4703 if (!RenameFn) 4704 Callee = getValue(I.getOperand(0)); 4705 else 4706 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 4707 4708 // Check if we can potentially perform a tail call. More detailed checking is 4709 // be done within LowerCallTo, after more information about the call is known. 4710 LowerCallTo(&I, Callee, I.isTailCall()); 4711} 4712 4713/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 4714/// this value and returns the result as a ValueVT value. This uses 4715/// Chain/Flag as the input and updates them for the output Chain/Flag. 4716/// If the Flag pointer is NULL, no flag is used. 4717SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, 4718 SDValue &Chain, SDValue *Flag) const { 4719 // Assemble the legal parts into the final values. 4720 SmallVector<SDValue, 4> Values(ValueVTs.size()); 4721 SmallVector<SDValue, 8> Parts; 4722 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 4723 // Copy the legal parts from the registers. 4724 EVT ValueVT = ValueVTs[Value]; 4725 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT); 4726 EVT RegisterVT = RegVTs[Value]; 4727 4728 Parts.resize(NumRegs); 4729 for (unsigned i = 0; i != NumRegs; ++i) { 4730 SDValue P; 4731 if (Flag == 0) { 4732 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 4733 } else { 4734 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 4735 *Flag = P.getValue(2); 4736 } 4737 4738 Chain = P.getValue(1); 4739 4740 // If the source register was virtual and if we know something about it, 4741 // add an assert node. 4742 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && 4743 RegisterVT.isInteger() && !RegisterVT.isVector()) { 4744 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; 4745 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 4746 if (FLI.LiveOutRegInfo.size() > SlotNo) { 4747 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo]; 4748 4749 unsigned RegSize = RegisterVT.getSizeInBits(); 4750 unsigned NumSignBits = LOI.NumSignBits; 4751 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 4752 4753 // FIXME: We capture more information than the dag can represent. For 4754 // now, just use the tightest assertzext/assertsext possible. 4755 bool isSExt = true; 4756 EVT FromVT(MVT::Other); 4757 if (NumSignBits == RegSize) 4758 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 4759 else if (NumZeroBits >= RegSize-1) 4760 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 4761 else if (NumSignBits > RegSize-8) 4762 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 4763 else if (NumZeroBits >= RegSize-8) 4764 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 4765 else if (NumSignBits > RegSize-16) 4766 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 4767 else if (NumZeroBits >= RegSize-16) 4768 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 4769 else if (NumSignBits > RegSize-32) 4770 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 4771 else if (NumZeroBits >= RegSize-32) 4772 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 4773 4774 if (FromVT != MVT::Other) 4775 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 4776 RegisterVT, P, DAG.getValueType(FromVT)); 4777 } 4778 } 4779 4780 Parts[i] = P; 4781 } 4782 4783 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 4784 NumRegs, RegisterVT, ValueVT); 4785 Part += NumRegs; 4786 Parts.clear(); 4787 } 4788 4789 return DAG.getNode(ISD::MERGE_VALUES, dl, 4790 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 4791 &Values[0], ValueVTs.size()); 4792} 4793 4794/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 4795/// specified value into the registers specified by this object. This uses 4796/// Chain/Flag as the input and updates them for the output Chain/Flag. 4797/// If the Flag pointer is NULL, no flag is used. 4798void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 4799 SDValue &Chain, SDValue *Flag) const { 4800 // Get the list of the values's legal parts. 4801 unsigned NumRegs = Regs.size(); 4802 SmallVector<SDValue, 8> Parts(NumRegs); 4803 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 4804 EVT ValueVT = ValueVTs[Value]; 4805 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT); 4806 EVT RegisterVT = RegVTs[Value]; 4807 4808 getCopyToParts(DAG, dl, 4809 Val.getValue(Val.getResNo() + Value), 4810 &Parts[Part], NumParts, RegisterVT); 4811 Part += NumParts; 4812 } 4813 4814 // Copy the parts into the registers. 4815 SmallVector<SDValue, 8> Chains(NumRegs); 4816 for (unsigned i = 0; i != NumRegs; ++i) { 4817 SDValue Part; 4818 if (Flag == 0) { 4819 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 4820 } else { 4821 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 4822 *Flag = Part.getValue(1); 4823 } 4824 4825 Chains[i] = Part.getValue(0); 4826 } 4827 4828 if (NumRegs == 1 || Flag) 4829 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 4830 // flagged to it. That is the CopyToReg nodes and the user are considered 4831 // a single scheduling unit. If we create a TokenFactor and return it as 4832 // chain, then the TokenFactor is both a predecessor (operand) of the 4833 // user as well as a successor (the TF operands are flagged to the user). 4834 // c1, f1 = CopyToReg 4835 // c2, f2 = CopyToReg 4836 // c3 = TokenFactor c1, c2 4837 // ... 4838 // = op c3, ..., f2 4839 Chain = Chains[NumRegs-1]; 4840 else 4841 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 4842} 4843 4844/// AddInlineAsmOperands - Add this value to the specified inlineasm node 4845/// operand list. This adds the code marker and includes the number of 4846/// values added into it. 4847void RegsForValue::AddInlineAsmOperands(unsigned Code, 4848 bool HasMatching,unsigned MatchingIdx, 4849 SelectionDAG &DAG, 4850 std::vector<SDValue> &Ops) const { 4851 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!"); 4852 unsigned Flag = Code | (Regs.size() << 3); 4853 if (HasMatching) 4854 Flag |= 0x80000000 | (MatchingIdx << 16); 4855 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 4856 Ops.push_back(Res); 4857 4858 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 4859 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 4860 EVT RegisterVT = RegVTs[Value]; 4861 for (unsigned i = 0; i != NumRegs; ++i) { 4862 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 4863 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 4864 } 4865 } 4866} 4867 4868/// isAllocatableRegister - If the specified register is safe to allocate, 4869/// i.e. it isn't a stack pointer or some other special register, return the 4870/// register class for the register. Otherwise, return null. 4871static const TargetRegisterClass * 4872isAllocatableRegister(unsigned Reg, MachineFunction &MF, 4873 const TargetLowering &TLI, 4874 const TargetRegisterInfo *TRI) { 4875 EVT FoundVT = MVT::Other; 4876 const TargetRegisterClass *FoundRC = 0; 4877 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 4878 E = TRI->regclass_end(); RCI != E; ++RCI) { 4879 EVT ThisVT = MVT::Other; 4880 4881 const TargetRegisterClass *RC = *RCI; 4882 // If none of the value types for this register class are valid, we 4883 // can't use it. For example, 64-bit reg classes on 32-bit targets. 4884 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 4885 I != E; ++I) { 4886 if (TLI.isTypeLegal(*I)) { 4887 // If we have already found this register in a different register class, 4888 // choose the one with the largest VT specified. For example, on 4889 // PowerPC, we favor f64 register classes over f32. 4890 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 4891 ThisVT = *I; 4892 break; 4893 } 4894 } 4895 } 4896 4897 if (ThisVT == MVT::Other) continue; 4898 4899 // NOTE: This isn't ideal. In particular, this might allocate the 4900 // frame pointer in functions that need it (due to them not being taken 4901 // out of allocation, because a variable sized allocation hasn't been seen 4902 // yet). This is a slight code pessimization, but should still work. 4903 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 4904 E = RC->allocation_order_end(MF); I != E; ++I) 4905 if (*I == Reg) { 4906 // We found a matching register class. Keep looking at others in case 4907 // we find one with larger registers that this physreg is also in. 4908 FoundRC = RC; 4909 FoundVT = ThisVT; 4910 break; 4911 } 4912 } 4913 return FoundRC; 4914} 4915 4916 4917namespace llvm { 4918/// AsmOperandInfo - This contains information for each constraint that we are 4919/// lowering. 4920class VISIBILITY_HIDDEN SDISelAsmOperandInfo : 4921 public TargetLowering::AsmOperandInfo { 4922public: 4923 /// CallOperand - If this is the result output operand or a clobber 4924 /// this is null, otherwise it is the incoming operand to the CallInst. 4925 /// This gets modified as the asm is processed. 4926 SDValue CallOperand; 4927 4928 /// AssignedRegs - If this is a register or register class operand, this 4929 /// contains the set of register corresponding to the operand. 4930 RegsForValue AssignedRegs; 4931 4932 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info) 4933 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 4934 } 4935 4936 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 4937 /// busy in OutputRegs/InputRegs. 4938 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 4939 std::set<unsigned> &OutputRegs, 4940 std::set<unsigned> &InputRegs, 4941 const TargetRegisterInfo &TRI) const { 4942 if (isOutReg) { 4943 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 4944 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 4945 } 4946 if (isInReg) { 4947 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 4948 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 4949 } 4950 } 4951 4952 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 4953 /// corresponds to. If there is no Value* for this operand, it returns 4954 /// MVT::Other. 4955 EVT getCallOperandValEVT(LLVMContext &Context, 4956 const TargetLowering &TLI, 4957 const TargetData *TD) const { 4958 if (CallOperandVal == 0) return MVT::Other; 4959 4960 if (isa<BasicBlock>(CallOperandVal)) 4961 return TLI.getPointerTy(); 4962 4963 const llvm::Type *OpTy = CallOperandVal->getType(); 4964 4965 // If this is an indirect operand, the operand is a pointer to the 4966 // accessed type. 4967 if (isIndirect) { 4968 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 4969 if (!PtrTy) 4970 llvm_report_error("Indirect operand for inline asm not a pointer!"); 4971 OpTy = PtrTy->getElementType(); 4972 } 4973 4974 // If OpTy is not a single value, it may be a struct/union that we 4975 // can tile with integers. 4976 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 4977 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 4978 switch (BitSize) { 4979 default: break; 4980 case 1: 4981 case 8: 4982 case 16: 4983 case 32: 4984 case 64: 4985 case 128: 4986 OpTy = IntegerType::get(Context, BitSize); 4987 break; 4988 } 4989 } 4990 4991 return TLI.getValueType(OpTy, true); 4992 } 4993 4994private: 4995 /// MarkRegAndAliases - Mark the specified register and all aliases in the 4996 /// specified set. 4997 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 4998 const TargetRegisterInfo &TRI) { 4999 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5000 Regs.insert(Reg); 5001 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5002 for (; *Aliases; ++Aliases) 5003 Regs.insert(*Aliases); 5004 } 5005}; 5006} // end llvm namespace. 5007 5008 5009/// GetRegistersForValue - Assign registers (virtual or physical) for the 5010/// specified operand. We prefer to assign virtual registers, to allow the 5011/// register allocator to handle the assignment process. However, if the asm 5012/// uses features that we can't model on machineinstrs, we have SDISel do the 5013/// allocation. This produces generally horrible, but correct, code. 5014/// 5015/// OpInfo describes the operand. 5016/// Input and OutputRegs are the set of already allocated physical registers. 5017/// 5018void SelectionDAGBuilder:: 5019GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, 5020 std::set<unsigned> &OutputRegs, 5021 std::set<unsigned> &InputRegs) { 5022 LLVMContext &Context = FuncInfo.Fn->getContext(); 5023 5024 // Compute whether this value requires an input register, an output register, 5025 // or both. 5026 bool isOutReg = false; 5027 bool isInReg = false; 5028 switch (OpInfo.Type) { 5029 case InlineAsm::isOutput: 5030 isOutReg = true; 5031 5032 // If there is an input constraint that matches this, we need to reserve 5033 // the input register so no other inputs allocate to it. 5034 isInReg = OpInfo.hasMatchingInput(); 5035 break; 5036 case InlineAsm::isInput: 5037 isInReg = true; 5038 isOutReg = false; 5039 break; 5040 case InlineAsm::isClobber: 5041 isOutReg = true; 5042 isInReg = true; 5043 break; 5044 } 5045 5046 5047 MachineFunction &MF = DAG.getMachineFunction(); 5048 SmallVector<unsigned, 4> Regs; 5049 5050 // If this is a constraint for a single physreg, or a constraint for a 5051 // register class, find it. 5052 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5053 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5054 OpInfo.ConstraintVT); 5055 5056 unsigned NumRegs = 1; 5057 if (OpInfo.ConstraintVT != MVT::Other) { 5058 // If this is a FP input in an integer register (or visa versa) insert a bit 5059 // cast of the input value. More generally, handle any case where the input 5060 // value disagrees with the register class we plan to stick this in. 5061 if (OpInfo.Type == InlineAsm::isInput && 5062 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5063 // Try to convert to the first EVT that the reg class contains. If the 5064 // types are identical size, use a bitcast to convert (e.g. two differing 5065 // vector types). 5066 EVT RegVT = *PhysReg.second->vt_begin(); 5067 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5068 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5069 RegVT, OpInfo.CallOperand); 5070 OpInfo.ConstraintVT = RegVT; 5071 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5072 // If the input is a FP value and we want it in FP registers, do a 5073 // bitcast to the corresponding integer type. This turns an f64 value 5074 // into i64, which can be passed with two i32 values on a 32-bit 5075 // machine. 5076 RegVT = EVT::getIntegerVT(Context, 5077 OpInfo.ConstraintVT.getSizeInBits()); 5078 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5079 RegVT, OpInfo.CallOperand); 5080 OpInfo.ConstraintVT = RegVT; 5081 } 5082 } 5083 5084 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5085 } 5086 5087 EVT RegVT; 5088 EVT ValueVT = OpInfo.ConstraintVT; 5089 5090 // If this is a constraint for a specific physical register, like {r17}, 5091 // assign it now. 5092 if (unsigned AssignedReg = PhysReg.first) { 5093 const TargetRegisterClass *RC = PhysReg.second; 5094 if (OpInfo.ConstraintVT == MVT::Other) 5095 ValueVT = *RC->vt_begin(); 5096 5097 // Get the actual register value type. This is important, because the user 5098 // may have asked for (e.g.) the AX register in i32 type. We need to 5099 // remember that AX is actually i16 to get the right extension. 5100 RegVT = *RC->vt_begin(); 5101 5102 // This is a explicit reference to a physical register. 5103 Regs.push_back(AssignedReg); 5104 5105 // If this is an expanded reference, add the rest of the regs to Regs. 5106 if (NumRegs != 1) { 5107 TargetRegisterClass::iterator I = RC->begin(); 5108 for (; *I != AssignedReg; ++I) 5109 assert(I != RC->end() && "Didn't find reg!"); 5110 5111 // Already added the first reg. 5112 --NumRegs; ++I; 5113 for (; NumRegs; --NumRegs, ++I) { 5114 assert(I != RC->end() && "Ran out of registers to allocate!"); 5115 Regs.push_back(*I); 5116 } 5117 } 5118 5119 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); 5120 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5121 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5122 return; 5123 } 5124 5125 // Otherwise, if this was a reference to an LLVM register class, create vregs 5126 // for this reference. 5127 if (const TargetRegisterClass *RC = PhysReg.second) { 5128 RegVT = *RC->vt_begin(); 5129 if (OpInfo.ConstraintVT == MVT::Other) 5130 ValueVT = RegVT; 5131 5132 // Create the appropriate number of virtual registers. 5133 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5134 for (; NumRegs; --NumRegs) 5135 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5136 5137 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); 5138 return; 5139 } 5140 5141 // This is a reference to a register class that doesn't directly correspond 5142 // to an LLVM register class. Allocate NumRegs consecutive, available, 5143 // registers from the class. 5144 std::vector<unsigned> RegClassRegs 5145 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 5146 OpInfo.ConstraintVT); 5147 5148 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5149 unsigned NumAllocated = 0; 5150 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 5151 unsigned Reg = RegClassRegs[i]; 5152 // See if this register is available. 5153 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 5154 (isInReg && InputRegs.count(Reg))) { // Already used. 5155 // Make sure we find consecutive registers. 5156 NumAllocated = 0; 5157 continue; 5158 } 5159 5160 // Check to see if this register is allocatable (i.e. don't give out the 5161 // stack pointer). 5162 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); 5163 if (!RC) { // Couldn't allocate this register. 5164 // Reset NumAllocated to make sure we return consecutive registers. 5165 NumAllocated = 0; 5166 continue; 5167 } 5168 5169 // Okay, this register is good, we can use it. 5170 ++NumAllocated; 5171 5172 // If we allocated enough consecutive registers, succeed. 5173 if (NumAllocated == NumRegs) { 5174 unsigned RegStart = (i-NumAllocated)+1; 5175 unsigned RegEnd = i+1; 5176 // Mark all of the allocated registers used. 5177 for (unsigned i = RegStart; i != RegEnd; ++i) 5178 Regs.push_back(RegClassRegs[i]); 5179 5180 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(), 5181 OpInfo.ConstraintVT); 5182 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5183 return; 5184 } 5185 } 5186 5187 // Otherwise, we couldn't allocate enough registers for this. 5188} 5189 5190/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being 5191/// processed uses a memory 'm' constraint. 5192static bool 5193hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos, 5194 const TargetLowering &TLI) { 5195 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) { 5196 InlineAsm::ConstraintInfo &CI = CInfos[i]; 5197 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) { 5198 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]); 5199 if (CType == TargetLowering::C_Memory) 5200 return true; 5201 } 5202 5203 // Indirect operand accesses access memory. 5204 if (CI.isIndirect) 5205 return true; 5206 } 5207 5208 return false; 5209} 5210 5211/// visitInlineAsm - Handle a call to an InlineAsm object. 5212/// 5213void SelectionDAGBuilder::visitInlineAsm(CallSite CS) { 5214 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5215 5216 /// ConstraintOperands - Information about all of the constraints. 5217 std::vector<SDISelAsmOperandInfo> ConstraintOperands; 5218 5219 std::set<unsigned> OutputRegs, InputRegs; 5220 5221 // Do a prepass over the constraints, canonicalizing them, and building up the 5222 // ConstraintOperands list. 5223 std::vector<InlineAsm::ConstraintInfo> 5224 ConstraintInfos = IA->ParseConstraints(); 5225 5226 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI); 5227 5228 SDValue Chain, Flag; 5229 5230 // We won't need to flush pending loads if this asm doesn't touch 5231 // memory and is nonvolatile. 5232 if (hasMemory || IA->hasSideEffects()) 5233 Chain = getRoot(); 5234 else 5235 Chain = DAG.getRoot(); 5236 5237 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5238 unsigned ResNo = 0; // ResNo - The result number of the next output. 5239 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 5240 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); 5241 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5242 5243 EVT OpVT = MVT::Other; 5244 5245 // Compute the value type for each operand. 5246 switch (OpInfo.Type) { 5247 case InlineAsm::isOutput: 5248 // Indirect outputs just consume an argument. 5249 if (OpInfo.isIndirect) { 5250 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 5251 break; 5252 } 5253 5254 // The return value of the call is this value. As such, there is no 5255 // corresponding argument. 5256 assert(!CS.getType()->isVoidTy() && 5257 "Bad inline asm!"); 5258 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5259 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5260 } else { 5261 assert(ResNo == 0 && "Asm only has one result!"); 5262 OpVT = TLI.getValueType(CS.getType()); 5263 } 5264 ++ResNo; 5265 break; 5266 case InlineAsm::isInput: 5267 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 5268 break; 5269 case InlineAsm::isClobber: 5270 // Nothing to do. 5271 break; 5272 } 5273 5274 // If this is an input or an indirect output, process the call argument. 5275 // BasicBlocks are labels, currently appearing only in asm's. 5276 if (OpInfo.CallOperandVal) { 5277 // Strip bitcasts, if any. This mostly comes up for functions. 5278 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts(); 5279 5280 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5281 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5282 } else { 5283 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5284 } 5285 5286 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5287 } 5288 5289 OpInfo.ConstraintVT = OpVT; 5290 } 5291 5292 // Second pass over the constraints: compute which constraint option to use 5293 // and assign registers to constraints that want a specific physreg. 5294 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 5295 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5296 5297 // If this is an output operand with a matching input operand, look up the 5298 // matching input. If their types mismatch, e.g. one is an integer, the 5299 // other is floating point, or their sizes are different, flag it as an 5300 // error. 5301 if (OpInfo.hasMatchingInput()) { 5302 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5303 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5304 if ((OpInfo.ConstraintVT.isInteger() != 5305 Input.ConstraintVT.isInteger()) || 5306 (OpInfo.ConstraintVT.getSizeInBits() != 5307 Input.ConstraintVT.getSizeInBits())) { 5308 llvm_report_error("Unsupported asm: input constraint" 5309 " with a matching output constraint of incompatible" 5310 " type!"); 5311 } 5312 Input.ConstraintVT = OpInfo.ConstraintVT; 5313 } 5314 } 5315 5316 // Compute the constraint code and ConstraintType to use. 5317 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG); 5318 5319 // If this is a memory input, and if the operand is not indirect, do what we 5320 // need to to provide an address for the memory input. 5321 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5322 !OpInfo.isIndirect) { 5323 assert(OpInfo.Type == InlineAsm::isInput && 5324 "Can only indirectify direct input operands!"); 5325 5326 // Memory operands really want the address of the value. If we don't have 5327 // an indirect input, put it in the constpool if we can, otherwise spill 5328 // it to a stack slot. 5329 5330 // If the operand is a float, integer, or vector constant, spill to a 5331 // constant pool entry to get its address. 5332 Value *OpVal = OpInfo.CallOperandVal; 5333 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5334 isa<ConstantVector>(OpVal)) { 5335 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5336 TLI.getPointerTy()); 5337 } else { 5338 // Otherwise, create a stack slot and emit a store to it before the 5339 // asm. 5340 const Type *Ty = OpVal->getType(); 5341 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5342 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5343 MachineFunction &MF = DAG.getMachineFunction(); 5344 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5345 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5346 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5347 OpInfo.CallOperand, StackSlot, NULL, 0, 5348 false, false, 0); 5349 OpInfo.CallOperand = StackSlot; 5350 } 5351 5352 // There is no longer a Value* corresponding to this operand. 5353 OpInfo.CallOperandVal = 0; 5354 5355 // It is now an indirect operand. 5356 OpInfo.isIndirect = true; 5357 } 5358 5359 // If this constraint is for a specific register, allocate it before 5360 // anything else. 5361 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5362 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5363 } 5364 5365 ConstraintInfos.clear(); 5366 5367 // Second pass - Loop over all of the operands, assigning virtual or physregs 5368 // to register class operands. 5369 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5370 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5371 5372 // C_Register operands have already been allocated, Other/Memory don't need 5373 // to be. 5374 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5375 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5376 } 5377 5378 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5379 std::vector<SDValue> AsmNodeOperands; 5380 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5381 AsmNodeOperands.push_back( 5382 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5383 TLI.getPointerTy())); 5384 5385 5386 // Loop over all of the inputs, copying the operand values into the 5387 // appropriate registers and processing the output regs. 5388 RegsForValue RetValRegs; 5389 5390 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5391 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5392 5393 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5394 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5395 5396 switch (OpInfo.Type) { 5397 case InlineAsm::isOutput: { 5398 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5399 OpInfo.ConstraintType != TargetLowering::C_Register) { 5400 // Memory output, or 'other' output (e.g. 'X' constraint). 5401 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5402 5403 // Add information to the INLINEASM node to know about this output. 5404 unsigned ResOpType = 4/*MEM*/ | (1<<3); 5405 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5406 TLI.getPointerTy())); 5407 AsmNodeOperands.push_back(OpInfo.CallOperand); 5408 break; 5409 } 5410 5411 // Otherwise, this is a register or register class output. 5412 5413 // Copy the output from the appropriate register. Find a register that 5414 // we can use. 5415 if (OpInfo.AssignedRegs.Regs.empty()) { 5416 llvm_report_error("Couldn't allocate output reg for" 5417 " constraint '" + OpInfo.ConstraintCode + "'!"); 5418 } 5419 5420 // If this is an indirect operand, store through the pointer after the 5421 // asm. 5422 if (OpInfo.isIndirect) { 5423 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5424 OpInfo.CallOperandVal)); 5425 } else { 5426 // This is the result value of the call. 5427 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5428 // Concatenate this output onto the outputs list. 5429 RetValRegs.append(OpInfo.AssignedRegs); 5430 } 5431 5432 // Add information to the INLINEASM node to know that this register is 5433 // set. 5434 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5435 6 /* EARLYCLOBBER REGDEF */ : 5436 2 /* REGDEF */ , 5437 false, 5438 0, 5439 DAG, 5440 AsmNodeOperands); 5441 break; 5442 } 5443 case InlineAsm::isInput: { 5444 SDValue InOperandVal = OpInfo.CallOperand; 5445 5446 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5447 // If this is required to match an output register we have already set, 5448 // just use its register. 5449 unsigned OperandNo = OpInfo.getMatchedOperand(); 5450 5451 // Scan until we find the definition we already emitted of this operand. 5452 // When we find it, create a RegsForValue operand. 5453 unsigned CurOp = 2; // The first operand. 5454 for (; OperandNo; --OperandNo) { 5455 // Advance to the next operand. 5456 unsigned OpFlag = 5457 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5458 assert(((OpFlag & 7) == 2 /*REGDEF*/ || 5459 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ || 5460 (OpFlag & 7) == 4 /*MEM*/) && 5461 "Skipped past definitions?"); 5462 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5463 } 5464 5465 unsigned OpFlag = 5466 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5467 if ((OpFlag & 7) == 2 /*REGDEF*/ 5468 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) { 5469 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5470 if (OpInfo.isIndirect) { 5471 llvm_report_error("Don't know how to handle tied indirect " 5472 "register inputs yet!"); 5473 } 5474 RegsForValue MatchedRegs; 5475 MatchedRegs.TLI = &TLI; 5476 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5477 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5478 MatchedRegs.RegVTs.push_back(RegVT); 5479 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5480 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5481 i != e; ++i) 5482 MatchedRegs.Regs.push_back 5483 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5484 5485 // Use the produced MatchedRegs object to 5486 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5487 Chain, &Flag); 5488 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, 5489 true, OpInfo.getMatchedOperand(), 5490 DAG, AsmNodeOperands); 5491 break; 5492 } else { 5493 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!"); 5494 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 && 5495 "Unexpected number of operands"); 5496 // Add information to the INLINEASM node to know about this input. 5497 // See InlineAsm.h isUseOperandTiedToDef. 5498 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16); 5499 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5500 TLI.getPointerTy())); 5501 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5502 break; 5503 } 5504 } 5505 5506 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5507 assert(!OpInfo.isIndirect && 5508 "Don't know how to handle indirect other inputs yet!"); 5509 5510 std::vector<SDValue> Ops; 5511 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 5512 hasMemory, Ops, DAG); 5513 if (Ops.empty()) { 5514 llvm_report_error("Invalid operand for inline asm" 5515 " constraint '" + OpInfo.ConstraintCode + "'!"); 5516 } 5517 5518 // Add information to the INLINEASM node to know about this input. 5519 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 5520 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5521 TLI.getPointerTy())); 5522 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5523 break; 5524 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5525 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5526 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5527 "Memory operands expect pointer values"); 5528 5529 // Add information to the INLINEASM node to know about this input. 5530 unsigned ResOpType = 4/*MEM*/ | (1<<3); 5531 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5532 TLI.getPointerTy())); 5533 AsmNodeOperands.push_back(InOperandVal); 5534 break; 5535 } 5536 5537 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5538 OpInfo.ConstraintType == TargetLowering::C_Register) && 5539 "Unknown constraint type!"); 5540 assert(!OpInfo.isIndirect && 5541 "Don't know how to handle indirect register inputs yet!"); 5542 5543 // Copy the input into the appropriate registers. 5544 if (OpInfo.AssignedRegs.Regs.empty() || 5545 !OpInfo.AssignedRegs.areValueTypesLegal()) { 5546 llvm_report_error("Couldn't allocate input reg for" 5547 " constraint '"+ OpInfo.ConstraintCode +"'!"); 5548 } 5549 5550 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5551 Chain, &Flag); 5552 5553 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0, 5554 DAG, AsmNodeOperands); 5555 break; 5556 } 5557 case InlineAsm::isClobber: { 5558 // Add the clobbered value to the operand list, so that the register 5559 // allocator is aware that the physreg got clobbered. 5560 if (!OpInfo.AssignedRegs.Regs.empty()) 5561 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */, 5562 false, 0, DAG, 5563 AsmNodeOperands); 5564 break; 5565 } 5566 } 5567 } 5568 5569 // Finish up input operands. 5570 AsmNodeOperands[0] = Chain; 5571 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5572 5573 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5574 DAG.getVTList(MVT::Other, MVT::Flag), 5575 &AsmNodeOperands[0], AsmNodeOperands.size()); 5576 Flag = Chain.getValue(1); 5577 5578 // If this asm returns a register value, copy the result from that register 5579 // and set it as the value of the call. 5580 if (!RetValRegs.Regs.empty()) { 5581 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(), 5582 Chain, &Flag); 5583 5584 // FIXME: Why don't we do this for inline asms with MRVs? 5585 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5586 EVT ResultType = TLI.getValueType(CS.getType()); 5587 5588 // If any of the results of the inline asm is a vector, it may have the 5589 // wrong width/num elts. This can happen for register classes that can 5590 // contain multiple different value types. The preg or vreg allocated may 5591 // not have the same VT as was expected. Convert it to the right type 5592 // with bit_convert. 5593 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5594 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5595 ResultType, Val); 5596 5597 } else if (ResultType != Val.getValueType() && 5598 ResultType.isInteger() && Val.getValueType().isInteger()) { 5599 // If a result value was tied to an input value, the computed result may 5600 // have a wider width than the expected result. Extract the relevant 5601 // portion. 5602 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 5603 } 5604 5605 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 5606 } 5607 5608 setValue(CS.getInstruction(), Val); 5609 // Don't need to use this as a chain in this case. 5610 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 5611 return; 5612 } 5613 5614 std::vector<std::pair<SDValue, Value*> > StoresToEmit; 5615 5616 // Process indirect outputs, first output all of the flagged copies out of 5617 // physregs. 5618 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 5619 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 5620 Value *Ptr = IndirectStoresToEmit[i].second; 5621 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(), 5622 Chain, &Flag); 5623 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 5624 5625 } 5626 5627 // Emit the non-flagged stores from the physregs. 5628 SmallVector<SDValue, 8> OutChains; 5629 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 5630 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 5631 StoresToEmit[i].first, 5632 getValue(StoresToEmit[i].second), 5633 StoresToEmit[i].second, 0, 5634 false, false, 0); 5635 OutChains.push_back(Val); 5636 } 5637 5638 if (!OutChains.empty()) 5639 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 5640 &OutChains[0], OutChains.size()); 5641 5642 DAG.setRoot(Chain); 5643} 5644 5645void SelectionDAGBuilder::visitVAStart(CallInst &I) { 5646 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 5647 MVT::Other, getRoot(), 5648 getValue(I.getOperand(1)), 5649 DAG.getSrcValue(I.getOperand(1)))); 5650} 5651 5652void SelectionDAGBuilder::visitVAArg(VAArgInst &I) { 5653 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 5654 getRoot(), getValue(I.getOperand(0)), 5655 DAG.getSrcValue(I.getOperand(0))); 5656 setValue(&I, V); 5657 DAG.setRoot(V.getValue(1)); 5658} 5659 5660void SelectionDAGBuilder::visitVAEnd(CallInst &I) { 5661 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 5662 MVT::Other, getRoot(), 5663 getValue(I.getOperand(1)), 5664 DAG.getSrcValue(I.getOperand(1)))); 5665} 5666 5667void SelectionDAGBuilder::visitVACopy(CallInst &I) { 5668 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 5669 MVT::Other, getRoot(), 5670 getValue(I.getOperand(1)), 5671 getValue(I.getOperand(2)), 5672 DAG.getSrcValue(I.getOperand(1)), 5673 DAG.getSrcValue(I.getOperand(2)))); 5674} 5675 5676/// TargetLowering::LowerCallTo - This is the default LowerCallTo 5677/// implementation, which just calls LowerCall. 5678/// FIXME: When all targets are 5679/// migrated to using LowerCall, this hook should be integrated into SDISel. 5680std::pair<SDValue, SDValue> 5681TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 5682 bool RetSExt, bool RetZExt, bool isVarArg, 5683 bool isInreg, unsigned NumFixedArgs, 5684 CallingConv::ID CallConv, bool isTailCall, 5685 bool isReturnValueUsed, 5686 SDValue Callee, 5687 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) { 5688 // Handle all of the outgoing arguments. 5689 SmallVector<ISD::OutputArg, 32> Outs; 5690 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 5691 SmallVector<EVT, 4> ValueVTs; 5692 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 5693 for (unsigned Value = 0, NumValues = ValueVTs.size(); 5694 Value != NumValues; ++Value) { 5695 EVT VT = ValueVTs[Value]; 5696 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 5697 SDValue Op = SDValue(Args[i].Node.getNode(), 5698 Args[i].Node.getResNo() + Value); 5699 ISD::ArgFlagsTy Flags; 5700 unsigned OriginalAlignment = 5701 getTargetData()->getABITypeAlignment(ArgTy); 5702 5703 if (Args[i].isZExt) 5704 Flags.setZExt(); 5705 if (Args[i].isSExt) 5706 Flags.setSExt(); 5707 if (Args[i].isInReg) 5708 Flags.setInReg(); 5709 if (Args[i].isSRet) 5710 Flags.setSRet(); 5711 if (Args[i].isByVal) { 5712 Flags.setByVal(); 5713 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 5714 const Type *ElementTy = Ty->getElementType(); 5715 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 5716 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy); 5717 // For ByVal, alignment should come from FE. BE will guess if this 5718 // info is not there but there are cases it cannot get right. 5719 if (Args[i].Alignment) 5720 FrameAlign = Args[i].Alignment; 5721 Flags.setByValAlign(FrameAlign); 5722 Flags.setByValSize(FrameSize); 5723 } 5724 if (Args[i].isNest) 5725 Flags.setNest(); 5726 Flags.setOrigAlign(OriginalAlignment); 5727 5728 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 5729 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 5730 SmallVector<SDValue, 4> Parts(NumParts); 5731 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 5732 5733 if (Args[i].isSExt) 5734 ExtendKind = ISD::SIGN_EXTEND; 5735 else if (Args[i].isZExt) 5736 ExtendKind = ISD::ZERO_EXTEND; 5737 5738 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 5739 PartVT, ExtendKind); 5740 5741 for (unsigned j = 0; j != NumParts; ++j) { 5742 // if it isn't first piece, alignment must be 1 5743 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs); 5744 if (NumParts > 1 && j == 0) 5745 MyFlags.Flags.setSplit(); 5746 else if (j != 0) 5747 MyFlags.Flags.setOrigAlign(1); 5748 5749 Outs.push_back(MyFlags); 5750 } 5751 } 5752 } 5753 5754 // Handle the incoming return values from the call. 5755 SmallVector<ISD::InputArg, 32> Ins; 5756 SmallVector<EVT, 4> RetTys; 5757 ComputeValueVTs(*this, RetTy, RetTys); 5758 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5759 EVT VT = RetTys[I]; 5760 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5761 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5762 for (unsigned i = 0; i != NumRegs; ++i) { 5763 ISD::InputArg MyFlags; 5764 MyFlags.VT = RegisterVT; 5765 MyFlags.Used = isReturnValueUsed; 5766 if (RetSExt) 5767 MyFlags.Flags.setSExt(); 5768 if (RetZExt) 5769 MyFlags.Flags.setZExt(); 5770 if (isInreg) 5771 MyFlags.Flags.setInReg(); 5772 Ins.push_back(MyFlags); 5773 } 5774 } 5775 5776 SmallVector<SDValue, 4> InVals; 5777 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 5778 Outs, Ins, dl, DAG, InVals); 5779 5780 // Verify that the target's LowerCall behaved as expected. 5781 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 5782 "LowerCall didn't return a valid chain!"); 5783 assert((!isTailCall || InVals.empty()) && 5784 "LowerCall emitted a return value for a tail call!"); 5785 assert((isTailCall || InVals.size() == Ins.size()) && 5786 "LowerCall didn't emit the correct number of values!"); 5787 5788 // For a tail call, the return value is merely live-out and there aren't 5789 // any nodes in the DAG representing it. Return a special value to 5790 // indicate that a tail call has been emitted and no more Instructions 5791 // should be processed in the current block. 5792 if (isTailCall) { 5793 DAG.setRoot(Chain); 5794 return std::make_pair(SDValue(), SDValue()); 5795 } 5796 5797 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 5798 assert(InVals[i].getNode() && 5799 "LowerCall emitted a null value!"); 5800 assert(Ins[i].VT == InVals[i].getValueType() && 5801 "LowerCall emitted a value with the wrong type!"); 5802 }); 5803 5804 // Collect the legal value parts into potentially illegal values 5805 // that correspond to the original function's return values. 5806 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5807 if (RetSExt) 5808 AssertOp = ISD::AssertSext; 5809 else if (RetZExt) 5810 AssertOp = ISD::AssertZext; 5811 SmallVector<SDValue, 4> ReturnValues; 5812 unsigned CurReg = 0; 5813 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5814 EVT VT = RetTys[I]; 5815 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5816 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5817 5818 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 5819 NumRegs, RegisterVT, VT, 5820 AssertOp)); 5821 CurReg += NumRegs; 5822 } 5823 5824 // For a function returning void, there is no return value. We can't create 5825 // such a node, so we just return a null return value in that case. In 5826 // that case, nothing will actualy look at the value. 5827 if (ReturnValues.empty()) 5828 return std::make_pair(SDValue(), Chain); 5829 5830 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 5831 DAG.getVTList(&RetTys[0], RetTys.size()), 5832 &ReturnValues[0], ReturnValues.size()); 5833 return std::make_pair(Res, Chain); 5834} 5835 5836void TargetLowering::LowerOperationWrapper(SDNode *N, 5837 SmallVectorImpl<SDValue> &Results, 5838 SelectionDAG &DAG) { 5839 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 5840 if (Res.getNode()) 5841 Results.push_back(Res); 5842} 5843 5844SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 5845 llvm_unreachable("LowerOperation not implemented for this target!"); 5846 return SDValue(); 5847} 5848 5849void SelectionDAGBuilder::CopyValueToVirtualRegister(Value *V, unsigned Reg) { 5850 SDValue Op = getValue(V); 5851 assert((Op.getOpcode() != ISD::CopyFromReg || 5852 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 5853 "Copy from a reg to the same reg!"); 5854 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 5855 5856 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 5857 SDValue Chain = DAG.getEntryNode(); 5858 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 5859 PendingExports.push_back(Chain); 5860} 5861 5862#include "llvm/CodeGen/SelectionDAGISel.h" 5863 5864void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) { 5865 // If this is the entry block, emit arguments. 5866 Function &F = *LLVMBB->getParent(); 5867 SelectionDAG &DAG = SDB->DAG; 5868 SDValue OldRoot = DAG.getRoot(); 5869 DebugLoc dl = SDB->getCurDebugLoc(); 5870 const TargetData *TD = TLI.getTargetData(); 5871 SmallVector<ISD::InputArg, 16> Ins; 5872 5873 // Check whether the function can return without sret-demotion. 5874 SmallVector<EVT, 4> OutVTs; 5875 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags; 5876 getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 5877 OutVTs, OutsFlags, TLI); 5878 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 5879 5880 FLI.CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(), F.isVarArg(), 5881 OutVTs, OutsFlags, DAG); 5882 if (!FLI.CanLowerReturn) { 5883 // Put in an sret pointer parameter before all the other parameters. 5884 SmallVector<EVT, 1> ValueVTs; 5885 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 5886 5887 // NOTE: Assuming that a pointer will never break down to more than one VT 5888 // or one register. 5889 ISD::ArgFlagsTy Flags; 5890 Flags.setSRet(); 5891 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), ValueVTs[0]); 5892 ISD::InputArg RetArg(Flags, RegisterVT, true); 5893 Ins.push_back(RetArg); 5894 } 5895 5896 // Set up the incoming argument description vector. 5897 unsigned Idx = 1; 5898 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 5899 I != E; ++I, ++Idx) { 5900 SmallVector<EVT, 4> ValueVTs; 5901 ComputeValueVTs(TLI, I->getType(), ValueVTs); 5902 bool isArgValueUsed = !I->use_empty(); 5903 for (unsigned Value = 0, NumValues = ValueVTs.size(); 5904 Value != NumValues; ++Value) { 5905 EVT VT = ValueVTs[Value]; 5906 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 5907 ISD::ArgFlagsTy Flags; 5908 unsigned OriginalAlignment = 5909 TD->getABITypeAlignment(ArgTy); 5910 5911 if (F.paramHasAttr(Idx, Attribute::ZExt)) 5912 Flags.setZExt(); 5913 if (F.paramHasAttr(Idx, Attribute::SExt)) 5914 Flags.setSExt(); 5915 if (F.paramHasAttr(Idx, Attribute::InReg)) 5916 Flags.setInReg(); 5917 if (F.paramHasAttr(Idx, Attribute::StructRet)) 5918 Flags.setSRet(); 5919 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 5920 Flags.setByVal(); 5921 const PointerType *Ty = cast<PointerType>(I->getType()); 5922 const Type *ElementTy = Ty->getElementType(); 5923 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy); 5924 unsigned FrameSize = TD->getTypeAllocSize(ElementTy); 5925 // For ByVal, alignment should be passed from FE. BE will guess if 5926 // this info is not there but there are cases it cannot get right. 5927 if (F.getParamAlignment(Idx)) 5928 FrameAlign = F.getParamAlignment(Idx); 5929 Flags.setByValAlign(FrameAlign); 5930 Flags.setByValSize(FrameSize); 5931 } 5932 if (F.paramHasAttr(Idx, Attribute::Nest)) 5933 Flags.setNest(); 5934 Flags.setOrigAlign(OriginalAlignment); 5935 5936 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 5937 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 5938 for (unsigned i = 0; i != NumRegs; ++i) { 5939 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 5940 if (NumRegs > 1 && i == 0) 5941 MyFlags.Flags.setSplit(); 5942 // if it isn't first piece, alignment must be 1 5943 else if (i > 0) 5944 MyFlags.Flags.setOrigAlign(1); 5945 Ins.push_back(MyFlags); 5946 } 5947 } 5948 } 5949 5950 // Call the target to set up the argument values. 5951 SmallVector<SDValue, 8> InVals; 5952 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 5953 F.isVarArg(), Ins, 5954 dl, DAG, InVals); 5955 5956 // Verify that the target's LowerFormalArguments behaved as expected. 5957 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 5958 "LowerFormalArguments didn't return a valid chain!"); 5959 assert(InVals.size() == Ins.size() && 5960 "LowerFormalArguments didn't emit the correct number of values!"); 5961 DEBUG({ 5962 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 5963 assert(InVals[i].getNode() && 5964 "LowerFormalArguments emitted a null value!"); 5965 assert(Ins[i].VT == InVals[i].getValueType() && 5966 "LowerFormalArguments emitted a value with the wrong type!"); 5967 } 5968 }); 5969 5970 // Update the DAG with the new chain value resulting from argument lowering. 5971 DAG.setRoot(NewRoot); 5972 5973 // Set up the argument values. 5974 unsigned i = 0; 5975 Idx = 1; 5976 if (!FLI.CanLowerReturn) { 5977 // Create a virtual register for the sret pointer, and put in a copy 5978 // from the sret argument into it. 5979 SmallVector<EVT, 1> ValueVTs; 5980 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 5981 EVT VT = ValueVTs[0]; 5982 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 5983 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5984 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 5985 RegVT, VT, AssertOp); 5986 5987 MachineFunction& MF = SDB->DAG.getMachineFunction(); 5988 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 5989 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 5990 FLI.DemoteRegister = SRetReg; 5991 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 5992 SRetReg, ArgValue); 5993 DAG.setRoot(NewRoot); 5994 5995 // i indexes lowered arguments. Bump it past the hidden sret argument. 5996 // Idx indexes LLVM arguments. Don't touch it. 5997 ++i; 5998 } 5999 6000 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6001 ++I, ++Idx) { 6002 SmallVector<SDValue, 4> ArgValues; 6003 SmallVector<EVT, 4> ValueVTs; 6004 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6005 unsigned NumValues = ValueVTs.size(); 6006 for (unsigned Value = 0; Value != NumValues; ++Value) { 6007 EVT VT = ValueVTs[Value]; 6008 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6009 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6010 6011 if (!I->use_empty()) { 6012 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6013 if (F.paramHasAttr(Idx, Attribute::SExt)) 6014 AssertOp = ISD::AssertSext; 6015 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6016 AssertOp = ISD::AssertZext; 6017 6018 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6019 NumParts, PartVT, VT, 6020 AssertOp)); 6021 } 6022 6023 i += NumParts; 6024 } 6025 6026 if (!I->use_empty()) { 6027 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6028 SDB->getCurDebugLoc()); 6029 SDB->setValue(I, Res); 6030 6031 // If this argument is live outside of the entry block, insert a copy from 6032 // whereever we got it to the vreg that other BB's will reference it as. 6033 SDB->CopyToExportRegsIfNeeded(I); 6034 } 6035 } 6036 6037 assert(i == InVals.size() && "Argument register count mismatch!"); 6038 6039 // Finally, if the target has anything special to do, allow it to do so. 6040 // FIXME: this should insert code into the DAG! 6041 EmitFunctionEntryCode(F, SDB->DAG.getMachineFunction()); 6042} 6043 6044/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6045/// ensure constants are generated when needed. Remember the virtual registers 6046/// that need to be added to the Machine PHI nodes as input. We cannot just 6047/// directly add them, because expansion might result in multiple MBB's for one 6048/// BB. As such, the start of the BB might correspond to a different MBB than 6049/// the end. 6050/// 6051void 6052SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) { 6053 TerminatorInst *TI = LLVMBB->getTerminator(); 6054 6055 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6056 6057 // Check successor nodes' PHI nodes that expect a constant to be available 6058 // from this block. 6059 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6060 BasicBlock *SuccBB = TI->getSuccessor(succ); 6061 if (!isa<PHINode>(SuccBB->begin())) continue; 6062 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB]; 6063 6064 // If this terminator has multiple identical successors (common for 6065 // switches), only handle each succ once. 6066 if (!SuccsHandled.insert(SuccMBB)) continue; 6067 6068 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6069 PHINode *PN; 6070 6071 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6072 // nodes and Machine PHI nodes, but the incoming operands have not been 6073 // emitted yet. 6074 for (BasicBlock::iterator I = SuccBB->begin(); 6075 (PN = dyn_cast<PHINode>(I)); ++I) { 6076 // Ignore dead phi's. 6077 if (PN->use_empty()) continue; 6078 6079 unsigned Reg; 6080 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6081 6082 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 6083 unsigned &RegOut = SDB->ConstantsOut[C]; 6084 if (RegOut == 0) { 6085 RegOut = FuncInfo->CreateRegForValue(C); 6086 SDB->CopyValueToVirtualRegister(C, RegOut); 6087 } 6088 Reg = RegOut; 6089 } else { 6090 Reg = FuncInfo->ValueMap[PHIOp]; 6091 if (Reg == 0) { 6092 assert(isa<AllocaInst>(PHIOp) && 6093 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6094 "Didn't codegen value into a register!??"); 6095 Reg = FuncInfo->CreateRegForValue(PHIOp); 6096 SDB->CopyValueToVirtualRegister(PHIOp, Reg); 6097 } 6098 } 6099 6100 // Remember that this register needs to added to the machine PHI node as 6101 // the input for this MBB. 6102 SmallVector<EVT, 4> ValueVTs; 6103 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6104 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6105 EVT VT = ValueVTs[vti]; 6106 unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6107 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6108 SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6109 Reg += NumRegisters; 6110 } 6111 } 6112 } 6113 SDB->ConstantsOut.clear(); 6114} 6115 6116/// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only 6117/// supports legal types, and it emits MachineInstrs directly instead of 6118/// creating SelectionDAG nodes. 6119/// 6120bool 6121SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, 6122 FastISel *F) { 6123 TerminatorInst *TI = LLVMBB->getTerminator(); 6124 6125 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6126 unsigned OrigNumPHINodesToUpdate = SDB->PHINodesToUpdate.size(); 6127 6128 // Check successor nodes' PHI nodes that expect a constant to be available 6129 // from this block. 6130 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6131 BasicBlock *SuccBB = TI->getSuccessor(succ); 6132 if (!isa<PHINode>(SuccBB->begin())) continue; 6133 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB]; 6134 6135 // If this terminator has multiple identical successors (common for 6136 // switches), only handle each succ once. 6137 if (!SuccsHandled.insert(SuccMBB)) continue; 6138 6139 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6140 PHINode *PN; 6141 6142 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6143 // nodes and Machine PHI nodes, but the incoming operands have not been 6144 // emitted yet. 6145 for (BasicBlock::iterator I = SuccBB->begin(); 6146 (PN = dyn_cast<PHINode>(I)); ++I) { 6147 // Ignore dead phi's. 6148 if (PN->use_empty()) continue; 6149 6150 // Only handle legal types. Two interesting things to note here. First, 6151 // by bailing out early, we may leave behind some dead instructions, 6152 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its 6153 // own moves. Second, this check is necessary becuase FastISel doesn't 6154 // use CreateRegForValue to create registers, so it always creates 6155 // exactly one register for each non-void instruction. 6156 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true); 6157 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) { 6158 // Promote MVT::i1. 6159 if (VT == MVT::i1) 6160 VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT); 6161 else { 6162 SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 6163 return false; 6164 } 6165 } 6166 6167 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6168 6169 unsigned Reg = F->getRegForValue(PHIOp); 6170 if (Reg == 0) { 6171 SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 6172 return false; 6173 } 6174 SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg)); 6175 } 6176 } 6177 6178 return true; 6179} 6180