SelectionDAGBuilder.cpp revision c187df2198bc6e2b038fa2d75af974644874d26f
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Analysis/DebugInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameLowering.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetIntrinsicInfo.h" 50#include "llvm/Target/TargetLibraryInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72// Limit the width of DAG chains. This is important in general to prevent 73// prevent DAG-based analysis from blowing up. For example, alias analysis and 74// load clustering may not complete in reasonable time. It is difficult to 75// recognize and avoid this situation within each individual analysis, and 76// future analyses are likely to have the same behavior. Limiting DAG width is 77// the safe approach, and will be especially important with global DAGs. 78// 79// MaxParallelChains default is arbitrarily high to avoid affecting 80// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81// sequence over this should have been converted to llvm.memcpy by the 82// frontend. It easy to induce this behavior with .ll code such as: 83// %buffer = alloca [4096 x i8] 84// %data = load [4096 x i8]* %argPtr 85// store [4096 x i8] %data, [4096 x i8]* %buffer 86static const unsigned MaxParallelChains = 64; 87 88static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92/// getCopyFromParts - Create a value that contains the specified legal parts 93/// combined into the value they represent. If the parts combine to a type 94/// larger then ValueVT then AssertOp can be used to specify whether the extra 95/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96/// (ISD::AssertSext). 97static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getTargetConstant(1, TLI.getPointerTy())); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209} 210 211/// getCopyFromParts - Create a value that contains the specified legal parts 212/// combined into the value they represent. If the parts combine to a type 213/// larger then ValueVT then AssertOp can be used to specify whether the extra 214/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 215/// (ISD::AssertSext). 216static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 217 const SDValue *Parts, unsigned NumParts, 218 EVT PartVT, EVT ValueVT) { 219 assert(ValueVT.isVector() && "Not a vector value"); 220 assert(NumParts > 0 && "No parts to assemble!"); 221 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 222 SDValue Val = Parts[0]; 223 224 // Handle a multi-element vector. 225 if (NumParts > 1) { 226 EVT IntermediateVT, RegisterVT; 227 unsigned NumIntermediates; 228 unsigned NumRegs = 229 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 230 NumIntermediates, RegisterVT); 231 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 232 NumParts = NumRegs; // Silence a compiler warning. 233 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 234 assert(RegisterVT == Parts[0].getValueType() && 235 "Part type doesn't match part!"); 236 237 // Assemble the parts into intermediate operands. 238 SmallVector<SDValue, 8> Ops(NumIntermediates); 239 if (NumIntermediates == NumParts) { 240 // If the register was not expanded, truncate or copy the value, 241 // as appropriate. 242 for (unsigned i = 0; i != NumParts; ++i) 243 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 244 PartVT, IntermediateVT); 245 } else if (NumParts > 0) { 246 // If the intermediate type was expanded, build the intermediate 247 // operands from the parts. 248 assert(NumParts % NumIntermediates == 0 && 249 "Must expand into a divisible number of parts!"); 250 unsigned Factor = NumParts / NumIntermediates; 251 for (unsigned i = 0; i != NumIntermediates; ++i) 252 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 253 PartVT, IntermediateVT); 254 } 255 256 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 257 // intermediate operands. 258 Val = DAG.getNode(IntermediateVT.isVector() ? 259 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 260 ValueVT, &Ops[0], NumIntermediates); 261 } 262 263 // There is now one part, held in Val. Correct it to match ValueVT. 264 PartVT = Val.getValueType(); 265 266 if (PartVT == ValueVT) 267 return Val; 268 269 if (PartVT.isVector()) { 270 // If the element type of the source/dest vectors are the same, but the 271 // parts vector has more elements than the value vector, then we have a 272 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 273 // elements we want. 274 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 275 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 276 "Cannot narrow, it would be a lossy transformation"); 277 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 278 DAG.getIntPtrConstant(0)); 279 } 280 281 // Vector/Vector bitcast. 282 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 283 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 284 285 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 286 "Cannot handle this kind of promotion"); 287 // Promoted vector extract 288 bool Smaller = ValueVT.bitsLE(PartVT); 289 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 290 DL, ValueVT, Val); 291 292 } 293 294 // Trivial bitcast if the types are the same size and the destination 295 // vector type is legal. 296 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 297 TLI.isTypeLegal(ValueVT)) 298 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 299 300 // Handle cases such as i8 -> <1 x i1> 301 assert(ValueVT.getVectorNumElements() == 1 && 302 "Only trivial scalar-to-vector conversions should get here!"); 303 304 if (ValueVT.getVectorNumElements() == 1 && 305 ValueVT.getVectorElementType() != PartVT) { 306 bool Smaller = ValueVT.bitsLE(PartVT); 307 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 308 DL, ValueVT.getScalarType(), Val); 309 } 310 311 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 312} 313 314 315 316 317static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 318 SDValue Val, SDValue *Parts, unsigned NumParts, 319 EVT PartVT); 320 321/// getCopyToParts - Create a series of nodes that contain the specified value 322/// split into legal parts. If the parts contain more bits than Val, then, for 323/// integers, ExtendKind can be used to specify how to generate the extra bits. 324static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 325 SDValue Val, SDValue *Parts, unsigned NumParts, 326 EVT PartVT, 327 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 328 EVT ValueVT = Val.getValueType(); 329 330 // Handle the vector case separately. 331 if (ValueVT.isVector()) 332 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 333 334 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 335 unsigned PartBits = PartVT.getSizeInBits(); 336 unsigned OrigNumParts = NumParts; 337 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 338 339 if (NumParts == 0) 340 return; 341 342 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 343 if (PartVT == ValueVT) { 344 assert(NumParts == 1 && "No-op copy with multiple parts!"); 345 Parts[0] = Val; 346 return; 347 } 348 349 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 350 // If the parts cover more bits than the value has, promote the value. 351 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 352 assert(NumParts == 1 && "Do not know what to promote to!"); 353 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 354 } else { 355 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 356 ValueVT.isInteger() && 357 "Unknown mismatch!"); 358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 360 if (PartVT == MVT::x86mmx) 361 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 362 } 363 } else if (PartBits == ValueVT.getSizeInBits()) { 364 // Different types of the same size. 365 assert(NumParts == 1 && PartVT != ValueVT); 366 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 367 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 368 // If the parts cover less bits than value has, truncate the value. 369 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 370 ValueVT.isInteger() && 371 "Unknown mismatch!"); 372 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 373 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 374 if (PartVT == MVT::x86mmx) 375 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 376 } 377 378 // The value may have changed - recompute ValueVT. 379 ValueVT = Val.getValueType(); 380 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 381 "Failed to tile the value with PartVT!"); 382 383 if (NumParts == 1) { 384 assert(PartVT == ValueVT && "Type conversion failed!"); 385 Parts[0] = Val; 386 return; 387 } 388 389 // Expand the value into multiple parts. 390 if (NumParts & (NumParts - 1)) { 391 // The number of parts is not a power of 2. Split off and copy the tail. 392 assert(PartVT.isInteger() && ValueVT.isInteger() && 393 "Do not know what to expand to!"); 394 unsigned RoundParts = 1 << Log2_32(NumParts); 395 unsigned RoundBits = RoundParts * PartBits; 396 unsigned OddParts = NumParts - RoundParts; 397 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 398 DAG.getIntPtrConstant(RoundBits)); 399 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 400 401 if (TLI.isBigEndian()) 402 // The odd parts were reversed by getCopyToParts - unreverse them. 403 std::reverse(Parts + RoundParts, Parts + NumParts); 404 405 NumParts = RoundParts; 406 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 407 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 408 } 409 410 // The number of parts is a power of 2. Repeatedly bisect the value using 411 // EXTRACT_ELEMENT. 412 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 413 EVT::getIntegerVT(*DAG.getContext(), 414 ValueVT.getSizeInBits()), 415 Val); 416 417 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 418 for (unsigned i = 0; i < NumParts; i += StepSize) { 419 unsigned ThisBits = StepSize * PartBits / 2; 420 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 421 SDValue &Part0 = Parts[i]; 422 SDValue &Part1 = Parts[i+StepSize/2]; 423 424 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 425 ThisVT, Part0, DAG.getIntPtrConstant(1)); 426 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 427 ThisVT, Part0, DAG.getIntPtrConstant(0)); 428 429 if (ThisBits == PartBits && ThisVT != PartVT) { 430 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 431 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 432 } 433 } 434 } 435 436 if (TLI.isBigEndian()) 437 std::reverse(Parts, Parts + OrigNumParts); 438} 439 440 441/// getCopyToPartsVector - Create a series of nodes that contain the specified 442/// value split into legal parts. 443static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 444 SDValue Val, SDValue *Parts, unsigned NumParts, 445 EVT PartVT) { 446 EVT ValueVT = Val.getValueType(); 447 assert(ValueVT.isVector() && "Not a vector"); 448 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 449 450 if (NumParts == 1) { 451 if (PartVT == ValueVT) { 452 // Nothing to do. 453 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 454 // Bitconvert vector->vector case. 455 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 456 } else if (PartVT.isVector() && 457 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 458 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 459 EVT ElementVT = PartVT.getVectorElementType(); 460 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 461 // undef elements. 462 SmallVector<SDValue, 16> Ops; 463 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 464 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 465 ElementVT, Val, DAG.getIntPtrConstant(i))); 466 467 for (unsigned i = ValueVT.getVectorNumElements(), 468 e = PartVT.getVectorNumElements(); i != e; ++i) 469 Ops.push_back(DAG.getUNDEF(ElementVT)); 470 471 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 472 473 // FIXME: Use CONCAT for 2x -> 4x. 474 475 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 476 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 477 } else if (PartVT.isVector() && 478 PartVT.getVectorElementType().bitsGE( 479 ValueVT.getVectorElementType()) && 480 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 481 482 // Promoted vector extract 483 bool Smaller = PartVT.bitsLE(ValueVT); 484 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 485 DL, PartVT, Val); 486 } else{ 487 // Vector -> scalar conversion. 488 assert(ValueVT.getVectorNumElements() == 1 && 489 "Only trivial vector-to-scalar conversions should get here!"); 490 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 491 PartVT, Val, DAG.getIntPtrConstant(0)); 492 493 bool Smaller = ValueVT.bitsLE(PartVT); 494 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 495 DL, PartVT, Val); 496 } 497 498 Parts[0] = Val; 499 return; 500 } 501 502 // Handle a multi-element vector. 503 EVT IntermediateVT, RegisterVT; 504 unsigned NumIntermediates; 505 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 506 IntermediateVT, 507 NumIntermediates, RegisterVT); 508 unsigned NumElements = ValueVT.getVectorNumElements(); 509 510 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 511 NumParts = NumRegs; // Silence a compiler warning. 512 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 513 514 // Split the vector into intermediate operands. 515 SmallVector<SDValue, 8> Ops(NumIntermediates); 516 for (unsigned i = 0; i != NumIntermediates; ++i) { 517 if (IntermediateVT.isVector()) 518 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 519 IntermediateVT, Val, 520 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 521 else 522 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 523 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 524 } 525 526 // Split the intermediate operands into legal parts. 527 if (NumParts == NumIntermediates) { 528 // If the register was not expanded, promote or copy the value, 529 // as appropriate. 530 for (unsigned i = 0; i != NumParts; ++i) 531 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 532 } else if (NumParts > 0) { 533 // If the intermediate type was expanded, split each the value into 534 // legal parts. 535 assert(NumParts % NumIntermediates == 0 && 536 "Must expand into a divisible number of parts!"); 537 unsigned Factor = NumParts / NumIntermediates; 538 for (unsigned i = 0; i != NumIntermediates; ++i) 539 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 540 } 541} 542 543 544 545 546namespace { 547 /// RegsForValue - This struct represents the registers (physical or virtual) 548 /// that a particular set of values is assigned, and the type information 549 /// about the value. The most common situation is to represent one value at a 550 /// time, but struct or array values are handled element-wise as multiple 551 /// values. The splitting of aggregates is performed recursively, so that we 552 /// never have aggregate-typed registers. The values at this point do not 553 /// necessarily have legal types, so each value may require one or more 554 /// registers of some legal type. 555 /// 556 struct RegsForValue { 557 /// ValueVTs - The value types of the values, which may not be legal, and 558 /// may need be promoted or synthesized from one or more registers. 559 /// 560 SmallVector<EVT, 4> ValueVTs; 561 562 /// RegVTs - The value types of the registers. This is the same size as 563 /// ValueVTs and it records, for each value, what the type of the assigned 564 /// register or registers are. (Individual values are never synthesized 565 /// from more than one type of register.) 566 /// 567 /// With virtual registers, the contents of RegVTs is redundant with TLI's 568 /// getRegisterType member function, however when with physical registers 569 /// it is necessary to have a separate record of the types. 570 /// 571 SmallVector<EVT, 4> RegVTs; 572 573 /// Regs - This list holds the registers assigned to the values. 574 /// Each legal or promoted value requires one register, and each 575 /// expanded value requires multiple registers. 576 /// 577 SmallVector<unsigned, 4> Regs; 578 579 RegsForValue() {} 580 581 RegsForValue(const SmallVector<unsigned, 4> ®s, 582 EVT regvt, EVT valuevt) 583 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 584 585 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 586 unsigned Reg, Type *Ty) { 587 ComputeValueVTs(tli, Ty, ValueVTs); 588 589 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 590 EVT ValueVT = ValueVTs[Value]; 591 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 592 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 593 for (unsigned i = 0; i != NumRegs; ++i) 594 Regs.push_back(Reg + i); 595 RegVTs.push_back(RegisterVT); 596 Reg += NumRegs; 597 } 598 } 599 600 /// areValueTypesLegal - Return true if types of all the values are legal. 601 bool areValueTypesLegal(const TargetLowering &TLI) { 602 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 603 EVT RegisterVT = RegVTs[Value]; 604 if (!TLI.isTypeLegal(RegisterVT)) 605 return false; 606 } 607 return true; 608 } 609 610 /// append - Add the specified values to this one. 611 void append(const RegsForValue &RHS) { 612 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 613 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 614 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 615 } 616 617 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 618 /// this value and returns the result as a ValueVTs value. This uses 619 /// Chain/Flag as the input and updates them for the output Chain/Flag. 620 /// If the Flag pointer is NULL, no flag is used. 621 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 622 DebugLoc dl, 623 SDValue &Chain, SDValue *Flag) const; 624 625 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 626 /// specified value into the registers specified by this object. This uses 627 /// Chain/Flag as the input and updates them for the output Chain/Flag. 628 /// If the Flag pointer is NULL, no flag is used. 629 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 630 SDValue &Chain, SDValue *Flag) const; 631 632 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 633 /// operand list. This adds the code marker, matching input operand index 634 /// (if applicable), and includes the number of values added into it. 635 void AddInlineAsmOperands(unsigned Kind, 636 bool HasMatching, unsigned MatchingIdx, 637 SelectionDAG &DAG, 638 std::vector<SDValue> &Ops) const; 639 }; 640} 641 642/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 643/// this value and returns the result as a ValueVT value. This uses 644/// Chain/Flag as the input and updates them for the output Chain/Flag. 645/// If the Flag pointer is NULL, no flag is used. 646SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 647 FunctionLoweringInfo &FuncInfo, 648 DebugLoc dl, 649 SDValue &Chain, SDValue *Flag) const { 650 // A Value with type {} or [0 x %t] needs no registers. 651 if (ValueVTs.empty()) 652 return SDValue(); 653 654 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 655 656 // Assemble the legal parts into the final values. 657 SmallVector<SDValue, 4> Values(ValueVTs.size()); 658 SmallVector<SDValue, 8> Parts; 659 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 660 // Copy the legal parts from the registers. 661 EVT ValueVT = ValueVTs[Value]; 662 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 663 EVT RegisterVT = RegVTs[Value]; 664 665 Parts.resize(NumRegs); 666 for (unsigned i = 0; i != NumRegs; ++i) { 667 SDValue P; 668 if (Flag == 0) { 669 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 670 } else { 671 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 672 *Flag = P.getValue(2); 673 } 674 675 Chain = P.getValue(1); 676 Parts[i] = P; 677 678 // If the source register was virtual and if we know something about it, 679 // add an assert node. 680 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 681 !RegisterVT.isInteger() || RegisterVT.isVector()) 682 continue; 683 684 const FunctionLoweringInfo::LiveOutInfo *LOI = 685 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 686 if (!LOI) 687 continue; 688 689 unsigned RegSize = RegisterVT.getSizeInBits(); 690 unsigned NumSignBits = LOI->NumSignBits; 691 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 692 693 // FIXME: We capture more information than the dag can represent. For 694 // now, just use the tightest assertzext/assertsext possible. 695 bool isSExt = true; 696 EVT FromVT(MVT::Other); 697 if (NumSignBits == RegSize) 698 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 699 else if (NumZeroBits >= RegSize-1) 700 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 701 else if (NumSignBits > RegSize-8) 702 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 703 else if (NumZeroBits >= RegSize-8) 704 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 705 else if (NumSignBits > RegSize-16) 706 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 707 else if (NumZeroBits >= RegSize-16) 708 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 709 else if (NumSignBits > RegSize-32) 710 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 711 else if (NumZeroBits >= RegSize-32) 712 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 713 else 714 continue; 715 716 // Add an assertion node. 717 assert(FromVT != MVT::Other); 718 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 719 RegisterVT, P, DAG.getValueType(FromVT)); 720 } 721 722 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 723 NumRegs, RegisterVT, ValueVT); 724 Part += NumRegs; 725 Parts.clear(); 726 } 727 728 return DAG.getNode(ISD::MERGE_VALUES, dl, 729 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 730 &Values[0], ValueVTs.size()); 731} 732 733/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 734/// specified value into the registers specified by this object. This uses 735/// Chain/Flag as the input and updates them for the output Chain/Flag. 736/// If the Flag pointer is NULL, no flag is used. 737void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 738 SDValue &Chain, SDValue *Flag) const { 739 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 740 741 // Get the list of the values's legal parts. 742 unsigned NumRegs = Regs.size(); 743 SmallVector<SDValue, 8> Parts(NumRegs); 744 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 745 EVT ValueVT = ValueVTs[Value]; 746 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 747 EVT RegisterVT = RegVTs[Value]; 748 749 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 750 &Parts[Part], NumParts, RegisterVT); 751 Part += NumParts; 752 } 753 754 // Copy the parts into the registers. 755 SmallVector<SDValue, 8> Chains(NumRegs); 756 for (unsigned i = 0; i != NumRegs; ++i) { 757 SDValue Part; 758 if (Flag == 0) { 759 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 760 } else { 761 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 762 *Flag = Part.getValue(1); 763 } 764 765 Chains[i] = Part.getValue(0); 766 } 767 768 if (NumRegs == 1 || Flag) 769 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 770 // flagged to it. That is the CopyToReg nodes and the user are considered 771 // a single scheduling unit. If we create a TokenFactor and return it as 772 // chain, then the TokenFactor is both a predecessor (operand) of the 773 // user as well as a successor (the TF operands are flagged to the user). 774 // c1, f1 = CopyToReg 775 // c2, f2 = CopyToReg 776 // c3 = TokenFactor c1, c2 777 // ... 778 // = op c3, ..., f2 779 Chain = Chains[NumRegs-1]; 780 else 781 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 782} 783 784/// AddInlineAsmOperands - Add this value to the specified inlineasm node 785/// operand list. This adds the code marker and includes the number of 786/// values added into it. 787void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 788 unsigned MatchingIdx, 789 SelectionDAG &DAG, 790 std::vector<SDValue> &Ops) const { 791 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 792 793 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 794 if (HasMatching) 795 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 796 else if (!Regs.empty() && 797 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 798 // Put the register class of the virtual registers in the flag word. That 799 // way, later passes can recompute register class constraints for inline 800 // assembly as well as normal instructions. 801 // Don't do this for tied operands that can use the regclass information 802 // from the def. 803 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 804 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 805 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 806 } 807 808 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 809 Ops.push_back(Res); 810 811 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 812 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 813 EVT RegisterVT = RegVTs[Value]; 814 for (unsigned i = 0; i != NumRegs; ++i) { 815 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 816 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 817 } 818 } 819} 820 821void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 822 const TargetLibraryInfo *li) { 823 AA = &aa; 824 GFI = gfi; 825 LibInfo = li; 826 TD = DAG.getTarget().getTargetData(); 827 LPadToCallSiteMap.clear(); 828} 829 830/// clear - Clear out the current SelectionDAG and the associated 831/// state and prepare this SelectionDAGBuilder object to be used 832/// for a new block. This doesn't clear out information about 833/// additional blocks that are needed to complete switch lowering 834/// or PHI node updating; that information is cleared out as it is 835/// consumed. 836void SelectionDAGBuilder::clear() { 837 NodeMap.clear(); 838 UnusedArgNodeMap.clear(); 839 PendingLoads.clear(); 840 PendingExports.clear(); 841 CurDebugLoc = DebugLoc(); 842 HasTailCall = false; 843} 844 845/// clearDanglingDebugInfo - Clear the dangling debug information 846/// map. This function is seperated from the clear so that debug 847/// information that is dangling in a basic block can be properly 848/// resolved in a different basic block. This allows the 849/// SelectionDAG to resolve dangling debug information attached 850/// to PHI nodes. 851void SelectionDAGBuilder::clearDanglingDebugInfo() { 852 DanglingDebugInfoMap.clear(); 853} 854 855/// getRoot - Return the current virtual root of the Selection DAG, 856/// flushing any PendingLoad items. This must be done before emitting 857/// a store or any other node that may need to be ordered after any 858/// prior load instructions. 859/// 860SDValue SelectionDAGBuilder::getRoot() { 861 if (PendingLoads.empty()) 862 return DAG.getRoot(); 863 864 if (PendingLoads.size() == 1) { 865 SDValue Root = PendingLoads[0]; 866 DAG.setRoot(Root); 867 PendingLoads.clear(); 868 return Root; 869 } 870 871 // Otherwise, we have to make a token factor node. 872 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 873 &PendingLoads[0], PendingLoads.size()); 874 PendingLoads.clear(); 875 DAG.setRoot(Root); 876 return Root; 877} 878 879/// getControlRoot - Similar to getRoot, but instead of flushing all the 880/// PendingLoad items, flush all the PendingExports items. It is necessary 881/// to do this before emitting a terminator instruction. 882/// 883SDValue SelectionDAGBuilder::getControlRoot() { 884 SDValue Root = DAG.getRoot(); 885 886 if (PendingExports.empty()) 887 return Root; 888 889 // Turn all of the CopyToReg chains into one factored node. 890 if (Root.getOpcode() != ISD::EntryToken) { 891 unsigned i = 0, e = PendingExports.size(); 892 for (; i != e; ++i) { 893 assert(PendingExports[i].getNode()->getNumOperands() > 1); 894 if (PendingExports[i].getNode()->getOperand(0) == Root) 895 break; // Don't add the root if we already indirectly depend on it. 896 } 897 898 if (i == e) 899 PendingExports.push_back(Root); 900 } 901 902 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 903 &PendingExports[0], 904 PendingExports.size()); 905 PendingExports.clear(); 906 DAG.setRoot(Root); 907 return Root; 908} 909 910void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 911 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 912 DAG.AssignOrdering(Node, SDNodeOrder); 913 914 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 915 AssignOrderingToNode(Node->getOperand(I).getNode()); 916} 917 918void SelectionDAGBuilder::visit(const Instruction &I) { 919 // Set up outgoing PHI node register values before emitting the terminator. 920 if (isa<TerminatorInst>(&I)) 921 HandlePHINodesInSuccessorBlocks(I.getParent()); 922 923 CurDebugLoc = I.getDebugLoc(); 924 925 visit(I.getOpcode(), I); 926 927 if (!isa<TerminatorInst>(&I) && !HasTailCall) 928 CopyToExportRegsIfNeeded(&I); 929 930 CurDebugLoc = DebugLoc(); 931} 932 933void SelectionDAGBuilder::visitPHI(const PHINode &) { 934 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 935} 936 937void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 938 // Note: this doesn't use InstVisitor, because it has to work with 939 // ConstantExpr's in addition to instructions. 940 switch (Opcode) { 941 default: llvm_unreachable("Unknown instruction type encountered!"); 942 // Build the switch statement using the Instruction.def file. 943#define HANDLE_INST(NUM, OPCODE, CLASS) \ 944 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 945#include "llvm/Instruction.def" 946 } 947 948 // Assign the ordering to the freshly created DAG nodes. 949 if (NodeMap.count(&I)) { 950 ++SDNodeOrder; 951 AssignOrderingToNode(getValue(&I).getNode()); 952 } 953} 954 955// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 956// generate the debug data structures now that we've seen its definition. 957void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 958 SDValue Val) { 959 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 960 if (DDI.getDI()) { 961 const DbgValueInst *DI = DDI.getDI(); 962 DebugLoc dl = DDI.getdl(); 963 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 964 MDNode *Variable = DI->getVariable(); 965 uint64_t Offset = DI->getOffset(); 966 SDDbgValue *SDV; 967 if (Val.getNode()) { 968 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 969 SDV = DAG.getDbgValue(Variable, Val.getNode(), 970 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 971 DAG.AddDbgValue(SDV, Val.getNode(), false); 972 } 973 } else 974 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 975 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 976 } 977} 978 979/// getValue - Return an SDValue for the given Value. 980SDValue SelectionDAGBuilder::getValue(const Value *V) { 981 // If we already have an SDValue for this value, use it. It's important 982 // to do this first, so that we don't create a CopyFromReg if we already 983 // have a regular SDValue. 984 SDValue &N = NodeMap[V]; 985 if (N.getNode()) return N; 986 987 // If there's a virtual register allocated and initialized for this 988 // value, use it. 989 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 990 if (It != FuncInfo.ValueMap.end()) { 991 unsigned InReg = It->second; 992 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 993 SDValue Chain = DAG.getEntryNode(); 994 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 995 resolveDanglingDebugInfo(V, N); 996 return N; 997 } 998 999 // Otherwise create a new SDValue and remember it. 1000 SDValue Val = getValueImpl(V); 1001 NodeMap[V] = Val; 1002 resolveDanglingDebugInfo(V, Val); 1003 return Val; 1004} 1005 1006/// getNonRegisterValue - Return an SDValue for the given Value, but 1007/// don't look in FuncInfo.ValueMap for a virtual register. 1008SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1009 // If we already have an SDValue for this value, use it. 1010 SDValue &N = NodeMap[V]; 1011 if (N.getNode()) return N; 1012 1013 // Otherwise create a new SDValue and remember it. 1014 SDValue Val = getValueImpl(V); 1015 NodeMap[V] = Val; 1016 resolveDanglingDebugInfo(V, Val); 1017 return Val; 1018} 1019 1020/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1021/// Create an SDValue for the given value. 1022SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1023 if (const Constant *C = dyn_cast<Constant>(V)) { 1024 EVT VT = TLI.getValueType(V->getType(), true); 1025 1026 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1027 return DAG.getConstant(*CI, VT); 1028 1029 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1030 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1031 1032 if (isa<ConstantPointerNull>(C)) 1033 return DAG.getConstant(0, TLI.getPointerTy()); 1034 1035 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1036 return DAG.getConstantFP(*CFP, VT); 1037 1038 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1039 return DAG.getUNDEF(VT); 1040 1041 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1042 visit(CE->getOpcode(), *CE); 1043 SDValue N1 = NodeMap[V]; 1044 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1045 return N1; 1046 } 1047 1048 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1049 SmallVector<SDValue, 4> Constants; 1050 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1051 OI != OE; ++OI) { 1052 SDNode *Val = getValue(*OI).getNode(); 1053 // If the operand is an empty aggregate, there are no values. 1054 if (!Val) continue; 1055 // Add each leaf value from the operand to the Constants list 1056 // to form a flattened list of all the values. 1057 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1058 Constants.push_back(SDValue(Val, i)); 1059 } 1060 1061 return DAG.getMergeValues(&Constants[0], Constants.size(), 1062 getCurDebugLoc()); 1063 } 1064 1065 if (const ConstantDataSequential *CDS = 1066 dyn_cast<ConstantDataSequential>(C)) { 1067 SmallVector<SDValue, 4> Ops; 1068 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { 1069 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1070 // Add each leaf value from the operand to the Constants list 1071 // to form a flattened list of all the values. 1072 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1073 Ops.push_back(SDValue(Val, i)); 1074 } 1075 1076 if (isa<ArrayType>(CDS->getType())) 1077 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc()); 1078 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1079 VT, &Ops[0], Ops.size()); 1080 } 1081 1082 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1083 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1084 "Unknown struct or array constant!"); 1085 1086 SmallVector<EVT, 4> ValueVTs; 1087 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1088 unsigned NumElts = ValueVTs.size(); 1089 if (NumElts == 0) 1090 return SDValue(); // empty struct 1091 SmallVector<SDValue, 4> Constants(NumElts); 1092 for (unsigned i = 0; i != NumElts; ++i) { 1093 EVT EltVT = ValueVTs[i]; 1094 if (isa<UndefValue>(C)) 1095 Constants[i] = DAG.getUNDEF(EltVT); 1096 else if (EltVT.isFloatingPoint()) 1097 Constants[i] = DAG.getConstantFP(0, EltVT); 1098 else 1099 Constants[i] = DAG.getConstant(0, EltVT); 1100 } 1101 1102 return DAG.getMergeValues(&Constants[0], NumElts, 1103 getCurDebugLoc()); 1104 } 1105 1106 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1107 return DAG.getBlockAddress(BA, VT); 1108 1109 VectorType *VecTy = cast<VectorType>(V->getType()); 1110 unsigned NumElements = VecTy->getNumElements(); 1111 1112 // Now that we know the number and type of the elements, get that number of 1113 // elements into the Ops array based on what kind of constant it is. 1114 SmallVector<SDValue, 16> Ops; 1115 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1116 for (unsigned i = 0; i != NumElements; ++i) 1117 Ops.push_back(getValue(CV->getOperand(i))); 1118 } else { 1119 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1120 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1121 1122 SDValue Op; 1123 if (EltVT.isFloatingPoint()) 1124 Op = DAG.getConstantFP(0, EltVT); 1125 else 1126 Op = DAG.getConstant(0, EltVT); 1127 Ops.assign(NumElements, Op); 1128 } 1129 1130 // Create a BUILD_VECTOR node. 1131 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1132 VT, &Ops[0], Ops.size()); 1133 } 1134 1135 // If this is a static alloca, generate it as the frameindex instead of 1136 // computation. 1137 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1138 DenseMap<const AllocaInst*, int>::iterator SI = 1139 FuncInfo.StaticAllocaMap.find(AI); 1140 if (SI != FuncInfo.StaticAllocaMap.end()) 1141 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1142 } 1143 1144 // If this is an instruction which fast-isel has deferred, select it now. 1145 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1146 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1147 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1148 SDValue Chain = DAG.getEntryNode(); 1149 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1150 } 1151 1152 llvm_unreachable("Can't get register for value!"); 1153} 1154 1155void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1156 SDValue Chain = getControlRoot(); 1157 SmallVector<ISD::OutputArg, 8> Outs; 1158 SmallVector<SDValue, 8> OutVals; 1159 1160 if (!FuncInfo.CanLowerReturn) { 1161 unsigned DemoteReg = FuncInfo.DemoteRegister; 1162 const Function *F = I.getParent()->getParent(); 1163 1164 // Emit a store of the return value through the virtual register. 1165 // Leave Outs empty so that LowerReturn won't try to load return 1166 // registers the usual way. 1167 SmallVector<EVT, 1> PtrValueVTs; 1168 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1169 PtrValueVTs); 1170 1171 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1172 SDValue RetOp = getValue(I.getOperand(0)); 1173 1174 SmallVector<EVT, 4> ValueVTs; 1175 SmallVector<uint64_t, 4> Offsets; 1176 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1177 unsigned NumValues = ValueVTs.size(); 1178 1179 SmallVector<SDValue, 4> Chains(NumValues); 1180 for (unsigned i = 0; i != NumValues; ++i) { 1181 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1182 RetPtr.getValueType(), RetPtr, 1183 DAG.getIntPtrConstant(Offsets[i])); 1184 Chains[i] = 1185 DAG.getStore(Chain, getCurDebugLoc(), 1186 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1187 // FIXME: better loc info would be nice. 1188 Add, MachinePointerInfo(), false, false, 0); 1189 } 1190 1191 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1192 MVT::Other, &Chains[0], NumValues); 1193 } else if (I.getNumOperands() != 0) { 1194 SmallVector<EVT, 4> ValueVTs; 1195 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1196 unsigned NumValues = ValueVTs.size(); 1197 if (NumValues) { 1198 SDValue RetOp = getValue(I.getOperand(0)); 1199 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1200 EVT VT = ValueVTs[j]; 1201 1202 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1203 1204 const Function *F = I.getParent()->getParent(); 1205 if (F->paramHasAttr(0, Attribute::SExt)) 1206 ExtendKind = ISD::SIGN_EXTEND; 1207 else if (F->paramHasAttr(0, Attribute::ZExt)) 1208 ExtendKind = ISD::ZERO_EXTEND; 1209 1210 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1211 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1212 1213 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1214 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1215 SmallVector<SDValue, 4> Parts(NumParts); 1216 getCopyToParts(DAG, getCurDebugLoc(), 1217 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1218 &Parts[0], NumParts, PartVT, ExtendKind); 1219 1220 // 'inreg' on function refers to return value 1221 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1222 if (F->paramHasAttr(0, Attribute::InReg)) 1223 Flags.setInReg(); 1224 1225 // Propagate extension type if any 1226 if (ExtendKind == ISD::SIGN_EXTEND) 1227 Flags.setSExt(); 1228 else if (ExtendKind == ISD::ZERO_EXTEND) 1229 Flags.setZExt(); 1230 1231 for (unsigned i = 0; i < NumParts; ++i) { 1232 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1233 /*isfixed=*/true)); 1234 OutVals.push_back(Parts[i]); 1235 } 1236 } 1237 } 1238 } 1239 1240 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1241 CallingConv::ID CallConv = 1242 DAG.getMachineFunction().getFunction()->getCallingConv(); 1243 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1244 Outs, OutVals, getCurDebugLoc(), DAG); 1245 1246 // Verify that the target's LowerReturn behaved as expected. 1247 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1248 "LowerReturn didn't return a valid chain!"); 1249 1250 // Update the DAG with the new chain value resulting from return lowering. 1251 DAG.setRoot(Chain); 1252} 1253 1254/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1255/// created for it, emit nodes to copy the value into the virtual 1256/// registers. 1257void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1258 // Skip empty types 1259 if (V->getType()->isEmptyTy()) 1260 return; 1261 1262 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1263 if (VMI != FuncInfo.ValueMap.end()) { 1264 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1265 CopyValueToVirtualRegister(V, VMI->second); 1266 } 1267} 1268 1269/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1270/// the current basic block, add it to ValueMap now so that we'll get a 1271/// CopyTo/FromReg. 1272void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1273 // No need to export constants. 1274 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1275 1276 // Already exported? 1277 if (FuncInfo.isExportedInst(V)) return; 1278 1279 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1280 CopyValueToVirtualRegister(V, Reg); 1281} 1282 1283bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1284 const BasicBlock *FromBB) { 1285 // The operands of the setcc have to be in this block. We don't know 1286 // how to export them from some other block. 1287 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1288 // Can export from current BB. 1289 if (VI->getParent() == FromBB) 1290 return true; 1291 1292 // Is already exported, noop. 1293 return FuncInfo.isExportedInst(V); 1294 } 1295 1296 // If this is an argument, we can export it if the BB is the entry block or 1297 // if it is already exported. 1298 if (isa<Argument>(V)) { 1299 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1300 return true; 1301 1302 // Otherwise, can only export this if it is already exported. 1303 return FuncInfo.isExportedInst(V); 1304 } 1305 1306 // Otherwise, constants can always be exported. 1307 return true; 1308} 1309 1310/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1311uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1312 const MachineBasicBlock *Dst) const { 1313 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1314 if (!BPI) 1315 return 0; 1316 const BasicBlock *SrcBB = Src->getBasicBlock(); 1317 const BasicBlock *DstBB = Dst->getBasicBlock(); 1318 return BPI->getEdgeWeight(SrcBB, DstBB); 1319} 1320 1321void SelectionDAGBuilder:: 1322addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1323 uint32_t Weight /* = 0 */) { 1324 if (!Weight) 1325 Weight = getEdgeWeight(Src, Dst); 1326 Src->addSuccessor(Dst, Weight); 1327} 1328 1329 1330static bool InBlock(const Value *V, const BasicBlock *BB) { 1331 if (const Instruction *I = dyn_cast<Instruction>(V)) 1332 return I->getParent() == BB; 1333 return true; 1334} 1335 1336/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1337/// This function emits a branch and is used at the leaves of an OR or an 1338/// AND operator tree. 1339/// 1340void 1341SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1342 MachineBasicBlock *TBB, 1343 MachineBasicBlock *FBB, 1344 MachineBasicBlock *CurBB, 1345 MachineBasicBlock *SwitchBB) { 1346 const BasicBlock *BB = CurBB->getBasicBlock(); 1347 1348 // If the leaf of the tree is a comparison, merge the condition into 1349 // the caseblock. 1350 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1351 // The operands of the cmp have to be in this block. We don't know 1352 // how to export them from some other block. If this is the first block 1353 // of the sequence, no exporting is needed. 1354 if (CurBB == SwitchBB || 1355 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1356 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1357 ISD::CondCode Condition; 1358 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1359 Condition = getICmpCondCode(IC->getPredicate()); 1360 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1361 Condition = getFCmpCondCode(FC->getPredicate()); 1362 if (TM.Options.NoNaNsFPMath) 1363 Condition = getFCmpCodeWithoutNaN(Condition); 1364 } else { 1365 Condition = ISD::SETEQ; // silence warning. 1366 llvm_unreachable("Unknown compare instruction"); 1367 } 1368 1369 CaseBlock CB(Condition, BOp->getOperand(0), 1370 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1371 SwitchCases.push_back(CB); 1372 return; 1373 } 1374 } 1375 1376 // Create a CaseBlock record representing this branch. 1377 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1378 NULL, TBB, FBB, CurBB); 1379 SwitchCases.push_back(CB); 1380} 1381 1382/// FindMergedConditions - If Cond is an expression like 1383void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1384 MachineBasicBlock *TBB, 1385 MachineBasicBlock *FBB, 1386 MachineBasicBlock *CurBB, 1387 MachineBasicBlock *SwitchBB, 1388 unsigned Opc) { 1389 // If this node is not part of the or/and tree, emit it as a branch. 1390 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1391 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1392 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1393 BOp->getParent() != CurBB->getBasicBlock() || 1394 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1395 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1396 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1397 return; 1398 } 1399 1400 // Create TmpBB after CurBB. 1401 MachineFunction::iterator BBI = CurBB; 1402 MachineFunction &MF = DAG.getMachineFunction(); 1403 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1404 CurBB->getParent()->insert(++BBI, TmpBB); 1405 1406 if (Opc == Instruction::Or) { 1407 // Codegen X | Y as: 1408 // jmp_if_X TBB 1409 // jmp TmpBB 1410 // TmpBB: 1411 // jmp_if_Y TBB 1412 // jmp FBB 1413 // 1414 1415 // Emit the LHS condition. 1416 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1417 1418 // Emit the RHS condition into TmpBB. 1419 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1420 } else { 1421 assert(Opc == Instruction::And && "Unknown merge op!"); 1422 // Codegen X & Y as: 1423 // jmp_if_X TmpBB 1424 // jmp FBB 1425 // TmpBB: 1426 // jmp_if_Y TBB 1427 // jmp FBB 1428 // 1429 // This requires creation of TmpBB after CurBB. 1430 1431 // Emit the LHS condition. 1432 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1433 1434 // Emit the RHS condition into TmpBB. 1435 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1436 } 1437} 1438 1439/// If the set of cases should be emitted as a series of branches, return true. 1440/// If we should emit this as a bunch of and/or'd together conditions, return 1441/// false. 1442bool 1443SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1444 if (Cases.size() != 2) return true; 1445 1446 // If this is two comparisons of the same values or'd or and'd together, they 1447 // will get folded into a single comparison, so don't emit two blocks. 1448 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1449 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1450 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1451 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1452 return false; 1453 } 1454 1455 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1456 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1457 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1458 Cases[0].CC == Cases[1].CC && 1459 isa<Constant>(Cases[0].CmpRHS) && 1460 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1461 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1462 return false; 1463 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1464 return false; 1465 } 1466 1467 return true; 1468} 1469 1470void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1471 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1472 1473 // Update machine-CFG edges. 1474 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1475 1476 // Figure out which block is immediately after the current one. 1477 MachineBasicBlock *NextBlock = 0; 1478 MachineFunction::iterator BBI = BrMBB; 1479 if (++BBI != FuncInfo.MF->end()) 1480 NextBlock = BBI; 1481 1482 if (I.isUnconditional()) { 1483 // Update machine-CFG edges. 1484 BrMBB->addSuccessor(Succ0MBB); 1485 1486 // If this is not a fall-through branch, emit the branch. 1487 if (Succ0MBB != NextBlock) 1488 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1489 MVT::Other, getControlRoot(), 1490 DAG.getBasicBlock(Succ0MBB))); 1491 1492 return; 1493 } 1494 1495 // If this condition is one of the special cases we handle, do special stuff 1496 // now. 1497 const Value *CondVal = I.getCondition(); 1498 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1499 1500 // If this is a series of conditions that are or'd or and'd together, emit 1501 // this as a sequence of branches instead of setcc's with and/or operations. 1502 // As long as jumps are not expensive, this should improve performance. 1503 // For example, instead of something like: 1504 // cmp A, B 1505 // C = seteq 1506 // cmp D, E 1507 // F = setle 1508 // or C, F 1509 // jnz foo 1510 // Emit: 1511 // cmp A, B 1512 // je foo 1513 // cmp D, E 1514 // jle foo 1515 // 1516 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1517 if (!TLI.isJumpExpensive() && 1518 BOp->hasOneUse() && 1519 (BOp->getOpcode() == Instruction::And || 1520 BOp->getOpcode() == Instruction::Or)) { 1521 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1522 BOp->getOpcode()); 1523 // If the compares in later blocks need to use values not currently 1524 // exported from this block, export them now. This block should always 1525 // be the first entry. 1526 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1527 1528 // Allow some cases to be rejected. 1529 if (ShouldEmitAsBranches(SwitchCases)) { 1530 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1531 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1532 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1533 } 1534 1535 // Emit the branch for this block. 1536 visitSwitchCase(SwitchCases[0], BrMBB); 1537 SwitchCases.erase(SwitchCases.begin()); 1538 return; 1539 } 1540 1541 // Okay, we decided not to do this, remove any inserted MBB's and clear 1542 // SwitchCases. 1543 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1544 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1545 1546 SwitchCases.clear(); 1547 } 1548 } 1549 1550 // Create a CaseBlock record representing this branch. 1551 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1552 NULL, Succ0MBB, Succ1MBB, BrMBB); 1553 1554 // Use visitSwitchCase to actually insert the fast branch sequence for this 1555 // cond branch. 1556 visitSwitchCase(CB, BrMBB); 1557} 1558 1559/// visitSwitchCase - Emits the necessary code to represent a single node in 1560/// the binary search tree resulting from lowering a switch instruction. 1561void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1562 MachineBasicBlock *SwitchBB) { 1563 SDValue Cond; 1564 SDValue CondLHS = getValue(CB.CmpLHS); 1565 DebugLoc dl = getCurDebugLoc(); 1566 1567 // Build the setcc now. 1568 if (CB.CmpMHS == NULL) { 1569 // Fold "(X == true)" to X and "(X == false)" to !X to 1570 // handle common cases produced by branch lowering. 1571 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1572 CB.CC == ISD::SETEQ) 1573 Cond = CondLHS; 1574 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1575 CB.CC == ISD::SETEQ) { 1576 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1577 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1578 } else 1579 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1580 } else { 1581 assert(CB.CC == ISD::SETCC_INVALID && 1582 "Condition is undefined for to-the-range belonging check."); 1583 1584 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1585 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1586 1587 SDValue CmpOp = getValue(CB.CmpMHS); 1588 EVT VT = CmpOp.getValueType(); 1589 1590 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) { 1591 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1592 ISD::SETULE); 1593 } else { 1594 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1595 VT, CmpOp, DAG.getConstant(Low, VT)); 1596 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1597 DAG.getConstant(High-Low, VT), ISD::SETULE); 1598 } 1599 } 1600 1601 // Update successor info 1602 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1603 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1604 1605 // Set NextBlock to be the MBB immediately after the current one, if any. 1606 // This is used to avoid emitting unnecessary branches to the next block. 1607 MachineBasicBlock *NextBlock = 0; 1608 MachineFunction::iterator BBI = SwitchBB; 1609 if (++BBI != FuncInfo.MF->end()) 1610 NextBlock = BBI; 1611 1612 // If the lhs block is the next block, invert the condition so that we can 1613 // fall through to the lhs instead of the rhs block. 1614 if (CB.TrueBB == NextBlock) { 1615 std::swap(CB.TrueBB, CB.FalseBB); 1616 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1617 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1618 } 1619 1620 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1621 MVT::Other, getControlRoot(), Cond, 1622 DAG.getBasicBlock(CB.TrueBB)); 1623 1624 // Insert the false branch. Do this even if it's a fall through branch, 1625 // this makes it easier to do DAG optimizations which require inverting 1626 // the branch condition. 1627 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1628 DAG.getBasicBlock(CB.FalseBB)); 1629 1630 DAG.setRoot(BrCond); 1631} 1632 1633/// visitJumpTable - Emit JumpTable node in the current MBB 1634void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1635 // Emit the code for the jump table 1636 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1637 EVT PTy = TLI.getPointerTy(); 1638 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1639 JT.Reg, PTy); 1640 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1641 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1642 MVT::Other, Index.getValue(1), 1643 Table, Index); 1644 DAG.setRoot(BrJumpTable); 1645} 1646 1647/// visitJumpTableHeader - This function emits necessary code to produce index 1648/// in the JumpTable from switch case. 1649void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1650 JumpTableHeader &JTH, 1651 MachineBasicBlock *SwitchBB) { 1652 // Subtract the lowest switch case value from the value being switched on and 1653 // conditional branch to default mbb if the result is greater than the 1654 // difference between smallest and largest cases. 1655 SDValue SwitchOp = getValue(JTH.SValue); 1656 EVT VT = SwitchOp.getValueType(); 1657 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1658 DAG.getConstant(JTH.First, VT)); 1659 1660 // The SDNode we just created, which holds the value being switched on minus 1661 // the smallest case value, needs to be copied to a virtual register so it 1662 // can be used as an index into the jump table in a subsequent basic block. 1663 // This value may be smaller or larger than the target's pointer type, and 1664 // therefore require extension or truncating. 1665 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1666 1667 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1668 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1669 JumpTableReg, SwitchOp); 1670 JT.Reg = JumpTableReg; 1671 1672 // Emit the range check for the jump table, and branch to the default block 1673 // for the switch statement if the value being switched on exceeds the largest 1674 // case in the switch. 1675 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1676 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1677 DAG.getConstant(JTH.Last-JTH.First,VT), 1678 ISD::SETUGT); 1679 1680 // Set NextBlock to be the MBB immediately after the current one, if any. 1681 // This is used to avoid emitting unnecessary branches to the next block. 1682 MachineBasicBlock *NextBlock = 0; 1683 MachineFunction::iterator BBI = SwitchBB; 1684 1685 if (++BBI != FuncInfo.MF->end()) 1686 NextBlock = BBI; 1687 1688 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1689 MVT::Other, CopyTo, CMP, 1690 DAG.getBasicBlock(JT.Default)); 1691 1692 if (JT.MBB != NextBlock) 1693 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1694 DAG.getBasicBlock(JT.MBB)); 1695 1696 DAG.setRoot(BrCond); 1697} 1698 1699/// visitBitTestHeader - This function emits necessary code to produce value 1700/// suitable for "bit tests" 1701void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1702 MachineBasicBlock *SwitchBB) { 1703 // Subtract the minimum value 1704 SDValue SwitchOp = getValue(B.SValue); 1705 EVT VT = SwitchOp.getValueType(); 1706 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1707 DAG.getConstant(B.First, VT)); 1708 1709 // Check range 1710 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1711 TLI.getSetCCResultType(Sub.getValueType()), 1712 Sub, DAG.getConstant(B.Range, VT), 1713 ISD::SETUGT); 1714 1715 // Determine the type of the test operands. 1716 bool UsePtrType = false; 1717 if (!TLI.isTypeLegal(VT)) 1718 UsePtrType = true; 1719 else { 1720 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1721 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1722 // Switch table case range are encoded into series of masks. 1723 // Just use pointer type, it's guaranteed to fit. 1724 UsePtrType = true; 1725 break; 1726 } 1727 } 1728 if (UsePtrType) { 1729 VT = TLI.getPointerTy(); 1730 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1731 } 1732 1733 B.RegVT = VT; 1734 B.Reg = FuncInfo.CreateReg(VT); 1735 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1736 B.Reg, Sub); 1737 1738 // Set NextBlock to be the MBB immediately after the current one, if any. 1739 // This is used to avoid emitting unnecessary branches to the next block. 1740 MachineBasicBlock *NextBlock = 0; 1741 MachineFunction::iterator BBI = SwitchBB; 1742 if (++BBI != FuncInfo.MF->end()) 1743 NextBlock = BBI; 1744 1745 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1746 1747 addSuccessorWithWeight(SwitchBB, B.Default); 1748 addSuccessorWithWeight(SwitchBB, MBB); 1749 1750 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1751 MVT::Other, CopyTo, RangeCmp, 1752 DAG.getBasicBlock(B.Default)); 1753 1754 if (MBB != NextBlock) 1755 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1756 DAG.getBasicBlock(MBB)); 1757 1758 DAG.setRoot(BrRange); 1759} 1760 1761/// visitBitTestCase - this function produces one "bit test" 1762void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1763 MachineBasicBlock* NextMBB, 1764 unsigned Reg, 1765 BitTestCase &B, 1766 MachineBasicBlock *SwitchBB) { 1767 EVT VT = BB.RegVT; 1768 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1769 Reg, VT); 1770 SDValue Cmp; 1771 unsigned PopCount = CountPopulation_64(B.Mask); 1772 if (PopCount == 1) { 1773 // Testing for a single bit; just compare the shift count with what it 1774 // would need to be to shift a 1 bit in that position. 1775 Cmp = DAG.getSetCC(getCurDebugLoc(), 1776 TLI.getSetCCResultType(VT), 1777 ShiftOp, 1778 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1779 ISD::SETEQ); 1780 } else if (PopCount == BB.Range) { 1781 // There is only one zero bit in the range, test for it directly. 1782 Cmp = DAG.getSetCC(getCurDebugLoc(), 1783 TLI.getSetCCResultType(VT), 1784 ShiftOp, 1785 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1786 ISD::SETNE); 1787 } else { 1788 // Make desired shift 1789 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1790 DAG.getConstant(1, VT), ShiftOp); 1791 1792 // Emit bit tests and jumps 1793 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1794 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1795 Cmp = DAG.getSetCC(getCurDebugLoc(), 1796 TLI.getSetCCResultType(VT), 1797 AndOp, DAG.getConstant(0, VT), 1798 ISD::SETNE); 1799 } 1800 1801 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1802 addSuccessorWithWeight(SwitchBB, NextMBB); 1803 1804 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1805 MVT::Other, getControlRoot(), 1806 Cmp, DAG.getBasicBlock(B.TargetBB)); 1807 1808 // Set NextBlock to be the MBB immediately after the current one, if any. 1809 // This is used to avoid emitting unnecessary branches to the next block. 1810 MachineBasicBlock *NextBlock = 0; 1811 MachineFunction::iterator BBI = SwitchBB; 1812 if (++BBI != FuncInfo.MF->end()) 1813 NextBlock = BBI; 1814 1815 if (NextMBB != NextBlock) 1816 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1817 DAG.getBasicBlock(NextMBB)); 1818 1819 DAG.setRoot(BrAnd); 1820} 1821 1822void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1823 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1824 1825 // Retrieve successors. 1826 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1827 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1828 1829 const Value *Callee(I.getCalledValue()); 1830 if (isa<InlineAsm>(Callee)) 1831 visitInlineAsm(&I); 1832 else 1833 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1834 1835 // If the value of the invoke is used outside of its defining block, make it 1836 // available as a virtual register. 1837 CopyToExportRegsIfNeeded(&I); 1838 1839 // Update successor info 1840 addSuccessorWithWeight(InvokeMBB, Return); 1841 addSuccessorWithWeight(InvokeMBB, LandingPad); 1842 1843 // Drop into normal successor. 1844 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1845 MVT::Other, getControlRoot(), 1846 DAG.getBasicBlock(Return))); 1847} 1848 1849void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1850 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1851} 1852 1853void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1854 assert(FuncInfo.MBB->isLandingPad() && 1855 "Call to landingpad not in landing pad!"); 1856 1857 MachineBasicBlock *MBB = FuncInfo.MBB; 1858 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1859 AddLandingPadInfo(LP, MMI, MBB); 1860 1861 // If there aren't registers to copy the values into (e.g., during SjLj 1862 // exceptions), then don't bother to create these DAG nodes. 1863 if (TLI.getExceptionPointerRegister() == 0 && 1864 TLI.getExceptionSelectorRegister() == 0) 1865 return; 1866 1867 SmallVector<EVT, 2> ValueVTs; 1868 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1869 1870 // Insert the EXCEPTIONADDR instruction. 1871 assert(FuncInfo.MBB->isLandingPad() && 1872 "Call to eh.exception not in landing pad!"); 1873 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1874 SDValue Ops[2]; 1875 Ops[0] = DAG.getRoot(); 1876 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1877 SDValue Chain = Op1.getValue(1); 1878 1879 // Insert the EHSELECTION instruction. 1880 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1881 Ops[0] = Op1; 1882 Ops[1] = Chain; 1883 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1884 Chain = Op2.getValue(1); 1885 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1886 1887 Ops[0] = Op1; 1888 Ops[1] = Op2; 1889 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1890 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1891 &Ops[0], 2); 1892 1893 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1894 setValue(&LP, RetPair.first); 1895 DAG.setRoot(RetPair.second); 1896} 1897 1898/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1899/// small case ranges). 1900bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1901 CaseRecVector& WorkList, 1902 const Value* SV, 1903 MachineBasicBlock *Default, 1904 MachineBasicBlock *SwitchBB) { 1905 Case& BackCase = *(CR.Range.second-1); 1906 1907 // Size is the number of Cases represented by this range. 1908 size_t Size = CR.Range.second - CR.Range.first; 1909 if (Size > 3) 1910 return false; 1911 1912 // Get the MachineFunction which holds the current MBB. This is used when 1913 // inserting any additional MBBs necessary to represent the switch. 1914 MachineFunction *CurMF = FuncInfo.MF; 1915 1916 // Figure out which block is immediately after the current one. 1917 MachineBasicBlock *NextBlock = 0; 1918 MachineFunction::iterator BBI = CR.CaseBB; 1919 1920 if (++BBI != FuncInfo.MF->end()) 1921 NextBlock = BBI; 1922 1923 // If any two of the cases has the same destination, and if one value 1924 // is the same as the other, but has one bit unset that the other has set, 1925 // use bit manipulation to do two compares at once. For example: 1926 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1927 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1928 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1929 if (Size == 2 && CR.CaseBB == SwitchBB) { 1930 Case &Small = *CR.Range.first; 1931 Case &Big = *(CR.Range.second-1); 1932 1933 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1934 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1935 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1936 1937 // Check that there is only one bit different. 1938 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1939 (SmallValue | BigValue) == BigValue) { 1940 // Isolate the common bit. 1941 APInt CommonBit = BigValue & ~SmallValue; 1942 assert((SmallValue | CommonBit) == BigValue && 1943 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1944 1945 SDValue CondLHS = getValue(SV); 1946 EVT VT = CondLHS.getValueType(); 1947 DebugLoc DL = getCurDebugLoc(); 1948 1949 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1950 DAG.getConstant(CommonBit, VT)); 1951 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1952 Or, DAG.getConstant(BigValue, VT), 1953 ISD::SETEQ); 1954 1955 // Update successor info. 1956 addSuccessorWithWeight(SwitchBB, Small.BB); 1957 addSuccessorWithWeight(SwitchBB, Default); 1958 1959 // Insert the true branch. 1960 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1961 getControlRoot(), Cond, 1962 DAG.getBasicBlock(Small.BB)); 1963 1964 // Insert the false branch. 1965 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1966 DAG.getBasicBlock(Default)); 1967 1968 DAG.setRoot(BrCond); 1969 return true; 1970 } 1971 } 1972 } 1973 1974 // Rearrange the case blocks so that the last one falls through if possible. 1975 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1976 // The last case block won't fall through into 'NextBlock' if we emit the 1977 // branches in this order. See if rearranging a case value would help. 1978 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1979 if (I->BB == NextBlock) { 1980 std::swap(*I, BackCase); 1981 break; 1982 } 1983 } 1984 } 1985 1986 // Create a CaseBlock record representing a conditional branch to 1987 // the Case's target mbb if the value being switched on SV is equal 1988 // to C. 1989 MachineBasicBlock *CurBlock = CR.CaseBB; 1990 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1991 MachineBasicBlock *FallThrough; 1992 if (I != E-1) { 1993 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1994 CurMF->insert(BBI, FallThrough); 1995 1996 // Put SV in a virtual register to make it available from the new blocks. 1997 ExportFromCurrentBlock(SV); 1998 } else { 1999 // If the last case doesn't match, go to the default block. 2000 FallThrough = Default; 2001 } 2002 2003 const Value *RHS, *LHS, *MHS; 2004 ISD::CondCode CC; 2005 if (I->High == I->Low) { 2006 // This is just small small case range :) containing exactly 1 case 2007 CC = ISD::SETEQ; 2008 LHS = SV; RHS = I->High; MHS = NULL; 2009 } else { 2010 CC = ISD::SETCC_INVALID; 2011 LHS = I->Low; MHS = SV; RHS = I->High; 2012 } 2013 2014 uint32_t ExtraWeight = I->ExtraWeight; 2015 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 2016 /* me */ CurBlock, 2017 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2); 2018 2019 // If emitting the first comparison, just call visitSwitchCase to emit the 2020 // code into the current block. Otherwise, push the CaseBlock onto the 2021 // vector to be later processed by SDISel, and insert the node's MBB 2022 // before the next MBB. 2023 if (CurBlock == SwitchBB) 2024 visitSwitchCase(CB, SwitchBB); 2025 else 2026 SwitchCases.push_back(CB); 2027 2028 CurBlock = FallThrough; 2029 } 2030 2031 return true; 2032} 2033 2034static inline bool areJTsAllowed(const TargetLowering &TLI) { 2035 return !TLI.getTargetMachine().Options.DisableJumpTables && 2036 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2037 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2038} 2039 2040static APInt ComputeRange(const APInt &First, const APInt &Last) { 2041 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2042 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth); 2043 return (LastExt - FirstExt + 1ULL); 2044} 2045 2046/// handleJTSwitchCase - Emit jumptable for current switch case range 2047bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2048 CaseRecVector &WorkList, 2049 const Value *SV, 2050 MachineBasicBlock *Default, 2051 MachineBasicBlock *SwitchBB) { 2052 Case& FrontCase = *CR.Range.first; 2053 Case& BackCase = *(CR.Range.second-1); 2054 2055 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2056 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2057 2058 APInt TSize(First.getBitWidth(), 0); 2059 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2060 TSize += I->size(); 2061 2062 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2063 return false; 2064 2065 APInt Range = ComputeRange(First, Last); 2066 // The density is TSize / Range. Require at least 40%. 2067 // It should not be possible for IntTSize to saturate for sane code, but make 2068 // sure we handle Range saturation correctly. 2069 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2070 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2071 if (IntTSize * 10 < IntRange * 4) 2072 return false; 2073 2074 DEBUG(dbgs() << "Lowering jump table\n" 2075 << "First entry: " << First << ". Last entry: " << Last << '\n' 2076 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2077 2078 // Get the MachineFunction which holds the current MBB. This is used when 2079 // inserting any additional MBBs necessary to represent the switch. 2080 MachineFunction *CurMF = FuncInfo.MF; 2081 2082 // Figure out which block is immediately after the current one. 2083 MachineFunction::iterator BBI = CR.CaseBB; 2084 ++BBI; 2085 2086 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2087 2088 // Create a new basic block to hold the code for loading the address 2089 // of the jump table, and jumping to it. Update successor information; 2090 // we will either branch to the default case for the switch, or the jump 2091 // table. 2092 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2093 CurMF->insert(BBI, JumpTableBB); 2094 2095 addSuccessorWithWeight(CR.CaseBB, Default); 2096 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2097 2098 // Build a vector of destination BBs, corresponding to each target 2099 // of the jump table. If the value of the jump table slot corresponds to 2100 // a case statement, push the case's BB onto the vector, otherwise, push 2101 // the default BB. 2102 std::vector<MachineBasicBlock*> DestBBs; 2103 APInt TEI = First; 2104 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2105 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2106 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2107 2108 if (Low.ule(TEI) && TEI.ule(High)) { 2109 DestBBs.push_back(I->BB); 2110 if (TEI==High) 2111 ++I; 2112 } else { 2113 DestBBs.push_back(Default); 2114 } 2115 } 2116 2117 // Update successor info. Add one edge to each unique successor. 2118 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2119 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2120 E = DestBBs.end(); I != E; ++I) { 2121 if (!SuccsHandled[(*I)->getNumber()]) { 2122 SuccsHandled[(*I)->getNumber()] = true; 2123 addSuccessorWithWeight(JumpTableBB, *I); 2124 } 2125 } 2126 2127 // Create a jump table index for this jump table. 2128 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2129 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2130 ->createJumpTableIndex(DestBBs); 2131 2132 // Set the jump table information so that we can codegen it as a second 2133 // MachineBasicBlock 2134 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2135 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2136 if (CR.CaseBB == SwitchBB) 2137 visitJumpTableHeader(JT, JTH, SwitchBB); 2138 2139 JTCases.push_back(JumpTableBlock(JTH, JT)); 2140 return true; 2141} 2142 2143/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2144/// 2 subtrees. 2145bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2146 CaseRecVector& WorkList, 2147 const Value* SV, 2148 MachineBasicBlock *Default, 2149 MachineBasicBlock *SwitchBB) { 2150 // Get the MachineFunction which holds the current MBB. This is used when 2151 // inserting any additional MBBs necessary to represent the switch. 2152 MachineFunction *CurMF = FuncInfo.MF; 2153 2154 // Figure out which block is immediately after the current one. 2155 MachineFunction::iterator BBI = CR.CaseBB; 2156 ++BBI; 2157 2158 Case& FrontCase = *CR.Range.first; 2159 Case& BackCase = *(CR.Range.second-1); 2160 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2161 2162 // Size is the number of Cases represented by this range. 2163 unsigned Size = CR.Range.second - CR.Range.first; 2164 2165 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2166 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2167 double FMetric = 0; 2168 CaseItr Pivot = CR.Range.first + Size/2; 2169 2170 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2171 // (heuristically) allow us to emit JumpTable's later. 2172 APInt TSize(First.getBitWidth(), 0); 2173 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2174 I!=E; ++I) 2175 TSize += I->size(); 2176 2177 APInt LSize = FrontCase.size(); 2178 APInt RSize = TSize-LSize; 2179 DEBUG(dbgs() << "Selecting best pivot: \n" 2180 << "First: " << First << ", Last: " << Last <<'\n' 2181 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2182 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2183 J!=E; ++I, ++J) { 2184 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2185 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2186 APInt Range = ComputeRange(LEnd, RBegin); 2187 assert((Range - 2ULL).isNonNegative() && 2188 "Invalid case distance"); 2189 // Use volatile double here to avoid excess precision issues on some hosts, 2190 // e.g. that use 80-bit X87 registers. 2191 volatile double LDensity = 2192 (double)LSize.roundToDouble() / 2193 (LEnd - First + 1ULL).roundToDouble(); 2194 volatile double RDensity = 2195 (double)RSize.roundToDouble() / 2196 (Last - RBegin + 1ULL).roundToDouble(); 2197 double Metric = Range.logBase2()*(LDensity+RDensity); 2198 // Should always split in some non-trivial place 2199 DEBUG(dbgs() <<"=>Step\n" 2200 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2201 << "LDensity: " << LDensity 2202 << ", RDensity: " << RDensity << '\n' 2203 << "Metric: " << Metric << '\n'); 2204 if (FMetric < Metric) { 2205 Pivot = J; 2206 FMetric = Metric; 2207 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2208 } 2209 2210 LSize += J->size(); 2211 RSize -= J->size(); 2212 } 2213 if (areJTsAllowed(TLI)) { 2214 // If our case is dense we *really* should handle it earlier! 2215 assert((FMetric > 0) && "Should handle dense range earlier!"); 2216 } else { 2217 Pivot = CR.Range.first + Size/2; 2218 } 2219 2220 CaseRange LHSR(CR.Range.first, Pivot); 2221 CaseRange RHSR(Pivot, CR.Range.second); 2222 const Constant *C = Pivot->Low; 2223 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2224 2225 // We know that we branch to the LHS if the Value being switched on is 2226 // less than the Pivot value, C. We use this to optimize our binary 2227 // tree a bit, by recognizing that if SV is greater than or equal to the 2228 // LHS's Case Value, and that Case Value is exactly one less than the 2229 // Pivot's Value, then we can branch directly to the LHS's Target, 2230 // rather than creating a leaf node for it. 2231 if ((LHSR.second - LHSR.first) == 1 && 2232 LHSR.first->High == CR.GE && 2233 cast<ConstantInt>(C)->getValue() == 2234 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2235 TrueBB = LHSR.first->BB; 2236 } else { 2237 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2238 CurMF->insert(BBI, TrueBB); 2239 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2240 2241 // Put SV in a virtual register to make it available from the new blocks. 2242 ExportFromCurrentBlock(SV); 2243 } 2244 2245 // Similar to the optimization above, if the Value being switched on is 2246 // known to be less than the Constant CR.LT, and the current Case Value 2247 // is CR.LT - 1, then we can branch directly to the target block for 2248 // the current Case Value, rather than emitting a RHS leaf node for it. 2249 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2250 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2251 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2252 FalseBB = RHSR.first->BB; 2253 } else { 2254 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2255 CurMF->insert(BBI, FalseBB); 2256 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2257 2258 // Put SV in a virtual register to make it available from the new blocks. 2259 ExportFromCurrentBlock(SV); 2260 } 2261 2262 // Create a CaseBlock record representing a conditional branch to 2263 // the LHS node if the value being switched on SV is less than C. 2264 // Otherwise, branch to LHS. 2265 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2266 2267 if (CR.CaseBB == SwitchBB) 2268 visitSwitchCase(CB, SwitchBB); 2269 else 2270 SwitchCases.push_back(CB); 2271 2272 return true; 2273} 2274 2275/// handleBitTestsSwitchCase - if current case range has few destination and 2276/// range span less, than machine word bitwidth, encode case range into series 2277/// of masks and emit bit tests with these masks. 2278bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2279 CaseRecVector& WorkList, 2280 const Value* SV, 2281 MachineBasicBlock* Default, 2282 MachineBasicBlock *SwitchBB){ 2283 EVT PTy = TLI.getPointerTy(); 2284 unsigned IntPtrBits = PTy.getSizeInBits(); 2285 2286 Case& FrontCase = *CR.Range.first; 2287 Case& BackCase = *(CR.Range.second-1); 2288 2289 // Get the MachineFunction which holds the current MBB. This is used when 2290 // inserting any additional MBBs necessary to represent the switch. 2291 MachineFunction *CurMF = FuncInfo.MF; 2292 2293 // If target does not have legal shift left, do not emit bit tests at all. 2294 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2295 return false; 2296 2297 size_t numCmps = 0; 2298 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2299 I!=E; ++I) { 2300 // Single case counts one, case range - two. 2301 numCmps += (I->Low == I->High ? 1 : 2); 2302 } 2303 2304 // Count unique destinations 2305 SmallSet<MachineBasicBlock*, 4> Dests; 2306 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2307 Dests.insert(I->BB); 2308 if (Dests.size() > 3) 2309 // Don't bother the code below, if there are too much unique destinations 2310 return false; 2311 } 2312 DEBUG(dbgs() << "Total number of unique destinations: " 2313 << Dests.size() << '\n' 2314 << "Total number of comparisons: " << numCmps << '\n'); 2315 2316 // Compute span of values. 2317 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2318 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2319 APInt cmpRange = maxValue - minValue; 2320 2321 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2322 << "Low bound: " << minValue << '\n' 2323 << "High bound: " << maxValue << '\n'); 2324 2325 if (cmpRange.uge(IntPtrBits) || 2326 (!(Dests.size() == 1 && numCmps >= 3) && 2327 !(Dests.size() == 2 && numCmps >= 5) && 2328 !(Dests.size() >= 3 && numCmps >= 6))) 2329 return false; 2330 2331 DEBUG(dbgs() << "Emitting bit tests\n"); 2332 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2333 2334 // Optimize the case where all the case values fit in a 2335 // word without having to subtract minValue. In this case, 2336 // we can optimize away the subtraction. 2337 if (maxValue.ult(IntPtrBits)) { 2338 cmpRange = maxValue; 2339 } else { 2340 lowBound = minValue; 2341 } 2342 2343 CaseBitsVector CasesBits; 2344 unsigned i, count = 0; 2345 2346 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2347 MachineBasicBlock* Dest = I->BB; 2348 for (i = 0; i < count; ++i) 2349 if (Dest == CasesBits[i].BB) 2350 break; 2351 2352 if (i == count) { 2353 assert((count < 3) && "Too much destinations to test!"); 2354 CasesBits.push_back(CaseBits(0, Dest, 0)); 2355 count++; 2356 } 2357 2358 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2359 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2360 2361 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2362 uint64_t hi = (highValue - lowBound).getZExtValue(); 2363 2364 for (uint64_t j = lo; j <= hi; j++) { 2365 CasesBits[i].Mask |= 1ULL << j; 2366 CasesBits[i].Bits++; 2367 } 2368 2369 } 2370 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2371 2372 BitTestInfo BTC; 2373 2374 // Figure out which block is immediately after the current one. 2375 MachineFunction::iterator BBI = CR.CaseBB; 2376 ++BBI; 2377 2378 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2379 2380 DEBUG(dbgs() << "Cases:\n"); 2381 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2382 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2383 << ", Bits: " << CasesBits[i].Bits 2384 << ", BB: " << CasesBits[i].BB << '\n'); 2385 2386 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2387 CurMF->insert(BBI, CaseBB); 2388 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2389 CaseBB, 2390 CasesBits[i].BB)); 2391 2392 // Put SV in a virtual register to make it available from the new blocks. 2393 ExportFromCurrentBlock(SV); 2394 } 2395 2396 BitTestBlock BTB(lowBound, cmpRange, SV, 2397 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2398 CR.CaseBB, Default, BTC); 2399 2400 if (CR.CaseBB == SwitchBB) 2401 visitBitTestHeader(BTB, SwitchBB); 2402 2403 BitTestCases.push_back(BTB); 2404 2405 return true; 2406} 2407 2408/// Clusterify - Transform simple list of Cases into list of CaseRange's 2409size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2410 const SwitchInst& SI) { 2411 size_t numCmps = 0; 2412 2413 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2414 // Start with "simple" cases 2415 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end(); 2416 i != e; ++i) { 2417 const BasicBlock *SuccBB = i.getCaseSuccessor(); 2418 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2419 2420 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0; 2421 2422 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(), 2423 SMBB, ExtraWeight)); 2424 } 2425 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2426 2427 // Merge case into clusters 2428 if (Cases.size() >= 2) 2429 // Must recompute end() each iteration because it may be 2430 // invalidated by erase if we hold on to it 2431 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2432 J != Cases.end(); ) { 2433 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2434 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2435 MachineBasicBlock* nextBB = J->BB; 2436 MachineBasicBlock* currentBB = I->BB; 2437 2438 // If the two neighboring cases go to the same destination, merge them 2439 // into a single case. 2440 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2441 I->High = J->High; 2442 J = Cases.erase(J); 2443 2444 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) { 2445 uint32_t CurWeight = currentBB->getBasicBlock() ? 2446 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16; 2447 uint32_t NextWeight = nextBB->getBasicBlock() ? 2448 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16; 2449 2450 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(), 2451 CurWeight + NextWeight); 2452 } 2453 } else { 2454 I = J++; 2455 } 2456 } 2457 2458 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2459 if (I->Low != I->High) 2460 // A range counts double, since it requires two compares. 2461 ++numCmps; 2462 } 2463 2464 return numCmps; 2465} 2466 2467void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2468 MachineBasicBlock *Last) { 2469 // Update JTCases. 2470 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2471 if (JTCases[i].first.HeaderBB == First) 2472 JTCases[i].first.HeaderBB = Last; 2473 2474 // Update BitTestCases. 2475 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2476 if (BitTestCases[i].Parent == First) 2477 BitTestCases[i].Parent = Last; 2478} 2479 2480void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2481 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2482 2483 // Figure out which block is immediately after the current one. 2484 MachineBasicBlock *NextBlock = 0; 2485 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2486 2487 // If there is only the default destination, branch to it if it is not the 2488 // next basic block. Otherwise, just fall through. 2489 if (!SI.getNumCases()) { 2490 // Update machine-CFG edges. 2491 2492 // If this is not a fall-through branch, emit the branch. 2493 SwitchMBB->addSuccessor(Default); 2494 if (Default != NextBlock) 2495 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2496 MVT::Other, getControlRoot(), 2497 DAG.getBasicBlock(Default))); 2498 2499 return; 2500 } 2501 2502 // If there are any non-default case statements, create a vector of Cases 2503 // representing each one, and sort the vector so that we can efficiently 2504 // create a binary search tree from them. 2505 CaseVector Cases; 2506 size_t numCmps = Clusterify(Cases, SI); 2507 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2508 << ". Total compares: " << numCmps << '\n'); 2509 (void)numCmps; 2510 2511 // Get the Value to be switched on and default basic blocks, which will be 2512 // inserted into CaseBlock records, representing basic blocks in the binary 2513 // search tree. 2514 const Value *SV = SI.getCondition(); 2515 2516 // Push the initial CaseRec onto the worklist 2517 CaseRecVector WorkList; 2518 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2519 CaseRange(Cases.begin(),Cases.end()))); 2520 2521 while (!WorkList.empty()) { 2522 // Grab a record representing a case range to process off the worklist 2523 CaseRec CR = WorkList.back(); 2524 WorkList.pop_back(); 2525 2526 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2527 continue; 2528 2529 // If the range has few cases (two or less) emit a series of specific 2530 // tests. 2531 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2532 continue; 2533 2534 // If the switch has more than 5 blocks, and at least 40% dense, and the 2535 // target supports indirect branches, then emit a jump table rather than 2536 // lowering the switch to a binary tree of conditional branches. 2537 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2538 continue; 2539 2540 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2541 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2542 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2543 } 2544} 2545 2546void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2547 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2548 2549 // Update machine-CFG edges with unique successors. 2550 SmallVector<BasicBlock*, 32> succs; 2551 succs.reserve(I.getNumSuccessors()); 2552 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2553 succs.push_back(I.getSuccessor(i)); 2554 array_pod_sort(succs.begin(), succs.end()); 2555 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2556 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2557 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2558 addSuccessorWithWeight(IndirectBrMBB, Succ); 2559 } 2560 2561 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2562 MVT::Other, getControlRoot(), 2563 getValue(I.getAddress()))); 2564} 2565 2566void SelectionDAGBuilder::visitFSub(const User &I) { 2567 // -0.0 - X --> fneg 2568 Type *Ty = I.getType(); 2569 if (isa<Constant>(I.getOperand(0)) && 2570 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2571 SDValue Op2 = getValue(I.getOperand(1)); 2572 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2573 Op2.getValueType(), Op2)); 2574 return; 2575 } 2576 2577 visitBinary(I, ISD::FSUB); 2578} 2579 2580void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2581 SDValue Op1 = getValue(I.getOperand(0)); 2582 SDValue Op2 = getValue(I.getOperand(1)); 2583 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2584 Op1.getValueType(), Op1, Op2)); 2585} 2586 2587void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2588 SDValue Op1 = getValue(I.getOperand(0)); 2589 SDValue Op2 = getValue(I.getOperand(1)); 2590 2591 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2592 2593 // Coerce the shift amount to the right type if we can. 2594 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2595 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2596 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2597 DebugLoc DL = getCurDebugLoc(); 2598 2599 // If the operand is smaller than the shift count type, promote it. 2600 if (ShiftSize > Op2Size) 2601 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2602 2603 // If the operand is larger than the shift count type but the shift 2604 // count type has enough bits to represent any shift value, truncate 2605 // it now. This is a common case and it exposes the truncate to 2606 // optimization early. 2607 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2608 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2609 // Otherwise we'll need to temporarily settle for some other convenient 2610 // type. Type legalization will make adjustments once the shiftee is split. 2611 else 2612 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2613 } 2614 2615 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2616 Op1.getValueType(), Op1, Op2)); 2617} 2618 2619void SelectionDAGBuilder::visitSDiv(const User &I) { 2620 SDValue Op1 = getValue(I.getOperand(0)); 2621 SDValue Op2 = getValue(I.getOperand(1)); 2622 2623 // Turn exact SDivs into multiplications. 2624 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2625 // exact bit. 2626 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2627 !isa<ConstantSDNode>(Op1) && 2628 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2629 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2630 else 2631 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2632 Op1, Op2)); 2633} 2634 2635void SelectionDAGBuilder::visitICmp(const User &I) { 2636 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2637 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2638 predicate = IC->getPredicate(); 2639 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2640 predicate = ICmpInst::Predicate(IC->getPredicate()); 2641 SDValue Op1 = getValue(I.getOperand(0)); 2642 SDValue Op2 = getValue(I.getOperand(1)); 2643 ISD::CondCode Opcode = getICmpCondCode(predicate); 2644 2645 EVT DestVT = TLI.getValueType(I.getType()); 2646 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2647} 2648 2649void SelectionDAGBuilder::visitFCmp(const User &I) { 2650 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2651 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2652 predicate = FC->getPredicate(); 2653 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2654 predicate = FCmpInst::Predicate(FC->getPredicate()); 2655 SDValue Op1 = getValue(I.getOperand(0)); 2656 SDValue Op2 = getValue(I.getOperand(1)); 2657 ISD::CondCode Condition = getFCmpCondCode(predicate); 2658 if (TM.Options.NoNaNsFPMath) 2659 Condition = getFCmpCodeWithoutNaN(Condition); 2660 EVT DestVT = TLI.getValueType(I.getType()); 2661 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2662} 2663 2664void SelectionDAGBuilder::visitSelect(const User &I) { 2665 SmallVector<EVT, 4> ValueVTs; 2666 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2667 unsigned NumValues = ValueVTs.size(); 2668 if (NumValues == 0) return; 2669 2670 SmallVector<SDValue, 4> Values(NumValues); 2671 SDValue Cond = getValue(I.getOperand(0)); 2672 SDValue TrueVal = getValue(I.getOperand(1)); 2673 SDValue FalseVal = getValue(I.getOperand(2)); 2674 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2675 ISD::VSELECT : ISD::SELECT; 2676 2677 for (unsigned i = 0; i != NumValues; ++i) 2678 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2679 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2680 Cond, 2681 SDValue(TrueVal.getNode(), 2682 TrueVal.getResNo() + i), 2683 SDValue(FalseVal.getNode(), 2684 FalseVal.getResNo() + i)); 2685 2686 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2687 DAG.getVTList(&ValueVTs[0], NumValues), 2688 &Values[0], NumValues)); 2689} 2690 2691void SelectionDAGBuilder::visitTrunc(const User &I) { 2692 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2693 SDValue N = getValue(I.getOperand(0)); 2694 EVT DestVT = TLI.getValueType(I.getType()); 2695 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2696} 2697 2698void SelectionDAGBuilder::visitZExt(const User &I) { 2699 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2700 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2701 SDValue N = getValue(I.getOperand(0)); 2702 EVT DestVT = TLI.getValueType(I.getType()); 2703 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2704} 2705 2706void SelectionDAGBuilder::visitSExt(const User &I) { 2707 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2708 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2709 SDValue N = getValue(I.getOperand(0)); 2710 EVT DestVT = TLI.getValueType(I.getType()); 2711 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2712} 2713 2714void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2715 // FPTrunc is never a no-op cast, no need to check 2716 SDValue N = getValue(I.getOperand(0)); 2717 EVT DestVT = TLI.getValueType(I.getType()); 2718 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2719 DestVT, N, 2720 DAG.getTargetConstant(0, TLI.getPointerTy()))); 2721} 2722 2723void SelectionDAGBuilder::visitFPExt(const User &I){ 2724 // FPExt is never a no-op cast, no need to check 2725 SDValue N = getValue(I.getOperand(0)); 2726 EVT DestVT = TLI.getValueType(I.getType()); 2727 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2728} 2729 2730void SelectionDAGBuilder::visitFPToUI(const User &I) { 2731 // FPToUI is never a no-op cast, no need to check 2732 SDValue N = getValue(I.getOperand(0)); 2733 EVT DestVT = TLI.getValueType(I.getType()); 2734 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2735} 2736 2737void SelectionDAGBuilder::visitFPToSI(const User &I) { 2738 // FPToSI is never a no-op cast, no need to check 2739 SDValue N = getValue(I.getOperand(0)); 2740 EVT DestVT = TLI.getValueType(I.getType()); 2741 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2742} 2743 2744void SelectionDAGBuilder::visitUIToFP(const User &I) { 2745 // UIToFP is never a no-op cast, no need to check 2746 SDValue N = getValue(I.getOperand(0)); 2747 EVT DestVT = TLI.getValueType(I.getType()); 2748 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2749} 2750 2751void SelectionDAGBuilder::visitSIToFP(const User &I){ 2752 // SIToFP is never a no-op cast, no need to check 2753 SDValue N = getValue(I.getOperand(0)); 2754 EVT DestVT = TLI.getValueType(I.getType()); 2755 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2756} 2757 2758void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2759 // What to do depends on the size of the integer and the size of the pointer. 2760 // We can either truncate, zero extend, or no-op, accordingly. 2761 SDValue N = getValue(I.getOperand(0)); 2762 EVT DestVT = TLI.getValueType(I.getType()); 2763 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2764} 2765 2766void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2767 // What to do depends on the size of the integer and the size of the pointer. 2768 // We can either truncate, zero extend, or no-op, accordingly. 2769 SDValue N = getValue(I.getOperand(0)); 2770 EVT DestVT = TLI.getValueType(I.getType()); 2771 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2772} 2773 2774void SelectionDAGBuilder::visitBitCast(const User &I) { 2775 SDValue N = getValue(I.getOperand(0)); 2776 EVT DestVT = TLI.getValueType(I.getType()); 2777 2778 // BitCast assures us that source and destination are the same size so this is 2779 // either a BITCAST or a no-op. 2780 if (DestVT != N.getValueType()) 2781 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2782 DestVT, N)); // convert types. 2783 else 2784 setValue(&I, N); // noop cast. 2785} 2786 2787void SelectionDAGBuilder::visitInsertElement(const User &I) { 2788 SDValue InVec = getValue(I.getOperand(0)); 2789 SDValue InVal = getValue(I.getOperand(1)); 2790 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2791 TLI.getPointerTy(), 2792 getValue(I.getOperand(2))); 2793 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2794 TLI.getValueType(I.getType()), 2795 InVec, InVal, InIdx)); 2796} 2797 2798void SelectionDAGBuilder::visitExtractElement(const User &I) { 2799 SDValue InVec = getValue(I.getOperand(0)); 2800 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2801 TLI.getPointerTy(), 2802 getValue(I.getOperand(1))); 2803 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2804 TLI.getValueType(I.getType()), InVec, InIdx)); 2805} 2806 2807// Utility for visitShuffleVector - Return true if every element in Mask, 2808// begining from position Pos and ending in Pos+Size, falls within the 2809// specified sequential range [L, L+Pos). or is undef. 2810static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2811 unsigned Pos, unsigned Size, int Low) { 2812 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2813 if (Mask[i] >= 0 && Mask[i] != Low) 2814 return false; 2815 return true; 2816} 2817 2818void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2819 SDValue Src1 = getValue(I.getOperand(0)); 2820 SDValue Src2 = getValue(I.getOperand(1)); 2821 2822 SmallVector<int, 8> Mask; 2823 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); 2824 unsigned MaskNumElts = Mask.size(); 2825 2826 EVT VT = TLI.getValueType(I.getType()); 2827 EVT SrcVT = Src1.getValueType(); 2828 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2829 2830 if (SrcNumElts == MaskNumElts) { 2831 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2832 &Mask[0])); 2833 return; 2834 } 2835 2836 // Normalize the shuffle vector since mask and vector length don't match. 2837 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2838 // Mask is longer than the source vectors and is a multiple of the source 2839 // vectors. We can use concatenate vector to make the mask and vectors 2840 // lengths match. 2841 if (SrcNumElts*2 == MaskNumElts) { 2842 // First check for Src1 in low and Src2 in high 2843 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 2844 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 2845 // The shuffle is concatenating two vectors together. 2846 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2847 VT, Src1, Src2)); 2848 return; 2849 } 2850 // Then check for Src2 in low and Src1 in high 2851 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 2852 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 2853 // The shuffle is concatenating two vectors together. 2854 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2855 VT, Src2, Src1)); 2856 return; 2857 } 2858 } 2859 2860 // Pad both vectors with undefs to make them the same length as the mask. 2861 unsigned NumConcat = MaskNumElts / SrcNumElts; 2862 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2863 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2864 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2865 2866 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2867 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2868 MOps1[0] = Src1; 2869 MOps2[0] = Src2; 2870 2871 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2872 getCurDebugLoc(), VT, 2873 &MOps1[0], NumConcat); 2874 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2875 getCurDebugLoc(), VT, 2876 &MOps2[0], NumConcat); 2877 2878 // Readjust mask for new input vector length. 2879 SmallVector<int, 8> MappedOps; 2880 for (unsigned i = 0; i != MaskNumElts; ++i) { 2881 int Idx = Mask[i]; 2882 if (Idx >= (int)SrcNumElts) 2883 Idx -= SrcNumElts - MaskNumElts; 2884 MappedOps.push_back(Idx); 2885 } 2886 2887 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2888 &MappedOps[0])); 2889 return; 2890 } 2891 2892 if (SrcNumElts > MaskNumElts) { 2893 // Analyze the access pattern of the vector to see if we can extract 2894 // two subvectors and do the shuffle. The analysis is done by calculating 2895 // the range of elements the mask access on both vectors. 2896 int MinRange[2] = { static_cast<int>(SrcNumElts), 2897 static_cast<int>(SrcNumElts)}; 2898 int MaxRange[2] = {-1, -1}; 2899 2900 for (unsigned i = 0; i != MaskNumElts; ++i) { 2901 int Idx = Mask[i]; 2902 unsigned Input = 0; 2903 if (Idx < 0) 2904 continue; 2905 2906 if (Idx >= (int)SrcNumElts) { 2907 Input = 1; 2908 Idx -= SrcNumElts; 2909 } 2910 if (Idx > MaxRange[Input]) 2911 MaxRange[Input] = Idx; 2912 if (Idx < MinRange[Input]) 2913 MinRange[Input] = Idx; 2914 } 2915 2916 // Check if the access is smaller than the vector size and can we find 2917 // a reasonable extract index. 2918 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not 2919 // Extract. 2920 int StartIdx[2]; // StartIdx to extract from 2921 for (unsigned Input = 0; Input < 2; ++Input) { 2922 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) { 2923 RangeUse[Input] = 0; // Unused 2924 StartIdx[Input] = 0; 2925 continue; 2926 } 2927 2928 // Find a good start index that is a multiple of the mask length. Then 2929 // see if the rest of the elements are in range. 2930 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2931 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2932 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2933 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2934 } 2935 2936 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2937 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2938 return; 2939 } 2940 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) { 2941 // Extract appropriate subvector and generate a vector shuffle 2942 for (unsigned Input = 0; Input < 2; ++Input) { 2943 SDValue &Src = Input == 0 ? Src1 : Src2; 2944 if (RangeUse[Input] == 0) 2945 Src = DAG.getUNDEF(VT); 2946 else 2947 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2948 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2949 } 2950 2951 // Calculate new mask. 2952 SmallVector<int, 8> MappedOps; 2953 for (unsigned i = 0; i != MaskNumElts; ++i) { 2954 int Idx = Mask[i]; 2955 if (Idx >= 0) { 2956 if (Idx < (int)SrcNumElts) 2957 Idx -= StartIdx[0]; 2958 else 2959 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; 2960 } 2961 MappedOps.push_back(Idx); 2962 } 2963 2964 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2965 &MappedOps[0])); 2966 return; 2967 } 2968 } 2969 2970 // We can't use either concat vectors or extract subvectors so fall back to 2971 // replacing the shuffle with extract and build vector. 2972 // to insert and build vector. 2973 EVT EltVT = VT.getVectorElementType(); 2974 EVT PtrVT = TLI.getPointerTy(); 2975 SmallVector<SDValue,8> Ops; 2976 for (unsigned i = 0; i != MaskNumElts; ++i) { 2977 int Idx = Mask[i]; 2978 SDValue Res; 2979 2980 if (Idx < 0) { 2981 Res = DAG.getUNDEF(EltVT); 2982 } else { 2983 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; 2984 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; 2985 2986 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2987 EltVT, Src, DAG.getConstant(Idx, PtrVT)); 2988 } 2989 2990 Ops.push_back(Res); 2991 } 2992 2993 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2994 VT, &Ops[0], Ops.size())); 2995} 2996 2997void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2998 const Value *Op0 = I.getOperand(0); 2999 const Value *Op1 = I.getOperand(1); 3000 Type *AggTy = I.getType(); 3001 Type *ValTy = Op1->getType(); 3002 bool IntoUndef = isa<UndefValue>(Op0); 3003 bool FromUndef = isa<UndefValue>(Op1); 3004 3005 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3006 3007 SmallVector<EVT, 4> AggValueVTs; 3008 ComputeValueVTs(TLI, AggTy, AggValueVTs); 3009 SmallVector<EVT, 4> ValValueVTs; 3010 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3011 3012 unsigned NumAggValues = AggValueVTs.size(); 3013 unsigned NumValValues = ValValueVTs.size(); 3014 SmallVector<SDValue, 4> Values(NumAggValues); 3015 3016 SDValue Agg = getValue(Op0); 3017 unsigned i = 0; 3018 // Copy the beginning value(s) from the original aggregate. 3019 for (; i != LinearIndex; ++i) 3020 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3021 SDValue(Agg.getNode(), Agg.getResNo() + i); 3022 // Copy values from the inserted value(s). 3023 if (NumValValues) { 3024 SDValue Val = getValue(Op1); 3025 for (; i != LinearIndex + NumValValues; ++i) 3026 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3027 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3028 } 3029 // Copy remaining value(s) from the original aggregate. 3030 for (; i != NumAggValues; ++i) 3031 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3032 SDValue(Agg.getNode(), Agg.getResNo() + i); 3033 3034 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3035 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3036 &Values[0], NumAggValues)); 3037} 3038 3039void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3040 const Value *Op0 = I.getOperand(0); 3041 Type *AggTy = Op0->getType(); 3042 Type *ValTy = I.getType(); 3043 bool OutOfUndef = isa<UndefValue>(Op0); 3044 3045 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3046 3047 SmallVector<EVT, 4> ValValueVTs; 3048 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3049 3050 unsigned NumValValues = ValValueVTs.size(); 3051 3052 // Ignore a extractvalue that produces an empty object 3053 if (!NumValValues) { 3054 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3055 return; 3056 } 3057 3058 SmallVector<SDValue, 4> Values(NumValValues); 3059 3060 SDValue Agg = getValue(Op0); 3061 // Copy out the selected value(s). 3062 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3063 Values[i - LinearIndex] = 3064 OutOfUndef ? 3065 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3066 SDValue(Agg.getNode(), Agg.getResNo() + i); 3067 3068 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3069 DAG.getVTList(&ValValueVTs[0], NumValValues), 3070 &Values[0], NumValValues)); 3071} 3072 3073void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3074 SDValue N = getValue(I.getOperand(0)); 3075 // Note that the pointer operand may be a vector of pointers. Take the scalar 3076 // element which holds a pointer. 3077 Type *Ty = I.getOperand(0)->getType()->getScalarType(); 3078 3079 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3080 OI != E; ++OI) { 3081 const Value *Idx = *OI; 3082 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3083 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3084 if (Field) { 3085 // N = N + Offset 3086 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3087 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3088 DAG.getIntPtrConstant(Offset)); 3089 } 3090 3091 Ty = StTy->getElementType(Field); 3092 } else { 3093 Ty = cast<SequentialType>(Ty)->getElementType(); 3094 3095 // If this is a constant subscript, handle it quickly. 3096 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3097 if (CI->isZero()) continue; 3098 uint64_t Offs = 3099 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3100 SDValue OffsVal; 3101 EVT PTy = TLI.getPointerTy(); 3102 unsigned PtrBits = PTy.getSizeInBits(); 3103 if (PtrBits < 64) 3104 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3105 TLI.getPointerTy(), 3106 DAG.getConstant(Offs, MVT::i64)); 3107 else 3108 OffsVal = DAG.getIntPtrConstant(Offs); 3109 3110 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3111 OffsVal); 3112 continue; 3113 } 3114 3115 // N = N + Idx * ElementSize; 3116 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3117 TD->getTypeAllocSize(Ty)); 3118 SDValue IdxN = getValue(Idx); 3119 3120 // If the index is smaller or larger than intptr_t, truncate or extend 3121 // it. 3122 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3123 3124 // If this is a multiply by a power of two, turn it into a shl 3125 // immediately. This is a very common case. 3126 if (ElementSize != 1) { 3127 if (ElementSize.isPowerOf2()) { 3128 unsigned Amt = ElementSize.logBase2(); 3129 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3130 N.getValueType(), IdxN, 3131 DAG.getConstant(Amt, IdxN.getValueType())); 3132 } else { 3133 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3134 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3135 N.getValueType(), IdxN, Scale); 3136 } 3137 } 3138 3139 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3140 N.getValueType(), N, IdxN); 3141 } 3142 } 3143 3144 setValue(&I, N); 3145} 3146 3147void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3148 // If this is a fixed sized alloca in the entry block of the function, 3149 // allocate it statically on the stack. 3150 if (FuncInfo.StaticAllocaMap.count(&I)) 3151 return; // getValue will auto-populate this. 3152 3153 Type *Ty = I.getAllocatedType(); 3154 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3155 unsigned Align = 3156 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3157 I.getAlignment()); 3158 3159 SDValue AllocSize = getValue(I.getArraySize()); 3160 3161 EVT IntPtr = TLI.getPointerTy(); 3162 if (AllocSize.getValueType() != IntPtr) 3163 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3164 3165 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3166 AllocSize, 3167 DAG.getConstant(TySize, IntPtr)); 3168 3169 // Handle alignment. If the requested alignment is less than or equal to 3170 // the stack alignment, ignore it. If the size is greater than or equal to 3171 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3172 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3173 if (Align <= StackAlign) 3174 Align = 0; 3175 3176 // Round the size of the allocation up to the stack alignment size 3177 // by add SA-1 to the size. 3178 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3179 AllocSize.getValueType(), AllocSize, 3180 DAG.getIntPtrConstant(StackAlign-1)); 3181 3182 // Mask out the low bits for alignment purposes. 3183 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3184 AllocSize.getValueType(), AllocSize, 3185 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3186 3187 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3188 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3189 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3190 VTs, Ops, 3); 3191 setValue(&I, DSA); 3192 DAG.setRoot(DSA.getValue(1)); 3193 3194 // Inform the Frame Information that we have just allocated a variable-sized 3195 // object. 3196 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3197} 3198 3199void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3200 if (I.isAtomic()) 3201 return visitAtomicLoad(I); 3202 3203 const Value *SV = I.getOperand(0); 3204 SDValue Ptr = getValue(SV); 3205 3206 Type *Ty = I.getType(); 3207 3208 bool isVolatile = I.isVolatile(); 3209 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3210 bool isInvariant = I.getMetadata("invariant.load") != 0; 3211 unsigned Alignment = I.getAlignment(); 3212 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3213 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 3214 3215 SmallVector<EVT, 4> ValueVTs; 3216 SmallVector<uint64_t, 4> Offsets; 3217 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3218 unsigned NumValues = ValueVTs.size(); 3219 if (NumValues == 0) 3220 return; 3221 3222 SDValue Root; 3223 bool ConstantMemory = false; 3224 if (I.isVolatile() || NumValues > MaxParallelChains) 3225 // Serialize volatile loads with other side effects. 3226 Root = getRoot(); 3227 else if (AA->pointsToConstantMemory( 3228 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3229 // Do not serialize (non-volatile) loads of constant memory with anything. 3230 Root = DAG.getEntryNode(); 3231 ConstantMemory = true; 3232 } else { 3233 // Do not serialize non-volatile loads against each other. 3234 Root = DAG.getRoot(); 3235 } 3236 3237 SmallVector<SDValue, 4> Values(NumValues); 3238 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3239 NumValues)); 3240 EVT PtrVT = Ptr.getValueType(); 3241 unsigned ChainI = 0; 3242 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3243 // Serializing loads here may result in excessive register pressure, and 3244 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3245 // could recover a bit by hoisting nodes upward in the chain by recognizing 3246 // they are side-effect free or do not alias. The optimizer should really 3247 // avoid this case by converting large object/array copies to llvm.memcpy 3248 // (MaxParallelChains should always remain as failsafe). 3249 if (ChainI == MaxParallelChains) { 3250 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3251 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3252 MVT::Other, &Chains[0], ChainI); 3253 Root = Chain; 3254 ChainI = 0; 3255 } 3256 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3257 PtrVT, Ptr, 3258 DAG.getConstant(Offsets[i], PtrVT)); 3259 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3260 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3261 isNonTemporal, isInvariant, Alignment, TBAAInfo, 3262 Ranges); 3263 3264 Values[i] = L; 3265 Chains[ChainI] = L.getValue(1); 3266 } 3267 3268 if (!ConstantMemory) { 3269 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3270 MVT::Other, &Chains[0], ChainI); 3271 if (isVolatile) 3272 DAG.setRoot(Chain); 3273 else 3274 PendingLoads.push_back(Chain); 3275 } 3276 3277 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3278 DAG.getVTList(&ValueVTs[0], NumValues), 3279 &Values[0], NumValues)); 3280} 3281 3282void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3283 if (I.isAtomic()) 3284 return visitAtomicStore(I); 3285 3286 const Value *SrcV = I.getOperand(0); 3287 const Value *PtrV = I.getOperand(1); 3288 3289 SmallVector<EVT, 4> ValueVTs; 3290 SmallVector<uint64_t, 4> Offsets; 3291 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3292 unsigned NumValues = ValueVTs.size(); 3293 if (NumValues == 0) 3294 return; 3295 3296 // Get the lowered operands. Note that we do this after 3297 // checking if NumResults is zero, because with zero results 3298 // the operands won't have values in the map. 3299 SDValue Src = getValue(SrcV); 3300 SDValue Ptr = getValue(PtrV); 3301 3302 SDValue Root = getRoot(); 3303 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3304 NumValues)); 3305 EVT PtrVT = Ptr.getValueType(); 3306 bool isVolatile = I.isVolatile(); 3307 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3308 unsigned Alignment = I.getAlignment(); 3309 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3310 3311 unsigned ChainI = 0; 3312 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3313 // See visitLoad comments. 3314 if (ChainI == MaxParallelChains) { 3315 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3316 MVT::Other, &Chains[0], ChainI); 3317 Root = Chain; 3318 ChainI = 0; 3319 } 3320 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3321 DAG.getConstant(Offsets[i], PtrVT)); 3322 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3323 SDValue(Src.getNode(), Src.getResNo() + i), 3324 Add, MachinePointerInfo(PtrV, Offsets[i]), 3325 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3326 Chains[ChainI] = St; 3327 } 3328 3329 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3330 MVT::Other, &Chains[0], ChainI); 3331 ++SDNodeOrder; 3332 AssignOrderingToNode(StoreNode.getNode()); 3333 DAG.setRoot(StoreNode); 3334} 3335 3336static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3337 SynchronizationScope Scope, 3338 bool Before, DebugLoc dl, 3339 SelectionDAG &DAG, 3340 const TargetLowering &TLI) { 3341 // Fence, if necessary 3342 if (Before) { 3343 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3344 Order = Release; 3345 else if (Order == Acquire || Order == Monotonic) 3346 return Chain; 3347 } else { 3348 if (Order == AcquireRelease) 3349 Order = Acquire; 3350 else if (Order == Release || Order == Monotonic) 3351 return Chain; 3352 } 3353 SDValue Ops[3]; 3354 Ops[0] = Chain; 3355 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3356 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3357 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3358} 3359 3360void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3361 DebugLoc dl = getCurDebugLoc(); 3362 AtomicOrdering Order = I.getOrdering(); 3363 SynchronizationScope Scope = I.getSynchScope(); 3364 3365 SDValue InChain = getRoot(); 3366 3367 if (TLI.getInsertFencesForAtomic()) 3368 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3369 DAG, TLI); 3370 3371 SDValue L = 3372 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3373 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3374 InChain, 3375 getValue(I.getPointerOperand()), 3376 getValue(I.getCompareOperand()), 3377 getValue(I.getNewValOperand()), 3378 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3379 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3380 Scope); 3381 3382 SDValue OutChain = L.getValue(1); 3383 3384 if (TLI.getInsertFencesForAtomic()) 3385 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3386 DAG, TLI); 3387 3388 setValue(&I, L); 3389 DAG.setRoot(OutChain); 3390} 3391 3392void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3393 DebugLoc dl = getCurDebugLoc(); 3394 ISD::NodeType NT; 3395 switch (I.getOperation()) { 3396 default: llvm_unreachable("Unknown atomicrmw operation"); 3397 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3398 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3399 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3400 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3401 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3402 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3403 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3404 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3405 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3406 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3407 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3408 } 3409 AtomicOrdering Order = I.getOrdering(); 3410 SynchronizationScope Scope = I.getSynchScope(); 3411 3412 SDValue InChain = getRoot(); 3413 3414 if (TLI.getInsertFencesForAtomic()) 3415 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3416 DAG, TLI); 3417 3418 SDValue L = 3419 DAG.getAtomic(NT, dl, 3420 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3421 InChain, 3422 getValue(I.getPointerOperand()), 3423 getValue(I.getValOperand()), 3424 I.getPointerOperand(), 0 /* Alignment */, 3425 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3426 Scope); 3427 3428 SDValue OutChain = L.getValue(1); 3429 3430 if (TLI.getInsertFencesForAtomic()) 3431 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3432 DAG, TLI); 3433 3434 setValue(&I, L); 3435 DAG.setRoot(OutChain); 3436} 3437 3438void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3439 DebugLoc dl = getCurDebugLoc(); 3440 SDValue Ops[3]; 3441 Ops[0] = getRoot(); 3442 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3443 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3444 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3445} 3446 3447void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3448 DebugLoc dl = getCurDebugLoc(); 3449 AtomicOrdering Order = I.getOrdering(); 3450 SynchronizationScope Scope = I.getSynchScope(); 3451 3452 SDValue InChain = getRoot(); 3453 3454 EVT VT = EVT::getEVT(I.getType()); 3455 3456 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3457 report_fatal_error("Cannot generate unaligned atomic load"); 3458 3459 SDValue L = 3460 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3461 getValue(I.getPointerOperand()), 3462 I.getPointerOperand(), I.getAlignment(), 3463 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3464 Scope); 3465 3466 SDValue OutChain = L.getValue(1); 3467 3468 if (TLI.getInsertFencesForAtomic()) 3469 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3470 DAG, TLI); 3471 3472 setValue(&I, L); 3473 DAG.setRoot(OutChain); 3474} 3475 3476void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3477 DebugLoc dl = getCurDebugLoc(); 3478 3479 AtomicOrdering Order = I.getOrdering(); 3480 SynchronizationScope Scope = I.getSynchScope(); 3481 3482 SDValue InChain = getRoot(); 3483 3484 EVT VT = EVT::getEVT(I.getValueOperand()->getType()); 3485 3486 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3487 report_fatal_error("Cannot generate unaligned atomic store"); 3488 3489 if (TLI.getInsertFencesForAtomic()) 3490 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3491 DAG, TLI); 3492 3493 SDValue OutChain = 3494 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3495 InChain, 3496 getValue(I.getPointerOperand()), 3497 getValue(I.getValueOperand()), 3498 I.getPointerOperand(), I.getAlignment(), 3499 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3500 Scope); 3501 3502 if (TLI.getInsertFencesForAtomic()) 3503 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3504 DAG, TLI); 3505 3506 DAG.setRoot(OutChain); 3507} 3508 3509/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3510/// node. 3511void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3512 unsigned Intrinsic) { 3513 bool HasChain = !I.doesNotAccessMemory(); 3514 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3515 3516 // Build the operand list. 3517 SmallVector<SDValue, 8> Ops; 3518 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3519 if (OnlyLoad) { 3520 // We don't need to serialize loads against other loads. 3521 Ops.push_back(DAG.getRoot()); 3522 } else { 3523 Ops.push_back(getRoot()); 3524 } 3525 } 3526 3527 // Info is set by getTgtMemInstrinsic 3528 TargetLowering::IntrinsicInfo Info; 3529 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3530 3531 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3532 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3533 Info.opc == ISD::INTRINSIC_W_CHAIN) 3534 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy())); 3535 3536 // Add all operands of the call to the operand list. 3537 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3538 SDValue Op = getValue(I.getArgOperand(i)); 3539 Ops.push_back(Op); 3540 } 3541 3542 SmallVector<EVT, 4> ValueVTs; 3543 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3544 3545 if (HasChain) 3546 ValueVTs.push_back(MVT::Other); 3547 3548 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3549 3550 // Create the node. 3551 SDValue Result; 3552 if (IsTgtIntrinsic) { 3553 // This is target intrinsic that touches memory 3554 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3555 VTs, &Ops[0], Ops.size(), 3556 Info.memVT, 3557 MachinePointerInfo(Info.ptrVal, Info.offset), 3558 Info.align, Info.vol, 3559 Info.readMem, Info.writeMem); 3560 } else if (!HasChain) { 3561 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3562 VTs, &Ops[0], Ops.size()); 3563 } else if (!I.getType()->isVoidTy()) { 3564 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3565 VTs, &Ops[0], Ops.size()); 3566 } else { 3567 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3568 VTs, &Ops[0], Ops.size()); 3569 } 3570 3571 if (HasChain) { 3572 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3573 if (OnlyLoad) 3574 PendingLoads.push_back(Chain); 3575 else 3576 DAG.setRoot(Chain); 3577 } 3578 3579 if (!I.getType()->isVoidTy()) { 3580 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3581 EVT VT = TLI.getValueType(PTy); 3582 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3583 } 3584 3585 setValue(&I, Result); 3586 } else { 3587 // Assign order to result here. If the intrinsic does not produce a result, 3588 // it won't be mapped to a SDNode and visit() will not assign it an order 3589 // number. 3590 ++SDNodeOrder; 3591 AssignOrderingToNode(Result.getNode()); 3592 } 3593} 3594 3595/// GetSignificand - Get the significand and build it into a floating-point 3596/// number with exponent of 1: 3597/// 3598/// Op = (Op & 0x007fffff) | 0x3f800000; 3599/// 3600/// where Op is the hexidecimal representation of floating point value. 3601static SDValue 3602GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3603 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3604 DAG.getConstant(0x007fffff, MVT::i32)); 3605 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3606 DAG.getConstant(0x3f800000, MVT::i32)); 3607 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3608} 3609 3610/// GetExponent - Get the exponent: 3611/// 3612/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3613/// 3614/// where Op is the hexidecimal representation of floating point value. 3615static SDValue 3616GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3617 DebugLoc dl) { 3618 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3619 DAG.getConstant(0x7f800000, MVT::i32)); 3620 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3621 DAG.getConstant(23, TLI.getPointerTy())); 3622 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3623 DAG.getConstant(127, MVT::i32)); 3624 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3625} 3626 3627/// getF32Constant - Get 32-bit floating point constant. 3628static SDValue 3629getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3630 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3631} 3632 3633/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3634/// limited-precision mode. 3635void 3636SelectionDAGBuilder::visitExp(const CallInst &I) { 3637 SDValue result; 3638 DebugLoc dl = getCurDebugLoc(); 3639 3640 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3641 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3642 SDValue Op = getValue(I.getArgOperand(0)); 3643 3644 // Put the exponent in the right bit position for later addition to the 3645 // final result: 3646 // 3647 // #define LOG2OFe 1.4426950f 3648 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3649 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3650 getF32Constant(DAG, 0x3fb8aa3b)); 3651 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3652 3653 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3654 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3655 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3656 3657 // IntegerPartOfX <<= 23; 3658 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3659 DAG.getConstant(23, TLI.getPointerTy())); 3660 3661 if (LimitFloatPrecision <= 6) { 3662 // For floating-point precision of 6: 3663 // 3664 // TwoToFractionalPartOfX = 3665 // 0.997535578f + 3666 // (0.735607626f + 0.252464424f * x) * x; 3667 // 3668 // error 0.0144103317, which is 6 bits 3669 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3670 getF32Constant(DAG, 0x3e814304)); 3671 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3672 getF32Constant(DAG, 0x3f3c50c8)); 3673 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3674 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3675 getF32Constant(DAG, 0x3f7f5e7e)); 3676 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3677 3678 // Add the exponent into the result in integer domain. 3679 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3680 TwoToFracPartOfX, IntegerPartOfX); 3681 3682 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3683 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3684 // For floating-point precision of 12: 3685 // 3686 // TwoToFractionalPartOfX = 3687 // 0.999892986f + 3688 // (0.696457318f + 3689 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3690 // 3691 // 0.000107046256 error, which is 13 to 14 bits 3692 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3693 getF32Constant(DAG, 0x3da235e3)); 3694 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3695 getF32Constant(DAG, 0x3e65b8f3)); 3696 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3697 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3698 getF32Constant(DAG, 0x3f324b07)); 3699 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3700 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3701 getF32Constant(DAG, 0x3f7ff8fd)); 3702 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3703 3704 // Add the exponent into the result in integer domain. 3705 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3706 TwoToFracPartOfX, IntegerPartOfX); 3707 3708 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3709 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3710 // For floating-point precision of 18: 3711 // 3712 // TwoToFractionalPartOfX = 3713 // 0.999999982f + 3714 // (0.693148872f + 3715 // (0.240227044f + 3716 // (0.554906021e-1f + 3717 // (0.961591928e-2f + 3718 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3719 // 3720 // error 2.47208000*10^(-7), which is better than 18 bits 3721 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3722 getF32Constant(DAG, 0x3924b03e)); 3723 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3724 getF32Constant(DAG, 0x3ab24b87)); 3725 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3726 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3727 getF32Constant(DAG, 0x3c1d8c17)); 3728 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3729 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3730 getF32Constant(DAG, 0x3d634a1d)); 3731 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3732 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3733 getF32Constant(DAG, 0x3e75fe14)); 3734 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3735 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3736 getF32Constant(DAG, 0x3f317234)); 3737 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3738 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3739 getF32Constant(DAG, 0x3f800000)); 3740 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3741 MVT::i32, t13); 3742 3743 // Add the exponent into the result in integer domain. 3744 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3745 TwoToFracPartOfX, IntegerPartOfX); 3746 3747 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3748 } 3749 } else { 3750 // No special expansion. 3751 result = DAG.getNode(ISD::FEXP, dl, 3752 getValue(I.getArgOperand(0)).getValueType(), 3753 getValue(I.getArgOperand(0))); 3754 } 3755 3756 setValue(&I, result); 3757} 3758 3759/// visitLog - Lower a log intrinsic. Handles the special sequences for 3760/// limited-precision mode. 3761void 3762SelectionDAGBuilder::visitLog(const CallInst &I) { 3763 SDValue result; 3764 DebugLoc dl = getCurDebugLoc(); 3765 3766 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3767 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3768 SDValue Op = getValue(I.getArgOperand(0)); 3769 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3770 3771 // Scale the exponent by log(2) [0.69314718f]. 3772 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3773 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3774 getF32Constant(DAG, 0x3f317218)); 3775 3776 // Get the significand and build it into a floating-point number with 3777 // exponent of 1. 3778 SDValue X = GetSignificand(DAG, Op1, dl); 3779 3780 if (LimitFloatPrecision <= 6) { 3781 // For floating-point precision of 6: 3782 // 3783 // LogofMantissa = 3784 // -1.1609546f + 3785 // (1.4034025f - 0.23903021f * x) * x; 3786 // 3787 // error 0.0034276066, which is better than 8 bits 3788 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3789 getF32Constant(DAG, 0xbe74c456)); 3790 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3791 getF32Constant(DAG, 0x3fb3a2b1)); 3792 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3793 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3794 getF32Constant(DAG, 0x3f949a29)); 3795 3796 result = DAG.getNode(ISD::FADD, dl, 3797 MVT::f32, LogOfExponent, LogOfMantissa); 3798 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3799 // For floating-point precision of 12: 3800 // 3801 // LogOfMantissa = 3802 // -1.7417939f + 3803 // (2.8212026f + 3804 // (-1.4699568f + 3805 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3806 // 3807 // error 0.000061011436, which is 14 bits 3808 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3809 getF32Constant(DAG, 0xbd67b6d6)); 3810 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3811 getF32Constant(DAG, 0x3ee4f4b8)); 3812 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3813 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3814 getF32Constant(DAG, 0x3fbc278b)); 3815 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3816 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3817 getF32Constant(DAG, 0x40348e95)); 3818 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3819 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3820 getF32Constant(DAG, 0x3fdef31a)); 3821 3822 result = DAG.getNode(ISD::FADD, dl, 3823 MVT::f32, LogOfExponent, LogOfMantissa); 3824 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3825 // For floating-point precision of 18: 3826 // 3827 // LogOfMantissa = 3828 // -2.1072184f + 3829 // (4.2372794f + 3830 // (-3.7029485f + 3831 // (2.2781945f + 3832 // (-0.87823314f + 3833 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3834 // 3835 // error 0.0000023660568, which is better than 18 bits 3836 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3837 getF32Constant(DAG, 0xbc91e5ac)); 3838 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3839 getF32Constant(DAG, 0x3e4350aa)); 3840 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3841 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3842 getF32Constant(DAG, 0x3f60d3e3)); 3843 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3844 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3845 getF32Constant(DAG, 0x4011cdf0)); 3846 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3847 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3848 getF32Constant(DAG, 0x406cfd1c)); 3849 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3850 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3851 getF32Constant(DAG, 0x408797cb)); 3852 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3853 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3854 getF32Constant(DAG, 0x4006dcab)); 3855 3856 result = DAG.getNode(ISD::FADD, dl, 3857 MVT::f32, LogOfExponent, LogOfMantissa); 3858 } 3859 } else { 3860 // No special expansion. 3861 result = DAG.getNode(ISD::FLOG, dl, 3862 getValue(I.getArgOperand(0)).getValueType(), 3863 getValue(I.getArgOperand(0))); 3864 } 3865 3866 setValue(&I, result); 3867} 3868 3869/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3870/// limited-precision mode. 3871void 3872SelectionDAGBuilder::visitLog2(const CallInst &I) { 3873 SDValue result; 3874 DebugLoc dl = getCurDebugLoc(); 3875 3876 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3877 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3878 SDValue Op = getValue(I.getArgOperand(0)); 3879 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3880 3881 // Get the exponent. 3882 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3883 3884 // Get the significand and build it into a floating-point number with 3885 // exponent of 1. 3886 SDValue X = GetSignificand(DAG, Op1, dl); 3887 3888 // Different possible minimax approximations of significand in 3889 // floating-point for various degrees of accuracy over [1,2]. 3890 if (LimitFloatPrecision <= 6) { 3891 // For floating-point precision of 6: 3892 // 3893 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3894 // 3895 // error 0.0049451742, which is more than 7 bits 3896 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3897 getF32Constant(DAG, 0xbeb08fe0)); 3898 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3899 getF32Constant(DAG, 0x40019463)); 3900 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3901 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3902 getF32Constant(DAG, 0x3fd6633d)); 3903 3904 result = DAG.getNode(ISD::FADD, dl, 3905 MVT::f32, LogOfExponent, Log2ofMantissa); 3906 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3907 // For floating-point precision of 12: 3908 // 3909 // Log2ofMantissa = 3910 // -2.51285454f + 3911 // (4.07009056f + 3912 // (-2.12067489f + 3913 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3914 // 3915 // error 0.0000876136000, which is better than 13 bits 3916 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3917 getF32Constant(DAG, 0xbda7262e)); 3918 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3919 getF32Constant(DAG, 0x3f25280b)); 3920 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3921 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3922 getF32Constant(DAG, 0x4007b923)); 3923 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3924 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3925 getF32Constant(DAG, 0x40823e2f)); 3926 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3927 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3928 getF32Constant(DAG, 0x4020d29c)); 3929 3930 result = DAG.getNode(ISD::FADD, dl, 3931 MVT::f32, LogOfExponent, Log2ofMantissa); 3932 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3933 // For floating-point precision of 18: 3934 // 3935 // Log2ofMantissa = 3936 // -3.0400495f + 3937 // (6.1129976f + 3938 // (-5.3420409f + 3939 // (3.2865683f + 3940 // (-1.2669343f + 3941 // (0.27515199f - 3942 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3943 // 3944 // error 0.0000018516, which is better than 18 bits 3945 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3946 getF32Constant(DAG, 0xbcd2769e)); 3947 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3948 getF32Constant(DAG, 0x3e8ce0b9)); 3949 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3950 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3951 getF32Constant(DAG, 0x3fa22ae7)); 3952 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3953 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3954 getF32Constant(DAG, 0x40525723)); 3955 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3956 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3957 getF32Constant(DAG, 0x40aaf200)); 3958 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3959 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3960 getF32Constant(DAG, 0x40c39dad)); 3961 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3962 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3963 getF32Constant(DAG, 0x4042902c)); 3964 3965 result = DAG.getNode(ISD::FADD, dl, 3966 MVT::f32, LogOfExponent, Log2ofMantissa); 3967 } 3968 } else { 3969 // No special expansion. 3970 result = DAG.getNode(ISD::FLOG2, dl, 3971 getValue(I.getArgOperand(0)).getValueType(), 3972 getValue(I.getArgOperand(0))); 3973 } 3974 3975 setValue(&I, result); 3976} 3977 3978/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3979/// limited-precision mode. 3980void 3981SelectionDAGBuilder::visitLog10(const CallInst &I) { 3982 SDValue result; 3983 DebugLoc dl = getCurDebugLoc(); 3984 3985 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3986 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3987 SDValue Op = getValue(I.getArgOperand(0)); 3988 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3989 3990 // Scale the exponent by log10(2) [0.30102999f]. 3991 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3992 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3993 getF32Constant(DAG, 0x3e9a209a)); 3994 3995 // Get the significand and build it into a floating-point number with 3996 // exponent of 1. 3997 SDValue X = GetSignificand(DAG, Op1, dl); 3998 3999 if (LimitFloatPrecision <= 6) { 4000 // For floating-point precision of 6: 4001 // 4002 // Log10ofMantissa = 4003 // -0.50419619f + 4004 // (0.60948995f - 0.10380950f * x) * x; 4005 // 4006 // error 0.0014886165, which is 6 bits 4007 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4008 getF32Constant(DAG, 0xbdd49a13)); 4009 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4010 getF32Constant(DAG, 0x3f1c0789)); 4011 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4012 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4013 getF32Constant(DAG, 0x3f011300)); 4014 4015 result = DAG.getNode(ISD::FADD, dl, 4016 MVT::f32, LogOfExponent, Log10ofMantissa); 4017 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4018 // For floating-point precision of 12: 4019 // 4020 // Log10ofMantissa = 4021 // -0.64831180f + 4022 // (0.91751397f + 4023 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4024 // 4025 // error 0.00019228036, which is better than 12 bits 4026 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4027 getF32Constant(DAG, 0x3d431f31)); 4028 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4029 getF32Constant(DAG, 0x3ea21fb2)); 4030 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4031 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4032 getF32Constant(DAG, 0x3f6ae232)); 4033 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4034 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4035 getF32Constant(DAG, 0x3f25f7c3)); 4036 4037 result = DAG.getNode(ISD::FADD, dl, 4038 MVT::f32, LogOfExponent, Log10ofMantissa); 4039 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4040 // For floating-point precision of 18: 4041 // 4042 // Log10ofMantissa = 4043 // -0.84299375f + 4044 // (1.5327582f + 4045 // (-1.0688956f + 4046 // (0.49102474f + 4047 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4048 // 4049 // error 0.0000037995730, which is better than 18 bits 4050 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4051 getF32Constant(DAG, 0x3c5d51ce)); 4052 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4053 getF32Constant(DAG, 0x3e00685a)); 4054 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4055 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4056 getF32Constant(DAG, 0x3efb6798)); 4057 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4058 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4059 getF32Constant(DAG, 0x3f88d192)); 4060 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4061 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4062 getF32Constant(DAG, 0x3fc4316c)); 4063 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4064 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4065 getF32Constant(DAG, 0x3f57ce70)); 4066 4067 result = DAG.getNode(ISD::FADD, dl, 4068 MVT::f32, LogOfExponent, Log10ofMantissa); 4069 } 4070 } else { 4071 // No special expansion. 4072 result = DAG.getNode(ISD::FLOG10, dl, 4073 getValue(I.getArgOperand(0)).getValueType(), 4074 getValue(I.getArgOperand(0))); 4075 } 4076 4077 setValue(&I, result); 4078} 4079 4080/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4081/// limited-precision mode. 4082void 4083SelectionDAGBuilder::visitExp2(const CallInst &I) { 4084 SDValue result; 4085 DebugLoc dl = getCurDebugLoc(); 4086 4087 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 4088 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4089 SDValue Op = getValue(I.getArgOperand(0)); 4090 4091 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4092 4093 // FractionalPartOfX = x - (float)IntegerPartOfX; 4094 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4095 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4096 4097 // IntegerPartOfX <<= 23; 4098 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4099 DAG.getConstant(23, TLI.getPointerTy())); 4100 4101 if (LimitFloatPrecision <= 6) { 4102 // For floating-point precision of 6: 4103 // 4104 // TwoToFractionalPartOfX = 4105 // 0.997535578f + 4106 // (0.735607626f + 0.252464424f * x) * x; 4107 // 4108 // error 0.0144103317, which is 6 bits 4109 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4110 getF32Constant(DAG, 0x3e814304)); 4111 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4112 getF32Constant(DAG, 0x3f3c50c8)); 4113 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4114 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4115 getF32Constant(DAG, 0x3f7f5e7e)); 4116 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4117 SDValue TwoToFractionalPartOfX = 4118 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4119 4120 result = DAG.getNode(ISD::BITCAST, dl, 4121 MVT::f32, TwoToFractionalPartOfX); 4122 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4123 // For floating-point precision of 12: 4124 // 4125 // TwoToFractionalPartOfX = 4126 // 0.999892986f + 4127 // (0.696457318f + 4128 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4129 // 4130 // error 0.000107046256, which is 13 to 14 bits 4131 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4132 getF32Constant(DAG, 0x3da235e3)); 4133 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4134 getF32Constant(DAG, 0x3e65b8f3)); 4135 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4136 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4137 getF32Constant(DAG, 0x3f324b07)); 4138 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4139 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4140 getF32Constant(DAG, 0x3f7ff8fd)); 4141 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4142 SDValue TwoToFractionalPartOfX = 4143 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4144 4145 result = DAG.getNode(ISD::BITCAST, dl, 4146 MVT::f32, TwoToFractionalPartOfX); 4147 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4148 // For floating-point precision of 18: 4149 // 4150 // TwoToFractionalPartOfX = 4151 // 0.999999982f + 4152 // (0.693148872f + 4153 // (0.240227044f + 4154 // (0.554906021e-1f + 4155 // (0.961591928e-2f + 4156 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4157 // error 2.47208000*10^(-7), which is better than 18 bits 4158 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4159 getF32Constant(DAG, 0x3924b03e)); 4160 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4161 getF32Constant(DAG, 0x3ab24b87)); 4162 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4163 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4164 getF32Constant(DAG, 0x3c1d8c17)); 4165 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4166 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4167 getF32Constant(DAG, 0x3d634a1d)); 4168 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4169 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4170 getF32Constant(DAG, 0x3e75fe14)); 4171 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4172 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4173 getF32Constant(DAG, 0x3f317234)); 4174 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4175 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4176 getF32Constant(DAG, 0x3f800000)); 4177 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4178 SDValue TwoToFractionalPartOfX = 4179 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4180 4181 result = DAG.getNode(ISD::BITCAST, dl, 4182 MVT::f32, TwoToFractionalPartOfX); 4183 } 4184 } else { 4185 // No special expansion. 4186 result = DAG.getNode(ISD::FEXP2, dl, 4187 getValue(I.getArgOperand(0)).getValueType(), 4188 getValue(I.getArgOperand(0))); 4189 } 4190 4191 setValue(&I, result); 4192} 4193 4194/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4195/// limited-precision mode with x == 10.0f. 4196void 4197SelectionDAGBuilder::visitPow(const CallInst &I) { 4198 SDValue result; 4199 const Value *Val = I.getArgOperand(0); 4200 DebugLoc dl = getCurDebugLoc(); 4201 bool IsExp10 = false; 4202 4203 if (getValue(Val).getValueType() == MVT::f32 && 4204 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4205 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4206 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4207 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4208 APFloat Ten(10.0f); 4209 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4210 } 4211 } 4212 } 4213 4214 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4215 SDValue Op = getValue(I.getArgOperand(1)); 4216 4217 // Put the exponent in the right bit position for later addition to the 4218 // final result: 4219 // 4220 // #define LOG2OF10 3.3219281f 4221 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4222 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4223 getF32Constant(DAG, 0x40549a78)); 4224 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4225 4226 // FractionalPartOfX = x - (float)IntegerPartOfX; 4227 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4228 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4229 4230 // IntegerPartOfX <<= 23; 4231 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4232 DAG.getConstant(23, TLI.getPointerTy())); 4233 4234 if (LimitFloatPrecision <= 6) { 4235 // For floating-point precision of 6: 4236 // 4237 // twoToFractionalPartOfX = 4238 // 0.997535578f + 4239 // (0.735607626f + 0.252464424f * x) * x; 4240 // 4241 // error 0.0144103317, which is 6 bits 4242 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4243 getF32Constant(DAG, 0x3e814304)); 4244 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4245 getF32Constant(DAG, 0x3f3c50c8)); 4246 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4247 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4248 getF32Constant(DAG, 0x3f7f5e7e)); 4249 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4250 SDValue TwoToFractionalPartOfX = 4251 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4252 4253 result = DAG.getNode(ISD::BITCAST, dl, 4254 MVT::f32, TwoToFractionalPartOfX); 4255 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4256 // For floating-point precision of 12: 4257 // 4258 // TwoToFractionalPartOfX = 4259 // 0.999892986f + 4260 // (0.696457318f + 4261 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4262 // 4263 // error 0.000107046256, which is 13 to 14 bits 4264 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4265 getF32Constant(DAG, 0x3da235e3)); 4266 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4267 getF32Constant(DAG, 0x3e65b8f3)); 4268 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4269 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4270 getF32Constant(DAG, 0x3f324b07)); 4271 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4272 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4273 getF32Constant(DAG, 0x3f7ff8fd)); 4274 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4275 SDValue TwoToFractionalPartOfX = 4276 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4277 4278 result = DAG.getNode(ISD::BITCAST, dl, 4279 MVT::f32, TwoToFractionalPartOfX); 4280 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4281 // For floating-point precision of 18: 4282 // 4283 // TwoToFractionalPartOfX = 4284 // 0.999999982f + 4285 // (0.693148872f + 4286 // (0.240227044f + 4287 // (0.554906021e-1f + 4288 // (0.961591928e-2f + 4289 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4290 // error 2.47208000*10^(-7), which is better than 18 bits 4291 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4292 getF32Constant(DAG, 0x3924b03e)); 4293 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4294 getF32Constant(DAG, 0x3ab24b87)); 4295 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4296 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4297 getF32Constant(DAG, 0x3c1d8c17)); 4298 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4299 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4300 getF32Constant(DAG, 0x3d634a1d)); 4301 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4302 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4303 getF32Constant(DAG, 0x3e75fe14)); 4304 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4305 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4306 getF32Constant(DAG, 0x3f317234)); 4307 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4308 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4309 getF32Constant(DAG, 0x3f800000)); 4310 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4311 SDValue TwoToFractionalPartOfX = 4312 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4313 4314 result = DAG.getNode(ISD::BITCAST, dl, 4315 MVT::f32, TwoToFractionalPartOfX); 4316 } 4317 } else { 4318 // No special expansion. 4319 result = DAG.getNode(ISD::FPOW, dl, 4320 getValue(I.getArgOperand(0)).getValueType(), 4321 getValue(I.getArgOperand(0)), 4322 getValue(I.getArgOperand(1))); 4323 } 4324 4325 setValue(&I, result); 4326} 4327 4328 4329/// ExpandPowI - Expand a llvm.powi intrinsic. 4330static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4331 SelectionDAG &DAG) { 4332 // If RHS is a constant, we can expand this out to a multiplication tree, 4333 // otherwise we end up lowering to a call to __powidf2 (for example). When 4334 // optimizing for size, we only want to do this if the expansion would produce 4335 // a small number of multiplies, otherwise we do the full expansion. 4336 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4337 // Get the exponent as a positive value. 4338 unsigned Val = RHSC->getSExtValue(); 4339 if ((int)Val < 0) Val = -Val; 4340 4341 // powi(x, 0) -> 1.0 4342 if (Val == 0) 4343 return DAG.getConstantFP(1.0, LHS.getValueType()); 4344 4345 const Function *F = DAG.getMachineFunction().getFunction(); 4346 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4347 // If optimizing for size, don't insert too many multiplies. This 4348 // inserts up to 5 multiplies. 4349 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4350 // We use the simple binary decomposition method to generate the multiply 4351 // sequence. There are more optimal ways to do this (for example, 4352 // powi(x,15) generates one more multiply than it should), but this has 4353 // the benefit of being both really simple and much better than a libcall. 4354 SDValue Res; // Logically starts equal to 1.0 4355 SDValue CurSquare = LHS; 4356 while (Val) { 4357 if (Val & 1) { 4358 if (Res.getNode()) 4359 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4360 else 4361 Res = CurSquare; // 1.0*CurSquare. 4362 } 4363 4364 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4365 CurSquare, CurSquare); 4366 Val >>= 1; 4367 } 4368 4369 // If the original was negative, invert the result, producing 1/(x*x*x). 4370 if (RHSC->getSExtValue() < 0) 4371 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4372 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4373 return Res; 4374 } 4375 } 4376 4377 // Otherwise, expand to a libcall. 4378 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4379} 4380 4381// getTruncatedArgReg - Find underlying register used for an truncated 4382// argument. 4383static unsigned getTruncatedArgReg(const SDValue &N) { 4384 if (N.getOpcode() != ISD::TRUNCATE) 4385 return 0; 4386 4387 const SDValue &Ext = N.getOperand(0); 4388 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4389 const SDValue &CFR = Ext.getOperand(0); 4390 if (CFR.getOpcode() == ISD::CopyFromReg) 4391 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4392 if (CFR.getOpcode() == ISD::TRUNCATE) 4393 return getTruncatedArgReg(CFR); 4394 } 4395 return 0; 4396} 4397 4398/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4399/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4400/// At the end of instruction selection, they will be inserted to the entry BB. 4401bool 4402SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4403 int64_t Offset, 4404 const SDValue &N) { 4405 const Argument *Arg = dyn_cast<Argument>(V); 4406 if (!Arg) 4407 return false; 4408 4409 MachineFunction &MF = DAG.getMachineFunction(); 4410 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4411 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4412 4413 // Ignore inlined function arguments here. 4414 DIVariable DV(Variable); 4415 if (DV.isInlinedFnArgument(MF.getFunction())) 4416 return false; 4417 4418 unsigned Reg = 0; 4419 // Some arguments' frame index is recorded during argument lowering. 4420 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4421 if (Offset) 4422 Reg = TRI->getFrameRegister(MF); 4423 4424 if (!Reg && N.getNode()) { 4425 if (N.getOpcode() == ISD::CopyFromReg) 4426 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4427 else 4428 Reg = getTruncatedArgReg(N); 4429 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4430 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4431 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4432 if (PR) 4433 Reg = PR; 4434 } 4435 } 4436 4437 if (!Reg) { 4438 // Check if ValueMap has reg number. 4439 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4440 if (VMI != FuncInfo.ValueMap.end()) 4441 Reg = VMI->second; 4442 } 4443 4444 if (!Reg && N.getNode()) { 4445 // Check if frame index is available. 4446 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4447 if (FrameIndexSDNode *FINode = 4448 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4449 Reg = TRI->getFrameRegister(MF); 4450 Offset = FINode->getIndex(); 4451 } 4452 } 4453 4454 if (!Reg) 4455 return false; 4456 4457 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4458 TII->get(TargetOpcode::DBG_VALUE)) 4459 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4460 FuncInfo.ArgDbgValues.push_back(&*MIB); 4461 return true; 4462} 4463 4464// VisualStudio defines setjmp as _setjmp 4465#if defined(_MSC_VER) && defined(setjmp) && \ 4466 !defined(setjmp_undefined_for_msvc) 4467# pragma push_macro("setjmp") 4468# undef setjmp 4469# define setjmp_undefined_for_msvc 4470#endif 4471 4472/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4473/// we want to emit this as a call to a named external function, return the name 4474/// otherwise lower it and return null. 4475const char * 4476SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4477 DebugLoc dl = getCurDebugLoc(); 4478 SDValue Res; 4479 4480 switch (Intrinsic) { 4481 default: 4482 // By default, turn this into a target intrinsic node. 4483 visitTargetIntrinsic(I, Intrinsic); 4484 return 0; 4485 case Intrinsic::vastart: visitVAStart(I); return 0; 4486 case Intrinsic::vaend: visitVAEnd(I); return 0; 4487 case Intrinsic::vacopy: visitVACopy(I); return 0; 4488 case Intrinsic::returnaddress: 4489 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4490 getValue(I.getArgOperand(0)))); 4491 return 0; 4492 case Intrinsic::frameaddress: 4493 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4494 getValue(I.getArgOperand(0)))); 4495 return 0; 4496 case Intrinsic::setjmp: 4497 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()]; 4498 case Intrinsic::longjmp: 4499 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()]; 4500 case Intrinsic::memcpy: { 4501 // Assert for address < 256 since we support only user defined address 4502 // spaces. 4503 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4504 < 256 && 4505 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4506 < 256 && 4507 "Unknown address space"); 4508 SDValue Op1 = getValue(I.getArgOperand(0)); 4509 SDValue Op2 = getValue(I.getArgOperand(1)); 4510 SDValue Op3 = getValue(I.getArgOperand(2)); 4511 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4512 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4513 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4514 MachinePointerInfo(I.getArgOperand(0)), 4515 MachinePointerInfo(I.getArgOperand(1)))); 4516 return 0; 4517 } 4518 case Intrinsic::memset: { 4519 // Assert for address < 256 since we support only user defined address 4520 // spaces. 4521 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4522 < 256 && 4523 "Unknown address space"); 4524 SDValue Op1 = getValue(I.getArgOperand(0)); 4525 SDValue Op2 = getValue(I.getArgOperand(1)); 4526 SDValue Op3 = getValue(I.getArgOperand(2)); 4527 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4528 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4529 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4530 MachinePointerInfo(I.getArgOperand(0)))); 4531 return 0; 4532 } 4533 case Intrinsic::memmove: { 4534 // Assert for address < 256 since we support only user defined address 4535 // spaces. 4536 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4537 < 256 && 4538 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4539 < 256 && 4540 "Unknown address space"); 4541 SDValue Op1 = getValue(I.getArgOperand(0)); 4542 SDValue Op2 = getValue(I.getArgOperand(1)); 4543 SDValue Op3 = getValue(I.getArgOperand(2)); 4544 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4545 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4546 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4547 MachinePointerInfo(I.getArgOperand(0)), 4548 MachinePointerInfo(I.getArgOperand(1)))); 4549 return 0; 4550 } 4551 case Intrinsic::dbg_declare: { 4552 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4553 MDNode *Variable = DI.getVariable(); 4554 const Value *Address = DI.getAddress(); 4555 if (!Address || !DIVariable(Variable).Verify()) { 4556 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4557 return 0; 4558 } 4559 4560 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4561 // but do not always have a corresponding SDNode built. The SDNodeOrder 4562 // absolute, but not relative, values are different depending on whether 4563 // debug info exists. 4564 ++SDNodeOrder; 4565 4566 // Check if address has undef value. 4567 if (isa<UndefValue>(Address) || 4568 (Address->use_empty() && !isa<Argument>(Address))) { 4569 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4570 return 0; 4571 } 4572 4573 SDValue &N = NodeMap[Address]; 4574 if (!N.getNode() && isa<Argument>(Address)) 4575 // Check unused arguments map. 4576 N = UnusedArgNodeMap[Address]; 4577 SDDbgValue *SDV; 4578 if (N.getNode()) { 4579 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4580 Address = BCI->getOperand(0); 4581 // Parameters are handled specially. 4582 bool isParameter = 4583 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable || 4584 isa<Argument>(Address)); 4585 4586 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4587 4588 if (isParameter && !AI) { 4589 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4590 if (FINode) 4591 // Byval parameter. We have a frame index at this point. 4592 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4593 0, dl, SDNodeOrder); 4594 else { 4595 // Address is an argument, so try to emit its dbg value using 4596 // virtual register info from the FuncInfo.ValueMap. 4597 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4598 return 0; 4599 } 4600 } else if (AI) 4601 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4602 0, dl, SDNodeOrder); 4603 else { 4604 // Can't do anything with other non-AI cases yet. 4605 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4606 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t"); 4607 DEBUG(Address->dump()); 4608 return 0; 4609 } 4610 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4611 } else { 4612 // If Address is an argument then try to emit its dbg value using 4613 // virtual register info from the FuncInfo.ValueMap. 4614 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4615 // If variable is pinned by a alloca in dominating bb then 4616 // use StaticAllocaMap. 4617 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4618 if (AI->getParent() != DI.getParent()) { 4619 DenseMap<const AllocaInst*, int>::iterator SI = 4620 FuncInfo.StaticAllocaMap.find(AI); 4621 if (SI != FuncInfo.StaticAllocaMap.end()) { 4622 SDV = DAG.getDbgValue(Variable, SI->second, 4623 0, dl, SDNodeOrder); 4624 DAG.AddDbgValue(SDV, 0, false); 4625 return 0; 4626 } 4627 } 4628 } 4629 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4630 } 4631 } 4632 return 0; 4633 } 4634 case Intrinsic::dbg_value: { 4635 const DbgValueInst &DI = cast<DbgValueInst>(I); 4636 if (!DIVariable(DI.getVariable()).Verify()) 4637 return 0; 4638 4639 MDNode *Variable = DI.getVariable(); 4640 uint64_t Offset = DI.getOffset(); 4641 const Value *V = DI.getValue(); 4642 if (!V) 4643 return 0; 4644 4645 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4646 // but do not always have a corresponding SDNode built. The SDNodeOrder 4647 // absolute, but not relative, values are different depending on whether 4648 // debug info exists. 4649 ++SDNodeOrder; 4650 SDDbgValue *SDV; 4651 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4652 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4653 DAG.AddDbgValue(SDV, 0, false); 4654 } else { 4655 // Do not use getValue() in here; we don't want to generate code at 4656 // this point if it hasn't been done yet. 4657 SDValue N = NodeMap[V]; 4658 if (!N.getNode() && isa<Argument>(V)) 4659 // Check unused arguments map. 4660 N = UnusedArgNodeMap[V]; 4661 if (N.getNode()) { 4662 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4663 SDV = DAG.getDbgValue(Variable, N.getNode(), 4664 N.getResNo(), Offset, dl, SDNodeOrder); 4665 DAG.AddDbgValue(SDV, N.getNode(), false); 4666 } 4667 } else if (!V->use_empty() ) { 4668 // Do not call getValue(V) yet, as we don't want to generate code. 4669 // Remember it for later. 4670 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4671 DanglingDebugInfoMap[V] = DDI; 4672 } else { 4673 // We may expand this to cover more cases. One case where we have no 4674 // data available is an unreferenced parameter. 4675 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4676 } 4677 } 4678 4679 // Build a debug info table entry. 4680 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4681 V = BCI->getOperand(0); 4682 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4683 // Don't handle byval struct arguments or VLAs, for example. 4684 if (!AI) { 4685 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); 4686 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); 4687 return 0; 4688 } 4689 DenseMap<const AllocaInst*, int>::iterator SI = 4690 FuncInfo.StaticAllocaMap.find(AI); 4691 if (SI == FuncInfo.StaticAllocaMap.end()) 4692 return 0; // VLAs. 4693 int FI = SI->second; 4694 4695 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4696 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4697 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4698 return 0; 4699 } 4700 4701 case Intrinsic::eh_typeid_for: { 4702 // Find the type id for the given typeinfo. 4703 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4704 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4705 Res = DAG.getConstant(TypeID, MVT::i32); 4706 setValue(&I, Res); 4707 return 0; 4708 } 4709 4710 case Intrinsic::eh_return_i32: 4711 case Intrinsic::eh_return_i64: 4712 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4713 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4714 MVT::Other, 4715 getControlRoot(), 4716 getValue(I.getArgOperand(0)), 4717 getValue(I.getArgOperand(1)))); 4718 return 0; 4719 case Intrinsic::eh_unwind_init: 4720 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4721 return 0; 4722 case Intrinsic::eh_dwarf_cfa: { 4723 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4724 TLI.getPointerTy()); 4725 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4726 TLI.getPointerTy(), 4727 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4728 TLI.getPointerTy()), 4729 CfaArg); 4730 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4731 TLI.getPointerTy(), 4732 DAG.getConstant(0, TLI.getPointerTy())); 4733 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4734 FA, Offset)); 4735 return 0; 4736 } 4737 case Intrinsic::eh_sjlj_callsite: { 4738 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4739 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4740 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4741 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4742 4743 MMI.setCurrentCallSite(CI->getZExtValue()); 4744 return 0; 4745 } 4746 case Intrinsic::eh_sjlj_functioncontext: { 4747 // Get and store the index of the function context. 4748 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4749 AllocaInst *FnCtx = 4750 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4751 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4752 MFI->setFunctionContextIndex(FI); 4753 return 0; 4754 } 4755 case Intrinsic::eh_sjlj_setjmp: { 4756 SDValue Ops[2]; 4757 Ops[0] = getRoot(); 4758 Ops[1] = getValue(I.getArgOperand(0)); 4759 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, 4760 DAG.getVTList(MVT::i32, MVT::Other), 4761 Ops, 2); 4762 setValue(&I, Op.getValue(0)); 4763 DAG.setRoot(Op.getValue(1)); 4764 return 0; 4765 } 4766 case Intrinsic::eh_sjlj_longjmp: { 4767 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4768 getRoot(), getValue(I.getArgOperand(0)))); 4769 return 0; 4770 } 4771 4772 case Intrinsic::x86_mmx_pslli_w: 4773 case Intrinsic::x86_mmx_pslli_d: 4774 case Intrinsic::x86_mmx_pslli_q: 4775 case Intrinsic::x86_mmx_psrli_w: 4776 case Intrinsic::x86_mmx_psrli_d: 4777 case Intrinsic::x86_mmx_psrli_q: 4778 case Intrinsic::x86_mmx_psrai_w: 4779 case Intrinsic::x86_mmx_psrai_d: { 4780 SDValue ShAmt = getValue(I.getArgOperand(1)); 4781 if (isa<ConstantSDNode>(ShAmt)) { 4782 visitTargetIntrinsic(I, Intrinsic); 4783 return 0; 4784 } 4785 unsigned NewIntrinsic = 0; 4786 EVT ShAmtVT = MVT::v2i32; 4787 switch (Intrinsic) { 4788 case Intrinsic::x86_mmx_pslli_w: 4789 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4790 break; 4791 case Intrinsic::x86_mmx_pslli_d: 4792 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4793 break; 4794 case Intrinsic::x86_mmx_pslli_q: 4795 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4796 break; 4797 case Intrinsic::x86_mmx_psrli_w: 4798 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4799 break; 4800 case Intrinsic::x86_mmx_psrli_d: 4801 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4802 break; 4803 case Intrinsic::x86_mmx_psrli_q: 4804 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4805 break; 4806 case Intrinsic::x86_mmx_psrai_w: 4807 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4808 break; 4809 case Intrinsic::x86_mmx_psrai_d: 4810 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4811 break; 4812 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4813 } 4814 4815 // The vector shift intrinsics with scalars uses 32b shift amounts but 4816 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4817 // to be zero. 4818 // We must do this early because v2i32 is not a legal type. 4819 DebugLoc dl = getCurDebugLoc(); 4820 SDValue ShOps[2]; 4821 ShOps[0] = ShAmt; 4822 ShOps[1] = DAG.getConstant(0, MVT::i32); 4823 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4824 EVT DestVT = TLI.getValueType(I.getType()); 4825 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4826 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4827 DAG.getConstant(NewIntrinsic, MVT::i32), 4828 getValue(I.getArgOperand(0)), ShAmt); 4829 setValue(&I, Res); 4830 return 0; 4831 } 4832 case Intrinsic::x86_avx_vinsertf128_pd_256: 4833 case Intrinsic::x86_avx_vinsertf128_ps_256: 4834 case Intrinsic::x86_avx_vinsertf128_si_256: 4835 case Intrinsic::x86_avx2_vinserti128: { 4836 DebugLoc dl = getCurDebugLoc(); 4837 EVT DestVT = TLI.getValueType(I.getType()); 4838 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType()); 4839 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) * 4840 ElVT.getVectorNumElements(); 4841 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT, 4842 getValue(I.getArgOperand(0)), 4843 getValue(I.getArgOperand(1)), 4844 DAG.getConstant(Idx, MVT::i32)); 4845 setValue(&I, Res); 4846 return 0; 4847 } 4848 case Intrinsic::convertff: 4849 case Intrinsic::convertfsi: 4850 case Intrinsic::convertfui: 4851 case Intrinsic::convertsif: 4852 case Intrinsic::convertuif: 4853 case Intrinsic::convertss: 4854 case Intrinsic::convertsu: 4855 case Intrinsic::convertus: 4856 case Intrinsic::convertuu: { 4857 ISD::CvtCode Code = ISD::CVT_INVALID; 4858 switch (Intrinsic) { 4859 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4860 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4861 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4862 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4863 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4864 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4865 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4866 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4867 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4868 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4869 } 4870 EVT DestVT = TLI.getValueType(I.getType()); 4871 const Value *Op1 = I.getArgOperand(0); 4872 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4873 DAG.getValueType(DestVT), 4874 DAG.getValueType(getValue(Op1).getValueType()), 4875 getValue(I.getArgOperand(1)), 4876 getValue(I.getArgOperand(2)), 4877 Code); 4878 setValue(&I, Res); 4879 return 0; 4880 } 4881 case Intrinsic::sqrt: 4882 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4883 getValue(I.getArgOperand(0)).getValueType(), 4884 getValue(I.getArgOperand(0)))); 4885 return 0; 4886 case Intrinsic::powi: 4887 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4888 getValue(I.getArgOperand(1)), DAG)); 4889 return 0; 4890 case Intrinsic::sin: 4891 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4892 getValue(I.getArgOperand(0)).getValueType(), 4893 getValue(I.getArgOperand(0)))); 4894 return 0; 4895 case Intrinsic::cos: 4896 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4897 getValue(I.getArgOperand(0)).getValueType(), 4898 getValue(I.getArgOperand(0)))); 4899 return 0; 4900 case Intrinsic::log: 4901 visitLog(I); 4902 return 0; 4903 case Intrinsic::log2: 4904 visitLog2(I); 4905 return 0; 4906 case Intrinsic::log10: 4907 visitLog10(I); 4908 return 0; 4909 case Intrinsic::exp: 4910 visitExp(I); 4911 return 0; 4912 case Intrinsic::exp2: 4913 visitExp2(I); 4914 return 0; 4915 case Intrinsic::pow: 4916 visitPow(I); 4917 return 0; 4918 case Intrinsic::fma: 4919 setValue(&I, DAG.getNode(ISD::FMA, dl, 4920 getValue(I.getArgOperand(0)).getValueType(), 4921 getValue(I.getArgOperand(0)), 4922 getValue(I.getArgOperand(1)), 4923 getValue(I.getArgOperand(2)))); 4924 return 0; 4925 case Intrinsic::convert_to_fp16: 4926 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4927 MVT::i16, getValue(I.getArgOperand(0)))); 4928 return 0; 4929 case Intrinsic::convert_from_fp16: 4930 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4931 MVT::f32, getValue(I.getArgOperand(0)))); 4932 return 0; 4933 case Intrinsic::pcmarker: { 4934 SDValue Tmp = getValue(I.getArgOperand(0)); 4935 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4936 return 0; 4937 } 4938 case Intrinsic::readcyclecounter: { 4939 SDValue Op = getRoot(); 4940 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4941 DAG.getVTList(MVT::i64, MVT::Other), 4942 &Op, 1); 4943 setValue(&I, Res); 4944 DAG.setRoot(Res.getValue(1)); 4945 return 0; 4946 } 4947 case Intrinsic::bswap: 4948 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4949 getValue(I.getArgOperand(0)).getValueType(), 4950 getValue(I.getArgOperand(0)))); 4951 return 0; 4952 case Intrinsic::cttz: { 4953 SDValue Arg = getValue(I.getArgOperand(0)); 4954 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4955 EVT Ty = Arg.getValueType(); 4956 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 4957 dl, Ty, Arg)); 4958 return 0; 4959 } 4960 case Intrinsic::ctlz: { 4961 SDValue Arg = getValue(I.getArgOperand(0)); 4962 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4963 EVT Ty = Arg.getValueType(); 4964 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 4965 dl, Ty, Arg)); 4966 return 0; 4967 } 4968 case Intrinsic::ctpop: { 4969 SDValue Arg = getValue(I.getArgOperand(0)); 4970 EVT Ty = Arg.getValueType(); 4971 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4972 return 0; 4973 } 4974 case Intrinsic::stacksave: { 4975 SDValue Op = getRoot(); 4976 Res = DAG.getNode(ISD::STACKSAVE, dl, 4977 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4978 setValue(&I, Res); 4979 DAG.setRoot(Res.getValue(1)); 4980 return 0; 4981 } 4982 case Intrinsic::stackrestore: { 4983 Res = getValue(I.getArgOperand(0)); 4984 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4985 return 0; 4986 } 4987 case Intrinsic::stackprotector: { 4988 // Emit code into the DAG to store the stack guard onto the stack. 4989 MachineFunction &MF = DAG.getMachineFunction(); 4990 MachineFrameInfo *MFI = MF.getFrameInfo(); 4991 EVT PtrTy = TLI.getPointerTy(); 4992 4993 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4994 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4995 4996 int FI = FuncInfo.StaticAllocaMap[Slot]; 4997 MFI->setStackProtectorIndex(FI); 4998 4999 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5000 5001 // Store the stack protector onto the stack. 5002 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 5003 MachinePointerInfo::getFixedStack(FI), 5004 true, false, 0); 5005 setValue(&I, Res); 5006 DAG.setRoot(Res); 5007 return 0; 5008 } 5009 case Intrinsic::objectsize: { 5010 // If we don't know by now, we're never going to know. 5011 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5012 5013 assert(CI && "Non-constant type in __builtin_object_size?"); 5014 5015 SDValue Arg = getValue(I.getCalledValue()); 5016 EVT Ty = Arg.getValueType(); 5017 5018 if (CI->isZero()) 5019 Res = DAG.getConstant(-1ULL, Ty); 5020 else 5021 Res = DAG.getConstant(0, Ty); 5022 5023 setValue(&I, Res); 5024 return 0; 5025 } 5026 case Intrinsic::var_annotation: 5027 // Discard annotate attributes 5028 return 0; 5029 5030 case Intrinsic::init_trampoline: { 5031 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5032 5033 SDValue Ops[6]; 5034 Ops[0] = getRoot(); 5035 Ops[1] = getValue(I.getArgOperand(0)); 5036 Ops[2] = getValue(I.getArgOperand(1)); 5037 Ops[3] = getValue(I.getArgOperand(2)); 5038 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5039 Ops[5] = DAG.getSrcValue(F); 5040 5041 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5042 5043 DAG.setRoot(Res); 5044 return 0; 5045 } 5046 case Intrinsic::adjust_trampoline: { 5047 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5048 TLI.getPointerTy(), 5049 getValue(I.getArgOperand(0)))); 5050 return 0; 5051 } 5052 case Intrinsic::gcroot: 5053 if (GFI) { 5054 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); 5055 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5056 5057 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5058 GFI->addStackRoot(FI->getIndex(), TypeMap); 5059 } 5060 return 0; 5061 case Intrinsic::gcread: 5062 case Intrinsic::gcwrite: 5063 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5064 case Intrinsic::flt_rounds: 5065 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5066 return 0; 5067 5068 case Intrinsic::expect: { 5069 // Just replace __builtin_expect(exp, c) with EXP. 5070 setValue(&I, getValue(I.getArgOperand(0))); 5071 return 0; 5072 } 5073 5074 case Intrinsic::trap: { 5075 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5076 if (TrapFuncName.empty()) { 5077 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 5078 return 0; 5079 } 5080 TargetLowering::ArgListTy Args; 5081 std::pair<SDValue, SDValue> Result = 5082 TLI.LowerCallTo(getRoot(), I.getType(), 5083 false, false, false, false, 0, CallingConv::C, 5084 /*isTailCall=*/false, 5085 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 5086 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5087 Args, DAG, getCurDebugLoc()); 5088 DAG.setRoot(Result.second); 5089 return 0; 5090 } 5091 case Intrinsic::debugtrap: { 5092 DAG.setRoot(DAG.getNode(ISD::DEBUGTRAP, dl,MVT::Other, getRoot())); 5093 return 0; 5094 } 5095 case Intrinsic::uadd_with_overflow: 5096 case Intrinsic::sadd_with_overflow: 5097 case Intrinsic::usub_with_overflow: 5098 case Intrinsic::ssub_with_overflow: 5099 case Intrinsic::umul_with_overflow: 5100 case Intrinsic::smul_with_overflow: { 5101 ISD::NodeType Op; 5102 switch (Intrinsic) { 5103 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 5104 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; 5105 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; 5106 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; 5107 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; 5108 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; 5109 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; 5110 } 5111 SDValue Op1 = getValue(I.getArgOperand(0)); 5112 SDValue Op2 = getValue(I.getArgOperand(1)); 5113 5114 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 5115 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 5116 return 0; 5117 } 5118 case Intrinsic::prefetch: { 5119 SDValue Ops[5]; 5120 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5121 Ops[0] = getRoot(); 5122 Ops[1] = getValue(I.getArgOperand(0)); 5123 Ops[2] = getValue(I.getArgOperand(1)); 5124 Ops[3] = getValue(I.getArgOperand(2)); 5125 Ops[4] = getValue(I.getArgOperand(3)); 5126 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5127 DAG.getVTList(MVT::Other), 5128 &Ops[0], 5, 5129 EVT::getIntegerVT(*Context, 8), 5130 MachinePointerInfo(I.getArgOperand(0)), 5131 0, /* align */ 5132 false, /* volatile */ 5133 rw==0, /* read */ 5134 rw==1)); /* write */ 5135 return 0; 5136 } 5137 5138 case Intrinsic::invariant_start: 5139 case Intrinsic::lifetime_start: 5140 // Discard region information. 5141 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5142 return 0; 5143 case Intrinsic::invariant_end: 5144 case Intrinsic::lifetime_end: 5145 // Discard region information. 5146 return 0; 5147 } 5148} 5149 5150void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5151 bool isTailCall, 5152 MachineBasicBlock *LandingPad) { 5153 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5154 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5155 Type *RetTy = FTy->getReturnType(); 5156 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5157 MCSymbol *BeginLabel = 0; 5158 5159 TargetLowering::ArgListTy Args; 5160 TargetLowering::ArgListEntry Entry; 5161 Args.reserve(CS.arg_size()); 5162 5163 // Check whether the function can return without sret-demotion. 5164 SmallVector<ISD::OutputArg, 4> Outs; 5165 SmallVector<uint64_t, 4> Offsets; 5166 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5167 Outs, TLI, &Offsets); 5168 5169 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5170 DAG.getMachineFunction(), 5171 FTy->isVarArg(), Outs, 5172 FTy->getContext()); 5173 5174 SDValue DemoteStackSlot; 5175 int DemoteStackIdx = -100; 5176 5177 if (!CanLowerReturn) { 5178 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5179 FTy->getReturnType()); 5180 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5181 FTy->getReturnType()); 5182 MachineFunction &MF = DAG.getMachineFunction(); 5183 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5184 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5185 5186 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5187 Entry.Node = DemoteStackSlot; 5188 Entry.Ty = StackSlotPtrType; 5189 Entry.isSExt = false; 5190 Entry.isZExt = false; 5191 Entry.isInReg = false; 5192 Entry.isSRet = true; 5193 Entry.isNest = false; 5194 Entry.isByVal = false; 5195 Entry.Alignment = Align; 5196 Args.push_back(Entry); 5197 RetTy = Type::getVoidTy(FTy->getContext()); 5198 } 5199 5200 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5201 i != e; ++i) { 5202 const Value *V = *i; 5203 5204 // Skip empty types 5205 if (V->getType()->isEmptyTy()) 5206 continue; 5207 5208 SDValue ArgNode = getValue(V); 5209 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5210 5211 unsigned attrInd = i - CS.arg_begin() + 1; 5212 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5213 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5214 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5215 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5216 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5217 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5218 Entry.Alignment = CS.getParamAlignment(attrInd); 5219 Args.push_back(Entry); 5220 } 5221 5222 if (LandingPad) { 5223 // Insert a label before the invoke call to mark the try range. This can be 5224 // used to detect deletion of the invoke via the MachineModuleInfo. 5225 BeginLabel = MMI.getContext().CreateTempSymbol(); 5226 5227 // For SjLj, keep track of which landing pads go with which invokes 5228 // so as to maintain the ordering of pads in the LSDA. 5229 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5230 if (CallSiteIndex) { 5231 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5232 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5233 5234 // Now that the call site is handled, stop tracking it. 5235 MMI.setCurrentCallSite(0); 5236 } 5237 5238 // Both PendingLoads and PendingExports must be flushed here; 5239 // this call might not return. 5240 (void)getRoot(); 5241 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5242 } 5243 5244 // Check if target-independent constraints permit a tail call here. 5245 // Target-dependent constraints are checked within TLI.LowerCallTo. 5246 if (isTailCall && 5247 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5248 isTailCall = false; 5249 5250 // If there's a possibility that fast-isel has already selected some amount 5251 // of the current basic block, don't emit a tail call. 5252 if (isTailCall && TM.Options.EnableFastISel) 5253 isTailCall = false; 5254 5255 std::pair<SDValue,SDValue> Result = 5256 TLI.LowerCallTo(getRoot(), RetTy, 5257 CS.paramHasAttr(0, Attribute::SExt), 5258 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 5259 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 5260 CS.getCallingConv(), 5261 isTailCall, 5262 CS.doesNotReturn(), 5263 !CS.getInstruction()->use_empty(), 5264 Callee, Args, DAG, getCurDebugLoc()); 5265 assert((isTailCall || Result.second.getNode()) && 5266 "Non-null chain expected with non-tail call!"); 5267 assert((Result.second.getNode() || !Result.first.getNode()) && 5268 "Null value expected with tail call!"); 5269 if (Result.first.getNode()) { 5270 setValue(CS.getInstruction(), Result.first); 5271 } else if (!CanLowerReturn && Result.second.getNode()) { 5272 // The instruction result is the result of loading from the 5273 // hidden sret parameter. 5274 SmallVector<EVT, 1> PVTs; 5275 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5276 5277 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5278 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5279 EVT PtrVT = PVTs[0]; 5280 unsigned NumValues = Outs.size(); 5281 SmallVector<SDValue, 4> Values(NumValues); 5282 SmallVector<SDValue, 4> Chains(NumValues); 5283 5284 for (unsigned i = 0; i < NumValues; ++i) { 5285 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5286 DemoteStackSlot, 5287 DAG.getConstant(Offsets[i], PtrVT)); 5288 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 5289 Add, 5290 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5291 false, false, false, 1); 5292 Values[i] = L; 5293 Chains[i] = L.getValue(1); 5294 } 5295 5296 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5297 MVT::Other, &Chains[0], NumValues); 5298 PendingLoads.push_back(Chain); 5299 5300 // Collect the legal value parts into potentially illegal values 5301 // that correspond to the original function's return values. 5302 SmallVector<EVT, 4> RetTys; 5303 RetTy = FTy->getReturnType(); 5304 ComputeValueVTs(TLI, RetTy, RetTys); 5305 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5306 SmallVector<SDValue, 4> ReturnValues; 5307 unsigned CurReg = 0; 5308 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5309 EVT VT = RetTys[I]; 5310 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 5311 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 5312 5313 SDValue ReturnValue = 5314 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 5315 RegisterVT, VT, AssertOp); 5316 ReturnValues.push_back(ReturnValue); 5317 CurReg += NumRegs; 5318 } 5319 5320 setValue(CS.getInstruction(), 5321 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5322 DAG.getVTList(&RetTys[0], RetTys.size()), 5323 &ReturnValues[0], ReturnValues.size())); 5324 } 5325 5326 // Assign order to nodes here. If the call does not produce a result, it won't 5327 // be mapped to a SDNode and visit() will not assign it an order number. 5328 if (!Result.second.getNode()) { 5329 // As a special case, a null chain means that a tail call has been emitted and 5330 // the DAG root is already updated. 5331 HasTailCall = true; 5332 ++SDNodeOrder; 5333 AssignOrderingToNode(DAG.getRoot().getNode()); 5334 } else { 5335 DAG.setRoot(Result.second); 5336 ++SDNodeOrder; 5337 AssignOrderingToNode(Result.second.getNode()); 5338 } 5339 5340 if (LandingPad) { 5341 // Insert a label at the end of the invoke call to mark the try range. This 5342 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5343 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5344 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5345 5346 // Inform MachineModuleInfo of range. 5347 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5348 } 5349} 5350 5351/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5352/// value is equal or not-equal to zero. 5353static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5354 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5355 UI != E; ++UI) { 5356 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5357 if (IC->isEquality()) 5358 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5359 if (C->isNullValue()) 5360 continue; 5361 // Unknown instruction. 5362 return false; 5363 } 5364 return true; 5365} 5366 5367static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5368 Type *LoadTy, 5369 SelectionDAGBuilder &Builder) { 5370 5371 // Check to see if this load can be trivially constant folded, e.g. if the 5372 // input is from a string literal. 5373 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5374 // Cast pointer to the type we really want to load. 5375 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5376 PointerType::getUnqual(LoadTy)); 5377 5378 if (const Constant *LoadCst = 5379 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5380 Builder.TD)) 5381 return Builder.getValue(LoadCst); 5382 } 5383 5384 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5385 // still constant memory, the input chain can be the entry node. 5386 SDValue Root; 5387 bool ConstantMemory = false; 5388 5389 // Do not serialize (non-volatile) loads of constant memory with anything. 5390 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5391 Root = Builder.DAG.getEntryNode(); 5392 ConstantMemory = true; 5393 } else { 5394 // Do not serialize non-volatile loads against each other. 5395 Root = Builder.DAG.getRoot(); 5396 } 5397 5398 SDValue Ptr = Builder.getValue(PtrVal); 5399 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5400 Ptr, MachinePointerInfo(PtrVal), 5401 false /*volatile*/, 5402 false /*nontemporal*/, 5403 false /*isinvariant*/, 1 /* align=1 */); 5404 5405 if (!ConstantMemory) 5406 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5407 return LoadVal; 5408} 5409 5410 5411/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5412/// If so, return true and lower it, otherwise return false and it will be 5413/// lowered like a normal call. 5414bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5415 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5416 if (I.getNumArgOperands() != 3) 5417 return false; 5418 5419 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5420 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5421 !I.getArgOperand(2)->getType()->isIntegerTy() || 5422 !I.getType()->isIntegerTy()) 5423 return false; 5424 5425 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5426 5427 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5428 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5429 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5430 bool ActuallyDoIt = true; 5431 MVT LoadVT; 5432 Type *LoadTy; 5433 switch (Size->getZExtValue()) { 5434 default: 5435 LoadVT = MVT::Other; 5436 LoadTy = 0; 5437 ActuallyDoIt = false; 5438 break; 5439 case 2: 5440 LoadVT = MVT::i16; 5441 LoadTy = Type::getInt16Ty(Size->getContext()); 5442 break; 5443 case 4: 5444 LoadVT = MVT::i32; 5445 LoadTy = Type::getInt32Ty(Size->getContext()); 5446 break; 5447 case 8: 5448 LoadVT = MVT::i64; 5449 LoadTy = Type::getInt64Ty(Size->getContext()); 5450 break; 5451 /* 5452 case 16: 5453 LoadVT = MVT::v4i32; 5454 LoadTy = Type::getInt32Ty(Size->getContext()); 5455 LoadTy = VectorType::get(LoadTy, 4); 5456 break; 5457 */ 5458 } 5459 5460 // This turns into unaligned loads. We only do this if the target natively 5461 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5462 // we'll only produce a small number of byte loads. 5463 5464 // Require that we can find a legal MVT, and only do this if the target 5465 // supports unaligned loads of that type. Expanding into byte loads would 5466 // bloat the code. 5467 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5468 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5469 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5470 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5471 ActuallyDoIt = false; 5472 } 5473 5474 if (ActuallyDoIt) { 5475 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5476 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5477 5478 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5479 ISD::SETNE); 5480 EVT CallVT = TLI.getValueType(I.getType(), true); 5481 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5482 return true; 5483 } 5484 } 5485 5486 5487 return false; 5488} 5489 5490 5491void SelectionDAGBuilder::visitCall(const CallInst &I) { 5492 // Handle inline assembly differently. 5493 if (isa<InlineAsm>(I.getCalledValue())) { 5494 visitInlineAsm(&I); 5495 return; 5496 } 5497 5498 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5499 ComputeUsesVAFloatArgument(I, &MMI); 5500 5501 const char *RenameFn = 0; 5502 if (Function *F = I.getCalledFunction()) { 5503 if (F->isDeclaration()) { 5504 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5505 if (unsigned IID = II->getIntrinsicID(F)) { 5506 RenameFn = visitIntrinsicCall(I, IID); 5507 if (!RenameFn) 5508 return; 5509 } 5510 } 5511 if (unsigned IID = F->getIntrinsicID()) { 5512 RenameFn = visitIntrinsicCall(I, IID); 5513 if (!RenameFn) 5514 return; 5515 } 5516 } 5517 5518 // Check for well-known libc/libm calls. If the function is internal, it 5519 // can't be a library call. 5520 if (!F->hasLocalLinkage() && F->hasName()) { 5521 StringRef Name = F->getName(); 5522 if ((LibInfo->has(LibFunc::copysign) && Name == "copysign") || 5523 (LibInfo->has(LibFunc::copysignf) && Name == "copysignf") || 5524 (LibInfo->has(LibFunc::copysignl) && Name == "copysignl")) { 5525 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5526 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5527 I.getType() == I.getArgOperand(0)->getType() && 5528 I.getType() == I.getArgOperand(1)->getType()) { 5529 SDValue LHS = getValue(I.getArgOperand(0)); 5530 SDValue RHS = getValue(I.getArgOperand(1)); 5531 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5532 LHS.getValueType(), LHS, RHS)); 5533 return; 5534 } 5535 } else if ((LibInfo->has(LibFunc::fabs) && Name == "fabs") || 5536 (LibInfo->has(LibFunc::fabsf) && Name == "fabsf") || 5537 (LibInfo->has(LibFunc::fabsl) && Name == "fabsl")) { 5538 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5539 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5540 I.getType() == I.getArgOperand(0)->getType()) { 5541 SDValue Tmp = getValue(I.getArgOperand(0)); 5542 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5543 Tmp.getValueType(), Tmp)); 5544 return; 5545 } 5546 } else if ((LibInfo->has(LibFunc::sin) && Name == "sin") || 5547 (LibInfo->has(LibFunc::sinf) && Name == "sinf") || 5548 (LibInfo->has(LibFunc::sinl) && Name == "sinl")) { 5549 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5550 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5551 I.getType() == I.getArgOperand(0)->getType() && 5552 I.onlyReadsMemory()) { 5553 SDValue Tmp = getValue(I.getArgOperand(0)); 5554 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5555 Tmp.getValueType(), Tmp)); 5556 return; 5557 } 5558 } else if ((LibInfo->has(LibFunc::cos) && Name == "cos") || 5559 (LibInfo->has(LibFunc::cosf) && Name == "cosf") || 5560 (LibInfo->has(LibFunc::cosl) && Name == "cosl")) { 5561 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5562 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5563 I.getType() == I.getArgOperand(0)->getType() && 5564 I.onlyReadsMemory()) { 5565 SDValue Tmp = getValue(I.getArgOperand(0)); 5566 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5567 Tmp.getValueType(), Tmp)); 5568 return; 5569 } 5570 } else if ((LibInfo->has(LibFunc::sqrt) && Name == "sqrt") || 5571 (LibInfo->has(LibFunc::sqrtf) && Name == "sqrtf") || 5572 (LibInfo->has(LibFunc::sqrtl) && Name == "sqrtl")) { 5573 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5574 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5575 I.getType() == I.getArgOperand(0)->getType() && 5576 I.onlyReadsMemory()) { 5577 SDValue Tmp = getValue(I.getArgOperand(0)); 5578 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5579 Tmp.getValueType(), Tmp)); 5580 return; 5581 } 5582 } else if ((LibInfo->has(LibFunc::floor) && Name == "floor") || 5583 (LibInfo->has(LibFunc::floorf) && Name == "floorf") || 5584 (LibInfo->has(LibFunc::floorl) && Name == "floorl")) { 5585 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5586 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5587 I.getType() == I.getArgOperand(0)->getType()) { 5588 SDValue Tmp = getValue(I.getArgOperand(0)); 5589 setValue(&I, DAG.getNode(ISD::FFLOOR, getCurDebugLoc(), 5590 Tmp.getValueType(), Tmp)); 5591 return; 5592 } 5593 } else if ((LibInfo->has(LibFunc::nearbyint) && Name == "nearbyint") || 5594 (LibInfo->has(LibFunc::nearbyintf) && Name == "nearbyintf") || 5595 (LibInfo->has(LibFunc::nearbyintl) && Name == "nearbyintl")) { 5596 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5597 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5598 I.getType() == I.getArgOperand(0)->getType()) { 5599 SDValue Tmp = getValue(I.getArgOperand(0)); 5600 setValue(&I, DAG.getNode(ISD::FNEARBYINT, getCurDebugLoc(), 5601 Tmp.getValueType(), Tmp)); 5602 return; 5603 } 5604 } else if ((LibInfo->has(LibFunc::ceil) && Name == "ceil") || 5605 (LibInfo->has(LibFunc::ceilf) && Name == "ceilf") || 5606 (LibInfo->has(LibFunc::ceill) && Name == "ceill")) { 5607 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5608 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5609 I.getType() == I.getArgOperand(0)->getType()) { 5610 SDValue Tmp = getValue(I.getArgOperand(0)); 5611 setValue(&I, DAG.getNode(ISD::FCEIL, getCurDebugLoc(), 5612 Tmp.getValueType(), Tmp)); 5613 return; 5614 } 5615 } else if ((LibInfo->has(LibFunc::rint) && Name == "rint") || 5616 (LibInfo->has(LibFunc::rintf) && Name == "rintf") || 5617 (LibInfo->has(LibFunc::rintl) && Name == "rintl")) { 5618 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5619 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5620 I.getType() == I.getArgOperand(0)->getType()) { 5621 SDValue Tmp = getValue(I.getArgOperand(0)); 5622 setValue(&I, DAG.getNode(ISD::FRINT, getCurDebugLoc(), 5623 Tmp.getValueType(), Tmp)); 5624 return; 5625 } 5626 } else if ((LibInfo->has(LibFunc::trunc) && Name == "trunc") || 5627 (LibInfo->has(LibFunc::truncf) && Name == "truncf") || 5628 (LibInfo->has(LibFunc::truncl) && Name == "truncl")) { 5629 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5630 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5631 I.getType() == I.getArgOperand(0)->getType()) { 5632 SDValue Tmp = getValue(I.getArgOperand(0)); 5633 setValue(&I, DAG.getNode(ISD::FTRUNC, getCurDebugLoc(), 5634 Tmp.getValueType(), Tmp)); 5635 return; 5636 } 5637 } else if ((LibInfo->has(LibFunc::log2) && Name == "log2") || 5638 (LibInfo->has(LibFunc::log2f) && Name == "log2f") || 5639 (LibInfo->has(LibFunc::log2l) && Name == "log2l")) { 5640 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5641 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5642 I.getType() == I.getArgOperand(0)->getType() && 5643 I.onlyReadsMemory()) { 5644 SDValue Tmp = getValue(I.getArgOperand(0)); 5645 setValue(&I, DAG.getNode(ISD::FLOG2, getCurDebugLoc(), 5646 Tmp.getValueType(), Tmp)); 5647 return; 5648 } 5649 } else if ((LibInfo->has(LibFunc::exp2) && Name == "exp2") || 5650 (LibInfo->has(LibFunc::exp2f) && Name == "exp2f") || 5651 (LibInfo->has(LibFunc::exp2l) && Name == "exp2l")) { 5652 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5653 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5654 I.getType() == I.getArgOperand(0)->getType() && 5655 I.onlyReadsMemory()) { 5656 SDValue Tmp = getValue(I.getArgOperand(0)); 5657 setValue(&I, DAG.getNode(ISD::FEXP2, getCurDebugLoc(), 5658 Tmp.getValueType(), Tmp)); 5659 return; 5660 } 5661 } else if (Name == "memcmp") { 5662 if (visitMemCmpCall(I)) 5663 return; 5664 } 5665 } 5666 } 5667 5668 SDValue Callee; 5669 if (!RenameFn) 5670 Callee = getValue(I.getCalledValue()); 5671 else 5672 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5673 5674 // Check if we can potentially perform a tail call. More detailed checking is 5675 // be done within LowerCallTo, after more information about the call is known. 5676 LowerCallTo(&I, Callee, I.isTailCall()); 5677} 5678 5679namespace { 5680 5681/// AsmOperandInfo - This contains information for each constraint that we are 5682/// lowering. 5683class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5684public: 5685 /// CallOperand - If this is the result output operand or a clobber 5686 /// this is null, otherwise it is the incoming operand to the CallInst. 5687 /// This gets modified as the asm is processed. 5688 SDValue CallOperand; 5689 5690 /// AssignedRegs - If this is a register or register class operand, this 5691 /// contains the set of register corresponding to the operand. 5692 RegsForValue AssignedRegs; 5693 5694 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5695 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5696 } 5697 5698 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5699 /// corresponds to. If there is no Value* for this operand, it returns 5700 /// MVT::Other. 5701 EVT getCallOperandValEVT(LLVMContext &Context, 5702 const TargetLowering &TLI, 5703 const TargetData *TD) const { 5704 if (CallOperandVal == 0) return MVT::Other; 5705 5706 if (isa<BasicBlock>(CallOperandVal)) 5707 return TLI.getPointerTy(); 5708 5709 llvm::Type *OpTy = CallOperandVal->getType(); 5710 5711 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5712 // If this is an indirect operand, the operand is a pointer to the 5713 // accessed type. 5714 if (isIndirect) { 5715 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5716 if (!PtrTy) 5717 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5718 OpTy = PtrTy->getElementType(); 5719 } 5720 5721 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5722 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5723 if (STy->getNumElements() == 1) 5724 OpTy = STy->getElementType(0); 5725 5726 // If OpTy is not a single value, it may be a struct/union that we 5727 // can tile with integers. 5728 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5729 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5730 switch (BitSize) { 5731 default: break; 5732 case 1: 5733 case 8: 5734 case 16: 5735 case 32: 5736 case 64: 5737 case 128: 5738 OpTy = IntegerType::get(Context, BitSize); 5739 break; 5740 } 5741 } 5742 5743 return TLI.getValueType(OpTy, true); 5744 } 5745}; 5746 5747typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5748 5749} // end anonymous namespace 5750 5751/// GetRegistersForValue - Assign registers (virtual or physical) for the 5752/// specified operand. We prefer to assign virtual registers, to allow the 5753/// register allocator to handle the assignment process. However, if the asm 5754/// uses features that we can't model on machineinstrs, we have SDISel do the 5755/// allocation. This produces generally horrible, but correct, code. 5756/// 5757/// OpInfo describes the operand. 5758/// 5759static void GetRegistersForValue(SelectionDAG &DAG, 5760 const TargetLowering &TLI, 5761 DebugLoc DL, 5762 SDISelAsmOperandInfo &OpInfo) { 5763 LLVMContext &Context = *DAG.getContext(); 5764 5765 MachineFunction &MF = DAG.getMachineFunction(); 5766 SmallVector<unsigned, 4> Regs; 5767 5768 // If this is a constraint for a single physreg, or a constraint for a 5769 // register class, find it. 5770 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5771 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5772 OpInfo.ConstraintVT); 5773 5774 unsigned NumRegs = 1; 5775 if (OpInfo.ConstraintVT != MVT::Other) { 5776 // If this is a FP input in an integer register (or visa versa) insert a bit 5777 // cast of the input value. More generally, handle any case where the input 5778 // value disagrees with the register class we plan to stick this in. 5779 if (OpInfo.Type == InlineAsm::isInput && 5780 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5781 // Try to convert to the first EVT that the reg class contains. If the 5782 // types are identical size, use a bitcast to convert (e.g. two differing 5783 // vector types). 5784 EVT RegVT = *PhysReg.second->vt_begin(); 5785 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5786 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5787 RegVT, OpInfo.CallOperand); 5788 OpInfo.ConstraintVT = RegVT; 5789 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5790 // If the input is a FP value and we want it in FP registers, do a 5791 // bitcast to the corresponding integer type. This turns an f64 value 5792 // into i64, which can be passed with two i32 values on a 32-bit 5793 // machine. 5794 RegVT = EVT::getIntegerVT(Context, 5795 OpInfo.ConstraintVT.getSizeInBits()); 5796 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5797 RegVT, OpInfo.CallOperand); 5798 OpInfo.ConstraintVT = RegVT; 5799 } 5800 } 5801 5802 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5803 } 5804 5805 EVT RegVT; 5806 EVT ValueVT = OpInfo.ConstraintVT; 5807 5808 // If this is a constraint for a specific physical register, like {r17}, 5809 // assign it now. 5810 if (unsigned AssignedReg = PhysReg.first) { 5811 const TargetRegisterClass *RC = PhysReg.second; 5812 if (OpInfo.ConstraintVT == MVT::Other) 5813 ValueVT = *RC->vt_begin(); 5814 5815 // Get the actual register value type. This is important, because the user 5816 // may have asked for (e.g.) the AX register in i32 type. We need to 5817 // remember that AX is actually i16 to get the right extension. 5818 RegVT = *RC->vt_begin(); 5819 5820 // This is a explicit reference to a physical register. 5821 Regs.push_back(AssignedReg); 5822 5823 // If this is an expanded reference, add the rest of the regs to Regs. 5824 if (NumRegs != 1) { 5825 TargetRegisterClass::iterator I = RC->begin(); 5826 for (; *I != AssignedReg; ++I) 5827 assert(I != RC->end() && "Didn't find reg!"); 5828 5829 // Already added the first reg. 5830 --NumRegs; ++I; 5831 for (; NumRegs; --NumRegs, ++I) { 5832 assert(I != RC->end() && "Ran out of registers to allocate!"); 5833 Regs.push_back(*I); 5834 } 5835 } 5836 5837 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5838 return; 5839 } 5840 5841 // Otherwise, if this was a reference to an LLVM register class, create vregs 5842 // for this reference. 5843 if (const TargetRegisterClass *RC = PhysReg.second) { 5844 RegVT = *RC->vt_begin(); 5845 if (OpInfo.ConstraintVT == MVT::Other) 5846 ValueVT = RegVT; 5847 5848 // Create the appropriate number of virtual registers. 5849 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5850 for (; NumRegs; --NumRegs) 5851 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5852 5853 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5854 return; 5855 } 5856 5857 // Otherwise, we couldn't allocate enough registers for this. 5858} 5859 5860/// visitInlineAsm - Handle a call to an InlineAsm object. 5861/// 5862void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5863 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5864 5865 /// ConstraintOperands - Information about all of the constraints. 5866 SDISelAsmOperandInfoVector ConstraintOperands; 5867 5868 TargetLowering::AsmOperandInfoVector 5869 TargetConstraints = TLI.ParseConstraints(CS); 5870 5871 bool hasMemory = false; 5872 5873 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5874 unsigned ResNo = 0; // ResNo - The result number of the next output. 5875 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5876 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5877 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5878 5879 EVT OpVT = MVT::Other; 5880 5881 // Compute the value type for each operand. 5882 switch (OpInfo.Type) { 5883 case InlineAsm::isOutput: 5884 // Indirect outputs just consume an argument. 5885 if (OpInfo.isIndirect) { 5886 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5887 break; 5888 } 5889 5890 // The return value of the call is this value. As such, there is no 5891 // corresponding argument. 5892 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5893 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5894 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5895 } else { 5896 assert(ResNo == 0 && "Asm only has one result!"); 5897 OpVT = TLI.getValueType(CS.getType()); 5898 } 5899 ++ResNo; 5900 break; 5901 case InlineAsm::isInput: 5902 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5903 break; 5904 case InlineAsm::isClobber: 5905 // Nothing to do. 5906 break; 5907 } 5908 5909 // If this is an input or an indirect output, process the call argument. 5910 // BasicBlocks are labels, currently appearing only in asm's. 5911 if (OpInfo.CallOperandVal) { 5912 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5913 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5914 } else { 5915 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5916 } 5917 5918 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5919 } 5920 5921 OpInfo.ConstraintVT = OpVT; 5922 5923 // Indirect operand accesses access memory. 5924 if (OpInfo.isIndirect) 5925 hasMemory = true; 5926 else { 5927 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5928 TargetLowering::ConstraintType 5929 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5930 if (CType == TargetLowering::C_Memory) { 5931 hasMemory = true; 5932 break; 5933 } 5934 } 5935 } 5936 } 5937 5938 SDValue Chain, Flag; 5939 5940 // We won't need to flush pending loads if this asm doesn't touch 5941 // memory and is nonvolatile. 5942 if (hasMemory || IA->hasSideEffects()) 5943 Chain = getRoot(); 5944 else 5945 Chain = DAG.getRoot(); 5946 5947 // Second pass over the constraints: compute which constraint option to use 5948 // and assign registers to constraints that want a specific physreg. 5949 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5950 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5951 5952 // If this is an output operand with a matching input operand, look up the 5953 // matching input. If their types mismatch, e.g. one is an integer, the 5954 // other is floating point, or their sizes are different, flag it as an 5955 // error. 5956 if (OpInfo.hasMatchingInput()) { 5957 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5958 5959 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5960 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5961 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5962 OpInfo.ConstraintVT); 5963 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5964 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 5965 Input.ConstraintVT); 5966 if ((OpInfo.ConstraintVT.isInteger() != 5967 Input.ConstraintVT.isInteger()) || 5968 (MatchRC.second != InputRC.second)) { 5969 report_fatal_error("Unsupported asm: input constraint" 5970 " with a matching output constraint of" 5971 " incompatible type!"); 5972 } 5973 Input.ConstraintVT = OpInfo.ConstraintVT; 5974 } 5975 } 5976 5977 // Compute the constraint code and ConstraintType to use. 5978 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5979 5980 // If this is a memory input, and if the operand is not indirect, do what we 5981 // need to to provide an address for the memory input. 5982 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5983 !OpInfo.isIndirect) { 5984 assert((OpInfo.isMultipleAlternative || 5985 (OpInfo.Type == InlineAsm::isInput)) && 5986 "Can only indirectify direct input operands!"); 5987 5988 // Memory operands really want the address of the value. If we don't have 5989 // an indirect input, put it in the constpool if we can, otherwise spill 5990 // it to a stack slot. 5991 // TODO: This isn't quite right. We need to handle these according to 5992 // the addressing mode that the constraint wants. Also, this may take 5993 // an additional register for the computation and we don't want that 5994 // either. 5995 5996 // If the operand is a float, integer, or vector constant, spill to a 5997 // constant pool entry to get its address. 5998 const Value *OpVal = OpInfo.CallOperandVal; 5999 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 6000 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { 6001 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 6002 TLI.getPointerTy()); 6003 } else { 6004 // Otherwise, create a stack slot and emit a store to it before the 6005 // asm. 6006 Type *Ty = OpVal->getType(); 6007 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 6008 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 6009 MachineFunction &MF = DAG.getMachineFunction(); 6010 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 6011 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 6012 Chain = DAG.getStore(Chain, getCurDebugLoc(), 6013 OpInfo.CallOperand, StackSlot, 6014 MachinePointerInfo::getFixedStack(SSFI), 6015 false, false, 0); 6016 OpInfo.CallOperand = StackSlot; 6017 } 6018 6019 // There is no longer a Value* corresponding to this operand. 6020 OpInfo.CallOperandVal = 0; 6021 6022 // It is now an indirect operand. 6023 OpInfo.isIndirect = true; 6024 } 6025 6026 // If this constraint is for a specific register, allocate it before 6027 // anything else. 6028 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6029 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6030 } 6031 6032 // Second pass - Loop over all of the operands, assigning virtual or physregs 6033 // to register class operands. 6034 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6035 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6036 6037 // C_Register operands have already been allocated, Other/Memory don't need 6038 // to be. 6039 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6040 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6041 } 6042 6043 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6044 std::vector<SDValue> AsmNodeOperands; 6045 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6046 AsmNodeOperands.push_back( 6047 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6048 TLI.getPointerTy())); 6049 6050 // If we have a !srcloc metadata node associated with it, we want to attach 6051 // this to the ultimately generated inline asm machineinstr. To do this, we 6052 // pass in the third operand as this (potentially null) inline asm MDNode. 6053 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6054 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6055 6056 // Remember the HasSideEffect and AlignStack bits as operand 3. 6057 unsigned ExtraInfo = 0; 6058 if (IA->hasSideEffects()) 6059 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6060 if (IA->isAlignStack()) 6061 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6062 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6063 TLI.getPointerTy())); 6064 6065 // Loop over all of the inputs, copying the operand values into the 6066 // appropriate registers and processing the output regs. 6067 RegsForValue RetValRegs; 6068 6069 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6070 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6071 6072 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6073 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6074 6075 switch (OpInfo.Type) { 6076 case InlineAsm::isOutput: { 6077 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6078 OpInfo.ConstraintType != TargetLowering::C_Register) { 6079 // Memory output, or 'other' output (e.g. 'X' constraint). 6080 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6081 6082 // Add information to the INLINEASM node to know about this output. 6083 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6084 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6085 TLI.getPointerTy())); 6086 AsmNodeOperands.push_back(OpInfo.CallOperand); 6087 break; 6088 } 6089 6090 // Otherwise, this is a register or register class output. 6091 6092 // Copy the output from the appropriate register. Find a register that 6093 // we can use. 6094 if (OpInfo.AssignedRegs.Regs.empty()) { 6095 LLVMContext &Ctx = *DAG.getContext(); 6096 Ctx.emitError(CS.getInstruction(), 6097 "couldn't allocate output register for constraint '" + 6098 Twine(OpInfo.ConstraintCode) + "'"); 6099 break; 6100 } 6101 6102 // If this is an indirect operand, store through the pointer after the 6103 // asm. 6104 if (OpInfo.isIndirect) { 6105 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6106 OpInfo.CallOperandVal)); 6107 } else { 6108 // This is the result value of the call. 6109 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6110 // Concatenate this output onto the outputs list. 6111 RetValRegs.append(OpInfo.AssignedRegs); 6112 } 6113 6114 // Add information to the INLINEASM node to know that this register is 6115 // set. 6116 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6117 InlineAsm::Kind_RegDefEarlyClobber : 6118 InlineAsm::Kind_RegDef, 6119 false, 6120 0, 6121 DAG, 6122 AsmNodeOperands); 6123 break; 6124 } 6125 case InlineAsm::isInput: { 6126 SDValue InOperandVal = OpInfo.CallOperand; 6127 6128 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6129 // If this is required to match an output register we have already set, 6130 // just use its register. 6131 unsigned OperandNo = OpInfo.getMatchedOperand(); 6132 6133 // Scan until we find the definition we already emitted of this operand. 6134 // When we find it, create a RegsForValue operand. 6135 unsigned CurOp = InlineAsm::Op_FirstOperand; 6136 for (; OperandNo; --OperandNo) { 6137 // Advance to the next operand. 6138 unsigned OpFlag = 6139 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6140 assert((InlineAsm::isRegDefKind(OpFlag) || 6141 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6142 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6143 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6144 } 6145 6146 unsigned OpFlag = 6147 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6148 if (InlineAsm::isRegDefKind(OpFlag) || 6149 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6150 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6151 if (OpInfo.isIndirect) { 6152 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6153 LLVMContext &Ctx = *DAG.getContext(); 6154 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6155 " don't know how to handle tied " 6156 "indirect register inputs"); 6157 } 6158 6159 RegsForValue MatchedRegs; 6160 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6161 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6162 MatchedRegs.RegVTs.push_back(RegVT); 6163 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6164 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6165 i != e; ++i) 6166 MatchedRegs.Regs.push_back 6167 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6168 6169 // Use the produced MatchedRegs object to 6170 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6171 Chain, &Flag); 6172 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6173 true, OpInfo.getMatchedOperand(), 6174 DAG, AsmNodeOperands); 6175 break; 6176 } 6177 6178 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6179 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6180 "Unexpected number of operands"); 6181 // Add information to the INLINEASM node to know about this input. 6182 // See InlineAsm.h isUseOperandTiedToDef. 6183 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6184 OpInfo.getMatchedOperand()); 6185 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6186 TLI.getPointerTy())); 6187 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6188 break; 6189 } 6190 6191 // Treat indirect 'X' constraint as memory. 6192 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6193 OpInfo.isIndirect) 6194 OpInfo.ConstraintType = TargetLowering::C_Memory; 6195 6196 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6197 std::vector<SDValue> Ops; 6198 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6199 Ops, DAG); 6200 if (Ops.empty()) { 6201 LLVMContext &Ctx = *DAG.getContext(); 6202 Ctx.emitError(CS.getInstruction(), 6203 "invalid operand for inline asm constraint '" + 6204 Twine(OpInfo.ConstraintCode) + "'"); 6205 break; 6206 } 6207 6208 // Add information to the INLINEASM node to know about this input. 6209 unsigned ResOpType = 6210 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6211 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6212 TLI.getPointerTy())); 6213 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6214 break; 6215 } 6216 6217 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6218 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6219 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6220 "Memory operands expect pointer values"); 6221 6222 // Add information to the INLINEASM node to know about this input. 6223 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6224 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6225 TLI.getPointerTy())); 6226 AsmNodeOperands.push_back(InOperandVal); 6227 break; 6228 } 6229 6230 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6231 OpInfo.ConstraintType == TargetLowering::C_Register) && 6232 "Unknown constraint type!"); 6233 assert(!OpInfo.isIndirect && 6234 "Don't know how to handle indirect register inputs yet!"); 6235 6236 // Copy the input into the appropriate registers. 6237 if (OpInfo.AssignedRegs.Regs.empty()) { 6238 LLVMContext &Ctx = *DAG.getContext(); 6239 Ctx.emitError(CS.getInstruction(), 6240 "couldn't allocate input reg for constraint '" + 6241 Twine(OpInfo.ConstraintCode) + "'"); 6242 break; 6243 } 6244 6245 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6246 Chain, &Flag); 6247 6248 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6249 DAG, AsmNodeOperands); 6250 break; 6251 } 6252 case InlineAsm::isClobber: { 6253 // Add the clobbered value to the operand list, so that the register 6254 // allocator is aware that the physreg got clobbered. 6255 if (!OpInfo.AssignedRegs.Regs.empty()) 6256 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6257 false, 0, DAG, 6258 AsmNodeOperands); 6259 break; 6260 } 6261 } 6262 } 6263 6264 // Finish up input operands. Set the input chain and add the flag last. 6265 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6266 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6267 6268 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6269 DAG.getVTList(MVT::Other, MVT::Glue), 6270 &AsmNodeOperands[0], AsmNodeOperands.size()); 6271 Flag = Chain.getValue(1); 6272 6273 // If this asm returns a register value, copy the result from that register 6274 // and set it as the value of the call. 6275 if (!RetValRegs.Regs.empty()) { 6276 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6277 Chain, &Flag); 6278 6279 // FIXME: Why don't we do this for inline asms with MRVs? 6280 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6281 EVT ResultType = TLI.getValueType(CS.getType()); 6282 6283 // If any of the results of the inline asm is a vector, it may have the 6284 // wrong width/num elts. This can happen for register classes that can 6285 // contain multiple different value types. The preg or vreg allocated may 6286 // not have the same VT as was expected. Convert it to the right type 6287 // with bit_convert. 6288 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6289 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6290 ResultType, Val); 6291 6292 } else if (ResultType != Val.getValueType() && 6293 ResultType.isInteger() && Val.getValueType().isInteger()) { 6294 // If a result value was tied to an input value, the computed result may 6295 // have a wider width than the expected result. Extract the relevant 6296 // portion. 6297 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6298 } 6299 6300 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6301 } 6302 6303 setValue(CS.getInstruction(), Val); 6304 // Don't need to use this as a chain in this case. 6305 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6306 return; 6307 } 6308 6309 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6310 6311 // Process indirect outputs, first output all of the flagged copies out of 6312 // physregs. 6313 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6314 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6315 const Value *Ptr = IndirectStoresToEmit[i].second; 6316 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6317 Chain, &Flag); 6318 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6319 } 6320 6321 // Emit the non-flagged stores from the physregs. 6322 SmallVector<SDValue, 8> OutChains; 6323 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6324 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6325 StoresToEmit[i].first, 6326 getValue(StoresToEmit[i].second), 6327 MachinePointerInfo(StoresToEmit[i].second), 6328 false, false, 0); 6329 OutChains.push_back(Val); 6330 } 6331 6332 if (!OutChains.empty()) 6333 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6334 &OutChains[0], OutChains.size()); 6335 6336 DAG.setRoot(Chain); 6337} 6338 6339void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6340 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6341 MVT::Other, getRoot(), 6342 getValue(I.getArgOperand(0)), 6343 DAG.getSrcValue(I.getArgOperand(0)))); 6344} 6345 6346void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6347 const TargetData &TD = *TLI.getTargetData(); 6348 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6349 getRoot(), getValue(I.getOperand(0)), 6350 DAG.getSrcValue(I.getOperand(0)), 6351 TD.getABITypeAlignment(I.getType())); 6352 setValue(&I, V); 6353 DAG.setRoot(V.getValue(1)); 6354} 6355 6356void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6357 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6358 MVT::Other, getRoot(), 6359 getValue(I.getArgOperand(0)), 6360 DAG.getSrcValue(I.getArgOperand(0)))); 6361} 6362 6363void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6364 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6365 MVT::Other, getRoot(), 6366 getValue(I.getArgOperand(0)), 6367 getValue(I.getArgOperand(1)), 6368 DAG.getSrcValue(I.getArgOperand(0)), 6369 DAG.getSrcValue(I.getArgOperand(1)))); 6370} 6371 6372/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6373/// implementation, which just calls LowerCall. 6374/// FIXME: When all targets are 6375/// migrated to using LowerCall, this hook should be integrated into SDISel. 6376std::pair<SDValue, SDValue> 6377TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy, 6378 bool RetSExt, bool RetZExt, bool isVarArg, 6379 bool isInreg, unsigned NumFixedArgs, 6380 CallingConv::ID CallConv, bool isTailCall, 6381 bool doesNotRet, bool isReturnValueUsed, 6382 SDValue Callee, 6383 ArgListTy &Args, SelectionDAG &DAG, 6384 DebugLoc dl) const { 6385 // Handle all of the outgoing arguments. 6386 SmallVector<ISD::OutputArg, 32> Outs; 6387 SmallVector<SDValue, 32> OutVals; 6388 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6389 SmallVector<EVT, 4> ValueVTs; 6390 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6391 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6392 Value != NumValues; ++Value) { 6393 EVT VT = ValueVTs[Value]; 6394 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6395 SDValue Op = SDValue(Args[i].Node.getNode(), 6396 Args[i].Node.getResNo() + Value); 6397 ISD::ArgFlagsTy Flags; 6398 unsigned OriginalAlignment = 6399 getTargetData()->getABITypeAlignment(ArgTy); 6400 6401 if (Args[i].isZExt) 6402 Flags.setZExt(); 6403 if (Args[i].isSExt) 6404 Flags.setSExt(); 6405 if (Args[i].isInReg) 6406 Flags.setInReg(); 6407 if (Args[i].isSRet) 6408 Flags.setSRet(); 6409 if (Args[i].isByVal) { 6410 Flags.setByVal(); 6411 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6412 Type *ElementTy = Ty->getElementType(); 6413 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6414 // For ByVal, alignment should come from FE. BE will guess if this 6415 // info is not there but there are cases it cannot get right. 6416 unsigned FrameAlign; 6417 if (Args[i].Alignment) 6418 FrameAlign = Args[i].Alignment; 6419 else 6420 FrameAlign = getByValTypeAlignment(ElementTy); 6421 Flags.setByValAlign(FrameAlign); 6422 } 6423 if (Args[i].isNest) 6424 Flags.setNest(); 6425 Flags.setOrigAlign(OriginalAlignment); 6426 6427 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6428 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6429 SmallVector<SDValue, 4> Parts(NumParts); 6430 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6431 6432 if (Args[i].isSExt) 6433 ExtendKind = ISD::SIGN_EXTEND; 6434 else if (Args[i].isZExt) 6435 ExtendKind = ISD::ZERO_EXTEND; 6436 6437 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6438 PartVT, ExtendKind); 6439 6440 for (unsigned j = 0; j != NumParts; ++j) { 6441 // if it isn't first piece, alignment must be 1 6442 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6443 i < NumFixedArgs); 6444 if (NumParts > 1 && j == 0) 6445 MyFlags.Flags.setSplit(); 6446 else if (j != 0) 6447 MyFlags.Flags.setOrigAlign(1); 6448 6449 Outs.push_back(MyFlags); 6450 OutVals.push_back(Parts[j]); 6451 } 6452 } 6453 } 6454 6455 // Handle the incoming return values from the call. 6456 SmallVector<ISD::InputArg, 32> Ins; 6457 SmallVector<EVT, 4> RetTys; 6458 ComputeValueVTs(*this, RetTy, RetTys); 6459 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6460 EVT VT = RetTys[I]; 6461 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6462 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6463 for (unsigned i = 0; i != NumRegs; ++i) { 6464 ISD::InputArg MyFlags; 6465 MyFlags.VT = RegisterVT.getSimpleVT(); 6466 MyFlags.Used = isReturnValueUsed; 6467 if (RetSExt) 6468 MyFlags.Flags.setSExt(); 6469 if (RetZExt) 6470 MyFlags.Flags.setZExt(); 6471 if (isInreg) 6472 MyFlags.Flags.setInReg(); 6473 Ins.push_back(MyFlags); 6474 } 6475 } 6476 6477 SmallVector<SDValue, 4> InVals; 6478 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, doesNotRet, isTailCall, 6479 Outs, OutVals, Ins, dl, DAG, InVals); 6480 6481 // Verify that the target's LowerCall behaved as expected. 6482 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6483 "LowerCall didn't return a valid chain!"); 6484 assert((!isTailCall || InVals.empty()) && 6485 "LowerCall emitted a return value for a tail call!"); 6486 assert((isTailCall || InVals.size() == Ins.size()) && 6487 "LowerCall didn't emit the correct number of values!"); 6488 6489 // For a tail call, the return value is merely live-out and there aren't 6490 // any nodes in the DAG representing it. Return a special value to 6491 // indicate that a tail call has been emitted and no more Instructions 6492 // should be processed in the current block. 6493 if (isTailCall) { 6494 DAG.setRoot(Chain); 6495 return std::make_pair(SDValue(), SDValue()); 6496 } 6497 6498 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6499 assert(InVals[i].getNode() && 6500 "LowerCall emitted a null value!"); 6501 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6502 "LowerCall emitted a value with the wrong type!"); 6503 }); 6504 6505 // Collect the legal value parts into potentially illegal values 6506 // that correspond to the original function's return values. 6507 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6508 if (RetSExt) 6509 AssertOp = ISD::AssertSext; 6510 else if (RetZExt) 6511 AssertOp = ISD::AssertZext; 6512 SmallVector<SDValue, 4> ReturnValues; 6513 unsigned CurReg = 0; 6514 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6515 EVT VT = RetTys[I]; 6516 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6517 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6518 6519 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6520 NumRegs, RegisterVT, VT, 6521 AssertOp)); 6522 CurReg += NumRegs; 6523 } 6524 6525 // For a function returning void, there is no return value. We can't create 6526 // such a node, so we just return a null return value in that case. In 6527 // that case, nothing will actually look at the value. 6528 if (ReturnValues.empty()) 6529 return std::make_pair(SDValue(), Chain); 6530 6531 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6532 DAG.getVTList(&RetTys[0], RetTys.size()), 6533 &ReturnValues[0], ReturnValues.size()); 6534 return std::make_pair(Res, Chain); 6535} 6536 6537void TargetLowering::LowerOperationWrapper(SDNode *N, 6538 SmallVectorImpl<SDValue> &Results, 6539 SelectionDAG &DAG) const { 6540 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6541 if (Res.getNode()) 6542 Results.push_back(Res); 6543} 6544 6545SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6546 llvm_unreachable("LowerOperation not implemented for this target!"); 6547} 6548 6549void 6550SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6551 SDValue Op = getNonRegisterValue(V); 6552 assert((Op.getOpcode() != ISD::CopyFromReg || 6553 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6554 "Copy from a reg to the same reg!"); 6555 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6556 6557 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6558 SDValue Chain = DAG.getEntryNode(); 6559 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6560 PendingExports.push_back(Chain); 6561} 6562 6563#include "llvm/CodeGen/SelectionDAGISel.h" 6564 6565/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6566/// entry block, return true. This includes arguments used by switches, since 6567/// the switch may expand into multiple basic blocks. 6568static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 6569 // With FastISel active, we may be splitting blocks, so force creation 6570 // of virtual registers for all non-dead arguments. 6571 if (FastISel) 6572 return A->use_empty(); 6573 6574 const BasicBlock *Entry = A->getParent()->begin(); 6575 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6576 UI != E; ++UI) { 6577 const User *U = *UI; 6578 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6579 return false; // Use not in entry block. 6580 } 6581 return true; 6582} 6583 6584void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6585 // If this is the entry block, emit arguments. 6586 const Function &F = *LLVMBB->getParent(); 6587 SelectionDAG &DAG = SDB->DAG; 6588 DebugLoc dl = SDB->getCurDebugLoc(); 6589 const TargetData *TD = TLI.getTargetData(); 6590 SmallVector<ISD::InputArg, 16> Ins; 6591 6592 // Check whether the function can return without sret-demotion. 6593 SmallVector<ISD::OutputArg, 4> Outs; 6594 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6595 Outs, TLI); 6596 6597 if (!FuncInfo->CanLowerReturn) { 6598 // Put in an sret pointer parameter before all the other parameters. 6599 SmallVector<EVT, 1> ValueVTs; 6600 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6601 6602 // NOTE: Assuming that a pointer will never break down to more than one VT 6603 // or one register. 6604 ISD::ArgFlagsTy Flags; 6605 Flags.setSRet(); 6606 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6607 ISD::InputArg RetArg(Flags, RegisterVT, true); 6608 Ins.push_back(RetArg); 6609 } 6610 6611 // Set up the incoming argument description vector. 6612 unsigned Idx = 1; 6613 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6614 I != E; ++I, ++Idx) { 6615 SmallVector<EVT, 4> ValueVTs; 6616 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6617 bool isArgValueUsed = !I->use_empty(); 6618 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6619 Value != NumValues; ++Value) { 6620 EVT VT = ValueVTs[Value]; 6621 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6622 ISD::ArgFlagsTy Flags; 6623 unsigned OriginalAlignment = 6624 TD->getABITypeAlignment(ArgTy); 6625 6626 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6627 Flags.setZExt(); 6628 if (F.paramHasAttr(Idx, Attribute::SExt)) 6629 Flags.setSExt(); 6630 if (F.paramHasAttr(Idx, Attribute::InReg)) 6631 Flags.setInReg(); 6632 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6633 Flags.setSRet(); 6634 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6635 Flags.setByVal(); 6636 PointerType *Ty = cast<PointerType>(I->getType()); 6637 Type *ElementTy = Ty->getElementType(); 6638 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6639 // For ByVal, alignment should be passed from FE. BE will guess if 6640 // this info is not there but there are cases it cannot get right. 6641 unsigned FrameAlign; 6642 if (F.getParamAlignment(Idx)) 6643 FrameAlign = F.getParamAlignment(Idx); 6644 else 6645 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6646 Flags.setByValAlign(FrameAlign); 6647 } 6648 if (F.paramHasAttr(Idx, Attribute::Nest)) 6649 Flags.setNest(); 6650 Flags.setOrigAlign(OriginalAlignment); 6651 6652 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6653 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6654 for (unsigned i = 0; i != NumRegs; ++i) { 6655 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6656 if (NumRegs > 1 && i == 0) 6657 MyFlags.Flags.setSplit(); 6658 // if it isn't first piece, alignment must be 1 6659 else if (i > 0) 6660 MyFlags.Flags.setOrigAlign(1); 6661 Ins.push_back(MyFlags); 6662 } 6663 } 6664 } 6665 6666 // Call the target to set up the argument values. 6667 SmallVector<SDValue, 8> InVals; 6668 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6669 F.isVarArg(), Ins, 6670 dl, DAG, InVals); 6671 6672 // Verify that the target's LowerFormalArguments behaved as expected. 6673 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6674 "LowerFormalArguments didn't return a valid chain!"); 6675 assert(InVals.size() == Ins.size() && 6676 "LowerFormalArguments didn't emit the correct number of values!"); 6677 DEBUG({ 6678 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6679 assert(InVals[i].getNode() && 6680 "LowerFormalArguments emitted a null value!"); 6681 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6682 "LowerFormalArguments emitted a value with the wrong type!"); 6683 } 6684 }); 6685 6686 // Update the DAG with the new chain value resulting from argument lowering. 6687 DAG.setRoot(NewRoot); 6688 6689 // Set up the argument values. 6690 unsigned i = 0; 6691 Idx = 1; 6692 if (!FuncInfo->CanLowerReturn) { 6693 // Create a virtual register for the sret pointer, and put in a copy 6694 // from the sret argument into it. 6695 SmallVector<EVT, 1> ValueVTs; 6696 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6697 EVT VT = ValueVTs[0]; 6698 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6699 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6700 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6701 RegVT, VT, AssertOp); 6702 6703 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6704 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6705 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6706 FuncInfo->DemoteRegister = SRetReg; 6707 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6708 SRetReg, ArgValue); 6709 DAG.setRoot(NewRoot); 6710 6711 // i indexes lowered arguments. Bump it past the hidden sret argument. 6712 // Idx indexes LLVM arguments. Don't touch it. 6713 ++i; 6714 } 6715 6716 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6717 ++I, ++Idx) { 6718 SmallVector<SDValue, 4> ArgValues; 6719 SmallVector<EVT, 4> ValueVTs; 6720 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6721 unsigned NumValues = ValueVTs.size(); 6722 6723 // If this argument is unused then remember its value. It is used to generate 6724 // debugging information. 6725 if (I->use_empty() && NumValues) 6726 SDB->setUnusedArgValue(I, InVals[i]); 6727 6728 for (unsigned Val = 0; Val != NumValues; ++Val) { 6729 EVT VT = ValueVTs[Val]; 6730 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6731 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6732 6733 if (!I->use_empty()) { 6734 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6735 if (F.paramHasAttr(Idx, Attribute::SExt)) 6736 AssertOp = ISD::AssertSext; 6737 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6738 AssertOp = ISD::AssertZext; 6739 6740 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6741 NumParts, PartVT, VT, 6742 AssertOp)); 6743 } 6744 6745 i += NumParts; 6746 } 6747 6748 // We don't need to do anything else for unused arguments. 6749 if (ArgValues.empty()) 6750 continue; 6751 6752 // Note down frame index. 6753 if (FrameIndexSDNode *FI = 6754 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6755 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6756 6757 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6758 SDB->getCurDebugLoc()); 6759 6760 SDB->setValue(I, Res); 6761 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6762 if (LoadSDNode *LNode = 6763 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6764 if (FrameIndexSDNode *FI = 6765 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6766 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6767 } 6768 6769 // If this argument is live outside of the entry block, insert a copy from 6770 // wherever we got it to the vreg that other BB's will reference it as. 6771 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6772 // If we can, though, try to skip creating an unnecessary vreg. 6773 // FIXME: This isn't very clean... it would be nice to make this more 6774 // general. It's also subtly incompatible with the hacks FastISel 6775 // uses with vregs. 6776 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6777 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6778 FuncInfo->ValueMap[I] = Reg; 6779 continue; 6780 } 6781 } 6782 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 6783 FuncInfo->InitializeRegForValue(I); 6784 SDB->CopyToExportRegsIfNeeded(I); 6785 } 6786 } 6787 6788 assert(i == InVals.size() && "Argument register count mismatch!"); 6789 6790 // Finally, if the target has anything special to do, allow it to do so. 6791 // FIXME: this should insert code into the DAG! 6792 EmitFunctionEntryCode(); 6793} 6794 6795/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6796/// ensure constants are generated when needed. Remember the virtual registers 6797/// that need to be added to the Machine PHI nodes as input. We cannot just 6798/// directly add them, because expansion might result in multiple MBB's for one 6799/// BB. As such, the start of the BB might correspond to a different MBB than 6800/// the end. 6801/// 6802void 6803SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6804 const TerminatorInst *TI = LLVMBB->getTerminator(); 6805 6806 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6807 6808 // Check successor nodes' PHI nodes that expect a constant to be available 6809 // from this block. 6810 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6811 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6812 if (!isa<PHINode>(SuccBB->begin())) continue; 6813 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6814 6815 // If this terminator has multiple identical successors (common for 6816 // switches), only handle each succ once. 6817 if (!SuccsHandled.insert(SuccMBB)) continue; 6818 6819 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6820 6821 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6822 // nodes and Machine PHI nodes, but the incoming operands have not been 6823 // emitted yet. 6824 for (BasicBlock::const_iterator I = SuccBB->begin(); 6825 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6826 // Ignore dead phi's. 6827 if (PN->use_empty()) continue; 6828 6829 // Skip empty types 6830 if (PN->getType()->isEmptyTy()) 6831 continue; 6832 6833 unsigned Reg; 6834 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6835 6836 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6837 unsigned &RegOut = ConstantsOut[C]; 6838 if (RegOut == 0) { 6839 RegOut = FuncInfo.CreateRegs(C->getType()); 6840 CopyValueToVirtualRegister(C, RegOut); 6841 } 6842 Reg = RegOut; 6843 } else { 6844 DenseMap<const Value *, unsigned>::iterator I = 6845 FuncInfo.ValueMap.find(PHIOp); 6846 if (I != FuncInfo.ValueMap.end()) 6847 Reg = I->second; 6848 else { 6849 assert(isa<AllocaInst>(PHIOp) && 6850 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6851 "Didn't codegen value into a register!??"); 6852 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6853 CopyValueToVirtualRegister(PHIOp, Reg); 6854 } 6855 } 6856 6857 // Remember that this register needs to added to the machine PHI node as 6858 // the input for this MBB. 6859 SmallVector<EVT, 4> ValueVTs; 6860 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6861 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6862 EVT VT = ValueVTs[vti]; 6863 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6864 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6865 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6866 Reg += NumRegisters; 6867 } 6868 } 6869 } 6870 ConstantsOut.clear(); 6871} 6872