SelectionDAGBuilder.cpp revision c2a8bdee8fc89aa5ab3166f2346566b8152d63eb
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/PseudoSourceValue.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Analysis/DebugInfo.h" 47#include "llvm/Target/TargetRegisterInfo.h" 48#include "llvm/Target/TargetData.h" 49#include "llvm/Target/TargetFrameInfo.h" 50#include "llvm/Target/TargetInstrInfo.h" 51#include "llvm/Target/TargetIntrinsicInfo.h" 52#include "llvm/Target/TargetLowering.h" 53#include "llvm/Target/TargetOptions.h" 54#include "llvm/Support/Compiler.h" 55#include "llvm/Support/CommandLine.h" 56#include "llvm/Support/Debug.h" 57#include "llvm/Support/ErrorHandling.h" 58#include "llvm/Support/MathExtras.h" 59#include "llvm/Support/raw_ostream.h" 60#include <algorithm> 61using namespace llvm; 62 63/// LimitFloatPrecision - Generate low-precision inline sequences for 64/// some float libcalls (6, 8 or 12 bits). 65static unsigned LimitFloatPrecision; 66 67static cl::opt<unsigned, true> 68LimitFPPrecision("limit-float-precision", 69 cl::desc("Generate low-precision inline sequences " 70 "for some float libcalls"), 71 cl::location(LimitFloatPrecision), 72 cl::init(0)); 73 74static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 75 const SDValue *Parts, unsigned NumParts, 76 EVT PartVT, EVT ValueVT); 77 78/// getCopyFromParts - Create a value that contains the specified legal parts 79/// combined into the value they represent. If the parts combine to a type 80/// larger then ValueVT then AssertOp can be used to specify whether the extra 81/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 82/// (ISD::AssertSext). 83static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 84 const SDValue *Parts, 85 unsigned NumParts, EVT PartVT, EVT ValueVT, 86 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 87 if (ValueVT.isVector()) 88 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 89 90 assert(NumParts > 0 && "No parts to assemble!"); 91 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 92 SDValue Val = Parts[0]; 93 94 if (NumParts > 1) { 95 // Assemble the value from multiple parts. 96 if (ValueVT.isInteger()) { 97 unsigned PartBits = PartVT.getSizeInBits(); 98 unsigned ValueBits = ValueVT.getSizeInBits(); 99 100 // Assemble the power of 2 part. 101 unsigned RoundParts = NumParts & (NumParts - 1) ? 102 1 << Log2_32(NumParts) : NumParts; 103 unsigned RoundBits = PartBits * RoundParts; 104 EVT RoundVT = RoundBits == ValueBits ? 105 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 106 SDValue Lo, Hi; 107 108 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 109 110 if (RoundParts > 2) { 111 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 112 PartVT, HalfVT); 113 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 114 RoundParts / 2, PartVT, HalfVT); 115 } else { 116 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[0]); 117 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[1]); 118 } 119 120 if (TLI.isBigEndian()) 121 std::swap(Lo, Hi); 122 123 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 124 125 if (RoundParts < NumParts) { 126 // Assemble the trailing non-power-of-2 part. 127 unsigned OddParts = NumParts - RoundParts; 128 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 129 Hi = getCopyFromParts(DAG, DL, 130 Parts + RoundParts, OddParts, PartVT, OddVT); 131 132 // Combine the round and odd parts. 133 Lo = Val; 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 137 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 138 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 139 DAG.getConstant(Lo.getValueType().getSizeInBits(), 140 TLI.getPointerTy())); 141 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 142 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 143 } 144 } else if (PartVT.isFloatingPoint()) { 145 // FP split into multiple FP parts (for ppcf128) 146 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 147 "Unexpected split"); 148 SDValue Lo, Hi; 149 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[0]); 150 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[1]); 151 if (TLI.isBigEndian()) 152 std::swap(Lo, Hi); 153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 154 } else { 155 // FP split into integer parts (soft fp) 156 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 157 !PartVT.isVector() && "Unexpected split"); 158 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 159 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 160 } 161 } 162 163 // There is now one part, held in Val. Correct it to match ValueVT. 164 PartVT = Val.getValueType(); 165 166 if (PartVT == ValueVT) 167 return Val; 168 169 if (PartVT.isInteger() && ValueVT.isInteger()) { 170 if (ValueVT.bitsLT(PartVT)) { 171 // For a truncate, see if we have any information to 172 // indicate whether the truncated bits will always be 173 // zero or sign-extension. 174 if (AssertOp != ISD::DELETED_NODE) 175 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 176 DAG.getValueType(ValueVT)); 177 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 178 } 179 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 180 } 181 182 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 183 // FP_ROUND's are always exact here. 184 if (ValueVT.bitsLT(Val.getValueType())) 185 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 186 DAG.getIntPtrConstant(1)); 187 188 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 189 } 190 191 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 192 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val); 193 194 llvm_unreachable("Unknown mismatch!"); 195 return SDValue(); 196} 197 198/// getCopyFromParts - Create a value that contains the specified legal parts 199/// combined into the value they represent. If the parts combine to a type 200/// larger then ValueVT then AssertOp can be used to specify whether the extra 201/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 202/// (ISD::AssertSext). 203static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 204 const SDValue *Parts, unsigned NumParts, 205 EVT PartVT, EVT ValueVT) { 206 assert(ValueVT.isVector() && "Not a vector value"); 207 assert(NumParts > 0 && "No parts to assemble!"); 208 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 209 SDValue Val = Parts[0]; 210 211 // Handle a multi-element vector. 212 if (NumParts > 1) { 213 EVT IntermediateVT, RegisterVT; 214 unsigned NumIntermediates; 215 unsigned NumRegs = 216 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 217 NumIntermediates, RegisterVT); 218 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 219 NumParts = NumRegs; // Silence a compiler warning. 220 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 221 assert(RegisterVT == Parts[0].getValueType() && 222 "Part type doesn't match part!"); 223 224 // Assemble the parts into intermediate operands. 225 SmallVector<SDValue, 8> Ops(NumIntermediates); 226 if (NumIntermediates == NumParts) { 227 // If the register was not expanded, truncate or copy the value, 228 // as appropriate. 229 for (unsigned i = 0; i != NumParts; ++i) 230 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 231 PartVT, IntermediateVT); 232 } else if (NumParts > 0) { 233 // If the intermediate type was expanded, build the intermediate 234 // operands from the parts. 235 assert(NumParts % NumIntermediates == 0 && 236 "Must expand into a divisible number of parts!"); 237 unsigned Factor = NumParts / NumIntermediates; 238 for (unsigned i = 0; i != NumIntermediates; ++i) 239 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 240 PartVT, IntermediateVT); 241 } 242 243 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 244 // intermediate operands. 245 Val = DAG.getNode(IntermediateVT.isVector() ? 246 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 247 ValueVT, &Ops[0], NumIntermediates); 248 } 249 250 // There is now one part, held in Val. Correct it to match ValueVT. 251 PartVT = Val.getValueType(); 252 253 if (PartVT == ValueVT) 254 return Val; 255 256 if (PartVT.isVector()) { 257 // If the element type of the source/dest vectors are the same, but the 258 // parts vector has more elements than the value vector, then we have a 259 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 260 // elements we want. 261 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 262 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 263 "Cannot narrow, it would be a lossy transformation"); 264 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 265 DAG.getIntPtrConstant(0)); 266 } 267 268 // Vector/Vector bitcast. 269 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val); 270 } 271 272 assert(ValueVT.getVectorElementType() == PartVT && 273 ValueVT.getVectorNumElements() == 1 && 274 "Only trivial scalar-to-vector conversions should get here!"); 275 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 276} 277 278 279 280 281static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 282 SDValue Val, SDValue *Parts, unsigned NumParts, 283 EVT PartVT); 284 285/// getCopyToParts - Create a series of nodes that contain the specified value 286/// split into legal parts. If the parts contain more bits than Val, then, for 287/// integers, ExtendKind can be used to specify how to generate the extra bits. 288static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 289 SDValue Val, SDValue *Parts, unsigned NumParts, 290 EVT PartVT, 291 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 292 EVT ValueVT = Val.getValueType(); 293 294 // Handle the vector case separately. 295 if (ValueVT.isVector()) 296 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 297 298 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 299 unsigned PartBits = PartVT.getSizeInBits(); 300 unsigned OrigNumParts = NumParts; 301 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 302 303 if (NumParts == 0) 304 return; 305 306 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 307 if (PartVT == ValueVT) { 308 assert(NumParts == 1 && "No-op copy with multiple parts!"); 309 Parts[0] = Val; 310 return; 311 } 312 313 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 314 // If the parts cover more bits than the value has, promote the value. 315 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 316 assert(NumParts == 1 && "Do not know what to promote to!"); 317 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 318 } else { 319 assert(PartVT.isInteger() && ValueVT.isInteger() && 320 "Unknown mismatch!"); 321 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 322 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 323 } 324 } else if (PartBits == ValueVT.getSizeInBits()) { 325 // Different types of the same size. 326 assert(NumParts == 1 && PartVT != ValueVT); 327 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val); 328 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 329 // If the parts cover less bits than value has, truncate the value. 330 assert(PartVT.isInteger() && ValueVT.isInteger() && 331 "Unknown mismatch!"); 332 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 333 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 334 } 335 336 // The value may have changed - recompute ValueVT. 337 ValueVT = Val.getValueType(); 338 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 339 "Failed to tile the value with PartVT!"); 340 341 if (NumParts == 1) { 342 assert(PartVT == ValueVT && "Type conversion failed!"); 343 Parts[0] = Val; 344 return; 345 } 346 347 // Expand the value into multiple parts. 348 if (NumParts & (NumParts - 1)) { 349 // The number of parts is not a power of 2. Split off and copy the tail. 350 assert(PartVT.isInteger() && ValueVT.isInteger() && 351 "Do not know what to expand to!"); 352 unsigned RoundParts = 1 << Log2_32(NumParts); 353 unsigned RoundBits = RoundParts * PartBits; 354 unsigned OddParts = NumParts - RoundParts; 355 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 356 DAG.getIntPtrConstant(RoundBits)); 357 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 358 359 if (TLI.isBigEndian()) 360 // The odd parts were reversed by getCopyToParts - unreverse them. 361 std::reverse(Parts + RoundParts, Parts + NumParts); 362 363 NumParts = RoundParts; 364 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 365 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 366 } 367 368 // The number of parts is a power of 2. Repeatedly bisect the value using 369 // EXTRACT_ELEMENT. 370 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, DL, 371 EVT::getIntegerVT(*DAG.getContext(), 372 ValueVT.getSizeInBits()), 373 Val); 374 375 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 376 for (unsigned i = 0; i < NumParts; i += StepSize) { 377 unsigned ThisBits = StepSize * PartBits / 2; 378 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 379 SDValue &Part0 = Parts[i]; 380 SDValue &Part1 = Parts[i+StepSize/2]; 381 382 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 383 ThisVT, Part0, DAG.getIntPtrConstant(1)); 384 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 385 ThisVT, Part0, DAG.getIntPtrConstant(0)); 386 387 if (ThisBits == PartBits && ThisVT != PartVT) { 388 Part0 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part0); 389 Part1 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part1); 390 } 391 } 392 } 393 394 if (TLI.isBigEndian()) 395 std::reverse(Parts, Parts + OrigNumParts); 396} 397 398 399/// getCopyToPartsVector - Create a series of nodes that contain the specified 400/// value split into legal parts. 401static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 402 SDValue Val, SDValue *Parts, unsigned NumParts, 403 EVT PartVT) { 404 EVT ValueVT = Val.getValueType(); 405 assert(ValueVT.isVector() && "Not a vector"); 406 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 407 408 if (NumParts == 1) { 409 if (PartVT == ValueVT) { 410 // Nothing to do. 411 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 412 // Bitconvert vector->vector case. 413 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val); 414 } else if (PartVT.isVector() && 415 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&& 416 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 417 EVT ElementVT = PartVT.getVectorElementType(); 418 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 419 // undef elements. 420 SmallVector<SDValue, 16> Ops; 421 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 422 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 423 ElementVT, Val, DAG.getIntPtrConstant(i))); 424 425 for (unsigned i = ValueVT.getVectorNumElements(), 426 e = PartVT.getVectorNumElements(); i != e; ++i) 427 Ops.push_back(DAG.getUNDEF(ElementVT)); 428 429 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 430 431 // FIXME: Use CONCAT for 2x -> 4x. 432 433 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 434 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 435 } else { 436 // Vector -> scalar conversion. 437 assert(ValueVT.getVectorElementType() == PartVT && 438 ValueVT.getVectorNumElements() == 1 && 439 "Only trivial vector-to-scalar conversions should get here!"); 440 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 441 PartVT, Val, DAG.getIntPtrConstant(0)); 442 } 443 444 Parts[0] = Val; 445 return; 446 } 447 448 // Handle a multi-element vector. 449 EVT IntermediateVT, RegisterVT; 450 unsigned NumIntermediates; 451 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 452 IntermediateVT, 453 NumIntermediates, RegisterVT); 454 unsigned NumElements = ValueVT.getVectorNumElements(); 455 456 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 457 NumParts = NumRegs; // Silence a compiler warning. 458 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 459 460 // Split the vector into intermediate operands. 461 SmallVector<SDValue, 8> Ops(NumIntermediates); 462 for (unsigned i = 0; i != NumIntermediates; ++i) { 463 if (IntermediateVT.isVector()) 464 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 465 IntermediateVT, Val, 466 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 467 else 468 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 469 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 470 } 471 472 // Split the intermediate operands into legal parts. 473 if (NumParts == NumIntermediates) { 474 // If the register was not expanded, promote or copy the value, 475 // as appropriate. 476 for (unsigned i = 0; i != NumParts; ++i) 477 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 478 } else if (NumParts > 0) { 479 // If the intermediate type was expanded, split each the value into 480 // legal parts. 481 assert(NumParts % NumIntermediates == 0 && 482 "Must expand into a divisible number of parts!"); 483 unsigned Factor = NumParts / NumIntermediates; 484 for (unsigned i = 0; i != NumIntermediates; ++i) 485 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 486 } 487} 488 489 490 491 492namespace { 493 /// RegsForValue - This struct represents the registers (physical or virtual) 494 /// that a particular set of values is assigned, and the type information 495 /// about the value. The most common situation is to represent one value at a 496 /// time, but struct or array values are handled element-wise as multiple 497 /// values. The splitting of aggregates is performed recursively, so that we 498 /// never have aggregate-typed registers. The values at this point do not 499 /// necessarily have legal types, so each value may require one or more 500 /// registers of some legal type. 501 /// 502 struct RegsForValue { 503 /// ValueVTs - The value types of the values, which may not be legal, and 504 /// may need be promoted or synthesized from one or more registers. 505 /// 506 SmallVector<EVT, 4> ValueVTs; 507 508 /// RegVTs - The value types of the registers. This is the same size as 509 /// ValueVTs and it records, for each value, what the type of the assigned 510 /// register or registers are. (Individual values are never synthesized 511 /// from more than one type of register.) 512 /// 513 /// With virtual registers, the contents of RegVTs is redundant with TLI's 514 /// getRegisterType member function, however when with physical registers 515 /// it is necessary to have a separate record of the types. 516 /// 517 SmallVector<EVT, 4> RegVTs; 518 519 /// Regs - This list holds the registers assigned to the values. 520 /// Each legal or promoted value requires one register, and each 521 /// expanded value requires multiple registers. 522 /// 523 SmallVector<unsigned, 4> Regs; 524 525 RegsForValue() {} 526 527 RegsForValue(const SmallVector<unsigned, 4> ®s, 528 EVT regvt, EVT valuevt) 529 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 530 531 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 532 unsigned Reg, const Type *Ty) { 533 ComputeValueVTs(tli, Ty, ValueVTs); 534 535 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 536 EVT ValueVT = ValueVTs[Value]; 537 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 538 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 539 for (unsigned i = 0; i != NumRegs; ++i) 540 Regs.push_back(Reg + i); 541 RegVTs.push_back(RegisterVT); 542 Reg += NumRegs; 543 } 544 } 545 546 /// areValueTypesLegal - Return true if types of all the values are legal. 547 bool areValueTypesLegal(const TargetLowering &TLI) { 548 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 549 EVT RegisterVT = RegVTs[Value]; 550 if (!TLI.isTypeLegal(RegisterVT)) 551 return false; 552 } 553 return true; 554 } 555 556 /// append - Add the specified values to this one. 557 void append(const RegsForValue &RHS) { 558 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 559 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 560 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 561 } 562 563 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 564 /// this value and returns the result as a ValueVTs value. This uses 565 /// Chain/Flag as the input and updates them for the output Chain/Flag. 566 /// If the Flag pointer is NULL, no flag is used. 567 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 568 DebugLoc dl, 569 SDValue &Chain, SDValue *Flag) const; 570 571 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 572 /// specified value into the registers specified by this object. This uses 573 /// Chain/Flag as the input and updates them for the output Chain/Flag. 574 /// If the Flag pointer is NULL, no flag is used. 575 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 576 SDValue &Chain, SDValue *Flag) const; 577 578 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 579 /// operand list. This adds the code marker, matching input operand index 580 /// (if applicable), and includes the number of values added into it. 581 void AddInlineAsmOperands(unsigned Kind, 582 bool HasMatching, unsigned MatchingIdx, 583 SelectionDAG &DAG, 584 std::vector<SDValue> &Ops) const; 585 }; 586} 587 588/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 589/// this value and returns the result as a ValueVT value. This uses 590/// Chain/Flag as the input and updates them for the output Chain/Flag. 591/// If the Flag pointer is NULL, no flag is used. 592SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 593 FunctionLoweringInfo &FuncInfo, 594 DebugLoc dl, 595 SDValue &Chain, SDValue *Flag) const { 596 // A Value with type {} or [0 x %t] needs no registers. 597 if (ValueVTs.empty()) 598 return SDValue(); 599 600 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 601 602 // Assemble the legal parts into the final values. 603 SmallVector<SDValue, 4> Values(ValueVTs.size()); 604 SmallVector<SDValue, 8> Parts; 605 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 606 // Copy the legal parts from the registers. 607 EVT ValueVT = ValueVTs[Value]; 608 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 609 EVT RegisterVT = RegVTs[Value]; 610 611 Parts.resize(NumRegs); 612 for (unsigned i = 0; i != NumRegs; ++i) { 613 SDValue P; 614 if (Flag == 0) { 615 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 616 } else { 617 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 618 *Flag = P.getValue(2); 619 } 620 621 Chain = P.getValue(1); 622 623 // If the source register was virtual and if we know something about it, 624 // add an assert node. 625 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && 626 RegisterVT.isInteger() && !RegisterVT.isVector()) { 627 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; 628 if (FuncInfo.LiveOutRegInfo.size() > SlotNo) { 629 const FunctionLoweringInfo::LiveOutInfo &LOI = 630 FuncInfo.LiveOutRegInfo[SlotNo]; 631 632 unsigned RegSize = RegisterVT.getSizeInBits(); 633 unsigned NumSignBits = LOI.NumSignBits; 634 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 635 636 // FIXME: We capture more information than the dag can represent. For 637 // now, just use the tightest assertzext/assertsext possible. 638 bool isSExt = true; 639 EVT FromVT(MVT::Other); 640 if (NumSignBits == RegSize) 641 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 642 else if (NumZeroBits >= RegSize-1) 643 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 644 else if (NumSignBits > RegSize-8) 645 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 646 else if (NumZeroBits >= RegSize-8) 647 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 648 else if (NumSignBits > RegSize-16) 649 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 650 else if (NumZeroBits >= RegSize-16) 651 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 652 else if (NumSignBits > RegSize-32) 653 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 654 else if (NumZeroBits >= RegSize-32) 655 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 656 657 if (FromVT != MVT::Other) 658 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 659 RegisterVT, P, DAG.getValueType(FromVT)); 660 } 661 } 662 663 Parts[i] = P; 664 } 665 666 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 667 NumRegs, RegisterVT, ValueVT); 668 Part += NumRegs; 669 Parts.clear(); 670 } 671 672 return DAG.getNode(ISD::MERGE_VALUES, dl, 673 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 674 &Values[0], ValueVTs.size()); 675} 676 677/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 678/// specified value into the registers specified by this object. This uses 679/// Chain/Flag as the input and updates them for the output Chain/Flag. 680/// If the Flag pointer is NULL, no flag is used. 681void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 682 SDValue &Chain, SDValue *Flag) const { 683 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 684 685 // Get the list of the values's legal parts. 686 unsigned NumRegs = Regs.size(); 687 SmallVector<SDValue, 8> Parts(NumRegs); 688 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 689 EVT ValueVT = ValueVTs[Value]; 690 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 691 EVT RegisterVT = RegVTs[Value]; 692 693 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 694 &Parts[Part], NumParts, RegisterVT); 695 Part += NumParts; 696 } 697 698 // Copy the parts into the registers. 699 SmallVector<SDValue, 8> Chains(NumRegs); 700 for (unsigned i = 0; i != NumRegs; ++i) { 701 SDValue Part; 702 if (Flag == 0) { 703 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 704 } else { 705 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 706 *Flag = Part.getValue(1); 707 } 708 709 Chains[i] = Part.getValue(0); 710 } 711 712 if (NumRegs == 1 || Flag) 713 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 714 // flagged to it. That is the CopyToReg nodes and the user are considered 715 // a single scheduling unit. If we create a TokenFactor and return it as 716 // chain, then the TokenFactor is both a predecessor (operand) of the 717 // user as well as a successor (the TF operands are flagged to the user). 718 // c1, f1 = CopyToReg 719 // c2, f2 = CopyToReg 720 // c3 = TokenFactor c1, c2 721 // ... 722 // = op c3, ..., f2 723 Chain = Chains[NumRegs-1]; 724 else 725 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 726} 727 728/// AddInlineAsmOperands - Add this value to the specified inlineasm node 729/// operand list. This adds the code marker and includes the number of 730/// values added into it. 731void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 732 unsigned MatchingIdx, 733 SelectionDAG &DAG, 734 std::vector<SDValue> &Ops) const { 735 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 736 737 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 738 if (HasMatching) 739 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 740 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 741 Ops.push_back(Res); 742 743 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 744 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 745 EVT RegisterVT = RegVTs[Value]; 746 for (unsigned i = 0; i != NumRegs; ++i) { 747 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 748 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 749 } 750 } 751} 752 753void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 754 AA = &aa; 755 GFI = gfi; 756 TD = DAG.getTarget().getTargetData(); 757} 758 759/// clear - Clear out the current SelectionDAG and the associated 760/// state and prepare this SelectionDAGBuilder object to be used 761/// for a new block. This doesn't clear out information about 762/// additional blocks that are needed to complete switch lowering 763/// or PHI node updating; that information is cleared out as it is 764/// consumed. 765void SelectionDAGBuilder::clear() { 766 NodeMap.clear(); 767 UnusedArgNodeMap.clear(); 768 PendingLoads.clear(); 769 PendingExports.clear(); 770 DanglingDebugInfoMap.clear(); 771 CurDebugLoc = DebugLoc(); 772 HasTailCall = false; 773} 774 775/// getRoot - Return the current virtual root of the Selection DAG, 776/// flushing any PendingLoad items. This must be done before emitting 777/// a store or any other node that may need to be ordered after any 778/// prior load instructions. 779/// 780SDValue SelectionDAGBuilder::getRoot() { 781 if (PendingLoads.empty()) 782 return DAG.getRoot(); 783 784 if (PendingLoads.size() == 1) { 785 SDValue Root = PendingLoads[0]; 786 DAG.setRoot(Root); 787 PendingLoads.clear(); 788 return Root; 789 } 790 791 // Otherwise, we have to make a token factor node. 792 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 793 &PendingLoads[0], PendingLoads.size()); 794 PendingLoads.clear(); 795 DAG.setRoot(Root); 796 return Root; 797} 798 799/// getControlRoot - Similar to getRoot, but instead of flushing all the 800/// PendingLoad items, flush all the PendingExports items. It is necessary 801/// to do this before emitting a terminator instruction. 802/// 803SDValue SelectionDAGBuilder::getControlRoot() { 804 SDValue Root = DAG.getRoot(); 805 806 if (PendingExports.empty()) 807 return Root; 808 809 // Turn all of the CopyToReg chains into one factored node. 810 if (Root.getOpcode() != ISD::EntryToken) { 811 unsigned i = 0, e = PendingExports.size(); 812 for (; i != e; ++i) { 813 assert(PendingExports[i].getNode()->getNumOperands() > 1); 814 if (PendingExports[i].getNode()->getOperand(0) == Root) 815 break; // Don't add the root if we already indirectly depend on it. 816 } 817 818 if (i == e) 819 PendingExports.push_back(Root); 820 } 821 822 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 823 &PendingExports[0], 824 PendingExports.size()); 825 PendingExports.clear(); 826 DAG.setRoot(Root); 827 return Root; 828} 829 830void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 831 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 832 DAG.AssignOrdering(Node, SDNodeOrder); 833 834 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 835 AssignOrderingToNode(Node->getOperand(I).getNode()); 836} 837 838void SelectionDAGBuilder::visit(const Instruction &I) { 839 // Set up outgoing PHI node register values before emitting the terminator. 840 if (isa<TerminatorInst>(&I)) 841 HandlePHINodesInSuccessorBlocks(I.getParent()); 842 843 CurDebugLoc = I.getDebugLoc(); 844 845 visit(I.getOpcode(), I); 846 847 if (!isa<TerminatorInst>(&I) && !HasTailCall) 848 CopyToExportRegsIfNeeded(&I); 849 850 CurDebugLoc = DebugLoc(); 851} 852 853void SelectionDAGBuilder::visitPHI(const PHINode &) { 854 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 855} 856 857void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 858 // Note: this doesn't use InstVisitor, because it has to work with 859 // ConstantExpr's in addition to instructions. 860 switch (Opcode) { 861 default: llvm_unreachable("Unknown instruction type encountered!"); 862 // Build the switch statement using the Instruction.def file. 863#define HANDLE_INST(NUM, OPCODE, CLASS) \ 864 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 865#include "llvm/Instruction.def" 866 } 867 868 // Assign the ordering to the freshly created DAG nodes. 869 if (NodeMap.count(&I)) { 870 ++SDNodeOrder; 871 AssignOrderingToNode(getValue(&I).getNode()); 872 } 873} 874 875// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 876// generate the debug data structures now that we've seen its definition. 877void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 878 SDValue Val) { 879 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 880 if (DDI.getDI()) { 881 const DbgValueInst *DI = DDI.getDI(); 882 DebugLoc dl = DDI.getdl(); 883 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 884 MDNode *Variable = DI->getVariable(); 885 uint64_t Offset = DI->getOffset(); 886 SDDbgValue *SDV; 887 if (Val.getNode()) { 888 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 889 SDV = DAG.getDbgValue(Variable, Val.getNode(), 890 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 891 DAG.AddDbgValue(SDV, Val.getNode(), false); 892 } 893 } else { 894 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()), 895 Offset, dl, SDNodeOrder); 896 DAG.AddDbgValue(SDV, 0, false); 897 } 898 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 899 } 900} 901 902// getValue - Return an SDValue for the given Value. 903SDValue SelectionDAGBuilder::getValue(const Value *V) { 904 // If we already have an SDValue for this value, use it. It's important 905 // to do this first, so that we don't create a CopyFromReg if we already 906 // have a regular SDValue. 907 SDValue &N = NodeMap[V]; 908 if (N.getNode()) return N; 909 910 // If there's a virtual register allocated and initialized for this 911 // value, use it. 912 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 913 if (It != FuncInfo.ValueMap.end()) { 914 unsigned InReg = It->second; 915 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 916 SDValue Chain = DAG.getEntryNode(); 917 return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 918 } 919 920 // Otherwise create a new SDValue and remember it. 921 SDValue Val = getValueImpl(V); 922 NodeMap[V] = Val; 923 resolveDanglingDebugInfo(V, Val); 924 return Val; 925} 926 927/// getNonRegisterValue - Return an SDValue for the given Value, but 928/// don't look in FuncInfo.ValueMap for a virtual register. 929SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 930 // If we already have an SDValue for this value, use it. 931 SDValue &N = NodeMap[V]; 932 if (N.getNode()) return N; 933 934 // Otherwise create a new SDValue and remember it. 935 SDValue Val = getValueImpl(V); 936 NodeMap[V] = Val; 937 resolveDanglingDebugInfo(V, Val); 938 return Val; 939} 940 941/// getValueImpl - Helper function for getValue and getNonRegisterValue. 942/// Create an SDValue for the given value. 943SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 944 if (const Constant *C = dyn_cast<Constant>(V)) { 945 EVT VT = TLI.getValueType(V->getType(), true); 946 947 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 948 return DAG.getConstant(*CI, VT); 949 950 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 951 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 952 953 if (isa<ConstantPointerNull>(C)) 954 return DAG.getConstant(0, TLI.getPointerTy()); 955 956 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 957 return DAG.getConstantFP(*CFP, VT); 958 959 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 960 return DAG.getUNDEF(VT); 961 962 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 963 visit(CE->getOpcode(), *CE); 964 SDValue N1 = NodeMap[V]; 965 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 966 return N1; 967 } 968 969 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 970 SmallVector<SDValue, 4> Constants; 971 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 972 OI != OE; ++OI) { 973 SDNode *Val = getValue(*OI).getNode(); 974 // If the operand is an empty aggregate, there are no values. 975 if (!Val) continue; 976 // Add each leaf value from the operand to the Constants list 977 // to form a flattened list of all the values. 978 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 979 Constants.push_back(SDValue(Val, i)); 980 } 981 982 return DAG.getMergeValues(&Constants[0], Constants.size(), 983 getCurDebugLoc()); 984 } 985 986 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 987 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 988 "Unknown struct or array constant!"); 989 990 SmallVector<EVT, 4> ValueVTs; 991 ComputeValueVTs(TLI, C->getType(), ValueVTs); 992 unsigned NumElts = ValueVTs.size(); 993 if (NumElts == 0) 994 return SDValue(); // empty struct 995 SmallVector<SDValue, 4> Constants(NumElts); 996 for (unsigned i = 0; i != NumElts; ++i) { 997 EVT EltVT = ValueVTs[i]; 998 if (isa<UndefValue>(C)) 999 Constants[i] = DAG.getUNDEF(EltVT); 1000 else if (EltVT.isFloatingPoint()) 1001 Constants[i] = DAG.getConstantFP(0, EltVT); 1002 else 1003 Constants[i] = DAG.getConstant(0, EltVT); 1004 } 1005 1006 return DAG.getMergeValues(&Constants[0], NumElts, 1007 getCurDebugLoc()); 1008 } 1009 1010 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1011 return DAG.getBlockAddress(BA, VT); 1012 1013 const VectorType *VecTy = cast<VectorType>(V->getType()); 1014 unsigned NumElements = VecTy->getNumElements(); 1015 1016 // Now that we know the number and type of the elements, get that number of 1017 // elements into the Ops array based on what kind of constant it is. 1018 SmallVector<SDValue, 16> Ops; 1019 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1020 for (unsigned i = 0; i != NumElements; ++i) 1021 Ops.push_back(getValue(CP->getOperand(i))); 1022 } else { 1023 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1024 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1025 1026 SDValue Op; 1027 if (EltVT.isFloatingPoint()) 1028 Op = DAG.getConstantFP(0, EltVT); 1029 else 1030 Op = DAG.getConstant(0, EltVT); 1031 Ops.assign(NumElements, Op); 1032 } 1033 1034 // Create a BUILD_VECTOR node. 1035 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1036 VT, &Ops[0], Ops.size()); 1037 } 1038 1039 // If this is a static alloca, generate it as the frameindex instead of 1040 // computation. 1041 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1042 DenseMap<const AllocaInst*, int>::iterator SI = 1043 FuncInfo.StaticAllocaMap.find(AI); 1044 if (SI != FuncInfo.StaticAllocaMap.end()) 1045 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1046 } 1047 1048 // If this is an instruction which fast-isel has deferred, select it now. 1049 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1050 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1051 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1052 SDValue Chain = DAG.getEntryNode(); 1053 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1054 } 1055 1056 llvm_unreachable("Can't get register for value!"); 1057 return SDValue(); 1058} 1059 1060void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1061 SDValue Chain = getControlRoot(); 1062 SmallVector<ISD::OutputArg, 8> Outs; 1063 SmallVector<SDValue, 8> OutVals; 1064 1065 if (!FuncInfo.CanLowerReturn) { 1066 unsigned DemoteReg = FuncInfo.DemoteRegister; 1067 const Function *F = I.getParent()->getParent(); 1068 1069 // Emit a store of the return value through the virtual register. 1070 // Leave Outs empty so that LowerReturn won't try to load return 1071 // registers the usual way. 1072 SmallVector<EVT, 1> PtrValueVTs; 1073 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1074 PtrValueVTs); 1075 1076 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1077 SDValue RetOp = getValue(I.getOperand(0)); 1078 1079 SmallVector<EVT, 4> ValueVTs; 1080 SmallVector<uint64_t, 4> Offsets; 1081 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1082 unsigned NumValues = ValueVTs.size(); 1083 1084 SmallVector<SDValue, 4> Chains(NumValues); 1085 for (unsigned i = 0; i != NumValues; ++i) { 1086 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1087 RetPtr.getValueType(), RetPtr, 1088 DAG.getIntPtrConstant(Offsets[i])); 1089 Chains[i] = 1090 DAG.getStore(Chain, getCurDebugLoc(), 1091 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1092 // FIXME: better loc info would be nice. 1093 Add, MachinePointerInfo(), false, false, 0); 1094 } 1095 1096 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1097 MVT::Other, &Chains[0], NumValues); 1098 } else if (I.getNumOperands() != 0) { 1099 SmallVector<EVT, 4> ValueVTs; 1100 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1101 unsigned NumValues = ValueVTs.size(); 1102 if (NumValues) { 1103 SDValue RetOp = getValue(I.getOperand(0)); 1104 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1105 EVT VT = ValueVTs[j]; 1106 1107 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1108 1109 const Function *F = I.getParent()->getParent(); 1110 if (F->paramHasAttr(0, Attribute::SExt)) 1111 ExtendKind = ISD::SIGN_EXTEND; 1112 else if (F->paramHasAttr(0, Attribute::ZExt)) 1113 ExtendKind = ISD::ZERO_EXTEND; 1114 1115 // FIXME: C calling convention requires the return type to be promoted 1116 // to at least 32-bit. But this is not necessary for non-C calling 1117 // conventions. The frontend should mark functions whose return values 1118 // require promoting with signext or zeroext attributes. 1119 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1120 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32); 1121 if (VT.bitsLT(MinVT)) 1122 VT = MinVT; 1123 } 1124 1125 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1126 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1127 SmallVector<SDValue, 4> Parts(NumParts); 1128 getCopyToParts(DAG, getCurDebugLoc(), 1129 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1130 &Parts[0], NumParts, PartVT, ExtendKind); 1131 1132 // 'inreg' on function refers to return value 1133 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1134 if (F->paramHasAttr(0, Attribute::InReg)) 1135 Flags.setInReg(); 1136 1137 // Propagate extension type if any 1138 if (F->paramHasAttr(0, Attribute::SExt)) 1139 Flags.setSExt(); 1140 else if (F->paramHasAttr(0, Attribute::ZExt)) 1141 Flags.setZExt(); 1142 1143 for (unsigned i = 0; i < NumParts; ++i) { 1144 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1145 /*isfixed=*/true)); 1146 OutVals.push_back(Parts[i]); 1147 } 1148 } 1149 } 1150 } 1151 1152 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1153 CallingConv::ID CallConv = 1154 DAG.getMachineFunction().getFunction()->getCallingConv(); 1155 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1156 Outs, OutVals, getCurDebugLoc(), DAG); 1157 1158 // Verify that the target's LowerReturn behaved as expected. 1159 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1160 "LowerReturn didn't return a valid chain!"); 1161 1162 // Update the DAG with the new chain value resulting from return lowering. 1163 DAG.setRoot(Chain); 1164} 1165 1166/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1167/// created for it, emit nodes to copy the value into the virtual 1168/// registers. 1169void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1170 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1171 if (VMI != FuncInfo.ValueMap.end()) { 1172 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1173 CopyValueToVirtualRegister(V, VMI->second); 1174 } 1175} 1176 1177/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1178/// the current basic block, add it to ValueMap now so that we'll get a 1179/// CopyTo/FromReg. 1180void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1181 // No need to export constants. 1182 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1183 1184 // Already exported? 1185 if (FuncInfo.isExportedInst(V)) return; 1186 1187 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1188 CopyValueToVirtualRegister(V, Reg); 1189} 1190 1191bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1192 const BasicBlock *FromBB) { 1193 // The operands of the setcc have to be in this block. We don't know 1194 // how to export them from some other block. 1195 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1196 // Can export from current BB. 1197 if (VI->getParent() == FromBB) 1198 return true; 1199 1200 // Is already exported, noop. 1201 return FuncInfo.isExportedInst(V); 1202 } 1203 1204 // If this is an argument, we can export it if the BB is the entry block or 1205 // if it is already exported. 1206 if (isa<Argument>(V)) { 1207 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1208 return true; 1209 1210 // Otherwise, can only export this if it is already exported. 1211 return FuncInfo.isExportedInst(V); 1212 } 1213 1214 // Otherwise, constants can always be exported. 1215 return true; 1216} 1217 1218static bool InBlock(const Value *V, const BasicBlock *BB) { 1219 if (const Instruction *I = dyn_cast<Instruction>(V)) 1220 return I->getParent() == BB; 1221 return true; 1222} 1223 1224/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1225/// This function emits a branch and is used at the leaves of an OR or an 1226/// AND operator tree. 1227/// 1228void 1229SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1230 MachineBasicBlock *TBB, 1231 MachineBasicBlock *FBB, 1232 MachineBasicBlock *CurBB, 1233 MachineBasicBlock *SwitchBB) { 1234 const BasicBlock *BB = CurBB->getBasicBlock(); 1235 1236 // If the leaf of the tree is a comparison, merge the condition into 1237 // the caseblock. 1238 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1239 // The operands of the cmp have to be in this block. We don't know 1240 // how to export them from some other block. If this is the first block 1241 // of the sequence, no exporting is needed. 1242 if (CurBB == SwitchBB || 1243 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1244 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1245 ISD::CondCode Condition; 1246 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1247 Condition = getICmpCondCode(IC->getPredicate()); 1248 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1249 Condition = getFCmpCondCode(FC->getPredicate()); 1250 } else { 1251 Condition = ISD::SETEQ; // silence warning. 1252 llvm_unreachable("Unknown compare instruction"); 1253 } 1254 1255 CaseBlock CB(Condition, BOp->getOperand(0), 1256 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1257 SwitchCases.push_back(CB); 1258 return; 1259 } 1260 } 1261 1262 // Create a CaseBlock record representing this branch. 1263 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1264 NULL, TBB, FBB, CurBB); 1265 SwitchCases.push_back(CB); 1266} 1267 1268/// FindMergedConditions - If Cond is an expression like 1269void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1270 MachineBasicBlock *TBB, 1271 MachineBasicBlock *FBB, 1272 MachineBasicBlock *CurBB, 1273 MachineBasicBlock *SwitchBB, 1274 unsigned Opc) { 1275 // If this node is not part of the or/and tree, emit it as a branch. 1276 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1277 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1278 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1279 BOp->getParent() != CurBB->getBasicBlock() || 1280 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1281 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1282 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1283 return; 1284 } 1285 1286 // Create TmpBB after CurBB. 1287 MachineFunction::iterator BBI = CurBB; 1288 MachineFunction &MF = DAG.getMachineFunction(); 1289 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1290 CurBB->getParent()->insert(++BBI, TmpBB); 1291 1292 if (Opc == Instruction::Or) { 1293 // Codegen X | Y as: 1294 // jmp_if_X TBB 1295 // jmp TmpBB 1296 // TmpBB: 1297 // jmp_if_Y TBB 1298 // jmp FBB 1299 // 1300 1301 // Emit the LHS condition. 1302 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1303 1304 // Emit the RHS condition into TmpBB. 1305 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1306 } else { 1307 assert(Opc == Instruction::And && "Unknown merge op!"); 1308 // Codegen X & Y as: 1309 // jmp_if_X TmpBB 1310 // jmp FBB 1311 // TmpBB: 1312 // jmp_if_Y TBB 1313 // jmp FBB 1314 // 1315 // This requires creation of TmpBB after CurBB. 1316 1317 // Emit the LHS condition. 1318 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1319 1320 // Emit the RHS condition into TmpBB. 1321 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1322 } 1323} 1324 1325/// If the set of cases should be emitted as a series of branches, return true. 1326/// If we should emit this as a bunch of and/or'd together conditions, return 1327/// false. 1328bool 1329SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1330 if (Cases.size() != 2) return true; 1331 1332 // If this is two comparisons of the same values or'd or and'd together, they 1333 // will get folded into a single comparison, so don't emit two blocks. 1334 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1335 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1336 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1337 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1338 return false; 1339 } 1340 1341 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1342 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1343 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1344 Cases[0].CC == Cases[1].CC && 1345 isa<Constant>(Cases[0].CmpRHS) && 1346 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1347 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1348 return false; 1349 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1350 return false; 1351 } 1352 1353 return true; 1354} 1355 1356void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1357 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1358 1359 // Update machine-CFG edges. 1360 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1361 1362 // Figure out which block is immediately after the current one. 1363 MachineBasicBlock *NextBlock = 0; 1364 MachineFunction::iterator BBI = BrMBB; 1365 if (++BBI != FuncInfo.MF->end()) 1366 NextBlock = BBI; 1367 1368 if (I.isUnconditional()) { 1369 // Update machine-CFG edges. 1370 BrMBB->addSuccessor(Succ0MBB); 1371 1372 // If this is not a fall-through branch, emit the branch. 1373 if (Succ0MBB != NextBlock) 1374 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1375 MVT::Other, getControlRoot(), 1376 DAG.getBasicBlock(Succ0MBB))); 1377 1378 return; 1379 } 1380 1381 // If this condition is one of the special cases we handle, do special stuff 1382 // now. 1383 const Value *CondVal = I.getCondition(); 1384 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1385 1386 // If this is a series of conditions that are or'd or and'd together, emit 1387 // this as a sequence of branches instead of setcc's with and/or operations. 1388 // For example, instead of something like: 1389 // cmp A, B 1390 // C = seteq 1391 // cmp D, E 1392 // F = setle 1393 // or C, F 1394 // jnz foo 1395 // Emit: 1396 // cmp A, B 1397 // je foo 1398 // cmp D, E 1399 // jle foo 1400 // 1401 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1402 if (BOp->hasOneUse() && 1403 (BOp->getOpcode() == Instruction::And || 1404 BOp->getOpcode() == Instruction::Or)) { 1405 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1406 BOp->getOpcode()); 1407 // If the compares in later blocks need to use values not currently 1408 // exported from this block, export them now. This block should always 1409 // be the first entry. 1410 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1411 1412 // Allow some cases to be rejected. 1413 if (ShouldEmitAsBranches(SwitchCases)) { 1414 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1415 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1416 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1417 } 1418 1419 // Emit the branch for this block. 1420 visitSwitchCase(SwitchCases[0], BrMBB); 1421 SwitchCases.erase(SwitchCases.begin()); 1422 return; 1423 } 1424 1425 // Okay, we decided not to do this, remove any inserted MBB's and clear 1426 // SwitchCases. 1427 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1428 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1429 1430 SwitchCases.clear(); 1431 } 1432 } 1433 1434 // Create a CaseBlock record representing this branch. 1435 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1436 NULL, Succ0MBB, Succ1MBB, BrMBB); 1437 1438 // Use visitSwitchCase to actually insert the fast branch sequence for this 1439 // cond branch. 1440 visitSwitchCase(CB, BrMBB); 1441} 1442 1443/// visitSwitchCase - Emits the necessary code to represent a single node in 1444/// the binary search tree resulting from lowering a switch instruction. 1445void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1446 MachineBasicBlock *SwitchBB) { 1447 SDValue Cond; 1448 SDValue CondLHS = getValue(CB.CmpLHS); 1449 DebugLoc dl = getCurDebugLoc(); 1450 1451 // Build the setcc now. 1452 if (CB.CmpMHS == NULL) { 1453 // Fold "(X == true)" to X and "(X == false)" to !X to 1454 // handle common cases produced by branch lowering. 1455 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1456 CB.CC == ISD::SETEQ) 1457 Cond = CondLHS; 1458 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1459 CB.CC == ISD::SETEQ) { 1460 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1461 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1462 } else 1463 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1464 } else { 1465 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1466 1467 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1468 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1469 1470 SDValue CmpOp = getValue(CB.CmpMHS); 1471 EVT VT = CmpOp.getValueType(); 1472 1473 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1474 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1475 ISD::SETLE); 1476 } else { 1477 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1478 VT, CmpOp, DAG.getConstant(Low, VT)); 1479 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1480 DAG.getConstant(High-Low, VT), ISD::SETULE); 1481 } 1482 } 1483 1484 // Update successor info 1485 SwitchBB->addSuccessor(CB.TrueBB); 1486 SwitchBB->addSuccessor(CB.FalseBB); 1487 1488 // Set NextBlock to be the MBB immediately after the current one, if any. 1489 // This is used to avoid emitting unnecessary branches to the next block. 1490 MachineBasicBlock *NextBlock = 0; 1491 MachineFunction::iterator BBI = SwitchBB; 1492 if (++BBI != FuncInfo.MF->end()) 1493 NextBlock = BBI; 1494 1495 // If the lhs block is the next block, invert the condition so that we can 1496 // fall through to the lhs instead of the rhs block. 1497 if (CB.TrueBB == NextBlock) { 1498 std::swap(CB.TrueBB, CB.FalseBB); 1499 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1500 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1501 } 1502 1503 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1504 MVT::Other, getControlRoot(), Cond, 1505 DAG.getBasicBlock(CB.TrueBB)); 1506 1507 // Insert the false branch. Do this even if it's a fall through branch, 1508 // this makes it easier to do DAG optimizations which require inverting 1509 // the branch condition. 1510 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1511 DAG.getBasicBlock(CB.FalseBB)); 1512 1513 DAG.setRoot(BrCond); 1514} 1515 1516/// visitJumpTable - Emit JumpTable node in the current MBB 1517void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1518 // Emit the code for the jump table 1519 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1520 EVT PTy = TLI.getPointerTy(); 1521 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1522 JT.Reg, PTy); 1523 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1524 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1525 MVT::Other, Index.getValue(1), 1526 Table, Index); 1527 DAG.setRoot(BrJumpTable); 1528} 1529 1530/// visitJumpTableHeader - This function emits necessary code to produce index 1531/// in the JumpTable from switch case. 1532void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1533 JumpTableHeader &JTH, 1534 MachineBasicBlock *SwitchBB) { 1535 // Subtract the lowest switch case value from the value being switched on and 1536 // conditional branch to default mbb if the result is greater than the 1537 // difference between smallest and largest cases. 1538 SDValue SwitchOp = getValue(JTH.SValue); 1539 EVT VT = SwitchOp.getValueType(); 1540 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1541 DAG.getConstant(JTH.First, VT)); 1542 1543 // The SDNode we just created, which holds the value being switched on minus 1544 // the smallest case value, needs to be copied to a virtual register so it 1545 // can be used as an index into the jump table in a subsequent basic block. 1546 // This value may be smaller or larger than the target's pointer type, and 1547 // therefore require extension or truncating. 1548 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1549 1550 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1551 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1552 JumpTableReg, SwitchOp); 1553 JT.Reg = JumpTableReg; 1554 1555 // Emit the range check for the jump table, and branch to the default block 1556 // for the switch statement if the value being switched on exceeds the largest 1557 // case in the switch. 1558 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1559 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1560 DAG.getConstant(JTH.Last-JTH.First,VT), 1561 ISD::SETUGT); 1562 1563 // Set NextBlock to be the MBB immediately after the current one, if any. 1564 // This is used to avoid emitting unnecessary branches to the next block. 1565 MachineBasicBlock *NextBlock = 0; 1566 MachineFunction::iterator BBI = SwitchBB; 1567 1568 if (++BBI != FuncInfo.MF->end()) 1569 NextBlock = BBI; 1570 1571 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1572 MVT::Other, CopyTo, CMP, 1573 DAG.getBasicBlock(JT.Default)); 1574 1575 if (JT.MBB != NextBlock) 1576 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1577 DAG.getBasicBlock(JT.MBB)); 1578 1579 DAG.setRoot(BrCond); 1580} 1581 1582/// visitBitTestHeader - This function emits necessary code to produce value 1583/// suitable for "bit tests" 1584void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1585 MachineBasicBlock *SwitchBB) { 1586 // Subtract the minimum value 1587 SDValue SwitchOp = getValue(B.SValue); 1588 EVT VT = SwitchOp.getValueType(); 1589 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1590 DAG.getConstant(B.First, VT)); 1591 1592 // Check range 1593 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1594 TLI.getSetCCResultType(Sub.getValueType()), 1595 Sub, DAG.getConstant(B.Range, VT), 1596 ISD::SETUGT); 1597 1598 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), 1599 TLI.getPointerTy()); 1600 1601 B.Reg = FuncInfo.CreateReg(TLI.getPointerTy()); 1602 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1603 B.Reg, ShiftOp); 1604 1605 // Set NextBlock to be the MBB immediately after the current one, if any. 1606 // This is used to avoid emitting unnecessary branches to the next block. 1607 MachineBasicBlock *NextBlock = 0; 1608 MachineFunction::iterator BBI = SwitchBB; 1609 if (++BBI != FuncInfo.MF->end()) 1610 NextBlock = BBI; 1611 1612 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1613 1614 SwitchBB->addSuccessor(B.Default); 1615 SwitchBB->addSuccessor(MBB); 1616 1617 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1618 MVT::Other, CopyTo, RangeCmp, 1619 DAG.getBasicBlock(B.Default)); 1620 1621 if (MBB != NextBlock) 1622 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1623 DAG.getBasicBlock(MBB)); 1624 1625 DAG.setRoot(BrRange); 1626} 1627 1628/// visitBitTestCase - this function produces one "bit test" 1629void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB, 1630 unsigned Reg, 1631 BitTestCase &B, 1632 MachineBasicBlock *SwitchBB) { 1633 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg, 1634 TLI.getPointerTy()); 1635 SDValue Cmp; 1636 if (CountPopulation_64(B.Mask) == 1) { 1637 // Testing for a single bit; just compare the shift count with what it 1638 // would need to be to shift a 1 bit in that position. 1639 Cmp = DAG.getSetCC(getCurDebugLoc(), 1640 TLI.getSetCCResultType(ShiftOp.getValueType()), 1641 ShiftOp, 1642 DAG.getConstant(CountTrailingZeros_64(B.Mask), 1643 TLI.getPointerTy()), 1644 ISD::SETEQ); 1645 } else { 1646 // Make desired shift 1647 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), 1648 TLI.getPointerTy(), 1649 DAG.getConstant(1, TLI.getPointerTy()), 1650 ShiftOp); 1651 1652 // Emit bit tests and jumps 1653 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1654 TLI.getPointerTy(), SwitchVal, 1655 DAG.getConstant(B.Mask, TLI.getPointerTy())); 1656 Cmp = DAG.getSetCC(getCurDebugLoc(), 1657 TLI.getSetCCResultType(AndOp.getValueType()), 1658 AndOp, DAG.getConstant(0, TLI.getPointerTy()), 1659 ISD::SETNE); 1660 } 1661 1662 SwitchBB->addSuccessor(B.TargetBB); 1663 SwitchBB->addSuccessor(NextMBB); 1664 1665 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1666 MVT::Other, getControlRoot(), 1667 Cmp, DAG.getBasicBlock(B.TargetBB)); 1668 1669 // Set NextBlock to be the MBB immediately after the current one, if any. 1670 // This is used to avoid emitting unnecessary branches to the next block. 1671 MachineBasicBlock *NextBlock = 0; 1672 MachineFunction::iterator BBI = SwitchBB; 1673 if (++BBI != FuncInfo.MF->end()) 1674 NextBlock = BBI; 1675 1676 if (NextMBB != NextBlock) 1677 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1678 DAG.getBasicBlock(NextMBB)); 1679 1680 DAG.setRoot(BrAnd); 1681} 1682 1683void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1684 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1685 1686 // Retrieve successors. 1687 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1688 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1689 1690 const Value *Callee(I.getCalledValue()); 1691 if (isa<InlineAsm>(Callee)) 1692 visitInlineAsm(&I); 1693 else 1694 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1695 1696 // If the value of the invoke is used outside of its defining block, make it 1697 // available as a virtual register. 1698 CopyToExportRegsIfNeeded(&I); 1699 1700 // Update successor info 1701 InvokeMBB->addSuccessor(Return); 1702 InvokeMBB->addSuccessor(LandingPad); 1703 1704 // Drop into normal successor. 1705 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1706 MVT::Other, getControlRoot(), 1707 DAG.getBasicBlock(Return))); 1708} 1709 1710void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1711} 1712 1713/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1714/// small case ranges). 1715bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1716 CaseRecVector& WorkList, 1717 const Value* SV, 1718 MachineBasicBlock *Default, 1719 MachineBasicBlock *SwitchBB) { 1720 Case& BackCase = *(CR.Range.second-1); 1721 1722 // Size is the number of Cases represented by this range. 1723 size_t Size = CR.Range.second - CR.Range.first; 1724 if (Size > 3) 1725 return false; 1726 1727 // Get the MachineFunction which holds the current MBB. This is used when 1728 // inserting any additional MBBs necessary to represent the switch. 1729 MachineFunction *CurMF = FuncInfo.MF; 1730 1731 // Figure out which block is immediately after the current one. 1732 MachineBasicBlock *NextBlock = 0; 1733 MachineFunction::iterator BBI = CR.CaseBB; 1734 1735 if (++BBI != FuncInfo.MF->end()) 1736 NextBlock = BBI; 1737 1738 // TODO: If any two of the cases has the same destination, and if one value 1739 // is the same as the other, but has one bit unset that the other has set, 1740 // use bit manipulation to do two compares at once. For example: 1741 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1742 1743 // Rearrange the case blocks so that the last one falls through if possible. 1744 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1745 // The last case block won't fall through into 'NextBlock' if we emit the 1746 // branches in this order. See if rearranging a case value would help. 1747 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1748 if (I->BB == NextBlock) { 1749 std::swap(*I, BackCase); 1750 break; 1751 } 1752 } 1753 } 1754 1755 // Create a CaseBlock record representing a conditional branch to 1756 // the Case's target mbb if the value being switched on SV is equal 1757 // to C. 1758 MachineBasicBlock *CurBlock = CR.CaseBB; 1759 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1760 MachineBasicBlock *FallThrough; 1761 if (I != E-1) { 1762 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1763 CurMF->insert(BBI, FallThrough); 1764 1765 // Put SV in a virtual register to make it available from the new blocks. 1766 ExportFromCurrentBlock(SV); 1767 } else { 1768 // If the last case doesn't match, go to the default block. 1769 FallThrough = Default; 1770 } 1771 1772 const Value *RHS, *LHS, *MHS; 1773 ISD::CondCode CC; 1774 if (I->High == I->Low) { 1775 // This is just small small case range :) containing exactly 1 case 1776 CC = ISD::SETEQ; 1777 LHS = SV; RHS = I->High; MHS = NULL; 1778 } else { 1779 CC = ISD::SETLE; 1780 LHS = I->Low; MHS = SV; RHS = I->High; 1781 } 1782 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1783 1784 // If emitting the first comparison, just call visitSwitchCase to emit the 1785 // code into the current block. Otherwise, push the CaseBlock onto the 1786 // vector to be later processed by SDISel, and insert the node's MBB 1787 // before the next MBB. 1788 if (CurBlock == SwitchBB) 1789 visitSwitchCase(CB, SwitchBB); 1790 else 1791 SwitchCases.push_back(CB); 1792 1793 CurBlock = FallThrough; 1794 } 1795 1796 return true; 1797} 1798 1799static inline bool areJTsAllowed(const TargetLowering &TLI) { 1800 return !DisableJumpTables && 1801 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1802 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1803} 1804 1805static APInt ComputeRange(const APInt &First, const APInt &Last) { 1806 APInt LastExt(Last), FirstExt(First); 1807 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1808 LastExt.sext(BitWidth); FirstExt.sext(BitWidth); 1809 return (LastExt - FirstExt + 1ULL); 1810} 1811 1812/// handleJTSwitchCase - Emit jumptable for current switch case range 1813bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1814 CaseRecVector& WorkList, 1815 const Value* SV, 1816 MachineBasicBlock* Default, 1817 MachineBasicBlock *SwitchBB) { 1818 Case& FrontCase = *CR.Range.first; 1819 Case& BackCase = *(CR.Range.second-1); 1820 1821 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1822 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1823 1824 APInt TSize(First.getBitWidth(), 0); 1825 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1826 I!=E; ++I) 1827 TSize += I->size(); 1828 1829 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1830 return false; 1831 1832 APInt Range = ComputeRange(First, Last); 1833 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1834 if (Density < 0.4) 1835 return false; 1836 1837 DEBUG(dbgs() << "Lowering jump table\n" 1838 << "First entry: " << First << ". Last entry: " << Last << '\n' 1839 << "Range: " << Range 1840 << "Size: " << TSize << ". Density: " << Density << "\n\n"); 1841 1842 // Get the MachineFunction which holds the current MBB. This is used when 1843 // inserting any additional MBBs necessary to represent the switch. 1844 MachineFunction *CurMF = FuncInfo.MF; 1845 1846 // Figure out which block is immediately after the current one. 1847 MachineFunction::iterator BBI = CR.CaseBB; 1848 ++BBI; 1849 1850 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1851 1852 // Create a new basic block to hold the code for loading the address 1853 // of the jump table, and jumping to it. Update successor information; 1854 // we will either branch to the default case for the switch, or the jump 1855 // table. 1856 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1857 CurMF->insert(BBI, JumpTableBB); 1858 CR.CaseBB->addSuccessor(Default); 1859 CR.CaseBB->addSuccessor(JumpTableBB); 1860 1861 // Build a vector of destination BBs, corresponding to each target 1862 // of the jump table. If the value of the jump table slot corresponds to 1863 // a case statement, push the case's BB onto the vector, otherwise, push 1864 // the default BB. 1865 std::vector<MachineBasicBlock*> DestBBs; 1866 APInt TEI = First; 1867 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1868 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 1869 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 1870 1871 if (Low.sle(TEI) && TEI.sle(High)) { 1872 DestBBs.push_back(I->BB); 1873 if (TEI==High) 1874 ++I; 1875 } else { 1876 DestBBs.push_back(Default); 1877 } 1878 } 1879 1880 // Update successor info. Add one edge to each unique successor. 1881 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1882 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1883 E = DestBBs.end(); I != E; ++I) { 1884 if (!SuccsHandled[(*I)->getNumber()]) { 1885 SuccsHandled[(*I)->getNumber()] = true; 1886 JumpTableBB->addSuccessor(*I); 1887 } 1888 } 1889 1890 // Create a jump table index for this jump table. 1891 unsigned JTEncoding = TLI.getJumpTableEncoding(); 1892 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 1893 ->createJumpTableIndex(DestBBs); 1894 1895 // Set the jump table information so that we can codegen it as a second 1896 // MachineBasicBlock 1897 JumpTable JT(-1U, JTI, JumpTableBB, Default); 1898 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 1899 if (CR.CaseBB == SwitchBB) 1900 visitJumpTableHeader(JT, JTH, SwitchBB); 1901 1902 JTCases.push_back(JumpTableBlock(JTH, JT)); 1903 1904 return true; 1905} 1906 1907/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1908/// 2 subtrees. 1909bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 1910 CaseRecVector& WorkList, 1911 const Value* SV, 1912 MachineBasicBlock *Default, 1913 MachineBasicBlock *SwitchBB) { 1914 // Get the MachineFunction which holds the current MBB. This is used when 1915 // inserting any additional MBBs necessary to represent the switch. 1916 MachineFunction *CurMF = FuncInfo.MF; 1917 1918 // Figure out which block is immediately after the current one. 1919 MachineFunction::iterator BBI = CR.CaseBB; 1920 ++BBI; 1921 1922 Case& FrontCase = *CR.Range.first; 1923 Case& BackCase = *(CR.Range.second-1); 1924 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1925 1926 // Size is the number of Cases represented by this range. 1927 unsigned Size = CR.Range.second - CR.Range.first; 1928 1929 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1930 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1931 double FMetric = 0; 1932 CaseItr Pivot = CR.Range.first + Size/2; 1933 1934 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1935 // (heuristically) allow us to emit JumpTable's later. 1936 APInt TSize(First.getBitWidth(), 0); 1937 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1938 I!=E; ++I) 1939 TSize += I->size(); 1940 1941 APInt LSize = FrontCase.size(); 1942 APInt RSize = TSize-LSize; 1943 DEBUG(dbgs() << "Selecting best pivot: \n" 1944 << "First: " << First << ", Last: " << Last <<'\n' 1945 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 1946 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1947 J!=E; ++I, ++J) { 1948 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 1949 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 1950 APInt Range = ComputeRange(LEnd, RBegin); 1951 assert((Range - 2ULL).isNonNegative() && 1952 "Invalid case distance"); 1953 double LDensity = (double)LSize.roundToDouble() / 1954 (LEnd - First + 1ULL).roundToDouble(); 1955 double RDensity = (double)RSize.roundToDouble() / 1956 (Last - RBegin + 1ULL).roundToDouble(); 1957 double Metric = Range.logBase2()*(LDensity+RDensity); 1958 // Should always split in some non-trivial place 1959 DEBUG(dbgs() <<"=>Step\n" 1960 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 1961 << "LDensity: " << LDensity 1962 << ", RDensity: " << RDensity << '\n' 1963 << "Metric: " << Metric << '\n'); 1964 if (FMetric < Metric) { 1965 Pivot = J; 1966 FMetric = Metric; 1967 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 1968 } 1969 1970 LSize += J->size(); 1971 RSize -= J->size(); 1972 } 1973 if (areJTsAllowed(TLI)) { 1974 // If our case is dense we *really* should handle it earlier! 1975 assert((FMetric > 0) && "Should handle dense range earlier!"); 1976 } else { 1977 Pivot = CR.Range.first + Size/2; 1978 } 1979 1980 CaseRange LHSR(CR.Range.first, Pivot); 1981 CaseRange RHSR(Pivot, CR.Range.second); 1982 Constant *C = Pivot->Low; 1983 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1984 1985 // We know that we branch to the LHS if the Value being switched on is 1986 // less than the Pivot value, C. We use this to optimize our binary 1987 // tree a bit, by recognizing that if SV is greater than or equal to the 1988 // LHS's Case Value, and that Case Value is exactly one less than the 1989 // Pivot's Value, then we can branch directly to the LHS's Target, 1990 // rather than creating a leaf node for it. 1991 if ((LHSR.second - LHSR.first) == 1 && 1992 LHSR.first->High == CR.GE && 1993 cast<ConstantInt>(C)->getValue() == 1994 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 1995 TrueBB = LHSR.first->BB; 1996 } else { 1997 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1998 CurMF->insert(BBI, TrueBB); 1999 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2000 2001 // Put SV in a virtual register to make it available from the new blocks. 2002 ExportFromCurrentBlock(SV); 2003 } 2004 2005 // Similar to the optimization above, if the Value being switched on is 2006 // known to be less than the Constant CR.LT, and the current Case Value 2007 // is CR.LT - 1, then we can branch directly to the target block for 2008 // the current Case Value, rather than emitting a RHS leaf node for it. 2009 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2010 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2011 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2012 FalseBB = RHSR.first->BB; 2013 } else { 2014 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2015 CurMF->insert(BBI, FalseBB); 2016 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2017 2018 // Put SV in a virtual register to make it available from the new blocks. 2019 ExportFromCurrentBlock(SV); 2020 } 2021 2022 // Create a CaseBlock record representing a conditional branch to 2023 // the LHS node if the value being switched on SV is less than C. 2024 // Otherwise, branch to LHS. 2025 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2026 2027 if (CR.CaseBB == SwitchBB) 2028 visitSwitchCase(CB, SwitchBB); 2029 else 2030 SwitchCases.push_back(CB); 2031 2032 return true; 2033} 2034 2035/// handleBitTestsSwitchCase - if current case range has few destination and 2036/// range span less, than machine word bitwidth, encode case range into series 2037/// of masks and emit bit tests with these masks. 2038bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2039 CaseRecVector& WorkList, 2040 const Value* SV, 2041 MachineBasicBlock* Default, 2042 MachineBasicBlock *SwitchBB){ 2043 EVT PTy = TLI.getPointerTy(); 2044 unsigned IntPtrBits = PTy.getSizeInBits(); 2045 2046 Case& FrontCase = *CR.Range.first; 2047 Case& BackCase = *(CR.Range.second-1); 2048 2049 // Get the MachineFunction which holds the current MBB. This is used when 2050 // inserting any additional MBBs necessary to represent the switch. 2051 MachineFunction *CurMF = FuncInfo.MF; 2052 2053 // If target does not have legal shift left, do not emit bit tests at all. 2054 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2055 return false; 2056 2057 size_t numCmps = 0; 2058 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2059 I!=E; ++I) { 2060 // Single case counts one, case range - two. 2061 numCmps += (I->Low == I->High ? 1 : 2); 2062 } 2063 2064 // Count unique destinations 2065 SmallSet<MachineBasicBlock*, 4> Dests; 2066 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2067 Dests.insert(I->BB); 2068 if (Dests.size() > 3) 2069 // Don't bother the code below, if there are too much unique destinations 2070 return false; 2071 } 2072 DEBUG(dbgs() << "Total number of unique destinations: " 2073 << Dests.size() << '\n' 2074 << "Total number of comparisons: " << numCmps << '\n'); 2075 2076 // Compute span of values. 2077 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2078 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2079 APInt cmpRange = maxValue - minValue; 2080 2081 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2082 << "Low bound: " << minValue << '\n' 2083 << "High bound: " << maxValue << '\n'); 2084 2085 if (cmpRange.uge(IntPtrBits) || 2086 (!(Dests.size() == 1 && numCmps >= 3) && 2087 !(Dests.size() == 2 && numCmps >= 5) && 2088 !(Dests.size() >= 3 && numCmps >= 6))) 2089 return false; 2090 2091 DEBUG(dbgs() << "Emitting bit tests\n"); 2092 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2093 2094 // Optimize the case where all the case values fit in a 2095 // word without having to subtract minValue. In this case, 2096 // we can optimize away the subtraction. 2097 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2098 cmpRange = maxValue; 2099 } else { 2100 lowBound = minValue; 2101 } 2102 2103 CaseBitsVector CasesBits; 2104 unsigned i, count = 0; 2105 2106 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2107 MachineBasicBlock* Dest = I->BB; 2108 for (i = 0; i < count; ++i) 2109 if (Dest == CasesBits[i].BB) 2110 break; 2111 2112 if (i == count) { 2113 assert((count < 3) && "Too much destinations to test!"); 2114 CasesBits.push_back(CaseBits(0, Dest, 0)); 2115 count++; 2116 } 2117 2118 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2119 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2120 2121 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2122 uint64_t hi = (highValue - lowBound).getZExtValue(); 2123 2124 for (uint64_t j = lo; j <= hi; j++) { 2125 CasesBits[i].Mask |= 1ULL << j; 2126 CasesBits[i].Bits++; 2127 } 2128 2129 } 2130 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2131 2132 BitTestInfo BTC; 2133 2134 // Figure out which block is immediately after the current one. 2135 MachineFunction::iterator BBI = CR.CaseBB; 2136 ++BBI; 2137 2138 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2139 2140 DEBUG(dbgs() << "Cases:\n"); 2141 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2142 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2143 << ", Bits: " << CasesBits[i].Bits 2144 << ", BB: " << CasesBits[i].BB << '\n'); 2145 2146 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2147 CurMF->insert(BBI, CaseBB); 2148 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2149 CaseBB, 2150 CasesBits[i].BB)); 2151 2152 // Put SV in a virtual register to make it available from the new blocks. 2153 ExportFromCurrentBlock(SV); 2154 } 2155 2156 BitTestBlock BTB(lowBound, cmpRange, SV, 2157 -1U, (CR.CaseBB == SwitchBB), 2158 CR.CaseBB, Default, BTC); 2159 2160 if (CR.CaseBB == SwitchBB) 2161 visitBitTestHeader(BTB, SwitchBB); 2162 2163 BitTestCases.push_back(BTB); 2164 2165 return true; 2166} 2167 2168/// Clusterify - Transform simple list of Cases into list of CaseRange's 2169size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2170 const SwitchInst& SI) { 2171 size_t numCmps = 0; 2172 2173 // Start with "simple" cases 2174 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2175 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2176 Cases.push_back(Case(SI.getSuccessorValue(i), 2177 SI.getSuccessorValue(i), 2178 SMBB)); 2179 } 2180 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2181 2182 // Merge case into clusters 2183 if (Cases.size() >= 2) 2184 // Must recompute end() each iteration because it may be 2185 // invalidated by erase if we hold on to it 2186 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) { 2187 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2188 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2189 MachineBasicBlock* nextBB = J->BB; 2190 MachineBasicBlock* currentBB = I->BB; 2191 2192 // If the two neighboring cases go to the same destination, merge them 2193 // into a single case. 2194 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2195 I->High = J->High; 2196 J = Cases.erase(J); 2197 } else { 2198 I = J++; 2199 } 2200 } 2201 2202 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2203 if (I->Low != I->High) 2204 // A range counts double, since it requires two compares. 2205 ++numCmps; 2206 } 2207 2208 return numCmps; 2209} 2210 2211void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2212 MachineBasicBlock *Last) { 2213 // Update JTCases. 2214 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2215 if (JTCases[i].first.HeaderBB == First) 2216 JTCases[i].first.HeaderBB = Last; 2217 2218 // Update BitTestCases. 2219 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2220 if (BitTestCases[i].Parent == First) 2221 BitTestCases[i].Parent = Last; 2222} 2223 2224void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2225 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2226 2227 // Figure out which block is immediately after the current one. 2228 MachineBasicBlock *NextBlock = 0; 2229 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2230 2231 // If there is only the default destination, branch to it if it is not the 2232 // next basic block. Otherwise, just fall through. 2233 if (SI.getNumOperands() == 2) { 2234 // Update machine-CFG edges. 2235 2236 // If this is not a fall-through branch, emit the branch. 2237 SwitchMBB->addSuccessor(Default); 2238 if (Default != NextBlock) 2239 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2240 MVT::Other, getControlRoot(), 2241 DAG.getBasicBlock(Default))); 2242 2243 return; 2244 } 2245 2246 // If there are any non-default case statements, create a vector of Cases 2247 // representing each one, and sort the vector so that we can efficiently 2248 // create a binary search tree from them. 2249 CaseVector Cases; 2250 size_t numCmps = Clusterify(Cases, SI); 2251 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2252 << ". Total compares: " << numCmps << '\n'); 2253 numCmps = 0; 2254 2255 // Get the Value to be switched on and default basic blocks, which will be 2256 // inserted into CaseBlock records, representing basic blocks in the binary 2257 // search tree. 2258 const Value *SV = SI.getOperand(0); 2259 2260 // Push the initial CaseRec onto the worklist 2261 CaseRecVector WorkList; 2262 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2263 CaseRange(Cases.begin(),Cases.end()))); 2264 2265 while (!WorkList.empty()) { 2266 // Grab a record representing a case range to process off the worklist 2267 CaseRec CR = WorkList.back(); 2268 WorkList.pop_back(); 2269 2270 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2271 continue; 2272 2273 // If the range has few cases (two or less) emit a series of specific 2274 // tests. 2275 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2276 continue; 2277 2278 // If the switch has more than 5 blocks, and at least 40% dense, and the 2279 // target supports indirect branches, then emit a jump table rather than 2280 // lowering the switch to a binary tree of conditional branches. 2281 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2282 continue; 2283 2284 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2285 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2286 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2287 } 2288} 2289 2290void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2291 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2292 2293 // Update machine-CFG edges with unique successors. 2294 SmallVector<BasicBlock*, 32> succs; 2295 succs.reserve(I.getNumSuccessors()); 2296 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2297 succs.push_back(I.getSuccessor(i)); 2298 array_pod_sort(succs.begin(), succs.end()); 2299 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2300 for (unsigned i = 0, e = succs.size(); i != e; ++i) 2301 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]); 2302 2303 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2304 MVT::Other, getControlRoot(), 2305 getValue(I.getAddress()))); 2306} 2307 2308void SelectionDAGBuilder::visitFSub(const User &I) { 2309 // -0.0 - X --> fneg 2310 const Type *Ty = I.getType(); 2311 if (Ty->isVectorTy()) { 2312 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2313 const VectorType *DestTy = cast<VectorType>(I.getType()); 2314 const Type *ElTy = DestTy->getElementType(); 2315 unsigned VL = DestTy->getNumElements(); 2316 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2317 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2318 if (CV == CNZ) { 2319 SDValue Op2 = getValue(I.getOperand(1)); 2320 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2321 Op2.getValueType(), Op2)); 2322 return; 2323 } 2324 } 2325 } 2326 2327 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2328 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2329 SDValue Op2 = getValue(I.getOperand(1)); 2330 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2331 Op2.getValueType(), Op2)); 2332 return; 2333 } 2334 2335 visitBinary(I, ISD::FSUB); 2336} 2337 2338void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2339 SDValue Op1 = getValue(I.getOperand(0)); 2340 SDValue Op2 = getValue(I.getOperand(1)); 2341 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2342 Op1.getValueType(), Op1, Op2)); 2343} 2344 2345void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2346 SDValue Op1 = getValue(I.getOperand(0)); 2347 SDValue Op2 = getValue(I.getOperand(1)); 2348 if (!I.getType()->isVectorTy() && 2349 Op2.getValueType() != TLI.getShiftAmountTy()) { 2350 // If the operand is smaller than the shift count type, promote it. 2351 EVT PTy = TLI.getPointerTy(); 2352 EVT STy = TLI.getShiftAmountTy(); 2353 if (STy.bitsGT(Op2.getValueType())) 2354 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2355 TLI.getShiftAmountTy(), Op2); 2356 // If the operand is larger than the shift count type but the shift 2357 // count type has enough bits to represent any shift value, truncate 2358 // it now. This is a common case and it exposes the truncate to 2359 // optimization early. 2360 else if (STy.getSizeInBits() >= 2361 Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2362 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2363 TLI.getShiftAmountTy(), Op2); 2364 // Otherwise we'll need to temporarily settle for some other 2365 // convenient type; type legalization will make adjustments as 2366 // needed. 2367 else if (PTy.bitsLT(Op2.getValueType())) 2368 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2369 TLI.getPointerTy(), Op2); 2370 else if (PTy.bitsGT(Op2.getValueType())) 2371 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2372 TLI.getPointerTy(), Op2); 2373 } 2374 2375 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2376 Op1.getValueType(), Op1, Op2)); 2377} 2378 2379void SelectionDAGBuilder::visitICmp(const User &I) { 2380 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2381 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2382 predicate = IC->getPredicate(); 2383 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2384 predicate = ICmpInst::Predicate(IC->getPredicate()); 2385 SDValue Op1 = getValue(I.getOperand(0)); 2386 SDValue Op2 = getValue(I.getOperand(1)); 2387 ISD::CondCode Opcode = getICmpCondCode(predicate); 2388 2389 EVT DestVT = TLI.getValueType(I.getType()); 2390 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2391} 2392 2393void SelectionDAGBuilder::visitFCmp(const User &I) { 2394 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2395 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2396 predicate = FC->getPredicate(); 2397 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2398 predicate = FCmpInst::Predicate(FC->getPredicate()); 2399 SDValue Op1 = getValue(I.getOperand(0)); 2400 SDValue Op2 = getValue(I.getOperand(1)); 2401 ISD::CondCode Condition = getFCmpCondCode(predicate); 2402 EVT DestVT = TLI.getValueType(I.getType()); 2403 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2404} 2405 2406void SelectionDAGBuilder::visitSelect(const User &I) { 2407 SmallVector<EVT, 4> ValueVTs; 2408 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2409 unsigned NumValues = ValueVTs.size(); 2410 if (NumValues == 0) return; 2411 2412 SmallVector<SDValue, 4> Values(NumValues); 2413 SDValue Cond = getValue(I.getOperand(0)); 2414 SDValue TrueVal = getValue(I.getOperand(1)); 2415 SDValue FalseVal = getValue(I.getOperand(2)); 2416 2417 for (unsigned i = 0; i != NumValues; ++i) 2418 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2419 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2420 Cond, 2421 SDValue(TrueVal.getNode(), 2422 TrueVal.getResNo() + i), 2423 SDValue(FalseVal.getNode(), 2424 FalseVal.getResNo() + i)); 2425 2426 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2427 DAG.getVTList(&ValueVTs[0], NumValues), 2428 &Values[0], NumValues)); 2429} 2430 2431void SelectionDAGBuilder::visitTrunc(const User &I) { 2432 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2433 SDValue N = getValue(I.getOperand(0)); 2434 EVT DestVT = TLI.getValueType(I.getType()); 2435 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2436} 2437 2438void SelectionDAGBuilder::visitZExt(const User &I) { 2439 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2440 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2441 SDValue N = getValue(I.getOperand(0)); 2442 EVT DestVT = TLI.getValueType(I.getType()); 2443 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2444} 2445 2446void SelectionDAGBuilder::visitSExt(const User &I) { 2447 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2448 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2449 SDValue N = getValue(I.getOperand(0)); 2450 EVT DestVT = TLI.getValueType(I.getType()); 2451 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2452} 2453 2454void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2455 // FPTrunc is never a no-op cast, no need to check 2456 SDValue N = getValue(I.getOperand(0)); 2457 EVT DestVT = TLI.getValueType(I.getType()); 2458 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2459 DestVT, N, DAG.getIntPtrConstant(0))); 2460} 2461 2462void SelectionDAGBuilder::visitFPExt(const User &I){ 2463 // FPTrunc is never a no-op cast, no need to check 2464 SDValue N = getValue(I.getOperand(0)); 2465 EVT DestVT = TLI.getValueType(I.getType()); 2466 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2467} 2468 2469void SelectionDAGBuilder::visitFPToUI(const User &I) { 2470 // FPToUI is never a no-op cast, no need to check 2471 SDValue N = getValue(I.getOperand(0)); 2472 EVT DestVT = TLI.getValueType(I.getType()); 2473 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2474} 2475 2476void SelectionDAGBuilder::visitFPToSI(const User &I) { 2477 // FPToSI is never a no-op cast, no need to check 2478 SDValue N = getValue(I.getOperand(0)); 2479 EVT DestVT = TLI.getValueType(I.getType()); 2480 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2481} 2482 2483void SelectionDAGBuilder::visitUIToFP(const User &I) { 2484 // UIToFP is never a no-op cast, no need to check 2485 SDValue N = getValue(I.getOperand(0)); 2486 EVT DestVT = TLI.getValueType(I.getType()); 2487 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2488} 2489 2490void SelectionDAGBuilder::visitSIToFP(const User &I){ 2491 // SIToFP is never a no-op cast, no need to check 2492 SDValue N = getValue(I.getOperand(0)); 2493 EVT DestVT = TLI.getValueType(I.getType()); 2494 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2495} 2496 2497void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2498 // What to do depends on the size of the integer and the size of the pointer. 2499 // We can either truncate, zero extend, or no-op, accordingly. 2500 SDValue N = getValue(I.getOperand(0)); 2501 EVT DestVT = TLI.getValueType(I.getType()); 2502 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2503} 2504 2505void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2506 // What to do depends on the size of the integer and the size of the pointer. 2507 // We can either truncate, zero extend, or no-op, accordingly. 2508 SDValue N = getValue(I.getOperand(0)); 2509 EVT DestVT = TLI.getValueType(I.getType()); 2510 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2511} 2512 2513void SelectionDAGBuilder::visitBitCast(const User &I) { 2514 SDValue N = getValue(I.getOperand(0)); 2515 EVT DestVT = TLI.getValueType(I.getType()); 2516 2517 // BitCast assures us that source and destination are the same size so this is 2518 // either a BIT_CONVERT or a no-op. 2519 if (DestVT != N.getValueType()) 2520 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 2521 DestVT, N)); // convert types. 2522 else 2523 setValue(&I, N); // noop cast. 2524} 2525 2526void SelectionDAGBuilder::visitInsertElement(const User &I) { 2527 SDValue InVec = getValue(I.getOperand(0)); 2528 SDValue InVal = getValue(I.getOperand(1)); 2529 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2530 TLI.getPointerTy(), 2531 getValue(I.getOperand(2))); 2532 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2533 TLI.getValueType(I.getType()), 2534 InVec, InVal, InIdx)); 2535} 2536 2537void SelectionDAGBuilder::visitExtractElement(const User &I) { 2538 SDValue InVec = getValue(I.getOperand(0)); 2539 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2540 TLI.getPointerTy(), 2541 getValue(I.getOperand(1))); 2542 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2543 TLI.getValueType(I.getType()), InVec, InIdx)); 2544} 2545 2546// Utility for visitShuffleVector - Returns true if the mask is mask starting 2547// from SIndx and increasing to the element length (undefs are allowed). 2548static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2549 unsigned MaskNumElts = Mask.size(); 2550 for (unsigned i = 0; i != MaskNumElts; ++i) 2551 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2552 return false; 2553 return true; 2554} 2555 2556void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2557 SmallVector<int, 8> Mask; 2558 SDValue Src1 = getValue(I.getOperand(0)); 2559 SDValue Src2 = getValue(I.getOperand(1)); 2560 2561 // Convert the ConstantVector mask operand into an array of ints, with -1 2562 // representing undef values. 2563 SmallVector<Constant*, 8> MaskElts; 2564 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2565 unsigned MaskNumElts = MaskElts.size(); 2566 for (unsigned i = 0; i != MaskNumElts; ++i) { 2567 if (isa<UndefValue>(MaskElts[i])) 2568 Mask.push_back(-1); 2569 else 2570 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2571 } 2572 2573 EVT VT = TLI.getValueType(I.getType()); 2574 EVT SrcVT = Src1.getValueType(); 2575 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2576 2577 if (SrcNumElts == MaskNumElts) { 2578 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2579 &Mask[0])); 2580 return; 2581 } 2582 2583 // Normalize the shuffle vector since mask and vector length don't match. 2584 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2585 // Mask is longer than the source vectors and is a multiple of the source 2586 // vectors. We can use concatenate vector to make the mask and vectors 2587 // lengths match. 2588 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2589 // The shuffle is concatenating two vectors together. 2590 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2591 VT, Src1, Src2)); 2592 return; 2593 } 2594 2595 // Pad both vectors with undefs to make them the same length as the mask. 2596 unsigned NumConcat = MaskNumElts / SrcNumElts; 2597 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2598 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2599 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2600 2601 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2602 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2603 MOps1[0] = Src1; 2604 MOps2[0] = Src2; 2605 2606 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2607 getCurDebugLoc(), VT, 2608 &MOps1[0], NumConcat); 2609 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2610 getCurDebugLoc(), VT, 2611 &MOps2[0], NumConcat); 2612 2613 // Readjust mask for new input vector length. 2614 SmallVector<int, 8> MappedOps; 2615 for (unsigned i = 0; i != MaskNumElts; ++i) { 2616 int Idx = Mask[i]; 2617 if (Idx < (int)SrcNumElts) 2618 MappedOps.push_back(Idx); 2619 else 2620 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2621 } 2622 2623 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2624 &MappedOps[0])); 2625 return; 2626 } 2627 2628 if (SrcNumElts > MaskNumElts) { 2629 // Analyze the access pattern of the vector to see if we can extract 2630 // two subvectors and do the shuffle. The analysis is done by calculating 2631 // the range of elements the mask access on both vectors. 2632 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2633 int MaxRange[2] = {-1, -1}; 2634 2635 for (unsigned i = 0; i != MaskNumElts; ++i) { 2636 int Idx = Mask[i]; 2637 int Input = 0; 2638 if (Idx < 0) 2639 continue; 2640 2641 if (Idx >= (int)SrcNumElts) { 2642 Input = 1; 2643 Idx -= SrcNumElts; 2644 } 2645 if (Idx > MaxRange[Input]) 2646 MaxRange[Input] = Idx; 2647 if (Idx < MinRange[Input]) 2648 MinRange[Input] = Idx; 2649 } 2650 2651 // Check if the access is smaller than the vector size and can we find 2652 // a reasonable extract index. 2653 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2654 // Extract. 2655 int StartIdx[2]; // StartIdx to extract from 2656 for (int Input=0; Input < 2; ++Input) { 2657 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2658 RangeUse[Input] = 0; // Unused 2659 StartIdx[Input] = 0; 2660 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2661 // Fits within range but we should see if we can find a good 2662 // start index that is a multiple of the mask length. 2663 if (MaxRange[Input] < (int)MaskNumElts) { 2664 RangeUse[Input] = 1; // Extract from beginning of the vector 2665 StartIdx[Input] = 0; 2666 } else { 2667 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2668 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2669 StartIdx[Input] + MaskNumElts < SrcNumElts) 2670 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2671 } 2672 } 2673 } 2674 2675 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2676 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2677 return; 2678 } 2679 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2680 // Extract appropriate subvector and generate a vector shuffle 2681 for (int Input=0; Input < 2; ++Input) { 2682 SDValue &Src = Input == 0 ? Src1 : Src2; 2683 if (RangeUse[Input] == 0) 2684 Src = DAG.getUNDEF(VT); 2685 else 2686 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2687 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2688 } 2689 2690 // Calculate new mask. 2691 SmallVector<int, 8> MappedOps; 2692 for (unsigned i = 0; i != MaskNumElts; ++i) { 2693 int Idx = Mask[i]; 2694 if (Idx < 0) 2695 MappedOps.push_back(Idx); 2696 else if (Idx < (int)SrcNumElts) 2697 MappedOps.push_back(Idx - StartIdx[0]); 2698 else 2699 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2700 } 2701 2702 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2703 &MappedOps[0])); 2704 return; 2705 } 2706 } 2707 2708 // We can't use either concat vectors or extract subvectors so fall back to 2709 // replacing the shuffle with extract and build vector. 2710 // to insert and build vector. 2711 EVT EltVT = VT.getVectorElementType(); 2712 EVT PtrVT = TLI.getPointerTy(); 2713 SmallVector<SDValue,8> Ops; 2714 for (unsigned i = 0; i != MaskNumElts; ++i) { 2715 if (Mask[i] < 0) { 2716 Ops.push_back(DAG.getUNDEF(EltVT)); 2717 } else { 2718 int Idx = Mask[i]; 2719 SDValue Res; 2720 2721 if (Idx < (int)SrcNumElts) 2722 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2723 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2724 else 2725 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2726 EltVT, Src2, 2727 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2728 2729 Ops.push_back(Res); 2730 } 2731 } 2732 2733 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2734 VT, &Ops[0], Ops.size())); 2735} 2736 2737void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2738 const Value *Op0 = I.getOperand(0); 2739 const Value *Op1 = I.getOperand(1); 2740 const Type *AggTy = I.getType(); 2741 const Type *ValTy = Op1->getType(); 2742 bool IntoUndef = isa<UndefValue>(Op0); 2743 bool FromUndef = isa<UndefValue>(Op1); 2744 2745 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2746 2747 SmallVector<EVT, 4> AggValueVTs; 2748 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2749 SmallVector<EVT, 4> ValValueVTs; 2750 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2751 2752 unsigned NumAggValues = AggValueVTs.size(); 2753 unsigned NumValValues = ValValueVTs.size(); 2754 SmallVector<SDValue, 4> Values(NumAggValues); 2755 2756 SDValue Agg = getValue(Op0); 2757 SDValue Val = getValue(Op1); 2758 unsigned i = 0; 2759 // Copy the beginning value(s) from the original aggregate. 2760 for (; i != LinearIndex; ++i) 2761 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2762 SDValue(Agg.getNode(), Agg.getResNo() + i); 2763 // Copy values from the inserted value(s). 2764 for (; i != LinearIndex + NumValValues; ++i) 2765 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2766 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2767 // Copy remaining value(s) from the original aggregate. 2768 for (; i != NumAggValues; ++i) 2769 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2770 SDValue(Agg.getNode(), Agg.getResNo() + i); 2771 2772 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2773 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2774 &Values[0], NumAggValues)); 2775} 2776 2777void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2778 const Value *Op0 = I.getOperand(0); 2779 const Type *AggTy = Op0->getType(); 2780 const Type *ValTy = I.getType(); 2781 bool OutOfUndef = isa<UndefValue>(Op0); 2782 2783 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2784 2785 SmallVector<EVT, 4> ValValueVTs; 2786 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2787 2788 unsigned NumValValues = ValValueVTs.size(); 2789 SmallVector<SDValue, 4> Values(NumValValues); 2790 2791 SDValue Agg = getValue(Op0); 2792 // Copy out the selected value(s). 2793 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2794 Values[i - LinearIndex] = 2795 OutOfUndef ? 2796 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2797 SDValue(Agg.getNode(), Agg.getResNo() + i); 2798 2799 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2800 DAG.getVTList(&ValValueVTs[0], NumValValues), 2801 &Values[0], NumValValues)); 2802} 2803 2804void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2805 SDValue N = getValue(I.getOperand(0)); 2806 const Type *Ty = I.getOperand(0)->getType(); 2807 2808 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2809 OI != E; ++OI) { 2810 const Value *Idx = *OI; 2811 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2812 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2813 if (Field) { 2814 // N = N + Offset 2815 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2816 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2817 DAG.getIntPtrConstant(Offset)); 2818 } 2819 2820 Ty = StTy->getElementType(Field); 2821 } else { 2822 Ty = cast<SequentialType>(Ty)->getElementType(); 2823 2824 // If this is a constant subscript, handle it quickly. 2825 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2826 if (CI->isZero()) continue; 2827 uint64_t Offs = 2828 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2829 SDValue OffsVal; 2830 EVT PTy = TLI.getPointerTy(); 2831 unsigned PtrBits = PTy.getSizeInBits(); 2832 if (PtrBits < 64) 2833 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2834 TLI.getPointerTy(), 2835 DAG.getConstant(Offs, MVT::i64)); 2836 else 2837 OffsVal = DAG.getIntPtrConstant(Offs); 2838 2839 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2840 OffsVal); 2841 continue; 2842 } 2843 2844 // N = N + Idx * ElementSize; 2845 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2846 TD->getTypeAllocSize(Ty)); 2847 SDValue IdxN = getValue(Idx); 2848 2849 // If the index is smaller or larger than intptr_t, truncate or extend 2850 // it. 2851 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2852 2853 // If this is a multiply by a power of two, turn it into a shl 2854 // immediately. This is a very common case. 2855 if (ElementSize != 1) { 2856 if (ElementSize.isPowerOf2()) { 2857 unsigned Amt = ElementSize.logBase2(); 2858 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2859 N.getValueType(), IdxN, 2860 DAG.getConstant(Amt, TLI.getPointerTy())); 2861 } else { 2862 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2863 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2864 N.getValueType(), IdxN, Scale); 2865 } 2866 } 2867 2868 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2869 N.getValueType(), N, IdxN); 2870 } 2871 } 2872 2873 setValue(&I, N); 2874} 2875 2876void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 2877 // If this is a fixed sized alloca in the entry block of the function, 2878 // allocate it statically on the stack. 2879 if (FuncInfo.StaticAllocaMap.count(&I)) 2880 return; // getValue will auto-populate this. 2881 2882 const Type *Ty = I.getAllocatedType(); 2883 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 2884 unsigned Align = 2885 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2886 I.getAlignment()); 2887 2888 SDValue AllocSize = getValue(I.getArraySize()); 2889 2890 EVT IntPtr = TLI.getPointerTy(); 2891 if (AllocSize.getValueType() != IntPtr) 2892 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 2893 2894 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 2895 AllocSize, 2896 DAG.getConstant(TySize, IntPtr)); 2897 2898 // Handle alignment. If the requested alignment is less than or equal to 2899 // the stack alignment, ignore it. If the size is greater than or equal to 2900 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2901 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); 2902 if (Align <= StackAlign) 2903 Align = 0; 2904 2905 // Round the size of the allocation up to the stack alignment size 2906 // by add SA-1 to the size. 2907 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2908 AllocSize.getValueType(), AllocSize, 2909 DAG.getIntPtrConstant(StackAlign-1)); 2910 2911 // Mask out the low bits for alignment purposes. 2912 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 2913 AllocSize.getValueType(), AllocSize, 2914 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2915 2916 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2917 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 2918 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 2919 VTs, Ops, 3); 2920 setValue(&I, DSA); 2921 DAG.setRoot(DSA.getValue(1)); 2922 2923 // Inform the Frame Information that we have just allocated a variable-sized 2924 // object. 2925 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 2926} 2927 2928void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 2929 const Value *SV = I.getOperand(0); 2930 SDValue Ptr = getValue(SV); 2931 2932 const Type *Ty = I.getType(); 2933 2934 bool isVolatile = I.isVolatile(); 2935 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2936 unsigned Alignment = I.getAlignment(); 2937 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 2938 2939 SmallVector<EVT, 4> ValueVTs; 2940 SmallVector<uint64_t, 4> Offsets; 2941 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2942 unsigned NumValues = ValueVTs.size(); 2943 if (NumValues == 0) 2944 return; 2945 2946 SDValue Root; 2947 bool ConstantMemory = false; 2948 if (I.isVolatile()) 2949 // Serialize volatile loads with other side effects. 2950 Root = getRoot(); 2951 else if (AA->pointsToConstantMemory( 2952 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 2953 // Do not serialize (non-volatile) loads of constant memory with anything. 2954 Root = DAG.getEntryNode(); 2955 ConstantMemory = true; 2956 } else { 2957 // Do not serialize non-volatile loads against each other. 2958 Root = DAG.getRoot(); 2959 } 2960 2961 SmallVector<SDValue, 4> Values(NumValues); 2962 SmallVector<SDValue, 4> Chains(NumValues); 2963 EVT PtrVT = Ptr.getValueType(); 2964 for (unsigned i = 0; i != NumValues; ++i) { 2965 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2966 PtrVT, Ptr, 2967 DAG.getConstant(Offsets[i], PtrVT)); 2968 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 2969 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 2970 isNonTemporal, Alignment, TBAAInfo); 2971 2972 Values[i] = L; 2973 Chains[i] = L.getValue(1); 2974 } 2975 2976 if (!ConstantMemory) { 2977 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 2978 MVT::Other, &Chains[0], NumValues); 2979 if (isVolatile) 2980 DAG.setRoot(Chain); 2981 else 2982 PendingLoads.push_back(Chain); 2983 } 2984 2985 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2986 DAG.getVTList(&ValueVTs[0], NumValues), 2987 &Values[0], NumValues)); 2988} 2989 2990void SelectionDAGBuilder::visitStore(const StoreInst &I) { 2991 const Value *SrcV = I.getOperand(0); 2992 const Value *PtrV = I.getOperand(1); 2993 2994 SmallVector<EVT, 4> ValueVTs; 2995 SmallVector<uint64_t, 4> Offsets; 2996 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 2997 unsigned NumValues = ValueVTs.size(); 2998 if (NumValues == 0) 2999 return; 3000 3001 // Get the lowered operands. Note that we do this after 3002 // checking if NumResults is zero, because with zero results 3003 // the operands won't have values in the map. 3004 SDValue Src = getValue(SrcV); 3005 SDValue Ptr = getValue(PtrV); 3006 3007 SDValue Root = getRoot(); 3008 SmallVector<SDValue, 4> Chains(NumValues); 3009 EVT PtrVT = Ptr.getValueType(); 3010 bool isVolatile = I.isVolatile(); 3011 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3012 unsigned Alignment = I.getAlignment(); 3013 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3014 3015 for (unsigned i = 0; i != NumValues; ++i) { 3016 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3017 DAG.getConstant(Offsets[i], PtrVT)); 3018 Chains[i] = DAG.getStore(Root, getCurDebugLoc(), 3019 SDValue(Src.getNode(), Src.getResNo() + i), 3020 Add, MachinePointerInfo(PtrV, Offsets[i]), 3021 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3022 } 3023 3024 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3025 MVT::Other, &Chains[0], NumValues); 3026 ++SDNodeOrder; 3027 AssignOrderingToNode(StoreNode.getNode()); 3028 DAG.setRoot(StoreNode); 3029} 3030 3031/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3032/// node. 3033void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3034 unsigned Intrinsic) { 3035 bool HasChain = !I.doesNotAccessMemory(); 3036 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3037 3038 // Build the operand list. 3039 SmallVector<SDValue, 8> Ops; 3040 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3041 if (OnlyLoad) { 3042 // We don't need to serialize loads against other loads. 3043 Ops.push_back(DAG.getRoot()); 3044 } else { 3045 Ops.push_back(getRoot()); 3046 } 3047 } 3048 3049 // Info is set by getTgtMemInstrinsic 3050 TargetLowering::IntrinsicInfo Info; 3051 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3052 3053 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3054 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3055 Info.opc == ISD::INTRINSIC_W_CHAIN) 3056 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3057 3058 // Add all operands of the call to the operand list. 3059 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3060 SDValue Op = getValue(I.getArgOperand(i)); 3061 assert(TLI.isTypeLegal(Op.getValueType()) && 3062 "Intrinsic uses a non-legal type?"); 3063 Ops.push_back(Op); 3064 } 3065 3066 SmallVector<EVT, 4> ValueVTs; 3067 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3068#ifndef NDEBUG 3069 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3070 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3071 "Intrinsic uses a non-legal type?"); 3072 } 3073#endif // NDEBUG 3074 3075 if (HasChain) 3076 ValueVTs.push_back(MVT::Other); 3077 3078 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3079 3080 // Create the node. 3081 SDValue Result; 3082 if (IsTgtIntrinsic) { 3083 // This is target intrinsic that touches memory 3084 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3085 VTs, &Ops[0], Ops.size(), 3086 Info.memVT, 3087 MachinePointerInfo(Info.ptrVal, Info.offset), 3088 Info.align, Info.vol, 3089 Info.readMem, Info.writeMem); 3090 } else if (!HasChain) { 3091 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3092 VTs, &Ops[0], Ops.size()); 3093 } else if (!I.getType()->isVoidTy()) { 3094 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3095 VTs, &Ops[0], Ops.size()); 3096 } else { 3097 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3098 VTs, &Ops[0], Ops.size()); 3099 } 3100 3101 if (HasChain) { 3102 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3103 if (OnlyLoad) 3104 PendingLoads.push_back(Chain); 3105 else 3106 DAG.setRoot(Chain); 3107 } 3108 3109 if (!I.getType()->isVoidTy()) { 3110 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3111 EVT VT = TLI.getValueType(PTy); 3112 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result); 3113 } 3114 3115 setValue(&I, Result); 3116 } 3117} 3118 3119/// GetSignificand - Get the significand and build it into a floating-point 3120/// number with exponent of 1: 3121/// 3122/// Op = (Op & 0x007fffff) | 0x3f800000; 3123/// 3124/// where Op is the hexidecimal representation of floating point value. 3125static SDValue 3126GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3127 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3128 DAG.getConstant(0x007fffff, MVT::i32)); 3129 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3130 DAG.getConstant(0x3f800000, MVT::i32)); 3131 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2); 3132} 3133 3134/// GetExponent - Get the exponent: 3135/// 3136/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3137/// 3138/// where Op is the hexidecimal representation of floating point value. 3139static SDValue 3140GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3141 DebugLoc dl) { 3142 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3143 DAG.getConstant(0x7f800000, MVT::i32)); 3144 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3145 DAG.getConstant(23, TLI.getPointerTy())); 3146 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3147 DAG.getConstant(127, MVT::i32)); 3148 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3149} 3150 3151/// getF32Constant - Get 32-bit floating point constant. 3152static SDValue 3153getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3154 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3155} 3156 3157/// Inlined utility function to implement binary input atomic intrinsics for 3158/// visitIntrinsicCall: I is a call instruction 3159/// Op is the associated NodeType for I 3160const char * 3161SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3162 ISD::NodeType Op) { 3163 SDValue Root = getRoot(); 3164 SDValue L = 3165 DAG.getAtomic(Op, getCurDebugLoc(), 3166 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3167 Root, 3168 getValue(I.getArgOperand(0)), 3169 getValue(I.getArgOperand(1)), 3170 I.getArgOperand(0)); 3171 setValue(&I, L); 3172 DAG.setRoot(L.getValue(1)); 3173 return 0; 3174} 3175 3176// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3177const char * 3178SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3179 SDValue Op1 = getValue(I.getArgOperand(0)); 3180 SDValue Op2 = getValue(I.getArgOperand(1)); 3181 3182 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3183 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3184 return 0; 3185} 3186 3187/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3188/// limited-precision mode. 3189void 3190SelectionDAGBuilder::visitExp(const CallInst &I) { 3191 SDValue result; 3192 DebugLoc dl = getCurDebugLoc(); 3193 3194 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3195 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3196 SDValue Op = getValue(I.getArgOperand(0)); 3197 3198 // Put the exponent in the right bit position for later addition to the 3199 // final result: 3200 // 3201 // #define LOG2OFe 1.4426950f 3202 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3203 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3204 getF32Constant(DAG, 0x3fb8aa3b)); 3205 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3206 3207 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3208 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3209 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3210 3211 // IntegerPartOfX <<= 23; 3212 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3213 DAG.getConstant(23, TLI.getPointerTy())); 3214 3215 if (LimitFloatPrecision <= 6) { 3216 // For floating-point precision of 6: 3217 // 3218 // TwoToFractionalPartOfX = 3219 // 0.997535578f + 3220 // (0.735607626f + 0.252464424f * x) * x; 3221 // 3222 // error 0.0144103317, which is 6 bits 3223 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3224 getF32Constant(DAG, 0x3e814304)); 3225 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3226 getF32Constant(DAG, 0x3f3c50c8)); 3227 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3228 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3229 getF32Constant(DAG, 0x3f7f5e7e)); 3230 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5); 3231 3232 // Add the exponent into the result in integer domain. 3233 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3234 TwoToFracPartOfX, IntegerPartOfX); 3235 3236 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6); 3237 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3238 // For floating-point precision of 12: 3239 // 3240 // TwoToFractionalPartOfX = 3241 // 0.999892986f + 3242 // (0.696457318f + 3243 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3244 // 3245 // 0.000107046256 error, which is 13 to 14 bits 3246 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3247 getF32Constant(DAG, 0x3da235e3)); 3248 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3249 getF32Constant(DAG, 0x3e65b8f3)); 3250 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3251 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3252 getF32Constant(DAG, 0x3f324b07)); 3253 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3254 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3255 getF32Constant(DAG, 0x3f7ff8fd)); 3256 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7); 3257 3258 // Add the exponent into the result in integer domain. 3259 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3260 TwoToFracPartOfX, IntegerPartOfX); 3261 3262 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8); 3263 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3264 // For floating-point precision of 18: 3265 // 3266 // TwoToFractionalPartOfX = 3267 // 0.999999982f + 3268 // (0.693148872f + 3269 // (0.240227044f + 3270 // (0.554906021e-1f + 3271 // (0.961591928e-2f + 3272 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3273 // 3274 // error 2.47208000*10^(-7), which is better than 18 bits 3275 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3276 getF32Constant(DAG, 0x3924b03e)); 3277 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3278 getF32Constant(DAG, 0x3ab24b87)); 3279 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3280 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3281 getF32Constant(DAG, 0x3c1d8c17)); 3282 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3283 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3284 getF32Constant(DAG, 0x3d634a1d)); 3285 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3286 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3287 getF32Constant(DAG, 0x3e75fe14)); 3288 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3289 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3290 getF32Constant(DAG, 0x3f317234)); 3291 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3292 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3293 getF32Constant(DAG, 0x3f800000)); 3294 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl, 3295 MVT::i32, t13); 3296 3297 // Add the exponent into the result in integer domain. 3298 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3299 TwoToFracPartOfX, IntegerPartOfX); 3300 3301 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14); 3302 } 3303 } else { 3304 // No special expansion. 3305 result = DAG.getNode(ISD::FEXP, dl, 3306 getValue(I.getArgOperand(0)).getValueType(), 3307 getValue(I.getArgOperand(0))); 3308 } 3309 3310 setValue(&I, result); 3311} 3312 3313/// visitLog - Lower a log intrinsic. Handles the special sequences for 3314/// limited-precision mode. 3315void 3316SelectionDAGBuilder::visitLog(const CallInst &I) { 3317 SDValue result; 3318 DebugLoc dl = getCurDebugLoc(); 3319 3320 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3321 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3322 SDValue Op = getValue(I.getArgOperand(0)); 3323 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3324 3325 // Scale the exponent by log(2) [0.69314718f]. 3326 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3327 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3328 getF32Constant(DAG, 0x3f317218)); 3329 3330 // Get the significand and build it into a floating-point number with 3331 // exponent of 1. 3332 SDValue X = GetSignificand(DAG, Op1, dl); 3333 3334 if (LimitFloatPrecision <= 6) { 3335 // For floating-point precision of 6: 3336 // 3337 // LogofMantissa = 3338 // -1.1609546f + 3339 // (1.4034025f - 0.23903021f * x) * x; 3340 // 3341 // error 0.0034276066, which is better than 8 bits 3342 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3343 getF32Constant(DAG, 0xbe74c456)); 3344 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3345 getF32Constant(DAG, 0x3fb3a2b1)); 3346 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3347 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3348 getF32Constant(DAG, 0x3f949a29)); 3349 3350 result = DAG.getNode(ISD::FADD, dl, 3351 MVT::f32, LogOfExponent, LogOfMantissa); 3352 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3353 // For floating-point precision of 12: 3354 // 3355 // LogOfMantissa = 3356 // -1.7417939f + 3357 // (2.8212026f + 3358 // (-1.4699568f + 3359 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3360 // 3361 // error 0.000061011436, which is 14 bits 3362 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3363 getF32Constant(DAG, 0xbd67b6d6)); 3364 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3365 getF32Constant(DAG, 0x3ee4f4b8)); 3366 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3367 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3368 getF32Constant(DAG, 0x3fbc278b)); 3369 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3370 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3371 getF32Constant(DAG, 0x40348e95)); 3372 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3373 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3374 getF32Constant(DAG, 0x3fdef31a)); 3375 3376 result = DAG.getNode(ISD::FADD, dl, 3377 MVT::f32, LogOfExponent, LogOfMantissa); 3378 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3379 // For floating-point precision of 18: 3380 // 3381 // LogOfMantissa = 3382 // -2.1072184f + 3383 // (4.2372794f + 3384 // (-3.7029485f + 3385 // (2.2781945f + 3386 // (-0.87823314f + 3387 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3388 // 3389 // error 0.0000023660568, which is better than 18 bits 3390 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3391 getF32Constant(DAG, 0xbc91e5ac)); 3392 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3393 getF32Constant(DAG, 0x3e4350aa)); 3394 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3395 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3396 getF32Constant(DAG, 0x3f60d3e3)); 3397 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3398 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3399 getF32Constant(DAG, 0x4011cdf0)); 3400 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3401 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3402 getF32Constant(DAG, 0x406cfd1c)); 3403 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3404 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3405 getF32Constant(DAG, 0x408797cb)); 3406 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3407 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3408 getF32Constant(DAG, 0x4006dcab)); 3409 3410 result = DAG.getNode(ISD::FADD, dl, 3411 MVT::f32, LogOfExponent, LogOfMantissa); 3412 } 3413 } else { 3414 // No special expansion. 3415 result = DAG.getNode(ISD::FLOG, dl, 3416 getValue(I.getArgOperand(0)).getValueType(), 3417 getValue(I.getArgOperand(0))); 3418 } 3419 3420 setValue(&I, result); 3421} 3422 3423/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3424/// limited-precision mode. 3425void 3426SelectionDAGBuilder::visitLog2(const CallInst &I) { 3427 SDValue result; 3428 DebugLoc dl = getCurDebugLoc(); 3429 3430 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3431 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3432 SDValue Op = getValue(I.getArgOperand(0)); 3433 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3434 3435 // Get the exponent. 3436 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3437 3438 // Get the significand and build it into a floating-point number with 3439 // exponent of 1. 3440 SDValue X = GetSignificand(DAG, Op1, dl); 3441 3442 // Different possible minimax approximations of significand in 3443 // floating-point for various degrees of accuracy over [1,2]. 3444 if (LimitFloatPrecision <= 6) { 3445 // For floating-point precision of 6: 3446 // 3447 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3448 // 3449 // error 0.0049451742, which is more than 7 bits 3450 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3451 getF32Constant(DAG, 0xbeb08fe0)); 3452 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3453 getF32Constant(DAG, 0x40019463)); 3454 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3455 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3456 getF32Constant(DAG, 0x3fd6633d)); 3457 3458 result = DAG.getNode(ISD::FADD, dl, 3459 MVT::f32, LogOfExponent, Log2ofMantissa); 3460 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3461 // For floating-point precision of 12: 3462 // 3463 // Log2ofMantissa = 3464 // -2.51285454f + 3465 // (4.07009056f + 3466 // (-2.12067489f + 3467 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3468 // 3469 // error 0.0000876136000, which is better than 13 bits 3470 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3471 getF32Constant(DAG, 0xbda7262e)); 3472 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3473 getF32Constant(DAG, 0x3f25280b)); 3474 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3475 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3476 getF32Constant(DAG, 0x4007b923)); 3477 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3478 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3479 getF32Constant(DAG, 0x40823e2f)); 3480 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3481 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3482 getF32Constant(DAG, 0x4020d29c)); 3483 3484 result = DAG.getNode(ISD::FADD, dl, 3485 MVT::f32, LogOfExponent, Log2ofMantissa); 3486 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3487 // For floating-point precision of 18: 3488 // 3489 // Log2ofMantissa = 3490 // -3.0400495f + 3491 // (6.1129976f + 3492 // (-5.3420409f + 3493 // (3.2865683f + 3494 // (-1.2669343f + 3495 // (0.27515199f - 3496 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3497 // 3498 // error 0.0000018516, which is better than 18 bits 3499 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3500 getF32Constant(DAG, 0xbcd2769e)); 3501 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3502 getF32Constant(DAG, 0x3e8ce0b9)); 3503 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3504 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3505 getF32Constant(DAG, 0x3fa22ae7)); 3506 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3507 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3508 getF32Constant(DAG, 0x40525723)); 3509 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3510 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3511 getF32Constant(DAG, 0x40aaf200)); 3512 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3513 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3514 getF32Constant(DAG, 0x40c39dad)); 3515 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3516 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3517 getF32Constant(DAG, 0x4042902c)); 3518 3519 result = DAG.getNode(ISD::FADD, dl, 3520 MVT::f32, LogOfExponent, Log2ofMantissa); 3521 } 3522 } else { 3523 // No special expansion. 3524 result = DAG.getNode(ISD::FLOG2, dl, 3525 getValue(I.getArgOperand(0)).getValueType(), 3526 getValue(I.getArgOperand(0))); 3527 } 3528 3529 setValue(&I, result); 3530} 3531 3532/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3533/// limited-precision mode. 3534void 3535SelectionDAGBuilder::visitLog10(const CallInst &I) { 3536 SDValue result; 3537 DebugLoc dl = getCurDebugLoc(); 3538 3539 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3540 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3541 SDValue Op = getValue(I.getArgOperand(0)); 3542 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3543 3544 // Scale the exponent by log10(2) [0.30102999f]. 3545 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3546 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3547 getF32Constant(DAG, 0x3e9a209a)); 3548 3549 // Get the significand and build it into a floating-point number with 3550 // exponent of 1. 3551 SDValue X = GetSignificand(DAG, Op1, dl); 3552 3553 if (LimitFloatPrecision <= 6) { 3554 // For floating-point precision of 6: 3555 // 3556 // Log10ofMantissa = 3557 // -0.50419619f + 3558 // (0.60948995f - 0.10380950f * x) * x; 3559 // 3560 // error 0.0014886165, which is 6 bits 3561 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3562 getF32Constant(DAG, 0xbdd49a13)); 3563 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3564 getF32Constant(DAG, 0x3f1c0789)); 3565 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3566 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3567 getF32Constant(DAG, 0x3f011300)); 3568 3569 result = DAG.getNode(ISD::FADD, dl, 3570 MVT::f32, LogOfExponent, Log10ofMantissa); 3571 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3572 // For floating-point precision of 12: 3573 // 3574 // Log10ofMantissa = 3575 // -0.64831180f + 3576 // (0.91751397f + 3577 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3578 // 3579 // error 0.00019228036, which is better than 12 bits 3580 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3581 getF32Constant(DAG, 0x3d431f31)); 3582 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3583 getF32Constant(DAG, 0x3ea21fb2)); 3584 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3585 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3586 getF32Constant(DAG, 0x3f6ae232)); 3587 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3588 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3589 getF32Constant(DAG, 0x3f25f7c3)); 3590 3591 result = DAG.getNode(ISD::FADD, dl, 3592 MVT::f32, LogOfExponent, Log10ofMantissa); 3593 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3594 // For floating-point precision of 18: 3595 // 3596 // Log10ofMantissa = 3597 // -0.84299375f + 3598 // (1.5327582f + 3599 // (-1.0688956f + 3600 // (0.49102474f + 3601 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3602 // 3603 // error 0.0000037995730, which is better than 18 bits 3604 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3605 getF32Constant(DAG, 0x3c5d51ce)); 3606 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3607 getF32Constant(DAG, 0x3e00685a)); 3608 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3609 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3610 getF32Constant(DAG, 0x3efb6798)); 3611 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3612 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3613 getF32Constant(DAG, 0x3f88d192)); 3614 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3615 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3616 getF32Constant(DAG, 0x3fc4316c)); 3617 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3618 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3619 getF32Constant(DAG, 0x3f57ce70)); 3620 3621 result = DAG.getNode(ISD::FADD, dl, 3622 MVT::f32, LogOfExponent, Log10ofMantissa); 3623 } 3624 } else { 3625 // No special expansion. 3626 result = DAG.getNode(ISD::FLOG10, dl, 3627 getValue(I.getArgOperand(0)).getValueType(), 3628 getValue(I.getArgOperand(0))); 3629 } 3630 3631 setValue(&I, result); 3632} 3633 3634/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3635/// limited-precision mode. 3636void 3637SelectionDAGBuilder::visitExp2(const CallInst &I) { 3638 SDValue result; 3639 DebugLoc dl = getCurDebugLoc(); 3640 3641 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3642 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3643 SDValue Op = getValue(I.getArgOperand(0)); 3644 3645 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3646 3647 // FractionalPartOfX = x - (float)IntegerPartOfX; 3648 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3649 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3650 3651 // IntegerPartOfX <<= 23; 3652 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3653 DAG.getConstant(23, TLI.getPointerTy())); 3654 3655 if (LimitFloatPrecision <= 6) { 3656 // For floating-point precision of 6: 3657 // 3658 // TwoToFractionalPartOfX = 3659 // 0.997535578f + 3660 // (0.735607626f + 0.252464424f * x) * x; 3661 // 3662 // error 0.0144103317, which is 6 bits 3663 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3664 getF32Constant(DAG, 0x3e814304)); 3665 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3666 getF32Constant(DAG, 0x3f3c50c8)); 3667 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3668 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3669 getF32Constant(DAG, 0x3f7f5e7e)); 3670 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3671 SDValue TwoToFractionalPartOfX = 3672 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3673 3674 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3675 MVT::f32, TwoToFractionalPartOfX); 3676 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3677 // For floating-point precision of 12: 3678 // 3679 // TwoToFractionalPartOfX = 3680 // 0.999892986f + 3681 // (0.696457318f + 3682 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3683 // 3684 // error 0.000107046256, which is 13 to 14 bits 3685 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3686 getF32Constant(DAG, 0x3da235e3)); 3687 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3688 getF32Constant(DAG, 0x3e65b8f3)); 3689 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3690 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3691 getF32Constant(DAG, 0x3f324b07)); 3692 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3693 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3694 getF32Constant(DAG, 0x3f7ff8fd)); 3695 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3696 SDValue TwoToFractionalPartOfX = 3697 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3698 3699 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3700 MVT::f32, TwoToFractionalPartOfX); 3701 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3702 // For floating-point precision of 18: 3703 // 3704 // TwoToFractionalPartOfX = 3705 // 0.999999982f + 3706 // (0.693148872f + 3707 // (0.240227044f + 3708 // (0.554906021e-1f + 3709 // (0.961591928e-2f + 3710 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3711 // error 2.47208000*10^(-7), which is better than 18 bits 3712 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3713 getF32Constant(DAG, 0x3924b03e)); 3714 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3715 getF32Constant(DAG, 0x3ab24b87)); 3716 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3717 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3718 getF32Constant(DAG, 0x3c1d8c17)); 3719 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3720 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3721 getF32Constant(DAG, 0x3d634a1d)); 3722 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3723 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3724 getF32Constant(DAG, 0x3e75fe14)); 3725 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3726 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3727 getF32Constant(DAG, 0x3f317234)); 3728 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3729 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3730 getF32Constant(DAG, 0x3f800000)); 3731 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3732 SDValue TwoToFractionalPartOfX = 3733 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3734 3735 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3736 MVT::f32, TwoToFractionalPartOfX); 3737 } 3738 } else { 3739 // No special expansion. 3740 result = DAG.getNode(ISD::FEXP2, dl, 3741 getValue(I.getArgOperand(0)).getValueType(), 3742 getValue(I.getArgOperand(0))); 3743 } 3744 3745 setValue(&I, result); 3746} 3747 3748/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3749/// limited-precision mode with x == 10.0f. 3750void 3751SelectionDAGBuilder::visitPow(const CallInst &I) { 3752 SDValue result; 3753 const Value *Val = I.getArgOperand(0); 3754 DebugLoc dl = getCurDebugLoc(); 3755 bool IsExp10 = false; 3756 3757 if (getValue(Val).getValueType() == MVT::f32 && 3758 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 3759 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3760 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3761 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3762 APFloat Ten(10.0f); 3763 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3764 } 3765 } 3766 } 3767 3768 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3769 SDValue Op = getValue(I.getArgOperand(1)); 3770 3771 // Put the exponent in the right bit position for later addition to the 3772 // final result: 3773 // 3774 // #define LOG2OF10 3.3219281f 3775 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3776 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3777 getF32Constant(DAG, 0x40549a78)); 3778 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3779 3780 // FractionalPartOfX = x - (float)IntegerPartOfX; 3781 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3782 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3783 3784 // IntegerPartOfX <<= 23; 3785 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3786 DAG.getConstant(23, TLI.getPointerTy())); 3787 3788 if (LimitFloatPrecision <= 6) { 3789 // For floating-point precision of 6: 3790 // 3791 // twoToFractionalPartOfX = 3792 // 0.997535578f + 3793 // (0.735607626f + 0.252464424f * x) * x; 3794 // 3795 // error 0.0144103317, which is 6 bits 3796 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3797 getF32Constant(DAG, 0x3e814304)); 3798 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3799 getF32Constant(DAG, 0x3f3c50c8)); 3800 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3801 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3802 getF32Constant(DAG, 0x3f7f5e7e)); 3803 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3804 SDValue TwoToFractionalPartOfX = 3805 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3806 3807 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3808 MVT::f32, TwoToFractionalPartOfX); 3809 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3810 // For floating-point precision of 12: 3811 // 3812 // TwoToFractionalPartOfX = 3813 // 0.999892986f + 3814 // (0.696457318f + 3815 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3816 // 3817 // error 0.000107046256, which is 13 to 14 bits 3818 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3819 getF32Constant(DAG, 0x3da235e3)); 3820 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3821 getF32Constant(DAG, 0x3e65b8f3)); 3822 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3823 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3824 getF32Constant(DAG, 0x3f324b07)); 3825 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3826 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3827 getF32Constant(DAG, 0x3f7ff8fd)); 3828 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3829 SDValue TwoToFractionalPartOfX = 3830 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3831 3832 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3833 MVT::f32, TwoToFractionalPartOfX); 3834 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3835 // For floating-point precision of 18: 3836 // 3837 // TwoToFractionalPartOfX = 3838 // 0.999999982f + 3839 // (0.693148872f + 3840 // (0.240227044f + 3841 // (0.554906021e-1f + 3842 // (0.961591928e-2f + 3843 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3844 // error 2.47208000*10^(-7), which is better than 18 bits 3845 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3846 getF32Constant(DAG, 0x3924b03e)); 3847 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3848 getF32Constant(DAG, 0x3ab24b87)); 3849 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3850 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3851 getF32Constant(DAG, 0x3c1d8c17)); 3852 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3853 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3854 getF32Constant(DAG, 0x3d634a1d)); 3855 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3856 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3857 getF32Constant(DAG, 0x3e75fe14)); 3858 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3859 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3860 getF32Constant(DAG, 0x3f317234)); 3861 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3862 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3863 getF32Constant(DAG, 0x3f800000)); 3864 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3865 SDValue TwoToFractionalPartOfX = 3866 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3867 3868 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3869 MVT::f32, TwoToFractionalPartOfX); 3870 } 3871 } else { 3872 // No special expansion. 3873 result = DAG.getNode(ISD::FPOW, dl, 3874 getValue(I.getArgOperand(0)).getValueType(), 3875 getValue(I.getArgOperand(0)), 3876 getValue(I.getArgOperand(1))); 3877 } 3878 3879 setValue(&I, result); 3880} 3881 3882 3883/// ExpandPowI - Expand a llvm.powi intrinsic. 3884static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 3885 SelectionDAG &DAG) { 3886 // If RHS is a constant, we can expand this out to a multiplication tree, 3887 // otherwise we end up lowering to a call to __powidf2 (for example). When 3888 // optimizing for size, we only want to do this if the expansion would produce 3889 // a small number of multiplies, otherwise we do the full expansion. 3890 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3891 // Get the exponent as a positive value. 3892 unsigned Val = RHSC->getSExtValue(); 3893 if ((int)Val < 0) Val = -Val; 3894 3895 // powi(x, 0) -> 1.0 3896 if (Val == 0) 3897 return DAG.getConstantFP(1.0, LHS.getValueType()); 3898 3899 const Function *F = DAG.getMachineFunction().getFunction(); 3900 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 3901 // If optimizing for size, don't insert too many multiplies. This 3902 // inserts up to 5 multiplies. 3903 CountPopulation_32(Val)+Log2_32(Val) < 7) { 3904 // We use the simple binary decomposition method to generate the multiply 3905 // sequence. There are more optimal ways to do this (for example, 3906 // powi(x,15) generates one more multiply than it should), but this has 3907 // the benefit of being both really simple and much better than a libcall. 3908 SDValue Res; // Logically starts equal to 1.0 3909 SDValue CurSquare = LHS; 3910 while (Val) { 3911 if (Val & 1) { 3912 if (Res.getNode()) 3913 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 3914 else 3915 Res = CurSquare; // 1.0*CurSquare. 3916 } 3917 3918 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 3919 CurSquare, CurSquare); 3920 Val >>= 1; 3921 } 3922 3923 // If the original was negative, invert the result, producing 1/(x*x*x). 3924 if (RHSC->getSExtValue() < 0) 3925 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 3926 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 3927 return Res; 3928 } 3929 } 3930 3931 // Otherwise, expand to a libcall. 3932 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 3933} 3934 3935/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 3936/// argument, create the corresponding DBG_VALUE machine instruction for it now. 3937/// At the end of instruction selection, they will be inserted to the entry BB. 3938bool 3939SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 3940 int64_t Offset, 3941 const SDValue &N) { 3942 const Argument *Arg = dyn_cast<Argument>(V); 3943 if (!Arg) 3944 return false; 3945 3946 MachineFunction &MF = DAG.getMachineFunction(); 3947 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 3948 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 3949 3950 // Ignore inlined function arguments here. 3951 DIVariable DV(Variable); 3952 if (DV.isInlinedFnArgument(MF.getFunction())) 3953 return false; 3954 3955 MachineBasicBlock *MBB = FuncInfo.MBB; 3956 if (MBB != &MF.front()) 3957 return false; 3958 3959 unsigned Reg = 0; 3960 if (Arg->hasByValAttr()) { 3961 // Byval arguments' frame index is recorded during argument lowering. 3962 // Use this info directly. 3963 Reg = TRI->getFrameRegister(MF); 3964 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 3965 // If byval argument ofset is not recorded then ignore this. 3966 if (!Offset) 3967 Reg = 0; 3968 } 3969 3970 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) { 3971 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 3972 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 3973 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 3974 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 3975 if (PR) 3976 Reg = PR; 3977 } 3978 } 3979 3980 if (!Reg) { 3981 // Check if ValueMap has reg number. 3982 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 3983 if (VMI != FuncInfo.ValueMap.end()) 3984 Reg = VMI->second; 3985 } 3986 3987 if (!Reg && N.getNode()) { 3988 // Check if frame index is available. 3989 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 3990 if (FrameIndexSDNode *FINode = 3991 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 3992 Reg = TRI->getFrameRegister(MF); 3993 Offset = FINode->getIndex(); 3994 } 3995 } 3996 3997 if (!Reg) 3998 return false; 3999 4000 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4001 TII->get(TargetOpcode::DBG_VALUE)) 4002 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4003 FuncInfo.ArgDbgValues.push_back(&*MIB); 4004 return true; 4005} 4006 4007// VisualStudio defines setjmp as _setjmp 4008#if defined(_MSC_VER) && defined(setjmp) && \ 4009 !defined(setjmp_undefined_for_msvc) 4010# pragma push_macro("setjmp") 4011# undef setjmp 4012# define setjmp_undefined_for_msvc 4013#endif 4014 4015/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4016/// we want to emit this as a call to a named external function, return the name 4017/// otherwise lower it and return null. 4018const char * 4019SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4020 DebugLoc dl = getCurDebugLoc(); 4021 SDValue Res; 4022 4023 switch (Intrinsic) { 4024 default: 4025 // By default, turn this into a target intrinsic node. 4026 visitTargetIntrinsic(I, Intrinsic); 4027 return 0; 4028 case Intrinsic::vastart: visitVAStart(I); return 0; 4029 case Intrinsic::vaend: visitVAEnd(I); return 0; 4030 case Intrinsic::vacopy: visitVACopy(I); return 0; 4031 case Intrinsic::returnaddress: 4032 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4033 getValue(I.getArgOperand(0)))); 4034 return 0; 4035 case Intrinsic::frameaddress: 4036 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4037 getValue(I.getArgOperand(0)))); 4038 return 0; 4039 case Intrinsic::setjmp: 4040 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4041 case Intrinsic::longjmp: 4042 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4043 case Intrinsic::memcpy: { 4044 // Assert for address < 256 since we support only user defined address 4045 // spaces. 4046 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4047 < 256 && 4048 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4049 < 256 && 4050 "Unknown address space"); 4051 SDValue Op1 = getValue(I.getArgOperand(0)); 4052 SDValue Op2 = getValue(I.getArgOperand(1)); 4053 SDValue Op3 = getValue(I.getArgOperand(2)); 4054 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4055 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4056 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4057 MachinePointerInfo(I.getArgOperand(0)), 4058 MachinePointerInfo(I.getArgOperand(1)))); 4059 return 0; 4060 } 4061 case Intrinsic::memset: { 4062 // Assert for address < 256 since we support only user defined address 4063 // spaces. 4064 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4065 < 256 && 4066 "Unknown address space"); 4067 SDValue Op1 = getValue(I.getArgOperand(0)); 4068 SDValue Op2 = getValue(I.getArgOperand(1)); 4069 SDValue Op3 = getValue(I.getArgOperand(2)); 4070 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4071 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4072 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4073 MachinePointerInfo(I.getArgOperand(0)))); 4074 return 0; 4075 } 4076 case Intrinsic::memmove: { 4077 // Assert for address < 256 since we support only user defined address 4078 // spaces. 4079 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4080 < 256 && 4081 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4082 < 256 && 4083 "Unknown address space"); 4084 SDValue Op1 = getValue(I.getArgOperand(0)); 4085 SDValue Op2 = getValue(I.getArgOperand(1)); 4086 SDValue Op3 = getValue(I.getArgOperand(2)); 4087 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4088 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4089 4090 // If the source and destination are known to not be aliases, we can 4091 // lower memmove as memcpy. 4092 uint64_t Size = -1ULL; 4093 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 4094 Size = C->getZExtValue(); 4095 if (AA->alias(I.getArgOperand(0), Size, I.getArgOperand(1), Size) == 4096 AliasAnalysis::NoAlias) { 4097 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4098 false, MachinePointerInfo(I.getArgOperand(0)), 4099 MachinePointerInfo(I.getArgOperand(1)))); 4100 return 0; 4101 } 4102 4103 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4104 MachinePointerInfo(I.getArgOperand(0)), 4105 MachinePointerInfo(I.getArgOperand(1)))); 4106 return 0; 4107 } 4108 case Intrinsic::dbg_declare: { 4109 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4110 MDNode *Variable = DI.getVariable(); 4111 const Value *Address = DI.getAddress(); 4112 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4113 return 0; 4114 4115 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4116 // but do not always have a corresponding SDNode built. The SDNodeOrder 4117 // absolute, but not relative, values are different depending on whether 4118 // debug info exists. 4119 ++SDNodeOrder; 4120 4121 // Check if address has undef value. 4122 if (isa<UndefValue>(Address) || 4123 (Address->use_empty() && !isa<Argument>(Address))) { 4124 SDDbgValue*SDV = 4125 DAG.getDbgValue(Variable, UndefValue::get(Address->getType()), 4126 0, dl, SDNodeOrder); 4127 DAG.AddDbgValue(SDV, 0, false); 4128 return 0; 4129 } 4130 4131 SDValue &N = NodeMap[Address]; 4132 if (!N.getNode() && isa<Argument>(Address)) 4133 // Check unused arguments map. 4134 N = UnusedArgNodeMap[Address]; 4135 SDDbgValue *SDV; 4136 if (N.getNode()) { 4137 // Parameters are handled specially. 4138 bool isParameter = 4139 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4140 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4141 Address = BCI->getOperand(0); 4142 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4143 4144 if (isParameter && !AI) { 4145 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4146 if (FINode) 4147 // Byval parameter. We have a frame index at this point. 4148 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4149 0, dl, SDNodeOrder); 4150 else 4151 // Can't do anything with other non-AI cases yet. This might be a 4152 // parameter of a callee function that got inlined, for example. 4153 return 0; 4154 } else if (AI) 4155 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4156 0, dl, SDNodeOrder); 4157 else 4158 // Can't do anything with other non-AI cases yet. 4159 return 0; 4160 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4161 } else { 4162 // If Address is an argument then try to emit its dbg value using 4163 // virtual register info from the FuncInfo.ValueMap. 4164 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4165 // If variable is pinned by a alloca in dominating bb then 4166 // use StaticAllocaMap. 4167 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4168 if (AI->getParent() != DI.getParent()) { 4169 DenseMap<const AllocaInst*, int>::iterator SI = 4170 FuncInfo.StaticAllocaMap.find(AI); 4171 if (SI != FuncInfo.StaticAllocaMap.end()) { 4172 SDV = DAG.getDbgValue(Variable, SI->second, 4173 0, dl, SDNodeOrder); 4174 DAG.AddDbgValue(SDV, 0, false); 4175 return 0; 4176 } 4177 } 4178 } 4179 // Otherwise add undef to help track missing debug info. 4180 SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()), 4181 0, dl, SDNodeOrder); 4182 DAG.AddDbgValue(SDV, 0, false); 4183 } 4184 } 4185 return 0; 4186 } 4187 case Intrinsic::dbg_value: { 4188 const DbgValueInst &DI = cast<DbgValueInst>(I); 4189 if (!DIVariable(DI.getVariable()).Verify()) 4190 return 0; 4191 4192 MDNode *Variable = DI.getVariable(); 4193 uint64_t Offset = DI.getOffset(); 4194 const Value *V = DI.getValue(); 4195 if (!V) 4196 return 0; 4197 4198 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4199 // but do not always have a corresponding SDNode built. The SDNodeOrder 4200 // absolute, but not relative, values are different depending on whether 4201 // debug info exists. 4202 ++SDNodeOrder; 4203 SDDbgValue *SDV; 4204 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4205 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4206 DAG.AddDbgValue(SDV, 0, false); 4207 } else { 4208 // Do not use getValue() in here; we don't want to generate code at 4209 // this point if it hasn't been done yet. 4210 SDValue N = NodeMap[V]; 4211 if (!N.getNode() && isa<Argument>(V)) 4212 // Check unused arguments map. 4213 N = UnusedArgNodeMap[V]; 4214 if (N.getNode()) { 4215 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4216 SDV = DAG.getDbgValue(Variable, N.getNode(), 4217 N.getResNo(), Offset, dl, SDNodeOrder); 4218 DAG.AddDbgValue(SDV, N.getNode(), false); 4219 } 4220 } else if (isa<PHINode>(V) && !V->use_empty() ) { 4221 // Do not call getValue(V) yet, as we don't want to generate code. 4222 // Remember it for later. 4223 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4224 DanglingDebugInfoMap[V] = DDI; 4225 } else { 4226 // We may expand this to cover more cases. One case where we have no 4227 // data available is an unreferenced parameter; we need this fallback. 4228 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()), 4229 Offset, dl, SDNodeOrder); 4230 DAG.AddDbgValue(SDV, 0, false); 4231 } 4232 } 4233 4234 // Build a debug info table entry. 4235 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4236 V = BCI->getOperand(0); 4237 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4238 // Don't handle byval struct arguments or VLAs, for example. 4239 if (!AI) 4240 return 0; 4241 DenseMap<const AllocaInst*, int>::iterator SI = 4242 FuncInfo.StaticAllocaMap.find(AI); 4243 if (SI == FuncInfo.StaticAllocaMap.end()) 4244 return 0; // VLAs. 4245 int FI = SI->second; 4246 4247 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4248 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4249 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4250 return 0; 4251 } 4252 case Intrinsic::eh_exception: { 4253 // Insert the EXCEPTIONADDR instruction. 4254 assert(FuncInfo.MBB->isLandingPad() && 4255 "Call to eh.exception not in landing pad!"); 4256 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4257 SDValue Ops[1]; 4258 Ops[0] = DAG.getRoot(); 4259 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4260 setValue(&I, Op); 4261 DAG.setRoot(Op.getValue(1)); 4262 return 0; 4263 } 4264 4265 case Intrinsic::eh_selector: { 4266 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4267 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4268 if (CallMBB->isLandingPad()) 4269 AddCatchInfo(I, &MMI, CallMBB); 4270 else { 4271#ifndef NDEBUG 4272 FuncInfo.CatchInfoLost.insert(&I); 4273#endif 4274 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4275 unsigned Reg = TLI.getExceptionSelectorRegister(); 4276 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4277 } 4278 4279 // Insert the EHSELECTION instruction. 4280 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4281 SDValue Ops[2]; 4282 Ops[0] = getValue(I.getArgOperand(0)); 4283 Ops[1] = getRoot(); 4284 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4285 DAG.setRoot(Op.getValue(1)); 4286 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4287 return 0; 4288 } 4289 4290 case Intrinsic::eh_typeid_for: { 4291 // Find the type id for the given typeinfo. 4292 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4293 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4294 Res = DAG.getConstant(TypeID, MVT::i32); 4295 setValue(&I, Res); 4296 return 0; 4297 } 4298 4299 case Intrinsic::eh_return_i32: 4300 case Intrinsic::eh_return_i64: 4301 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4302 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4303 MVT::Other, 4304 getControlRoot(), 4305 getValue(I.getArgOperand(0)), 4306 getValue(I.getArgOperand(1)))); 4307 return 0; 4308 case Intrinsic::eh_unwind_init: 4309 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4310 return 0; 4311 case Intrinsic::eh_dwarf_cfa: { 4312 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4313 TLI.getPointerTy()); 4314 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4315 TLI.getPointerTy(), 4316 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4317 TLI.getPointerTy()), 4318 CfaArg); 4319 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4320 TLI.getPointerTy(), 4321 DAG.getConstant(0, TLI.getPointerTy())); 4322 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4323 FA, Offset)); 4324 return 0; 4325 } 4326 case Intrinsic::eh_sjlj_callsite: { 4327 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4328 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4329 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4330 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4331 4332 MMI.setCurrentCallSite(CI->getZExtValue()); 4333 return 0; 4334 } 4335 case Intrinsic::eh_sjlj_setjmp: { 4336 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4337 getValue(I.getArgOperand(0)))); 4338 return 0; 4339 } 4340 case Intrinsic::eh_sjlj_longjmp: { 4341 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4342 getRoot(), getValue(I.getArgOperand(0)))); 4343 return 0; 4344 } 4345 case Intrinsic::eh_sjlj_dispatch_setup: { 4346 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4347 getRoot(), getValue(I.getArgOperand(0)))); 4348 return 0; 4349 } 4350 4351 case Intrinsic::x86_mmx_pslli_w: 4352 case Intrinsic::x86_mmx_pslli_d: 4353 case Intrinsic::x86_mmx_pslli_q: 4354 case Intrinsic::x86_mmx_psrli_w: 4355 case Intrinsic::x86_mmx_psrli_d: 4356 case Intrinsic::x86_mmx_psrli_q: 4357 case Intrinsic::x86_mmx_psrai_w: 4358 case Intrinsic::x86_mmx_psrai_d: { 4359 SDValue ShAmt = getValue(I.getArgOperand(1)); 4360 if (isa<ConstantSDNode>(ShAmt)) { 4361 visitTargetIntrinsic(I, Intrinsic); 4362 return 0; 4363 } 4364 unsigned NewIntrinsic = 0; 4365 EVT ShAmtVT = MVT::v2i32; 4366 switch (Intrinsic) { 4367 case Intrinsic::x86_mmx_pslli_w: 4368 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4369 break; 4370 case Intrinsic::x86_mmx_pslli_d: 4371 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4372 break; 4373 case Intrinsic::x86_mmx_pslli_q: 4374 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4375 break; 4376 case Intrinsic::x86_mmx_psrli_w: 4377 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4378 break; 4379 case Intrinsic::x86_mmx_psrli_d: 4380 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4381 break; 4382 case Intrinsic::x86_mmx_psrli_q: 4383 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4384 break; 4385 case Intrinsic::x86_mmx_psrai_w: 4386 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4387 break; 4388 case Intrinsic::x86_mmx_psrai_d: 4389 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4390 break; 4391 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4392 } 4393 4394 // The vector shift intrinsics with scalars uses 32b shift amounts but 4395 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4396 // to be zero. 4397 // We must do this early because v2i32 is not a legal type. 4398 DebugLoc dl = getCurDebugLoc(); 4399 SDValue ShOps[2]; 4400 ShOps[0] = ShAmt; 4401 ShOps[1] = DAG.getConstant(0, MVT::i32); 4402 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4403 EVT DestVT = TLI.getValueType(I.getType()); 4404 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, DestVT, ShAmt); 4405 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4406 DAG.getConstant(NewIntrinsic, MVT::i32), 4407 getValue(I.getArgOperand(0)), ShAmt); 4408 setValue(&I, Res); 4409 return 0; 4410 } 4411 case Intrinsic::convertff: 4412 case Intrinsic::convertfsi: 4413 case Intrinsic::convertfui: 4414 case Intrinsic::convertsif: 4415 case Intrinsic::convertuif: 4416 case Intrinsic::convertss: 4417 case Intrinsic::convertsu: 4418 case Intrinsic::convertus: 4419 case Intrinsic::convertuu: { 4420 ISD::CvtCode Code = ISD::CVT_INVALID; 4421 switch (Intrinsic) { 4422 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4423 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4424 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4425 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4426 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4427 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4428 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4429 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4430 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4431 } 4432 EVT DestVT = TLI.getValueType(I.getType()); 4433 const Value *Op1 = I.getArgOperand(0); 4434 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4435 DAG.getValueType(DestVT), 4436 DAG.getValueType(getValue(Op1).getValueType()), 4437 getValue(I.getArgOperand(1)), 4438 getValue(I.getArgOperand(2)), 4439 Code); 4440 setValue(&I, Res); 4441 return 0; 4442 } 4443 case Intrinsic::sqrt: 4444 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4445 getValue(I.getArgOperand(0)).getValueType(), 4446 getValue(I.getArgOperand(0)))); 4447 return 0; 4448 case Intrinsic::powi: 4449 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4450 getValue(I.getArgOperand(1)), DAG)); 4451 return 0; 4452 case Intrinsic::sin: 4453 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4454 getValue(I.getArgOperand(0)).getValueType(), 4455 getValue(I.getArgOperand(0)))); 4456 return 0; 4457 case Intrinsic::cos: 4458 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4459 getValue(I.getArgOperand(0)).getValueType(), 4460 getValue(I.getArgOperand(0)))); 4461 return 0; 4462 case Intrinsic::log: 4463 visitLog(I); 4464 return 0; 4465 case Intrinsic::log2: 4466 visitLog2(I); 4467 return 0; 4468 case Intrinsic::log10: 4469 visitLog10(I); 4470 return 0; 4471 case Intrinsic::exp: 4472 visitExp(I); 4473 return 0; 4474 case Intrinsic::exp2: 4475 visitExp2(I); 4476 return 0; 4477 case Intrinsic::pow: 4478 visitPow(I); 4479 return 0; 4480 case Intrinsic::convert_to_fp16: 4481 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4482 MVT::i16, getValue(I.getArgOperand(0)))); 4483 return 0; 4484 case Intrinsic::convert_from_fp16: 4485 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4486 MVT::f32, getValue(I.getArgOperand(0)))); 4487 return 0; 4488 case Intrinsic::pcmarker: { 4489 SDValue Tmp = getValue(I.getArgOperand(0)); 4490 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4491 return 0; 4492 } 4493 case Intrinsic::readcyclecounter: { 4494 SDValue Op = getRoot(); 4495 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4496 DAG.getVTList(MVT::i64, MVT::Other), 4497 &Op, 1); 4498 setValue(&I, Res); 4499 DAG.setRoot(Res.getValue(1)); 4500 return 0; 4501 } 4502 case Intrinsic::bswap: 4503 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4504 getValue(I.getArgOperand(0)).getValueType(), 4505 getValue(I.getArgOperand(0)))); 4506 return 0; 4507 case Intrinsic::cttz: { 4508 SDValue Arg = getValue(I.getArgOperand(0)); 4509 EVT Ty = Arg.getValueType(); 4510 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4511 return 0; 4512 } 4513 case Intrinsic::ctlz: { 4514 SDValue Arg = getValue(I.getArgOperand(0)); 4515 EVT Ty = Arg.getValueType(); 4516 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4517 return 0; 4518 } 4519 case Intrinsic::ctpop: { 4520 SDValue Arg = getValue(I.getArgOperand(0)); 4521 EVT Ty = Arg.getValueType(); 4522 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4523 return 0; 4524 } 4525 case Intrinsic::stacksave: { 4526 SDValue Op = getRoot(); 4527 Res = DAG.getNode(ISD::STACKSAVE, dl, 4528 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4529 setValue(&I, Res); 4530 DAG.setRoot(Res.getValue(1)); 4531 return 0; 4532 } 4533 case Intrinsic::stackrestore: { 4534 Res = getValue(I.getArgOperand(0)); 4535 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4536 return 0; 4537 } 4538 case Intrinsic::stackprotector: { 4539 // Emit code into the DAG to store the stack guard onto the stack. 4540 MachineFunction &MF = DAG.getMachineFunction(); 4541 MachineFrameInfo *MFI = MF.getFrameInfo(); 4542 EVT PtrTy = TLI.getPointerTy(); 4543 4544 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4545 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4546 4547 int FI = FuncInfo.StaticAllocaMap[Slot]; 4548 MFI->setStackProtectorIndex(FI); 4549 4550 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4551 4552 // Store the stack protector onto the stack. 4553 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4554 MachinePointerInfo::getFixedStack(FI), 4555 true, false, 0); 4556 setValue(&I, Res); 4557 DAG.setRoot(Res); 4558 return 0; 4559 } 4560 case Intrinsic::objectsize: { 4561 // If we don't know by now, we're never going to know. 4562 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4563 4564 assert(CI && "Non-constant type in __builtin_object_size?"); 4565 4566 SDValue Arg = getValue(I.getCalledValue()); 4567 EVT Ty = Arg.getValueType(); 4568 4569 if (CI->isZero()) 4570 Res = DAG.getConstant(-1ULL, Ty); 4571 else 4572 Res = DAG.getConstant(0, Ty); 4573 4574 setValue(&I, Res); 4575 return 0; 4576 } 4577 case Intrinsic::var_annotation: 4578 // Discard annotate attributes 4579 return 0; 4580 4581 case Intrinsic::init_trampoline: { 4582 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4583 4584 SDValue Ops[6]; 4585 Ops[0] = getRoot(); 4586 Ops[1] = getValue(I.getArgOperand(0)); 4587 Ops[2] = getValue(I.getArgOperand(1)); 4588 Ops[3] = getValue(I.getArgOperand(2)); 4589 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4590 Ops[5] = DAG.getSrcValue(F); 4591 4592 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4593 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4594 Ops, 6); 4595 4596 setValue(&I, Res); 4597 DAG.setRoot(Res.getValue(1)); 4598 return 0; 4599 } 4600 case Intrinsic::gcroot: 4601 if (GFI) { 4602 const Value *Alloca = I.getArgOperand(0); 4603 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4604 4605 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4606 GFI->addStackRoot(FI->getIndex(), TypeMap); 4607 } 4608 return 0; 4609 case Intrinsic::gcread: 4610 case Intrinsic::gcwrite: 4611 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4612 return 0; 4613 case Intrinsic::flt_rounds: 4614 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4615 return 0; 4616 case Intrinsic::trap: 4617 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4618 return 0; 4619 case Intrinsic::uadd_with_overflow: 4620 return implVisitAluOverflow(I, ISD::UADDO); 4621 case Intrinsic::sadd_with_overflow: 4622 return implVisitAluOverflow(I, ISD::SADDO); 4623 case Intrinsic::usub_with_overflow: 4624 return implVisitAluOverflow(I, ISD::USUBO); 4625 case Intrinsic::ssub_with_overflow: 4626 return implVisitAluOverflow(I, ISD::SSUBO); 4627 case Intrinsic::umul_with_overflow: 4628 return implVisitAluOverflow(I, ISD::UMULO); 4629 case Intrinsic::smul_with_overflow: 4630 return implVisitAluOverflow(I, ISD::SMULO); 4631 4632 case Intrinsic::prefetch: { 4633 SDValue Ops[4]; 4634 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 4635 Ops[0] = getRoot(); 4636 Ops[1] = getValue(I.getArgOperand(0)); 4637 Ops[2] = getValue(I.getArgOperand(1)); 4638 Ops[3] = getValue(I.getArgOperand(2)); 4639 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 4640 DAG.getVTList(MVT::Other), 4641 &Ops[0], 4, 4642 EVT::getIntegerVT(*Context, 8), 4643 MachinePointerInfo(I.getArgOperand(0)), 4644 0, /* align */ 4645 false, /* volatile */ 4646 rw==0, /* read */ 4647 rw==1)); /* write */ 4648 return 0; 4649 } 4650 case Intrinsic::memory_barrier: { 4651 SDValue Ops[6]; 4652 Ops[0] = getRoot(); 4653 for (int x = 1; x < 6; ++x) 4654 Ops[x] = getValue(I.getArgOperand(x - 1)); 4655 4656 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4657 return 0; 4658 } 4659 case Intrinsic::atomic_cmp_swap: { 4660 SDValue Root = getRoot(); 4661 SDValue L = 4662 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4663 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 4664 Root, 4665 getValue(I.getArgOperand(0)), 4666 getValue(I.getArgOperand(1)), 4667 getValue(I.getArgOperand(2)), 4668 MachinePointerInfo(I.getArgOperand(0))); 4669 setValue(&I, L); 4670 DAG.setRoot(L.getValue(1)); 4671 return 0; 4672 } 4673 case Intrinsic::atomic_load_add: 4674 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4675 case Intrinsic::atomic_load_sub: 4676 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4677 case Intrinsic::atomic_load_or: 4678 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4679 case Intrinsic::atomic_load_xor: 4680 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4681 case Intrinsic::atomic_load_and: 4682 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4683 case Intrinsic::atomic_load_nand: 4684 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4685 case Intrinsic::atomic_load_max: 4686 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4687 case Intrinsic::atomic_load_min: 4688 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4689 case Intrinsic::atomic_load_umin: 4690 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4691 case Intrinsic::atomic_load_umax: 4692 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4693 case Intrinsic::atomic_swap: 4694 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4695 4696 case Intrinsic::invariant_start: 4697 case Intrinsic::lifetime_start: 4698 // Discard region information. 4699 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4700 return 0; 4701 case Intrinsic::invariant_end: 4702 case Intrinsic::lifetime_end: 4703 // Discard region information. 4704 return 0; 4705 } 4706} 4707 4708void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 4709 bool isTailCall, 4710 MachineBasicBlock *LandingPad) { 4711 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4712 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4713 const Type *RetTy = FTy->getReturnType(); 4714 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4715 MCSymbol *BeginLabel = 0; 4716 4717 TargetLowering::ArgListTy Args; 4718 TargetLowering::ArgListEntry Entry; 4719 Args.reserve(CS.arg_size()); 4720 4721 // Check whether the function can return without sret-demotion. 4722 SmallVector<ISD::OutputArg, 4> Outs; 4723 SmallVector<uint64_t, 4> Offsets; 4724 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4725 Outs, TLI, &Offsets); 4726 4727 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4728 FTy->isVarArg(), Outs, FTy->getContext()); 4729 4730 SDValue DemoteStackSlot; 4731 int DemoteStackIdx = -100; 4732 4733 if (!CanLowerReturn) { 4734 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4735 FTy->getReturnType()); 4736 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4737 FTy->getReturnType()); 4738 MachineFunction &MF = DAG.getMachineFunction(); 4739 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4740 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4741 4742 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 4743 Entry.Node = DemoteStackSlot; 4744 Entry.Ty = StackSlotPtrType; 4745 Entry.isSExt = false; 4746 Entry.isZExt = false; 4747 Entry.isInReg = false; 4748 Entry.isSRet = true; 4749 Entry.isNest = false; 4750 Entry.isByVal = false; 4751 Entry.Alignment = Align; 4752 Args.push_back(Entry); 4753 RetTy = Type::getVoidTy(FTy->getContext()); 4754 } 4755 4756 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4757 i != e; ++i) { 4758 SDValue ArgNode = getValue(*i); 4759 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 4760 4761 unsigned attrInd = i - CS.arg_begin() + 1; 4762 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4763 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4764 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4765 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4766 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4767 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4768 Entry.Alignment = CS.getParamAlignment(attrInd); 4769 Args.push_back(Entry); 4770 } 4771 4772 if (LandingPad) { 4773 // Insert a label before the invoke call to mark the try range. This can be 4774 // used to detect deletion of the invoke via the MachineModuleInfo. 4775 BeginLabel = MMI.getContext().CreateTempSymbol(); 4776 4777 // For SjLj, keep track of which landing pads go with which invokes 4778 // so as to maintain the ordering of pads in the LSDA. 4779 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 4780 if (CallSiteIndex) { 4781 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4782 // Now that the call site is handled, stop tracking it. 4783 MMI.setCurrentCallSite(0); 4784 } 4785 4786 // Both PendingLoads and PendingExports must be flushed here; 4787 // this call might not return. 4788 (void)getRoot(); 4789 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4790 } 4791 4792 // Check if target-independent constraints permit a tail call here. 4793 // Target-dependent constraints are checked within TLI.LowerCallTo. 4794 if (isTailCall && 4795 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4796 isTailCall = false; 4797 4798 // If there's a possibility that fast-isel has already selected some amount 4799 // of the current basic block, don't emit a tail call. 4800 if (isTailCall && EnableFastISel) 4801 isTailCall = false; 4802 4803 std::pair<SDValue,SDValue> Result = 4804 TLI.LowerCallTo(getRoot(), RetTy, 4805 CS.paramHasAttr(0, Attribute::SExt), 4806 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4807 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4808 CS.getCallingConv(), 4809 isTailCall, 4810 !CS.getInstruction()->use_empty(), 4811 Callee, Args, DAG, getCurDebugLoc()); 4812 assert((isTailCall || Result.second.getNode()) && 4813 "Non-null chain expected with non-tail call!"); 4814 assert((Result.second.getNode() || !Result.first.getNode()) && 4815 "Null value expected with tail call!"); 4816 if (Result.first.getNode()) { 4817 setValue(CS.getInstruction(), Result.first); 4818 } else if (!CanLowerReturn && Result.second.getNode()) { 4819 // The instruction result is the result of loading from the 4820 // hidden sret parameter. 4821 SmallVector<EVT, 1> PVTs; 4822 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 4823 4824 ComputeValueVTs(TLI, PtrRetTy, PVTs); 4825 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 4826 EVT PtrVT = PVTs[0]; 4827 unsigned NumValues = Outs.size(); 4828 SmallVector<SDValue, 4> Values(NumValues); 4829 SmallVector<SDValue, 4> Chains(NumValues); 4830 4831 for (unsigned i = 0; i < NumValues; ++i) { 4832 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 4833 DemoteStackSlot, 4834 DAG.getConstant(Offsets[i], PtrVT)); 4835 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 4836 Add, 4837 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 4838 false, false, 1); 4839 Values[i] = L; 4840 Chains[i] = L.getValue(1); 4841 } 4842 4843 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 4844 MVT::Other, &Chains[0], NumValues); 4845 PendingLoads.push_back(Chain); 4846 4847 // Collect the legal value parts into potentially illegal values 4848 // that correspond to the original function's return values. 4849 SmallVector<EVT, 4> RetTys; 4850 RetTy = FTy->getReturnType(); 4851 ComputeValueVTs(TLI, RetTy, RetTys); 4852 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4853 SmallVector<SDValue, 4> ReturnValues; 4854 unsigned CurReg = 0; 4855 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4856 EVT VT = RetTys[I]; 4857 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 4858 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 4859 4860 SDValue ReturnValue = 4861 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 4862 RegisterVT, VT, AssertOp); 4863 ReturnValues.push_back(ReturnValue); 4864 CurReg += NumRegs; 4865 } 4866 4867 setValue(CS.getInstruction(), 4868 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 4869 DAG.getVTList(&RetTys[0], RetTys.size()), 4870 &ReturnValues[0], ReturnValues.size())); 4871 4872 } 4873 4874 // As a special case, a null chain means that a tail call has been emitted and 4875 // the DAG root is already updated. 4876 if (Result.second.getNode()) 4877 DAG.setRoot(Result.second); 4878 else 4879 HasTailCall = true; 4880 4881 if (LandingPad) { 4882 // Insert a label at the end of the invoke call to mark the try range. This 4883 // can be used to detect deletion of the invoke via the MachineModuleInfo. 4884 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 4885 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 4886 4887 // Inform MachineModuleInfo of range. 4888 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 4889 } 4890} 4891 4892/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 4893/// value is equal or not-equal to zero. 4894static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 4895 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 4896 UI != E; ++UI) { 4897 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 4898 if (IC->isEquality()) 4899 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 4900 if (C->isNullValue()) 4901 continue; 4902 // Unknown instruction. 4903 return false; 4904 } 4905 return true; 4906} 4907 4908static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 4909 const Type *LoadTy, 4910 SelectionDAGBuilder &Builder) { 4911 4912 // Check to see if this load can be trivially constant folded, e.g. if the 4913 // input is from a string literal. 4914 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 4915 // Cast pointer to the type we really want to load. 4916 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 4917 PointerType::getUnqual(LoadTy)); 4918 4919 if (const Constant *LoadCst = 4920 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 4921 Builder.TD)) 4922 return Builder.getValue(LoadCst); 4923 } 4924 4925 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 4926 // still constant memory, the input chain can be the entry node. 4927 SDValue Root; 4928 bool ConstantMemory = false; 4929 4930 // Do not serialize (non-volatile) loads of constant memory with anything. 4931 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 4932 Root = Builder.DAG.getEntryNode(); 4933 ConstantMemory = true; 4934 } else { 4935 // Do not serialize non-volatile loads against each other. 4936 Root = Builder.DAG.getRoot(); 4937 } 4938 4939 SDValue Ptr = Builder.getValue(PtrVal); 4940 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 4941 Ptr, MachinePointerInfo(PtrVal), 4942 false /*volatile*/, 4943 false /*nontemporal*/, 1 /* align=1 */); 4944 4945 if (!ConstantMemory) 4946 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 4947 return LoadVal; 4948} 4949 4950 4951/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 4952/// If so, return true and lower it, otherwise return false and it will be 4953/// lowered like a normal call. 4954bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 4955 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 4956 if (I.getNumArgOperands() != 3) 4957 return false; 4958 4959 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 4960 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 4961 !I.getArgOperand(2)->getType()->isIntegerTy() || 4962 !I.getType()->isIntegerTy()) 4963 return false; 4964 4965 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 4966 4967 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 4968 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 4969 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 4970 bool ActuallyDoIt = true; 4971 MVT LoadVT; 4972 const Type *LoadTy; 4973 switch (Size->getZExtValue()) { 4974 default: 4975 LoadVT = MVT::Other; 4976 LoadTy = 0; 4977 ActuallyDoIt = false; 4978 break; 4979 case 2: 4980 LoadVT = MVT::i16; 4981 LoadTy = Type::getInt16Ty(Size->getContext()); 4982 break; 4983 case 4: 4984 LoadVT = MVT::i32; 4985 LoadTy = Type::getInt32Ty(Size->getContext()); 4986 break; 4987 case 8: 4988 LoadVT = MVT::i64; 4989 LoadTy = Type::getInt64Ty(Size->getContext()); 4990 break; 4991 /* 4992 case 16: 4993 LoadVT = MVT::v4i32; 4994 LoadTy = Type::getInt32Ty(Size->getContext()); 4995 LoadTy = VectorType::get(LoadTy, 4); 4996 break; 4997 */ 4998 } 4999 5000 // This turns into unaligned loads. We only do this if the target natively 5001 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5002 // we'll only produce a small number of byte loads. 5003 5004 // Require that we can find a legal MVT, and only do this if the target 5005 // supports unaligned loads of that type. Expanding into byte loads would 5006 // bloat the code. 5007 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5008 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5009 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5010 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5011 ActuallyDoIt = false; 5012 } 5013 5014 if (ActuallyDoIt) { 5015 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5016 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5017 5018 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5019 ISD::SETNE); 5020 EVT CallVT = TLI.getValueType(I.getType(), true); 5021 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5022 return true; 5023 } 5024 } 5025 5026 5027 return false; 5028} 5029 5030 5031void SelectionDAGBuilder::visitCall(const CallInst &I) { 5032 // Handle inline assembly differently. 5033 if (isa<InlineAsm>(I.getCalledValue())) { 5034 visitInlineAsm(&I); 5035 return; 5036 } 5037 5038 // See if any floating point values are being passed to this function. This is 5039 // used to emit an undefined reference to fltused on Windows. 5040 const FunctionType *FT = 5041 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5042 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5043 if (FT->isVarArg() && 5044 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5045 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5046 const Type* T = I.getArgOperand(i)->getType(); 5047 for (po_iterator<const Type*> i = po_begin(T), 5048 e = po_end(T); 5049 i != e; ++i) { 5050 if (i->isFloatingPointTy()) { 5051 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5052 break; 5053 } 5054 } 5055 } 5056 } 5057 5058 const char *RenameFn = 0; 5059 if (Function *F = I.getCalledFunction()) { 5060 if (F->isDeclaration()) { 5061 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5062 if (unsigned IID = II->getIntrinsicID(F)) { 5063 RenameFn = visitIntrinsicCall(I, IID); 5064 if (!RenameFn) 5065 return; 5066 } 5067 } 5068 if (unsigned IID = F->getIntrinsicID()) { 5069 RenameFn = visitIntrinsicCall(I, IID); 5070 if (!RenameFn) 5071 return; 5072 } 5073 } 5074 5075 // Check for well-known libc/libm calls. If the function is internal, it 5076 // can't be a library call. 5077 if (!F->hasLocalLinkage() && F->hasName()) { 5078 StringRef Name = F->getName(); 5079 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5080 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5081 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5082 I.getType() == I.getArgOperand(0)->getType() && 5083 I.getType() == I.getArgOperand(1)->getType()) { 5084 SDValue LHS = getValue(I.getArgOperand(0)); 5085 SDValue RHS = getValue(I.getArgOperand(1)); 5086 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5087 LHS.getValueType(), LHS, RHS)); 5088 return; 5089 } 5090 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5091 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5092 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5093 I.getType() == I.getArgOperand(0)->getType()) { 5094 SDValue Tmp = getValue(I.getArgOperand(0)); 5095 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5096 Tmp.getValueType(), Tmp)); 5097 return; 5098 } 5099 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5100 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5101 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5102 I.getType() == I.getArgOperand(0)->getType() && 5103 I.onlyReadsMemory()) { 5104 SDValue Tmp = getValue(I.getArgOperand(0)); 5105 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5106 Tmp.getValueType(), Tmp)); 5107 return; 5108 } 5109 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5110 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5111 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5112 I.getType() == I.getArgOperand(0)->getType() && 5113 I.onlyReadsMemory()) { 5114 SDValue Tmp = getValue(I.getArgOperand(0)); 5115 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5116 Tmp.getValueType(), Tmp)); 5117 return; 5118 } 5119 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5120 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5121 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5122 I.getType() == I.getArgOperand(0)->getType() && 5123 I.onlyReadsMemory()) { 5124 SDValue Tmp = getValue(I.getArgOperand(0)); 5125 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5126 Tmp.getValueType(), Tmp)); 5127 return; 5128 } 5129 } else if (Name == "memcmp") { 5130 if (visitMemCmpCall(I)) 5131 return; 5132 } 5133 } 5134 } 5135 5136 SDValue Callee; 5137 if (!RenameFn) 5138 Callee = getValue(I.getCalledValue()); 5139 else 5140 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5141 5142 // Check if we can potentially perform a tail call. More detailed checking is 5143 // be done within LowerCallTo, after more information about the call is known. 5144 LowerCallTo(&I, Callee, I.isTailCall()); 5145} 5146 5147namespace llvm { 5148 5149/// AsmOperandInfo - This contains information for each constraint that we are 5150/// lowering. 5151class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo : 5152 public TargetLowering::AsmOperandInfo { 5153public: 5154 /// CallOperand - If this is the result output operand or a clobber 5155 /// this is null, otherwise it is the incoming operand to the CallInst. 5156 /// This gets modified as the asm is processed. 5157 SDValue CallOperand; 5158 5159 /// AssignedRegs - If this is a register or register class operand, this 5160 /// contains the set of register corresponding to the operand. 5161 RegsForValue AssignedRegs; 5162 5163 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5164 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5165 } 5166 5167 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5168 /// busy in OutputRegs/InputRegs. 5169 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5170 std::set<unsigned> &OutputRegs, 5171 std::set<unsigned> &InputRegs, 5172 const TargetRegisterInfo &TRI) const { 5173 if (isOutReg) { 5174 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5175 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5176 } 5177 if (isInReg) { 5178 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5179 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5180 } 5181 } 5182 5183 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5184 /// corresponds to. If there is no Value* for this operand, it returns 5185 /// MVT::Other. 5186 EVT getCallOperandValEVT(LLVMContext &Context, 5187 const TargetLowering &TLI, 5188 const TargetData *TD) const { 5189 if (CallOperandVal == 0) return MVT::Other; 5190 5191 if (isa<BasicBlock>(CallOperandVal)) 5192 return TLI.getPointerTy(); 5193 5194 const llvm::Type *OpTy = CallOperandVal->getType(); 5195 5196 // If this is an indirect operand, the operand is a pointer to the 5197 // accessed type. 5198 if (isIndirect) { 5199 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5200 if (!PtrTy) 5201 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5202 OpTy = PtrTy->getElementType(); 5203 } 5204 5205 // If OpTy is not a single value, it may be a struct/union that we 5206 // can tile with integers. 5207 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5208 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5209 switch (BitSize) { 5210 default: break; 5211 case 1: 5212 case 8: 5213 case 16: 5214 case 32: 5215 case 64: 5216 case 128: 5217 OpTy = IntegerType::get(Context, BitSize); 5218 break; 5219 } 5220 } 5221 5222 return TLI.getValueType(OpTy, true); 5223 } 5224 5225private: 5226 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5227 /// specified set. 5228 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5229 const TargetRegisterInfo &TRI) { 5230 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5231 Regs.insert(Reg); 5232 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5233 for (; *Aliases; ++Aliases) 5234 Regs.insert(*Aliases); 5235 } 5236}; 5237 5238typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5239 5240} // end llvm namespace. 5241 5242/// isAllocatableRegister - If the specified register is safe to allocate, 5243/// i.e. it isn't a stack pointer or some other special register, return the 5244/// register class for the register. Otherwise, return null. 5245static const TargetRegisterClass * 5246isAllocatableRegister(unsigned Reg, MachineFunction &MF, 5247 const TargetLowering &TLI, 5248 const TargetRegisterInfo *TRI) { 5249 EVT FoundVT = MVT::Other; 5250 const TargetRegisterClass *FoundRC = 0; 5251 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 5252 E = TRI->regclass_end(); RCI != E; ++RCI) { 5253 EVT ThisVT = MVT::Other; 5254 5255 const TargetRegisterClass *RC = *RCI; 5256 // If none of the value types for this register class are valid, we 5257 // can't use it. For example, 64-bit reg classes on 32-bit targets. 5258 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 5259 I != E; ++I) { 5260 if (TLI.isTypeLegal(*I)) { 5261 // If we have already found this register in a different register class, 5262 // choose the one with the largest VT specified. For example, on 5263 // PowerPC, we favor f64 register classes over f32. 5264 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 5265 ThisVT = *I; 5266 break; 5267 } 5268 } 5269 } 5270 5271 if (ThisVT == MVT::Other) continue; 5272 5273 // NOTE: This isn't ideal. In particular, this might allocate the 5274 // frame pointer in functions that need it (due to them not being taken 5275 // out of allocation, because a variable sized allocation hasn't been seen 5276 // yet). This is a slight code pessimization, but should still work. 5277 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 5278 E = RC->allocation_order_end(MF); I != E; ++I) 5279 if (*I == Reg) { 5280 // We found a matching register class. Keep looking at others in case 5281 // we find one with larger registers that this physreg is also in. 5282 FoundRC = RC; 5283 FoundVT = ThisVT; 5284 break; 5285 } 5286 } 5287 return FoundRC; 5288} 5289 5290/// GetRegistersForValue - Assign registers (virtual or physical) for the 5291/// specified operand. We prefer to assign virtual registers, to allow the 5292/// register allocator to handle the assignment process. However, if the asm 5293/// uses features that we can't model on machineinstrs, we have SDISel do the 5294/// allocation. This produces generally horrible, but correct, code. 5295/// 5296/// OpInfo describes the operand. 5297/// Input and OutputRegs are the set of already allocated physical registers. 5298/// 5299void SelectionDAGBuilder:: 5300GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, 5301 std::set<unsigned> &OutputRegs, 5302 std::set<unsigned> &InputRegs) { 5303 LLVMContext &Context = FuncInfo.Fn->getContext(); 5304 5305 // Compute whether this value requires an input register, an output register, 5306 // or both. 5307 bool isOutReg = false; 5308 bool isInReg = false; 5309 switch (OpInfo.Type) { 5310 case InlineAsm::isOutput: 5311 isOutReg = true; 5312 5313 // If there is an input constraint that matches this, we need to reserve 5314 // the input register so no other inputs allocate to it. 5315 isInReg = OpInfo.hasMatchingInput(); 5316 break; 5317 case InlineAsm::isInput: 5318 isInReg = true; 5319 isOutReg = false; 5320 break; 5321 case InlineAsm::isClobber: 5322 isOutReg = true; 5323 isInReg = true; 5324 break; 5325 } 5326 5327 5328 MachineFunction &MF = DAG.getMachineFunction(); 5329 SmallVector<unsigned, 4> Regs; 5330 5331 // If this is a constraint for a single physreg, or a constraint for a 5332 // register class, find it. 5333 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5334 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5335 OpInfo.ConstraintVT); 5336 5337 unsigned NumRegs = 1; 5338 if (OpInfo.ConstraintVT != MVT::Other) { 5339 // If this is a FP input in an integer register (or visa versa) insert a bit 5340 // cast of the input value. More generally, handle any case where the input 5341 // value disagrees with the register class we plan to stick this in. 5342 if (OpInfo.Type == InlineAsm::isInput && 5343 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5344 // Try to convert to the first EVT that the reg class contains. If the 5345 // types are identical size, use a bitcast to convert (e.g. two differing 5346 // vector types). 5347 EVT RegVT = *PhysReg.second->vt_begin(); 5348 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5349 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5350 RegVT, OpInfo.CallOperand); 5351 OpInfo.ConstraintVT = RegVT; 5352 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5353 // If the input is a FP value and we want it in FP registers, do a 5354 // bitcast to the corresponding integer type. This turns an f64 value 5355 // into i64, which can be passed with two i32 values on a 32-bit 5356 // machine. 5357 RegVT = EVT::getIntegerVT(Context, 5358 OpInfo.ConstraintVT.getSizeInBits()); 5359 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5360 RegVT, OpInfo.CallOperand); 5361 OpInfo.ConstraintVT = RegVT; 5362 } 5363 } 5364 5365 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5366 } 5367 5368 EVT RegVT; 5369 EVT ValueVT = OpInfo.ConstraintVT; 5370 5371 // If this is a constraint for a specific physical register, like {r17}, 5372 // assign it now. 5373 if (unsigned AssignedReg = PhysReg.first) { 5374 const TargetRegisterClass *RC = PhysReg.second; 5375 if (OpInfo.ConstraintVT == MVT::Other) 5376 ValueVT = *RC->vt_begin(); 5377 5378 // Get the actual register value type. This is important, because the user 5379 // may have asked for (e.g.) the AX register in i32 type. We need to 5380 // remember that AX is actually i16 to get the right extension. 5381 RegVT = *RC->vt_begin(); 5382 5383 // This is a explicit reference to a physical register. 5384 Regs.push_back(AssignedReg); 5385 5386 // If this is an expanded reference, add the rest of the regs to Regs. 5387 if (NumRegs != 1) { 5388 TargetRegisterClass::iterator I = RC->begin(); 5389 for (; *I != AssignedReg; ++I) 5390 assert(I != RC->end() && "Didn't find reg!"); 5391 5392 // Already added the first reg. 5393 --NumRegs; ++I; 5394 for (; NumRegs; --NumRegs, ++I) { 5395 assert(I != RC->end() && "Ran out of registers to allocate!"); 5396 Regs.push_back(*I); 5397 } 5398 } 5399 5400 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5401 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5402 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5403 return; 5404 } 5405 5406 // Otherwise, if this was a reference to an LLVM register class, create vregs 5407 // for this reference. 5408 if (const TargetRegisterClass *RC = PhysReg.second) { 5409 RegVT = *RC->vt_begin(); 5410 if (OpInfo.ConstraintVT == MVT::Other) 5411 ValueVT = RegVT; 5412 5413 // Create the appropriate number of virtual registers. 5414 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5415 for (; NumRegs; --NumRegs) 5416 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5417 5418 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5419 return; 5420 } 5421 5422 // This is a reference to a register class that doesn't directly correspond 5423 // to an LLVM register class. Allocate NumRegs consecutive, available, 5424 // registers from the class. 5425 std::vector<unsigned> RegClassRegs 5426 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 5427 OpInfo.ConstraintVT); 5428 5429 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5430 unsigned NumAllocated = 0; 5431 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 5432 unsigned Reg = RegClassRegs[i]; 5433 // See if this register is available. 5434 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 5435 (isInReg && InputRegs.count(Reg))) { // Already used. 5436 // Make sure we find consecutive registers. 5437 NumAllocated = 0; 5438 continue; 5439 } 5440 5441 // Check to see if this register is allocatable (i.e. don't give out the 5442 // stack pointer). 5443 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); 5444 if (!RC) { // Couldn't allocate this register. 5445 // Reset NumAllocated to make sure we return consecutive registers. 5446 NumAllocated = 0; 5447 continue; 5448 } 5449 5450 // Okay, this register is good, we can use it. 5451 ++NumAllocated; 5452 5453 // If we allocated enough consecutive registers, succeed. 5454 if (NumAllocated == NumRegs) { 5455 unsigned RegStart = (i-NumAllocated)+1; 5456 unsigned RegEnd = i+1; 5457 // Mark all of the allocated registers used. 5458 for (unsigned i = RegStart; i != RegEnd; ++i) 5459 Regs.push_back(RegClassRegs[i]); 5460 5461 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 5462 OpInfo.ConstraintVT); 5463 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5464 return; 5465 } 5466 } 5467 5468 // Otherwise, we couldn't allocate enough registers for this. 5469} 5470 5471/// visitInlineAsm - Handle a call to an InlineAsm object. 5472/// 5473void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5474 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5475 5476 /// ConstraintOperands - Information about all of the constraints. 5477 SDISelAsmOperandInfoVector ConstraintOperands; 5478 5479 std::set<unsigned> OutputRegs, InputRegs; 5480 5481 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS); 5482 bool hasMemory = false; 5483 5484 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5485 unsigned ResNo = 0; // ResNo - The result number of the next output. 5486 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5487 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5488 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5489 5490 EVT OpVT = MVT::Other; 5491 5492 // Compute the value type for each operand. 5493 switch (OpInfo.Type) { 5494 case InlineAsm::isOutput: 5495 // Indirect outputs just consume an argument. 5496 if (OpInfo.isIndirect) { 5497 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5498 break; 5499 } 5500 5501 // The return value of the call is this value. As such, there is no 5502 // corresponding argument. 5503 assert(!CS.getType()->isVoidTy() && 5504 "Bad inline asm!"); 5505 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5506 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5507 } else { 5508 assert(ResNo == 0 && "Asm only has one result!"); 5509 OpVT = TLI.getValueType(CS.getType()); 5510 } 5511 ++ResNo; 5512 break; 5513 case InlineAsm::isInput: 5514 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5515 break; 5516 case InlineAsm::isClobber: 5517 // Nothing to do. 5518 break; 5519 } 5520 5521 // If this is an input or an indirect output, process the call argument. 5522 // BasicBlocks are labels, currently appearing only in asm's. 5523 if (OpInfo.CallOperandVal) { 5524 // Strip bitcasts, if any. This mostly comes up for functions. 5525 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts(); 5526 5527 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5528 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5529 } else { 5530 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5531 } 5532 5533 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5534 } 5535 5536 OpInfo.ConstraintVT = OpVT; 5537 5538 // Indirect operand accesses access memory. 5539 if (OpInfo.isIndirect) 5540 hasMemory = true; 5541 else { 5542 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5543 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]); 5544 if (CType == TargetLowering::C_Memory) { 5545 hasMemory = true; 5546 break; 5547 } 5548 } 5549 } 5550 } 5551 5552 SDValue Chain, Flag; 5553 5554 // We won't need to flush pending loads if this asm doesn't touch 5555 // memory and is nonvolatile. 5556 if (hasMemory || IA->hasSideEffects()) 5557 Chain = getRoot(); 5558 else 5559 Chain = DAG.getRoot(); 5560 5561 // Second pass over the constraints: compute which constraint option to use 5562 // and assign registers to constraints that want a specific physreg. 5563 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5564 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5565 5566 // If this is an output operand with a matching input operand, look up the 5567 // matching input. If their types mismatch, e.g. one is an integer, the 5568 // other is floating point, or their sizes are different, flag it as an 5569 // error. 5570 if (OpInfo.hasMatchingInput()) { 5571 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5572 5573 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5574 if ((OpInfo.ConstraintVT.isInteger() != 5575 Input.ConstraintVT.isInteger()) || 5576 (OpInfo.ConstraintVT.getSizeInBits() != 5577 Input.ConstraintVT.getSizeInBits())) { 5578 report_fatal_error("Unsupported asm: input constraint" 5579 " with a matching output constraint of" 5580 " incompatible type!"); 5581 } 5582 Input.ConstraintVT = OpInfo.ConstraintVT; 5583 } 5584 } 5585 5586 // Compute the constraint code and ConstraintType to use. 5587 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5588 5589 // If this is a memory input, and if the operand is not indirect, do what we 5590 // need to to provide an address for the memory input. 5591 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5592 !OpInfo.isIndirect) { 5593 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && 5594 "Can only indirectify direct input operands!"); 5595 5596 // Memory operands really want the address of the value. If we don't have 5597 // an indirect input, put it in the constpool if we can, otherwise spill 5598 // it to a stack slot. 5599 5600 // If the operand is a float, integer, or vector constant, spill to a 5601 // constant pool entry to get its address. 5602 const Value *OpVal = OpInfo.CallOperandVal; 5603 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5604 isa<ConstantVector>(OpVal)) { 5605 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5606 TLI.getPointerTy()); 5607 } else { 5608 // Otherwise, create a stack slot and emit a store to it before the 5609 // asm. 5610 const Type *Ty = OpVal->getType(); 5611 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5612 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5613 MachineFunction &MF = DAG.getMachineFunction(); 5614 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5615 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5616 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5617 OpInfo.CallOperand, StackSlot, 5618 MachinePointerInfo::getFixedStack(SSFI), 5619 false, false, 0); 5620 OpInfo.CallOperand = StackSlot; 5621 } 5622 5623 // There is no longer a Value* corresponding to this operand. 5624 OpInfo.CallOperandVal = 0; 5625 5626 // It is now an indirect operand. 5627 OpInfo.isIndirect = true; 5628 } 5629 5630 // If this constraint is for a specific register, allocate it before 5631 // anything else. 5632 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5633 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5634 } 5635 5636 // Second pass - Loop over all of the operands, assigning virtual or physregs 5637 // to register class operands. 5638 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5639 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5640 5641 // C_Register operands have already been allocated, Other/Memory don't need 5642 // to be. 5643 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5644 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5645 } 5646 5647 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5648 std::vector<SDValue> AsmNodeOperands; 5649 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5650 AsmNodeOperands.push_back( 5651 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5652 TLI.getPointerTy())); 5653 5654 // If we have a !srcloc metadata node associated with it, we want to attach 5655 // this to the ultimately generated inline asm machineinstr. To do this, we 5656 // pass in the third operand as this (potentially null) inline asm MDNode. 5657 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5658 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5659 5660 // Remember the AlignStack bit as operand 3. 5661 AsmNodeOperands.push_back(DAG.getTargetConstant(IA->isAlignStack() ? 1 : 0, 5662 MVT::i1)); 5663 5664 // Loop over all of the inputs, copying the operand values into the 5665 // appropriate registers and processing the output regs. 5666 RegsForValue RetValRegs; 5667 5668 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5669 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5670 5671 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5672 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5673 5674 switch (OpInfo.Type) { 5675 case InlineAsm::isOutput: { 5676 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5677 OpInfo.ConstraintType != TargetLowering::C_Register) { 5678 // Memory output, or 'other' output (e.g. 'X' constraint). 5679 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5680 5681 // Add information to the INLINEASM node to know about this output. 5682 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5683 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5684 TLI.getPointerTy())); 5685 AsmNodeOperands.push_back(OpInfo.CallOperand); 5686 break; 5687 } 5688 5689 // Otherwise, this is a register or register class output. 5690 5691 // Copy the output from the appropriate register. Find a register that 5692 // we can use. 5693 if (OpInfo.AssignedRegs.Regs.empty()) 5694 report_fatal_error("Couldn't allocate output reg for constraint '" + 5695 Twine(OpInfo.ConstraintCode) + "'!"); 5696 5697 // If this is an indirect operand, store through the pointer after the 5698 // asm. 5699 if (OpInfo.isIndirect) { 5700 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5701 OpInfo.CallOperandVal)); 5702 } else { 5703 // This is the result value of the call. 5704 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5705 // Concatenate this output onto the outputs list. 5706 RetValRegs.append(OpInfo.AssignedRegs); 5707 } 5708 5709 // Add information to the INLINEASM node to know that this register is 5710 // set. 5711 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5712 InlineAsm::Kind_RegDefEarlyClobber : 5713 InlineAsm::Kind_RegDef, 5714 false, 5715 0, 5716 DAG, 5717 AsmNodeOperands); 5718 break; 5719 } 5720 case InlineAsm::isInput: { 5721 SDValue InOperandVal = OpInfo.CallOperand; 5722 5723 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5724 // If this is required to match an output register we have already set, 5725 // just use its register. 5726 unsigned OperandNo = OpInfo.getMatchedOperand(); 5727 5728 // Scan until we find the definition we already emitted of this operand. 5729 // When we find it, create a RegsForValue operand. 5730 unsigned CurOp = InlineAsm::Op_FirstOperand; 5731 for (; OperandNo; --OperandNo) { 5732 // Advance to the next operand. 5733 unsigned OpFlag = 5734 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5735 assert((InlineAsm::isRegDefKind(OpFlag) || 5736 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5737 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5738 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5739 } 5740 5741 unsigned OpFlag = 5742 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5743 if (InlineAsm::isRegDefKind(OpFlag) || 5744 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5745 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5746 if (OpInfo.isIndirect) { 5747 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5748 LLVMContext &Ctx = *DAG.getContext(); 5749 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5750 " don't know how to handle tied " 5751 "indirect register inputs"); 5752 } 5753 5754 RegsForValue MatchedRegs; 5755 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5756 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5757 MatchedRegs.RegVTs.push_back(RegVT); 5758 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5759 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5760 i != e; ++i) 5761 MatchedRegs.Regs.push_back 5762 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5763 5764 // Use the produced MatchedRegs object to 5765 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5766 Chain, &Flag); 5767 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 5768 true, OpInfo.getMatchedOperand(), 5769 DAG, AsmNodeOperands); 5770 break; 5771 } 5772 5773 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 5774 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 5775 "Unexpected number of operands"); 5776 // Add information to the INLINEASM node to know about this input. 5777 // See InlineAsm.h isUseOperandTiedToDef. 5778 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 5779 OpInfo.getMatchedOperand()); 5780 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5781 TLI.getPointerTy())); 5782 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5783 break; 5784 } 5785 5786 // Treat indirect 'X' constraint as memory. 5787 if (OpInfo.ConstraintType == TargetLowering::C_Other && 5788 OpInfo.isIndirect) 5789 OpInfo.ConstraintType = TargetLowering::C_Memory; 5790 5791 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5792 std::vector<SDValue> Ops; 5793 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 5794 Ops, DAG); 5795 if (Ops.empty()) 5796 report_fatal_error("Invalid operand for inline asm constraint '" + 5797 Twine(OpInfo.ConstraintCode) + "'!"); 5798 5799 // Add information to the INLINEASM node to know about this input. 5800 unsigned ResOpType = 5801 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 5802 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5803 TLI.getPointerTy())); 5804 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5805 break; 5806 } 5807 5808 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5809 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5810 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5811 "Memory operands expect pointer values"); 5812 5813 // Add information to the INLINEASM node to know about this input. 5814 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5815 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5816 TLI.getPointerTy())); 5817 AsmNodeOperands.push_back(InOperandVal); 5818 break; 5819 } 5820 5821 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5822 OpInfo.ConstraintType == TargetLowering::C_Register) && 5823 "Unknown constraint type!"); 5824 assert(!OpInfo.isIndirect && 5825 "Don't know how to handle indirect register inputs yet!"); 5826 5827 // Copy the input into the appropriate registers. 5828 if (OpInfo.AssignedRegs.Regs.empty() || 5829 !OpInfo.AssignedRegs.areValueTypesLegal(TLI)) 5830 report_fatal_error("Couldn't allocate input reg for constraint '" + 5831 Twine(OpInfo.ConstraintCode) + "'!"); 5832 5833 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5834 Chain, &Flag); 5835 5836 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 5837 DAG, AsmNodeOperands); 5838 break; 5839 } 5840 case InlineAsm::isClobber: { 5841 // Add the clobbered value to the operand list, so that the register 5842 // allocator is aware that the physreg got clobbered. 5843 if (!OpInfo.AssignedRegs.Regs.empty()) 5844 OpInfo.AssignedRegs.AddInlineAsmOperands( 5845 InlineAsm::Kind_RegDefEarlyClobber, 5846 false, 0, DAG, 5847 AsmNodeOperands); 5848 break; 5849 } 5850 } 5851 } 5852 5853 // Finish up input operands. Set the input chain and add the flag last. 5854 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 5855 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5856 5857 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5858 DAG.getVTList(MVT::Other, MVT::Flag), 5859 &AsmNodeOperands[0], AsmNodeOperands.size()); 5860 Flag = Chain.getValue(1); 5861 5862 // If this asm returns a register value, copy the result from that register 5863 // and set it as the value of the call. 5864 if (!RetValRegs.Regs.empty()) { 5865 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5866 Chain, &Flag); 5867 5868 // FIXME: Why don't we do this for inline asms with MRVs? 5869 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5870 EVT ResultType = TLI.getValueType(CS.getType()); 5871 5872 // If any of the results of the inline asm is a vector, it may have the 5873 // wrong width/num elts. This can happen for register classes that can 5874 // contain multiple different value types. The preg or vreg allocated may 5875 // not have the same VT as was expected. Convert it to the right type 5876 // with bit_convert. 5877 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5878 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5879 ResultType, Val); 5880 5881 } else if (ResultType != Val.getValueType() && 5882 ResultType.isInteger() && Val.getValueType().isInteger()) { 5883 // If a result value was tied to an input value, the computed result may 5884 // have a wider width than the expected result. Extract the relevant 5885 // portion. 5886 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 5887 } 5888 5889 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 5890 } 5891 5892 setValue(CS.getInstruction(), Val); 5893 // Don't need to use this as a chain in this case. 5894 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 5895 return; 5896 } 5897 5898 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 5899 5900 // Process indirect outputs, first output all of the flagged copies out of 5901 // physregs. 5902 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 5903 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 5904 const Value *Ptr = IndirectStoresToEmit[i].second; 5905 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5906 Chain, &Flag); 5907 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 5908 } 5909 5910 // Emit the non-flagged stores from the physregs. 5911 SmallVector<SDValue, 8> OutChains; 5912 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 5913 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 5914 StoresToEmit[i].first, 5915 getValue(StoresToEmit[i].second), 5916 MachinePointerInfo(StoresToEmit[i].second), 5917 false, false, 0); 5918 OutChains.push_back(Val); 5919 } 5920 5921 if (!OutChains.empty()) 5922 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 5923 &OutChains[0], OutChains.size()); 5924 5925 DAG.setRoot(Chain); 5926} 5927 5928void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 5929 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 5930 MVT::Other, getRoot(), 5931 getValue(I.getArgOperand(0)), 5932 DAG.getSrcValue(I.getArgOperand(0)))); 5933} 5934 5935void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 5936 const TargetData &TD = *TLI.getTargetData(); 5937 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 5938 getRoot(), getValue(I.getOperand(0)), 5939 DAG.getSrcValue(I.getOperand(0)), 5940 TD.getABITypeAlignment(I.getType())); 5941 setValue(&I, V); 5942 DAG.setRoot(V.getValue(1)); 5943} 5944 5945void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 5946 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 5947 MVT::Other, getRoot(), 5948 getValue(I.getArgOperand(0)), 5949 DAG.getSrcValue(I.getArgOperand(0)))); 5950} 5951 5952void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 5953 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 5954 MVT::Other, getRoot(), 5955 getValue(I.getArgOperand(0)), 5956 getValue(I.getArgOperand(1)), 5957 DAG.getSrcValue(I.getArgOperand(0)), 5958 DAG.getSrcValue(I.getArgOperand(1)))); 5959} 5960 5961/// TargetLowering::LowerCallTo - This is the default LowerCallTo 5962/// implementation, which just calls LowerCall. 5963/// FIXME: When all targets are 5964/// migrated to using LowerCall, this hook should be integrated into SDISel. 5965std::pair<SDValue, SDValue> 5966TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 5967 bool RetSExt, bool RetZExt, bool isVarArg, 5968 bool isInreg, unsigned NumFixedArgs, 5969 CallingConv::ID CallConv, bool isTailCall, 5970 bool isReturnValueUsed, 5971 SDValue Callee, 5972 ArgListTy &Args, SelectionDAG &DAG, 5973 DebugLoc dl) const { 5974 // Handle all of the outgoing arguments. 5975 SmallVector<ISD::OutputArg, 32> Outs; 5976 SmallVector<SDValue, 32> OutVals; 5977 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 5978 SmallVector<EVT, 4> ValueVTs; 5979 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 5980 for (unsigned Value = 0, NumValues = ValueVTs.size(); 5981 Value != NumValues; ++Value) { 5982 EVT VT = ValueVTs[Value]; 5983 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 5984 SDValue Op = SDValue(Args[i].Node.getNode(), 5985 Args[i].Node.getResNo() + Value); 5986 ISD::ArgFlagsTy Flags; 5987 unsigned OriginalAlignment = 5988 getTargetData()->getABITypeAlignment(ArgTy); 5989 5990 if (Args[i].isZExt) 5991 Flags.setZExt(); 5992 if (Args[i].isSExt) 5993 Flags.setSExt(); 5994 if (Args[i].isInReg) 5995 Flags.setInReg(); 5996 if (Args[i].isSRet) 5997 Flags.setSRet(); 5998 if (Args[i].isByVal) { 5999 Flags.setByVal(); 6000 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 6001 const Type *ElementTy = Ty->getElementType(); 6002 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 6003 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy); 6004 // For ByVal, alignment should come from FE. BE will guess if this 6005 // info is not there but there are cases it cannot get right. 6006 if (Args[i].Alignment) 6007 FrameAlign = Args[i].Alignment; 6008 Flags.setByValAlign(FrameAlign); 6009 Flags.setByValSize(FrameSize); 6010 } 6011 if (Args[i].isNest) 6012 Flags.setNest(); 6013 Flags.setOrigAlign(OriginalAlignment); 6014 6015 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6016 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6017 SmallVector<SDValue, 4> Parts(NumParts); 6018 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6019 6020 if (Args[i].isSExt) 6021 ExtendKind = ISD::SIGN_EXTEND; 6022 else if (Args[i].isZExt) 6023 ExtendKind = ISD::ZERO_EXTEND; 6024 6025 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6026 PartVT, ExtendKind); 6027 6028 for (unsigned j = 0; j != NumParts; ++j) { 6029 // if it isn't first piece, alignment must be 1 6030 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6031 i < NumFixedArgs); 6032 if (NumParts > 1 && j == 0) 6033 MyFlags.Flags.setSplit(); 6034 else if (j != 0) 6035 MyFlags.Flags.setOrigAlign(1); 6036 6037 Outs.push_back(MyFlags); 6038 OutVals.push_back(Parts[j]); 6039 } 6040 } 6041 } 6042 6043 // Handle the incoming return values from the call. 6044 SmallVector<ISD::InputArg, 32> Ins; 6045 SmallVector<EVT, 4> RetTys; 6046 ComputeValueVTs(*this, RetTy, RetTys); 6047 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6048 EVT VT = RetTys[I]; 6049 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6050 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6051 for (unsigned i = 0; i != NumRegs; ++i) { 6052 ISD::InputArg MyFlags; 6053 MyFlags.VT = RegisterVT; 6054 MyFlags.Used = isReturnValueUsed; 6055 if (RetSExt) 6056 MyFlags.Flags.setSExt(); 6057 if (RetZExt) 6058 MyFlags.Flags.setZExt(); 6059 if (isInreg) 6060 MyFlags.Flags.setInReg(); 6061 Ins.push_back(MyFlags); 6062 } 6063 } 6064 6065 SmallVector<SDValue, 4> InVals; 6066 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6067 Outs, OutVals, Ins, dl, DAG, InVals); 6068 6069 // Verify that the target's LowerCall behaved as expected. 6070 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6071 "LowerCall didn't return a valid chain!"); 6072 assert((!isTailCall || InVals.empty()) && 6073 "LowerCall emitted a return value for a tail call!"); 6074 assert((isTailCall || InVals.size() == Ins.size()) && 6075 "LowerCall didn't emit the correct number of values!"); 6076 6077 // For a tail call, the return value is merely live-out and there aren't 6078 // any nodes in the DAG representing it. Return a special value to 6079 // indicate that a tail call has been emitted and no more Instructions 6080 // should be processed in the current block. 6081 if (isTailCall) { 6082 DAG.setRoot(Chain); 6083 return std::make_pair(SDValue(), SDValue()); 6084 } 6085 6086 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6087 assert(InVals[i].getNode() && 6088 "LowerCall emitted a null value!"); 6089 assert(Ins[i].VT == InVals[i].getValueType() && 6090 "LowerCall emitted a value with the wrong type!"); 6091 }); 6092 6093 // Collect the legal value parts into potentially illegal values 6094 // that correspond to the original function's return values. 6095 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6096 if (RetSExt) 6097 AssertOp = ISD::AssertSext; 6098 else if (RetZExt) 6099 AssertOp = ISD::AssertZext; 6100 SmallVector<SDValue, 4> ReturnValues; 6101 unsigned CurReg = 0; 6102 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6103 EVT VT = RetTys[I]; 6104 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6105 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6106 6107 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6108 NumRegs, RegisterVT, VT, 6109 AssertOp)); 6110 CurReg += NumRegs; 6111 } 6112 6113 // For a function returning void, there is no return value. We can't create 6114 // such a node, so we just return a null return value in that case. In 6115 // that case, nothing will actualy look at the value. 6116 if (ReturnValues.empty()) 6117 return std::make_pair(SDValue(), Chain); 6118 6119 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6120 DAG.getVTList(&RetTys[0], RetTys.size()), 6121 &ReturnValues[0], ReturnValues.size()); 6122 return std::make_pair(Res, Chain); 6123} 6124 6125void TargetLowering::LowerOperationWrapper(SDNode *N, 6126 SmallVectorImpl<SDValue> &Results, 6127 SelectionDAG &DAG) const { 6128 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6129 if (Res.getNode()) 6130 Results.push_back(Res); 6131} 6132 6133SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6134 llvm_unreachable("LowerOperation not implemented for this target!"); 6135 return SDValue(); 6136} 6137 6138void 6139SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6140 SDValue Op = getNonRegisterValue(V); 6141 assert((Op.getOpcode() != ISD::CopyFromReg || 6142 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6143 "Copy from a reg to the same reg!"); 6144 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6145 6146 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6147 SDValue Chain = DAG.getEntryNode(); 6148 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6149 PendingExports.push_back(Chain); 6150} 6151 6152#include "llvm/CodeGen/SelectionDAGISel.h" 6153 6154void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6155 // If this is the entry block, emit arguments. 6156 const Function &F = *LLVMBB->getParent(); 6157 SelectionDAG &DAG = SDB->DAG; 6158 DebugLoc dl = SDB->getCurDebugLoc(); 6159 const TargetData *TD = TLI.getTargetData(); 6160 SmallVector<ISD::InputArg, 16> Ins; 6161 6162 // Check whether the function can return without sret-demotion. 6163 SmallVector<ISD::OutputArg, 4> Outs; 6164 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6165 Outs, TLI); 6166 6167 if (!FuncInfo->CanLowerReturn) { 6168 // Put in an sret pointer parameter before all the other parameters. 6169 SmallVector<EVT, 1> ValueVTs; 6170 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6171 6172 // NOTE: Assuming that a pointer will never break down to more than one VT 6173 // or one register. 6174 ISD::ArgFlagsTy Flags; 6175 Flags.setSRet(); 6176 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6177 ISD::InputArg RetArg(Flags, RegisterVT, true); 6178 Ins.push_back(RetArg); 6179 } 6180 6181 // Set up the incoming argument description vector. 6182 unsigned Idx = 1; 6183 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6184 I != E; ++I, ++Idx) { 6185 SmallVector<EVT, 4> ValueVTs; 6186 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6187 bool isArgValueUsed = !I->use_empty(); 6188 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6189 Value != NumValues; ++Value) { 6190 EVT VT = ValueVTs[Value]; 6191 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6192 ISD::ArgFlagsTy Flags; 6193 unsigned OriginalAlignment = 6194 TD->getABITypeAlignment(ArgTy); 6195 6196 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6197 Flags.setZExt(); 6198 if (F.paramHasAttr(Idx, Attribute::SExt)) 6199 Flags.setSExt(); 6200 if (F.paramHasAttr(Idx, Attribute::InReg)) 6201 Flags.setInReg(); 6202 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6203 Flags.setSRet(); 6204 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6205 Flags.setByVal(); 6206 const PointerType *Ty = cast<PointerType>(I->getType()); 6207 const Type *ElementTy = Ty->getElementType(); 6208 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6209 unsigned FrameSize = TD->getTypeAllocSize(ElementTy); 6210 // For ByVal, alignment should be passed from FE. BE will guess if 6211 // this info is not there but there are cases it cannot get right. 6212 if (F.getParamAlignment(Idx)) 6213 FrameAlign = F.getParamAlignment(Idx); 6214 Flags.setByValAlign(FrameAlign); 6215 Flags.setByValSize(FrameSize); 6216 } 6217 if (F.paramHasAttr(Idx, Attribute::Nest)) 6218 Flags.setNest(); 6219 Flags.setOrigAlign(OriginalAlignment); 6220 6221 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6222 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6223 for (unsigned i = 0; i != NumRegs; ++i) { 6224 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6225 if (NumRegs > 1 && i == 0) 6226 MyFlags.Flags.setSplit(); 6227 // if it isn't first piece, alignment must be 1 6228 else if (i > 0) 6229 MyFlags.Flags.setOrigAlign(1); 6230 Ins.push_back(MyFlags); 6231 } 6232 } 6233 } 6234 6235 // Call the target to set up the argument values. 6236 SmallVector<SDValue, 8> InVals; 6237 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6238 F.isVarArg(), Ins, 6239 dl, DAG, InVals); 6240 6241 // Verify that the target's LowerFormalArguments behaved as expected. 6242 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6243 "LowerFormalArguments didn't return a valid chain!"); 6244 assert(InVals.size() == Ins.size() && 6245 "LowerFormalArguments didn't emit the correct number of values!"); 6246 DEBUG({ 6247 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6248 assert(InVals[i].getNode() && 6249 "LowerFormalArguments emitted a null value!"); 6250 assert(Ins[i].VT == InVals[i].getValueType() && 6251 "LowerFormalArguments emitted a value with the wrong type!"); 6252 } 6253 }); 6254 6255 // Update the DAG with the new chain value resulting from argument lowering. 6256 DAG.setRoot(NewRoot); 6257 6258 // Set up the argument values. 6259 unsigned i = 0; 6260 Idx = 1; 6261 if (!FuncInfo->CanLowerReturn) { 6262 // Create a virtual register for the sret pointer, and put in a copy 6263 // from the sret argument into it. 6264 SmallVector<EVT, 1> ValueVTs; 6265 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6266 EVT VT = ValueVTs[0]; 6267 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6268 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6269 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6270 RegVT, VT, AssertOp); 6271 6272 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6273 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6274 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6275 FuncInfo->DemoteRegister = SRetReg; 6276 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6277 SRetReg, ArgValue); 6278 DAG.setRoot(NewRoot); 6279 6280 // i indexes lowered arguments. Bump it past the hidden sret argument. 6281 // Idx indexes LLVM arguments. Don't touch it. 6282 ++i; 6283 } 6284 6285 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6286 ++I, ++Idx) { 6287 SmallVector<SDValue, 4> ArgValues; 6288 SmallVector<EVT, 4> ValueVTs; 6289 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6290 unsigned NumValues = ValueVTs.size(); 6291 6292 // If this argument is unused then remember its value. It is used to generate 6293 // debugging information. 6294 if (I->use_empty() && NumValues) 6295 SDB->setUnusedArgValue(I, InVals[i]); 6296 6297 for (unsigned Value = 0; Value != NumValues; ++Value) { 6298 EVT VT = ValueVTs[Value]; 6299 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6300 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6301 6302 if (!I->use_empty()) { 6303 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6304 if (F.paramHasAttr(Idx, Attribute::SExt)) 6305 AssertOp = ISD::AssertSext; 6306 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6307 AssertOp = ISD::AssertZext; 6308 6309 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6310 NumParts, PartVT, VT, 6311 AssertOp)); 6312 } 6313 6314 i += NumParts; 6315 } 6316 6317 // Note down frame index for byval arguments. 6318 if (I->hasByValAttr() && !ArgValues.empty()) 6319 if (FrameIndexSDNode *FI = 6320 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6321 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6322 6323 if (!I->use_empty()) { 6324 SDValue Res; 6325 if (!ArgValues.empty()) 6326 Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6327 SDB->getCurDebugLoc()); 6328 SDB->setValue(I, Res); 6329 6330 // If this argument is live outside of the entry block, insert a copy from 6331 // whereever we got it to the vreg that other BB's will reference it as. 6332 SDB->CopyToExportRegsIfNeeded(I); 6333 } 6334 } 6335 6336 assert(i == InVals.size() && "Argument register count mismatch!"); 6337 6338 // Finally, if the target has anything special to do, allow it to do so. 6339 // FIXME: this should insert code into the DAG! 6340 EmitFunctionEntryCode(); 6341} 6342 6343/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6344/// ensure constants are generated when needed. Remember the virtual registers 6345/// that need to be added to the Machine PHI nodes as input. We cannot just 6346/// directly add them, because expansion might result in multiple MBB's for one 6347/// BB. As such, the start of the BB might correspond to a different MBB than 6348/// the end. 6349/// 6350void 6351SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6352 const TerminatorInst *TI = LLVMBB->getTerminator(); 6353 6354 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6355 6356 // Check successor nodes' PHI nodes that expect a constant to be available 6357 // from this block. 6358 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6359 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6360 if (!isa<PHINode>(SuccBB->begin())) continue; 6361 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6362 6363 // If this terminator has multiple identical successors (common for 6364 // switches), only handle each succ once. 6365 if (!SuccsHandled.insert(SuccMBB)) continue; 6366 6367 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6368 6369 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6370 // nodes and Machine PHI nodes, but the incoming operands have not been 6371 // emitted yet. 6372 for (BasicBlock::const_iterator I = SuccBB->begin(); 6373 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6374 // Ignore dead phi's. 6375 if (PN->use_empty()) continue; 6376 6377 unsigned Reg; 6378 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6379 6380 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6381 unsigned &RegOut = ConstantsOut[C]; 6382 if (RegOut == 0) { 6383 RegOut = FuncInfo.CreateRegs(C->getType()); 6384 CopyValueToVirtualRegister(C, RegOut); 6385 } 6386 Reg = RegOut; 6387 } else { 6388 DenseMap<const Value *, unsigned>::iterator I = 6389 FuncInfo.ValueMap.find(PHIOp); 6390 if (I != FuncInfo.ValueMap.end()) 6391 Reg = I->second; 6392 else { 6393 assert(isa<AllocaInst>(PHIOp) && 6394 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6395 "Didn't codegen value into a register!??"); 6396 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6397 CopyValueToVirtualRegister(PHIOp, Reg); 6398 } 6399 } 6400 6401 // Remember that this register needs to added to the machine PHI node as 6402 // the input for this MBB. 6403 SmallVector<EVT, 4> ValueVTs; 6404 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6405 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6406 EVT VT = ValueVTs[vti]; 6407 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6408 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6409 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6410 Reg += NumRegisters; 6411 } 6412 } 6413 } 6414 ConstantsOut.clear(); 6415} 6416