SelectionDAGBuilder.cpp revision ce1cdac94207a3bdfeb6b3b1b666e588dfdc6c3d
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/PseudoSourceValue.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Analysis/DebugInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameLowering.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72// Limit the width of DAG chains. This is important in general to prevent 73// prevent DAG-based analysis from blowing up. For example, alias analysis and 74// load clustering may not complete in reasonable time. It is difficult to 75// recognize and avoid this situation within each individual analysis, and 76// future analyses are likely to have the same behavior. Limiting DAG width is 77// the safe approach, and will be especially important with global DAGs. 78// 79// MaxParallelChains default is arbitrarily high to avoid affecting 80// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81// sequence over this should have been converted to llvm.memcpy by the 82// frontend. It easy to induce this behavior with .ll code such as: 83// %buffer = alloca [4096 x i8] 84// %data = load [4096 x i8]* %argPtr 85// store [4096 x i8] %data, [4096 x i8]* %buffer 86static const unsigned MaxParallelChains = 64; 87 88static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92/// getCopyFromParts - Create a value that contains the specified legal parts 93/// combined into the value they represent. If the parts combine to a type 94/// larger then ValueVT then AssertOp can be used to specify whether the extra 95/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96/// (ISD::AssertSext). 97static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getIntPtrConstant(1)); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209 return SDValue(); 210} 211 212/// getCopyFromParts - Create a value that contains the specified legal parts 213/// combined into the value they represent. If the parts combine to a type 214/// larger then ValueVT then AssertOp can be used to specify whether the extra 215/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216/// (ISD::AssertSext). 217static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 284 } 285 286 assert(ValueVT.getVectorElementType() == PartVT && 287 ValueVT.getVectorNumElements() == 1 && 288 "Only trivial scalar-to-vector conversions should get here!"); 289 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 290} 291 292 293 294 295static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 296 SDValue Val, SDValue *Parts, unsigned NumParts, 297 EVT PartVT); 298 299/// getCopyToParts - Create a series of nodes that contain the specified value 300/// split into legal parts. If the parts contain more bits than Val, then, for 301/// integers, ExtendKind can be used to specify how to generate the extra bits. 302static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 303 SDValue Val, SDValue *Parts, unsigned NumParts, 304 EVT PartVT, 305 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 306 EVT ValueVT = Val.getValueType(); 307 308 // Handle the vector case separately. 309 if (ValueVT.isVector()) 310 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 311 312 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 313 unsigned PartBits = PartVT.getSizeInBits(); 314 unsigned OrigNumParts = NumParts; 315 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 316 317 if (NumParts == 0) 318 return; 319 320 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 321 if (PartVT == ValueVT) { 322 assert(NumParts == 1 && "No-op copy with multiple parts!"); 323 Parts[0] = Val; 324 return; 325 } 326 327 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 328 // If the parts cover more bits than the value has, promote the value. 329 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 330 assert(NumParts == 1 && "Do not know what to promote to!"); 331 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 332 } else { 333 assert(PartVT.isInteger() && ValueVT.isInteger() && 334 "Unknown mismatch!"); 335 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 336 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 337 } 338 } else if (PartBits == ValueVT.getSizeInBits()) { 339 // Different types of the same size. 340 assert(NumParts == 1 && PartVT != ValueVT); 341 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 342 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 343 // If the parts cover less bits than value has, truncate the value. 344 assert(PartVT.isInteger() && ValueVT.isInteger() && 345 "Unknown mismatch!"); 346 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 347 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 348 } 349 350 // The value may have changed - recompute ValueVT. 351 ValueVT = Val.getValueType(); 352 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 353 "Failed to tile the value with PartVT!"); 354 355 if (NumParts == 1) { 356 assert(PartVT == ValueVT && "Type conversion failed!"); 357 Parts[0] = Val; 358 return; 359 } 360 361 // Expand the value into multiple parts. 362 if (NumParts & (NumParts - 1)) { 363 // The number of parts is not a power of 2. Split off and copy the tail. 364 assert(PartVT.isInteger() && ValueVT.isInteger() && 365 "Do not know what to expand to!"); 366 unsigned RoundParts = 1 << Log2_32(NumParts); 367 unsigned RoundBits = RoundParts * PartBits; 368 unsigned OddParts = NumParts - RoundParts; 369 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 370 DAG.getIntPtrConstant(RoundBits)); 371 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 372 373 if (TLI.isBigEndian()) 374 // The odd parts were reversed by getCopyToParts - unreverse them. 375 std::reverse(Parts + RoundParts, Parts + NumParts); 376 377 NumParts = RoundParts; 378 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 379 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 380 } 381 382 // The number of parts is a power of 2. Repeatedly bisect the value using 383 // EXTRACT_ELEMENT. 384 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 385 EVT::getIntegerVT(*DAG.getContext(), 386 ValueVT.getSizeInBits()), 387 Val); 388 389 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 390 for (unsigned i = 0; i < NumParts; i += StepSize) { 391 unsigned ThisBits = StepSize * PartBits / 2; 392 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 393 SDValue &Part0 = Parts[i]; 394 SDValue &Part1 = Parts[i+StepSize/2]; 395 396 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 397 ThisVT, Part0, DAG.getIntPtrConstant(1)); 398 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 399 ThisVT, Part0, DAG.getIntPtrConstant(0)); 400 401 if (ThisBits == PartBits && ThisVT != PartVT) { 402 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 403 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 404 } 405 } 406 } 407 408 if (TLI.isBigEndian()) 409 std::reverse(Parts, Parts + OrigNumParts); 410} 411 412 413/// getCopyToPartsVector - Create a series of nodes that contain the specified 414/// value split into legal parts. 415static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 416 SDValue Val, SDValue *Parts, unsigned NumParts, 417 EVT PartVT) { 418 EVT ValueVT = Val.getValueType(); 419 assert(ValueVT.isVector() && "Not a vector"); 420 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 421 422 if (NumParts == 1) { 423 if (PartVT == ValueVT) { 424 // Nothing to do. 425 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 426 // Bitconvert vector->vector case. 427 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 428 } else if (PartVT.isVector() && 429 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&& 430 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 431 EVT ElementVT = PartVT.getVectorElementType(); 432 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 433 // undef elements. 434 SmallVector<SDValue, 16> Ops; 435 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 436 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 437 ElementVT, Val, DAG.getIntPtrConstant(i))); 438 439 for (unsigned i = ValueVT.getVectorNumElements(), 440 e = PartVT.getVectorNumElements(); i != e; ++i) 441 Ops.push_back(DAG.getUNDEF(ElementVT)); 442 443 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 444 445 // FIXME: Use CONCAT for 2x -> 4x. 446 447 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 448 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 449 } else { 450 // Vector -> scalar conversion. 451 assert(ValueVT.getVectorElementType() == PartVT && 452 ValueVT.getVectorNumElements() == 1 && 453 "Only trivial vector-to-scalar conversions should get here!"); 454 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 455 PartVT, Val, DAG.getIntPtrConstant(0)); 456 } 457 458 Parts[0] = Val; 459 return; 460 } 461 462 // Handle a multi-element vector. 463 EVT IntermediateVT, RegisterVT; 464 unsigned NumIntermediates; 465 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 466 IntermediateVT, 467 NumIntermediates, RegisterVT); 468 unsigned NumElements = ValueVT.getVectorNumElements(); 469 470 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 471 NumParts = NumRegs; // Silence a compiler warning. 472 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 473 474 // Split the vector into intermediate operands. 475 SmallVector<SDValue, 8> Ops(NumIntermediates); 476 for (unsigned i = 0; i != NumIntermediates; ++i) { 477 if (IntermediateVT.isVector()) 478 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 479 IntermediateVT, Val, 480 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 481 else 482 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 483 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 484 } 485 486 // Split the intermediate operands into legal parts. 487 if (NumParts == NumIntermediates) { 488 // If the register was not expanded, promote or copy the value, 489 // as appropriate. 490 for (unsigned i = 0; i != NumParts; ++i) 491 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 492 } else if (NumParts > 0) { 493 // If the intermediate type was expanded, split each the value into 494 // legal parts. 495 assert(NumParts % NumIntermediates == 0 && 496 "Must expand into a divisible number of parts!"); 497 unsigned Factor = NumParts / NumIntermediates; 498 for (unsigned i = 0; i != NumIntermediates; ++i) 499 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 500 } 501} 502 503 504 505 506namespace { 507 /// RegsForValue - This struct represents the registers (physical or virtual) 508 /// that a particular set of values is assigned, and the type information 509 /// about the value. The most common situation is to represent one value at a 510 /// time, but struct or array values are handled element-wise as multiple 511 /// values. The splitting of aggregates is performed recursively, so that we 512 /// never have aggregate-typed registers. The values at this point do not 513 /// necessarily have legal types, so each value may require one or more 514 /// registers of some legal type. 515 /// 516 struct RegsForValue { 517 /// ValueVTs - The value types of the values, which may not be legal, and 518 /// may need be promoted or synthesized from one or more registers. 519 /// 520 SmallVector<EVT, 4> ValueVTs; 521 522 /// RegVTs - The value types of the registers. This is the same size as 523 /// ValueVTs and it records, for each value, what the type of the assigned 524 /// register or registers are. (Individual values are never synthesized 525 /// from more than one type of register.) 526 /// 527 /// With virtual registers, the contents of RegVTs is redundant with TLI's 528 /// getRegisterType member function, however when with physical registers 529 /// it is necessary to have a separate record of the types. 530 /// 531 SmallVector<EVT, 4> RegVTs; 532 533 /// Regs - This list holds the registers assigned to the values. 534 /// Each legal or promoted value requires one register, and each 535 /// expanded value requires multiple registers. 536 /// 537 SmallVector<unsigned, 4> Regs; 538 539 RegsForValue() {} 540 541 RegsForValue(const SmallVector<unsigned, 4> ®s, 542 EVT regvt, EVT valuevt) 543 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 544 545 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 546 unsigned Reg, const Type *Ty) { 547 ComputeValueVTs(tli, Ty, ValueVTs); 548 549 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 550 EVT ValueVT = ValueVTs[Value]; 551 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 552 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 553 for (unsigned i = 0; i != NumRegs; ++i) 554 Regs.push_back(Reg + i); 555 RegVTs.push_back(RegisterVT); 556 Reg += NumRegs; 557 } 558 } 559 560 /// areValueTypesLegal - Return true if types of all the values are legal. 561 bool areValueTypesLegal(const TargetLowering &TLI) { 562 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 563 EVT RegisterVT = RegVTs[Value]; 564 if (!TLI.isTypeLegal(RegisterVT)) 565 return false; 566 } 567 return true; 568 } 569 570 /// append - Add the specified values to this one. 571 void append(const RegsForValue &RHS) { 572 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 573 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 574 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 575 } 576 577 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 578 /// this value and returns the result as a ValueVTs value. This uses 579 /// Chain/Flag as the input and updates them for the output Chain/Flag. 580 /// If the Flag pointer is NULL, no flag is used. 581 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 582 DebugLoc dl, 583 SDValue &Chain, SDValue *Flag) const; 584 585 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 586 /// specified value into the registers specified by this object. This uses 587 /// Chain/Flag as the input and updates them for the output Chain/Flag. 588 /// If the Flag pointer is NULL, no flag is used. 589 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 590 SDValue &Chain, SDValue *Flag) const; 591 592 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 593 /// operand list. This adds the code marker, matching input operand index 594 /// (if applicable), and includes the number of values added into it. 595 void AddInlineAsmOperands(unsigned Kind, 596 bool HasMatching, unsigned MatchingIdx, 597 SelectionDAG &DAG, 598 std::vector<SDValue> &Ops) const; 599 }; 600} 601 602/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 603/// this value and returns the result as a ValueVT value. This uses 604/// Chain/Flag as the input and updates them for the output Chain/Flag. 605/// If the Flag pointer is NULL, no flag is used. 606SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 607 FunctionLoweringInfo &FuncInfo, 608 DebugLoc dl, 609 SDValue &Chain, SDValue *Flag) const { 610 // A Value with type {} or [0 x %t] needs no registers. 611 if (ValueVTs.empty()) 612 return SDValue(); 613 614 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 615 616 // Assemble the legal parts into the final values. 617 SmallVector<SDValue, 4> Values(ValueVTs.size()); 618 SmallVector<SDValue, 8> Parts; 619 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 620 // Copy the legal parts from the registers. 621 EVT ValueVT = ValueVTs[Value]; 622 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 623 EVT RegisterVT = RegVTs[Value]; 624 625 Parts.resize(NumRegs); 626 for (unsigned i = 0; i != NumRegs; ++i) { 627 SDValue P; 628 if (Flag == 0) { 629 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 630 } else { 631 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 632 *Flag = P.getValue(2); 633 } 634 635 Chain = P.getValue(1); 636 Parts[i] = P; 637 638 // If the source register was virtual and if we know something about it, 639 // add an assert node. 640 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 641 !RegisterVT.isInteger() || RegisterVT.isVector()) 642 continue; 643 644 const FunctionLoweringInfo::LiveOutInfo *LOI = 645 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 646 if (!LOI) 647 continue; 648 649 unsigned RegSize = RegisterVT.getSizeInBits(); 650 unsigned NumSignBits = LOI->NumSignBits; 651 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 652 653 // FIXME: We capture more information than the dag can represent. For 654 // now, just use the tightest assertzext/assertsext possible. 655 bool isSExt = true; 656 EVT FromVT(MVT::Other); 657 if (NumSignBits == RegSize) 658 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 659 else if (NumZeroBits >= RegSize-1) 660 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 661 else if (NumSignBits > RegSize-8) 662 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 663 else if (NumZeroBits >= RegSize-8) 664 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 665 else if (NumSignBits > RegSize-16) 666 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 667 else if (NumZeroBits >= RegSize-16) 668 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 669 else if (NumSignBits > RegSize-32) 670 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 671 else if (NumZeroBits >= RegSize-32) 672 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 673 else 674 continue; 675 676 // Add an assertion node. 677 assert(FromVT != MVT::Other); 678 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 679 RegisterVT, P, DAG.getValueType(FromVT)); 680 } 681 682 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 683 NumRegs, RegisterVT, ValueVT); 684 Part += NumRegs; 685 Parts.clear(); 686 } 687 688 return DAG.getNode(ISD::MERGE_VALUES, dl, 689 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 690 &Values[0], ValueVTs.size()); 691} 692 693/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 694/// specified value into the registers specified by this object. This uses 695/// Chain/Flag as the input and updates them for the output Chain/Flag. 696/// If the Flag pointer is NULL, no flag is used. 697void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 698 SDValue &Chain, SDValue *Flag) const { 699 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 700 701 // Get the list of the values's legal parts. 702 unsigned NumRegs = Regs.size(); 703 SmallVector<SDValue, 8> Parts(NumRegs); 704 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 705 EVT ValueVT = ValueVTs[Value]; 706 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 707 EVT RegisterVT = RegVTs[Value]; 708 709 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 710 &Parts[Part], NumParts, RegisterVT); 711 Part += NumParts; 712 } 713 714 // Copy the parts into the registers. 715 SmallVector<SDValue, 8> Chains(NumRegs); 716 for (unsigned i = 0; i != NumRegs; ++i) { 717 SDValue Part; 718 if (Flag == 0) { 719 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 720 } else { 721 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 722 *Flag = Part.getValue(1); 723 } 724 725 Chains[i] = Part.getValue(0); 726 } 727 728 if (NumRegs == 1 || Flag) 729 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 730 // flagged to it. That is the CopyToReg nodes and the user are considered 731 // a single scheduling unit. If we create a TokenFactor and return it as 732 // chain, then the TokenFactor is both a predecessor (operand) of the 733 // user as well as a successor (the TF operands are flagged to the user). 734 // c1, f1 = CopyToReg 735 // c2, f2 = CopyToReg 736 // c3 = TokenFactor c1, c2 737 // ... 738 // = op c3, ..., f2 739 Chain = Chains[NumRegs-1]; 740 else 741 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 742} 743 744/// AddInlineAsmOperands - Add this value to the specified inlineasm node 745/// operand list. This adds the code marker and includes the number of 746/// values added into it. 747void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 748 unsigned MatchingIdx, 749 SelectionDAG &DAG, 750 std::vector<SDValue> &Ops) const { 751 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 752 753 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 754 if (HasMatching) 755 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 756 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 757 Ops.push_back(Res); 758 759 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 760 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 761 EVT RegisterVT = RegVTs[Value]; 762 for (unsigned i = 0; i != NumRegs; ++i) { 763 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 764 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 765 } 766 } 767} 768 769void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 770 AA = &aa; 771 GFI = gfi; 772 TD = DAG.getTarget().getTargetData(); 773} 774 775/// clear - Clear out the current SelectionDAG and the associated 776/// state and prepare this SelectionDAGBuilder object to be used 777/// for a new block. This doesn't clear out information about 778/// additional blocks that are needed to complete switch lowering 779/// or PHI node updating; that information is cleared out as it is 780/// consumed. 781void SelectionDAGBuilder::clear() { 782 NodeMap.clear(); 783 UnusedArgNodeMap.clear(); 784 PendingLoads.clear(); 785 PendingExports.clear(); 786 DanglingDebugInfoMap.clear(); 787 CurDebugLoc = DebugLoc(); 788 HasTailCall = false; 789} 790 791/// getRoot - Return the current virtual root of the Selection DAG, 792/// flushing any PendingLoad items. This must be done before emitting 793/// a store or any other node that may need to be ordered after any 794/// prior load instructions. 795/// 796SDValue SelectionDAGBuilder::getRoot() { 797 if (PendingLoads.empty()) 798 return DAG.getRoot(); 799 800 if (PendingLoads.size() == 1) { 801 SDValue Root = PendingLoads[0]; 802 DAG.setRoot(Root); 803 PendingLoads.clear(); 804 return Root; 805 } 806 807 // Otherwise, we have to make a token factor node. 808 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 809 &PendingLoads[0], PendingLoads.size()); 810 PendingLoads.clear(); 811 DAG.setRoot(Root); 812 return Root; 813} 814 815/// getControlRoot - Similar to getRoot, but instead of flushing all the 816/// PendingLoad items, flush all the PendingExports items. It is necessary 817/// to do this before emitting a terminator instruction. 818/// 819SDValue SelectionDAGBuilder::getControlRoot() { 820 SDValue Root = DAG.getRoot(); 821 822 if (PendingExports.empty()) 823 return Root; 824 825 // Turn all of the CopyToReg chains into one factored node. 826 if (Root.getOpcode() != ISD::EntryToken) { 827 unsigned i = 0, e = PendingExports.size(); 828 for (; i != e; ++i) { 829 assert(PendingExports[i].getNode()->getNumOperands() > 1); 830 if (PendingExports[i].getNode()->getOperand(0) == Root) 831 break; // Don't add the root if we already indirectly depend on it. 832 } 833 834 if (i == e) 835 PendingExports.push_back(Root); 836 } 837 838 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 839 &PendingExports[0], 840 PendingExports.size()); 841 PendingExports.clear(); 842 DAG.setRoot(Root); 843 return Root; 844} 845 846void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 847 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 848 DAG.AssignOrdering(Node, SDNodeOrder); 849 850 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 851 AssignOrderingToNode(Node->getOperand(I).getNode()); 852} 853 854void SelectionDAGBuilder::visit(const Instruction &I) { 855 // Set up outgoing PHI node register values before emitting the terminator. 856 if (isa<TerminatorInst>(&I)) 857 HandlePHINodesInSuccessorBlocks(I.getParent()); 858 859 CurDebugLoc = I.getDebugLoc(); 860 861 visit(I.getOpcode(), I); 862 863 if (!isa<TerminatorInst>(&I) && !HasTailCall) 864 CopyToExportRegsIfNeeded(&I); 865 866 CurDebugLoc = DebugLoc(); 867} 868 869void SelectionDAGBuilder::visitPHI(const PHINode &) { 870 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 871} 872 873void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 874 // Note: this doesn't use InstVisitor, because it has to work with 875 // ConstantExpr's in addition to instructions. 876 switch (Opcode) { 877 default: llvm_unreachable("Unknown instruction type encountered!"); 878 // Build the switch statement using the Instruction.def file. 879#define HANDLE_INST(NUM, OPCODE, CLASS) \ 880 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 881#include "llvm/Instruction.def" 882 } 883 884 // Assign the ordering to the freshly created DAG nodes. 885 if (NodeMap.count(&I)) { 886 ++SDNodeOrder; 887 AssignOrderingToNode(getValue(&I).getNode()); 888 } 889} 890 891// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 892// generate the debug data structures now that we've seen its definition. 893void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 894 SDValue Val) { 895 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 896 if (DDI.getDI()) { 897 const DbgValueInst *DI = DDI.getDI(); 898 DebugLoc dl = DDI.getdl(); 899 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 900 MDNode *Variable = DI->getVariable(); 901 uint64_t Offset = DI->getOffset(); 902 SDDbgValue *SDV; 903 if (Val.getNode()) { 904 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 905 SDV = DAG.getDbgValue(Variable, Val.getNode(), 906 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 907 DAG.AddDbgValue(SDV, Val.getNode(), false); 908 } 909 } else 910 DEBUG(dbgs() << "Dropping debug info for " << DI); 911 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 912 } 913} 914 915// getValue - Return an SDValue for the given Value. 916SDValue SelectionDAGBuilder::getValue(const Value *V) { 917 // If we already have an SDValue for this value, use it. It's important 918 // to do this first, so that we don't create a CopyFromReg if we already 919 // have a regular SDValue. 920 SDValue &N = NodeMap[V]; 921 if (N.getNode()) return N; 922 923 // If there's a virtual register allocated and initialized for this 924 // value, use it. 925 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 926 if (It != FuncInfo.ValueMap.end()) { 927 unsigned InReg = It->second; 928 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 929 SDValue Chain = DAG.getEntryNode(); 930 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 931 resolveDanglingDebugInfo(V, N); 932 return N; 933 } 934 935 // Otherwise create a new SDValue and remember it. 936 SDValue Val = getValueImpl(V); 937 NodeMap[V] = Val; 938 resolveDanglingDebugInfo(V, Val); 939 return Val; 940} 941 942/// getNonRegisterValue - Return an SDValue for the given Value, but 943/// don't look in FuncInfo.ValueMap for a virtual register. 944SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 945 // If we already have an SDValue for this value, use it. 946 SDValue &N = NodeMap[V]; 947 if (N.getNode()) return N; 948 949 // Otherwise create a new SDValue and remember it. 950 SDValue Val = getValueImpl(V); 951 NodeMap[V] = Val; 952 resolveDanglingDebugInfo(V, Val); 953 return Val; 954} 955 956/// getValueImpl - Helper function for getValue and getNonRegisterValue. 957/// Create an SDValue for the given value. 958SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 959 if (const Constant *C = dyn_cast<Constant>(V)) { 960 EVT VT = TLI.getValueType(V->getType(), true); 961 962 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 963 return DAG.getConstant(*CI, VT); 964 965 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 966 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 967 968 if (isa<ConstantPointerNull>(C)) 969 return DAG.getConstant(0, TLI.getPointerTy()); 970 971 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 972 return DAG.getConstantFP(*CFP, VT); 973 974 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 975 return DAG.getUNDEF(VT); 976 977 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 978 visit(CE->getOpcode(), *CE); 979 SDValue N1 = NodeMap[V]; 980 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 981 return N1; 982 } 983 984 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 985 SmallVector<SDValue, 4> Constants; 986 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 987 OI != OE; ++OI) { 988 SDNode *Val = getValue(*OI).getNode(); 989 // If the operand is an empty aggregate, there are no values. 990 if (!Val) continue; 991 // Add each leaf value from the operand to the Constants list 992 // to form a flattened list of all the values. 993 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 994 Constants.push_back(SDValue(Val, i)); 995 } 996 997 return DAG.getMergeValues(&Constants[0], Constants.size(), 998 getCurDebugLoc()); 999 } 1000 1001 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1002 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1003 "Unknown struct or array constant!"); 1004 1005 SmallVector<EVT, 4> ValueVTs; 1006 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1007 unsigned NumElts = ValueVTs.size(); 1008 if (NumElts == 0) 1009 return SDValue(); // empty struct 1010 SmallVector<SDValue, 4> Constants(NumElts); 1011 for (unsigned i = 0; i != NumElts; ++i) { 1012 EVT EltVT = ValueVTs[i]; 1013 if (isa<UndefValue>(C)) 1014 Constants[i] = DAG.getUNDEF(EltVT); 1015 else if (EltVT.isFloatingPoint()) 1016 Constants[i] = DAG.getConstantFP(0, EltVT); 1017 else 1018 Constants[i] = DAG.getConstant(0, EltVT); 1019 } 1020 1021 return DAG.getMergeValues(&Constants[0], NumElts, 1022 getCurDebugLoc()); 1023 } 1024 1025 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1026 return DAG.getBlockAddress(BA, VT); 1027 1028 const VectorType *VecTy = cast<VectorType>(V->getType()); 1029 unsigned NumElements = VecTy->getNumElements(); 1030 1031 // Now that we know the number and type of the elements, get that number of 1032 // elements into the Ops array based on what kind of constant it is. 1033 SmallVector<SDValue, 16> Ops; 1034 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1035 for (unsigned i = 0; i != NumElements; ++i) 1036 Ops.push_back(getValue(CP->getOperand(i))); 1037 } else { 1038 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1039 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1040 1041 SDValue Op; 1042 if (EltVT.isFloatingPoint()) 1043 Op = DAG.getConstantFP(0, EltVT); 1044 else 1045 Op = DAG.getConstant(0, EltVT); 1046 Ops.assign(NumElements, Op); 1047 } 1048 1049 // Create a BUILD_VECTOR node. 1050 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1051 VT, &Ops[0], Ops.size()); 1052 } 1053 1054 // If this is a static alloca, generate it as the frameindex instead of 1055 // computation. 1056 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1057 DenseMap<const AllocaInst*, int>::iterator SI = 1058 FuncInfo.StaticAllocaMap.find(AI); 1059 if (SI != FuncInfo.StaticAllocaMap.end()) 1060 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1061 } 1062 1063 // If this is an instruction which fast-isel has deferred, select it now. 1064 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1065 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1066 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1067 SDValue Chain = DAG.getEntryNode(); 1068 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1069 } 1070 1071 llvm_unreachable("Can't get register for value!"); 1072 return SDValue(); 1073} 1074 1075void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1076 SDValue Chain = getControlRoot(); 1077 SmallVector<ISD::OutputArg, 8> Outs; 1078 SmallVector<SDValue, 8> OutVals; 1079 1080 if (!FuncInfo.CanLowerReturn) { 1081 unsigned DemoteReg = FuncInfo.DemoteRegister; 1082 const Function *F = I.getParent()->getParent(); 1083 1084 // Emit a store of the return value through the virtual register. 1085 // Leave Outs empty so that LowerReturn won't try to load return 1086 // registers the usual way. 1087 SmallVector<EVT, 1> PtrValueVTs; 1088 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1089 PtrValueVTs); 1090 1091 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1092 SDValue RetOp = getValue(I.getOperand(0)); 1093 1094 SmallVector<EVT, 4> ValueVTs; 1095 SmallVector<uint64_t, 4> Offsets; 1096 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1097 unsigned NumValues = ValueVTs.size(); 1098 1099 SmallVector<SDValue, 4> Chains(NumValues); 1100 for (unsigned i = 0; i != NumValues; ++i) { 1101 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1102 RetPtr.getValueType(), RetPtr, 1103 DAG.getIntPtrConstant(Offsets[i])); 1104 Chains[i] = 1105 DAG.getStore(Chain, getCurDebugLoc(), 1106 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1107 // FIXME: better loc info would be nice. 1108 Add, MachinePointerInfo(), false, false, 0); 1109 } 1110 1111 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1112 MVT::Other, &Chains[0], NumValues); 1113 } else if (I.getNumOperands() != 0) { 1114 SmallVector<EVT, 4> ValueVTs; 1115 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1116 unsigned NumValues = ValueVTs.size(); 1117 if (NumValues) { 1118 SDValue RetOp = getValue(I.getOperand(0)); 1119 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1120 EVT VT = ValueVTs[j]; 1121 1122 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1123 1124 const Function *F = I.getParent()->getParent(); 1125 if (F->paramHasAttr(0, Attribute::SExt)) 1126 ExtendKind = ISD::SIGN_EXTEND; 1127 else if (F->paramHasAttr(0, Attribute::ZExt)) 1128 ExtendKind = ISD::ZERO_EXTEND; 1129 1130 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1131 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1132 1133 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1134 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1135 SmallVector<SDValue, 4> Parts(NumParts); 1136 getCopyToParts(DAG, getCurDebugLoc(), 1137 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1138 &Parts[0], NumParts, PartVT, ExtendKind); 1139 1140 // 'inreg' on function refers to return value 1141 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1142 if (F->paramHasAttr(0, Attribute::InReg)) 1143 Flags.setInReg(); 1144 1145 // Propagate extension type if any 1146 if (ExtendKind == ISD::SIGN_EXTEND) 1147 Flags.setSExt(); 1148 else if (ExtendKind == ISD::ZERO_EXTEND) 1149 Flags.setZExt(); 1150 1151 for (unsigned i = 0; i < NumParts; ++i) { 1152 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1153 /*isfixed=*/true)); 1154 OutVals.push_back(Parts[i]); 1155 } 1156 } 1157 } 1158 } 1159 1160 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1161 CallingConv::ID CallConv = 1162 DAG.getMachineFunction().getFunction()->getCallingConv(); 1163 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1164 Outs, OutVals, getCurDebugLoc(), DAG); 1165 1166 // Verify that the target's LowerReturn behaved as expected. 1167 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1168 "LowerReturn didn't return a valid chain!"); 1169 1170 // Update the DAG with the new chain value resulting from return lowering. 1171 DAG.setRoot(Chain); 1172} 1173 1174/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1175/// created for it, emit nodes to copy the value into the virtual 1176/// registers. 1177void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1178 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1179 if (VMI != FuncInfo.ValueMap.end()) { 1180 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1181 CopyValueToVirtualRegister(V, VMI->second); 1182 } 1183} 1184 1185/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1186/// the current basic block, add it to ValueMap now so that we'll get a 1187/// CopyTo/FromReg. 1188void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1189 // No need to export constants. 1190 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1191 1192 // Already exported? 1193 if (FuncInfo.isExportedInst(V)) return; 1194 1195 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1196 CopyValueToVirtualRegister(V, Reg); 1197} 1198 1199bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1200 const BasicBlock *FromBB) { 1201 // The operands of the setcc have to be in this block. We don't know 1202 // how to export them from some other block. 1203 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1204 // Can export from current BB. 1205 if (VI->getParent() == FromBB) 1206 return true; 1207 1208 // Is already exported, noop. 1209 return FuncInfo.isExportedInst(V); 1210 } 1211 1212 // If this is an argument, we can export it if the BB is the entry block or 1213 // if it is already exported. 1214 if (isa<Argument>(V)) { 1215 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1216 return true; 1217 1218 // Otherwise, can only export this if it is already exported. 1219 return FuncInfo.isExportedInst(V); 1220 } 1221 1222 // Otherwise, constants can always be exported. 1223 return true; 1224} 1225 1226static bool InBlock(const Value *V, const BasicBlock *BB) { 1227 if (const Instruction *I = dyn_cast<Instruction>(V)) 1228 return I->getParent() == BB; 1229 return true; 1230} 1231 1232/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1233/// This function emits a branch and is used at the leaves of an OR or an 1234/// AND operator tree. 1235/// 1236void 1237SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1238 MachineBasicBlock *TBB, 1239 MachineBasicBlock *FBB, 1240 MachineBasicBlock *CurBB, 1241 MachineBasicBlock *SwitchBB) { 1242 const BasicBlock *BB = CurBB->getBasicBlock(); 1243 1244 // If the leaf of the tree is a comparison, merge the condition into 1245 // the caseblock. 1246 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1247 // The operands of the cmp have to be in this block. We don't know 1248 // how to export them from some other block. If this is the first block 1249 // of the sequence, no exporting is needed. 1250 if (CurBB == SwitchBB || 1251 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1252 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1253 ISD::CondCode Condition; 1254 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1255 Condition = getICmpCondCode(IC->getPredicate()); 1256 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1257 Condition = getFCmpCondCode(FC->getPredicate()); 1258 } else { 1259 Condition = ISD::SETEQ; // silence warning. 1260 llvm_unreachable("Unknown compare instruction"); 1261 } 1262 1263 CaseBlock CB(Condition, BOp->getOperand(0), 1264 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1265 SwitchCases.push_back(CB); 1266 return; 1267 } 1268 } 1269 1270 // Create a CaseBlock record representing this branch. 1271 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1272 NULL, TBB, FBB, CurBB); 1273 SwitchCases.push_back(CB); 1274} 1275 1276/// FindMergedConditions - If Cond is an expression like 1277void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1278 MachineBasicBlock *TBB, 1279 MachineBasicBlock *FBB, 1280 MachineBasicBlock *CurBB, 1281 MachineBasicBlock *SwitchBB, 1282 unsigned Opc) { 1283 // If this node is not part of the or/and tree, emit it as a branch. 1284 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1285 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1286 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1287 BOp->getParent() != CurBB->getBasicBlock() || 1288 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1289 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1290 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1291 return; 1292 } 1293 1294 // Create TmpBB after CurBB. 1295 MachineFunction::iterator BBI = CurBB; 1296 MachineFunction &MF = DAG.getMachineFunction(); 1297 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1298 CurBB->getParent()->insert(++BBI, TmpBB); 1299 1300 if (Opc == Instruction::Or) { 1301 // Codegen X | Y as: 1302 // jmp_if_X TBB 1303 // jmp TmpBB 1304 // TmpBB: 1305 // jmp_if_Y TBB 1306 // jmp FBB 1307 // 1308 1309 // Emit the LHS condition. 1310 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1311 1312 // Emit the RHS condition into TmpBB. 1313 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1314 } else { 1315 assert(Opc == Instruction::And && "Unknown merge op!"); 1316 // Codegen X & Y as: 1317 // jmp_if_X TmpBB 1318 // jmp FBB 1319 // TmpBB: 1320 // jmp_if_Y TBB 1321 // jmp FBB 1322 // 1323 // This requires creation of TmpBB after CurBB. 1324 1325 // Emit the LHS condition. 1326 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1327 1328 // Emit the RHS condition into TmpBB. 1329 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1330 } 1331} 1332 1333/// If the set of cases should be emitted as a series of branches, return true. 1334/// If we should emit this as a bunch of and/or'd together conditions, return 1335/// false. 1336bool 1337SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1338 if (Cases.size() != 2) return true; 1339 1340 // If this is two comparisons of the same values or'd or and'd together, they 1341 // will get folded into a single comparison, so don't emit two blocks. 1342 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1343 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1344 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1345 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1346 return false; 1347 } 1348 1349 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1350 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1351 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1352 Cases[0].CC == Cases[1].CC && 1353 isa<Constant>(Cases[0].CmpRHS) && 1354 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1355 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1356 return false; 1357 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1358 return false; 1359 } 1360 1361 return true; 1362} 1363 1364void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1365 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1366 1367 // Update machine-CFG edges. 1368 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1369 1370 // Figure out which block is immediately after the current one. 1371 MachineBasicBlock *NextBlock = 0; 1372 MachineFunction::iterator BBI = BrMBB; 1373 if (++BBI != FuncInfo.MF->end()) 1374 NextBlock = BBI; 1375 1376 if (I.isUnconditional()) { 1377 // Update machine-CFG edges. 1378 BrMBB->addSuccessor(Succ0MBB); 1379 1380 // If this is not a fall-through branch, emit the branch. 1381 if (Succ0MBB != NextBlock) 1382 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1383 MVT::Other, getControlRoot(), 1384 DAG.getBasicBlock(Succ0MBB))); 1385 1386 return; 1387 } 1388 1389 // If this condition is one of the special cases we handle, do special stuff 1390 // now. 1391 const Value *CondVal = I.getCondition(); 1392 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1393 1394 // If this is a series of conditions that are or'd or and'd together, emit 1395 // this as a sequence of branches instead of setcc's with and/or operations. 1396 // As long as jumps are not expensive, this should improve performance. 1397 // For example, instead of something like: 1398 // cmp A, B 1399 // C = seteq 1400 // cmp D, E 1401 // F = setle 1402 // or C, F 1403 // jnz foo 1404 // Emit: 1405 // cmp A, B 1406 // je foo 1407 // cmp D, E 1408 // jle foo 1409 // 1410 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1411 if (!TLI.isJumpExpensive() && 1412 BOp->hasOneUse() && 1413 (BOp->getOpcode() == Instruction::And || 1414 BOp->getOpcode() == Instruction::Or)) { 1415 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1416 BOp->getOpcode()); 1417 // If the compares in later blocks need to use values not currently 1418 // exported from this block, export them now. This block should always 1419 // be the first entry. 1420 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1421 1422 // Allow some cases to be rejected. 1423 if (ShouldEmitAsBranches(SwitchCases)) { 1424 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1425 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1426 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1427 } 1428 1429 // Emit the branch for this block. 1430 visitSwitchCase(SwitchCases[0], BrMBB); 1431 SwitchCases.erase(SwitchCases.begin()); 1432 return; 1433 } 1434 1435 // Okay, we decided not to do this, remove any inserted MBB's and clear 1436 // SwitchCases. 1437 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1438 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1439 1440 SwitchCases.clear(); 1441 } 1442 } 1443 1444 // Create a CaseBlock record representing this branch. 1445 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1446 NULL, Succ0MBB, Succ1MBB, BrMBB); 1447 1448 // Use visitSwitchCase to actually insert the fast branch sequence for this 1449 // cond branch. 1450 visitSwitchCase(CB, BrMBB); 1451} 1452 1453/// visitSwitchCase - Emits the necessary code to represent a single node in 1454/// the binary search tree resulting from lowering a switch instruction. 1455void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1456 MachineBasicBlock *SwitchBB) { 1457 SDValue Cond; 1458 SDValue CondLHS = getValue(CB.CmpLHS); 1459 DebugLoc dl = getCurDebugLoc(); 1460 1461 // Build the setcc now. 1462 if (CB.CmpMHS == NULL) { 1463 // Fold "(X == true)" to X and "(X == false)" to !X to 1464 // handle common cases produced by branch lowering. 1465 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1466 CB.CC == ISD::SETEQ) 1467 Cond = CondLHS; 1468 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1469 CB.CC == ISD::SETEQ) { 1470 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1471 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1472 } else 1473 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1474 } else { 1475 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1476 1477 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1478 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1479 1480 SDValue CmpOp = getValue(CB.CmpMHS); 1481 EVT VT = CmpOp.getValueType(); 1482 1483 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1484 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1485 ISD::SETLE); 1486 } else { 1487 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1488 VT, CmpOp, DAG.getConstant(Low, VT)); 1489 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1490 DAG.getConstant(High-Low, VT), ISD::SETULE); 1491 } 1492 } 1493 1494 // Update successor info 1495 SwitchBB->addSuccessor(CB.TrueBB); 1496 SwitchBB->addSuccessor(CB.FalseBB); 1497 1498 // Set NextBlock to be the MBB immediately after the current one, if any. 1499 // This is used to avoid emitting unnecessary branches to the next block. 1500 MachineBasicBlock *NextBlock = 0; 1501 MachineFunction::iterator BBI = SwitchBB; 1502 if (++BBI != FuncInfo.MF->end()) 1503 NextBlock = BBI; 1504 1505 // If the lhs block is the next block, invert the condition so that we can 1506 // fall through to the lhs instead of the rhs block. 1507 if (CB.TrueBB == NextBlock) { 1508 std::swap(CB.TrueBB, CB.FalseBB); 1509 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1510 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1511 } 1512 1513 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1514 MVT::Other, getControlRoot(), Cond, 1515 DAG.getBasicBlock(CB.TrueBB)); 1516 1517 // Insert the false branch. Do this even if it's a fall through branch, 1518 // this makes it easier to do DAG optimizations which require inverting 1519 // the branch condition. 1520 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1521 DAG.getBasicBlock(CB.FalseBB)); 1522 1523 DAG.setRoot(BrCond); 1524} 1525 1526/// visitJumpTable - Emit JumpTable node in the current MBB 1527void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1528 // Emit the code for the jump table 1529 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1530 EVT PTy = TLI.getPointerTy(); 1531 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1532 JT.Reg, PTy); 1533 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1534 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1535 MVT::Other, Index.getValue(1), 1536 Table, Index); 1537 DAG.setRoot(BrJumpTable); 1538} 1539 1540/// visitJumpTableHeader - This function emits necessary code to produce index 1541/// in the JumpTable from switch case. 1542void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1543 JumpTableHeader &JTH, 1544 MachineBasicBlock *SwitchBB) { 1545 // Subtract the lowest switch case value from the value being switched on and 1546 // conditional branch to default mbb if the result is greater than the 1547 // difference between smallest and largest cases. 1548 SDValue SwitchOp = getValue(JTH.SValue); 1549 EVT VT = SwitchOp.getValueType(); 1550 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1551 DAG.getConstant(JTH.First, VT)); 1552 1553 // The SDNode we just created, which holds the value being switched on minus 1554 // the smallest case value, needs to be copied to a virtual register so it 1555 // can be used as an index into the jump table in a subsequent basic block. 1556 // This value may be smaller or larger than the target's pointer type, and 1557 // therefore require extension or truncating. 1558 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1559 1560 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1561 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1562 JumpTableReg, SwitchOp); 1563 JT.Reg = JumpTableReg; 1564 1565 // Emit the range check for the jump table, and branch to the default block 1566 // for the switch statement if the value being switched on exceeds the largest 1567 // case in the switch. 1568 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1569 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1570 DAG.getConstant(JTH.Last-JTH.First,VT), 1571 ISD::SETUGT); 1572 1573 // Set NextBlock to be the MBB immediately after the current one, if any. 1574 // This is used to avoid emitting unnecessary branches to the next block. 1575 MachineBasicBlock *NextBlock = 0; 1576 MachineFunction::iterator BBI = SwitchBB; 1577 1578 if (++BBI != FuncInfo.MF->end()) 1579 NextBlock = BBI; 1580 1581 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1582 MVT::Other, CopyTo, CMP, 1583 DAG.getBasicBlock(JT.Default)); 1584 1585 if (JT.MBB != NextBlock) 1586 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1587 DAG.getBasicBlock(JT.MBB)); 1588 1589 DAG.setRoot(BrCond); 1590} 1591 1592/// visitBitTestHeader - This function emits necessary code to produce value 1593/// suitable for "bit tests" 1594void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1595 MachineBasicBlock *SwitchBB) { 1596 // Subtract the minimum value 1597 SDValue SwitchOp = getValue(B.SValue); 1598 EVT VT = SwitchOp.getValueType(); 1599 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1600 DAG.getConstant(B.First, VT)); 1601 1602 // Check range 1603 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1604 TLI.getSetCCResultType(Sub.getValueType()), 1605 Sub, DAG.getConstant(B.Range, VT), 1606 ISD::SETUGT); 1607 1608 // Determine the type of the test operands. 1609 bool UsePtrType = false; 1610 if (!TLI.isTypeLegal(VT)) 1611 UsePtrType = true; 1612 else { 1613 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1614 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) { 1615 // Switch table case range are encoded into series of masks. 1616 // Just use pointer type, it's guaranteed to fit. 1617 UsePtrType = true; 1618 break; 1619 } 1620 } 1621 if (UsePtrType) { 1622 VT = TLI.getPointerTy(); 1623 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1624 } 1625 1626 B.RegVT = VT; 1627 B.Reg = FuncInfo.CreateReg(VT); 1628 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1629 B.Reg, Sub); 1630 1631 // Set NextBlock to be the MBB immediately after the current one, if any. 1632 // This is used to avoid emitting unnecessary branches to the next block. 1633 MachineBasicBlock *NextBlock = 0; 1634 MachineFunction::iterator BBI = SwitchBB; 1635 if (++BBI != FuncInfo.MF->end()) 1636 NextBlock = BBI; 1637 1638 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1639 1640 SwitchBB->addSuccessor(B.Default); 1641 SwitchBB->addSuccessor(MBB); 1642 1643 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1644 MVT::Other, CopyTo, RangeCmp, 1645 DAG.getBasicBlock(B.Default)); 1646 1647 if (MBB != NextBlock) 1648 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1649 DAG.getBasicBlock(MBB)); 1650 1651 DAG.setRoot(BrRange); 1652} 1653 1654/// visitBitTestCase - this function produces one "bit test" 1655void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1656 MachineBasicBlock* NextMBB, 1657 unsigned Reg, 1658 BitTestCase &B, 1659 MachineBasicBlock *SwitchBB) { 1660 EVT VT = BB.RegVT; 1661 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1662 Reg, VT); 1663 SDValue Cmp; 1664 if (CountPopulation_64(B.Mask) == 1) { 1665 // Testing for a single bit; just compare the shift count with what it 1666 // would need to be to shift a 1 bit in that position. 1667 Cmp = DAG.getSetCC(getCurDebugLoc(), 1668 TLI.getSetCCResultType(VT), 1669 ShiftOp, 1670 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1671 ISD::SETEQ); 1672 } else { 1673 // Make desired shift 1674 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1675 DAG.getConstant(1, VT), ShiftOp); 1676 1677 // Emit bit tests and jumps 1678 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1679 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1680 Cmp = DAG.getSetCC(getCurDebugLoc(), 1681 TLI.getSetCCResultType(VT), 1682 AndOp, DAG.getConstant(0, VT), 1683 ISD::SETNE); 1684 } 1685 1686 SwitchBB->addSuccessor(B.TargetBB); 1687 SwitchBB->addSuccessor(NextMBB); 1688 1689 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1690 MVT::Other, getControlRoot(), 1691 Cmp, DAG.getBasicBlock(B.TargetBB)); 1692 1693 // Set NextBlock to be the MBB immediately after the current one, if any. 1694 // This is used to avoid emitting unnecessary branches to the next block. 1695 MachineBasicBlock *NextBlock = 0; 1696 MachineFunction::iterator BBI = SwitchBB; 1697 if (++BBI != FuncInfo.MF->end()) 1698 NextBlock = BBI; 1699 1700 if (NextMBB != NextBlock) 1701 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1702 DAG.getBasicBlock(NextMBB)); 1703 1704 DAG.setRoot(BrAnd); 1705} 1706 1707void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1708 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1709 1710 // Retrieve successors. 1711 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1712 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1713 1714 const Value *Callee(I.getCalledValue()); 1715 if (isa<InlineAsm>(Callee)) 1716 visitInlineAsm(&I); 1717 else 1718 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1719 1720 // If the value of the invoke is used outside of its defining block, make it 1721 // available as a virtual register. 1722 CopyToExportRegsIfNeeded(&I); 1723 1724 // Update successor info 1725 InvokeMBB->addSuccessor(Return); 1726 InvokeMBB->addSuccessor(LandingPad); 1727 1728 // Drop into normal successor. 1729 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1730 MVT::Other, getControlRoot(), 1731 DAG.getBasicBlock(Return))); 1732} 1733 1734void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1735} 1736 1737/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1738/// small case ranges). 1739bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1740 CaseRecVector& WorkList, 1741 const Value* SV, 1742 MachineBasicBlock *Default, 1743 MachineBasicBlock *SwitchBB) { 1744 Case& BackCase = *(CR.Range.second-1); 1745 1746 // Size is the number of Cases represented by this range. 1747 size_t Size = CR.Range.second - CR.Range.first; 1748 if (Size > 3) 1749 return false; 1750 1751 // Get the MachineFunction which holds the current MBB. This is used when 1752 // inserting any additional MBBs necessary to represent the switch. 1753 MachineFunction *CurMF = FuncInfo.MF; 1754 1755 // Figure out which block is immediately after the current one. 1756 MachineBasicBlock *NextBlock = 0; 1757 MachineFunction::iterator BBI = CR.CaseBB; 1758 1759 if (++BBI != FuncInfo.MF->end()) 1760 NextBlock = BBI; 1761 1762 // If any two of the cases has the same destination, and if one value 1763 // is the same as the other, but has one bit unset that the other has set, 1764 // use bit manipulation to do two compares at once. For example: 1765 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1766 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1767 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1768 if (Size == 2 && CR.CaseBB == SwitchBB) { 1769 Case &Small = *CR.Range.first; 1770 Case &Big = *(CR.Range.second-1); 1771 1772 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1773 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1774 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1775 1776 // Check that there is only one bit different. 1777 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1778 (SmallValue | BigValue) == BigValue) { 1779 // Isolate the common bit. 1780 APInt CommonBit = BigValue & ~SmallValue; 1781 assert((SmallValue | CommonBit) == BigValue && 1782 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1783 1784 SDValue CondLHS = getValue(SV); 1785 EVT VT = CondLHS.getValueType(); 1786 DebugLoc DL = getCurDebugLoc(); 1787 1788 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1789 DAG.getConstant(CommonBit, VT)); 1790 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1791 Or, DAG.getConstant(BigValue, VT), 1792 ISD::SETEQ); 1793 1794 // Update successor info. 1795 SwitchBB->addSuccessor(Small.BB); 1796 SwitchBB->addSuccessor(Default); 1797 1798 // Insert the true branch. 1799 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1800 getControlRoot(), Cond, 1801 DAG.getBasicBlock(Small.BB)); 1802 1803 // Insert the false branch. 1804 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1805 DAG.getBasicBlock(Default)); 1806 1807 DAG.setRoot(BrCond); 1808 return true; 1809 } 1810 } 1811 } 1812 1813 // Rearrange the case blocks so that the last one falls through if possible. 1814 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1815 // The last case block won't fall through into 'NextBlock' if we emit the 1816 // branches in this order. See if rearranging a case value would help. 1817 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1818 if (I->BB == NextBlock) { 1819 std::swap(*I, BackCase); 1820 break; 1821 } 1822 } 1823 } 1824 1825 // Create a CaseBlock record representing a conditional branch to 1826 // the Case's target mbb if the value being switched on SV is equal 1827 // to C. 1828 MachineBasicBlock *CurBlock = CR.CaseBB; 1829 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1830 MachineBasicBlock *FallThrough; 1831 if (I != E-1) { 1832 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1833 CurMF->insert(BBI, FallThrough); 1834 1835 // Put SV in a virtual register to make it available from the new blocks. 1836 ExportFromCurrentBlock(SV); 1837 } else { 1838 // If the last case doesn't match, go to the default block. 1839 FallThrough = Default; 1840 } 1841 1842 const Value *RHS, *LHS, *MHS; 1843 ISD::CondCode CC; 1844 if (I->High == I->Low) { 1845 // This is just small small case range :) containing exactly 1 case 1846 CC = ISD::SETEQ; 1847 LHS = SV; RHS = I->High; MHS = NULL; 1848 } else { 1849 CC = ISD::SETLE; 1850 LHS = I->Low; MHS = SV; RHS = I->High; 1851 } 1852 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1853 1854 // If emitting the first comparison, just call visitSwitchCase to emit the 1855 // code into the current block. Otherwise, push the CaseBlock onto the 1856 // vector to be later processed by SDISel, and insert the node's MBB 1857 // before the next MBB. 1858 if (CurBlock == SwitchBB) 1859 visitSwitchCase(CB, SwitchBB); 1860 else 1861 SwitchCases.push_back(CB); 1862 1863 CurBlock = FallThrough; 1864 } 1865 1866 return true; 1867} 1868 1869static inline bool areJTsAllowed(const TargetLowering &TLI) { 1870 return !DisableJumpTables && 1871 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1872 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1873} 1874 1875static APInt ComputeRange(const APInt &First, const APInt &Last) { 1876 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1877 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 1878 return (LastExt - FirstExt + 1ULL); 1879} 1880 1881/// handleJTSwitchCase - Emit jumptable for current switch case range 1882bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1883 CaseRecVector& WorkList, 1884 const Value* SV, 1885 MachineBasicBlock* Default, 1886 MachineBasicBlock *SwitchBB) { 1887 Case& FrontCase = *CR.Range.first; 1888 Case& BackCase = *(CR.Range.second-1); 1889 1890 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1891 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1892 1893 APInt TSize(First.getBitWidth(), 0); 1894 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1895 I!=E; ++I) 1896 TSize += I->size(); 1897 1898 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1899 return false; 1900 1901 APInt Range = ComputeRange(First, Last); 1902 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1903 if (Density < 0.4) 1904 return false; 1905 1906 DEBUG(dbgs() << "Lowering jump table\n" 1907 << "First entry: " << First << ". Last entry: " << Last << '\n' 1908 << "Range: " << Range 1909 << ". Size: " << TSize << ". Density: " << Density << "\n\n"); 1910 1911 // Get the MachineFunction which holds the current MBB. This is used when 1912 // inserting any additional MBBs necessary to represent the switch. 1913 MachineFunction *CurMF = FuncInfo.MF; 1914 1915 // Figure out which block is immediately after the current one. 1916 MachineFunction::iterator BBI = CR.CaseBB; 1917 ++BBI; 1918 1919 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1920 1921 // Create a new basic block to hold the code for loading the address 1922 // of the jump table, and jumping to it. Update successor information; 1923 // we will either branch to the default case for the switch, or the jump 1924 // table. 1925 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1926 CurMF->insert(BBI, JumpTableBB); 1927 CR.CaseBB->addSuccessor(Default); 1928 CR.CaseBB->addSuccessor(JumpTableBB); 1929 1930 // Build a vector of destination BBs, corresponding to each target 1931 // of the jump table. If the value of the jump table slot corresponds to 1932 // a case statement, push the case's BB onto the vector, otherwise, push 1933 // the default BB. 1934 std::vector<MachineBasicBlock*> DestBBs; 1935 APInt TEI = First; 1936 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1937 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 1938 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 1939 1940 if (Low.sle(TEI) && TEI.sle(High)) { 1941 DestBBs.push_back(I->BB); 1942 if (TEI==High) 1943 ++I; 1944 } else { 1945 DestBBs.push_back(Default); 1946 } 1947 } 1948 1949 // Update successor info. Add one edge to each unique successor. 1950 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1951 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1952 E = DestBBs.end(); I != E; ++I) { 1953 if (!SuccsHandled[(*I)->getNumber()]) { 1954 SuccsHandled[(*I)->getNumber()] = true; 1955 JumpTableBB->addSuccessor(*I); 1956 } 1957 } 1958 1959 // Create a jump table index for this jump table. 1960 unsigned JTEncoding = TLI.getJumpTableEncoding(); 1961 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 1962 ->createJumpTableIndex(DestBBs); 1963 1964 // Set the jump table information so that we can codegen it as a second 1965 // MachineBasicBlock 1966 JumpTable JT(-1U, JTI, JumpTableBB, Default); 1967 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 1968 if (CR.CaseBB == SwitchBB) 1969 visitJumpTableHeader(JT, JTH, SwitchBB); 1970 1971 JTCases.push_back(JumpTableBlock(JTH, JT)); 1972 1973 return true; 1974} 1975 1976/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1977/// 2 subtrees. 1978bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 1979 CaseRecVector& WorkList, 1980 const Value* SV, 1981 MachineBasicBlock *Default, 1982 MachineBasicBlock *SwitchBB) { 1983 // Get the MachineFunction which holds the current MBB. This is used when 1984 // inserting any additional MBBs necessary to represent the switch. 1985 MachineFunction *CurMF = FuncInfo.MF; 1986 1987 // Figure out which block is immediately after the current one. 1988 MachineFunction::iterator BBI = CR.CaseBB; 1989 ++BBI; 1990 1991 Case& FrontCase = *CR.Range.first; 1992 Case& BackCase = *(CR.Range.second-1); 1993 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1994 1995 // Size is the number of Cases represented by this range. 1996 unsigned Size = CR.Range.second - CR.Range.first; 1997 1998 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1999 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2000 double FMetric = 0; 2001 CaseItr Pivot = CR.Range.first + Size/2; 2002 2003 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2004 // (heuristically) allow us to emit JumpTable's later. 2005 APInt TSize(First.getBitWidth(), 0); 2006 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2007 I!=E; ++I) 2008 TSize += I->size(); 2009 2010 APInt LSize = FrontCase.size(); 2011 APInt RSize = TSize-LSize; 2012 DEBUG(dbgs() << "Selecting best pivot: \n" 2013 << "First: " << First << ", Last: " << Last <<'\n' 2014 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2015 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2016 J!=E; ++I, ++J) { 2017 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2018 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2019 APInt Range = ComputeRange(LEnd, RBegin); 2020 assert((Range - 2ULL).isNonNegative() && 2021 "Invalid case distance"); 2022 // Use volatile double here to avoid excess precision issues on some hosts, 2023 // e.g. that use 80-bit X87 registers. 2024 volatile double LDensity = 2025 (double)LSize.roundToDouble() / 2026 (LEnd - First + 1ULL).roundToDouble(); 2027 volatile double RDensity = 2028 (double)RSize.roundToDouble() / 2029 (Last - RBegin + 1ULL).roundToDouble(); 2030 double Metric = Range.logBase2()*(LDensity+RDensity); 2031 // Should always split in some non-trivial place 2032 DEBUG(dbgs() <<"=>Step\n" 2033 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2034 << "LDensity: " << LDensity 2035 << ", RDensity: " << RDensity << '\n' 2036 << "Metric: " << Metric << '\n'); 2037 if (FMetric < Metric) { 2038 Pivot = J; 2039 FMetric = Metric; 2040 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2041 } 2042 2043 LSize += J->size(); 2044 RSize -= J->size(); 2045 } 2046 if (areJTsAllowed(TLI)) { 2047 // If our case is dense we *really* should handle it earlier! 2048 assert((FMetric > 0) && "Should handle dense range earlier!"); 2049 } else { 2050 Pivot = CR.Range.first + Size/2; 2051 } 2052 2053 CaseRange LHSR(CR.Range.first, Pivot); 2054 CaseRange RHSR(Pivot, CR.Range.second); 2055 Constant *C = Pivot->Low; 2056 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2057 2058 // We know that we branch to the LHS if the Value being switched on is 2059 // less than the Pivot value, C. We use this to optimize our binary 2060 // tree a bit, by recognizing that if SV is greater than or equal to the 2061 // LHS's Case Value, and that Case Value is exactly one less than the 2062 // Pivot's Value, then we can branch directly to the LHS's Target, 2063 // rather than creating a leaf node for it. 2064 if ((LHSR.second - LHSR.first) == 1 && 2065 LHSR.first->High == CR.GE && 2066 cast<ConstantInt>(C)->getValue() == 2067 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2068 TrueBB = LHSR.first->BB; 2069 } else { 2070 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2071 CurMF->insert(BBI, TrueBB); 2072 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2073 2074 // Put SV in a virtual register to make it available from the new blocks. 2075 ExportFromCurrentBlock(SV); 2076 } 2077 2078 // Similar to the optimization above, if the Value being switched on is 2079 // known to be less than the Constant CR.LT, and the current Case Value 2080 // is CR.LT - 1, then we can branch directly to the target block for 2081 // the current Case Value, rather than emitting a RHS leaf node for it. 2082 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2083 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2084 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2085 FalseBB = RHSR.first->BB; 2086 } else { 2087 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2088 CurMF->insert(BBI, FalseBB); 2089 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2090 2091 // Put SV in a virtual register to make it available from the new blocks. 2092 ExportFromCurrentBlock(SV); 2093 } 2094 2095 // Create a CaseBlock record representing a conditional branch to 2096 // the LHS node if the value being switched on SV is less than C. 2097 // Otherwise, branch to LHS. 2098 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2099 2100 if (CR.CaseBB == SwitchBB) 2101 visitSwitchCase(CB, SwitchBB); 2102 else 2103 SwitchCases.push_back(CB); 2104 2105 return true; 2106} 2107 2108/// handleBitTestsSwitchCase - if current case range has few destination and 2109/// range span less, than machine word bitwidth, encode case range into series 2110/// of masks and emit bit tests with these masks. 2111bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2112 CaseRecVector& WorkList, 2113 const Value* SV, 2114 MachineBasicBlock* Default, 2115 MachineBasicBlock *SwitchBB){ 2116 EVT PTy = TLI.getPointerTy(); 2117 unsigned IntPtrBits = PTy.getSizeInBits(); 2118 2119 Case& FrontCase = *CR.Range.first; 2120 Case& BackCase = *(CR.Range.second-1); 2121 2122 // Get the MachineFunction which holds the current MBB. This is used when 2123 // inserting any additional MBBs necessary to represent the switch. 2124 MachineFunction *CurMF = FuncInfo.MF; 2125 2126 // If target does not have legal shift left, do not emit bit tests at all. 2127 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2128 return false; 2129 2130 size_t numCmps = 0; 2131 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2132 I!=E; ++I) { 2133 // Single case counts one, case range - two. 2134 numCmps += (I->Low == I->High ? 1 : 2); 2135 } 2136 2137 // Count unique destinations 2138 SmallSet<MachineBasicBlock*, 4> Dests; 2139 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2140 Dests.insert(I->BB); 2141 if (Dests.size() > 3) 2142 // Don't bother the code below, if there are too much unique destinations 2143 return false; 2144 } 2145 DEBUG(dbgs() << "Total number of unique destinations: " 2146 << Dests.size() << '\n' 2147 << "Total number of comparisons: " << numCmps << '\n'); 2148 2149 // Compute span of values. 2150 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2151 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2152 APInt cmpRange = maxValue - minValue; 2153 2154 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2155 << "Low bound: " << minValue << '\n' 2156 << "High bound: " << maxValue << '\n'); 2157 2158 if (cmpRange.uge(IntPtrBits) || 2159 (!(Dests.size() == 1 && numCmps >= 3) && 2160 !(Dests.size() == 2 && numCmps >= 5) && 2161 !(Dests.size() >= 3 && numCmps >= 6))) 2162 return false; 2163 2164 DEBUG(dbgs() << "Emitting bit tests\n"); 2165 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2166 2167 // Optimize the case where all the case values fit in a 2168 // word without having to subtract minValue. In this case, 2169 // we can optimize away the subtraction. 2170 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2171 cmpRange = maxValue; 2172 } else { 2173 lowBound = minValue; 2174 } 2175 2176 CaseBitsVector CasesBits; 2177 unsigned i, count = 0; 2178 2179 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2180 MachineBasicBlock* Dest = I->BB; 2181 for (i = 0; i < count; ++i) 2182 if (Dest == CasesBits[i].BB) 2183 break; 2184 2185 if (i == count) { 2186 assert((count < 3) && "Too much destinations to test!"); 2187 CasesBits.push_back(CaseBits(0, Dest, 0)); 2188 count++; 2189 } 2190 2191 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2192 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2193 2194 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2195 uint64_t hi = (highValue - lowBound).getZExtValue(); 2196 2197 for (uint64_t j = lo; j <= hi; j++) { 2198 CasesBits[i].Mask |= 1ULL << j; 2199 CasesBits[i].Bits++; 2200 } 2201 2202 } 2203 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2204 2205 BitTestInfo BTC; 2206 2207 // Figure out which block is immediately after the current one. 2208 MachineFunction::iterator BBI = CR.CaseBB; 2209 ++BBI; 2210 2211 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2212 2213 DEBUG(dbgs() << "Cases:\n"); 2214 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2215 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2216 << ", Bits: " << CasesBits[i].Bits 2217 << ", BB: " << CasesBits[i].BB << '\n'); 2218 2219 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2220 CurMF->insert(BBI, CaseBB); 2221 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2222 CaseBB, 2223 CasesBits[i].BB)); 2224 2225 // Put SV in a virtual register to make it available from the new blocks. 2226 ExportFromCurrentBlock(SV); 2227 } 2228 2229 BitTestBlock BTB(lowBound, cmpRange, SV, 2230 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2231 CR.CaseBB, Default, BTC); 2232 2233 if (CR.CaseBB == SwitchBB) 2234 visitBitTestHeader(BTB, SwitchBB); 2235 2236 BitTestCases.push_back(BTB); 2237 2238 return true; 2239} 2240 2241/// Clusterify - Transform simple list of Cases into list of CaseRange's 2242size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2243 const SwitchInst& SI) { 2244 size_t numCmps = 0; 2245 2246 // Start with "simple" cases 2247 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2248 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2249 Cases.push_back(Case(SI.getSuccessorValue(i), 2250 SI.getSuccessorValue(i), 2251 SMBB)); 2252 } 2253 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2254 2255 // Merge case into clusters 2256 if (Cases.size() >= 2) 2257 // Must recompute end() each iteration because it may be 2258 // invalidated by erase if we hold on to it 2259 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2260 J != Cases.end(); ) { 2261 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2262 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2263 MachineBasicBlock* nextBB = J->BB; 2264 MachineBasicBlock* currentBB = I->BB; 2265 2266 // If the two neighboring cases go to the same destination, merge them 2267 // into a single case. 2268 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2269 I->High = J->High; 2270 J = Cases.erase(J); 2271 } else { 2272 I = J++; 2273 } 2274 } 2275 2276 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2277 if (I->Low != I->High) 2278 // A range counts double, since it requires two compares. 2279 ++numCmps; 2280 } 2281 2282 return numCmps; 2283} 2284 2285void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2286 MachineBasicBlock *Last) { 2287 // Update JTCases. 2288 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2289 if (JTCases[i].first.HeaderBB == First) 2290 JTCases[i].first.HeaderBB = Last; 2291 2292 // Update BitTestCases. 2293 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2294 if (BitTestCases[i].Parent == First) 2295 BitTestCases[i].Parent = Last; 2296} 2297 2298void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2299 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2300 2301 // Figure out which block is immediately after the current one. 2302 MachineBasicBlock *NextBlock = 0; 2303 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2304 2305 // If there is only the default destination, branch to it if it is not the 2306 // next basic block. Otherwise, just fall through. 2307 if (SI.getNumOperands() == 2) { 2308 // Update machine-CFG edges. 2309 2310 // If this is not a fall-through branch, emit the branch. 2311 SwitchMBB->addSuccessor(Default); 2312 if (Default != NextBlock) 2313 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2314 MVT::Other, getControlRoot(), 2315 DAG.getBasicBlock(Default))); 2316 2317 return; 2318 } 2319 2320 // If there are any non-default case statements, create a vector of Cases 2321 // representing each one, and sort the vector so that we can efficiently 2322 // create a binary search tree from them. 2323 CaseVector Cases; 2324 size_t numCmps = Clusterify(Cases, SI); 2325 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2326 << ". Total compares: " << numCmps << '\n'); 2327 numCmps = 0; 2328 2329 // Get the Value to be switched on and default basic blocks, which will be 2330 // inserted into CaseBlock records, representing basic blocks in the binary 2331 // search tree. 2332 const Value *SV = SI.getOperand(0); 2333 2334 // Push the initial CaseRec onto the worklist 2335 CaseRecVector WorkList; 2336 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2337 CaseRange(Cases.begin(),Cases.end()))); 2338 2339 while (!WorkList.empty()) { 2340 // Grab a record representing a case range to process off the worklist 2341 CaseRec CR = WorkList.back(); 2342 WorkList.pop_back(); 2343 2344 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2345 continue; 2346 2347 // If the range has few cases (two or less) emit a series of specific 2348 // tests. 2349 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2350 continue; 2351 2352 // If the switch has more than 5 blocks, and at least 40% dense, and the 2353 // target supports indirect branches, then emit a jump table rather than 2354 // lowering the switch to a binary tree of conditional branches. 2355 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2356 continue; 2357 2358 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2359 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2360 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2361 } 2362} 2363 2364void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2365 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2366 2367 // Update machine-CFG edges with unique successors. 2368 SmallVector<BasicBlock*, 32> succs; 2369 succs.reserve(I.getNumSuccessors()); 2370 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2371 succs.push_back(I.getSuccessor(i)); 2372 array_pod_sort(succs.begin(), succs.end()); 2373 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2374 for (unsigned i = 0, e = succs.size(); i != e; ++i) 2375 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]); 2376 2377 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2378 MVT::Other, getControlRoot(), 2379 getValue(I.getAddress()))); 2380} 2381 2382void SelectionDAGBuilder::visitFSub(const User &I) { 2383 // -0.0 - X --> fneg 2384 const Type *Ty = I.getType(); 2385 if (isa<Constant>(I.getOperand(0)) && 2386 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2387 SDValue Op2 = getValue(I.getOperand(1)); 2388 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2389 Op2.getValueType(), Op2)); 2390 return; 2391 } 2392 2393 visitBinary(I, ISD::FSUB); 2394} 2395 2396void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2397 SDValue Op1 = getValue(I.getOperand(0)); 2398 SDValue Op2 = getValue(I.getOperand(1)); 2399 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2400 Op1.getValueType(), Op1, Op2)); 2401} 2402 2403void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2404 SDValue Op1 = getValue(I.getOperand(0)); 2405 SDValue Op2 = getValue(I.getOperand(1)); 2406 2407 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2408 2409 // Coerce the shift amount to the right type if we can. 2410 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2411 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2412 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2413 DebugLoc DL = getCurDebugLoc(); 2414 2415 // If the operand is smaller than the shift count type, promote it. 2416 if (ShiftSize > Op2Size) 2417 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2418 2419 // If the operand is larger than the shift count type but the shift 2420 // count type has enough bits to represent any shift value, truncate 2421 // it now. This is a common case and it exposes the truncate to 2422 // optimization early. 2423 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2424 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2425 // Otherwise we'll need to temporarily settle for some other convenient 2426 // type. Type legalization will make adjustments once the shiftee is split. 2427 else 2428 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2429 } 2430 2431 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2432 Op1.getValueType(), Op1, Op2)); 2433} 2434 2435void SelectionDAGBuilder::visitICmp(const User &I) { 2436 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2437 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2438 predicate = IC->getPredicate(); 2439 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2440 predicate = ICmpInst::Predicate(IC->getPredicate()); 2441 SDValue Op1 = getValue(I.getOperand(0)); 2442 SDValue Op2 = getValue(I.getOperand(1)); 2443 ISD::CondCode Opcode = getICmpCondCode(predicate); 2444 2445 EVT DestVT = TLI.getValueType(I.getType()); 2446 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2447} 2448 2449void SelectionDAGBuilder::visitFCmp(const User &I) { 2450 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2451 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2452 predicate = FC->getPredicate(); 2453 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2454 predicate = FCmpInst::Predicate(FC->getPredicate()); 2455 SDValue Op1 = getValue(I.getOperand(0)); 2456 SDValue Op2 = getValue(I.getOperand(1)); 2457 ISD::CondCode Condition = getFCmpCondCode(predicate); 2458 EVT DestVT = TLI.getValueType(I.getType()); 2459 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2460} 2461 2462void SelectionDAGBuilder::visitSelect(const User &I) { 2463 SmallVector<EVT, 4> ValueVTs; 2464 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2465 unsigned NumValues = ValueVTs.size(); 2466 if (NumValues == 0) return; 2467 2468 SmallVector<SDValue, 4> Values(NumValues); 2469 SDValue Cond = getValue(I.getOperand(0)); 2470 SDValue TrueVal = getValue(I.getOperand(1)); 2471 SDValue FalseVal = getValue(I.getOperand(2)); 2472 2473 for (unsigned i = 0; i != NumValues; ++i) 2474 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2475 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2476 Cond, 2477 SDValue(TrueVal.getNode(), 2478 TrueVal.getResNo() + i), 2479 SDValue(FalseVal.getNode(), 2480 FalseVal.getResNo() + i)); 2481 2482 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2483 DAG.getVTList(&ValueVTs[0], NumValues), 2484 &Values[0], NumValues)); 2485} 2486 2487void SelectionDAGBuilder::visitTrunc(const User &I) { 2488 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2489 SDValue N = getValue(I.getOperand(0)); 2490 EVT DestVT = TLI.getValueType(I.getType()); 2491 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2492} 2493 2494void SelectionDAGBuilder::visitZExt(const User &I) { 2495 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2496 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2497 SDValue N = getValue(I.getOperand(0)); 2498 EVT DestVT = TLI.getValueType(I.getType()); 2499 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2500} 2501 2502void SelectionDAGBuilder::visitSExt(const User &I) { 2503 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2504 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2505 SDValue N = getValue(I.getOperand(0)); 2506 EVT DestVT = TLI.getValueType(I.getType()); 2507 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2508} 2509 2510void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2511 // FPTrunc is never a no-op cast, no need to check 2512 SDValue N = getValue(I.getOperand(0)); 2513 EVT DestVT = TLI.getValueType(I.getType()); 2514 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2515 DestVT, N, DAG.getIntPtrConstant(0))); 2516} 2517 2518void SelectionDAGBuilder::visitFPExt(const User &I){ 2519 // FPTrunc is never a no-op cast, no need to check 2520 SDValue N = getValue(I.getOperand(0)); 2521 EVT DestVT = TLI.getValueType(I.getType()); 2522 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2523} 2524 2525void SelectionDAGBuilder::visitFPToUI(const User &I) { 2526 // FPToUI is never a no-op cast, no need to check 2527 SDValue N = getValue(I.getOperand(0)); 2528 EVT DestVT = TLI.getValueType(I.getType()); 2529 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2530} 2531 2532void SelectionDAGBuilder::visitFPToSI(const User &I) { 2533 // FPToSI is never a no-op cast, no need to check 2534 SDValue N = getValue(I.getOperand(0)); 2535 EVT DestVT = TLI.getValueType(I.getType()); 2536 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2537} 2538 2539void SelectionDAGBuilder::visitUIToFP(const User &I) { 2540 // UIToFP is never a no-op cast, no need to check 2541 SDValue N = getValue(I.getOperand(0)); 2542 EVT DestVT = TLI.getValueType(I.getType()); 2543 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2544} 2545 2546void SelectionDAGBuilder::visitSIToFP(const User &I){ 2547 // SIToFP is never a no-op cast, no need to check 2548 SDValue N = getValue(I.getOperand(0)); 2549 EVT DestVT = TLI.getValueType(I.getType()); 2550 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2551} 2552 2553void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2554 // What to do depends on the size of the integer and the size of the pointer. 2555 // We can either truncate, zero extend, or no-op, accordingly. 2556 SDValue N = getValue(I.getOperand(0)); 2557 EVT DestVT = TLI.getValueType(I.getType()); 2558 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2559} 2560 2561void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2562 // What to do depends on the size of the integer and the size of the pointer. 2563 // We can either truncate, zero extend, or no-op, accordingly. 2564 SDValue N = getValue(I.getOperand(0)); 2565 EVT DestVT = TLI.getValueType(I.getType()); 2566 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2567} 2568 2569void SelectionDAGBuilder::visitBitCast(const User &I) { 2570 SDValue N = getValue(I.getOperand(0)); 2571 EVT DestVT = TLI.getValueType(I.getType()); 2572 2573 // BitCast assures us that source and destination are the same size so this is 2574 // either a BITCAST or a no-op. 2575 if (DestVT != N.getValueType()) 2576 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2577 DestVT, N)); // convert types. 2578 else 2579 setValue(&I, N); // noop cast. 2580} 2581 2582void SelectionDAGBuilder::visitInsertElement(const User &I) { 2583 SDValue InVec = getValue(I.getOperand(0)); 2584 SDValue InVal = getValue(I.getOperand(1)); 2585 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2586 TLI.getPointerTy(), 2587 getValue(I.getOperand(2))); 2588 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2589 TLI.getValueType(I.getType()), 2590 InVec, InVal, InIdx)); 2591} 2592 2593void SelectionDAGBuilder::visitExtractElement(const User &I) { 2594 SDValue InVec = getValue(I.getOperand(0)); 2595 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2596 TLI.getPointerTy(), 2597 getValue(I.getOperand(1))); 2598 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2599 TLI.getValueType(I.getType()), InVec, InIdx)); 2600} 2601 2602// Utility for visitShuffleVector - Returns true if the mask is mask starting 2603// from SIndx and increasing to the element length (undefs are allowed). 2604static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2605 unsigned MaskNumElts = Mask.size(); 2606 for (unsigned i = 0; i != MaskNumElts; ++i) 2607 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2608 return false; 2609 return true; 2610} 2611 2612void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2613 SmallVector<int, 8> Mask; 2614 SDValue Src1 = getValue(I.getOperand(0)); 2615 SDValue Src2 = getValue(I.getOperand(1)); 2616 2617 // Convert the ConstantVector mask operand into an array of ints, with -1 2618 // representing undef values. 2619 SmallVector<Constant*, 8> MaskElts; 2620 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2621 unsigned MaskNumElts = MaskElts.size(); 2622 for (unsigned i = 0; i != MaskNumElts; ++i) { 2623 if (isa<UndefValue>(MaskElts[i])) 2624 Mask.push_back(-1); 2625 else 2626 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2627 } 2628 2629 EVT VT = TLI.getValueType(I.getType()); 2630 EVT SrcVT = Src1.getValueType(); 2631 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2632 2633 if (SrcNumElts == MaskNumElts) { 2634 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2635 &Mask[0])); 2636 return; 2637 } 2638 2639 // Normalize the shuffle vector since mask and vector length don't match. 2640 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2641 // Mask is longer than the source vectors and is a multiple of the source 2642 // vectors. We can use concatenate vector to make the mask and vectors 2643 // lengths match. 2644 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2645 // The shuffle is concatenating two vectors together. 2646 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2647 VT, Src1, Src2)); 2648 return; 2649 } 2650 2651 // Pad both vectors with undefs to make them the same length as the mask. 2652 unsigned NumConcat = MaskNumElts / SrcNumElts; 2653 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2654 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2655 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2656 2657 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2658 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2659 MOps1[0] = Src1; 2660 MOps2[0] = Src2; 2661 2662 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2663 getCurDebugLoc(), VT, 2664 &MOps1[0], NumConcat); 2665 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2666 getCurDebugLoc(), VT, 2667 &MOps2[0], NumConcat); 2668 2669 // Readjust mask for new input vector length. 2670 SmallVector<int, 8> MappedOps; 2671 for (unsigned i = 0; i != MaskNumElts; ++i) { 2672 int Idx = Mask[i]; 2673 if (Idx < (int)SrcNumElts) 2674 MappedOps.push_back(Idx); 2675 else 2676 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2677 } 2678 2679 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2680 &MappedOps[0])); 2681 return; 2682 } 2683 2684 if (SrcNumElts > MaskNumElts) { 2685 // Analyze the access pattern of the vector to see if we can extract 2686 // two subvectors and do the shuffle. The analysis is done by calculating 2687 // the range of elements the mask access on both vectors. 2688 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2689 int MaxRange[2] = {-1, -1}; 2690 2691 for (unsigned i = 0; i != MaskNumElts; ++i) { 2692 int Idx = Mask[i]; 2693 int Input = 0; 2694 if (Idx < 0) 2695 continue; 2696 2697 if (Idx >= (int)SrcNumElts) { 2698 Input = 1; 2699 Idx -= SrcNumElts; 2700 } 2701 if (Idx > MaxRange[Input]) 2702 MaxRange[Input] = Idx; 2703 if (Idx < MinRange[Input]) 2704 MinRange[Input] = Idx; 2705 } 2706 2707 // Check if the access is smaller than the vector size and can we find 2708 // a reasonable extract index. 2709 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2710 // Extract. 2711 int StartIdx[2]; // StartIdx to extract from 2712 for (int Input=0; Input < 2; ++Input) { 2713 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2714 RangeUse[Input] = 0; // Unused 2715 StartIdx[Input] = 0; 2716 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2717 // Fits within range but we should see if we can find a good 2718 // start index that is a multiple of the mask length. 2719 if (MaxRange[Input] < (int)MaskNumElts) { 2720 RangeUse[Input] = 1; // Extract from beginning of the vector 2721 StartIdx[Input] = 0; 2722 } else { 2723 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2724 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2725 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2726 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2727 } 2728 } 2729 } 2730 2731 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2732 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2733 return; 2734 } 2735 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2736 // Extract appropriate subvector and generate a vector shuffle 2737 for (int Input=0; Input < 2; ++Input) { 2738 SDValue &Src = Input == 0 ? Src1 : Src2; 2739 if (RangeUse[Input] == 0) 2740 Src = DAG.getUNDEF(VT); 2741 else 2742 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2743 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2744 } 2745 2746 // Calculate new mask. 2747 SmallVector<int, 8> MappedOps; 2748 for (unsigned i = 0; i != MaskNumElts; ++i) { 2749 int Idx = Mask[i]; 2750 if (Idx < 0) 2751 MappedOps.push_back(Idx); 2752 else if (Idx < (int)SrcNumElts) 2753 MappedOps.push_back(Idx - StartIdx[0]); 2754 else 2755 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2756 } 2757 2758 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2759 &MappedOps[0])); 2760 return; 2761 } 2762 } 2763 2764 // We can't use either concat vectors or extract subvectors so fall back to 2765 // replacing the shuffle with extract and build vector. 2766 // to insert and build vector. 2767 EVT EltVT = VT.getVectorElementType(); 2768 EVT PtrVT = TLI.getPointerTy(); 2769 SmallVector<SDValue,8> Ops; 2770 for (unsigned i = 0; i != MaskNumElts; ++i) { 2771 if (Mask[i] < 0) { 2772 Ops.push_back(DAG.getUNDEF(EltVT)); 2773 } else { 2774 int Idx = Mask[i]; 2775 SDValue Res; 2776 2777 if (Idx < (int)SrcNumElts) 2778 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2779 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2780 else 2781 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2782 EltVT, Src2, 2783 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2784 2785 Ops.push_back(Res); 2786 } 2787 } 2788 2789 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2790 VT, &Ops[0], Ops.size())); 2791} 2792 2793void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2794 const Value *Op0 = I.getOperand(0); 2795 const Value *Op1 = I.getOperand(1); 2796 const Type *AggTy = I.getType(); 2797 const Type *ValTy = Op1->getType(); 2798 bool IntoUndef = isa<UndefValue>(Op0); 2799 bool FromUndef = isa<UndefValue>(Op1); 2800 2801 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2802 2803 SmallVector<EVT, 4> AggValueVTs; 2804 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2805 SmallVector<EVT, 4> ValValueVTs; 2806 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2807 2808 unsigned NumAggValues = AggValueVTs.size(); 2809 unsigned NumValValues = ValValueVTs.size(); 2810 SmallVector<SDValue, 4> Values(NumAggValues); 2811 2812 SDValue Agg = getValue(Op0); 2813 SDValue Val = getValue(Op1); 2814 unsigned i = 0; 2815 // Copy the beginning value(s) from the original aggregate. 2816 for (; i != LinearIndex; ++i) 2817 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2818 SDValue(Agg.getNode(), Agg.getResNo() + i); 2819 // Copy values from the inserted value(s). 2820 for (; i != LinearIndex + NumValValues; ++i) 2821 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2822 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2823 // Copy remaining value(s) from the original aggregate. 2824 for (; i != NumAggValues; ++i) 2825 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2826 SDValue(Agg.getNode(), Agg.getResNo() + i); 2827 2828 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2829 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2830 &Values[0], NumAggValues)); 2831} 2832 2833void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2834 const Value *Op0 = I.getOperand(0); 2835 const Type *AggTy = Op0->getType(); 2836 const Type *ValTy = I.getType(); 2837 bool OutOfUndef = isa<UndefValue>(Op0); 2838 2839 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2840 2841 SmallVector<EVT, 4> ValValueVTs; 2842 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2843 2844 unsigned NumValValues = ValValueVTs.size(); 2845 SmallVector<SDValue, 4> Values(NumValValues); 2846 2847 SDValue Agg = getValue(Op0); 2848 // Copy out the selected value(s). 2849 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2850 Values[i - LinearIndex] = 2851 OutOfUndef ? 2852 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2853 SDValue(Agg.getNode(), Agg.getResNo() + i); 2854 2855 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2856 DAG.getVTList(&ValValueVTs[0], NumValValues), 2857 &Values[0], NumValValues)); 2858} 2859 2860void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2861 SDValue N = getValue(I.getOperand(0)); 2862 const Type *Ty = I.getOperand(0)->getType(); 2863 2864 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2865 OI != E; ++OI) { 2866 const Value *Idx = *OI; 2867 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2868 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2869 if (Field) { 2870 // N = N + Offset 2871 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2872 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2873 DAG.getIntPtrConstant(Offset)); 2874 } 2875 2876 Ty = StTy->getElementType(Field); 2877 } else { 2878 Ty = cast<SequentialType>(Ty)->getElementType(); 2879 2880 // If this is a constant subscript, handle it quickly. 2881 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2882 if (CI->isZero()) continue; 2883 uint64_t Offs = 2884 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2885 SDValue OffsVal; 2886 EVT PTy = TLI.getPointerTy(); 2887 unsigned PtrBits = PTy.getSizeInBits(); 2888 if (PtrBits < 64) 2889 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2890 TLI.getPointerTy(), 2891 DAG.getConstant(Offs, MVT::i64)); 2892 else 2893 OffsVal = DAG.getIntPtrConstant(Offs); 2894 2895 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2896 OffsVal); 2897 continue; 2898 } 2899 2900 // N = N + Idx * ElementSize; 2901 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2902 TD->getTypeAllocSize(Ty)); 2903 SDValue IdxN = getValue(Idx); 2904 2905 // If the index is smaller or larger than intptr_t, truncate or extend 2906 // it. 2907 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2908 2909 // If this is a multiply by a power of two, turn it into a shl 2910 // immediately. This is a very common case. 2911 if (ElementSize != 1) { 2912 if (ElementSize.isPowerOf2()) { 2913 unsigned Amt = ElementSize.logBase2(); 2914 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2915 N.getValueType(), IdxN, 2916 DAG.getConstant(Amt, TLI.getPointerTy())); 2917 } else { 2918 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2919 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2920 N.getValueType(), IdxN, Scale); 2921 } 2922 } 2923 2924 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2925 N.getValueType(), N, IdxN); 2926 } 2927 } 2928 2929 setValue(&I, N); 2930} 2931 2932void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 2933 // If this is a fixed sized alloca in the entry block of the function, 2934 // allocate it statically on the stack. 2935 if (FuncInfo.StaticAllocaMap.count(&I)) 2936 return; // getValue will auto-populate this. 2937 2938 const Type *Ty = I.getAllocatedType(); 2939 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 2940 unsigned Align = 2941 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2942 I.getAlignment()); 2943 2944 SDValue AllocSize = getValue(I.getArraySize()); 2945 2946 EVT IntPtr = TLI.getPointerTy(); 2947 if (AllocSize.getValueType() != IntPtr) 2948 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 2949 2950 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 2951 AllocSize, 2952 DAG.getConstant(TySize, IntPtr)); 2953 2954 // Handle alignment. If the requested alignment is less than or equal to 2955 // the stack alignment, ignore it. If the size is greater than or equal to 2956 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2957 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 2958 if (Align <= StackAlign) 2959 Align = 0; 2960 2961 // Round the size of the allocation up to the stack alignment size 2962 // by add SA-1 to the size. 2963 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2964 AllocSize.getValueType(), AllocSize, 2965 DAG.getIntPtrConstant(StackAlign-1)); 2966 2967 // Mask out the low bits for alignment purposes. 2968 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 2969 AllocSize.getValueType(), AllocSize, 2970 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2971 2972 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2973 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 2974 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 2975 VTs, Ops, 3); 2976 setValue(&I, DSA); 2977 DAG.setRoot(DSA.getValue(1)); 2978 2979 // Inform the Frame Information that we have just allocated a variable-sized 2980 // object. 2981 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 2982} 2983 2984void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 2985 const Value *SV = I.getOperand(0); 2986 SDValue Ptr = getValue(SV); 2987 2988 const Type *Ty = I.getType(); 2989 2990 bool isVolatile = I.isVolatile(); 2991 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2992 unsigned Alignment = I.getAlignment(); 2993 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 2994 2995 SmallVector<EVT, 4> ValueVTs; 2996 SmallVector<uint64_t, 4> Offsets; 2997 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2998 unsigned NumValues = ValueVTs.size(); 2999 if (NumValues == 0) 3000 return; 3001 3002 SDValue Root; 3003 bool ConstantMemory = false; 3004 if (I.isVolatile() || NumValues > MaxParallelChains) 3005 // Serialize volatile loads with other side effects. 3006 Root = getRoot(); 3007 else if (AA->pointsToConstantMemory( 3008 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3009 // Do not serialize (non-volatile) loads of constant memory with anything. 3010 Root = DAG.getEntryNode(); 3011 ConstantMemory = true; 3012 } else { 3013 // Do not serialize non-volatile loads against each other. 3014 Root = DAG.getRoot(); 3015 } 3016 3017 SmallVector<SDValue, 4> Values(NumValues); 3018 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3019 NumValues)); 3020 EVT PtrVT = Ptr.getValueType(); 3021 unsigned ChainI = 0; 3022 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3023 // Serializing loads here may result in excessive register pressure, and 3024 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3025 // could recover a bit by hoisting nodes upward in the chain by recognizing 3026 // they are side-effect free or do not alias. The optimizer should really 3027 // avoid this case by converting large object/array copies to llvm.memcpy 3028 // (MaxParallelChains should always remain as failsafe). 3029 if (ChainI == MaxParallelChains) { 3030 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3031 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3032 MVT::Other, &Chains[0], ChainI); 3033 Root = Chain; 3034 ChainI = 0; 3035 } 3036 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3037 PtrVT, Ptr, 3038 DAG.getConstant(Offsets[i], PtrVT)); 3039 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3040 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3041 isNonTemporal, Alignment, TBAAInfo); 3042 3043 Values[i] = L; 3044 Chains[ChainI] = L.getValue(1); 3045 } 3046 3047 if (!ConstantMemory) { 3048 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3049 MVT::Other, &Chains[0], ChainI); 3050 if (isVolatile) 3051 DAG.setRoot(Chain); 3052 else 3053 PendingLoads.push_back(Chain); 3054 } 3055 3056 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3057 DAG.getVTList(&ValueVTs[0], NumValues), 3058 &Values[0], NumValues)); 3059} 3060 3061void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3062 const Value *SrcV = I.getOperand(0); 3063 const Value *PtrV = I.getOperand(1); 3064 3065 SmallVector<EVT, 4> ValueVTs; 3066 SmallVector<uint64_t, 4> Offsets; 3067 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3068 unsigned NumValues = ValueVTs.size(); 3069 if (NumValues == 0) 3070 return; 3071 3072 // Get the lowered operands. Note that we do this after 3073 // checking if NumResults is zero, because with zero results 3074 // the operands won't have values in the map. 3075 SDValue Src = getValue(SrcV); 3076 SDValue Ptr = getValue(PtrV); 3077 3078 SDValue Root = getRoot(); 3079 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3080 NumValues)); 3081 EVT PtrVT = Ptr.getValueType(); 3082 bool isVolatile = I.isVolatile(); 3083 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3084 unsigned Alignment = I.getAlignment(); 3085 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3086 3087 unsigned ChainI = 0; 3088 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3089 // See visitLoad comments. 3090 if (ChainI == MaxParallelChains) { 3091 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3092 MVT::Other, &Chains[0], ChainI); 3093 Root = Chain; 3094 ChainI = 0; 3095 } 3096 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3097 DAG.getConstant(Offsets[i], PtrVT)); 3098 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3099 SDValue(Src.getNode(), Src.getResNo() + i), 3100 Add, MachinePointerInfo(PtrV, Offsets[i]), 3101 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3102 Chains[ChainI] = St; 3103 } 3104 3105 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3106 MVT::Other, &Chains[0], ChainI); 3107 ++SDNodeOrder; 3108 AssignOrderingToNode(StoreNode.getNode()); 3109 DAG.setRoot(StoreNode); 3110} 3111 3112/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3113/// node. 3114void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3115 unsigned Intrinsic) { 3116 bool HasChain = !I.doesNotAccessMemory(); 3117 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3118 3119 // Build the operand list. 3120 SmallVector<SDValue, 8> Ops; 3121 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3122 if (OnlyLoad) { 3123 // We don't need to serialize loads against other loads. 3124 Ops.push_back(DAG.getRoot()); 3125 } else { 3126 Ops.push_back(getRoot()); 3127 } 3128 } 3129 3130 // Info is set by getTgtMemInstrinsic 3131 TargetLowering::IntrinsicInfo Info; 3132 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3133 3134 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3135 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3136 Info.opc == ISD::INTRINSIC_W_CHAIN) 3137 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3138 3139 // Add all operands of the call to the operand list. 3140 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3141 SDValue Op = getValue(I.getArgOperand(i)); 3142 assert(TLI.isTypeLegal(Op.getValueType()) && 3143 "Intrinsic uses a non-legal type?"); 3144 Ops.push_back(Op); 3145 } 3146 3147 SmallVector<EVT, 4> ValueVTs; 3148 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3149#ifndef NDEBUG 3150 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3151 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3152 "Intrinsic uses a non-legal type?"); 3153 } 3154#endif // NDEBUG 3155 3156 if (HasChain) 3157 ValueVTs.push_back(MVT::Other); 3158 3159 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3160 3161 // Create the node. 3162 SDValue Result; 3163 if (IsTgtIntrinsic) { 3164 // This is target intrinsic that touches memory 3165 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3166 VTs, &Ops[0], Ops.size(), 3167 Info.memVT, 3168 MachinePointerInfo(Info.ptrVal, Info.offset), 3169 Info.align, Info.vol, 3170 Info.readMem, Info.writeMem); 3171 } else if (!HasChain) { 3172 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3173 VTs, &Ops[0], Ops.size()); 3174 } else if (!I.getType()->isVoidTy()) { 3175 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3176 VTs, &Ops[0], Ops.size()); 3177 } else { 3178 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3179 VTs, &Ops[0], Ops.size()); 3180 } 3181 3182 if (HasChain) { 3183 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3184 if (OnlyLoad) 3185 PendingLoads.push_back(Chain); 3186 else 3187 DAG.setRoot(Chain); 3188 } 3189 3190 if (!I.getType()->isVoidTy()) { 3191 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3192 EVT VT = TLI.getValueType(PTy); 3193 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3194 } 3195 3196 setValue(&I, Result); 3197 } 3198} 3199 3200/// GetSignificand - Get the significand and build it into a floating-point 3201/// number with exponent of 1: 3202/// 3203/// Op = (Op & 0x007fffff) | 0x3f800000; 3204/// 3205/// where Op is the hexidecimal representation of floating point value. 3206static SDValue 3207GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3208 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3209 DAG.getConstant(0x007fffff, MVT::i32)); 3210 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3211 DAG.getConstant(0x3f800000, MVT::i32)); 3212 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3213} 3214 3215/// GetExponent - Get the exponent: 3216/// 3217/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3218/// 3219/// where Op is the hexidecimal representation of floating point value. 3220static SDValue 3221GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3222 DebugLoc dl) { 3223 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3224 DAG.getConstant(0x7f800000, MVT::i32)); 3225 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3226 DAG.getConstant(23, TLI.getPointerTy())); 3227 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3228 DAG.getConstant(127, MVT::i32)); 3229 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3230} 3231 3232/// getF32Constant - Get 32-bit floating point constant. 3233static SDValue 3234getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3235 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3236} 3237 3238/// Inlined utility function to implement binary input atomic intrinsics for 3239/// visitIntrinsicCall: I is a call instruction 3240/// Op is the associated NodeType for I 3241const char * 3242SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3243 ISD::NodeType Op) { 3244 SDValue Root = getRoot(); 3245 SDValue L = 3246 DAG.getAtomic(Op, getCurDebugLoc(), 3247 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3248 Root, 3249 getValue(I.getArgOperand(0)), 3250 getValue(I.getArgOperand(1)), 3251 I.getArgOperand(0)); 3252 setValue(&I, L); 3253 DAG.setRoot(L.getValue(1)); 3254 return 0; 3255} 3256 3257// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3258const char * 3259SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3260 SDValue Op1 = getValue(I.getArgOperand(0)); 3261 SDValue Op2 = getValue(I.getArgOperand(1)); 3262 3263 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3264 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3265 return 0; 3266} 3267 3268/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3269/// limited-precision mode. 3270void 3271SelectionDAGBuilder::visitExp(const CallInst &I) { 3272 SDValue result; 3273 DebugLoc dl = getCurDebugLoc(); 3274 3275 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3276 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3277 SDValue Op = getValue(I.getArgOperand(0)); 3278 3279 // Put the exponent in the right bit position for later addition to the 3280 // final result: 3281 // 3282 // #define LOG2OFe 1.4426950f 3283 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3284 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3285 getF32Constant(DAG, 0x3fb8aa3b)); 3286 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3287 3288 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3289 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3290 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3291 3292 // IntegerPartOfX <<= 23; 3293 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3294 DAG.getConstant(23, TLI.getPointerTy())); 3295 3296 if (LimitFloatPrecision <= 6) { 3297 // For floating-point precision of 6: 3298 // 3299 // TwoToFractionalPartOfX = 3300 // 0.997535578f + 3301 // (0.735607626f + 0.252464424f * x) * x; 3302 // 3303 // error 0.0144103317, which is 6 bits 3304 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3305 getF32Constant(DAG, 0x3e814304)); 3306 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3307 getF32Constant(DAG, 0x3f3c50c8)); 3308 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3309 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3310 getF32Constant(DAG, 0x3f7f5e7e)); 3311 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3312 3313 // Add the exponent into the result in integer domain. 3314 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3315 TwoToFracPartOfX, IntegerPartOfX); 3316 3317 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3318 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3319 // For floating-point precision of 12: 3320 // 3321 // TwoToFractionalPartOfX = 3322 // 0.999892986f + 3323 // (0.696457318f + 3324 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3325 // 3326 // 0.000107046256 error, which is 13 to 14 bits 3327 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3328 getF32Constant(DAG, 0x3da235e3)); 3329 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3330 getF32Constant(DAG, 0x3e65b8f3)); 3331 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3332 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3333 getF32Constant(DAG, 0x3f324b07)); 3334 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3335 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3336 getF32Constant(DAG, 0x3f7ff8fd)); 3337 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3338 3339 // Add the exponent into the result in integer domain. 3340 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3341 TwoToFracPartOfX, IntegerPartOfX); 3342 3343 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3344 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3345 // For floating-point precision of 18: 3346 // 3347 // TwoToFractionalPartOfX = 3348 // 0.999999982f + 3349 // (0.693148872f + 3350 // (0.240227044f + 3351 // (0.554906021e-1f + 3352 // (0.961591928e-2f + 3353 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3354 // 3355 // error 2.47208000*10^(-7), which is better than 18 bits 3356 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3357 getF32Constant(DAG, 0x3924b03e)); 3358 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3359 getF32Constant(DAG, 0x3ab24b87)); 3360 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3361 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3362 getF32Constant(DAG, 0x3c1d8c17)); 3363 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3364 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3365 getF32Constant(DAG, 0x3d634a1d)); 3366 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3367 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3368 getF32Constant(DAG, 0x3e75fe14)); 3369 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3370 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3371 getF32Constant(DAG, 0x3f317234)); 3372 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3373 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3374 getF32Constant(DAG, 0x3f800000)); 3375 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3376 MVT::i32, t13); 3377 3378 // Add the exponent into the result in integer domain. 3379 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3380 TwoToFracPartOfX, IntegerPartOfX); 3381 3382 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3383 } 3384 } else { 3385 // No special expansion. 3386 result = DAG.getNode(ISD::FEXP, dl, 3387 getValue(I.getArgOperand(0)).getValueType(), 3388 getValue(I.getArgOperand(0))); 3389 } 3390 3391 setValue(&I, result); 3392} 3393 3394/// visitLog - Lower a log intrinsic. Handles the special sequences for 3395/// limited-precision mode. 3396void 3397SelectionDAGBuilder::visitLog(const CallInst &I) { 3398 SDValue result; 3399 DebugLoc dl = getCurDebugLoc(); 3400 3401 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3402 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3403 SDValue Op = getValue(I.getArgOperand(0)); 3404 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3405 3406 // Scale the exponent by log(2) [0.69314718f]. 3407 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3408 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3409 getF32Constant(DAG, 0x3f317218)); 3410 3411 // Get the significand and build it into a floating-point number with 3412 // exponent of 1. 3413 SDValue X = GetSignificand(DAG, Op1, dl); 3414 3415 if (LimitFloatPrecision <= 6) { 3416 // For floating-point precision of 6: 3417 // 3418 // LogofMantissa = 3419 // -1.1609546f + 3420 // (1.4034025f - 0.23903021f * x) * x; 3421 // 3422 // error 0.0034276066, which is better than 8 bits 3423 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3424 getF32Constant(DAG, 0xbe74c456)); 3425 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3426 getF32Constant(DAG, 0x3fb3a2b1)); 3427 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3428 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3429 getF32Constant(DAG, 0x3f949a29)); 3430 3431 result = DAG.getNode(ISD::FADD, dl, 3432 MVT::f32, LogOfExponent, LogOfMantissa); 3433 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3434 // For floating-point precision of 12: 3435 // 3436 // LogOfMantissa = 3437 // -1.7417939f + 3438 // (2.8212026f + 3439 // (-1.4699568f + 3440 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3441 // 3442 // error 0.000061011436, which is 14 bits 3443 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3444 getF32Constant(DAG, 0xbd67b6d6)); 3445 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3446 getF32Constant(DAG, 0x3ee4f4b8)); 3447 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3448 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3449 getF32Constant(DAG, 0x3fbc278b)); 3450 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3451 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3452 getF32Constant(DAG, 0x40348e95)); 3453 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3454 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3455 getF32Constant(DAG, 0x3fdef31a)); 3456 3457 result = DAG.getNode(ISD::FADD, dl, 3458 MVT::f32, LogOfExponent, LogOfMantissa); 3459 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3460 // For floating-point precision of 18: 3461 // 3462 // LogOfMantissa = 3463 // -2.1072184f + 3464 // (4.2372794f + 3465 // (-3.7029485f + 3466 // (2.2781945f + 3467 // (-0.87823314f + 3468 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3469 // 3470 // error 0.0000023660568, which is better than 18 bits 3471 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3472 getF32Constant(DAG, 0xbc91e5ac)); 3473 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3474 getF32Constant(DAG, 0x3e4350aa)); 3475 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3476 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3477 getF32Constant(DAG, 0x3f60d3e3)); 3478 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3479 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3480 getF32Constant(DAG, 0x4011cdf0)); 3481 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3482 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3483 getF32Constant(DAG, 0x406cfd1c)); 3484 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3485 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3486 getF32Constant(DAG, 0x408797cb)); 3487 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3488 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3489 getF32Constant(DAG, 0x4006dcab)); 3490 3491 result = DAG.getNode(ISD::FADD, dl, 3492 MVT::f32, LogOfExponent, LogOfMantissa); 3493 } 3494 } else { 3495 // No special expansion. 3496 result = DAG.getNode(ISD::FLOG, dl, 3497 getValue(I.getArgOperand(0)).getValueType(), 3498 getValue(I.getArgOperand(0))); 3499 } 3500 3501 setValue(&I, result); 3502} 3503 3504/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3505/// limited-precision mode. 3506void 3507SelectionDAGBuilder::visitLog2(const CallInst &I) { 3508 SDValue result; 3509 DebugLoc dl = getCurDebugLoc(); 3510 3511 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3512 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3513 SDValue Op = getValue(I.getArgOperand(0)); 3514 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3515 3516 // Get the exponent. 3517 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3518 3519 // Get the significand and build it into a floating-point number with 3520 // exponent of 1. 3521 SDValue X = GetSignificand(DAG, Op1, dl); 3522 3523 // Different possible minimax approximations of significand in 3524 // floating-point for various degrees of accuracy over [1,2]. 3525 if (LimitFloatPrecision <= 6) { 3526 // For floating-point precision of 6: 3527 // 3528 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3529 // 3530 // error 0.0049451742, which is more than 7 bits 3531 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3532 getF32Constant(DAG, 0xbeb08fe0)); 3533 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3534 getF32Constant(DAG, 0x40019463)); 3535 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3536 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3537 getF32Constant(DAG, 0x3fd6633d)); 3538 3539 result = DAG.getNode(ISD::FADD, dl, 3540 MVT::f32, LogOfExponent, Log2ofMantissa); 3541 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3542 // For floating-point precision of 12: 3543 // 3544 // Log2ofMantissa = 3545 // -2.51285454f + 3546 // (4.07009056f + 3547 // (-2.12067489f + 3548 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3549 // 3550 // error 0.0000876136000, which is better than 13 bits 3551 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3552 getF32Constant(DAG, 0xbda7262e)); 3553 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3554 getF32Constant(DAG, 0x3f25280b)); 3555 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3556 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3557 getF32Constant(DAG, 0x4007b923)); 3558 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3559 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3560 getF32Constant(DAG, 0x40823e2f)); 3561 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3562 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3563 getF32Constant(DAG, 0x4020d29c)); 3564 3565 result = DAG.getNode(ISD::FADD, dl, 3566 MVT::f32, LogOfExponent, Log2ofMantissa); 3567 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3568 // For floating-point precision of 18: 3569 // 3570 // Log2ofMantissa = 3571 // -3.0400495f + 3572 // (6.1129976f + 3573 // (-5.3420409f + 3574 // (3.2865683f + 3575 // (-1.2669343f + 3576 // (0.27515199f - 3577 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3578 // 3579 // error 0.0000018516, which is better than 18 bits 3580 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3581 getF32Constant(DAG, 0xbcd2769e)); 3582 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3583 getF32Constant(DAG, 0x3e8ce0b9)); 3584 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3585 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3586 getF32Constant(DAG, 0x3fa22ae7)); 3587 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3588 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3589 getF32Constant(DAG, 0x40525723)); 3590 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3591 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3592 getF32Constant(DAG, 0x40aaf200)); 3593 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3594 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3595 getF32Constant(DAG, 0x40c39dad)); 3596 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3597 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3598 getF32Constant(DAG, 0x4042902c)); 3599 3600 result = DAG.getNode(ISD::FADD, dl, 3601 MVT::f32, LogOfExponent, Log2ofMantissa); 3602 } 3603 } else { 3604 // No special expansion. 3605 result = DAG.getNode(ISD::FLOG2, dl, 3606 getValue(I.getArgOperand(0)).getValueType(), 3607 getValue(I.getArgOperand(0))); 3608 } 3609 3610 setValue(&I, result); 3611} 3612 3613/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3614/// limited-precision mode. 3615void 3616SelectionDAGBuilder::visitLog10(const CallInst &I) { 3617 SDValue result; 3618 DebugLoc dl = getCurDebugLoc(); 3619 3620 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3621 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3622 SDValue Op = getValue(I.getArgOperand(0)); 3623 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3624 3625 // Scale the exponent by log10(2) [0.30102999f]. 3626 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3627 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3628 getF32Constant(DAG, 0x3e9a209a)); 3629 3630 // Get the significand and build it into a floating-point number with 3631 // exponent of 1. 3632 SDValue X = GetSignificand(DAG, Op1, dl); 3633 3634 if (LimitFloatPrecision <= 6) { 3635 // For floating-point precision of 6: 3636 // 3637 // Log10ofMantissa = 3638 // -0.50419619f + 3639 // (0.60948995f - 0.10380950f * x) * x; 3640 // 3641 // error 0.0014886165, which is 6 bits 3642 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3643 getF32Constant(DAG, 0xbdd49a13)); 3644 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3645 getF32Constant(DAG, 0x3f1c0789)); 3646 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3647 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3648 getF32Constant(DAG, 0x3f011300)); 3649 3650 result = DAG.getNode(ISD::FADD, dl, 3651 MVT::f32, LogOfExponent, Log10ofMantissa); 3652 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3653 // For floating-point precision of 12: 3654 // 3655 // Log10ofMantissa = 3656 // -0.64831180f + 3657 // (0.91751397f + 3658 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3659 // 3660 // error 0.00019228036, which is better than 12 bits 3661 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3662 getF32Constant(DAG, 0x3d431f31)); 3663 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3664 getF32Constant(DAG, 0x3ea21fb2)); 3665 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3666 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3667 getF32Constant(DAG, 0x3f6ae232)); 3668 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3669 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3670 getF32Constant(DAG, 0x3f25f7c3)); 3671 3672 result = DAG.getNode(ISD::FADD, dl, 3673 MVT::f32, LogOfExponent, Log10ofMantissa); 3674 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3675 // For floating-point precision of 18: 3676 // 3677 // Log10ofMantissa = 3678 // -0.84299375f + 3679 // (1.5327582f + 3680 // (-1.0688956f + 3681 // (0.49102474f + 3682 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3683 // 3684 // error 0.0000037995730, which is better than 18 bits 3685 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3686 getF32Constant(DAG, 0x3c5d51ce)); 3687 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3688 getF32Constant(DAG, 0x3e00685a)); 3689 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3690 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3691 getF32Constant(DAG, 0x3efb6798)); 3692 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3693 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3694 getF32Constant(DAG, 0x3f88d192)); 3695 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3696 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3697 getF32Constant(DAG, 0x3fc4316c)); 3698 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3699 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3700 getF32Constant(DAG, 0x3f57ce70)); 3701 3702 result = DAG.getNode(ISD::FADD, dl, 3703 MVT::f32, LogOfExponent, Log10ofMantissa); 3704 } 3705 } else { 3706 // No special expansion. 3707 result = DAG.getNode(ISD::FLOG10, dl, 3708 getValue(I.getArgOperand(0)).getValueType(), 3709 getValue(I.getArgOperand(0))); 3710 } 3711 3712 setValue(&I, result); 3713} 3714 3715/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3716/// limited-precision mode. 3717void 3718SelectionDAGBuilder::visitExp2(const CallInst &I) { 3719 SDValue result; 3720 DebugLoc dl = getCurDebugLoc(); 3721 3722 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3723 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3724 SDValue Op = getValue(I.getArgOperand(0)); 3725 3726 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3727 3728 // FractionalPartOfX = x - (float)IntegerPartOfX; 3729 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3730 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3731 3732 // IntegerPartOfX <<= 23; 3733 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3734 DAG.getConstant(23, TLI.getPointerTy())); 3735 3736 if (LimitFloatPrecision <= 6) { 3737 // For floating-point precision of 6: 3738 // 3739 // TwoToFractionalPartOfX = 3740 // 0.997535578f + 3741 // (0.735607626f + 0.252464424f * x) * x; 3742 // 3743 // error 0.0144103317, which is 6 bits 3744 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3745 getF32Constant(DAG, 0x3e814304)); 3746 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3747 getF32Constant(DAG, 0x3f3c50c8)); 3748 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3749 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3750 getF32Constant(DAG, 0x3f7f5e7e)); 3751 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3752 SDValue TwoToFractionalPartOfX = 3753 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3754 3755 result = DAG.getNode(ISD::BITCAST, dl, 3756 MVT::f32, TwoToFractionalPartOfX); 3757 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3758 // For floating-point precision of 12: 3759 // 3760 // TwoToFractionalPartOfX = 3761 // 0.999892986f + 3762 // (0.696457318f + 3763 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3764 // 3765 // error 0.000107046256, which is 13 to 14 bits 3766 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3767 getF32Constant(DAG, 0x3da235e3)); 3768 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3769 getF32Constant(DAG, 0x3e65b8f3)); 3770 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3771 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3772 getF32Constant(DAG, 0x3f324b07)); 3773 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3774 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3775 getF32Constant(DAG, 0x3f7ff8fd)); 3776 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3777 SDValue TwoToFractionalPartOfX = 3778 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3779 3780 result = DAG.getNode(ISD::BITCAST, dl, 3781 MVT::f32, TwoToFractionalPartOfX); 3782 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3783 // For floating-point precision of 18: 3784 // 3785 // TwoToFractionalPartOfX = 3786 // 0.999999982f + 3787 // (0.693148872f + 3788 // (0.240227044f + 3789 // (0.554906021e-1f + 3790 // (0.961591928e-2f + 3791 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3792 // error 2.47208000*10^(-7), which is better than 18 bits 3793 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3794 getF32Constant(DAG, 0x3924b03e)); 3795 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3796 getF32Constant(DAG, 0x3ab24b87)); 3797 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3798 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3799 getF32Constant(DAG, 0x3c1d8c17)); 3800 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3801 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3802 getF32Constant(DAG, 0x3d634a1d)); 3803 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3804 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3805 getF32Constant(DAG, 0x3e75fe14)); 3806 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3807 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3808 getF32Constant(DAG, 0x3f317234)); 3809 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3810 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3811 getF32Constant(DAG, 0x3f800000)); 3812 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 3813 SDValue TwoToFractionalPartOfX = 3814 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3815 3816 result = DAG.getNode(ISD::BITCAST, dl, 3817 MVT::f32, TwoToFractionalPartOfX); 3818 } 3819 } else { 3820 // No special expansion. 3821 result = DAG.getNode(ISD::FEXP2, dl, 3822 getValue(I.getArgOperand(0)).getValueType(), 3823 getValue(I.getArgOperand(0))); 3824 } 3825 3826 setValue(&I, result); 3827} 3828 3829/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3830/// limited-precision mode with x == 10.0f. 3831void 3832SelectionDAGBuilder::visitPow(const CallInst &I) { 3833 SDValue result; 3834 const Value *Val = I.getArgOperand(0); 3835 DebugLoc dl = getCurDebugLoc(); 3836 bool IsExp10 = false; 3837 3838 if (getValue(Val).getValueType() == MVT::f32 && 3839 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 3840 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3841 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3842 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3843 APFloat Ten(10.0f); 3844 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3845 } 3846 } 3847 } 3848 3849 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3850 SDValue Op = getValue(I.getArgOperand(1)); 3851 3852 // Put the exponent in the right bit position for later addition to the 3853 // final result: 3854 // 3855 // #define LOG2OF10 3.3219281f 3856 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3857 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3858 getF32Constant(DAG, 0x40549a78)); 3859 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3860 3861 // FractionalPartOfX = x - (float)IntegerPartOfX; 3862 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3863 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3864 3865 // IntegerPartOfX <<= 23; 3866 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3867 DAG.getConstant(23, TLI.getPointerTy())); 3868 3869 if (LimitFloatPrecision <= 6) { 3870 // For floating-point precision of 6: 3871 // 3872 // twoToFractionalPartOfX = 3873 // 0.997535578f + 3874 // (0.735607626f + 0.252464424f * x) * x; 3875 // 3876 // error 0.0144103317, which is 6 bits 3877 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3878 getF32Constant(DAG, 0x3e814304)); 3879 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3880 getF32Constant(DAG, 0x3f3c50c8)); 3881 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3882 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3883 getF32Constant(DAG, 0x3f7f5e7e)); 3884 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3885 SDValue TwoToFractionalPartOfX = 3886 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3887 3888 result = DAG.getNode(ISD::BITCAST, dl, 3889 MVT::f32, TwoToFractionalPartOfX); 3890 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3891 // For floating-point precision of 12: 3892 // 3893 // TwoToFractionalPartOfX = 3894 // 0.999892986f + 3895 // (0.696457318f + 3896 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3897 // 3898 // error 0.000107046256, which is 13 to 14 bits 3899 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3900 getF32Constant(DAG, 0x3da235e3)); 3901 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3902 getF32Constant(DAG, 0x3e65b8f3)); 3903 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3904 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3905 getF32Constant(DAG, 0x3f324b07)); 3906 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3907 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3908 getF32Constant(DAG, 0x3f7ff8fd)); 3909 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3910 SDValue TwoToFractionalPartOfX = 3911 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3912 3913 result = DAG.getNode(ISD::BITCAST, dl, 3914 MVT::f32, TwoToFractionalPartOfX); 3915 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3916 // For floating-point precision of 18: 3917 // 3918 // TwoToFractionalPartOfX = 3919 // 0.999999982f + 3920 // (0.693148872f + 3921 // (0.240227044f + 3922 // (0.554906021e-1f + 3923 // (0.961591928e-2f + 3924 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3925 // error 2.47208000*10^(-7), which is better than 18 bits 3926 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3927 getF32Constant(DAG, 0x3924b03e)); 3928 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3929 getF32Constant(DAG, 0x3ab24b87)); 3930 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3931 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3932 getF32Constant(DAG, 0x3c1d8c17)); 3933 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3934 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3935 getF32Constant(DAG, 0x3d634a1d)); 3936 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3937 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3938 getF32Constant(DAG, 0x3e75fe14)); 3939 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3940 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3941 getF32Constant(DAG, 0x3f317234)); 3942 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3943 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3944 getF32Constant(DAG, 0x3f800000)); 3945 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 3946 SDValue TwoToFractionalPartOfX = 3947 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3948 3949 result = DAG.getNode(ISD::BITCAST, dl, 3950 MVT::f32, TwoToFractionalPartOfX); 3951 } 3952 } else { 3953 // No special expansion. 3954 result = DAG.getNode(ISD::FPOW, dl, 3955 getValue(I.getArgOperand(0)).getValueType(), 3956 getValue(I.getArgOperand(0)), 3957 getValue(I.getArgOperand(1))); 3958 } 3959 3960 setValue(&I, result); 3961} 3962 3963 3964/// ExpandPowI - Expand a llvm.powi intrinsic. 3965static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 3966 SelectionDAG &DAG) { 3967 // If RHS is a constant, we can expand this out to a multiplication tree, 3968 // otherwise we end up lowering to a call to __powidf2 (for example). When 3969 // optimizing for size, we only want to do this if the expansion would produce 3970 // a small number of multiplies, otherwise we do the full expansion. 3971 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3972 // Get the exponent as a positive value. 3973 unsigned Val = RHSC->getSExtValue(); 3974 if ((int)Val < 0) Val = -Val; 3975 3976 // powi(x, 0) -> 1.0 3977 if (Val == 0) 3978 return DAG.getConstantFP(1.0, LHS.getValueType()); 3979 3980 const Function *F = DAG.getMachineFunction().getFunction(); 3981 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 3982 // If optimizing for size, don't insert too many multiplies. This 3983 // inserts up to 5 multiplies. 3984 CountPopulation_32(Val)+Log2_32(Val) < 7) { 3985 // We use the simple binary decomposition method to generate the multiply 3986 // sequence. There are more optimal ways to do this (for example, 3987 // powi(x,15) generates one more multiply than it should), but this has 3988 // the benefit of being both really simple and much better than a libcall. 3989 SDValue Res; // Logically starts equal to 1.0 3990 SDValue CurSquare = LHS; 3991 while (Val) { 3992 if (Val & 1) { 3993 if (Res.getNode()) 3994 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 3995 else 3996 Res = CurSquare; // 1.0*CurSquare. 3997 } 3998 3999 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4000 CurSquare, CurSquare); 4001 Val >>= 1; 4002 } 4003 4004 // If the original was negative, invert the result, producing 1/(x*x*x). 4005 if (RHSC->getSExtValue() < 0) 4006 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4007 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4008 return Res; 4009 } 4010 } 4011 4012 // Otherwise, expand to a libcall. 4013 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4014} 4015 4016/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4017/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4018/// At the end of instruction selection, they will be inserted to the entry BB. 4019bool 4020SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4021 int64_t Offset, 4022 const SDValue &N) { 4023 const Argument *Arg = dyn_cast<Argument>(V); 4024 if (!Arg) 4025 return false; 4026 4027 MachineFunction &MF = DAG.getMachineFunction(); 4028 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4029 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4030 4031 // Ignore inlined function arguments here. 4032 DIVariable DV(Variable); 4033 if (DV.isInlinedFnArgument(MF.getFunction())) 4034 return false; 4035 4036 unsigned Reg = 0; 4037 if (Arg->hasByValAttr()) { 4038 // Byval arguments' frame index is recorded during argument lowering. 4039 // Use this info directly. 4040 Reg = TRI->getFrameRegister(MF); 4041 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 4042 // If byval argument ofset is not recorded then ignore this. 4043 if (!Offset) 4044 Reg = 0; 4045 } 4046 4047 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) { 4048 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4049 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 4050 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4051 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4052 if (PR) 4053 Reg = PR; 4054 } 4055 } 4056 4057 if (!Reg) { 4058 // Check if ValueMap has reg number. 4059 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4060 if (VMI != FuncInfo.ValueMap.end()) 4061 Reg = VMI->second; 4062 } 4063 4064 if (!Reg && N.getNode()) { 4065 // Check if frame index is available. 4066 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4067 if (FrameIndexSDNode *FINode = 4068 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4069 Reg = TRI->getFrameRegister(MF); 4070 Offset = FINode->getIndex(); 4071 } 4072 } 4073 4074 if (!Reg) 4075 return false; 4076 4077 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4078 TII->get(TargetOpcode::DBG_VALUE)) 4079 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4080 FuncInfo.ArgDbgValues.push_back(&*MIB); 4081 return true; 4082} 4083 4084// VisualStudio defines setjmp as _setjmp 4085#if defined(_MSC_VER) && defined(setjmp) && \ 4086 !defined(setjmp_undefined_for_msvc) 4087# pragma push_macro("setjmp") 4088# undef setjmp 4089# define setjmp_undefined_for_msvc 4090#endif 4091 4092/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4093/// we want to emit this as a call to a named external function, return the name 4094/// otherwise lower it and return null. 4095const char * 4096SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4097 DebugLoc dl = getCurDebugLoc(); 4098 SDValue Res; 4099 4100 switch (Intrinsic) { 4101 default: 4102 // By default, turn this into a target intrinsic node. 4103 visitTargetIntrinsic(I, Intrinsic); 4104 return 0; 4105 case Intrinsic::vastart: visitVAStart(I); return 0; 4106 case Intrinsic::vaend: visitVAEnd(I); return 0; 4107 case Intrinsic::vacopy: visitVACopy(I); return 0; 4108 case Intrinsic::returnaddress: 4109 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4110 getValue(I.getArgOperand(0)))); 4111 return 0; 4112 case Intrinsic::frameaddress: 4113 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4114 getValue(I.getArgOperand(0)))); 4115 return 0; 4116 case Intrinsic::setjmp: 4117 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4118 case Intrinsic::longjmp: 4119 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4120 case Intrinsic::memcpy: { 4121 // Assert for address < 256 since we support only user defined address 4122 // spaces. 4123 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4124 < 256 && 4125 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4126 < 256 && 4127 "Unknown address space"); 4128 SDValue Op1 = getValue(I.getArgOperand(0)); 4129 SDValue Op2 = getValue(I.getArgOperand(1)); 4130 SDValue Op3 = getValue(I.getArgOperand(2)); 4131 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4132 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4133 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4134 MachinePointerInfo(I.getArgOperand(0)), 4135 MachinePointerInfo(I.getArgOperand(1)))); 4136 return 0; 4137 } 4138 case Intrinsic::memset: { 4139 // Assert for address < 256 since we support only user defined address 4140 // spaces. 4141 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4142 < 256 && 4143 "Unknown address space"); 4144 SDValue Op1 = getValue(I.getArgOperand(0)); 4145 SDValue Op2 = getValue(I.getArgOperand(1)); 4146 SDValue Op3 = getValue(I.getArgOperand(2)); 4147 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4148 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4149 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4150 MachinePointerInfo(I.getArgOperand(0)))); 4151 return 0; 4152 } 4153 case Intrinsic::memmove: { 4154 // Assert for address < 256 since we support only user defined address 4155 // spaces. 4156 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4157 < 256 && 4158 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4159 < 256 && 4160 "Unknown address space"); 4161 SDValue Op1 = getValue(I.getArgOperand(0)); 4162 SDValue Op2 = getValue(I.getArgOperand(1)); 4163 SDValue Op3 = getValue(I.getArgOperand(2)); 4164 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4165 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4166 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4167 MachinePointerInfo(I.getArgOperand(0)), 4168 MachinePointerInfo(I.getArgOperand(1)))); 4169 return 0; 4170 } 4171 case Intrinsic::dbg_declare: { 4172 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4173 MDNode *Variable = DI.getVariable(); 4174 const Value *Address = DI.getAddress(); 4175 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4176 return 0; 4177 4178 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4179 // but do not always have a corresponding SDNode built. The SDNodeOrder 4180 // absolute, but not relative, values are different depending on whether 4181 // debug info exists. 4182 ++SDNodeOrder; 4183 4184 // Check if address has undef value. 4185 if (isa<UndefValue>(Address) || 4186 (Address->use_empty() && !isa<Argument>(Address))) { 4187 DEBUG(dbgs() << "Dropping debug info for " << DI); 4188 return 0; 4189 } 4190 4191 SDValue &N = NodeMap[Address]; 4192 if (!N.getNode() && isa<Argument>(Address)) 4193 // Check unused arguments map. 4194 N = UnusedArgNodeMap[Address]; 4195 SDDbgValue *SDV; 4196 if (N.getNode()) { 4197 // Parameters are handled specially. 4198 bool isParameter = 4199 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4200 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4201 Address = BCI->getOperand(0); 4202 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4203 4204 if (isParameter && !AI) { 4205 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4206 if (FINode) 4207 // Byval parameter. We have a frame index at this point. 4208 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4209 0, dl, SDNodeOrder); 4210 else { 4211 // Can't do anything with other non-AI cases yet. This might be a 4212 // parameter of a callee function that got inlined, for example. 4213 DEBUG(dbgs() << "Dropping debug info for " << DI); 4214 return 0; 4215 } 4216 } else if (AI) 4217 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4218 0, dl, SDNodeOrder); 4219 else { 4220 // Can't do anything with other non-AI cases yet. 4221 DEBUG(dbgs() << "Dropping debug info for " << DI); 4222 return 0; 4223 } 4224 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4225 } else { 4226 // If Address is an argument then try to emit its dbg value using 4227 // virtual register info from the FuncInfo.ValueMap. 4228 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4229 // If variable is pinned by a alloca in dominating bb then 4230 // use StaticAllocaMap. 4231 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4232 if (AI->getParent() != DI.getParent()) { 4233 DenseMap<const AllocaInst*, int>::iterator SI = 4234 FuncInfo.StaticAllocaMap.find(AI); 4235 if (SI != FuncInfo.StaticAllocaMap.end()) { 4236 SDV = DAG.getDbgValue(Variable, SI->second, 4237 0, dl, SDNodeOrder); 4238 DAG.AddDbgValue(SDV, 0, false); 4239 return 0; 4240 } 4241 } 4242 } 4243 DEBUG(dbgs() << "Dropping debug info for " << DI); 4244 } 4245 } 4246 return 0; 4247 } 4248 case Intrinsic::dbg_value: { 4249 const DbgValueInst &DI = cast<DbgValueInst>(I); 4250 if (!DIVariable(DI.getVariable()).Verify()) 4251 return 0; 4252 4253 MDNode *Variable = DI.getVariable(); 4254 uint64_t Offset = DI.getOffset(); 4255 const Value *V = DI.getValue(); 4256 if (!V) 4257 return 0; 4258 4259 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4260 // but do not always have a corresponding SDNode built. The SDNodeOrder 4261 // absolute, but not relative, values are different depending on whether 4262 // debug info exists. 4263 ++SDNodeOrder; 4264 SDDbgValue *SDV; 4265 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4266 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4267 DAG.AddDbgValue(SDV, 0, false); 4268 } else { 4269 // Do not use getValue() in here; we don't want to generate code at 4270 // this point if it hasn't been done yet. 4271 SDValue N = NodeMap[V]; 4272 if (!N.getNode() && isa<Argument>(V)) 4273 // Check unused arguments map. 4274 N = UnusedArgNodeMap[V]; 4275 if (N.getNode()) { 4276 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4277 SDV = DAG.getDbgValue(Variable, N.getNode(), 4278 N.getResNo(), Offset, dl, SDNodeOrder); 4279 DAG.AddDbgValue(SDV, N.getNode(), false); 4280 } 4281 } else if (!V->use_empty() ) { 4282 // Do not call getValue(V) yet, as we don't want to generate code. 4283 // Remember it for later. 4284 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4285 DanglingDebugInfoMap[V] = DDI; 4286 } else { 4287 // We may expand this to cover more cases. One case where we have no 4288 // data available is an unreferenced parameter. 4289 DEBUG(dbgs() << "Dropping debug info for " << DI); 4290 } 4291 } 4292 4293 // Build a debug info table entry. 4294 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4295 V = BCI->getOperand(0); 4296 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4297 // Don't handle byval struct arguments or VLAs, for example. 4298 if (!AI) 4299 return 0; 4300 DenseMap<const AllocaInst*, int>::iterator SI = 4301 FuncInfo.StaticAllocaMap.find(AI); 4302 if (SI == FuncInfo.StaticAllocaMap.end()) 4303 return 0; // VLAs. 4304 int FI = SI->second; 4305 4306 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4307 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4308 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4309 return 0; 4310 } 4311 case Intrinsic::eh_exception: { 4312 // Insert the EXCEPTIONADDR instruction. 4313 assert(FuncInfo.MBB->isLandingPad() && 4314 "Call to eh.exception not in landing pad!"); 4315 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4316 SDValue Ops[1]; 4317 Ops[0] = DAG.getRoot(); 4318 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4319 setValue(&I, Op); 4320 DAG.setRoot(Op.getValue(1)); 4321 return 0; 4322 } 4323 4324 case Intrinsic::eh_selector: { 4325 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4326 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4327 if (CallMBB->isLandingPad()) 4328 AddCatchInfo(I, &MMI, CallMBB); 4329 else { 4330#ifndef NDEBUG 4331 FuncInfo.CatchInfoLost.insert(&I); 4332#endif 4333 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4334 unsigned Reg = TLI.getExceptionSelectorRegister(); 4335 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4336 } 4337 4338 // Insert the EHSELECTION instruction. 4339 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4340 SDValue Ops[2]; 4341 Ops[0] = getValue(I.getArgOperand(0)); 4342 Ops[1] = getRoot(); 4343 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4344 DAG.setRoot(Op.getValue(1)); 4345 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4346 return 0; 4347 } 4348 4349 case Intrinsic::eh_typeid_for: { 4350 // Find the type id for the given typeinfo. 4351 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4352 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4353 Res = DAG.getConstant(TypeID, MVT::i32); 4354 setValue(&I, Res); 4355 return 0; 4356 } 4357 4358 case Intrinsic::eh_return_i32: 4359 case Intrinsic::eh_return_i64: 4360 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4361 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4362 MVT::Other, 4363 getControlRoot(), 4364 getValue(I.getArgOperand(0)), 4365 getValue(I.getArgOperand(1)))); 4366 return 0; 4367 case Intrinsic::eh_unwind_init: 4368 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4369 return 0; 4370 case Intrinsic::eh_dwarf_cfa: { 4371 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4372 TLI.getPointerTy()); 4373 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4374 TLI.getPointerTy(), 4375 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4376 TLI.getPointerTy()), 4377 CfaArg); 4378 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4379 TLI.getPointerTy(), 4380 DAG.getConstant(0, TLI.getPointerTy())); 4381 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4382 FA, Offset)); 4383 return 0; 4384 } 4385 case Intrinsic::eh_sjlj_callsite: { 4386 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4387 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4388 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4389 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4390 4391 MMI.setCurrentCallSite(CI->getZExtValue()); 4392 return 0; 4393 } 4394 case Intrinsic::eh_sjlj_setjmp: { 4395 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4396 getValue(I.getArgOperand(0)))); 4397 return 0; 4398 } 4399 case Intrinsic::eh_sjlj_longjmp: { 4400 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4401 getRoot(), getValue(I.getArgOperand(0)))); 4402 return 0; 4403 } 4404 case Intrinsic::eh_sjlj_dispatch_setup: { 4405 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4406 getRoot())); 4407 return 0; 4408 } 4409 4410 case Intrinsic::x86_mmx_pslli_w: 4411 case Intrinsic::x86_mmx_pslli_d: 4412 case Intrinsic::x86_mmx_pslli_q: 4413 case Intrinsic::x86_mmx_psrli_w: 4414 case Intrinsic::x86_mmx_psrli_d: 4415 case Intrinsic::x86_mmx_psrli_q: 4416 case Intrinsic::x86_mmx_psrai_w: 4417 case Intrinsic::x86_mmx_psrai_d: { 4418 SDValue ShAmt = getValue(I.getArgOperand(1)); 4419 if (isa<ConstantSDNode>(ShAmt)) { 4420 visitTargetIntrinsic(I, Intrinsic); 4421 return 0; 4422 } 4423 unsigned NewIntrinsic = 0; 4424 EVT ShAmtVT = MVT::v2i32; 4425 switch (Intrinsic) { 4426 case Intrinsic::x86_mmx_pslli_w: 4427 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4428 break; 4429 case Intrinsic::x86_mmx_pslli_d: 4430 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4431 break; 4432 case Intrinsic::x86_mmx_pslli_q: 4433 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4434 break; 4435 case Intrinsic::x86_mmx_psrli_w: 4436 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4437 break; 4438 case Intrinsic::x86_mmx_psrli_d: 4439 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4440 break; 4441 case Intrinsic::x86_mmx_psrli_q: 4442 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4443 break; 4444 case Intrinsic::x86_mmx_psrai_w: 4445 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4446 break; 4447 case Intrinsic::x86_mmx_psrai_d: 4448 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4449 break; 4450 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4451 } 4452 4453 // The vector shift intrinsics with scalars uses 32b shift amounts but 4454 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4455 // to be zero. 4456 // We must do this early because v2i32 is not a legal type. 4457 DebugLoc dl = getCurDebugLoc(); 4458 SDValue ShOps[2]; 4459 ShOps[0] = ShAmt; 4460 ShOps[1] = DAG.getConstant(0, MVT::i32); 4461 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4462 EVT DestVT = TLI.getValueType(I.getType()); 4463 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4464 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4465 DAG.getConstant(NewIntrinsic, MVT::i32), 4466 getValue(I.getArgOperand(0)), ShAmt); 4467 setValue(&I, Res); 4468 return 0; 4469 } 4470 case Intrinsic::convertff: 4471 case Intrinsic::convertfsi: 4472 case Intrinsic::convertfui: 4473 case Intrinsic::convertsif: 4474 case Intrinsic::convertuif: 4475 case Intrinsic::convertss: 4476 case Intrinsic::convertsu: 4477 case Intrinsic::convertus: 4478 case Intrinsic::convertuu: { 4479 ISD::CvtCode Code = ISD::CVT_INVALID; 4480 switch (Intrinsic) { 4481 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4482 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4483 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4484 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4485 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4486 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4487 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4488 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4489 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4490 } 4491 EVT DestVT = TLI.getValueType(I.getType()); 4492 const Value *Op1 = I.getArgOperand(0); 4493 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4494 DAG.getValueType(DestVT), 4495 DAG.getValueType(getValue(Op1).getValueType()), 4496 getValue(I.getArgOperand(1)), 4497 getValue(I.getArgOperand(2)), 4498 Code); 4499 setValue(&I, Res); 4500 return 0; 4501 } 4502 case Intrinsic::sqrt: 4503 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4504 getValue(I.getArgOperand(0)).getValueType(), 4505 getValue(I.getArgOperand(0)))); 4506 return 0; 4507 case Intrinsic::powi: 4508 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4509 getValue(I.getArgOperand(1)), DAG)); 4510 return 0; 4511 case Intrinsic::sin: 4512 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4513 getValue(I.getArgOperand(0)).getValueType(), 4514 getValue(I.getArgOperand(0)))); 4515 return 0; 4516 case Intrinsic::cos: 4517 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4518 getValue(I.getArgOperand(0)).getValueType(), 4519 getValue(I.getArgOperand(0)))); 4520 return 0; 4521 case Intrinsic::log: 4522 visitLog(I); 4523 return 0; 4524 case Intrinsic::log2: 4525 visitLog2(I); 4526 return 0; 4527 case Intrinsic::log10: 4528 visitLog10(I); 4529 return 0; 4530 case Intrinsic::exp: 4531 visitExp(I); 4532 return 0; 4533 case Intrinsic::exp2: 4534 visitExp2(I); 4535 return 0; 4536 case Intrinsic::pow: 4537 visitPow(I); 4538 return 0; 4539 case Intrinsic::convert_to_fp16: 4540 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4541 MVT::i16, getValue(I.getArgOperand(0)))); 4542 return 0; 4543 case Intrinsic::convert_from_fp16: 4544 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4545 MVT::f32, getValue(I.getArgOperand(0)))); 4546 return 0; 4547 case Intrinsic::pcmarker: { 4548 SDValue Tmp = getValue(I.getArgOperand(0)); 4549 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4550 return 0; 4551 } 4552 case Intrinsic::readcyclecounter: { 4553 SDValue Op = getRoot(); 4554 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4555 DAG.getVTList(MVT::i64, MVT::Other), 4556 &Op, 1); 4557 setValue(&I, Res); 4558 DAG.setRoot(Res.getValue(1)); 4559 return 0; 4560 } 4561 case Intrinsic::bswap: 4562 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4563 getValue(I.getArgOperand(0)).getValueType(), 4564 getValue(I.getArgOperand(0)))); 4565 return 0; 4566 case Intrinsic::cttz: { 4567 SDValue Arg = getValue(I.getArgOperand(0)); 4568 EVT Ty = Arg.getValueType(); 4569 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4570 return 0; 4571 } 4572 case Intrinsic::ctlz: { 4573 SDValue Arg = getValue(I.getArgOperand(0)); 4574 EVT Ty = Arg.getValueType(); 4575 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4576 return 0; 4577 } 4578 case Intrinsic::ctpop: { 4579 SDValue Arg = getValue(I.getArgOperand(0)); 4580 EVT Ty = Arg.getValueType(); 4581 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4582 return 0; 4583 } 4584 case Intrinsic::stacksave: { 4585 SDValue Op = getRoot(); 4586 Res = DAG.getNode(ISD::STACKSAVE, dl, 4587 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4588 setValue(&I, Res); 4589 DAG.setRoot(Res.getValue(1)); 4590 return 0; 4591 } 4592 case Intrinsic::stackrestore: { 4593 Res = getValue(I.getArgOperand(0)); 4594 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4595 return 0; 4596 } 4597 case Intrinsic::stackprotector: { 4598 // Emit code into the DAG to store the stack guard onto the stack. 4599 MachineFunction &MF = DAG.getMachineFunction(); 4600 MachineFrameInfo *MFI = MF.getFrameInfo(); 4601 EVT PtrTy = TLI.getPointerTy(); 4602 4603 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4604 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4605 4606 int FI = FuncInfo.StaticAllocaMap[Slot]; 4607 MFI->setStackProtectorIndex(FI); 4608 4609 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4610 4611 // Store the stack protector onto the stack. 4612 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4613 MachinePointerInfo::getFixedStack(FI), 4614 true, false, 0); 4615 setValue(&I, Res); 4616 DAG.setRoot(Res); 4617 return 0; 4618 } 4619 case Intrinsic::objectsize: { 4620 // If we don't know by now, we're never going to know. 4621 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4622 4623 assert(CI && "Non-constant type in __builtin_object_size?"); 4624 4625 SDValue Arg = getValue(I.getCalledValue()); 4626 EVT Ty = Arg.getValueType(); 4627 4628 if (CI->isZero()) 4629 Res = DAG.getConstant(-1ULL, Ty); 4630 else 4631 Res = DAG.getConstant(0, Ty); 4632 4633 setValue(&I, Res); 4634 return 0; 4635 } 4636 case Intrinsic::var_annotation: 4637 // Discard annotate attributes 4638 return 0; 4639 4640 case Intrinsic::init_trampoline: { 4641 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4642 4643 SDValue Ops[6]; 4644 Ops[0] = getRoot(); 4645 Ops[1] = getValue(I.getArgOperand(0)); 4646 Ops[2] = getValue(I.getArgOperand(1)); 4647 Ops[3] = getValue(I.getArgOperand(2)); 4648 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4649 Ops[5] = DAG.getSrcValue(F); 4650 4651 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4652 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4653 Ops, 6); 4654 4655 setValue(&I, Res); 4656 DAG.setRoot(Res.getValue(1)); 4657 return 0; 4658 } 4659 case Intrinsic::gcroot: 4660 if (GFI) { 4661 const Value *Alloca = I.getArgOperand(0); 4662 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4663 4664 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4665 GFI->addStackRoot(FI->getIndex(), TypeMap); 4666 } 4667 return 0; 4668 case Intrinsic::gcread: 4669 case Intrinsic::gcwrite: 4670 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4671 return 0; 4672 case Intrinsic::flt_rounds: 4673 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4674 return 0; 4675 case Intrinsic::trap: { 4676 StringRef TrapFuncName = getTrapFunctionName(); 4677 if (TrapFuncName.empty()) { 4678 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4679 return 0; 4680 } 4681 TargetLowering::ArgListTy Args; 4682 std::pair<SDValue, SDValue> Result = 4683 TLI.LowerCallTo(getRoot(), I.getType(), 4684 false, false, false, false, 0, CallingConv::C, 4685 /*isTailCall=*/false, /*isReturnValueUsed=*/true, 4686 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 4687 Args, DAG, getCurDebugLoc()); 4688 DAG.setRoot(Result.second); 4689 return 0; 4690 } 4691 case Intrinsic::uadd_with_overflow: 4692 return implVisitAluOverflow(I, ISD::UADDO); 4693 case Intrinsic::sadd_with_overflow: 4694 return implVisitAluOverflow(I, ISD::SADDO); 4695 case Intrinsic::usub_with_overflow: 4696 return implVisitAluOverflow(I, ISD::USUBO); 4697 case Intrinsic::ssub_with_overflow: 4698 return implVisitAluOverflow(I, ISD::SSUBO); 4699 case Intrinsic::umul_with_overflow: 4700 return implVisitAluOverflow(I, ISD::UMULO); 4701 case Intrinsic::smul_with_overflow: 4702 return implVisitAluOverflow(I, ISD::SMULO); 4703 4704 case Intrinsic::prefetch: { 4705 SDValue Ops[4]; 4706 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 4707 Ops[0] = getRoot(); 4708 Ops[1] = getValue(I.getArgOperand(0)); 4709 Ops[2] = getValue(I.getArgOperand(1)); 4710 Ops[3] = getValue(I.getArgOperand(2)); 4711 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 4712 DAG.getVTList(MVT::Other), 4713 &Ops[0], 4, 4714 EVT::getIntegerVT(*Context, 8), 4715 MachinePointerInfo(I.getArgOperand(0)), 4716 0, /* align */ 4717 false, /* volatile */ 4718 rw==0, /* read */ 4719 rw==1)); /* write */ 4720 return 0; 4721 } 4722 case Intrinsic::memory_barrier: { 4723 SDValue Ops[6]; 4724 Ops[0] = getRoot(); 4725 for (int x = 1; x < 6; ++x) 4726 Ops[x] = getValue(I.getArgOperand(x - 1)); 4727 4728 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4729 return 0; 4730 } 4731 case Intrinsic::atomic_cmp_swap: { 4732 SDValue Root = getRoot(); 4733 SDValue L = 4734 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4735 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 4736 Root, 4737 getValue(I.getArgOperand(0)), 4738 getValue(I.getArgOperand(1)), 4739 getValue(I.getArgOperand(2)), 4740 MachinePointerInfo(I.getArgOperand(0))); 4741 setValue(&I, L); 4742 DAG.setRoot(L.getValue(1)); 4743 return 0; 4744 } 4745 case Intrinsic::atomic_load_add: 4746 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4747 case Intrinsic::atomic_load_sub: 4748 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4749 case Intrinsic::atomic_load_or: 4750 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4751 case Intrinsic::atomic_load_xor: 4752 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4753 case Intrinsic::atomic_load_and: 4754 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4755 case Intrinsic::atomic_load_nand: 4756 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4757 case Intrinsic::atomic_load_max: 4758 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4759 case Intrinsic::atomic_load_min: 4760 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4761 case Intrinsic::atomic_load_umin: 4762 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4763 case Intrinsic::atomic_load_umax: 4764 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4765 case Intrinsic::atomic_swap: 4766 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4767 4768 case Intrinsic::invariant_start: 4769 case Intrinsic::lifetime_start: 4770 // Discard region information. 4771 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4772 return 0; 4773 case Intrinsic::invariant_end: 4774 case Intrinsic::lifetime_end: 4775 // Discard region information. 4776 return 0; 4777 } 4778} 4779 4780void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 4781 bool isTailCall, 4782 MachineBasicBlock *LandingPad) { 4783 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4784 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4785 const Type *RetTy = FTy->getReturnType(); 4786 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4787 MCSymbol *BeginLabel = 0; 4788 4789 TargetLowering::ArgListTy Args; 4790 TargetLowering::ArgListEntry Entry; 4791 Args.reserve(CS.arg_size()); 4792 4793 // Check whether the function can return without sret-demotion. 4794 SmallVector<ISD::OutputArg, 4> Outs; 4795 SmallVector<uint64_t, 4> Offsets; 4796 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4797 Outs, TLI, &Offsets); 4798 4799 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4800 FTy->isVarArg(), Outs, FTy->getContext()); 4801 4802 SDValue DemoteStackSlot; 4803 int DemoteStackIdx = -100; 4804 4805 if (!CanLowerReturn) { 4806 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4807 FTy->getReturnType()); 4808 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4809 FTy->getReturnType()); 4810 MachineFunction &MF = DAG.getMachineFunction(); 4811 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4812 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4813 4814 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 4815 Entry.Node = DemoteStackSlot; 4816 Entry.Ty = StackSlotPtrType; 4817 Entry.isSExt = false; 4818 Entry.isZExt = false; 4819 Entry.isInReg = false; 4820 Entry.isSRet = true; 4821 Entry.isNest = false; 4822 Entry.isByVal = false; 4823 Entry.Alignment = Align; 4824 Args.push_back(Entry); 4825 RetTy = Type::getVoidTy(FTy->getContext()); 4826 } 4827 4828 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4829 i != e; ++i) { 4830 SDValue ArgNode = getValue(*i); 4831 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 4832 4833 unsigned attrInd = i - CS.arg_begin() + 1; 4834 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4835 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4836 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4837 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4838 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4839 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4840 Entry.Alignment = CS.getParamAlignment(attrInd); 4841 Args.push_back(Entry); 4842 } 4843 4844 if (LandingPad) { 4845 // Insert a label before the invoke call to mark the try range. This can be 4846 // used to detect deletion of the invoke via the MachineModuleInfo. 4847 BeginLabel = MMI.getContext().CreateTempSymbol(); 4848 4849 // For SjLj, keep track of which landing pads go with which invokes 4850 // so as to maintain the ordering of pads in the LSDA. 4851 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 4852 if (CallSiteIndex) { 4853 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4854 // Now that the call site is handled, stop tracking it. 4855 MMI.setCurrentCallSite(0); 4856 } 4857 4858 // Both PendingLoads and PendingExports must be flushed here; 4859 // this call might not return. 4860 (void)getRoot(); 4861 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4862 } 4863 4864 // Check if target-independent constraints permit a tail call here. 4865 // Target-dependent constraints are checked within TLI.LowerCallTo. 4866 if (isTailCall && 4867 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4868 isTailCall = false; 4869 4870 // If there's a possibility that fast-isel has already selected some amount 4871 // of the current basic block, don't emit a tail call. 4872 if (isTailCall && EnableFastISel) 4873 isTailCall = false; 4874 4875 std::pair<SDValue,SDValue> Result = 4876 TLI.LowerCallTo(getRoot(), RetTy, 4877 CS.paramHasAttr(0, Attribute::SExt), 4878 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4879 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4880 CS.getCallingConv(), 4881 isTailCall, 4882 !CS.getInstruction()->use_empty(), 4883 Callee, Args, DAG, getCurDebugLoc()); 4884 assert((isTailCall || Result.second.getNode()) && 4885 "Non-null chain expected with non-tail call!"); 4886 assert((Result.second.getNode() || !Result.first.getNode()) && 4887 "Null value expected with tail call!"); 4888 if (Result.first.getNode()) { 4889 setValue(CS.getInstruction(), Result.first); 4890 } else if (!CanLowerReturn && Result.second.getNode()) { 4891 // The instruction result is the result of loading from the 4892 // hidden sret parameter. 4893 SmallVector<EVT, 1> PVTs; 4894 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 4895 4896 ComputeValueVTs(TLI, PtrRetTy, PVTs); 4897 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 4898 EVT PtrVT = PVTs[0]; 4899 unsigned NumValues = Outs.size(); 4900 SmallVector<SDValue, 4> Values(NumValues); 4901 SmallVector<SDValue, 4> Chains(NumValues); 4902 4903 for (unsigned i = 0; i < NumValues; ++i) { 4904 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 4905 DemoteStackSlot, 4906 DAG.getConstant(Offsets[i], PtrVT)); 4907 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 4908 Add, 4909 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 4910 false, false, 1); 4911 Values[i] = L; 4912 Chains[i] = L.getValue(1); 4913 } 4914 4915 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 4916 MVT::Other, &Chains[0], NumValues); 4917 PendingLoads.push_back(Chain); 4918 4919 // Collect the legal value parts into potentially illegal values 4920 // that correspond to the original function's return values. 4921 SmallVector<EVT, 4> RetTys; 4922 RetTy = FTy->getReturnType(); 4923 ComputeValueVTs(TLI, RetTy, RetTys); 4924 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4925 SmallVector<SDValue, 4> ReturnValues; 4926 unsigned CurReg = 0; 4927 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4928 EVT VT = RetTys[I]; 4929 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 4930 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 4931 4932 SDValue ReturnValue = 4933 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 4934 RegisterVT, VT, AssertOp); 4935 ReturnValues.push_back(ReturnValue); 4936 CurReg += NumRegs; 4937 } 4938 4939 setValue(CS.getInstruction(), 4940 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 4941 DAG.getVTList(&RetTys[0], RetTys.size()), 4942 &ReturnValues[0], ReturnValues.size())); 4943 } 4944 4945 // Assign order to nodes here. If the call does not produce a result, it won't 4946 // be mapped to a SDNode and visit() will not assign it an order number. 4947 if (!Result.second.getNode()) { 4948 // As a special case, a null chain means that a tail call has been emitted and 4949 // the DAG root is already updated. 4950 HasTailCall = true; 4951 ++SDNodeOrder; 4952 AssignOrderingToNode(DAG.getRoot().getNode()); 4953 } else { 4954 DAG.setRoot(Result.second); 4955 ++SDNodeOrder; 4956 AssignOrderingToNode(Result.second.getNode()); 4957 } 4958 4959 if (LandingPad) { 4960 // Insert a label at the end of the invoke call to mark the try range. This 4961 // can be used to detect deletion of the invoke via the MachineModuleInfo. 4962 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 4963 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 4964 4965 // Inform MachineModuleInfo of range. 4966 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 4967 } 4968} 4969 4970/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 4971/// value is equal or not-equal to zero. 4972static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 4973 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 4974 UI != E; ++UI) { 4975 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 4976 if (IC->isEquality()) 4977 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 4978 if (C->isNullValue()) 4979 continue; 4980 // Unknown instruction. 4981 return false; 4982 } 4983 return true; 4984} 4985 4986static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 4987 const Type *LoadTy, 4988 SelectionDAGBuilder &Builder) { 4989 4990 // Check to see if this load can be trivially constant folded, e.g. if the 4991 // input is from a string literal. 4992 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 4993 // Cast pointer to the type we really want to load. 4994 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 4995 PointerType::getUnqual(LoadTy)); 4996 4997 if (const Constant *LoadCst = 4998 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 4999 Builder.TD)) 5000 return Builder.getValue(LoadCst); 5001 } 5002 5003 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5004 // still constant memory, the input chain can be the entry node. 5005 SDValue Root; 5006 bool ConstantMemory = false; 5007 5008 // Do not serialize (non-volatile) loads of constant memory with anything. 5009 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5010 Root = Builder.DAG.getEntryNode(); 5011 ConstantMemory = true; 5012 } else { 5013 // Do not serialize non-volatile loads against each other. 5014 Root = Builder.DAG.getRoot(); 5015 } 5016 5017 SDValue Ptr = Builder.getValue(PtrVal); 5018 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5019 Ptr, MachinePointerInfo(PtrVal), 5020 false /*volatile*/, 5021 false /*nontemporal*/, 1 /* align=1 */); 5022 5023 if (!ConstantMemory) 5024 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5025 return LoadVal; 5026} 5027 5028 5029/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5030/// If so, return true and lower it, otherwise return false and it will be 5031/// lowered like a normal call. 5032bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5033 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5034 if (I.getNumArgOperands() != 3) 5035 return false; 5036 5037 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5038 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5039 !I.getArgOperand(2)->getType()->isIntegerTy() || 5040 !I.getType()->isIntegerTy()) 5041 return false; 5042 5043 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5044 5045 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5046 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5047 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5048 bool ActuallyDoIt = true; 5049 MVT LoadVT; 5050 const Type *LoadTy; 5051 switch (Size->getZExtValue()) { 5052 default: 5053 LoadVT = MVT::Other; 5054 LoadTy = 0; 5055 ActuallyDoIt = false; 5056 break; 5057 case 2: 5058 LoadVT = MVT::i16; 5059 LoadTy = Type::getInt16Ty(Size->getContext()); 5060 break; 5061 case 4: 5062 LoadVT = MVT::i32; 5063 LoadTy = Type::getInt32Ty(Size->getContext()); 5064 break; 5065 case 8: 5066 LoadVT = MVT::i64; 5067 LoadTy = Type::getInt64Ty(Size->getContext()); 5068 break; 5069 /* 5070 case 16: 5071 LoadVT = MVT::v4i32; 5072 LoadTy = Type::getInt32Ty(Size->getContext()); 5073 LoadTy = VectorType::get(LoadTy, 4); 5074 break; 5075 */ 5076 } 5077 5078 // This turns into unaligned loads. We only do this if the target natively 5079 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5080 // we'll only produce a small number of byte loads. 5081 5082 // Require that we can find a legal MVT, and only do this if the target 5083 // supports unaligned loads of that type. Expanding into byte loads would 5084 // bloat the code. 5085 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5086 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5087 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5088 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5089 ActuallyDoIt = false; 5090 } 5091 5092 if (ActuallyDoIt) { 5093 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5094 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5095 5096 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5097 ISD::SETNE); 5098 EVT CallVT = TLI.getValueType(I.getType(), true); 5099 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5100 return true; 5101 } 5102 } 5103 5104 5105 return false; 5106} 5107 5108 5109void SelectionDAGBuilder::visitCall(const CallInst &I) { 5110 // Handle inline assembly differently. 5111 if (isa<InlineAsm>(I.getCalledValue())) { 5112 visitInlineAsm(&I); 5113 return; 5114 } 5115 5116 // See if any floating point values are being passed to this function. This is 5117 // used to emit an undefined reference to fltused on Windows. 5118 const FunctionType *FT = 5119 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5120 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5121 if (FT->isVarArg() && 5122 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5123 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5124 const Type* T = I.getArgOperand(i)->getType(); 5125 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T); 5126 i != e; ++i) { 5127 if (!i->isFloatingPointTy()) continue; 5128 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5129 break; 5130 } 5131 } 5132 } 5133 5134 const char *RenameFn = 0; 5135 if (Function *F = I.getCalledFunction()) { 5136 if (F->isDeclaration()) { 5137 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5138 if (unsigned IID = II->getIntrinsicID(F)) { 5139 RenameFn = visitIntrinsicCall(I, IID); 5140 if (!RenameFn) 5141 return; 5142 } 5143 } 5144 if (unsigned IID = F->getIntrinsicID()) { 5145 RenameFn = visitIntrinsicCall(I, IID); 5146 if (!RenameFn) 5147 return; 5148 } 5149 } 5150 5151 // Check for well-known libc/libm calls. If the function is internal, it 5152 // can't be a library call. 5153 if (!F->hasLocalLinkage() && F->hasName()) { 5154 StringRef Name = F->getName(); 5155 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5156 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5157 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5158 I.getType() == I.getArgOperand(0)->getType() && 5159 I.getType() == I.getArgOperand(1)->getType()) { 5160 SDValue LHS = getValue(I.getArgOperand(0)); 5161 SDValue RHS = getValue(I.getArgOperand(1)); 5162 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5163 LHS.getValueType(), LHS, RHS)); 5164 return; 5165 } 5166 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5167 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5168 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5169 I.getType() == I.getArgOperand(0)->getType()) { 5170 SDValue Tmp = getValue(I.getArgOperand(0)); 5171 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5172 Tmp.getValueType(), Tmp)); 5173 return; 5174 } 5175 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5176 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5177 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5178 I.getType() == I.getArgOperand(0)->getType() && 5179 I.onlyReadsMemory()) { 5180 SDValue Tmp = getValue(I.getArgOperand(0)); 5181 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5182 Tmp.getValueType(), Tmp)); 5183 return; 5184 } 5185 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5186 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5187 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5188 I.getType() == I.getArgOperand(0)->getType() && 5189 I.onlyReadsMemory()) { 5190 SDValue Tmp = getValue(I.getArgOperand(0)); 5191 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5192 Tmp.getValueType(), Tmp)); 5193 return; 5194 } 5195 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5196 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5197 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5198 I.getType() == I.getArgOperand(0)->getType() && 5199 I.onlyReadsMemory()) { 5200 SDValue Tmp = getValue(I.getArgOperand(0)); 5201 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5202 Tmp.getValueType(), Tmp)); 5203 return; 5204 } 5205 } else if (Name == "memcmp") { 5206 if (visitMemCmpCall(I)) 5207 return; 5208 } 5209 } 5210 } 5211 5212 SDValue Callee; 5213 if (!RenameFn) 5214 Callee = getValue(I.getCalledValue()); 5215 else 5216 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5217 5218 // Check if we can potentially perform a tail call. More detailed checking is 5219 // be done within LowerCallTo, after more information about the call is known. 5220 LowerCallTo(&I, Callee, I.isTailCall()); 5221} 5222 5223namespace { 5224 5225/// AsmOperandInfo - This contains information for each constraint that we are 5226/// lowering. 5227class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5228public: 5229 /// CallOperand - If this is the result output operand or a clobber 5230 /// this is null, otherwise it is the incoming operand to the CallInst. 5231 /// This gets modified as the asm is processed. 5232 SDValue CallOperand; 5233 5234 /// AssignedRegs - If this is a register or register class operand, this 5235 /// contains the set of register corresponding to the operand. 5236 RegsForValue AssignedRegs; 5237 5238 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5239 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5240 } 5241 5242 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5243 /// busy in OutputRegs/InputRegs. 5244 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5245 std::set<unsigned> &OutputRegs, 5246 std::set<unsigned> &InputRegs, 5247 const TargetRegisterInfo &TRI) const { 5248 if (isOutReg) { 5249 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5250 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5251 } 5252 if (isInReg) { 5253 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5254 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5255 } 5256 } 5257 5258 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5259 /// corresponds to. If there is no Value* for this operand, it returns 5260 /// MVT::Other. 5261 EVT getCallOperandValEVT(LLVMContext &Context, 5262 const TargetLowering &TLI, 5263 const TargetData *TD) const { 5264 if (CallOperandVal == 0) return MVT::Other; 5265 5266 if (isa<BasicBlock>(CallOperandVal)) 5267 return TLI.getPointerTy(); 5268 5269 const llvm::Type *OpTy = CallOperandVal->getType(); 5270 5271 // If this is an indirect operand, the operand is a pointer to the 5272 // accessed type. 5273 if (isIndirect) { 5274 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5275 if (!PtrTy) 5276 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5277 OpTy = PtrTy->getElementType(); 5278 } 5279 5280 // If OpTy is not a single value, it may be a struct/union that we 5281 // can tile with integers. 5282 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5283 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5284 switch (BitSize) { 5285 default: break; 5286 case 1: 5287 case 8: 5288 case 16: 5289 case 32: 5290 case 64: 5291 case 128: 5292 OpTy = IntegerType::get(Context, BitSize); 5293 break; 5294 } 5295 } 5296 5297 return TLI.getValueType(OpTy, true); 5298 } 5299 5300private: 5301 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5302 /// specified set. 5303 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5304 const TargetRegisterInfo &TRI) { 5305 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5306 Regs.insert(Reg); 5307 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5308 for (; *Aliases; ++Aliases) 5309 Regs.insert(*Aliases); 5310 } 5311}; 5312 5313typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5314 5315} // end anonymous namespace 5316 5317/// isAllocatableRegister - If the specified register is safe to allocate, 5318/// i.e. it isn't a stack pointer or some other special register, return the 5319/// register class for the register. Otherwise, return null. 5320static const TargetRegisterClass * 5321isAllocatableRegister(unsigned Reg, MachineFunction &MF, 5322 const TargetLowering &TLI, 5323 const TargetRegisterInfo *TRI) { 5324 EVT FoundVT = MVT::Other; 5325 const TargetRegisterClass *FoundRC = 0; 5326 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 5327 E = TRI->regclass_end(); RCI != E; ++RCI) { 5328 EVT ThisVT = MVT::Other; 5329 5330 const TargetRegisterClass *RC = *RCI; 5331 // If none of the value types for this register class are valid, we 5332 // can't use it. For example, 64-bit reg classes on 32-bit targets. 5333 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 5334 I != E; ++I) { 5335 if (TLI.isTypeLegal(*I)) { 5336 // If we have already found this register in a different register class, 5337 // choose the one with the largest VT specified. For example, on 5338 // PowerPC, we favor f64 register classes over f32. 5339 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 5340 ThisVT = *I; 5341 break; 5342 } 5343 } 5344 } 5345 5346 if (ThisVT == MVT::Other) continue; 5347 5348 // NOTE: This isn't ideal. In particular, this might allocate the 5349 // frame pointer in functions that need it (due to them not being taken 5350 // out of allocation, because a variable sized allocation hasn't been seen 5351 // yet). This is a slight code pessimization, but should still work. 5352 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 5353 E = RC->allocation_order_end(MF); I != E; ++I) 5354 if (*I == Reg) { 5355 // We found a matching register class. Keep looking at others in case 5356 // we find one with larger registers that this physreg is also in. 5357 FoundRC = RC; 5358 FoundVT = ThisVT; 5359 break; 5360 } 5361 } 5362 return FoundRC; 5363} 5364 5365/// GetRegistersForValue - Assign registers (virtual or physical) for the 5366/// specified operand. We prefer to assign virtual registers, to allow the 5367/// register allocator to handle the assignment process. However, if the asm 5368/// uses features that we can't model on machineinstrs, we have SDISel do the 5369/// allocation. This produces generally horrible, but correct, code. 5370/// 5371/// OpInfo describes the operand. 5372/// Input and OutputRegs are the set of already allocated physical registers. 5373/// 5374static void GetRegistersForValue(SelectionDAG &DAG, 5375 const TargetLowering &TLI, 5376 DebugLoc DL, 5377 SDISelAsmOperandInfo &OpInfo, 5378 std::set<unsigned> &OutputRegs, 5379 std::set<unsigned> &InputRegs) { 5380 LLVMContext &Context = *DAG.getContext(); 5381 5382 // Compute whether this value requires an input register, an output register, 5383 // or both. 5384 bool isOutReg = false; 5385 bool isInReg = false; 5386 switch (OpInfo.Type) { 5387 case InlineAsm::isOutput: 5388 isOutReg = true; 5389 5390 // If there is an input constraint that matches this, we need to reserve 5391 // the input register so no other inputs allocate to it. 5392 isInReg = OpInfo.hasMatchingInput(); 5393 break; 5394 case InlineAsm::isInput: 5395 isInReg = true; 5396 isOutReg = false; 5397 break; 5398 case InlineAsm::isClobber: 5399 isOutReg = true; 5400 isInReg = true; 5401 break; 5402 } 5403 5404 5405 MachineFunction &MF = DAG.getMachineFunction(); 5406 SmallVector<unsigned, 4> Regs; 5407 5408 // If this is a constraint for a single physreg, or a constraint for a 5409 // register class, find it. 5410 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5411 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5412 OpInfo.ConstraintVT); 5413 5414 unsigned NumRegs = 1; 5415 if (OpInfo.ConstraintVT != MVT::Other) { 5416 // If this is a FP input in an integer register (or visa versa) insert a bit 5417 // cast of the input value. More generally, handle any case where the input 5418 // value disagrees with the register class we plan to stick this in. 5419 if (OpInfo.Type == InlineAsm::isInput && 5420 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5421 // Try to convert to the first EVT that the reg class contains. If the 5422 // types are identical size, use a bitcast to convert (e.g. two differing 5423 // vector types). 5424 EVT RegVT = *PhysReg.second->vt_begin(); 5425 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5426 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5427 RegVT, OpInfo.CallOperand); 5428 OpInfo.ConstraintVT = RegVT; 5429 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5430 // If the input is a FP value and we want it in FP registers, do a 5431 // bitcast to the corresponding integer type. This turns an f64 value 5432 // into i64, which can be passed with two i32 values on a 32-bit 5433 // machine. 5434 RegVT = EVT::getIntegerVT(Context, 5435 OpInfo.ConstraintVT.getSizeInBits()); 5436 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5437 RegVT, OpInfo.CallOperand); 5438 OpInfo.ConstraintVT = RegVT; 5439 } 5440 } 5441 5442 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5443 } 5444 5445 EVT RegVT; 5446 EVT ValueVT = OpInfo.ConstraintVT; 5447 5448 // If this is a constraint for a specific physical register, like {r17}, 5449 // assign it now. 5450 if (unsigned AssignedReg = PhysReg.first) { 5451 const TargetRegisterClass *RC = PhysReg.second; 5452 if (OpInfo.ConstraintVT == MVT::Other) 5453 ValueVT = *RC->vt_begin(); 5454 5455 // Get the actual register value type. This is important, because the user 5456 // may have asked for (e.g.) the AX register in i32 type. We need to 5457 // remember that AX is actually i16 to get the right extension. 5458 RegVT = *RC->vt_begin(); 5459 5460 // This is a explicit reference to a physical register. 5461 Regs.push_back(AssignedReg); 5462 5463 // If this is an expanded reference, add the rest of the regs to Regs. 5464 if (NumRegs != 1) { 5465 TargetRegisterClass::iterator I = RC->begin(); 5466 for (; *I != AssignedReg; ++I) 5467 assert(I != RC->end() && "Didn't find reg!"); 5468 5469 // Already added the first reg. 5470 --NumRegs; ++I; 5471 for (; NumRegs; --NumRegs, ++I) { 5472 assert(I != RC->end() && "Ran out of registers to allocate!"); 5473 Regs.push_back(*I); 5474 } 5475 } 5476 5477 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5478 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5479 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5480 return; 5481 } 5482 5483 // Otherwise, if this was a reference to an LLVM register class, create vregs 5484 // for this reference. 5485 if (const TargetRegisterClass *RC = PhysReg.second) { 5486 RegVT = *RC->vt_begin(); 5487 if (OpInfo.ConstraintVT == MVT::Other) 5488 ValueVT = RegVT; 5489 5490 // Create the appropriate number of virtual registers. 5491 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5492 for (; NumRegs; --NumRegs) 5493 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5494 5495 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5496 return; 5497 } 5498 5499 // This is a reference to a register class that doesn't directly correspond 5500 // to an LLVM register class. Allocate NumRegs consecutive, available, 5501 // registers from the class. 5502 std::vector<unsigned> RegClassRegs 5503 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 5504 OpInfo.ConstraintVT); 5505 5506 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5507 unsigned NumAllocated = 0; 5508 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 5509 unsigned Reg = RegClassRegs[i]; 5510 // See if this register is available. 5511 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 5512 (isInReg && InputRegs.count(Reg))) { // Already used. 5513 // Make sure we find consecutive registers. 5514 NumAllocated = 0; 5515 continue; 5516 } 5517 5518 // Check to see if this register is allocatable (i.e. don't give out the 5519 // stack pointer). 5520 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); 5521 if (!RC) { // Couldn't allocate this register. 5522 // Reset NumAllocated to make sure we return consecutive registers. 5523 NumAllocated = 0; 5524 continue; 5525 } 5526 5527 // Okay, this register is good, we can use it. 5528 ++NumAllocated; 5529 5530 // If we allocated enough consecutive registers, succeed. 5531 if (NumAllocated == NumRegs) { 5532 unsigned RegStart = (i-NumAllocated)+1; 5533 unsigned RegEnd = i+1; 5534 // Mark all of the allocated registers used. 5535 for (unsigned i = RegStart; i != RegEnd; ++i) 5536 Regs.push_back(RegClassRegs[i]); 5537 5538 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 5539 OpInfo.ConstraintVT); 5540 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5541 return; 5542 } 5543 } 5544 5545 // Otherwise, we couldn't allocate enough registers for this. 5546} 5547 5548/// visitInlineAsm - Handle a call to an InlineAsm object. 5549/// 5550void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5551 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5552 5553 /// ConstraintOperands - Information about all of the constraints. 5554 SDISelAsmOperandInfoVector ConstraintOperands; 5555 5556 std::set<unsigned> OutputRegs, InputRegs; 5557 5558 TargetLowering::AsmOperandInfoVector 5559 TargetConstraints = TLI.ParseConstraints(CS); 5560 5561 bool hasMemory = false; 5562 5563 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5564 unsigned ResNo = 0; // ResNo - The result number of the next output. 5565 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5566 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5567 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5568 5569 EVT OpVT = MVT::Other; 5570 5571 // Compute the value type for each operand. 5572 switch (OpInfo.Type) { 5573 case InlineAsm::isOutput: 5574 // Indirect outputs just consume an argument. 5575 if (OpInfo.isIndirect) { 5576 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5577 break; 5578 } 5579 5580 // The return value of the call is this value. As such, there is no 5581 // corresponding argument. 5582 assert(!CS.getType()->isVoidTy() && 5583 "Bad inline asm!"); 5584 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5585 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5586 } else { 5587 assert(ResNo == 0 && "Asm only has one result!"); 5588 OpVT = TLI.getValueType(CS.getType()); 5589 } 5590 ++ResNo; 5591 break; 5592 case InlineAsm::isInput: 5593 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5594 break; 5595 case InlineAsm::isClobber: 5596 // Nothing to do. 5597 break; 5598 } 5599 5600 // If this is an input or an indirect output, process the call argument. 5601 // BasicBlocks are labels, currently appearing only in asm's. 5602 if (OpInfo.CallOperandVal) { 5603 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5604 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5605 } else { 5606 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5607 } 5608 5609 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5610 } 5611 5612 OpInfo.ConstraintVT = OpVT; 5613 5614 // Indirect operand accesses access memory. 5615 if (OpInfo.isIndirect) 5616 hasMemory = true; 5617 else { 5618 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5619 TargetLowering::ConstraintType 5620 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5621 if (CType == TargetLowering::C_Memory) { 5622 hasMemory = true; 5623 break; 5624 } 5625 } 5626 } 5627 } 5628 5629 SDValue Chain, Flag; 5630 5631 // We won't need to flush pending loads if this asm doesn't touch 5632 // memory and is nonvolatile. 5633 if (hasMemory || IA->hasSideEffects()) 5634 Chain = getRoot(); 5635 else 5636 Chain = DAG.getRoot(); 5637 5638 // Second pass over the constraints: compute which constraint option to use 5639 // and assign registers to constraints that want a specific physreg. 5640 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5641 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5642 5643 // If this is an output operand with a matching input operand, look up the 5644 // matching input. If their types mismatch, e.g. one is an integer, the 5645 // other is floating point, or their sizes are different, flag it as an 5646 // error. 5647 if (OpInfo.hasMatchingInput()) { 5648 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5649 5650 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5651 if ((OpInfo.ConstraintVT.isInteger() != 5652 Input.ConstraintVT.isInteger()) || 5653 (OpInfo.ConstraintVT.getSizeInBits() != 5654 Input.ConstraintVT.getSizeInBits())) { 5655 report_fatal_error("Unsupported asm: input constraint" 5656 " with a matching output constraint of" 5657 " incompatible type!"); 5658 } 5659 Input.ConstraintVT = OpInfo.ConstraintVT; 5660 } 5661 } 5662 5663 // Compute the constraint code and ConstraintType to use. 5664 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5665 5666 // If this is a memory input, and if the operand is not indirect, do what we 5667 // need to to provide an address for the memory input. 5668 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5669 !OpInfo.isIndirect) { 5670 assert((OpInfo.isMultipleAlternative || 5671 (OpInfo.Type == InlineAsm::isInput)) && 5672 "Can only indirectify direct input operands!"); 5673 5674 // Memory operands really want the address of the value. If we don't have 5675 // an indirect input, put it in the constpool if we can, otherwise spill 5676 // it to a stack slot. 5677 5678 // If the operand is a float, integer, or vector constant, spill to a 5679 // constant pool entry to get its address. 5680 const Value *OpVal = OpInfo.CallOperandVal; 5681 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5682 isa<ConstantVector>(OpVal)) { 5683 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5684 TLI.getPointerTy()); 5685 } else { 5686 // Otherwise, create a stack slot and emit a store to it before the 5687 // asm. 5688 const Type *Ty = OpVal->getType(); 5689 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5690 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5691 MachineFunction &MF = DAG.getMachineFunction(); 5692 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5693 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5694 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5695 OpInfo.CallOperand, StackSlot, 5696 MachinePointerInfo::getFixedStack(SSFI), 5697 false, false, 0); 5698 OpInfo.CallOperand = StackSlot; 5699 } 5700 5701 // There is no longer a Value* corresponding to this operand. 5702 OpInfo.CallOperandVal = 0; 5703 5704 // It is now an indirect operand. 5705 OpInfo.isIndirect = true; 5706 } 5707 5708 // If this constraint is for a specific register, allocate it before 5709 // anything else. 5710 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5711 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5712 InputRegs); 5713 } 5714 5715 // Second pass - Loop over all of the operands, assigning virtual or physregs 5716 // to register class operands. 5717 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5718 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5719 5720 // C_Register operands have already been allocated, Other/Memory don't need 5721 // to be. 5722 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5723 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5724 InputRegs); 5725 } 5726 5727 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5728 std::vector<SDValue> AsmNodeOperands; 5729 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5730 AsmNodeOperands.push_back( 5731 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5732 TLI.getPointerTy())); 5733 5734 // If we have a !srcloc metadata node associated with it, we want to attach 5735 // this to the ultimately generated inline asm machineinstr. To do this, we 5736 // pass in the third operand as this (potentially null) inline asm MDNode. 5737 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5738 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5739 5740 // Remember the HasSideEffect and AlignStack bits as operand 3. 5741 unsigned ExtraInfo = 0; 5742 if (IA->hasSideEffects()) 5743 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 5744 if (IA->isAlignStack()) 5745 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 5746 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 5747 TLI.getPointerTy())); 5748 5749 // Loop over all of the inputs, copying the operand values into the 5750 // appropriate registers and processing the output regs. 5751 RegsForValue RetValRegs; 5752 5753 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5754 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5755 5756 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5757 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5758 5759 switch (OpInfo.Type) { 5760 case InlineAsm::isOutput: { 5761 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5762 OpInfo.ConstraintType != TargetLowering::C_Register) { 5763 // Memory output, or 'other' output (e.g. 'X' constraint). 5764 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5765 5766 // Add information to the INLINEASM node to know about this output. 5767 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5768 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5769 TLI.getPointerTy())); 5770 AsmNodeOperands.push_back(OpInfo.CallOperand); 5771 break; 5772 } 5773 5774 // Otherwise, this is a register or register class output. 5775 5776 // Copy the output from the appropriate register. Find a register that 5777 // we can use. 5778 if (OpInfo.AssignedRegs.Regs.empty()) 5779 report_fatal_error("Couldn't allocate output reg for constraint '" + 5780 Twine(OpInfo.ConstraintCode) + "'!"); 5781 5782 // If this is an indirect operand, store through the pointer after the 5783 // asm. 5784 if (OpInfo.isIndirect) { 5785 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5786 OpInfo.CallOperandVal)); 5787 } else { 5788 // This is the result value of the call. 5789 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5790 // Concatenate this output onto the outputs list. 5791 RetValRegs.append(OpInfo.AssignedRegs); 5792 } 5793 5794 // Add information to the INLINEASM node to know that this register is 5795 // set. 5796 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5797 InlineAsm::Kind_RegDefEarlyClobber : 5798 InlineAsm::Kind_RegDef, 5799 false, 5800 0, 5801 DAG, 5802 AsmNodeOperands); 5803 break; 5804 } 5805 case InlineAsm::isInput: { 5806 SDValue InOperandVal = OpInfo.CallOperand; 5807 5808 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5809 // If this is required to match an output register we have already set, 5810 // just use its register. 5811 unsigned OperandNo = OpInfo.getMatchedOperand(); 5812 5813 // Scan until we find the definition we already emitted of this operand. 5814 // When we find it, create a RegsForValue operand. 5815 unsigned CurOp = InlineAsm::Op_FirstOperand; 5816 for (; OperandNo; --OperandNo) { 5817 // Advance to the next operand. 5818 unsigned OpFlag = 5819 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5820 assert((InlineAsm::isRegDefKind(OpFlag) || 5821 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5822 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5823 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5824 } 5825 5826 unsigned OpFlag = 5827 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5828 if (InlineAsm::isRegDefKind(OpFlag) || 5829 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5830 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5831 if (OpInfo.isIndirect) { 5832 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5833 LLVMContext &Ctx = *DAG.getContext(); 5834 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5835 " don't know how to handle tied " 5836 "indirect register inputs"); 5837 } 5838 5839 RegsForValue MatchedRegs; 5840 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5841 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5842 MatchedRegs.RegVTs.push_back(RegVT); 5843 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5844 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5845 i != e; ++i) 5846 MatchedRegs.Regs.push_back 5847 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5848 5849 // Use the produced MatchedRegs object to 5850 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5851 Chain, &Flag); 5852 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 5853 true, OpInfo.getMatchedOperand(), 5854 DAG, AsmNodeOperands); 5855 break; 5856 } 5857 5858 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 5859 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 5860 "Unexpected number of operands"); 5861 // Add information to the INLINEASM node to know about this input. 5862 // See InlineAsm.h isUseOperandTiedToDef. 5863 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 5864 OpInfo.getMatchedOperand()); 5865 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5866 TLI.getPointerTy())); 5867 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5868 break; 5869 } 5870 5871 // Treat indirect 'X' constraint as memory. 5872 if (OpInfo.ConstraintType == TargetLowering::C_Other && 5873 OpInfo.isIndirect) 5874 OpInfo.ConstraintType = TargetLowering::C_Memory; 5875 5876 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5877 std::vector<SDValue> Ops; 5878 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 5879 Ops, DAG); 5880 if (Ops.empty()) 5881 report_fatal_error("Invalid operand for inline asm constraint '" + 5882 Twine(OpInfo.ConstraintCode) + "'!"); 5883 5884 // Add information to the INLINEASM node to know about this input. 5885 unsigned ResOpType = 5886 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 5887 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5888 TLI.getPointerTy())); 5889 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5890 break; 5891 } 5892 5893 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5894 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5895 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5896 "Memory operands expect pointer values"); 5897 5898 // Add information to the INLINEASM node to know about this input. 5899 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5900 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5901 TLI.getPointerTy())); 5902 AsmNodeOperands.push_back(InOperandVal); 5903 break; 5904 } 5905 5906 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5907 OpInfo.ConstraintType == TargetLowering::C_Register) && 5908 "Unknown constraint type!"); 5909 assert(!OpInfo.isIndirect && 5910 "Don't know how to handle indirect register inputs yet!"); 5911 5912 // Copy the input into the appropriate registers. 5913 if (OpInfo.AssignedRegs.Regs.empty() || 5914 !OpInfo.AssignedRegs.areValueTypesLegal(TLI)) 5915 report_fatal_error("Couldn't allocate input reg for constraint '" + 5916 Twine(OpInfo.ConstraintCode) + "'!"); 5917 5918 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5919 Chain, &Flag); 5920 5921 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 5922 DAG, AsmNodeOperands); 5923 break; 5924 } 5925 case InlineAsm::isClobber: { 5926 // Add the clobbered value to the operand list, so that the register 5927 // allocator is aware that the physreg got clobbered. 5928 if (!OpInfo.AssignedRegs.Regs.empty()) 5929 OpInfo.AssignedRegs.AddInlineAsmOperands( 5930 InlineAsm::Kind_RegDefEarlyClobber, 5931 false, 0, DAG, 5932 AsmNodeOperands); 5933 break; 5934 } 5935 } 5936 } 5937 5938 // Finish up input operands. Set the input chain and add the flag last. 5939 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 5940 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5941 5942 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5943 DAG.getVTList(MVT::Other, MVT::Glue), 5944 &AsmNodeOperands[0], AsmNodeOperands.size()); 5945 Flag = Chain.getValue(1); 5946 5947 // If this asm returns a register value, copy the result from that register 5948 // and set it as the value of the call. 5949 if (!RetValRegs.Regs.empty()) { 5950 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5951 Chain, &Flag); 5952 5953 // FIXME: Why don't we do this for inline asms with MRVs? 5954 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5955 EVT ResultType = TLI.getValueType(CS.getType()); 5956 5957 // If any of the results of the inline asm is a vector, it may have the 5958 // wrong width/num elts. This can happen for register classes that can 5959 // contain multiple different value types. The preg or vreg allocated may 5960 // not have the same VT as was expected. Convert it to the right type 5961 // with bit_convert. 5962 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5963 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 5964 ResultType, Val); 5965 5966 } else if (ResultType != Val.getValueType() && 5967 ResultType.isInteger() && Val.getValueType().isInteger()) { 5968 // If a result value was tied to an input value, the computed result may 5969 // have a wider width than the expected result. Extract the relevant 5970 // portion. 5971 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 5972 } 5973 5974 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 5975 } 5976 5977 setValue(CS.getInstruction(), Val); 5978 // Don't need to use this as a chain in this case. 5979 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 5980 return; 5981 } 5982 5983 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 5984 5985 // Process indirect outputs, first output all of the flagged copies out of 5986 // physregs. 5987 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 5988 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 5989 const Value *Ptr = IndirectStoresToEmit[i].second; 5990 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5991 Chain, &Flag); 5992 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 5993 } 5994 5995 // Emit the non-flagged stores from the physregs. 5996 SmallVector<SDValue, 8> OutChains; 5997 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 5998 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 5999 StoresToEmit[i].first, 6000 getValue(StoresToEmit[i].second), 6001 MachinePointerInfo(StoresToEmit[i].second), 6002 false, false, 0); 6003 OutChains.push_back(Val); 6004 } 6005 6006 if (!OutChains.empty()) 6007 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6008 &OutChains[0], OutChains.size()); 6009 6010 DAG.setRoot(Chain); 6011} 6012 6013void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6014 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6015 MVT::Other, getRoot(), 6016 getValue(I.getArgOperand(0)), 6017 DAG.getSrcValue(I.getArgOperand(0)))); 6018} 6019 6020void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6021 const TargetData &TD = *TLI.getTargetData(); 6022 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6023 getRoot(), getValue(I.getOperand(0)), 6024 DAG.getSrcValue(I.getOperand(0)), 6025 TD.getABITypeAlignment(I.getType())); 6026 setValue(&I, V); 6027 DAG.setRoot(V.getValue(1)); 6028} 6029 6030void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6031 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6032 MVT::Other, getRoot(), 6033 getValue(I.getArgOperand(0)), 6034 DAG.getSrcValue(I.getArgOperand(0)))); 6035} 6036 6037void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6038 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6039 MVT::Other, getRoot(), 6040 getValue(I.getArgOperand(0)), 6041 getValue(I.getArgOperand(1)), 6042 DAG.getSrcValue(I.getArgOperand(0)), 6043 DAG.getSrcValue(I.getArgOperand(1)))); 6044} 6045 6046/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6047/// implementation, which just calls LowerCall. 6048/// FIXME: When all targets are 6049/// migrated to using LowerCall, this hook should be integrated into SDISel. 6050std::pair<SDValue, SDValue> 6051TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 6052 bool RetSExt, bool RetZExt, bool isVarArg, 6053 bool isInreg, unsigned NumFixedArgs, 6054 CallingConv::ID CallConv, bool isTailCall, 6055 bool isReturnValueUsed, 6056 SDValue Callee, 6057 ArgListTy &Args, SelectionDAG &DAG, 6058 DebugLoc dl) const { 6059 // Handle all of the outgoing arguments. 6060 SmallVector<ISD::OutputArg, 32> Outs; 6061 SmallVector<SDValue, 32> OutVals; 6062 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6063 SmallVector<EVT, 4> ValueVTs; 6064 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6065 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6066 Value != NumValues; ++Value) { 6067 EVT VT = ValueVTs[Value]; 6068 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6069 SDValue Op = SDValue(Args[i].Node.getNode(), 6070 Args[i].Node.getResNo() + Value); 6071 ISD::ArgFlagsTy Flags; 6072 unsigned OriginalAlignment = 6073 getTargetData()->getABITypeAlignment(ArgTy); 6074 6075 if (Args[i].isZExt) 6076 Flags.setZExt(); 6077 if (Args[i].isSExt) 6078 Flags.setSExt(); 6079 if (Args[i].isInReg) 6080 Flags.setInReg(); 6081 if (Args[i].isSRet) 6082 Flags.setSRet(); 6083 if (Args[i].isByVal) { 6084 Flags.setByVal(); 6085 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 6086 const Type *ElementTy = Ty->getElementType(); 6087 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 6088 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy); 6089 // For ByVal, alignment should come from FE. BE will guess if this 6090 // info is not there but there are cases it cannot get right. 6091 if (Args[i].Alignment) 6092 FrameAlign = Args[i].Alignment; 6093 Flags.setByValAlign(FrameAlign); 6094 Flags.setByValSize(FrameSize); 6095 } 6096 if (Args[i].isNest) 6097 Flags.setNest(); 6098 Flags.setOrigAlign(OriginalAlignment); 6099 6100 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6101 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6102 SmallVector<SDValue, 4> Parts(NumParts); 6103 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6104 6105 if (Args[i].isSExt) 6106 ExtendKind = ISD::SIGN_EXTEND; 6107 else if (Args[i].isZExt) 6108 ExtendKind = ISD::ZERO_EXTEND; 6109 6110 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6111 PartVT, ExtendKind); 6112 6113 for (unsigned j = 0; j != NumParts; ++j) { 6114 // if it isn't first piece, alignment must be 1 6115 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6116 i < NumFixedArgs); 6117 if (NumParts > 1 && j == 0) 6118 MyFlags.Flags.setSplit(); 6119 else if (j != 0) 6120 MyFlags.Flags.setOrigAlign(1); 6121 6122 Outs.push_back(MyFlags); 6123 OutVals.push_back(Parts[j]); 6124 } 6125 } 6126 } 6127 6128 // Handle the incoming return values from the call. 6129 SmallVector<ISD::InputArg, 32> Ins; 6130 SmallVector<EVT, 4> RetTys; 6131 ComputeValueVTs(*this, RetTy, RetTys); 6132 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6133 EVT VT = RetTys[I]; 6134 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6135 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6136 for (unsigned i = 0; i != NumRegs; ++i) { 6137 ISD::InputArg MyFlags; 6138 MyFlags.VT = RegisterVT.getSimpleVT(); 6139 MyFlags.Used = isReturnValueUsed; 6140 if (RetSExt) 6141 MyFlags.Flags.setSExt(); 6142 if (RetZExt) 6143 MyFlags.Flags.setZExt(); 6144 if (isInreg) 6145 MyFlags.Flags.setInReg(); 6146 Ins.push_back(MyFlags); 6147 } 6148 } 6149 6150 SmallVector<SDValue, 4> InVals; 6151 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6152 Outs, OutVals, Ins, dl, DAG, InVals); 6153 6154 // Verify that the target's LowerCall behaved as expected. 6155 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6156 "LowerCall didn't return a valid chain!"); 6157 assert((!isTailCall || InVals.empty()) && 6158 "LowerCall emitted a return value for a tail call!"); 6159 assert((isTailCall || InVals.size() == Ins.size()) && 6160 "LowerCall didn't emit the correct number of values!"); 6161 6162 // For a tail call, the return value is merely live-out and there aren't 6163 // any nodes in the DAG representing it. Return a special value to 6164 // indicate that a tail call has been emitted and no more Instructions 6165 // should be processed in the current block. 6166 if (isTailCall) { 6167 DAG.setRoot(Chain); 6168 return std::make_pair(SDValue(), SDValue()); 6169 } 6170 6171 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6172 assert(InVals[i].getNode() && 6173 "LowerCall emitted a null value!"); 6174 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6175 "LowerCall emitted a value with the wrong type!"); 6176 }); 6177 6178 // Collect the legal value parts into potentially illegal values 6179 // that correspond to the original function's return values. 6180 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6181 if (RetSExt) 6182 AssertOp = ISD::AssertSext; 6183 else if (RetZExt) 6184 AssertOp = ISD::AssertZext; 6185 SmallVector<SDValue, 4> ReturnValues; 6186 unsigned CurReg = 0; 6187 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6188 EVT VT = RetTys[I]; 6189 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6190 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6191 6192 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6193 NumRegs, RegisterVT, VT, 6194 AssertOp)); 6195 CurReg += NumRegs; 6196 } 6197 6198 // For a function returning void, there is no return value. We can't create 6199 // such a node, so we just return a null return value in that case. In 6200 // that case, nothing will actually look at the value. 6201 if (ReturnValues.empty()) 6202 return std::make_pair(SDValue(), Chain); 6203 6204 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6205 DAG.getVTList(&RetTys[0], RetTys.size()), 6206 &ReturnValues[0], ReturnValues.size()); 6207 return std::make_pair(Res, Chain); 6208} 6209 6210void TargetLowering::LowerOperationWrapper(SDNode *N, 6211 SmallVectorImpl<SDValue> &Results, 6212 SelectionDAG &DAG) const { 6213 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6214 if (Res.getNode()) 6215 Results.push_back(Res); 6216} 6217 6218SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6219 llvm_unreachable("LowerOperation not implemented for this target!"); 6220 return SDValue(); 6221} 6222 6223void 6224SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6225 SDValue Op = getNonRegisterValue(V); 6226 assert((Op.getOpcode() != ISD::CopyFromReg || 6227 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6228 "Copy from a reg to the same reg!"); 6229 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6230 6231 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6232 SDValue Chain = DAG.getEntryNode(); 6233 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6234 PendingExports.push_back(Chain); 6235} 6236 6237#include "llvm/CodeGen/SelectionDAGISel.h" 6238 6239/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6240/// entry block, return true. This includes arguments used by switches, since 6241/// the switch may expand into multiple basic blocks. 6242static bool isOnlyUsedInEntryBlock(const Argument *A) { 6243 // With FastISel active, we may be splitting blocks, so force creation 6244 // of virtual registers for all non-dead arguments. 6245 if (EnableFastISel) 6246 return A->use_empty(); 6247 6248 const BasicBlock *Entry = A->getParent()->begin(); 6249 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6250 UI != E; ++UI) { 6251 const User *U = *UI; 6252 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6253 return false; // Use not in entry block. 6254 } 6255 return true; 6256} 6257 6258void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6259 // If this is the entry block, emit arguments. 6260 const Function &F = *LLVMBB->getParent(); 6261 SelectionDAG &DAG = SDB->DAG; 6262 DebugLoc dl = SDB->getCurDebugLoc(); 6263 const TargetData *TD = TLI.getTargetData(); 6264 SmallVector<ISD::InputArg, 16> Ins; 6265 6266 // Check whether the function can return without sret-demotion. 6267 SmallVector<ISD::OutputArg, 4> Outs; 6268 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6269 Outs, TLI); 6270 6271 if (!FuncInfo->CanLowerReturn) { 6272 // Put in an sret pointer parameter before all the other parameters. 6273 SmallVector<EVT, 1> ValueVTs; 6274 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6275 6276 // NOTE: Assuming that a pointer will never break down to more than one VT 6277 // or one register. 6278 ISD::ArgFlagsTy Flags; 6279 Flags.setSRet(); 6280 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6281 ISD::InputArg RetArg(Flags, RegisterVT, true); 6282 Ins.push_back(RetArg); 6283 } 6284 6285 // Set up the incoming argument description vector. 6286 unsigned Idx = 1; 6287 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6288 I != E; ++I, ++Idx) { 6289 SmallVector<EVT, 4> ValueVTs; 6290 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6291 bool isArgValueUsed = !I->use_empty(); 6292 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6293 Value != NumValues; ++Value) { 6294 EVT VT = ValueVTs[Value]; 6295 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6296 ISD::ArgFlagsTy Flags; 6297 unsigned OriginalAlignment = 6298 TD->getABITypeAlignment(ArgTy); 6299 6300 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6301 Flags.setZExt(); 6302 if (F.paramHasAttr(Idx, Attribute::SExt)) 6303 Flags.setSExt(); 6304 if (F.paramHasAttr(Idx, Attribute::InReg)) 6305 Flags.setInReg(); 6306 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6307 Flags.setSRet(); 6308 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6309 Flags.setByVal(); 6310 const PointerType *Ty = cast<PointerType>(I->getType()); 6311 const Type *ElementTy = Ty->getElementType(); 6312 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6313 unsigned FrameSize = TD->getTypeAllocSize(ElementTy); 6314 // For ByVal, alignment should be passed from FE. BE will guess if 6315 // this info is not there but there are cases it cannot get right. 6316 if (F.getParamAlignment(Idx)) 6317 FrameAlign = F.getParamAlignment(Idx); 6318 Flags.setByValAlign(FrameAlign); 6319 Flags.setByValSize(FrameSize); 6320 } 6321 if (F.paramHasAttr(Idx, Attribute::Nest)) 6322 Flags.setNest(); 6323 Flags.setOrigAlign(OriginalAlignment); 6324 6325 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6326 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6327 for (unsigned i = 0; i != NumRegs; ++i) { 6328 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6329 if (NumRegs > 1 && i == 0) 6330 MyFlags.Flags.setSplit(); 6331 // if it isn't first piece, alignment must be 1 6332 else if (i > 0) 6333 MyFlags.Flags.setOrigAlign(1); 6334 Ins.push_back(MyFlags); 6335 } 6336 } 6337 } 6338 6339 // Call the target to set up the argument values. 6340 SmallVector<SDValue, 8> InVals; 6341 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6342 F.isVarArg(), Ins, 6343 dl, DAG, InVals); 6344 6345 // Verify that the target's LowerFormalArguments behaved as expected. 6346 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6347 "LowerFormalArguments didn't return a valid chain!"); 6348 assert(InVals.size() == Ins.size() && 6349 "LowerFormalArguments didn't emit the correct number of values!"); 6350 DEBUG({ 6351 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6352 assert(InVals[i].getNode() && 6353 "LowerFormalArguments emitted a null value!"); 6354 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6355 "LowerFormalArguments emitted a value with the wrong type!"); 6356 } 6357 }); 6358 6359 // Update the DAG with the new chain value resulting from argument lowering. 6360 DAG.setRoot(NewRoot); 6361 6362 // Set up the argument values. 6363 unsigned i = 0; 6364 Idx = 1; 6365 if (!FuncInfo->CanLowerReturn) { 6366 // Create a virtual register for the sret pointer, and put in a copy 6367 // from the sret argument into it. 6368 SmallVector<EVT, 1> ValueVTs; 6369 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6370 EVT VT = ValueVTs[0]; 6371 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6372 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6373 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6374 RegVT, VT, AssertOp); 6375 6376 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6377 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6378 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6379 FuncInfo->DemoteRegister = SRetReg; 6380 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6381 SRetReg, ArgValue); 6382 DAG.setRoot(NewRoot); 6383 6384 // i indexes lowered arguments. Bump it past the hidden sret argument. 6385 // Idx indexes LLVM arguments. Don't touch it. 6386 ++i; 6387 } 6388 6389 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6390 ++I, ++Idx) { 6391 SmallVector<SDValue, 4> ArgValues; 6392 SmallVector<EVT, 4> ValueVTs; 6393 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6394 unsigned NumValues = ValueVTs.size(); 6395 6396 // If this argument is unused then remember its value. It is used to generate 6397 // debugging information. 6398 if (I->use_empty() && NumValues) 6399 SDB->setUnusedArgValue(I, InVals[i]); 6400 6401 for (unsigned Val = 0; Val != NumValues; ++Val) { 6402 EVT VT = ValueVTs[Val]; 6403 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6404 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6405 6406 if (!I->use_empty()) { 6407 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6408 if (F.paramHasAttr(Idx, Attribute::SExt)) 6409 AssertOp = ISD::AssertSext; 6410 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6411 AssertOp = ISD::AssertZext; 6412 6413 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6414 NumParts, PartVT, VT, 6415 AssertOp)); 6416 } 6417 6418 i += NumParts; 6419 } 6420 6421 // We don't need to do anything else for unused arguments. 6422 if (ArgValues.empty()) 6423 continue; 6424 6425 // Note down frame index for byval arguments. 6426 if (I->hasByValAttr()) 6427 if (FrameIndexSDNode *FI = 6428 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6429 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6430 6431 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6432 SDB->getCurDebugLoc()); 6433 SDB->setValue(I, Res); 6434 6435 // If this argument is live outside of the entry block, insert a copy from 6436 // wherever we got it to the vreg that other BB's will reference it as. 6437 if (Res.getOpcode() == ISD::CopyFromReg) { 6438 // If we can, though, try to skip creating an unnecessary vreg. 6439 // FIXME: This isn't very clean... it would be nice to make this more 6440 // general. 6441 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6442 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6443 FuncInfo->ValueMap[I] = Reg; 6444 continue; 6445 } 6446 } 6447 if (!isOnlyUsedInEntryBlock(I)) { 6448 FuncInfo->InitializeRegForValue(I); 6449 SDB->CopyToExportRegsIfNeeded(I); 6450 } 6451 } 6452 6453 assert(i == InVals.size() && "Argument register count mismatch!"); 6454 6455 // Finally, if the target has anything special to do, allow it to do so. 6456 // FIXME: this should insert code into the DAG! 6457 EmitFunctionEntryCode(); 6458} 6459 6460/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6461/// ensure constants are generated when needed. Remember the virtual registers 6462/// that need to be added to the Machine PHI nodes as input. We cannot just 6463/// directly add them, because expansion might result in multiple MBB's for one 6464/// BB. As such, the start of the BB might correspond to a different MBB than 6465/// the end. 6466/// 6467void 6468SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6469 const TerminatorInst *TI = LLVMBB->getTerminator(); 6470 6471 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6472 6473 // Check successor nodes' PHI nodes that expect a constant to be available 6474 // from this block. 6475 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6476 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6477 if (!isa<PHINode>(SuccBB->begin())) continue; 6478 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6479 6480 // If this terminator has multiple identical successors (common for 6481 // switches), only handle each succ once. 6482 if (!SuccsHandled.insert(SuccMBB)) continue; 6483 6484 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6485 6486 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6487 // nodes and Machine PHI nodes, but the incoming operands have not been 6488 // emitted yet. 6489 for (BasicBlock::const_iterator I = SuccBB->begin(); 6490 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6491 // Ignore dead phi's. 6492 if (PN->use_empty()) continue; 6493 6494 unsigned Reg; 6495 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6496 6497 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6498 unsigned &RegOut = ConstantsOut[C]; 6499 if (RegOut == 0) { 6500 RegOut = FuncInfo.CreateRegs(C->getType()); 6501 CopyValueToVirtualRegister(C, RegOut); 6502 } 6503 Reg = RegOut; 6504 } else { 6505 DenseMap<const Value *, unsigned>::iterator I = 6506 FuncInfo.ValueMap.find(PHIOp); 6507 if (I != FuncInfo.ValueMap.end()) 6508 Reg = I->second; 6509 else { 6510 assert(isa<AllocaInst>(PHIOp) && 6511 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6512 "Didn't codegen value into a register!??"); 6513 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6514 CopyValueToVirtualRegister(PHIOp, Reg); 6515 } 6516 } 6517 6518 // Remember that this register needs to added to the machine PHI node as 6519 // the input for this MBB. 6520 SmallVector<EVT, 4> ValueVTs; 6521 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6522 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6523 EVT VT = ValueVTs[vti]; 6524 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6525 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6526 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6527 Reg += NumRegisters; 6528 } 6529 } 6530 } 6531 ConstantsOut.clear(); 6532} 6533