SelectionDAGBuilder.cpp revision dc54f8ebe288c7313e22902d4bdfe030e479db48
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Analysis/DebugInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameLowering.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetIntrinsicInfo.h" 50#include "llvm/Target/TargetLibraryInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/CRSBuilder.h" 55#include "llvm/Support/Debug.h" 56#include "llvm/Support/ErrorHandling.h" 57#include "llvm/Support/MathExtras.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62/// LimitFloatPrecision - Generate low-precision inline sequences for 63/// some float libcalls (6, 8 or 12 bits). 64static unsigned LimitFloatPrecision; 65 66static cl::opt<unsigned, true> 67LimitFPPrecision("limit-float-precision", 68 cl::desc("Generate low-precision inline sequences " 69 "for some float libcalls"), 70 cl::location(LimitFloatPrecision), 71 cl::init(0)); 72 73// Limit the width of DAG chains. This is important in general to prevent 74// prevent DAG-based analysis from blowing up. For example, alias analysis and 75// load clustering may not complete in reasonable time. It is difficult to 76// recognize and avoid this situation within each individual analysis, and 77// future analyses are likely to have the same behavior. Limiting DAG width is 78// the safe approach, and will be especially important with global DAGs. 79// 80// MaxParallelChains default is arbitrarily high to avoid affecting 81// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 82// sequence over this should have been converted to llvm.memcpy by the 83// frontend. It easy to induce this behavior with .ll code such as: 84// %buffer = alloca [4096 x i8] 85// %data = load [4096 x i8]* %argPtr 86// store [4096 x i8] %data, [4096 x i8]* %buffer 87static const unsigned MaxParallelChains = 64; 88 89static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 90 const SDValue *Parts, unsigned NumParts, 91 EVT PartVT, EVT ValueVT); 92 93/// getCopyFromParts - Create a value that contains the specified legal parts 94/// combined into the value they represent. If the parts combine to a type 95/// larger then ValueVT then AssertOp can be used to specify whether the extra 96/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 97/// (ISD::AssertSext). 98static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 99 const SDValue *Parts, 100 unsigned NumParts, EVT PartVT, EVT ValueVT, 101 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 102 if (ValueVT.isVector()) 103 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 104 105 assert(NumParts > 0 && "No parts to assemble!"); 106 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 107 SDValue Val = Parts[0]; 108 109 if (NumParts > 1) { 110 // Assemble the value from multiple parts. 111 if (ValueVT.isInteger()) { 112 unsigned PartBits = PartVT.getSizeInBits(); 113 unsigned ValueBits = ValueVT.getSizeInBits(); 114 115 // Assemble the power of 2 part. 116 unsigned RoundParts = NumParts & (NumParts - 1) ? 117 1 << Log2_32(NumParts) : NumParts; 118 unsigned RoundBits = PartBits * RoundParts; 119 EVT RoundVT = RoundBits == ValueBits ? 120 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 121 SDValue Lo, Hi; 122 123 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 124 125 if (RoundParts > 2) { 126 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 127 PartVT, HalfVT); 128 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 129 RoundParts / 2, PartVT, HalfVT); 130 } else { 131 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 132 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 133 } 134 135 if (TLI.isBigEndian()) 136 std::swap(Lo, Hi); 137 138 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 139 140 if (RoundParts < NumParts) { 141 // Assemble the trailing non-power-of-2 part. 142 unsigned OddParts = NumParts - RoundParts; 143 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 144 Hi = getCopyFromParts(DAG, DL, 145 Parts + RoundParts, OddParts, PartVT, OddVT); 146 147 // Combine the round and odd parts. 148 Lo = Val; 149 if (TLI.isBigEndian()) 150 std::swap(Lo, Hi); 151 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 152 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 153 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 154 DAG.getConstant(Lo.getValueType().getSizeInBits(), 155 TLI.getPointerTy())); 156 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 157 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 158 } 159 } else if (PartVT.isFloatingPoint()) { 160 // FP split into multiple FP parts (for ppcf128) 161 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 162 "Unexpected split"); 163 SDValue Lo, Hi; 164 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 165 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 166 if (TLI.isBigEndian()) 167 std::swap(Lo, Hi); 168 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 169 } else { 170 // FP split into integer parts (soft fp) 171 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 172 !PartVT.isVector() && "Unexpected split"); 173 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 174 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 175 } 176 } 177 178 // There is now one part, held in Val. Correct it to match ValueVT. 179 PartVT = Val.getValueType(); 180 181 if (PartVT == ValueVT) 182 return Val; 183 184 if (PartVT.isInteger() && ValueVT.isInteger()) { 185 if (ValueVT.bitsLT(PartVT)) { 186 // For a truncate, see if we have any information to 187 // indicate whether the truncated bits will always be 188 // zero or sign-extension. 189 if (AssertOp != ISD::DELETED_NODE) 190 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 191 DAG.getValueType(ValueVT)); 192 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 193 } 194 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 195 } 196 197 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 198 // FP_ROUND's are always exact here. 199 if (ValueVT.bitsLT(Val.getValueType())) 200 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 201 DAG.getTargetConstant(1, TLI.getPointerTy())); 202 203 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 204 } 205 206 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 207 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 208 209 llvm_unreachable("Unknown mismatch!"); 210} 211 212/// getCopyFromParts - Create a value that contains the specified legal parts 213/// combined into the value they represent. If the parts combine to a type 214/// larger then ValueVT then AssertOp can be used to specify whether the extra 215/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216/// (ISD::AssertSext). 217static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 287 "Cannot handle this kind of promotion"); 288 // Promoted vector extract 289 bool Smaller = ValueVT.bitsLE(PartVT); 290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 291 DL, ValueVT, Val); 292 293 } 294 295 // Trivial bitcast if the types are the same size and the destination 296 // vector type is legal. 297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 298 TLI.isTypeLegal(ValueVT)) 299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 300 301 // Handle cases such as i8 -> <1 x i1> 302 assert(ValueVT.getVectorNumElements() == 1 && 303 "Only trivial scalar-to-vector conversions should get here!"); 304 305 if (ValueVT.getVectorNumElements() == 1 && 306 ValueVT.getVectorElementType() != PartVT) { 307 bool Smaller = ValueVT.bitsLE(PartVT); 308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 309 DL, ValueVT.getScalarType(), Val); 310 } 311 312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 313} 314 315 316 317 318static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 319 SDValue Val, SDValue *Parts, unsigned NumParts, 320 EVT PartVT); 321 322/// getCopyToParts - Create a series of nodes that contain the specified value 323/// split into legal parts. If the parts contain more bits than Val, then, for 324/// integers, ExtendKind can be used to specify how to generate the extra bits. 325static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 326 SDValue Val, SDValue *Parts, unsigned NumParts, 327 EVT PartVT, 328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 329 EVT ValueVT = Val.getValueType(); 330 331 // Handle the vector case separately. 332 if (ValueVT.isVector()) 333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 334 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 336 unsigned PartBits = PartVT.getSizeInBits(); 337 unsigned OrigNumParts = NumParts; 338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 339 340 if (NumParts == 0) 341 return; 342 343 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 344 if (PartVT == ValueVT) { 345 assert(NumParts == 1 && "No-op copy with multiple parts!"); 346 Parts[0] = Val; 347 return; 348 } 349 350 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 351 // If the parts cover more bits than the value has, promote the value. 352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 353 assert(NumParts == 1 && "Do not know what to promote to!"); 354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 355 } else { 356 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 357 ValueVT.isInteger() && 358 "Unknown mismatch!"); 359 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 360 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 361 if (PartVT == MVT::x86mmx) 362 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 363 } 364 } else if (PartBits == ValueVT.getSizeInBits()) { 365 // Different types of the same size. 366 assert(NumParts == 1 && PartVT != ValueVT); 367 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 368 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 369 // If the parts cover less bits than value has, truncate the value. 370 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 371 ValueVT.isInteger() && 372 "Unknown mismatch!"); 373 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 374 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 375 if (PartVT == MVT::x86mmx) 376 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 377 } 378 379 // The value may have changed - recompute ValueVT. 380 ValueVT = Val.getValueType(); 381 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 382 "Failed to tile the value with PartVT!"); 383 384 if (NumParts == 1) { 385 assert(PartVT == ValueVT && "Type conversion failed!"); 386 Parts[0] = Val; 387 return; 388 } 389 390 // Expand the value into multiple parts. 391 if (NumParts & (NumParts - 1)) { 392 // The number of parts is not a power of 2. Split off and copy the tail. 393 assert(PartVT.isInteger() && ValueVT.isInteger() && 394 "Do not know what to expand to!"); 395 unsigned RoundParts = 1 << Log2_32(NumParts); 396 unsigned RoundBits = RoundParts * PartBits; 397 unsigned OddParts = NumParts - RoundParts; 398 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 399 DAG.getIntPtrConstant(RoundBits)); 400 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 401 402 if (TLI.isBigEndian()) 403 // The odd parts were reversed by getCopyToParts - unreverse them. 404 std::reverse(Parts + RoundParts, Parts + NumParts); 405 406 NumParts = RoundParts; 407 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 408 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 409 } 410 411 // The number of parts is a power of 2. Repeatedly bisect the value using 412 // EXTRACT_ELEMENT. 413 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 414 EVT::getIntegerVT(*DAG.getContext(), 415 ValueVT.getSizeInBits()), 416 Val); 417 418 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 419 for (unsigned i = 0; i < NumParts; i += StepSize) { 420 unsigned ThisBits = StepSize * PartBits / 2; 421 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 422 SDValue &Part0 = Parts[i]; 423 SDValue &Part1 = Parts[i+StepSize/2]; 424 425 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 426 ThisVT, Part0, DAG.getIntPtrConstant(1)); 427 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 428 ThisVT, Part0, DAG.getIntPtrConstant(0)); 429 430 if (ThisBits == PartBits && ThisVT != PartVT) { 431 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 432 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 433 } 434 } 435 } 436 437 if (TLI.isBigEndian()) 438 std::reverse(Parts, Parts + OrigNumParts); 439} 440 441 442/// getCopyToPartsVector - Create a series of nodes that contain the specified 443/// value split into legal parts. 444static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 445 SDValue Val, SDValue *Parts, unsigned NumParts, 446 EVT PartVT) { 447 EVT ValueVT = Val.getValueType(); 448 assert(ValueVT.isVector() && "Not a vector"); 449 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 450 451 if (NumParts == 1) { 452 if (PartVT == ValueVT) { 453 // Nothing to do. 454 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 455 // Bitconvert vector->vector case. 456 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 457 } else if (PartVT.isVector() && 458 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 459 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 460 EVT ElementVT = PartVT.getVectorElementType(); 461 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 462 // undef elements. 463 SmallVector<SDValue, 16> Ops; 464 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 465 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 466 ElementVT, Val, DAG.getIntPtrConstant(i))); 467 468 for (unsigned i = ValueVT.getVectorNumElements(), 469 e = PartVT.getVectorNumElements(); i != e; ++i) 470 Ops.push_back(DAG.getUNDEF(ElementVT)); 471 472 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 473 474 // FIXME: Use CONCAT for 2x -> 4x. 475 476 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 477 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 478 } else if (PartVT.isVector() && 479 PartVT.getVectorElementType().bitsGE( 480 ValueVT.getVectorElementType()) && 481 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 482 483 // Promoted vector extract 484 bool Smaller = PartVT.bitsLE(ValueVT); 485 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 486 DL, PartVT, Val); 487 } else{ 488 // Vector -> scalar conversion. 489 assert(ValueVT.getVectorNumElements() == 1 && 490 "Only trivial vector-to-scalar conversions should get here!"); 491 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 492 PartVT, Val, DAG.getIntPtrConstant(0)); 493 494 bool Smaller = ValueVT.bitsLE(PartVT); 495 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 496 DL, PartVT, Val); 497 } 498 499 Parts[0] = Val; 500 return; 501 } 502 503 // Handle a multi-element vector. 504 EVT IntermediateVT, RegisterVT; 505 unsigned NumIntermediates; 506 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 507 IntermediateVT, 508 NumIntermediates, RegisterVT); 509 unsigned NumElements = ValueVT.getVectorNumElements(); 510 511 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 512 NumParts = NumRegs; // Silence a compiler warning. 513 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 514 515 // Split the vector into intermediate operands. 516 SmallVector<SDValue, 8> Ops(NumIntermediates); 517 for (unsigned i = 0; i != NumIntermediates; ++i) { 518 if (IntermediateVT.isVector()) 519 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 520 IntermediateVT, Val, 521 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 522 else 523 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 524 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 525 } 526 527 // Split the intermediate operands into legal parts. 528 if (NumParts == NumIntermediates) { 529 // If the register was not expanded, promote or copy the value, 530 // as appropriate. 531 for (unsigned i = 0; i != NumParts; ++i) 532 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 533 } else if (NumParts > 0) { 534 // If the intermediate type was expanded, split each the value into 535 // legal parts. 536 assert(NumParts % NumIntermediates == 0 && 537 "Must expand into a divisible number of parts!"); 538 unsigned Factor = NumParts / NumIntermediates; 539 for (unsigned i = 0; i != NumIntermediates; ++i) 540 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 541 } 542} 543 544 545 546 547namespace { 548 /// RegsForValue - This struct represents the registers (physical or virtual) 549 /// that a particular set of values is assigned, and the type information 550 /// about the value. The most common situation is to represent one value at a 551 /// time, but struct or array values are handled element-wise as multiple 552 /// values. The splitting of aggregates is performed recursively, so that we 553 /// never have aggregate-typed registers. The values at this point do not 554 /// necessarily have legal types, so each value may require one or more 555 /// registers of some legal type. 556 /// 557 struct RegsForValue { 558 /// ValueVTs - The value types of the values, which may not be legal, and 559 /// may need be promoted or synthesized from one or more registers. 560 /// 561 SmallVector<EVT, 4> ValueVTs; 562 563 /// RegVTs - The value types of the registers. This is the same size as 564 /// ValueVTs and it records, for each value, what the type of the assigned 565 /// register or registers are. (Individual values are never synthesized 566 /// from more than one type of register.) 567 /// 568 /// With virtual registers, the contents of RegVTs is redundant with TLI's 569 /// getRegisterType member function, however when with physical registers 570 /// it is necessary to have a separate record of the types. 571 /// 572 SmallVector<EVT, 4> RegVTs; 573 574 /// Regs - This list holds the registers assigned to the values. 575 /// Each legal or promoted value requires one register, and each 576 /// expanded value requires multiple registers. 577 /// 578 SmallVector<unsigned, 4> Regs; 579 580 RegsForValue() {} 581 582 RegsForValue(const SmallVector<unsigned, 4> ®s, 583 EVT regvt, EVT valuevt) 584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 585 586 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 587 unsigned Reg, Type *Ty) { 588 ComputeValueVTs(tli, Ty, ValueVTs); 589 590 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 591 EVT ValueVT = ValueVTs[Value]; 592 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 593 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 594 for (unsigned i = 0; i != NumRegs; ++i) 595 Regs.push_back(Reg + i); 596 RegVTs.push_back(RegisterVT); 597 Reg += NumRegs; 598 } 599 } 600 601 /// areValueTypesLegal - Return true if types of all the values are legal. 602 bool areValueTypesLegal(const TargetLowering &TLI) { 603 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 604 EVT RegisterVT = RegVTs[Value]; 605 if (!TLI.isTypeLegal(RegisterVT)) 606 return false; 607 } 608 return true; 609 } 610 611 /// append - Add the specified values to this one. 612 void append(const RegsForValue &RHS) { 613 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 614 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 615 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 616 } 617 618 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 619 /// this value and returns the result as a ValueVTs value. This uses 620 /// Chain/Flag as the input and updates them for the output Chain/Flag. 621 /// If the Flag pointer is NULL, no flag is used. 622 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 623 DebugLoc dl, 624 SDValue &Chain, SDValue *Flag) const; 625 626 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 627 /// specified value into the registers specified by this object. This uses 628 /// Chain/Flag as the input and updates them for the output Chain/Flag. 629 /// If the Flag pointer is NULL, no flag is used. 630 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 631 SDValue &Chain, SDValue *Flag) const; 632 633 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 634 /// operand list. This adds the code marker, matching input operand index 635 /// (if applicable), and includes the number of values added into it. 636 void AddInlineAsmOperands(unsigned Kind, 637 bool HasMatching, unsigned MatchingIdx, 638 SelectionDAG &DAG, 639 std::vector<SDValue> &Ops) const; 640 }; 641} 642 643/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 644/// this value and returns the result as a ValueVT value. This uses 645/// Chain/Flag as the input and updates them for the output Chain/Flag. 646/// If the Flag pointer is NULL, no flag is used. 647SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 648 FunctionLoweringInfo &FuncInfo, 649 DebugLoc dl, 650 SDValue &Chain, SDValue *Flag) const { 651 // A Value with type {} or [0 x %t] needs no registers. 652 if (ValueVTs.empty()) 653 return SDValue(); 654 655 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 656 657 // Assemble the legal parts into the final values. 658 SmallVector<SDValue, 4> Values(ValueVTs.size()); 659 SmallVector<SDValue, 8> Parts; 660 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 661 // Copy the legal parts from the registers. 662 EVT ValueVT = ValueVTs[Value]; 663 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 664 EVT RegisterVT = RegVTs[Value]; 665 666 Parts.resize(NumRegs); 667 for (unsigned i = 0; i != NumRegs; ++i) { 668 SDValue P; 669 if (Flag == 0) { 670 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 671 } else { 672 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 673 *Flag = P.getValue(2); 674 } 675 676 Chain = P.getValue(1); 677 Parts[i] = P; 678 679 // If the source register was virtual and if we know something about it, 680 // add an assert node. 681 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 682 !RegisterVT.isInteger() || RegisterVT.isVector()) 683 continue; 684 685 const FunctionLoweringInfo::LiveOutInfo *LOI = 686 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 687 if (!LOI) 688 continue; 689 690 unsigned RegSize = RegisterVT.getSizeInBits(); 691 unsigned NumSignBits = LOI->NumSignBits; 692 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 693 694 // FIXME: We capture more information than the dag can represent. For 695 // now, just use the tightest assertzext/assertsext possible. 696 bool isSExt = true; 697 EVT FromVT(MVT::Other); 698 if (NumSignBits == RegSize) 699 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 700 else if (NumZeroBits >= RegSize-1) 701 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 702 else if (NumSignBits > RegSize-8) 703 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 704 else if (NumZeroBits >= RegSize-8) 705 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 706 else if (NumSignBits > RegSize-16) 707 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 708 else if (NumZeroBits >= RegSize-16) 709 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 710 else if (NumSignBits > RegSize-32) 711 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 712 else if (NumZeroBits >= RegSize-32) 713 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 714 else 715 continue; 716 717 // Add an assertion node. 718 assert(FromVT != MVT::Other); 719 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 720 RegisterVT, P, DAG.getValueType(FromVT)); 721 } 722 723 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 724 NumRegs, RegisterVT, ValueVT); 725 Part += NumRegs; 726 Parts.clear(); 727 } 728 729 return DAG.getNode(ISD::MERGE_VALUES, dl, 730 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 731 &Values[0], ValueVTs.size()); 732} 733 734/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 735/// specified value into the registers specified by this object. This uses 736/// Chain/Flag as the input and updates them for the output Chain/Flag. 737/// If the Flag pointer is NULL, no flag is used. 738void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 739 SDValue &Chain, SDValue *Flag) const { 740 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 741 742 // Get the list of the values's legal parts. 743 unsigned NumRegs = Regs.size(); 744 SmallVector<SDValue, 8> Parts(NumRegs); 745 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 746 EVT ValueVT = ValueVTs[Value]; 747 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 748 EVT RegisterVT = RegVTs[Value]; 749 750 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 751 &Parts[Part], NumParts, RegisterVT); 752 Part += NumParts; 753 } 754 755 // Copy the parts into the registers. 756 SmallVector<SDValue, 8> Chains(NumRegs); 757 for (unsigned i = 0; i != NumRegs; ++i) { 758 SDValue Part; 759 if (Flag == 0) { 760 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 761 } else { 762 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 763 *Flag = Part.getValue(1); 764 } 765 766 Chains[i] = Part.getValue(0); 767 } 768 769 if (NumRegs == 1 || Flag) 770 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 771 // flagged to it. That is the CopyToReg nodes and the user are considered 772 // a single scheduling unit. If we create a TokenFactor and return it as 773 // chain, then the TokenFactor is both a predecessor (operand) of the 774 // user as well as a successor (the TF operands are flagged to the user). 775 // c1, f1 = CopyToReg 776 // c2, f2 = CopyToReg 777 // c3 = TokenFactor c1, c2 778 // ... 779 // = op c3, ..., f2 780 Chain = Chains[NumRegs-1]; 781 else 782 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 783} 784 785/// AddInlineAsmOperands - Add this value to the specified inlineasm node 786/// operand list. This adds the code marker and includes the number of 787/// values added into it. 788void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 789 unsigned MatchingIdx, 790 SelectionDAG &DAG, 791 std::vector<SDValue> &Ops) const { 792 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 793 794 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 795 if (HasMatching) 796 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 797 else if (!Regs.empty() && 798 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 799 // Put the register class of the virtual registers in the flag word. That 800 // way, later passes can recompute register class constraints for inline 801 // assembly as well as normal instructions. 802 // Don't do this for tied operands that can use the regclass information 803 // from the def. 804 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 805 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 806 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 807 } 808 809 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 810 Ops.push_back(Res); 811 812 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 813 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 814 EVT RegisterVT = RegVTs[Value]; 815 for (unsigned i = 0; i != NumRegs; ++i) { 816 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 817 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 818 } 819 } 820} 821 822void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 823 const TargetLibraryInfo *li) { 824 AA = &aa; 825 GFI = gfi; 826 LibInfo = li; 827 TD = DAG.getTarget().getTargetData(); 828 LPadToCallSiteMap.clear(); 829} 830 831/// clear - Clear out the current SelectionDAG and the associated 832/// state and prepare this SelectionDAGBuilder object to be used 833/// for a new block. This doesn't clear out information about 834/// additional blocks that are needed to complete switch lowering 835/// or PHI node updating; that information is cleared out as it is 836/// consumed. 837void SelectionDAGBuilder::clear() { 838 NodeMap.clear(); 839 UnusedArgNodeMap.clear(); 840 PendingLoads.clear(); 841 PendingExports.clear(); 842 CurDebugLoc = DebugLoc(); 843 HasTailCall = false; 844} 845 846/// clearDanglingDebugInfo - Clear the dangling debug information 847/// map. This function is seperated from the clear so that debug 848/// information that is dangling in a basic block can be properly 849/// resolved in a different basic block. This allows the 850/// SelectionDAG to resolve dangling debug information attached 851/// to PHI nodes. 852void SelectionDAGBuilder::clearDanglingDebugInfo() { 853 DanglingDebugInfoMap.clear(); 854} 855 856/// getRoot - Return the current virtual root of the Selection DAG, 857/// flushing any PendingLoad items. This must be done before emitting 858/// a store or any other node that may need to be ordered after any 859/// prior load instructions. 860/// 861SDValue SelectionDAGBuilder::getRoot() { 862 if (PendingLoads.empty()) 863 return DAG.getRoot(); 864 865 if (PendingLoads.size() == 1) { 866 SDValue Root = PendingLoads[0]; 867 DAG.setRoot(Root); 868 PendingLoads.clear(); 869 return Root; 870 } 871 872 // Otherwise, we have to make a token factor node. 873 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 874 &PendingLoads[0], PendingLoads.size()); 875 PendingLoads.clear(); 876 DAG.setRoot(Root); 877 return Root; 878} 879 880/// getControlRoot - Similar to getRoot, but instead of flushing all the 881/// PendingLoad items, flush all the PendingExports items. It is necessary 882/// to do this before emitting a terminator instruction. 883/// 884SDValue SelectionDAGBuilder::getControlRoot() { 885 SDValue Root = DAG.getRoot(); 886 887 if (PendingExports.empty()) 888 return Root; 889 890 // Turn all of the CopyToReg chains into one factored node. 891 if (Root.getOpcode() != ISD::EntryToken) { 892 unsigned i = 0, e = PendingExports.size(); 893 for (; i != e; ++i) { 894 assert(PendingExports[i].getNode()->getNumOperands() > 1); 895 if (PendingExports[i].getNode()->getOperand(0) == Root) 896 break; // Don't add the root if we already indirectly depend on it. 897 } 898 899 if (i == e) 900 PendingExports.push_back(Root); 901 } 902 903 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 904 &PendingExports[0], 905 PendingExports.size()); 906 PendingExports.clear(); 907 DAG.setRoot(Root); 908 return Root; 909} 910 911void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 912 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 913 DAG.AssignOrdering(Node, SDNodeOrder); 914 915 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 916 AssignOrderingToNode(Node->getOperand(I).getNode()); 917} 918 919void SelectionDAGBuilder::visit(const Instruction &I) { 920 // Set up outgoing PHI node register values before emitting the terminator. 921 if (isa<TerminatorInst>(&I)) 922 HandlePHINodesInSuccessorBlocks(I.getParent()); 923 924 CurDebugLoc = I.getDebugLoc(); 925 926 visit(I.getOpcode(), I); 927 928 if (!isa<TerminatorInst>(&I) && !HasTailCall) 929 CopyToExportRegsIfNeeded(&I); 930 931 CurDebugLoc = DebugLoc(); 932} 933 934void SelectionDAGBuilder::visitPHI(const PHINode &) { 935 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 936} 937 938void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 939 // Note: this doesn't use InstVisitor, because it has to work with 940 // ConstantExpr's in addition to instructions. 941 switch (Opcode) { 942 default: llvm_unreachable("Unknown instruction type encountered!"); 943 // Build the switch statement using the Instruction.def file. 944#define HANDLE_INST(NUM, OPCODE, CLASS) \ 945 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 946#include "llvm/Instruction.def" 947 } 948 949 // Assign the ordering to the freshly created DAG nodes. 950 if (NodeMap.count(&I)) { 951 ++SDNodeOrder; 952 AssignOrderingToNode(getValue(&I).getNode()); 953 } 954} 955 956// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 957// generate the debug data structures now that we've seen its definition. 958void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 959 SDValue Val) { 960 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 961 if (DDI.getDI()) { 962 const DbgValueInst *DI = DDI.getDI(); 963 DebugLoc dl = DDI.getdl(); 964 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 965 MDNode *Variable = DI->getVariable(); 966 uint64_t Offset = DI->getOffset(); 967 SDDbgValue *SDV; 968 if (Val.getNode()) { 969 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 970 SDV = DAG.getDbgValue(Variable, Val.getNode(), 971 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 972 DAG.AddDbgValue(SDV, Val.getNode(), false); 973 } 974 } else 975 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 976 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 977 } 978} 979 980/// getValue - Return an SDValue for the given Value. 981SDValue SelectionDAGBuilder::getValue(const Value *V) { 982 // If we already have an SDValue for this value, use it. It's important 983 // to do this first, so that we don't create a CopyFromReg if we already 984 // have a regular SDValue. 985 SDValue &N = NodeMap[V]; 986 if (N.getNode()) return N; 987 988 // If there's a virtual register allocated and initialized for this 989 // value, use it. 990 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 991 if (It != FuncInfo.ValueMap.end()) { 992 unsigned InReg = It->second; 993 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 994 SDValue Chain = DAG.getEntryNode(); 995 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 996 resolveDanglingDebugInfo(V, N); 997 return N; 998 } 999 1000 // Otherwise create a new SDValue and remember it. 1001 SDValue Val = getValueImpl(V); 1002 NodeMap[V] = Val; 1003 resolveDanglingDebugInfo(V, Val); 1004 return Val; 1005} 1006 1007/// getNonRegisterValue - Return an SDValue for the given Value, but 1008/// don't look in FuncInfo.ValueMap for a virtual register. 1009SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1010 // If we already have an SDValue for this value, use it. 1011 SDValue &N = NodeMap[V]; 1012 if (N.getNode()) return N; 1013 1014 // Otherwise create a new SDValue and remember it. 1015 SDValue Val = getValueImpl(V); 1016 NodeMap[V] = Val; 1017 resolveDanglingDebugInfo(V, Val); 1018 return Val; 1019} 1020 1021/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1022/// Create an SDValue for the given value. 1023SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1024 if (const Constant *C = dyn_cast<Constant>(V)) { 1025 EVT VT = TLI.getValueType(V->getType(), true); 1026 1027 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1028 return DAG.getConstant(*CI, VT); 1029 1030 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1031 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1032 1033 if (isa<ConstantPointerNull>(C)) 1034 return DAG.getConstant(0, TLI.getPointerTy()); 1035 1036 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1037 return DAG.getConstantFP(*CFP, VT); 1038 1039 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1040 return DAG.getUNDEF(VT); 1041 1042 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1043 visit(CE->getOpcode(), *CE); 1044 SDValue N1 = NodeMap[V]; 1045 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1046 return N1; 1047 } 1048 1049 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1050 SmallVector<SDValue, 4> Constants; 1051 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1052 OI != OE; ++OI) { 1053 SDNode *Val = getValue(*OI).getNode(); 1054 // If the operand is an empty aggregate, there are no values. 1055 if (!Val) continue; 1056 // Add each leaf value from the operand to the Constants list 1057 // to form a flattened list of all the values. 1058 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1059 Constants.push_back(SDValue(Val, i)); 1060 } 1061 1062 return DAG.getMergeValues(&Constants[0], Constants.size(), 1063 getCurDebugLoc()); 1064 } 1065 1066 if (const ConstantDataSequential *CDS = 1067 dyn_cast<ConstantDataSequential>(C)) { 1068 SmallVector<SDValue, 4> Ops; 1069 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { 1070 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1071 // Add each leaf value from the operand to the Constants list 1072 // to form a flattened list of all the values. 1073 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1074 Ops.push_back(SDValue(Val, i)); 1075 } 1076 1077 if (isa<ArrayType>(CDS->getType())) 1078 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc()); 1079 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1080 VT, &Ops[0], Ops.size()); 1081 } 1082 1083 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1084 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1085 "Unknown struct or array constant!"); 1086 1087 SmallVector<EVT, 4> ValueVTs; 1088 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1089 unsigned NumElts = ValueVTs.size(); 1090 if (NumElts == 0) 1091 return SDValue(); // empty struct 1092 SmallVector<SDValue, 4> Constants(NumElts); 1093 for (unsigned i = 0; i != NumElts; ++i) { 1094 EVT EltVT = ValueVTs[i]; 1095 if (isa<UndefValue>(C)) 1096 Constants[i] = DAG.getUNDEF(EltVT); 1097 else if (EltVT.isFloatingPoint()) 1098 Constants[i] = DAG.getConstantFP(0, EltVT); 1099 else 1100 Constants[i] = DAG.getConstant(0, EltVT); 1101 } 1102 1103 return DAG.getMergeValues(&Constants[0], NumElts, 1104 getCurDebugLoc()); 1105 } 1106 1107 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1108 return DAG.getBlockAddress(BA, VT); 1109 1110 VectorType *VecTy = cast<VectorType>(V->getType()); 1111 unsigned NumElements = VecTy->getNumElements(); 1112 1113 // Now that we know the number and type of the elements, get that number of 1114 // elements into the Ops array based on what kind of constant it is. 1115 SmallVector<SDValue, 16> Ops; 1116 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1117 for (unsigned i = 0; i != NumElements; ++i) 1118 Ops.push_back(getValue(CV->getOperand(i))); 1119 } else { 1120 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1121 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1122 1123 SDValue Op; 1124 if (EltVT.isFloatingPoint()) 1125 Op = DAG.getConstantFP(0, EltVT); 1126 else 1127 Op = DAG.getConstant(0, EltVT); 1128 Ops.assign(NumElements, Op); 1129 } 1130 1131 // Create a BUILD_VECTOR node. 1132 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1133 VT, &Ops[0], Ops.size()); 1134 } 1135 1136 // If this is a static alloca, generate it as the frameindex instead of 1137 // computation. 1138 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1139 DenseMap<const AllocaInst*, int>::iterator SI = 1140 FuncInfo.StaticAllocaMap.find(AI); 1141 if (SI != FuncInfo.StaticAllocaMap.end()) 1142 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1143 } 1144 1145 // If this is an instruction which fast-isel has deferred, select it now. 1146 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1147 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1148 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1149 SDValue Chain = DAG.getEntryNode(); 1150 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1151 } 1152 1153 llvm_unreachable("Can't get register for value!"); 1154} 1155 1156void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1157 SDValue Chain = getControlRoot(); 1158 SmallVector<ISD::OutputArg, 8> Outs; 1159 SmallVector<SDValue, 8> OutVals; 1160 1161 if (!FuncInfo.CanLowerReturn) { 1162 unsigned DemoteReg = FuncInfo.DemoteRegister; 1163 const Function *F = I.getParent()->getParent(); 1164 1165 // Emit a store of the return value through the virtual register. 1166 // Leave Outs empty so that LowerReturn won't try to load return 1167 // registers the usual way. 1168 SmallVector<EVT, 1> PtrValueVTs; 1169 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1170 PtrValueVTs); 1171 1172 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1173 SDValue RetOp = getValue(I.getOperand(0)); 1174 1175 SmallVector<EVT, 4> ValueVTs; 1176 SmallVector<uint64_t, 4> Offsets; 1177 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1178 unsigned NumValues = ValueVTs.size(); 1179 1180 SmallVector<SDValue, 4> Chains(NumValues); 1181 for (unsigned i = 0; i != NumValues; ++i) { 1182 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1183 RetPtr.getValueType(), RetPtr, 1184 DAG.getIntPtrConstant(Offsets[i])); 1185 Chains[i] = 1186 DAG.getStore(Chain, getCurDebugLoc(), 1187 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1188 // FIXME: better loc info would be nice. 1189 Add, MachinePointerInfo(), false, false, 0); 1190 } 1191 1192 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1193 MVT::Other, &Chains[0], NumValues); 1194 } else if (I.getNumOperands() != 0) { 1195 SmallVector<EVT, 4> ValueVTs; 1196 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1197 unsigned NumValues = ValueVTs.size(); 1198 if (NumValues) { 1199 SDValue RetOp = getValue(I.getOperand(0)); 1200 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1201 EVT VT = ValueVTs[j]; 1202 1203 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1204 1205 const Function *F = I.getParent()->getParent(); 1206 if (F->paramHasAttr(0, Attribute::SExt)) 1207 ExtendKind = ISD::SIGN_EXTEND; 1208 else if (F->paramHasAttr(0, Attribute::ZExt)) 1209 ExtendKind = ISD::ZERO_EXTEND; 1210 1211 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1212 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1213 1214 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1215 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1216 SmallVector<SDValue, 4> Parts(NumParts); 1217 getCopyToParts(DAG, getCurDebugLoc(), 1218 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1219 &Parts[0], NumParts, PartVT, ExtendKind); 1220 1221 // 'inreg' on function refers to return value 1222 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1223 if (F->paramHasAttr(0, Attribute::InReg)) 1224 Flags.setInReg(); 1225 1226 // Propagate extension type if any 1227 if (ExtendKind == ISD::SIGN_EXTEND) 1228 Flags.setSExt(); 1229 else if (ExtendKind == ISD::ZERO_EXTEND) 1230 Flags.setZExt(); 1231 1232 for (unsigned i = 0; i < NumParts; ++i) { 1233 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1234 /*isfixed=*/true)); 1235 OutVals.push_back(Parts[i]); 1236 } 1237 } 1238 } 1239 } 1240 1241 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1242 CallingConv::ID CallConv = 1243 DAG.getMachineFunction().getFunction()->getCallingConv(); 1244 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1245 Outs, OutVals, getCurDebugLoc(), DAG); 1246 1247 // Verify that the target's LowerReturn behaved as expected. 1248 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1249 "LowerReturn didn't return a valid chain!"); 1250 1251 // Update the DAG with the new chain value resulting from return lowering. 1252 DAG.setRoot(Chain); 1253} 1254 1255/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1256/// created for it, emit nodes to copy the value into the virtual 1257/// registers. 1258void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1259 // Skip empty types 1260 if (V->getType()->isEmptyTy()) 1261 return; 1262 1263 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1264 if (VMI != FuncInfo.ValueMap.end()) { 1265 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1266 CopyValueToVirtualRegister(V, VMI->second); 1267 } 1268} 1269 1270/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1271/// the current basic block, add it to ValueMap now so that we'll get a 1272/// CopyTo/FromReg. 1273void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1274 // No need to export constants. 1275 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1276 1277 // Already exported? 1278 if (FuncInfo.isExportedInst(V)) return; 1279 1280 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1281 CopyValueToVirtualRegister(V, Reg); 1282} 1283 1284bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1285 const BasicBlock *FromBB) { 1286 // The operands of the setcc have to be in this block. We don't know 1287 // how to export them from some other block. 1288 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1289 // Can export from current BB. 1290 if (VI->getParent() == FromBB) 1291 return true; 1292 1293 // Is already exported, noop. 1294 return FuncInfo.isExportedInst(V); 1295 } 1296 1297 // If this is an argument, we can export it if the BB is the entry block or 1298 // if it is already exported. 1299 if (isa<Argument>(V)) { 1300 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1301 return true; 1302 1303 // Otherwise, can only export this if it is already exported. 1304 return FuncInfo.isExportedInst(V); 1305 } 1306 1307 // Otherwise, constants can always be exported. 1308 return true; 1309} 1310 1311/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1312uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1313 const MachineBasicBlock *Dst) const { 1314 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1315 if (!BPI) 1316 return 0; 1317 const BasicBlock *SrcBB = Src->getBasicBlock(); 1318 const BasicBlock *DstBB = Dst->getBasicBlock(); 1319 return BPI->getEdgeWeight(SrcBB, DstBB); 1320} 1321 1322void SelectionDAGBuilder:: 1323addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1324 uint32_t Weight /* = 0 */) { 1325 if (!Weight) 1326 Weight = getEdgeWeight(Src, Dst); 1327 Src->addSuccessor(Dst, Weight); 1328} 1329 1330 1331static bool InBlock(const Value *V, const BasicBlock *BB) { 1332 if (const Instruction *I = dyn_cast<Instruction>(V)) 1333 return I->getParent() == BB; 1334 return true; 1335} 1336 1337/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1338/// This function emits a branch and is used at the leaves of an OR or an 1339/// AND operator tree. 1340/// 1341void 1342SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1343 MachineBasicBlock *TBB, 1344 MachineBasicBlock *FBB, 1345 MachineBasicBlock *CurBB, 1346 MachineBasicBlock *SwitchBB) { 1347 const BasicBlock *BB = CurBB->getBasicBlock(); 1348 1349 // If the leaf of the tree is a comparison, merge the condition into 1350 // the caseblock. 1351 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1352 // The operands of the cmp have to be in this block. We don't know 1353 // how to export them from some other block. If this is the first block 1354 // of the sequence, no exporting is needed. 1355 if (CurBB == SwitchBB || 1356 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1357 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1358 ISD::CondCode Condition; 1359 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1360 Condition = getICmpCondCode(IC->getPredicate()); 1361 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1362 Condition = getFCmpCondCode(FC->getPredicate()); 1363 if (TM.Options.NoNaNsFPMath) 1364 Condition = getFCmpCodeWithoutNaN(Condition); 1365 } else { 1366 Condition = ISD::SETEQ; // silence warning. 1367 llvm_unreachable("Unknown compare instruction"); 1368 } 1369 1370 CaseBlock CB(Condition, BOp->getOperand(0), 1371 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1372 SwitchCases.push_back(CB); 1373 return; 1374 } 1375 } 1376 1377 // Create a CaseBlock record representing this branch. 1378 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1379 NULL, TBB, FBB, CurBB); 1380 SwitchCases.push_back(CB); 1381} 1382 1383/// FindMergedConditions - If Cond is an expression like 1384void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1385 MachineBasicBlock *TBB, 1386 MachineBasicBlock *FBB, 1387 MachineBasicBlock *CurBB, 1388 MachineBasicBlock *SwitchBB, 1389 unsigned Opc) { 1390 // If this node is not part of the or/and tree, emit it as a branch. 1391 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1392 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1393 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1394 BOp->getParent() != CurBB->getBasicBlock() || 1395 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1396 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1397 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1398 return; 1399 } 1400 1401 // Create TmpBB after CurBB. 1402 MachineFunction::iterator BBI = CurBB; 1403 MachineFunction &MF = DAG.getMachineFunction(); 1404 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1405 CurBB->getParent()->insert(++BBI, TmpBB); 1406 1407 if (Opc == Instruction::Or) { 1408 // Codegen X | Y as: 1409 // jmp_if_X TBB 1410 // jmp TmpBB 1411 // TmpBB: 1412 // jmp_if_Y TBB 1413 // jmp FBB 1414 // 1415 1416 // Emit the LHS condition. 1417 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1418 1419 // Emit the RHS condition into TmpBB. 1420 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1421 } else { 1422 assert(Opc == Instruction::And && "Unknown merge op!"); 1423 // Codegen X & Y as: 1424 // jmp_if_X TmpBB 1425 // jmp FBB 1426 // TmpBB: 1427 // jmp_if_Y TBB 1428 // jmp FBB 1429 // 1430 // This requires creation of TmpBB after CurBB. 1431 1432 // Emit the LHS condition. 1433 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1434 1435 // Emit the RHS condition into TmpBB. 1436 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1437 } 1438} 1439 1440/// If the set of cases should be emitted as a series of branches, return true. 1441/// If we should emit this as a bunch of and/or'd together conditions, return 1442/// false. 1443bool 1444SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1445 if (Cases.size() != 2) return true; 1446 1447 // If this is two comparisons of the same values or'd or and'd together, they 1448 // will get folded into a single comparison, so don't emit two blocks. 1449 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1450 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1451 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1452 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1453 return false; 1454 } 1455 1456 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1457 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1458 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1459 Cases[0].CC == Cases[1].CC && 1460 isa<Constant>(Cases[0].CmpRHS) && 1461 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1462 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1463 return false; 1464 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1465 return false; 1466 } 1467 1468 return true; 1469} 1470 1471void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1472 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1473 1474 // Update machine-CFG edges. 1475 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1476 1477 // Figure out which block is immediately after the current one. 1478 MachineBasicBlock *NextBlock = 0; 1479 MachineFunction::iterator BBI = BrMBB; 1480 if (++BBI != FuncInfo.MF->end()) 1481 NextBlock = BBI; 1482 1483 if (I.isUnconditional()) { 1484 // Update machine-CFG edges. 1485 BrMBB->addSuccessor(Succ0MBB); 1486 1487 // If this is not a fall-through branch, emit the branch. 1488 if (Succ0MBB != NextBlock) 1489 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1490 MVT::Other, getControlRoot(), 1491 DAG.getBasicBlock(Succ0MBB))); 1492 1493 return; 1494 } 1495 1496 // If this condition is one of the special cases we handle, do special stuff 1497 // now. 1498 const Value *CondVal = I.getCondition(); 1499 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1500 1501 // If this is a series of conditions that are or'd or and'd together, emit 1502 // this as a sequence of branches instead of setcc's with and/or operations. 1503 // As long as jumps are not expensive, this should improve performance. 1504 // For example, instead of something like: 1505 // cmp A, B 1506 // C = seteq 1507 // cmp D, E 1508 // F = setle 1509 // or C, F 1510 // jnz foo 1511 // Emit: 1512 // cmp A, B 1513 // je foo 1514 // cmp D, E 1515 // jle foo 1516 // 1517 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1518 if (!TLI.isJumpExpensive() && 1519 BOp->hasOneUse() && 1520 (BOp->getOpcode() == Instruction::And || 1521 BOp->getOpcode() == Instruction::Or)) { 1522 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1523 BOp->getOpcode()); 1524 // If the compares in later blocks need to use values not currently 1525 // exported from this block, export them now. This block should always 1526 // be the first entry. 1527 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1528 1529 // Allow some cases to be rejected. 1530 if (ShouldEmitAsBranches(SwitchCases)) { 1531 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1532 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1533 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1534 } 1535 1536 // Emit the branch for this block. 1537 visitSwitchCase(SwitchCases[0], BrMBB); 1538 SwitchCases.erase(SwitchCases.begin()); 1539 return; 1540 } 1541 1542 // Okay, we decided not to do this, remove any inserted MBB's and clear 1543 // SwitchCases. 1544 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1545 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1546 1547 SwitchCases.clear(); 1548 } 1549 } 1550 1551 // Create a CaseBlock record representing this branch. 1552 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1553 NULL, Succ0MBB, Succ1MBB, BrMBB); 1554 1555 // Use visitSwitchCase to actually insert the fast branch sequence for this 1556 // cond branch. 1557 visitSwitchCase(CB, BrMBB); 1558} 1559 1560/// visitSwitchCase - Emits the necessary code to represent a single node in 1561/// the binary search tree resulting from lowering a switch instruction. 1562void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1563 MachineBasicBlock *SwitchBB) { 1564 SDValue Cond; 1565 SDValue CondLHS = getValue(CB.CmpLHS); 1566 DebugLoc dl = getCurDebugLoc(); 1567 1568 // Build the setcc now. 1569 if (CB.CmpMHS == NULL) { 1570 // Fold "(X == true)" to X and "(X == false)" to !X to 1571 // handle common cases produced by branch lowering. 1572 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1573 CB.CC == ISD::SETEQ) 1574 Cond = CondLHS; 1575 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1576 CB.CC == ISD::SETEQ) { 1577 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1578 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1579 } else 1580 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1581 } else { 1582 assert(CB.CC == ISD::SETCC_INVALID && 1583 "Condition is undefined for to-the-range belonging check."); 1584 1585 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1586 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1587 1588 SDValue CmpOp = getValue(CB.CmpMHS); 1589 EVT VT = CmpOp.getValueType(); 1590 1591 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) { 1592 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1593 ISD::SETULE); 1594 } else { 1595 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1596 VT, CmpOp, DAG.getConstant(Low, VT)); 1597 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1598 DAG.getConstant(High-Low, VT), ISD::SETULE); 1599 } 1600 } 1601 1602 // Update successor info 1603 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1604 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1605 1606 // Set NextBlock to be the MBB immediately after the current one, if any. 1607 // This is used to avoid emitting unnecessary branches to the next block. 1608 MachineBasicBlock *NextBlock = 0; 1609 MachineFunction::iterator BBI = SwitchBB; 1610 if (++BBI != FuncInfo.MF->end()) 1611 NextBlock = BBI; 1612 1613 // If the lhs block is the next block, invert the condition so that we can 1614 // fall through to the lhs instead of the rhs block. 1615 if (CB.TrueBB == NextBlock) { 1616 std::swap(CB.TrueBB, CB.FalseBB); 1617 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1618 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1619 } 1620 1621 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1622 MVT::Other, getControlRoot(), Cond, 1623 DAG.getBasicBlock(CB.TrueBB)); 1624 1625 // Insert the false branch. Do this even if it's a fall through branch, 1626 // this makes it easier to do DAG optimizations which require inverting 1627 // the branch condition. 1628 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1629 DAG.getBasicBlock(CB.FalseBB)); 1630 1631 DAG.setRoot(BrCond); 1632} 1633 1634/// visitJumpTable - Emit JumpTable node in the current MBB 1635void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1636 // Emit the code for the jump table 1637 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1638 EVT PTy = TLI.getPointerTy(); 1639 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1640 JT.Reg, PTy); 1641 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1642 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1643 MVT::Other, Index.getValue(1), 1644 Table, Index); 1645 DAG.setRoot(BrJumpTable); 1646} 1647 1648/// visitJumpTableHeader - This function emits necessary code to produce index 1649/// in the JumpTable from switch case. 1650void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1651 JumpTableHeader &JTH, 1652 MachineBasicBlock *SwitchBB) { 1653 // Subtract the lowest switch case value from the value being switched on and 1654 // conditional branch to default mbb if the result is greater than the 1655 // difference between smallest and largest cases. 1656 SDValue SwitchOp = getValue(JTH.SValue); 1657 EVT VT = SwitchOp.getValueType(); 1658 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1659 DAG.getConstant(JTH.First, VT)); 1660 1661 // The SDNode we just created, which holds the value being switched on minus 1662 // the smallest case value, needs to be copied to a virtual register so it 1663 // can be used as an index into the jump table in a subsequent basic block. 1664 // This value may be smaller or larger than the target's pointer type, and 1665 // therefore require extension or truncating. 1666 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1667 1668 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1669 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1670 JumpTableReg, SwitchOp); 1671 JT.Reg = JumpTableReg; 1672 1673 // Emit the range check for the jump table, and branch to the default block 1674 // for the switch statement if the value being switched on exceeds the largest 1675 // case in the switch. 1676 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1677 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1678 DAG.getConstant(JTH.Last-JTH.First,VT), 1679 ISD::SETUGT); 1680 1681 // Set NextBlock to be the MBB immediately after the current one, if any. 1682 // This is used to avoid emitting unnecessary branches to the next block. 1683 MachineBasicBlock *NextBlock = 0; 1684 MachineFunction::iterator BBI = SwitchBB; 1685 1686 if (++BBI != FuncInfo.MF->end()) 1687 NextBlock = BBI; 1688 1689 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1690 MVT::Other, CopyTo, CMP, 1691 DAG.getBasicBlock(JT.Default)); 1692 1693 if (JT.MBB != NextBlock) 1694 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1695 DAG.getBasicBlock(JT.MBB)); 1696 1697 DAG.setRoot(BrCond); 1698} 1699 1700/// visitBitTestHeader - This function emits necessary code to produce value 1701/// suitable for "bit tests" 1702void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1703 MachineBasicBlock *SwitchBB) { 1704 // Subtract the minimum value 1705 SDValue SwitchOp = getValue(B.SValue); 1706 EVT VT = SwitchOp.getValueType(); 1707 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1708 DAG.getConstant(B.First, VT)); 1709 1710 // Check range 1711 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1712 TLI.getSetCCResultType(Sub.getValueType()), 1713 Sub, DAG.getConstant(B.Range, VT), 1714 ISD::SETUGT); 1715 1716 // Determine the type of the test operands. 1717 bool UsePtrType = false; 1718 if (!TLI.isTypeLegal(VT)) 1719 UsePtrType = true; 1720 else { 1721 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1722 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1723 // Switch table case range are encoded into series of masks. 1724 // Just use pointer type, it's guaranteed to fit. 1725 UsePtrType = true; 1726 break; 1727 } 1728 } 1729 if (UsePtrType) { 1730 VT = TLI.getPointerTy(); 1731 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1732 } 1733 1734 B.RegVT = VT; 1735 B.Reg = FuncInfo.CreateReg(VT); 1736 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1737 B.Reg, Sub); 1738 1739 // Set NextBlock to be the MBB immediately after the current one, if any. 1740 // This is used to avoid emitting unnecessary branches to the next block. 1741 MachineBasicBlock *NextBlock = 0; 1742 MachineFunction::iterator BBI = SwitchBB; 1743 if (++BBI != FuncInfo.MF->end()) 1744 NextBlock = BBI; 1745 1746 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1747 1748 addSuccessorWithWeight(SwitchBB, B.Default); 1749 addSuccessorWithWeight(SwitchBB, MBB); 1750 1751 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1752 MVT::Other, CopyTo, RangeCmp, 1753 DAG.getBasicBlock(B.Default)); 1754 1755 if (MBB != NextBlock) 1756 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1757 DAG.getBasicBlock(MBB)); 1758 1759 DAG.setRoot(BrRange); 1760} 1761 1762/// visitBitTestCase - this function produces one "bit test" 1763void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1764 MachineBasicBlock* NextMBB, 1765 unsigned Reg, 1766 BitTestCase &B, 1767 MachineBasicBlock *SwitchBB) { 1768 EVT VT = BB.RegVT; 1769 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1770 Reg, VT); 1771 SDValue Cmp; 1772 unsigned PopCount = CountPopulation_64(B.Mask); 1773 if (PopCount == 1) { 1774 // Testing for a single bit; just compare the shift count with what it 1775 // would need to be to shift a 1 bit in that position. 1776 Cmp = DAG.getSetCC(getCurDebugLoc(), 1777 TLI.getSetCCResultType(VT), 1778 ShiftOp, 1779 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1780 ISD::SETEQ); 1781 } else if (PopCount == BB.Range) { 1782 // There is only one zero bit in the range, test for it directly. 1783 Cmp = DAG.getSetCC(getCurDebugLoc(), 1784 TLI.getSetCCResultType(VT), 1785 ShiftOp, 1786 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1787 ISD::SETNE); 1788 } else { 1789 // Make desired shift 1790 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1791 DAG.getConstant(1, VT), ShiftOp); 1792 1793 // Emit bit tests and jumps 1794 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1795 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1796 Cmp = DAG.getSetCC(getCurDebugLoc(), 1797 TLI.getSetCCResultType(VT), 1798 AndOp, DAG.getConstant(0, VT), 1799 ISD::SETNE); 1800 } 1801 1802 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1803 addSuccessorWithWeight(SwitchBB, NextMBB); 1804 1805 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1806 MVT::Other, getControlRoot(), 1807 Cmp, DAG.getBasicBlock(B.TargetBB)); 1808 1809 // Set NextBlock to be the MBB immediately after the current one, if any. 1810 // This is used to avoid emitting unnecessary branches to the next block. 1811 MachineBasicBlock *NextBlock = 0; 1812 MachineFunction::iterator BBI = SwitchBB; 1813 if (++BBI != FuncInfo.MF->end()) 1814 NextBlock = BBI; 1815 1816 if (NextMBB != NextBlock) 1817 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1818 DAG.getBasicBlock(NextMBB)); 1819 1820 DAG.setRoot(BrAnd); 1821} 1822 1823void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1824 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1825 1826 // Retrieve successors. 1827 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1828 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1829 1830 const Value *Callee(I.getCalledValue()); 1831 if (isa<InlineAsm>(Callee)) 1832 visitInlineAsm(&I); 1833 else 1834 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1835 1836 // If the value of the invoke is used outside of its defining block, make it 1837 // available as a virtual register. 1838 CopyToExportRegsIfNeeded(&I); 1839 1840 // Update successor info 1841 addSuccessorWithWeight(InvokeMBB, Return); 1842 addSuccessorWithWeight(InvokeMBB, LandingPad); 1843 1844 // Drop into normal successor. 1845 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1846 MVT::Other, getControlRoot(), 1847 DAG.getBasicBlock(Return))); 1848} 1849 1850void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1851 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1852} 1853 1854void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1855 assert(FuncInfo.MBB->isLandingPad() && 1856 "Call to landingpad not in landing pad!"); 1857 1858 MachineBasicBlock *MBB = FuncInfo.MBB; 1859 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1860 AddLandingPadInfo(LP, MMI, MBB); 1861 1862 // If there aren't registers to copy the values into (e.g., during SjLj 1863 // exceptions), then don't bother to create these DAG nodes. 1864 if (TLI.getExceptionPointerRegister() == 0 && 1865 TLI.getExceptionSelectorRegister() == 0) 1866 return; 1867 1868 SmallVector<EVT, 2> ValueVTs; 1869 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1870 1871 // Insert the EXCEPTIONADDR instruction. 1872 assert(FuncInfo.MBB->isLandingPad() && 1873 "Call to eh.exception not in landing pad!"); 1874 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1875 SDValue Ops[2]; 1876 Ops[0] = DAG.getRoot(); 1877 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1878 SDValue Chain = Op1.getValue(1); 1879 1880 // Insert the EHSELECTION instruction. 1881 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1882 Ops[0] = Op1; 1883 Ops[1] = Chain; 1884 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1885 Chain = Op2.getValue(1); 1886 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1887 1888 Ops[0] = Op1; 1889 Ops[1] = Op2; 1890 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1891 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1892 &Ops[0], 2); 1893 1894 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1895 setValue(&LP, RetPair.first); 1896 DAG.setRoot(RetPair.second); 1897} 1898 1899/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1900/// small case ranges). 1901bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1902 CaseRecVector& WorkList, 1903 const Value* SV, 1904 MachineBasicBlock *Default, 1905 MachineBasicBlock *SwitchBB) { 1906 // Size is the number of Cases represented by this range. 1907 size_t Size = CR.Range.second - CR.Range.first; 1908 if (Size > 3) 1909 return false; 1910 1911 // Get the MachineFunction which holds the current MBB. This is used when 1912 // inserting any additional MBBs necessary to represent the switch. 1913 MachineFunction *CurMF = FuncInfo.MF; 1914 1915 // Figure out which block is immediately after the current one. 1916 MachineBasicBlock *NextBlock = 0; 1917 MachineFunction::iterator BBI = CR.CaseBB; 1918 1919 if (++BBI != FuncInfo.MF->end()) 1920 NextBlock = BBI; 1921 1922 // If any two of the cases has the same destination, and if one value 1923 // is the same as the other, but has one bit unset that the other has set, 1924 // use bit manipulation to do two compares at once. For example: 1925 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1926 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1927 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1928 if (Size == 2 && CR.CaseBB == SwitchBB) { 1929 Case &Small = *CR.Range.first; 1930 Case &Big = *(CR.Range.second-1); 1931 1932 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1933 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1934 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1935 1936 // Check that there is only one bit different. 1937 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1938 (SmallValue | BigValue) == BigValue) { 1939 // Isolate the common bit. 1940 APInt CommonBit = BigValue & ~SmallValue; 1941 assert((SmallValue | CommonBit) == BigValue && 1942 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1943 1944 SDValue CondLHS = getValue(SV); 1945 EVT VT = CondLHS.getValueType(); 1946 DebugLoc DL = getCurDebugLoc(); 1947 1948 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1949 DAG.getConstant(CommonBit, VT)); 1950 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1951 Or, DAG.getConstant(BigValue, VT), 1952 ISD::SETEQ); 1953 1954 // Update successor info. 1955 addSuccessorWithWeight(SwitchBB, Small.BB); 1956 addSuccessorWithWeight(SwitchBB, Default); 1957 1958 // Insert the true branch. 1959 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1960 getControlRoot(), Cond, 1961 DAG.getBasicBlock(Small.BB)); 1962 1963 // Insert the false branch. 1964 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1965 DAG.getBasicBlock(Default)); 1966 1967 DAG.setRoot(BrCond); 1968 return true; 1969 } 1970 } 1971 } 1972 1973 // Order cases by weight so the most likely case will be checked first. 1974 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1975 if (BPI) { 1976 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) { 1977 uint32_t IWeight = BPI->getEdgeWeight(SwitchBB->getBasicBlock(), 1978 I->BB->getBasicBlock()); 1979 for (CaseItr J = CR.Range.first; J < I; ++J) { 1980 uint32_t JWeight = BPI->getEdgeWeight(SwitchBB->getBasicBlock(), 1981 J->BB->getBasicBlock()); 1982 if (IWeight > JWeight) 1983 std::swap(*I, *J); 1984 } 1985 } 1986 } 1987 // Rearrange the case blocks so that the last one falls through if possible. 1988 Case &BackCase = *(CR.Range.second-1); 1989 if (Size > 1 && 1990 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1991 // The last case block won't fall through into 'NextBlock' if we emit the 1992 // branches in this order. See if rearranging a case value would help. 1993 // We start at the bottom as it's the case with the least weight. 1994 for (CaseItr I = CR.Range.second-2, E = CR.Range.first; I >= E; --I) { 1995 if (I->BB == NextBlock) { 1996 std::swap(*I, BackCase); 1997 break; 1998 } 1999 } 2000 } 2001 2002 // Create a CaseBlock record representing a conditional branch to 2003 // the Case's target mbb if the value being switched on SV is equal 2004 // to C. 2005 MachineBasicBlock *CurBlock = CR.CaseBB; 2006 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2007 MachineBasicBlock *FallThrough; 2008 if (I != E-1) { 2009 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 2010 CurMF->insert(BBI, FallThrough); 2011 2012 // Put SV in a virtual register to make it available from the new blocks. 2013 ExportFromCurrentBlock(SV); 2014 } else { 2015 // If the last case doesn't match, go to the default block. 2016 FallThrough = Default; 2017 } 2018 2019 const Value *RHS, *LHS, *MHS; 2020 ISD::CondCode CC; 2021 if (I->High == I->Low) { 2022 // This is just small small case range :) containing exactly 1 case 2023 CC = ISD::SETEQ; 2024 LHS = SV; RHS = I->High; MHS = NULL; 2025 } else { 2026 CC = ISD::SETCC_INVALID; 2027 LHS = I->Low; MHS = SV; RHS = I->High; 2028 } 2029 2030 uint32_t ExtraWeight = I->ExtraWeight; 2031 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 2032 /* me */ CurBlock, 2033 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2); 2034 2035 // If emitting the first comparison, just call visitSwitchCase to emit the 2036 // code into the current block. Otherwise, push the CaseBlock onto the 2037 // vector to be later processed by SDISel, and insert the node's MBB 2038 // before the next MBB. 2039 if (CurBlock == SwitchBB) 2040 visitSwitchCase(CB, SwitchBB); 2041 else 2042 SwitchCases.push_back(CB); 2043 2044 CurBlock = FallThrough; 2045 } 2046 2047 return true; 2048} 2049 2050static inline bool areJTsAllowed(const TargetLowering &TLI) { 2051 return !TLI.getTargetMachine().Options.DisableJumpTables && 2052 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2053 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2054} 2055 2056static APInt ComputeRange(const APInt &First, const APInt &Last) { 2057 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2058 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth); 2059 return (LastExt - FirstExt + 1ULL); 2060} 2061 2062/// handleJTSwitchCase - Emit jumptable for current switch case range 2063bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2064 CaseRecVector &WorkList, 2065 const Value *SV, 2066 MachineBasicBlock *Default, 2067 MachineBasicBlock *SwitchBB) { 2068 Case& FrontCase = *CR.Range.first; 2069 Case& BackCase = *(CR.Range.second-1); 2070 2071 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2072 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2073 2074 APInt TSize(First.getBitWidth(), 0); 2075 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2076 TSize += I->size(); 2077 2078 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2079 return false; 2080 2081 APInt Range = ComputeRange(First, Last); 2082 // The density is TSize / Range. Require at least 40%. 2083 // It should not be possible for IntTSize to saturate for sane code, but make 2084 // sure we handle Range saturation correctly. 2085 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2086 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2087 if (IntTSize * 10 < IntRange * 4) 2088 return false; 2089 2090 DEBUG(dbgs() << "Lowering jump table\n" 2091 << "First entry: " << First << ". Last entry: " << Last << '\n' 2092 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2093 2094 // Get the MachineFunction which holds the current MBB. This is used when 2095 // inserting any additional MBBs necessary to represent the switch. 2096 MachineFunction *CurMF = FuncInfo.MF; 2097 2098 // Figure out which block is immediately after the current one. 2099 MachineFunction::iterator BBI = CR.CaseBB; 2100 ++BBI; 2101 2102 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2103 2104 // Create a new basic block to hold the code for loading the address 2105 // of the jump table, and jumping to it. Update successor information; 2106 // we will either branch to the default case for the switch, or the jump 2107 // table. 2108 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2109 CurMF->insert(BBI, JumpTableBB); 2110 2111 addSuccessorWithWeight(CR.CaseBB, Default); 2112 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2113 2114 // Build a vector of destination BBs, corresponding to each target 2115 // of the jump table. If the value of the jump table slot corresponds to 2116 // a case statement, push the case's BB onto the vector, otherwise, push 2117 // the default BB. 2118 std::vector<MachineBasicBlock*> DestBBs; 2119 APInt TEI = First; 2120 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2121 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2122 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2123 2124 if (Low.ule(TEI) && TEI.ule(High)) { 2125 DestBBs.push_back(I->BB); 2126 if (TEI==High) 2127 ++I; 2128 } else { 2129 DestBBs.push_back(Default); 2130 } 2131 } 2132 2133 // Update successor info. Add one edge to each unique successor. 2134 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2135 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2136 E = DestBBs.end(); I != E; ++I) { 2137 if (!SuccsHandled[(*I)->getNumber()]) { 2138 SuccsHandled[(*I)->getNumber()] = true; 2139 addSuccessorWithWeight(JumpTableBB, *I); 2140 } 2141 } 2142 2143 // Create a jump table index for this jump table. 2144 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2145 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2146 ->createJumpTableIndex(DestBBs); 2147 2148 // Set the jump table information so that we can codegen it as a second 2149 // MachineBasicBlock 2150 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2151 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2152 if (CR.CaseBB == SwitchBB) 2153 visitJumpTableHeader(JT, JTH, SwitchBB); 2154 2155 JTCases.push_back(JumpTableBlock(JTH, JT)); 2156 return true; 2157} 2158 2159/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2160/// 2 subtrees. 2161bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2162 CaseRecVector& WorkList, 2163 const Value* SV, 2164 MachineBasicBlock *Default, 2165 MachineBasicBlock *SwitchBB) { 2166 // Get the MachineFunction which holds the current MBB. This is used when 2167 // inserting any additional MBBs necessary to represent the switch. 2168 MachineFunction *CurMF = FuncInfo.MF; 2169 2170 // Figure out which block is immediately after the current one. 2171 MachineFunction::iterator BBI = CR.CaseBB; 2172 ++BBI; 2173 2174 Case& FrontCase = *CR.Range.first; 2175 Case& BackCase = *(CR.Range.second-1); 2176 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2177 2178 // Size is the number of Cases represented by this range. 2179 unsigned Size = CR.Range.second - CR.Range.first; 2180 2181 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2182 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2183 double FMetric = 0; 2184 CaseItr Pivot = CR.Range.first + Size/2; 2185 2186 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2187 // (heuristically) allow us to emit JumpTable's later. 2188 APInt TSize(First.getBitWidth(), 0); 2189 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2190 I!=E; ++I) 2191 TSize += I->size(); 2192 2193 APInt LSize = FrontCase.size(); 2194 APInt RSize = TSize-LSize; 2195 DEBUG(dbgs() << "Selecting best pivot: \n" 2196 << "First: " << First << ", Last: " << Last <<'\n' 2197 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2198 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2199 J!=E; ++I, ++J) { 2200 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2201 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2202 APInt Range = ComputeRange(LEnd, RBegin); 2203 assert((Range - 2ULL).isNonNegative() && 2204 "Invalid case distance"); 2205 // Use volatile double here to avoid excess precision issues on some hosts, 2206 // e.g. that use 80-bit X87 registers. 2207 volatile double LDensity = 2208 (double)LSize.roundToDouble() / 2209 (LEnd - First + 1ULL).roundToDouble(); 2210 volatile double RDensity = 2211 (double)RSize.roundToDouble() / 2212 (Last - RBegin + 1ULL).roundToDouble(); 2213 double Metric = Range.logBase2()*(LDensity+RDensity); 2214 // Should always split in some non-trivial place 2215 DEBUG(dbgs() <<"=>Step\n" 2216 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2217 << "LDensity: " << LDensity 2218 << ", RDensity: " << RDensity << '\n' 2219 << "Metric: " << Metric << '\n'); 2220 if (FMetric < Metric) { 2221 Pivot = J; 2222 FMetric = Metric; 2223 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2224 } 2225 2226 LSize += J->size(); 2227 RSize -= J->size(); 2228 } 2229 if (areJTsAllowed(TLI)) { 2230 // If our case is dense we *really* should handle it earlier! 2231 assert((FMetric > 0) && "Should handle dense range earlier!"); 2232 } else { 2233 Pivot = CR.Range.first + Size/2; 2234 } 2235 2236 CaseRange LHSR(CR.Range.first, Pivot); 2237 CaseRange RHSR(Pivot, CR.Range.second); 2238 const Constant *C = Pivot->Low; 2239 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2240 2241 // We know that we branch to the LHS if the Value being switched on is 2242 // less than the Pivot value, C. We use this to optimize our binary 2243 // tree a bit, by recognizing that if SV is greater than or equal to the 2244 // LHS's Case Value, and that Case Value is exactly one less than the 2245 // Pivot's Value, then we can branch directly to the LHS's Target, 2246 // rather than creating a leaf node for it. 2247 if ((LHSR.second - LHSR.first) == 1 && 2248 LHSR.first->High == CR.GE && 2249 cast<ConstantInt>(C)->getValue() == 2250 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2251 TrueBB = LHSR.first->BB; 2252 } else { 2253 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2254 CurMF->insert(BBI, TrueBB); 2255 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2256 2257 // Put SV in a virtual register to make it available from the new blocks. 2258 ExportFromCurrentBlock(SV); 2259 } 2260 2261 // Similar to the optimization above, if the Value being switched on is 2262 // known to be less than the Constant CR.LT, and the current Case Value 2263 // is CR.LT - 1, then we can branch directly to the target block for 2264 // the current Case Value, rather than emitting a RHS leaf node for it. 2265 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2266 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2267 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2268 FalseBB = RHSR.first->BB; 2269 } else { 2270 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2271 CurMF->insert(BBI, FalseBB); 2272 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2273 2274 // Put SV in a virtual register to make it available from the new blocks. 2275 ExportFromCurrentBlock(SV); 2276 } 2277 2278 // Create a CaseBlock record representing a conditional branch to 2279 // the LHS node if the value being switched on SV is less than C. 2280 // Otherwise, branch to LHS. 2281 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2282 2283 if (CR.CaseBB == SwitchBB) 2284 visitSwitchCase(CB, SwitchBB); 2285 else 2286 SwitchCases.push_back(CB); 2287 2288 return true; 2289} 2290 2291/// handleBitTestsSwitchCase - if current case range has few destination and 2292/// range span less, than machine word bitwidth, encode case range into series 2293/// of masks and emit bit tests with these masks. 2294bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2295 CaseRecVector& WorkList, 2296 const Value* SV, 2297 MachineBasicBlock* Default, 2298 MachineBasicBlock *SwitchBB){ 2299 EVT PTy = TLI.getPointerTy(); 2300 unsigned IntPtrBits = PTy.getSizeInBits(); 2301 2302 Case& FrontCase = *CR.Range.first; 2303 Case& BackCase = *(CR.Range.second-1); 2304 2305 // Get the MachineFunction which holds the current MBB. This is used when 2306 // inserting any additional MBBs necessary to represent the switch. 2307 MachineFunction *CurMF = FuncInfo.MF; 2308 2309 // If target does not have legal shift left, do not emit bit tests at all. 2310 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2311 return false; 2312 2313 size_t numCmps = 0; 2314 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2315 I!=E; ++I) { 2316 // Single case counts one, case range - two. 2317 numCmps += (I->Low == I->High ? 1 : 2); 2318 } 2319 2320 // Count unique destinations 2321 SmallSet<MachineBasicBlock*, 4> Dests; 2322 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2323 Dests.insert(I->BB); 2324 if (Dests.size() > 3) 2325 // Don't bother the code below, if there are too much unique destinations 2326 return false; 2327 } 2328 DEBUG(dbgs() << "Total number of unique destinations: " 2329 << Dests.size() << '\n' 2330 << "Total number of comparisons: " << numCmps << '\n'); 2331 2332 // Compute span of values. 2333 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2334 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2335 APInt cmpRange = maxValue - minValue; 2336 2337 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2338 << "Low bound: " << minValue << '\n' 2339 << "High bound: " << maxValue << '\n'); 2340 2341 if (cmpRange.uge(IntPtrBits) || 2342 (!(Dests.size() == 1 && numCmps >= 3) && 2343 !(Dests.size() == 2 && numCmps >= 5) && 2344 !(Dests.size() >= 3 && numCmps >= 6))) 2345 return false; 2346 2347 DEBUG(dbgs() << "Emitting bit tests\n"); 2348 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2349 2350 // Optimize the case where all the case values fit in a 2351 // word without having to subtract minValue. In this case, 2352 // we can optimize away the subtraction. 2353 if (maxValue.ult(IntPtrBits)) { 2354 cmpRange = maxValue; 2355 } else { 2356 lowBound = minValue; 2357 } 2358 2359 CaseBitsVector CasesBits; 2360 unsigned i, count = 0; 2361 2362 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2363 MachineBasicBlock* Dest = I->BB; 2364 for (i = 0; i < count; ++i) 2365 if (Dest == CasesBits[i].BB) 2366 break; 2367 2368 if (i == count) { 2369 assert((count < 3) && "Too much destinations to test!"); 2370 CasesBits.push_back(CaseBits(0, Dest, 0)); 2371 count++; 2372 } 2373 2374 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2375 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2376 2377 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2378 uint64_t hi = (highValue - lowBound).getZExtValue(); 2379 2380 for (uint64_t j = lo; j <= hi; j++) { 2381 CasesBits[i].Mask |= 1ULL << j; 2382 CasesBits[i].Bits++; 2383 } 2384 2385 } 2386 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2387 2388 BitTestInfo BTC; 2389 2390 // Figure out which block is immediately after the current one. 2391 MachineFunction::iterator BBI = CR.CaseBB; 2392 ++BBI; 2393 2394 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2395 2396 DEBUG(dbgs() << "Cases:\n"); 2397 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2398 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2399 << ", Bits: " << CasesBits[i].Bits 2400 << ", BB: " << CasesBits[i].BB << '\n'); 2401 2402 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2403 CurMF->insert(BBI, CaseBB); 2404 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2405 CaseBB, 2406 CasesBits[i].BB)); 2407 2408 // Put SV in a virtual register to make it available from the new blocks. 2409 ExportFromCurrentBlock(SV); 2410 } 2411 2412 BitTestBlock BTB(lowBound, cmpRange, SV, 2413 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2414 CR.CaseBB, Default, BTC); 2415 2416 if (CR.CaseBB == SwitchBB) 2417 visitBitTestHeader(BTB, SwitchBB); 2418 2419 BitTestCases.push_back(BTB); 2420 2421 return true; 2422} 2423 2424/// Clusterify - Transform simple list of Cases into list of CaseRange's 2425size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2426 const SwitchInst& SI) { 2427 2428 /// Use a shorter form of declaration, and also 2429 /// show the we want to use CRSBuilder as Clusterifier. 2430 typedef CRSBuilderBase<MachineBasicBlock, true> Clusterifier; 2431 2432 Clusterifier TheClusterifier; 2433 2434 // Start with "simple" cases 2435 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end(); 2436 i != e; ++i) { 2437 const BasicBlock *SuccBB = i.getCaseSuccessor(); 2438 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2439 2440 TheClusterifier.add(i.getCaseValueEx(), SMBB); 2441 } 2442 2443 TheClusterifier.optimize(); 2444 2445 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2446 size_t numCmps = 0; 2447 for (Clusterifier::RangeIterator i = TheClusterifier.begin(), 2448 e = TheClusterifier.end(); i != e; ++i, ++numCmps) { 2449 Clusterifier::Cluster &C = *i; 2450 unsigned W = 0; 2451 if (BPI) { 2452 W = BPI->getEdgeWeight(SI.getParent(), C.second->getBasicBlock()); 2453 if (!W) 2454 W = 16; 2455 W *= C.first.Weight; 2456 BPI->setEdgeWeight(SI.getParent(), C.second->getBasicBlock(), W); 2457 } 2458 2459 Cases.push_back(Case(C.first.Low, C.first.High, C.second, W)); 2460 2461 if (C.first.Low != C.first.High) 2462 // A range counts double, since it requires two compares. 2463 ++numCmps; 2464 } 2465 2466 return numCmps; 2467} 2468 2469void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2470 MachineBasicBlock *Last) { 2471 // Update JTCases. 2472 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2473 if (JTCases[i].first.HeaderBB == First) 2474 JTCases[i].first.HeaderBB = Last; 2475 2476 // Update BitTestCases. 2477 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2478 if (BitTestCases[i].Parent == First) 2479 BitTestCases[i].Parent = Last; 2480} 2481 2482void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2483 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2484 2485 // Figure out which block is immediately after the current one. 2486 MachineBasicBlock *NextBlock = 0; 2487 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2488 2489 // If there is only the default destination, branch to it if it is not the 2490 // next basic block. Otherwise, just fall through. 2491 if (!SI.getNumCases()) { 2492 // Update machine-CFG edges. 2493 2494 // If this is not a fall-through branch, emit the branch. 2495 SwitchMBB->addSuccessor(Default); 2496 if (Default != NextBlock) 2497 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2498 MVT::Other, getControlRoot(), 2499 DAG.getBasicBlock(Default))); 2500 2501 return; 2502 } 2503 2504 // If there are any non-default case statements, create a vector of Cases 2505 // representing each one, and sort the vector so that we can efficiently 2506 // create a binary search tree from them. 2507 CaseVector Cases; 2508 size_t numCmps = Clusterify(Cases, SI); 2509 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2510 << ". Total compares: " << numCmps << '\n'); 2511 (void)numCmps; 2512 2513 // Get the Value to be switched on and default basic blocks, which will be 2514 // inserted into CaseBlock records, representing basic blocks in the binary 2515 // search tree. 2516 const Value *SV = SI.getCondition(); 2517 2518 // Push the initial CaseRec onto the worklist 2519 CaseRecVector WorkList; 2520 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2521 CaseRange(Cases.begin(),Cases.end()))); 2522 2523 while (!WorkList.empty()) { 2524 // Grab a record representing a case range to process off the worklist 2525 CaseRec CR = WorkList.back(); 2526 WorkList.pop_back(); 2527 2528 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2529 continue; 2530 2531 // If the range has few cases (two or less) emit a series of specific 2532 // tests. 2533 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2534 continue; 2535 2536 // If the switch has more than 5 blocks, and at least 40% dense, and the 2537 // target supports indirect branches, then emit a jump table rather than 2538 // lowering the switch to a binary tree of conditional branches. 2539 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2540 continue; 2541 2542 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2543 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2544 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2545 } 2546} 2547 2548void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2549 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2550 2551 // Update machine-CFG edges with unique successors. 2552 SmallVector<BasicBlock*, 32> succs; 2553 succs.reserve(I.getNumSuccessors()); 2554 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2555 succs.push_back(I.getSuccessor(i)); 2556 array_pod_sort(succs.begin(), succs.end()); 2557 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2558 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2559 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2560 addSuccessorWithWeight(IndirectBrMBB, Succ); 2561 } 2562 2563 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2564 MVT::Other, getControlRoot(), 2565 getValue(I.getAddress()))); 2566} 2567 2568void SelectionDAGBuilder::visitFSub(const User &I) { 2569 // -0.0 - X --> fneg 2570 Type *Ty = I.getType(); 2571 if (isa<Constant>(I.getOperand(0)) && 2572 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2573 SDValue Op2 = getValue(I.getOperand(1)); 2574 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2575 Op2.getValueType(), Op2)); 2576 return; 2577 } 2578 2579 visitBinary(I, ISD::FSUB); 2580} 2581 2582void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2583 SDValue Op1 = getValue(I.getOperand(0)); 2584 SDValue Op2 = getValue(I.getOperand(1)); 2585 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2586 Op1.getValueType(), Op1, Op2)); 2587} 2588 2589void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2590 SDValue Op1 = getValue(I.getOperand(0)); 2591 SDValue Op2 = getValue(I.getOperand(1)); 2592 2593 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2594 2595 // Coerce the shift amount to the right type if we can. 2596 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2597 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2598 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2599 DebugLoc DL = getCurDebugLoc(); 2600 2601 // If the operand is smaller than the shift count type, promote it. 2602 if (ShiftSize > Op2Size) 2603 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2604 2605 // If the operand is larger than the shift count type but the shift 2606 // count type has enough bits to represent any shift value, truncate 2607 // it now. This is a common case and it exposes the truncate to 2608 // optimization early. 2609 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2610 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2611 // Otherwise we'll need to temporarily settle for some other convenient 2612 // type. Type legalization will make adjustments once the shiftee is split. 2613 else 2614 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2615 } 2616 2617 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2618 Op1.getValueType(), Op1, Op2)); 2619} 2620 2621void SelectionDAGBuilder::visitSDiv(const User &I) { 2622 SDValue Op1 = getValue(I.getOperand(0)); 2623 SDValue Op2 = getValue(I.getOperand(1)); 2624 2625 // Turn exact SDivs into multiplications. 2626 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2627 // exact bit. 2628 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2629 !isa<ConstantSDNode>(Op1) && 2630 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2631 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2632 else 2633 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2634 Op1, Op2)); 2635} 2636 2637void SelectionDAGBuilder::visitICmp(const User &I) { 2638 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2639 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2640 predicate = IC->getPredicate(); 2641 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2642 predicate = ICmpInst::Predicate(IC->getPredicate()); 2643 SDValue Op1 = getValue(I.getOperand(0)); 2644 SDValue Op2 = getValue(I.getOperand(1)); 2645 ISD::CondCode Opcode = getICmpCondCode(predicate); 2646 2647 EVT DestVT = TLI.getValueType(I.getType()); 2648 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2649} 2650 2651void SelectionDAGBuilder::visitFCmp(const User &I) { 2652 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2653 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2654 predicate = FC->getPredicate(); 2655 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2656 predicate = FCmpInst::Predicate(FC->getPredicate()); 2657 SDValue Op1 = getValue(I.getOperand(0)); 2658 SDValue Op2 = getValue(I.getOperand(1)); 2659 ISD::CondCode Condition = getFCmpCondCode(predicate); 2660 if (TM.Options.NoNaNsFPMath) 2661 Condition = getFCmpCodeWithoutNaN(Condition); 2662 EVT DestVT = TLI.getValueType(I.getType()); 2663 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2664} 2665 2666void SelectionDAGBuilder::visitSelect(const User &I) { 2667 SmallVector<EVT, 4> ValueVTs; 2668 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2669 unsigned NumValues = ValueVTs.size(); 2670 if (NumValues == 0) return; 2671 2672 SmallVector<SDValue, 4> Values(NumValues); 2673 SDValue Cond = getValue(I.getOperand(0)); 2674 SDValue TrueVal = getValue(I.getOperand(1)); 2675 SDValue FalseVal = getValue(I.getOperand(2)); 2676 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2677 ISD::VSELECT : ISD::SELECT; 2678 2679 for (unsigned i = 0; i != NumValues; ++i) 2680 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2681 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2682 Cond, 2683 SDValue(TrueVal.getNode(), 2684 TrueVal.getResNo() + i), 2685 SDValue(FalseVal.getNode(), 2686 FalseVal.getResNo() + i)); 2687 2688 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2689 DAG.getVTList(&ValueVTs[0], NumValues), 2690 &Values[0], NumValues)); 2691} 2692 2693void SelectionDAGBuilder::visitTrunc(const User &I) { 2694 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2695 SDValue N = getValue(I.getOperand(0)); 2696 EVT DestVT = TLI.getValueType(I.getType()); 2697 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2698} 2699 2700void SelectionDAGBuilder::visitZExt(const User &I) { 2701 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2702 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2703 SDValue N = getValue(I.getOperand(0)); 2704 EVT DestVT = TLI.getValueType(I.getType()); 2705 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2706} 2707 2708void SelectionDAGBuilder::visitSExt(const User &I) { 2709 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2710 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2711 SDValue N = getValue(I.getOperand(0)); 2712 EVT DestVT = TLI.getValueType(I.getType()); 2713 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2714} 2715 2716void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2717 // FPTrunc is never a no-op cast, no need to check 2718 SDValue N = getValue(I.getOperand(0)); 2719 EVT DestVT = TLI.getValueType(I.getType()); 2720 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2721 DestVT, N, 2722 DAG.getTargetConstant(0, TLI.getPointerTy()))); 2723} 2724 2725void SelectionDAGBuilder::visitFPExt(const User &I){ 2726 // FPExt is never a no-op cast, no need to check 2727 SDValue N = getValue(I.getOperand(0)); 2728 EVT DestVT = TLI.getValueType(I.getType()); 2729 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2730} 2731 2732void SelectionDAGBuilder::visitFPToUI(const User &I) { 2733 // FPToUI is never a no-op cast, no need to check 2734 SDValue N = getValue(I.getOperand(0)); 2735 EVT DestVT = TLI.getValueType(I.getType()); 2736 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2737} 2738 2739void SelectionDAGBuilder::visitFPToSI(const User &I) { 2740 // FPToSI is never a no-op cast, no need to check 2741 SDValue N = getValue(I.getOperand(0)); 2742 EVT DestVT = TLI.getValueType(I.getType()); 2743 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2744} 2745 2746void SelectionDAGBuilder::visitUIToFP(const User &I) { 2747 // UIToFP is never a no-op cast, no need to check 2748 SDValue N = getValue(I.getOperand(0)); 2749 EVT DestVT = TLI.getValueType(I.getType()); 2750 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2751} 2752 2753void SelectionDAGBuilder::visitSIToFP(const User &I){ 2754 // SIToFP is never a no-op cast, no need to check 2755 SDValue N = getValue(I.getOperand(0)); 2756 EVT DestVT = TLI.getValueType(I.getType()); 2757 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2758} 2759 2760void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2761 // What to do depends on the size of the integer and the size of the pointer. 2762 // We can either truncate, zero extend, or no-op, accordingly. 2763 SDValue N = getValue(I.getOperand(0)); 2764 EVT DestVT = TLI.getValueType(I.getType()); 2765 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2766} 2767 2768void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2769 // What to do depends on the size of the integer and the size of the pointer. 2770 // We can either truncate, zero extend, or no-op, accordingly. 2771 SDValue N = getValue(I.getOperand(0)); 2772 EVT DestVT = TLI.getValueType(I.getType()); 2773 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2774} 2775 2776void SelectionDAGBuilder::visitBitCast(const User &I) { 2777 SDValue N = getValue(I.getOperand(0)); 2778 EVT DestVT = TLI.getValueType(I.getType()); 2779 2780 // BitCast assures us that source and destination are the same size so this is 2781 // either a BITCAST or a no-op. 2782 if (DestVT != N.getValueType()) 2783 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2784 DestVT, N)); // convert types. 2785 else 2786 setValue(&I, N); // noop cast. 2787} 2788 2789void SelectionDAGBuilder::visitInsertElement(const User &I) { 2790 SDValue InVec = getValue(I.getOperand(0)); 2791 SDValue InVal = getValue(I.getOperand(1)); 2792 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2793 TLI.getPointerTy(), 2794 getValue(I.getOperand(2))); 2795 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2796 TLI.getValueType(I.getType()), 2797 InVec, InVal, InIdx)); 2798} 2799 2800void SelectionDAGBuilder::visitExtractElement(const User &I) { 2801 SDValue InVec = getValue(I.getOperand(0)); 2802 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2803 TLI.getPointerTy(), 2804 getValue(I.getOperand(1))); 2805 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2806 TLI.getValueType(I.getType()), InVec, InIdx)); 2807} 2808 2809// Utility for visitShuffleVector - Return true if every element in Mask, 2810// begining from position Pos and ending in Pos+Size, falls within the 2811// specified sequential range [L, L+Pos). or is undef. 2812static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2813 unsigned Pos, unsigned Size, int Low) { 2814 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2815 if (Mask[i] >= 0 && Mask[i] != Low) 2816 return false; 2817 return true; 2818} 2819 2820void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2821 SDValue Src1 = getValue(I.getOperand(0)); 2822 SDValue Src2 = getValue(I.getOperand(1)); 2823 2824 SmallVector<int, 8> Mask; 2825 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); 2826 unsigned MaskNumElts = Mask.size(); 2827 2828 EVT VT = TLI.getValueType(I.getType()); 2829 EVT SrcVT = Src1.getValueType(); 2830 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2831 2832 if (SrcNumElts == MaskNumElts) { 2833 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2834 &Mask[0])); 2835 return; 2836 } 2837 2838 // Normalize the shuffle vector since mask and vector length don't match. 2839 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2840 // Mask is longer than the source vectors and is a multiple of the source 2841 // vectors. We can use concatenate vector to make the mask and vectors 2842 // lengths match. 2843 if (SrcNumElts*2 == MaskNumElts) { 2844 // First check for Src1 in low and Src2 in high 2845 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 2846 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 2847 // The shuffle is concatenating two vectors together. 2848 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2849 VT, Src1, Src2)); 2850 return; 2851 } 2852 // Then check for Src2 in low and Src1 in high 2853 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 2854 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 2855 // The shuffle is concatenating two vectors together. 2856 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2857 VT, Src2, Src1)); 2858 return; 2859 } 2860 } 2861 2862 // Pad both vectors with undefs to make them the same length as the mask. 2863 unsigned NumConcat = MaskNumElts / SrcNumElts; 2864 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2865 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2866 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2867 2868 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2869 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2870 MOps1[0] = Src1; 2871 MOps2[0] = Src2; 2872 2873 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2874 getCurDebugLoc(), VT, 2875 &MOps1[0], NumConcat); 2876 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2877 getCurDebugLoc(), VT, 2878 &MOps2[0], NumConcat); 2879 2880 // Readjust mask for new input vector length. 2881 SmallVector<int, 8> MappedOps; 2882 for (unsigned i = 0; i != MaskNumElts; ++i) { 2883 int Idx = Mask[i]; 2884 if (Idx >= (int)SrcNumElts) 2885 Idx -= SrcNumElts - MaskNumElts; 2886 MappedOps.push_back(Idx); 2887 } 2888 2889 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2890 &MappedOps[0])); 2891 return; 2892 } 2893 2894 if (SrcNumElts > MaskNumElts) { 2895 // Analyze the access pattern of the vector to see if we can extract 2896 // two subvectors and do the shuffle. The analysis is done by calculating 2897 // the range of elements the mask access on both vectors. 2898 int MinRange[2] = { static_cast<int>(SrcNumElts), 2899 static_cast<int>(SrcNumElts)}; 2900 int MaxRange[2] = {-1, -1}; 2901 2902 for (unsigned i = 0; i != MaskNumElts; ++i) { 2903 int Idx = Mask[i]; 2904 unsigned Input = 0; 2905 if (Idx < 0) 2906 continue; 2907 2908 if (Idx >= (int)SrcNumElts) { 2909 Input = 1; 2910 Idx -= SrcNumElts; 2911 } 2912 if (Idx > MaxRange[Input]) 2913 MaxRange[Input] = Idx; 2914 if (Idx < MinRange[Input]) 2915 MinRange[Input] = Idx; 2916 } 2917 2918 // Check if the access is smaller than the vector size and can we find 2919 // a reasonable extract index. 2920 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not 2921 // Extract. 2922 int StartIdx[2]; // StartIdx to extract from 2923 for (unsigned Input = 0; Input < 2; ++Input) { 2924 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) { 2925 RangeUse[Input] = 0; // Unused 2926 StartIdx[Input] = 0; 2927 continue; 2928 } 2929 2930 // Find a good start index that is a multiple of the mask length. Then 2931 // see if the rest of the elements are in range. 2932 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2933 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2934 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2935 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2936 } 2937 2938 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2939 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2940 return; 2941 } 2942 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) { 2943 // Extract appropriate subvector and generate a vector shuffle 2944 for (unsigned Input = 0; Input < 2; ++Input) { 2945 SDValue &Src = Input == 0 ? Src1 : Src2; 2946 if (RangeUse[Input] == 0) 2947 Src = DAG.getUNDEF(VT); 2948 else 2949 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2950 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2951 } 2952 2953 // Calculate new mask. 2954 SmallVector<int, 8> MappedOps; 2955 for (unsigned i = 0; i != MaskNumElts; ++i) { 2956 int Idx = Mask[i]; 2957 if (Idx >= 0) { 2958 if (Idx < (int)SrcNumElts) 2959 Idx -= StartIdx[0]; 2960 else 2961 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; 2962 } 2963 MappedOps.push_back(Idx); 2964 } 2965 2966 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2967 &MappedOps[0])); 2968 return; 2969 } 2970 } 2971 2972 // We can't use either concat vectors or extract subvectors so fall back to 2973 // replacing the shuffle with extract and build vector. 2974 // to insert and build vector. 2975 EVT EltVT = VT.getVectorElementType(); 2976 EVT PtrVT = TLI.getPointerTy(); 2977 SmallVector<SDValue,8> Ops; 2978 for (unsigned i = 0; i != MaskNumElts; ++i) { 2979 int Idx = Mask[i]; 2980 SDValue Res; 2981 2982 if (Idx < 0) { 2983 Res = DAG.getUNDEF(EltVT); 2984 } else { 2985 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; 2986 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; 2987 2988 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2989 EltVT, Src, DAG.getConstant(Idx, PtrVT)); 2990 } 2991 2992 Ops.push_back(Res); 2993 } 2994 2995 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2996 VT, &Ops[0], Ops.size())); 2997} 2998 2999void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 3000 const Value *Op0 = I.getOperand(0); 3001 const Value *Op1 = I.getOperand(1); 3002 Type *AggTy = I.getType(); 3003 Type *ValTy = Op1->getType(); 3004 bool IntoUndef = isa<UndefValue>(Op0); 3005 bool FromUndef = isa<UndefValue>(Op1); 3006 3007 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3008 3009 SmallVector<EVT, 4> AggValueVTs; 3010 ComputeValueVTs(TLI, AggTy, AggValueVTs); 3011 SmallVector<EVT, 4> ValValueVTs; 3012 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3013 3014 unsigned NumAggValues = AggValueVTs.size(); 3015 unsigned NumValValues = ValValueVTs.size(); 3016 SmallVector<SDValue, 4> Values(NumAggValues); 3017 3018 SDValue Agg = getValue(Op0); 3019 unsigned i = 0; 3020 // Copy the beginning value(s) from the original aggregate. 3021 for (; i != LinearIndex; ++i) 3022 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3023 SDValue(Agg.getNode(), Agg.getResNo() + i); 3024 // Copy values from the inserted value(s). 3025 if (NumValValues) { 3026 SDValue Val = getValue(Op1); 3027 for (; i != LinearIndex + NumValValues; ++i) 3028 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3029 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3030 } 3031 // Copy remaining value(s) from the original aggregate. 3032 for (; i != NumAggValues; ++i) 3033 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3034 SDValue(Agg.getNode(), Agg.getResNo() + i); 3035 3036 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3037 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3038 &Values[0], NumAggValues)); 3039} 3040 3041void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3042 const Value *Op0 = I.getOperand(0); 3043 Type *AggTy = Op0->getType(); 3044 Type *ValTy = I.getType(); 3045 bool OutOfUndef = isa<UndefValue>(Op0); 3046 3047 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3048 3049 SmallVector<EVT, 4> ValValueVTs; 3050 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3051 3052 unsigned NumValValues = ValValueVTs.size(); 3053 3054 // Ignore a extractvalue that produces an empty object 3055 if (!NumValValues) { 3056 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3057 return; 3058 } 3059 3060 SmallVector<SDValue, 4> Values(NumValValues); 3061 3062 SDValue Agg = getValue(Op0); 3063 // Copy out the selected value(s). 3064 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3065 Values[i - LinearIndex] = 3066 OutOfUndef ? 3067 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3068 SDValue(Agg.getNode(), Agg.getResNo() + i); 3069 3070 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3071 DAG.getVTList(&ValValueVTs[0], NumValValues), 3072 &Values[0], NumValValues)); 3073} 3074 3075void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3076 SDValue N = getValue(I.getOperand(0)); 3077 // Note that the pointer operand may be a vector of pointers. Take the scalar 3078 // element which holds a pointer. 3079 Type *Ty = I.getOperand(0)->getType()->getScalarType(); 3080 3081 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3082 OI != E; ++OI) { 3083 const Value *Idx = *OI; 3084 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3085 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3086 if (Field) { 3087 // N = N + Offset 3088 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3089 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3090 DAG.getIntPtrConstant(Offset)); 3091 } 3092 3093 Ty = StTy->getElementType(Field); 3094 } else { 3095 Ty = cast<SequentialType>(Ty)->getElementType(); 3096 3097 // If this is a constant subscript, handle it quickly. 3098 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3099 if (CI->isZero()) continue; 3100 uint64_t Offs = 3101 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3102 SDValue OffsVal; 3103 EVT PTy = TLI.getPointerTy(); 3104 unsigned PtrBits = PTy.getSizeInBits(); 3105 if (PtrBits < 64) 3106 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3107 TLI.getPointerTy(), 3108 DAG.getConstant(Offs, MVT::i64)); 3109 else 3110 OffsVal = DAG.getIntPtrConstant(Offs); 3111 3112 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3113 OffsVal); 3114 continue; 3115 } 3116 3117 // N = N + Idx * ElementSize; 3118 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3119 TD->getTypeAllocSize(Ty)); 3120 SDValue IdxN = getValue(Idx); 3121 3122 // If the index is smaller or larger than intptr_t, truncate or extend 3123 // it. 3124 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3125 3126 // If this is a multiply by a power of two, turn it into a shl 3127 // immediately. This is a very common case. 3128 if (ElementSize != 1) { 3129 if (ElementSize.isPowerOf2()) { 3130 unsigned Amt = ElementSize.logBase2(); 3131 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3132 N.getValueType(), IdxN, 3133 DAG.getConstant(Amt, IdxN.getValueType())); 3134 } else { 3135 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3136 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3137 N.getValueType(), IdxN, Scale); 3138 } 3139 } 3140 3141 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3142 N.getValueType(), N, IdxN); 3143 } 3144 } 3145 3146 setValue(&I, N); 3147} 3148 3149void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3150 // If this is a fixed sized alloca in the entry block of the function, 3151 // allocate it statically on the stack. 3152 if (FuncInfo.StaticAllocaMap.count(&I)) 3153 return; // getValue will auto-populate this. 3154 3155 Type *Ty = I.getAllocatedType(); 3156 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3157 unsigned Align = 3158 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3159 I.getAlignment()); 3160 3161 SDValue AllocSize = getValue(I.getArraySize()); 3162 3163 EVT IntPtr = TLI.getPointerTy(); 3164 if (AllocSize.getValueType() != IntPtr) 3165 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3166 3167 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3168 AllocSize, 3169 DAG.getConstant(TySize, IntPtr)); 3170 3171 // Handle alignment. If the requested alignment is less than or equal to 3172 // the stack alignment, ignore it. If the size is greater than or equal to 3173 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3174 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3175 if (Align <= StackAlign) 3176 Align = 0; 3177 3178 // Round the size of the allocation up to the stack alignment size 3179 // by add SA-1 to the size. 3180 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3181 AllocSize.getValueType(), AllocSize, 3182 DAG.getIntPtrConstant(StackAlign-1)); 3183 3184 // Mask out the low bits for alignment purposes. 3185 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3186 AllocSize.getValueType(), AllocSize, 3187 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3188 3189 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3190 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3191 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3192 VTs, Ops, 3); 3193 setValue(&I, DSA); 3194 DAG.setRoot(DSA.getValue(1)); 3195 3196 // Inform the Frame Information that we have just allocated a variable-sized 3197 // object. 3198 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3199} 3200 3201void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3202 if (I.isAtomic()) 3203 return visitAtomicLoad(I); 3204 3205 const Value *SV = I.getOperand(0); 3206 SDValue Ptr = getValue(SV); 3207 3208 Type *Ty = I.getType(); 3209 3210 bool isVolatile = I.isVolatile(); 3211 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3212 bool isInvariant = I.getMetadata("invariant.load") != 0; 3213 unsigned Alignment = I.getAlignment(); 3214 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3215 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 3216 3217 SmallVector<EVT, 4> ValueVTs; 3218 SmallVector<uint64_t, 4> Offsets; 3219 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3220 unsigned NumValues = ValueVTs.size(); 3221 if (NumValues == 0) 3222 return; 3223 3224 SDValue Root; 3225 bool ConstantMemory = false; 3226 if (I.isVolatile() || NumValues > MaxParallelChains) 3227 // Serialize volatile loads with other side effects. 3228 Root = getRoot(); 3229 else if (AA->pointsToConstantMemory( 3230 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3231 // Do not serialize (non-volatile) loads of constant memory with anything. 3232 Root = DAG.getEntryNode(); 3233 ConstantMemory = true; 3234 } else { 3235 // Do not serialize non-volatile loads against each other. 3236 Root = DAG.getRoot(); 3237 } 3238 3239 SmallVector<SDValue, 4> Values(NumValues); 3240 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3241 NumValues)); 3242 EVT PtrVT = Ptr.getValueType(); 3243 unsigned ChainI = 0; 3244 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3245 // Serializing loads here may result in excessive register pressure, and 3246 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3247 // could recover a bit by hoisting nodes upward in the chain by recognizing 3248 // they are side-effect free or do not alias. The optimizer should really 3249 // avoid this case by converting large object/array copies to llvm.memcpy 3250 // (MaxParallelChains should always remain as failsafe). 3251 if (ChainI == MaxParallelChains) { 3252 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3253 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3254 MVT::Other, &Chains[0], ChainI); 3255 Root = Chain; 3256 ChainI = 0; 3257 } 3258 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3259 PtrVT, Ptr, 3260 DAG.getConstant(Offsets[i], PtrVT)); 3261 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3262 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3263 isNonTemporal, isInvariant, Alignment, TBAAInfo, 3264 Ranges); 3265 3266 Values[i] = L; 3267 Chains[ChainI] = L.getValue(1); 3268 } 3269 3270 if (!ConstantMemory) { 3271 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3272 MVT::Other, &Chains[0], ChainI); 3273 if (isVolatile) 3274 DAG.setRoot(Chain); 3275 else 3276 PendingLoads.push_back(Chain); 3277 } 3278 3279 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3280 DAG.getVTList(&ValueVTs[0], NumValues), 3281 &Values[0], NumValues)); 3282} 3283 3284void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3285 if (I.isAtomic()) 3286 return visitAtomicStore(I); 3287 3288 const Value *SrcV = I.getOperand(0); 3289 const Value *PtrV = I.getOperand(1); 3290 3291 SmallVector<EVT, 4> ValueVTs; 3292 SmallVector<uint64_t, 4> Offsets; 3293 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3294 unsigned NumValues = ValueVTs.size(); 3295 if (NumValues == 0) 3296 return; 3297 3298 // Get the lowered operands. Note that we do this after 3299 // checking if NumResults is zero, because with zero results 3300 // the operands won't have values in the map. 3301 SDValue Src = getValue(SrcV); 3302 SDValue Ptr = getValue(PtrV); 3303 3304 SDValue Root = getRoot(); 3305 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3306 NumValues)); 3307 EVT PtrVT = Ptr.getValueType(); 3308 bool isVolatile = I.isVolatile(); 3309 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3310 unsigned Alignment = I.getAlignment(); 3311 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3312 3313 unsigned ChainI = 0; 3314 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3315 // See visitLoad comments. 3316 if (ChainI == MaxParallelChains) { 3317 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3318 MVT::Other, &Chains[0], ChainI); 3319 Root = Chain; 3320 ChainI = 0; 3321 } 3322 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3323 DAG.getConstant(Offsets[i], PtrVT)); 3324 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3325 SDValue(Src.getNode(), Src.getResNo() + i), 3326 Add, MachinePointerInfo(PtrV, Offsets[i]), 3327 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3328 Chains[ChainI] = St; 3329 } 3330 3331 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3332 MVT::Other, &Chains[0], ChainI); 3333 ++SDNodeOrder; 3334 AssignOrderingToNode(StoreNode.getNode()); 3335 DAG.setRoot(StoreNode); 3336} 3337 3338static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3339 SynchronizationScope Scope, 3340 bool Before, DebugLoc dl, 3341 SelectionDAG &DAG, 3342 const TargetLowering &TLI) { 3343 // Fence, if necessary 3344 if (Before) { 3345 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3346 Order = Release; 3347 else if (Order == Acquire || Order == Monotonic) 3348 return Chain; 3349 } else { 3350 if (Order == AcquireRelease) 3351 Order = Acquire; 3352 else if (Order == Release || Order == Monotonic) 3353 return Chain; 3354 } 3355 SDValue Ops[3]; 3356 Ops[0] = Chain; 3357 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3358 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3359 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3360} 3361 3362void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3363 DebugLoc dl = getCurDebugLoc(); 3364 AtomicOrdering Order = I.getOrdering(); 3365 SynchronizationScope Scope = I.getSynchScope(); 3366 3367 SDValue InChain = getRoot(); 3368 3369 if (TLI.getInsertFencesForAtomic()) 3370 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3371 DAG, TLI); 3372 3373 SDValue L = 3374 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3375 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3376 InChain, 3377 getValue(I.getPointerOperand()), 3378 getValue(I.getCompareOperand()), 3379 getValue(I.getNewValOperand()), 3380 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3381 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3382 Scope); 3383 3384 SDValue OutChain = L.getValue(1); 3385 3386 if (TLI.getInsertFencesForAtomic()) 3387 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3388 DAG, TLI); 3389 3390 setValue(&I, L); 3391 DAG.setRoot(OutChain); 3392} 3393 3394void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3395 DebugLoc dl = getCurDebugLoc(); 3396 ISD::NodeType NT; 3397 switch (I.getOperation()) { 3398 default: llvm_unreachable("Unknown atomicrmw operation"); 3399 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3400 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3401 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3402 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3403 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3404 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3405 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3406 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3407 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3408 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3409 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3410 } 3411 AtomicOrdering Order = I.getOrdering(); 3412 SynchronizationScope Scope = I.getSynchScope(); 3413 3414 SDValue InChain = getRoot(); 3415 3416 if (TLI.getInsertFencesForAtomic()) 3417 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3418 DAG, TLI); 3419 3420 SDValue L = 3421 DAG.getAtomic(NT, dl, 3422 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3423 InChain, 3424 getValue(I.getPointerOperand()), 3425 getValue(I.getValOperand()), 3426 I.getPointerOperand(), 0 /* Alignment */, 3427 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3428 Scope); 3429 3430 SDValue OutChain = L.getValue(1); 3431 3432 if (TLI.getInsertFencesForAtomic()) 3433 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3434 DAG, TLI); 3435 3436 setValue(&I, L); 3437 DAG.setRoot(OutChain); 3438} 3439 3440void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3441 DebugLoc dl = getCurDebugLoc(); 3442 SDValue Ops[3]; 3443 Ops[0] = getRoot(); 3444 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3445 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3446 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3447} 3448 3449void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3450 DebugLoc dl = getCurDebugLoc(); 3451 AtomicOrdering Order = I.getOrdering(); 3452 SynchronizationScope Scope = I.getSynchScope(); 3453 3454 SDValue InChain = getRoot(); 3455 3456 EVT VT = EVT::getEVT(I.getType()); 3457 3458 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3459 report_fatal_error("Cannot generate unaligned atomic load"); 3460 3461 SDValue L = 3462 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3463 getValue(I.getPointerOperand()), 3464 I.getPointerOperand(), I.getAlignment(), 3465 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3466 Scope); 3467 3468 SDValue OutChain = L.getValue(1); 3469 3470 if (TLI.getInsertFencesForAtomic()) 3471 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3472 DAG, TLI); 3473 3474 setValue(&I, L); 3475 DAG.setRoot(OutChain); 3476} 3477 3478void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3479 DebugLoc dl = getCurDebugLoc(); 3480 3481 AtomicOrdering Order = I.getOrdering(); 3482 SynchronizationScope Scope = I.getSynchScope(); 3483 3484 SDValue InChain = getRoot(); 3485 3486 EVT VT = EVT::getEVT(I.getValueOperand()->getType()); 3487 3488 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3489 report_fatal_error("Cannot generate unaligned atomic store"); 3490 3491 if (TLI.getInsertFencesForAtomic()) 3492 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3493 DAG, TLI); 3494 3495 SDValue OutChain = 3496 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3497 InChain, 3498 getValue(I.getPointerOperand()), 3499 getValue(I.getValueOperand()), 3500 I.getPointerOperand(), I.getAlignment(), 3501 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3502 Scope); 3503 3504 if (TLI.getInsertFencesForAtomic()) 3505 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3506 DAG, TLI); 3507 3508 DAG.setRoot(OutChain); 3509} 3510 3511/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3512/// node. 3513void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3514 unsigned Intrinsic) { 3515 bool HasChain = !I.doesNotAccessMemory(); 3516 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3517 3518 // Build the operand list. 3519 SmallVector<SDValue, 8> Ops; 3520 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3521 if (OnlyLoad) { 3522 // We don't need to serialize loads against other loads. 3523 Ops.push_back(DAG.getRoot()); 3524 } else { 3525 Ops.push_back(getRoot()); 3526 } 3527 } 3528 3529 // Info is set by getTgtMemInstrinsic 3530 TargetLowering::IntrinsicInfo Info; 3531 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3532 3533 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3534 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3535 Info.opc == ISD::INTRINSIC_W_CHAIN) 3536 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy())); 3537 3538 // Add all operands of the call to the operand list. 3539 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3540 SDValue Op = getValue(I.getArgOperand(i)); 3541 Ops.push_back(Op); 3542 } 3543 3544 SmallVector<EVT, 4> ValueVTs; 3545 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3546 3547 if (HasChain) 3548 ValueVTs.push_back(MVT::Other); 3549 3550 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3551 3552 // Create the node. 3553 SDValue Result; 3554 if (IsTgtIntrinsic) { 3555 // This is target intrinsic that touches memory 3556 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3557 VTs, &Ops[0], Ops.size(), 3558 Info.memVT, 3559 MachinePointerInfo(Info.ptrVal, Info.offset), 3560 Info.align, Info.vol, 3561 Info.readMem, Info.writeMem); 3562 } else if (!HasChain) { 3563 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3564 VTs, &Ops[0], Ops.size()); 3565 } else if (!I.getType()->isVoidTy()) { 3566 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3567 VTs, &Ops[0], Ops.size()); 3568 } else { 3569 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3570 VTs, &Ops[0], Ops.size()); 3571 } 3572 3573 if (HasChain) { 3574 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3575 if (OnlyLoad) 3576 PendingLoads.push_back(Chain); 3577 else 3578 DAG.setRoot(Chain); 3579 } 3580 3581 if (!I.getType()->isVoidTy()) { 3582 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3583 EVT VT = TLI.getValueType(PTy); 3584 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3585 } 3586 3587 setValue(&I, Result); 3588 } else { 3589 // Assign order to result here. If the intrinsic does not produce a result, 3590 // it won't be mapped to a SDNode and visit() will not assign it an order 3591 // number. 3592 ++SDNodeOrder; 3593 AssignOrderingToNode(Result.getNode()); 3594 } 3595} 3596 3597/// GetSignificand - Get the significand and build it into a floating-point 3598/// number with exponent of 1: 3599/// 3600/// Op = (Op & 0x007fffff) | 0x3f800000; 3601/// 3602/// where Op is the hexidecimal representation of floating point value. 3603static SDValue 3604GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3605 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3606 DAG.getConstant(0x007fffff, MVT::i32)); 3607 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3608 DAG.getConstant(0x3f800000, MVT::i32)); 3609 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3610} 3611 3612/// GetExponent - Get the exponent: 3613/// 3614/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3615/// 3616/// where Op is the hexidecimal representation of floating point value. 3617static SDValue 3618GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3619 DebugLoc dl) { 3620 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3621 DAG.getConstant(0x7f800000, MVT::i32)); 3622 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3623 DAG.getConstant(23, TLI.getPointerTy())); 3624 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3625 DAG.getConstant(127, MVT::i32)); 3626 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3627} 3628 3629/// getF32Constant - Get 32-bit floating point constant. 3630static SDValue 3631getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3632 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3633} 3634 3635/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3636/// limited-precision mode. 3637void 3638SelectionDAGBuilder::visitExp(const CallInst &I) { 3639 SDValue result; 3640 DebugLoc dl = getCurDebugLoc(); 3641 3642 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3643 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3644 SDValue Op = getValue(I.getArgOperand(0)); 3645 3646 // Put the exponent in the right bit position for later addition to the 3647 // final result: 3648 // 3649 // #define LOG2OFe 1.4426950f 3650 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3651 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3652 getF32Constant(DAG, 0x3fb8aa3b)); 3653 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3654 3655 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3656 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3657 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3658 3659 // IntegerPartOfX <<= 23; 3660 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3661 DAG.getConstant(23, TLI.getPointerTy())); 3662 3663 if (LimitFloatPrecision <= 6) { 3664 // For floating-point precision of 6: 3665 // 3666 // TwoToFractionalPartOfX = 3667 // 0.997535578f + 3668 // (0.735607626f + 0.252464424f * x) * x; 3669 // 3670 // error 0.0144103317, which is 6 bits 3671 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3672 getF32Constant(DAG, 0x3e814304)); 3673 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3674 getF32Constant(DAG, 0x3f3c50c8)); 3675 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3676 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3677 getF32Constant(DAG, 0x3f7f5e7e)); 3678 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3679 3680 // Add the exponent into the result in integer domain. 3681 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3682 TwoToFracPartOfX, IntegerPartOfX); 3683 3684 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3685 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3686 // For floating-point precision of 12: 3687 // 3688 // TwoToFractionalPartOfX = 3689 // 0.999892986f + 3690 // (0.696457318f + 3691 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3692 // 3693 // 0.000107046256 error, which is 13 to 14 bits 3694 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3695 getF32Constant(DAG, 0x3da235e3)); 3696 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3697 getF32Constant(DAG, 0x3e65b8f3)); 3698 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3699 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3700 getF32Constant(DAG, 0x3f324b07)); 3701 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3702 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3703 getF32Constant(DAG, 0x3f7ff8fd)); 3704 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3705 3706 // Add the exponent into the result in integer domain. 3707 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3708 TwoToFracPartOfX, IntegerPartOfX); 3709 3710 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3711 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3712 // For floating-point precision of 18: 3713 // 3714 // TwoToFractionalPartOfX = 3715 // 0.999999982f + 3716 // (0.693148872f + 3717 // (0.240227044f + 3718 // (0.554906021e-1f + 3719 // (0.961591928e-2f + 3720 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3721 // 3722 // error 2.47208000*10^(-7), which is better than 18 bits 3723 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3724 getF32Constant(DAG, 0x3924b03e)); 3725 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3726 getF32Constant(DAG, 0x3ab24b87)); 3727 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3728 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3729 getF32Constant(DAG, 0x3c1d8c17)); 3730 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3731 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3732 getF32Constant(DAG, 0x3d634a1d)); 3733 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3734 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3735 getF32Constant(DAG, 0x3e75fe14)); 3736 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3737 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3738 getF32Constant(DAG, 0x3f317234)); 3739 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3740 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3741 getF32Constant(DAG, 0x3f800000)); 3742 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3743 MVT::i32, t13); 3744 3745 // Add the exponent into the result in integer domain. 3746 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3747 TwoToFracPartOfX, IntegerPartOfX); 3748 3749 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3750 } 3751 } else { 3752 // No special expansion. 3753 result = DAG.getNode(ISD::FEXP, dl, 3754 getValue(I.getArgOperand(0)).getValueType(), 3755 getValue(I.getArgOperand(0))); 3756 } 3757 3758 setValue(&I, result); 3759} 3760 3761/// visitLog - Lower a log intrinsic. Handles the special sequences for 3762/// limited-precision mode. 3763void 3764SelectionDAGBuilder::visitLog(const CallInst &I) { 3765 SDValue result; 3766 DebugLoc dl = getCurDebugLoc(); 3767 3768 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3769 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3770 SDValue Op = getValue(I.getArgOperand(0)); 3771 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3772 3773 // Scale the exponent by log(2) [0.69314718f]. 3774 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3775 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3776 getF32Constant(DAG, 0x3f317218)); 3777 3778 // Get the significand and build it into a floating-point number with 3779 // exponent of 1. 3780 SDValue X = GetSignificand(DAG, Op1, dl); 3781 3782 if (LimitFloatPrecision <= 6) { 3783 // For floating-point precision of 6: 3784 // 3785 // LogofMantissa = 3786 // -1.1609546f + 3787 // (1.4034025f - 0.23903021f * x) * x; 3788 // 3789 // error 0.0034276066, which is better than 8 bits 3790 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3791 getF32Constant(DAG, 0xbe74c456)); 3792 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3793 getF32Constant(DAG, 0x3fb3a2b1)); 3794 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3795 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3796 getF32Constant(DAG, 0x3f949a29)); 3797 3798 result = DAG.getNode(ISD::FADD, dl, 3799 MVT::f32, LogOfExponent, LogOfMantissa); 3800 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3801 // For floating-point precision of 12: 3802 // 3803 // LogOfMantissa = 3804 // -1.7417939f + 3805 // (2.8212026f + 3806 // (-1.4699568f + 3807 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3808 // 3809 // error 0.000061011436, which is 14 bits 3810 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3811 getF32Constant(DAG, 0xbd67b6d6)); 3812 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3813 getF32Constant(DAG, 0x3ee4f4b8)); 3814 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3815 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3816 getF32Constant(DAG, 0x3fbc278b)); 3817 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3818 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3819 getF32Constant(DAG, 0x40348e95)); 3820 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3821 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3822 getF32Constant(DAG, 0x3fdef31a)); 3823 3824 result = DAG.getNode(ISD::FADD, dl, 3825 MVT::f32, LogOfExponent, LogOfMantissa); 3826 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3827 // For floating-point precision of 18: 3828 // 3829 // LogOfMantissa = 3830 // -2.1072184f + 3831 // (4.2372794f + 3832 // (-3.7029485f + 3833 // (2.2781945f + 3834 // (-0.87823314f + 3835 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3836 // 3837 // error 0.0000023660568, which is better than 18 bits 3838 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3839 getF32Constant(DAG, 0xbc91e5ac)); 3840 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3841 getF32Constant(DAG, 0x3e4350aa)); 3842 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3843 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3844 getF32Constant(DAG, 0x3f60d3e3)); 3845 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3846 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3847 getF32Constant(DAG, 0x4011cdf0)); 3848 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3849 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3850 getF32Constant(DAG, 0x406cfd1c)); 3851 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3852 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3853 getF32Constant(DAG, 0x408797cb)); 3854 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3855 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3856 getF32Constant(DAG, 0x4006dcab)); 3857 3858 result = DAG.getNode(ISD::FADD, dl, 3859 MVT::f32, LogOfExponent, LogOfMantissa); 3860 } 3861 } else { 3862 // No special expansion. 3863 result = DAG.getNode(ISD::FLOG, dl, 3864 getValue(I.getArgOperand(0)).getValueType(), 3865 getValue(I.getArgOperand(0))); 3866 } 3867 3868 setValue(&I, result); 3869} 3870 3871/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3872/// limited-precision mode. 3873void 3874SelectionDAGBuilder::visitLog2(const CallInst &I) { 3875 SDValue result; 3876 DebugLoc dl = getCurDebugLoc(); 3877 3878 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3879 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3880 SDValue Op = getValue(I.getArgOperand(0)); 3881 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3882 3883 // Get the exponent. 3884 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3885 3886 // Get the significand and build it into a floating-point number with 3887 // exponent of 1. 3888 SDValue X = GetSignificand(DAG, Op1, dl); 3889 3890 // Different possible minimax approximations of significand in 3891 // floating-point for various degrees of accuracy over [1,2]. 3892 if (LimitFloatPrecision <= 6) { 3893 // For floating-point precision of 6: 3894 // 3895 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3896 // 3897 // error 0.0049451742, which is more than 7 bits 3898 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3899 getF32Constant(DAG, 0xbeb08fe0)); 3900 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3901 getF32Constant(DAG, 0x40019463)); 3902 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3903 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3904 getF32Constant(DAG, 0x3fd6633d)); 3905 3906 result = DAG.getNode(ISD::FADD, dl, 3907 MVT::f32, LogOfExponent, Log2ofMantissa); 3908 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3909 // For floating-point precision of 12: 3910 // 3911 // Log2ofMantissa = 3912 // -2.51285454f + 3913 // (4.07009056f + 3914 // (-2.12067489f + 3915 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3916 // 3917 // error 0.0000876136000, which is better than 13 bits 3918 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3919 getF32Constant(DAG, 0xbda7262e)); 3920 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3921 getF32Constant(DAG, 0x3f25280b)); 3922 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3923 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3924 getF32Constant(DAG, 0x4007b923)); 3925 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3926 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3927 getF32Constant(DAG, 0x40823e2f)); 3928 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3929 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3930 getF32Constant(DAG, 0x4020d29c)); 3931 3932 result = DAG.getNode(ISD::FADD, dl, 3933 MVT::f32, LogOfExponent, Log2ofMantissa); 3934 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3935 // For floating-point precision of 18: 3936 // 3937 // Log2ofMantissa = 3938 // -3.0400495f + 3939 // (6.1129976f + 3940 // (-5.3420409f + 3941 // (3.2865683f + 3942 // (-1.2669343f + 3943 // (0.27515199f - 3944 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3945 // 3946 // error 0.0000018516, which is better than 18 bits 3947 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3948 getF32Constant(DAG, 0xbcd2769e)); 3949 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3950 getF32Constant(DAG, 0x3e8ce0b9)); 3951 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3952 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3953 getF32Constant(DAG, 0x3fa22ae7)); 3954 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3955 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3956 getF32Constant(DAG, 0x40525723)); 3957 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3958 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3959 getF32Constant(DAG, 0x40aaf200)); 3960 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3961 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3962 getF32Constant(DAG, 0x40c39dad)); 3963 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3964 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3965 getF32Constant(DAG, 0x4042902c)); 3966 3967 result = DAG.getNode(ISD::FADD, dl, 3968 MVT::f32, LogOfExponent, Log2ofMantissa); 3969 } 3970 } else { 3971 // No special expansion. 3972 result = DAG.getNode(ISD::FLOG2, dl, 3973 getValue(I.getArgOperand(0)).getValueType(), 3974 getValue(I.getArgOperand(0))); 3975 } 3976 3977 setValue(&I, result); 3978} 3979 3980/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3981/// limited-precision mode. 3982void 3983SelectionDAGBuilder::visitLog10(const CallInst &I) { 3984 SDValue result; 3985 DebugLoc dl = getCurDebugLoc(); 3986 3987 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3988 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3989 SDValue Op = getValue(I.getArgOperand(0)); 3990 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3991 3992 // Scale the exponent by log10(2) [0.30102999f]. 3993 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3994 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3995 getF32Constant(DAG, 0x3e9a209a)); 3996 3997 // Get the significand and build it into a floating-point number with 3998 // exponent of 1. 3999 SDValue X = GetSignificand(DAG, Op1, dl); 4000 4001 if (LimitFloatPrecision <= 6) { 4002 // For floating-point precision of 6: 4003 // 4004 // Log10ofMantissa = 4005 // -0.50419619f + 4006 // (0.60948995f - 0.10380950f * x) * x; 4007 // 4008 // error 0.0014886165, which is 6 bits 4009 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4010 getF32Constant(DAG, 0xbdd49a13)); 4011 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4012 getF32Constant(DAG, 0x3f1c0789)); 4013 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4014 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4015 getF32Constant(DAG, 0x3f011300)); 4016 4017 result = DAG.getNode(ISD::FADD, dl, 4018 MVT::f32, LogOfExponent, Log10ofMantissa); 4019 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4020 // For floating-point precision of 12: 4021 // 4022 // Log10ofMantissa = 4023 // -0.64831180f + 4024 // (0.91751397f + 4025 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4026 // 4027 // error 0.00019228036, which is better than 12 bits 4028 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4029 getF32Constant(DAG, 0x3d431f31)); 4030 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4031 getF32Constant(DAG, 0x3ea21fb2)); 4032 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4033 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4034 getF32Constant(DAG, 0x3f6ae232)); 4035 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4036 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4037 getF32Constant(DAG, 0x3f25f7c3)); 4038 4039 result = DAG.getNode(ISD::FADD, dl, 4040 MVT::f32, LogOfExponent, Log10ofMantissa); 4041 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4042 // For floating-point precision of 18: 4043 // 4044 // Log10ofMantissa = 4045 // -0.84299375f + 4046 // (1.5327582f + 4047 // (-1.0688956f + 4048 // (0.49102474f + 4049 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4050 // 4051 // error 0.0000037995730, which is better than 18 bits 4052 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4053 getF32Constant(DAG, 0x3c5d51ce)); 4054 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4055 getF32Constant(DAG, 0x3e00685a)); 4056 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4057 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4058 getF32Constant(DAG, 0x3efb6798)); 4059 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4060 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4061 getF32Constant(DAG, 0x3f88d192)); 4062 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4063 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4064 getF32Constant(DAG, 0x3fc4316c)); 4065 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4066 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4067 getF32Constant(DAG, 0x3f57ce70)); 4068 4069 result = DAG.getNode(ISD::FADD, dl, 4070 MVT::f32, LogOfExponent, Log10ofMantissa); 4071 } 4072 } else { 4073 // No special expansion. 4074 result = DAG.getNode(ISD::FLOG10, dl, 4075 getValue(I.getArgOperand(0)).getValueType(), 4076 getValue(I.getArgOperand(0))); 4077 } 4078 4079 setValue(&I, result); 4080} 4081 4082/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4083/// limited-precision mode. 4084void 4085SelectionDAGBuilder::visitExp2(const CallInst &I) { 4086 SDValue result; 4087 DebugLoc dl = getCurDebugLoc(); 4088 4089 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 4090 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4091 SDValue Op = getValue(I.getArgOperand(0)); 4092 4093 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4094 4095 // FractionalPartOfX = x - (float)IntegerPartOfX; 4096 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4097 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4098 4099 // IntegerPartOfX <<= 23; 4100 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4101 DAG.getConstant(23, TLI.getPointerTy())); 4102 4103 if (LimitFloatPrecision <= 6) { 4104 // For floating-point precision of 6: 4105 // 4106 // TwoToFractionalPartOfX = 4107 // 0.997535578f + 4108 // (0.735607626f + 0.252464424f * x) * x; 4109 // 4110 // error 0.0144103317, which is 6 bits 4111 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4112 getF32Constant(DAG, 0x3e814304)); 4113 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4114 getF32Constant(DAG, 0x3f3c50c8)); 4115 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4116 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4117 getF32Constant(DAG, 0x3f7f5e7e)); 4118 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4119 SDValue TwoToFractionalPartOfX = 4120 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4121 4122 result = DAG.getNode(ISD::BITCAST, dl, 4123 MVT::f32, TwoToFractionalPartOfX); 4124 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4125 // For floating-point precision of 12: 4126 // 4127 // TwoToFractionalPartOfX = 4128 // 0.999892986f + 4129 // (0.696457318f + 4130 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4131 // 4132 // error 0.000107046256, which is 13 to 14 bits 4133 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4134 getF32Constant(DAG, 0x3da235e3)); 4135 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4136 getF32Constant(DAG, 0x3e65b8f3)); 4137 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4138 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4139 getF32Constant(DAG, 0x3f324b07)); 4140 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4141 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4142 getF32Constant(DAG, 0x3f7ff8fd)); 4143 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4144 SDValue TwoToFractionalPartOfX = 4145 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4146 4147 result = DAG.getNode(ISD::BITCAST, dl, 4148 MVT::f32, TwoToFractionalPartOfX); 4149 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4150 // For floating-point precision of 18: 4151 // 4152 // TwoToFractionalPartOfX = 4153 // 0.999999982f + 4154 // (0.693148872f + 4155 // (0.240227044f + 4156 // (0.554906021e-1f + 4157 // (0.961591928e-2f + 4158 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4159 // error 2.47208000*10^(-7), which is better than 18 bits 4160 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4161 getF32Constant(DAG, 0x3924b03e)); 4162 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4163 getF32Constant(DAG, 0x3ab24b87)); 4164 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4165 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4166 getF32Constant(DAG, 0x3c1d8c17)); 4167 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4168 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4169 getF32Constant(DAG, 0x3d634a1d)); 4170 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4171 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4172 getF32Constant(DAG, 0x3e75fe14)); 4173 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4174 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4175 getF32Constant(DAG, 0x3f317234)); 4176 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4177 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4178 getF32Constant(DAG, 0x3f800000)); 4179 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4180 SDValue TwoToFractionalPartOfX = 4181 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4182 4183 result = DAG.getNode(ISD::BITCAST, dl, 4184 MVT::f32, TwoToFractionalPartOfX); 4185 } 4186 } else { 4187 // No special expansion. 4188 result = DAG.getNode(ISD::FEXP2, dl, 4189 getValue(I.getArgOperand(0)).getValueType(), 4190 getValue(I.getArgOperand(0))); 4191 } 4192 4193 setValue(&I, result); 4194} 4195 4196/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4197/// limited-precision mode with x == 10.0f. 4198void 4199SelectionDAGBuilder::visitPow(const CallInst &I) { 4200 SDValue result; 4201 const Value *Val = I.getArgOperand(0); 4202 DebugLoc dl = getCurDebugLoc(); 4203 bool IsExp10 = false; 4204 4205 if (getValue(Val).getValueType() == MVT::f32 && 4206 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4207 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4208 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4209 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4210 APFloat Ten(10.0f); 4211 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4212 } 4213 } 4214 } 4215 4216 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4217 SDValue Op = getValue(I.getArgOperand(1)); 4218 4219 // Put the exponent in the right bit position for later addition to the 4220 // final result: 4221 // 4222 // #define LOG2OF10 3.3219281f 4223 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4224 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4225 getF32Constant(DAG, 0x40549a78)); 4226 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4227 4228 // FractionalPartOfX = x - (float)IntegerPartOfX; 4229 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4230 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4231 4232 // IntegerPartOfX <<= 23; 4233 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4234 DAG.getConstant(23, TLI.getPointerTy())); 4235 4236 if (LimitFloatPrecision <= 6) { 4237 // For floating-point precision of 6: 4238 // 4239 // twoToFractionalPartOfX = 4240 // 0.997535578f + 4241 // (0.735607626f + 0.252464424f * x) * x; 4242 // 4243 // error 0.0144103317, which is 6 bits 4244 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4245 getF32Constant(DAG, 0x3e814304)); 4246 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4247 getF32Constant(DAG, 0x3f3c50c8)); 4248 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4249 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4250 getF32Constant(DAG, 0x3f7f5e7e)); 4251 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4252 SDValue TwoToFractionalPartOfX = 4253 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4254 4255 result = DAG.getNode(ISD::BITCAST, dl, 4256 MVT::f32, TwoToFractionalPartOfX); 4257 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4258 // For floating-point precision of 12: 4259 // 4260 // TwoToFractionalPartOfX = 4261 // 0.999892986f + 4262 // (0.696457318f + 4263 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4264 // 4265 // error 0.000107046256, which is 13 to 14 bits 4266 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4267 getF32Constant(DAG, 0x3da235e3)); 4268 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4269 getF32Constant(DAG, 0x3e65b8f3)); 4270 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4271 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4272 getF32Constant(DAG, 0x3f324b07)); 4273 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4274 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4275 getF32Constant(DAG, 0x3f7ff8fd)); 4276 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4277 SDValue TwoToFractionalPartOfX = 4278 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4279 4280 result = DAG.getNode(ISD::BITCAST, dl, 4281 MVT::f32, TwoToFractionalPartOfX); 4282 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4283 // For floating-point precision of 18: 4284 // 4285 // TwoToFractionalPartOfX = 4286 // 0.999999982f + 4287 // (0.693148872f + 4288 // (0.240227044f + 4289 // (0.554906021e-1f + 4290 // (0.961591928e-2f + 4291 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4292 // error 2.47208000*10^(-7), which is better than 18 bits 4293 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4294 getF32Constant(DAG, 0x3924b03e)); 4295 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4296 getF32Constant(DAG, 0x3ab24b87)); 4297 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4298 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4299 getF32Constant(DAG, 0x3c1d8c17)); 4300 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4301 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4302 getF32Constant(DAG, 0x3d634a1d)); 4303 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4304 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4305 getF32Constant(DAG, 0x3e75fe14)); 4306 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4307 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4308 getF32Constant(DAG, 0x3f317234)); 4309 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4310 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4311 getF32Constant(DAG, 0x3f800000)); 4312 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4313 SDValue TwoToFractionalPartOfX = 4314 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4315 4316 result = DAG.getNode(ISD::BITCAST, dl, 4317 MVT::f32, TwoToFractionalPartOfX); 4318 } 4319 } else { 4320 // No special expansion. 4321 result = DAG.getNode(ISD::FPOW, dl, 4322 getValue(I.getArgOperand(0)).getValueType(), 4323 getValue(I.getArgOperand(0)), 4324 getValue(I.getArgOperand(1))); 4325 } 4326 4327 setValue(&I, result); 4328} 4329 4330 4331/// ExpandPowI - Expand a llvm.powi intrinsic. 4332static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4333 SelectionDAG &DAG) { 4334 // If RHS is a constant, we can expand this out to a multiplication tree, 4335 // otherwise we end up lowering to a call to __powidf2 (for example). When 4336 // optimizing for size, we only want to do this if the expansion would produce 4337 // a small number of multiplies, otherwise we do the full expansion. 4338 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4339 // Get the exponent as a positive value. 4340 unsigned Val = RHSC->getSExtValue(); 4341 if ((int)Val < 0) Val = -Val; 4342 4343 // powi(x, 0) -> 1.0 4344 if (Val == 0) 4345 return DAG.getConstantFP(1.0, LHS.getValueType()); 4346 4347 const Function *F = DAG.getMachineFunction().getFunction(); 4348 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4349 // If optimizing for size, don't insert too many multiplies. This 4350 // inserts up to 5 multiplies. 4351 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4352 // We use the simple binary decomposition method to generate the multiply 4353 // sequence. There are more optimal ways to do this (for example, 4354 // powi(x,15) generates one more multiply than it should), but this has 4355 // the benefit of being both really simple and much better than a libcall. 4356 SDValue Res; // Logically starts equal to 1.0 4357 SDValue CurSquare = LHS; 4358 while (Val) { 4359 if (Val & 1) { 4360 if (Res.getNode()) 4361 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4362 else 4363 Res = CurSquare; // 1.0*CurSquare. 4364 } 4365 4366 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4367 CurSquare, CurSquare); 4368 Val >>= 1; 4369 } 4370 4371 // If the original was negative, invert the result, producing 1/(x*x*x). 4372 if (RHSC->getSExtValue() < 0) 4373 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4374 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4375 return Res; 4376 } 4377 } 4378 4379 // Otherwise, expand to a libcall. 4380 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4381} 4382 4383// getTruncatedArgReg - Find underlying register used for an truncated 4384// argument. 4385static unsigned getTruncatedArgReg(const SDValue &N) { 4386 if (N.getOpcode() != ISD::TRUNCATE) 4387 return 0; 4388 4389 const SDValue &Ext = N.getOperand(0); 4390 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4391 const SDValue &CFR = Ext.getOperand(0); 4392 if (CFR.getOpcode() == ISD::CopyFromReg) 4393 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4394 if (CFR.getOpcode() == ISD::TRUNCATE) 4395 return getTruncatedArgReg(CFR); 4396 } 4397 return 0; 4398} 4399 4400/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4401/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4402/// At the end of instruction selection, they will be inserted to the entry BB. 4403bool 4404SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4405 int64_t Offset, 4406 const SDValue &N) { 4407 const Argument *Arg = dyn_cast<Argument>(V); 4408 if (!Arg) 4409 return false; 4410 4411 MachineFunction &MF = DAG.getMachineFunction(); 4412 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4413 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4414 4415 // Ignore inlined function arguments here. 4416 DIVariable DV(Variable); 4417 if (DV.isInlinedFnArgument(MF.getFunction())) 4418 return false; 4419 4420 unsigned Reg = 0; 4421 // Some arguments' frame index is recorded during argument lowering. 4422 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4423 if (Offset) 4424 Reg = TRI->getFrameRegister(MF); 4425 4426 if (!Reg && N.getNode()) { 4427 if (N.getOpcode() == ISD::CopyFromReg) 4428 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4429 else 4430 Reg = getTruncatedArgReg(N); 4431 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4432 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4433 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4434 if (PR) 4435 Reg = PR; 4436 } 4437 } 4438 4439 if (!Reg) { 4440 // Check if ValueMap has reg number. 4441 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4442 if (VMI != FuncInfo.ValueMap.end()) 4443 Reg = VMI->second; 4444 } 4445 4446 if (!Reg && N.getNode()) { 4447 // Check if frame index is available. 4448 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4449 if (FrameIndexSDNode *FINode = 4450 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4451 Reg = TRI->getFrameRegister(MF); 4452 Offset = FINode->getIndex(); 4453 } 4454 } 4455 4456 if (!Reg) 4457 return false; 4458 4459 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4460 TII->get(TargetOpcode::DBG_VALUE)) 4461 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4462 FuncInfo.ArgDbgValues.push_back(&*MIB); 4463 return true; 4464} 4465 4466// VisualStudio defines setjmp as _setjmp 4467#if defined(_MSC_VER) && defined(setjmp) && \ 4468 !defined(setjmp_undefined_for_msvc) 4469# pragma push_macro("setjmp") 4470# undef setjmp 4471# define setjmp_undefined_for_msvc 4472#endif 4473 4474/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4475/// we want to emit this as a call to a named external function, return the name 4476/// otherwise lower it and return null. 4477const char * 4478SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4479 DebugLoc dl = getCurDebugLoc(); 4480 SDValue Res; 4481 4482 switch (Intrinsic) { 4483 default: 4484 // By default, turn this into a target intrinsic node. 4485 visitTargetIntrinsic(I, Intrinsic); 4486 return 0; 4487 case Intrinsic::vastart: visitVAStart(I); return 0; 4488 case Intrinsic::vaend: visitVAEnd(I); return 0; 4489 case Intrinsic::vacopy: visitVACopy(I); return 0; 4490 case Intrinsic::returnaddress: 4491 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4492 getValue(I.getArgOperand(0)))); 4493 return 0; 4494 case Intrinsic::frameaddress: 4495 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4496 getValue(I.getArgOperand(0)))); 4497 return 0; 4498 case Intrinsic::setjmp: 4499 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()]; 4500 case Intrinsic::longjmp: 4501 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()]; 4502 case Intrinsic::memcpy: { 4503 // Assert for address < 256 since we support only user defined address 4504 // spaces. 4505 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4506 < 256 && 4507 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4508 < 256 && 4509 "Unknown address space"); 4510 SDValue Op1 = getValue(I.getArgOperand(0)); 4511 SDValue Op2 = getValue(I.getArgOperand(1)); 4512 SDValue Op3 = getValue(I.getArgOperand(2)); 4513 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4514 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4515 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4516 MachinePointerInfo(I.getArgOperand(0)), 4517 MachinePointerInfo(I.getArgOperand(1)))); 4518 return 0; 4519 } 4520 case Intrinsic::memset: { 4521 // Assert for address < 256 since we support only user defined address 4522 // spaces. 4523 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4524 < 256 && 4525 "Unknown address space"); 4526 SDValue Op1 = getValue(I.getArgOperand(0)); 4527 SDValue Op2 = getValue(I.getArgOperand(1)); 4528 SDValue Op3 = getValue(I.getArgOperand(2)); 4529 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4530 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4531 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4532 MachinePointerInfo(I.getArgOperand(0)))); 4533 return 0; 4534 } 4535 case Intrinsic::memmove: { 4536 // Assert for address < 256 since we support only user defined address 4537 // spaces. 4538 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4539 < 256 && 4540 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4541 < 256 && 4542 "Unknown address space"); 4543 SDValue Op1 = getValue(I.getArgOperand(0)); 4544 SDValue Op2 = getValue(I.getArgOperand(1)); 4545 SDValue Op3 = getValue(I.getArgOperand(2)); 4546 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4547 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4548 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4549 MachinePointerInfo(I.getArgOperand(0)), 4550 MachinePointerInfo(I.getArgOperand(1)))); 4551 return 0; 4552 } 4553 case Intrinsic::dbg_declare: { 4554 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4555 MDNode *Variable = DI.getVariable(); 4556 const Value *Address = DI.getAddress(); 4557 if (!Address || !DIVariable(Variable).Verify()) { 4558 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4559 return 0; 4560 } 4561 4562 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4563 // but do not always have a corresponding SDNode built. The SDNodeOrder 4564 // absolute, but not relative, values are different depending on whether 4565 // debug info exists. 4566 ++SDNodeOrder; 4567 4568 // Check if address has undef value. 4569 if (isa<UndefValue>(Address) || 4570 (Address->use_empty() && !isa<Argument>(Address))) { 4571 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4572 return 0; 4573 } 4574 4575 SDValue &N = NodeMap[Address]; 4576 if (!N.getNode() && isa<Argument>(Address)) 4577 // Check unused arguments map. 4578 N = UnusedArgNodeMap[Address]; 4579 SDDbgValue *SDV; 4580 if (N.getNode()) { 4581 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4582 Address = BCI->getOperand(0); 4583 // Parameters are handled specially. 4584 bool isParameter = 4585 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable || 4586 isa<Argument>(Address)); 4587 4588 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4589 4590 if (isParameter && !AI) { 4591 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4592 if (FINode) 4593 // Byval parameter. We have a frame index at this point. 4594 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4595 0, dl, SDNodeOrder); 4596 else { 4597 // Address is an argument, so try to emit its dbg value using 4598 // virtual register info from the FuncInfo.ValueMap. 4599 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4600 return 0; 4601 } 4602 } else if (AI) 4603 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4604 0, dl, SDNodeOrder); 4605 else { 4606 // Can't do anything with other non-AI cases yet. 4607 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4608 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t"); 4609 DEBUG(Address->dump()); 4610 return 0; 4611 } 4612 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4613 } else { 4614 // If Address is an argument then try to emit its dbg value using 4615 // virtual register info from the FuncInfo.ValueMap. 4616 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4617 // If variable is pinned by a alloca in dominating bb then 4618 // use StaticAllocaMap. 4619 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4620 if (AI->getParent() != DI.getParent()) { 4621 DenseMap<const AllocaInst*, int>::iterator SI = 4622 FuncInfo.StaticAllocaMap.find(AI); 4623 if (SI != FuncInfo.StaticAllocaMap.end()) { 4624 SDV = DAG.getDbgValue(Variable, SI->second, 4625 0, dl, SDNodeOrder); 4626 DAG.AddDbgValue(SDV, 0, false); 4627 return 0; 4628 } 4629 } 4630 } 4631 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4632 } 4633 } 4634 return 0; 4635 } 4636 case Intrinsic::dbg_value: { 4637 const DbgValueInst &DI = cast<DbgValueInst>(I); 4638 if (!DIVariable(DI.getVariable()).Verify()) 4639 return 0; 4640 4641 MDNode *Variable = DI.getVariable(); 4642 uint64_t Offset = DI.getOffset(); 4643 const Value *V = DI.getValue(); 4644 if (!V) 4645 return 0; 4646 4647 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4648 // but do not always have a corresponding SDNode built. The SDNodeOrder 4649 // absolute, but not relative, values are different depending on whether 4650 // debug info exists. 4651 ++SDNodeOrder; 4652 SDDbgValue *SDV; 4653 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4654 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4655 DAG.AddDbgValue(SDV, 0, false); 4656 } else { 4657 // Do not use getValue() in here; we don't want to generate code at 4658 // this point if it hasn't been done yet. 4659 SDValue N = NodeMap[V]; 4660 if (!N.getNode() && isa<Argument>(V)) 4661 // Check unused arguments map. 4662 N = UnusedArgNodeMap[V]; 4663 if (N.getNode()) { 4664 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4665 SDV = DAG.getDbgValue(Variable, N.getNode(), 4666 N.getResNo(), Offset, dl, SDNodeOrder); 4667 DAG.AddDbgValue(SDV, N.getNode(), false); 4668 } 4669 } else if (!V->use_empty() ) { 4670 // Do not call getValue(V) yet, as we don't want to generate code. 4671 // Remember it for later. 4672 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4673 DanglingDebugInfoMap[V] = DDI; 4674 } else { 4675 // We may expand this to cover more cases. One case where we have no 4676 // data available is an unreferenced parameter. 4677 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4678 } 4679 } 4680 4681 // Build a debug info table entry. 4682 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4683 V = BCI->getOperand(0); 4684 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4685 // Don't handle byval struct arguments or VLAs, for example. 4686 if (!AI) { 4687 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); 4688 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); 4689 return 0; 4690 } 4691 DenseMap<const AllocaInst*, int>::iterator SI = 4692 FuncInfo.StaticAllocaMap.find(AI); 4693 if (SI == FuncInfo.StaticAllocaMap.end()) 4694 return 0; // VLAs. 4695 int FI = SI->second; 4696 4697 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4698 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4699 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4700 return 0; 4701 } 4702 4703 case Intrinsic::eh_typeid_for: { 4704 // Find the type id for the given typeinfo. 4705 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4706 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4707 Res = DAG.getConstant(TypeID, MVT::i32); 4708 setValue(&I, Res); 4709 return 0; 4710 } 4711 4712 case Intrinsic::eh_return_i32: 4713 case Intrinsic::eh_return_i64: 4714 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4715 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4716 MVT::Other, 4717 getControlRoot(), 4718 getValue(I.getArgOperand(0)), 4719 getValue(I.getArgOperand(1)))); 4720 return 0; 4721 case Intrinsic::eh_unwind_init: 4722 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4723 return 0; 4724 case Intrinsic::eh_dwarf_cfa: { 4725 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4726 TLI.getPointerTy()); 4727 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4728 TLI.getPointerTy(), 4729 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4730 TLI.getPointerTy()), 4731 CfaArg); 4732 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4733 TLI.getPointerTy(), 4734 DAG.getConstant(0, TLI.getPointerTy())); 4735 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4736 FA, Offset)); 4737 return 0; 4738 } 4739 case Intrinsic::eh_sjlj_callsite: { 4740 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4741 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4742 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4743 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4744 4745 MMI.setCurrentCallSite(CI->getZExtValue()); 4746 return 0; 4747 } 4748 case Intrinsic::eh_sjlj_functioncontext: { 4749 // Get and store the index of the function context. 4750 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4751 AllocaInst *FnCtx = 4752 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4753 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4754 MFI->setFunctionContextIndex(FI); 4755 return 0; 4756 } 4757 case Intrinsic::eh_sjlj_setjmp: { 4758 SDValue Ops[2]; 4759 Ops[0] = getRoot(); 4760 Ops[1] = getValue(I.getArgOperand(0)); 4761 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, 4762 DAG.getVTList(MVT::i32, MVT::Other), 4763 Ops, 2); 4764 setValue(&I, Op.getValue(0)); 4765 DAG.setRoot(Op.getValue(1)); 4766 return 0; 4767 } 4768 case Intrinsic::eh_sjlj_longjmp: { 4769 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4770 getRoot(), getValue(I.getArgOperand(0)))); 4771 return 0; 4772 } 4773 4774 case Intrinsic::x86_mmx_pslli_w: 4775 case Intrinsic::x86_mmx_pslli_d: 4776 case Intrinsic::x86_mmx_pslli_q: 4777 case Intrinsic::x86_mmx_psrli_w: 4778 case Intrinsic::x86_mmx_psrli_d: 4779 case Intrinsic::x86_mmx_psrli_q: 4780 case Intrinsic::x86_mmx_psrai_w: 4781 case Intrinsic::x86_mmx_psrai_d: { 4782 SDValue ShAmt = getValue(I.getArgOperand(1)); 4783 if (isa<ConstantSDNode>(ShAmt)) { 4784 visitTargetIntrinsic(I, Intrinsic); 4785 return 0; 4786 } 4787 unsigned NewIntrinsic = 0; 4788 EVT ShAmtVT = MVT::v2i32; 4789 switch (Intrinsic) { 4790 case Intrinsic::x86_mmx_pslli_w: 4791 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4792 break; 4793 case Intrinsic::x86_mmx_pslli_d: 4794 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4795 break; 4796 case Intrinsic::x86_mmx_pslli_q: 4797 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4798 break; 4799 case Intrinsic::x86_mmx_psrli_w: 4800 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4801 break; 4802 case Intrinsic::x86_mmx_psrli_d: 4803 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4804 break; 4805 case Intrinsic::x86_mmx_psrli_q: 4806 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4807 break; 4808 case Intrinsic::x86_mmx_psrai_w: 4809 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4810 break; 4811 case Intrinsic::x86_mmx_psrai_d: 4812 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4813 break; 4814 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4815 } 4816 4817 // The vector shift intrinsics with scalars uses 32b shift amounts but 4818 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4819 // to be zero. 4820 // We must do this early because v2i32 is not a legal type. 4821 DebugLoc dl = getCurDebugLoc(); 4822 SDValue ShOps[2]; 4823 ShOps[0] = ShAmt; 4824 ShOps[1] = DAG.getConstant(0, MVT::i32); 4825 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4826 EVT DestVT = TLI.getValueType(I.getType()); 4827 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4828 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4829 DAG.getConstant(NewIntrinsic, MVT::i32), 4830 getValue(I.getArgOperand(0)), ShAmt); 4831 setValue(&I, Res); 4832 return 0; 4833 } 4834 case Intrinsic::x86_avx_vinsertf128_pd_256: 4835 case Intrinsic::x86_avx_vinsertf128_ps_256: 4836 case Intrinsic::x86_avx_vinsertf128_si_256: 4837 case Intrinsic::x86_avx2_vinserti128: { 4838 DebugLoc dl = getCurDebugLoc(); 4839 EVT DestVT = TLI.getValueType(I.getType()); 4840 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType()); 4841 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) * 4842 ElVT.getVectorNumElements(); 4843 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT, 4844 getValue(I.getArgOperand(0)), 4845 getValue(I.getArgOperand(1)), 4846 DAG.getConstant(Idx, MVT::i32)); 4847 setValue(&I, Res); 4848 return 0; 4849 } 4850 case Intrinsic::convertff: 4851 case Intrinsic::convertfsi: 4852 case Intrinsic::convertfui: 4853 case Intrinsic::convertsif: 4854 case Intrinsic::convertuif: 4855 case Intrinsic::convertss: 4856 case Intrinsic::convertsu: 4857 case Intrinsic::convertus: 4858 case Intrinsic::convertuu: { 4859 ISD::CvtCode Code = ISD::CVT_INVALID; 4860 switch (Intrinsic) { 4861 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4862 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4863 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4864 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4865 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4866 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4867 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4868 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4869 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4870 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4871 } 4872 EVT DestVT = TLI.getValueType(I.getType()); 4873 const Value *Op1 = I.getArgOperand(0); 4874 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4875 DAG.getValueType(DestVT), 4876 DAG.getValueType(getValue(Op1).getValueType()), 4877 getValue(I.getArgOperand(1)), 4878 getValue(I.getArgOperand(2)), 4879 Code); 4880 setValue(&I, Res); 4881 return 0; 4882 } 4883 case Intrinsic::sqrt: 4884 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4885 getValue(I.getArgOperand(0)).getValueType(), 4886 getValue(I.getArgOperand(0)))); 4887 return 0; 4888 case Intrinsic::powi: 4889 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4890 getValue(I.getArgOperand(1)), DAG)); 4891 return 0; 4892 case Intrinsic::sin: 4893 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4894 getValue(I.getArgOperand(0)).getValueType(), 4895 getValue(I.getArgOperand(0)))); 4896 return 0; 4897 case Intrinsic::cos: 4898 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4899 getValue(I.getArgOperand(0)).getValueType(), 4900 getValue(I.getArgOperand(0)))); 4901 return 0; 4902 case Intrinsic::log: 4903 visitLog(I); 4904 return 0; 4905 case Intrinsic::log2: 4906 visitLog2(I); 4907 return 0; 4908 case Intrinsic::log10: 4909 visitLog10(I); 4910 return 0; 4911 case Intrinsic::exp: 4912 visitExp(I); 4913 return 0; 4914 case Intrinsic::exp2: 4915 visitExp2(I); 4916 return 0; 4917 case Intrinsic::pow: 4918 visitPow(I); 4919 return 0; 4920 case Intrinsic::fma: 4921 setValue(&I, DAG.getNode(ISD::FMA, dl, 4922 getValue(I.getArgOperand(0)).getValueType(), 4923 getValue(I.getArgOperand(0)), 4924 getValue(I.getArgOperand(1)), 4925 getValue(I.getArgOperand(2)))); 4926 return 0; 4927 case Intrinsic::convert_to_fp16: 4928 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4929 MVT::i16, getValue(I.getArgOperand(0)))); 4930 return 0; 4931 case Intrinsic::convert_from_fp16: 4932 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4933 MVT::f32, getValue(I.getArgOperand(0)))); 4934 return 0; 4935 case Intrinsic::pcmarker: { 4936 SDValue Tmp = getValue(I.getArgOperand(0)); 4937 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4938 return 0; 4939 } 4940 case Intrinsic::readcyclecounter: { 4941 SDValue Op = getRoot(); 4942 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4943 DAG.getVTList(MVT::i64, MVT::Other), 4944 &Op, 1); 4945 setValue(&I, Res); 4946 DAG.setRoot(Res.getValue(1)); 4947 return 0; 4948 } 4949 case Intrinsic::bswap: 4950 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4951 getValue(I.getArgOperand(0)).getValueType(), 4952 getValue(I.getArgOperand(0)))); 4953 return 0; 4954 case Intrinsic::cttz: { 4955 SDValue Arg = getValue(I.getArgOperand(0)); 4956 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4957 EVT Ty = Arg.getValueType(); 4958 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 4959 dl, Ty, Arg)); 4960 return 0; 4961 } 4962 case Intrinsic::ctlz: { 4963 SDValue Arg = getValue(I.getArgOperand(0)); 4964 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4965 EVT Ty = Arg.getValueType(); 4966 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 4967 dl, Ty, Arg)); 4968 return 0; 4969 } 4970 case Intrinsic::ctpop: { 4971 SDValue Arg = getValue(I.getArgOperand(0)); 4972 EVT Ty = Arg.getValueType(); 4973 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4974 return 0; 4975 } 4976 case Intrinsic::stacksave: { 4977 SDValue Op = getRoot(); 4978 Res = DAG.getNode(ISD::STACKSAVE, dl, 4979 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4980 setValue(&I, Res); 4981 DAG.setRoot(Res.getValue(1)); 4982 return 0; 4983 } 4984 case Intrinsic::stackrestore: { 4985 Res = getValue(I.getArgOperand(0)); 4986 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4987 return 0; 4988 } 4989 case Intrinsic::stackprotector: { 4990 // Emit code into the DAG to store the stack guard onto the stack. 4991 MachineFunction &MF = DAG.getMachineFunction(); 4992 MachineFrameInfo *MFI = MF.getFrameInfo(); 4993 EVT PtrTy = TLI.getPointerTy(); 4994 4995 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4996 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4997 4998 int FI = FuncInfo.StaticAllocaMap[Slot]; 4999 MFI->setStackProtectorIndex(FI); 5000 5001 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5002 5003 // Store the stack protector onto the stack. 5004 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 5005 MachinePointerInfo::getFixedStack(FI), 5006 true, false, 0); 5007 setValue(&I, Res); 5008 DAG.setRoot(Res); 5009 return 0; 5010 } 5011 case Intrinsic::objectsize: { 5012 // If we don't know by now, we're never going to know. 5013 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5014 5015 assert(CI && "Non-constant type in __builtin_object_size?"); 5016 5017 SDValue Arg = getValue(I.getCalledValue()); 5018 EVT Ty = Arg.getValueType(); 5019 5020 if (CI->isZero()) 5021 Res = DAG.getConstant(-1ULL, Ty); 5022 else 5023 Res = DAG.getConstant(0, Ty); 5024 5025 setValue(&I, Res); 5026 return 0; 5027 } 5028 case Intrinsic::var_annotation: 5029 // Discard annotate attributes 5030 return 0; 5031 5032 case Intrinsic::init_trampoline: { 5033 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5034 5035 SDValue Ops[6]; 5036 Ops[0] = getRoot(); 5037 Ops[1] = getValue(I.getArgOperand(0)); 5038 Ops[2] = getValue(I.getArgOperand(1)); 5039 Ops[3] = getValue(I.getArgOperand(2)); 5040 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5041 Ops[5] = DAG.getSrcValue(F); 5042 5043 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5044 5045 DAG.setRoot(Res); 5046 return 0; 5047 } 5048 case Intrinsic::adjust_trampoline: { 5049 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5050 TLI.getPointerTy(), 5051 getValue(I.getArgOperand(0)))); 5052 return 0; 5053 } 5054 case Intrinsic::gcroot: 5055 if (GFI) { 5056 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); 5057 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5058 5059 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5060 GFI->addStackRoot(FI->getIndex(), TypeMap); 5061 } 5062 return 0; 5063 case Intrinsic::gcread: 5064 case Intrinsic::gcwrite: 5065 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5066 case Intrinsic::flt_rounds: 5067 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5068 return 0; 5069 5070 case Intrinsic::expect: { 5071 // Just replace __builtin_expect(exp, c) with EXP. 5072 setValue(&I, getValue(I.getArgOperand(0))); 5073 return 0; 5074 } 5075 5076 case Intrinsic::trap: { 5077 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5078 if (TrapFuncName.empty()) { 5079 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 5080 return 0; 5081 } 5082 TargetLowering::ArgListTy Args; 5083 TargetLowering:: 5084 CallLoweringInfo CLI(getRoot(), I.getType(), 5085 false, false, false, false, 0, CallingConv::C, 5086 /*isTailCall=*/false, 5087 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 5088 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5089 Args, DAG, getCurDebugLoc()); 5090 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI); 5091 DAG.setRoot(Result.second); 5092 return 0; 5093 } 5094 case Intrinsic::debugtrap: { 5095 DAG.setRoot(DAG.getNode(ISD::DEBUGTRAP, dl,MVT::Other, getRoot())); 5096 return 0; 5097 } 5098 case Intrinsic::uadd_with_overflow: 5099 case Intrinsic::sadd_with_overflow: 5100 case Intrinsic::usub_with_overflow: 5101 case Intrinsic::ssub_with_overflow: 5102 case Intrinsic::umul_with_overflow: 5103 case Intrinsic::smul_with_overflow: { 5104 ISD::NodeType Op; 5105 switch (Intrinsic) { 5106 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 5107 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; 5108 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; 5109 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; 5110 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; 5111 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; 5112 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; 5113 } 5114 SDValue Op1 = getValue(I.getArgOperand(0)); 5115 SDValue Op2 = getValue(I.getArgOperand(1)); 5116 5117 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 5118 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 5119 return 0; 5120 } 5121 case Intrinsic::prefetch: { 5122 SDValue Ops[5]; 5123 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5124 Ops[0] = getRoot(); 5125 Ops[1] = getValue(I.getArgOperand(0)); 5126 Ops[2] = getValue(I.getArgOperand(1)); 5127 Ops[3] = getValue(I.getArgOperand(2)); 5128 Ops[4] = getValue(I.getArgOperand(3)); 5129 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5130 DAG.getVTList(MVT::Other), 5131 &Ops[0], 5, 5132 EVT::getIntegerVT(*Context, 8), 5133 MachinePointerInfo(I.getArgOperand(0)), 5134 0, /* align */ 5135 false, /* volatile */ 5136 rw==0, /* read */ 5137 rw==1)); /* write */ 5138 return 0; 5139 } 5140 5141 case Intrinsic::invariant_start: 5142 case Intrinsic::lifetime_start: 5143 // Discard region information. 5144 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5145 return 0; 5146 case Intrinsic::invariant_end: 5147 case Intrinsic::lifetime_end: 5148 // Discard region information. 5149 return 0; 5150 } 5151} 5152 5153void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5154 bool isTailCall, 5155 MachineBasicBlock *LandingPad) { 5156 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5157 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5158 Type *RetTy = FTy->getReturnType(); 5159 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5160 MCSymbol *BeginLabel = 0; 5161 5162 TargetLowering::ArgListTy Args; 5163 TargetLowering::ArgListEntry Entry; 5164 Args.reserve(CS.arg_size()); 5165 5166 // Check whether the function can return without sret-demotion. 5167 SmallVector<ISD::OutputArg, 4> Outs; 5168 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5169 Outs, TLI); 5170 5171 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5172 DAG.getMachineFunction(), 5173 FTy->isVarArg(), Outs, 5174 FTy->getContext()); 5175 5176 SDValue DemoteStackSlot; 5177 int DemoteStackIdx = -100; 5178 5179 if (!CanLowerReturn) { 5180 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5181 FTy->getReturnType()); 5182 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5183 FTy->getReturnType()); 5184 MachineFunction &MF = DAG.getMachineFunction(); 5185 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5186 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5187 5188 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5189 Entry.Node = DemoteStackSlot; 5190 Entry.Ty = StackSlotPtrType; 5191 Entry.isSExt = false; 5192 Entry.isZExt = false; 5193 Entry.isInReg = false; 5194 Entry.isSRet = true; 5195 Entry.isNest = false; 5196 Entry.isByVal = false; 5197 Entry.Alignment = Align; 5198 Args.push_back(Entry); 5199 RetTy = Type::getVoidTy(FTy->getContext()); 5200 } 5201 5202 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5203 i != e; ++i) { 5204 const Value *V = *i; 5205 5206 // Skip empty types 5207 if (V->getType()->isEmptyTy()) 5208 continue; 5209 5210 SDValue ArgNode = getValue(V); 5211 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5212 5213 unsigned attrInd = i - CS.arg_begin() + 1; 5214 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5215 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5216 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5217 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5218 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5219 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5220 Entry.Alignment = CS.getParamAlignment(attrInd); 5221 Args.push_back(Entry); 5222 } 5223 5224 if (LandingPad) { 5225 // Insert a label before the invoke call to mark the try range. This can be 5226 // used to detect deletion of the invoke via the MachineModuleInfo. 5227 BeginLabel = MMI.getContext().CreateTempSymbol(); 5228 5229 // For SjLj, keep track of which landing pads go with which invokes 5230 // so as to maintain the ordering of pads in the LSDA. 5231 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5232 if (CallSiteIndex) { 5233 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5234 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5235 5236 // Now that the call site is handled, stop tracking it. 5237 MMI.setCurrentCallSite(0); 5238 } 5239 5240 // Both PendingLoads and PendingExports must be flushed here; 5241 // this call might not return. 5242 (void)getRoot(); 5243 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5244 } 5245 5246 // Check if target-independent constraints permit a tail call here. 5247 // Target-dependent constraints are checked within TLI.LowerCallTo. 5248 if (isTailCall && 5249 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5250 isTailCall = false; 5251 5252 // If there's a possibility that fast-isel has already selected some amount 5253 // of the current basic block, don't emit a tail call. 5254 if (isTailCall && TM.Options.EnableFastISel) 5255 isTailCall = false; 5256 5257 TargetLowering:: 5258 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG, 5259 getCurDebugLoc(), CS); 5260 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI); 5261 assert((isTailCall || Result.second.getNode()) && 5262 "Non-null chain expected with non-tail call!"); 5263 assert((Result.second.getNode() || !Result.first.getNode()) && 5264 "Null value expected with tail call!"); 5265 if (Result.first.getNode()) { 5266 setValue(CS.getInstruction(), Result.first); 5267 } else if (!CanLowerReturn && Result.second.getNode()) { 5268 // The instruction result is the result of loading from the 5269 // hidden sret parameter. 5270 SmallVector<EVT, 1> PVTs; 5271 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5272 5273 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5274 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5275 EVT PtrVT = PVTs[0]; 5276 5277 SmallVector<EVT, 4> RetTys; 5278 SmallVector<uint64_t, 4> Offsets; 5279 RetTy = FTy->getReturnType(); 5280 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets); 5281 5282 unsigned NumValues = RetTys.size(); 5283 SmallVector<SDValue, 4> Values(NumValues); 5284 SmallVector<SDValue, 4> Chains(NumValues); 5285 5286 for (unsigned i = 0; i < NumValues; ++i) { 5287 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5288 DemoteStackSlot, 5289 DAG.getConstant(Offsets[i], PtrVT)); 5290 SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add, 5291 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5292 false, false, false, 1); 5293 Values[i] = L; 5294 Chains[i] = L.getValue(1); 5295 } 5296 5297 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5298 MVT::Other, &Chains[0], NumValues); 5299 PendingLoads.push_back(Chain); 5300 5301 setValue(CS.getInstruction(), 5302 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5303 DAG.getVTList(&RetTys[0], RetTys.size()), 5304 &Values[0], Values.size())); 5305 } 5306 5307 // Assign order to nodes here. If the call does not produce a result, it won't 5308 // be mapped to a SDNode and visit() will not assign it an order number. 5309 if (!Result.second.getNode()) { 5310 // As a special case, a null chain means that a tail call has been emitted and 5311 // the DAG root is already updated. 5312 HasTailCall = true; 5313 ++SDNodeOrder; 5314 AssignOrderingToNode(DAG.getRoot().getNode()); 5315 } else { 5316 DAG.setRoot(Result.second); 5317 ++SDNodeOrder; 5318 AssignOrderingToNode(Result.second.getNode()); 5319 } 5320 5321 if (LandingPad) { 5322 // Insert a label at the end of the invoke call to mark the try range. This 5323 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5324 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5325 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5326 5327 // Inform MachineModuleInfo of range. 5328 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5329 } 5330} 5331 5332/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5333/// value is equal or not-equal to zero. 5334static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5335 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5336 UI != E; ++UI) { 5337 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5338 if (IC->isEquality()) 5339 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5340 if (C->isNullValue()) 5341 continue; 5342 // Unknown instruction. 5343 return false; 5344 } 5345 return true; 5346} 5347 5348static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5349 Type *LoadTy, 5350 SelectionDAGBuilder &Builder) { 5351 5352 // Check to see if this load can be trivially constant folded, e.g. if the 5353 // input is from a string literal. 5354 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5355 // Cast pointer to the type we really want to load. 5356 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5357 PointerType::getUnqual(LoadTy)); 5358 5359 if (const Constant *LoadCst = 5360 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5361 Builder.TD)) 5362 return Builder.getValue(LoadCst); 5363 } 5364 5365 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5366 // still constant memory, the input chain can be the entry node. 5367 SDValue Root; 5368 bool ConstantMemory = false; 5369 5370 // Do not serialize (non-volatile) loads of constant memory with anything. 5371 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5372 Root = Builder.DAG.getEntryNode(); 5373 ConstantMemory = true; 5374 } else { 5375 // Do not serialize non-volatile loads against each other. 5376 Root = Builder.DAG.getRoot(); 5377 } 5378 5379 SDValue Ptr = Builder.getValue(PtrVal); 5380 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5381 Ptr, MachinePointerInfo(PtrVal), 5382 false /*volatile*/, 5383 false /*nontemporal*/, 5384 false /*isinvariant*/, 1 /* align=1 */); 5385 5386 if (!ConstantMemory) 5387 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5388 return LoadVal; 5389} 5390 5391 5392/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5393/// If so, return true and lower it, otherwise return false and it will be 5394/// lowered like a normal call. 5395bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5396 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5397 if (I.getNumArgOperands() != 3) 5398 return false; 5399 5400 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5401 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5402 !I.getArgOperand(2)->getType()->isIntegerTy() || 5403 !I.getType()->isIntegerTy()) 5404 return false; 5405 5406 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5407 5408 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5409 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5410 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5411 bool ActuallyDoIt = true; 5412 MVT LoadVT; 5413 Type *LoadTy; 5414 switch (Size->getZExtValue()) { 5415 default: 5416 LoadVT = MVT::Other; 5417 LoadTy = 0; 5418 ActuallyDoIt = false; 5419 break; 5420 case 2: 5421 LoadVT = MVT::i16; 5422 LoadTy = Type::getInt16Ty(Size->getContext()); 5423 break; 5424 case 4: 5425 LoadVT = MVT::i32; 5426 LoadTy = Type::getInt32Ty(Size->getContext()); 5427 break; 5428 case 8: 5429 LoadVT = MVT::i64; 5430 LoadTy = Type::getInt64Ty(Size->getContext()); 5431 break; 5432 /* 5433 case 16: 5434 LoadVT = MVT::v4i32; 5435 LoadTy = Type::getInt32Ty(Size->getContext()); 5436 LoadTy = VectorType::get(LoadTy, 4); 5437 break; 5438 */ 5439 } 5440 5441 // This turns into unaligned loads. We only do this if the target natively 5442 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5443 // we'll only produce a small number of byte loads. 5444 5445 // Require that we can find a legal MVT, and only do this if the target 5446 // supports unaligned loads of that type. Expanding into byte loads would 5447 // bloat the code. 5448 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5449 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5450 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5451 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5452 ActuallyDoIt = false; 5453 } 5454 5455 if (ActuallyDoIt) { 5456 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5457 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5458 5459 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5460 ISD::SETNE); 5461 EVT CallVT = TLI.getValueType(I.getType(), true); 5462 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5463 return true; 5464 } 5465 } 5466 5467 5468 return false; 5469} 5470 5471 5472void SelectionDAGBuilder::visitCall(const CallInst &I) { 5473 // Handle inline assembly differently. 5474 if (isa<InlineAsm>(I.getCalledValue())) { 5475 visitInlineAsm(&I); 5476 return; 5477 } 5478 5479 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5480 ComputeUsesVAFloatArgument(I, &MMI); 5481 5482 const char *RenameFn = 0; 5483 if (Function *F = I.getCalledFunction()) { 5484 if (F->isDeclaration()) { 5485 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5486 if (unsigned IID = II->getIntrinsicID(F)) { 5487 RenameFn = visitIntrinsicCall(I, IID); 5488 if (!RenameFn) 5489 return; 5490 } 5491 } 5492 if (unsigned IID = F->getIntrinsicID()) { 5493 RenameFn = visitIntrinsicCall(I, IID); 5494 if (!RenameFn) 5495 return; 5496 } 5497 } 5498 5499 // Check for well-known libc/libm calls. If the function is internal, it 5500 // can't be a library call. 5501 if (!F->hasLocalLinkage() && F->hasName()) { 5502 StringRef Name = F->getName(); 5503 if ((LibInfo->has(LibFunc::copysign) && Name == "copysign") || 5504 (LibInfo->has(LibFunc::copysignf) && Name == "copysignf") || 5505 (LibInfo->has(LibFunc::copysignl) && Name == "copysignl")) { 5506 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5507 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5508 I.getType() == I.getArgOperand(0)->getType() && 5509 I.getType() == I.getArgOperand(1)->getType()) { 5510 SDValue LHS = getValue(I.getArgOperand(0)); 5511 SDValue RHS = getValue(I.getArgOperand(1)); 5512 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5513 LHS.getValueType(), LHS, RHS)); 5514 return; 5515 } 5516 } else if ((LibInfo->has(LibFunc::fabs) && Name == "fabs") || 5517 (LibInfo->has(LibFunc::fabsf) && Name == "fabsf") || 5518 (LibInfo->has(LibFunc::fabsl) && Name == "fabsl")) { 5519 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5520 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5521 I.getType() == I.getArgOperand(0)->getType()) { 5522 SDValue Tmp = getValue(I.getArgOperand(0)); 5523 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5524 Tmp.getValueType(), Tmp)); 5525 return; 5526 } 5527 } else if ((LibInfo->has(LibFunc::sin) && Name == "sin") || 5528 (LibInfo->has(LibFunc::sinf) && Name == "sinf") || 5529 (LibInfo->has(LibFunc::sinl) && Name == "sinl")) { 5530 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5531 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5532 I.getType() == I.getArgOperand(0)->getType() && 5533 I.onlyReadsMemory()) { 5534 SDValue Tmp = getValue(I.getArgOperand(0)); 5535 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5536 Tmp.getValueType(), Tmp)); 5537 return; 5538 } 5539 } else if ((LibInfo->has(LibFunc::cos) && Name == "cos") || 5540 (LibInfo->has(LibFunc::cosf) && Name == "cosf") || 5541 (LibInfo->has(LibFunc::cosl) && Name == "cosl")) { 5542 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5543 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5544 I.getType() == I.getArgOperand(0)->getType() && 5545 I.onlyReadsMemory()) { 5546 SDValue Tmp = getValue(I.getArgOperand(0)); 5547 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5548 Tmp.getValueType(), Tmp)); 5549 return; 5550 } 5551 } else if ((LibInfo->has(LibFunc::sqrt) && Name == "sqrt") || 5552 (LibInfo->has(LibFunc::sqrtf) && Name == "sqrtf") || 5553 (LibInfo->has(LibFunc::sqrtl) && Name == "sqrtl")) { 5554 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5555 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5556 I.getType() == I.getArgOperand(0)->getType() && 5557 I.onlyReadsMemory()) { 5558 SDValue Tmp = getValue(I.getArgOperand(0)); 5559 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5560 Tmp.getValueType(), Tmp)); 5561 return; 5562 } 5563 } else if ((LibInfo->has(LibFunc::floor) && Name == "floor") || 5564 (LibInfo->has(LibFunc::floorf) && Name == "floorf") || 5565 (LibInfo->has(LibFunc::floorl) && Name == "floorl")) { 5566 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5567 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5568 I.getType() == I.getArgOperand(0)->getType()) { 5569 SDValue Tmp = getValue(I.getArgOperand(0)); 5570 setValue(&I, DAG.getNode(ISD::FFLOOR, getCurDebugLoc(), 5571 Tmp.getValueType(), Tmp)); 5572 return; 5573 } 5574 } else if ((LibInfo->has(LibFunc::nearbyint) && Name == "nearbyint") || 5575 (LibInfo->has(LibFunc::nearbyintf) && Name == "nearbyintf") || 5576 (LibInfo->has(LibFunc::nearbyintl) && Name == "nearbyintl")) { 5577 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5578 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5579 I.getType() == I.getArgOperand(0)->getType()) { 5580 SDValue Tmp = getValue(I.getArgOperand(0)); 5581 setValue(&I, DAG.getNode(ISD::FNEARBYINT, getCurDebugLoc(), 5582 Tmp.getValueType(), Tmp)); 5583 return; 5584 } 5585 } else if ((LibInfo->has(LibFunc::ceil) && Name == "ceil") || 5586 (LibInfo->has(LibFunc::ceilf) && Name == "ceilf") || 5587 (LibInfo->has(LibFunc::ceill) && Name == "ceill")) { 5588 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5589 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5590 I.getType() == I.getArgOperand(0)->getType()) { 5591 SDValue Tmp = getValue(I.getArgOperand(0)); 5592 setValue(&I, DAG.getNode(ISD::FCEIL, getCurDebugLoc(), 5593 Tmp.getValueType(), Tmp)); 5594 return; 5595 } 5596 } else if ((LibInfo->has(LibFunc::rint) && Name == "rint") || 5597 (LibInfo->has(LibFunc::rintf) && Name == "rintf") || 5598 (LibInfo->has(LibFunc::rintl) && Name == "rintl")) { 5599 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5600 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5601 I.getType() == I.getArgOperand(0)->getType()) { 5602 SDValue Tmp = getValue(I.getArgOperand(0)); 5603 setValue(&I, DAG.getNode(ISD::FRINT, getCurDebugLoc(), 5604 Tmp.getValueType(), Tmp)); 5605 return; 5606 } 5607 } else if ((LibInfo->has(LibFunc::trunc) && Name == "trunc") || 5608 (LibInfo->has(LibFunc::truncf) && Name == "truncf") || 5609 (LibInfo->has(LibFunc::truncl) && Name == "truncl")) { 5610 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5611 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5612 I.getType() == I.getArgOperand(0)->getType()) { 5613 SDValue Tmp = getValue(I.getArgOperand(0)); 5614 setValue(&I, DAG.getNode(ISD::FTRUNC, getCurDebugLoc(), 5615 Tmp.getValueType(), Tmp)); 5616 return; 5617 } 5618 } else if ((LibInfo->has(LibFunc::log2) && Name == "log2") || 5619 (LibInfo->has(LibFunc::log2f) && Name == "log2f") || 5620 (LibInfo->has(LibFunc::log2l) && Name == "log2l")) { 5621 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5622 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5623 I.getType() == I.getArgOperand(0)->getType() && 5624 I.onlyReadsMemory()) { 5625 SDValue Tmp = getValue(I.getArgOperand(0)); 5626 setValue(&I, DAG.getNode(ISD::FLOG2, getCurDebugLoc(), 5627 Tmp.getValueType(), Tmp)); 5628 return; 5629 } 5630 } else if ((LibInfo->has(LibFunc::exp2) && Name == "exp2") || 5631 (LibInfo->has(LibFunc::exp2f) && Name == "exp2f") || 5632 (LibInfo->has(LibFunc::exp2l) && Name == "exp2l")) { 5633 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5634 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5635 I.getType() == I.getArgOperand(0)->getType() && 5636 I.onlyReadsMemory()) { 5637 SDValue Tmp = getValue(I.getArgOperand(0)); 5638 setValue(&I, DAG.getNode(ISD::FEXP2, getCurDebugLoc(), 5639 Tmp.getValueType(), Tmp)); 5640 return; 5641 } 5642 } else if (Name == "memcmp") { 5643 if (visitMemCmpCall(I)) 5644 return; 5645 } 5646 } 5647 } 5648 5649 SDValue Callee; 5650 if (!RenameFn) 5651 Callee = getValue(I.getCalledValue()); 5652 else 5653 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5654 5655 // Check if we can potentially perform a tail call. More detailed checking is 5656 // be done within LowerCallTo, after more information about the call is known. 5657 LowerCallTo(&I, Callee, I.isTailCall()); 5658} 5659 5660namespace { 5661 5662/// AsmOperandInfo - This contains information for each constraint that we are 5663/// lowering. 5664class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5665public: 5666 /// CallOperand - If this is the result output operand or a clobber 5667 /// this is null, otherwise it is the incoming operand to the CallInst. 5668 /// This gets modified as the asm is processed. 5669 SDValue CallOperand; 5670 5671 /// AssignedRegs - If this is a register or register class operand, this 5672 /// contains the set of register corresponding to the operand. 5673 RegsForValue AssignedRegs; 5674 5675 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5676 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5677 } 5678 5679 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5680 /// corresponds to. If there is no Value* for this operand, it returns 5681 /// MVT::Other. 5682 EVT getCallOperandValEVT(LLVMContext &Context, 5683 const TargetLowering &TLI, 5684 const TargetData *TD) const { 5685 if (CallOperandVal == 0) return MVT::Other; 5686 5687 if (isa<BasicBlock>(CallOperandVal)) 5688 return TLI.getPointerTy(); 5689 5690 llvm::Type *OpTy = CallOperandVal->getType(); 5691 5692 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5693 // If this is an indirect operand, the operand is a pointer to the 5694 // accessed type. 5695 if (isIndirect) { 5696 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5697 if (!PtrTy) 5698 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5699 OpTy = PtrTy->getElementType(); 5700 } 5701 5702 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5703 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5704 if (STy->getNumElements() == 1) 5705 OpTy = STy->getElementType(0); 5706 5707 // If OpTy is not a single value, it may be a struct/union that we 5708 // can tile with integers. 5709 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5710 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5711 switch (BitSize) { 5712 default: break; 5713 case 1: 5714 case 8: 5715 case 16: 5716 case 32: 5717 case 64: 5718 case 128: 5719 OpTy = IntegerType::get(Context, BitSize); 5720 break; 5721 } 5722 } 5723 5724 return TLI.getValueType(OpTy, true); 5725 } 5726}; 5727 5728typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5729 5730} // end anonymous namespace 5731 5732/// GetRegistersForValue - Assign registers (virtual or physical) for the 5733/// specified operand. We prefer to assign virtual registers, to allow the 5734/// register allocator to handle the assignment process. However, if the asm 5735/// uses features that we can't model on machineinstrs, we have SDISel do the 5736/// allocation. This produces generally horrible, but correct, code. 5737/// 5738/// OpInfo describes the operand. 5739/// 5740static void GetRegistersForValue(SelectionDAG &DAG, 5741 const TargetLowering &TLI, 5742 DebugLoc DL, 5743 SDISelAsmOperandInfo &OpInfo) { 5744 LLVMContext &Context = *DAG.getContext(); 5745 5746 MachineFunction &MF = DAG.getMachineFunction(); 5747 SmallVector<unsigned, 4> Regs; 5748 5749 // If this is a constraint for a single physreg, or a constraint for a 5750 // register class, find it. 5751 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5752 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5753 OpInfo.ConstraintVT); 5754 5755 unsigned NumRegs = 1; 5756 if (OpInfo.ConstraintVT != MVT::Other) { 5757 // If this is a FP input in an integer register (or visa versa) insert a bit 5758 // cast of the input value. More generally, handle any case where the input 5759 // value disagrees with the register class we plan to stick this in. 5760 if (OpInfo.Type == InlineAsm::isInput && 5761 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5762 // Try to convert to the first EVT that the reg class contains. If the 5763 // types are identical size, use a bitcast to convert (e.g. two differing 5764 // vector types). 5765 EVT RegVT = *PhysReg.second->vt_begin(); 5766 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5767 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5768 RegVT, OpInfo.CallOperand); 5769 OpInfo.ConstraintVT = RegVT; 5770 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5771 // If the input is a FP value and we want it in FP registers, do a 5772 // bitcast to the corresponding integer type. This turns an f64 value 5773 // into i64, which can be passed with two i32 values on a 32-bit 5774 // machine. 5775 RegVT = EVT::getIntegerVT(Context, 5776 OpInfo.ConstraintVT.getSizeInBits()); 5777 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5778 RegVT, OpInfo.CallOperand); 5779 OpInfo.ConstraintVT = RegVT; 5780 } 5781 } 5782 5783 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5784 } 5785 5786 EVT RegVT; 5787 EVT ValueVT = OpInfo.ConstraintVT; 5788 5789 // If this is a constraint for a specific physical register, like {r17}, 5790 // assign it now. 5791 if (unsigned AssignedReg = PhysReg.first) { 5792 const TargetRegisterClass *RC = PhysReg.second; 5793 if (OpInfo.ConstraintVT == MVT::Other) 5794 ValueVT = *RC->vt_begin(); 5795 5796 // Get the actual register value type. This is important, because the user 5797 // may have asked for (e.g.) the AX register in i32 type. We need to 5798 // remember that AX is actually i16 to get the right extension. 5799 RegVT = *RC->vt_begin(); 5800 5801 // This is a explicit reference to a physical register. 5802 Regs.push_back(AssignedReg); 5803 5804 // If this is an expanded reference, add the rest of the regs to Regs. 5805 if (NumRegs != 1) { 5806 TargetRegisterClass::iterator I = RC->begin(); 5807 for (; *I != AssignedReg; ++I) 5808 assert(I != RC->end() && "Didn't find reg!"); 5809 5810 // Already added the first reg. 5811 --NumRegs; ++I; 5812 for (; NumRegs; --NumRegs, ++I) { 5813 assert(I != RC->end() && "Ran out of registers to allocate!"); 5814 Regs.push_back(*I); 5815 } 5816 } 5817 5818 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5819 return; 5820 } 5821 5822 // Otherwise, if this was a reference to an LLVM register class, create vregs 5823 // for this reference. 5824 if (const TargetRegisterClass *RC = PhysReg.second) { 5825 RegVT = *RC->vt_begin(); 5826 if (OpInfo.ConstraintVT == MVT::Other) 5827 ValueVT = RegVT; 5828 5829 // Create the appropriate number of virtual registers. 5830 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5831 for (; NumRegs; --NumRegs) 5832 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5833 5834 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5835 return; 5836 } 5837 5838 // Otherwise, we couldn't allocate enough registers for this. 5839} 5840 5841/// visitInlineAsm - Handle a call to an InlineAsm object. 5842/// 5843void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5844 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5845 5846 /// ConstraintOperands - Information about all of the constraints. 5847 SDISelAsmOperandInfoVector ConstraintOperands; 5848 5849 TargetLowering::AsmOperandInfoVector 5850 TargetConstraints = TLI.ParseConstraints(CS); 5851 5852 bool hasMemory = false; 5853 5854 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5855 unsigned ResNo = 0; // ResNo - The result number of the next output. 5856 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5857 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5858 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5859 5860 EVT OpVT = MVT::Other; 5861 5862 // Compute the value type for each operand. 5863 switch (OpInfo.Type) { 5864 case InlineAsm::isOutput: 5865 // Indirect outputs just consume an argument. 5866 if (OpInfo.isIndirect) { 5867 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5868 break; 5869 } 5870 5871 // The return value of the call is this value. As such, there is no 5872 // corresponding argument. 5873 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5874 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5875 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5876 } else { 5877 assert(ResNo == 0 && "Asm only has one result!"); 5878 OpVT = TLI.getValueType(CS.getType()); 5879 } 5880 ++ResNo; 5881 break; 5882 case InlineAsm::isInput: 5883 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5884 break; 5885 case InlineAsm::isClobber: 5886 // Nothing to do. 5887 break; 5888 } 5889 5890 // If this is an input or an indirect output, process the call argument. 5891 // BasicBlocks are labels, currently appearing only in asm's. 5892 if (OpInfo.CallOperandVal) { 5893 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5894 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5895 } else { 5896 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5897 } 5898 5899 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5900 } 5901 5902 OpInfo.ConstraintVT = OpVT; 5903 5904 // Indirect operand accesses access memory. 5905 if (OpInfo.isIndirect) 5906 hasMemory = true; 5907 else { 5908 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5909 TargetLowering::ConstraintType 5910 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5911 if (CType == TargetLowering::C_Memory) { 5912 hasMemory = true; 5913 break; 5914 } 5915 } 5916 } 5917 } 5918 5919 SDValue Chain, Flag; 5920 5921 // We won't need to flush pending loads if this asm doesn't touch 5922 // memory and is nonvolatile. 5923 if (hasMemory || IA->hasSideEffects()) 5924 Chain = getRoot(); 5925 else 5926 Chain = DAG.getRoot(); 5927 5928 // Second pass over the constraints: compute which constraint option to use 5929 // and assign registers to constraints that want a specific physreg. 5930 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5931 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5932 5933 // If this is an output operand with a matching input operand, look up the 5934 // matching input. If their types mismatch, e.g. one is an integer, the 5935 // other is floating point, or their sizes are different, flag it as an 5936 // error. 5937 if (OpInfo.hasMatchingInput()) { 5938 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5939 5940 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5941 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5942 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5943 OpInfo.ConstraintVT); 5944 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5945 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 5946 Input.ConstraintVT); 5947 if ((OpInfo.ConstraintVT.isInteger() != 5948 Input.ConstraintVT.isInteger()) || 5949 (MatchRC.second != InputRC.second)) { 5950 report_fatal_error("Unsupported asm: input constraint" 5951 " with a matching output constraint of" 5952 " incompatible type!"); 5953 } 5954 Input.ConstraintVT = OpInfo.ConstraintVT; 5955 } 5956 } 5957 5958 // Compute the constraint code and ConstraintType to use. 5959 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5960 5961 // If this is a memory input, and if the operand is not indirect, do what we 5962 // need to to provide an address for the memory input. 5963 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5964 !OpInfo.isIndirect) { 5965 assert((OpInfo.isMultipleAlternative || 5966 (OpInfo.Type == InlineAsm::isInput)) && 5967 "Can only indirectify direct input operands!"); 5968 5969 // Memory operands really want the address of the value. If we don't have 5970 // an indirect input, put it in the constpool if we can, otherwise spill 5971 // it to a stack slot. 5972 // TODO: This isn't quite right. We need to handle these according to 5973 // the addressing mode that the constraint wants. Also, this may take 5974 // an additional register for the computation and we don't want that 5975 // either. 5976 5977 // If the operand is a float, integer, or vector constant, spill to a 5978 // constant pool entry to get its address. 5979 const Value *OpVal = OpInfo.CallOperandVal; 5980 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5981 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { 5982 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5983 TLI.getPointerTy()); 5984 } else { 5985 // Otherwise, create a stack slot and emit a store to it before the 5986 // asm. 5987 Type *Ty = OpVal->getType(); 5988 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5989 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5990 MachineFunction &MF = DAG.getMachineFunction(); 5991 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5992 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5993 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5994 OpInfo.CallOperand, StackSlot, 5995 MachinePointerInfo::getFixedStack(SSFI), 5996 false, false, 0); 5997 OpInfo.CallOperand = StackSlot; 5998 } 5999 6000 // There is no longer a Value* corresponding to this operand. 6001 OpInfo.CallOperandVal = 0; 6002 6003 // It is now an indirect operand. 6004 OpInfo.isIndirect = true; 6005 } 6006 6007 // If this constraint is for a specific register, allocate it before 6008 // anything else. 6009 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6010 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6011 } 6012 6013 // Second pass - Loop over all of the operands, assigning virtual or physregs 6014 // to register class operands. 6015 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6016 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6017 6018 // C_Register operands have already been allocated, Other/Memory don't need 6019 // to be. 6020 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6021 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6022 } 6023 6024 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6025 std::vector<SDValue> AsmNodeOperands; 6026 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6027 AsmNodeOperands.push_back( 6028 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6029 TLI.getPointerTy())); 6030 6031 // If we have a !srcloc metadata node associated with it, we want to attach 6032 // this to the ultimately generated inline asm machineinstr. To do this, we 6033 // pass in the third operand as this (potentially null) inline asm MDNode. 6034 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6035 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6036 6037 // Remember the HasSideEffect and AlignStack bits as operand 3. 6038 unsigned ExtraInfo = 0; 6039 if (IA->hasSideEffects()) 6040 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6041 if (IA->isAlignStack()) 6042 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6043 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6044 TLI.getPointerTy())); 6045 6046 // Loop over all of the inputs, copying the operand values into the 6047 // appropriate registers and processing the output regs. 6048 RegsForValue RetValRegs; 6049 6050 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6051 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6052 6053 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6054 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6055 6056 switch (OpInfo.Type) { 6057 case InlineAsm::isOutput: { 6058 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6059 OpInfo.ConstraintType != TargetLowering::C_Register) { 6060 // Memory output, or 'other' output (e.g. 'X' constraint). 6061 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6062 6063 // Add information to the INLINEASM node to know about this output. 6064 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6065 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6066 TLI.getPointerTy())); 6067 AsmNodeOperands.push_back(OpInfo.CallOperand); 6068 break; 6069 } 6070 6071 // Otherwise, this is a register or register class output. 6072 6073 // Copy the output from the appropriate register. Find a register that 6074 // we can use. 6075 if (OpInfo.AssignedRegs.Regs.empty()) { 6076 LLVMContext &Ctx = *DAG.getContext(); 6077 Ctx.emitError(CS.getInstruction(), 6078 "couldn't allocate output register for constraint '" + 6079 Twine(OpInfo.ConstraintCode) + "'"); 6080 break; 6081 } 6082 6083 // If this is an indirect operand, store through the pointer after the 6084 // asm. 6085 if (OpInfo.isIndirect) { 6086 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6087 OpInfo.CallOperandVal)); 6088 } else { 6089 // This is the result value of the call. 6090 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6091 // Concatenate this output onto the outputs list. 6092 RetValRegs.append(OpInfo.AssignedRegs); 6093 } 6094 6095 // Add information to the INLINEASM node to know that this register is 6096 // set. 6097 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6098 InlineAsm::Kind_RegDefEarlyClobber : 6099 InlineAsm::Kind_RegDef, 6100 false, 6101 0, 6102 DAG, 6103 AsmNodeOperands); 6104 break; 6105 } 6106 case InlineAsm::isInput: { 6107 SDValue InOperandVal = OpInfo.CallOperand; 6108 6109 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6110 // If this is required to match an output register we have already set, 6111 // just use its register. 6112 unsigned OperandNo = OpInfo.getMatchedOperand(); 6113 6114 // Scan until we find the definition we already emitted of this operand. 6115 // When we find it, create a RegsForValue operand. 6116 unsigned CurOp = InlineAsm::Op_FirstOperand; 6117 for (; OperandNo; --OperandNo) { 6118 // Advance to the next operand. 6119 unsigned OpFlag = 6120 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6121 assert((InlineAsm::isRegDefKind(OpFlag) || 6122 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6123 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6124 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6125 } 6126 6127 unsigned OpFlag = 6128 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6129 if (InlineAsm::isRegDefKind(OpFlag) || 6130 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6131 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6132 if (OpInfo.isIndirect) { 6133 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6134 LLVMContext &Ctx = *DAG.getContext(); 6135 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6136 " don't know how to handle tied " 6137 "indirect register inputs"); 6138 } 6139 6140 RegsForValue MatchedRegs; 6141 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6142 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6143 MatchedRegs.RegVTs.push_back(RegVT); 6144 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6145 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6146 i != e; ++i) 6147 MatchedRegs.Regs.push_back 6148 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6149 6150 // Use the produced MatchedRegs object to 6151 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6152 Chain, &Flag); 6153 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6154 true, OpInfo.getMatchedOperand(), 6155 DAG, AsmNodeOperands); 6156 break; 6157 } 6158 6159 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6160 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6161 "Unexpected number of operands"); 6162 // Add information to the INLINEASM node to know about this input. 6163 // See InlineAsm.h isUseOperandTiedToDef. 6164 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6165 OpInfo.getMatchedOperand()); 6166 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6167 TLI.getPointerTy())); 6168 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6169 break; 6170 } 6171 6172 // Treat indirect 'X' constraint as memory. 6173 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6174 OpInfo.isIndirect) 6175 OpInfo.ConstraintType = TargetLowering::C_Memory; 6176 6177 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6178 std::vector<SDValue> Ops; 6179 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6180 Ops, DAG); 6181 if (Ops.empty()) { 6182 LLVMContext &Ctx = *DAG.getContext(); 6183 Ctx.emitError(CS.getInstruction(), 6184 "invalid operand for inline asm constraint '" + 6185 Twine(OpInfo.ConstraintCode) + "'"); 6186 break; 6187 } 6188 6189 // Add information to the INLINEASM node to know about this input. 6190 unsigned ResOpType = 6191 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6192 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6193 TLI.getPointerTy())); 6194 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6195 break; 6196 } 6197 6198 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6199 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6200 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6201 "Memory operands expect pointer values"); 6202 6203 // Add information to the INLINEASM node to know about this input. 6204 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6205 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6206 TLI.getPointerTy())); 6207 AsmNodeOperands.push_back(InOperandVal); 6208 break; 6209 } 6210 6211 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6212 OpInfo.ConstraintType == TargetLowering::C_Register) && 6213 "Unknown constraint type!"); 6214 assert(!OpInfo.isIndirect && 6215 "Don't know how to handle indirect register inputs yet!"); 6216 6217 // Copy the input into the appropriate registers. 6218 if (OpInfo.AssignedRegs.Regs.empty()) { 6219 LLVMContext &Ctx = *DAG.getContext(); 6220 Ctx.emitError(CS.getInstruction(), 6221 "couldn't allocate input reg for constraint '" + 6222 Twine(OpInfo.ConstraintCode) + "'"); 6223 break; 6224 } 6225 6226 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6227 Chain, &Flag); 6228 6229 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6230 DAG, AsmNodeOperands); 6231 break; 6232 } 6233 case InlineAsm::isClobber: { 6234 // Add the clobbered value to the operand list, so that the register 6235 // allocator is aware that the physreg got clobbered. 6236 if (!OpInfo.AssignedRegs.Regs.empty()) 6237 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6238 false, 0, DAG, 6239 AsmNodeOperands); 6240 break; 6241 } 6242 } 6243 } 6244 6245 // Finish up input operands. Set the input chain and add the flag last. 6246 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6247 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6248 6249 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6250 DAG.getVTList(MVT::Other, MVT::Glue), 6251 &AsmNodeOperands[0], AsmNodeOperands.size()); 6252 Flag = Chain.getValue(1); 6253 6254 // If this asm returns a register value, copy the result from that register 6255 // and set it as the value of the call. 6256 if (!RetValRegs.Regs.empty()) { 6257 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6258 Chain, &Flag); 6259 6260 // FIXME: Why don't we do this for inline asms with MRVs? 6261 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6262 EVT ResultType = TLI.getValueType(CS.getType()); 6263 6264 // If any of the results of the inline asm is a vector, it may have the 6265 // wrong width/num elts. This can happen for register classes that can 6266 // contain multiple different value types. The preg or vreg allocated may 6267 // not have the same VT as was expected. Convert it to the right type 6268 // with bit_convert. 6269 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6270 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6271 ResultType, Val); 6272 6273 } else if (ResultType != Val.getValueType() && 6274 ResultType.isInteger() && Val.getValueType().isInteger()) { 6275 // If a result value was tied to an input value, the computed result may 6276 // have a wider width than the expected result. Extract the relevant 6277 // portion. 6278 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6279 } 6280 6281 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6282 } 6283 6284 setValue(CS.getInstruction(), Val); 6285 // Don't need to use this as a chain in this case. 6286 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6287 return; 6288 } 6289 6290 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6291 6292 // Process indirect outputs, first output all of the flagged copies out of 6293 // physregs. 6294 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6295 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6296 const Value *Ptr = IndirectStoresToEmit[i].second; 6297 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6298 Chain, &Flag); 6299 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6300 } 6301 6302 // Emit the non-flagged stores from the physregs. 6303 SmallVector<SDValue, 8> OutChains; 6304 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6305 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6306 StoresToEmit[i].first, 6307 getValue(StoresToEmit[i].second), 6308 MachinePointerInfo(StoresToEmit[i].second), 6309 false, false, 0); 6310 OutChains.push_back(Val); 6311 } 6312 6313 if (!OutChains.empty()) 6314 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6315 &OutChains[0], OutChains.size()); 6316 6317 DAG.setRoot(Chain); 6318} 6319 6320void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6321 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6322 MVT::Other, getRoot(), 6323 getValue(I.getArgOperand(0)), 6324 DAG.getSrcValue(I.getArgOperand(0)))); 6325} 6326 6327void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6328 const TargetData &TD = *TLI.getTargetData(); 6329 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6330 getRoot(), getValue(I.getOperand(0)), 6331 DAG.getSrcValue(I.getOperand(0)), 6332 TD.getABITypeAlignment(I.getType())); 6333 setValue(&I, V); 6334 DAG.setRoot(V.getValue(1)); 6335} 6336 6337void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6338 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6339 MVT::Other, getRoot(), 6340 getValue(I.getArgOperand(0)), 6341 DAG.getSrcValue(I.getArgOperand(0)))); 6342} 6343 6344void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6345 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6346 MVT::Other, getRoot(), 6347 getValue(I.getArgOperand(0)), 6348 getValue(I.getArgOperand(1)), 6349 DAG.getSrcValue(I.getArgOperand(0)), 6350 DAG.getSrcValue(I.getArgOperand(1)))); 6351} 6352 6353/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6354/// implementation, which just calls LowerCall. 6355/// FIXME: When all targets are 6356/// migrated to using LowerCall, this hook should be integrated into SDISel. 6357std::pair<SDValue, SDValue> 6358TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { 6359 // Handle all of the outgoing arguments. 6360 CLI.Outs.clear(); 6361 CLI.OutVals.clear(); 6362 ArgListTy &Args = CLI.Args; 6363 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6364 SmallVector<EVT, 4> ValueVTs; 6365 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6366 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6367 Value != NumValues; ++Value) { 6368 EVT VT = ValueVTs[Value]; 6369 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); 6370 SDValue Op = SDValue(Args[i].Node.getNode(), 6371 Args[i].Node.getResNo() + Value); 6372 ISD::ArgFlagsTy Flags; 6373 unsigned OriginalAlignment = 6374 getTargetData()->getABITypeAlignment(ArgTy); 6375 6376 if (Args[i].isZExt) 6377 Flags.setZExt(); 6378 if (Args[i].isSExt) 6379 Flags.setSExt(); 6380 if (Args[i].isInReg) 6381 Flags.setInReg(); 6382 if (Args[i].isSRet) 6383 Flags.setSRet(); 6384 if (Args[i].isByVal) { 6385 Flags.setByVal(); 6386 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6387 Type *ElementTy = Ty->getElementType(); 6388 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6389 // For ByVal, alignment should come from FE. BE will guess if this 6390 // info is not there but there are cases it cannot get right. 6391 unsigned FrameAlign; 6392 if (Args[i].Alignment) 6393 FrameAlign = Args[i].Alignment; 6394 else 6395 FrameAlign = getByValTypeAlignment(ElementTy); 6396 Flags.setByValAlign(FrameAlign); 6397 } 6398 if (Args[i].isNest) 6399 Flags.setNest(); 6400 Flags.setOrigAlign(OriginalAlignment); 6401 6402 EVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT); 6403 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT); 6404 SmallVector<SDValue, 4> Parts(NumParts); 6405 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6406 6407 if (Args[i].isSExt) 6408 ExtendKind = ISD::SIGN_EXTEND; 6409 else if (Args[i].isZExt) 6410 ExtendKind = ISD::ZERO_EXTEND; 6411 6412 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, 6413 PartVT, ExtendKind); 6414 6415 for (unsigned j = 0; j != NumParts; ++j) { 6416 // if it isn't first piece, alignment must be 1 6417 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6418 i < CLI.NumFixedArgs); 6419 if (NumParts > 1 && j == 0) 6420 MyFlags.Flags.setSplit(); 6421 else if (j != 0) 6422 MyFlags.Flags.setOrigAlign(1); 6423 6424 CLI.Outs.push_back(MyFlags); 6425 CLI.OutVals.push_back(Parts[j]); 6426 } 6427 } 6428 } 6429 6430 // Handle the incoming return values from the call. 6431 CLI.Ins.clear(); 6432 SmallVector<EVT, 4> RetTys; 6433 ComputeValueVTs(*this, CLI.RetTy, RetTys); 6434 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6435 EVT VT = RetTys[I]; 6436 EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6437 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6438 for (unsigned i = 0; i != NumRegs; ++i) { 6439 ISD::InputArg MyFlags; 6440 MyFlags.VT = RegisterVT.getSimpleVT(); 6441 MyFlags.Used = CLI.IsReturnValueUsed; 6442 if (CLI.RetSExt) 6443 MyFlags.Flags.setSExt(); 6444 if (CLI.RetZExt) 6445 MyFlags.Flags.setZExt(); 6446 if (CLI.IsInReg) 6447 MyFlags.Flags.setInReg(); 6448 CLI.Ins.push_back(MyFlags); 6449 } 6450 } 6451 6452 SmallVector<SDValue, 4> InVals; 6453 CLI.Chain = LowerCall(CLI, InVals); 6454 6455 // Verify that the target's LowerCall behaved as expected. 6456 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && 6457 "LowerCall didn't return a valid chain!"); 6458 assert((!CLI.IsTailCall || InVals.empty()) && 6459 "LowerCall emitted a return value for a tail call!"); 6460 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && 6461 "LowerCall didn't emit the correct number of values!"); 6462 6463 // For a tail call, the return value is merely live-out and there aren't 6464 // any nodes in the DAG representing it. Return a special value to 6465 // indicate that a tail call has been emitted and no more Instructions 6466 // should be processed in the current block. 6467 if (CLI.IsTailCall) { 6468 CLI.DAG.setRoot(CLI.Chain); 6469 return std::make_pair(SDValue(), SDValue()); 6470 } 6471 6472 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { 6473 assert(InVals[i].getNode() && 6474 "LowerCall emitted a null value!"); 6475 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && 6476 "LowerCall emitted a value with the wrong type!"); 6477 }); 6478 6479 // Collect the legal value parts into potentially illegal values 6480 // that correspond to the original function's return values. 6481 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6482 if (CLI.RetSExt) 6483 AssertOp = ISD::AssertSext; 6484 else if (CLI.RetZExt) 6485 AssertOp = ISD::AssertZext; 6486 SmallVector<SDValue, 4> ReturnValues; 6487 unsigned CurReg = 0; 6488 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6489 EVT VT = RetTys[I]; 6490 EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6491 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6492 6493 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], 6494 NumRegs, RegisterVT, VT, 6495 AssertOp)); 6496 CurReg += NumRegs; 6497 } 6498 6499 // For a function returning void, there is no return value. We can't create 6500 // such a node, so we just return a null return value in that case. In 6501 // that case, nothing will actually look at the value. 6502 if (ReturnValues.empty()) 6503 return std::make_pair(SDValue(), CLI.Chain); 6504 6505 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, 6506 CLI.DAG.getVTList(&RetTys[0], RetTys.size()), 6507 &ReturnValues[0], ReturnValues.size()); 6508 return std::make_pair(Res, CLI.Chain); 6509} 6510 6511void TargetLowering::LowerOperationWrapper(SDNode *N, 6512 SmallVectorImpl<SDValue> &Results, 6513 SelectionDAG &DAG) const { 6514 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6515 if (Res.getNode()) 6516 Results.push_back(Res); 6517} 6518 6519SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6520 llvm_unreachable("LowerOperation not implemented for this target!"); 6521} 6522 6523void 6524SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6525 SDValue Op = getNonRegisterValue(V); 6526 assert((Op.getOpcode() != ISD::CopyFromReg || 6527 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6528 "Copy from a reg to the same reg!"); 6529 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6530 6531 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6532 SDValue Chain = DAG.getEntryNode(); 6533 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6534 PendingExports.push_back(Chain); 6535} 6536 6537#include "llvm/CodeGen/SelectionDAGISel.h" 6538 6539/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6540/// entry block, return true. This includes arguments used by switches, since 6541/// the switch may expand into multiple basic blocks. 6542static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 6543 // With FastISel active, we may be splitting blocks, so force creation 6544 // of virtual registers for all non-dead arguments. 6545 if (FastISel) 6546 return A->use_empty(); 6547 6548 const BasicBlock *Entry = A->getParent()->begin(); 6549 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6550 UI != E; ++UI) { 6551 const User *U = *UI; 6552 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6553 return false; // Use not in entry block. 6554 } 6555 return true; 6556} 6557 6558void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6559 // If this is the entry block, emit arguments. 6560 const Function &F = *LLVMBB->getParent(); 6561 SelectionDAG &DAG = SDB->DAG; 6562 DebugLoc dl = SDB->getCurDebugLoc(); 6563 const TargetData *TD = TLI.getTargetData(); 6564 SmallVector<ISD::InputArg, 16> Ins; 6565 6566 // Check whether the function can return without sret-demotion. 6567 SmallVector<ISD::OutputArg, 4> Outs; 6568 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6569 Outs, TLI); 6570 6571 if (!FuncInfo->CanLowerReturn) { 6572 // Put in an sret pointer parameter before all the other parameters. 6573 SmallVector<EVT, 1> ValueVTs; 6574 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6575 6576 // NOTE: Assuming that a pointer will never break down to more than one VT 6577 // or one register. 6578 ISD::ArgFlagsTy Flags; 6579 Flags.setSRet(); 6580 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6581 ISD::InputArg RetArg(Flags, RegisterVT, true); 6582 Ins.push_back(RetArg); 6583 } 6584 6585 // Set up the incoming argument description vector. 6586 unsigned Idx = 1; 6587 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6588 I != E; ++I, ++Idx) { 6589 SmallVector<EVT, 4> ValueVTs; 6590 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6591 bool isArgValueUsed = !I->use_empty(); 6592 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6593 Value != NumValues; ++Value) { 6594 EVT VT = ValueVTs[Value]; 6595 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6596 ISD::ArgFlagsTy Flags; 6597 unsigned OriginalAlignment = 6598 TD->getABITypeAlignment(ArgTy); 6599 6600 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6601 Flags.setZExt(); 6602 if (F.paramHasAttr(Idx, Attribute::SExt)) 6603 Flags.setSExt(); 6604 if (F.paramHasAttr(Idx, Attribute::InReg)) 6605 Flags.setInReg(); 6606 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6607 Flags.setSRet(); 6608 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6609 Flags.setByVal(); 6610 PointerType *Ty = cast<PointerType>(I->getType()); 6611 Type *ElementTy = Ty->getElementType(); 6612 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6613 // For ByVal, alignment should be passed from FE. BE will guess if 6614 // this info is not there but there are cases it cannot get right. 6615 unsigned FrameAlign; 6616 if (F.getParamAlignment(Idx)) 6617 FrameAlign = F.getParamAlignment(Idx); 6618 else 6619 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6620 Flags.setByValAlign(FrameAlign); 6621 } 6622 if (F.paramHasAttr(Idx, Attribute::Nest)) 6623 Flags.setNest(); 6624 Flags.setOrigAlign(OriginalAlignment); 6625 6626 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6627 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6628 for (unsigned i = 0; i != NumRegs; ++i) { 6629 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6630 if (NumRegs > 1 && i == 0) 6631 MyFlags.Flags.setSplit(); 6632 // if it isn't first piece, alignment must be 1 6633 else if (i > 0) 6634 MyFlags.Flags.setOrigAlign(1); 6635 Ins.push_back(MyFlags); 6636 } 6637 } 6638 } 6639 6640 // Call the target to set up the argument values. 6641 SmallVector<SDValue, 8> InVals; 6642 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6643 F.isVarArg(), Ins, 6644 dl, DAG, InVals); 6645 6646 // Verify that the target's LowerFormalArguments behaved as expected. 6647 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6648 "LowerFormalArguments didn't return a valid chain!"); 6649 assert(InVals.size() == Ins.size() && 6650 "LowerFormalArguments didn't emit the correct number of values!"); 6651 DEBUG({ 6652 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6653 assert(InVals[i].getNode() && 6654 "LowerFormalArguments emitted a null value!"); 6655 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6656 "LowerFormalArguments emitted a value with the wrong type!"); 6657 } 6658 }); 6659 6660 // Update the DAG with the new chain value resulting from argument lowering. 6661 DAG.setRoot(NewRoot); 6662 6663 // Set up the argument values. 6664 unsigned i = 0; 6665 Idx = 1; 6666 if (!FuncInfo->CanLowerReturn) { 6667 // Create a virtual register for the sret pointer, and put in a copy 6668 // from the sret argument into it. 6669 SmallVector<EVT, 1> ValueVTs; 6670 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6671 EVT VT = ValueVTs[0]; 6672 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6673 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6674 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6675 RegVT, VT, AssertOp); 6676 6677 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6678 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6679 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6680 FuncInfo->DemoteRegister = SRetReg; 6681 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6682 SRetReg, ArgValue); 6683 DAG.setRoot(NewRoot); 6684 6685 // i indexes lowered arguments. Bump it past the hidden sret argument. 6686 // Idx indexes LLVM arguments. Don't touch it. 6687 ++i; 6688 } 6689 6690 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6691 ++I, ++Idx) { 6692 SmallVector<SDValue, 4> ArgValues; 6693 SmallVector<EVT, 4> ValueVTs; 6694 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6695 unsigned NumValues = ValueVTs.size(); 6696 6697 // If this argument is unused then remember its value. It is used to generate 6698 // debugging information. 6699 if (I->use_empty() && NumValues) 6700 SDB->setUnusedArgValue(I, InVals[i]); 6701 6702 for (unsigned Val = 0; Val != NumValues; ++Val) { 6703 EVT VT = ValueVTs[Val]; 6704 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6705 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6706 6707 if (!I->use_empty()) { 6708 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6709 if (F.paramHasAttr(Idx, Attribute::SExt)) 6710 AssertOp = ISD::AssertSext; 6711 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6712 AssertOp = ISD::AssertZext; 6713 6714 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6715 NumParts, PartVT, VT, 6716 AssertOp)); 6717 } 6718 6719 i += NumParts; 6720 } 6721 6722 // We don't need to do anything else for unused arguments. 6723 if (ArgValues.empty()) 6724 continue; 6725 6726 // Note down frame index. 6727 if (FrameIndexSDNode *FI = 6728 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6729 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6730 6731 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6732 SDB->getCurDebugLoc()); 6733 6734 SDB->setValue(I, Res); 6735 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6736 if (LoadSDNode *LNode = 6737 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6738 if (FrameIndexSDNode *FI = 6739 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6740 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6741 } 6742 6743 // If this argument is live outside of the entry block, insert a copy from 6744 // wherever we got it to the vreg that other BB's will reference it as. 6745 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6746 // If we can, though, try to skip creating an unnecessary vreg. 6747 // FIXME: This isn't very clean... it would be nice to make this more 6748 // general. It's also subtly incompatible with the hacks FastISel 6749 // uses with vregs. 6750 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6751 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6752 FuncInfo->ValueMap[I] = Reg; 6753 continue; 6754 } 6755 } 6756 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 6757 FuncInfo->InitializeRegForValue(I); 6758 SDB->CopyToExportRegsIfNeeded(I); 6759 } 6760 } 6761 6762 assert(i == InVals.size() && "Argument register count mismatch!"); 6763 6764 // Finally, if the target has anything special to do, allow it to do so. 6765 // FIXME: this should insert code into the DAG! 6766 EmitFunctionEntryCode(); 6767} 6768 6769/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6770/// ensure constants are generated when needed. Remember the virtual registers 6771/// that need to be added to the Machine PHI nodes as input. We cannot just 6772/// directly add them, because expansion might result in multiple MBB's for one 6773/// BB. As such, the start of the BB might correspond to a different MBB than 6774/// the end. 6775/// 6776void 6777SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6778 const TerminatorInst *TI = LLVMBB->getTerminator(); 6779 6780 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6781 6782 // Check successor nodes' PHI nodes that expect a constant to be available 6783 // from this block. 6784 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6785 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6786 if (!isa<PHINode>(SuccBB->begin())) continue; 6787 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6788 6789 // If this terminator has multiple identical successors (common for 6790 // switches), only handle each succ once. 6791 if (!SuccsHandled.insert(SuccMBB)) continue; 6792 6793 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6794 6795 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6796 // nodes and Machine PHI nodes, but the incoming operands have not been 6797 // emitted yet. 6798 for (BasicBlock::const_iterator I = SuccBB->begin(); 6799 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6800 // Ignore dead phi's. 6801 if (PN->use_empty()) continue; 6802 6803 // Skip empty types 6804 if (PN->getType()->isEmptyTy()) 6805 continue; 6806 6807 unsigned Reg; 6808 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6809 6810 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6811 unsigned &RegOut = ConstantsOut[C]; 6812 if (RegOut == 0) { 6813 RegOut = FuncInfo.CreateRegs(C->getType()); 6814 CopyValueToVirtualRegister(C, RegOut); 6815 } 6816 Reg = RegOut; 6817 } else { 6818 DenseMap<const Value *, unsigned>::iterator I = 6819 FuncInfo.ValueMap.find(PHIOp); 6820 if (I != FuncInfo.ValueMap.end()) 6821 Reg = I->second; 6822 else { 6823 assert(isa<AllocaInst>(PHIOp) && 6824 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6825 "Didn't codegen value into a register!??"); 6826 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6827 CopyValueToVirtualRegister(PHIOp, Reg); 6828 } 6829 } 6830 6831 // Remember that this register needs to added to the machine PHI node as 6832 // the input for this MBB. 6833 SmallVector<EVT, 4> ValueVTs; 6834 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6835 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6836 EVT VT = ValueVTs[vti]; 6837 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6838 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6839 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6840 Reg += NumRegisters; 6841 } 6842 } 6843 } 6844 ConstantsOut.clear(); 6845} 6846