SelectionDAGBuilder.cpp revision e5c65911a659e49320d214bf0702793ad37b5ed5
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SelectionDAGBuilder.h" 16#include "SDNodeDbgValue.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Analysis/ValueTracking.h" 23#include "llvm/CallingConv.h" 24#include "llvm/CodeGen/Analysis.h" 25#include "llvm/CodeGen/FastISel.h" 26#include "llvm/CodeGen/FunctionLoweringInfo.h" 27#include "llvm/CodeGen/GCMetadata.h" 28#include "llvm/CodeGen/GCStrategy.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/Constants.h" 37#include "llvm/DataLayout.h" 38#include "llvm/DebugInfo.h" 39#include "llvm/DerivedTypes.h" 40#include "llvm/Function.h" 41#include "llvm/GlobalVariable.h" 42#include "llvm/InlineAsm.h" 43#include "llvm/Instructions.h" 44#include "llvm/IntrinsicInst.h" 45#include "llvm/Intrinsics.h" 46#include "llvm/LLVMContext.h" 47#include "llvm/Module.h" 48#include "llvm/Support/CommandLine.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/ErrorHandling.h" 51#include "llvm/Support/IntegersSubsetMapping.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54#include "llvm/Target/TargetFrameLowering.h" 55#include "llvm/Target/TargetInstrInfo.h" 56#include "llvm/Target/TargetIntrinsicInfo.h" 57#include "llvm/Target/TargetLibraryInfo.h" 58#include "llvm/Target/TargetLowering.h" 59#include "llvm/Target/TargetOptions.h" 60#include <algorithm> 61using namespace llvm; 62 63/// LimitFloatPrecision - Generate low-precision inline sequences for 64/// some float libcalls (6, 8 or 12 bits). 65static unsigned LimitFloatPrecision; 66 67static cl::opt<unsigned, true> 68LimitFPPrecision("limit-float-precision", 69 cl::desc("Generate low-precision inline sequences " 70 "for some float libcalls"), 71 cl::location(LimitFloatPrecision), 72 cl::init(0)); 73 74// Limit the width of DAG chains. This is important in general to prevent 75// prevent DAG-based analysis from blowing up. For example, alias analysis and 76// load clustering may not complete in reasonable time. It is difficult to 77// recognize and avoid this situation within each individual analysis, and 78// future analyses are likely to have the same behavior. Limiting DAG width is 79// the safe approach, and will be especially important with global DAGs. 80// 81// MaxParallelChains default is arbitrarily high to avoid affecting 82// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 83// sequence over this should have been converted to llvm.memcpy by the 84// frontend. It easy to induce this behavior with .ll code such as: 85// %buffer = alloca [4096 x i8] 86// %data = load [4096 x i8]* %argPtr 87// store [4096 x i8] %data, [4096 x i8]* %buffer 88static const unsigned MaxParallelChains = 64; 89 90static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 91 const SDValue *Parts, unsigned NumParts, 92 EVT PartVT, EVT ValueVT, const Value *V); 93 94/// getCopyFromParts - Create a value that contains the specified legal parts 95/// combined into the value they represent. If the parts combine to a type 96/// larger then ValueVT then AssertOp can be used to specify whether the extra 97/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 98/// (ISD::AssertSext). 99static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 100 const SDValue *Parts, 101 unsigned NumParts, EVT PartVT, EVT ValueVT, 102 const Value *V, 103 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 104 if (ValueVT.isVector()) 105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, 106 PartVT, ValueVT, V); 107 108 assert(NumParts > 0 && "No parts to assemble!"); 109 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 110 SDValue Val = Parts[0]; 111 112 if (NumParts > 1) { 113 // Assemble the value from multiple parts. 114 if (ValueVT.isInteger()) { 115 unsigned PartBits = PartVT.getSizeInBits(); 116 unsigned ValueBits = ValueVT.getSizeInBits(); 117 118 // Assemble the power of 2 part. 119 unsigned RoundParts = NumParts & (NumParts - 1) ? 120 1 << Log2_32(NumParts) : NumParts; 121 unsigned RoundBits = PartBits * RoundParts; 122 EVT RoundVT = RoundBits == ValueBits ? 123 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 124 SDValue Lo, Hi; 125 126 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 127 128 if (RoundParts > 2) { 129 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 130 PartVT, HalfVT, V); 131 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 132 RoundParts / 2, PartVT, HalfVT, V); 133 } else { 134 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 135 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 136 } 137 138 if (TLI.isBigEndian()) 139 std::swap(Lo, Hi); 140 141 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 142 143 if (RoundParts < NumParts) { 144 // Assemble the trailing non-power-of-2 part. 145 unsigned OddParts = NumParts - RoundParts; 146 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 147 Hi = getCopyFromParts(DAG, DL, 148 Parts + RoundParts, OddParts, PartVT, OddVT, V); 149 150 // Combine the round and odd parts. 151 Lo = Val; 152 if (TLI.isBigEndian()) 153 std::swap(Lo, Hi); 154 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 155 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 156 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 157 DAG.getConstant(Lo.getValueType().getSizeInBits(), 158 TLI.getPointerTy())); 159 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 160 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 161 } 162 } else if (PartVT.isFloatingPoint()) { 163 // FP split into multiple FP parts (for ppcf128) 164 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 165 "Unexpected split"); 166 SDValue Lo, Hi; 167 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 168 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 169 if (TLI.isBigEndian()) 170 std::swap(Lo, Hi); 171 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 172 } else { 173 // FP split into integer parts (soft fp) 174 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 175 !PartVT.isVector() && "Unexpected split"); 176 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 177 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V); 178 } 179 } 180 181 // There is now one part, held in Val. Correct it to match ValueVT. 182 PartVT = Val.getValueType(); 183 184 if (PartVT == ValueVT) 185 return Val; 186 187 if (PartVT.isInteger() && ValueVT.isInteger()) { 188 if (ValueVT.bitsLT(PartVT)) { 189 // For a truncate, see if we have any information to 190 // indicate whether the truncated bits will always be 191 // zero or sign-extension. 192 if (AssertOp != ISD::DELETED_NODE) 193 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 194 DAG.getValueType(ValueVT)); 195 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 196 } 197 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 198 } 199 200 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 201 // FP_ROUND's are always exact here. 202 if (ValueVT.bitsLT(Val.getValueType())) 203 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 204 DAG.getTargetConstant(1, TLI.getPointerTy())); 205 206 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 207 } 208 209 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 210 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 211 212 llvm_unreachable("Unknown mismatch!"); 213} 214 215/// getCopyFromPartsVector - Create a value that contains the specified legal 216/// parts combined into the value they represent. If the parts combine to a 217/// type larger then ValueVT then AssertOp can be used to specify whether the 218/// extra bits are known to be zero (ISD::AssertZext) or sign extended from 219/// ValueVT (ISD::AssertSext). 220static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 221 const SDValue *Parts, unsigned NumParts, 222 EVT PartVT, EVT ValueVT, const Value *V) { 223 assert(ValueVT.isVector() && "Not a vector value"); 224 assert(NumParts > 0 && "No parts to assemble!"); 225 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 226 SDValue Val = Parts[0]; 227 228 // Handle a multi-element vector. 229 if (NumParts > 1) { 230 EVT IntermediateVT; 231 MVT RegisterVT; 232 unsigned NumIntermediates; 233 unsigned NumRegs = 234 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 235 NumIntermediates, RegisterVT); 236 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 237 NumParts = NumRegs; // Silence a compiler warning. 238 assert(RegisterVT == PartVT.getSimpleVT() && 239 "Part type doesn't match vector breakdown!"); 240 assert(RegisterVT == Parts[0].getSimpleValueType() && 241 "Part type doesn't match part!"); 242 243 // Assemble the parts into intermediate operands. 244 SmallVector<SDValue, 8> Ops(NumIntermediates); 245 if (NumIntermediates == NumParts) { 246 // If the register was not expanded, truncate or copy the value, 247 // as appropriate. 248 for (unsigned i = 0; i != NumParts; ++i) 249 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 250 PartVT, IntermediateVT, V); 251 } else if (NumParts > 0) { 252 // If the intermediate type was expanded, build the intermediate 253 // operands from the parts. 254 assert(NumParts % NumIntermediates == 0 && 255 "Must expand into a divisible number of parts!"); 256 unsigned Factor = NumParts / NumIntermediates; 257 for (unsigned i = 0; i != NumIntermediates; ++i) 258 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 259 PartVT, IntermediateVT, V); 260 } 261 262 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 263 // intermediate operands. 264 Val = DAG.getNode(IntermediateVT.isVector() ? 265 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 266 ValueVT, &Ops[0], NumIntermediates); 267 } 268 269 // There is now one part, held in Val. Correct it to match ValueVT. 270 PartVT = Val.getValueType(); 271 272 if (PartVT == ValueVT) 273 return Val; 274 275 if (PartVT.isVector()) { 276 // If the element type of the source/dest vectors are the same, but the 277 // parts vector has more elements than the value vector, then we have a 278 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 279 // elements we want. 280 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 281 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 282 "Cannot narrow, it would be a lossy transformation"); 283 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 284 DAG.getIntPtrConstant(0)); 285 } 286 287 // Vector/Vector bitcast. 288 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 289 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 290 291 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 292 "Cannot handle this kind of promotion"); 293 // Promoted vector extract 294 bool Smaller = ValueVT.bitsLE(PartVT); 295 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 296 DL, ValueVT, Val); 297 298 } 299 300 // Trivial bitcast if the types are the same size and the destination 301 // vector type is legal. 302 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 303 TLI.isTypeLegal(ValueVT)) 304 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 305 306 // Handle cases such as i8 -> <1 x i1> 307 if (ValueVT.getVectorNumElements() != 1) { 308 LLVMContext &Ctx = *DAG.getContext(); 309 Twine ErrMsg("non-trivial scalar-to-vector conversion"); 310 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) { 311 if (const CallInst *CI = dyn_cast<CallInst>(I)) 312 if (isa<InlineAsm>(CI->getCalledValue())) 313 ErrMsg = ErrMsg + ", possible invalid constraint for vector type"; 314 Ctx.emitError(I, ErrMsg); 315 } else { 316 Ctx.emitError(ErrMsg); 317 } 318 report_fatal_error("Cannot handle scalar-to-vector conversion!"); 319 } 320 321 if (ValueVT.getVectorNumElements() == 1 && 322 ValueVT.getVectorElementType() != PartVT) { 323 bool Smaller = ValueVT.bitsLE(PartVT); 324 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 325 DL, ValueVT.getScalarType(), Val); 326 } 327 328 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 329} 330 331static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 332 SDValue Val, SDValue *Parts, unsigned NumParts, 333 EVT PartVT, const Value *V); 334 335/// getCopyToParts - Create a series of nodes that contain the specified value 336/// split into legal parts. If the parts contain more bits than Val, then, for 337/// integers, ExtendKind can be used to specify how to generate the extra bits. 338static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 339 SDValue Val, SDValue *Parts, unsigned NumParts, 340 EVT PartVT, const Value *V, 341 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 342 EVT ValueVT = Val.getValueType(); 343 344 // Handle the vector case separately. 345 if (ValueVT.isVector()) 346 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V); 347 348 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 349 unsigned PartBits = PartVT.getSizeInBits(); 350 unsigned OrigNumParts = NumParts; 351 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 352 353 if (NumParts == 0) 354 return; 355 356 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 357 if (PartVT == ValueVT) { 358 assert(NumParts == 1 && "No-op copy with multiple parts!"); 359 Parts[0] = Val; 360 return; 361 } 362 363 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 364 // If the parts cover more bits than the value has, promote the value. 365 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 366 assert(NumParts == 1 && "Do not know what to promote to!"); 367 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 368 } else { 369 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 370 ValueVT.isInteger() && 371 "Unknown mismatch!"); 372 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 373 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 374 if (PartVT == MVT::x86mmx) 375 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 376 } 377 } else if (PartBits == ValueVT.getSizeInBits()) { 378 // Different types of the same size. 379 assert(NumParts == 1 && PartVT != ValueVT); 380 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 381 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 382 // If the parts cover less bits than value has, truncate the value. 383 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 384 ValueVT.isInteger() && 385 "Unknown mismatch!"); 386 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 387 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 388 if (PartVT == MVT::x86mmx) 389 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 390 } 391 392 // The value may have changed - recompute ValueVT. 393 ValueVT = Val.getValueType(); 394 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 395 "Failed to tile the value with PartVT!"); 396 397 if (NumParts == 1) { 398 if (PartVT != ValueVT) { 399 LLVMContext &Ctx = *DAG.getContext(); 400 Twine ErrMsg("scalar-to-vector conversion failed"); 401 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) { 402 if (const CallInst *CI = dyn_cast<CallInst>(I)) 403 if (isa<InlineAsm>(CI->getCalledValue())) 404 ErrMsg = ErrMsg + ", possible invalid constraint for vector type"; 405 Ctx.emitError(I, ErrMsg); 406 } else { 407 Ctx.emitError(ErrMsg); 408 } 409 } 410 411 Parts[0] = Val; 412 return; 413 } 414 415 // Expand the value into multiple parts. 416 if (NumParts & (NumParts - 1)) { 417 // The number of parts is not a power of 2. Split off and copy the tail. 418 assert(PartVT.isInteger() && ValueVT.isInteger() && 419 "Do not know what to expand to!"); 420 unsigned RoundParts = 1 << Log2_32(NumParts); 421 unsigned RoundBits = RoundParts * PartBits; 422 unsigned OddParts = NumParts - RoundParts; 423 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 424 DAG.getIntPtrConstant(RoundBits)); 425 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V); 426 427 if (TLI.isBigEndian()) 428 // The odd parts were reversed by getCopyToParts - unreverse them. 429 std::reverse(Parts + RoundParts, Parts + NumParts); 430 431 NumParts = RoundParts; 432 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 433 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 434 } 435 436 // The number of parts is a power of 2. Repeatedly bisect the value using 437 // EXTRACT_ELEMENT. 438 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 439 EVT::getIntegerVT(*DAG.getContext(), 440 ValueVT.getSizeInBits()), 441 Val); 442 443 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 444 for (unsigned i = 0; i < NumParts; i += StepSize) { 445 unsigned ThisBits = StepSize * PartBits / 2; 446 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 447 SDValue &Part0 = Parts[i]; 448 SDValue &Part1 = Parts[i+StepSize/2]; 449 450 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 451 ThisVT, Part0, DAG.getIntPtrConstant(1)); 452 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 453 ThisVT, Part0, DAG.getIntPtrConstant(0)); 454 455 if (ThisBits == PartBits && ThisVT != PartVT) { 456 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 457 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 458 } 459 } 460 } 461 462 if (TLI.isBigEndian()) 463 std::reverse(Parts, Parts + OrigNumParts); 464} 465 466 467/// getCopyToPartsVector - Create a series of nodes that contain the specified 468/// value split into legal parts. 469static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 470 SDValue Val, SDValue *Parts, unsigned NumParts, 471 EVT PartVT, const Value *V) { 472 EVT ValueVT = Val.getValueType(); 473 assert(ValueVT.isVector() && "Not a vector"); 474 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 475 476 if (NumParts == 1) { 477 if (PartVT == ValueVT) { 478 // Nothing to do. 479 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 480 // Bitconvert vector->vector case. 481 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 482 } else if (PartVT.isVector() && 483 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 484 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 485 EVT ElementVT = PartVT.getVectorElementType(); 486 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 487 // undef elements. 488 SmallVector<SDValue, 16> Ops; 489 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 490 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 491 ElementVT, Val, DAG.getIntPtrConstant(i))); 492 493 for (unsigned i = ValueVT.getVectorNumElements(), 494 e = PartVT.getVectorNumElements(); i != e; ++i) 495 Ops.push_back(DAG.getUNDEF(ElementVT)); 496 497 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 498 499 // FIXME: Use CONCAT for 2x -> 4x. 500 501 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 502 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 503 } else if (PartVT.isVector() && 504 PartVT.getVectorElementType().bitsGE( 505 ValueVT.getVectorElementType()) && 506 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 507 508 // Promoted vector extract 509 bool Smaller = PartVT.bitsLE(ValueVT); 510 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 511 DL, PartVT, Val); 512 } else{ 513 // Vector -> scalar conversion. 514 assert(ValueVT.getVectorNumElements() == 1 && 515 "Only trivial vector-to-scalar conversions should get here!"); 516 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 517 PartVT, Val, DAG.getIntPtrConstant(0)); 518 519 bool Smaller = ValueVT.bitsLE(PartVT); 520 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 521 DL, PartVT, Val); 522 } 523 524 Parts[0] = Val; 525 return; 526 } 527 528 // Handle a multi-element vector. 529 EVT IntermediateVT; 530 MVT RegisterVT; 531 unsigned NumIntermediates; 532 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 533 IntermediateVT, 534 NumIntermediates, RegisterVT); 535 unsigned NumElements = ValueVT.getVectorNumElements(); 536 537 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 538 NumParts = NumRegs; // Silence a compiler warning. 539 assert(RegisterVT == PartVT.getSimpleVT() && 540 "Part type doesn't match vector breakdown!"); 541 542 // Split the vector into intermediate operands. 543 SmallVector<SDValue, 8> Ops(NumIntermediates); 544 for (unsigned i = 0; i != NumIntermediates; ++i) { 545 if (IntermediateVT.isVector()) 546 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 547 IntermediateVT, Val, 548 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 549 else 550 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 551 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 552 } 553 554 // Split the intermediate operands into legal parts. 555 if (NumParts == NumIntermediates) { 556 // If the register was not expanded, promote or copy the value, 557 // as appropriate. 558 for (unsigned i = 0; i != NumParts; ++i) 559 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V); 560 } else if (NumParts > 0) { 561 // If the intermediate type was expanded, split each the value into 562 // legal parts. 563 assert(NumParts % NumIntermediates == 0 && 564 "Must expand into a divisible number of parts!"); 565 unsigned Factor = NumParts / NumIntermediates; 566 for (unsigned i = 0; i != NumIntermediates; ++i) 567 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V); 568 } 569} 570 571namespace { 572 /// RegsForValue - This struct represents the registers (physical or virtual) 573 /// that a particular set of values is assigned, and the type information 574 /// about the value. The most common situation is to represent one value at a 575 /// time, but struct or array values are handled element-wise as multiple 576 /// values. The splitting of aggregates is performed recursively, so that we 577 /// never have aggregate-typed registers. The values at this point do not 578 /// necessarily have legal types, so each value may require one or more 579 /// registers of some legal type. 580 /// 581 struct RegsForValue { 582 /// ValueVTs - The value types of the values, which may not be legal, and 583 /// may need be promoted or synthesized from one or more registers. 584 /// 585 SmallVector<EVT, 4> ValueVTs; 586 587 /// RegVTs - The value types of the registers. This is the same size as 588 /// ValueVTs and it records, for each value, what the type of the assigned 589 /// register or registers are. (Individual values are never synthesized 590 /// from more than one type of register.) 591 /// 592 /// With virtual registers, the contents of RegVTs is redundant with TLI's 593 /// getRegisterType member function, however when with physical registers 594 /// it is necessary to have a separate record of the types. 595 /// 596 SmallVector<EVT, 4> RegVTs; 597 598 /// Regs - This list holds the registers assigned to the values. 599 /// Each legal or promoted value requires one register, and each 600 /// expanded value requires multiple registers. 601 /// 602 SmallVector<unsigned, 4> Regs; 603 604 RegsForValue() {} 605 606 RegsForValue(const SmallVector<unsigned, 4> ®s, 607 EVT regvt, EVT valuevt) 608 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 609 610 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 611 unsigned Reg, Type *Ty) { 612 ComputeValueVTs(tli, Ty, ValueVTs); 613 614 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 615 EVT ValueVT = ValueVTs[Value]; 616 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 617 MVT RegisterVT = tli.getRegisterType(Context, ValueVT); 618 for (unsigned i = 0; i != NumRegs; ++i) 619 Regs.push_back(Reg + i); 620 RegVTs.push_back(RegisterVT); 621 Reg += NumRegs; 622 } 623 } 624 625 /// areValueTypesLegal - Return true if types of all the values are legal. 626 bool areValueTypesLegal(const TargetLowering &TLI) { 627 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 628 EVT RegisterVT = RegVTs[Value]; 629 if (!TLI.isTypeLegal(RegisterVT)) 630 return false; 631 } 632 return true; 633 } 634 635 /// append - Add the specified values to this one. 636 void append(const RegsForValue &RHS) { 637 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 638 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 639 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 640 } 641 642 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 643 /// this value and returns the result as a ValueVTs value. This uses 644 /// Chain/Flag as the input and updates them for the output Chain/Flag. 645 /// If the Flag pointer is NULL, no flag is used. 646 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 647 DebugLoc dl, 648 SDValue &Chain, SDValue *Flag, 649 const Value *V = 0) const; 650 651 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 652 /// specified value into the registers specified by this object. This uses 653 /// Chain/Flag as the input and updates them for the output Chain/Flag. 654 /// If the Flag pointer is NULL, no flag is used. 655 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 656 SDValue &Chain, SDValue *Flag, const Value *V) const; 657 658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 659 /// operand list. This adds the code marker, matching input operand index 660 /// (if applicable), and includes the number of values added into it. 661 void AddInlineAsmOperands(unsigned Kind, 662 bool HasMatching, unsigned MatchingIdx, 663 SelectionDAG &DAG, 664 std::vector<SDValue> &Ops) const; 665 }; 666} 667 668/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 669/// this value and returns the result as a ValueVT value. This uses 670/// Chain/Flag as the input and updates them for the output Chain/Flag. 671/// If the Flag pointer is NULL, no flag is used. 672SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 673 FunctionLoweringInfo &FuncInfo, 674 DebugLoc dl, 675 SDValue &Chain, SDValue *Flag, 676 const Value *V) const { 677 // A Value with type {} or [0 x %t] needs no registers. 678 if (ValueVTs.empty()) 679 return SDValue(); 680 681 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 682 683 // Assemble the legal parts into the final values. 684 SmallVector<SDValue, 4> Values(ValueVTs.size()); 685 SmallVector<SDValue, 8> Parts; 686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 687 // Copy the legal parts from the registers. 688 EVT ValueVT = ValueVTs[Value]; 689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 690 EVT RegisterVT = RegVTs[Value]; 691 692 Parts.resize(NumRegs); 693 for (unsigned i = 0; i != NumRegs; ++i) { 694 SDValue P; 695 if (Flag == 0) { 696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 697 } else { 698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 699 *Flag = P.getValue(2); 700 } 701 702 Chain = P.getValue(1); 703 Parts[i] = P; 704 705 // If the source register was virtual and if we know something about it, 706 // add an assert node. 707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 708 !RegisterVT.isInteger() || RegisterVT.isVector()) 709 continue; 710 711 const FunctionLoweringInfo::LiveOutInfo *LOI = 712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 713 if (!LOI) 714 continue; 715 716 unsigned RegSize = RegisterVT.getSizeInBits(); 717 unsigned NumSignBits = LOI->NumSignBits; 718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 719 720 // FIXME: We capture more information than the dag can represent. For 721 // now, just use the tightest assertzext/assertsext possible. 722 bool isSExt = true; 723 EVT FromVT(MVT::Other); 724 if (NumSignBits == RegSize) 725 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 726 else if (NumZeroBits >= RegSize-1) 727 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 728 else if (NumSignBits > RegSize-8) 729 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 730 else if (NumZeroBits >= RegSize-8) 731 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 732 else if (NumSignBits > RegSize-16) 733 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 734 else if (NumZeroBits >= RegSize-16) 735 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 736 else if (NumSignBits > RegSize-32) 737 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 738 else if (NumZeroBits >= RegSize-32) 739 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 740 else 741 continue; 742 743 // Add an assertion node. 744 assert(FromVT != MVT::Other); 745 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 746 RegisterVT, P, DAG.getValueType(FromVT)); 747 } 748 749 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 750 NumRegs, RegisterVT, ValueVT, V); 751 Part += NumRegs; 752 Parts.clear(); 753 } 754 755 return DAG.getNode(ISD::MERGE_VALUES, dl, 756 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 757 &Values[0], ValueVTs.size()); 758} 759 760/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 761/// specified value into the registers specified by this object. This uses 762/// Chain/Flag as the input and updates them for the output Chain/Flag. 763/// If the Flag pointer is NULL, no flag is used. 764void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 765 SDValue &Chain, SDValue *Flag, 766 const Value *V) const { 767 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 768 769 // Get the list of the values's legal parts. 770 unsigned NumRegs = Regs.size(); 771 SmallVector<SDValue, 8> Parts(NumRegs); 772 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 773 EVT ValueVT = ValueVTs[Value]; 774 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 775 EVT RegisterVT = RegVTs[Value]; 776 ISD::NodeType ExtendKind = 777 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND; 778 779 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 780 &Parts[Part], NumParts, RegisterVT, V, ExtendKind); 781 Part += NumParts; 782 } 783 784 // Copy the parts into the registers. 785 SmallVector<SDValue, 8> Chains(NumRegs); 786 for (unsigned i = 0; i != NumRegs; ++i) { 787 SDValue Part; 788 if (Flag == 0) { 789 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 790 } else { 791 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 792 *Flag = Part.getValue(1); 793 } 794 795 Chains[i] = Part.getValue(0); 796 } 797 798 if (NumRegs == 1 || Flag) 799 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 800 // flagged to it. That is the CopyToReg nodes and the user are considered 801 // a single scheduling unit. If we create a TokenFactor and return it as 802 // chain, then the TokenFactor is both a predecessor (operand) of the 803 // user as well as a successor (the TF operands are flagged to the user). 804 // c1, f1 = CopyToReg 805 // c2, f2 = CopyToReg 806 // c3 = TokenFactor c1, c2 807 // ... 808 // = op c3, ..., f2 809 Chain = Chains[NumRegs-1]; 810 else 811 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 812} 813 814/// AddInlineAsmOperands - Add this value to the specified inlineasm node 815/// operand list. This adds the code marker and includes the number of 816/// values added into it. 817void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 818 unsigned MatchingIdx, 819 SelectionDAG &DAG, 820 std::vector<SDValue> &Ops) const { 821 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 822 823 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 824 if (HasMatching) 825 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 826 else if (!Regs.empty() && 827 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 828 // Put the register class of the virtual registers in the flag word. That 829 // way, later passes can recompute register class constraints for inline 830 // assembly as well as normal instructions. 831 // Don't do this for tied operands that can use the regclass information 832 // from the def. 833 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 834 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 835 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 836 } 837 838 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 839 Ops.push_back(Res); 840 841 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 842 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 843 EVT RegisterVT = RegVTs[Value]; 844 for (unsigned i = 0; i != NumRegs; ++i) { 845 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 846 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 847 } 848 } 849} 850 851void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 852 const TargetLibraryInfo *li) { 853 AA = &aa; 854 GFI = gfi; 855 LibInfo = li; 856 TD = DAG.getTarget().getDataLayout(); 857 Context = DAG.getContext(); 858 LPadToCallSiteMap.clear(); 859} 860 861/// clear - Clear out the current SelectionDAG and the associated 862/// state and prepare this SelectionDAGBuilder object to be used 863/// for a new block. This doesn't clear out information about 864/// additional blocks that are needed to complete switch lowering 865/// or PHI node updating; that information is cleared out as it is 866/// consumed. 867void SelectionDAGBuilder::clear() { 868 NodeMap.clear(); 869 UnusedArgNodeMap.clear(); 870 PendingLoads.clear(); 871 PendingExports.clear(); 872 CurDebugLoc = DebugLoc(); 873 HasTailCall = false; 874} 875 876/// clearDanglingDebugInfo - Clear the dangling debug information 877/// map. This function is separated from the clear so that debug 878/// information that is dangling in a basic block can be properly 879/// resolved in a different basic block. This allows the 880/// SelectionDAG to resolve dangling debug information attached 881/// to PHI nodes. 882void SelectionDAGBuilder::clearDanglingDebugInfo() { 883 DanglingDebugInfoMap.clear(); 884} 885 886/// getRoot - Return the current virtual root of the Selection DAG, 887/// flushing any PendingLoad items. This must be done before emitting 888/// a store or any other node that may need to be ordered after any 889/// prior load instructions. 890/// 891SDValue SelectionDAGBuilder::getRoot() { 892 if (PendingLoads.empty()) 893 return DAG.getRoot(); 894 895 if (PendingLoads.size() == 1) { 896 SDValue Root = PendingLoads[0]; 897 DAG.setRoot(Root); 898 PendingLoads.clear(); 899 return Root; 900 } 901 902 // Otherwise, we have to make a token factor node. 903 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 904 &PendingLoads[0], PendingLoads.size()); 905 PendingLoads.clear(); 906 DAG.setRoot(Root); 907 return Root; 908} 909 910/// getControlRoot - Similar to getRoot, but instead of flushing all the 911/// PendingLoad items, flush all the PendingExports items. It is necessary 912/// to do this before emitting a terminator instruction. 913/// 914SDValue SelectionDAGBuilder::getControlRoot() { 915 SDValue Root = DAG.getRoot(); 916 917 if (PendingExports.empty()) 918 return Root; 919 920 // Turn all of the CopyToReg chains into one factored node. 921 if (Root.getOpcode() != ISD::EntryToken) { 922 unsigned i = 0, e = PendingExports.size(); 923 for (; i != e; ++i) { 924 assert(PendingExports[i].getNode()->getNumOperands() > 1); 925 if (PendingExports[i].getNode()->getOperand(0) == Root) 926 break; // Don't add the root if we already indirectly depend on it. 927 } 928 929 if (i == e) 930 PendingExports.push_back(Root); 931 } 932 933 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 934 &PendingExports[0], 935 PendingExports.size()); 936 PendingExports.clear(); 937 DAG.setRoot(Root); 938 return Root; 939} 940 941void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 942 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 943 DAG.AssignOrdering(Node, SDNodeOrder); 944 945 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 946 AssignOrderingToNode(Node->getOperand(I).getNode()); 947} 948 949void SelectionDAGBuilder::visit(const Instruction &I) { 950 // Set up outgoing PHI node register values before emitting the terminator. 951 if (isa<TerminatorInst>(&I)) 952 HandlePHINodesInSuccessorBlocks(I.getParent()); 953 954 CurDebugLoc = I.getDebugLoc(); 955 956 visit(I.getOpcode(), I); 957 958 if (!isa<TerminatorInst>(&I) && !HasTailCall) 959 CopyToExportRegsIfNeeded(&I); 960 961 CurDebugLoc = DebugLoc(); 962} 963 964void SelectionDAGBuilder::visitPHI(const PHINode &) { 965 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 966} 967 968void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 969 // Note: this doesn't use InstVisitor, because it has to work with 970 // ConstantExpr's in addition to instructions. 971 switch (Opcode) { 972 default: llvm_unreachable("Unknown instruction type encountered!"); 973 // Build the switch statement using the Instruction.def file. 974#define HANDLE_INST(NUM, OPCODE, CLASS) \ 975 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break; 976#include "llvm/Instruction.def" 977 } 978 979 // Assign the ordering to the freshly created DAG nodes. 980 if (NodeMap.count(&I)) { 981 ++SDNodeOrder; 982 AssignOrderingToNode(getValue(&I).getNode()); 983 } 984} 985 986// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 987// generate the debug data structures now that we've seen its definition. 988void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 989 SDValue Val) { 990 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 991 if (DDI.getDI()) { 992 const DbgValueInst *DI = DDI.getDI(); 993 DebugLoc dl = DDI.getdl(); 994 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 995 MDNode *Variable = DI->getVariable(); 996 uint64_t Offset = DI->getOffset(); 997 SDDbgValue *SDV; 998 if (Val.getNode()) { 999 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 1000 SDV = DAG.getDbgValue(Variable, Val.getNode(), 1001 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 1002 DAG.AddDbgValue(SDV, Val.getNode(), false); 1003 } 1004 } else 1005 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 1006 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 1007 } 1008} 1009 1010/// getValue - Return an SDValue for the given Value. 1011SDValue SelectionDAGBuilder::getValue(const Value *V) { 1012 // If we already have an SDValue for this value, use it. It's important 1013 // to do this first, so that we don't create a CopyFromReg if we already 1014 // have a regular SDValue. 1015 SDValue &N = NodeMap[V]; 1016 if (N.getNode()) return N; 1017 1018 // If there's a virtual register allocated and initialized for this 1019 // value, use it. 1020 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 1021 if (It != FuncInfo.ValueMap.end()) { 1022 unsigned InReg = It->second; 1023 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 1024 SDValue Chain = DAG.getEntryNode(); 1025 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V); 1026 resolveDanglingDebugInfo(V, N); 1027 return N; 1028 } 1029 1030 // Otherwise create a new SDValue and remember it. 1031 SDValue Val = getValueImpl(V); 1032 NodeMap[V] = Val; 1033 resolveDanglingDebugInfo(V, Val); 1034 return Val; 1035} 1036 1037/// getNonRegisterValue - Return an SDValue for the given Value, but 1038/// don't look in FuncInfo.ValueMap for a virtual register. 1039SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1040 // If we already have an SDValue for this value, use it. 1041 SDValue &N = NodeMap[V]; 1042 if (N.getNode()) return N; 1043 1044 // Otherwise create a new SDValue and remember it. 1045 SDValue Val = getValueImpl(V); 1046 NodeMap[V] = Val; 1047 resolveDanglingDebugInfo(V, Val); 1048 return Val; 1049} 1050 1051/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1052/// Create an SDValue for the given value. 1053SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1054 if (const Constant *C = dyn_cast<Constant>(V)) { 1055 EVT VT = TLI.getValueType(V->getType(), true); 1056 1057 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1058 return DAG.getConstant(*CI, VT); 1059 1060 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1061 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1062 1063 if (isa<ConstantPointerNull>(C)) 1064 return DAG.getConstant(0, TLI.getPointerTy()); 1065 1066 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1067 return DAG.getConstantFP(*CFP, VT); 1068 1069 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1070 return DAG.getUNDEF(VT); 1071 1072 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1073 visit(CE->getOpcode(), *CE); 1074 SDValue N1 = NodeMap[V]; 1075 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1076 return N1; 1077 } 1078 1079 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1080 SmallVector<SDValue, 4> Constants; 1081 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1082 OI != OE; ++OI) { 1083 SDNode *Val = getValue(*OI).getNode(); 1084 // If the operand is an empty aggregate, there are no values. 1085 if (!Val) continue; 1086 // Add each leaf value from the operand to the Constants list 1087 // to form a flattened list of all the values. 1088 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1089 Constants.push_back(SDValue(Val, i)); 1090 } 1091 1092 return DAG.getMergeValues(&Constants[0], Constants.size(), 1093 getCurDebugLoc()); 1094 } 1095 1096 if (const ConstantDataSequential *CDS = 1097 dyn_cast<ConstantDataSequential>(C)) { 1098 SmallVector<SDValue, 4> Ops; 1099 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { 1100 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1101 // Add each leaf value from the operand to the Constants list 1102 // to form a flattened list of all the values. 1103 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1104 Ops.push_back(SDValue(Val, i)); 1105 } 1106 1107 if (isa<ArrayType>(CDS->getType())) 1108 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc()); 1109 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1110 VT, &Ops[0], Ops.size()); 1111 } 1112 1113 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1114 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1115 "Unknown struct or array constant!"); 1116 1117 SmallVector<EVT, 4> ValueVTs; 1118 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1119 unsigned NumElts = ValueVTs.size(); 1120 if (NumElts == 0) 1121 return SDValue(); // empty struct 1122 SmallVector<SDValue, 4> Constants(NumElts); 1123 for (unsigned i = 0; i != NumElts; ++i) { 1124 EVT EltVT = ValueVTs[i]; 1125 if (isa<UndefValue>(C)) 1126 Constants[i] = DAG.getUNDEF(EltVT); 1127 else if (EltVT.isFloatingPoint()) 1128 Constants[i] = DAG.getConstantFP(0, EltVT); 1129 else 1130 Constants[i] = DAG.getConstant(0, EltVT); 1131 } 1132 1133 return DAG.getMergeValues(&Constants[0], NumElts, 1134 getCurDebugLoc()); 1135 } 1136 1137 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1138 return DAG.getBlockAddress(BA, VT); 1139 1140 VectorType *VecTy = cast<VectorType>(V->getType()); 1141 unsigned NumElements = VecTy->getNumElements(); 1142 1143 // Now that we know the number and type of the elements, get that number of 1144 // elements into the Ops array based on what kind of constant it is. 1145 SmallVector<SDValue, 16> Ops; 1146 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1147 for (unsigned i = 0; i != NumElements; ++i) 1148 Ops.push_back(getValue(CV->getOperand(i))); 1149 } else { 1150 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1151 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1152 1153 SDValue Op; 1154 if (EltVT.isFloatingPoint()) 1155 Op = DAG.getConstantFP(0, EltVT); 1156 else 1157 Op = DAG.getConstant(0, EltVT); 1158 Ops.assign(NumElements, Op); 1159 } 1160 1161 // Create a BUILD_VECTOR node. 1162 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1163 VT, &Ops[0], Ops.size()); 1164 } 1165 1166 // If this is a static alloca, generate it as the frameindex instead of 1167 // computation. 1168 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1169 DenseMap<const AllocaInst*, int>::iterator SI = 1170 FuncInfo.StaticAllocaMap.find(AI); 1171 if (SI != FuncInfo.StaticAllocaMap.end()) 1172 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1173 } 1174 1175 // If this is an instruction which fast-isel has deferred, select it now. 1176 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1177 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1178 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1179 SDValue Chain = DAG.getEntryNode(); 1180 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V); 1181 } 1182 1183 llvm_unreachable("Can't get register for value!"); 1184} 1185 1186void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1187 SDValue Chain = getControlRoot(); 1188 SmallVector<ISD::OutputArg, 8> Outs; 1189 SmallVector<SDValue, 8> OutVals; 1190 1191 if (!FuncInfo.CanLowerReturn) { 1192 unsigned DemoteReg = FuncInfo.DemoteRegister; 1193 const Function *F = I.getParent()->getParent(); 1194 1195 // Emit a store of the return value through the virtual register. 1196 // Leave Outs empty so that LowerReturn won't try to load return 1197 // registers the usual way. 1198 SmallVector<EVT, 1> PtrValueVTs; 1199 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1200 PtrValueVTs); 1201 1202 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1203 SDValue RetOp = getValue(I.getOperand(0)); 1204 1205 SmallVector<EVT, 4> ValueVTs; 1206 SmallVector<uint64_t, 4> Offsets; 1207 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1208 unsigned NumValues = ValueVTs.size(); 1209 1210 SmallVector<SDValue, 4> Chains(NumValues); 1211 for (unsigned i = 0; i != NumValues; ++i) { 1212 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1213 RetPtr.getValueType(), RetPtr, 1214 DAG.getIntPtrConstant(Offsets[i])); 1215 Chains[i] = 1216 DAG.getStore(Chain, getCurDebugLoc(), 1217 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1218 // FIXME: better loc info would be nice. 1219 Add, MachinePointerInfo(), false, false, 0); 1220 } 1221 1222 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1223 MVT::Other, &Chains[0], NumValues); 1224 } else if (I.getNumOperands() != 0) { 1225 SmallVector<EVT, 4> ValueVTs; 1226 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1227 unsigned NumValues = ValueVTs.size(); 1228 if (NumValues) { 1229 SDValue RetOp = getValue(I.getOperand(0)); 1230 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1231 EVT VT = ValueVTs[j]; 1232 1233 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1234 1235 const Function *F = I.getParent()->getParent(); 1236 if (F->getRetAttributes().hasAttribute(Attribute::SExt)) 1237 ExtendKind = ISD::SIGN_EXTEND; 1238 else if (F->getRetAttributes().hasAttribute(Attribute::ZExt)) 1239 ExtendKind = ISD::ZERO_EXTEND; 1240 1241 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1242 VT = TLI.getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind); 1243 1244 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1245 MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1246 SmallVector<SDValue, 4> Parts(NumParts); 1247 getCopyToParts(DAG, getCurDebugLoc(), 1248 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1249 &Parts[0], NumParts, PartVT, &I, ExtendKind); 1250 1251 // 'inreg' on function refers to return value 1252 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1253 if (F->getRetAttributes().hasAttribute(Attribute::InReg)) 1254 Flags.setInReg(); 1255 1256 // Propagate extension type if any 1257 if (ExtendKind == ISD::SIGN_EXTEND) 1258 Flags.setSExt(); 1259 else if (ExtendKind == ISD::ZERO_EXTEND) 1260 Flags.setZExt(); 1261 1262 for (unsigned i = 0; i < NumParts; ++i) { 1263 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1264 /*isfixed=*/true, 0, 0)); 1265 OutVals.push_back(Parts[i]); 1266 } 1267 } 1268 } 1269 } 1270 1271 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1272 CallingConv::ID CallConv = 1273 DAG.getMachineFunction().getFunction()->getCallingConv(); 1274 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1275 Outs, OutVals, getCurDebugLoc(), DAG); 1276 1277 // Verify that the target's LowerReturn behaved as expected. 1278 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1279 "LowerReturn didn't return a valid chain!"); 1280 1281 // Update the DAG with the new chain value resulting from return lowering. 1282 DAG.setRoot(Chain); 1283} 1284 1285/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1286/// created for it, emit nodes to copy the value into the virtual 1287/// registers. 1288void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1289 // Skip empty types 1290 if (V->getType()->isEmptyTy()) 1291 return; 1292 1293 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1294 if (VMI != FuncInfo.ValueMap.end()) { 1295 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1296 CopyValueToVirtualRegister(V, VMI->second); 1297 } 1298} 1299 1300/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1301/// the current basic block, add it to ValueMap now so that we'll get a 1302/// CopyTo/FromReg. 1303void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1304 // No need to export constants. 1305 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1306 1307 // Already exported? 1308 if (FuncInfo.isExportedInst(V)) return; 1309 1310 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1311 CopyValueToVirtualRegister(V, Reg); 1312} 1313 1314bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1315 const BasicBlock *FromBB) { 1316 // The operands of the setcc have to be in this block. We don't know 1317 // how to export them from some other block. 1318 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1319 // Can export from current BB. 1320 if (VI->getParent() == FromBB) 1321 return true; 1322 1323 // Is already exported, noop. 1324 return FuncInfo.isExportedInst(V); 1325 } 1326 1327 // If this is an argument, we can export it if the BB is the entry block or 1328 // if it is already exported. 1329 if (isa<Argument>(V)) { 1330 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1331 return true; 1332 1333 // Otherwise, can only export this if it is already exported. 1334 return FuncInfo.isExportedInst(V); 1335 } 1336 1337 // Otherwise, constants can always be exported. 1338 return true; 1339} 1340 1341/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1342uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1343 const MachineBasicBlock *Dst) const { 1344 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1345 if (!BPI) 1346 return 0; 1347 const BasicBlock *SrcBB = Src->getBasicBlock(); 1348 const BasicBlock *DstBB = Dst->getBasicBlock(); 1349 return BPI->getEdgeWeight(SrcBB, DstBB); 1350} 1351 1352void SelectionDAGBuilder:: 1353addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1354 uint32_t Weight /* = 0 */) { 1355 if (!Weight) 1356 Weight = getEdgeWeight(Src, Dst); 1357 Src->addSuccessor(Dst, Weight); 1358} 1359 1360 1361static bool InBlock(const Value *V, const BasicBlock *BB) { 1362 if (const Instruction *I = dyn_cast<Instruction>(V)) 1363 return I->getParent() == BB; 1364 return true; 1365} 1366 1367/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1368/// This function emits a branch and is used at the leaves of an OR or an 1369/// AND operator tree. 1370/// 1371void 1372SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1373 MachineBasicBlock *TBB, 1374 MachineBasicBlock *FBB, 1375 MachineBasicBlock *CurBB, 1376 MachineBasicBlock *SwitchBB) { 1377 const BasicBlock *BB = CurBB->getBasicBlock(); 1378 1379 // If the leaf of the tree is a comparison, merge the condition into 1380 // the caseblock. 1381 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1382 // The operands of the cmp have to be in this block. We don't know 1383 // how to export them from some other block. If this is the first block 1384 // of the sequence, no exporting is needed. 1385 if (CurBB == SwitchBB || 1386 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1387 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1388 ISD::CondCode Condition; 1389 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1390 Condition = getICmpCondCode(IC->getPredicate()); 1391 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1392 Condition = getFCmpCondCode(FC->getPredicate()); 1393 if (TM.Options.NoNaNsFPMath) 1394 Condition = getFCmpCodeWithoutNaN(Condition); 1395 } else { 1396 Condition = ISD::SETEQ; // silence warning. 1397 llvm_unreachable("Unknown compare instruction"); 1398 } 1399 1400 CaseBlock CB(Condition, BOp->getOperand(0), 1401 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1402 SwitchCases.push_back(CB); 1403 return; 1404 } 1405 } 1406 1407 // Create a CaseBlock record representing this branch. 1408 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1409 NULL, TBB, FBB, CurBB); 1410 SwitchCases.push_back(CB); 1411} 1412 1413/// FindMergedConditions - If Cond is an expression like 1414void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1415 MachineBasicBlock *TBB, 1416 MachineBasicBlock *FBB, 1417 MachineBasicBlock *CurBB, 1418 MachineBasicBlock *SwitchBB, 1419 unsigned Opc) { 1420 // If this node is not part of the or/and tree, emit it as a branch. 1421 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1422 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1423 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1424 BOp->getParent() != CurBB->getBasicBlock() || 1425 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1426 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1427 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1428 return; 1429 } 1430 1431 // Create TmpBB after CurBB. 1432 MachineFunction::iterator BBI = CurBB; 1433 MachineFunction &MF = DAG.getMachineFunction(); 1434 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1435 CurBB->getParent()->insert(++BBI, TmpBB); 1436 1437 if (Opc == Instruction::Or) { 1438 // Codegen X | Y as: 1439 // jmp_if_X TBB 1440 // jmp TmpBB 1441 // TmpBB: 1442 // jmp_if_Y TBB 1443 // jmp FBB 1444 // 1445 1446 // Emit the LHS condition. 1447 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1448 1449 // Emit the RHS condition into TmpBB. 1450 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1451 } else { 1452 assert(Opc == Instruction::And && "Unknown merge op!"); 1453 // Codegen X & Y as: 1454 // jmp_if_X TmpBB 1455 // jmp FBB 1456 // TmpBB: 1457 // jmp_if_Y TBB 1458 // jmp FBB 1459 // 1460 // This requires creation of TmpBB after CurBB. 1461 1462 // Emit the LHS condition. 1463 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1464 1465 // Emit the RHS condition into TmpBB. 1466 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1467 } 1468} 1469 1470/// If the set of cases should be emitted as a series of branches, return true. 1471/// If we should emit this as a bunch of and/or'd together conditions, return 1472/// false. 1473bool 1474SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1475 if (Cases.size() != 2) return true; 1476 1477 // If this is two comparisons of the same values or'd or and'd together, they 1478 // will get folded into a single comparison, so don't emit two blocks. 1479 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1480 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1481 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1482 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1483 return false; 1484 } 1485 1486 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1487 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1488 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1489 Cases[0].CC == Cases[1].CC && 1490 isa<Constant>(Cases[0].CmpRHS) && 1491 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1492 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1493 return false; 1494 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1495 return false; 1496 } 1497 1498 return true; 1499} 1500 1501void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1502 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1503 1504 // Update machine-CFG edges. 1505 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1506 1507 // Figure out which block is immediately after the current one. 1508 MachineBasicBlock *NextBlock = 0; 1509 MachineFunction::iterator BBI = BrMBB; 1510 if (++BBI != FuncInfo.MF->end()) 1511 NextBlock = BBI; 1512 1513 if (I.isUnconditional()) { 1514 // Update machine-CFG edges. 1515 BrMBB->addSuccessor(Succ0MBB); 1516 1517 // If this is not a fall-through branch, emit the branch. 1518 if (Succ0MBB != NextBlock) 1519 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1520 MVT::Other, getControlRoot(), 1521 DAG.getBasicBlock(Succ0MBB))); 1522 1523 return; 1524 } 1525 1526 // If this condition is one of the special cases we handle, do special stuff 1527 // now. 1528 const Value *CondVal = I.getCondition(); 1529 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1530 1531 // If this is a series of conditions that are or'd or and'd together, emit 1532 // this as a sequence of branches instead of setcc's with and/or operations. 1533 // As long as jumps are not expensive, this should improve performance. 1534 // For example, instead of something like: 1535 // cmp A, B 1536 // C = seteq 1537 // cmp D, E 1538 // F = setle 1539 // or C, F 1540 // jnz foo 1541 // Emit: 1542 // cmp A, B 1543 // je foo 1544 // cmp D, E 1545 // jle foo 1546 // 1547 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1548 if (!TLI.isJumpExpensive() && 1549 BOp->hasOneUse() && 1550 (BOp->getOpcode() == Instruction::And || 1551 BOp->getOpcode() == Instruction::Or)) { 1552 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1553 BOp->getOpcode()); 1554 // If the compares in later blocks need to use values not currently 1555 // exported from this block, export them now. This block should always 1556 // be the first entry. 1557 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1558 1559 // Allow some cases to be rejected. 1560 if (ShouldEmitAsBranches(SwitchCases)) { 1561 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1562 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1563 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1564 } 1565 1566 // Emit the branch for this block. 1567 visitSwitchCase(SwitchCases[0], BrMBB); 1568 SwitchCases.erase(SwitchCases.begin()); 1569 return; 1570 } 1571 1572 // Okay, we decided not to do this, remove any inserted MBB's and clear 1573 // SwitchCases. 1574 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1575 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1576 1577 SwitchCases.clear(); 1578 } 1579 } 1580 1581 // Create a CaseBlock record representing this branch. 1582 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1583 NULL, Succ0MBB, Succ1MBB, BrMBB); 1584 1585 // Use visitSwitchCase to actually insert the fast branch sequence for this 1586 // cond branch. 1587 visitSwitchCase(CB, BrMBB); 1588} 1589 1590/// visitSwitchCase - Emits the necessary code to represent a single node in 1591/// the binary search tree resulting from lowering a switch instruction. 1592void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1593 MachineBasicBlock *SwitchBB) { 1594 SDValue Cond; 1595 SDValue CondLHS = getValue(CB.CmpLHS); 1596 DebugLoc dl = getCurDebugLoc(); 1597 1598 // Build the setcc now. 1599 if (CB.CmpMHS == NULL) { 1600 // Fold "(X == true)" to X and "(X == false)" to !X to 1601 // handle common cases produced by branch lowering. 1602 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1603 CB.CC == ISD::SETEQ) 1604 Cond = CondLHS; 1605 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1606 CB.CC == ISD::SETEQ) { 1607 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1608 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1609 } else 1610 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1611 } else { 1612 assert(CB.CC == ISD::SETCC_INVALID && 1613 "Condition is undefined for to-the-range belonging check."); 1614 1615 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1616 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1617 1618 SDValue CmpOp = getValue(CB.CmpMHS); 1619 EVT VT = CmpOp.getValueType(); 1620 1621 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) { 1622 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1623 ISD::SETULE); 1624 } else { 1625 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1626 VT, CmpOp, DAG.getConstant(Low, VT)); 1627 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1628 DAG.getConstant(High-Low, VT), ISD::SETULE); 1629 } 1630 } 1631 1632 // Update successor info 1633 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1634 // TrueBB and FalseBB are always different unless the incoming IR is 1635 // degenerate. This only happens when running llc on weird IR. 1636 if (CB.TrueBB != CB.FalseBB) 1637 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1638 1639 // Set NextBlock to be the MBB immediately after the current one, if any. 1640 // This is used to avoid emitting unnecessary branches to the next block. 1641 MachineBasicBlock *NextBlock = 0; 1642 MachineFunction::iterator BBI = SwitchBB; 1643 if (++BBI != FuncInfo.MF->end()) 1644 NextBlock = BBI; 1645 1646 // If the lhs block is the next block, invert the condition so that we can 1647 // fall through to the lhs instead of the rhs block. 1648 if (CB.TrueBB == NextBlock) { 1649 std::swap(CB.TrueBB, CB.FalseBB); 1650 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1651 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1652 } 1653 1654 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1655 MVT::Other, getControlRoot(), Cond, 1656 DAG.getBasicBlock(CB.TrueBB)); 1657 1658 // Insert the false branch. Do this even if it's a fall through branch, 1659 // this makes it easier to do DAG optimizations which require inverting 1660 // the branch condition. 1661 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1662 DAG.getBasicBlock(CB.FalseBB)); 1663 1664 DAG.setRoot(BrCond); 1665} 1666 1667/// visitJumpTable - Emit JumpTable node in the current MBB 1668void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1669 // Emit the code for the jump table 1670 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1671 EVT PTy = TLI.getPointerTy(); 1672 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1673 JT.Reg, PTy); 1674 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1675 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1676 MVT::Other, Index.getValue(1), 1677 Table, Index); 1678 DAG.setRoot(BrJumpTable); 1679} 1680 1681/// visitJumpTableHeader - This function emits necessary code to produce index 1682/// in the JumpTable from switch case. 1683void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1684 JumpTableHeader &JTH, 1685 MachineBasicBlock *SwitchBB) { 1686 // Subtract the lowest switch case value from the value being switched on and 1687 // conditional branch to default mbb if the result is greater than the 1688 // difference between smallest and largest cases. 1689 SDValue SwitchOp = getValue(JTH.SValue); 1690 EVT VT = SwitchOp.getValueType(); 1691 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1692 DAG.getConstant(JTH.First, VT)); 1693 1694 // The SDNode we just created, which holds the value being switched on minus 1695 // the smallest case value, needs to be copied to a virtual register so it 1696 // can be used as an index into the jump table in a subsequent basic block. 1697 // This value may be smaller or larger than the target's pointer type, and 1698 // therefore require extension or truncating. 1699 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1700 1701 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1702 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1703 JumpTableReg, SwitchOp); 1704 JT.Reg = JumpTableReg; 1705 1706 // Emit the range check for the jump table, and branch to the default block 1707 // for the switch statement if the value being switched on exceeds the largest 1708 // case in the switch. 1709 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1710 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1711 DAG.getConstant(JTH.Last-JTH.First,VT), 1712 ISD::SETUGT); 1713 1714 // Set NextBlock to be the MBB immediately after the current one, if any. 1715 // This is used to avoid emitting unnecessary branches to the next block. 1716 MachineBasicBlock *NextBlock = 0; 1717 MachineFunction::iterator BBI = SwitchBB; 1718 1719 if (++BBI != FuncInfo.MF->end()) 1720 NextBlock = BBI; 1721 1722 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1723 MVT::Other, CopyTo, CMP, 1724 DAG.getBasicBlock(JT.Default)); 1725 1726 if (JT.MBB != NextBlock) 1727 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1728 DAG.getBasicBlock(JT.MBB)); 1729 1730 DAG.setRoot(BrCond); 1731} 1732 1733/// visitBitTestHeader - This function emits necessary code to produce value 1734/// suitable for "bit tests" 1735void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1736 MachineBasicBlock *SwitchBB) { 1737 // Subtract the minimum value 1738 SDValue SwitchOp = getValue(B.SValue); 1739 EVT VT = SwitchOp.getValueType(); 1740 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1741 DAG.getConstant(B.First, VT)); 1742 1743 // Check range 1744 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1745 TLI.getSetCCResultType(Sub.getValueType()), 1746 Sub, DAG.getConstant(B.Range, VT), 1747 ISD::SETUGT); 1748 1749 // Determine the type of the test operands. 1750 bool UsePtrType = false; 1751 if (!TLI.isTypeLegal(VT)) 1752 UsePtrType = true; 1753 else { 1754 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1755 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1756 // Switch table case range are encoded into series of masks. 1757 // Just use pointer type, it's guaranteed to fit. 1758 UsePtrType = true; 1759 break; 1760 } 1761 } 1762 if (UsePtrType) { 1763 VT = TLI.getPointerTy(); 1764 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1765 } 1766 1767 B.RegVT = VT.getSimpleVT(); 1768 B.Reg = FuncInfo.CreateReg(B.RegVT.getSimpleVT()); 1769 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1770 B.Reg, Sub); 1771 1772 // Set NextBlock to be the MBB immediately after the current one, if any. 1773 // This is used to avoid emitting unnecessary branches to the next block. 1774 MachineBasicBlock *NextBlock = 0; 1775 MachineFunction::iterator BBI = SwitchBB; 1776 if (++BBI != FuncInfo.MF->end()) 1777 NextBlock = BBI; 1778 1779 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1780 1781 addSuccessorWithWeight(SwitchBB, B.Default); 1782 addSuccessorWithWeight(SwitchBB, MBB); 1783 1784 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1785 MVT::Other, CopyTo, RangeCmp, 1786 DAG.getBasicBlock(B.Default)); 1787 1788 if (MBB != NextBlock) 1789 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1790 DAG.getBasicBlock(MBB)); 1791 1792 DAG.setRoot(BrRange); 1793} 1794 1795/// visitBitTestCase - this function produces one "bit test" 1796void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1797 MachineBasicBlock* NextMBB, 1798 uint32_t BranchWeightToNext, 1799 unsigned Reg, 1800 BitTestCase &B, 1801 MachineBasicBlock *SwitchBB) { 1802 EVT VT = BB.RegVT; 1803 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1804 Reg, VT); 1805 SDValue Cmp; 1806 unsigned PopCount = CountPopulation_64(B.Mask); 1807 if (PopCount == 1) { 1808 // Testing for a single bit; just compare the shift count with what it 1809 // would need to be to shift a 1 bit in that position. 1810 Cmp = DAG.getSetCC(getCurDebugLoc(), 1811 TLI.getSetCCResultType(VT), 1812 ShiftOp, 1813 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1814 ISD::SETEQ); 1815 } else if (PopCount == BB.Range) { 1816 // There is only one zero bit in the range, test for it directly. 1817 Cmp = DAG.getSetCC(getCurDebugLoc(), 1818 TLI.getSetCCResultType(VT), 1819 ShiftOp, 1820 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1821 ISD::SETNE); 1822 } else { 1823 // Make desired shift 1824 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1825 DAG.getConstant(1, VT), ShiftOp); 1826 1827 // Emit bit tests and jumps 1828 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1829 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1830 Cmp = DAG.getSetCC(getCurDebugLoc(), 1831 TLI.getSetCCResultType(VT), 1832 AndOp, DAG.getConstant(0, VT), 1833 ISD::SETNE); 1834 } 1835 1836 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight. 1837 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight); 1838 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext. 1839 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext); 1840 1841 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1842 MVT::Other, getControlRoot(), 1843 Cmp, DAG.getBasicBlock(B.TargetBB)); 1844 1845 // Set NextBlock to be the MBB immediately after the current one, if any. 1846 // This is used to avoid emitting unnecessary branches to the next block. 1847 MachineBasicBlock *NextBlock = 0; 1848 MachineFunction::iterator BBI = SwitchBB; 1849 if (++BBI != FuncInfo.MF->end()) 1850 NextBlock = BBI; 1851 1852 if (NextMBB != NextBlock) 1853 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1854 DAG.getBasicBlock(NextMBB)); 1855 1856 DAG.setRoot(BrAnd); 1857} 1858 1859void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1860 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1861 1862 // Retrieve successors. 1863 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1864 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1865 1866 const Value *Callee(I.getCalledValue()); 1867 const Function *Fn = dyn_cast<Function>(Callee); 1868 if (isa<InlineAsm>(Callee)) 1869 visitInlineAsm(&I); 1870 else if (Fn && Fn->isIntrinsic()) { 1871 assert(Fn->getIntrinsicID() == Intrinsic::donothing); 1872 // Ignore invokes to @llvm.donothing: jump directly to the next BB. 1873 } else 1874 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1875 1876 // If the value of the invoke is used outside of its defining block, make it 1877 // available as a virtual register. 1878 CopyToExportRegsIfNeeded(&I); 1879 1880 // Update successor info 1881 addSuccessorWithWeight(InvokeMBB, Return); 1882 addSuccessorWithWeight(InvokeMBB, LandingPad); 1883 1884 // Drop into normal successor. 1885 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1886 MVT::Other, getControlRoot(), 1887 DAG.getBasicBlock(Return))); 1888} 1889 1890void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1891 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1892} 1893 1894void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1895 assert(FuncInfo.MBB->isLandingPad() && 1896 "Call to landingpad not in landing pad!"); 1897 1898 MachineBasicBlock *MBB = FuncInfo.MBB; 1899 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1900 AddLandingPadInfo(LP, MMI, MBB); 1901 1902 // If there aren't registers to copy the values into (e.g., during SjLj 1903 // exceptions), then don't bother to create these DAG nodes. 1904 if (TLI.getExceptionPointerRegister() == 0 && 1905 TLI.getExceptionSelectorRegister() == 0) 1906 return; 1907 1908 SmallVector<EVT, 2> ValueVTs; 1909 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1910 1911 // Insert the EXCEPTIONADDR instruction. 1912 assert(FuncInfo.MBB->isLandingPad() && 1913 "Call to eh.exception not in landing pad!"); 1914 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1915 SDValue Ops[2]; 1916 Ops[0] = DAG.getRoot(); 1917 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1918 SDValue Chain = Op1.getValue(1); 1919 1920 // Insert the EHSELECTION instruction. 1921 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1922 Ops[0] = Op1; 1923 Ops[1] = Chain; 1924 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1925 Chain = Op2.getValue(1); 1926 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1927 1928 Ops[0] = Op1; 1929 Ops[1] = Op2; 1930 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1931 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1932 &Ops[0], 2); 1933 1934 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1935 setValue(&LP, RetPair.first); 1936 DAG.setRoot(RetPair.second); 1937} 1938 1939/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1940/// small case ranges). 1941bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1942 CaseRecVector& WorkList, 1943 const Value* SV, 1944 MachineBasicBlock *Default, 1945 MachineBasicBlock *SwitchBB) { 1946 // Size is the number of Cases represented by this range. 1947 size_t Size = CR.Range.second - CR.Range.first; 1948 if (Size > 3) 1949 return false; 1950 1951 // Get the MachineFunction which holds the current MBB. This is used when 1952 // inserting any additional MBBs necessary to represent the switch. 1953 MachineFunction *CurMF = FuncInfo.MF; 1954 1955 // Figure out which block is immediately after the current one. 1956 MachineBasicBlock *NextBlock = 0; 1957 MachineFunction::iterator BBI = CR.CaseBB; 1958 1959 if (++BBI != FuncInfo.MF->end()) 1960 NextBlock = BBI; 1961 1962 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1963 // If any two of the cases has the same destination, and if one value 1964 // is the same as the other, but has one bit unset that the other has set, 1965 // use bit manipulation to do two compares at once. For example: 1966 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1967 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1968 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1969 if (Size == 2 && CR.CaseBB == SwitchBB) { 1970 Case &Small = *CR.Range.first; 1971 Case &Big = *(CR.Range.second-1); 1972 1973 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1974 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1975 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1976 1977 // Check that there is only one bit different. 1978 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1979 (SmallValue | BigValue) == BigValue) { 1980 // Isolate the common bit. 1981 APInt CommonBit = BigValue & ~SmallValue; 1982 assert((SmallValue | CommonBit) == BigValue && 1983 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1984 1985 SDValue CondLHS = getValue(SV); 1986 EVT VT = CondLHS.getValueType(); 1987 DebugLoc DL = getCurDebugLoc(); 1988 1989 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1990 DAG.getConstant(CommonBit, VT)); 1991 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1992 Or, DAG.getConstant(BigValue, VT), 1993 ISD::SETEQ); 1994 1995 // Update successor info. 1996 // Both Small and Big will jump to Small.BB, so we sum up the weights. 1997 addSuccessorWithWeight(SwitchBB, Small.BB, 1998 Small.ExtraWeight + Big.ExtraWeight); 1999 addSuccessorWithWeight(SwitchBB, Default, 2000 // The default destination is the first successor in IR. 2001 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0); 2002 2003 // Insert the true branch. 2004 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 2005 getControlRoot(), Cond, 2006 DAG.getBasicBlock(Small.BB)); 2007 2008 // Insert the false branch. 2009 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 2010 DAG.getBasicBlock(Default)); 2011 2012 DAG.setRoot(BrCond); 2013 return true; 2014 } 2015 } 2016 } 2017 2018 // Order cases by weight so the most likely case will be checked first. 2019 uint32_t UnhandledWeights = 0; 2020 if (BPI) { 2021 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) { 2022 uint32_t IWeight = I->ExtraWeight; 2023 UnhandledWeights += IWeight; 2024 for (CaseItr J = CR.Range.first; J < I; ++J) { 2025 uint32_t JWeight = J->ExtraWeight; 2026 if (IWeight > JWeight) 2027 std::swap(*I, *J); 2028 } 2029 } 2030 } 2031 // Rearrange the case blocks so that the last one falls through if possible. 2032 Case &BackCase = *(CR.Range.second-1); 2033 if (Size > 1 && 2034 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 2035 // The last case block won't fall through into 'NextBlock' if we emit the 2036 // branches in this order. See if rearranging a case value would help. 2037 // We start at the bottom as it's the case with the least weight. 2038 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){ 2039 if (I->BB == NextBlock) { 2040 std::swap(*I, BackCase); 2041 break; 2042 } 2043 } 2044 } 2045 2046 // Create a CaseBlock record representing a conditional branch to 2047 // the Case's target mbb if the value being switched on SV is equal 2048 // to C. 2049 MachineBasicBlock *CurBlock = CR.CaseBB; 2050 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2051 MachineBasicBlock *FallThrough; 2052 if (I != E-1) { 2053 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 2054 CurMF->insert(BBI, FallThrough); 2055 2056 // Put SV in a virtual register to make it available from the new blocks. 2057 ExportFromCurrentBlock(SV); 2058 } else { 2059 // If the last case doesn't match, go to the default block. 2060 FallThrough = Default; 2061 } 2062 2063 const Value *RHS, *LHS, *MHS; 2064 ISD::CondCode CC; 2065 if (I->High == I->Low) { 2066 // This is just small small case range :) containing exactly 1 case 2067 CC = ISD::SETEQ; 2068 LHS = SV; RHS = I->High; MHS = NULL; 2069 } else { 2070 CC = ISD::SETCC_INVALID; 2071 LHS = I->Low; MHS = SV; RHS = I->High; 2072 } 2073 2074 // The false weight should be sum of all un-handled cases. 2075 UnhandledWeights -= I->ExtraWeight; 2076 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 2077 /* me */ CurBlock, 2078 /* trueweight */ I->ExtraWeight, 2079 /* falseweight */ UnhandledWeights); 2080 2081 // If emitting the first comparison, just call visitSwitchCase to emit the 2082 // code into the current block. Otherwise, push the CaseBlock onto the 2083 // vector to be later processed by SDISel, and insert the node's MBB 2084 // before the next MBB. 2085 if (CurBlock == SwitchBB) 2086 visitSwitchCase(CB, SwitchBB); 2087 else 2088 SwitchCases.push_back(CB); 2089 2090 CurBlock = FallThrough; 2091 } 2092 2093 return true; 2094} 2095 2096static inline bool areJTsAllowed(const TargetLowering &TLI) { 2097 return TLI.supportJumpTables() && 2098 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2099 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2100} 2101 2102static APInt ComputeRange(const APInt &First, const APInt &Last) { 2103 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2104 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth); 2105 return (LastExt - FirstExt + 1ULL); 2106} 2107 2108/// handleJTSwitchCase - Emit jumptable for current switch case range 2109bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2110 CaseRecVector &WorkList, 2111 const Value *SV, 2112 MachineBasicBlock *Default, 2113 MachineBasicBlock *SwitchBB) { 2114 Case& FrontCase = *CR.Range.first; 2115 Case& BackCase = *(CR.Range.second-1); 2116 2117 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2118 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2119 2120 APInt TSize(First.getBitWidth(), 0); 2121 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2122 TSize += I->size(); 2123 2124 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries())) 2125 return false; 2126 2127 APInt Range = ComputeRange(First, Last); 2128 // The density is TSize / Range. Require at least 40%. 2129 // It should not be possible for IntTSize to saturate for sane code, but make 2130 // sure we handle Range saturation correctly. 2131 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2132 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2133 if (IntTSize * 10 < IntRange * 4) 2134 return false; 2135 2136 DEBUG(dbgs() << "Lowering jump table\n" 2137 << "First entry: " << First << ". Last entry: " << Last << '\n' 2138 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2139 2140 // Get the MachineFunction which holds the current MBB. This is used when 2141 // inserting any additional MBBs necessary to represent the switch. 2142 MachineFunction *CurMF = FuncInfo.MF; 2143 2144 // Figure out which block is immediately after the current one. 2145 MachineFunction::iterator BBI = CR.CaseBB; 2146 ++BBI; 2147 2148 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2149 2150 // Create a new basic block to hold the code for loading the address 2151 // of the jump table, and jumping to it. Update successor information; 2152 // we will either branch to the default case for the switch, or the jump 2153 // table. 2154 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2155 CurMF->insert(BBI, JumpTableBB); 2156 2157 addSuccessorWithWeight(CR.CaseBB, Default); 2158 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2159 2160 // Build a vector of destination BBs, corresponding to each target 2161 // of the jump table. If the value of the jump table slot corresponds to 2162 // a case statement, push the case's BB onto the vector, otherwise, push 2163 // the default BB. 2164 std::vector<MachineBasicBlock*> DestBBs; 2165 APInt TEI = First; 2166 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2167 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2168 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2169 2170 if (Low.ule(TEI) && TEI.ule(High)) { 2171 DestBBs.push_back(I->BB); 2172 if (TEI==High) 2173 ++I; 2174 } else { 2175 DestBBs.push_back(Default); 2176 } 2177 } 2178 2179 // Calculate weight for each unique destination in CR. 2180 DenseMap<MachineBasicBlock*, uint32_t> DestWeights; 2181 if (FuncInfo.BPI) 2182 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2183 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr = 2184 DestWeights.find(I->BB); 2185 if (Itr != DestWeights.end()) 2186 Itr->second += I->ExtraWeight; 2187 else 2188 DestWeights[I->BB] = I->ExtraWeight; 2189 } 2190 2191 // Update successor info. Add one edge to each unique successor. 2192 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2193 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2194 E = DestBBs.end(); I != E; ++I) { 2195 if (!SuccsHandled[(*I)->getNumber()]) { 2196 SuccsHandled[(*I)->getNumber()] = true; 2197 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr = 2198 DestWeights.find(*I); 2199 addSuccessorWithWeight(JumpTableBB, *I, 2200 Itr != DestWeights.end() ? Itr->second : 0); 2201 } 2202 } 2203 2204 // Create a jump table index for this jump table. 2205 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2206 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2207 ->createJumpTableIndex(DestBBs); 2208 2209 // Set the jump table information so that we can codegen it as a second 2210 // MachineBasicBlock 2211 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2212 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2213 if (CR.CaseBB == SwitchBB) 2214 visitJumpTableHeader(JT, JTH, SwitchBB); 2215 2216 JTCases.push_back(JumpTableBlock(JTH, JT)); 2217 return true; 2218} 2219 2220/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2221/// 2 subtrees. 2222bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2223 CaseRecVector& WorkList, 2224 const Value* SV, 2225 MachineBasicBlock *Default, 2226 MachineBasicBlock *SwitchBB) { 2227 // Get the MachineFunction which holds the current MBB. This is used when 2228 // inserting any additional MBBs necessary to represent the switch. 2229 MachineFunction *CurMF = FuncInfo.MF; 2230 2231 // Figure out which block is immediately after the current one. 2232 MachineFunction::iterator BBI = CR.CaseBB; 2233 ++BBI; 2234 2235 Case& FrontCase = *CR.Range.first; 2236 Case& BackCase = *(CR.Range.second-1); 2237 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2238 2239 // Size is the number of Cases represented by this range. 2240 unsigned Size = CR.Range.second - CR.Range.first; 2241 2242 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2243 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2244 double FMetric = 0; 2245 CaseItr Pivot = CR.Range.first + Size/2; 2246 2247 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2248 // (heuristically) allow us to emit JumpTable's later. 2249 APInt TSize(First.getBitWidth(), 0); 2250 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2251 I!=E; ++I) 2252 TSize += I->size(); 2253 2254 APInt LSize = FrontCase.size(); 2255 APInt RSize = TSize-LSize; 2256 DEBUG(dbgs() << "Selecting best pivot: \n" 2257 << "First: " << First << ", Last: " << Last <<'\n' 2258 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2259 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2260 J!=E; ++I, ++J) { 2261 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2262 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2263 APInt Range = ComputeRange(LEnd, RBegin); 2264 assert((Range - 2ULL).isNonNegative() && 2265 "Invalid case distance"); 2266 // Use volatile double here to avoid excess precision issues on some hosts, 2267 // e.g. that use 80-bit X87 registers. 2268 volatile double LDensity = 2269 (double)LSize.roundToDouble() / 2270 (LEnd - First + 1ULL).roundToDouble(); 2271 volatile double RDensity = 2272 (double)RSize.roundToDouble() / 2273 (Last - RBegin + 1ULL).roundToDouble(); 2274 double Metric = Range.logBase2()*(LDensity+RDensity); 2275 // Should always split in some non-trivial place 2276 DEBUG(dbgs() <<"=>Step\n" 2277 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2278 << "LDensity: " << LDensity 2279 << ", RDensity: " << RDensity << '\n' 2280 << "Metric: " << Metric << '\n'); 2281 if (FMetric < Metric) { 2282 Pivot = J; 2283 FMetric = Metric; 2284 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2285 } 2286 2287 LSize += J->size(); 2288 RSize -= J->size(); 2289 } 2290 if (areJTsAllowed(TLI)) { 2291 // If our case is dense we *really* should handle it earlier! 2292 assert((FMetric > 0) && "Should handle dense range earlier!"); 2293 } else { 2294 Pivot = CR.Range.first + Size/2; 2295 } 2296 2297 CaseRange LHSR(CR.Range.first, Pivot); 2298 CaseRange RHSR(Pivot, CR.Range.second); 2299 const Constant *C = Pivot->Low; 2300 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2301 2302 // We know that we branch to the LHS if the Value being switched on is 2303 // less than the Pivot value, C. We use this to optimize our binary 2304 // tree a bit, by recognizing that if SV is greater than or equal to the 2305 // LHS's Case Value, and that Case Value is exactly one less than the 2306 // Pivot's Value, then we can branch directly to the LHS's Target, 2307 // rather than creating a leaf node for it. 2308 if ((LHSR.second - LHSR.first) == 1 && 2309 LHSR.first->High == CR.GE && 2310 cast<ConstantInt>(C)->getValue() == 2311 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2312 TrueBB = LHSR.first->BB; 2313 } else { 2314 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2315 CurMF->insert(BBI, TrueBB); 2316 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2317 2318 // Put SV in a virtual register to make it available from the new blocks. 2319 ExportFromCurrentBlock(SV); 2320 } 2321 2322 // Similar to the optimization above, if the Value being switched on is 2323 // known to be less than the Constant CR.LT, and the current Case Value 2324 // is CR.LT - 1, then we can branch directly to the target block for 2325 // the current Case Value, rather than emitting a RHS leaf node for it. 2326 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2327 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2328 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2329 FalseBB = RHSR.first->BB; 2330 } else { 2331 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2332 CurMF->insert(BBI, FalseBB); 2333 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2334 2335 // Put SV in a virtual register to make it available from the new blocks. 2336 ExportFromCurrentBlock(SV); 2337 } 2338 2339 // Create a CaseBlock record representing a conditional branch to 2340 // the LHS node if the value being switched on SV is less than C. 2341 // Otherwise, branch to LHS. 2342 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2343 2344 if (CR.CaseBB == SwitchBB) 2345 visitSwitchCase(CB, SwitchBB); 2346 else 2347 SwitchCases.push_back(CB); 2348 2349 return true; 2350} 2351 2352/// handleBitTestsSwitchCase - if current case range has few destination and 2353/// range span less, than machine word bitwidth, encode case range into series 2354/// of masks and emit bit tests with these masks. 2355bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2356 CaseRecVector& WorkList, 2357 const Value* SV, 2358 MachineBasicBlock* Default, 2359 MachineBasicBlock *SwitchBB){ 2360 EVT PTy = TLI.getPointerTy(); 2361 unsigned IntPtrBits = PTy.getSizeInBits(); 2362 2363 Case& FrontCase = *CR.Range.first; 2364 Case& BackCase = *(CR.Range.second-1); 2365 2366 // Get the MachineFunction which holds the current MBB. This is used when 2367 // inserting any additional MBBs necessary to represent the switch. 2368 MachineFunction *CurMF = FuncInfo.MF; 2369 2370 // If target does not have legal shift left, do not emit bit tests at all. 2371 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2372 return false; 2373 2374 size_t numCmps = 0; 2375 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2376 I!=E; ++I) { 2377 // Single case counts one, case range - two. 2378 numCmps += (I->Low == I->High ? 1 : 2); 2379 } 2380 2381 // Count unique destinations 2382 SmallSet<MachineBasicBlock*, 4> Dests; 2383 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2384 Dests.insert(I->BB); 2385 if (Dests.size() > 3) 2386 // Don't bother the code below, if there are too much unique destinations 2387 return false; 2388 } 2389 DEBUG(dbgs() << "Total number of unique destinations: " 2390 << Dests.size() << '\n' 2391 << "Total number of comparisons: " << numCmps << '\n'); 2392 2393 // Compute span of values. 2394 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2395 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2396 APInt cmpRange = maxValue - minValue; 2397 2398 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2399 << "Low bound: " << minValue << '\n' 2400 << "High bound: " << maxValue << '\n'); 2401 2402 if (cmpRange.uge(IntPtrBits) || 2403 (!(Dests.size() == 1 && numCmps >= 3) && 2404 !(Dests.size() == 2 && numCmps >= 5) && 2405 !(Dests.size() >= 3 && numCmps >= 6))) 2406 return false; 2407 2408 DEBUG(dbgs() << "Emitting bit tests\n"); 2409 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2410 2411 // Optimize the case where all the case values fit in a 2412 // word without having to subtract minValue. In this case, 2413 // we can optimize away the subtraction. 2414 if (maxValue.ult(IntPtrBits)) { 2415 cmpRange = maxValue; 2416 } else { 2417 lowBound = minValue; 2418 } 2419 2420 CaseBitsVector CasesBits; 2421 unsigned i, count = 0; 2422 2423 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2424 MachineBasicBlock* Dest = I->BB; 2425 for (i = 0; i < count; ++i) 2426 if (Dest == CasesBits[i].BB) 2427 break; 2428 2429 if (i == count) { 2430 assert((count < 3) && "Too much destinations to test!"); 2431 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/)); 2432 count++; 2433 } 2434 2435 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2436 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2437 2438 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2439 uint64_t hi = (highValue - lowBound).getZExtValue(); 2440 CasesBits[i].ExtraWeight += I->ExtraWeight; 2441 2442 for (uint64_t j = lo; j <= hi; j++) { 2443 CasesBits[i].Mask |= 1ULL << j; 2444 CasesBits[i].Bits++; 2445 } 2446 2447 } 2448 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2449 2450 BitTestInfo BTC; 2451 2452 // Figure out which block is immediately after the current one. 2453 MachineFunction::iterator BBI = CR.CaseBB; 2454 ++BBI; 2455 2456 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2457 2458 DEBUG(dbgs() << "Cases:\n"); 2459 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2460 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2461 << ", Bits: " << CasesBits[i].Bits 2462 << ", BB: " << CasesBits[i].BB << '\n'); 2463 2464 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2465 CurMF->insert(BBI, CaseBB); 2466 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2467 CaseBB, 2468 CasesBits[i].BB, CasesBits[i].ExtraWeight)); 2469 2470 // Put SV in a virtual register to make it available from the new blocks. 2471 ExportFromCurrentBlock(SV); 2472 } 2473 2474 BitTestBlock BTB(lowBound, cmpRange, SV, 2475 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2476 CR.CaseBB, Default, BTC); 2477 2478 if (CR.CaseBB == SwitchBB) 2479 visitBitTestHeader(BTB, SwitchBB); 2480 2481 BitTestCases.push_back(BTB); 2482 2483 return true; 2484} 2485 2486/// Clusterify - Transform simple list of Cases into list of CaseRange's 2487size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2488 const SwitchInst& SI) { 2489 2490 /// Use a shorter form of declaration, and also 2491 /// show the we want to use CRSBuilder as Clusterifier. 2492 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier; 2493 2494 Clusterifier TheClusterifier; 2495 2496 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2497 // Start with "simple" cases 2498 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end(); 2499 i != e; ++i) { 2500 const BasicBlock *SuccBB = i.getCaseSuccessor(); 2501 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2502 2503 TheClusterifier.add(i.getCaseValueEx(), SMBB, 2504 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0); 2505 } 2506 2507 TheClusterifier.optimize(); 2508 2509 size_t numCmps = 0; 2510 for (Clusterifier::RangeIterator i = TheClusterifier.begin(), 2511 e = TheClusterifier.end(); i != e; ++i, ++numCmps) { 2512 Clusterifier::Cluster &C = *i; 2513 // Update edge weight for the cluster. 2514 unsigned W = C.first.Weight; 2515 2516 // FIXME: Currently work with ConstantInt based numbers. 2517 // Changing it to APInt based is a pretty heavy for this commit. 2518 Cases.push_back(Case(C.first.getLow().toConstantInt(), 2519 C.first.getHigh().toConstantInt(), C.second, W)); 2520 2521 if (C.first.getLow() != C.first.getHigh()) 2522 // A range counts double, since it requires two compares. 2523 ++numCmps; 2524 } 2525 2526 return numCmps; 2527} 2528 2529void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2530 MachineBasicBlock *Last) { 2531 // Update JTCases. 2532 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2533 if (JTCases[i].first.HeaderBB == First) 2534 JTCases[i].first.HeaderBB = Last; 2535 2536 // Update BitTestCases. 2537 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2538 if (BitTestCases[i].Parent == First) 2539 BitTestCases[i].Parent = Last; 2540} 2541 2542void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2543 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2544 2545 // Figure out which block is immediately after the current one. 2546 MachineBasicBlock *NextBlock = 0; 2547 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2548 2549 // If there is only the default destination, branch to it if it is not the 2550 // next basic block. Otherwise, just fall through. 2551 if (!SI.getNumCases()) { 2552 // Update machine-CFG edges. 2553 2554 // If this is not a fall-through branch, emit the branch. 2555 SwitchMBB->addSuccessor(Default); 2556 if (Default != NextBlock) 2557 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2558 MVT::Other, getControlRoot(), 2559 DAG.getBasicBlock(Default))); 2560 2561 return; 2562 } 2563 2564 // If there are any non-default case statements, create a vector of Cases 2565 // representing each one, and sort the vector so that we can efficiently 2566 // create a binary search tree from them. 2567 CaseVector Cases; 2568 size_t numCmps = Clusterify(Cases, SI); 2569 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2570 << ". Total compares: " << numCmps << '\n'); 2571 (void)numCmps; 2572 2573 // Get the Value to be switched on and default basic blocks, which will be 2574 // inserted into CaseBlock records, representing basic blocks in the binary 2575 // search tree. 2576 const Value *SV = SI.getCondition(); 2577 2578 // Push the initial CaseRec onto the worklist 2579 CaseRecVector WorkList; 2580 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2581 CaseRange(Cases.begin(),Cases.end()))); 2582 2583 while (!WorkList.empty()) { 2584 // Grab a record representing a case range to process off the worklist 2585 CaseRec CR = WorkList.back(); 2586 WorkList.pop_back(); 2587 2588 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2589 continue; 2590 2591 // If the range has few cases (two or less) emit a series of specific 2592 // tests. 2593 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2594 continue; 2595 2596 // If the switch has more than N blocks, and is at least 40% dense, and the 2597 // target supports indirect branches, then emit a jump table rather than 2598 // lowering the switch to a binary tree of conditional branches. 2599 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries(). 2600 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2601 continue; 2602 2603 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2604 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2605 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2606 } 2607} 2608 2609void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2610 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2611 2612 // Update machine-CFG edges with unique successors. 2613 SmallSet<BasicBlock*, 32> Done; 2614 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) { 2615 BasicBlock *BB = I.getSuccessor(i); 2616 bool Inserted = Done.insert(BB); 2617 if (!Inserted) 2618 continue; 2619 2620 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB]; 2621 addSuccessorWithWeight(IndirectBrMBB, Succ); 2622 } 2623 2624 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2625 MVT::Other, getControlRoot(), 2626 getValue(I.getAddress()))); 2627} 2628 2629void SelectionDAGBuilder::visitFSub(const User &I) { 2630 // -0.0 - X --> fneg 2631 Type *Ty = I.getType(); 2632 if (isa<Constant>(I.getOperand(0)) && 2633 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2634 SDValue Op2 = getValue(I.getOperand(1)); 2635 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2636 Op2.getValueType(), Op2)); 2637 return; 2638 } 2639 2640 visitBinary(I, ISD::FSUB); 2641} 2642 2643void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2644 SDValue Op1 = getValue(I.getOperand(0)); 2645 SDValue Op2 = getValue(I.getOperand(1)); 2646 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2647 Op1.getValueType(), Op1, Op2)); 2648} 2649 2650void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2651 SDValue Op1 = getValue(I.getOperand(0)); 2652 SDValue Op2 = getValue(I.getOperand(1)); 2653 2654 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2655 2656 // Coerce the shift amount to the right type if we can. 2657 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2658 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2659 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2660 DebugLoc DL = getCurDebugLoc(); 2661 2662 // If the operand is smaller than the shift count type, promote it. 2663 if (ShiftSize > Op2Size) 2664 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2665 2666 // If the operand is larger than the shift count type but the shift 2667 // count type has enough bits to represent any shift value, truncate 2668 // it now. This is a common case and it exposes the truncate to 2669 // optimization early. 2670 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2671 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2672 // Otherwise we'll need to temporarily settle for some other convenient 2673 // type. Type legalization will make adjustments once the shiftee is split. 2674 else 2675 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2676 } 2677 2678 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2679 Op1.getValueType(), Op1, Op2)); 2680} 2681 2682void SelectionDAGBuilder::visitSDiv(const User &I) { 2683 SDValue Op1 = getValue(I.getOperand(0)); 2684 SDValue Op2 = getValue(I.getOperand(1)); 2685 2686 // Turn exact SDivs into multiplications. 2687 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2688 // exact bit. 2689 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2690 !isa<ConstantSDNode>(Op1) && 2691 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2692 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2693 else 2694 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2695 Op1, Op2)); 2696} 2697 2698void SelectionDAGBuilder::visitICmp(const User &I) { 2699 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2700 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2701 predicate = IC->getPredicate(); 2702 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2703 predicate = ICmpInst::Predicate(IC->getPredicate()); 2704 SDValue Op1 = getValue(I.getOperand(0)); 2705 SDValue Op2 = getValue(I.getOperand(1)); 2706 ISD::CondCode Opcode = getICmpCondCode(predicate); 2707 2708 EVT DestVT = TLI.getValueType(I.getType()); 2709 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2710} 2711 2712void SelectionDAGBuilder::visitFCmp(const User &I) { 2713 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2714 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2715 predicate = FC->getPredicate(); 2716 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2717 predicate = FCmpInst::Predicate(FC->getPredicate()); 2718 SDValue Op1 = getValue(I.getOperand(0)); 2719 SDValue Op2 = getValue(I.getOperand(1)); 2720 ISD::CondCode Condition = getFCmpCondCode(predicate); 2721 if (TM.Options.NoNaNsFPMath) 2722 Condition = getFCmpCodeWithoutNaN(Condition); 2723 EVT DestVT = TLI.getValueType(I.getType()); 2724 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2725} 2726 2727void SelectionDAGBuilder::visitSelect(const User &I) { 2728 SmallVector<EVT, 4> ValueVTs; 2729 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2730 unsigned NumValues = ValueVTs.size(); 2731 if (NumValues == 0) return; 2732 2733 SmallVector<SDValue, 4> Values(NumValues); 2734 SDValue Cond = getValue(I.getOperand(0)); 2735 SDValue TrueVal = getValue(I.getOperand(1)); 2736 SDValue FalseVal = getValue(I.getOperand(2)); 2737 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2738 ISD::VSELECT : ISD::SELECT; 2739 2740 for (unsigned i = 0; i != NumValues; ++i) 2741 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2742 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2743 Cond, 2744 SDValue(TrueVal.getNode(), 2745 TrueVal.getResNo() + i), 2746 SDValue(FalseVal.getNode(), 2747 FalseVal.getResNo() + i)); 2748 2749 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2750 DAG.getVTList(&ValueVTs[0], NumValues), 2751 &Values[0], NumValues)); 2752} 2753 2754void SelectionDAGBuilder::visitTrunc(const User &I) { 2755 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2756 SDValue N = getValue(I.getOperand(0)); 2757 EVT DestVT = TLI.getValueType(I.getType()); 2758 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2759} 2760 2761void SelectionDAGBuilder::visitZExt(const User &I) { 2762 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2763 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2764 SDValue N = getValue(I.getOperand(0)); 2765 EVT DestVT = TLI.getValueType(I.getType()); 2766 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2767} 2768 2769void SelectionDAGBuilder::visitSExt(const User &I) { 2770 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2771 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2772 SDValue N = getValue(I.getOperand(0)); 2773 EVT DestVT = TLI.getValueType(I.getType()); 2774 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2775} 2776 2777void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2778 // FPTrunc is never a no-op cast, no need to check 2779 SDValue N = getValue(I.getOperand(0)); 2780 EVT DestVT = TLI.getValueType(I.getType()); 2781 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2782 DestVT, N, 2783 DAG.getTargetConstant(0, TLI.getPointerTy()))); 2784} 2785 2786void SelectionDAGBuilder::visitFPExt(const User &I){ 2787 // FPExt is never a no-op cast, no need to check 2788 SDValue N = getValue(I.getOperand(0)); 2789 EVT DestVT = TLI.getValueType(I.getType()); 2790 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2791} 2792 2793void SelectionDAGBuilder::visitFPToUI(const User &I) { 2794 // FPToUI is never a no-op cast, no need to check 2795 SDValue N = getValue(I.getOperand(0)); 2796 EVT DestVT = TLI.getValueType(I.getType()); 2797 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2798} 2799 2800void SelectionDAGBuilder::visitFPToSI(const User &I) { 2801 // FPToSI is never a no-op cast, no need to check 2802 SDValue N = getValue(I.getOperand(0)); 2803 EVT DestVT = TLI.getValueType(I.getType()); 2804 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2805} 2806 2807void SelectionDAGBuilder::visitUIToFP(const User &I) { 2808 // UIToFP is never a no-op cast, no need to check 2809 SDValue N = getValue(I.getOperand(0)); 2810 EVT DestVT = TLI.getValueType(I.getType()); 2811 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2812} 2813 2814void SelectionDAGBuilder::visitSIToFP(const User &I){ 2815 // SIToFP is never a no-op cast, no need to check 2816 SDValue N = getValue(I.getOperand(0)); 2817 EVT DestVT = TLI.getValueType(I.getType()); 2818 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2819} 2820 2821void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2822 // What to do depends on the size of the integer and the size of the pointer. 2823 // We can either truncate, zero extend, or no-op, accordingly. 2824 SDValue N = getValue(I.getOperand(0)); 2825 EVT DestVT = TLI.getValueType(I.getType()); 2826 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2827} 2828 2829void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2830 // What to do depends on the size of the integer and the size of the pointer. 2831 // We can either truncate, zero extend, or no-op, accordingly. 2832 SDValue N = getValue(I.getOperand(0)); 2833 EVT DestVT = TLI.getValueType(I.getType()); 2834 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2835} 2836 2837void SelectionDAGBuilder::visitBitCast(const User &I) { 2838 SDValue N = getValue(I.getOperand(0)); 2839 EVT DestVT = TLI.getValueType(I.getType()); 2840 2841 // BitCast assures us that source and destination are the same size so this is 2842 // either a BITCAST or a no-op. 2843 if (DestVT != N.getValueType()) 2844 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2845 DestVT, N)); // convert types. 2846 else 2847 setValue(&I, N); // noop cast. 2848} 2849 2850void SelectionDAGBuilder::visitInsertElement(const User &I) { 2851 SDValue InVec = getValue(I.getOperand(0)); 2852 SDValue InVal = getValue(I.getOperand(1)); 2853 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2854 TLI.getPointerTy(), 2855 getValue(I.getOperand(2))); 2856 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2857 TLI.getValueType(I.getType()), 2858 InVec, InVal, InIdx)); 2859} 2860 2861void SelectionDAGBuilder::visitExtractElement(const User &I) { 2862 SDValue InVec = getValue(I.getOperand(0)); 2863 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2864 TLI.getPointerTy(), 2865 getValue(I.getOperand(1))); 2866 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2867 TLI.getValueType(I.getType()), InVec, InIdx)); 2868} 2869 2870// Utility for visitShuffleVector - Return true if every element in Mask, 2871// beginning from position Pos and ending in Pos+Size, falls within the 2872// specified sequential range [L, L+Pos). or is undef. 2873static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2874 unsigned Pos, unsigned Size, int Low) { 2875 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2876 if (Mask[i] >= 0 && Mask[i] != Low) 2877 return false; 2878 return true; 2879} 2880 2881void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2882 SDValue Src1 = getValue(I.getOperand(0)); 2883 SDValue Src2 = getValue(I.getOperand(1)); 2884 2885 SmallVector<int, 8> Mask; 2886 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); 2887 unsigned MaskNumElts = Mask.size(); 2888 2889 EVT VT = TLI.getValueType(I.getType()); 2890 EVT SrcVT = Src1.getValueType(); 2891 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2892 2893 if (SrcNumElts == MaskNumElts) { 2894 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2895 &Mask[0])); 2896 return; 2897 } 2898 2899 // Normalize the shuffle vector since mask and vector length don't match. 2900 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2901 // Mask is longer than the source vectors and is a multiple of the source 2902 // vectors. We can use concatenate vector to make the mask and vectors 2903 // lengths match. 2904 if (SrcNumElts*2 == MaskNumElts) { 2905 // First check for Src1 in low and Src2 in high 2906 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 2907 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 2908 // The shuffle is concatenating two vectors together. 2909 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2910 VT, Src1, Src2)); 2911 return; 2912 } 2913 // Then check for Src2 in low and Src1 in high 2914 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 2915 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 2916 // The shuffle is concatenating two vectors together. 2917 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2918 VT, Src2, Src1)); 2919 return; 2920 } 2921 } 2922 2923 // Pad both vectors with undefs to make them the same length as the mask. 2924 unsigned NumConcat = MaskNumElts / SrcNumElts; 2925 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2926 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2927 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2928 2929 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2930 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2931 MOps1[0] = Src1; 2932 MOps2[0] = Src2; 2933 2934 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2935 getCurDebugLoc(), VT, 2936 &MOps1[0], NumConcat); 2937 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2938 getCurDebugLoc(), VT, 2939 &MOps2[0], NumConcat); 2940 2941 // Readjust mask for new input vector length. 2942 SmallVector<int, 8> MappedOps; 2943 for (unsigned i = 0; i != MaskNumElts; ++i) { 2944 int Idx = Mask[i]; 2945 if (Idx >= (int)SrcNumElts) 2946 Idx -= SrcNumElts - MaskNumElts; 2947 MappedOps.push_back(Idx); 2948 } 2949 2950 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2951 &MappedOps[0])); 2952 return; 2953 } 2954 2955 if (SrcNumElts > MaskNumElts) { 2956 // Analyze the access pattern of the vector to see if we can extract 2957 // two subvectors and do the shuffle. The analysis is done by calculating 2958 // the range of elements the mask access on both vectors. 2959 int MinRange[2] = { static_cast<int>(SrcNumElts), 2960 static_cast<int>(SrcNumElts)}; 2961 int MaxRange[2] = {-1, -1}; 2962 2963 for (unsigned i = 0; i != MaskNumElts; ++i) { 2964 int Idx = Mask[i]; 2965 unsigned Input = 0; 2966 if (Idx < 0) 2967 continue; 2968 2969 if (Idx >= (int)SrcNumElts) { 2970 Input = 1; 2971 Idx -= SrcNumElts; 2972 } 2973 if (Idx > MaxRange[Input]) 2974 MaxRange[Input] = Idx; 2975 if (Idx < MinRange[Input]) 2976 MinRange[Input] = Idx; 2977 } 2978 2979 // Check if the access is smaller than the vector size and can we find 2980 // a reasonable extract index. 2981 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not 2982 // Extract. 2983 int StartIdx[2]; // StartIdx to extract from 2984 for (unsigned Input = 0; Input < 2; ++Input) { 2985 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) { 2986 RangeUse[Input] = 0; // Unused 2987 StartIdx[Input] = 0; 2988 continue; 2989 } 2990 2991 // Find a good start index that is a multiple of the mask length. Then 2992 // see if the rest of the elements are in range. 2993 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2994 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2995 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2996 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2997 } 2998 2999 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 3000 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 3001 return; 3002 } 3003 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) { 3004 // Extract appropriate subvector and generate a vector shuffle 3005 for (unsigned Input = 0; Input < 2; ++Input) { 3006 SDValue &Src = Input == 0 ? Src1 : Src2; 3007 if (RangeUse[Input] == 0) 3008 Src = DAG.getUNDEF(VT); 3009 else 3010 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 3011 Src, DAG.getIntPtrConstant(StartIdx[Input])); 3012 } 3013 3014 // Calculate new mask. 3015 SmallVector<int, 8> MappedOps; 3016 for (unsigned i = 0; i != MaskNumElts; ++i) { 3017 int Idx = Mask[i]; 3018 if (Idx >= 0) { 3019 if (Idx < (int)SrcNumElts) 3020 Idx -= StartIdx[0]; 3021 else 3022 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; 3023 } 3024 MappedOps.push_back(Idx); 3025 } 3026 3027 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 3028 &MappedOps[0])); 3029 return; 3030 } 3031 } 3032 3033 // We can't use either concat vectors or extract subvectors so fall back to 3034 // replacing the shuffle with extract and build vector. 3035 // to insert and build vector. 3036 EVT EltVT = VT.getVectorElementType(); 3037 EVT PtrVT = TLI.getPointerTy(); 3038 SmallVector<SDValue,8> Ops; 3039 for (unsigned i = 0; i != MaskNumElts; ++i) { 3040 int Idx = Mask[i]; 3041 SDValue Res; 3042 3043 if (Idx < 0) { 3044 Res = DAG.getUNDEF(EltVT); 3045 } else { 3046 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; 3047 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; 3048 3049 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 3050 EltVT, Src, DAG.getConstant(Idx, PtrVT)); 3051 } 3052 3053 Ops.push_back(Res); 3054 } 3055 3056 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 3057 VT, &Ops[0], Ops.size())); 3058} 3059 3060void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 3061 const Value *Op0 = I.getOperand(0); 3062 const Value *Op1 = I.getOperand(1); 3063 Type *AggTy = I.getType(); 3064 Type *ValTy = Op1->getType(); 3065 bool IntoUndef = isa<UndefValue>(Op0); 3066 bool FromUndef = isa<UndefValue>(Op1); 3067 3068 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3069 3070 SmallVector<EVT, 4> AggValueVTs; 3071 ComputeValueVTs(TLI, AggTy, AggValueVTs); 3072 SmallVector<EVT, 4> ValValueVTs; 3073 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3074 3075 unsigned NumAggValues = AggValueVTs.size(); 3076 unsigned NumValValues = ValValueVTs.size(); 3077 SmallVector<SDValue, 4> Values(NumAggValues); 3078 3079 SDValue Agg = getValue(Op0); 3080 unsigned i = 0; 3081 // Copy the beginning value(s) from the original aggregate. 3082 for (; i != LinearIndex; ++i) 3083 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3084 SDValue(Agg.getNode(), Agg.getResNo() + i); 3085 // Copy values from the inserted value(s). 3086 if (NumValValues) { 3087 SDValue Val = getValue(Op1); 3088 for (; i != LinearIndex + NumValValues; ++i) 3089 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3090 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3091 } 3092 // Copy remaining value(s) from the original aggregate. 3093 for (; i != NumAggValues; ++i) 3094 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3095 SDValue(Agg.getNode(), Agg.getResNo() + i); 3096 3097 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3098 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3099 &Values[0], NumAggValues)); 3100} 3101 3102void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3103 const Value *Op0 = I.getOperand(0); 3104 Type *AggTy = Op0->getType(); 3105 Type *ValTy = I.getType(); 3106 bool OutOfUndef = isa<UndefValue>(Op0); 3107 3108 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3109 3110 SmallVector<EVT, 4> ValValueVTs; 3111 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3112 3113 unsigned NumValValues = ValValueVTs.size(); 3114 3115 // Ignore a extractvalue that produces an empty object 3116 if (!NumValValues) { 3117 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3118 return; 3119 } 3120 3121 SmallVector<SDValue, 4> Values(NumValValues); 3122 3123 SDValue Agg = getValue(Op0); 3124 // Copy out the selected value(s). 3125 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3126 Values[i - LinearIndex] = 3127 OutOfUndef ? 3128 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3129 SDValue(Agg.getNode(), Agg.getResNo() + i); 3130 3131 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3132 DAG.getVTList(&ValValueVTs[0], NumValValues), 3133 &Values[0], NumValValues)); 3134} 3135 3136void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3137 SDValue N = getValue(I.getOperand(0)); 3138 // Note that the pointer operand may be a vector of pointers. Take the scalar 3139 // element which holds a pointer. 3140 Type *Ty = I.getOperand(0)->getType()->getScalarType(); 3141 3142 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3143 OI != E; ++OI) { 3144 const Value *Idx = *OI; 3145 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3146 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue(); 3147 if (Field) { 3148 // N = N + Offset 3149 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3150 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3151 DAG.getConstant(Offset, N.getValueType())); 3152 } 3153 3154 Ty = StTy->getElementType(Field); 3155 } else { 3156 Ty = cast<SequentialType>(Ty)->getElementType(); 3157 3158 // If this is a constant subscript, handle it quickly. 3159 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3160 if (CI->isZero()) continue; 3161 uint64_t Offs = 3162 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3163 SDValue OffsVal; 3164 EVT PTy = TLI.getPointerTy(); 3165 unsigned PtrBits = PTy.getSizeInBits(); 3166 if (PtrBits < 64) 3167 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3168 TLI.getPointerTy(), 3169 DAG.getConstant(Offs, MVT::i64)); 3170 else 3171 OffsVal = DAG.getIntPtrConstant(Offs); 3172 3173 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3174 OffsVal); 3175 continue; 3176 } 3177 3178 // N = N + Idx * ElementSize; 3179 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3180 TD->getTypeAllocSize(Ty)); 3181 SDValue IdxN = getValue(Idx); 3182 3183 // If the index is smaller or larger than intptr_t, truncate or extend 3184 // it. 3185 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3186 3187 // If this is a multiply by a power of two, turn it into a shl 3188 // immediately. This is a very common case. 3189 if (ElementSize != 1) { 3190 if (ElementSize.isPowerOf2()) { 3191 unsigned Amt = ElementSize.logBase2(); 3192 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3193 N.getValueType(), IdxN, 3194 DAG.getConstant(Amt, IdxN.getValueType())); 3195 } else { 3196 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType()); 3197 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3198 N.getValueType(), IdxN, Scale); 3199 } 3200 } 3201 3202 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3203 N.getValueType(), N, IdxN); 3204 } 3205 } 3206 3207 setValue(&I, N); 3208} 3209 3210void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3211 // If this is a fixed sized alloca in the entry block of the function, 3212 // allocate it statically on the stack. 3213 if (FuncInfo.StaticAllocaMap.count(&I)) 3214 return; // getValue will auto-populate this. 3215 3216 Type *Ty = I.getAllocatedType(); 3217 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty); 3218 unsigned Align = 3219 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty), 3220 I.getAlignment()); 3221 3222 SDValue AllocSize = getValue(I.getArraySize()); 3223 3224 EVT IntPtr = TLI.getPointerTy(); 3225 if (AllocSize.getValueType() != IntPtr) 3226 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3227 3228 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3229 AllocSize, 3230 DAG.getConstant(TySize, IntPtr)); 3231 3232 // Handle alignment. If the requested alignment is less than or equal to 3233 // the stack alignment, ignore it. If the size is greater than or equal to 3234 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3235 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3236 if (Align <= StackAlign) 3237 Align = 0; 3238 3239 // Round the size of the allocation up to the stack alignment size 3240 // by add SA-1 to the size. 3241 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3242 AllocSize.getValueType(), AllocSize, 3243 DAG.getIntPtrConstant(StackAlign-1)); 3244 3245 // Mask out the low bits for alignment purposes. 3246 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3247 AllocSize.getValueType(), AllocSize, 3248 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3249 3250 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3251 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3252 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3253 VTs, Ops, 3); 3254 setValue(&I, DSA); 3255 DAG.setRoot(DSA.getValue(1)); 3256 3257 // Inform the Frame Information that we have just allocated a variable-sized 3258 // object. 3259 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3260} 3261 3262void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3263 if (I.isAtomic()) 3264 return visitAtomicLoad(I); 3265 3266 const Value *SV = I.getOperand(0); 3267 SDValue Ptr = getValue(SV); 3268 3269 Type *Ty = I.getType(); 3270 3271 bool isVolatile = I.isVolatile(); 3272 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3273 bool isInvariant = I.getMetadata("invariant.load") != 0; 3274 unsigned Alignment = I.getAlignment(); 3275 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3276 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 3277 3278 SmallVector<EVT, 4> ValueVTs; 3279 SmallVector<uint64_t, 4> Offsets; 3280 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3281 unsigned NumValues = ValueVTs.size(); 3282 if (NumValues == 0) 3283 return; 3284 3285 SDValue Root; 3286 bool ConstantMemory = false; 3287 if (I.isVolatile() || NumValues > MaxParallelChains) 3288 // Serialize volatile loads with other side effects. 3289 Root = getRoot(); 3290 else if (AA->pointsToConstantMemory( 3291 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3292 // Do not serialize (non-volatile) loads of constant memory with anything. 3293 Root = DAG.getEntryNode(); 3294 ConstantMemory = true; 3295 } else { 3296 // Do not serialize non-volatile loads against each other. 3297 Root = DAG.getRoot(); 3298 } 3299 3300 SmallVector<SDValue, 4> Values(NumValues); 3301 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3302 NumValues)); 3303 EVT PtrVT = Ptr.getValueType(); 3304 unsigned ChainI = 0; 3305 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3306 // Serializing loads here may result in excessive register pressure, and 3307 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3308 // could recover a bit by hoisting nodes upward in the chain by recognizing 3309 // they are side-effect free or do not alias. The optimizer should really 3310 // avoid this case by converting large object/array copies to llvm.memcpy 3311 // (MaxParallelChains should always remain as failsafe). 3312 if (ChainI == MaxParallelChains) { 3313 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3314 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3315 MVT::Other, &Chains[0], ChainI); 3316 Root = Chain; 3317 ChainI = 0; 3318 } 3319 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3320 PtrVT, Ptr, 3321 DAG.getConstant(Offsets[i], PtrVT)); 3322 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3323 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3324 isNonTemporal, isInvariant, Alignment, TBAAInfo, 3325 Ranges); 3326 3327 Values[i] = L; 3328 Chains[ChainI] = L.getValue(1); 3329 } 3330 3331 if (!ConstantMemory) { 3332 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3333 MVT::Other, &Chains[0], ChainI); 3334 if (isVolatile) 3335 DAG.setRoot(Chain); 3336 else 3337 PendingLoads.push_back(Chain); 3338 } 3339 3340 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3341 DAG.getVTList(&ValueVTs[0], NumValues), 3342 &Values[0], NumValues)); 3343} 3344 3345void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3346 if (I.isAtomic()) 3347 return visitAtomicStore(I); 3348 3349 const Value *SrcV = I.getOperand(0); 3350 const Value *PtrV = I.getOperand(1); 3351 3352 SmallVector<EVT, 4> ValueVTs; 3353 SmallVector<uint64_t, 4> Offsets; 3354 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3355 unsigned NumValues = ValueVTs.size(); 3356 if (NumValues == 0) 3357 return; 3358 3359 // Get the lowered operands. Note that we do this after 3360 // checking if NumResults is zero, because with zero results 3361 // the operands won't have values in the map. 3362 SDValue Src = getValue(SrcV); 3363 SDValue Ptr = getValue(PtrV); 3364 3365 SDValue Root = getRoot(); 3366 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3367 NumValues)); 3368 EVT PtrVT = Ptr.getValueType(); 3369 bool isVolatile = I.isVolatile(); 3370 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3371 unsigned Alignment = I.getAlignment(); 3372 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3373 3374 unsigned ChainI = 0; 3375 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3376 // See visitLoad comments. 3377 if (ChainI == MaxParallelChains) { 3378 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3379 MVT::Other, &Chains[0], ChainI); 3380 Root = Chain; 3381 ChainI = 0; 3382 } 3383 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3384 DAG.getConstant(Offsets[i], PtrVT)); 3385 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3386 SDValue(Src.getNode(), Src.getResNo() + i), 3387 Add, MachinePointerInfo(PtrV, Offsets[i]), 3388 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3389 Chains[ChainI] = St; 3390 } 3391 3392 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3393 MVT::Other, &Chains[0], ChainI); 3394 ++SDNodeOrder; 3395 AssignOrderingToNode(StoreNode.getNode()); 3396 DAG.setRoot(StoreNode); 3397} 3398 3399static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3400 SynchronizationScope Scope, 3401 bool Before, DebugLoc dl, 3402 SelectionDAG &DAG, 3403 const TargetLowering &TLI) { 3404 // Fence, if necessary 3405 if (Before) { 3406 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3407 Order = Release; 3408 else if (Order == Acquire || Order == Monotonic) 3409 return Chain; 3410 } else { 3411 if (Order == AcquireRelease) 3412 Order = Acquire; 3413 else if (Order == Release || Order == Monotonic) 3414 return Chain; 3415 } 3416 SDValue Ops[3]; 3417 Ops[0] = Chain; 3418 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3419 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3420 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3421} 3422 3423void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3424 DebugLoc dl = getCurDebugLoc(); 3425 AtomicOrdering Order = I.getOrdering(); 3426 SynchronizationScope Scope = I.getSynchScope(); 3427 3428 SDValue InChain = getRoot(); 3429 3430 if (TLI.getInsertFencesForAtomic()) 3431 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3432 DAG, TLI); 3433 3434 SDValue L = 3435 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3436 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3437 InChain, 3438 getValue(I.getPointerOperand()), 3439 getValue(I.getCompareOperand()), 3440 getValue(I.getNewValOperand()), 3441 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3442 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3443 Scope); 3444 3445 SDValue OutChain = L.getValue(1); 3446 3447 if (TLI.getInsertFencesForAtomic()) 3448 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3449 DAG, TLI); 3450 3451 setValue(&I, L); 3452 DAG.setRoot(OutChain); 3453} 3454 3455void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3456 DebugLoc dl = getCurDebugLoc(); 3457 ISD::NodeType NT; 3458 switch (I.getOperation()) { 3459 default: llvm_unreachable("Unknown atomicrmw operation"); 3460 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3461 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3462 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3463 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3464 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3465 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3466 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3467 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3468 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3469 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3470 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3471 } 3472 AtomicOrdering Order = I.getOrdering(); 3473 SynchronizationScope Scope = I.getSynchScope(); 3474 3475 SDValue InChain = getRoot(); 3476 3477 if (TLI.getInsertFencesForAtomic()) 3478 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3479 DAG, TLI); 3480 3481 SDValue L = 3482 DAG.getAtomic(NT, dl, 3483 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3484 InChain, 3485 getValue(I.getPointerOperand()), 3486 getValue(I.getValOperand()), 3487 I.getPointerOperand(), 0 /* Alignment */, 3488 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3489 Scope); 3490 3491 SDValue OutChain = L.getValue(1); 3492 3493 if (TLI.getInsertFencesForAtomic()) 3494 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3495 DAG, TLI); 3496 3497 setValue(&I, L); 3498 DAG.setRoot(OutChain); 3499} 3500 3501void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3502 DebugLoc dl = getCurDebugLoc(); 3503 SDValue Ops[3]; 3504 Ops[0] = getRoot(); 3505 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3506 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3507 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3508} 3509 3510void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3511 DebugLoc dl = getCurDebugLoc(); 3512 AtomicOrdering Order = I.getOrdering(); 3513 SynchronizationScope Scope = I.getSynchScope(); 3514 3515 SDValue InChain = getRoot(); 3516 3517 EVT VT = TLI.getValueType(I.getType()); 3518 3519 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3520 report_fatal_error("Cannot generate unaligned atomic load"); 3521 3522 SDValue L = 3523 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3524 getValue(I.getPointerOperand()), 3525 I.getPointerOperand(), I.getAlignment(), 3526 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3527 Scope); 3528 3529 SDValue OutChain = L.getValue(1); 3530 3531 if (TLI.getInsertFencesForAtomic()) 3532 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3533 DAG, TLI); 3534 3535 setValue(&I, L); 3536 DAG.setRoot(OutChain); 3537} 3538 3539void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3540 DebugLoc dl = getCurDebugLoc(); 3541 3542 AtomicOrdering Order = I.getOrdering(); 3543 SynchronizationScope Scope = I.getSynchScope(); 3544 3545 SDValue InChain = getRoot(); 3546 3547 EVT VT = TLI.getValueType(I.getValueOperand()->getType()); 3548 3549 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3550 report_fatal_error("Cannot generate unaligned atomic store"); 3551 3552 if (TLI.getInsertFencesForAtomic()) 3553 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3554 DAG, TLI); 3555 3556 SDValue OutChain = 3557 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3558 InChain, 3559 getValue(I.getPointerOperand()), 3560 getValue(I.getValueOperand()), 3561 I.getPointerOperand(), I.getAlignment(), 3562 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3563 Scope); 3564 3565 if (TLI.getInsertFencesForAtomic()) 3566 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3567 DAG, TLI); 3568 3569 DAG.setRoot(OutChain); 3570} 3571 3572/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3573/// node. 3574void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3575 unsigned Intrinsic) { 3576 bool HasChain = !I.doesNotAccessMemory(); 3577 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3578 3579 // Build the operand list. 3580 SmallVector<SDValue, 8> Ops; 3581 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3582 if (OnlyLoad) { 3583 // We don't need to serialize loads against other loads. 3584 Ops.push_back(DAG.getRoot()); 3585 } else { 3586 Ops.push_back(getRoot()); 3587 } 3588 } 3589 3590 // Info is set by getTgtMemInstrinsic 3591 TargetLowering::IntrinsicInfo Info; 3592 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3593 3594 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3595 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3596 Info.opc == ISD::INTRINSIC_W_CHAIN) 3597 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy())); 3598 3599 // Add all operands of the call to the operand list. 3600 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3601 SDValue Op = getValue(I.getArgOperand(i)); 3602 Ops.push_back(Op); 3603 } 3604 3605 SmallVector<EVT, 4> ValueVTs; 3606 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3607 3608 if (HasChain) 3609 ValueVTs.push_back(MVT::Other); 3610 3611 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3612 3613 // Create the node. 3614 SDValue Result; 3615 if (IsTgtIntrinsic) { 3616 // This is target intrinsic that touches memory 3617 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3618 VTs, &Ops[0], Ops.size(), 3619 Info.memVT, 3620 MachinePointerInfo(Info.ptrVal, Info.offset), 3621 Info.align, Info.vol, 3622 Info.readMem, Info.writeMem); 3623 } else if (!HasChain) { 3624 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3625 VTs, &Ops[0], Ops.size()); 3626 } else if (!I.getType()->isVoidTy()) { 3627 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3628 VTs, &Ops[0], Ops.size()); 3629 } else { 3630 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3631 VTs, &Ops[0], Ops.size()); 3632 } 3633 3634 if (HasChain) { 3635 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3636 if (OnlyLoad) 3637 PendingLoads.push_back(Chain); 3638 else 3639 DAG.setRoot(Chain); 3640 } 3641 3642 if (!I.getType()->isVoidTy()) { 3643 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3644 EVT VT = TLI.getValueType(PTy); 3645 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3646 } 3647 3648 setValue(&I, Result); 3649 } else { 3650 // Assign order to result here. If the intrinsic does not produce a result, 3651 // it won't be mapped to a SDNode and visit() will not assign it an order 3652 // number. 3653 ++SDNodeOrder; 3654 AssignOrderingToNode(Result.getNode()); 3655 } 3656} 3657 3658/// GetSignificand - Get the significand and build it into a floating-point 3659/// number with exponent of 1: 3660/// 3661/// Op = (Op & 0x007fffff) | 0x3f800000; 3662/// 3663/// where Op is the hexidecimal representation of floating point value. 3664static SDValue 3665GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3666 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3667 DAG.getConstant(0x007fffff, MVT::i32)); 3668 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3669 DAG.getConstant(0x3f800000, MVT::i32)); 3670 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3671} 3672 3673/// GetExponent - Get the exponent: 3674/// 3675/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3676/// 3677/// where Op is the hexidecimal representation of floating point value. 3678static SDValue 3679GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3680 DebugLoc dl) { 3681 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3682 DAG.getConstant(0x7f800000, MVT::i32)); 3683 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3684 DAG.getConstant(23, TLI.getPointerTy())); 3685 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3686 DAG.getConstant(127, MVT::i32)); 3687 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3688} 3689 3690/// getF32Constant - Get 32-bit floating point constant. 3691static SDValue 3692getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3693 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3694} 3695 3696/// expandExp - Lower an exp intrinsic. Handles the special sequences for 3697/// limited-precision mode. 3698static SDValue expandExp(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 3699 const TargetLowering &TLI) { 3700 if (Op.getValueType() == MVT::f32 && 3701 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3702 3703 // Put the exponent in the right bit position for later addition to the 3704 // final result: 3705 // 3706 // #define LOG2OFe 1.4426950f 3707 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3708 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3709 getF32Constant(DAG, 0x3fb8aa3b)); 3710 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3711 3712 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3713 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3714 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3715 3716 // IntegerPartOfX <<= 23; 3717 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3718 DAG.getConstant(23, TLI.getPointerTy())); 3719 3720 SDValue TwoToFracPartOfX; 3721 if (LimitFloatPrecision <= 6) { 3722 // For floating-point precision of 6: 3723 // 3724 // TwoToFractionalPartOfX = 3725 // 0.997535578f + 3726 // (0.735607626f + 0.252464424f * x) * x; 3727 // 3728 // error 0.0144103317, which is 6 bits 3729 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3730 getF32Constant(DAG, 0x3e814304)); 3731 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3732 getF32Constant(DAG, 0x3f3c50c8)); 3733 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3734 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3735 getF32Constant(DAG, 0x3f7f5e7e)); 3736 } else if (LimitFloatPrecision <= 12) { 3737 // For floating-point precision of 12: 3738 // 3739 // TwoToFractionalPartOfX = 3740 // 0.999892986f + 3741 // (0.696457318f + 3742 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3743 // 3744 // 0.000107046256 error, which is 13 to 14 bits 3745 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3746 getF32Constant(DAG, 0x3da235e3)); 3747 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3748 getF32Constant(DAG, 0x3e65b8f3)); 3749 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3750 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3751 getF32Constant(DAG, 0x3f324b07)); 3752 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3753 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3754 getF32Constant(DAG, 0x3f7ff8fd)); 3755 } else { // LimitFloatPrecision <= 18 3756 // For floating-point precision of 18: 3757 // 3758 // TwoToFractionalPartOfX = 3759 // 0.999999982f + 3760 // (0.693148872f + 3761 // (0.240227044f + 3762 // (0.554906021e-1f + 3763 // (0.961591928e-2f + 3764 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3765 // 3766 // error 2.47208000*10^(-7), which is better than 18 bits 3767 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3768 getF32Constant(DAG, 0x3924b03e)); 3769 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3770 getF32Constant(DAG, 0x3ab24b87)); 3771 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3772 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3773 getF32Constant(DAG, 0x3c1d8c17)); 3774 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3775 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3776 getF32Constant(DAG, 0x3d634a1d)); 3777 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3778 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3779 getF32Constant(DAG, 0x3e75fe14)); 3780 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3781 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3782 getF32Constant(DAG, 0x3f317234)); 3783 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3784 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3785 getF32Constant(DAG, 0x3f800000)); 3786 } 3787 3788 // Add the exponent into the result in integer domain. 3789 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX); 3790 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 3791 DAG.getNode(ISD::ADD, dl, MVT::i32, 3792 t13, IntegerPartOfX)); 3793 } 3794 3795 // No special expansion. 3796 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op); 3797} 3798 3799/// expandLog - Lower a log intrinsic. Handles the special sequences for 3800/// limited-precision mode. 3801static SDValue expandLog(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 3802 const TargetLowering &TLI) { 3803 if (Op.getValueType() == MVT::f32 && 3804 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3805 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3806 3807 // Scale the exponent by log(2) [0.69314718f]. 3808 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3809 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3810 getF32Constant(DAG, 0x3f317218)); 3811 3812 // Get the significand and build it into a floating-point number with 3813 // exponent of 1. 3814 SDValue X = GetSignificand(DAG, Op1, dl); 3815 3816 SDValue LogOfMantissa; 3817 if (LimitFloatPrecision <= 6) { 3818 // For floating-point precision of 6: 3819 // 3820 // LogofMantissa = 3821 // -1.1609546f + 3822 // (1.4034025f - 0.23903021f * x) * x; 3823 // 3824 // error 0.0034276066, which is better than 8 bits 3825 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3826 getF32Constant(DAG, 0xbe74c456)); 3827 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3828 getF32Constant(DAG, 0x3fb3a2b1)); 3829 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3830 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3831 getF32Constant(DAG, 0x3f949a29)); 3832 } else if (LimitFloatPrecision <= 12) { 3833 // For floating-point precision of 12: 3834 // 3835 // LogOfMantissa = 3836 // -1.7417939f + 3837 // (2.8212026f + 3838 // (-1.4699568f + 3839 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3840 // 3841 // error 0.000061011436, which is 14 bits 3842 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3843 getF32Constant(DAG, 0xbd67b6d6)); 3844 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3845 getF32Constant(DAG, 0x3ee4f4b8)); 3846 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3847 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3848 getF32Constant(DAG, 0x3fbc278b)); 3849 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3850 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3851 getF32Constant(DAG, 0x40348e95)); 3852 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3853 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3854 getF32Constant(DAG, 0x3fdef31a)); 3855 } else { // LimitFloatPrecision <= 18 3856 // For floating-point precision of 18: 3857 // 3858 // LogOfMantissa = 3859 // -2.1072184f + 3860 // (4.2372794f + 3861 // (-3.7029485f + 3862 // (2.2781945f + 3863 // (-0.87823314f + 3864 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3865 // 3866 // error 0.0000023660568, which is better than 18 bits 3867 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3868 getF32Constant(DAG, 0xbc91e5ac)); 3869 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3870 getF32Constant(DAG, 0x3e4350aa)); 3871 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3872 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3873 getF32Constant(DAG, 0x3f60d3e3)); 3874 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3875 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3876 getF32Constant(DAG, 0x4011cdf0)); 3877 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3878 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3879 getF32Constant(DAG, 0x406cfd1c)); 3880 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3881 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3882 getF32Constant(DAG, 0x408797cb)); 3883 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3884 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3885 getF32Constant(DAG, 0x4006dcab)); 3886 } 3887 3888 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa); 3889 } 3890 3891 // No special expansion. 3892 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op); 3893} 3894 3895/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for 3896/// limited-precision mode. 3897static SDValue expandLog2(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 3898 const TargetLowering &TLI) { 3899 if (Op.getValueType() == MVT::f32 && 3900 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3901 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3902 3903 // Get the exponent. 3904 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3905 3906 // Get the significand and build it into a floating-point number with 3907 // exponent of 1. 3908 SDValue X = GetSignificand(DAG, Op1, dl); 3909 3910 // Different possible minimax approximations of significand in 3911 // floating-point for various degrees of accuracy over [1,2]. 3912 SDValue Log2ofMantissa; 3913 if (LimitFloatPrecision <= 6) { 3914 // For floating-point precision of 6: 3915 // 3916 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3917 // 3918 // error 0.0049451742, which is more than 7 bits 3919 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3920 getF32Constant(DAG, 0xbeb08fe0)); 3921 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3922 getF32Constant(DAG, 0x40019463)); 3923 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3924 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3925 getF32Constant(DAG, 0x3fd6633d)); 3926 } else if (LimitFloatPrecision <= 12) { 3927 // For floating-point precision of 12: 3928 // 3929 // Log2ofMantissa = 3930 // -2.51285454f + 3931 // (4.07009056f + 3932 // (-2.12067489f + 3933 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3934 // 3935 // error 0.0000876136000, which is better than 13 bits 3936 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3937 getF32Constant(DAG, 0xbda7262e)); 3938 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3939 getF32Constant(DAG, 0x3f25280b)); 3940 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3941 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3942 getF32Constant(DAG, 0x4007b923)); 3943 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3944 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3945 getF32Constant(DAG, 0x40823e2f)); 3946 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3947 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3948 getF32Constant(DAG, 0x4020d29c)); 3949 } else { // LimitFloatPrecision <= 18 3950 // For floating-point precision of 18: 3951 // 3952 // Log2ofMantissa = 3953 // -3.0400495f + 3954 // (6.1129976f + 3955 // (-5.3420409f + 3956 // (3.2865683f + 3957 // (-1.2669343f + 3958 // (0.27515199f - 3959 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3960 // 3961 // error 0.0000018516, which is better than 18 bits 3962 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3963 getF32Constant(DAG, 0xbcd2769e)); 3964 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3965 getF32Constant(DAG, 0x3e8ce0b9)); 3966 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3967 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3968 getF32Constant(DAG, 0x3fa22ae7)); 3969 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3970 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3971 getF32Constant(DAG, 0x40525723)); 3972 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3973 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3974 getF32Constant(DAG, 0x40aaf200)); 3975 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3976 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3977 getF32Constant(DAG, 0x40c39dad)); 3978 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3979 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3980 getF32Constant(DAG, 0x4042902c)); 3981 } 3982 3983 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa); 3984 } 3985 3986 // No special expansion. 3987 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op); 3988} 3989 3990/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for 3991/// limited-precision mode. 3992static SDValue expandLog10(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 3993 const TargetLowering &TLI) { 3994 if (Op.getValueType() == MVT::f32 && 3995 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3996 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3997 3998 // Scale the exponent by log10(2) [0.30102999f]. 3999 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 4000 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 4001 getF32Constant(DAG, 0x3e9a209a)); 4002 4003 // Get the significand and build it into a floating-point number with 4004 // exponent of 1. 4005 SDValue X = GetSignificand(DAG, Op1, dl); 4006 4007 SDValue Log10ofMantissa; 4008 if (LimitFloatPrecision <= 6) { 4009 // For floating-point precision of 6: 4010 // 4011 // Log10ofMantissa = 4012 // -0.50419619f + 4013 // (0.60948995f - 0.10380950f * x) * x; 4014 // 4015 // error 0.0014886165, which is 6 bits 4016 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4017 getF32Constant(DAG, 0xbdd49a13)); 4018 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4019 getF32Constant(DAG, 0x3f1c0789)); 4020 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4021 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4022 getF32Constant(DAG, 0x3f011300)); 4023 } else if (LimitFloatPrecision <= 12) { 4024 // For floating-point precision of 12: 4025 // 4026 // Log10ofMantissa = 4027 // -0.64831180f + 4028 // (0.91751397f + 4029 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4030 // 4031 // error 0.00019228036, which is better than 12 bits 4032 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4033 getF32Constant(DAG, 0x3d431f31)); 4034 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4035 getF32Constant(DAG, 0x3ea21fb2)); 4036 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4037 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4038 getF32Constant(DAG, 0x3f6ae232)); 4039 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4040 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4041 getF32Constant(DAG, 0x3f25f7c3)); 4042 } else { // LimitFloatPrecision <= 18 4043 // For floating-point precision of 18: 4044 // 4045 // Log10ofMantissa = 4046 // -0.84299375f + 4047 // (1.5327582f + 4048 // (-1.0688956f + 4049 // (0.49102474f + 4050 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4051 // 4052 // error 0.0000037995730, which is better than 18 bits 4053 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4054 getF32Constant(DAG, 0x3c5d51ce)); 4055 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4056 getF32Constant(DAG, 0x3e00685a)); 4057 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4058 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4059 getF32Constant(DAG, 0x3efb6798)); 4060 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4061 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4062 getF32Constant(DAG, 0x3f88d192)); 4063 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4064 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4065 getF32Constant(DAG, 0x3fc4316c)); 4066 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4067 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4068 getF32Constant(DAG, 0x3f57ce70)); 4069 } 4070 4071 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa); 4072 } 4073 4074 // No special expansion. 4075 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op); 4076} 4077 4078/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4079/// limited-precision mode. 4080static SDValue expandExp2(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 4081 const TargetLowering &TLI) { 4082 if (Op.getValueType() == MVT::f32 && 4083 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4084 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4085 4086 // FractionalPartOfX = x - (float)IntegerPartOfX; 4087 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4088 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4089 4090 // IntegerPartOfX <<= 23; 4091 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4092 DAG.getConstant(23, TLI.getPointerTy())); 4093 4094 SDValue TwoToFractionalPartOfX; 4095 if (LimitFloatPrecision <= 6) { 4096 // For floating-point precision of 6: 4097 // 4098 // TwoToFractionalPartOfX = 4099 // 0.997535578f + 4100 // (0.735607626f + 0.252464424f * x) * x; 4101 // 4102 // error 0.0144103317, which is 6 bits 4103 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4104 getF32Constant(DAG, 0x3e814304)); 4105 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4106 getF32Constant(DAG, 0x3f3c50c8)); 4107 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4108 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4109 getF32Constant(DAG, 0x3f7f5e7e)); 4110 } else if (LimitFloatPrecision <= 12) { 4111 // For floating-point precision of 12: 4112 // 4113 // TwoToFractionalPartOfX = 4114 // 0.999892986f + 4115 // (0.696457318f + 4116 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4117 // 4118 // error 0.000107046256, which is 13 to 14 bits 4119 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4120 getF32Constant(DAG, 0x3da235e3)); 4121 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4122 getF32Constant(DAG, 0x3e65b8f3)); 4123 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4124 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4125 getF32Constant(DAG, 0x3f324b07)); 4126 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4127 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4128 getF32Constant(DAG, 0x3f7ff8fd)); 4129 } else { // LimitFloatPrecision <= 18 4130 // For floating-point precision of 18: 4131 // 4132 // TwoToFractionalPartOfX = 4133 // 0.999999982f + 4134 // (0.693148872f + 4135 // (0.240227044f + 4136 // (0.554906021e-1f + 4137 // (0.961591928e-2f + 4138 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4139 // error 2.47208000*10^(-7), which is better than 18 bits 4140 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4141 getF32Constant(DAG, 0x3924b03e)); 4142 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4143 getF32Constant(DAG, 0x3ab24b87)); 4144 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4145 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4146 getF32Constant(DAG, 0x3c1d8c17)); 4147 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4148 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4149 getF32Constant(DAG, 0x3d634a1d)); 4150 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4151 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4152 getF32Constant(DAG, 0x3e75fe14)); 4153 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4154 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4155 getF32Constant(DAG, 0x3f317234)); 4156 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4157 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4158 getF32Constant(DAG, 0x3f800000)); 4159 } 4160 4161 // Add the exponent into the result in integer domain. 4162 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, 4163 TwoToFractionalPartOfX); 4164 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 4165 DAG.getNode(ISD::ADD, dl, MVT::i32, 4166 t13, IntegerPartOfX)); 4167 } 4168 4169 // No special expansion. 4170 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op); 4171} 4172 4173/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4174/// limited-precision mode with x == 10.0f. 4175static SDValue expandPow(DebugLoc dl, SDValue LHS, SDValue RHS, 4176 SelectionDAG &DAG, const TargetLowering &TLI) { 4177 bool IsExp10 = false; 4178 if (LHS.getValueType() == MVT::f32 && LHS.getValueType() == MVT::f32 && 4179 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4180 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) { 4181 APFloat Ten(10.0f); 4182 IsExp10 = LHSC->isExactlyValue(Ten); 4183 } 4184 } 4185 4186 if (IsExp10) { 4187 // Put the exponent in the right bit position for later addition to the 4188 // final result: 4189 // 4190 // #define LOG2OF10 3.3219281f 4191 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4192 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS, 4193 getF32Constant(DAG, 0x40549a78)); 4194 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4195 4196 // FractionalPartOfX = x - (float)IntegerPartOfX; 4197 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4198 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4199 4200 // IntegerPartOfX <<= 23; 4201 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4202 DAG.getConstant(23, TLI.getPointerTy())); 4203 4204 SDValue TwoToFractionalPartOfX; 4205 if (LimitFloatPrecision <= 6) { 4206 // For floating-point precision of 6: 4207 // 4208 // twoToFractionalPartOfX = 4209 // 0.997535578f + 4210 // (0.735607626f + 0.252464424f * x) * x; 4211 // 4212 // error 0.0144103317, which is 6 bits 4213 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4214 getF32Constant(DAG, 0x3e814304)); 4215 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4216 getF32Constant(DAG, 0x3f3c50c8)); 4217 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4218 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4219 getF32Constant(DAG, 0x3f7f5e7e)); 4220 } else if (LimitFloatPrecision <= 12) { 4221 // For floating-point precision of 12: 4222 // 4223 // TwoToFractionalPartOfX = 4224 // 0.999892986f + 4225 // (0.696457318f + 4226 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4227 // 4228 // error 0.000107046256, which is 13 to 14 bits 4229 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4230 getF32Constant(DAG, 0x3da235e3)); 4231 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4232 getF32Constant(DAG, 0x3e65b8f3)); 4233 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4234 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4235 getF32Constant(DAG, 0x3f324b07)); 4236 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4237 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4238 getF32Constant(DAG, 0x3f7ff8fd)); 4239 } else { // LimitFloatPrecision <= 18 4240 // For floating-point precision of 18: 4241 // 4242 // TwoToFractionalPartOfX = 4243 // 0.999999982f + 4244 // (0.693148872f + 4245 // (0.240227044f + 4246 // (0.554906021e-1f + 4247 // (0.961591928e-2f + 4248 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4249 // error 2.47208000*10^(-7), which is better than 18 bits 4250 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4251 getF32Constant(DAG, 0x3924b03e)); 4252 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4253 getF32Constant(DAG, 0x3ab24b87)); 4254 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4255 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4256 getF32Constant(DAG, 0x3c1d8c17)); 4257 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4258 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4259 getF32Constant(DAG, 0x3d634a1d)); 4260 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4261 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4262 getF32Constant(DAG, 0x3e75fe14)); 4263 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4264 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4265 getF32Constant(DAG, 0x3f317234)); 4266 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4267 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4268 getF32Constant(DAG, 0x3f800000)); 4269 } 4270 4271 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX); 4272 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 4273 DAG.getNode(ISD::ADD, dl, MVT::i32, 4274 t13, IntegerPartOfX)); 4275 } 4276 4277 // No special expansion. 4278 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS); 4279} 4280 4281 4282/// ExpandPowI - Expand a llvm.powi intrinsic. 4283static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4284 SelectionDAG &DAG) { 4285 // If RHS is a constant, we can expand this out to a multiplication tree, 4286 // otherwise we end up lowering to a call to __powidf2 (for example). When 4287 // optimizing for size, we only want to do this if the expansion would produce 4288 // a small number of multiplies, otherwise we do the full expansion. 4289 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4290 // Get the exponent as a positive value. 4291 unsigned Val = RHSC->getSExtValue(); 4292 if ((int)Val < 0) Val = -Val; 4293 4294 // powi(x, 0) -> 1.0 4295 if (Val == 0) 4296 return DAG.getConstantFP(1.0, LHS.getValueType()); 4297 4298 const Function *F = DAG.getMachineFunction().getFunction(); 4299 if (!F->getFnAttributes().hasAttribute(Attribute::OptimizeForSize) || 4300 // If optimizing for size, don't insert too many multiplies. This 4301 // inserts up to 5 multiplies. 4302 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4303 // We use the simple binary decomposition method to generate the multiply 4304 // sequence. There are more optimal ways to do this (for example, 4305 // powi(x,15) generates one more multiply than it should), but this has 4306 // the benefit of being both really simple and much better than a libcall. 4307 SDValue Res; // Logically starts equal to 1.0 4308 SDValue CurSquare = LHS; 4309 while (Val) { 4310 if (Val & 1) { 4311 if (Res.getNode()) 4312 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4313 else 4314 Res = CurSquare; // 1.0*CurSquare. 4315 } 4316 4317 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4318 CurSquare, CurSquare); 4319 Val >>= 1; 4320 } 4321 4322 // If the original was negative, invert the result, producing 1/(x*x*x). 4323 if (RHSC->getSExtValue() < 0) 4324 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4325 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4326 return Res; 4327 } 4328 } 4329 4330 // Otherwise, expand to a libcall. 4331 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4332} 4333 4334// getTruncatedArgReg - Find underlying register used for an truncated 4335// argument. 4336static unsigned getTruncatedArgReg(const SDValue &N) { 4337 if (N.getOpcode() != ISD::TRUNCATE) 4338 return 0; 4339 4340 const SDValue &Ext = N.getOperand(0); 4341 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4342 const SDValue &CFR = Ext.getOperand(0); 4343 if (CFR.getOpcode() == ISD::CopyFromReg) 4344 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4345 if (CFR.getOpcode() == ISD::TRUNCATE) 4346 return getTruncatedArgReg(CFR); 4347 } 4348 return 0; 4349} 4350 4351/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4352/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4353/// At the end of instruction selection, they will be inserted to the entry BB. 4354bool 4355SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4356 int64_t Offset, 4357 const SDValue &N) { 4358 const Argument *Arg = dyn_cast<Argument>(V); 4359 if (!Arg) 4360 return false; 4361 4362 MachineFunction &MF = DAG.getMachineFunction(); 4363 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4364 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4365 4366 // Ignore inlined function arguments here. 4367 DIVariable DV(Variable); 4368 if (DV.isInlinedFnArgument(MF.getFunction())) 4369 return false; 4370 4371 unsigned Reg = 0; 4372 // Some arguments' frame index is recorded during argument lowering. 4373 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4374 if (Offset) 4375 Reg = TRI->getFrameRegister(MF); 4376 4377 if (!Reg && N.getNode()) { 4378 if (N.getOpcode() == ISD::CopyFromReg) 4379 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4380 else 4381 Reg = getTruncatedArgReg(N); 4382 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4383 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4384 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4385 if (PR) 4386 Reg = PR; 4387 } 4388 } 4389 4390 if (!Reg) { 4391 // Check if ValueMap has reg number. 4392 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4393 if (VMI != FuncInfo.ValueMap.end()) 4394 Reg = VMI->second; 4395 } 4396 4397 if (!Reg && N.getNode()) { 4398 // Check if frame index is available. 4399 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4400 if (FrameIndexSDNode *FINode = 4401 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4402 Reg = TRI->getFrameRegister(MF); 4403 Offset = FINode->getIndex(); 4404 } 4405 } 4406 4407 if (!Reg) 4408 return false; 4409 4410 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4411 TII->get(TargetOpcode::DBG_VALUE)) 4412 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4413 FuncInfo.ArgDbgValues.push_back(&*MIB); 4414 return true; 4415} 4416 4417// VisualStudio defines setjmp as _setjmp 4418#if defined(_MSC_VER) && defined(setjmp) && \ 4419 !defined(setjmp_undefined_for_msvc) 4420# pragma push_macro("setjmp") 4421# undef setjmp 4422# define setjmp_undefined_for_msvc 4423#endif 4424 4425/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4426/// we want to emit this as a call to a named external function, return the name 4427/// otherwise lower it and return null. 4428const char * 4429SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4430 DebugLoc dl = getCurDebugLoc(); 4431 SDValue Res; 4432 4433 switch (Intrinsic) { 4434 default: 4435 // By default, turn this into a target intrinsic node. 4436 visitTargetIntrinsic(I, Intrinsic); 4437 return 0; 4438 case Intrinsic::vastart: visitVAStart(I); return 0; 4439 case Intrinsic::vaend: visitVAEnd(I); return 0; 4440 case Intrinsic::vacopy: visitVACopy(I); return 0; 4441 case Intrinsic::returnaddress: 4442 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4443 getValue(I.getArgOperand(0)))); 4444 return 0; 4445 case Intrinsic::frameaddress: 4446 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4447 getValue(I.getArgOperand(0)))); 4448 return 0; 4449 case Intrinsic::setjmp: 4450 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()]; 4451 case Intrinsic::longjmp: 4452 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()]; 4453 case Intrinsic::memcpy: { 4454 // Assert for address < 256 since we support only user defined address 4455 // spaces. 4456 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4457 < 256 && 4458 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4459 < 256 && 4460 "Unknown address space"); 4461 SDValue Op1 = getValue(I.getArgOperand(0)); 4462 SDValue Op2 = getValue(I.getArgOperand(1)); 4463 SDValue Op3 = getValue(I.getArgOperand(2)); 4464 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4465 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4466 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4467 MachinePointerInfo(I.getArgOperand(0)), 4468 MachinePointerInfo(I.getArgOperand(1)))); 4469 return 0; 4470 } 4471 case Intrinsic::memset: { 4472 // Assert for address < 256 since we support only user defined address 4473 // spaces. 4474 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4475 < 256 && 4476 "Unknown address space"); 4477 SDValue Op1 = getValue(I.getArgOperand(0)); 4478 SDValue Op2 = getValue(I.getArgOperand(1)); 4479 SDValue Op3 = getValue(I.getArgOperand(2)); 4480 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4481 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4482 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4483 MachinePointerInfo(I.getArgOperand(0)))); 4484 return 0; 4485 } 4486 case Intrinsic::memmove: { 4487 // Assert for address < 256 since we support only user defined address 4488 // spaces. 4489 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4490 < 256 && 4491 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4492 < 256 && 4493 "Unknown address space"); 4494 SDValue Op1 = getValue(I.getArgOperand(0)); 4495 SDValue Op2 = getValue(I.getArgOperand(1)); 4496 SDValue Op3 = getValue(I.getArgOperand(2)); 4497 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4498 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4499 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4500 MachinePointerInfo(I.getArgOperand(0)), 4501 MachinePointerInfo(I.getArgOperand(1)))); 4502 return 0; 4503 } 4504 case Intrinsic::dbg_declare: { 4505 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4506 MDNode *Variable = DI.getVariable(); 4507 const Value *Address = DI.getAddress(); 4508 if (!Address || !DIVariable(Variable).Verify()) { 4509 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4510 return 0; 4511 } 4512 4513 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4514 // but do not always have a corresponding SDNode built. The SDNodeOrder 4515 // absolute, but not relative, values are different depending on whether 4516 // debug info exists. 4517 ++SDNodeOrder; 4518 4519 // Check if address has undef value. 4520 if (isa<UndefValue>(Address) || 4521 (Address->use_empty() && !isa<Argument>(Address))) { 4522 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4523 return 0; 4524 } 4525 4526 SDValue &N = NodeMap[Address]; 4527 if (!N.getNode() && isa<Argument>(Address)) 4528 // Check unused arguments map. 4529 N = UnusedArgNodeMap[Address]; 4530 SDDbgValue *SDV; 4531 if (N.getNode()) { 4532 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4533 Address = BCI->getOperand(0); 4534 // Parameters are handled specially. 4535 bool isParameter = 4536 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable || 4537 isa<Argument>(Address)); 4538 4539 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4540 4541 if (isParameter && !AI) { 4542 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4543 if (FINode) 4544 // Byval parameter. We have a frame index at this point. 4545 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4546 0, dl, SDNodeOrder); 4547 else { 4548 // Address is an argument, so try to emit its dbg value using 4549 // virtual register info from the FuncInfo.ValueMap. 4550 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4551 return 0; 4552 } 4553 } else if (AI) 4554 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4555 0, dl, SDNodeOrder); 4556 else { 4557 // Can't do anything with other non-AI cases yet. 4558 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4559 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t"); 4560 DEBUG(Address->dump()); 4561 return 0; 4562 } 4563 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4564 } else { 4565 // If Address is an argument then try to emit its dbg value using 4566 // virtual register info from the FuncInfo.ValueMap. 4567 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4568 // If variable is pinned by a alloca in dominating bb then 4569 // use StaticAllocaMap. 4570 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4571 if (AI->getParent() != DI.getParent()) { 4572 DenseMap<const AllocaInst*, int>::iterator SI = 4573 FuncInfo.StaticAllocaMap.find(AI); 4574 if (SI != FuncInfo.StaticAllocaMap.end()) { 4575 SDV = DAG.getDbgValue(Variable, SI->second, 4576 0, dl, SDNodeOrder); 4577 DAG.AddDbgValue(SDV, 0, false); 4578 return 0; 4579 } 4580 } 4581 } 4582 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4583 } 4584 } 4585 return 0; 4586 } 4587 case Intrinsic::dbg_value: { 4588 const DbgValueInst &DI = cast<DbgValueInst>(I); 4589 if (!DIVariable(DI.getVariable()).Verify()) 4590 return 0; 4591 4592 MDNode *Variable = DI.getVariable(); 4593 uint64_t Offset = DI.getOffset(); 4594 const Value *V = DI.getValue(); 4595 if (!V) 4596 return 0; 4597 4598 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4599 // but do not always have a corresponding SDNode built. The SDNodeOrder 4600 // absolute, but not relative, values are different depending on whether 4601 // debug info exists. 4602 ++SDNodeOrder; 4603 SDDbgValue *SDV; 4604 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4605 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4606 DAG.AddDbgValue(SDV, 0, false); 4607 } else { 4608 // Do not use getValue() in here; we don't want to generate code at 4609 // this point if it hasn't been done yet. 4610 SDValue N = NodeMap[V]; 4611 if (!N.getNode() && isa<Argument>(V)) 4612 // Check unused arguments map. 4613 N = UnusedArgNodeMap[V]; 4614 if (N.getNode()) { 4615 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4616 SDV = DAG.getDbgValue(Variable, N.getNode(), 4617 N.getResNo(), Offset, dl, SDNodeOrder); 4618 DAG.AddDbgValue(SDV, N.getNode(), false); 4619 } 4620 } else if (!V->use_empty() ) { 4621 // Do not call getValue(V) yet, as we don't want to generate code. 4622 // Remember it for later. 4623 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4624 DanglingDebugInfoMap[V] = DDI; 4625 } else { 4626 // We may expand this to cover more cases. One case where we have no 4627 // data available is an unreferenced parameter. 4628 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4629 } 4630 } 4631 4632 // Build a debug info table entry. 4633 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4634 V = BCI->getOperand(0); 4635 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4636 // Don't handle byval struct arguments or VLAs, for example. 4637 if (!AI) { 4638 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); 4639 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); 4640 return 0; 4641 } 4642 DenseMap<const AllocaInst*, int>::iterator SI = 4643 FuncInfo.StaticAllocaMap.find(AI); 4644 if (SI == FuncInfo.StaticAllocaMap.end()) 4645 return 0; // VLAs. 4646 int FI = SI->second; 4647 4648 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4649 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4650 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4651 return 0; 4652 } 4653 4654 case Intrinsic::eh_typeid_for: { 4655 // Find the type id for the given typeinfo. 4656 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4657 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4658 Res = DAG.getConstant(TypeID, MVT::i32); 4659 setValue(&I, Res); 4660 return 0; 4661 } 4662 4663 case Intrinsic::eh_return_i32: 4664 case Intrinsic::eh_return_i64: 4665 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4666 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4667 MVT::Other, 4668 getControlRoot(), 4669 getValue(I.getArgOperand(0)), 4670 getValue(I.getArgOperand(1)))); 4671 return 0; 4672 case Intrinsic::eh_unwind_init: 4673 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4674 return 0; 4675 case Intrinsic::eh_dwarf_cfa: { 4676 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4677 TLI.getPointerTy()); 4678 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4679 TLI.getPointerTy(), 4680 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4681 TLI.getPointerTy()), 4682 CfaArg); 4683 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4684 TLI.getPointerTy(), 4685 DAG.getConstant(0, TLI.getPointerTy())); 4686 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4687 FA, Offset)); 4688 return 0; 4689 } 4690 case Intrinsic::eh_sjlj_callsite: { 4691 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4692 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4693 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4694 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4695 4696 MMI.setCurrentCallSite(CI->getZExtValue()); 4697 return 0; 4698 } 4699 case Intrinsic::eh_sjlj_functioncontext: { 4700 // Get and store the index of the function context. 4701 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4702 AllocaInst *FnCtx = 4703 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4704 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4705 MFI->setFunctionContextIndex(FI); 4706 return 0; 4707 } 4708 case Intrinsic::eh_sjlj_setjmp: { 4709 SDValue Ops[2]; 4710 Ops[0] = getRoot(); 4711 Ops[1] = getValue(I.getArgOperand(0)); 4712 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, 4713 DAG.getVTList(MVT::i32, MVT::Other), 4714 Ops, 2); 4715 setValue(&I, Op.getValue(0)); 4716 DAG.setRoot(Op.getValue(1)); 4717 return 0; 4718 } 4719 case Intrinsic::eh_sjlj_longjmp: { 4720 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4721 getRoot(), getValue(I.getArgOperand(0)))); 4722 return 0; 4723 } 4724 4725 case Intrinsic::x86_mmx_pslli_w: 4726 case Intrinsic::x86_mmx_pslli_d: 4727 case Intrinsic::x86_mmx_pslli_q: 4728 case Intrinsic::x86_mmx_psrli_w: 4729 case Intrinsic::x86_mmx_psrli_d: 4730 case Intrinsic::x86_mmx_psrli_q: 4731 case Intrinsic::x86_mmx_psrai_w: 4732 case Intrinsic::x86_mmx_psrai_d: { 4733 SDValue ShAmt = getValue(I.getArgOperand(1)); 4734 if (isa<ConstantSDNode>(ShAmt)) { 4735 visitTargetIntrinsic(I, Intrinsic); 4736 return 0; 4737 } 4738 unsigned NewIntrinsic = 0; 4739 EVT ShAmtVT = MVT::v2i32; 4740 switch (Intrinsic) { 4741 case Intrinsic::x86_mmx_pslli_w: 4742 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4743 break; 4744 case Intrinsic::x86_mmx_pslli_d: 4745 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4746 break; 4747 case Intrinsic::x86_mmx_pslli_q: 4748 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4749 break; 4750 case Intrinsic::x86_mmx_psrli_w: 4751 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4752 break; 4753 case Intrinsic::x86_mmx_psrli_d: 4754 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4755 break; 4756 case Intrinsic::x86_mmx_psrli_q: 4757 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4758 break; 4759 case Intrinsic::x86_mmx_psrai_w: 4760 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4761 break; 4762 case Intrinsic::x86_mmx_psrai_d: 4763 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4764 break; 4765 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4766 } 4767 4768 // The vector shift intrinsics with scalars uses 32b shift amounts but 4769 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4770 // to be zero. 4771 // We must do this early because v2i32 is not a legal type. 4772 SDValue ShOps[2]; 4773 ShOps[0] = ShAmt; 4774 ShOps[1] = DAG.getConstant(0, MVT::i32); 4775 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4776 EVT DestVT = TLI.getValueType(I.getType()); 4777 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4778 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4779 DAG.getConstant(NewIntrinsic, MVT::i32), 4780 getValue(I.getArgOperand(0)), ShAmt); 4781 setValue(&I, Res); 4782 return 0; 4783 } 4784 case Intrinsic::x86_avx_vinsertf128_pd_256: 4785 case Intrinsic::x86_avx_vinsertf128_ps_256: 4786 case Intrinsic::x86_avx_vinsertf128_si_256: 4787 case Intrinsic::x86_avx2_vinserti128: { 4788 EVT DestVT = TLI.getValueType(I.getType()); 4789 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType()); 4790 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) * 4791 ElVT.getVectorNumElements(); 4792 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT, 4793 getValue(I.getArgOperand(0)), 4794 getValue(I.getArgOperand(1)), 4795 DAG.getIntPtrConstant(Idx)); 4796 setValue(&I, Res); 4797 return 0; 4798 } 4799 case Intrinsic::x86_avx_vextractf128_pd_256: 4800 case Intrinsic::x86_avx_vextractf128_ps_256: 4801 case Intrinsic::x86_avx_vextractf128_si_256: 4802 case Intrinsic::x86_avx2_vextracti128: { 4803 EVT DestVT = TLI.getValueType(I.getType()); 4804 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) * 4805 DestVT.getVectorNumElements(); 4806 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, 4807 getValue(I.getArgOperand(0)), 4808 DAG.getIntPtrConstant(Idx)); 4809 setValue(&I, Res); 4810 return 0; 4811 } 4812 case Intrinsic::convertff: 4813 case Intrinsic::convertfsi: 4814 case Intrinsic::convertfui: 4815 case Intrinsic::convertsif: 4816 case Intrinsic::convertuif: 4817 case Intrinsic::convertss: 4818 case Intrinsic::convertsu: 4819 case Intrinsic::convertus: 4820 case Intrinsic::convertuu: { 4821 ISD::CvtCode Code = ISD::CVT_INVALID; 4822 switch (Intrinsic) { 4823 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4824 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4825 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4826 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4827 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4828 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4829 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4830 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4831 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4832 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4833 } 4834 EVT DestVT = TLI.getValueType(I.getType()); 4835 const Value *Op1 = I.getArgOperand(0); 4836 Res = DAG.getConvertRndSat(DestVT, dl, getValue(Op1), 4837 DAG.getValueType(DestVT), 4838 DAG.getValueType(getValue(Op1).getValueType()), 4839 getValue(I.getArgOperand(1)), 4840 getValue(I.getArgOperand(2)), 4841 Code); 4842 setValue(&I, Res); 4843 return 0; 4844 } 4845 case Intrinsic::powi: 4846 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4847 getValue(I.getArgOperand(1)), DAG)); 4848 return 0; 4849 case Intrinsic::log: 4850 setValue(&I, expandLog(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4851 return 0; 4852 case Intrinsic::log2: 4853 setValue(&I, expandLog2(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4854 return 0; 4855 case Intrinsic::log10: 4856 setValue(&I, expandLog10(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4857 return 0; 4858 case Intrinsic::exp: 4859 setValue(&I, expandExp(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4860 return 0; 4861 case Intrinsic::exp2: 4862 setValue(&I, expandExp2(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4863 return 0; 4864 case Intrinsic::pow: 4865 setValue(&I, expandPow(dl, getValue(I.getArgOperand(0)), 4866 getValue(I.getArgOperand(1)), DAG, TLI)); 4867 return 0; 4868 case Intrinsic::sqrt: 4869 case Intrinsic::fabs: 4870 case Intrinsic::sin: 4871 case Intrinsic::cos: 4872 case Intrinsic::floor: 4873 case Intrinsic::ceil: 4874 case Intrinsic::trunc: 4875 case Intrinsic::rint: 4876 case Intrinsic::nearbyint: { 4877 unsigned Opcode; 4878 switch (Intrinsic) { 4879 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4880 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; 4881 case Intrinsic::fabs: Opcode = ISD::FABS; break; 4882 case Intrinsic::sin: Opcode = ISD::FSIN; break; 4883 case Intrinsic::cos: Opcode = ISD::FCOS; break; 4884 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; 4885 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; 4886 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; 4887 case Intrinsic::rint: Opcode = ISD::FRINT; break; 4888 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; 4889 } 4890 4891 setValue(&I, DAG.getNode(Opcode, dl, 4892 getValue(I.getArgOperand(0)).getValueType(), 4893 getValue(I.getArgOperand(0)))); 4894 return 0; 4895 } 4896 case Intrinsic::fma: 4897 setValue(&I, DAG.getNode(ISD::FMA, dl, 4898 getValue(I.getArgOperand(0)).getValueType(), 4899 getValue(I.getArgOperand(0)), 4900 getValue(I.getArgOperand(1)), 4901 getValue(I.getArgOperand(2)))); 4902 return 0; 4903 case Intrinsic::fmuladd: { 4904 EVT VT = TLI.getValueType(I.getType()); 4905 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && 4906 TLI.isOperationLegalOrCustom(ISD::FMA, VT) && 4907 TLI.isFMAFasterThanMulAndAdd(VT)){ 4908 setValue(&I, DAG.getNode(ISD::FMA, dl, 4909 getValue(I.getArgOperand(0)).getValueType(), 4910 getValue(I.getArgOperand(0)), 4911 getValue(I.getArgOperand(1)), 4912 getValue(I.getArgOperand(2)))); 4913 } else { 4914 SDValue Mul = DAG.getNode(ISD::FMUL, dl, 4915 getValue(I.getArgOperand(0)).getValueType(), 4916 getValue(I.getArgOperand(0)), 4917 getValue(I.getArgOperand(1))); 4918 SDValue Add = DAG.getNode(ISD::FADD, dl, 4919 getValue(I.getArgOperand(0)).getValueType(), 4920 Mul, 4921 getValue(I.getArgOperand(2))); 4922 setValue(&I, Add); 4923 } 4924 return 0; 4925 } 4926 case Intrinsic::convert_to_fp16: 4927 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4928 MVT::i16, getValue(I.getArgOperand(0)))); 4929 return 0; 4930 case Intrinsic::convert_from_fp16: 4931 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4932 MVT::f32, getValue(I.getArgOperand(0)))); 4933 return 0; 4934 case Intrinsic::pcmarker: { 4935 SDValue Tmp = getValue(I.getArgOperand(0)); 4936 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4937 return 0; 4938 } 4939 case Intrinsic::readcyclecounter: { 4940 SDValue Op = getRoot(); 4941 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4942 DAG.getVTList(MVT::i64, MVT::Other), 4943 &Op, 1); 4944 setValue(&I, Res); 4945 DAG.setRoot(Res.getValue(1)); 4946 return 0; 4947 } 4948 case Intrinsic::bswap: 4949 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4950 getValue(I.getArgOperand(0)).getValueType(), 4951 getValue(I.getArgOperand(0)))); 4952 return 0; 4953 case Intrinsic::cttz: { 4954 SDValue Arg = getValue(I.getArgOperand(0)); 4955 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4956 EVT Ty = Arg.getValueType(); 4957 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 4958 dl, Ty, Arg)); 4959 return 0; 4960 } 4961 case Intrinsic::ctlz: { 4962 SDValue Arg = getValue(I.getArgOperand(0)); 4963 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4964 EVT Ty = Arg.getValueType(); 4965 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 4966 dl, Ty, Arg)); 4967 return 0; 4968 } 4969 case Intrinsic::ctpop: { 4970 SDValue Arg = getValue(I.getArgOperand(0)); 4971 EVT Ty = Arg.getValueType(); 4972 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4973 return 0; 4974 } 4975 case Intrinsic::stacksave: { 4976 SDValue Op = getRoot(); 4977 Res = DAG.getNode(ISD::STACKSAVE, dl, 4978 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4979 setValue(&I, Res); 4980 DAG.setRoot(Res.getValue(1)); 4981 return 0; 4982 } 4983 case Intrinsic::stackrestore: { 4984 Res = getValue(I.getArgOperand(0)); 4985 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4986 return 0; 4987 } 4988 case Intrinsic::stackprotector: { 4989 // Emit code into the DAG to store the stack guard onto the stack. 4990 MachineFunction &MF = DAG.getMachineFunction(); 4991 MachineFrameInfo *MFI = MF.getFrameInfo(); 4992 EVT PtrTy = TLI.getPointerTy(); 4993 4994 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4995 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4996 4997 int FI = FuncInfo.StaticAllocaMap[Slot]; 4998 MFI->setStackProtectorIndex(FI); 4999 5000 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5001 5002 // Store the stack protector onto the stack. 5003 Res = DAG.getStore(getRoot(), dl, Src, FIN, 5004 MachinePointerInfo::getFixedStack(FI), 5005 true, false, 0); 5006 setValue(&I, Res); 5007 DAG.setRoot(Res); 5008 return 0; 5009 } 5010 case Intrinsic::objectsize: { 5011 // If we don't know by now, we're never going to know. 5012 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5013 5014 assert(CI && "Non-constant type in __builtin_object_size?"); 5015 5016 SDValue Arg = getValue(I.getCalledValue()); 5017 EVT Ty = Arg.getValueType(); 5018 5019 if (CI->isZero()) 5020 Res = DAG.getConstant(-1ULL, Ty); 5021 else 5022 Res = DAG.getConstant(0, Ty); 5023 5024 setValue(&I, Res); 5025 return 0; 5026 } 5027 case Intrinsic::var_annotation: 5028 // Discard annotate attributes 5029 return 0; 5030 5031 case Intrinsic::init_trampoline: { 5032 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5033 5034 SDValue Ops[6]; 5035 Ops[0] = getRoot(); 5036 Ops[1] = getValue(I.getArgOperand(0)); 5037 Ops[2] = getValue(I.getArgOperand(1)); 5038 Ops[3] = getValue(I.getArgOperand(2)); 5039 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5040 Ops[5] = DAG.getSrcValue(F); 5041 5042 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5043 5044 DAG.setRoot(Res); 5045 return 0; 5046 } 5047 case Intrinsic::adjust_trampoline: { 5048 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5049 TLI.getPointerTy(), 5050 getValue(I.getArgOperand(0)))); 5051 return 0; 5052 } 5053 case Intrinsic::gcroot: 5054 if (GFI) { 5055 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); 5056 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5057 5058 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5059 GFI->addStackRoot(FI->getIndex(), TypeMap); 5060 } 5061 return 0; 5062 case Intrinsic::gcread: 5063 case Intrinsic::gcwrite: 5064 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5065 case Intrinsic::flt_rounds: 5066 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5067 return 0; 5068 5069 case Intrinsic::expect: { 5070 // Just replace __builtin_expect(exp, c) with EXP. 5071 setValue(&I, getValue(I.getArgOperand(0))); 5072 return 0; 5073 } 5074 5075 case Intrinsic::debugtrap: 5076 case Intrinsic::trap: { 5077 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5078 if (TrapFuncName.empty()) { 5079 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ? 5080 ISD::TRAP : ISD::DEBUGTRAP; 5081 DAG.setRoot(DAG.getNode(Op, dl,MVT::Other, getRoot())); 5082 return 0; 5083 } 5084 TargetLowering::ArgListTy Args; 5085 TargetLowering:: 5086 CallLoweringInfo CLI(getRoot(), I.getType(), 5087 false, false, false, false, 0, CallingConv::C, 5088 /*isTailCall=*/false, 5089 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 5090 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5091 Args, DAG, dl); 5092 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI); 5093 DAG.setRoot(Result.second); 5094 return 0; 5095 } 5096 5097 case Intrinsic::uadd_with_overflow: 5098 case Intrinsic::sadd_with_overflow: 5099 case Intrinsic::usub_with_overflow: 5100 case Intrinsic::ssub_with_overflow: 5101 case Intrinsic::umul_with_overflow: 5102 case Intrinsic::smul_with_overflow: { 5103 ISD::NodeType Op; 5104 switch (Intrinsic) { 5105 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 5106 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; 5107 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; 5108 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; 5109 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; 5110 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; 5111 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; 5112 } 5113 SDValue Op1 = getValue(I.getArgOperand(0)); 5114 SDValue Op2 = getValue(I.getArgOperand(1)); 5115 5116 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 5117 setValue(&I, DAG.getNode(Op, dl, VTs, Op1, Op2)); 5118 return 0; 5119 } 5120 case Intrinsic::prefetch: { 5121 SDValue Ops[5]; 5122 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5123 Ops[0] = getRoot(); 5124 Ops[1] = getValue(I.getArgOperand(0)); 5125 Ops[2] = getValue(I.getArgOperand(1)); 5126 Ops[3] = getValue(I.getArgOperand(2)); 5127 Ops[4] = getValue(I.getArgOperand(3)); 5128 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5129 DAG.getVTList(MVT::Other), 5130 &Ops[0], 5, 5131 EVT::getIntegerVT(*Context, 8), 5132 MachinePointerInfo(I.getArgOperand(0)), 5133 0, /* align */ 5134 false, /* volatile */ 5135 rw==0, /* read */ 5136 rw==1)); /* write */ 5137 return 0; 5138 } 5139 case Intrinsic::lifetime_start: 5140 case Intrinsic::lifetime_end: { 5141 bool IsStart = (Intrinsic == Intrinsic::lifetime_start); 5142 // Stack coloring is not enabled in O0, discard region information. 5143 if (TM.getOptLevel() == CodeGenOpt::None) 5144 return 0; 5145 5146 SmallVector<Value *, 4> Allocas; 5147 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD); 5148 5149 for (SmallVector<Value*, 4>::iterator Object = Allocas.begin(), 5150 E = Allocas.end(); Object != E; ++Object) { 5151 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object); 5152 5153 // Could not find an Alloca. 5154 if (!LifetimeObject) 5155 continue; 5156 5157 int FI = FuncInfo.StaticAllocaMap[LifetimeObject]; 5158 5159 SDValue Ops[2]; 5160 Ops[0] = getRoot(); 5161 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true); 5162 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END); 5163 5164 Res = DAG.getNode(Opcode, dl, MVT::Other, Ops, 2); 5165 DAG.setRoot(Res); 5166 } 5167 } 5168 case Intrinsic::invariant_start: 5169 // Discard region information. 5170 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5171 return 0; 5172 case Intrinsic::invariant_end: 5173 // Discard region information. 5174 return 0; 5175 case Intrinsic::donothing: 5176 // ignore 5177 return 0; 5178 } 5179} 5180 5181void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5182 bool isTailCall, 5183 MachineBasicBlock *LandingPad) { 5184 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5185 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5186 Type *RetTy = FTy->getReturnType(); 5187 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5188 MCSymbol *BeginLabel = 0; 5189 5190 TargetLowering::ArgListTy Args; 5191 TargetLowering::ArgListEntry Entry; 5192 Args.reserve(CS.arg_size()); 5193 5194 // Check whether the function can return without sret-demotion. 5195 SmallVector<ISD::OutputArg, 4> Outs; 5196 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5197 Outs, TLI); 5198 5199 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5200 DAG.getMachineFunction(), 5201 FTy->isVarArg(), Outs, 5202 FTy->getContext()); 5203 5204 SDValue DemoteStackSlot; 5205 int DemoteStackIdx = -100; 5206 5207 if (!CanLowerReturn) { 5208 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize( 5209 FTy->getReturnType()); 5210 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment( 5211 FTy->getReturnType()); 5212 MachineFunction &MF = DAG.getMachineFunction(); 5213 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5214 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5215 5216 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5217 Entry.Node = DemoteStackSlot; 5218 Entry.Ty = StackSlotPtrType; 5219 Entry.isSExt = false; 5220 Entry.isZExt = false; 5221 Entry.isInReg = false; 5222 Entry.isSRet = true; 5223 Entry.isNest = false; 5224 Entry.isByVal = false; 5225 Entry.Alignment = Align; 5226 Args.push_back(Entry); 5227 RetTy = Type::getVoidTy(FTy->getContext()); 5228 } 5229 5230 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5231 i != e; ++i) { 5232 const Value *V = *i; 5233 5234 // Skip empty types 5235 if (V->getType()->isEmptyTy()) 5236 continue; 5237 5238 SDValue ArgNode = getValue(V); 5239 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5240 5241 unsigned attrInd = i - CS.arg_begin() + 1; 5242 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5243 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5244 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5245 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5246 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5247 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5248 Entry.Alignment = CS.getParamAlignment(attrInd); 5249 Args.push_back(Entry); 5250 } 5251 5252 if (LandingPad) { 5253 // Insert a label before the invoke call to mark the try range. This can be 5254 // used to detect deletion of the invoke via the MachineModuleInfo. 5255 BeginLabel = MMI.getContext().CreateTempSymbol(); 5256 5257 // For SjLj, keep track of which landing pads go with which invokes 5258 // so as to maintain the ordering of pads in the LSDA. 5259 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5260 if (CallSiteIndex) { 5261 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5262 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5263 5264 // Now that the call site is handled, stop tracking it. 5265 MMI.setCurrentCallSite(0); 5266 } 5267 5268 // Both PendingLoads and PendingExports must be flushed here; 5269 // this call might not return. 5270 (void)getRoot(); 5271 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5272 } 5273 5274 // Check if target-independent constraints permit a tail call here. 5275 // Target-dependent constraints are checked within TLI.LowerCallTo. 5276 if (isTailCall && 5277 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5278 isTailCall = false; 5279 5280 TargetLowering:: 5281 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG, 5282 getCurDebugLoc(), CS); 5283 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI); 5284 assert((isTailCall || Result.second.getNode()) && 5285 "Non-null chain expected with non-tail call!"); 5286 assert((Result.second.getNode() || !Result.first.getNode()) && 5287 "Null value expected with tail call!"); 5288 if (Result.first.getNode()) { 5289 setValue(CS.getInstruction(), Result.first); 5290 } else if (!CanLowerReturn && Result.second.getNode()) { 5291 // The instruction result is the result of loading from the 5292 // hidden sret parameter. 5293 SmallVector<EVT, 1> PVTs; 5294 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5295 5296 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5297 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5298 EVT PtrVT = PVTs[0]; 5299 5300 SmallVector<EVT, 4> RetTys; 5301 SmallVector<uint64_t, 4> Offsets; 5302 RetTy = FTy->getReturnType(); 5303 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets); 5304 5305 unsigned NumValues = RetTys.size(); 5306 SmallVector<SDValue, 4> Values(NumValues); 5307 SmallVector<SDValue, 4> Chains(NumValues); 5308 5309 for (unsigned i = 0; i < NumValues; ++i) { 5310 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5311 DemoteStackSlot, 5312 DAG.getConstant(Offsets[i], PtrVT)); 5313 SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add, 5314 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5315 false, false, false, 1); 5316 Values[i] = L; 5317 Chains[i] = L.getValue(1); 5318 } 5319 5320 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5321 MVT::Other, &Chains[0], NumValues); 5322 PendingLoads.push_back(Chain); 5323 5324 setValue(CS.getInstruction(), 5325 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5326 DAG.getVTList(&RetTys[0], RetTys.size()), 5327 &Values[0], Values.size())); 5328 } 5329 5330 // Assign order to nodes here. If the call does not produce a result, it won't 5331 // be mapped to a SDNode and visit() will not assign it an order number. 5332 if (!Result.second.getNode()) { 5333 // As a special case, a null chain means that a tail call has been emitted and 5334 // the DAG root is already updated. 5335 HasTailCall = true; 5336 ++SDNodeOrder; 5337 AssignOrderingToNode(DAG.getRoot().getNode()); 5338 } else { 5339 DAG.setRoot(Result.second); 5340 ++SDNodeOrder; 5341 AssignOrderingToNode(Result.second.getNode()); 5342 } 5343 5344 if (LandingPad) { 5345 // Insert a label at the end of the invoke call to mark the try range. This 5346 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5347 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5348 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5349 5350 // Inform MachineModuleInfo of range. 5351 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5352 } 5353} 5354 5355/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5356/// value is equal or not-equal to zero. 5357static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5358 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5359 UI != E; ++UI) { 5360 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5361 if (IC->isEquality()) 5362 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5363 if (C->isNullValue()) 5364 continue; 5365 // Unknown instruction. 5366 return false; 5367 } 5368 return true; 5369} 5370 5371static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5372 Type *LoadTy, 5373 SelectionDAGBuilder &Builder) { 5374 5375 // Check to see if this load can be trivially constant folded, e.g. if the 5376 // input is from a string literal. 5377 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5378 // Cast pointer to the type we really want to load. 5379 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5380 PointerType::getUnqual(LoadTy)); 5381 5382 if (const Constant *LoadCst = 5383 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5384 Builder.TD)) 5385 return Builder.getValue(LoadCst); 5386 } 5387 5388 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5389 // still constant memory, the input chain can be the entry node. 5390 SDValue Root; 5391 bool ConstantMemory = false; 5392 5393 // Do not serialize (non-volatile) loads of constant memory with anything. 5394 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5395 Root = Builder.DAG.getEntryNode(); 5396 ConstantMemory = true; 5397 } else { 5398 // Do not serialize non-volatile loads against each other. 5399 Root = Builder.DAG.getRoot(); 5400 } 5401 5402 SDValue Ptr = Builder.getValue(PtrVal); 5403 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5404 Ptr, MachinePointerInfo(PtrVal), 5405 false /*volatile*/, 5406 false /*nontemporal*/, 5407 false /*isinvariant*/, 1 /* align=1 */); 5408 5409 if (!ConstantMemory) 5410 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5411 return LoadVal; 5412} 5413 5414 5415/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5416/// If so, return true and lower it, otherwise return false and it will be 5417/// lowered like a normal call. 5418bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5419 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5420 if (I.getNumArgOperands() != 3) 5421 return false; 5422 5423 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5424 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5425 !I.getArgOperand(2)->getType()->isIntegerTy() || 5426 !I.getType()->isIntegerTy()) 5427 return false; 5428 5429 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5430 5431 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5432 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5433 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5434 bool ActuallyDoIt = true; 5435 MVT LoadVT; 5436 Type *LoadTy; 5437 switch (Size->getZExtValue()) { 5438 default: 5439 LoadVT = MVT::Other; 5440 LoadTy = 0; 5441 ActuallyDoIt = false; 5442 break; 5443 case 2: 5444 LoadVT = MVT::i16; 5445 LoadTy = Type::getInt16Ty(Size->getContext()); 5446 break; 5447 case 4: 5448 LoadVT = MVT::i32; 5449 LoadTy = Type::getInt32Ty(Size->getContext()); 5450 break; 5451 case 8: 5452 LoadVT = MVT::i64; 5453 LoadTy = Type::getInt64Ty(Size->getContext()); 5454 break; 5455 /* 5456 case 16: 5457 LoadVT = MVT::v4i32; 5458 LoadTy = Type::getInt32Ty(Size->getContext()); 5459 LoadTy = VectorType::get(LoadTy, 4); 5460 break; 5461 */ 5462 } 5463 5464 // This turns into unaligned loads. We only do this if the target natively 5465 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5466 // we'll only produce a small number of byte loads. 5467 5468 // Require that we can find a legal MVT, and only do this if the target 5469 // supports unaligned loads of that type. Expanding into byte loads would 5470 // bloat the code. 5471 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5472 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5473 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5474 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5475 ActuallyDoIt = false; 5476 } 5477 5478 if (ActuallyDoIt) { 5479 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5480 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5481 5482 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5483 ISD::SETNE); 5484 EVT CallVT = TLI.getValueType(I.getType(), true); 5485 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5486 return true; 5487 } 5488 } 5489 5490 5491 return false; 5492} 5493 5494/// visitUnaryFloatCall - If a call instruction is a unary floating-point 5495/// operation (as expected), translate it to an SDNode with the specified opcode 5496/// and return true. 5497bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I, 5498 unsigned Opcode) { 5499 // Sanity check that it really is a unary floating-point call. 5500 if (I.getNumArgOperands() != 1 || 5501 !I.getArgOperand(0)->getType()->isFloatingPointTy() || 5502 I.getType() != I.getArgOperand(0)->getType() || 5503 !I.onlyReadsMemory()) 5504 return false; 5505 5506 SDValue Tmp = getValue(I.getArgOperand(0)); 5507 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), Tmp.getValueType(), Tmp)); 5508 return true; 5509} 5510 5511void SelectionDAGBuilder::visitCall(const CallInst &I) { 5512 // Handle inline assembly differently. 5513 if (isa<InlineAsm>(I.getCalledValue())) { 5514 visitInlineAsm(&I); 5515 return; 5516 } 5517 5518 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5519 ComputeUsesVAFloatArgument(I, &MMI); 5520 5521 const char *RenameFn = 0; 5522 if (Function *F = I.getCalledFunction()) { 5523 if (F->isDeclaration()) { 5524 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5525 if (unsigned IID = II->getIntrinsicID(F)) { 5526 RenameFn = visitIntrinsicCall(I, IID); 5527 if (!RenameFn) 5528 return; 5529 } 5530 } 5531 if (unsigned IID = F->getIntrinsicID()) { 5532 RenameFn = visitIntrinsicCall(I, IID); 5533 if (!RenameFn) 5534 return; 5535 } 5536 } 5537 5538 // Check for well-known libc/libm calls. If the function is internal, it 5539 // can't be a library call. 5540 LibFunc::Func Func; 5541 if (!F->hasLocalLinkage() && F->hasName() && 5542 LibInfo->getLibFunc(F->getName(), Func) && 5543 LibInfo->hasOptimizedCodeGen(Func)) { 5544 switch (Func) { 5545 default: break; 5546 case LibFunc::copysign: 5547 case LibFunc::copysignf: 5548 case LibFunc::copysignl: 5549 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5550 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5551 I.getType() == I.getArgOperand(0)->getType() && 5552 I.getType() == I.getArgOperand(1)->getType() && 5553 I.onlyReadsMemory()) { 5554 SDValue LHS = getValue(I.getArgOperand(0)); 5555 SDValue RHS = getValue(I.getArgOperand(1)); 5556 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5557 LHS.getValueType(), LHS, RHS)); 5558 return; 5559 } 5560 break; 5561 case LibFunc::fabs: 5562 case LibFunc::fabsf: 5563 case LibFunc::fabsl: 5564 if (visitUnaryFloatCall(I, ISD::FABS)) 5565 return; 5566 break; 5567 case LibFunc::sin: 5568 case LibFunc::sinf: 5569 case LibFunc::sinl: 5570 if (visitUnaryFloatCall(I, ISD::FSIN)) 5571 return; 5572 break; 5573 case LibFunc::cos: 5574 case LibFunc::cosf: 5575 case LibFunc::cosl: 5576 if (visitUnaryFloatCall(I, ISD::FCOS)) 5577 return; 5578 break; 5579 case LibFunc::sqrt: 5580 case LibFunc::sqrtf: 5581 case LibFunc::sqrtl: 5582 if (visitUnaryFloatCall(I, ISD::FSQRT)) 5583 return; 5584 break; 5585 case LibFunc::floor: 5586 case LibFunc::floorf: 5587 case LibFunc::floorl: 5588 if (visitUnaryFloatCall(I, ISD::FFLOOR)) 5589 return; 5590 break; 5591 case LibFunc::nearbyint: 5592 case LibFunc::nearbyintf: 5593 case LibFunc::nearbyintl: 5594 if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) 5595 return; 5596 break; 5597 case LibFunc::ceil: 5598 case LibFunc::ceilf: 5599 case LibFunc::ceill: 5600 if (visitUnaryFloatCall(I, ISD::FCEIL)) 5601 return; 5602 break; 5603 case LibFunc::rint: 5604 case LibFunc::rintf: 5605 case LibFunc::rintl: 5606 if (visitUnaryFloatCall(I, ISD::FRINT)) 5607 return; 5608 break; 5609 case LibFunc::trunc: 5610 case LibFunc::truncf: 5611 case LibFunc::truncl: 5612 if (visitUnaryFloatCall(I, ISD::FTRUNC)) 5613 return; 5614 break; 5615 case LibFunc::log2: 5616 case LibFunc::log2f: 5617 case LibFunc::log2l: 5618 if (visitUnaryFloatCall(I, ISD::FLOG2)) 5619 return; 5620 break; 5621 case LibFunc::exp2: 5622 case LibFunc::exp2f: 5623 case LibFunc::exp2l: 5624 if (visitUnaryFloatCall(I, ISD::FEXP2)) 5625 return; 5626 break; 5627 case LibFunc::memcmp: 5628 if (visitMemCmpCall(I)) 5629 return; 5630 break; 5631 } 5632 } 5633 } 5634 5635 SDValue Callee; 5636 if (!RenameFn) 5637 Callee = getValue(I.getCalledValue()); 5638 else 5639 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5640 5641 // Check if we can potentially perform a tail call. More detailed checking is 5642 // be done within LowerCallTo, after more information about the call is known. 5643 LowerCallTo(&I, Callee, I.isTailCall()); 5644} 5645 5646namespace { 5647 5648/// AsmOperandInfo - This contains information for each constraint that we are 5649/// lowering. 5650class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5651public: 5652 /// CallOperand - If this is the result output operand or a clobber 5653 /// this is null, otherwise it is the incoming operand to the CallInst. 5654 /// This gets modified as the asm is processed. 5655 SDValue CallOperand; 5656 5657 /// AssignedRegs - If this is a register or register class operand, this 5658 /// contains the set of register corresponding to the operand. 5659 RegsForValue AssignedRegs; 5660 5661 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5662 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5663 } 5664 5665 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5666 /// corresponds to. If there is no Value* for this operand, it returns 5667 /// MVT::Other. 5668 EVT getCallOperandValEVT(LLVMContext &Context, 5669 const TargetLowering &TLI, 5670 const DataLayout *TD) const { 5671 if (CallOperandVal == 0) return MVT::Other; 5672 5673 if (isa<BasicBlock>(CallOperandVal)) 5674 return TLI.getPointerTy(); 5675 5676 llvm::Type *OpTy = CallOperandVal->getType(); 5677 5678 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5679 // If this is an indirect operand, the operand is a pointer to the 5680 // accessed type. 5681 if (isIndirect) { 5682 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5683 if (!PtrTy) 5684 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5685 OpTy = PtrTy->getElementType(); 5686 } 5687 5688 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5689 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5690 if (STy->getNumElements() == 1) 5691 OpTy = STy->getElementType(0); 5692 5693 // If OpTy is not a single value, it may be a struct/union that we 5694 // can tile with integers. 5695 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5696 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5697 switch (BitSize) { 5698 default: break; 5699 case 1: 5700 case 8: 5701 case 16: 5702 case 32: 5703 case 64: 5704 case 128: 5705 OpTy = IntegerType::get(Context, BitSize); 5706 break; 5707 } 5708 } 5709 5710 return TLI.getValueType(OpTy, true); 5711 } 5712}; 5713 5714typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5715 5716} // end anonymous namespace 5717 5718/// GetRegistersForValue - Assign registers (virtual or physical) for the 5719/// specified operand. We prefer to assign virtual registers, to allow the 5720/// register allocator to handle the assignment process. However, if the asm 5721/// uses features that we can't model on machineinstrs, we have SDISel do the 5722/// allocation. This produces generally horrible, but correct, code. 5723/// 5724/// OpInfo describes the operand. 5725/// 5726static void GetRegistersForValue(SelectionDAG &DAG, 5727 const TargetLowering &TLI, 5728 DebugLoc DL, 5729 SDISelAsmOperandInfo &OpInfo) { 5730 LLVMContext &Context = *DAG.getContext(); 5731 5732 MachineFunction &MF = DAG.getMachineFunction(); 5733 SmallVector<unsigned, 4> Regs; 5734 5735 // If this is a constraint for a single physreg, or a constraint for a 5736 // register class, find it. 5737 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5738 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5739 OpInfo.ConstraintVT); 5740 5741 unsigned NumRegs = 1; 5742 if (OpInfo.ConstraintVT != MVT::Other) { 5743 // If this is a FP input in an integer register (or visa versa) insert a bit 5744 // cast of the input value. More generally, handle any case where the input 5745 // value disagrees with the register class we plan to stick this in. 5746 if (OpInfo.Type == InlineAsm::isInput && 5747 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5748 // Try to convert to the first EVT that the reg class contains. If the 5749 // types are identical size, use a bitcast to convert (e.g. two differing 5750 // vector types). 5751 EVT RegVT = *PhysReg.second->vt_begin(); 5752 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5753 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5754 RegVT, OpInfo.CallOperand); 5755 OpInfo.ConstraintVT = RegVT; 5756 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5757 // If the input is a FP value and we want it in FP registers, do a 5758 // bitcast to the corresponding integer type. This turns an f64 value 5759 // into i64, which can be passed with two i32 values on a 32-bit 5760 // machine. 5761 RegVT = EVT::getIntegerVT(Context, 5762 OpInfo.ConstraintVT.getSizeInBits()); 5763 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5764 RegVT, OpInfo.CallOperand); 5765 OpInfo.ConstraintVT = RegVT; 5766 } 5767 } 5768 5769 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5770 } 5771 5772 EVT RegVT; 5773 EVT ValueVT = OpInfo.ConstraintVT; 5774 5775 // If this is a constraint for a specific physical register, like {r17}, 5776 // assign it now. 5777 if (unsigned AssignedReg = PhysReg.first) { 5778 const TargetRegisterClass *RC = PhysReg.second; 5779 if (OpInfo.ConstraintVT == MVT::Other) 5780 ValueVT = *RC->vt_begin(); 5781 5782 // Get the actual register value type. This is important, because the user 5783 // may have asked for (e.g.) the AX register in i32 type. We need to 5784 // remember that AX is actually i16 to get the right extension. 5785 RegVT = *RC->vt_begin(); 5786 5787 // This is a explicit reference to a physical register. 5788 Regs.push_back(AssignedReg); 5789 5790 // If this is an expanded reference, add the rest of the regs to Regs. 5791 if (NumRegs != 1) { 5792 TargetRegisterClass::iterator I = RC->begin(); 5793 for (; *I != AssignedReg; ++I) 5794 assert(I != RC->end() && "Didn't find reg!"); 5795 5796 // Already added the first reg. 5797 --NumRegs; ++I; 5798 for (; NumRegs; --NumRegs, ++I) { 5799 assert(I != RC->end() && "Ran out of registers to allocate!"); 5800 Regs.push_back(*I); 5801 } 5802 } 5803 5804 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5805 return; 5806 } 5807 5808 // Otherwise, if this was a reference to an LLVM register class, create vregs 5809 // for this reference. 5810 if (const TargetRegisterClass *RC = PhysReg.second) { 5811 RegVT = *RC->vt_begin(); 5812 if (OpInfo.ConstraintVT == MVT::Other) 5813 ValueVT = RegVT; 5814 5815 // Create the appropriate number of virtual registers. 5816 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5817 for (; NumRegs; --NumRegs) 5818 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5819 5820 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5821 return; 5822 } 5823 5824 // Otherwise, we couldn't allocate enough registers for this. 5825} 5826 5827/// visitInlineAsm - Handle a call to an InlineAsm object. 5828/// 5829void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5830 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5831 5832 /// ConstraintOperands - Information about all of the constraints. 5833 SDISelAsmOperandInfoVector ConstraintOperands; 5834 5835 TargetLowering::AsmOperandInfoVector 5836 TargetConstraints = TLI.ParseConstraints(CS); 5837 5838 bool hasMemory = false; 5839 5840 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5841 unsigned ResNo = 0; // ResNo - The result number of the next output. 5842 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5843 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5844 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5845 5846 EVT OpVT = MVT::Other; 5847 5848 // Compute the value type for each operand. 5849 switch (OpInfo.Type) { 5850 case InlineAsm::isOutput: 5851 // Indirect outputs just consume an argument. 5852 if (OpInfo.isIndirect) { 5853 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5854 break; 5855 } 5856 5857 // The return value of the call is this value. As such, there is no 5858 // corresponding argument. 5859 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5860 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5861 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5862 } else { 5863 assert(ResNo == 0 && "Asm only has one result!"); 5864 OpVT = TLI.getValueType(CS.getType()); 5865 } 5866 ++ResNo; 5867 break; 5868 case InlineAsm::isInput: 5869 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5870 break; 5871 case InlineAsm::isClobber: 5872 // Nothing to do. 5873 break; 5874 } 5875 5876 // If this is an input or an indirect output, process the call argument. 5877 // BasicBlocks are labels, currently appearing only in asm's. 5878 if (OpInfo.CallOperandVal) { 5879 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5880 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5881 } else { 5882 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5883 } 5884 5885 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5886 } 5887 5888 OpInfo.ConstraintVT = OpVT; 5889 5890 // Indirect operand accesses access memory. 5891 if (OpInfo.isIndirect) 5892 hasMemory = true; 5893 else { 5894 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5895 TargetLowering::ConstraintType 5896 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5897 if (CType == TargetLowering::C_Memory) { 5898 hasMemory = true; 5899 break; 5900 } 5901 } 5902 } 5903 } 5904 5905 SDValue Chain, Flag; 5906 5907 // We won't need to flush pending loads if this asm doesn't touch 5908 // memory and is nonvolatile. 5909 if (hasMemory || IA->hasSideEffects()) 5910 Chain = getRoot(); 5911 else 5912 Chain = DAG.getRoot(); 5913 5914 // Second pass over the constraints: compute which constraint option to use 5915 // and assign registers to constraints that want a specific physreg. 5916 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5917 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5918 5919 // If this is an output operand with a matching input operand, look up the 5920 // matching input. If their types mismatch, e.g. one is an integer, the 5921 // other is floating point, or their sizes are different, flag it as an 5922 // error. 5923 if (OpInfo.hasMatchingInput()) { 5924 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5925 5926 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5927 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5928 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5929 OpInfo.ConstraintVT); 5930 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5931 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 5932 Input.ConstraintVT); 5933 if ((OpInfo.ConstraintVT.isInteger() != 5934 Input.ConstraintVT.isInteger()) || 5935 (MatchRC.second != InputRC.second)) { 5936 report_fatal_error("Unsupported asm: input constraint" 5937 " with a matching output constraint of" 5938 " incompatible type!"); 5939 } 5940 Input.ConstraintVT = OpInfo.ConstraintVT; 5941 } 5942 } 5943 5944 // Compute the constraint code and ConstraintType to use. 5945 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5946 5947 // If this is a memory input, and if the operand is not indirect, do what we 5948 // need to to provide an address for the memory input. 5949 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5950 !OpInfo.isIndirect) { 5951 assert((OpInfo.isMultipleAlternative || 5952 (OpInfo.Type == InlineAsm::isInput)) && 5953 "Can only indirectify direct input operands!"); 5954 5955 // Memory operands really want the address of the value. If we don't have 5956 // an indirect input, put it in the constpool if we can, otherwise spill 5957 // it to a stack slot. 5958 // TODO: This isn't quite right. We need to handle these according to 5959 // the addressing mode that the constraint wants. Also, this may take 5960 // an additional register for the computation and we don't want that 5961 // either. 5962 5963 // If the operand is a float, integer, or vector constant, spill to a 5964 // constant pool entry to get its address. 5965 const Value *OpVal = OpInfo.CallOperandVal; 5966 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5967 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { 5968 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5969 TLI.getPointerTy()); 5970 } else { 5971 // Otherwise, create a stack slot and emit a store to it before the 5972 // asm. 5973 Type *Ty = OpVal->getType(); 5974 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty); 5975 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty); 5976 MachineFunction &MF = DAG.getMachineFunction(); 5977 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5978 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5979 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5980 OpInfo.CallOperand, StackSlot, 5981 MachinePointerInfo::getFixedStack(SSFI), 5982 false, false, 0); 5983 OpInfo.CallOperand = StackSlot; 5984 } 5985 5986 // There is no longer a Value* corresponding to this operand. 5987 OpInfo.CallOperandVal = 0; 5988 5989 // It is now an indirect operand. 5990 OpInfo.isIndirect = true; 5991 } 5992 5993 // If this constraint is for a specific register, allocate it before 5994 // anything else. 5995 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5996 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 5997 } 5998 5999 // Second pass - Loop over all of the operands, assigning virtual or physregs 6000 // to register class operands. 6001 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6002 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6003 6004 // C_Register operands have already been allocated, Other/Memory don't need 6005 // to be. 6006 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6007 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6008 } 6009 6010 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6011 std::vector<SDValue> AsmNodeOperands; 6012 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6013 AsmNodeOperands.push_back( 6014 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6015 TLI.getPointerTy())); 6016 6017 // If we have a !srcloc metadata node associated with it, we want to attach 6018 // this to the ultimately generated inline asm machineinstr. To do this, we 6019 // pass in the third operand as this (potentially null) inline asm MDNode. 6020 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6021 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6022 6023 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore 6024 // bits as operand 3. 6025 unsigned ExtraInfo = 0; 6026 if (IA->hasSideEffects()) 6027 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6028 if (IA->isAlignStack()) 6029 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6030 // Set the asm dialect. 6031 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect; 6032 6033 // Determine if this InlineAsm MayLoad or MayStore based on the constraints. 6034 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 6035 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i]; 6036 6037 // Compute the constraint code and ConstraintType to use. 6038 TLI.ComputeConstraintToUse(OpInfo, SDValue()); 6039 6040 // Ideally, we would only check against memory constraints. However, the 6041 // meaning of an other constraint can be target-specific and we can't easily 6042 // reason about it. Therefore, be conservative and set MayLoad/MayStore 6043 // for other constriants as well. 6044 if (OpInfo.ConstraintType == TargetLowering::C_Memory || 6045 OpInfo.ConstraintType == TargetLowering::C_Other) { 6046 if (OpInfo.Type == InlineAsm::isInput) 6047 ExtraInfo |= InlineAsm::Extra_MayLoad; 6048 else if (OpInfo.Type == InlineAsm::isOutput) 6049 ExtraInfo |= InlineAsm::Extra_MayStore; 6050 } 6051 } 6052 6053 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6054 TLI.getPointerTy())); 6055 6056 // Loop over all of the inputs, copying the operand values into the 6057 // appropriate registers and processing the output regs. 6058 RegsForValue RetValRegs; 6059 6060 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6061 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6062 6063 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6064 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6065 6066 switch (OpInfo.Type) { 6067 case InlineAsm::isOutput: { 6068 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6069 OpInfo.ConstraintType != TargetLowering::C_Register) { 6070 // Memory output, or 'other' output (e.g. 'X' constraint). 6071 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6072 6073 // Add information to the INLINEASM node to know about this output. 6074 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6075 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6076 TLI.getPointerTy())); 6077 AsmNodeOperands.push_back(OpInfo.CallOperand); 6078 break; 6079 } 6080 6081 // Otherwise, this is a register or register class output. 6082 6083 // Copy the output from the appropriate register. Find a register that 6084 // we can use. 6085 if (OpInfo.AssignedRegs.Regs.empty()) { 6086 LLVMContext &Ctx = *DAG.getContext(); 6087 Ctx.emitError(CS.getInstruction(), 6088 "couldn't allocate output register for constraint '" + 6089 Twine(OpInfo.ConstraintCode) + "'"); 6090 break; 6091 } 6092 6093 // If this is an indirect operand, store through the pointer after the 6094 // asm. 6095 if (OpInfo.isIndirect) { 6096 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6097 OpInfo.CallOperandVal)); 6098 } else { 6099 // This is the result value of the call. 6100 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6101 // Concatenate this output onto the outputs list. 6102 RetValRegs.append(OpInfo.AssignedRegs); 6103 } 6104 6105 // Add information to the INLINEASM node to know that this register is 6106 // set. 6107 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6108 InlineAsm::Kind_RegDefEarlyClobber : 6109 InlineAsm::Kind_RegDef, 6110 false, 6111 0, 6112 DAG, 6113 AsmNodeOperands); 6114 break; 6115 } 6116 case InlineAsm::isInput: { 6117 SDValue InOperandVal = OpInfo.CallOperand; 6118 6119 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6120 // If this is required to match an output register we have already set, 6121 // just use its register. 6122 unsigned OperandNo = OpInfo.getMatchedOperand(); 6123 6124 // Scan until we find the definition we already emitted of this operand. 6125 // When we find it, create a RegsForValue operand. 6126 unsigned CurOp = InlineAsm::Op_FirstOperand; 6127 for (; OperandNo; --OperandNo) { 6128 // Advance to the next operand. 6129 unsigned OpFlag = 6130 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6131 assert((InlineAsm::isRegDefKind(OpFlag) || 6132 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6133 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6134 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6135 } 6136 6137 unsigned OpFlag = 6138 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6139 if (InlineAsm::isRegDefKind(OpFlag) || 6140 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6141 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6142 if (OpInfo.isIndirect) { 6143 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6144 LLVMContext &Ctx = *DAG.getContext(); 6145 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6146 " don't know how to handle tied " 6147 "indirect register inputs"); 6148 } 6149 6150 RegsForValue MatchedRegs; 6151 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6152 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType(); 6153 MatchedRegs.RegVTs.push_back(RegVT); 6154 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6155 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6156 i != e; ++i) 6157 MatchedRegs.Regs.push_back 6158 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6159 6160 // Use the produced MatchedRegs object to 6161 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6162 Chain, &Flag, CS.getInstruction()); 6163 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6164 true, OpInfo.getMatchedOperand(), 6165 DAG, AsmNodeOperands); 6166 break; 6167 } 6168 6169 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6170 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6171 "Unexpected number of operands"); 6172 // Add information to the INLINEASM node to know about this input. 6173 // See InlineAsm.h isUseOperandTiedToDef. 6174 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6175 OpInfo.getMatchedOperand()); 6176 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6177 TLI.getPointerTy())); 6178 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6179 break; 6180 } 6181 6182 // Treat indirect 'X' constraint as memory. 6183 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6184 OpInfo.isIndirect) 6185 OpInfo.ConstraintType = TargetLowering::C_Memory; 6186 6187 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6188 std::vector<SDValue> Ops; 6189 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6190 Ops, DAG); 6191 if (Ops.empty()) { 6192 LLVMContext &Ctx = *DAG.getContext(); 6193 Ctx.emitError(CS.getInstruction(), 6194 "invalid operand for inline asm constraint '" + 6195 Twine(OpInfo.ConstraintCode) + "'"); 6196 break; 6197 } 6198 6199 // Add information to the INLINEASM node to know about this input. 6200 unsigned ResOpType = 6201 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6202 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6203 TLI.getPointerTy())); 6204 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6205 break; 6206 } 6207 6208 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6209 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6210 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6211 "Memory operands expect pointer values"); 6212 6213 // Add information to the INLINEASM node to know about this input. 6214 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6215 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6216 TLI.getPointerTy())); 6217 AsmNodeOperands.push_back(InOperandVal); 6218 break; 6219 } 6220 6221 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6222 OpInfo.ConstraintType == TargetLowering::C_Register) && 6223 "Unknown constraint type!"); 6224 6225 // TODO: Support this. 6226 if (OpInfo.isIndirect) { 6227 LLVMContext &Ctx = *DAG.getContext(); 6228 Ctx.emitError(CS.getInstruction(), 6229 "Don't know how to handle indirect register inputs yet " 6230 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'"); 6231 break; 6232 } 6233 6234 // Copy the input into the appropriate registers. 6235 if (OpInfo.AssignedRegs.Regs.empty()) { 6236 LLVMContext &Ctx = *DAG.getContext(); 6237 Ctx.emitError(CS.getInstruction(), 6238 "couldn't allocate input reg for constraint '" + 6239 Twine(OpInfo.ConstraintCode) + "'"); 6240 break; 6241 } 6242 6243 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6244 Chain, &Flag, CS.getInstruction()); 6245 6246 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6247 DAG, AsmNodeOperands); 6248 break; 6249 } 6250 case InlineAsm::isClobber: { 6251 // Add the clobbered value to the operand list, so that the register 6252 // allocator is aware that the physreg got clobbered. 6253 if (!OpInfo.AssignedRegs.Regs.empty()) 6254 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6255 false, 0, DAG, 6256 AsmNodeOperands); 6257 break; 6258 } 6259 } 6260 } 6261 6262 // Finish up input operands. Set the input chain and add the flag last. 6263 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6264 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6265 6266 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6267 DAG.getVTList(MVT::Other, MVT::Glue), 6268 &AsmNodeOperands[0], AsmNodeOperands.size()); 6269 Flag = Chain.getValue(1); 6270 6271 // If this asm returns a register value, copy the result from that register 6272 // and set it as the value of the call. 6273 if (!RetValRegs.Regs.empty()) { 6274 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6275 Chain, &Flag, CS.getInstruction()); 6276 6277 // FIXME: Why don't we do this for inline asms with MRVs? 6278 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6279 EVT ResultType = TLI.getValueType(CS.getType()); 6280 6281 // If any of the results of the inline asm is a vector, it may have the 6282 // wrong width/num elts. This can happen for register classes that can 6283 // contain multiple different value types. The preg or vreg allocated may 6284 // not have the same VT as was expected. Convert it to the right type 6285 // with bit_convert. 6286 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6287 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6288 ResultType, Val); 6289 6290 } else if (ResultType != Val.getValueType() && 6291 ResultType.isInteger() && Val.getValueType().isInteger()) { 6292 // If a result value was tied to an input value, the computed result may 6293 // have a wider width than the expected result. Extract the relevant 6294 // portion. 6295 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6296 } 6297 6298 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6299 } 6300 6301 setValue(CS.getInstruction(), Val); 6302 // Don't need to use this as a chain in this case. 6303 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6304 return; 6305 } 6306 6307 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6308 6309 // Process indirect outputs, first output all of the flagged copies out of 6310 // physregs. 6311 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6312 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6313 const Value *Ptr = IndirectStoresToEmit[i].second; 6314 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6315 Chain, &Flag, IA); 6316 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6317 } 6318 6319 // Emit the non-flagged stores from the physregs. 6320 SmallVector<SDValue, 8> OutChains; 6321 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6322 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6323 StoresToEmit[i].first, 6324 getValue(StoresToEmit[i].second), 6325 MachinePointerInfo(StoresToEmit[i].second), 6326 false, false, 0); 6327 OutChains.push_back(Val); 6328 } 6329 6330 if (!OutChains.empty()) 6331 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6332 &OutChains[0], OutChains.size()); 6333 6334 DAG.setRoot(Chain); 6335} 6336 6337void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6338 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6339 MVT::Other, getRoot(), 6340 getValue(I.getArgOperand(0)), 6341 DAG.getSrcValue(I.getArgOperand(0)))); 6342} 6343 6344void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6345 const DataLayout &TD = *TLI.getDataLayout(); 6346 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6347 getRoot(), getValue(I.getOperand(0)), 6348 DAG.getSrcValue(I.getOperand(0)), 6349 TD.getABITypeAlignment(I.getType())); 6350 setValue(&I, V); 6351 DAG.setRoot(V.getValue(1)); 6352} 6353 6354void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6355 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6356 MVT::Other, getRoot(), 6357 getValue(I.getArgOperand(0)), 6358 DAG.getSrcValue(I.getArgOperand(0)))); 6359} 6360 6361void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6362 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6363 MVT::Other, getRoot(), 6364 getValue(I.getArgOperand(0)), 6365 getValue(I.getArgOperand(1)), 6366 DAG.getSrcValue(I.getArgOperand(0)), 6367 DAG.getSrcValue(I.getArgOperand(1)))); 6368} 6369 6370/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6371/// implementation, which just calls LowerCall. 6372/// FIXME: When all targets are 6373/// migrated to using LowerCall, this hook should be integrated into SDISel. 6374std::pair<SDValue, SDValue> 6375TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { 6376 // Handle all of the outgoing arguments. 6377 CLI.Outs.clear(); 6378 CLI.OutVals.clear(); 6379 ArgListTy &Args = CLI.Args; 6380 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6381 SmallVector<EVT, 4> ValueVTs; 6382 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6383 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6384 Value != NumValues; ++Value) { 6385 EVT VT = ValueVTs[Value]; 6386 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); 6387 SDValue Op = SDValue(Args[i].Node.getNode(), 6388 Args[i].Node.getResNo() + Value); 6389 ISD::ArgFlagsTy Flags; 6390 unsigned OriginalAlignment = 6391 getDataLayout()->getABITypeAlignment(ArgTy); 6392 6393 if (Args[i].isZExt) 6394 Flags.setZExt(); 6395 if (Args[i].isSExt) 6396 Flags.setSExt(); 6397 if (Args[i].isInReg) 6398 Flags.setInReg(); 6399 if (Args[i].isSRet) 6400 Flags.setSRet(); 6401 if (Args[i].isByVal) { 6402 Flags.setByVal(); 6403 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6404 Type *ElementTy = Ty->getElementType(); 6405 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy)); 6406 // For ByVal, alignment should come from FE. BE will guess if this 6407 // info is not there but there are cases it cannot get right. 6408 unsigned FrameAlign; 6409 if (Args[i].Alignment) 6410 FrameAlign = Args[i].Alignment; 6411 else 6412 FrameAlign = getByValTypeAlignment(ElementTy); 6413 Flags.setByValAlign(FrameAlign); 6414 } 6415 if (Args[i].isNest) 6416 Flags.setNest(); 6417 Flags.setOrigAlign(OriginalAlignment); 6418 6419 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT); 6420 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT); 6421 SmallVector<SDValue, 4> Parts(NumParts); 6422 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6423 6424 if (Args[i].isSExt) 6425 ExtendKind = ISD::SIGN_EXTEND; 6426 else if (Args[i].isZExt) 6427 ExtendKind = ISD::ZERO_EXTEND; 6428 6429 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, 6430 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind); 6431 6432 for (unsigned j = 0; j != NumParts; ++j) { 6433 // if it isn't first piece, alignment must be 1 6434 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6435 i < CLI.NumFixedArgs, 6436 i, j*Parts[j].getValueType().getStoreSize()); 6437 if (NumParts > 1 && j == 0) 6438 MyFlags.Flags.setSplit(); 6439 else if (j != 0) 6440 MyFlags.Flags.setOrigAlign(1); 6441 6442 CLI.Outs.push_back(MyFlags); 6443 CLI.OutVals.push_back(Parts[j]); 6444 } 6445 } 6446 } 6447 6448 // Handle the incoming return values from the call. 6449 CLI.Ins.clear(); 6450 SmallVector<EVT, 4> RetTys; 6451 ComputeValueVTs(*this, CLI.RetTy, RetTys); 6452 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6453 EVT VT = RetTys[I]; 6454 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6455 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6456 for (unsigned i = 0; i != NumRegs; ++i) { 6457 ISD::InputArg MyFlags; 6458 MyFlags.VT = RegisterVT; 6459 MyFlags.Used = CLI.IsReturnValueUsed; 6460 if (CLI.RetSExt) 6461 MyFlags.Flags.setSExt(); 6462 if (CLI.RetZExt) 6463 MyFlags.Flags.setZExt(); 6464 if (CLI.IsInReg) 6465 MyFlags.Flags.setInReg(); 6466 CLI.Ins.push_back(MyFlags); 6467 } 6468 } 6469 6470 SmallVector<SDValue, 4> InVals; 6471 CLI.Chain = LowerCall(CLI, InVals); 6472 6473 // Verify that the target's LowerCall behaved as expected. 6474 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && 6475 "LowerCall didn't return a valid chain!"); 6476 assert((!CLI.IsTailCall || InVals.empty()) && 6477 "LowerCall emitted a return value for a tail call!"); 6478 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && 6479 "LowerCall didn't emit the correct number of values!"); 6480 6481 // For a tail call, the return value is merely live-out and there aren't 6482 // any nodes in the DAG representing it. Return a special value to 6483 // indicate that a tail call has been emitted and no more Instructions 6484 // should be processed in the current block. 6485 if (CLI.IsTailCall) { 6486 CLI.DAG.setRoot(CLI.Chain); 6487 return std::make_pair(SDValue(), SDValue()); 6488 } 6489 6490 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { 6491 assert(InVals[i].getNode() && 6492 "LowerCall emitted a null value!"); 6493 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && 6494 "LowerCall emitted a value with the wrong type!"); 6495 }); 6496 6497 // Collect the legal value parts into potentially illegal values 6498 // that correspond to the original function's return values. 6499 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6500 if (CLI.RetSExt) 6501 AssertOp = ISD::AssertSext; 6502 else if (CLI.RetZExt) 6503 AssertOp = ISD::AssertZext; 6504 SmallVector<SDValue, 4> ReturnValues; 6505 unsigned CurReg = 0; 6506 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6507 EVT VT = RetTys[I]; 6508 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6509 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6510 6511 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], 6512 NumRegs, RegisterVT, VT, NULL, 6513 AssertOp)); 6514 CurReg += NumRegs; 6515 } 6516 6517 // For a function returning void, there is no return value. We can't create 6518 // such a node, so we just return a null return value in that case. In 6519 // that case, nothing will actually look at the value. 6520 if (ReturnValues.empty()) 6521 return std::make_pair(SDValue(), CLI.Chain); 6522 6523 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, 6524 CLI.DAG.getVTList(&RetTys[0], RetTys.size()), 6525 &ReturnValues[0], ReturnValues.size()); 6526 return std::make_pair(Res, CLI.Chain); 6527} 6528 6529void TargetLowering::LowerOperationWrapper(SDNode *N, 6530 SmallVectorImpl<SDValue> &Results, 6531 SelectionDAG &DAG) const { 6532 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6533 if (Res.getNode()) 6534 Results.push_back(Res); 6535} 6536 6537SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6538 llvm_unreachable("LowerOperation not implemented for this target!"); 6539} 6540 6541void 6542SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6543 SDValue Op = getNonRegisterValue(V); 6544 assert((Op.getOpcode() != ISD::CopyFromReg || 6545 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6546 "Copy from a reg to the same reg!"); 6547 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6548 6549 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6550 SDValue Chain = DAG.getEntryNode(); 6551 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0, V); 6552 PendingExports.push_back(Chain); 6553} 6554 6555#include "llvm/CodeGen/SelectionDAGISel.h" 6556 6557/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6558/// entry block, return true. This includes arguments used by switches, since 6559/// the switch may expand into multiple basic blocks. 6560static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 6561 // With FastISel active, we may be splitting blocks, so force creation 6562 // of virtual registers for all non-dead arguments. 6563 if (FastISel) 6564 return A->use_empty(); 6565 6566 const BasicBlock *Entry = A->getParent()->begin(); 6567 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6568 UI != E; ++UI) { 6569 const User *U = *UI; 6570 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6571 return false; // Use not in entry block. 6572 } 6573 return true; 6574} 6575 6576void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6577 // If this is the entry block, emit arguments. 6578 const Function &F = *LLVMBB->getParent(); 6579 SelectionDAG &DAG = SDB->DAG; 6580 DebugLoc dl = SDB->getCurDebugLoc(); 6581 const DataLayout *TD = TLI.getDataLayout(); 6582 SmallVector<ISD::InputArg, 16> Ins; 6583 6584 // Check whether the function can return without sret-demotion. 6585 SmallVector<ISD::OutputArg, 4> Outs; 6586 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6587 Outs, TLI); 6588 6589 if (!FuncInfo->CanLowerReturn) { 6590 // Put in an sret pointer parameter before all the other parameters. 6591 SmallVector<EVT, 1> ValueVTs; 6592 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6593 6594 // NOTE: Assuming that a pointer will never break down to more than one VT 6595 // or one register. 6596 ISD::ArgFlagsTy Flags; 6597 Flags.setSRet(); 6598 MVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6599 ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0); 6600 Ins.push_back(RetArg); 6601 } 6602 6603 // Set up the incoming argument description vector. 6604 unsigned Idx = 1; 6605 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6606 I != E; ++I, ++Idx) { 6607 SmallVector<EVT, 4> ValueVTs; 6608 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6609 bool isArgValueUsed = !I->use_empty(); 6610 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6611 Value != NumValues; ++Value) { 6612 EVT VT = ValueVTs[Value]; 6613 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6614 ISD::ArgFlagsTy Flags; 6615 unsigned OriginalAlignment = 6616 TD->getABITypeAlignment(ArgTy); 6617 6618 if (F.getParamAttributes(Idx).hasAttribute(Attribute::ZExt)) 6619 Flags.setZExt(); 6620 if (F.getParamAttributes(Idx).hasAttribute(Attribute::SExt)) 6621 Flags.setSExt(); 6622 if (F.getParamAttributes(Idx).hasAttribute(Attribute::InReg)) 6623 Flags.setInReg(); 6624 if (F.getParamAttributes(Idx).hasAttribute(Attribute::StructRet)) 6625 Flags.setSRet(); 6626 if (F.getParamAttributes(Idx).hasAttribute(Attribute::ByVal)) { 6627 Flags.setByVal(); 6628 PointerType *Ty = cast<PointerType>(I->getType()); 6629 Type *ElementTy = Ty->getElementType(); 6630 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6631 // For ByVal, alignment should be passed from FE. BE will guess if 6632 // this info is not there but there are cases it cannot get right. 6633 unsigned FrameAlign; 6634 if (F.getParamAlignment(Idx)) 6635 FrameAlign = F.getParamAlignment(Idx); 6636 else 6637 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6638 Flags.setByValAlign(FrameAlign); 6639 } 6640 if (F.getParamAttributes(Idx).hasAttribute(Attribute::Nest)) 6641 Flags.setNest(); 6642 Flags.setOrigAlign(OriginalAlignment); 6643 6644 MVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6645 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6646 for (unsigned i = 0; i != NumRegs; ++i) { 6647 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed, 6648 Idx-1, i*RegisterVT.getStoreSize()); 6649 if (NumRegs > 1 && i == 0) 6650 MyFlags.Flags.setSplit(); 6651 // if it isn't first piece, alignment must be 1 6652 else if (i > 0) 6653 MyFlags.Flags.setOrigAlign(1); 6654 Ins.push_back(MyFlags); 6655 } 6656 } 6657 } 6658 6659 // Call the target to set up the argument values. 6660 SmallVector<SDValue, 8> InVals; 6661 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6662 F.isVarArg(), Ins, 6663 dl, DAG, InVals); 6664 6665 // Verify that the target's LowerFormalArguments behaved as expected. 6666 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6667 "LowerFormalArguments didn't return a valid chain!"); 6668 assert(InVals.size() == Ins.size() && 6669 "LowerFormalArguments didn't emit the correct number of values!"); 6670 DEBUG({ 6671 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6672 assert(InVals[i].getNode() && 6673 "LowerFormalArguments emitted a null value!"); 6674 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6675 "LowerFormalArguments emitted a value with the wrong type!"); 6676 } 6677 }); 6678 6679 // Update the DAG with the new chain value resulting from argument lowering. 6680 DAG.setRoot(NewRoot); 6681 6682 // Set up the argument values. 6683 unsigned i = 0; 6684 Idx = 1; 6685 if (!FuncInfo->CanLowerReturn) { 6686 // Create a virtual register for the sret pointer, and put in a copy 6687 // from the sret argument into it. 6688 SmallVector<EVT, 1> ValueVTs; 6689 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6690 MVT VT = ValueVTs[0].getSimpleVT(); 6691 MVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6692 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6693 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6694 RegVT, VT, NULL, AssertOp); 6695 6696 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6697 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6698 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6699 FuncInfo->DemoteRegister = SRetReg; 6700 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6701 SRetReg, ArgValue); 6702 DAG.setRoot(NewRoot); 6703 6704 // i indexes lowered arguments. Bump it past the hidden sret argument. 6705 // Idx indexes LLVM arguments. Don't touch it. 6706 ++i; 6707 } 6708 6709 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6710 ++I, ++Idx) { 6711 SmallVector<SDValue, 4> ArgValues; 6712 SmallVector<EVT, 4> ValueVTs; 6713 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6714 unsigned NumValues = ValueVTs.size(); 6715 6716 // If this argument is unused then remember its value. It is used to generate 6717 // debugging information. 6718 if (I->use_empty() && NumValues) 6719 SDB->setUnusedArgValue(I, InVals[i]); 6720 6721 for (unsigned Val = 0; Val != NumValues; ++Val) { 6722 EVT VT = ValueVTs[Val]; 6723 MVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6724 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6725 6726 if (!I->use_empty()) { 6727 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6728 if (F.getParamAttributes(Idx).hasAttribute(Attribute::SExt)) 6729 AssertOp = ISD::AssertSext; 6730 else if (F.getParamAttributes(Idx).hasAttribute(Attribute::ZExt)) 6731 AssertOp = ISD::AssertZext; 6732 6733 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6734 NumParts, PartVT, VT, 6735 NULL, AssertOp)); 6736 } 6737 6738 i += NumParts; 6739 } 6740 6741 // We don't need to do anything else for unused arguments. 6742 if (ArgValues.empty()) 6743 continue; 6744 6745 // Note down frame index. 6746 if (FrameIndexSDNode *FI = 6747 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6748 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6749 6750 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6751 SDB->getCurDebugLoc()); 6752 6753 SDB->setValue(I, Res); 6754 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6755 if (LoadSDNode *LNode = 6756 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6757 if (FrameIndexSDNode *FI = 6758 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6759 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6760 } 6761 6762 // If this argument is live outside of the entry block, insert a copy from 6763 // wherever we got it to the vreg that other BB's will reference it as. 6764 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6765 // If we can, though, try to skip creating an unnecessary vreg. 6766 // FIXME: This isn't very clean... it would be nice to make this more 6767 // general. It's also subtly incompatible with the hacks FastISel 6768 // uses with vregs. 6769 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6770 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6771 FuncInfo->ValueMap[I] = Reg; 6772 continue; 6773 } 6774 } 6775 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 6776 FuncInfo->InitializeRegForValue(I); 6777 SDB->CopyToExportRegsIfNeeded(I); 6778 } 6779 } 6780 6781 assert(i == InVals.size() && "Argument register count mismatch!"); 6782 6783 // Finally, if the target has anything special to do, allow it to do so. 6784 // FIXME: this should insert code into the DAG! 6785 EmitFunctionEntryCode(); 6786} 6787 6788/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6789/// ensure constants are generated when needed. Remember the virtual registers 6790/// that need to be added to the Machine PHI nodes as input. We cannot just 6791/// directly add them, because expansion might result in multiple MBB's for one 6792/// BB. As such, the start of the BB might correspond to a different MBB than 6793/// the end. 6794/// 6795void 6796SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6797 const TerminatorInst *TI = LLVMBB->getTerminator(); 6798 6799 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6800 6801 // Check successor nodes' PHI nodes that expect a constant to be available 6802 // from this block. 6803 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6804 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6805 if (!isa<PHINode>(SuccBB->begin())) continue; 6806 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6807 6808 // If this terminator has multiple identical successors (common for 6809 // switches), only handle each succ once. 6810 if (!SuccsHandled.insert(SuccMBB)) continue; 6811 6812 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6813 6814 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6815 // nodes and Machine PHI nodes, but the incoming operands have not been 6816 // emitted yet. 6817 for (BasicBlock::const_iterator I = SuccBB->begin(); 6818 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6819 // Ignore dead phi's. 6820 if (PN->use_empty()) continue; 6821 6822 // Skip empty types 6823 if (PN->getType()->isEmptyTy()) 6824 continue; 6825 6826 unsigned Reg; 6827 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6828 6829 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6830 unsigned &RegOut = ConstantsOut[C]; 6831 if (RegOut == 0) { 6832 RegOut = FuncInfo.CreateRegs(C->getType()); 6833 CopyValueToVirtualRegister(C, RegOut); 6834 } 6835 Reg = RegOut; 6836 } else { 6837 DenseMap<const Value *, unsigned>::iterator I = 6838 FuncInfo.ValueMap.find(PHIOp); 6839 if (I != FuncInfo.ValueMap.end()) 6840 Reg = I->second; 6841 else { 6842 assert(isa<AllocaInst>(PHIOp) && 6843 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6844 "Didn't codegen value into a register!??"); 6845 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6846 CopyValueToVirtualRegister(PHIOp, Reg); 6847 } 6848 } 6849 6850 // Remember that this register needs to added to the machine PHI node as 6851 // the input for this MBB. 6852 SmallVector<EVT, 4> ValueVTs; 6853 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6854 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6855 EVT VT = ValueVTs[vti]; 6856 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6857 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6858 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6859 Reg += NumRegisters; 6860 } 6861 } 6862 } 6863 ConstantsOut.clear(); 6864} 6865