SelectionDAGBuilder.cpp revision ebe8173941238cfbabadb1c63bca7fb7dcf2adbe
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/PseudoSourceValue.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Analysis/DebugInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameLowering.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/CommandLine.h" 55#include "llvm/Support/Debug.h" 56#include "llvm/Support/ErrorHandling.h" 57#include "llvm/Support/MathExtras.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62/// LimitFloatPrecision - Generate low-precision inline sequences for 63/// some float libcalls (6, 8 or 12 bits). 64static unsigned LimitFloatPrecision; 65 66static cl::opt<unsigned, true> 67LimitFPPrecision("limit-float-precision", 68 cl::desc("Generate low-precision inline sequences " 69 "for some float libcalls"), 70 cl::location(LimitFloatPrecision), 71 cl::init(0)); 72 73// Limit the width of DAG chains. This is important in general to prevent 74// prevent DAG-based analysis from blowing up. For example, alias analysis and 75// load clustering may not complete in reasonable time. It is difficult to 76// recognize and avoid this situation within each individual analysis, and 77// future analyses are likely to have the same behavior. Limiting DAG width is 78// the safe approach, and will be especially important with global DAGs. 79// 80// MaxParallelChains default is arbitrarily high to avoid affecting 81// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 82// sequence over this should have been converted to llvm.memcpy by the 83// frontend. It easy to induce this behavior with .ll code such as: 84// %buffer = alloca [4096 x i8] 85// %data = load [4096 x i8]* %argPtr 86// store [4096 x i8] %data, [4096 x i8]* %buffer 87static const unsigned MaxParallelChains = 64; 88 89static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 90 const SDValue *Parts, unsigned NumParts, 91 EVT PartVT, EVT ValueVT); 92 93/// getCopyFromParts - Create a value that contains the specified legal parts 94/// combined into the value they represent. If the parts combine to a type 95/// larger then ValueVT then AssertOp can be used to specify whether the extra 96/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 97/// (ISD::AssertSext). 98static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 99 const SDValue *Parts, 100 unsigned NumParts, EVT PartVT, EVT ValueVT, 101 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 102 if (ValueVT.isVector()) 103 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 104 105 assert(NumParts > 0 && "No parts to assemble!"); 106 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 107 SDValue Val = Parts[0]; 108 109 if (NumParts > 1) { 110 // Assemble the value from multiple parts. 111 if (ValueVT.isInteger()) { 112 unsigned PartBits = PartVT.getSizeInBits(); 113 unsigned ValueBits = ValueVT.getSizeInBits(); 114 115 // Assemble the power of 2 part. 116 unsigned RoundParts = NumParts & (NumParts - 1) ? 117 1 << Log2_32(NumParts) : NumParts; 118 unsigned RoundBits = PartBits * RoundParts; 119 EVT RoundVT = RoundBits == ValueBits ? 120 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 121 SDValue Lo, Hi; 122 123 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 124 125 if (RoundParts > 2) { 126 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 127 PartVT, HalfVT); 128 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 129 RoundParts / 2, PartVT, HalfVT); 130 } else { 131 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 132 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 133 } 134 135 if (TLI.isBigEndian()) 136 std::swap(Lo, Hi); 137 138 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 139 140 if (RoundParts < NumParts) { 141 // Assemble the trailing non-power-of-2 part. 142 unsigned OddParts = NumParts - RoundParts; 143 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 144 Hi = getCopyFromParts(DAG, DL, 145 Parts + RoundParts, OddParts, PartVT, OddVT); 146 147 // Combine the round and odd parts. 148 Lo = Val; 149 if (TLI.isBigEndian()) 150 std::swap(Lo, Hi); 151 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 152 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 153 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 154 DAG.getConstant(Lo.getValueType().getSizeInBits(), 155 TLI.getPointerTy())); 156 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 157 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 158 } 159 } else if (PartVT.isFloatingPoint()) { 160 // FP split into multiple FP parts (for ppcf128) 161 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 162 "Unexpected split"); 163 SDValue Lo, Hi; 164 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 165 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 166 if (TLI.isBigEndian()) 167 std::swap(Lo, Hi); 168 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 169 } else { 170 // FP split into integer parts (soft fp) 171 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 172 !PartVT.isVector() && "Unexpected split"); 173 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 174 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 175 } 176 } 177 178 // There is now one part, held in Val. Correct it to match ValueVT. 179 PartVT = Val.getValueType(); 180 181 if (PartVT == ValueVT) 182 return Val; 183 184 if (PartVT.isInteger() && ValueVT.isInteger()) { 185 if (ValueVT.bitsLT(PartVT)) { 186 // For a truncate, see if we have any information to 187 // indicate whether the truncated bits will always be 188 // zero or sign-extension. 189 if (AssertOp != ISD::DELETED_NODE) 190 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 191 DAG.getValueType(ValueVT)); 192 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 193 } 194 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 195 } 196 197 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 198 // FP_ROUND's are always exact here. 199 if (ValueVT.bitsLT(Val.getValueType())) 200 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 201 DAG.getIntPtrConstant(1)); 202 203 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 204 } 205 206 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 207 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 208 209 llvm_unreachable("Unknown mismatch!"); 210 return SDValue(); 211} 212 213/// getCopyFromParts - Create a value that contains the specified legal parts 214/// combined into the value they represent. If the parts combine to a type 215/// larger then ValueVT then AssertOp can be used to specify whether the extra 216/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 217/// (ISD::AssertSext). 218static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 219 const SDValue *Parts, unsigned NumParts, 220 EVT PartVT, EVT ValueVT) { 221 assert(ValueVT.isVector() && "Not a vector value"); 222 assert(NumParts > 0 && "No parts to assemble!"); 223 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 224 SDValue Val = Parts[0]; 225 226 // Handle a multi-element vector. 227 if (NumParts > 1) { 228 EVT IntermediateVT, RegisterVT; 229 unsigned NumIntermediates; 230 unsigned NumRegs = 231 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 232 NumIntermediates, RegisterVT); 233 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 234 NumParts = NumRegs; // Silence a compiler warning. 235 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 236 assert(RegisterVT == Parts[0].getValueType() && 237 "Part type doesn't match part!"); 238 239 // Assemble the parts into intermediate operands. 240 SmallVector<SDValue, 8> Ops(NumIntermediates); 241 if (NumIntermediates == NumParts) { 242 // If the register was not expanded, truncate or copy the value, 243 // as appropriate. 244 for (unsigned i = 0; i != NumParts; ++i) 245 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 246 PartVT, IntermediateVT); 247 } else if (NumParts > 0) { 248 // If the intermediate type was expanded, build the intermediate 249 // operands from the parts. 250 assert(NumParts % NumIntermediates == 0 && 251 "Must expand into a divisible number of parts!"); 252 unsigned Factor = NumParts / NumIntermediates; 253 for (unsigned i = 0; i != NumIntermediates; ++i) 254 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 255 PartVT, IntermediateVT); 256 } 257 258 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 259 // intermediate operands. 260 Val = DAG.getNode(IntermediateVT.isVector() ? 261 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 262 ValueVT, &Ops[0], NumIntermediates); 263 } 264 265 // There is now one part, held in Val. Correct it to match ValueVT. 266 PartVT = Val.getValueType(); 267 268 if (PartVT == ValueVT) 269 return Val; 270 271 if (PartVT.isVector()) { 272 // If the element type of the source/dest vectors are the same, but the 273 // parts vector has more elements than the value vector, then we have a 274 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 275 // elements we want. 276 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 277 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 278 "Cannot narrow, it would be a lossy transformation"); 279 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 280 DAG.getIntPtrConstant(0)); 281 } 282 283 // Vector/Vector bitcast. 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 } 286 287 assert(ValueVT.getVectorElementType() == PartVT && 288 ValueVT.getVectorNumElements() == 1 && 289 "Only trivial scalar-to-vector conversions should get here!"); 290 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 291} 292 293 294 295 296static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 297 SDValue Val, SDValue *Parts, unsigned NumParts, 298 EVT PartVT); 299 300/// getCopyToParts - Create a series of nodes that contain the specified value 301/// split into legal parts. If the parts contain more bits than Val, then, for 302/// integers, ExtendKind can be used to specify how to generate the extra bits. 303static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 304 SDValue Val, SDValue *Parts, unsigned NumParts, 305 EVT PartVT, 306 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 307 EVT ValueVT = Val.getValueType(); 308 309 // Handle the vector case separately. 310 if (ValueVT.isVector()) 311 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 312 313 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 314 unsigned PartBits = PartVT.getSizeInBits(); 315 unsigned OrigNumParts = NumParts; 316 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 317 318 if (NumParts == 0) 319 return; 320 321 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 322 if (PartVT == ValueVT) { 323 assert(NumParts == 1 && "No-op copy with multiple parts!"); 324 Parts[0] = Val; 325 return; 326 } 327 328 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 329 // If the parts cover more bits than the value has, promote the value. 330 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 331 assert(NumParts == 1 && "Do not know what to promote to!"); 332 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 333 } else { 334 assert(PartVT.isInteger() && ValueVT.isInteger() && 335 "Unknown mismatch!"); 336 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 337 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 338 } 339 } else if (PartBits == ValueVT.getSizeInBits()) { 340 // Different types of the same size. 341 assert(NumParts == 1 && PartVT != ValueVT); 342 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 343 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 344 // If the parts cover less bits than value has, truncate the value. 345 assert(PartVT.isInteger() && ValueVT.isInteger() && 346 "Unknown mismatch!"); 347 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 348 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 349 } 350 351 // The value may have changed - recompute ValueVT. 352 ValueVT = Val.getValueType(); 353 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 354 "Failed to tile the value with PartVT!"); 355 356 if (NumParts == 1) { 357 assert(PartVT == ValueVT && "Type conversion failed!"); 358 Parts[0] = Val; 359 return; 360 } 361 362 // Expand the value into multiple parts. 363 if (NumParts & (NumParts - 1)) { 364 // The number of parts is not a power of 2. Split off and copy the tail. 365 assert(PartVT.isInteger() && ValueVT.isInteger() && 366 "Do not know what to expand to!"); 367 unsigned RoundParts = 1 << Log2_32(NumParts); 368 unsigned RoundBits = RoundParts * PartBits; 369 unsigned OddParts = NumParts - RoundParts; 370 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 371 DAG.getIntPtrConstant(RoundBits)); 372 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 373 374 if (TLI.isBigEndian()) 375 // The odd parts were reversed by getCopyToParts - unreverse them. 376 std::reverse(Parts + RoundParts, Parts + NumParts); 377 378 NumParts = RoundParts; 379 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 380 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 381 } 382 383 // The number of parts is a power of 2. Repeatedly bisect the value using 384 // EXTRACT_ELEMENT. 385 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 386 EVT::getIntegerVT(*DAG.getContext(), 387 ValueVT.getSizeInBits()), 388 Val); 389 390 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 391 for (unsigned i = 0; i < NumParts; i += StepSize) { 392 unsigned ThisBits = StepSize * PartBits / 2; 393 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 394 SDValue &Part0 = Parts[i]; 395 SDValue &Part1 = Parts[i+StepSize/2]; 396 397 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 398 ThisVT, Part0, DAG.getIntPtrConstant(1)); 399 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 400 ThisVT, Part0, DAG.getIntPtrConstant(0)); 401 402 if (ThisBits == PartBits && ThisVT != PartVT) { 403 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 404 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 405 } 406 } 407 } 408 409 if (TLI.isBigEndian()) 410 std::reverse(Parts, Parts + OrigNumParts); 411} 412 413 414/// getCopyToPartsVector - Create a series of nodes that contain the specified 415/// value split into legal parts. 416static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 417 SDValue Val, SDValue *Parts, unsigned NumParts, 418 EVT PartVT) { 419 EVT ValueVT = Val.getValueType(); 420 assert(ValueVT.isVector() && "Not a vector"); 421 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 422 423 if (NumParts == 1) { 424 if (PartVT == ValueVT) { 425 // Nothing to do. 426 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 427 // Bitconvert vector->vector case. 428 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 429 } else if (PartVT.isVector() && 430 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&& 431 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 432 EVT ElementVT = PartVT.getVectorElementType(); 433 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 434 // undef elements. 435 SmallVector<SDValue, 16> Ops; 436 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 437 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 438 ElementVT, Val, DAG.getIntPtrConstant(i))); 439 440 for (unsigned i = ValueVT.getVectorNumElements(), 441 e = PartVT.getVectorNumElements(); i != e; ++i) 442 Ops.push_back(DAG.getUNDEF(ElementVT)); 443 444 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 445 446 // FIXME: Use CONCAT for 2x -> 4x. 447 448 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 449 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 450 } else { 451 // Vector -> scalar conversion. 452 assert(ValueVT.getVectorElementType() == PartVT && 453 ValueVT.getVectorNumElements() == 1 && 454 "Only trivial vector-to-scalar conversions should get here!"); 455 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 456 PartVT, Val, DAG.getIntPtrConstant(0)); 457 } 458 459 Parts[0] = Val; 460 return; 461 } 462 463 // Handle a multi-element vector. 464 EVT IntermediateVT, RegisterVT; 465 unsigned NumIntermediates; 466 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 467 IntermediateVT, 468 NumIntermediates, RegisterVT); 469 unsigned NumElements = ValueVT.getVectorNumElements(); 470 471 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 472 NumParts = NumRegs; // Silence a compiler warning. 473 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 474 475 // Split the vector into intermediate operands. 476 SmallVector<SDValue, 8> Ops(NumIntermediates); 477 for (unsigned i = 0; i != NumIntermediates; ++i) { 478 if (IntermediateVT.isVector()) 479 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 480 IntermediateVT, Val, 481 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 482 else 483 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 484 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 485 } 486 487 // Split the intermediate operands into legal parts. 488 if (NumParts == NumIntermediates) { 489 // If the register was not expanded, promote or copy the value, 490 // as appropriate. 491 for (unsigned i = 0; i != NumParts; ++i) 492 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 493 } else if (NumParts > 0) { 494 // If the intermediate type was expanded, split each the value into 495 // legal parts. 496 assert(NumParts % NumIntermediates == 0 && 497 "Must expand into a divisible number of parts!"); 498 unsigned Factor = NumParts / NumIntermediates; 499 for (unsigned i = 0; i != NumIntermediates; ++i) 500 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 501 } 502} 503 504 505 506 507namespace { 508 /// RegsForValue - This struct represents the registers (physical or virtual) 509 /// that a particular set of values is assigned, and the type information 510 /// about the value. The most common situation is to represent one value at a 511 /// time, but struct or array values are handled element-wise as multiple 512 /// values. The splitting of aggregates is performed recursively, so that we 513 /// never have aggregate-typed registers. The values at this point do not 514 /// necessarily have legal types, so each value may require one or more 515 /// registers of some legal type. 516 /// 517 struct RegsForValue { 518 /// ValueVTs - The value types of the values, which may not be legal, and 519 /// may need be promoted or synthesized from one or more registers. 520 /// 521 SmallVector<EVT, 4> ValueVTs; 522 523 /// RegVTs - The value types of the registers. This is the same size as 524 /// ValueVTs and it records, for each value, what the type of the assigned 525 /// register or registers are. (Individual values are never synthesized 526 /// from more than one type of register.) 527 /// 528 /// With virtual registers, the contents of RegVTs is redundant with TLI's 529 /// getRegisterType member function, however when with physical registers 530 /// it is necessary to have a separate record of the types. 531 /// 532 SmallVector<EVT, 4> RegVTs; 533 534 /// Regs - This list holds the registers assigned to the values. 535 /// Each legal or promoted value requires one register, and each 536 /// expanded value requires multiple registers. 537 /// 538 SmallVector<unsigned, 4> Regs; 539 540 RegsForValue() {} 541 542 RegsForValue(const SmallVector<unsigned, 4> ®s, 543 EVT regvt, EVT valuevt) 544 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 545 546 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 547 unsigned Reg, const Type *Ty) { 548 ComputeValueVTs(tli, Ty, ValueVTs); 549 550 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 551 EVT ValueVT = ValueVTs[Value]; 552 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 553 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 554 for (unsigned i = 0; i != NumRegs; ++i) 555 Regs.push_back(Reg + i); 556 RegVTs.push_back(RegisterVT); 557 Reg += NumRegs; 558 } 559 } 560 561 /// areValueTypesLegal - Return true if types of all the values are legal. 562 bool areValueTypesLegal(const TargetLowering &TLI) { 563 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 564 EVT RegisterVT = RegVTs[Value]; 565 if (!TLI.isTypeLegal(RegisterVT)) 566 return false; 567 } 568 return true; 569 } 570 571 /// append - Add the specified values to this one. 572 void append(const RegsForValue &RHS) { 573 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 574 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 575 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 576 } 577 578 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 579 /// this value and returns the result as a ValueVTs value. This uses 580 /// Chain/Flag as the input and updates them for the output Chain/Flag. 581 /// If the Flag pointer is NULL, no flag is used. 582 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 583 DebugLoc dl, 584 SDValue &Chain, SDValue *Flag) const; 585 586 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 587 /// specified value into the registers specified by this object. This uses 588 /// Chain/Flag as the input and updates them for the output Chain/Flag. 589 /// If the Flag pointer is NULL, no flag is used. 590 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 591 SDValue &Chain, SDValue *Flag) const; 592 593 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 594 /// operand list. This adds the code marker, matching input operand index 595 /// (if applicable), and includes the number of values added into it. 596 void AddInlineAsmOperands(unsigned Kind, 597 bool HasMatching, unsigned MatchingIdx, 598 SelectionDAG &DAG, 599 std::vector<SDValue> &Ops) const; 600 }; 601} 602 603/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 604/// this value and returns the result as a ValueVT value. This uses 605/// Chain/Flag as the input and updates them for the output Chain/Flag. 606/// If the Flag pointer is NULL, no flag is used. 607SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 608 FunctionLoweringInfo &FuncInfo, 609 DebugLoc dl, 610 SDValue &Chain, SDValue *Flag) const { 611 // A Value with type {} or [0 x %t] needs no registers. 612 if (ValueVTs.empty()) 613 return SDValue(); 614 615 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 616 617 // Assemble the legal parts into the final values. 618 SmallVector<SDValue, 4> Values(ValueVTs.size()); 619 SmallVector<SDValue, 8> Parts; 620 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 621 // Copy the legal parts from the registers. 622 EVT ValueVT = ValueVTs[Value]; 623 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 624 EVT RegisterVT = RegVTs[Value]; 625 626 Parts.resize(NumRegs); 627 for (unsigned i = 0; i != NumRegs; ++i) { 628 SDValue P; 629 if (Flag == 0) { 630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 631 } else { 632 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 633 *Flag = P.getValue(2); 634 } 635 636 Chain = P.getValue(1); 637 Parts[i] = P; 638 639 // If the source register was virtual and if we know something about it, 640 // add an assert node. 641 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 642 !RegisterVT.isInteger() || RegisterVT.isVector()) 643 continue; 644 645 const FunctionLoweringInfo::LiveOutInfo *LOI = 646 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 647 if (!LOI) 648 continue; 649 650 unsigned RegSize = RegisterVT.getSizeInBits(); 651 unsigned NumSignBits = LOI->NumSignBits; 652 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 653 654 // FIXME: We capture more information than the dag can represent. For 655 // now, just use the tightest assertzext/assertsext possible. 656 bool isSExt = true; 657 EVT FromVT(MVT::Other); 658 if (NumSignBits == RegSize) 659 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 660 else if (NumZeroBits >= RegSize-1) 661 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 662 else if (NumSignBits > RegSize-8) 663 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 664 else if (NumZeroBits >= RegSize-8) 665 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 666 else if (NumSignBits > RegSize-16) 667 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 668 else if (NumZeroBits >= RegSize-16) 669 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 670 else if (NumSignBits > RegSize-32) 671 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 672 else if (NumZeroBits >= RegSize-32) 673 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 674 else 675 continue; 676 677 // Add an assertion node. 678 assert(FromVT != MVT::Other); 679 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 680 RegisterVT, P, DAG.getValueType(FromVT)); 681 } 682 683 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 684 NumRegs, RegisterVT, ValueVT); 685 Part += NumRegs; 686 Parts.clear(); 687 } 688 689 return DAG.getNode(ISD::MERGE_VALUES, dl, 690 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 691 &Values[0], ValueVTs.size()); 692} 693 694/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 695/// specified value into the registers specified by this object. This uses 696/// Chain/Flag as the input and updates them for the output Chain/Flag. 697/// If the Flag pointer is NULL, no flag is used. 698void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 699 SDValue &Chain, SDValue *Flag) const { 700 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 701 702 // Get the list of the values's legal parts. 703 unsigned NumRegs = Regs.size(); 704 SmallVector<SDValue, 8> Parts(NumRegs); 705 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 706 EVT ValueVT = ValueVTs[Value]; 707 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 708 EVT RegisterVT = RegVTs[Value]; 709 710 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 711 &Parts[Part], NumParts, RegisterVT); 712 Part += NumParts; 713 } 714 715 // Copy the parts into the registers. 716 SmallVector<SDValue, 8> Chains(NumRegs); 717 for (unsigned i = 0; i != NumRegs; ++i) { 718 SDValue Part; 719 if (Flag == 0) { 720 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 721 } else { 722 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 723 *Flag = Part.getValue(1); 724 } 725 726 Chains[i] = Part.getValue(0); 727 } 728 729 if (NumRegs == 1 || Flag) 730 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 731 // flagged to it. That is the CopyToReg nodes and the user are considered 732 // a single scheduling unit. If we create a TokenFactor and return it as 733 // chain, then the TokenFactor is both a predecessor (operand) of the 734 // user as well as a successor (the TF operands are flagged to the user). 735 // c1, f1 = CopyToReg 736 // c2, f2 = CopyToReg 737 // c3 = TokenFactor c1, c2 738 // ... 739 // = op c3, ..., f2 740 Chain = Chains[NumRegs-1]; 741 else 742 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 743} 744 745/// AddInlineAsmOperands - Add this value to the specified inlineasm node 746/// operand list. This adds the code marker and includes the number of 747/// values added into it. 748void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 749 unsigned MatchingIdx, 750 SelectionDAG &DAG, 751 std::vector<SDValue> &Ops) const { 752 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 753 754 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 755 if (HasMatching) 756 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 757 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 758 Ops.push_back(Res); 759 760 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 761 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 762 EVT RegisterVT = RegVTs[Value]; 763 for (unsigned i = 0; i != NumRegs; ++i) { 764 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 765 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 766 } 767 } 768} 769 770void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 771 AA = &aa; 772 GFI = gfi; 773 TD = DAG.getTarget().getTargetData(); 774} 775 776/// clear - Clear out the current SelectionDAG and the associated 777/// state and prepare this SelectionDAGBuilder object to be used 778/// for a new block. This doesn't clear out information about 779/// additional blocks that are needed to complete switch lowering 780/// or PHI node updating; that information is cleared out as it is 781/// consumed. 782void SelectionDAGBuilder::clear() { 783 NodeMap.clear(); 784 UnusedArgNodeMap.clear(); 785 PendingLoads.clear(); 786 PendingExports.clear(); 787 DanglingDebugInfoMap.clear(); 788 CurDebugLoc = DebugLoc(); 789 HasTailCall = false; 790} 791 792/// getRoot - Return the current virtual root of the Selection DAG, 793/// flushing any PendingLoad items. This must be done before emitting 794/// a store or any other node that may need to be ordered after any 795/// prior load instructions. 796/// 797SDValue SelectionDAGBuilder::getRoot() { 798 if (PendingLoads.empty()) 799 return DAG.getRoot(); 800 801 if (PendingLoads.size() == 1) { 802 SDValue Root = PendingLoads[0]; 803 DAG.setRoot(Root); 804 PendingLoads.clear(); 805 return Root; 806 } 807 808 // Otherwise, we have to make a token factor node. 809 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 810 &PendingLoads[0], PendingLoads.size()); 811 PendingLoads.clear(); 812 DAG.setRoot(Root); 813 return Root; 814} 815 816/// getControlRoot - Similar to getRoot, but instead of flushing all the 817/// PendingLoad items, flush all the PendingExports items. It is necessary 818/// to do this before emitting a terminator instruction. 819/// 820SDValue SelectionDAGBuilder::getControlRoot() { 821 SDValue Root = DAG.getRoot(); 822 823 if (PendingExports.empty()) 824 return Root; 825 826 // Turn all of the CopyToReg chains into one factored node. 827 if (Root.getOpcode() != ISD::EntryToken) { 828 unsigned i = 0, e = PendingExports.size(); 829 for (; i != e; ++i) { 830 assert(PendingExports[i].getNode()->getNumOperands() > 1); 831 if (PendingExports[i].getNode()->getOperand(0) == Root) 832 break; // Don't add the root if we already indirectly depend on it. 833 } 834 835 if (i == e) 836 PendingExports.push_back(Root); 837 } 838 839 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 840 &PendingExports[0], 841 PendingExports.size()); 842 PendingExports.clear(); 843 DAG.setRoot(Root); 844 return Root; 845} 846 847void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 848 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 849 DAG.AssignOrdering(Node, SDNodeOrder); 850 851 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 852 AssignOrderingToNode(Node->getOperand(I).getNode()); 853} 854 855void SelectionDAGBuilder::visit(const Instruction &I) { 856 // Set up outgoing PHI node register values before emitting the terminator. 857 if (isa<TerminatorInst>(&I)) 858 HandlePHINodesInSuccessorBlocks(I.getParent()); 859 860 CurDebugLoc = I.getDebugLoc(); 861 862 visit(I.getOpcode(), I); 863 864 if (!isa<TerminatorInst>(&I) && !HasTailCall) 865 CopyToExportRegsIfNeeded(&I); 866 867 CurDebugLoc = DebugLoc(); 868} 869 870void SelectionDAGBuilder::visitPHI(const PHINode &) { 871 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 872} 873 874void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 875 // Note: this doesn't use InstVisitor, because it has to work with 876 // ConstantExpr's in addition to instructions. 877 switch (Opcode) { 878 default: llvm_unreachable("Unknown instruction type encountered!"); 879 // Build the switch statement using the Instruction.def file. 880#define HANDLE_INST(NUM, OPCODE, CLASS) \ 881 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 882#include "llvm/Instruction.def" 883 } 884 885 // Assign the ordering to the freshly created DAG nodes. 886 if (NodeMap.count(&I)) { 887 ++SDNodeOrder; 888 AssignOrderingToNode(getValue(&I).getNode()); 889 } 890} 891 892// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 893// generate the debug data structures now that we've seen its definition. 894void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 895 SDValue Val) { 896 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 897 if (DDI.getDI()) { 898 const DbgValueInst *DI = DDI.getDI(); 899 DebugLoc dl = DDI.getdl(); 900 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 901 MDNode *Variable = DI->getVariable(); 902 uint64_t Offset = DI->getOffset(); 903 SDDbgValue *SDV; 904 if (Val.getNode()) { 905 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 906 SDV = DAG.getDbgValue(Variable, Val.getNode(), 907 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 908 DAG.AddDbgValue(SDV, Val.getNode(), false); 909 } 910 } else 911 DEBUG(dbgs() << "Dropping debug info for " << DI); 912 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 913 } 914} 915 916// getValue - Return an SDValue for the given Value. 917SDValue SelectionDAGBuilder::getValue(const Value *V) { 918 // If we already have an SDValue for this value, use it. It's important 919 // to do this first, so that we don't create a CopyFromReg if we already 920 // have a regular SDValue. 921 SDValue &N = NodeMap[V]; 922 if (N.getNode()) return N; 923 924 // If there's a virtual register allocated and initialized for this 925 // value, use it. 926 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 927 if (It != FuncInfo.ValueMap.end()) { 928 unsigned InReg = It->second; 929 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 930 SDValue Chain = DAG.getEntryNode(); 931 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 932 resolveDanglingDebugInfo(V, N); 933 return N; 934 } 935 936 // Otherwise create a new SDValue and remember it. 937 SDValue Val = getValueImpl(V); 938 NodeMap[V] = Val; 939 resolveDanglingDebugInfo(V, Val); 940 return Val; 941} 942 943/// getNonRegisterValue - Return an SDValue for the given Value, but 944/// don't look in FuncInfo.ValueMap for a virtual register. 945SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 946 // If we already have an SDValue for this value, use it. 947 SDValue &N = NodeMap[V]; 948 if (N.getNode()) return N; 949 950 // Otherwise create a new SDValue and remember it. 951 SDValue Val = getValueImpl(V); 952 NodeMap[V] = Val; 953 resolveDanglingDebugInfo(V, Val); 954 return Val; 955} 956 957/// getValueImpl - Helper function for getValue and getNonRegisterValue. 958/// Create an SDValue for the given value. 959SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 960 if (const Constant *C = dyn_cast<Constant>(V)) { 961 EVT VT = TLI.getValueType(V->getType(), true); 962 963 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 964 return DAG.getConstant(*CI, VT); 965 966 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 967 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 968 969 if (isa<ConstantPointerNull>(C)) 970 return DAG.getConstant(0, TLI.getPointerTy()); 971 972 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 973 return DAG.getConstantFP(*CFP, VT); 974 975 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 976 return DAG.getUNDEF(VT); 977 978 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 979 visit(CE->getOpcode(), *CE); 980 SDValue N1 = NodeMap[V]; 981 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 982 return N1; 983 } 984 985 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 986 SmallVector<SDValue, 4> Constants; 987 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 988 OI != OE; ++OI) { 989 SDNode *Val = getValue(*OI).getNode(); 990 // If the operand is an empty aggregate, there are no values. 991 if (!Val) continue; 992 // Add each leaf value from the operand to the Constants list 993 // to form a flattened list of all the values. 994 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 995 Constants.push_back(SDValue(Val, i)); 996 } 997 998 return DAG.getMergeValues(&Constants[0], Constants.size(), 999 getCurDebugLoc()); 1000 } 1001 1002 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1003 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1004 "Unknown struct or array constant!"); 1005 1006 SmallVector<EVT, 4> ValueVTs; 1007 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1008 unsigned NumElts = ValueVTs.size(); 1009 if (NumElts == 0) 1010 return SDValue(); // empty struct 1011 SmallVector<SDValue, 4> Constants(NumElts); 1012 for (unsigned i = 0; i != NumElts; ++i) { 1013 EVT EltVT = ValueVTs[i]; 1014 if (isa<UndefValue>(C)) 1015 Constants[i] = DAG.getUNDEF(EltVT); 1016 else if (EltVT.isFloatingPoint()) 1017 Constants[i] = DAG.getConstantFP(0, EltVT); 1018 else 1019 Constants[i] = DAG.getConstant(0, EltVT); 1020 } 1021 1022 return DAG.getMergeValues(&Constants[0], NumElts, 1023 getCurDebugLoc()); 1024 } 1025 1026 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1027 return DAG.getBlockAddress(BA, VT); 1028 1029 const VectorType *VecTy = cast<VectorType>(V->getType()); 1030 unsigned NumElements = VecTy->getNumElements(); 1031 1032 // Now that we know the number and type of the elements, get that number of 1033 // elements into the Ops array based on what kind of constant it is. 1034 SmallVector<SDValue, 16> Ops; 1035 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1036 for (unsigned i = 0; i != NumElements; ++i) 1037 Ops.push_back(getValue(CP->getOperand(i))); 1038 } else { 1039 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1040 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1041 1042 SDValue Op; 1043 if (EltVT.isFloatingPoint()) 1044 Op = DAG.getConstantFP(0, EltVT); 1045 else 1046 Op = DAG.getConstant(0, EltVT); 1047 Ops.assign(NumElements, Op); 1048 } 1049 1050 // Create a BUILD_VECTOR node. 1051 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1052 VT, &Ops[0], Ops.size()); 1053 } 1054 1055 // If this is a static alloca, generate it as the frameindex instead of 1056 // computation. 1057 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1058 DenseMap<const AllocaInst*, int>::iterator SI = 1059 FuncInfo.StaticAllocaMap.find(AI); 1060 if (SI != FuncInfo.StaticAllocaMap.end()) 1061 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1062 } 1063 1064 // If this is an instruction which fast-isel has deferred, select it now. 1065 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1066 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1067 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1068 SDValue Chain = DAG.getEntryNode(); 1069 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1070 } 1071 1072 llvm_unreachable("Can't get register for value!"); 1073 return SDValue(); 1074} 1075 1076void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1077 SDValue Chain = getControlRoot(); 1078 SmallVector<ISD::OutputArg, 8> Outs; 1079 SmallVector<SDValue, 8> OutVals; 1080 1081 if (!FuncInfo.CanLowerReturn) { 1082 unsigned DemoteReg = FuncInfo.DemoteRegister; 1083 const Function *F = I.getParent()->getParent(); 1084 1085 // Emit a store of the return value through the virtual register. 1086 // Leave Outs empty so that LowerReturn won't try to load return 1087 // registers the usual way. 1088 SmallVector<EVT, 1> PtrValueVTs; 1089 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1090 PtrValueVTs); 1091 1092 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1093 SDValue RetOp = getValue(I.getOperand(0)); 1094 1095 SmallVector<EVT, 4> ValueVTs; 1096 SmallVector<uint64_t, 4> Offsets; 1097 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1098 unsigned NumValues = ValueVTs.size(); 1099 1100 SmallVector<SDValue, 4> Chains(NumValues); 1101 for (unsigned i = 0; i != NumValues; ++i) { 1102 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1103 RetPtr.getValueType(), RetPtr, 1104 DAG.getIntPtrConstant(Offsets[i])); 1105 Chains[i] = 1106 DAG.getStore(Chain, getCurDebugLoc(), 1107 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1108 // FIXME: better loc info would be nice. 1109 Add, MachinePointerInfo(), false, false, 0); 1110 } 1111 1112 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1113 MVT::Other, &Chains[0], NumValues); 1114 } else if (I.getNumOperands() != 0) { 1115 SmallVector<EVT, 4> ValueVTs; 1116 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1117 unsigned NumValues = ValueVTs.size(); 1118 if (NumValues) { 1119 SDValue RetOp = getValue(I.getOperand(0)); 1120 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1121 EVT VT = ValueVTs[j]; 1122 1123 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1124 1125 const Function *F = I.getParent()->getParent(); 1126 if (F->paramHasAttr(0, Attribute::SExt)) 1127 ExtendKind = ISD::SIGN_EXTEND; 1128 else if (F->paramHasAttr(0, Attribute::ZExt)) 1129 ExtendKind = ISD::ZERO_EXTEND; 1130 1131 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1132 MVT ReturnMVT = TLI.getTypeForExtendedInteger(VT, ExtendKind); 1133 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), ReturnMVT); 1134 if (VT.bitsLT(MinVT)) 1135 VT = MinVT; 1136 } 1137 1138 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1139 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1140 SmallVector<SDValue, 4> Parts(NumParts); 1141 getCopyToParts(DAG, getCurDebugLoc(), 1142 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1143 &Parts[0], NumParts, PartVT, ExtendKind); 1144 1145 // 'inreg' on function refers to return value 1146 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1147 if (F->paramHasAttr(0, Attribute::InReg)) 1148 Flags.setInReg(); 1149 1150 // Propagate extension type if any 1151 if (ExtendKind == ISD::SIGN_EXTEND) 1152 Flags.setSExt(); 1153 else if (ExtendKind == ISD::ZERO_EXTEND) 1154 Flags.setZExt(); 1155 1156 for (unsigned i = 0; i < NumParts; ++i) { 1157 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1158 /*isfixed=*/true)); 1159 OutVals.push_back(Parts[i]); 1160 } 1161 } 1162 } 1163 } 1164 1165 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1166 CallingConv::ID CallConv = 1167 DAG.getMachineFunction().getFunction()->getCallingConv(); 1168 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1169 Outs, OutVals, getCurDebugLoc(), DAG); 1170 1171 // Verify that the target's LowerReturn behaved as expected. 1172 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1173 "LowerReturn didn't return a valid chain!"); 1174 1175 // Update the DAG with the new chain value resulting from return lowering. 1176 DAG.setRoot(Chain); 1177} 1178 1179/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1180/// created for it, emit nodes to copy the value into the virtual 1181/// registers. 1182void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1183 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1184 if (VMI != FuncInfo.ValueMap.end()) { 1185 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1186 CopyValueToVirtualRegister(V, VMI->second); 1187 } 1188} 1189 1190/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1191/// the current basic block, add it to ValueMap now so that we'll get a 1192/// CopyTo/FromReg. 1193void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1194 // No need to export constants. 1195 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1196 1197 // Already exported? 1198 if (FuncInfo.isExportedInst(V)) return; 1199 1200 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1201 CopyValueToVirtualRegister(V, Reg); 1202} 1203 1204bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1205 const BasicBlock *FromBB) { 1206 // The operands of the setcc have to be in this block. We don't know 1207 // how to export them from some other block. 1208 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1209 // Can export from current BB. 1210 if (VI->getParent() == FromBB) 1211 return true; 1212 1213 // Is already exported, noop. 1214 return FuncInfo.isExportedInst(V); 1215 } 1216 1217 // If this is an argument, we can export it if the BB is the entry block or 1218 // if it is already exported. 1219 if (isa<Argument>(V)) { 1220 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1221 return true; 1222 1223 // Otherwise, can only export this if it is already exported. 1224 return FuncInfo.isExportedInst(V); 1225 } 1226 1227 // Otherwise, constants can always be exported. 1228 return true; 1229} 1230 1231static bool InBlock(const Value *V, const BasicBlock *BB) { 1232 if (const Instruction *I = dyn_cast<Instruction>(V)) 1233 return I->getParent() == BB; 1234 return true; 1235} 1236 1237/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1238/// This function emits a branch and is used at the leaves of an OR or an 1239/// AND operator tree. 1240/// 1241void 1242SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1243 MachineBasicBlock *TBB, 1244 MachineBasicBlock *FBB, 1245 MachineBasicBlock *CurBB, 1246 MachineBasicBlock *SwitchBB) { 1247 const BasicBlock *BB = CurBB->getBasicBlock(); 1248 1249 // If the leaf of the tree is a comparison, merge the condition into 1250 // the caseblock. 1251 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1252 // The operands of the cmp have to be in this block. We don't know 1253 // how to export them from some other block. If this is the first block 1254 // of the sequence, no exporting is needed. 1255 if (CurBB == SwitchBB || 1256 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1257 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1258 ISD::CondCode Condition; 1259 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1260 Condition = getICmpCondCode(IC->getPredicate()); 1261 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1262 Condition = getFCmpCondCode(FC->getPredicate()); 1263 } else { 1264 Condition = ISD::SETEQ; // silence warning. 1265 llvm_unreachable("Unknown compare instruction"); 1266 } 1267 1268 CaseBlock CB(Condition, BOp->getOperand(0), 1269 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1270 SwitchCases.push_back(CB); 1271 return; 1272 } 1273 } 1274 1275 // Create a CaseBlock record representing this branch. 1276 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1277 NULL, TBB, FBB, CurBB); 1278 SwitchCases.push_back(CB); 1279} 1280 1281/// FindMergedConditions - If Cond is an expression like 1282void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1283 MachineBasicBlock *TBB, 1284 MachineBasicBlock *FBB, 1285 MachineBasicBlock *CurBB, 1286 MachineBasicBlock *SwitchBB, 1287 unsigned Opc) { 1288 // If this node is not part of the or/and tree, emit it as a branch. 1289 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1290 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1291 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1292 BOp->getParent() != CurBB->getBasicBlock() || 1293 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1294 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1295 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1296 return; 1297 } 1298 1299 // Create TmpBB after CurBB. 1300 MachineFunction::iterator BBI = CurBB; 1301 MachineFunction &MF = DAG.getMachineFunction(); 1302 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1303 CurBB->getParent()->insert(++BBI, TmpBB); 1304 1305 if (Opc == Instruction::Or) { 1306 // Codegen X | Y as: 1307 // jmp_if_X TBB 1308 // jmp TmpBB 1309 // TmpBB: 1310 // jmp_if_Y TBB 1311 // jmp FBB 1312 // 1313 1314 // Emit the LHS condition. 1315 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1316 1317 // Emit the RHS condition into TmpBB. 1318 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1319 } else { 1320 assert(Opc == Instruction::And && "Unknown merge op!"); 1321 // Codegen X & Y as: 1322 // jmp_if_X TmpBB 1323 // jmp FBB 1324 // TmpBB: 1325 // jmp_if_Y TBB 1326 // jmp FBB 1327 // 1328 // This requires creation of TmpBB after CurBB. 1329 1330 // Emit the LHS condition. 1331 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1332 1333 // Emit the RHS condition into TmpBB. 1334 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1335 } 1336} 1337 1338/// If the set of cases should be emitted as a series of branches, return true. 1339/// If we should emit this as a bunch of and/or'd together conditions, return 1340/// false. 1341bool 1342SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1343 if (Cases.size() != 2) return true; 1344 1345 // If this is two comparisons of the same values or'd or and'd together, they 1346 // will get folded into a single comparison, so don't emit two blocks. 1347 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1348 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1349 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1350 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1351 return false; 1352 } 1353 1354 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1355 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1356 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1357 Cases[0].CC == Cases[1].CC && 1358 isa<Constant>(Cases[0].CmpRHS) && 1359 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1360 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1361 return false; 1362 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1363 return false; 1364 } 1365 1366 return true; 1367} 1368 1369void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1370 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1371 1372 // Update machine-CFG edges. 1373 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1374 1375 // Figure out which block is immediately after the current one. 1376 MachineBasicBlock *NextBlock = 0; 1377 MachineFunction::iterator BBI = BrMBB; 1378 if (++BBI != FuncInfo.MF->end()) 1379 NextBlock = BBI; 1380 1381 if (I.isUnconditional()) { 1382 // Update machine-CFG edges. 1383 BrMBB->addSuccessor(Succ0MBB); 1384 1385 // If this is not a fall-through branch, emit the branch. 1386 if (Succ0MBB != NextBlock) 1387 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1388 MVT::Other, getControlRoot(), 1389 DAG.getBasicBlock(Succ0MBB))); 1390 1391 return; 1392 } 1393 1394 // If this condition is one of the special cases we handle, do special stuff 1395 // now. 1396 const Value *CondVal = I.getCondition(); 1397 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1398 1399 // If this is a series of conditions that are or'd or and'd together, emit 1400 // this as a sequence of branches instead of setcc's with and/or operations. 1401 // As long as jumps are not expensive, this should improve performance. 1402 // For example, instead of something like: 1403 // cmp A, B 1404 // C = seteq 1405 // cmp D, E 1406 // F = setle 1407 // or C, F 1408 // jnz foo 1409 // Emit: 1410 // cmp A, B 1411 // je foo 1412 // cmp D, E 1413 // jle foo 1414 // 1415 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1416 if (!TLI.isJumpExpensive() && 1417 BOp->hasOneUse() && 1418 (BOp->getOpcode() == Instruction::And || 1419 BOp->getOpcode() == Instruction::Or)) { 1420 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1421 BOp->getOpcode()); 1422 // If the compares in later blocks need to use values not currently 1423 // exported from this block, export them now. This block should always 1424 // be the first entry. 1425 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1426 1427 // Allow some cases to be rejected. 1428 if (ShouldEmitAsBranches(SwitchCases)) { 1429 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1430 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1431 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1432 } 1433 1434 // Emit the branch for this block. 1435 visitSwitchCase(SwitchCases[0], BrMBB); 1436 SwitchCases.erase(SwitchCases.begin()); 1437 return; 1438 } 1439 1440 // Okay, we decided not to do this, remove any inserted MBB's and clear 1441 // SwitchCases. 1442 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1443 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1444 1445 SwitchCases.clear(); 1446 } 1447 } 1448 1449 // Create a CaseBlock record representing this branch. 1450 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1451 NULL, Succ0MBB, Succ1MBB, BrMBB); 1452 1453 // Use visitSwitchCase to actually insert the fast branch sequence for this 1454 // cond branch. 1455 visitSwitchCase(CB, BrMBB); 1456} 1457 1458/// visitSwitchCase - Emits the necessary code to represent a single node in 1459/// the binary search tree resulting from lowering a switch instruction. 1460void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1461 MachineBasicBlock *SwitchBB) { 1462 SDValue Cond; 1463 SDValue CondLHS = getValue(CB.CmpLHS); 1464 DebugLoc dl = getCurDebugLoc(); 1465 1466 // Build the setcc now. 1467 if (CB.CmpMHS == NULL) { 1468 // Fold "(X == true)" to X and "(X == false)" to !X to 1469 // handle common cases produced by branch lowering. 1470 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1471 CB.CC == ISD::SETEQ) 1472 Cond = CondLHS; 1473 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1474 CB.CC == ISD::SETEQ) { 1475 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1476 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1477 } else 1478 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1479 } else { 1480 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1481 1482 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1483 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1484 1485 SDValue CmpOp = getValue(CB.CmpMHS); 1486 EVT VT = CmpOp.getValueType(); 1487 1488 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1489 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1490 ISD::SETLE); 1491 } else { 1492 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1493 VT, CmpOp, DAG.getConstant(Low, VT)); 1494 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1495 DAG.getConstant(High-Low, VT), ISD::SETULE); 1496 } 1497 } 1498 1499 // Update successor info 1500 SwitchBB->addSuccessor(CB.TrueBB); 1501 SwitchBB->addSuccessor(CB.FalseBB); 1502 1503 // Set NextBlock to be the MBB immediately after the current one, if any. 1504 // This is used to avoid emitting unnecessary branches to the next block. 1505 MachineBasicBlock *NextBlock = 0; 1506 MachineFunction::iterator BBI = SwitchBB; 1507 if (++BBI != FuncInfo.MF->end()) 1508 NextBlock = BBI; 1509 1510 // If the lhs block is the next block, invert the condition so that we can 1511 // fall through to the lhs instead of the rhs block. 1512 if (CB.TrueBB == NextBlock) { 1513 std::swap(CB.TrueBB, CB.FalseBB); 1514 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1515 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1516 } 1517 1518 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1519 MVT::Other, getControlRoot(), Cond, 1520 DAG.getBasicBlock(CB.TrueBB)); 1521 1522 // Insert the false branch. Do this even if it's a fall through branch, 1523 // this makes it easier to do DAG optimizations which require inverting 1524 // the branch condition. 1525 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1526 DAG.getBasicBlock(CB.FalseBB)); 1527 1528 DAG.setRoot(BrCond); 1529} 1530 1531/// visitJumpTable - Emit JumpTable node in the current MBB 1532void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1533 // Emit the code for the jump table 1534 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1535 EVT PTy = TLI.getPointerTy(); 1536 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1537 JT.Reg, PTy); 1538 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1539 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1540 MVT::Other, Index.getValue(1), 1541 Table, Index); 1542 DAG.setRoot(BrJumpTable); 1543} 1544 1545/// visitJumpTableHeader - This function emits necessary code to produce index 1546/// in the JumpTable from switch case. 1547void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1548 JumpTableHeader &JTH, 1549 MachineBasicBlock *SwitchBB) { 1550 // Subtract the lowest switch case value from the value being switched on and 1551 // conditional branch to default mbb if the result is greater than the 1552 // difference between smallest and largest cases. 1553 SDValue SwitchOp = getValue(JTH.SValue); 1554 EVT VT = SwitchOp.getValueType(); 1555 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1556 DAG.getConstant(JTH.First, VT)); 1557 1558 // The SDNode we just created, which holds the value being switched on minus 1559 // the smallest case value, needs to be copied to a virtual register so it 1560 // can be used as an index into the jump table in a subsequent basic block. 1561 // This value may be smaller or larger than the target's pointer type, and 1562 // therefore require extension or truncating. 1563 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1564 1565 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1566 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1567 JumpTableReg, SwitchOp); 1568 JT.Reg = JumpTableReg; 1569 1570 // Emit the range check for the jump table, and branch to the default block 1571 // for the switch statement if the value being switched on exceeds the largest 1572 // case in the switch. 1573 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1574 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1575 DAG.getConstant(JTH.Last-JTH.First,VT), 1576 ISD::SETUGT); 1577 1578 // Set NextBlock to be the MBB immediately after the current one, if any. 1579 // This is used to avoid emitting unnecessary branches to the next block. 1580 MachineBasicBlock *NextBlock = 0; 1581 MachineFunction::iterator BBI = SwitchBB; 1582 1583 if (++BBI != FuncInfo.MF->end()) 1584 NextBlock = BBI; 1585 1586 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1587 MVT::Other, CopyTo, CMP, 1588 DAG.getBasicBlock(JT.Default)); 1589 1590 if (JT.MBB != NextBlock) 1591 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1592 DAG.getBasicBlock(JT.MBB)); 1593 1594 DAG.setRoot(BrCond); 1595} 1596 1597/// visitBitTestHeader - This function emits necessary code to produce value 1598/// suitable for "bit tests" 1599void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1600 MachineBasicBlock *SwitchBB) { 1601 // Subtract the minimum value 1602 SDValue SwitchOp = getValue(B.SValue); 1603 EVT VT = SwitchOp.getValueType(); 1604 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1605 DAG.getConstant(B.First, VT)); 1606 1607 // Check range 1608 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1609 TLI.getSetCCResultType(Sub.getValueType()), 1610 Sub, DAG.getConstant(B.Range, VT), 1611 ISD::SETUGT); 1612 1613 // Determine the type of the test operands. 1614 bool UsePtrType = false; 1615 if (!TLI.isTypeLegal(VT)) 1616 UsePtrType = true; 1617 else { 1618 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1619 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) { 1620 // Switch table case range are encoded into series of masks. 1621 // Just use pointer type, it's guaranteed to fit. 1622 UsePtrType = true; 1623 break; 1624 } 1625 } 1626 if (UsePtrType) { 1627 VT = TLI.getPointerTy(); 1628 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1629 } 1630 1631 B.RegVT = VT; 1632 B.Reg = FuncInfo.CreateReg(VT); 1633 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1634 B.Reg, Sub); 1635 1636 // Set NextBlock to be the MBB immediately after the current one, if any. 1637 // This is used to avoid emitting unnecessary branches to the next block. 1638 MachineBasicBlock *NextBlock = 0; 1639 MachineFunction::iterator BBI = SwitchBB; 1640 if (++BBI != FuncInfo.MF->end()) 1641 NextBlock = BBI; 1642 1643 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1644 1645 SwitchBB->addSuccessor(B.Default); 1646 SwitchBB->addSuccessor(MBB); 1647 1648 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1649 MVT::Other, CopyTo, RangeCmp, 1650 DAG.getBasicBlock(B.Default)); 1651 1652 if (MBB != NextBlock) 1653 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1654 DAG.getBasicBlock(MBB)); 1655 1656 DAG.setRoot(BrRange); 1657} 1658 1659/// visitBitTestCase - this function produces one "bit test" 1660void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1661 MachineBasicBlock* NextMBB, 1662 unsigned Reg, 1663 BitTestCase &B, 1664 MachineBasicBlock *SwitchBB) { 1665 EVT VT = BB.RegVT; 1666 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1667 Reg, VT); 1668 SDValue Cmp; 1669 if (CountPopulation_64(B.Mask) == 1) { 1670 // Testing for a single bit; just compare the shift count with what it 1671 // would need to be to shift a 1 bit in that position. 1672 Cmp = DAG.getSetCC(getCurDebugLoc(), 1673 TLI.getSetCCResultType(VT), 1674 ShiftOp, 1675 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1676 ISD::SETEQ); 1677 } else { 1678 // Make desired shift 1679 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1680 DAG.getConstant(1, VT), ShiftOp); 1681 1682 // Emit bit tests and jumps 1683 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1684 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1685 Cmp = DAG.getSetCC(getCurDebugLoc(), 1686 TLI.getSetCCResultType(VT), 1687 AndOp, DAG.getConstant(0, VT), 1688 ISD::SETNE); 1689 } 1690 1691 SwitchBB->addSuccessor(B.TargetBB); 1692 SwitchBB->addSuccessor(NextMBB); 1693 1694 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1695 MVT::Other, getControlRoot(), 1696 Cmp, DAG.getBasicBlock(B.TargetBB)); 1697 1698 // Set NextBlock to be the MBB immediately after the current one, if any. 1699 // This is used to avoid emitting unnecessary branches to the next block. 1700 MachineBasicBlock *NextBlock = 0; 1701 MachineFunction::iterator BBI = SwitchBB; 1702 if (++BBI != FuncInfo.MF->end()) 1703 NextBlock = BBI; 1704 1705 if (NextMBB != NextBlock) 1706 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1707 DAG.getBasicBlock(NextMBB)); 1708 1709 DAG.setRoot(BrAnd); 1710} 1711 1712void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1713 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1714 1715 // Retrieve successors. 1716 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1717 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1718 1719 const Value *Callee(I.getCalledValue()); 1720 if (isa<InlineAsm>(Callee)) 1721 visitInlineAsm(&I); 1722 else 1723 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1724 1725 // If the value of the invoke is used outside of its defining block, make it 1726 // available as a virtual register. 1727 CopyToExportRegsIfNeeded(&I); 1728 1729 // Update successor info 1730 InvokeMBB->addSuccessor(Return); 1731 InvokeMBB->addSuccessor(LandingPad); 1732 1733 // Drop into normal successor. 1734 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1735 MVT::Other, getControlRoot(), 1736 DAG.getBasicBlock(Return))); 1737} 1738 1739void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1740} 1741 1742/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1743/// small case ranges). 1744bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1745 CaseRecVector& WorkList, 1746 const Value* SV, 1747 MachineBasicBlock *Default, 1748 MachineBasicBlock *SwitchBB) { 1749 Case& BackCase = *(CR.Range.second-1); 1750 1751 // Size is the number of Cases represented by this range. 1752 size_t Size = CR.Range.second - CR.Range.first; 1753 if (Size > 3) 1754 return false; 1755 1756 // Get the MachineFunction which holds the current MBB. This is used when 1757 // inserting any additional MBBs necessary to represent the switch. 1758 MachineFunction *CurMF = FuncInfo.MF; 1759 1760 // Figure out which block is immediately after the current one. 1761 MachineBasicBlock *NextBlock = 0; 1762 MachineFunction::iterator BBI = CR.CaseBB; 1763 1764 if (++BBI != FuncInfo.MF->end()) 1765 NextBlock = BBI; 1766 1767 // If any two of the cases has the same destination, and if one value 1768 // is the same as the other, but has one bit unset that the other has set, 1769 // use bit manipulation to do two compares at once. For example: 1770 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1771 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1772 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1773 if (Size == 2 && CR.CaseBB == SwitchBB) { 1774 Case &Small = *CR.Range.first; 1775 Case &Big = *(CR.Range.second-1); 1776 1777 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1778 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1779 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1780 1781 // Check that there is only one bit different. 1782 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1783 (SmallValue | BigValue) == BigValue) { 1784 // Isolate the common bit. 1785 APInt CommonBit = BigValue & ~SmallValue; 1786 assert((SmallValue | CommonBit) == BigValue && 1787 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1788 1789 SDValue CondLHS = getValue(SV); 1790 EVT VT = CondLHS.getValueType(); 1791 DebugLoc DL = getCurDebugLoc(); 1792 1793 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1794 DAG.getConstant(CommonBit, VT)); 1795 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1796 Or, DAG.getConstant(BigValue, VT), 1797 ISD::SETEQ); 1798 1799 // Update successor info. 1800 SwitchBB->addSuccessor(Small.BB); 1801 SwitchBB->addSuccessor(Default); 1802 1803 // Insert the true branch. 1804 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1805 getControlRoot(), Cond, 1806 DAG.getBasicBlock(Small.BB)); 1807 1808 // Insert the false branch. 1809 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1810 DAG.getBasicBlock(Default)); 1811 1812 DAG.setRoot(BrCond); 1813 return true; 1814 } 1815 } 1816 } 1817 1818 // Rearrange the case blocks so that the last one falls through if possible. 1819 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1820 // The last case block won't fall through into 'NextBlock' if we emit the 1821 // branches in this order. See if rearranging a case value would help. 1822 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1823 if (I->BB == NextBlock) { 1824 std::swap(*I, BackCase); 1825 break; 1826 } 1827 } 1828 } 1829 1830 // Create a CaseBlock record representing a conditional branch to 1831 // the Case's target mbb if the value being switched on SV is equal 1832 // to C. 1833 MachineBasicBlock *CurBlock = CR.CaseBB; 1834 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1835 MachineBasicBlock *FallThrough; 1836 if (I != E-1) { 1837 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1838 CurMF->insert(BBI, FallThrough); 1839 1840 // Put SV in a virtual register to make it available from the new blocks. 1841 ExportFromCurrentBlock(SV); 1842 } else { 1843 // If the last case doesn't match, go to the default block. 1844 FallThrough = Default; 1845 } 1846 1847 const Value *RHS, *LHS, *MHS; 1848 ISD::CondCode CC; 1849 if (I->High == I->Low) { 1850 // This is just small small case range :) containing exactly 1 case 1851 CC = ISD::SETEQ; 1852 LHS = SV; RHS = I->High; MHS = NULL; 1853 } else { 1854 CC = ISD::SETLE; 1855 LHS = I->Low; MHS = SV; RHS = I->High; 1856 } 1857 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1858 1859 // If emitting the first comparison, just call visitSwitchCase to emit the 1860 // code into the current block. Otherwise, push the CaseBlock onto the 1861 // vector to be later processed by SDISel, and insert the node's MBB 1862 // before the next MBB. 1863 if (CurBlock == SwitchBB) 1864 visitSwitchCase(CB, SwitchBB); 1865 else 1866 SwitchCases.push_back(CB); 1867 1868 CurBlock = FallThrough; 1869 } 1870 1871 return true; 1872} 1873 1874static inline bool areJTsAllowed(const TargetLowering &TLI) { 1875 return !DisableJumpTables && 1876 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1877 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1878} 1879 1880static APInt ComputeRange(const APInt &First, const APInt &Last) { 1881 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1882 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 1883 return (LastExt - FirstExt + 1ULL); 1884} 1885 1886/// handleJTSwitchCase - Emit jumptable for current switch case range 1887bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1888 CaseRecVector& WorkList, 1889 const Value* SV, 1890 MachineBasicBlock* Default, 1891 MachineBasicBlock *SwitchBB) { 1892 Case& FrontCase = *CR.Range.first; 1893 Case& BackCase = *(CR.Range.second-1); 1894 1895 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1896 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1897 1898 APInt TSize(First.getBitWidth(), 0); 1899 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1900 I!=E; ++I) 1901 TSize += I->size(); 1902 1903 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1904 return false; 1905 1906 APInt Range = ComputeRange(First, Last); 1907 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1908 if (Density < 0.4) 1909 return false; 1910 1911 DEBUG(dbgs() << "Lowering jump table\n" 1912 << "First entry: " << First << ". Last entry: " << Last << '\n' 1913 << "Range: " << Range 1914 << ". Size: " << TSize << ". Density: " << Density << "\n\n"); 1915 1916 // Get the MachineFunction which holds the current MBB. This is used when 1917 // inserting any additional MBBs necessary to represent the switch. 1918 MachineFunction *CurMF = FuncInfo.MF; 1919 1920 // Figure out which block is immediately after the current one. 1921 MachineFunction::iterator BBI = CR.CaseBB; 1922 ++BBI; 1923 1924 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1925 1926 // Create a new basic block to hold the code for loading the address 1927 // of the jump table, and jumping to it. Update successor information; 1928 // we will either branch to the default case for the switch, or the jump 1929 // table. 1930 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1931 CurMF->insert(BBI, JumpTableBB); 1932 CR.CaseBB->addSuccessor(Default); 1933 CR.CaseBB->addSuccessor(JumpTableBB); 1934 1935 // Build a vector of destination BBs, corresponding to each target 1936 // of the jump table. If the value of the jump table slot corresponds to 1937 // a case statement, push the case's BB onto the vector, otherwise, push 1938 // the default BB. 1939 std::vector<MachineBasicBlock*> DestBBs; 1940 APInt TEI = First; 1941 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1942 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 1943 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 1944 1945 if (Low.sle(TEI) && TEI.sle(High)) { 1946 DestBBs.push_back(I->BB); 1947 if (TEI==High) 1948 ++I; 1949 } else { 1950 DestBBs.push_back(Default); 1951 } 1952 } 1953 1954 // Update successor info. Add one edge to each unique successor. 1955 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1956 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1957 E = DestBBs.end(); I != E; ++I) { 1958 if (!SuccsHandled[(*I)->getNumber()]) { 1959 SuccsHandled[(*I)->getNumber()] = true; 1960 JumpTableBB->addSuccessor(*I); 1961 } 1962 } 1963 1964 // Create a jump table index for this jump table. 1965 unsigned JTEncoding = TLI.getJumpTableEncoding(); 1966 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 1967 ->createJumpTableIndex(DestBBs); 1968 1969 // Set the jump table information so that we can codegen it as a second 1970 // MachineBasicBlock 1971 JumpTable JT(-1U, JTI, JumpTableBB, Default); 1972 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 1973 if (CR.CaseBB == SwitchBB) 1974 visitJumpTableHeader(JT, JTH, SwitchBB); 1975 1976 JTCases.push_back(JumpTableBlock(JTH, JT)); 1977 1978 return true; 1979} 1980 1981/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1982/// 2 subtrees. 1983bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 1984 CaseRecVector& WorkList, 1985 const Value* SV, 1986 MachineBasicBlock *Default, 1987 MachineBasicBlock *SwitchBB) { 1988 // Get the MachineFunction which holds the current MBB. This is used when 1989 // inserting any additional MBBs necessary to represent the switch. 1990 MachineFunction *CurMF = FuncInfo.MF; 1991 1992 // Figure out which block is immediately after the current one. 1993 MachineFunction::iterator BBI = CR.CaseBB; 1994 ++BBI; 1995 1996 Case& FrontCase = *CR.Range.first; 1997 Case& BackCase = *(CR.Range.second-1); 1998 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1999 2000 // Size is the number of Cases represented by this range. 2001 unsigned Size = CR.Range.second - CR.Range.first; 2002 2003 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2004 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2005 double FMetric = 0; 2006 CaseItr Pivot = CR.Range.first + Size/2; 2007 2008 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2009 // (heuristically) allow us to emit JumpTable's later. 2010 APInt TSize(First.getBitWidth(), 0); 2011 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2012 I!=E; ++I) 2013 TSize += I->size(); 2014 2015 APInt LSize = FrontCase.size(); 2016 APInt RSize = TSize-LSize; 2017 DEBUG(dbgs() << "Selecting best pivot: \n" 2018 << "First: " << First << ", Last: " << Last <<'\n' 2019 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2020 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2021 J!=E; ++I, ++J) { 2022 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2023 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2024 APInt Range = ComputeRange(LEnd, RBegin); 2025 assert((Range - 2ULL).isNonNegative() && 2026 "Invalid case distance"); 2027 double LDensity = (double)LSize.roundToDouble() / 2028 (LEnd - First + 1ULL).roundToDouble(); 2029 double RDensity = (double)RSize.roundToDouble() / 2030 (Last - RBegin + 1ULL).roundToDouble(); 2031 double Metric = Range.logBase2()*(LDensity+RDensity); 2032 // Should always split in some non-trivial place 2033 DEBUG(dbgs() <<"=>Step\n" 2034 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2035 << "LDensity: " << LDensity 2036 << ", RDensity: " << RDensity << '\n' 2037 << "Metric: " << Metric << '\n'); 2038 if (FMetric < Metric) { 2039 Pivot = J; 2040 FMetric = Metric; 2041 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2042 } 2043 2044 LSize += J->size(); 2045 RSize -= J->size(); 2046 } 2047 if (areJTsAllowed(TLI)) { 2048 // If our case is dense we *really* should handle it earlier! 2049 assert((FMetric > 0) && "Should handle dense range earlier!"); 2050 } else { 2051 Pivot = CR.Range.first + Size/2; 2052 } 2053 2054 CaseRange LHSR(CR.Range.first, Pivot); 2055 CaseRange RHSR(Pivot, CR.Range.second); 2056 Constant *C = Pivot->Low; 2057 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2058 2059 // We know that we branch to the LHS if the Value being switched on is 2060 // less than the Pivot value, C. We use this to optimize our binary 2061 // tree a bit, by recognizing that if SV is greater than or equal to the 2062 // LHS's Case Value, and that Case Value is exactly one less than the 2063 // Pivot's Value, then we can branch directly to the LHS's Target, 2064 // rather than creating a leaf node for it. 2065 if ((LHSR.second - LHSR.first) == 1 && 2066 LHSR.first->High == CR.GE && 2067 cast<ConstantInt>(C)->getValue() == 2068 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2069 TrueBB = LHSR.first->BB; 2070 } else { 2071 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2072 CurMF->insert(BBI, TrueBB); 2073 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2074 2075 // Put SV in a virtual register to make it available from the new blocks. 2076 ExportFromCurrentBlock(SV); 2077 } 2078 2079 // Similar to the optimization above, if the Value being switched on is 2080 // known to be less than the Constant CR.LT, and the current Case Value 2081 // is CR.LT - 1, then we can branch directly to the target block for 2082 // the current Case Value, rather than emitting a RHS leaf node for it. 2083 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2084 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2085 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2086 FalseBB = RHSR.first->BB; 2087 } else { 2088 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2089 CurMF->insert(BBI, FalseBB); 2090 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2091 2092 // Put SV in a virtual register to make it available from the new blocks. 2093 ExportFromCurrentBlock(SV); 2094 } 2095 2096 // Create a CaseBlock record representing a conditional branch to 2097 // the LHS node if the value being switched on SV is less than C. 2098 // Otherwise, branch to LHS. 2099 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2100 2101 if (CR.CaseBB == SwitchBB) 2102 visitSwitchCase(CB, SwitchBB); 2103 else 2104 SwitchCases.push_back(CB); 2105 2106 return true; 2107} 2108 2109/// handleBitTestsSwitchCase - if current case range has few destination and 2110/// range span less, than machine word bitwidth, encode case range into series 2111/// of masks and emit bit tests with these masks. 2112bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2113 CaseRecVector& WorkList, 2114 const Value* SV, 2115 MachineBasicBlock* Default, 2116 MachineBasicBlock *SwitchBB){ 2117 EVT PTy = TLI.getPointerTy(); 2118 unsigned IntPtrBits = PTy.getSizeInBits(); 2119 2120 Case& FrontCase = *CR.Range.first; 2121 Case& BackCase = *(CR.Range.second-1); 2122 2123 // Get the MachineFunction which holds the current MBB. This is used when 2124 // inserting any additional MBBs necessary to represent the switch. 2125 MachineFunction *CurMF = FuncInfo.MF; 2126 2127 // If target does not have legal shift left, do not emit bit tests at all. 2128 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2129 return false; 2130 2131 size_t numCmps = 0; 2132 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2133 I!=E; ++I) { 2134 // Single case counts one, case range - two. 2135 numCmps += (I->Low == I->High ? 1 : 2); 2136 } 2137 2138 // Count unique destinations 2139 SmallSet<MachineBasicBlock*, 4> Dests; 2140 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2141 Dests.insert(I->BB); 2142 if (Dests.size() > 3) 2143 // Don't bother the code below, if there are too much unique destinations 2144 return false; 2145 } 2146 DEBUG(dbgs() << "Total number of unique destinations: " 2147 << Dests.size() << '\n' 2148 << "Total number of comparisons: " << numCmps << '\n'); 2149 2150 // Compute span of values. 2151 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2152 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2153 APInt cmpRange = maxValue - minValue; 2154 2155 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2156 << "Low bound: " << minValue << '\n' 2157 << "High bound: " << maxValue << '\n'); 2158 2159 if (cmpRange.uge(IntPtrBits) || 2160 (!(Dests.size() == 1 && numCmps >= 3) && 2161 !(Dests.size() == 2 && numCmps >= 5) && 2162 !(Dests.size() >= 3 && numCmps >= 6))) 2163 return false; 2164 2165 DEBUG(dbgs() << "Emitting bit tests\n"); 2166 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2167 2168 // Optimize the case where all the case values fit in a 2169 // word without having to subtract minValue. In this case, 2170 // we can optimize away the subtraction. 2171 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2172 cmpRange = maxValue; 2173 } else { 2174 lowBound = minValue; 2175 } 2176 2177 CaseBitsVector CasesBits; 2178 unsigned i, count = 0; 2179 2180 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2181 MachineBasicBlock* Dest = I->BB; 2182 for (i = 0; i < count; ++i) 2183 if (Dest == CasesBits[i].BB) 2184 break; 2185 2186 if (i == count) { 2187 assert((count < 3) && "Too much destinations to test!"); 2188 CasesBits.push_back(CaseBits(0, Dest, 0)); 2189 count++; 2190 } 2191 2192 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2193 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2194 2195 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2196 uint64_t hi = (highValue - lowBound).getZExtValue(); 2197 2198 for (uint64_t j = lo; j <= hi; j++) { 2199 CasesBits[i].Mask |= 1ULL << j; 2200 CasesBits[i].Bits++; 2201 } 2202 2203 } 2204 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2205 2206 BitTestInfo BTC; 2207 2208 // Figure out which block is immediately after the current one. 2209 MachineFunction::iterator BBI = CR.CaseBB; 2210 ++BBI; 2211 2212 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2213 2214 DEBUG(dbgs() << "Cases:\n"); 2215 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2216 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2217 << ", Bits: " << CasesBits[i].Bits 2218 << ", BB: " << CasesBits[i].BB << '\n'); 2219 2220 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2221 CurMF->insert(BBI, CaseBB); 2222 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2223 CaseBB, 2224 CasesBits[i].BB)); 2225 2226 // Put SV in a virtual register to make it available from the new blocks. 2227 ExportFromCurrentBlock(SV); 2228 } 2229 2230 BitTestBlock BTB(lowBound, cmpRange, SV, 2231 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2232 CR.CaseBB, Default, BTC); 2233 2234 if (CR.CaseBB == SwitchBB) 2235 visitBitTestHeader(BTB, SwitchBB); 2236 2237 BitTestCases.push_back(BTB); 2238 2239 return true; 2240} 2241 2242/// Clusterify - Transform simple list of Cases into list of CaseRange's 2243size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2244 const SwitchInst& SI) { 2245 size_t numCmps = 0; 2246 2247 // Start with "simple" cases 2248 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2249 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2250 Cases.push_back(Case(SI.getSuccessorValue(i), 2251 SI.getSuccessorValue(i), 2252 SMBB)); 2253 } 2254 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2255 2256 // Merge case into clusters 2257 if (Cases.size() >= 2) 2258 // Must recompute end() each iteration because it may be 2259 // invalidated by erase if we hold on to it 2260 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2261 J != Cases.end(); ) { 2262 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2263 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2264 MachineBasicBlock* nextBB = J->BB; 2265 MachineBasicBlock* currentBB = I->BB; 2266 2267 // If the two neighboring cases go to the same destination, merge them 2268 // into a single case. 2269 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2270 I->High = J->High; 2271 J = Cases.erase(J); 2272 } else { 2273 I = J++; 2274 } 2275 } 2276 2277 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2278 if (I->Low != I->High) 2279 // A range counts double, since it requires two compares. 2280 ++numCmps; 2281 } 2282 2283 return numCmps; 2284} 2285 2286void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2287 MachineBasicBlock *Last) { 2288 // Update JTCases. 2289 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2290 if (JTCases[i].first.HeaderBB == First) 2291 JTCases[i].first.HeaderBB = Last; 2292 2293 // Update BitTestCases. 2294 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2295 if (BitTestCases[i].Parent == First) 2296 BitTestCases[i].Parent = Last; 2297} 2298 2299void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2300 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2301 2302 // Figure out which block is immediately after the current one. 2303 MachineBasicBlock *NextBlock = 0; 2304 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2305 2306 // If there is only the default destination, branch to it if it is not the 2307 // next basic block. Otherwise, just fall through. 2308 if (SI.getNumOperands() == 2) { 2309 // Update machine-CFG edges. 2310 2311 // If this is not a fall-through branch, emit the branch. 2312 SwitchMBB->addSuccessor(Default); 2313 if (Default != NextBlock) 2314 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2315 MVT::Other, getControlRoot(), 2316 DAG.getBasicBlock(Default))); 2317 2318 return; 2319 } 2320 2321 // If there are any non-default case statements, create a vector of Cases 2322 // representing each one, and sort the vector so that we can efficiently 2323 // create a binary search tree from them. 2324 CaseVector Cases; 2325 size_t numCmps = Clusterify(Cases, SI); 2326 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2327 << ". Total compares: " << numCmps << '\n'); 2328 numCmps = 0; 2329 2330 // Get the Value to be switched on and default basic blocks, which will be 2331 // inserted into CaseBlock records, representing basic blocks in the binary 2332 // search tree. 2333 const Value *SV = SI.getOperand(0); 2334 2335 // Push the initial CaseRec onto the worklist 2336 CaseRecVector WorkList; 2337 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2338 CaseRange(Cases.begin(),Cases.end()))); 2339 2340 while (!WorkList.empty()) { 2341 // Grab a record representing a case range to process off the worklist 2342 CaseRec CR = WorkList.back(); 2343 WorkList.pop_back(); 2344 2345 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2346 continue; 2347 2348 // If the range has few cases (two or less) emit a series of specific 2349 // tests. 2350 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2351 continue; 2352 2353 // If the switch has more than 5 blocks, and at least 40% dense, and the 2354 // target supports indirect branches, then emit a jump table rather than 2355 // lowering the switch to a binary tree of conditional branches. 2356 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2357 continue; 2358 2359 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2360 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2361 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2362 } 2363} 2364 2365void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2366 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2367 2368 // Update machine-CFG edges with unique successors. 2369 SmallVector<BasicBlock*, 32> succs; 2370 succs.reserve(I.getNumSuccessors()); 2371 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2372 succs.push_back(I.getSuccessor(i)); 2373 array_pod_sort(succs.begin(), succs.end()); 2374 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2375 for (unsigned i = 0, e = succs.size(); i != e; ++i) 2376 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]); 2377 2378 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2379 MVT::Other, getControlRoot(), 2380 getValue(I.getAddress()))); 2381} 2382 2383void SelectionDAGBuilder::visitFSub(const User &I) { 2384 // -0.0 - X --> fneg 2385 const Type *Ty = I.getType(); 2386 if (isa<Constant>(I.getOperand(0)) && 2387 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2388 SDValue Op2 = getValue(I.getOperand(1)); 2389 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2390 Op2.getValueType(), Op2)); 2391 return; 2392 } 2393 2394 visitBinary(I, ISD::FSUB); 2395} 2396 2397void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2398 SDValue Op1 = getValue(I.getOperand(0)); 2399 SDValue Op2 = getValue(I.getOperand(1)); 2400 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2401 Op1.getValueType(), Op1, Op2)); 2402} 2403 2404void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2405 SDValue Op1 = getValue(I.getOperand(0)); 2406 SDValue Op2 = getValue(I.getOperand(1)); 2407 2408 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2409 2410 // Coerce the shift amount to the right type if we can. 2411 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2412 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2413 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2414 DebugLoc DL = getCurDebugLoc(); 2415 2416 // If the operand is smaller than the shift count type, promote it. 2417 if (ShiftSize > Op2Size) 2418 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2419 2420 // If the operand is larger than the shift count type but the shift 2421 // count type has enough bits to represent any shift value, truncate 2422 // it now. This is a common case and it exposes the truncate to 2423 // optimization early. 2424 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2425 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2426 // Otherwise we'll need to temporarily settle for some other convenient 2427 // type. Type legalization will make adjustments once the shiftee is split. 2428 else 2429 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2430 } 2431 2432 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2433 Op1.getValueType(), Op1, Op2)); 2434} 2435 2436void SelectionDAGBuilder::visitICmp(const User &I) { 2437 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2438 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2439 predicate = IC->getPredicate(); 2440 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2441 predicate = ICmpInst::Predicate(IC->getPredicate()); 2442 SDValue Op1 = getValue(I.getOperand(0)); 2443 SDValue Op2 = getValue(I.getOperand(1)); 2444 ISD::CondCode Opcode = getICmpCondCode(predicate); 2445 2446 EVT DestVT = TLI.getValueType(I.getType()); 2447 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2448} 2449 2450void SelectionDAGBuilder::visitFCmp(const User &I) { 2451 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2452 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2453 predicate = FC->getPredicate(); 2454 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2455 predicate = FCmpInst::Predicate(FC->getPredicate()); 2456 SDValue Op1 = getValue(I.getOperand(0)); 2457 SDValue Op2 = getValue(I.getOperand(1)); 2458 ISD::CondCode Condition = getFCmpCondCode(predicate); 2459 EVT DestVT = TLI.getValueType(I.getType()); 2460 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2461} 2462 2463void SelectionDAGBuilder::visitSelect(const User &I) { 2464 SmallVector<EVT, 4> ValueVTs; 2465 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2466 unsigned NumValues = ValueVTs.size(); 2467 if (NumValues == 0) return; 2468 2469 SmallVector<SDValue, 4> Values(NumValues); 2470 SDValue Cond = getValue(I.getOperand(0)); 2471 SDValue TrueVal = getValue(I.getOperand(1)); 2472 SDValue FalseVal = getValue(I.getOperand(2)); 2473 2474 for (unsigned i = 0; i != NumValues; ++i) 2475 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2476 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2477 Cond, 2478 SDValue(TrueVal.getNode(), 2479 TrueVal.getResNo() + i), 2480 SDValue(FalseVal.getNode(), 2481 FalseVal.getResNo() + i)); 2482 2483 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2484 DAG.getVTList(&ValueVTs[0], NumValues), 2485 &Values[0], NumValues)); 2486} 2487 2488void SelectionDAGBuilder::visitTrunc(const User &I) { 2489 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2490 SDValue N = getValue(I.getOperand(0)); 2491 EVT DestVT = TLI.getValueType(I.getType()); 2492 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2493} 2494 2495void SelectionDAGBuilder::visitZExt(const User &I) { 2496 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2497 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2498 SDValue N = getValue(I.getOperand(0)); 2499 EVT DestVT = TLI.getValueType(I.getType()); 2500 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2501} 2502 2503void SelectionDAGBuilder::visitSExt(const User &I) { 2504 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2505 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2506 SDValue N = getValue(I.getOperand(0)); 2507 EVT DestVT = TLI.getValueType(I.getType()); 2508 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2509} 2510 2511void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2512 // FPTrunc is never a no-op cast, no need to check 2513 SDValue N = getValue(I.getOperand(0)); 2514 EVT DestVT = TLI.getValueType(I.getType()); 2515 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2516 DestVT, N, DAG.getIntPtrConstant(0))); 2517} 2518 2519void SelectionDAGBuilder::visitFPExt(const User &I){ 2520 // FPTrunc is never a no-op cast, no need to check 2521 SDValue N = getValue(I.getOperand(0)); 2522 EVT DestVT = TLI.getValueType(I.getType()); 2523 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2524} 2525 2526void SelectionDAGBuilder::visitFPToUI(const User &I) { 2527 // FPToUI is never a no-op cast, no need to check 2528 SDValue N = getValue(I.getOperand(0)); 2529 EVT DestVT = TLI.getValueType(I.getType()); 2530 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2531} 2532 2533void SelectionDAGBuilder::visitFPToSI(const User &I) { 2534 // FPToSI is never a no-op cast, no need to check 2535 SDValue N = getValue(I.getOperand(0)); 2536 EVT DestVT = TLI.getValueType(I.getType()); 2537 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2538} 2539 2540void SelectionDAGBuilder::visitUIToFP(const User &I) { 2541 // UIToFP is never a no-op cast, no need to check 2542 SDValue N = getValue(I.getOperand(0)); 2543 EVT DestVT = TLI.getValueType(I.getType()); 2544 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2545} 2546 2547void SelectionDAGBuilder::visitSIToFP(const User &I){ 2548 // SIToFP is never a no-op cast, no need to check 2549 SDValue N = getValue(I.getOperand(0)); 2550 EVT DestVT = TLI.getValueType(I.getType()); 2551 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2552} 2553 2554void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2555 // What to do depends on the size of the integer and the size of the pointer. 2556 // We can either truncate, zero extend, or no-op, accordingly. 2557 SDValue N = getValue(I.getOperand(0)); 2558 EVT DestVT = TLI.getValueType(I.getType()); 2559 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2560} 2561 2562void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2563 // What to do depends on the size of the integer and the size of the pointer. 2564 // We can either truncate, zero extend, or no-op, accordingly. 2565 SDValue N = getValue(I.getOperand(0)); 2566 EVT DestVT = TLI.getValueType(I.getType()); 2567 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2568} 2569 2570void SelectionDAGBuilder::visitBitCast(const User &I) { 2571 SDValue N = getValue(I.getOperand(0)); 2572 EVT DestVT = TLI.getValueType(I.getType()); 2573 2574 // BitCast assures us that source and destination are the same size so this is 2575 // either a BITCAST or a no-op. 2576 if (DestVT != N.getValueType()) 2577 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2578 DestVT, N)); // convert types. 2579 else 2580 setValue(&I, N); // noop cast. 2581} 2582 2583void SelectionDAGBuilder::visitInsertElement(const User &I) { 2584 SDValue InVec = getValue(I.getOperand(0)); 2585 SDValue InVal = getValue(I.getOperand(1)); 2586 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2587 TLI.getPointerTy(), 2588 getValue(I.getOperand(2))); 2589 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2590 TLI.getValueType(I.getType()), 2591 InVec, InVal, InIdx)); 2592} 2593 2594void SelectionDAGBuilder::visitExtractElement(const User &I) { 2595 SDValue InVec = getValue(I.getOperand(0)); 2596 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2597 TLI.getPointerTy(), 2598 getValue(I.getOperand(1))); 2599 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2600 TLI.getValueType(I.getType()), InVec, InIdx)); 2601} 2602 2603// Utility for visitShuffleVector - Returns true if the mask is mask starting 2604// from SIndx and increasing to the element length (undefs are allowed). 2605static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2606 unsigned MaskNumElts = Mask.size(); 2607 for (unsigned i = 0; i != MaskNumElts; ++i) 2608 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2609 return false; 2610 return true; 2611} 2612 2613void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2614 SmallVector<int, 8> Mask; 2615 SDValue Src1 = getValue(I.getOperand(0)); 2616 SDValue Src2 = getValue(I.getOperand(1)); 2617 2618 // Convert the ConstantVector mask operand into an array of ints, with -1 2619 // representing undef values. 2620 SmallVector<Constant*, 8> MaskElts; 2621 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2622 unsigned MaskNumElts = MaskElts.size(); 2623 for (unsigned i = 0; i != MaskNumElts; ++i) { 2624 if (isa<UndefValue>(MaskElts[i])) 2625 Mask.push_back(-1); 2626 else 2627 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2628 } 2629 2630 EVT VT = TLI.getValueType(I.getType()); 2631 EVT SrcVT = Src1.getValueType(); 2632 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2633 2634 if (SrcNumElts == MaskNumElts) { 2635 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2636 &Mask[0])); 2637 return; 2638 } 2639 2640 // Normalize the shuffle vector since mask and vector length don't match. 2641 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2642 // Mask is longer than the source vectors and is a multiple of the source 2643 // vectors. We can use concatenate vector to make the mask and vectors 2644 // lengths match. 2645 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2646 // The shuffle is concatenating two vectors together. 2647 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2648 VT, Src1, Src2)); 2649 return; 2650 } 2651 2652 // Pad both vectors with undefs to make them the same length as the mask. 2653 unsigned NumConcat = MaskNumElts / SrcNumElts; 2654 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2655 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2656 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2657 2658 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2659 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2660 MOps1[0] = Src1; 2661 MOps2[0] = Src2; 2662 2663 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2664 getCurDebugLoc(), VT, 2665 &MOps1[0], NumConcat); 2666 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2667 getCurDebugLoc(), VT, 2668 &MOps2[0], NumConcat); 2669 2670 // Readjust mask for new input vector length. 2671 SmallVector<int, 8> MappedOps; 2672 for (unsigned i = 0; i != MaskNumElts; ++i) { 2673 int Idx = Mask[i]; 2674 if (Idx < (int)SrcNumElts) 2675 MappedOps.push_back(Idx); 2676 else 2677 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2678 } 2679 2680 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2681 &MappedOps[0])); 2682 return; 2683 } 2684 2685 if (SrcNumElts > MaskNumElts) { 2686 // Analyze the access pattern of the vector to see if we can extract 2687 // two subvectors and do the shuffle. The analysis is done by calculating 2688 // the range of elements the mask access on both vectors. 2689 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2690 int MaxRange[2] = {-1, -1}; 2691 2692 for (unsigned i = 0; i != MaskNumElts; ++i) { 2693 int Idx = Mask[i]; 2694 int Input = 0; 2695 if (Idx < 0) 2696 continue; 2697 2698 if (Idx >= (int)SrcNumElts) { 2699 Input = 1; 2700 Idx -= SrcNumElts; 2701 } 2702 if (Idx > MaxRange[Input]) 2703 MaxRange[Input] = Idx; 2704 if (Idx < MinRange[Input]) 2705 MinRange[Input] = Idx; 2706 } 2707 2708 // Check if the access is smaller than the vector size and can we find 2709 // a reasonable extract index. 2710 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2711 // Extract. 2712 int StartIdx[2]; // StartIdx to extract from 2713 for (int Input=0; Input < 2; ++Input) { 2714 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2715 RangeUse[Input] = 0; // Unused 2716 StartIdx[Input] = 0; 2717 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2718 // Fits within range but we should see if we can find a good 2719 // start index that is a multiple of the mask length. 2720 if (MaxRange[Input] < (int)MaskNumElts) { 2721 RangeUse[Input] = 1; // Extract from beginning of the vector 2722 StartIdx[Input] = 0; 2723 } else { 2724 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2725 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2726 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2727 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2728 } 2729 } 2730 } 2731 2732 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2733 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2734 return; 2735 } 2736 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2737 // Extract appropriate subvector and generate a vector shuffle 2738 for (int Input=0; Input < 2; ++Input) { 2739 SDValue &Src = Input == 0 ? Src1 : Src2; 2740 if (RangeUse[Input] == 0) 2741 Src = DAG.getUNDEF(VT); 2742 else 2743 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2744 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2745 } 2746 2747 // Calculate new mask. 2748 SmallVector<int, 8> MappedOps; 2749 for (unsigned i = 0; i != MaskNumElts; ++i) { 2750 int Idx = Mask[i]; 2751 if (Idx < 0) 2752 MappedOps.push_back(Idx); 2753 else if (Idx < (int)SrcNumElts) 2754 MappedOps.push_back(Idx - StartIdx[0]); 2755 else 2756 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2757 } 2758 2759 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2760 &MappedOps[0])); 2761 return; 2762 } 2763 } 2764 2765 // We can't use either concat vectors or extract subvectors so fall back to 2766 // replacing the shuffle with extract and build vector. 2767 // to insert and build vector. 2768 EVT EltVT = VT.getVectorElementType(); 2769 EVT PtrVT = TLI.getPointerTy(); 2770 SmallVector<SDValue,8> Ops; 2771 for (unsigned i = 0; i != MaskNumElts; ++i) { 2772 if (Mask[i] < 0) { 2773 Ops.push_back(DAG.getUNDEF(EltVT)); 2774 } else { 2775 int Idx = Mask[i]; 2776 SDValue Res; 2777 2778 if (Idx < (int)SrcNumElts) 2779 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2780 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2781 else 2782 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2783 EltVT, Src2, 2784 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2785 2786 Ops.push_back(Res); 2787 } 2788 } 2789 2790 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2791 VT, &Ops[0], Ops.size())); 2792} 2793 2794void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2795 const Value *Op0 = I.getOperand(0); 2796 const Value *Op1 = I.getOperand(1); 2797 const Type *AggTy = I.getType(); 2798 const Type *ValTy = Op1->getType(); 2799 bool IntoUndef = isa<UndefValue>(Op0); 2800 bool FromUndef = isa<UndefValue>(Op1); 2801 2802 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2803 2804 SmallVector<EVT, 4> AggValueVTs; 2805 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2806 SmallVector<EVT, 4> ValValueVTs; 2807 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2808 2809 unsigned NumAggValues = AggValueVTs.size(); 2810 unsigned NumValValues = ValValueVTs.size(); 2811 SmallVector<SDValue, 4> Values(NumAggValues); 2812 2813 SDValue Agg = getValue(Op0); 2814 SDValue Val = getValue(Op1); 2815 unsigned i = 0; 2816 // Copy the beginning value(s) from the original aggregate. 2817 for (; i != LinearIndex; ++i) 2818 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2819 SDValue(Agg.getNode(), Agg.getResNo() + i); 2820 // Copy values from the inserted value(s). 2821 for (; i != LinearIndex + NumValValues; ++i) 2822 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2823 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2824 // Copy remaining value(s) from the original aggregate. 2825 for (; i != NumAggValues; ++i) 2826 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2827 SDValue(Agg.getNode(), Agg.getResNo() + i); 2828 2829 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2830 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2831 &Values[0], NumAggValues)); 2832} 2833 2834void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2835 const Value *Op0 = I.getOperand(0); 2836 const Type *AggTy = Op0->getType(); 2837 const Type *ValTy = I.getType(); 2838 bool OutOfUndef = isa<UndefValue>(Op0); 2839 2840 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2841 2842 SmallVector<EVT, 4> ValValueVTs; 2843 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2844 2845 unsigned NumValValues = ValValueVTs.size(); 2846 SmallVector<SDValue, 4> Values(NumValValues); 2847 2848 SDValue Agg = getValue(Op0); 2849 // Copy out the selected value(s). 2850 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2851 Values[i - LinearIndex] = 2852 OutOfUndef ? 2853 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2854 SDValue(Agg.getNode(), Agg.getResNo() + i); 2855 2856 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2857 DAG.getVTList(&ValValueVTs[0], NumValValues), 2858 &Values[0], NumValValues)); 2859} 2860 2861void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2862 SDValue N = getValue(I.getOperand(0)); 2863 const Type *Ty = I.getOperand(0)->getType(); 2864 2865 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2866 OI != E; ++OI) { 2867 const Value *Idx = *OI; 2868 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2869 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2870 if (Field) { 2871 // N = N + Offset 2872 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2873 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2874 DAG.getIntPtrConstant(Offset)); 2875 } 2876 2877 Ty = StTy->getElementType(Field); 2878 } else { 2879 Ty = cast<SequentialType>(Ty)->getElementType(); 2880 2881 // If this is a constant subscript, handle it quickly. 2882 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2883 if (CI->isZero()) continue; 2884 uint64_t Offs = 2885 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2886 SDValue OffsVal; 2887 EVT PTy = TLI.getPointerTy(); 2888 unsigned PtrBits = PTy.getSizeInBits(); 2889 if (PtrBits < 64) 2890 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2891 TLI.getPointerTy(), 2892 DAG.getConstant(Offs, MVT::i64)); 2893 else 2894 OffsVal = DAG.getIntPtrConstant(Offs); 2895 2896 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2897 OffsVal); 2898 continue; 2899 } 2900 2901 // N = N + Idx * ElementSize; 2902 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2903 TD->getTypeAllocSize(Ty)); 2904 SDValue IdxN = getValue(Idx); 2905 2906 // If the index is smaller or larger than intptr_t, truncate or extend 2907 // it. 2908 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2909 2910 // If this is a multiply by a power of two, turn it into a shl 2911 // immediately. This is a very common case. 2912 if (ElementSize != 1) { 2913 if (ElementSize.isPowerOf2()) { 2914 unsigned Amt = ElementSize.logBase2(); 2915 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2916 N.getValueType(), IdxN, 2917 DAG.getConstant(Amt, TLI.getPointerTy())); 2918 } else { 2919 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2920 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2921 N.getValueType(), IdxN, Scale); 2922 } 2923 } 2924 2925 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2926 N.getValueType(), N, IdxN); 2927 } 2928 } 2929 2930 setValue(&I, N); 2931} 2932 2933void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 2934 // If this is a fixed sized alloca in the entry block of the function, 2935 // allocate it statically on the stack. 2936 if (FuncInfo.StaticAllocaMap.count(&I)) 2937 return; // getValue will auto-populate this. 2938 2939 const Type *Ty = I.getAllocatedType(); 2940 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 2941 unsigned Align = 2942 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2943 I.getAlignment()); 2944 2945 SDValue AllocSize = getValue(I.getArraySize()); 2946 2947 EVT IntPtr = TLI.getPointerTy(); 2948 if (AllocSize.getValueType() != IntPtr) 2949 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 2950 2951 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 2952 AllocSize, 2953 DAG.getConstant(TySize, IntPtr)); 2954 2955 // Handle alignment. If the requested alignment is less than or equal to 2956 // the stack alignment, ignore it. If the size is greater than or equal to 2957 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2958 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 2959 if (Align <= StackAlign) 2960 Align = 0; 2961 2962 // Round the size of the allocation up to the stack alignment size 2963 // by add SA-1 to the size. 2964 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2965 AllocSize.getValueType(), AllocSize, 2966 DAG.getIntPtrConstant(StackAlign-1)); 2967 2968 // Mask out the low bits for alignment purposes. 2969 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 2970 AllocSize.getValueType(), AllocSize, 2971 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2972 2973 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2974 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 2975 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 2976 VTs, Ops, 3); 2977 setValue(&I, DSA); 2978 DAG.setRoot(DSA.getValue(1)); 2979 2980 // Inform the Frame Information that we have just allocated a variable-sized 2981 // object. 2982 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 2983} 2984 2985void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 2986 const Value *SV = I.getOperand(0); 2987 SDValue Ptr = getValue(SV); 2988 2989 const Type *Ty = I.getType(); 2990 2991 bool isVolatile = I.isVolatile(); 2992 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2993 unsigned Alignment = I.getAlignment(); 2994 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 2995 2996 SmallVector<EVT, 4> ValueVTs; 2997 SmallVector<uint64_t, 4> Offsets; 2998 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2999 unsigned NumValues = ValueVTs.size(); 3000 if (NumValues == 0) 3001 return; 3002 3003 SDValue Root; 3004 bool ConstantMemory = false; 3005 if (I.isVolatile() || NumValues > MaxParallelChains) 3006 // Serialize volatile loads with other side effects. 3007 Root = getRoot(); 3008 else if (AA->pointsToConstantMemory( 3009 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3010 // Do not serialize (non-volatile) loads of constant memory with anything. 3011 Root = DAG.getEntryNode(); 3012 ConstantMemory = true; 3013 } else { 3014 // Do not serialize non-volatile loads against each other. 3015 Root = DAG.getRoot(); 3016 } 3017 3018 SmallVector<SDValue, 4> Values(NumValues); 3019 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3020 NumValues)); 3021 EVT PtrVT = Ptr.getValueType(); 3022 unsigned ChainI = 0; 3023 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3024 // Serializing loads here may result in excessive register pressure, and 3025 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3026 // could recover a bit by hoisting nodes upward in the chain by recognizing 3027 // they are side-effect free or do not alias. The optimizer should really 3028 // avoid this case by converting large object/array copies to llvm.memcpy 3029 // (MaxParallelChains should always remain as failsafe). 3030 if (ChainI == MaxParallelChains) { 3031 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3032 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3033 MVT::Other, &Chains[0], ChainI); 3034 Root = Chain; 3035 ChainI = 0; 3036 } 3037 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3038 PtrVT, Ptr, 3039 DAG.getConstant(Offsets[i], PtrVT)); 3040 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3041 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3042 isNonTemporal, Alignment, TBAAInfo); 3043 3044 Values[i] = L; 3045 Chains[ChainI] = L.getValue(1); 3046 } 3047 3048 if (!ConstantMemory) { 3049 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3050 MVT::Other, &Chains[0], ChainI); 3051 if (isVolatile) 3052 DAG.setRoot(Chain); 3053 else 3054 PendingLoads.push_back(Chain); 3055 } 3056 3057 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3058 DAG.getVTList(&ValueVTs[0], NumValues), 3059 &Values[0], NumValues)); 3060} 3061 3062void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3063 const Value *SrcV = I.getOperand(0); 3064 const Value *PtrV = I.getOperand(1); 3065 3066 SmallVector<EVT, 4> ValueVTs; 3067 SmallVector<uint64_t, 4> Offsets; 3068 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3069 unsigned NumValues = ValueVTs.size(); 3070 if (NumValues == 0) 3071 return; 3072 3073 // Get the lowered operands. Note that we do this after 3074 // checking if NumResults is zero, because with zero results 3075 // the operands won't have values in the map. 3076 SDValue Src = getValue(SrcV); 3077 SDValue Ptr = getValue(PtrV); 3078 3079 SDValue Root = getRoot(); 3080 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3081 NumValues)); 3082 EVT PtrVT = Ptr.getValueType(); 3083 bool isVolatile = I.isVolatile(); 3084 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3085 unsigned Alignment = I.getAlignment(); 3086 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3087 3088 unsigned ChainI = 0; 3089 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3090 // See visitLoad comments. 3091 if (ChainI == MaxParallelChains) { 3092 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3093 MVT::Other, &Chains[0], ChainI); 3094 Root = Chain; 3095 ChainI = 0; 3096 } 3097 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3098 DAG.getConstant(Offsets[i], PtrVT)); 3099 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3100 SDValue(Src.getNode(), Src.getResNo() + i), 3101 Add, MachinePointerInfo(PtrV, Offsets[i]), 3102 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3103 Chains[ChainI] = St; 3104 } 3105 3106 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3107 MVT::Other, &Chains[0], ChainI); 3108 ++SDNodeOrder; 3109 AssignOrderingToNode(StoreNode.getNode()); 3110 DAG.setRoot(StoreNode); 3111} 3112 3113/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3114/// node. 3115void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3116 unsigned Intrinsic) { 3117 bool HasChain = !I.doesNotAccessMemory(); 3118 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3119 3120 // Build the operand list. 3121 SmallVector<SDValue, 8> Ops; 3122 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3123 if (OnlyLoad) { 3124 // We don't need to serialize loads against other loads. 3125 Ops.push_back(DAG.getRoot()); 3126 } else { 3127 Ops.push_back(getRoot()); 3128 } 3129 } 3130 3131 // Info is set by getTgtMemInstrinsic 3132 TargetLowering::IntrinsicInfo Info; 3133 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3134 3135 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3136 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3137 Info.opc == ISD::INTRINSIC_W_CHAIN) 3138 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3139 3140 // Add all operands of the call to the operand list. 3141 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3142 SDValue Op = getValue(I.getArgOperand(i)); 3143 assert(TLI.isTypeLegal(Op.getValueType()) && 3144 "Intrinsic uses a non-legal type?"); 3145 Ops.push_back(Op); 3146 } 3147 3148 SmallVector<EVT, 4> ValueVTs; 3149 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3150#ifndef NDEBUG 3151 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3152 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3153 "Intrinsic uses a non-legal type?"); 3154 } 3155#endif // NDEBUG 3156 3157 if (HasChain) 3158 ValueVTs.push_back(MVT::Other); 3159 3160 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3161 3162 // Create the node. 3163 SDValue Result; 3164 if (IsTgtIntrinsic) { 3165 // This is target intrinsic that touches memory 3166 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3167 VTs, &Ops[0], Ops.size(), 3168 Info.memVT, 3169 MachinePointerInfo(Info.ptrVal, Info.offset), 3170 Info.align, Info.vol, 3171 Info.readMem, Info.writeMem); 3172 } else if (!HasChain) { 3173 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3174 VTs, &Ops[0], Ops.size()); 3175 } else if (!I.getType()->isVoidTy()) { 3176 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3177 VTs, &Ops[0], Ops.size()); 3178 } else { 3179 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3180 VTs, &Ops[0], Ops.size()); 3181 } 3182 3183 if (HasChain) { 3184 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3185 if (OnlyLoad) 3186 PendingLoads.push_back(Chain); 3187 else 3188 DAG.setRoot(Chain); 3189 } 3190 3191 if (!I.getType()->isVoidTy()) { 3192 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3193 EVT VT = TLI.getValueType(PTy); 3194 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3195 } 3196 3197 setValue(&I, Result); 3198 } 3199} 3200 3201/// GetSignificand - Get the significand and build it into a floating-point 3202/// number with exponent of 1: 3203/// 3204/// Op = (Op & 0x007fffff) | 0x3f800000; 3205/// 3206/// where Op is the hexidecimal representation of floating point value. 3207static SDValue 3208GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3209 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3210 DAG.getConstant(0x007fffff, MVT::i32)); 3211 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3212 DAG.getConstant(0x3f800000, MVT::i32)); 3213 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3214} 3215 3216/// GetExponent - Get the exponent: 3217/// 3218/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3219/// 3220/// where Op is the hexidecimal representation of floating point value. 3221static SDValue 3222GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3223 DebugLoc dl) { 3224 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3225 DAG.getConstant(0x7f800000, MVT::i32)); 3226 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3227 DAG.getConstant(23, TLI.getPointerTy())); 3228 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3229 DAG.getConstant(127, MVT::i32)); 3230 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3231} 3232 3233/// getF32Constant - Get 32-bit floating point constant. 3234static SDValue 3235getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3236 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3237} 3238 3239/// Inlined utility function to implement binary input atomic intrinsics for 3240/// visitIntrinsicCall: I is a call instruction 3241/// Op is the associated NodeType for I 3242const char * 3243SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3244 ISD::NodeType Op) { 3245 SDValue Root = getRoot(); 3246 SDValue L = 3247 DAG.getAtomic(Op, getCurDebugLoc(), 3248 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3249 Root, 3250 getValue(I.getArgOperand(0)), 3251 getValue(I.getArgOperand(1)), 3252 I.getArgOperand(0)); 3253 setValue(&I, L); 3254 DAG.setRoot(L.getValue(1)); 3255 return 0; 3256} 3257 3258// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3259const char * 3260SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3261 SDValue Op1 = getValue(I.getArgOperand(0)); 3262 SDValue Op2 = getValue(I.getArgOperand(1)); 3263 3264 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3265 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3266 return 0; 3267} 3268 3269/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3270/// limited-precision mode. 3271void 3272SelectionDAGBuilder::visitExp(const CallInst &I) { 3273 SDValue result; 3274 DebugLoc dl = getCurDebugLoc(); 3275 3276 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3277 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3278 SDValue Op = getValue(I.getArgOperand(0)); 3279 3280 // Put the exponent in the right bit position for later addition to the 3281 // final result: 3282 // 3283 // #define LOG2OFe 1.4426950f 3284 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3285 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3286 getF32Constant(DAG, 0x3fb8aa3b)); 3287 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3288 3289 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3290 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3291 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3292 3293 // IntegerPartOfX <<= 23; 3294 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3295 DAG.getConstant(23, TLI.getPointerTy())); 3296 3297 if (LimitFloatPrecision <= 6) { 3298 // For floating-point precision of 6: 3299 // 3300 // TwoToFractionalPartOfX = 3301 // 0.997535578f + 3302 // (0.735607626f + 0.252464424f * x) * x; 3303 // 3304 // error 0.0144103317, which is 6 bits 3305 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3306 getF32Constant(DAG, 0x3e814304)); 3307 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3308 getF32Constant(DAG, 0x3f3c50c8)); 3309 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3310 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3311 getF32Constant(DAG, 0x3f7f5e7e)); 3312 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3313 3314 // Add the exponent into the result in integer domain. 3315 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3316 TwoToFracPartOfX, IntegerPartOfX); 3317 3318 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3319 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3320 // For floating-point precision of 12: 3321 // 3322 // TwoToFractionalPartOfX = 3323 // 0.999892986f + 3324 // (0.696457318f + 3325 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3326 // 3327 // 0.000107046256 error, which is 13 to 14 bits 3328 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3329 getF32Constant(DAG, 0x3da235e3)); 3330 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3331 getF32Constant(DAG, 0x3e65b8f3)); 3332 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3333 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3334 getF32Constant(DAG, 0x3f324b07)); 3335 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3336 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3337 getF32Constant(DAG, 0x3f7ff8fd)); 3338 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3339 3340 // Add the exponent into the result in integer domain. 3341 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3342 TwoToFracPartOfX, IntegerPartOfX); 3343 3344 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3345 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3346 // For floating-point precision of 18: 3347 // 3348 // TwoToFractionalPartOfX = 3349 // 0.999999982f + 3350 // (0.693148872f + 3351 // (0.240227044f + 3352 // (0.554906021e-1f + 3353 // (0.961591928e-2f + 3354 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3355 // 3356 // error 2.47208000*10^(-7), which is better than 18 bits 3357 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3358 getF32Constant(DAG, 0x3924b03e)); 3359 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3360 getF32Constant(DAG, 0x3ab24b87)); 3361 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3362 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3363 getF32Constant(DAG, 0x3c1d8c17)); 3364 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3365 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3366 getF32Constant(DAG, 0x3d634a1d)); 3367 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3368 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3369 getF32Constant(DAG, 0x3e75fe14)); 3370 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3371 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3372 getF32Constant(DAG, 0x3f317234)); 3373 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3374 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3375 getF32Constant(DAG, 0x3f800000)); 3376 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3377 MVT::i32, t13); 3378 3379 // Add the exponent into the result in integer domain. 3380 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3381 TwoToFracPartOfX, IntegerPartOfX); 3382 3383 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3384 } 3385 } else { 3386 // No special expansion. 3387 result = DAG.getNode(ISD::FEXP, dl, 3388 getValue(I.getArgOperand(0)).getValueType(), 3389 getValue(I.getArgOperand(0))); 3390 } 3391 3392 setValue(&I, result); 3393} 3394 3395/// visitLog - Lower a log intrinsic. Handles the special sequences for 3396/// limited-precision mode. 3397void 3398SelectionDAGBuilder::visitLog(const CallInst &I) { 3399 SDValue result; 3400 DebugLoc dl = getCurDebugLoc(); 3401 3402 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3403 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3404 SDValue Op = getValue(I.getArgOperand(0)); 3405 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3406 3407 // Scale the exponent by log(2) [0.69314718f]. 3408 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3409 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3410 getF32Constant(DAG, 0x3f317218)); 3411 3412 // Get the significand and build it into a floating-point number with 3413 // exponent of 1. 3414 SDValue X = GetSignificand(DAG, Op1, dl); 3415 3416 if (LimitFloatPrecision <= 6) { 3417 // For floating-point precision of 6: 3418 // 3419 // LogofMantissa = 3420 // -1.1609546f + 3421 // (1.4034025f - 0.23903021f * x) * x; 3422 // 3423 // error 0.0034276066, which is better than 8 bits 3424 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3425 getF32Constant(DAG, 0xbe74c456)); 3426 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3427 getF32Constant(DAG, 0x3fb3a2b1)); 3428 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3429 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3430 getF32Constant(DAG, 0x3f949a29)); 3431 3432 result = DAG.getNode(ISD::FADD, dl, 3433 MVT::f32, LogOfExponent, LogOfMantissa); 3434 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3435 // For floating-point precision of 12: 3436 // 3437 // LogOfMantissa = 3438 // -1.7417939f + 3439 // (2.8212026f + 3440 // (-1.4699568f + 3441 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3442 // 3443 // error 0.000061011436, which is 14 bits 3444 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3445 getF32Constant(DAG, 0xbd67b6d6)); 3446 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3447 getF32Constant(DAG, 0x3ee4f4b8)); 3448 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3449 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3450 getF32Constant(DAG, 0x3fbc278b)); 3451 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3452 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3453 getF32Constant(DAG, 0x40348e95)); 3454 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3455 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3456 getF32Constant(DAG, 0x3fdef31a)); 3457 3458 result = DAG.getNode(ISD::FADD, dl, 3459 MVT::f32, LogOfExponent, LogOfMantissa); 3460 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3461 // For floating-point precision of 18: 3462 // 3463 // LogOfMantissa = 3464 // -2.1072184f + 3465 // (4.2372794f + 3466 // (-3.7029485f + 3467 // (2.2781945f + 3468 // (-0.87823314f + 3469 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3470 // 3471 // error 0.0000023660568, which is better than 18 bits 3472 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3473 getF32Constant(DAG, 0xbc91e5ac)); 3474 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3475 getF32Constant(DAG, 0x3e4350aa)); 3476 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3477 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3478 getF32Constant(DAG, 0x3f60d3e3)); 3479 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3480 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3481 getF32Constant(DAG, 0x4011cdf0)); 3482 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3483 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3484 getF32Constant(DAG, 0x406cfd1c)); 3485 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3486 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3487 getF32Constant(DAG, 0x408797cb)); 3488 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3489 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3490 getF32Constant(DAG, 0x4006dcab)); 3491 3492 result = DAG.getNode(ISD::FADD, dl, 3493 MVT::f32, LogOfExponent, LogOfMantissa); 3494 } 3495 } else { 3496 // No special expansion. 3497 result = DAG.getNode(ISD::FLOG, dl, 3498 getValue(I.getArgOperand(0)).getValueType(), 3499 getValue(I.getArgOperand(0))); 3500 } 3501 3502 setValue(&I, result); 3503} 3504 3505/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3506/// limited-precision mode. 3507void 3508SelectionDAGBuilder::visitLog2(const CallInst &I) { 3509 SDValue result; 3510 DebugLoc dl = getCurDebugLoc(); 3511 3512 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3513 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3514 SDValue Op = getValue(I.getArgOperand(0)); 3515 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3516 3517 // Get the exponent. 3518 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3519 3520 // Get the significand and build it into a floating-point number with 3521 // exponent of 1. 3522 SDValue X = GetSignificand(DAG, Op1, dl); 3523 3524 // Different possible minimax approximations of significand in 3525 // floating-point for various degrees of accuracy over [1,2]. 3526 if (LimitFloatPrecision <= 6) { 3527 // For floating-point precision of 6: 3528 // 3529 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3530 // 3531 // error 0.0049451742, which is more than 7 bits 3532 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3533 getF32Constant(DAG, 0xbeb08fe0)); 3534 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3535 getF32Constant(DAG, 0x40019463)); 3536 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3537 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3538 getF32Constant(DAG, 0x3fd6633d)); 3539 3540 result = DAG.getNode(ISD::FADD, dl, 3541 MVT::f32, LogOfExponent, Log2ofMantissa); 3542 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3543 // For floating-point precision of 12: 3544 // 3545 // Log2ofMantissa = 3546 // -2.51285454f + 3547 // (4.07009056f + 3548 // (-2.12067489f + 3549 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3550 // 3551 // error 0.0000876136000, which is better than 13 bits 3552 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3553 getF32Constant(DAG, 0xbda7262e)); 3554 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3555 getF32Constant(DAG, 0x3f25280b)); 3556 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3557 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3558 getF32Constant(DAG, 0x4007b923)); 3559 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3560 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3561 getF32Constant(DAG, 0x40823e2f)); 3562 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3563 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3564 getF32Constant(DAG, 0x4020d29c)); 3565 3566 result = DAG.getNode(ISD::FADD, dl, 3567 MVT::f32, LogOfExponent, Log2ofMantissa); 3568 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3569 // For floating-point precision of 18: 3570 // 3571 // Log2ofMantissa = 3572 // -3.0400495f + 3573 // (6.1129976f + 3574 // (-5.3420409f + 3575 // (3.2865683f + 3576 // (-1.2669343f + 3577 // (0.27515199f - 3578 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3579 // 3580 // error 0.0000018516, which is better than 18 bits 3581 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3582 getF32Constant(DAG, 0xbcd2769e)); 3583 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3584 getF32Constant(DAG, 0x3e8ce0b9)); 3585 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3586 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3587 getF32Constant(DAG, 0x3fa22ae7)); 3588 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3589 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3590 getF32Constant(DAG, 0x40525723)); 3591 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3592 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3593 getF32Constant(DAG, 0x40aaf200)); 3594 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3595 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3596 getF32Constant(DAG, 0x40c39dad)); 3597 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3598 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3599 getF32Constant(DAG, 0x4042902c)); 3600 3601 result = DAG.getNode(ISD::FADD, dl, 3602 MVT::f32, LogOfExponent, Log2ofMantissa); 3603 } 3604 } else { 3605 // No special expansion. 3606 result = DAG.getNode(ISD::FLOG2, dl, 3607 getValue(I.getArgOperand(0)).getValueType(), 3608 getValue(I.getArgOperand(0))); 3609 } 3610 3611 setValue(&I, result); 3612} 3613 3614/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3615/// limited-precision mode. 3616void 3617SelectionDAGBuilder::visitLog10(const CallInst &I) { 3618 SDValue result; 3619 DebugLoc dl = getCurDebugLoc(); 3620 3621 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3622 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3623 SDValue Op = getValue(I.getArgOperand(0)); 3624 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3625 3626 // Scale the exponent by log10(2) [0.30102999f]. 3627 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3628 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3629 getF32Constant(DAG, 0x3e9a209a)); 3630 3631 // Get the significand and build it into a floating-point number with 3632 // exponent of 1. 3633 SDValue X = GetSignificand(DAG, Op1, dl); 3634 3635 if (LimitFloatPrecision <= 6) { 3636 // For floating-point precision of 6: 3637 // 3638 // Log10ofMantissa = 3639 // -0.50419619f + 3640 // (0.60948995f - 0.10380950f * x) * x; 3641 // 3642 // error 0.0014886165, which is 6 bits 3643 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3644 getF32Constant(DAG, 0xbdd49a13)); 3645 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3646 getF32Constant(DAG, 0x3f1c0789)); 3647 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3648 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3649 getF32Constant(DAG, 0x3f011300)); 3650 3651 result = DAG.getNode(ISD::FADD, dl, 3652 MVT::f32, LogOfExponent, Log10ofMantissa); 3653 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3654 // For floating-point precision of 12: 3655 // 3656 // Log10ofMantissa = 3657 // -0.64831180f + 3658 // (0.91751397f + 3659 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3660 // 3661 // error 0.00019228036, which is better than 12 bits 3662 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3663 getF32Constant(DAG, 0x3d431f31)); 3664 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3665 getF32Constant(DAG, 0x3ea21fb2)); 3666 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3667 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3668 getF32Constant(DAG, 0x3f6ae232)); 3669 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3670 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3671 getF32Constant(DAG, 0x3f25f7c3)); 3672 3673 result = DAG.getNode(ISD::FADD, dl, 3674 MVT::f32, LogOfExponent, Log10ofMantissa); 3675 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3676 // For floating-point precision of 18: 3677 // 3678 // Log10ofMantissa = 3679 // -0.84299375f + 3680 // (1.5327582f + 3681 // (-1.0688956f + 3682 // (0.49102474f + 3683 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3684 // 3685 // error 0.0000037995730, which is better than 18 bits 3686 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3687 getF32Constant(DAG, 0x3c5d51ce)); 3688 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3689 getF32Constant(DAG, 0x3e00685a)); 3690 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3691 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3692 getF32Constant(DAG, 0x3efb6798)); 3693 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3694 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3695 getF32Constant(DAG, 0x3f88d192)); 3696 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3697 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3698 getF32Constant(DAG, 0x3fc4316c)); 3699 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3700 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3701 getF32Constant(DAG, 0x3f57ce70)); 3702 3703 result = DAG.getNode(ISD::FADD, dl, 3704 MVT::f32, LogOfExponent, Log10ofMantissa); 3705 } 3706 } else { 3707 // No special expansion. 3708 result = DAG.getNode(ISD::FLOG10, dl, 3709 getValue(I.getArgOperand(0)).getValueType(), 3710 getValue(I.getArgOperand(0))); 3711 } 3712 3713 setValue(&I, result); 3714} 3715 3716/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3717/// limited-precision mode. 3718void 3719SelectionDAGBuilder::visitExp2(const CallInst &I) { 3720 SDValue result; 3721 DebugLoc dl = getCurDebugLoc(); 3722 3723 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3724 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3725 SDValue Op = getValue(I.getArgOperand(0)); 3726 3727 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3728 3729 // FractionalPartOfX = x - (float)IntegerPartOfX; 3730 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3731 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3732 3733 // IntegerPartOfX <<= 23; 3734 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3735 DAG.getConstant(23, TLI.getPointerTy())); 3736 3737 if (LimitFloatPrecision <= 6) { 3738 // For floating-point precision of 6: 3739 // 3740 // TwoToFractionalPartOfX = 3741 // 0.997535578f + 3742 // (0.735607626f + 0.252464424f * x) * x; 3743 // 3744 // error 0.0144103317, which is 6 bits 3745 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3746 getF32Constant(DAG, 0x3e814304)); 3747 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3748 getF32Constant(DAG, 0x3f3c50c8)); 3749 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3750 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3751 getF32Constant(DAG, 0x3f7f5e7e)); 3752 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3753 SDValue TwoToFractionalPartOfX = 3754 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3755 3756 result = DAG.getNode(ISD::BITCAST, dl, 3757 MVT::f32, TwoToFractionalPartOfX); 3758 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3759 // For floating-point precision of 12: 3760 // 3761 // TwoToFractionalPartOfX = 3762 // 0.999892986f + 3763 // (0.696457318f + 3764 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3765 // 3766 // error 0.000107046256, which is 13 to 14 bits 3767 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3768 getF32Constant(DAG, 0x3da235e3)); 3769 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3770 getF32Constant(DAG, 0x3e65b8f3)); 3771 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3772 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3773 getF32Constant(DAG, 0x3f324b07)); 3774 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3775 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3776 getF32Constant(DAG, 0x3f7ff8fd)); 3777 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3778 SDValue TwoToFractionalPartOfX = 3779 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3780 3781 result = DAG.getNode(ISD::BITCAST, dl, 3782 MVT::f32, TwoToFractionalPartOfX); 3783 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3784 // For floating-point precision of 18: 3785 // 3786 // TwoToFractionalPartOfX = 3787 // 0.999999982f + 3788 // (0.693148872f + 3789 // (0.240227044f + 3790 // (0.554906021e-1f + 3791 // (0.961591928e-2f + 3792 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3793 // error 2.47208000*10^(-7), which is better than 18 bits 3794 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3795 getF32Constant(DAG, 0x3924b03e)); 3796 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3797 getF32Constant(DAG, 0x3ab24b87)); 3798 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3799 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3800 getF32Constant(DAG, 0x3c1d8c17)); 3801 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3802 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3803 getF32Constant(DAG, 0x3d634a1d)); 3804 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3805 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3806 getF32Constant(DAG, 0x3e75fe14)); 3807 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3808 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3809 getF32Constant(DAG, 0x3f317234)); 3810 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3811 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3812 getF32Constant(DAG, 0x3f800000)); 3813 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 3814 SDValue TwoToFractionalPartOfX = 3815 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3816 3817 result = DAG.getNode(ISD::BITCAST, dl, 3818 MVT::f32, TwoToFractionalPartOfX); 3819 } 3820 } else { 3821 // No special expansion. 3822 result = DAG.getNode(ISD::FEXP2, dl, 3823 getValue(I.getArgOperand(0)).getValueType(), 3824 getValue(I.getArgOperand(0))); 3825 } 3826 3827 setValue(&I, result); 3828} 3829 3830/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3831/// limited-precision mode with x == 10.0f. 3832void 3833SelectionDAGBuilder::visitPow(const CallInst &I) { 3834 SDValue result; 3835 const Value *Val = I.getArgOperand(0); 3836 DebugLoc dl = getCurDebugLoc(); 3837 bool IsExp10 = false; 3838 3839 if (getValue(Val).getValueType() == MVT::f32 && 3840 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 3841 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3842 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3843 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3844 APFloat Ten(10.0f); 3845 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3846 } 3847 } 3848 } 3849 3850 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3851 SDValue Op = getValue(I.getArgOperand(1)); 3852 3853 // Put the exponent in the right bit position for later addition to the 3854 // final result: 3855 // 3856 // #define LOG2OF10 3.3219281f 3857 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3858 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3859 getF32Constant(DAG, 0x40549a78)); 3860 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3861 3862 // FractionalPartOfX = x - (float)IntegerPartOfX; 3863 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3864 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3865 3866 // IntegerPartOfX <<= 23; 3867 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3868 DAG.getConstant(23, TLI.getPointerTy())); 3869 3870 if (LimitFloatPrecision <= 6) { 3871 // For floating-point precision of 6: 3872 // 3873 // twoToFractionalPartOfX = 3874 // 0.997535578f + 3875 // (0.735607626f + 0.252464424f * x) * x; 3876 // 3877 // error 0.0144103317, which is 6 bits 3878 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3879 getF32Constant(DAG, 0x3e814304)); 3880 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3881 getF32Constant(DAG, 0x3f3c50c8)); 3882 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3883 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3884 getF32Constant(DAG, 0x3f7f5e7e)); 3885 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3886 SDValue TwoToFractionalPartOfX = 3887 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3888 3889 result = DAG.getNode(ISD::BITCAST, dl, 3890 MVT::f32, TwoToFractionalPartOfX); 3891 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3892 // For floating-point precision of 12: 3893 // 3894 // TwoToFractionalPartOfX = 3895 // 0.999892986f + 3896 // (0.696457318f + 3897 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3898 // 3899 // error 0.000107046256, which is 13 to 14 bits 3900 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3901 getF32Constant(DAG, 0x3da235e3)); 3902 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3903 getF32Constant(DAG, 0x3e65b8f3)); 3904 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3905 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3906 getF32Constant(DAG, 0x3f324b07)); 3907 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3908 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3909 getF32Constant(DAG, 0x3f7ff8fd)); 3910 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3911 SDValue TwoToFractionalPartOfX = 3912 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3913 3914 result = DAG.getNode(ISD::BITCAST, dl, 3915 MVT::f32, TwoToFractionalPartOfX); 3916 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3917 // For floating-point precision of 18: 3918 // 3919 // TwoToFractionalPartOfX = 3920 // 0.999999982f + 3921 // (0.693148872f + 3922 // (0.240227044f + 3923 // (0.554906021e-1f + 3924 // (0.961591928e-2f + 3925 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3926 // error 2.47208000*10^(-7), which is better than 18 bits 3927 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3928 getF32Constant(DAG, 0x3924b03e)); 3929 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3930 getF32Constant(DAG, 0x3ab24b87)); 3931 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3932 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3933 getF32Constant(DAG, 0x3c1d8c17)); 3934 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3935 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3936 getF32Constant(DAG, 0x3d634a1d)); 3937 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3938 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3939 getF32Constant(DAG, 0x3e75fe14)); 3940 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3941 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3942 getF32Constant(DAG, 0x3f317234)); 3943 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3944 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3945 getF32Constant(DAG, 0x3f800000)); 3946 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 3947 SDValue TwoToFractionalPartOfX = 3948 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3949 3950 result = DAG.getNode(ISD::BITCAST, dl, 3951 MVT::f32, TwoToFractionalPartOfX); 3952 } 3953 } else { 3954 // No special expansion. 3955 result = DAG.getNode(ISD::FPOW, dl, 3956 getValue(I.getArgOperand(0)).getValueType(), 3957 getValue(I.getArgOperand(0)), 3958 getValue(I.getArgOperand(1))); 3959 } 3960 3961 setValue(&I, result); 3962} 3963 3964 3965/// ExpandPowI - Expand a llvm.powi intrinsic. 3966static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 3967 SelectionDAG &DAG) { 3968 // If RHS is a constant, we can expand this out to a multiplication tree, 3969 // otherwise we end up lowering to a call to __powidf2 (for example). When 3970 // optimizing for size, we only want to do this if the expansion would produce 3971 // a small number of multiplies, otherwise we do the full expansion. 3972 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3973 // Get the exponent as a positive value. 3974 unsigned Val = RHSC->getSExtValue(); 3975 if ((int)Val < 0) Val = -Val; 3976 3977 // powi(x, 0) -> 1.0 3978 if (Val == 0) 3979 return DAG.getConstantFP(1.0, LHS.getValueType()); 3980 3981 const Function *F = DAG.getMachineFunction().getFunction(); 3982 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 3983 // If optimizing for size, don't insert too many multiplies. This 3984 // inserts up to 5 multiplies. 3985 CountPopulation_32(Val)+Log2_32(Val) < 7) { 3986 // We use the simple binary decomposition method to generate the multiply 3987 // sequence. There are more optimal ways to do this (for example, 3988 // powi(x,15) generates one more multiply than it should), but this has 3989 // the benefit of being both really simple and much better than a libcall. 3990 SDValue Res; // Logically starts equal to 1.0 3991 SDValue CurSquare = LHS; 3992 while (Val) { 3993 if (Val & 1) { 3994 if (Res.getNode()) 3995 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 3996 else 3997 Res = CurSquare; // 1.0*CurSquare. 3998 } 3999 4000 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4001 CurSquare, CurSquare); 4002 Val >>= 1; 4003 } 4004 4005 // If the original was negative, invert the result, producing 1/(x*x*x). 4006 if (RHSC->getSExtValue() < 0) 4007 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4008 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4009 return Res; 4010 } 4011 } 4012 4013 // Otherwise, expand to a libcall. 4014 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4015} 4016 4017/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4018/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4019/// At the end of instruction selection, they will be inserted to the entry BB. 4020bool 4021SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4022 int64_t Offset, 4023 const SDValue &N) { 4024 const Argument *Arg = dyn_cast<Argument>(V); 4025 if (!Arg) 4026 return false; 4027 4028 MachineFunction &MF = DAG.getMachineFunction(); 4029 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4030 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4031 4032 // Ignore inlined function arguments here. 4033 DIVariable DV(Variable); 4034 if (DV.isInlinedFnArgument(MF.getFunction())) 4035 return false; 4036 4037 MachineBasicBlock *MBB = FuncInfo.MBB; 4038 if (MBB != &MF.front()) 4039 return false; 4040 4041 unsigned Reg = 0; 4042 if (Arg->hasByValAttr()) { 4043 // Byval arguments' frame index is recorded during argument lowering. 4044 // Use this info directly. 4045 Reg = TRI->getFrameRegister(MF); 4046 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 4047 // If byval argument ofset is not recorded then ignore this. 4048 if (!Offset) 4049 Reg = 0; 4050 } 4051 4052 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) { 4053 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4054 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 4055 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4056 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4057 if (PR) 4058 Reg = PR; 4059 } 4060 } 4061 4062 if (!Reg) { 4063 // Check if ValueMap has reg number. 4064 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4065 if (VMI != FuncInfo.ValueMap.end()) 4066 Reg = VMI->second; 4067 } 4068 4069 if (!Reg && N.getNode()) { 4070 // Check if frame index is available. 4071 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4072 if (FrameIndexSDNode *FINode = 4073 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4074 Reg = TRI->getFrameRegister(MF); 4075 Offset = FINode->getIndex(); 4076 } 4077 } 4078 4079 if (!Reg) 4080 return false; 4081 4082 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4083 TII->get(TargetOpcode::DBG_VALUE)) 4084 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4085 FuncInfo.ArgDbgValues.push_back(&*MIB); 4086 return true; 4087} 4088 4089// VisualStudio defines setjmp as _setjmp 4090#if defined(_MSC_VER) && defined(setjmp) && \ 4091 !defined(setjmp_undefined_for_msvc) 4092# pragma push_macro("setjmp") 4093# undef setjmp 4094# define setjmp_undefined_for_msvc 4095#endif 4096 4097/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4098/// we want to emit this as a call to a named external function, return the name 4099/// otherwise lower it and return null. 4100const char * 4101SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4102 DebugLoc dl = getCurDebugLoc(); 4103 SDValue Res; 4104 4105 switch (Intrinsic) { 4106 default: 4107 // By default, turn this into a target intrinsic node. 4108 visitTargetIntrinsic(I, Intrinsic); 4109 return 0; 4110 case Intrinsic::vastart: visitVAStart(I); return 0; 4111 case Intrinsic::vaend: visitVAEnd(I); return 0; 4112 case Intrinsic::vacopy: visitVACopy(I); return 0; 4113 case Intrinsic::returnaddress: 4114 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4115 getValue(I.getArgOperand(0)))); 4116 return 0; 4117 case Intrinsic::frameaddress: 4118 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4119 getValue(I.getArgOperand(0)))); 4120 return 0; 4121 case Intrinsic::setjmp: 4122 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4123 case Intrinsic::longjmp: 4124 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4125 case Intrinsic::memcpy: { 4126 // Assert for address < 256 since we support only user defined address 4127 // spaces. 4128 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4129 < 256 && 4130 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4131 < 256 && 4132 "Unknown address space"); 4133 SDValue Op1 = getValue(I.getArgOperand(0)); 4134 SDValue Op2 = getValue(I.getArgOperand(1)); 4135 SDValue Op3 = getValue(I.getArgOperand(2)); 4136 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4137 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4138 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4139 MachinePointerInfo(I.getArgOperand(0)), 4140 MachinePointerInfo(I.getArgOperand(1)))); 4141 return 0; 4142 } 4143 case Intrinsic::memset: { 4144 // Assert for address < 256 since we support only user defined address 4145 // spaces. 4146 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4147 < 256 && 4148 "Unknown address space"); 4149 SDValue Op1 = getValue(I.getArgOperand(0)); 4150 SDValue Op2 = getValue(I.getArgOperand(1)); 4151 SDValue Op3 = getValue(I.getArgOperand(2)); 4152 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4153 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4154 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4155 MachinePointerInfo(I.getArgOperand(0)))); 4156 return 0; 4157 } 4158 case Intrinsic::memmove: { 4159 // Assert for address < 256 since we support only user defined address 4160 // spaces. 4161 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4162 < 256 && 4163 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4164 < 256 && 4165 "Unknown address space"); 4166 SDValue Op1 = getValue(I.getArgOperand(0)); 4167 SDValue Op2 = getValue(I.getArgOperand(1)); 4168 SDValue Op3 = getValue(I.getArgOperand(2)); 4169 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4170 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4171 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4172 MachinePointerInfo(I.getArgOperand(0)), 4173 MachinePointerInfo(I.getArgOperand(1)))); 4174 return 0; 4175 } 4176 case Intrinsic::dbg_declare: { 4177 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4178 MDNode *Variable = DI.getVariable(); 4179 const Value *Address = DI.getAddress(); 4180 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4181 return 0; 4182 4183 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4184 // but do not always have a corresponding SDNode built. The SDNodeOrder 4185 // absolute, but not relative, values are different depending on whether 4186 // debug info exists. 4187 ++SDNodeOrder; 4188 4189 // Check if address has undef value. 4190 if (isa<UndefValue>(Address) || 4191 (Address->use_empty() && !isa<Argument>(Address))) { 4192 DEBUG(dbgs() << "Dropping debug info for " << DI); 4193 return 0; 4194 } 4195 4196 SDValue &N = NodeMap[Address]; 4197 if (!N.getNode() && isa<Argument>(Address)) 4198 // Check unused arguments map. 4199 N = UnusedArgNodeMap[Address]; 4200 SDDbgValue *SDV; 4201 if (N.getNode()) { 4202 // Parameters are handled specially. 4203 bool isParameter = 4204 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4205 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4206 Address = BCI->getOperand(0); 4207 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4208 4209 if (isParameter && !AI) { 4210 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4211 if (FINode) 4212 // Byval parameter. We have a frame index at this point. 4213 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4214 0, dl, SDNodeOrder); 4215 else { 4216 // Can't do anything with other non-AI cases yet. This might be a 4217 // parameter of a callee function that got inlined, for example. 4218 DEBUG(dbgs() << "Dropping debug info for " << DI); 4219 return 0; 4220 } 4221 } else if (AI) 4222 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4223 0, dl, SDNodeOrder); 4224 else { 4225 // Can't do anything with other non-AI cases yet. 4226 DEBUG(dbgs() << "Dropping debug info for " << DI); 4227 return 0; 4228 } 4229 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4230 } else { 4231 // If Address is an argument then try to emit its dbg value using 4232 // virtual register info from the FuncInfo.ValueMap. 4233 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4234 // If variable is pinned by a alloca in dominating bb then 4235 // use StaticAllocaMap. 4236 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4237 if (AI->getParent() != DI.getParent()) { 4238 DenseMap<const AllocaInst*, int>::iterator SI = 4239 FuncInfo.StaticAllocaMap.find(AI); 4240 if (SI != FuncInfo.StaticAllocaMap.end()) { 4241 SDV = DAG.getDbgValue(Variable, SI->second, 4242 0, dl, SDNodeOrder); 4243 DAG.AddDbgValue(SDV, 0, false); 4244 return 0; 4245 } 4246 } 4247 } 4248 DEBUG(dbgs() << "Dropping debug info for " << DI); 4249 } 4250 } 4251 return 0; 4252 } 4253 case Intrinsic::dbg_value: { 4254 const DbgValueInst &DI = cast<DbgValueInst>(I); 4255 if (!DIVariable(DI.getVariable()).Verify()) 4256 return 0; 4257 4258 MDNode *Variable = DI.getVariable(); 4259 uint64_t Offset = DI.getOffset(); 4260 const Value *V = DI.getValue(); 4261 if (!V) 4262 return 0; 4263 4264 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4265 // but do not always have a corresponding SDNode built. The SDNodeOrder 4266 // absolute, but not relative, values are different depending on whether 4267 // debug info exists. 4268 ++SDNodeOrder; 4269 SDDbgValue *SDV; 4270 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4271 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4272 DAG.AddDbgValue(SDV, 0, false); 4273 } else { 4274 // Do not use getValue() in here; we don't want to generate code at 4275 // this point if it hasn't been done yet. 4276 SDValue N = NodeMap[V]; 4277 if (!N.getNode() && isa<Argument>(V)) 4278 // Check unused arguments map. 4279 N = UnusedArgNodeMap[V]; 4280 if (N.getNode()) { 4281 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4282 SDV = DAG.getDbgValue(Variable, N.getNode(), 4283 N.getResNo(), Offset, dl, SDNodeOrder); 4284 DAG.AddDbgValue(SDV, N.getNode(), false); 4285 } 4286 } else if (!V->use_empty() ) { 4287 // Do not call getValue(V) yet, as we don't want to generate code. 4288 // Remember it for later. 4289 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4290 DanglingDebugInfoMap[V] = DDI; 4291 } else { 4292 // We may expand this to cover more cases. One case where we have no 4293 // data available is an unreferenced parameter. 4294 DEBUG(dbgs() << "Dropping debug info for " << DI); 4295 } 4296 } 4297 4298 // Build a debug info table entry. 4299 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4300 V = BCI->getOperand(0); 4301 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4302 // Don't handle byval struct arguments or VLAs, for example. 4303 if (!AI) 4304 return 0; 4305 DenseMap<const AllocaInst*, int>::iterator SI = 4306 FuncInfo.StaticAllocaMap.find(AI); 4307 if (SI == FuncInfo.StaticAllocaMap.end()) 4308 return 0; // VLAs. 4309 int FI = SI->second; 4310 4311 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4312 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4313 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4314 return 0; 4315 } 4316 case Intrinsic::eh_exception: { 4317 // Insert the EXCEPTIONADDR instruction. 4318 assert(FuncInfo.MBB->isLandingPad() && 4319 "Call to eh.exception not in landing pad!"); 4320 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4321 SDValue Ops[1]; 4322 Ops[0] = DAG.getRoot(); 4323 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4324 setValue(&I, Op); 4325 DAG.setRoot(Op.getValue(1)); 4326 return 0; 4327 } 4328 4329 case Intrinsic::eh_selector: { 4330 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4331 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4332 if (CallMBB->isLandingPad()) 4333 AddCatchInfo(I, &MMI, CallMBB); 4334 else { 4335#ifndef NDEBUG 4336 FuncInfo.CatchInfoLost.insert(&I); 4337#endif 4338 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4339 unsigned Reg = TLI.getExceptionSelectorRegister(); 4340 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4341 } 4342 4343 // Insert the EHSELECTION instruction. 4344 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4345 SDValue Ops[2]; 4346 Ops[0] = getValue(I.getArgOperand(0)); 4347 Ops[1] = getRoot(); 4348 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4349 DAG.setRoot(Op.getValue(1)); 4350 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4351 return 0; 4352 } 4353 4354 case Intrinsic::eh_typeid_for: { 4355 // Find the type id for the given typeinfo. 4356 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4357 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4358 Res = DAG.getConstant(TypeID, MVT::i32); 4359 setValue(&I, Res); 4360 return 0; 4361 } 4362 4363 case Intrinsic::eh_return_i32: 4364 case Intrinsic::eh_return_i64: 4365 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4366 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4367 MVT::Other, 4368 getControlRoot(), 4369 getValue(I.getArgOperand(0)), 4370 getValue(I.getArgOperand(1)))); 4371 return 0; 4372 case Intrinsic::eh_unwind_init: 4373 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4374 return 0; 4375 case Intrinsic::eh_dwarf_cfa: { 4376 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4377 TLI.getPointerTy()); 4378 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4379 TLI.getPointerTy(), 4380 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4381 TLI.getPointerTy()), 4382 CfaArg); 4383 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4384 TLI.getPointerTy(), 4385 DAG.getConstant(0, TLI.getPointerTy())); 4386 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4387 FA, Offset)); 4388 return 0; 4389 } 4390 case Intrinsic::eh_sjlj_callsite: { 4391 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4392 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4393 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4394 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4395 4396 MMI.setCurrentCallSite(CI->getZExtValue()); 4397 return 0; 4398 } 4399 case Intrinsic::eh_sjlj_setjmp: { 4400 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4401 getValue(I.getArgOperand(0)))); 4402 return 0; 4403 } 4404 case Intrinsic::eh_sjlj_longjmp: { 4405 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4406 getRoot(), getValue(I.getArgOperand(0)))); 4407 return 0; 4408 } 4409 case Intrinsic::eh_sjlj_dispatch_setup: { 4410 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4411 getRoot(), getValue(I.getArgOperand(0)))); 4412 return 0; 4413 } 4414 4415 case Intrinsic::x86_mmx_pslli_w: 4416 case Intrinsic::x86_mmx_pslli_d: 4417 case Intrinsic::x86_mmx_pslli_q: 4418 case Intrinsic::x86_mmx_psrli_w: 4419 case Intrinsic::x86_mmx_psrli_d: 4420 case Intrinsic::x86_mmx_psrli_q: 4421 case Intrinsic::x86_mmx_psrai_w: 4422 case Intrinsic::x86_mmx_psrai_d: { 4423 SDValue ShAmt = getValue(I.getArgOperand(1)); 4424 if (isa<ConstantSDNode>(ShAmt)) { 4425 visitTargetIntrinsic(I, Intrinsic); 4426 return 0; 4427 } 4428 unsigned NewIntrinsic = 0; 4429 EVT ShAmtVT = MVT::v2i32; 4430 switch (Intrinsic) { 4431 case Intrinsic::x86_mmx_pslli_w: 4432 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4433 break; 4434 case Intrinsic::x86_mmx_pslli_d: 4435 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4436 break; 4437 case Intrinsic::x86_mmx_pslli_q: 4438 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4439 break; 4440 case Intrinsic::x86_mmx_psrli_w: 4441 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4442 break; 4443 case Intrinsic::x86_mmx_psrli_d: 4444 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4445 break; 4446 case Intrinsic::x86_mmx_psrli_q: 4447 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4448 break; 4449 case Intrinsic::x86_mmx_psrai_w: 4450 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4451 break; 4452 case Intrinsic::x86_mmx_psrai_d: 4453 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4454 break; 4455 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4456 } 4457 4458 // The vector shift intrinsics with scalars uses 32b shift amounts but 4459 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4460 // to be zero. 4461 // We must do this early because v2i32 is not a legal type. 4462 DebugLoc dl = getCurDebugLoc(); 4463 SDValue ShOps[2]; 4464 ShOps[0] = ShAmt; 4465 ShOps[1] = DAG.getConstant(0, MVT::i32); 4466 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4467 EVT DestVT = TLI.getValueType(I.getType()); 4468 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4469 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4470 DAG.getConstant(NewIntrinsic, MVT::i32), 4471 getValue(I.getArgOperand(0)), ShAmt); 4472 setValue(&I, Res); 4473 return 0; 4474 } 4475 case Intrinsic::convertff: 4476 case Intrinsic::convertfsi: 4477 case Intrinsic::convertfui: 4478 case Intrinsic::convertsif: 4479 case Intrinsic::convertuif: 4480 case Intrinsic::convertss: 4481 case Intrinsic::convertsu: 4482 case Intrinsic::convertus: 4483 case Intrinsic::convertuu: { 4484 ISD::CvtCode Code = ISD::CVT_INVALID; 4485 switch (Intrinsic) { 4486 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4487 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4488 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4489 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4490 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4491 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4492 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4493 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4494 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4495 } 4496 EVT DestVT = TLI.getValueType(I.getType()); 4497 const Value *Op1 = I.getArgOperand(0); 4498 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4499 DAG.getValueType(DestVT), 4500 DAG.getValueType(getValue(Op1).getValueType()), 4501 getValue(I.getArgOperand(1)), 4502 getValue(I.getArgOperand(2)), 4503 Code); 4504 setValue(&I, Res); 4505 return 0; 4506 } 4507 case Intrinsic::sqrt: 4508 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4509 getValue(I.getArgOperand(0)).getValueType(), 4510 getValue(I.getArgOperand(0)))); 4511 return 0; 4512 case Intrinsic::powi: 4513 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4514 getValue(I.getArgOperand(1)), DAG)); 4515 return 0; 4516 case Intrinsic::sin: 4517 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4518 getValue(I.getArgOperand(0)).getValueType(), 4519 getValue(I.getArgOperand(0)))); 4520 return 0; 4521 case Intrinsic::cos: 4522 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4523 getValue(I.getArgOperand(0)).getValueType(), 4524 getValue(I.getArgOperand(0)))); 4525 return 0; 4526 case Intrinsic::log: 4527 visitLog(I); 4528 return 0; 4529 case Intrinsic::log2: 4530 visitLog2(I); 4531 return 0; 4532 case Intrinsic::log10: 4533 visitLog10(I); 4534 return 0; 4535 case Intrinsic::exp: 4536 visitExp(I); 4537 return 0; 4538 case Intrinsic::exp2: 4539 visitExp2(I); 4540 return 0; 4541 case Intrinsic::pow: 4542 visitPow(I); 4543 return 0; 4544 case Intrinsic::convert_to_fp16: 4545 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4546 MVT::i16, getValue(I.getArgOperand(0)))); 4547 return 0; 4548 case Intrinsic::convert_from_fp16: 4549 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4550 MVT::f32, getValue(I.getArgOperand(0)))); 4551 return 0; 4552 case Intrinsic::pcmarker: { 4553 SDValue Tmp = getValue(I.getArgOperand(0)); 4554 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4555 return 0; 4556 } 4557 case Intrinsic::readcyclecounter: { 4558 SDValue Op = getRoot(); 4559 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4560 DAG.getVTList(MVT::i64, MVT::Other), 4561 &Op, 1); 4562 setValue(&I, Res); 4563 DAG.setRoot(Res.getValue(1)); 4564 return 0; 4565 } 4566 case Intrinsic::bswap: 4567 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4568 getValue(I.getArgOperand(0)).getValueType(), 4569 getValue(I.getArgOperand(0)))); 4570 return 0; 4571 case Intrinsic::cttz: { 4572 SDValue Arg = getValue(I.getArgOperand(0)); 4573 EVT Ty = Arg.getValueType(); 4574 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4575 return 0; 4576 } 4577 case Intrinsic::ctlz: { 4578 SDValue Arg = getValue(I.getArgOperand(0)); 4579 EVT Ty = Arg.getValueType(); 4580 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4581 return 0; 4582 } 4583 case Intrinsic::ctpop: { 4584 SDValue Arg = getValue(I.getArgOperand(0)); 4585 EVT Ty = Arg.getValueType(); 4586 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4587 return 0; 4588 } 4589 case Intrinsic::stacksave: { 4590 SDValue Op = getRoot(); 4591 Res = DAG.getNode(ISD::STACKSAVE, dl, 4592 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4593 setValue(&I, Res); 4594 DAG.setRoot(Res.getValue(1)); 4595 return 0; 4596 } 4597 case Intrinsic::stackrestore: { 4598 Res = getValue(I.getArgOperand(0)); 4599 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4600 return 0; 4601 } 4602 case Intrinsic::stackprotector: { 4603 // Emit code into the DAG to store the stack guard onto the stack. 4604 MachineFunction &MF = DAG.getMachineFunction(); 4605 MachineFrameInfo *MFI = MF.getFrameInfo(); 4606 EVT PtrTy = TLI.getPointerTy(); 4607 4608 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4609 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4610 4611 int FI = FuncInfo.StaticAllocaMap[Slot]; 4612 MFI->setStackProtectorIndex(FI); 4613 4614 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4615 4616 // Store the stack protector onto the stack. 4617 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4618 MachinePointerInfo::getFixedStack(FI), 4619 true, false, 0); 4620 setValue(&I, Res); 4621 DAG.setRoot(Res); 4622 return 0; 4623 } 4624 case Intrinsic::objectsize: { 4625 // If we don't know by now, we're never going to know. 4626 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4627 4628 assert(CI && "Non-constant type in __builtin_object_size?"); 4629 4630 SDValue Arg = getValue(I.getCalledValue()); 4631 EVT Ty = Arg.getValueType(); 4632 4633 if (CI->isZero()) 4634 Res = DAG.getConstant(-1ULL, Ty); 4635 else 4636 Res = DAG.getConstant(0, Ty); 4637 4638 setValue(&I, Res); 4639 return 0; 4640 } 4641 case Intrinsic::var_annotation: 4642 // Discard annotate attributes 4643 return 0; 4644 4645 case Intrinsic::init_trampoline: { 4646 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4647 4648 SDValue Ops[6]; 4649 Ops[0] = getRoot(); 4650 Ops[1] = getValue(I.getArgOperand(0)); 4651 Ops[2] = getValue(I.getArgOperand(1)); 4652 Ops[3] = getValue(I.getArgOperand(2)); 4653 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4654 Ops[5] = DAG.getSrcValue(F); 4655 4656 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4657 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4658 Ops, 6); 4659 4660 setValue(&I, Res); 4661 DAG.setRoot(Res.getValue(1)); 4662 return 0; 4663 } 4664 case Intrinsic::gcroot: 4665 if (GFI) { 4666 const Value *Alloca = I.getArgOperand(0); 4667 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4668 4669 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4670 GFI->addStackRoot(FI->getIndex(), TypeMap); 4671 } 4672 return 0; 4673 case Intrinsic::gcread: 4674 case Intrinsic::gcwrite: 4675 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4676 return 0; 4677 case Intrinsic::flt_rounds: 4678 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4679 return 0; 4680 case Intrinsic::trap: 4681 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4682 return 0; 4683 case Intrinsic::uadd_with_overflow: 4684 return implVisitAluOverflow(I, ISD::UADDO); 4685 case Intrinsic::sadd_with_overflow: 4686 return implVisitAluOverflow(I, ISD::SADDO); 4687 case Intrinsic::usub_with_overflow: 4688 return implVisitAluOverflow(I, ISD::USUBO); 4689 case Intrinsic::ssub_with_overflow: 4690 return implVisitAluOverflow(I, ISD::SSUBO); 4691 case Intrinsic::umul_with_overflow: 4692 return implVisitAluOverflow(I, ISD::UMULO); 4693 case Intrinsic::smul_with_overflow: 4694 return implVisitAluOverflow(I, ISD::SMULO); 4695 4696 case Intrinsic::prefetch: { 4697 SDValue Ops[4]; 4698 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 4699 Ops[0] = getRoot(); 4700 Ops[1] = getValue(I.getArgOperand(0)); 4701 Ops[2] = getValue(I.getArgOperand(1)); 4702 Ops[3] = getValue(I.getArgOperand(2)); 4703 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 4704 DAG.getVTList(MVT::Other), 4705 &Ops[0], 4, 4706 EVT::getIntegerVT(*Context, 8), 4707 MachinePointerInfo(I.getArgOperand(0)), 4708 0, /* align */ 4709 false, /* volatile */ 4710 rw==0, /* read */ 4711 rw==1)); /* write */ 4712 return 0; 4713 } 4714 case Intrinsic::memory_barrier: { 4715 SDValue Ops[6]; 4716 Ops[0] = getRoot(); 4717 for (int x = 1; x < 6; ++x) 4718 Ops[x] = getValue(I.getArgOperand(x - 1)); 4719 4720 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4721 return 0; 4722 } 4723 case Intrinsic::atomic_cmp_swap: { 4724 SDValue Root = getRoot(); 4725 SDValue L = 4726 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4727 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 4728 Root, 4729 getValue(I.getArgOperand(0)), 4730 getValue(I.getArgOperand(1)), 4731 getValue(I.getArgOperand(2)), 4732 MachinePointerInfo(I.getArgOperand(0))); 4733 setValue(&I, L); 4734 DAG.setRoot(L.getValue(1)); 4735 return 0; 4736 } 4737 case Intrinsic::atomic_load_add: 4738 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4739 case Intrinsic::atomic_load_sub: 4740 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4741 case Intrinsic::atomic_load_or: 4742 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4743 case Intrinsic::atomic_load_xor: 4744 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4745 case Intrinsic::atomic_load_and: 4746 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4747 case Intrinsic::atomic_load_nand: 4748 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4749 case Intrinsic::atomic_load_max: 4750 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4751 case Intrinsic::atomic_load_min: 4752 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4753 case Intrinsic::atomic_load_umin: 4754 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4755 case Intrinsic::atomic_load_umax: 4756 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4757 case Intrinsic::atomic_swap: 4758 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4759 4760 case Intrinsic::invariant_start: 4761 case Intrinsic::lifetime_start: 4762 // Discard region information. 4763 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4764 return 0; 4765 case Intrinsic::invariant_end: 4766 case Intrinsic::lifetime_end: 4767 // Discard region information. 4768 return 0; 4769 } 4770} 4771 4772void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 4773 bool isTailCall, 4774 MachineBasicBlock *LandingPad) { 4775 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4776 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4777 const Type *RetTy = FTy->getReturnType(); 4778 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4779 MCSymbol *BeginLabel = 0; 4780 4781 TargetLowering::ArgListTy Args; 4782 TargetLowering::ArgListEntry Entry; 4783 Args.reserve(CS.arg_size()); 4784 4785 // Check whether the function can return without sret-demotion. 4786 SmallVector<ISD::OutputArg, 4> Outs; 4787 SmallVector<uint64_t, 4> Offsets; 4788 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4789 Outs, TLI, &Offsets); 4790 4791 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4792 FTy->isVarArg(), Outs, FTy->getContext()); 4793 4794 SDValue DemoteStackSlot; 4795 int DemoteStackIdx = -100; 4796 4797 if (!CanLowerReturn) { 4798 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4799 FTy->getReturnType()); 4800 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4801 FTy->getReturnType()); 4802 MachineFunction &MF = DAG.getMachineFunction(); 4803 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4804 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4805 4806 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 4807 Entry.Node = DemoteStackSlot; 4808 Entry.Ty = StackSlotPtrType; 4809 Entry.isSExt = false; 4810 Entry.isZExt = false; 4811 Entry.isInReg = false; 4812 Entry.isSRet = true; 4813 Entry.isNest = false; 4814 Entry.isByVal = false; 4815 Entry.Alignment = Align; 4816 Args.push_back(Entry); 4817 RetTy = Type::getVoidTy(FTy->getContext()); 4818 } 4819 4820 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4821 i != e; ++i) { 4822 SDValue ArgNode = getValue(*i); 4823 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 4824 4825 unsigned attrInd = i - CS.arg_begin() + 1; 4826 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4827 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4828 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4829 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4830 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4831 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4832 Entry.Alignment = CS.getParamAlignment(attrInd); 4833 Args.push_back(Entry); 4834 } 4835 4836 if (LandingPad) { 4837 // Insert a label before the invoke call to mark the try range. This can be 4838 // used to detect deletion of the invoke via the MachineModuleInfo. 4839 BeginLabel = MMI.getContext().CreateTempSymbol(); 4840 4841 // For SjLj, keep track of which landing pads go with which invokes 4842 // so as to maintain the ordering of pads in the LSDA. 4843 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 4844 if (CallSiteIndex) { 4845 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4846 // Now that the call site is handled, stop tracking it. 4847 MMI.setCurrentCallSite(0); 4848 } 4849 4850 // Both PendingLoads and PendingExports must be flushed here; 4851 // this call might not return. 4852 (void)getRoot(); 4853 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4854 } 4855 4856 // Check if target-independent constraints permit a tail call here. 4857 // Target-dependent constraints are checked within TLI.LowerCallTo. 4858 if (isTailCall && 4859 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4860 isTailCall = false; 4861 4862 // If there's a possibility that fast-isel has already selected some amount 4863 // of the current basic block, don't emit a tail call. 4864 if (isTailCall && EnableFastISel) 4865 isTailCall = false; 4866 4867 std::pair<SDValue,SDValue> Result = 4868 TLI.LowerCallTo(getRoot(), RetTy, 4869 CS.paramHasAttr(0, Attribute::SExt), 4870 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4871 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4872 CS.getCallingConv(), 4873 isTailCall, 4874 !CS.getInstruction()->use_empty(), 4875 Callee, Args, DAG, getCurDebugLoc()); 4876 assert((isTailCall || Result.second.getNode()) && 4877 "Non-null chain expected with non-tail call!"); 4878 assert((Result.second.getNode() || !Result.first.getNode()) && 4879 "Null value expected with tail call!"); 4880 if (Result.first.getNode()) { 4881 setValue(CS.getInstruction(), Result.first); 4882 } else if (!CanLowerReturn && Result.second.getNode()) { 4883 // The instruction result is the result of loading from the 4884 // hidden sret parameter. 4885 SmallVector<EVT, 1> PVTs; 4886 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 4887 4888 ComputeValueVTs(TLI, PtrRetTy, PVTs); 4889 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 4890 EVT PtrVT = PVTs[0]; 4891 unsigned NumValues = Outs.size(); 4892 SmallVector<SDValue, 4> Values(NumValues); 4893 SmallVector<SDValue, 4> Chains(NumValues); 4894 4895 for (unsigned i = 0; i < NumValues; ++i) { 4896 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 4897 DemoteStackSlot, 4898 DAG.getConstant(Offsets[i], PtrVT)); 4899 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 4900 Add, 4901 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 4902 false, false, 1); 4903 Values[i] = L; 4904 Chains[i] = L.getValue(1); 4905 } 4906 4907 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 4908 MVT::Other, &Chains[0], NumValues); 4909 PendingLoads.push_back(Chain); 4910 4911 // Collect the legal value parts into potentially illegal values 4912 // that correspond to the original function's return values. 4913 SmallVector<EVT, 4> RetTys; 4914 RetTy = FTy->getReturnType(); 4915 ComputeValueVTs(TLI, RetTy, RetTys); 4916 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4917 SmallVector<SDValue, 4> ReturnValues; 4918 unsigned CurReg = 0; 4919 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4920 EVT VT = RetTys[I]; 4921 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 4922 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 4923 4924 SDValue ReturnValue = 4925 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 4926 RegisterVT, VT, AssertOp); 4927 ReturnValues.push_back(ReturnValue); 4928 CurReg += NumRegs; 4929 } 4930 4931 setValue(CS.getInstruction(), 4932 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 4933 DAG.getVTList(&RetTys[0], RetTys.size()), 4934 &ReturnValues[0], ReturnValues.size())); 4935 4936 } 4937 4938 // As a special case, a null chain means that a tail call has been emitted and 4939 // the DAG root is already updated. 4940 if (Result.second.getNode()) 4941 DAG.setRoot(Result.second); 4942 else 4943 HasTailCall = true; 4944 4945 if (LandingPad) { 4946 // Insert a label at the end of the invoke call to mark the try range. This 4947 // can be used to detect deletion of the invoke via the MachineModuleInfo. 4948 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 4949 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 4950 4951 // Inform MachineModuleInfo of range. 4952 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 4953 } 4954} 4955 4956/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 4957/// value is equal or not-equal to zero. 4958static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 4959 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 4960 UI != E; ++UI) { 4961 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 4962 if (IC->isEquality()) 4963 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 4964 if (C->isNullValue()) 4965 continue; 4966 // Unknown instruction. 4967 return false; 4968 } 4969 return true; 4970} 4971 4972static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 4973 const Type *LoadTy, 4974 SelectionDAGBuilder &Builder) { 4975 4976 // Check to see if this load can be trivially constant folded, e.g. if the 4977 // input is from a string literal. 4978 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 4979 // Cast pointer to the type we really want to load. 4980 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 4981 PointerType::getUnqual(LoadTy)); 4982 4983 if (const Constant *LoadCst = 4984 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 4985 Builder.TD)) 4986 return Builder.getValue(LoadCst); 4987 } 4988 4989 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 4990 // still constant memory, the input chain can be the entry node. 4991 SDValue Root; 4992 bool ConstantMemory = false; 4993 4994 // Do not serialize (non-volatile) loads of constant memory with anything. 4995 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 4996 Root = Builder.DAG.getEntryNode(); 4997 ConstantMemory = true; 4998 } else { 4999 // Do not serialize non-volatile loads against each other. 5000 Root = Builder.DAG.getRoot(); 5001 } 5002 5003 SDValue Ptr = Builder.getValue(PtrVal); 5004 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5005 Ptr, MachinePointerInfo(PtrVal), 5006 false /*volatile*/, 5007 false /*nontemporal*/, 1 /* align=1 */); 5008 5009 if (!ConstantMemory) 5010 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5011 return LoadVal; 5012} 5013 5014 5015/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5016/// If so, return true and lower it, otherwise return false and it will be 5017/// lowered like a normal call. 5018bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5019 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5020 if (I.getNumArgOperands() != 3) 5021 return false; 5022 5023 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5024 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5025 !I.getArgOperand(2)->getType()->isIntegerTy() || 5026 !I.getType()->isIntegerTy()) 5027 return false; 5028 5029 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5030 5031 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5032 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5033 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5034 bool ActuallyDoIt = true; 5035 MVT LoadVT; 5036 const Type *LoadTy; 5037 switch (Size->getZExtValue()) { 5038 default: 5039 LoadVT = MVT::Other; 5040 LoadTy = 0; 5041 ActuallyDoIt = false; 5042 break; 5043 case 2: 5044 LoadVT = MVT::i16; 5045 LoadTy = Type::getInt16Ty(Size->getContext()); 5046 break; 5047 case 4: 5048 LoadVT = MVT::i32; 5049 LoadTy = Type::getInt32Ty(Size->getContext()); 5050 break; 5051 case 8: 5052 LoadVT = MVT::i64; 5053 LoadTy = Type::getInt64Ty(Size->getContext()); 5054 break; 5055 /* 5056 case 16: 5057 LoadVT = MVT::v4i32; 5058 LoadTy = Type::getInt32Ty(Size->getContext()); 5059 LoadTy = VectorType::get(LoadTy, 4); 5060 break; 5061 */ 5062 } 5063 5064 // This turns into unaligned loads. We only do this if the target natively 5065 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5066 // we'll only produce a small number of byte loads. 5067 5068 // Require that we can find a legal MVT, and only do this if the target 5069 // supports unaligned loads of that type. Expanding into byte loads would 5070 // bloat the code. 5071 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5072 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5073 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5074 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5075 ActuallyDoIt = false; 5076 } 5077 5078 if (ActuallyDoIt) { 5079 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5080 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5081 5082 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5083 ISD::SETNE); 5084 EVT CallVT = TLI.getValueType(I.getType(), true); 5085 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5086 return true; 5087 } 5088 } 5089 5090 5091 return false; 5092} 5093 5094 5095void SelectionDAGBuilder::visitCall(const CallInst &I) { 5096 // Handle inline assembly differently. 5097 if (isa<InlineAsm>(I.getCalledValue())) { 5098 visitInlineAsm(&I); 5099 return; 5100 } 5101 5102 // See if any floating point values are being passed to this function. This is 5103 // used to emit an undefined reference to fltused on Windows. 5104 const FunctionType *FT = 5105 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5106 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5107 if (FT->isVarArg() && 5108 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5109 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5110 const Type* T = I.getArgOperand(i)->getType(); 5111 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T); 5112 i != e; ++i) { 5113 if (!i->isFloatingPointTy()) continue; 5114 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5115 break; 5116 } 5117 } 5118 } 5119 5120 const char *RenameFn = 0; 5121 if (Function *F = I.getCalledFunction()) { 5122 if (F->isDeclaration()) { 5123 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5124 if (unsigned IID = II->getIntrinsicID(F)) { 5125 RenameFn = visitIntrinsicCall(I, IID); 5126 if (!RenameFn) 5127 return; 5128 } 5129 } 5130 if (unsigned IID = F->getIntrinsicID()) { 5131 RenameFn = visitIntrinsicCall(I, IID); 5132 if (!RenameFn) 5133 return; 5134 } 5135 } 5136 5137 // Check for well-known libc/libm calls. If the function is internal, it 5138 // can't be a library call. 5139 if (!F->hasLocalLinkage() && F->hasName()) { 5140 StringRef Name = F->getName(); 5141 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5142 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5143 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5144 I.getType() == I.getArgOperand(0)->getType() && 5145 I.getType() == I.getArgOperand(1)->getType()) { 5146 SDValue LHS = getValue(I.getArgOperand(0)); 5147 SDValue RHS = getValue(I.getArgOperand(1)); 5148 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5149 LHS.getValueType(), LHS, RHS)); 5150 return; 5151 } 5152 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5153 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5154 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5155 I.getType() == I.getArgOperand(0)->getType()) { 5156 SDValue Tmp = getValue(I.getArgOperand(0)); 5157 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5158 Tmp.getValueType(), Tmp)); 5159 return; 5160 } 5161 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5162 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5163 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5164 I.getType() == I.getArgOperand(0)->getType() && 5165 I.onlyReadsMemory()) { 5166 SDValue Tmp = getValue(I.getArgOperand(0)); 5167 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5168 Tmp.getValueType(), Tmp)); 5169 return; 5170 } 5171 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5172 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5173 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5174 I.getType() == I.getArgOperand(0)->getType() && 5175 I.onlyReadsMemory()) { 5176 SDValue Tmp = getValue(I.getArgOperand(0)); 5177 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5178 Tmp.getValueType(), Tmp)); 5179 return; 5180 } 5181 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5182 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5183 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5184 I.getType() == I.getArgOperand(0)->getType() && 5185 I.onlyReadsMemory()) { 5186 SDValue Tmp = getValue(I.getArgOperand(0)); 5187 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5188 Tmp.getValueType(), Tmp)); 5189 return; 5190 } 5191 } else if (Name == "memcmp") { 5192 if (visitMemCmpCall(I)) 5193 return; 5194 } 5195 } 5196 } 5197 5198 SDValue Callee; 5199 if (!RenameFn) 5200 Callee = getValue(I.getCalledValue()); 5201 else 5202 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5203 5204 // Check if we can potentially perform a tail call. More detailed checking is 5205 // be done within LowerCallTo, after more information about the call is known. 5206 LowerCallTo(&I, Callee, I.isTailCall()); 5207} 5208 5209namespace llvm { 5210 5211/// AsmOperandInfo - This contains information for each constraint that we are 5212/// lowering. 5213class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo : 5214 public TargetLowering::AsmOperandInfo { 5215public: 5216 /// CallOperand - If this is the result output operand or a clobber 5217 /// this is null, otherwise it is the incoming operand to the CallInst. 5218 /// This gets modified as the asm is processed. 5219 SDValue CallOperand; 5220 5221 /// AssignedRegs - If this is a register or register class operand, this 5222 /// contains the set of register corresponding to the operand. 5223 RegsForValue AssignedRegs; 5224 5225 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5226 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5227 } 5228 5229 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5230 /// busy in OutputRegs/InputRegs. 5231 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5232 std::set<unsigned> &OutputRegs, 5233 std::set<unsigned> &InputRegs, 5234 const TargetRegisterInfo &TRI) const { 5235 if (isOutReg) { 5236 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5237 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5238 } 5239 if (isInReg) { 5240 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5241 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5242 } 5243 } 5244 5245 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5246 /// corresponds to. If there is no Value* for this operand, it returns 5247 /// MVT::Other. 5248 EVT getCallOperandValEVT(LLVMContext &Context, 5249 const TargetLowering &TLI, 5250 const TargetData *TD) const { 5251 if (CallOperandVal == 0) return MVT::Other; 5252 5253 if (isa<BasicBlock>(CallOperandVal)) 5254 return TLI.getPointerTy(); 5255 5256 const llvm::Type *OpTy = CallOperandVal->getType(); 5257 5258 // If this is an indirect operand, the operand is a pointer to the 5259 // accessed type. 5260 if (isIndirect) { 5261 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5262 if (!PtrTy) 5263 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5264 OpTy = PtrTy->getElementType(); 5265 } 5266 5267 // If OpTy is not a single value, it may be a struct/union that we 5268 // can tile with integers. 5269 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5270 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5271 switch (BitSize) { 5272 default: break; 5273 case 1: 5274 case 8: 5275 case 16: 5276 case 32: 5277 case 64: 5278 case 128: 5279 OpTy = IntegerType::get(Context, BitSize); 5280 break; 5281 } 5282 } 5283 5284 return TLI.getValueType(OpTy, true); 5285 } 5286 5287private: 5288 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5289 /// specified set. 5290 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5291 const TargetRegisterInfo &TRI) { 5292 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5293 Regs.insert(Reg); 5294 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5295 for (; *Aliases; ++Aliases) 5296 Regs.insert(*Aliases); 5297 } 5298}; 5299 5300typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5301 5302} // end llvm namespace. 5303 5304/// isAllocatableRegister - If the specified register is safe to allocate, 5305/// i.e. it isn't a stack pointer or some other special register, return the 5306/// register class for the register. Otherwise, return null. 5307static const TargetRegisterClass * 5308isAllocatableRegister(unsigned Reg, MachineFunction &MF, 5309 const TargetLowering &TLI, 5310 const TargetRegisterInfo *TRI) { 5311 EVT FoundVT = MVT::Other; 5312 const TargetRegisterClass *FoundRC = 0; 5313 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 5314 E = TRI->regclass_end(); RCI != E; ++RCI) { 5315 EVT ThisVT = MVT::Other; 5316 5317 const TargetRegisterClass *RC = *RCI; 5318 // If none of the value types for this register class are valid, we 5319 // can't use it. For example, 64-bit reg classes on 32-bit targets. 5320 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 5321 I != E; ++I) { 5322 if (TLI.isTypeLegal(*I)) { 5323 // If we have already found this register in a different register class, 5324 // choose the one with the largest VT specified. For example, on 5325 // PowerPC, we favor f64 register classes over f32. 5326 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 5327 ThisVT = *I; 5328 break; 5329 } 5330 } 5331 } 5332 5333 if (ThisVT == MVT::Other) continue; 5334 5335 // NOTE: This isn't ideal. In particular, this might allocate the 5336 // frame pointer in functions that need it (due to them not being taken 5337 // out of allocation, because a variable sized allocation hasn't been seen 5338 // yet). This is a slight code pessimization, but should still work. 5339 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 5340 E = RC->allocation_order_end(MF); I != E; ++I) 5341 if (*I == Reg) { 5342 // We found a matching register class. Keep looking at others in case 5343 // we find one with larger registers that this physreg is also in. 5344 FoundRC = RC; 5345 FoundVT = ThisVT; 5346 break; 5347 } 5348 } 5349 return FoundRC; 5350} 5351 5352/// GetRegistersForValue - Assign registers (virtual or physical) for the 5353/// specified operand. We prefer to assign virtual registers, to allow the 5354/// register allocator to handle the assignment process. However, if the asm 5355/// uses features that we can't model on machineinstrs, we have SDISel do the 5356/// allocation. This produces generally horrible, but correct, code. 5357/// 5358/// OpInfo describes the operand. 5359/// Input and OutputRegs are the set of already allocated physical registers. 5360/// 5361void SelectionDAGBuilder:: 5362GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, 5363 std::set<unsigned> &OutputRegs, 5364 std::set<unsigned> &InputRegs) { 5365 LLVMContext &Context = FuncInfo.Fn->getContext(); 5366 5367 // Compute whether this value requires an input register, an output register, 5368 // or both. 5369 bool isOutReg = false; 5370 bool isInReg = false; 5371 switch (OpInfo.Type) { 5372 case InlineAsm::isOutput: 5373 isOutReg = true; 5374 5375 // If there is an input constraint that matches this, we need to reserve 5376 // the input register so no other inputs allocate to it. 5377 isInReg = OpInfo.hasMatchingInput(); 5378 break; 5379 case InlineAsm::isInput: 5380 isInReg = true; 5381 isOutReg = false; 5382 break; 5383 case InlineAsm::isClobber: 5384 isOutReg = true; 5385 isInReg = true; 5386 break; 5387 } 5388 5389 5390 MachineFunction &MF = DAG.getMachineFunction(); 5391 SmallVector<unsigned, 4> Regs; 5392 5393 // If this is a constraint for a single physreg, or a constraint for a 5394 // register class, find it. 5395 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5396 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5397 OpInfo.ConstraintVT); 5398 5399 unsigned NumRegs = 1; 5400 if (OpInfo.ConstraintVT != MVT::Other) { 5401 // If this is a FP input in an integer register (or visa versa) insert a bit 5402 // cast of the input value. More generally, handle any case where the input 5403 // value disagrees with the register class we plan to stick this in. 5404 if (OpInfo.Type == InlineAsm::isInput && 5405 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5406 // Try to convert to the first EVT that the reg class contains. If the 5407 // types are identical size, use a bitcast to convert (e.g. two differing 5408 // vector types). 5409 EVT RegVT = *PhysReg.second->vt_begin(); 5410 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5411 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 5412 RegVT, OpInfo.CallOperand); 5413 OpInfo.ConstraintVT = RegVT; 5414 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5415 // If the input is a FP value and we want it in FP registers, do a 5416 // bitcast to the corresponding integer type. This turns an f64 value 5417 // into i64, which can be passed with two i32 values on a 32-bit 5418 // machine. 5419 RegVT = EVT::getIntegerVT(Context, 5420 OpInfo.ConstraintVT.getSizeInBits()); 5421 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 5422 RegVT, OpInfo.CallOperand); 5423 OpInfo.ConstraintVT = RegVT; 5424 } 5425 } 5426 5427 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5428 } 5429 5430 EVT RegVT; 5431 EVT ValueVT = OpInfo.ConstraintVT; 5432 5433 // If this is a constraint for a specific physical register, like {r17}, 5434 // assign it now. 5435 if (unsigned AssignedReg = PhysReg.first) { 5436 const TargetRegisterClass *RC = PhysReg.second; 5437 if (OpInfo.ConstraintVT == MVT::Other) 5438 ValueVT = *RC->vt_begin(); 5439 5440 // Get the actual register value type. This is important, because the user 5441 // may have asked for (e.g.) the AX register in i32 type. We need to 5442 // remember that AX is actually i16 to get the right extension. 5443 RegVT = *RC->vt_begin(); 5444 5445 // This is a explicit reference to a physical register. 5446 Regs.push_back(AssignedReg); 5447 5448 // If this is an expanded reference, add the rest of the regs to Regs. 5449 if (NumRegs != 1) { 5450 TargetRegisterClass::iterator I = RC->begin(); 5451 for (; *I != AssignedReg; ++I) 5452 assert(I != RC->end() && "Didn't find reg!"); 5453 5454 // Already added the first reg. 5455 --NumRegs; ++I; 5456 for (; NumRegs; --NumRegs, ++I) { 5457 assert(I != RC->end() && "Ran out of registers to allocate!"); 5458 Regs.push_back(*I); 5459 } 5460 } 5461 5462 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5463 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5464 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5465 return; 5466 } 5467 5468 // Otherwise, if this was a reference to an LLVM register class, create vregs 5469 // for this reference. 5470 if (const TargetRegisterClass *RC = PhysReg.second) { 5471 RegVT = *RC->vt_begin(); 5472 if (OpInfo.ConstraintVT == MVT::Other) 5473 ValueVT = RegVT; 5474 5475 // Create the appropriate number of virtual registers. 5476 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5477 for (; NumRegs; --NumRegs) 5478 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5479 5480 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5481 return; 5482 } 5483 5484 // This is a reference to a register class that doesn't directly correspond 5485 // to an LLVM register class. Allocate NumRegs consecutive, available, 5486 // registers from the class. 5487 std::vector<unsigned> RegClassRegs 5488 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 5489 OpInfo.ConstraintVT); 5490 5491 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5492 unsigned NumAllocated = 0; 5493 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 5494 unsigned Reg = RegClassRegs[i]; 5495 // See if this register is available. 5496 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 5497 (isInReg && InputRegs.count(Reg))) { // Already used. 5498 // Make sure we find consecutive registers. 5499 NumAllocated = 0; 5500 continue; 5501 } 5502 5503 // Check to see if this register is allocatable (i.e. don't give out the 5504 // stack pointer). 5505 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); 5506 if (!RC) { // Couldn't allocate this register. 5507 // Reset NumAllocated to make sure we return consecutive registers. 5508 NumAllocated = 0; 5509 continue; 5510 } 5511 5512 // Okay, this register is good, we can use it. 5513 ++NumAllocated; 5514 5515 // If we allocated enough consecutive registers, succeed. 5516 if (NumAllocated == NumRegs) { 5517 unsigned RegStart = (i-NumAllocated)+1; 5518 unsigned RegEnd = i+1; 5519 // Mark all of the allocated registers used. 5520 for (unsigned i = RegStart; i != RegEnd; ++i) 5521 Regs.push_back(RegClassRegs[i]); 5522 5523 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 5524 OpInfo.ConstraintVT); 5525 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5526 return; 5527 } 5528 } 5529 5530 // Otherwise, we couldn't allocate enough registers for this. 5531} 5532 5533/// visitInlineAsm - Handle a call to an InlineAsm object. 5534/// 5535void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5536 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5537 5538 /// ConstraintOperands - Information about all of the constraints. 5539 SDISelAsmOperandInfoVector ConstraintOperands; 5540 5541 std::set<unsigned> OutputRegs, InputRegs; 5542 5543 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS); 5544 bool hasMemory = false; 5545 5546 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5547 unsigned ResNo = 0; // ResNo - The result number of the next output. 5548 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5549 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5550 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5551 5552 EVT OpVT = MVT::Other; 5553 5554 // Compute the value type for each operand. 5555 switch (OpInfo.Type) { 5556 case InlineAsm::isOutput: 5557 // Indirect outputs just consume an argument. 5558 if (OpInfo.isIndirect) { 5559 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5560 break; 5561 } 5562 5563 // The return value of the call is this value. As such, there is no 5564 // corresponding argument. 5565 assert(!CS.getType()->isVoidTy() && 5566 "Bad inline asm!"); 5567 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5568 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5569 } else { 5570 assert(ResNo == 0 && "Asm only has one result!"); 5571 OpVT = TLI.getValueType(CS.getType()); 5572 } 5573 ++ResNo; 5574 break; 5575 case InlineAsm::isInput: 5576 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5577 break; 5578 case InlineAsm::isClobber: 5579 // Nothing to do. 5580 break; 5581 } 5582 5583 // If this is an input or an indirect output, process the call argument. 5584 // BasicBlocks are labels, currently appearing only in asm's. 5585 if (OpInfo.CallOperandVal) { 5586 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5587 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5588 } else { 5589 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5590 } 5591 5592 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5593 } 5594 5595 OpInfo.ConstraintVT = OpVT; 5596 5597 // Indirect operand accesses access memory. 5598 if (OpInfo.isIndirect) 5599 hasMemory = true; 5600 else { 5601 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5602 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]); 5603 if (CType == TargetLowering::C_Memory) { 5604 hasMemory = true; 5605 break; 5606 } 5607 } 5608 } 5609 } 5610 5611 SDValue Chain, Flag; 5612 5613 // We won't need to flush pending loads if this asm doesn't touch 5614 // memory and is nonvolatile. 5615 if (hasMemory || IA->hasSideEffects()) 5616 Chain = getRoot(); 5617 else 5618 Chain = DAG.getRoot(); 5619 5620 // Second pass over the constraints: compute which constraint option to use 5621 // and assign registers to constraints that want a specific physreg. 5622 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5623 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5624 5625 // If this is an output operand with a matching input operand, look up the 5626 // matching input. If their types mismatch, e.g. one is an integer, the 5627 // other is floating point, or their sizes are different, flag it as an 5628 // error. 5629 if (OpInfo.hasMatchingInput()) { 5630 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5631 5632 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5633 if ((OpInfo.ConstraintVT.isInteger() != 5634 Input.ConstraintVT.isInteger()) || 5635 (OpInfo.ConstraintVT.getSizeInBits() != 5636 Input.ConstraintVT.getSizeInBits())) { 5637 report_fatal_error("Unsupported asm: input constraint" 5638 " with a matching output constraint of" 5639 " incompatible type!"); 5640 } 5641 Input.ConstraintVT = OpInfo.ConstraintVT; 5642 } 5643 } 5644 5645 // Compute the constraint code and ConstraintType to use. 5646 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5647 5648 // If this is a memory input, and if the operand is not indirect, do what we 5649 // need to to provide an address for the memory input. 5650 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5651 !OpInfo.isIndirect) { 5652 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && 5653 "Can only indirectify direct input operands!"); 5654 5655 // Memory operands really want the address of the value. If we don't have 5656 // an indirect input, put it in the constpool if we can, otherwise spill 5657 // it to a stack slot. 5658 5659 // If the operand is a float, integer, or vector constant, spill to a 5660 // constant pool entry to get its address. 5661 const Value *OpVal = OpInfo.CallOperandVal; 5662 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5663 isa<ConstantVector>(OpVal)) { 5664 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5665 TLI.getPointerTy()); 5666 } else { 5667 // Otherwise, create a stack slot and emit a store to it before the 5668 // asm. 5669 const Type *Ty = OpVal->getType(); 5670 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5671 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5672 MachineFunction &MF = DAG.getMachineFunction(); 5673 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5674 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5675 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5676 OpInfo.CallOperand, StackSlot, 5677 MachinePointerInfo::getFixedStack(SSFI), 5678 false, false, 0); 5679 OpInfo.CallOperand = StackSlot; 5680 } 5681 5682 // There is no longer a Value* corresponding to this operand. 5683 OpInfo.CallOperandVal = 0; 5684 5685 // It is now an indirect operand. 5686 OpInfo.isIndirect = true; 5687 } 5688 5689 // If this constraint is for a specific register, allocate it before 5690 // anything else. 5691 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5692 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5693 } 5694 5695 // Second pass - Loop over all of the operands, assigning virtual or physregs 5696 // to register class operands. 5697 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5698 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5699 5700 // C_Register operands have already been allocated, Other/Memory don't need 5701 // to be. 5702 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5703 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5704 } 5705 5706 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5707 std::vector<SDValue> AsmNodeOperands; 5708 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5709 AsmNodeOperands.push_back( 5710 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5711 TLI.getPointerTy())); 5712 5713 // If we have a !srcloc metadata node associated with it, we want to attach 5714 // this to the ultimately generated inline asm machineinstr. To do this, we 5715 // pass in the third operand as this (potentially null) inline asm MDNode. 5716 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5717 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5718 5719 // Remember the HasSideEffect and AlignStack bits as operand 3. 5720 unsigned ExtraInfo = 0; 5721 if (IA->hasSideEffects()) 5722 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 5723 if (IA->isAlignStack()) 5724 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 5725 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 5726 TLI.getPointerTy())); 5727 5728 // Loop over all of the inputs, copying the operand values into the 5729 // appropriate registers and processing the output regs. 5730 RegsForValue RetValRegs; 5731 5732 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5733 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5734 5735 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5736 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5737 5738 switch (OpInfo.Type) { 5739 case InlineAsm::isOutput: { 5740 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5741 OpInfo.ConstraintType != TargetLowering::C_Register) { 5742 // Memory output, or 'other' output (e.g. 'X' constraint). 5743 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5744 5745 // Add information to the INLINEASM node to know about this output. 5746 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5747 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5748 TLI.getPointerTy())); 5749 AsmNodeOperands.push_back(OpInfo.CallOperand); 5750 break; 5751 } 5752 5753 // Otherwise, this is a register or register class output. 5754 5755 // Copy the output from the appropriate register. Find a register that 5756 // we can use. 5757 if (OpInfo.AssignedRegs.Regs.empty()) 5758 report_fatal_error("Couldn't allocate output reg for constraint '" + 5759 Twine(OpInfo.ConstraintCode) + "'!"); 5760 5761 // If this is an indirect operand, store through the pointer after the 5762 // asm. 5763 if (OpInfo.isIndirect) { 5764 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5765 OpInfo.CallOperandVal)); 5766 } else { 5767 // This is the result value of the call. 5768 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5769 // Concatenate this output onto the outputs list. 5770 RetValRegs.append(OpInfo.AssignedRegs); 5771 } 5772 5773 // Add information to the INLINEASM node to know that this register is 5774 // set. 5775 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5776 InlineAsm::Kind_RegDefEarlyClobber : 5777 InlineAsm::Kind_RegDef, 5778 false, 5779 0, 5780 DAG, 5781 AsmNodeOperands); 5782 break; 5783 } 5784 case InlineAsm::isInput: { 5785 SDValue InOperandVal = OpInfo.CallOperand; 5786 5787 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5788 // If this is required to match an output register we have already set, 5789 // just use its register. 5790 unsigned OperandNo = OpInfo.getMatchedOperand(); 5791 5792 // Scan until we find the definition we already emitted of this operand. 5793 // When we find it, create a RegsForValue operand. 5794 unsigned CurOp = InlineAsm::Op_FirstOperand; 5795 for (; OperandNo; --OperandNo) { 5796 // Advance to the next operand. 5797 unsigned OpFlag = 5798 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5799 assert((InlineAsm::isRegDefKind(OpFlag) || 5800 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5801 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5802 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5803 } 5804 5805 unsigned OpFlag = 5806 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5807 if (InlineAsm::isRegDefKind(OpFlag) || 5808 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5809 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5810 if (OpInfo.isIndirect) { 5811 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5812 LLVMContext &Ctx = *DAG.getContext(); 5813 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5814 " don't know how to handle tied " 5815 "indirect register inputs"); 5816 } 5817 5818 RegsForValue MatchedRegs; 5819 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5820 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5821 MatchedRegs.RegVTs.push_back(RegVT); 5822 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5823 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5824 i != e; ++i) 5825 MatchedRegs.Regs.push_back 5826 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5827 5828 // Use the produced MatchedRegs object to 5829 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5830 Chain, &Flag); 5831 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 5832 true, OpInfo.getMatchedOperand(), 5833 DAG, AsmNodeOperands); 5834 break; 5835 } 5836 5837 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 5838 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 5839 "Unexpected number of operands"); 5840 // Add information to the INLINEASM node to know about this input. 5841 // See InlineAsm.h isUseOperandTiedToDef. 5842 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 5843 OpInfo.getMatchedOperand()); 5844 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5845 TLI.getPointerTy())); 5846 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5847 break; 5848 } 5849 5850 // Treat indirect 'X' constraint as memory. 5851 if (OpInfo.ConstraintType == TargetLowering::C_Other && 5852 OpInfo.isIndirect) 5853 OpInfo.ConstraintType = TargetLowering::C_Memory; 5854 5855 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5856 std::vector<SDValue> Ops; 5857 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 5858 Ops, DAG); 5859 if (Ops.empty()) 5860 report_fatal_error("Invalid operand for inline asm constraint '" + 5861 Twine(OpInfo.ConstraintCode) + "'!"); 5862 5863 // Add information to the INLINEASM node to know about this input. 5864 unsigned ResOpType = 5865 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 5866 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5867 TLI.getPointerTy())); 5868 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5869 break; 5870 } 5871 5872 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5873 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5874 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5875 "Memory operands expect pointer values"); 5876 5877 // Add information to the INLINEASM node to know about this input. 5878 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5879 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5880 TLI.getPointerTy())); 5881 AsmNodeOperands.push_back(InOperandVal); 5882 break; 5883 } 5884 5885 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5886 OpInfo.ConstraintType == TargetLowering::C_Register) && 5887 "Unknown constraint type!"); 5888 assert(!OpInfo.isIndirect && 5889 "Don't know how to handle indirect register inputs yet!"); 5890 5891 // Copy the input into the appropriate registers. 5892 if (OpInfo.AssignedRegs.Regs.empty() || 5893 !OpInfo.AssignedRegs.areValueTypesLegal(TLI)) 5894 report_fatal_error("Couldn't allocate input reg for constraint '" + 5895 Twine(OpInfo.ConstraintCode) + "'!"); 5896 5897 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5898 Chain, &Flag); 5899 5900 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 5901 DAG, AsmNodeOperands); 5902 break; 5903 } 5904 case InlineAsm::isClobber: { 5905 // Add the clobbered value to the operand list, so that the register 5906 // allocator is aware that the physreg got clobbered. 5907 if (!OpInfo.AssignedRegs.Regs.empty()) 5908 OpInfo.AssignedRegs.AddInlineAsmOperands( 5909 InlineAsm::Kind_RegDefEarlyClobber, 5910 false, 0, DAG, 5911 AsmNodeOperands); 5912 break; 5913 } 5914 } 5915 } 5916 5917 // Finish up input operands. Set the input chain and add the flag last. 5918 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 5919 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5920 5921 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5922 DAG.getVTList(MVT::Other, MVT::Glue), 5923 &AsmNodeOperands[0], AsmNodeOperands.size()); 5924 Flag = Chain.getValue(1); 5925 5926 // If this asm returns a register value, copy the result from that register 5927 // and set it as the value of the call. 5928 if (!RetValRegs.Regs.empty()) { 5929 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5930 Chain, &Flag); 5931 5932 // FIXME: Why don't we do this for inline asms with MRVs? 5933 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5934 EVT ResultType = TLI.getValueType(CS.getType()); 5935 5936 // If any of the results of the inline asm is a vector, it may have the 5937 // wrong width/num elts. This can happen for register classes that can 5938 // contain multiple different value types. The preg or vreg allocated may 5939 // not have the same VT as was expected. Convert it to the right type 5940 // with bit_convert. 5941 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5942 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 5943 ResultType, Val); 5944 5945 } else if (ResultType != Val.getValueType() && 5946 ResultType.isInteger() && Val.getValueType().isInteger()) { 5947 // If a result value was tied to an input value, the computed result may 5948 // have a wider width than the expected result. Extract the relevant 5949 // portion. 5950 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 5951 } 5952 5953 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 5954 } 5955 5956 setValue(CS.getInstruction(), Val); 5957 // Don't need to use this as a chain in this case. 5958 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 5959 return; 5960 } 5961 5962 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 5963 5964 // Process indirect outputs, first output all of the flagged copies out of 5965 // physregs. 5966 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 5967 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 5968 const Value *Ptr = IndirectStoresToEmit[i].second; 5969 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5970 Chain, &Flag); 5971 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 5972 } 5973 5974 // Emit the non-flagged stores from the physregs. 5975 SmallVector<SDValue, 8> OutChains; 5976 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 5977 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 5978 StoresToEmit[i].first, 5979 getValue(StoresToEmit[i].second), 5980 MachinePointerInfo(StoresToEmit[i].second), 5981 false, false, 0); 5982 OutChains.push_back(Val); 5983 } 5984 5985 if (!OutChains.empty()) 5986 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 5987 &OutChains[0], OutChains.size()); 5988 5989 DAG.setRoot(Chain); 5990} 5991 5992void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 5993 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 5994 MVT::Other, getRoot(), 5995 getValue(I.getArgOperand(0)), 5996 DAG.getSrcValue(I.getArgOperand(0)))); 5997} 5998 5999void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6000 const TargetData &TD = *TLI.getTargetData(); 6001 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6002 getRoot(), getValue(I.getOperand(0)), 6003 DAG.getSrcValue(I.getOperand(0)), 6004 TD.getABITypeAlignment(I.getType())); 6005 setValue(&I, V); 6006 DAG.setRoot(V.getValue(1)); 6007} 6008 6009void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6010 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6011 MVT::Other, getRoot(), 6012 getValue(I.getArgOperand(0)), 6013 DAG.getSrcValue(I.getArgOperand(0)))); 6014} 6015 6016void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6017 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6018 MVT::Other, getRoot(), 6019 getValue(I.getArgOperand(0)), 6020 getValue(I.getArgOperand(1)), 6021 DAG.getSrcValue(I.getArgOperand(0)), 6022 DAG.getSrcValue(I.getArgOperand(1)))); 6023} 6024 6025/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6026/// implementation, which just calls LowerCall. 6027/// FIXME: When all targets are 6028/// migrated to using LowerCall, this hook should be integrated into SDISel. 6029std::pair<SDValue, SDValue> 6030TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 6031 bool RetSExt, bool RetZExt, bool isVarArg, 6032 bool isInreg, unsigned NumFixedArgs, 6033 CallingConv::ID CallConv, bool isTailCall, 6034 bool isReturnValueUsed, 6035 SDValue Callee, 6036 ArgListTy &Args, SelectionDAG &DAG, 6037 DebugLoc dl) const { 6038 // Handle all of the outgoing arguments. 6039 SmallVector<ISD::OutputArg, 32> Outs; 6040 SmallVector<SDValue, 32> OutVals; 6041 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6042 SmallVector<EVT, 4> ValueVTs; 6043 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6044 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6045 Value != NumValues; ++Value) { 6046 EVT VT = ValueVTs[Value]; 6047 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6048 SDValue Op = SDValue(Args[i].Node.getNode(), 6049 Args[i].Node.getResNo() + Value); 6050 ISD::ArgFlagsTy Flags; 6051 unsigned OriginalAlignment = 6052 getTargetData()->getABITypeAlignment(ArgTy); 6053 6054 if (Args[i].isZExt) 6055 Flags.setZExt(); 6056 if (Args[i].isSExt) 6057 Flags.setSExt(); 6058 if (Args[i].isInReg) 6059 Flags.setInReg(); 6060 if (Args[i].isSRet) 6061 Flags.setSRet(); 6062 if (Args[i].isByVal) { 6063 Flags.setByVal(); 6064 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 6065 const Type *ElementTy = Ty->getElementType(); 6066 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 6067 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy); 6068 // For ByVal, alignment should come from FE. BE will guess if this 6069 // info is not there but there are cases it cannot get right. 6070 if (Args[i].Alignment) 6071 FrameAlign = Args[i].Alignment; 6072 Flags.setByValAlign(FrameAlign); 6073 Flags.setByValSize(FrameSize); 6074 } 6075 if (Args[i].isNest) 6076 Flags.setNest(); 6077 Flags.setOrigAlign(OriginalAlignment); 6078 6079 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6080 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6081 SmallVector<SDValue, 4> Parts(NumParts); 6082 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6083 6084 if (Args[i].isSExt) 6085 ExtendKind = ISD::SIGN_EXTEND; 6086 else if (Args[i].isZExt) 6087 ExtendKind = ISD::ZERO_EXTEND; 6088 6089 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6090 PartVT, ExtendKind); 6091 6092 for (unsigned j = 0; j != NumParts; ++j) { 6093 // if it isn't first piece, alignment must be 1 6094 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6095 i < NumFixedArgs); 6096 if (NumParts > 1 && j == 0) 6097 MyFlags.Flags.setSplit(); 6098 else if (j != 0) 6099 MyFlags.Flags.setOrigAlign(1); 6100 6101 Outs.push_back(MyFlags); 6102 OutVals.push_back(Parts[j]); 6103 } 6104 } 6105 } 6106 6107 // Handle the incoming return values from the call. 6108 SmallVector<ISD::InputArg, 32> Ins; 6109 SmallVector<EVT, 4> RetTys; 6110 ComputeValueVTs(*this, RetTy, RetTys); 6111 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6112 EVT VT = RetTys[I]; 6113 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6114 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6115 for (unsigned i = 0; i != NumRegs; ++i) { 6116 ISD::InputArg MyFlags; 6117 MyFlags.VT = RegisterVT.getSimpleVT(); 6118 MyFlags.Used = isReturnValueUsed; 6119 if (RetSExt) 6120 MyFlags.Flags.setSExt(); 6121 if (RetZExt) 6122 MyFlags.Flags.setZExt(); 6123 if (isInreg) 6124 MyFlags.Flags.setInReg(); 6125 Ins.push_back(MyFlags); 6126 } 6127 } 6128 6129 SmallVector<SDValue, 4> InVals; 6130 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6131 Outs, OutVals, Ins, dl, DAG, InVals); 6132 6133 // Verify that the target's LowerCall behaved as expected. 6134 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6135 "LowerCall didn't return a valid chain!"); 6136 assert((!isTailCall || InVals.empty()) && 6137 "LowerCall emitted a return value for a tail call!"); 6138 assert((isTailCall || InVals.size() == Ins.size()) && 6139 "LowerCall didn't emit the correct number of values!"); 6140 6141 // For a tail call, the return value is merely live-out and there aren't 6142 // any nodes in the DAG representing it. Return a special value to 6143 // indicate that a tail call has been emitted and no more Instructions 6144 // should be processed in the current block. 6145 if (isTailCall) { 6146 DAG.setRoot(Chain); 6147 return std::make_pair(SDValue(), SDValue()); 6148 } 6149 6150 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6151 assert(InVals[i].getNode() && 6152 "LowerCall emitted a null value!"); 6153 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6154 "LowerCall emitted a value with the wrong type!"); 6155 }); 6156 6157 // Collect the legal value parts into potentially illegal values 6158 // that correspond to the original function's return values. 6159 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6160 if (RetSExt) 6161 AssertOp = ISD::AssertSext; 6162 else if (RetZExt) 6163 AssertOp = ISD::AssertZext; 6164 SmallVector<SDValue, 4> ReturnValues; 6165 unsigned CurReg = 0; 6166 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6167 EVT VT = RetTys[I]; 6168 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6169 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6170 6171 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6172 NumRegs, RegisterVT, VT, 6173 AssertOp)); 6174 CurReg += NumRegs; 6175 } 6176 6177 // For a function returning void, there is no return value. We can't create 6178 // such a node, so we just return a null return value in that case. In 6179 // that case, nothing will actualy look at the value. 6180 if (ReturnValues.empty()) 6181 return std::make_pair(SDValue(), Chain); 6182 6183 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6184 DAG.getVTList(&RetTys[0], RetTys.size()), 6185 &ReturnValues[0], ReturnValues.size()); 6186 return std::make_pair(Res, Chain); 6187} 6188 6189void TargetLowering::LowerOperationWrapper(SDNode *N, 6190 SmallVectorImpl<SDValue> &Results, 6191 SelectionDAG &DAG) const { 6192 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6193 if (Res.getNode()) 6194 Results.push_back(Res); 6195} 6196 6197SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6198 llvm_unreachable("LowerOperation not implemented for this target!"); 6199 return SDValue(); 6200} 6201 6202void 6203SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6204 SDValue Op = getNonRegisterValue(V); 6205 assert((Op.getOpcode() != ISD::CopyFromReg || 6206 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6207 "Copy from a reg to the same reg!"); 6208 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6209 6210 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6211 SDValue Chain = DAG.getEntryNode(); 6212 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6213 PendingExports.push_back(Chain); 6214} 6215 6216#include "llvm/CodeGen/SelectionDAGISel.h" 6217 6218void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6219 // If this is the entry block, emit arguments. 6220 const Function &F = *LLVMBB->getParent(); 6221 SelectionDAG &DAG = SDB->DAG; 6222 DebugLoc dl = SDB->getCurDebugLoc(); 6223 const TargetData *TD = TLI.getTargetData(); 6224 SmallVector<ISD::InputArg, 16> Ins; 6225 6226 // Check whether the function can return without sret-demotion. 6227 SmallVector<ISD::OutputArg, 4> Outs; 6228 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6229 Outs, TLI); 6230 6231 if (!FuncInfo->CanLowerReturn) { 6232 // Put in an sret pointer parameter before all the other parameters. 6233 SmallVector<EVT, 1> ValueVTs; 6234 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6235 6236 // NOTE: Assuming that a pointer will never break down to more than one VT 6237 // or one register. 6238 ISD::ArgFlagsTy Flags; 6239 Flags.setSRet(); 6240 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6241 ISD::InputArg RetArg(Flags, RegisterVT, true); 6242 Ins.push_back(RetArg); 6243 } 6244 6245 // Set up the incoming argument description vector. 6246 unsigned Idx = 1; 6247 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6248 I != E; ++I, ++Idx) { 6249 SmallVector<EVT, 4> ValueVTs; 6250 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6251 bool isArgValueUsed = !I->use_empty(); 6252 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6253 Value != NumValues; ++Value) { 6254 EVT VT = ValueVTs[Value]; 6255 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6256 ISD::ArgFlagsTy Flags; 6257 unsigned OriginalAlignment = 6258 TD->getABITypeAlignment(ArgTy); 6259 6260 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6261 Flags.setZExt(); 6262 if (F.paramHasAttr(Idx, Attribute::SExt)) 6263 Flags.setSExt(); 6264 if (F.paramHasAttr(Idx, Attribute::InReg)) 6265 Flags.setInReg(); 6266 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6267 Flags.setSRet(); 6268 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6269 Flags.setByVal(); 6270 const PointerType *Ty = cast<PointerType>(I->getType()); 6271 const Type *ElementTy = Ty->getElementType(); 6272 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6273 unsigned FrameSize = TD->getTypeAllocSize(ElementTy); 6274 // For ByVal, alignment should be passed from FE. BE will guess if 6275 // this info is not there but there are cases it cannot get right. 6276 if (F.getParamAlignment(Idx)) 6277 FrameAlign = F.getParamAlignment(Idx); 6278 Flags.setByValAlign(FrameAlign); 6279 Flags.setByValSize(FrameSize); 6280 } 6281 if (F.paramHasAttr(Idx, Attribute::Nest)) 6282 Flags.setNest(); 6283 Flags.setOrigAlign(OriginalAlignment); 6284 6285 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6286 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6287 for (unsigned i = 0; i != NumRegs; ++i) { 6288 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6289 if (NumRegs > 1 && i == 0) 6290 MyFlags.Flags.setSplit(); 6291 // if it isn't first piece, alignment must be 1 6292 else if (i > 0) 6293 MyFlags.Flags.setOrigAlign(1); 6294 Ins.push_back(MyFlags); 6295 } 6296 } 6297 } 6298 6299 // Call the target to set up the argument values. 6300 SmallVector<SDValue, 8> InVals; 6301 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6302 F.isVarArg(), Ins, 6303 dl, DAG, InVals); 6304 6305 // Verify that the target's LowerFormalArguments behaved as expected. 6306 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6307 "LowerFormalArguments didn't return a valid chain!"); 6308 assert(InVals.size() == Ins.size() && 6309 "LowerFormalArguments didn't emit the correct number of values!"); 6310 DEBUG({ 6311 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6312 assert(InVals[i].getNode() && 6313 "LowerFormalArguments emitted a null value!"); 6314 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6315 "LowerFormalArguments emitted a value with the wrong type!"); 6316 } 6317 }); 6318 6319 // Update the DAG with the new chain value resulting from argument lowering. 6320 DAG.setRoot(NewRoot); 6321 6322 // Set up the argument values. 6323 unsigned i = 0; 6324 Idx = 1; 6325 if (!FuncInfo->CanLowerReturn) { 6326 // Create a virtual register for the sret pointer, and put in a copy 6327 // from the sret argument into it. 6328 SmallVector<EVT, 1> ValueVTs; 6329 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6330 EVT VT = ValueVTs[0]; 6331 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6332 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6333 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6334 RegVT, VT, AssertOp); 6335 6336 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6337 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6338 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6339 FuncInfo->DemoteRegister = SRetReg; 6340 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6341 SRetReg, ArgValue); 6342 DAG.setRoot(NewRoot); 6343 6344 // i indexes lowered arguments. Bump it past the hidden sret argument. 6345 // Idx indexes LLVM arguments. Don't touch it. 6346 ++i; 6347 } 6348 6349 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6350 ++I, ++Idx) { 6351 SmallVector<SDValue, 4> ArgValues; 6352 SmallVector<EVT, 4> ValueVTs; 6353 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6354 unsigned NumValues = ValueVTs.size(); 6355 6356 // If this argument is unused then remember its value. It is used to generate 6357 // debugging information. 6358 if (I->use_empty() && NumValues) 6359 SDB->setUnusedArgValue(I, InVals[i]); 6360 6361 for (unsigned Value = 0; Value != NumValues; ++Value) { 6362 EVT VT = ValueVTs[Value]; 6363 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6364 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6365 6366 if (!I->use_empty()) { 6367 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6368 if (F.paramHasAttr(Idx, Attribute::SExt)) 6369 AssertOp = ISD::AssertSext; 6370 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6371 AssertOp = ISD::AssertZext; 6372 6373 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6374 NumParts, PartVT, VT, 6375 AssertOp)); 6376 } 6377 6378 i += NumParts; 6379 } 6380 6381 // Note down frame index for byval arguments. 6382 if (I->hasByValAttr() && !ArgValues.empty()) 6383 if (FrameIndexSDNode *FI = 6384 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6385 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6386 6387 if (!I->use_empty()) { 6388 SDValue Res; 6389 if (!ArgValues.empty()) 6390 Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6391 SDB->getCurDebugLoc()); 6392 SDB->setValue(I, Res); 6393 6394 // If this argument is live outside of the entry block, insert a copy from 6395 // whereever we got it to the vreg that other BB's will reference it as. 6396 SDB->CopyToExportRegsIfNeeded(I); 6397 } 6398 } 6399 6400 assert(i == InVals.size() && "Argument register count mismatch!"); 6401 6402 // Finally, if the target has anything special to do, allow it to do so. 6403 // FIXME: this should insert code into the DAG! 6404 EmitFunctionEntryCode(); 6405} 6406 6407/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6408/// ensure constants are generated when needed. Remember the virtual registers 6409/// that need to be added to the Machine PHI nodes as input. We cannot just 6410/// directly add them, because expansion might result in multiple MBB's for one 6411/// BB. As such, the start of the BB might correspond to a different MBB than 6412/// the end. 6413/// 6414void 6415SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6416 const TerminatorInst *TI = LLVMBB->getTerminator(); 6417 6418 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6419 6420 // Check successor nodes' PHI nodes that expect a constant to be available 6421 // from this block. 6422 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6423 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6424 if (!isa<PHINode>(SuccBB->begin())) continue; 6425 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6426 6427 // If this terminator has multiple identical successors (common for 6428 // switches), only handle each succ once. 6429 if (!SuccsHandled.insert(SuccMBB)) continue; 6430 6431 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6432 6433 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6434 // nodes and Machine PHI nodes, but the incoming operands have not been 6435 // emitted yet. 6436 for (BasicBlock::const_iterator I = SuccBB->begin(); 6437 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6438 // Ignore dead phi's. 6439 if (PN->use_empty()) continue; 6440 6441 unsigned Reg; 6442 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6443 6444 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6445 unsigned &RegOut = ConstantsOut[C]; 6446 if (RegOut == 0) { 6447 RegOut = FuncInfo.CreateRegs(C->getType()); 6448 CopyValueToVirtualRegister(C, RegOut); 6449 } 6450 Reg = RegOut; 6451 } else { 6452 DenseMap<const Value *, unsigned>::iterator I = 6453 FuncInfo.ValueMap.find(PHIOp); 6454 if (I != FuncInfo.ValueMap.end()) 6455 Reg = I->second; 6456 else { 6457 assert(isa<AllocaInst>(PHIOp) && 6458 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6459 "Didn't codegen value into a register!??"); 6460 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6461 CopyValueToVirtualRegister(PHIOp, Reg); 6462 } 6463 } 6464 6465 // Remember that this register needs to added to the machine PHI node as 6466 // the input for this MBB. 6467 SmallVector<EVT, 4> ValueVTs; 6468 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6469 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6470 EVT VT = ValueVTs[vti]; 6471 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6472 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6473 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6474 Reg += NumRegisters; 6475 } 6476 } 6477 } 6478 ConstantsOut.clear(); 6479} 6480