SelectionDAGBuilder.cpp revision ed4efd3358c69dc73eea174ac4b252402d17f471
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/PseudoSourceValue.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Analysis/DebugInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameLowering.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/CommandLine.h" 55#include "llvm/Support/Debug.h" 56#include "llvm/Support/ErrorHandling.h" 57#include "llvm/Support/MathExtras.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62/// LimitFloatPrecision - Generate low-precision inline sequences for 63/// some float libcalls (6, 8 or 12 bits). 64static unsigned LimitFloatPrecision; 65 66static cl::opt<unsigned, true> 67LimitFPPrecision("limit-float-precision", 68 cl::desc("Generate low-precision inline sequences " 69 "for some float libcalls"), 70 cl::location(LimitFloatPrecision), 71 cl::init(0)); 72 73// Limit the width of DAG chains. This is important in general to prevent 74// prevent DAG-based analysis from blowing up. For example, alias analysis and 75// load clustering may not complete in reasonable time. It is difficult to 76// recognize and avoid this situation within each individual analysis, and 77// future analyses are likely to have the same behavior. Limiting DAG width is 78// the safe approach, and will be especially important with global DAGs. 79// 80// MaxParallelChains default is arbitrarily high to avoid affecting 81// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 82// sequence over this should have been converted to llvm.memcpy by the 83// frontend. It easy to induce this behavior with .ll code such as: 84// %buffer = alloca [4096 x i8] 85// %data = load [4096 x i8]* %argPtr 86// store [4096 x i8] %data, [4096 x i8]* %buffer 87static cl::opt<unsigned> 88MaxParallelChains("dag-chain-limit", cl::desc("Max parallel isel dag chains"), 89 cl::init(64), cl::Hidden); 90 91static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 92 const SDValue *Parts, unsigned NumParts, 93 EVT PartVT, EVT ValueVT); 94 95/// getCopyFromParts - Create a value that contains the specified legal parts 96/// combined into the value they represent. If the parts combine to a type 97/// larger then ValueVT then AssertOp can be used to specify whether the extra 98/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 99/// (ISD::AssertSext). 100static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 101 const SDValue *Parts, 102 unsigned NumParts, EVT PartVT, EVT ValueVT, 103 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 104 if (ValueVT.isVector()) 105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 106 107 assert(NumParts > 0 && "No parts to assemble!"); 108 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 109 SDValue Val = Parts[0]; 110 111 if (NumParts > 1) { 112 // Assemble the value from multiple parts. 113 if (ValueVT.isInteger()) { 114 unsigned PartBits = PartVT.getSizeInBits(); 115 unsigned ValueBits = ValueVT.getSizeInBits(); 116 117 // Assemble the power of 2 part. 118 unsigned RoundParts = NumParts & (NumParts - 1) ? 119 1 << Log2_32(NumParts) : NumParts; 120 unsigned RoundBits = PartBits * RoundParts; 121 EVT RoundVT = RoundBits == ValueBits ? 122 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 123 SDValue Lo, Hi; 124 125 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 126 127 if (RoundParts > 2) { 128 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 129 PartVT, HalfVT); 130 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 131 RoundParts / 2, PartVT, HalfVT); 132 } else { 133 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 134 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 135 } 136 137 if (TLI.isBigEndian()) 138 std::swap(Lo, Hi); 139 140 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 141 142 if (RoundParts < NumParts) { 143 // Assemble the trailing non-power-of-2 part. 144 unsigned OddParts = NumParts - RoundParts; 145 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 146 Hi = getCopyFromParts(DAG, DL, 147 Parts + RoundParts, OddParts, PartVT, OddVT); 148 149 // Combine the round and odd parts. 150 Lo = Val; 151 if (TLI.isBigEndian()) 152 std::swap(Lo, Hi); 153 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 154 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 155 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 156 DAG.getConstant(Lo.getValueType().getSizeInBits(), 157 TLI.getPointerTy())); 158 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 159 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 160 } 161 } else if (PartVT.isFloatingPoint()) { 162 // FP split into multiple FP parts (for ppcf128) 163 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 164 "Unexpected split"); 165 SDValue Lo, Hi; 166 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 167 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 168 if (TLI.isBigEndian()) 169 std::swap(Lo, Hi); 170 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 171 } else { 172 // FP split into integer parts (soft fp) 173 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 174 !PartVT.isVector() && "Unexpected split"); 175 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 176 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 177 } 178 } 179 180 // There is now one part, held in Val. Correct it to match ValueVT. 181 PartVT = Val.getValueType(); 182 183 if (PartVT == ValueVT) 184 return Val; 185 186 if (PartVT.isInteger() && ValueVT.isInteger()) { 187 if (ValueVT.bitsLT(PartVT)) { 188 // For a truncate, see if we have any information to 189 // indicate whether the truncated bits will always be 190 // zero or sign-extension. 191 if (AssertOp != ISD::DELETED_NODE) 192 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 193 DAG.getValueType(ValueVT)); 194 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 195 } 196 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 197 } 198 199 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 200 // FP_ROUND's are always exact here. 201 if (ValueVT.bitsLT(Val.getValueType())) 202 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 203 DAG.getIntPtrConstant(1)); 204 205 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 206 } 207 208 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 209 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 210 211 llvm_unreachable("Unknown mismatch!"); 212 return SDValue(); 213} 214 215/// getCopyFromParts - Create a value that contains the specified legal parts 216/// combined into the value they represent. If the parts combine to a type 217/// larger then ValueVT then AssertOp can be used to specify whether the extra 218/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 219/// (ISD::AssertSext). 220static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 221 const SDValue *Parts, unsigned NumParts, 222 EVT PartVT, EVT ValueVT) { 223 assert(ValueVT.isVector() && "Not a vector value"); 224 assert(NumParts > 0 && "No parts to assemble!"); 225 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 226 SDValue Val = Parts[0]; 227 228 // Handle a multi-element vector. 229 if (NumParts > 1) { 230 EVT IntermediateVT, RegisterVT; 231 unsigned NumIntermediates; 232 unsigned NumRegs = 233 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 234 NumIntermediates, RegisterVT); 235 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 236 NumParts = NumRegs; // Silence a compiler warning. 237 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 238 assert(RegisterVT == Parts[0].getValueType() && 239 "Part type doesn't match part!"); 240 241 // Assemble the parts into intermediate operands. 242 SmallVector<SDValue, 8> Ops(NumIntermediates); 243 if (NumIntermediates == NumParts) { 244 // If the register was not expanded, truncate or copy the value, 245 // as appropriate. 246 for (unsigned i = 0; i != NumParts; ++i) 247 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 248 PartVT, IntermediateVT); 249 } else if (NumParts > 0) { 250 // If the intermediate type was expanded, build the intermediate 251 // operands from the parts. 252 assert(NumParts % NumIntermediates == 0 && 253 "Must expand into a divisible number of parts!"); 254 unsigned Factor = NumParts / NumIntermediates; 255 for (unsigned i = 0; i != NumIntermediates; ++i) 256 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 257 PartVT, IntermediateVT); 258 } 259 260 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 261 // intermediate operands. 262 Val = DAG.getNode(IntermediateVT.isVector() ? 263 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 264 ValueVT, &Ops[0], NumIntermediates); 265 } 266 267 // There is now one part, held in Val. Correct it to match ValueVT. 268 PartVT = Val.getValueType(); 269 270 if (PartVT == ValueVT) 271 return Val; 272 273 if (PartVT.isVector()) { 274 // If the element type of the source/dest vectors are the same, but the 275 // parts vector has more elements than the value vector, then we have a 276 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 277 // elements we want. 278 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 279 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 280 "Cannot narrow, it would be a lossy transformation"); 281 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 282 DAG.getIntPtrConstant(0)); 283 } 284 285 // Vector/Vector bitcast. 286 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 287 } 288 289 assert(ValueVT.getVectorElementType() == PartVT && 290 ValueVT.getVectorNumElements() == 1 && 291 "Only trivial scalar-to-vector conversions should get here!"); 292 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 293} 294 295 296 297 298static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 299 SDValue Val, SDValue *Parts, unsigned NumParts, 300 EVT PartVT); 301 302/// getCopyToParts - Create a series of nodes that contain the specified value 303/// split into legal parts. If the parts contain more bits than Val, then, for 304/// integers, ExtendKind can be used to specify how to generate the extra bits. 305static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 306 SDValue Val, SDValue *Parts, unsigned NumParts, 307 EVT PartVT, 308 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 309 EVT ValueVT = Val.getValueType(); 310 311 // Handle the vector case separately. 312 if (ValueVT.isVector()) 313 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 314 315 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 316 unsigned PartBits = PartVT.getSizeInBits(); 317 unsigned OrigNumParts = NumParts; 318 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 319 320 if (NumParts == 0) 321 return; 322 323 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 324 if (PartVT == ValueVT) { 325 assert(NumParts == 1 && "No-op copy with multiple parts!"); 326 Parts[0] = Val; 327 return; 328 } 329 330 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 331 // If the parts cover more bits than the value has, promote the value. 332 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 333 assert(NumParts == 1 && "Do not know what to promote to!"); 334 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 335 } else { 336 assert(PartVT.isInteger() && ValueVT.isInteger() && 337 "Unknown mismatch!"); 338 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 339 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 340 } 341 } else if (PartBits == ValueVT.getSizeInBits()) { 342 // Different types of the same size. 343 assert(NumParts == 1 && PartVT != ValueVT); 344 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 345 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 346 // If the parts cover less bits than value has, truncate the value. 347 assert(PartVT.isInteger() && ValueVT.isInteger() && 348 "Unknown mismatch!"); 349 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 350 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 351 } 352 353 // The value may have changed - recompute ValueVT. 354 ValueVT = Val.getValueType(); 355 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 356 "Failed to tile the value with PartVT!"); 357 358 if (NumParts == 1) { 359 assert(PartVT == ValueVT && "Type conversion failed!"); 360 Parts[0] = Val; 361 return; 362 } 363 364 // Expand the value into multiple parts. 365 if (NumParts & (NumParts - 1)) { 366 // The number of parts is not a power of 2. Split off and copy the tail. 367 assert(PartVT.isInteger() && ValueVT.isInteger() && 368 "Do not know what to expand to!"); 369 unsigned RoundParts = 1 << Log2_32(NumParts); 370 unsigned RoundBits = RoundParts * PartBits; 371 unsigned OddParts = NumParts - RoundParts; 372 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 373 DAG.getIntPtrConstant(RoundBits)); 374 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 375 376 if (TLI.isBigEndian()) 377 // The odd parts were reversed by getCopyToParts - unreverse them. 378 std::reverse(Parts + RoundParts, Parts + NumParts); 379 380 NumParts = RoundParts; 381 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 382 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 383 } 384 385 // The number of parts is a power of 2. Repeatedly bisect the value using 386 // EXTRACT_ELEMENT. 387 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 388 EVT::getIntegerVT(*DAG.getContext(), 389 ValueVT.getSizeInBits()), 390 Val); 391 392 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 393 for (unsigned i = 0; i < NumParts; i += StepSize) { 394 unsigned ThisBits = StepSize * PartBits / 2; 395 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 396 SDValue &Part0 = Parts[i]; 397 SDValue &Part1 = Parts[i+StepSize/2]; 398 399 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 400 ThisVT, Part0, DAG.getIntPtrConstant(1)); 401 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 402 ThisVT, Part0, DAG.getIntPtrConstant(0)); 403 404 if (ThisBits == PartBits && ThisVT != PartVT) { 405 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 406 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 407 } 408 } 409 } 410 411 if (TLI.isBigEndian()) 412 std::reverse(Parts, Parts + OrigNumParts); 413} 414 415 416/// getCopyToPartsVector - Create a series of nodes that contain the specified 417/// value split into legal parts. 418static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 419 SDValue Val, SDValue *Parts, unsigned NumParts, 420 EVT PartVT) { 421 EVT ValueVT = Val.getValueType(); 422 assert(ValueVT.isVector() && "Not a vector"); 423 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 424 425 if (NumParts == 1) { 426 if (PartVT == ValueVT) { 427 // Nothing to do. 428 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 429 // Bitconvert vector->vector case. 430 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 431 } else if (PartVT.isVector() && 432 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&& 433 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 434 EVT ElementVT = PartVT.getVectorElementType(); 435 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 436 // undef elements. 437 SmallVector<SDValue, 16> Ops; 438 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 439 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 440 ElementVT, Val, DAG.getIntPtrConstant(i))); 441 442 for (unsigned i = ValueVT.getVectorNumElements(), 443 e = PartVT.getVectorNumElements(); i != e; ++i) 444 Ops.push_back(DAG.getUNDEF(ElementVT)); 445 446 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 447 448 // FIXME: Use CONCAT for 2x -> 4x. 449 450 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 451 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 452 } else { 453 // Vector -> scalar conversion. 454 assert(ValueVT.getVectorElementType() == PartVT && 455 ValueVT.getVectorNumElements() == 1 && 456 "Only trivial vector-to-scalar conversions should get here!"); 457 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 458 PartVT, Val, DAG.getIntPtrConstant(0)); 459 } 460 461 Parts[0] = Val; 462 return; 463 } 464 465 // Handle a multi-element vector. 466 EVT IntermediateVT, RegisterVT; 467 unsigned NumIntermediates; 468 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 469 IntermediateVT, 470 NumIntermediates, RegisterVT); 471 unsigned NumElements = ValueVT.getVectorNumElements(); 472 473 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 474 NumParts = NumRegs; // Silence a compiler warning. 475 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 476 477 // Split the vector into intermediate operands. 478 SmallVector<SDValue, 8> Ops(NumIntermediates); 479 for (unsigned i = 0; i != NumIntermediates; ++i) { 480 if (IntermediateVT.isVector()) 481 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 482 IntermediateVT, Val, 483 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 484 else 485 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 486 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 487 } 488 489 // Split the intermediate operands into legal parts. 490 if (NumParts == NumIntermediates) { 491 // If the register was not expanded, promote or copy the value, 492 // as appropriate. 493 for (unsigned i = 0; i != NumParts; ++i) 494 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 495 } else if (NumParts > 0) { 496 // If the intermediate type was expanded, split each the value into 497 // legal parts. 498 assert(NumParts % NumIntermediates == 0 && 499 "Must expand into a divisible number of parts!"); 500 unsigned Factor = NumParts / NumIntermediates; 501 for (unsigned i = 0; i != NumIntermediates; ++i) 502 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 503 } 504} 505 506 507 508 509namespace { 510 /// RegsForValue - This struct represents the registers (physical or virtual) 511 /// that a particular set of values is assigned, and the type information 512 /// about the value. The most common situation is to represent one value at a 513 /// time, but struct or array values are handled element-wise as multiple 514 /// values. The splitting of aggregates is performed recursively, so that we 515 /// never have aggregate-typed registers. The values at this point do not 516 /// necessarily have legal types, so each value may require one or more 517 /// registers of some legal type. 518 /// 519 struct RegsForValue { 520 /// ValueVTs - The value types of the values, which may not be legal, and 521 /// may need be promoted or synthesized from one or more registers. 522 /// 523 SmallVector<EVT, 4> ValueVTs; 524 525 /// RegVTs - The value types of the registers. This is the same size as 526 /// ValueVTs and it records, for each value, what the type of the assigned 527 /// register or registers are. (Individual values are never synthesized 528 /// from more than one type of register.) 529 /// 530 /// With virtual registers, the contents of RegVTs is redundant with TLI's 531 /// getRegisterType member function, however when with physical registers 532 /// it is necessary to have a separate record of the types. 533 /// 534 SmallVector<EVT, 4> RegVTs; 535 536 /// Regs - This list holds the registers assigned to the values. 537 /// Each legal or promoted value requires one register, and each 538 /// expanded value requires multiple registers. 539 /// 540 SmallVector<unsigned, 4> Regs; 541 542 RegsForValue() {} 543 544 RegsForValue(const SmallVector<unsigned, 4> ®s, 545 EVT regvt, EVT valuevt) 546 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 547 548 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 549 unsigned Reg, const Type *Ty) { 550 ComputeValueVTs(tli, Ty, ValueVTs); 551 552 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 553 EVT ValueVT = ValueVTs[Value]; 554 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 555 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 556 for (unsigned i = 0; i != NumRegs; ++i) 557 Regs.push_back(Reg + i); 558 RegVTs.push_back(RegisterVT); 559 Reg += NumRegs; 560 } 561 } 562 563 /// areValueTypesLegal - Return true if types of all the values are legal. 564 bool areValueTypesLegal(const TargetLowering &TLI) { 565 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 566 EVT RegisterVT = RegVTs[Value]; 567 if (!TLI.isTypeLegal(RegisterVT)) 568 return false; 569 } 570 return true; 571 } 572 573 /// append - Add the specified values to this one. 574 void append(const RegsForValue &RHS) { 575 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 576 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 577 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 578 } 579 580 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 581 /// this value and returns the result as a ValueVTs value. This uses 582 /// Chain/Flag as the input and updates them for the output Chain/Flag. 583 /// If the Flag pointer is NULL, no flag is used. 584 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 585 DebugLoc dl, 586 SDValue &Chain, SDValue *Flag) const; 587 588 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 589 /// specified value into the registers specified by this object. This uses 590 /// Chain/Flag as the input and updates them for the output Chain/Flag. 591 /// If the Flag pointer is NULL, no flag is used. 592 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 593 SDValue &Chain, SDValue *Flag) const; 594 595 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 596 /// operand list. This adds the code marker, matching input operand index 597 /// (if applicable), and includes the number of values added into it. 598 void AddInlineAsmOperands(unsigned Kind, 599 bool HasMatching, unsigned MatchingIdx, 600 SelectionDAG &DAG, 601 std::vector<SDValue> &Ops) const; 602 }; 603} 604 605/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 606/// this value and returns the result as a ValueVT value. This uses 607/// Chain/Flag as the input and updates them for the output Chain/Flag. 608/// If the Flag pointer is NULL, no flag is used. 609SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 610 FunctionLoweringInfo &FuncInfo, 611 DebugLoc dl, 612 SDValue &Chain, SDValue *Flag) const { 613 // A Value with type {} or [0 x %t] needs no registers. 614 if (ValueVTs.empty()) 615 return SDValue(); 616 617 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 618 619 // Assemble the legal parts into the final values. 620 SmallVector<SDValue, 4> Values(ValueVTs.size()); 621 SmallVector<SDValue, 8> Parts; 622 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 623 // Copy the legal parts from the registers. 624 EVT ValueVT = ValueVTs[Value]; 625 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 626 EVT RegisterVT = RegVTs[Value]; 627 628 Parts.resize(NumRegs); 629 for (unsigned i = 0; i != NumRegs; ++i) { 630 SDValue P; 631 if (Flag == 0) { 632 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 633 } else { 634 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 635 *Flag = P.getValue(2); 636 } 637 638 Chain = P.getValue(1); 639 Parts[i] = P; 640 641 // If the source register was virtual and if we know something about it, 642 // add an assert node. 643 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 644 !RegisterVT.isInteger() || RegisterVT.isVector() || 645 !FuncInfo.LiveOutRegInfo.inBounds(Regs[Part+i])) 646 continue; 647 648 const FunctionLoweringInfo::LiveOutInfo &LOI = 649 FuncInfo.LiveOutRegInfo[Regs[Part+i]]; 650 651 unsigned RegSize = RegisterVT.getSizeInBits(); 652 unsigned NumSignBits = LOI.NumSignBits; 653 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 654 655 // FIXME: We capture more information than the dag can represent. For 656 // now, just use the tightest assertzext/assertsext possible. 657 bool isSExt = true; 658 EVT FromVT(MVT::Other); 659 if (NumSignBits == RegSize) 660 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 661 else if (NumZeroBits >= RegSize-1) 662 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 663 else if (NumSignBits > RegSize-8) 664 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 665 else if (NumZeroBits >= RegSize-8) 666 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 667 else if (NumSignBits > RegSize-16) 668 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 669 else if (NumZeroBits >= RegSize-16) 670 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 671 else if (NumSignBits > RegSize-32) 672 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 673 else if (NumZeroBits >= RegSize-32) 674 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 675 else 676 continue; 677 678 // Add an assertion node. 679 assert(FromVT != MVT::Other); 680 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 681 RegisterVT, P, DAG.getValueType(FromVT)); 682 } 683 684 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 685 NumRegs, RegisterVT, ValueVT); 686 Part += NumRegs; 687 Parts.clear(); 688 } 689 690 return DAG.getNode(ISD::MERGE_VALUES, dl, 691 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 692 &Values[0], ValueVTs.size()); 693} 694 695/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 696/// specified value into the registers specified by this object. This uses 697/// Chain/Flag as the input and updates them for the output Chain/Flag. 698/// If the Flag pointer is NULL, no flag is used. 699void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 700 SDValue &Chain, SDValue *Flag) const { 701 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 702 703 // Get the list of the values's legal parts. 704 unsigned NumRegs = Regs.size(); 705 SmallVector<SDValue, 8> Parts(NumRegs); 706 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 707 EVT ValueVT = ValueVTs[Value]; 708 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 709 EVT RegisterVT = RegVTs[Value]; 710 711 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 712 &Parts[Part], NumParts, RegisterVT); 713 Part += NumParts; 714 } 715 716 // Copy the parts into the registers. 717 SmallVector<SDValue, 8> Chains(NumRegs); 718 for (unsigned i = 0; i != NumRegs; ++i) { 719 SDValue Part; 720 if (Flag == 0) { 721 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 722 } else { 723 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 724 *Flag = Part.getValue(1); 725 } 726 727 Chains[i] = Part.getValue(0); 728 } 729 730 if (NumRegs == 1 || Flag) 731 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 732 // flagged to it. That is the CopyToReg nodes and the user are considered 733 // a single scheduling unit. If we create a TokenFactor and return it as 734 // chain, then the TokenFactor is both a predecessor (operand) of the 735 // user as well as a successor (the TF operands are flagged to the user). 736 // c1, f1 = CopyToReg 737 // c2, f2 = CopyToReg 738 // c3 = TokenFactor c1, c2 739 // ... 740 // = op c3, ..., f2 741 Chain = Chains[NumRegs-1]; 742 else 743 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 744} 745 746/// AddInlineAsmOperands - Add this value to the specified inlineasm node 747/// operand list. This adds the code marker and includes the number of 748/// values added into it. 749void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 750 unsigned MatchingIdx, 751 SelectionDAG &DAG, 752 std::vector<SDValue> &Ops) const { 753 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 754 755 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 756 if (HasMatching) 757 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 758 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 759 Ops.push_back(Res); 760 761 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 762 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 763 EVT RegisterVT = RegVTs[Value]; 764 for (unsigned i = 0; i != NumRegs; ++i) { 765 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 766 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 767 } 768 } 769} 770 771void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 772 AA = &aa; 773 GFI = gfi; 774 TD = DAG.getTarget().getTargetData(); 775} 776 777/// clear - Clear out the current SelectionDAG and the associated 778/// state and prepare this SelectionDAGBuilder object to be used 779/// for a new block. This doesn't clear out information about 780/// additional blocks that are needed to complete switch lowering 781/// or PHI node updating; that information is cleared out as it is 782/// consumed. 783void SelectionDAGBuilder::clear() { 784 NodeMap.clear(); 785 UnusedArgNodeMap.clear(); 786 PendingLoads.clear(); 787 PendingExports.clear(); 788 DanglingDebugInfoMap.clear(); 789 CurDebugLoc = DebugLoc(); 790 HasTailCall = false; 791} 792 793/// getRoot - Return the current virtual root of the Selection DAG, 794/// flushing any PendingLoad items. This must be done before emitting 795/// a store or any other node that may need to be ordered after any 796/// prior load instructions. 797/// 798SDValue SelectionDAGBuilder::getRoot() { 799 if (PendingLoads.empty()) 800 return DAG.getRoot(); 801 802 if (PendingLoads.size() == 1) { 803 SDValue Root = PendingLoads[0]; 804 DAG.setRoot(Root); 805 PendingLoads.clear(); 806 return Root; 807 } 808 809 // Otherwise, we have to make a token factor node. 810 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 811 &PendingLoads[0], PendingLoads.size()); 812 PendingLoads.clear(); 813 DAG.setRoot(Root); 814 return Root; 815} 816 817/// getControlRoot - Similar to getRoot, but instead of flushing all the 818/// PendingLoad items, flush all the PendingExports items. It is necessary 819/// to do this before emitting a terminator instruction. 820/// 821SDValue SelectionDAGBuilder::getControlRoot() { 822 SDValue Root = DAG.getRoot(); 823 824 if (PendingExports.empty()) 825 return Root; 826 827 // Turn all of the CopyToReg chains into one factored node. 828 if (Root.getOpcode() != ISD::EntryToken) { 829 unsigned i = 0, e = PendingExports.size(); 830 for (; i != e; ++i) { 831 assert(PendingExports[i].getNode()->getNumOperands() > 1); 832 if (PendingExports[i].getNode()->getOperand(0) == Root) 833 break; // Don't add the root if we already indirectly depend on it. 834 } 835 836 if (i == e) 837 PendingExports.push_back(Root); 838 } 839 840 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 841 &PendingExports[0], 842 PendingExports.size()); 843 PendingExports.clear(); 844 DAG.setRoot(Root); 845 return Root; 846} 847 848void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 849 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 850 DAG.AssignOrdering(Node, SDNodeOrder); 851 852 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 853 AssignOrderingToNode(Node->getOperand(I).getNode()); 854} 855 856void SelectionDAGBuilder::visit(const Instruction &I) { 857 // Set up outgoing PHI node register values before emitting the terminator. 858 if (isa<TerminatorInst>(&I)) 859 HandlePHINodesInSuccessorBlocks(I.getParent()); 860 861 CurDebugLoc = I.getDebugLoc(); 862 863 visit(I.getOpcode(), I); 864 865 if (!isa<TerminatorInst>(&I) && !HasTailCall) 866 CopyToExportRegsIfNeeded(&I); 867 868 CurDebugLoc = DebugLoc(); 869} 870 871void SelectionDAGBuilder::visitPHI(const PHINode &) { 872 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 873} 874 875void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 876 // Note: this doesn't use InstVisitor, because it has to work with 877 // ConstantExpr's in addition to instructions. 878 switch (Opcode) { 879 default: llvm_unreachable("Unknown instruction type encountered!"); 880 // Build the switch statement using the Instruction.def file. 881#define HANDLE_INST(NUM, OPCODE, CLASS) \ 882 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 883#include "llvm/Instruction.def" 884 } 885 886 // Assign the ordering to the freshly created DAG nodes. 887 if (NodeMap.count(&I)) { 888 ++SDNodeOrder; 889 AssignOrderingToNode(getValue(&I).getNode()); 890 } 891} 892 893// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 894// generate the debug data structures now that we've seen its definition. 895void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 896 SDValue Val) { 897 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 898 if (DDI.getDI()) { 899 const DbgValueInst *DI = DDI.getDI(); 900 DebugLoc dl = DDI.getdl(); 901 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 902 MDNode *Variable = DI->getVariable(); 903 uint64_t Offset = DI->getOffset(); 904 SDDbgValue *SDV; 905 if (Val.getNode()) { 906 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 907 SDV = DAG.getDbgValue(Variable, Val.getNode(), 908 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 909 DAG.AddDbgValue(SDV, Val.getNode(), false); 910 } 911 } else 912 DEBUG(dbgs() << "Dropping debug info for " << DI); 913 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 914 } 915} 916 917// getValue - Return an SDValue for the given Value. 918SDValue SelectionDAGBuilder::getValue(const Value *V) { 919 // If we already have an SDValue for this value, use it. It's important 920 // to do this first, so that we don't create a CopyFromReg if we already 921 // have a regular SDValue. 922 SDValue &N = NodeMap[V]; 923 if (N.getNode()) return N; 924 925 // If there's a virtual register allocated and initialized for this 926 // value, use it. 927 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 928 if (It != FuncInfo.ValueMap.end()) { 929 unsigned InReg = It->second; 930 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 931 SDValue Chain = DAG.getEntryNode(); 932 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 933 resolveDanglingDebugInfo(V, N); 934 return N; 935 } 936 937 // Otherwise create a new SDValue and remember it. 938 SDValue Val = getValueImpl(V); 939 NodeMap[V] = Val; 940 resolveDanglingDebugInfo(V, Val); 941 return Val; 942} 943 944/// getNonRegisterValue - Return an SDValue for the given Value, but 945/// don't look in FuncInfo.ValueMap for a virtual register. 946SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 947 // If we already have an SDValue for this value, use it. 948 SDValue &N = NodeMap[V]; 949 if (N.getNode()) return N; 950 951 // Otherwise create a new SDValue and remember it. 952 SDValue Val = getValueImpl(V); 953 NodeMap[V] = Val; 954 resolveDanglingDebugInfo(V, Val); 955 return Val; 956} 957 958/// getValueImpl - Helper function for getValue and getNonRegisterValue. 959/// Create an SDValue for the given value. 960SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 961 if (const Constant *C = dyn_cast<Constant>(V)) { 962 EVT VT = TLI.getValueType(V->getType(), true); 963 964 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 965 return DAG.getConstant(*CI, VT); 966 967 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 968 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 969 970 if (isa<ConstantPointerNull>(C)) 971 return DAG.getConstant(0, TLI.getPointerTy()); 972 973 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 974 return DAG.getConstantFP(*CFP, VT); 975 976 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 977 return DAG.getUNDEF(VT); 978 979 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 980 visit(CE->getOpcode(), *CE); 981 SDValue N1 = NodeMap[V]; 982 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 983 return N1; 984 } 985 986 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 987 SmallVector<SDValue, 4> Constants; 988 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 989 OI != OE; ++OI) { 990 SDNode *Val = getValue(*OI).getNode(); 991 // If the operand is an empty aggregate, there are no values. 992 if (!Val) continue; 993 // Add each leaf value from the operand to the Constants list 994 // to form a flattened list of all the values. 995 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 996 Constants.push_back(SDValue(Val, i)); 997 } 998 999 return DAG.getMergeValues(&Constants[0], Constants.size(), 1000 getCurDebugLoc()); 1001 } 1002 1003 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1004 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1005 "Unknown struct or array constant!"); 1006 1007 SmallVector<EVT, 4> ValueVTs; 1008 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1009 unsigned NumElts = ValueVTs.size(); 1010 if (NumElts == 0) 1011 return SDValue(); // empty struct 1012 SmallVector<SDValue, 4> Constants(NumElts); 1013 for (unsigned i = 0; i != NumElts; ++i) { 1014 EVT EltVT = ValueVTs[i]; 1015 if (isa<UndefValue>(C)) 1016 Constants[i] = DAG.getUNDEF(EltVT); 1017 else if (EltVT.isFloatingPoint()) 1018 Constants[i] = DAG.getConstantFP(0, EltVT); 1019 else 1020 Constants[i] = DAG.getConstant(0, EltVT); 1021 } 1022 1023 return DAG.getMergeValues(&Constants[0], NumElts, 1024 getCurDebugLoc()); 1025 } 1026 1027 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1028 return DAG.getBlockAddress(BA, VT); 1029 1030 const VectorType *VecTy = cast<VectorType>(V->getType()); 1031 unsigned NumElements = VecTy->getNumElements(); 1032 1033 // Now that we know the number and type of the elements, get that number of 1034 // elements into the Ops array based on what kind of constant it is. 1035 SmallVector<SDValue, 16> Ops; 1036 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1037 for (unsigned i = 0; i != NumElements; ++i) 1038 Ops.push_back(getValue(CP->getOperand(i))); 1039 } else { 1040 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1041 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1042 1043 SDValue Op; 1044 if (EltVT.isFloatingPoint()) 1045 Op = DAG.getConstantFP(0, EltVT); 1046 else 1047 Op = DAG.getConstant(0, EltVT); 1048 Ops.assign(NumElements, Op); 1049 } 1050 1051 // Create a BUILD_VECTOR node. 1052 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1053 VT, &Ops[0], Ops.size()); 1054 } 1055 1056 // If this is a static alloca, generate it as the frameindex instead of 1057 // computation. 1058 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1059 DenseMap<const AllocaInst*, int>::iterator SI = 1060 FuncInfo.StaticAllocaMap.find(AI); 1061 if (SI != FuncInfo.StaticAllocaMap.end()) 1062 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1063 } 1064 1065 // If this is an instruction which fast-isel has deferred, select it now. 1066 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1067 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1068 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1069 SDValue Chain = DAG.getEntryNode(); 1070 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1071 } 1072 1073 llvm_unreachable("Can't get register for value!"); 1074 return SDValue(); 1075} 1076 1077void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1078 SDValue Chain = getControlRoot(); 1079 SmallVector<ISD::OutputArg, 8> Outs; 1080 SmallVector<SDValue, 8> OutVals; 1081 1082 if (!FuncInfo.CanLowerReturn) { 1083 unsigned DemoteReg = FuncInfo.DemoteRegister; 1084 const Function *F = I.getParent()->getParent(); 1085 1086 // Emit a store of the return value through the virtual register. 1087 // Leave Outs empty so that LowerReturn won't try to load return 1088 // registers the usual way. 1089 SmallVector<EVT, 1> PtrValueVTs; 1090 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1091 PtrValueVTs); 1092 1093 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1094 SDValue RetOp = getValue(I.getOperand(0)); 1095 1096 SmallVector<EVT, 4> ValueVTs; 1097 SmallVector<uint64_t, 4> Offsets; 1098 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1099 unsigned NumValues = ValueVTs.size(); 1100 1101 SmallVector<SDValue, 4> Chains(NumValues); 1102 for (unsigned i = 0; i != NumValues; ++i) { 1103 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1104 RetPtr.getValueType(), RetPtr, 1105 DAG.getIntPtrConstant(Offsets[i])); 1106 Chains[i] = 1107 DAG.getStore(Chain, getCurDebugLoc(), 1108 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1109 // FIXME: better loc info would be nice. 1110 Add, MachinePointerInfo(), false, false, 0); 1111 } 1112 1113 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1114 MVT::Other, &Chains[0], NumValues); 1115 } else if (I.getNumOperands() != 0) { 1116 SmallVector<EVT, 4> ValueVTs; 1117 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1118 unsigned NumValues = ValueVTs.size(); 1119 if (NumValues) { 1120 SDValue RetOp = getValue(I.getOperand(0)); 1121 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1122 EVT VT = ValueVTs[j]; 1123 1124 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1125 1126 const Function *F = I.getParent()->getParent(); 1127 if (F->paramHasAttr(0, Attribute::SExt)) 1128 ExtendKind = ISD::SIGN_EXTEND; 1129 else if (F->paramHasAttr(0, Attribute::ZExt)) 1130 ExtendKind = ISD::ZERO_EXTEND; 1131 1132 // FIXME: C calling convention requires the return type to be promoted 1133 // to at least 32-bit. But this is not necessary for non-C calling 1134 // conventions. The frontend should mark functions whose return values 1135 // require promoting with signext or zeroext attributes. 1136 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1137 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32); 1138 if (VT.bitsLT(MinVT)) 1139 VT = MinVT; 1140 } 1141 1142 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1143 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1144 SmallVector<SDValue, 4> Parts(NumParts); 1145 getCopyToParts(DAG, getCurDebugLoc(), 1146 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1147 &Parts[0], NumParts, PartVT, ExtendKind); 1148 1149 // 'inreg' on function refers to return value 1150 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1151 if (F->paramHasAttr(0, Attribute::InReg)) 1152 Flags.setInReg(); 1153 1154 // Propagate extension type if any 1155 if (F->paramHasAttr(0, Attribute::SExt)) 1156 Flags.setSExt(); 1157 else if (F->paramHasAttr(0, Attribute::ZExt)) 1158 Flags.setZExt(); 1159 1160 for (unsigned i = 0; i < NumParts; ++i) { 1161 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1162 /*isfixed=*/true)); 1163 OutVals.push_back(Parts[i]); 1164 } 1165 } 1166 } 1167 } 1168 1169 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1170 CallingConv::ID CallConv = 1171 DAG.getMachineFunction().getFunction()->getCallingConv(); 1172 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1173 Outs, OutVals, getCurDebugLoc(), DAG); 1174 1175 // Verify that the target's LowerReturn behaved as expected. 1176 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1177 "LowerReturn didn't return a valid chain!"); 1178 1179 // Update the DAG with the new chain value resulting from return lowering. 1180 DAG.setRoot(Chain); 1181} 1182 1183/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1184/// created for it, emit nodes to copy the value into the virtual 1185/// registers. 1186void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1187 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1188 if (VMI != FuncInfo.ValueMap.end()) { 1189 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1190 CopyValueToVirtualRegister(V, VMI->second); 1191 } 1192} 1193 1194/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1195/// the current basic block, add it to ValueMap now so that we'll get a 1196/// CopyTo/FromReg. 1197void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1198 // No need to export constants. 1199 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1200 1201 // Already exported? 1202 if (FuncInfo.isExportedInst(V)) return; 1203 1204 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1205 CopyValueToVirtualRegister(V, Reg); 1206} 1207 1208bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1209 const BasicBlock *FromBB) { 1210 // The operands of the setcc have to be in this block. We don't know 1211 // how to export them from some other block. 1212 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1213 // Can export from current BB. 1214 if (VI->getParent() == FromBB) 1215 return true; 1216 1217 // Is already exported, noop. 1218 return FuncInfo.isExportedInst(V); 1219 } 1220 1221 // If this is an argument, we can export it if the BB is the entry block or 1222 // if it is already exported. 1223 if (isa<Argument>(V)) { 1224 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1225 return true; 1226 1227 // Otherwise, can only export this if it is already exported. 1228 return FuncInfo.isExportedInst(V); 1229 } 1230 1231 // Otherwise, constants can always be exported. 1232 return true; 1233} 1234 1235static bool InBlock(const Value *V, const BasicBlock *BB) { 1236 if (const Instruction *I = dyn_cast<Instruction>(V)) 1237 return I->getParent() == BB; 1238 return true; 1239} 1240 1241/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1242/// This function emits a branch and is used at the leaves of an OR or an 1243/// AND operator tree. 1244/// 1245void 1246SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1247 MachineBasicBlock *TBB, 1248 MachineBasicBlock *FBB, 1249 MachineBasicBlock *CurBB, 1250 MachineBasicBlock *SwitchBB) { 1251 const BasicBlock *BB = CurBB->getBasicBlock(); 1252 1253 // If the leaf of the tree is a comparison, merge the condition into 1254 // the caseblock. 1255 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1256 // The operands of the cmp have to be in this block. We don't know 1257 // how to export them from some other block. If this is the first block 1258 // of the sequence, no exporting is needed. 1259 if (CurBB == SwitchBB || 1260 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1261 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1262 ISD::CondCode Condition; 1263 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1264 Condition = getICmpCondCode(IC->getPredicate()); 1265 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1266 Condition = getFCmpCondCode(FC->getPredicate()); 1267 } else { 1268 Condition = ISD::SETEQ; // silence warning. 1269 llvm_unreachable("Unknown compare instruction"); 1270 } 1271 1272 CaseBlock CB(Condition, BOp->getOperand(0), 1273 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1274 SwitchCases.push_back(CB); 1275 return; 1276 } 1277 } 1278 1279 // Create a CaseBlock record representing this branch. 1280 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1281 NULL, TBB, FBB, CurBB); 1282 SwitchCases.push_back(CB); 1283} 1284 1285/// FindMergedConditions - If Cond is an expression like 1286void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1287 MachineBasicBlock *TBB, 1288 MachineBasicBlock *FBB, 1289 MachineBasicBlock *CurBB, 1290 MachineBasicBlock *SwitchBB, 1291 unsigned Opc) { 1292 // If this node is not part of the or/and tree, emit it as a branch. 1293 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1294 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1295 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1296 BOp->getParent() != CurBB->getBasicBlock() || 1297 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1298 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1299 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1300 return; 1301 } 1302 1303 // Create TmpBB after CurBB. 1304 MachineFunction::iterator BBI = CurBB; 1305 MachineFunction &MF = DAG.getMachineFunction(); 1306 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1307 CurBB->getParent()->insert(++BBI, TmpBB); 1308 1309 if (Opc == Instruction::Or) { 1310 // Codegen X | Y as: 1311 // jmp_if_X TBB 1312 // jmp TmpBB 1313 // TmpBB: 1314 // jmp_if_Y TBB 1315 // jmp FBB 1316 // 1317 1318 // Emit the LHS condition. 1319 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1320 1321 // Emit the RHS condition into TmpBB. 1322 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1323 } else { 1324 assert(Opc == Instruction::And && "Unknown merge op!"); 1325 // Codegen X & Y as: 1326 // jmp_if_X TmpBB 1327 // jmp FBB 1328 // TmpBB: 1329 // jmp_if_Y TBB 1330 // jmp FBB 1331 // 1332 // This requires creation of TmpBB after CurBB. 1333 1334 // Emit the LHS condition. 1335 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1336 1337 // Emit the RHS condition into TmpBB. 1338 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1339 } 1340} 1341 1342/// If the set of cases should be emitted as a series of branches, return true. 1343/// If we should emit this as a bunch of and/or'd together conditions, return 1344/// false. 1345bool 1346SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1347 if (Cases.size() != 2) return true; 1348 1349 // If this is two comparisons of the same values or'd or and'd together, they 1350 // will get folded into a single comparison, so don't emit two blocks. 1351 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1352 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1353 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1354 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1355 return false; 1356 } 1357 1358 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1359 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1360 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1361 Cases[0].CC == Cases[1].CC && 1362 isa<Constant>(Cases[0].CmpRHS) && 1363 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1364 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1365 return false; 1366 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1367 return false; 1368 } 1369 1370 return true; 1371} 1372 1373void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1374 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1375 1376 // Update machine-CFG edges. 1377 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1378 1379 // Figure out which block is immediately after the current one. 1380 MachineBasicBlock *NextBlock = 0; 1381 MachineFunction::iterator BBI = BrMBB; 1382 if (++BBI != FuncInfo.MF->end()) 1383 NextBlock = BBI; 1384 1385 if (I.isUnconditional()) { 1386 // Update machine-CFG edges. 1387 BrMBB->addSuccessor(Succ0MBB); 1388 1389 // If this is not a fall-through branch, emit the branch. 1390 if (Succ0MBB != NextBlock) 1391 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1392 MVT::Other, getControlRoot(), 1393 DAG.getBasicBlock(Succ0MBB))); 1394 1395 return; 1396 } 1397 1398 // If this condition is one of the special cases we handle, do special stuff 1399 // now. 1400 const Value *CondVal = I.getCondition(); 1401 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1402 1403 // If this is a series of conditions that are or'd or and'd together, emit 1404 // this as a sequence of branches instead of setcc's with and/or operations. 1405 // As long as jumps are not expensive, this should improve performance. 1406 // For example, instead of something like: 1407 // cmp A, B 1408 // C = seteq 1409 // cmp D, E 1410 // F = setle 1411 // or C, F 1412 // jnz foo 1413 // Emit: 1414 // cmp A, B 1415 // je foo 1416 // cmp D, E 1417 // jle foo 1418 // 1419 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1420 if (!TLI.isJumpExpensive() && 1421 BOp->hasOneUse() && 1422 (BOp->getOpcode() == Instruction::And || 1423 BOp->getOpcode() == Instruction::Or)) { 1424 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1425 BOp->getOpcode()); 1426 // If the compares in later blocks need to use values not currently 1427 // exported from this block, export them now. This block should always 1428 // be the first entry. 1429 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1430 1431 // Allow some cases to be rejected. 1432 if (ShouldEmitAsBranches(SwitchCases)) { 1433 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1434 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1435 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1436 } 1437 1438 // Emit the branch for this block. 1439 visitSwitchCase(SwitchCases[0], BrMBB); 1440 SwitchCases.erase(SwitchCases.begin()); 1441 return; 1442 } 1443 1444 // Okay, we decided not to do this, remove any inserted MBB's and clear 1445 // SwitchCases. 1446 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1447 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1448 1449 SwitchCases.clear(); 1450 } 1451 } 1452 1453 // Create a CaseBlock record representing this branch. 1454 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1455 NULL, Succ0MBB, Succ1MBB, BrMBB); 1456 1457 // Use visitSwitchCase to actually insert the fast branch sequence for this 1458 // cond branch. 1459 visitSwitchCase(CB, BrMBB); 1460} 1461 1462/// visitSwitchCase - Emits the necessary code to represent a single node in 1463/// the binary search tree resulting from lowering a switch instruction. 1464void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1465 MachineBasicBlock *SwitchBB) { 1466 SDValue Cond; 1467 SDValue CondLHS = getValue(CB.CmpLHS); 1468 DebugLoc dl = getCurDebugLoc(); 1469 1470 // Build the setcc now. 1471 if (CB.CmpMHS == NULL) { 1472 // Fold "(X == true)" to X and "(X == false)" to !X to 1473 // handle common cases produced by branch lowering. 1474 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1475 CB.CC == ISD::SETEQ) 1476 Cond = CondLHS; 1477 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1478 CB.CC == ISD::SETEQ) { 1479 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1480 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1481 } else 1482 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1483 } else { 1484 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1485 1486 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1487 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1488 1489 SDValue CmpOp = getValue(CB.CmpMHS); 1490 EVT VT = CmpOp.getValueType(); 1491 1492 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1493 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1494 ISD::SETLE); 1495 } else { 1496 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1497 VT, CmpOp, DAG.getConstant(Low, VT)); 1498 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1499 DAG.getConstant(High-Low, VT), ISD::SETULE); 1500 } 1501 } 1502 1503 // Update successor info 1504 SwitchBB->addSuccessor(CB.TrueBB); 1505 SwitchBB->addSuccessor(CB.FalseBB); 1506 1507 // Set NextBlock to be the MBB immediately after the current one, if any. 1508 // This is used to avoid emitting unnecessary branches to the next block. 1509 MachineBasicBlock *NextBlock = 0; 1510 MachineFunction::iterator BBI = SwitchBB; 1511 if (++BBI != FuncInfo.MF->end()) 1512 NextBlock = BBI; 1513 1514 // If the lhs block is the next block, invert the condition so that we can 1515 // fall through to the lhs instead of the rhs block. 1516 if (CB.TrueBB == NextBlock) { 1517 std::swap(CB.TrueBB, CB.FalseBB); 1518 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1519 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1520 } 1521 1522 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1523 MVT::Other, getControlRoot(), Cond, 1524 DAG.getBasicBlock(CB.TrueBB)); 1525 1526 // Insert the false branch. Do this even if it's a fall through branch, 1527 // this makes it easier to do DAG optimizations which require inverting 1528 // the branch condition. 1529 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1530 DAG.getBasicBlock(CB.FalseBB)); 1531 1532 DAG.setRoot(BrCond); 1533} 1534 1535/// visitJumpTable - Emit JumpTable node in the current MBB 1536void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1537 // Emit the code for the jump table 1538 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1539 EVT PTy = TLI.getPointerTy(); 1540 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1541 JT.Reg, PTy); 1542 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1543 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1544 MVT::Other, Index.getValue(1), 1545 Table, Index); 1546 DAG.setRoot(BrJumpTable); 1547} 1548 1549/// visitJumpTableHeader - This function emits necessary code to produce index 1550/// in the JumpTable from switch case. 1551void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1552 JumpTableHeader &JTH, 1553 MachineBasicBlock *SwitchBB) { 1554 // Subtract the lowest switch case value from the value being switched on and 1555 // conditional branch to default mbb if the result is greater than the 1556 // difference between smallest and largest cases. 1557 SDValue SwitchOp = getValue(JTH.SValue); 1558 EVT VT = SwitchOp.getValueType(); 1559 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1560 DAG.getConstant(JTH.First, VT)); 1561 1562 // The SDNode we just created, which holds the value being switched on minus 1563 // the smallest case value, needs to be copied to a virtual register so it 1564 // can be used as an index into the jump table in a subsequent basic block. 1565 // This value may be smaller or larger than the target's pointer type, and 1566 // therefore require extension or truncating. 1567 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1568 1569 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1570 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1571 JumpTableReg, SwitchOp); 1572 JT.Reg = JumpTableReg; 1573 1574 // Emit the range check for the jump table, and branch to the default block 1575 // for the switch statement if the value being switched on exceeds the largest 1576 // case in the switch. 1577 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1578 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1579 DAG.getConstant(JTH.Last-JTH.First,VT), 1580 ISD::SETUGT); 1581 1582 // Set NextBlock to be the MBB immediately after the current one, if any. 1583 // This is used to avoid emitting unnecessary branches to the next block. 1584 MachineBasicBlock *NextBlock = 0; 1585 MachineFunction::iterator BBI = SwitchBB; 1586 1587 if (++BBI != FuncInfo.MF->end()) 1588 NextBlock = BBI; 1589 1590 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1591 MVT::Other, CopyTo, CMP, 1592 DAG.getBasicBlock(JT.Default)); 1593 1594 if (JT.MBB != NextBlock) 1595 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1596 DAG.getBasicBlock(JT.MBB)); 1597 1598 DAG.setRoot(BrCond); 1599} 1600 1601/// visitBitTestHeader - This function emits necessary code to produce value 1602/// suitable for "bit tests" 1603void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1604 MachineBasicBlock *SwitchBB) { 1605 // Subtract the minimum value 1606 SDValue SwitchOp = getValue(B.SValue); 1607 EVT VT = SwitchOp.getValueType(); 1608 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1609 DAG.getConstant(B.First, VT)); 1610 1611 // Check range 1612 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1613 TLI.getSetCCResultType(Sub.getValueType()), 1614 Sub, DAG.getConstant(B.Range, VT), 1615 ISD::SETUGT); 1616 1617 // Determine the type of the test operands. 1618 bool UsePtrType = false; 1619 if (!TLI.isTypeLegal(VT)) 1620 UsePtrType = true; 1621 else { 1622 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1623 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) { 1624 // Switch table case range are encoded into series of masks. 1625 // Just use pointer type, it's guaranteed to fit. 1626 UsePtrType = true; 1627 break; 1628 } 1629 } 1630 if (UsePtrType) { 1631 VT = TLI.getPointerTy(); 1632 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1633 } 1634 1635 B.RegVT = VT; 1636 B.Reg = FuncInfo.CreateReg(VT); 1637 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1638 B.Reg, Sub); 1639 1640 // Set NextBlock to be the MBB immediately after the current one, if any. 1641 // This is used to avoid emitting unnecessary branches to the next block. 1642 MachineBasicBlock *NextBlock = 0; 1643 MachineFunction::iterator BBI = SwitchBB; 1644 if (++BBI != FuncInfo.MF->end()) 1645 NextBlock = BBI; 1646 1647 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1648 1649 SwitchBB->addSuccessor(B.Default); 1650 SwitchBB->addSuccessor(MBB); 1651 1652 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1653 MVT::Other, CopyTo, RangeCmp, 1654 DAG.getBasicBlock(B.Default)); 1655 1656 if (MBB != NextBlock) 1657 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1658 DAG.getBasicBlock(MBB)); 1659 1660 DAG.setRoot(BrRange); 1661} 1662 1663/// visitBitTestCase - this function produces one "bit test" 1664void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1665 MachineBasicBlock* NextMBB, 1666 unsigned Reg, 1667 BitTestCase &B, 1668 MachineBasicBlock *SwitchBB) { 1669 EVT VT = BB.RegVT; 1670 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1671 Reg, VT); 1672 SDValue Cmp; 1673 if (CountPopulation_64(B.Mask) == 1) { 1674 // Testing for a single bit; just compare the shift count with what it 1675 // would need to be to shift a 1 bit in that position. 1676 Cmp = DAG.getSetCC(getCurDebugLoc(), 1677 TLI.getSetCCResultType(VT), 1678 ShiftOp, 1679 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1680 ISD::SETEQ); 1681 } else { 1682 // Make desired shift 1683 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1684 DAG.getConstant(1, VT), ShiftOp); 1685 1686 // Emit bit tests and jumps 1687 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1688 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1689 Cmp = DAG.getSetCC(getCurDebugLoc(), 1690 TLI.getSetCCResultType(VT), 1691 AndOp, DAG.getConstant(0, VT), 1692 ISD::SETNE); 1693 } 1694 1695 SwitchBB->addSuccessor(B.TargetBB); 1696 SwitchBB->addSuccessor(NextMBB); 1697 1698 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1699 MVT::Other, getControlRoot(), 1700 Cmp, DAG.getBasicBlock(B.TargetBB)); 1701 1702 // Set NextBlock to be the MBB immediately after the current one, if any. 1703 // This is used to avoid emitting unnecessary branches to the next block. 1704 MachineBasicBlock *NextBlock = 0; 1705 MachineFunction::iterator BBI = SwitchBB; 1706 if (++BBI != FuncInfo.MF->end()) 1707 NextBlock = BBI; 1708 1709 if (NextMBB != NextBlock) 1710 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1711 DAG.getBasicBlock(NextMBB)); 1712 1713 DAG.setRoot(BrAnd); 1714} 1715 1716void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1717 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1718 1719 // Retrieve successors. 1720 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1721 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1722 1723 const Value *Callee(I.getCalledValue()); 1724 if (isa<InlineAsm>(Callee)) 1725 visitInlineAsm(&I); 1726 else 1727 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1728 1729 // If the value of the invoke is used outside of its defining block, make it 1730 // available as a virtual register. 1731 CopyToExportRegsIfNeeded(&I); 1732 1733 // Update successor info 1734 InvokeMBB->addSuccessor(Return); 1735 InvokeMBB->addSuccessor(LandingPad); 1736 1737 // Drop into normal successor. 1738 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1739 MVT::Other, getControlRoot(), 1740 DAG.getBasicBlock(Return))); 1741} 1742 1743void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1744} 1745 1746/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1747/// small case ranges). 1748bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1749 CaseRecVector& WorkList, 1750 const Value* SV, 1751 MachineBasicBlock *Default, 1752 MachineBasicBlock *SwitchBB) { 1753 Case& BackCase = *(CR.Range.second-1); 1754 1755 // Size is the number of Cases represented by this range. 1756 size_t Size = CR.Range.second - CR.Range.first; 1757 if (Size > 3) 1758 return false; 1759 1760 // Get the MachineFunction which holds the current MBB. This is used when 1761 // inserting any additional MBBs necessary to represent the switch. 1762 MachineFunction *CurMF = FuncInfo.MF; 1763 1764 // Figure out which block is immediately after the current one. 1765 MachineBasicBlock *NextBlock = 0; 1766 MachineFunction::iterator BBI = CR.CaseBB; 1767 1768 if (++BBI != FuncInfo.MF->end()) 1769 NextBlock = BBI; 1770 1771 // If any two of the cases has the same destination, and if one value 1772 // is the same as the other, but has one bit unset that the other has set, 1773 // use bit manipulation to do two compares at once. For example: 1774 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1775 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1776 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1777 if (Size == 2 && CR.CaseBB == SwitchBB) { 1778 Case &Small = *CR.Range.first; 1779 Case &Big = *(CR.Range.second-1); 1780 1781 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1782 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1783 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1784 1785 // Check that there is only one bit different. 1786 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1787 (SmallValue | BigValue) == BigValue) { 1788 // Isolate the common bit. 1789 APInt CommonBit = BigValue & ~SmallValue; 1790 assert((SmallValue | CommonBit) == BigValue && 1791 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1792 1793 SDValue CondLHS = getValue(SV); 1794 EVT VT = CondLHS.getValueType(); 1795 DebugLoc DL = getCurDebugLoc(); 1796 1797 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1798 DAG.getConstant(CommonBit, VT)); 1799 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1800 Or, DAG.getConstant(BigValue, VT), 1801 ISD::SETEQ); 1802 1803 // Update successor info. 1804 SwitchBB->addSuccessor(Small.BB); 1805 SwitchBB->addSuccessor(Default); 1806 1807 // Insert the true branch. 1808 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1809 getControlRoot(), Cond, 1810 DAG.getBasicBlock(Small.BB)); 1811 1812 // Insert the false branch. 1813 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1814 DAG.getBasicBlock(Default)); 1815 1816 DAG.setRoot(BrCond); 1817 return true; 1818 } 1819 } 1820 } 1821 1822 // Rearrange the case blocks so that the last one falls through if possible. 1823 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1824 // The last case block won't fall through into 'NextBlock' if we emit the 1825 // branches in this order. See if rearranging a case value would help. 1826 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1827 if (I->BB == NextBlock) { 1828 std::swap(*I, BackCase); 1829 break; 1830 } 1831 } 1832 } 1833 1834 // Create a CaseBlock record representing a conditional branch to 1835 // the Case's target mbb if the value being switched on SV is equal 1836 // to C. 1837 MachineBasicBlock *CurBlock = CR.CaseBB; 1838 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1839 MachineBasicBlock *FallThrough; 1840 if (I != E-1) { 1841 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1842 CurMF->insert(BBI, FallThrough); 1843 1844 // Put SV in a virtual register to make it available from the new blocks. 1845 ExportFromCurrentBlock(SV); 1846 } else { 1847 // If the last case doesn't match, go to the default block. 1848 FallThrough = Default; 1849 } 1850 1851 const Value *RHS, *LHS, *MHS; 1852 ISD::CondCode CC; 1853 if (I->High == I->Low) { 1854 // This is just small small case range :) containing exactly 1 case 1855 CC = ISD::SETEQ; 1856 LHS = SV; RHS = I->High; MHS = NULL; 1857 } else { 1858 CC = ISD::SETLE; 1859 LHS = I->Low; MHS = SV; RHS = I->High; 1860 } 1861 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1862 1863 // If emitting the first comparison, just call visitSwitchCase to emit the 1864 // code into the current block. Otherwise, push the CaseBlock onto the 1865 // vector to be later processed by SDISel, and insert the node's MBB 1866 // before the next MBB. 1867 if (CurBlock == SwitchBB) 1868 visitSwitchCase(CB, SwitchBB); 1869 else 1870 SwitchCases.push_back(CB); 1871 1872 CurBlock = FallThrough; 1873 } 1874 1875 return true; 1876} 1877 1878static inline bool areJTsAllowed(const TargetLowering &TLI) { 1879 return !DisableJumpTables && 1880 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1881 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1882} 1883 1884static APInt ComputeRange(const APInt &First, const APInt &Last) { 1885 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1886 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 1887 return (LastExt - FirstExt + 1ULL); 1888} 1889 1890/// handleJTSwitchCase - Emit jumptable for current switch case range 1891bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1892 CaseRecVector& WorkList, 1893 const Value* SV, 1894 MachineBasicBlock* Default, 1895 MachineBasicBlock *SwitchBB) { 1896 Case& FrontCase = *CR.Range.first; 1897 Case& BackCase = *(CR.Range.second-1); 1898 1899 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1900 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1901 1902 APInt TSize(First.getBitWidth(), 0); 1903 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1904 I!=E; ++I) 1905 TSize += I->size(); 1906 1907 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1908 return false; 1909 1910 APInt Range = ComputeRange(First, Last); 1911 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1912 if (Density < 0.4) 1913 return false; 1914 1915 DEBUG(dbgs() << "Lowering jump table\n" 1916 << "First entry: " << First << ". Last entry: " << Last << '\n' 1917 << "Range: " << Range 1918 << "Size: " << TSize << ". Density: " << Density << "\n\n"); 1919 1920 // Get the MachineFunction which holds the current MBB. This is used when 1921 // inserting any additional MBBs necessary to represent the switch. 1922 MachineFunction *CurMF = FuncInfo.MF; 1923 1924 // Figure out which block is immediately after the current one. 1925 MachineFunction::iterator BBI = CR.CaseBB; 1926 ++BBI; 1927 1928 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1929 1930 // Create a new basic block to hold the code for loading the address 1931 // of the jump table, and jumping to it. Update successor information; 1932 // we will either branch to the default case for the switch, or the jump 1933 // table. 1934 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1935 CurMF->insert(BBI, JumpTableBB); 1936 CR.CaseBB->addSuccessor(Default); 1937 CR.CaseBB->addSuccessor(JumpTableBB); 1938 1939 // Build a vector of destination BBs, corresponding to each target 1940 // of the jump table. If the value of the jump table slot corresponds to 1941 // a case statement, push the case's BB onto the vector, otherwise, push 1942 // the default BB. 1943 std::vector<MachineBasicBlock*> DestBBs; 1944 APInt TEI = First; 1945 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1946 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 1947 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 1948 1949 if (Low.sle(TEI) && TEI.sle(High)) { 1950 DestBBs.push_back(I->BB); 1951 if (TEI==High) 1952 ++I; 1953 } else { 1954 DestBBs.push_back(Default); 1955 } 1956 } 1957 1958 // Update successor info. Add one edge to each unique successor. 1959 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1960 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1961 E = DestBBs.end(); I != E; ++I) { 1962 if (!SuccsHandled[(*I)->getNumber()]) { 1963 SuccsHandled[(*I)->getNumber()] = true; 1964 JumpTableBB->addSuccessor(*I); 1965 } 1966 } 1967 1968 // Create a jump table index for this jump table. 1969 unsigned JTEncoding = TLI.getJumpTableEncoding(); 1970 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 1971 ->createJumpTableIndex(DestBBs); 1972 1973 // Set the jump table information so that we can codegen it as a second 1974 // MachineBasicBlock 1975 JumpTable JT(-1U, JTI, JumpTableBB, Default); 1976 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 1977 if (CR.CaseBB == SwitchBB) 1978 visitJumpTableHeader(JT, JTH, SwitchBB); 1979 1980 JTCases.push_back(JumpTableBlock(JTH, JT)); 1981 1982 return true; 1983} 1984 1985/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1986/// 2 subtrees. 1987bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 1988 CaseRecVector& WorkList, 1989 const Value* SV, 1990 MachineBasicBlock *Default, 1991 MachineBasicBlock *SwitchBB) { 1992 // Get the MachineFunction which holds the current MBB. This is used when 1993 // inserting any additional MBBs necessary to represent the switch. 1994 MachineFunction *CurMF = FuncInfo.MF; 1995 1996 // Figure out which block is immediately after the current one. 1997 MachineFunction::iterator BBI = CR.CaseBB; 1998 ++BBI; 1999 2000 Case& FrontCase = *CR.Range.first; 2001 Case& BackCase = *(CR.Range.second-1); 2002 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2003 2004 // Size is the number of Cases represented by this range. 2005 unsigned Size = CR.Range.second - CR.Range.first; 2006 2007 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2008 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2009 double FMetric = 0; 2010 CaseItr Pivot = CR.Range.first + Size/2; 2011 2012 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2013 // (heuristically) allow us to emit JumpTable's later. 2014 APInt TSize(First.getBitWidth(), 0); 2015 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2016 I!=E; ++I) 2017 TSize += I->size(); 2018 2019 APInt LSize = FrontCase.size(); 2020 APInt RSize = TSize-LSize; 2021 DEBUG(dbgs() << "Selecting best pivot: \n" 2022 << "First: " << First << ", Last: " << Last <<'\n' 2023 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2024 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2025 J!=E; ++I, ++J) { 2026 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2027 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2028 APInt Range = ComputeRange(LEnd, RBegin); 2029 assert((Range - 2ULL).isNonNegative() && 2030 "Invalid case distance"); 2031 double LDensity = (double)LSize.roundToDouble() / 2032 (LEnd - First + 1ULL).roundToDouble(); 2033 double RDensity = (double)RSize.roundToDouble() / 2034 (Last - RBegin + 1ULL).roundToDouble(); 2035 double Metric = Range.logBase2()*(LDensity+RDensity); 2036 // Should always split in some non-trivial place 2037 DEBUG(dbgs() <<"=>Step\n" 2038 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2039 << "LDensity: " << LDensity 2040 << ", RDensity: " << RDensity << '\n' 2041 << "Metric: " << Metric << '\n'); 2042 if (FMetric < Metric) { 2043 Pivot = J; 2044 FMetric = Metric; 2045 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2046 } 2047 2048 LSize += J->size(); 2049 RSize -= J->size(); 2050 } 2051 if (areJTsAllowed(TLI)) { 2052 // If our case is dense we *really* should handle it earlier! 2053 assert((FMetric > 0) && "Should handle dense range earlier!"); 2054 } else { 2055 Pivot = CR.Range.first + Size/2; 2056 } 2057 2058 CaseRange LHSR(CR.Range.first, Pivot); 2059 CaseRange RHSR(Pivot, CR.Range.second); 2060 Constant *C = Pivot->Low; 2061 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2062 2063 // We know that we branch to the LHS if the Value being switched on is 2064 // less than the Pivot value, C. We use this to optimize our binary 2065 // tree a bit, by recognizing that if SV is greater than or equal to the 2066 // LHS's Case Value, and that Case Value is exactly one less than the 2067 // Pivot's Value, then we can branch directly to the LHS's Target, 2068 // rather than creating a leaf node for it. 2069 if ((LHSR.second - LHSR.first) == 1 && 2070 LHSR.first->High == CR.GE && 2071 cast<ConstantInt>(C)->getValue() == 2072 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2073 TrueBB = LHSR.first->BB; 2074 } else { 2075 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2076 CurMF->insert(BBI, TrueBB); 2077 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2078 2079 // Put SV in a virtual register to make it available from the new blocks. 2080 ExportFromCurrentBlock(SV); 2081 } 2082 2083 // Similar to the optimization above, if the Value being switched on is 2084 // known to be less than the Constant CR.LT, and the current Case Value 2085 // is CR.LT - 1, then we can branch directly to the target block for 2086 // the current Case Value, rather than emitting a RHS leaf node for it. 2087 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2088 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2089 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2090 FalseBB = RHSR.first->BB; 2091 } else { 2092 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2093 CurMF->insert(BBI, FalseBB); 2094 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2095 2096 // Put SV in a virtual register to make it available from the new blocks. 2097 ExportFromCurrentBlock(SV); 2098 } 2099 2100 // Create a CaseBlock record representing a conditional branch to 2101 // the LHS node if the value being switched on SV is less than C. 2102 // Otherwise, branch to LHS. 2103 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2104 2105 if (CR.CaseBB == SwitchBB) 2106 visitSwitchCase(CB, SwitchBB); 2107 else 2108 SwitchCases.push_back(CB); 2109 2110 return true; 2111} 2112 2113/// handleBitTestsSwitchCase - if current case range has few destination and 2114/// range span less, than machine word bitwidth, encode case range into series 2115/// of masks and emit bit tests with these masks. 2116bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2117 CaseRecVector& WorkList, 2118 const Value* SV, 2119 MachineBasicBlock* Default, 2120 MachineBasicBlock *SwitchBB){ 2121 EVT PTy = TLI.getPointerTy(); 2122 unsigned IntPtrBits = PTy.getSizeInBits(); 2123 2124 Case& FrontCase = *CR.Range.first; 2125 Case& BackCase = *(CR.Range.second-1); 2126 2127 // Get the MachineFunction which holds the current MBB. This is used when 2128 // inserting any additional MBBs necessary to represent the switch. 2129 MachineFunction *CurMF = FuncInfo.MF; 2130 2131 // If target does not have legal shift left, do not emit bit tests at all. 2132 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2133 return false; 2134 2135 size_t numCmps = 0; 2136 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2137 I!=E; ++I) { 2138 // Single case counts one, case range - two. 2139 numCmps += (I->Low == I->High ? 1 : 2); 2140 } 2141 2142 // Count unique destinations 2143 SmallSet<MachineBasicBlock*, 4> Dests; 2144 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2145 Dests.insert(I->BB); 2146 if (Dests.size() > 3) 2147 // Don't bother the code below, if there are too much unique destinations 2148 return false; 2149 } 2150 DEBUG(dbgs() << "Total number of unique destinations: " 2151 << Dests.size() << '\n' 2152 << "Total number of comparisons: " << numCmps << '\n'); 2153 2154 // Compute span of values. 2155 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2156 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2157 APInt cmpRange = maxValue - minValue; 2158 2159 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2160 << "Low bound: " << minValue << '\n' 2161 << "High bound: " << maxValue << '\n'); 2162 2163 if (cmpRange.uge(IntPtrBits) || 2164 (!(Dests.size() == 1 && numCmps >= 3) && 2165 !(Dests.size() == 2 && numCmps >= 5) && 2166 !(Dests.size() >= 3 && numCmps >= 6))) 2167 return false; 2168 2169 DEBUG(dbgs() << "Emitting bit tests\n"); 2170 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2171 2172 // Optimize the case where all the case values fit in a 2173 // word without having to subtract minValue. In this case, 2174 // we can optimize away the subtraction. 2175 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2176 cmpRange = maxValue; 2177 } else { 2178 lowBound = minValue; 2179 } 2180 2181 CaseBitsVector CasesBits; 2182 unsigned i, count = 0; 2183 2184 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2185 MachineBasicBlock* Dest = I->BB; 2186 for (i = 0; i < count; ++i) 2187 if (Dest == CasesBits[i].BB) 2188 break; 2189 2190 if (i == count) { 2191 assert((count < 3) && "Too much destinations to test!"); 2192 CasesBits.push_back(CaseBits(0, Dest, 0)); 2193 count++; 2194 } 2195 2196 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2197 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2198 2199 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2200 uint64_t hi = (highValue - lowBound).getZExtValue(); 2201 2202 for (uint64_t j = lo; j <= hi; j++) { 2203 CasesBits[i].Mask |= 1ULL << j; 2204 CasesBits[i].Bits++; 2205 } 2206 2207 } 2208 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2209 2210 BitTestInfo BTC; 2211 2212 // Figure out which block is immediately after the current one. 2213 MachineFunction::iterator BBI = CR.CaseBB; 2214 ++BBI; 2215 2216 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2217 2218 DEBUG(dbgs() << "Cases:\n"); 2219 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2220 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2221 << ", Bits: " << CasesBits[i].Bits 2222 << ", BB: " << CasesBits[i].BB << '\n'); 2223 2224 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2225 CurMF->insert(BBI, CaseBB); 2226 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2227 CaseBB, 2228 CasesBits[i].BB)); 2229 2230 // Put SV in a virtual register to make it available from the new blocks. 2231 ExportFromCurrentBlock(SV); 2232 } 2233 2234 BitTestBlock BTB(lowBound, cmpRange, SV, 2235 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2236 CR.CaseBB, Default, BTC); 2237 2238 if (CR.CaseBB == SwitchBB) 2239 visitBitTestHeader(BTB, SwitchBB); 2240 2241 BitTestCases.push_back(BTB); 2242 2243 return true; 2244} 2245 2246/// Clusterify - Transform simple list of Cases into list of CaseRange's 2247size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2248 const SwitchInst& SI) { 2249 size_t numCmps = 0; 2250 2251 // Start with "simple" cases 2252 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2253 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2254 Cases.push_back(Case(SI.getSuccessorValue(i), 2255 SI.getSuccessorValue(i), 2256 SMBB)); 2257 } 2258 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2259 2260 // Merge case into clusters 2261 if (Cases.size() >= 2) 2262 // Must recompute end() each iteration because it may be 2263 // invalidated by erase if we hold on to it 2264 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2265 J != Cases.end(); ) { 2266 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2267 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2268 MachineBasicBlock* nextBB = J->BB; 2269 MachineBasicBlock* currentBB = I->BB; 2270 2271 // If the two neighboring cases go to the same destination, merge them 2272 // into a single case. 2273 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2274 I->High = J->High; 2275 J = Cases.erase(J); 2276 } else { 2277 I = J++; 2278 } 2279 } 2280 2281 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2282 if (I->Low != I->High) 2283 // A range counts double, since it requires two compares. 2284 ++numCmps; 2285 } 2286 2287 return numCmps; 2288} 2289 2290void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2291 MachineBasicBlock *Last) { 2292 // Update JTCases. 2293 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2294 if (JTCases[i].first.HeaderBB == First) 2295 JTCases[i].first.HeaderBB = Last; 2296 2297 // Update BitTestCases. 2298 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2299 if (BitTestCases[i].Parent == First) 2300 BitTestCases[i].Parent = Last; 2301} 2302 2303void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2304 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2305 2306 // Figure out which block is immediately after the current one. 2307 MachineBasicBlock *NextBlock = 0; 2308 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2309 2310 // If there is only the default destination, branch to it if it is not the 2311 // next basic block. Otherwise, just fall through. 2312 if (SI.getNumOperands() == 2) { 2313 // Update machine-CFG edges. 2314 2315 // If this is not a fall-through branch, emit the branch. 2316 SwitchMBB->addSuccessor(Default); 2317 if (Default != NextBlock) 2318 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2319 MVT::Other, getControlRoot(), 2320 DAG.getBasicBlock(Default))); 2321 2322 return; 2323 } 2324 2325 // If there are any non-default case statements, create a vector of Cases 2326 // representing each one, and sort the vector so that we can efficiently 2327 // create a binary search tree from them. 2328 CaseVector Cases; 2329 size_t numCmps = Clusterify(Cases, SI); 2330 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2331 << ". Total compares: " << numCmps << '\n'); 2332 numCmps = 0; 2333 2334 // Get the Value to be switched on and default basic blocks, which will be 2335 // inserted into CaseBlock records, representing basic blocks in the binary 2336 // search tree. 2337 const Value *SV = SI.getOperand(0); 2338 2339 // Push the initial CaseRec onto the worklist 2340 CaseRecVector WorkList; 2341 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2342 CaseRange(Cases.begin(),Cases.end()))); 2343 2344 while (!WorkList.empty()) { 2345 // Grab a record representing a case range to process off the worklist 2346 CaseRec CR = WorkList.back(); 2347 WorkList.pop_back(); 2348 2349 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2350 continue; 2351 2352 // If the range has few cases (two or less) emit a series of specific 2353 // tests. 2354 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2355 continue; 2356 2357 // If the switch has more than 5 blocks, and at least 40% dense, and the 2358 // target supports indirect branches, then emit a jump table rather than 2359 // lowering the switch to a binary tree of conditional branches. 2360 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2361 continue; 2362 2363 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2364 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2365 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2366 } 2367} 2368 2369void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2370 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2371 2372 // Update machine-CFG edges with unique successors. 2373 SmallVector<BasicBlock*, 32> succs; 2374 succs.reserve(I.getNumSuccessors()); 2375 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2376 succs.push_back(I.getSuccessor(i)); 2377 array_pod_sort(succs.begin(), succs.end()); 2378 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2379 for (unsigned i = 0, e = succs.size(); i != e; ++i) 2380 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]); 2381 2382 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2383 MVT::Other, getControlRoot(), 2384 getValue(I.getAddress()))); 2385} 2386 2387void SelectionDAGBuilder::visitFSub(const User &I) { 2388 // -0.0 - X --> fneg 2389 const Type *Ty = I.getType(); 2390 if (Ty->isVectorTy()) { 2391 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2392 const VectorType *DestTy = cast<VectorType>(I.getType()); 2393 const Type *ElTy = DestTy->getElementType(); 2394 unsigned VL = DestTy->getNumElements(); 2395 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2396 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2397 if (CV == CNZ) { 2398 SDValue Op2 = getValue(I.getOperand(1)); 2399 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2400 Op2.getValueType(), Op2)); 2401 return; 2402 } 2403 } 2404 } 2405 2406 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2407 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2408 SDValue Op2 = getValue(I.getOperand(1)); 2409 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2410 Op2.getValueType(), Op2)); 2411 return; 2412 } 2413 2414 visitBinary(I, ISD::FSUB); 2415} 2416 2417void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2418 SDValue Op1 = getValue(I.getOperand(0)); 2419 SDValue Op2 = getValue(I.getOperand(1)); 2420 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2421 Op1.getValueType(), Op1, Op2)); 2422} 2423 2424void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2425 SDValue Op1 = getValue(I.getOperand(0)); 2426 SDValue Op2 = getValue(I.getOperand(1)); 2427 if (!I.getType()->isVectorTy() && 2428 Op2.getValueType() != TLI.getShiftAmountTy()) { 2429 // If the operand is smaller than the shift count type, promote it. 2430 EVT PTy = TLI.getPointerTy(); 2431 EVT STy = TLI.getShiftAmountTy(); 2432 if (STy.bitsGT(Op2.getValueType())) 2433 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2434 TLI.getShiftAmountTy(), Op2); 2435 // If the operand is larger than the shift count type but the shift 2436 // count type has enough bits to represent any shift value, truncate 2437 // it now. This is a common case and it exposes the truncate to 2438 // optimization early. 2439 else if (STy.getSizeInBits() >= 2440 Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2441 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2442 TLI.getShiftAmountTy(), Op2); 2443 // Otherwise we'll need to temporarily settle for some other 2444 // convenient type; type legalization will make adjustments as 2445 // needed. 2446 else if (PTy.bitsLT(Op2.getValueType())) 2447 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2448 TLI.getPointerTy(), Op2); 2449 else if (PTy.bitsGT(Op2.getValueType())) 2450 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2451 TLI.getPointerTy(), Op2); 2452 } 2453 2454 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2455 Op1.getValueType(), Op1, Op2)); 2456} 2457 2458void SelectionDAGBuilder::visitICmp(const User &I) { 2459 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2460 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2461 predicate = IC->getPredicate(); 2462 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2463 predicate = ICmpInst::Predicate(IC->getPredicate()); 2464 SDValue Op1 = getValue(I.getOperand(0)); 2465 SDValue Op2 = getValue(I.getOperand(1)); 2466 ISD::CondCode Opcode = getICmpCondCode(predicate); 2467 2468 EVT DestVT = TLI.getValueType(I.getType()); 2469 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2470} 2471 2472void SelectionDAGBuilder::visitFCmp(const User &I) { 2473 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2474 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2475 predicate = FC->getPredicate(); 2476 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2477 predicate = FCmpInst::Predicate(FC->getPredicate()); 2478 SDValue Op1 = getValue(I.getOperand(0)); 2479 SDValue Op2 = getValue(I.getOperand(1)); 2480 ISD::CondCode Condition = getFCmpCondCode(predicate); 2481 EVT DestVT = TLI.getValueType(I.getType()); 2482 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2483} 2484 2485void SelectionDAGBuilder::visitSelect(const User &I) { 2486 SmallVector<EVT, 4> ValueVTs; 2487 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2488 unsigned NumValues = ValueVTs.size(); 2489 if (NumValues == 0) return; 2490 2491 SmallVector<SDValue, 4> Values(NumValues); 2492 SDValue Cond = getValue(I.getOperand(0)); 2493 SDValue TrueVal = getValue(I.getOperand(1)); 2494 SDValue FalseVal = getValue(I.getOperand(2)); 2495 2496 for (unsigned i = 0; i != NumValues; ++i) 2497 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2498 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2499 Cond, 2500 SDValue(TrueVal.getNode(), 2501 TrueVal.getResNo() + i), 2502 SDValue(FalseVal.getNode(), 2503 FalseVal.getResNo() + i)); 2504 2505 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2506 DAG.getVTList(&ValueVTs[0], NumValues), 2507 &Values[0], NumValues)); 2508} 2509 2510void SelectionDAGBuilder::visitTrunc(const User &I) { 2511 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2512 SDValue N = getValue(I.getOperand(0)); 2513 EVT DestVT = TLI.getValueType(I.getType()); 2514 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2515} 2516 2517void SelectionDAGBuilder::visitZExt(const User &I) { 2518 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2519 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2520 SDValue N = getValue(I.getOperand(0)); 2521 EVT DestVT = TLI.getValueType(I.getType()); 2522 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2523} 2524 2525void SelectionDAGBuilder::visitSExt(const User &I) { 2526 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2527 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2528 SDValue N = getValue(I.getOperand(0)); 2529 EVT DestVT = TLI.getValueType(I.getType()); 2530 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2531} 2532 2533void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2534 // FPTrunc is never a no-op cast, no need to check 2535 SDValue N = getValue(I.getOperand(0)); 2536 EVT DestVT = TLI.getValueType(I.getType()); 2537 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2538 DestVT, N, DAG.getIntPtrConstant(0))); 2539} 2540 2541void SelectionDAGBuilder::visitFPExt(const User &I){ 2542 // FPTrunc is never a no-op cast, no need to check 2543 SDValue N = getValue(I.getOperand(0)); 2544 EVT DestVT = TLI.getValueType(I.getType()); 2545 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2546} 2547 2548void SelectionDAGBuilder::visitFPToUI(const User &I) { 2549 // FPToUI is never a no-op cast, no need to check 2550 SDValue N = getValue(I.getOperand(0)); 2551 EVT DestVT = TLI.getValueType(I.getType()); 2552 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2553} 2554 2555void SelectionDAGBuilder::visitFPToSI(const User &I) { 2556 // FPToSI is never a no-op cast, no need to check 2557 SDValue N = getValue(I.getOperand(0)); 2558 EVT DestVT = TLI.getValueType(I.getType()); 2559 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2560} 2561 2562void SelectionDAGBuilder::visitUIToFP(const User &I) { 2563 // UIToFP is never a no-op cast, no need to check 2564 SDValue N = getValue(I.getOperand(0)); 2565 EVT DestVT = TLI.getValueType(I.getType()); 2566 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2567} 2568 2569void SelectionDAGBuilder::visitSIToFP(const User &I){ 2570 // SIToFP is never a no-op cast, no need to check 2571 SDValue N = getValue(I.getOperand(0)); 2572 EVT DestVT = TLI.getValueType(I.getType()); 2573 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2574} 2575 2576void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2577 // What to do depends on the size of the integer and the size of the pointer. 2578 // We can either truncate, zero extend, or no-op, accordingly. 2579 SDValue N = getValue(I.getOperand(0)); 2580 EVT DestVT = TLI.getValueType(I.getType()); 2581 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2582} 2583 2584void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2585 // What to do depends on the size of the integer and the size of the pointer. 2586 // We can either truncate, zero extend, or no-op, accordingly. 2587 SDValue N = getValue(I.getOperand(0)); 2588 EVT DestVT = TLI.getValueType(I.getType()); 2589 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2590} 2591 2592void SelectionDAGBuilder::visitBitCast(const User &I) { 2593 SDValue N = getValue(I.getOperand(0)); 2594 EVT DestVT = TLI.getValueType(I.getType()); 2595 2596 // BitCast assures us that source and destination are the same size so this is 2597 // either a BITCAST or a no-op. 2598 if (DestVT != N.getValueType()) 2599 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2600 DestVT, N)); // convert types. 2601 else 2602 setValue(&I, N); // noop cast. 2603} 2604 2605void SelectionDAGBuilder::visitInsertElement(const User &I) { 2606 SDValue InVec = getValue(I.getOperand(0)); 2607 SDValue InVal = getValue(I.getOperand(1)); 2608 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2609 TLI.getPointerTy(), 2610 getValue(I.getOperand(2))); 2611 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2612 TLI.getValueType(I.getType()), 2613 InVec, InVal, InIdx)); 2614} 2615 2616void SelectionDAGBuilder::visitExtractElement(const User &I) { 2617 SDValue InVec = getValue(I.getOperand(0)); 2618 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2619 TLI.getPointerTy(), 2620 getValue(I.getOperand(1))); 2621 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2622 TLI.getValueType(I.getType()), InVec, InIdx)); 2623} 2624 2625// Utility for visitShuffleVector - Returns true if the mask is mask starting 2626// from SIndx and increasing to the element length (undefs are allowed). 2627static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2628 unsigned MaskNumElts = Mask.size(); 2629 for (unsigned i = 0; i != MaskNumElts; ++i) 2630 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2631 return false; 2632 return true; 2633} 2634 2635void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2636 SmallVector<int, 8> Mask; 2637 SDValue Src1 = getValue(I.getOperand(0)); 2638 SDValue Src2 = getValue(I.getOperand(1)); 2639 2640 // Convert the ConstantVector mask operand into an array of ints, with -1 2641 // representing undef values. 2642 SmallVector<Constant*, 8> MaskElts; 2643 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2644 unsigned MaskNumElts = MaskElts.size(); 2645 for (unsigned i = 0; i != MaskNumElts; ++i) { 2646 if (isa<UndefValue>(MaskElts[i])) 2647 Mask.push_back(-1); 2648 else 2649 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2650 } 2651 2652 EVT VT = TLI.getValueType(I.getType()); 2653 EVT SrcVT = Src1.getValueType(); 2654 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2655 2656 if (SrcNumElts == MaskNumElts) { 2657 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2658 &Mask[0])); 2659 return; 2660 } 2661 2662 // Normalize the shuffle vector since mask and vector length don't match. 2663 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2664 // Mask is longer than the source vectors and is a multiple of the source 2665 // vectors. We can use concatenate vector to make the mask and vectors 2666 // lengths match. 2667 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2668 // The shuffle is concatenating two vectors together. 2669 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2670 VT, Src1, Src2)); 2671 return; 2672 } 2673 2674 // Pad both vectors with undefs to make them the same length as the mask. 2675 unsigned NumConcat = MaskNumElts / SrcNumElts; 2676 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2677 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2678 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2679 2680 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2681 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2682 MOps1[0] = Src1; 2683 MOps2[0] = Src2; 2684 2685 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2686 getCurDebugLoc(), VT, 2687 &MOps1[0], NumConcat); 2688 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2689 getCurDebugLoc(), VT, 2690 &MOps2[0], NumConcat); 2691 2692 // Readjust mask for new input vector length. 2693 SmallVector<int, 8> MappedOps; 2694 for (unsigned i = 0; i != MaskNumElts; ++i) { 2695 int Idx = Mask[i]; 2696 if (Idx < (int)SrcNumElts) 2697 MappedOps.push_back(Idx); 2698 else 2699 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2700 } 2701 2702 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2703 &MappedOps[0])); 2704 return; 2705 } 2706 2707 if (SrcNumElts > MaskNumElts) { 2708 // Analyze the access pattern of the vector to see if we can extract 2709 // two subvectors and do the shuffle. The analysis is done by calculating 2710 // the range of elements the mask access on both vectors. 2711 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2712 int MaxRange[2] = {-1, -1}; 2713 2714 for (unsigned i = 0; i != MaskNumElts; ++i) { 2715 int Idx = Mask[i]; 2716 int Input = 0; 2717 if (Idx < 0) 2718 continue; 2719 2720 if (Idx >= (int)SrcNumElts) { 2721 Input = 1; 2722 Idx -= SrcNumElts; 2723 } 2724 if (Idx > MaxRange[Input]) 2725 MaxRange[Input] = Idx; 2726 if (Idx < MinRange[Input]) 2727 MinRange[Input] = Idx; 2728 } 2729 2730 // Check if the access is smaller than the vector size and can we find 2731 // a reasonable extract index. 2732 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2733 // Extract. 2734 int StartIdx[2]; // StartIdx to extract from 2735 for (int Input=0; Input < 2; ++Input) { 2736 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2737 RangeUse[Input] = 0; // Unused 2738 StartIdx[Input] = 0; 2739 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2740 // Fits within range but we should see if we can find a good 2741 // start index that is a multiple of the mask length. 2742 if (MaxRange[Input] < (int)MaskNumElts) { 2743 RangeUse[Input] = 1; // Extract from beginning of the vector 2744 StartIdx[Input] = 0; 2745 } else { 2746 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2747 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2748 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2749 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2750 } 2751 } 2752 } 2753 2754 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2755 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2756 return; 2757 } 2758 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2759 // Extract appropriate subvector and generate a vector shuffle 2760 for (int Input=0; Input < 2; ++Input) { 2761 SDValue &Src = Input == 0 ? Src1 : Src2; 2762 if (RangeUse[Input] == 0) 2763 Src = DAG.getUNDEF(VT); 2764 else 2765 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2766 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2767 } 2768 2769 // Calculate new mask. 2770 SmallVector<int, 8> MappedOps; 2771 for (unsigned i = 0; i != MaskNumElts; ++i) { 2772 int Idx = Mask[i]; 2773 if (Idx < 0) 2774 MappedOps.push_back(Idx); 2775 else if (Idx < (int)SrcNumElts) 2776 MappedOps.push_back(Idx - StartIdx[0]); 2777 else 2778 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2779 } 2780 2781 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2782 &MappedOps[0])); 2783 return; 2784 } 2785 } 2786 2787 // We can't use either concat vectors or extract subvectors so fall back to 2788 // replacing the shuffle with extract and build vector. 2789 // to insert and build vector. 2790 EVT EltVT = VT.getVectorElementType(); 2791 EVT PtrVT = TLI.getPointerTy(); 2792 SmallVector<SDValue,8> Ops; 2793 for (unsigned i = 0; i != MaskNumElts; ++i) { 2794 if (Mask[i] < 0) { 2795 Ops.push_back(DAG.getUNDEF(EltVT)); 2796 } else { 2797 int Idx = Mask[i]; 2798 SDValue Res; 2799 2800 if (Idx < (int)SrcNumElts) 2801 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2802 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2803 else 2804 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2805 EltVT, Src2, 2806 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2807 2808 Ops.push_back(Res); 2809 } 2810 } 2811 2812 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2813 VT, &Ops[0], Ops.size())); 2814} 2815 2816void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2817 const Value *Op0 = I.getOperand(0); 2818 const Value *Op1 = I.getOperand(1); 2819 const Type *AggTy = I.getType(); 2820 const Type *ValTy = Op1->getType(); 2821 bool IntoUndef = isa<UndefValue>(Op0); 2822 bool FromUndef = isa<UndefValue>(Op1); 2823 2824 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2825 2826 SmallVector<EVT, 4> AggValueVTs; 2827 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2828 SmallVector<EVT, 4> ValValueVTs; 2829 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2830 2831 unsigned NumAggValues = AggValueVTs.size(); 2832 unsigned NumValValues = ValValueVTs.size(); 2833 SmallVector<SDValue, 4> Values(NumAggValues); 2834 2835 SDValue Agg = getValue(Op0); 2836 SDValue Val = getValue(Op1); 2837 unsigned i = 0; 2838 // Copy the beginning value(s) from the original aggregate. 2839 for (; i != LinearIndex; ++i) 2840 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2841 SDValue(Agg.getNode(), Agg.getResNo() + i); 2842 // Copy values from the inserted value(s). 2843 for (; i != LinearIndex + NumValValues; ++i) 2844 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2845 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2846 // Copy remaining value(s) from the original aggregate. 2847 for (; i != NumAggValues; ++i) 2848 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2849 SDValue(Agg.getNode(), Agg.getResNo() + i); 2850 2851 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2852 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2853 &Values[0], NumAggValues)); 2854} 2855 2856void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2857 const Value *Op0 = I.getOperand(0); 2858 const Type *AggTy = Op0->getType(); 2859 const Type *ValTy = I.getType(); 2860 bool OutOfUndef = isa<UndefValue>(Op0); 2861 2862 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2863 2864 SmallVector<EVT, 4> ValValueVTs; 2865 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2866 2867 unsigned NumValValues = ValValueVTs.size(); 2868 SmallVector<SDValue, 4> Values(NumValValues); 2869 2870 SDValue Agg = getValue(Op0); 2871 // Copy out the selected value(s). 2872 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2873 Values[i - LinearIndex] = 2874 OutOfUndef ? 2875 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2876 SDValue(Agg.getNode(), Agg.getResNo() + i); 2877 2878 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2879 DAG.getVTList(&ValValueVTs[0], NumValValues), 2880 &Values[0], NumValValues)); 2881} 2882 2883void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2884 SDValue N = getValue(I.getOperand(0)); 2885 const Type *Ty = I.getOperand(0)->getType(); 2886 2887 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2888 OI != E; ++OI) { 2889 const Value *Idx = *OI; 2890 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2891 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2892 if (Field) { 2893 // N = N + Offset 2894 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2895 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2896 DAG.getIntPtrConstant(Offset)); 2897 } 2898 2899 Ty = StTy->getElementType(Field); 2900 } else { 2901 Ty = cast<SequentialType>(Ty)->getElementType(); 2902 2903 // If this is a constant subscript, handle it quickly. 2904 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2905 if (CI->isZero()) continue; 2906 uint64_t Offs = 2907 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2908 SDValue OffsVal; 2909 EVT PTy = TLI.getPointerTy(); 2910 unsigned PtrBits = PTy.getSizeInBits(); 2911 if (PtrBits < 64) 2912 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2913 TLI.getPointerTy(), 2914 DAG.getConstant(Offs, MVT::i64)); 2915 else 2916 OffsVal = DAG.getIntPtrConstant(Offs); 2917 2918 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2919 OffsVal); 2920 continue; 2921 } 2922 2923 // N = N + Idx * ElementSize; 2924 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2925 TD->getTypeAllocSize(Ty)); 2926 SDValue IdxN = getValue(Idx); 2927 2928 // If the index is smaller or larger than intptr_t, truncate or extend 2929 // it. 2930 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2931 2932 // If this is a multiply by a power of two, turn it into a shl 2933 // immediately. This is a very common case. 2934 if (ElementSize != 1) { 2935 if (ElementSize.isPowerOf2()) { 2936 unsigned Amt = ElementSize.logBase2(); 2937 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2938 N.getValueType(), IdxN, 2939 DAG.getConstant(Amt, TLI.getPointerTy())); 2940 } else { 2941 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2942 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2943 N.getValueType(), IdxN, Scale); 2944 } 2945 } 2946 2947 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2948 N.getValueType(), N, IdxN); 2949 } 2950 } 2951 2952 setValue(&I, N); 2953} 2954 2955void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 2956 // If this is a fixed sized alloca in the entry block of the function, 2957 // allocate it statically on the stack. 2958 if (FuncInfo.StaticAllocaMap.count(&I)) 2959 return; // getValue will auto-populate this. 2960 2961 const Type *Ty = I.getAllocatedType(); 2962 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 2963 unsigned Align = 2964 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2965 I.getAlignment()); 2966 2967 SDValue AllocSize = getValue(I.getArraySize()); 2968 2969 EVT IntPtr = TLI.getPointerTy(); 2970 if (AllocSize.getValueType() != IntPtr) 2971 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 2972 2973 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 2974 AllocSize, 2975 DAG.getConstant(TySize, IntPtr)); 2976 2977 // Handle alignment. If the requested alignment is less than or equal to 2978 // the stack alignment, ignore it. If the size is greater than or equal to 2979 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2980 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 2981 if (Align <= StackAlign) 2982 Align = 0; 2983 2984 // Round the size of the allocation up to the stack alignment size 2985 // by add SA-1 to the size. 2986 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2987 AllocSize.getValueType(), AllocSize, 2988 DAG.getIntPtrConstant(StackAlign-1)); 2989 2990 // Mask out the low bits for alignment purposes. 2991 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 2992 AllocSize.getValueType(), AllocSize, 2993 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2994 2995 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2996 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 2997 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 2998 VTs, Ops, 3); 2999 setValue(&I, DSA); 3000 DAG.setRoot(DSA.getValue(1)); 3001 3002 // Inform the Frame Information that we have just allocated a variable-sized 3003 // object. 3004 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3005} 3006 3007void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3008 const Value *SV = I.getOperand(0); 3009 SDValue Ptr = getValue(SV); 3010 3011 const Type *Ty = I.getType(); 3012 3013 bool isVolatile = I.isVolatile(); 3014 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3015 unsigned Alignment = I.getAlignment(); 3016 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3017 3018 SmallVector<EVT, 4> ValueVTs; 3019 SmallVector<uint64_t, 4> Offsets; 3020 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3021 unsigned NumValues = ValueVTs.size(); 3022 if (NumValues == 0) 3023 return; 3024 3025 SDValue Root; 3026 bool ConstantMemory = false; 3027 if (I.isVolatile() || NumValues > MaxParallelChains) 3028 // Serialize volatile loads with other side effects. 3029 Root = getRoot(); 3030 else if (AA->pointsToConstantMemory( 3031 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3032 // Do not serialize (non-volatile) loads of constant memory with anything. 3033 Root = DAG.getEntryNode(); 3034 ConstantMemory = true; 3035 } else { 3036 // Do not serialize non-volatile loads against each other. 3037 Root = DAG.getRoot(); 3038 } 3039 3040 SmallVector<SDValue, 4> Values(NumValues); 3041 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3042 NumValues)); 3043 EVT PtrVT = Ptr.getValueType(); 3044 unsigned ChainI = 0; 3045 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3046 // Serializing loads here may result in excessive register pressure, and 3047 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3048 // could recover a bit by hoisting nodes upward in the chain by recognizing 3049 // they are side-effect free or do not alias. The optimizer should really 3050 // avoid this case by converting large object/array copies to llvm.memcpy 3051 // (MaxParallelChains should always remain as failsafe). 3052 if (ChainI == MaxParallelChains) { 3053 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3054 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3055 MVT::Other, &Chains[0], ChainI); 3056 Root = Chain; 3057 ChainI = 0; 3058 } 3059 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3060 PtrVT, Ptr, 3061 DAG.getConstant(Offsets[i], PtrVT)); 3062 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3063 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3064 isNonTemporal, Alignment, TBAAInfo); 3065 3066 Values[i] = L; 3067 Chains[ChainI] = L.getValue(1); 3068 } 3069 3070 if (!ConstantMemory) { 3071 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3072 MVT::Other, &Chains[0], ChainI); 3073 if (isVolatile) 3074 DAG.setRoot(Chain); 3075 else 3076 PendingLoads.push_back(Chain); 3077 } 3078 3079 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3080 DAG.getVTList(&ValueVTs[0], NumValues), 3081 &Values[0], NumValues)); 3082} 3083 3084void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3085 const Value *SrcV = I.getOperand(0); 3086 const Value *PtrV = I.getOperand(1); 3087 3088 SmallVector<EVT, 4> ValueVTs; 3089 SmallVector<uint64_t, 4> Offsets; 3090 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3091 unsigned NumValues = ValueVTs.size(); 3092 if (NumValues == 0) 3093 return; 3094 3095 // Get the lowered operands. Note that we do this after 3096 // checking if NumResults is zero, because with zero results 3097 // the operands won't have values in the map. 3098 SDValue Src = getValue(SrcV); 3099 SDValue Ptr = getValue(PtrV); 3100 3101 SDValue Root = getRoot(); 3102 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3103 NumValues)); 3104 EVT PtrVT = Ptr.getValueType(); 3105 bool isVolatile = I.isVolatile(); 3106 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3107 unsigned Alignment = I.getAlignment(); 3108 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3109 3110 unsigned ChainI = 0; 3111 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3112 // See visitLoad comments. 3113 if (ChainI == MaxParallelChains) { 3114 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3115 MVT::Other, &Chains[0], ChainI); 3116 Root = Chain; 3117 ChainI = 0; 3118 } 3119 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3120 DAG.getConstant(Offsets[i], PtrVT)); 3121 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3122 SDValue(Src.getNode(), Src.getResNo() + i), 3123 Add, MachinePointerInfo(PtrV, Offsets[i]), 3124 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3125 Chains[ChainI] = St; 3126 } 3127 3128 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3129 MVT::Other, &Chains[0], ChainI); 3130 ++SDNodeOrder; 3131 AssignOrderingToNode(StoreNode.getNode()); 3132 DAG.setRoot(StoreNode); 3133} 3134 3135/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3136/// node. 3137void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3138 unsigned Intrinsic) { 3139 bool HasChain = !I.doesNotAccessMemory(); 3140 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3141 3142 // Build the operand list. 3143 SmallVector<SDValue, 8> Ops; 3144 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3145 if (OnlyLoad) { 3146 // We don't need to serialize loads against other loads. 3147 Ops.push_back(DAG.getRoot()); 3148 } else { 3149 Ops.push_back(getRoot()); 3150 } 3151 } 3152 3153 // Info is set by getTgtMemInstrinsic 3154 TargetLowering::IntrinsicInfo Info; 3155 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3156 3157 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3158 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3159 Info.opc == ISD::INTRINSIC_W_CHAIN) 3160 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3161 3162 // Add all operands of the call to the operand list. 3163 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3164 SDValue Op = getValue(I.getArgOperand(i)); 3165 assert(TLI.isTypeLegal(Op.getValueType()) && 3166 "Intrinsic uses a non-legal type?"); 3167 Ops.push_back(Op); 3168 } 3169 3170 SmallVector<EVT, 4> ValueVTs; 3171 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3172#ifndef NDEBUG 3173 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3174 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3175 "Intrinsic uses a non-legal type?"); 3176 } 3177#endif // NDEBUG 3178 3179 if (HasChain) 3180 ValueVTs.push_back(MVT::Other); 3181 3182 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3183 3184 // Create the node. 3185 SDValue Result; 3186 if (IsTgtIntrinsic) { 3187 // This is target intrinsic that touches memory 3188 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3189 VTs, &Ops[0], Ops.size(), 3190 Info.memVT, 3191 MachinePointerInfo(Info.ptrVal, Info.offset), 3192 Info.align, Info.vol, 3193 Info.readMem, Info.writeMem); 3194 } else if (!HasChain) { 3195 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3196 VTs, &Ops[0], Ops.size()); 3197 } else if (!I.getType()->isVoidTy()) { 3198 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3199 VTs, &Ops[0], Ops.size()); 3200 } else { 3201 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3202 VTs, &Ops[0], Ops.size()); 3203 } 3204 3205 if (HasChain) { 3206 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3207 if (OnlyLoad) 3208 PendingLoads.push_back(Chain); 3209 else 3210 DAG.setRoot(Chain); 3211 } 3212 3213 if (!I.getType()->isVoidTy()) { 3214 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3215 EVT VT = TLI.getValueType(PTy); 3216 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3217 } 3218 3219 setValue(&I, Result); 3220 } 3221} 3222 3223/// GetSignificand - Get the significand and build it into a floating-point 3224/// number with exponent of 1: 3225/// 3226/// Op = (Op & 0x007fffff) | 0x3f800000; 3227/// 3228/// where Op is the hexidecimal representation of floating point value. 3229static SDValue 3230GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3231 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3232 DAG.getConstant(0x007fffff, MVT::i32)); 3233 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3234 DAG.getConstant(0x3f800000, MVT::i32)); 3235 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3236} 3237 3238/// GetExponent - Get the exponent: 3239/// 3240/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3241/// 3242/// where Op is the hexidecimal representation of floating point value. 3243static SDValue 3244GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3245 DebugLoc dl) { 3246 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3247 DAG.getConstant(0x7f800000, MVT::i32)); 3248 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3249 DAG.getConstant(23, TLI.getPointerTy())); 3250 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3251 DAG.getConstant(127, MVT::i32)); 3252 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3253} 3254 3255/// getF32Constant - Get 32-bit floating point constant. 3256static SDValue 3257getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3258 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3259} 3260 3261/// Inlined utility function to implement binary input atomic intrinsics for 3262/// visitIntrinsicCall: I is a call instruction 3263/// Op is the associated NodeType for I 3264const char * 3265SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3266 ISD::NodeType Op) { 3267 SDValue Root = getRoot(); 3268 SDValue L = 3269 DAG.getAtomic(Op, getCurDebugLoc(), 3270 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3271 Root, 3272 getValue(I.getArgOperand(0)), 3273 getValue(I.getArgOperand(1)), 3274 I.getArgOperand(0)); 3275 setValue(&I, L); 3276 DAG.setRoot(L.getValue(1)); 3277 return 0; 3278} 3279 3280// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3281const char * 3282SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3283 SDValue Op1 = getValue(I.getArgOperand(0)); 3284 SDValue Op2 = getValue(I.getArgOperand(1)); 3285 3286 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3287 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3288 return 0; 3289} 3290 3291/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3292/// limited-precision mode. 3293void 3294SelectionDAGBuilder::visitExp(const CallInst &I) { 3295 SDValue result; 3296 DebugLoc dl = getCurDebugLoc(); 3297 3298 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3299 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3300 SDValue Op = getValue(I.getArgOperand(0)); 3301 3302 // Put the exponent in the right bit position for later addition to the 3303 // final result: 3304 // 3305 // #define LOG2OFe 1.4426950f 3306 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3307 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3308 getF32Constant(DAG, 0x3fb8aa3b)); 3309 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3310 3311 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3312 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3313 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3314 3315 // IntegerPartOfX <<= 23; 3316 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3317 DAG.getConstant(23, TLI.getPointerTy())); 3318 3319 if (LimitFloatPrecision <= 6) { 3320 // For floating-point precision of 6: 3321 // 3322 // TwoToFractionalPartOfX = 3323 // 0.997535578f + 3324 // (0.735607626f + 0.252464424f * x) * x; 3325 // 3326 // error 0.0144103317, which is 6 bits 3327 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3328 getF32Constant(DAG, 0x3e814304)); 3329 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3330 getF32Constant(DAG, 0x3f3c50c8)); 3331 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3332 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3333 getF32Constant(DAG, 0x3f7f5e7e)); 3334 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3335 3336 // Add the exponent into the result in integer domain. 3337 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3338 TwoToFracPartOfX, IntegerPartOfX); 3339 3340 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3341 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3342 // For floating-point precision of 12: 3343 // 3344 // TwoToFractionalPartOfX = 3345 // 0.999892986f + 3346 // (0.696457318f + 3347 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3348 // 3349 // 0.000107046256 error, which is 13 to 14 bits 3350 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3351 getF32Constant(DAG, 0x3da235e3)); 3352 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3353 getF32Constant(DAG, 0x3e65b8f3)); 3354 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3355 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3356 getF32Constant(DAG, 0x3f324b07)); 3357 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3358 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3359 getF32Constant(DAG, 0x3f7ff8fd)); 3360 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3361 3362 // Add the exponent into the result in integer domain. 3363 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3364 TwoToFracPartOfX, IntegerPartOfX); 3365 3366 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3367 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3368 // For floating-point precision of 18: 3369 // 3370 // TwoToFractionalPartOfX = 3371 // 0.999999982f + 3372 // (0.693148872f + 3373 // (0.240227044f + 3374 // (0.554906021e-1f + 3375 // (0.961591928e-2f + 3376 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3377 // 3378 // error 2.47208000*10^(-7), which is better than 18 bits 3379 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3380 getF32Constant(DAG, 0x3924b03e)); 3381 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3382 getF32Constant(DAG, 0x3ab24b87)); 3383 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3384 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3385 getF32Constant(DAG, 0x3c1d8c17)); 3386 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3387 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3388 getF32Constant(DAG, 0x3d634a1d)); 3389 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3390 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3391 getF32Constant(DAG, 0x3e75fe14)); 3392 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3393 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3394 getF32Constant(DAG, 0x3f317234)); 3395 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3396 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3397 getF32Constant(DAG, 0x3f800000)); 3398 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3399 MVT::i32, t13); 3400 3401 // Add the exponent into the result in integer domain. 3402 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3403 TwoToFracPartOfX, IntegerPartOfX); 3404 3405 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3406 } 3407 } else { 3408 // No special expansion. 3409 result = DAG.getNode(ISD::FEXP, dl, 3410 getValue(I.getArgOperand(0)).getValueType(), 3411 getValue(I.getArgOperand(0))); 3412 } 3413 3414 setValue(&I, result); 3415} 3416 3417/// visitLog - Lower a log intrinsic. Handles the special sequences for 3418/// limited-precision mode. 3419void 3420SelectionDAGBuilder::visitLog(const CallInst &I) { 3421 SDValue result; 3422 DebugLoc dl = getCurDebugLoc(); 3423 3424 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3425 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3426 SDValue Op = getValue(I.getArgOperand(0)); 3427 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3428 3429 // Scale the exponent by log(2) [0.69314718f]. 3430 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3431 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3432 getF32Constant(DAG, 0x3f317218)); 3433 3434 // Get the significand and build it into a floating-point number with 3435 // exponent of 1. 3436 SDValue X = GetSignificand(DAG, Op1, dl); 3437 3438 if (LimitFloatPrecision <= 6) { 3439 // For floating-point precision of 6: 3440 // 3441 // LogofMantissa = 3442 // -1.1609546f + 3443 // (1.4034025f - 0.23903021f * x) * x; 3444 // 3445 // error 0.0034276066, which is better than 8 bits 3446 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3447 getF32Constant(DAG, 0xbe74c456)); 3448 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3449 getF32Constant(DAG, 0x3fb3a2b1)); 3450 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3451 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3452 getF32Constant(DAG, 0x3f949a29)); 3453 3454 result = DAG.getNode(ISD::FADD, dl, 3455 MVT::f32, LogOfExponent, LogOfMantissa); 3456 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3457 // For floating-point precision of 12: 3458 // 3459 // LogOfMantissa = 3460 // -1.7417939f + 3461 // (2.8212026f + 3462 // (-1.4699568f + 3463 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3464 // 3465 // error 0.000061011436, which is 14 bits 3466 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3467 getF32Constant(DAG, 0xbd67b6d6)); 3468 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3469 getF32Constant(DAG, 0x3ee4f4b8)); 3470 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3471 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3472 getF32Constant(DAG, 0x3fbc278b)); 3473 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3474 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3475 getF32Constant(DAG, 0x40348e95)); 3476 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3477 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3478 getF32Constant(DAG, 0x3fdef31a)); 3479 3480 result = DAG.getNode(ISD::FADD, dl, 3481 MVT::f32, LogOfExponent, LogOfMantissa); 3482 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3483 // For floating-point precision of 18: 3484 // 3485 // LogOfMantissa = 3486 // -2.1072184f + 3487 // (4.2372794f + 3488 // (-3.7029485f + 3489 // (2.2781945f + 3490 // (-0.87823314f + 3491 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3492 // 3493 // error 0.0000023660568, which is better than 18 bits 3494 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3495 getF32Constant(DAG, 0xbc91e5ac)); 3496 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3497 getF32Constant(DAG, 0x3e4350aa)); 3498 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3499 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3500 getF32Constant(DAG, 0x3f60d3e3)); 3501 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3502 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3503 getF32Constant(DAG, 0x4011cdf0)); 3504 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3505 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3506 getF32Constant(DAG, 0x406cfd1c)); 3507 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3508 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3509 getF32Constant(DAG, 0x408797cb)); 3510 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3511 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3512 getF32Constant(DAG, 0x4006dcab)); 3513 3514 result = DAG.getNode(ISD::FADD, dl, 3515 MVT::f32, LogOfExponent, LogOfMantissa); 3516 } 3517 } else { 3518 // No special expansion. 3519 result = DAG.getNode(ISD::FLOG, dl, 3520 getValue(I.getArgOperand(0)).getValueType(), 3521 getValue(I.getArgOperand(0))); 3522 } 3523 3524 setValue(&I, result); 3525} 3526 3527/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3528/// limited-precision mode. 3529void 3530SelectionDAGBuilder::visitLog2(const CallInst &I) { 3531 SDValue result; 3532 DebugLoc dl = getCurDebugLoc(); 3533 3534 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3535 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3536 SDValue Op = getValue(I.getArgOperand(0)); 3537 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3538 3539 // Get the exponent. 3540 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3541 3542 // Get the significand and build it into a floating-point number with 3543 // exponent of 1. 3544 SDValue X = GetSignificand(DAG, Op1, dl); 3545 3546 // Different possible minimax approximations of significand in 3547 // floating-point for various degrees of accuracy over [1,2]. 3548 if (LimitFloatPrecision <= 6) { 3549 // For floating-point precision of 6: 3550 // 3551 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3552 // 3553 // error 0.0049451742, which is more than 7 bits 3554 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3555 getF32Constant(DAG, 0xbeb08fe0)); 3556 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3557 getF32Constant(DAG, 0x40019463)); 3558 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3559 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3560 getF32Constant(DAG, 0x3fd6633d)); 3561 3562 result = DAG.getNode(ISD::FADD, dl, 3563 MVT::f32, LogOfExponent, Log2ofMantissa); 3564 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3565 // For floating-point precision of 12: 3566 // 3567 // Log2ofMantissa = 3568 // -2.51285454f + 3569 // (4.07009056f + 3570 // (-2.12067489f + 3571 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3572 // 3573 // error 0.0000876136000, which is better than 13 bits 3574 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3575 getF32Constant(DAG, 0xbda7262e)); 3576 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3577 getF32Constant(DAG, 0x3f25280b)); 3578 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3579 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3580 getF32Constant(DAG, 0x4007b923)); 3581 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3582 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3583 getF32Constant(DAG, 0x40823e2f)); 3584 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3585 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3586 getF32Constant(DAG, 0x4020d29c)); 3587 3588 result = DAG.getNode(ISD::FADD, dl, 3589 MVT::f32, LogOfExponent, Log2ofMantissa); 3590 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3591 // For floating-point precision of 18: 3592 // 3593 // Log2ofMantissa = 3594 // -3.0400495f + 3595 // (6.1129976f + 3596 // (-5.3420409f + 3597 // (3.2865683f + 3598 // (-1.2669343f + 3599 // (0.27515199f - 3600 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3601 // 3602 // error 0.0000018516, which is better than 18 bits 3603 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3604 getF32Constant(DAG, 0xbcd2769e)); 3605 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3606 getF32Constant(DAG, 0x3e8ce0b9)); 3607 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3608 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3609 getF32Constant(DAG, 0x3fa22ae7)); 3610 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3611 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3612 getF32Constant(DAG, 0x40525723)); 3613 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3614 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3615 getF32Constant(DAG, 0x40aaf200)); 3616 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3617 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3618 getF32Constant(DAG, 0x40c39dad)); 3619 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3620 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3621 getF32Constant(DAG, 0x4042902c)); 3622 3623 result = DAG.getNode(ISD::FADD, dl, 3624 MVT::f32, LogOfExponent, Log2ofMantissa); 3625 } 3626 } else { 3627 // No special expansion. 3628 result = DAG.getNode(ISD::FLOG2, dl, 3629 getValue(I.getArgOperand(0)).getValueType(), 3630 getValue(I.getArgOperand(0))); 3631 } 3632 3633 setValue(&I, result); 3634} 3635 3636/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3637/// limited-precision mode. 3638void 3639SelectionDAGBuilder::visitLog10(const CallInst &I) { 3640 SDValue result; 3641 DebugLoc dl = getCurDebugLoc(); 3642 3643 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3644 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3645 SDValue Op = getValue(I.getArgOperand(0)); 3646 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3647 3648 // Scale the exponent by log10(2) [0.30102999f]. 3649 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3650 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3651 getF32Constant(DAG, 0x3e9a209a)); 3652 3653 // Get the significand and build it into a floating-point number with 3654 // exponent of 1. 3655 SDValue X = GetSignificand(DAG, Op1, dl); 3656 3657 if (LimitFloatPrecision <= 6) { 3658 // For floating-point precision of 6: 3659 // 3660 // Log10ofMantissa = 3661 // -0.50419619f + 3662 // (0.60948995f - 0.10380950f * x) * x; 3663 // 3664 // error 0.0014886165, which is 6 bits 3665 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3666 getF32Constant(DAG, 0xbdd49a13)); 3667 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3668 getF32Constant(DAG, 0x3f1c0789)); 3669 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3670 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3671 getF32Constant(DAG, 0x3f011300)); 3672 3673 result = DAG.getNode(ISD::FADD, dl, 3674 MVT::f32, LogOfExponent, Log10ofMantissa); 3675 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3676 // For floating-point precision of 12: 3677 // 3678 // Log10ofMantissa = 3679 // -0.64831180f + 3680 // (0.91751397f + 3681 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3682 // 3683 // error 0.00019228036, which is better than 12 bits 3684 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3685 getF32Constant(DAG, 0x3d431f31)); 3686 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3687 getF32Constant(DAG, 0x3ea21fb2)); 3688 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3689 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3690 getF32Constant(DAG, 0x3f6ae232)); 3691 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3692 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3693 getF32Constant(DAG, 0x3f25f7c3)); 3694 3695 result = DAG.getNode(ISD::FADD, dl, 3696 MVT::f32, LogOfExponent, Log10ofMantissa); 3697 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3698 // For floating-point precision of 18: 3699 // 3700 // Log10ofMantissa = 3701 // -0.84299375f + 3702 // (1.5327582f + 3703 // (-1.0688956f + 3704 // (0.49102474f + 3705 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3706 // 3707 // error 0.0000037995730, which is better than 18 bits 3708 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3709 getF32Constant(DAG, 0x3c5d51ce)); 3710 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3711 getF32Constant(DAG, 0x3e00685a)); 3712 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3713 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3714 getF32Constant(DAG, 0x3efb6798)); 3715 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3716 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3717 getF32Constant(DAG, 0x3f88d192)); 3718 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3719 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3720 getF32Constant(DAG, 0x3fc4316c)); 3721 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3722 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3723 getF32Constant(DAG, 0x3f57ce70)); 3724 3725 result = DAG.getNode(ISD::FADD, dl, 3726 MVT::f32, LogOfExponent, Log10ofMantissa); 3727 } 3728 } else { 3729 // No special expansion. 3730 result = DAG.getNode(ISD::FLOG10, dl, 3731 getValue(I.getArgOperand(0)).getValueType(), 3732 getValue(I.getArgOperand(0))); 3733 } 3734 3735 setValue(&I, result); 3736} 3737 3738/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3739/// limited-precision mode. 3740void 3741SelectionDAGBuilder::visitExp2(const CallInst &I) { 3742 SDValue result; 3743 DebugLoc dl = getCurDebugLoc(); 3744 3745 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3746 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3747 SDValue Op = getValue(I.getArgOperand(0)); 3748 3749 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3750 3751 // FractionalPartOfX = x - (float)IntegerPartOfX; 3752 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3753 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3754 3755 // IntegerPartOfX <<= 23; 3756 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3757 DAG.getConstant(23, TLI.getPointerTy())); 3758 3759 if (LimitFloatPrecision <= 6) { 3760 // For floating-point precision of 6: 3761 // 3762 // TwoToFractionalPartOfX = 3763 // 0.997535578f + 3764 // (0.735607626f + 0.252464424f * x) * x; 3765 // 3766 // error 0.0144103317, which is 6 bits 3767 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3768 getF32Constant(DAG, 0x3e814304)); 3769 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3770 getF32Constant(DAG, 0x3f3c50c8)); 3771 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3772 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3773 getF32Constant(DAG, 0x3f7f5e7e)); 3774 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3775 SDValue TwoToFractionalPartOfX = 3776 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3777 3778 result = DAG.getNode(ISD::BITCAST, dl, 3779 MVT::f32, TwoToFractionalPartOfX); 3780 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3781 // For floating-point precision of 12: 3782 // 3783 // TwoToFractionalPartOfX = 3784 // 0.999892986f + 3785 // (0.696457318f + 3786 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3787 // 3788 // error 0.000107046256, which is 13 to 14 bits 3789 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3790 getF32Constant(DAG, 0x3da235e3)); 3791 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3792 getF32Constant(DAG, 0x3e65b8f3)); 3793 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3794 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3795 getF32Constant(DAG, 0x3f324b07)); 3796 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3797 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3798 getF32Constant(DAG, 0x3f7ff8fd)); 3799 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3800 SDValue TwoToFractionalPartOfX = 3801 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3802 3803 result = DAG.getNode(ISD::BITCAST, dl, 3804 MVT::f32, TwoToFractionalPartOfX); 3805 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3806 // For floating-point precision of 18: 3807 // 3808 // TwoToFractionalPartOfX = 3809 // 0.999999982f + 3810 // (0.693148872f + 3811 // (0.240227044f + 3812 // (0.554906021e-1f + 3813 // (0.961591928e-2f + 3814 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3815 // error 2.47208000*10^(-7), which is better than 18 bits 3816 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3817 getF32Constant(DAG, 0x3924b03e)); 3818 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3819 getF32Constant(DAG, 0x3ab24b87)); 3820 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3821 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3822 getF32Constant(DAG, 0x3c1d8c17)); 3823 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3824 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3825 getF32Constant(DAG, 0x3d634a1d)); 3826 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3827 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3828 getF32Constant(DAG, 0x3e75fe14)); 3829 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3830 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3831 getF32Constant(DAG, 0x3f317234)); 3832 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3833 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3834 getF32Constant(DAG, 0x3f800000)); 3835 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 3836 SDValue TwoToFractionalPartOfX = 3837 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3838 3839 result = DAG.getNode(ISD::BITCAST, dl, 3840 MVT::f32, TwoToFractionalPartOfX); 3841 } 3842 } else { 3843 // No special expansion. 3844 result = DAG.getNode(ISD::FEXP2, dl, 3845 getValue(I.getArgOperand(0)).getValueType(), 3846 getValue(I.getArgOperand(0))); 3847 } 3848 3849 setValue(&I, result); 3850} 3851 3852/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3853/// limited-precision mode with x == 10.0f. 3854void 3855SelectionDAGBuilder::visitPow(const CallInst &I) { 3856 SDValue result; 3857 const Value *Val = I.getArgOperand(0); 3858 DebugLoc dl = getCurDebugLoc(); 3859 bool IsExp10 = false; 3860 3861 if (getValue(Val).getValueType() == MVT::f32 && 3862 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 3863 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3864 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3865 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3866 APFloat Ten(10.0f); 3867 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3868 } 3869 } 3870 } 3871 3872 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3873 SDValue Op = getValue(I.getArgOperand(1)); 3874 3875 // Put the exponent in the right bit position for later addition to the 3876 // final result: 3877 // 3878 // #define LOG2OF10 3.3219281f 3879 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3880 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3881 getF32Constant(DAG, 0x40549a78)); 3882 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3883 3884 // FractionalPartOfX = x - (float)IntegerPartOfX; 3885 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3886 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3887 3888 // IntegerPartOfX <<= 23; 3889 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3890 DAG.getConstant(23, TLI.getPointerTy())); 3891 3892 if (LimitFloatPrecision <= 6) { 3893 // For floating-point precision of 6: 3894 // 3895 // twoToFractionalPartOfX = 3896 // 0.997535578f + 3897 // (0.735607626f + 0.252464424f * x) * x; 3898 // 3899 // error 0.0144103317, which is 6 bits 3900 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3901 getF32Constant(DAG, 0x3e814304)); 3902 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3903 getF32Constant(DAG, 0x3f3c50c8)); 3904 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3905 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3906 getF32Constant(DAG, 0x3f7f5e7e)); 3907 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3908 SDValue TwoToFractionalPartOfX = 3909 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3910 3911 result = DAG.getNode(ISD::BITCAST, dl, 3912 MVT::f32, TwoToFractionalPartOfX); 3913 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3914 // For floating-point precision of 12: 3915 // 3916 // TwoToFractionalPartOfX = 3917 // 0.999892986f + 3918 // (0.696457318f + 3919 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3920 // 3921 // error 0.000107046256, which is 13 to 14 bits 3922 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3923 getF32Constant(DAG, 0x3da235e3)); 3924 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3925 getF32Constant(DAG, 0x3e65b8f3)); 3926 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3927 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3928 getF32Constant(DAG, 0x3f324b07)); 3929 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3930 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3931 getF32Constant(DAG, 0x3f7ff8fd)); 3932 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3933 SDValue TwoToFractionalPartOfX = 3934 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3935 3936 result = DAG.getNode(ISD::BITCAST, dl, 3937 MVT::f32, TwoToFractionalPartOfX); 3938 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3939 // For floating-point precision of 18: 3940 // 3941 // TwoToFractionalPartOfX = 3942 // 0.999999982f + 3943 // (0.693148872f + 3944 // (0.240227044f + 3945 // (0.554906021e-1f + 3946 // (0.961591928e-2f + 3947 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3948 // error 2.47208000*10^(-7), which is better than 18 bits 3949 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3950 getF32Constant(DAG, 0x3924b03e)); 3951 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3952 getF32Constant(DAG, 0x3ab24b87)); 3953 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3954 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3955 getF32Constant(DAG, 0x3c1d8c17)); 3956 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3957 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3958 getF32Constant(DAG, 0x3d634a1d)); 3959 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3960 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3961 getF32Constant(DAG, 0x3e75fe14)); 3962 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3963 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3964 getF32Constant(DAG, 0x3f317234)); 3965 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3966 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3967 getF32Constant(DAG, 0x3f800000)); 3968 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 3969 SDValue TwoToFractionalPartOfX = 3970 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3971 3972 result = DAG.getNode(ISD::BITCAST, dl, 3973 MVT::f32, TwoToFractionalPartOfX); 3974 } 3975 } else { 3976 // No special expansion. 3977 result = DAG.getNode(ISD::FPOW, dl, 3978 getValue(I.getArgOperand(0)).getValueType(), 3979 getValue(I.getArgOperand(0)), 3980 getValue(I.getArgOperand(1))); 3981 } 3982 3983 setValue(&I, result); 3984} 3985 3986 3987/// ExpandPowI - Expand a llvm.powi intrinsic. 3988static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 3989 SelectionDAG &DAG) { 3990 // If RHS is a constant, we can expand this out to a multiplication tree, 3991 // otherwise we end up lowering to a call to __powidf2 (for example). When 3992 // optimizing for size, we only want to do this if the expansion would produce 3993 // a small number of multiplies, otherwise we do the full expansion. 3994 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3995 // Get the exponent as a positive value. 3996 unsigned Val = RHSC->getSExtValue(); 3997 if ((int)Val < 0) Val = -Val; 3998 3999 // powi(x, 0) -> 1.0 4000 if (Val == 0) 4001 return DAG.getConstantFP(1.0, LHS.getValueType()); 4002 4003 const Function *F = DAG.getMachineFunction().getFunction(); 4004 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4005 // If optimizing for size, don't insert too many multiplies. This 4006 // inserts up to 5 multiplies. 4007 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4008 // We use the simple binary decomposition method to generate the multiply 4009 // sequence. There are more optimal ways to do this (for example, 4010 // powi(x,15) generates one more multiply than it should), but this has 4011 // the benefit of being both really simple and much better than a libcall. 4012 SDValue Res; // Logically starts equal to 1.0 4013 SDValue CurSquare = LHS; 4014 while (Val) { 4015 if (Val & 1) { 4016 if (Res.getNode()) 4017 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4018 else 4019 Res = CurSquare; // 1.0*CurSquare. 4020 } 4021 4022 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4023 CurSquare, CurSquare); 4024 Val >>= 1; 4025 } 4026 4027 // If the original was negative, invert the result, producing 1/(x*x*x). 4028 if (RHSC->getSExtValue() < 0) 4029 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4030 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4031 return Res; 4032 } 4033 } 4034 4035 // Otherwise, expand to a libcall. 4036 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4037} 4038 4039/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4040/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4041/// At the end of instruction selection, they will be inserted to the entry BB. 4042bool 4043SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4044 int64_t Offset, 4045 const SDValue &N) { 4046 const Argument *Arg = dyn_cast<Argument>(V); 4047 if (!Arg) 4048 return false; 4049 4050 MachineFunction &MF = DAG.getMachineFunction(); 4051 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4052 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4053 4054 // Ignore inlined function arguments here. 4055 DIVariable DV(Variable); 4056 if (DV.isInlinedFnArgument(MF.getFunction())) 4057 return false; 4058 4059 MachineBasicBlock *MBB = FuncInfo.MBB; 4060 if (MBB != &MF.front()) 4061 return false; 4062 4063 unsigned Reg = 0; 4064 if (Arg->hasByValAttr()) { 4065 // Byval arguments' frame index is recorded during argument lowering. 4066 // Use this info directly. 4067 Reg = TRI->getFrameRegister(MF); 4068 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 4069 // If byval argument ofset is not recorded then ignore this. 4070 if (!Offset) 4071 Reg = 0; 4072 } 4073 4074 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) { 4075 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4076 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 4077 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4078 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4079 if (PR) 4080 Reg = PR; 4081 } 4082 } 4083 4084 if (!Reg) { 4085 // Check if ValueMap has reg number. 4086 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4087 if (VMI != FuncInfo.ValueMap.end()) 4088 Reg = VMI->second; 4089 } 4090 4091 if (!Reg && N.getNode()) { 4092 // Check if frame index is available. 4093 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4094 if (FrameIndexSDNode *FINode = 4095 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4096 Reg = TRI->getFrameRegister(MF); 4097 Offset = FINode->getIndex(); 4098 } 4099 } 4100 4101 if (!Reg) 4102 return false; 4103 4104 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4105 TII->get(TargetOpcode::DBG_VALUE)) 4106 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4107 FuncInfo.ArgDbgValues.push_back(&*MIB); 4108 return true; 4109} 4110 4111// VisualStudio defines setjmp as _setjmp 4112#if defined(_MSC_VER) && defined(setjmp) && \ 4113 !defined(setjmp_undefined_for_msvc) 4114# pragma push_macro("setjmp") 4115# undef setjmp 4116# define setjmp_undefined_for_msvc 4117#endif 4118 4119/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4120/// we want to emit this as a call to a named external function, return the name 4121/// otherwise lower it and return null. 4122const char * 4123SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4124 DebugLoc dl = getCurDebugLoc(); 4125 SDValue Res; 4126 4127 switch (Intrinsic) { 4128 default: 4129 // By default, turn this into a target intrinsic node. 4130 visitTargetIntrinsic(I, Intrinsic); 4131 return 0; 4132 case Intrinsic::vastart: visitVAStart(I); return 0; 4133 case Intrinsic::vaend: visitVAEnd(I); return 0; 4134 case Intrinsic::vacopy: visitVACopy(I); return 0; 4135 case Intrinsic::returnaddress: 4136 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4137 getValue(I.getArgOperand(0)))); 4138 return 0; 4139 case Intrinsic::frameaddress: 4140 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4141 getValue(I.getArgOperand(0)))); 4142 return 0; 4143 case Intrinsic::setjmp: 4144 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4145 case Intrinsic::longjmp: 4146 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4147 case Intrinsic::memcpy: { 4148 // Assert for address < 256 since we support only user defined address 4149 // spaces. 4150 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4151 < 256 && 4152 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4153 < 256 && 4154 "Unknown address space"); 4155 SDValue Op1 = getValue(I.getArgOperand(0)); 4156 SDValue Op2 = getValue(I.getArgOperand(1)); 4157 SDValue Op3 = getValue(I.getArgOperand(2)); 4158 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4159 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4160 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4161 MachinePointerInfo(I.getArgOperand(0)), 4162 MachinePointerInfo(I.getArgOperand(1)))); 4163 return 0; 4164 } 4165 case Intrinsic::memset: { 4166 // Assert for address < 256 since we support only user defined address 4167 // spaces. 4168 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4169 < 256 && 4170 "Unknown address space"); 4171 SDValue Op1 = getValue(I.getArgOperand(0)); 4172 SDValue Op2 = getValue(I.getArgOperand(1)); 4173 SDValue Op3 = getValue(I.getArgOperand(2)); 4174 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4175 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4176 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4177 MachinePointerInfo(I.getArgOperand(0)))); 4178 return 0; 4179 } 4180 case Intrinsic::memmove: { 4181 // Assert for address < 256 since we support only user defined address 4182 // spaces. 4183 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4184 < 256 && 4185 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4186 < 256 && 4187 "Unknown address space"); 4188 SDValue Op1 = getValue(I.getArgOperand(0)); 4189 SDValue Op2 = getValue(I.getArgOperand(1)); 4190 SDValue Op3 = getValue(I.getArgOperand(2)); 4191 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4192 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4193 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4194 MachinePointerInfo(I.getArgOperand(0)), 4195 MachinePointerInfo(I.getArgOperand(1)))); 4196 return 0; 4197 } 4198 case Intrinsic::dbg_declare: { 4199 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4200 MDNode *Variable = DI.getVariable(); 4201 const Value *Address = DI.getAddress(); 4202 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4203 return 0; 4204 4205 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4206 // but do not always have a corresponding SDNode built. The SDNodeOrder 4207 // absolute, but not relative, values are different depending on whether 4208 // debug info exists. 4209 ++SDNodeOrder; 4210 4211 // Check if address has undef value. 4212 if (isa<UndefValue>(Address) || 4213 (Address->use_empty() && !isa<Argument>(Address))) { 4214 DEBUG(dbgs() << "Dropping debug info for " << DI); 4215 return 0; 4216 } 4217 4218 SDValue &N = NodeMap[Address]; 4219 if (!N.getNode() && isa<Argument>(Address)) 4220 // Check unused arguments map. 4221 N = UnusedArgNodeMap[Address]; 4222 SDDbgValue *SDV; 4223 if (N.getNode()) { 4224 // Parameters are handled specially. 4225 bool isParameter = 4226 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4227 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4228 Address = BCI->getOperand(0); 4229 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4230 4231 if (isParameter && !AI) { 4232 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4233 if (FINode) 4234 // Byval parameter. We have a frame index at this point. 4235 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4236 0, dl, SDNodeOrder); 4237 else { 4238 // Can't do anything with other non-AI cases yet. This might be a 4239 // parameter of a callee function that got inlined, for example. 4240 DEBUG(dbgs() << "Dropping debug info for " << DI); 4241 return 0; 4242 } 4243 } else if (AI) 4244 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4245 0, dl, SDNodeOrder); 4246 else { 4247 // Can't do anything with other non-AI cases yet. 4248 DEBUG(dbgs() << "Dropping debug info for " << DI); 4249 return 0; 4250 } 4251 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4252 } else { 4253 // If Address is an argument then try to emit its dbg value using 4254 // virtual register info from the FuncInfo.ValueMap. 4255 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4256 // If variable is pinned by a alloca in dominating bb then 4257 // use StaticAllocaMap. 4258 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4259 if (AI->getParent() != DI.getParent()) { 4260 DenseMap<const AllocaInst*, int>::iterator SI = 4261 FuncInfo.StaticAllocaMap.find(AI); 4262 if (SI != FuncInfo.StaticAllocaMap.end()) { 4263 SDV = DAG.getDbgValue(Variable, SI->second, 4264 0, dl, SDNodeOrder); 4265 DAG.AddDbgValue(SDV, 0, false); 4266 return 0; 4267 } 4268 } 4269 } 4270 DEBUG(dbgs() << "Dropping debug info for " << DI); 4271 } 4272 } 4273 return 0; 4274 } 4275 case Intrinsic::dbg_value: { 4276 const DbgValueInst &DI = cast<DbgValueInst>(I); 4277 if (!DIVariable(DI.getVariable()).Verify()) 4278 return 0; 4279 4280 MDNode *Variable = DI.getVariable(); 4281 uint64_t Offset = DI.getOffset(); 4282 const Value *V = DI.getValue(); 4283 if (!V) 4284 return 0; 4285 4286 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4287 // but do not always have a corresponding SDNode built. The SDNodeOrder 4288 // absolute, but not relative, values are different depending on whether 4289 // debug info exists. 4290 ++SDNodeOrder; 4291 SDDbgValue *SDV; 4292 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4293 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4294 DAG.AddDbgValue(SDV, 0, false); 4295 } else { 4296 // Do not use getValue() in here; we don't want to generate code at 4297 // this point if it hasn't been done yet. 4298 SDValue N = NodeMap[V]; 4299 if (!N.getNode() && isa<Argument>(V)) 4300 // Check unused arguments map. 4301 N = UnusedArgNodeMap[V]; 4302 if (N.getNode()) { 4303 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4304 SDV = DAG.getDbgValue(Variable, N.getNode(), 4305 N.getResNo(), Offset, dl, SDNodeOrder); 4306 DAG.AddDbgValue(SDV, N.getNode(), false); 4307 } 4308 } else if (isa<PHINode>(V) && !V->use_empty() ) { 4309 // Do not call getValue(V) yet, as we don't want to generate code. 4310 // Remember it for later. 4311 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4312 DanglingDebugInfoMap[V] = DDI; 4313 } else { 4314 // We may expand this to cover more cases. One case where we have no 4315 // data available is an unreferenced parameter. 4316 DEBUG(dbgs() << "Dropping debug info for " << DI); 4317 } 4318 } 4319 4320 // Build a debug info table entry. 4321 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4322 V = BCI->getOperand(0); 4323 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4324 // Don't handle byval struct arguments or VLAs, for example. 4325 if (!AI) 4326 return 0; 4327 DenseMap<const AllocaInst*, int>::iterator SI = 4328 FuncInfo.StaticAllocaMap.find(AI); 4329 if (SI == FuncInfo.StaticAllocaMap.end()) 4330 return 0; // VLAs. 4331 int FI = SI->second; 4332 4333 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4334 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4335 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4336 return 0; 4337 } 4338 case Intrinsic::eh_exception: { 4339 // Insert the EXCEPTIONADDR instruction. 4340 assert(FuncInfo.MBB->isLandingPad() && 4341 "Call to eh.exception not in landing pad!"); 4342 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4343 SDValue Ops[1]; 4344 Ops[0] = DAG.getRoot(); 4345 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4346 setValue(&I, Op); 4347 DAG.setRoot(Op.getValue(1)); 4348 return 0; 4349 } 4350 4351 case Intrinsic::eh_selector: { 4352 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4353 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4354 if (CallMBB->isLandingPad()) 4355 AddCatchInfo(I, &MMI, CallMBB); 4356 else { 4357#ifndef NDEBUG 4358 FuncInfo.CatchInfoLost.insert(&I); 4359#endif 4360 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4361 unsigned Reg = TLI.getExceptionSelectorRegister(); 4362 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4363 } 4364 4365 // Insert the EHSELECTION instruction. 4366 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4367 SDValue Ops[2]; 4368 Ops[0] = getValue(I.getArgOperand(0)); 4369 Ops[1] = getRoot(); 4370 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4371 DAG.setRoot(Op.getValue(1)); 4372 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4373 return 0; 4374 } 4375 4376 case Intrinsic::eh_typeid_for: { 4377 // Find the type id for the given typeinfo. 4378 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4379 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4380 Res = DAG.getConstant(TypeID, MVT::i32); 4381 setValue(&I, Res); 4382 return 0; 4383 } 4384 4385 case Intrinsic::eh_return_i32: 4386 case Intrinsic::eh_return_i64: 4387 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4388 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4389 MVT::Other, 4390 getControlRoot(), 4391 getValue(I.getArgOperand(0)), 4392 getValue(I.getArgOperand(1)))); 4393 return 0; 4394 case Intrinsic::eh_unwind_init: 4395 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4396 return 0; 4397 case Intrinsic::eh_dwarf_cfa: { 4398 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4399 TLI.getPointerTy()); 4400 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4401 TLI.getPointerTy(), 4402 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4403 TLI.getPointerTy()), 4404 CfaArg); 4405 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4406 TLI.getPointerTy(), 4407 DAG.getConstant(0, TLI.getPointerTy())); 4408 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4409 FA, Offset)); 4410 return 0; 4411 } 4412 case Intrinsic::eh_sjlj_callsite: { 4413 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4414 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4415 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4416 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4417 4418 MMI.setCurrentCallSite(CI->getZExtValue()); 4419 return 0; 4420 } 4421 case Intrinsic::eh_sjlj_setjmp: { 4422 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4423 getValue(I.getArgOperand(0)))); 4424 return 0; 4425 } 4426 case Intrinsic::eh_sjlj_longjmp: { 4427 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4428 getRoot(), getValue(I.getArgOperand(0)))); 4429 return 0; 4430 } 4431 case Intrinsic::eh_sjlj_dispatch_setup: { 4432 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4433 getRoot(), getValue(I.getArgOperand(0)))); 4434 return 0; 4435 } 4436 4437 case Intrinsic::x86_mmx_pslli_w: 4438 case Intrinsic::x86_mmx_pslli_d: 4439 case Intrinsic::x86_mmx_pslli_q: 4440 case Intrinsic::x86_mmx_psrli_w: 4441 case Intrinsic::x86_mmx_psrli_d: 4442 case Intrinsic::x86_mmx_psrli_q: 4443 case Intrinsic::x86_mmx_psrai_w: 4444 case Intrinsic::x86_mmx_psrai_d: { 4445 SDValue ShAmt = getValue(I.getArgOperand(1)); 4446 if (isa<ConstantSDNode>(ShAmt)) { 4447 visitTargetIntrinsic(I, Intrinsic); 4448 return 0; 4449 } 4450 unsigned NewIntrinsic = 0; 4451 EVT ShAmtVT = MVT::v2i32; 4452 switch (Intrinsic) { 4453 case Intrinsic::x86_mmx_pslli_w: 4454 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4455 break; 4456 case Intrinsic::x86_mmx_pslli_d: 4457 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4458 break; 4459 case Intrinsic::x86_mmx_pslli_q: 4460 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4461 break; 4462 case Intrinsic::x86_mmx_psrli_w: 4463 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4464 break; 4465 case Intrinsic::x86_mmx_psrli_d: 4466 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4467 break; 4468 case Intrinsic::x86_mmx_psrli_q: 4469 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4470 break; 4471 case Intrinsic::x86_mmx_psrai_w: 4472 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4473 break; 4474 case Intrinsic::x86_mmx_psrai_d: 4475 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4476 break; 4477 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4478 } 4479 4480 // The vector shift intrinsics with scalars uses 32b shift amounts but 4481 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4482 // to be zero. 4483 // We must do this early because v2i32 is not a legal type. 4484 DebugLoc dl = getCurDebugLoc(); 4485 SDValue ShOps[2]; 4486 ShOps[0] = ShAmt; 4487 ShOps[1] = DAG.getConstant(0, MVT::i32); 4488 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4489 EVT DestVT = TLI.getValueType(I.getType()); 4490 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4491 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4492 DAG.getConstant(NewIntrinsic, MVT::i32), 4493 getValue(I.getArgOperand(0)), ShAmt); 4494 setValue(&I, Res); 4495 return 0; 4496 } 4497 case Intrinsic::convertff: 4498 case Intrinsic::convertfsi: 4499 case Intrinsic::convertfui: 4500 case Intrinsic::convertsif: 4501 case Intrinsic::convertuif: 4502 case Intrinsic::convertss: 4503 case Intrinsic::convertsu: 4504 case Intrinsic::convertus: 4505 case Intrinsic::convertuu: { 4506 ISD::CvtCode Code = ISD::CVT_INVALID; 4507 switch (Intrinsic) { 4508 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4509 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4510 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4511 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4512 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4513 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4514 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4515 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4516 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4517 } 4518 EVT DestVT = TLI.getValueType(I.getType()); 4519 const Value *Op1 = I.getArgOperand(0); 4520 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4521 DAG.getValueType(DestVT), 4522 DAG.getValueType(getValue(Op1).getValueType()), 4523 getValue(I.getArgOperand(1)), 4524 getValue(I.getArgOperand(2)), 4525 Code); 4526 setValue(&I, Res); 4527 return 0; 4528 } 4529 case Intrinsic::sqrt: 4530 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4531 getValue(I.getArgOperand(0)).getValueType(), 4532 getValue(I.getArgOperand(0)))); 4533 return 0; 4534 case Intrinsic::powi: 4535 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4536 getValue(I.getArgOperand(1)), DAG)); 4537 return 0; 4538 case Intrinsic::sin: 4539 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4540 getValue(I.getArgOperand(0)).getValueType(), 4541 getValue(I.getArgOperand(0)))); 4542 return 0; 4543 case Intrinsic::cos: 4544 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4545 getValue(I.getArgOperand(0)).getValueType(), 4546 getValue(I.getArgOperand(0)))); 4547 return 0; 4548 case Intrinsic::log: 4549 visitLog(I); 4550 return 0; 4551 case Intrinsic::log2: 4552 visitLog2(I); 4553 return 0; 4554 case Intrinsic::log10: 4555 visitLog10(I); 4556 return 0; 4557 case Intrinsic::exp: 4558 visitExp(I); 4559 return 0; 4560 case Intrinsic::exp2: 4561 visitExp2(I); 4562 return 0; 4563 case Intrinsic::pow: 4564 visitPow(I); 4565 return 0; 4566 case Intrinsic::convert_to_fp16: 4567 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4568 MVT::i16, getValue(I.getArgOperand(0)))); 4569 return 0; 4570 case Intrinsic::convert_from_fp16: 4571 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4572 MVT::f32, getValue(I.getArgOperand(0)))); 4573 return 0; 4574 case Intrinsic::pcmarker: { 4575 SDValue Tmp = getValue(I.getArgOperand(0)); 4576 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4577 return 0; 4578 } 4579 case Intrinsic::readcyclecounter: { 4580 SDValue Op = getRoot(); 4581 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4582 DAG.getVTList(MVT::i64, MVT::Other), 4583 &Op, 1); 4584 setValue(&I, Res); 4585 DAG.setRoot(Res.getValue(1)); 4586 return 0; 4587 } 4588 case Intrinsic::bswap: 4589 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4590 getValue(I.getArgOperand(0)).getValueType(), 4591 getValue(I.getArgOperand(0)))); 4592 return 0; 4593 case Intrinsic::cttz: { 4594 SDValue Arg = getValue(I.getArgOperand(0)); 4595 EVT Ty = Arg.getValueType(); 4596 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4597 return 0; 4598 } 4599 case Intrinsic::ctlz: { 4600 SDValue Arg = getValue(I.getArgOperand(0)); 4601 EVT Ty = Arg.getValueType(); 4602 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4603 return 0; 4604 } 4605 case Intrinsic::ctpop: { 4606 SDValue Arg = getValue(I.getArgOperand(0)); 4607 EVT Ty = Arg.getValueType(); 4608 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4609 return 0; 4610 } 4611 case Intrinsic::stacksave: { 4612 SDValue Op = getRoot(); 4613 Res = DAG.getNode(ISD::STACKSAVE, dl, 4614 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4615 setValue(&I, Res); 4616 DAG.setRoot(Res.getValue(1)); 4617 return 0; 4618 } 4619 case Intrinsic::stackrestore: { 4620 Res = getValue(I.getArgOperand(0)); 4621 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4622 return 0; 4623 } 4624 case Intrinsic::stackprotector: { 4625 // Emit code into the DAG to store the stack guard onto the stack. 4626 MachineFunction &MF = DAG.getMachineFunction(); 4627 MachineFrameInfo *MFI = MF.getFrameInfo(); 4628 EVT PtrTy = TLI.getPointerTy(); 4629 4630 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4631 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4632 4633 int FI = FuncInfo.StaticAllocaMap[Slot]; 4634 MFI->setStackProtectorIndex(FI); 4635 4636 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4637 4638 // Store the stack protector onto the stack. 4639 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4640 MachinePointerInfo::getFixedStack(FI), 4641 true, false, 0); 4642 setValue(&I, Res); 4643 DAG.setRoot(Res); 4644 return 0; 4645 } 4646 case Intrinsic::objectsize: { 4647 // If we don't know by now, we're never going to know. 4648 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4649 4650 assert(CI && "Non-constant type in __builtin_object_size?"); 4651 4652 SDValue Arg = getValue(I.getCalledValue()); 4653 EVT Ty = Arg.getValueType(); 4654 4655 if (CI->isZero()) 4656 Res = DAG.getConstant(-1ULL, Ty); 4657 else 4658 Res = DAG.getConstant(0, Ty); 4659 4660 setValue(&I, Res); 4661 return 0; 4662 } 4663 case Intrinsic::var_annotation: 4664 // Discard annotate attributes 4665 return 0; 4666 4667 case Intrinsic::init_trampoline: { 4668 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4669 4670 SDValue Ops[6]; 4671 Ops[0] = getRoot(); 4672 Ops[1] = getValue(I.getArgOperand(0)); 4673 Ops[2] = getValue(I.getArgOperand(1)); 4674 Ops[3] = getValue(I.getArgOperand(2)); 4675 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4676 Ops[5] = DAG.getSrcValue(F); 4677 4678 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4679 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4680 Ops, 6); 4681 4682 setValue(&I, Res); 4683 DAG.setRoot(Res.getValue(1)); 4684 return 0; 4685 } 4686 case Intrinsic::gcroot: 4687 if (GFI) { 4688 const Value *Alloca = I.getArgOperand(0); 4689 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4690 4691 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4692 GFI->addStackRoot(FI->getIndex(), TypeMap); 4693 } 4694 return 0; 4695 case Intrinsic::gcread: 4696 case Intrinsic::gcwrite: 4697 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4698 return 0; 4699 case Intrinsic::flt_rounds: 4700 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4701 return 0; 4702 case Intrinsic::trap: 4703 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4704 return 0; 4705 case Intrinsic::uadd_with_overflow: 4706 return implVisitAluOverflow(I, ISD::UADDO); 4707 case Intrinsic::sadd_with_overflow: 4708 return implVisitAluOverflow(I, ISD::SADDO); 4709 case Intrinsic::usub_with_overflow: 4710 return implVisitAluOverflow(I, ISD::USUBO); 4711 case Intrinsic::ssub_with_overflow: 4712 return implVisitAluOverflow(I, ISD::SSUBO); 4713 case Intrinsic::umul_with_overflow: 4714 return implVisitAluOverflow(I, ISD::UMULO); 4715 case Intrinsic::smul_with_overflow: 4716 return implVisitAluOverflow(I, ISD::SMULO); 4717 4718 case Intrinsic::prefetch: { 4719 SDValue Ops[4]; 4720 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 4721 Ops[0] = getRoot(); 4722 Ops[1] = getValue(I.getArgOperand(0)); 4723 Ops[2] = getValue(I.getArgOperand(1)); 4724 Ops[3] = getValue(I.getArgOperand(2)); 4725 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 4726 DAG.getVTList(MVT::Other), 4727 &Ops[0], 4, 4728 EVT::getIntegerVT(*Context, 8), 4729 MachinePointerInfo(I.getArgOperand(0)), 4730 0, /* align */ 4731 false, /* volatile */ 4732 rw==0, /* read */ 4733 rw==1)); /* write */ 4734 return 0; 4735 } 4736 case Intrinsic::memory_barrier: { 4737 SDValue Ops[6]; 4738 Ops[0] = getRoot(); 4739 for (int x = 1; x < 6; ++x) 4740 Ops[x] = getValue(I.getArgOperand(x - 1)); 4741 4742 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4743 return 0; 4744 } 4745 case Intrinsic::atomic_cmp_swap: { 4746 SDValue Root = getRoot(); 4747 SDValue L = 4748 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4749 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 4750 Root, 4751 getValue(I.getArgOperand(0)), 4752 getValue(I.getArgOperand(1)), 4753 getValue(I.getArgOperand(2)), 4754 MachinePointerInfo(I.getArgOperand(0))); 4755 setValue(&I, L); 4756 DAG.setRoot(L.getValue(1)); 4757 return 0; 4758 } 4759 case Intrinsic::atomic_load_add: 4760 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4761 case Intrinsic::atomic_load_sub: 4762 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4763 case Intrinsic::atomic_load_or: 4764 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4765 case Intrinsic::atomic_load_xor: 4766 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4767 case Intrinsic::atomic_load_and: 4768 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4769 case Intrinsic::atomic_load_nand: 4770 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4771 case Intrinsic::atomic_load_max: 4772 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4773 case Intrinsic::atomic_load_min: 4774 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4775 case Intrinsic::atomic_load_umin: 4776 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4777 case Intrinsic::atomic_load_umax: 4778 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4779 case Intrinsic::atomic_swap: 4780 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4781 4782 case Intrinsic::invariant_start: 4783 case Intrinsic::lifetime_start: 4784 // Discard region information. 4785 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4786 return 0; 4787 case Intrinsic::invariant_end: 4788 case Intrinsic::lifetime_end: 4789 // Discard region information. 4790 return 0; 4791 } 4792} 4793 4794void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 4795 bool isTailCall, 4796 MachineBasicBlock *LandingPad) { 4797 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4798 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4799 const Type *RetTy = FTy->getReturnType(); 4800 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4801 MCSymbol *BeginLabel = 0; 4802 4803 TargetLowering::ArgListTy Args; 4804 TargetLowering::ArgListEntry Entry; 4805 Args.reserve(CS.arg_size()); 4806 4807 // Check whether the function can return without sret-demotion. 4808 SmallVector<ISD::OutputArg, 4> Outs; 4809 SmallVector<uint64_t, 4> Offsets; 4810 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4811 Outs, TLI, &Offsets); 4812 4813 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4814 FTy->isVarArg(), Outs, FTy->getContext()); 4815 4816 SDValue DemoteStackSlot; 4817 int DemoteStackIdx = -100; 4818 4819 if (!CanLowerReturn) { 4820 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4821 FTy->getReturnType()); 4822 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4823 FTy->getReturnType()); 4824 MachineFunction &MF = DAG.getMachineFunction(); 4825 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4826 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4827 4828 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 4829 Entry.Node = DemoteStackSlot; 4830 Entry.Ty = StackSlotPtrType; 4831 Entry.isSExt = false; 4832 Entry.isZExt = false; 4833 Entry.isInReg = false; 4834 Entry.isSRet = true; 4835 Entry.isNest = false; 4836 Entry.isByVal = false; 4837 Entry.Alignment = Align; 4838 Args.push_back(Entry); 4839 RetTy = Type::getVoidTy(FTy->getContext()); 4840 } 4841 4842 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4843 i != e; ++i) { 4844 SDValue ArgNode = getValue(*i); 4845 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 4846 4847 unsigned attrInd = i - CS.arg_begin() + 1; 4848 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4849 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4850 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4851 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4852 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4853 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4854 Entry.Alignment = CS.getParamAlignment(attrInd); 4855 Args.push_back(Entry); 4856 } 4857 4858 if (LandingPad) { 4859 // Insert a label before the invoke call to mark the try range. This can be 4860 // used to detect deletion of the invoke via the MachineModuleInfo. 4861 BeginLabel = MMI.getContext().CreateTempSymbol(); 4862 4863 // For SjLj, keep track of which landing pads go with which invokes 4864 // so as to maintain the ordering of pads in the LSDA. 4865 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 4866 if (CallSiteIndex) { 4867 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4868 // Now that the call site is handled, stop tracking it. 4869 MMI.setCurrentCallSite(0); 4870 } 4871 4872 // Both PendingLoads and PendingExports must be flushed here; 4873 // this call might not return. 4874 (void)getRoot(); 4875 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4876 } 4877 4878 // Check if target-independent constraints permit a tail call here. 4879 // Target-dependent constraints are checked within TLI.LowerCallTo. 4880 if (isTailCall && 4881 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4882 isTailCall = false; 4883 4884 // If there's a possibility that fast-isel has already selected some amount 4885 // of the current basic block, don't emit a tail call. 4886 if (isTailCall && EnableFastISel) 4887 isTailCall = false; 4888 4889 std::pair<SDValue,SDValue> Result = 4890 TLI.LowerCallTo(getRoot(), RetTy, 4891 CS.paramHasAttr(0, Attribute::SExt), 4892 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4893 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4894 CS.getCallingConv(), 4895 isTailCall, 4896 !CS.getInstruction()->use_empty(), 4897 Callee, Args, DAG, getCurDebugLoc()); 4898 assert((isTailCall || Result.second.getNode()) && 4899 "Non-null chain expected with non-tail call!"); 4900 assert((Result.second.getNode() || !Result.first.getNode()) && 4901 "Null value expected with tail call!"); 4902 if (Result.first.getNode()) { 4903 setValue(CS.getInstruction(), Result.first); 4904 } else if (!CanLowerReturn && Result.second.getNode()) { 4905 // The instruction result is the result of loading from the 4906 // hidden sret parameter. 4907 SmallVector<EVT, 1> PVTs; 4908 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 4909 4910 ComputeValueVTs(TLI, PtrRetTy, PVTs); 4911 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 4912 EVT PtrVT = PVTs[0]; 4913 unsigned NumValues = Outs.size(); 4914 SmallVector<SDValue, 4> Values(NumValues); 4915 SmallVector<SDValue, 4> Chains(NumValues); 4916 4917 for (unsigned i = 0; i < NumValues; ++i) { 4918 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 4919 DemoteStackSlot, 4920 DAG.getConstant(Offsets[i], PtrVT)); 4921 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 4922 Add, 4923 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 4924 false, false, 1); 4925 Values[i] = L; 4926 Chains[i] = L.getValue(1); 4927 } 4928 4929 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 4930 MVT::Other, &Chains[0], NumValues); 4931 PendingLoads.push_back(Chain); 4932 4933 // Collect the legal value parts into potentially illegal values 4934 // that correspond to the original function's return values. 4935 SmallVector<EVT, 4> RetTys; 4936 RetTy = FTy->getReturnType(); 4937 ComputeValueVTs(TLI, RetTy, RetTys); 4938 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4939 SmallVector<SDValue, 4> ReturnValues; 4940 unsigned CurReg = 0; 4941 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4942 EVT VT = RetTys[I]; 4943 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 4944 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 4945 4946 SDValue ReturnValue = 4947 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 4948 RegisterVT, VT, AssertOp); 4949 ReturnValues.push_back(ReturnValue); 4950 CurReg += NumRegs; 4951 } 4952 4953 setValue(CS.getInstruction(), 4954 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 4955 DAG.getVTList(&RetTys[0], RetTys.size()), 4956 &ReturnValues[0], ReturnValues.size())); 4957 4958 } 4959 4960 // As a special case, a null chain means that a tail call has been emitted and 4961 // the DAG root is already updated. 4962 if (Result.second.getNode()) 4963 DAG.setRoot(Result.second); 4964 else 4965 HasTailCall = true; 4966 4967 if (LandingPad) { 4968 // Insert a label at the end of the invoke call to mark the try range. This 4969 // can be used to detect deletion of the invoke via the MachineModuleInfo. 4970 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 4971 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 4972 4973 // Inform MachineModuleInfo of range. 4974 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 4975 } 4976} 4977 4978/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 4979/// value is equal or not-equal to zero. 4980static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 4981 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 4982 UI != E; ++UI) { 4983 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 4984 if (IC->isEquality()) 4985 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 4986 if (C->isNullValue()) 4987 continue; 4988 // Unknown instruction. 4989 return false; 4990 } 4991 return true; 4992} 4993 4994static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 4995 const Type *LoadTy, 4996 SelectionDAGBuilder &Builder) { 4997 4998 // Check to see if this load can be trivially constant folded, e.g. if the 4999 // input is from a string literal. 5000 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5001 // Cast pointer to the type we really want to load. 5002 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5003 PointerType::getUnqual(LoadTy)); 5004 5005 if (const Constant *LoadCst = 5006 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5007 Builder.TD)) 5008 return Builder.getValue(LoadCst); 5009 } 5010 5011 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5012 // still constant memory, the input chain can be the entry node. 5013 SDValue Root; 5014 bool ConstantMemory = false; 5015 5016 // Do not serialize (non-volatile) loads of constant memory with anything. 5017 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5018 Root = Builder.DAG.getEntryNode(); 5019 ConstantMemory = true; 5020 } else { 5021 // Do not serialize non-volatile loads against each other. 5022 Root = Builder.DAG.getRoot(); 5023 } 5024 5025 SDValue Ptr = Builder.getValue(PtrVal); 5026 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5027 Ptr, MachinePointerInfo(PtrVal), 5028 false /*volatile*/, 5029 false /*nontemporal*/, 1 /* align=1 */); 5030 5031 if (!ConstantMemory) 5032 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5033 return LoadVal; 5034} 5035 5036 5037/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5038/// If so, return true and lower it, otherwise return false and it will be 5039/// lowered like a normal call. 5040bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5041 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5042 if (I.getNumArgOperands() != 3) 5043 return false; 5044 5045 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5046 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5047 !I.getArgOperand(2)->getType()->isIntegerTy() || 5048 !I.getType()->isIntegerTy()) 5049 return false; 5050 5051 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5052 5053 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5054 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5055 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5056 bool ActuallyDoIt = true; 5057 MVT LoadVT; 5058 const Type *LoadTy; 5059 switch (Size->getZExtValue()) { 5060 default: 5061 LoadVT = MVT::Other; 5062 LoadTy = 0; 5063 ActuallyDoIt = false; 5064 break; 5065 case 2: 5066 LoadVT = MVT::i16; 5067 LoadTy = Type::getInt16Ty(Size->getContext()); 5068 break; 5069 case 4: 5070 LoadVT = MVT::i32; 5071 LoadTy = Type::getInt32Ty(Size->getContext()); 5072 break; 5073 case 8: 5074 LoadVT = MVT::i64; 5075 LoadTy = Type::getInt64Ty(Size->getContext()); 5076 break; 5077 /* 5078 case 16: 5079 LoadVT = MVT::v4i32; 5080 LoadTy = Type::getInt32Ty(Size->getContext()); 5081 LoadTy = VectorType::get(LoadTy, 4); 5082 break; 5083 */ 5084 } 5085 5086 // This turns into unaligned loads. We only do this if the target natively 5087 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5088 // we'll only produce a small number of byte loads. 5089 5090 // Require that we can find a legal MVT, and only do this if the target 5091 // supports unaligned loads of that type. Expanding into byte loads would 5092 // bloat the code. 5093 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5094 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5095 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5096 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5097 ActuallyDoIt = false; 5098 } 5099 5100 if (ActuallyDoIt) { 5101 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5102 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5103 5104 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5105 ISD::SETNE); 5106 EVT CallVT = TLI.getValueType(I.getType(), true); 5107 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5108 return true; 5109 } 5110 } 5111 5112 5113 return false; 5114} 5115 5116 5117void SelectionDAGBuilder::visitCall(const CallInst &I) { 5118 // Handle inline assembly differently. 5119 if (isa<InlineAsm>(I.getCalledValue())) { 5120 visitInlineAsm(&I); 5121 return; 5122 } 5123 5124 // See if any floating point values are being passed to this function. This is 5125 // used to emit an undefined reference to fltused on Windows. 5126 const FunctionType *FT = 5127 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5128 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5129 if (FT->isVarArg() && 5130 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5131 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5132 const Type* T = I.getArgOperand(i)->getType(); 5133 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T); 5134 i != e; ++i) { 5135 if (!i->isFloatingPointTy()) continue; 5136 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5137 break; 5138 } 5139 } 5140 } 5141 5142 const char *RenameFn = 0; 5143 if (Function *F = I.getCalledFunction()) { 5144 if (F->isDeclaration()) { 5145 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5146 if (unsigned IID = II->getIntrinsicID(F)) { 5147 RenameFn = visitIntrinsicCall(I, IID); 5148 if (!RenameFn) 5149 return; 5150 } 5151 } 5152 if (unsigned IID = F->getIntrinsicID()) { 5153 RenameFn = visitIntrinsicCall(I, IID); 5154 if (!RenameFn) 5155 return; 5156 } 5157 } 5158 5159 // Check for well-known libc/libm calls. If the function is internal, it 5160 // can't be a library call. 5161 if (!F->hasLocalLinkage() && F->hasName()) { 5162 StringRef Name = F->getName(); 5163 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5164 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5165 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5166 I.getType() == I.getArgOperand(0)->getType() && 5167 I.getType() == I.getArgOperand(1)->getType()) { 5168 SDValue LHS = getValue(I.getArgOperand(0)); 5169 SDValue RHS = getValue(I.getArgOperand(1)); 5170 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5171 LHS.getValueType(), LHS, RHS)); 5172 return; 5173 } 5174 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5175 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5176 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5177 I.getType() == I.getArgOperand(0)->getType()) { 5178 SDValue Tmp = getValue(I.getArgOperand(0)); 5179 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5180 Tmp.getValueType(), Tmp)); 5181 return; 5182 } 5183 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5184 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5185 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5186 I.getType() == I.getArgOperand(0)->getType() && 5187 I.onlyReadsMemory()) { 5188 SDValue Tmp = getValue(I.getArgOperand(0)); 5189 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5190 Tmp.getValueType(), Tmp)); 5191 return; 5192 } 5193 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5194 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5195 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5196 I.getType() == I.getArgOperand(0)->getType() && 5197 I.onlyReadsMemory()) { 5198 SDValue Tmp = getValue(I.getArgOperand(0)); 5199 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5200 Tmp.getValueType(), Tmp)); 5201 return; 5202 } 5203 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5204 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5205 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5206 I.getType() == I.getArgOperand(0)->getType() && 5207 I.onlyReadsMemory()) { 5208 SDValue Tmp = getValue(I.getArgOperand(0)); 5209 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5210 Tmp.getValueType(), Tmp)); 5211 return; 5212 } 5213 } else if (Name == "memcmp") { 5214 if (visitMemCmpCall(I)) 5215 return; 5216 } 5217 } 5218 } 5219 5220 SDValue Callee; 5221 if (!RenameFn) 5222 Callee = getValue(I.getCalledValue()); 5223 else 5224 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5225 5226 // Check if we can potentially perform a tail call. More detailed checking is 5227 // be done within LowerCallTo, after more information about the call is known. 5228 LowerCallTo(&I, Callee, I.isTailCall()); 5229} 5230 5231namespace llvm { 5232 5233/// AsmOperandInfo - This contains information for each constraint that we are 5234/// lowering. 5235class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo : 5236 public TargetLowering::AsmOperandInfo { 5237public: 5238 /// CallOperand - If this is the result output operand or a clobber 5239 /// this is null, otherwise it is the incoming operand to the CallInst. 5240 /// This gets modified as the asm is processed. 5241 SDValue CallOperand; 5242 5243 /// AssignedRegs - If this is a register or register class operand, this 5244 /// contains the set of register corresponding to the operand. 5245 RegsForValue AssignedRegs; 5246 5247 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5248 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5249 } 5250 5251 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5252 /// busy in OutputRegs/InputRegs. 5253 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5254 std::set<unsigned> &OutputRegs, 5255 std::set<unsigned> &InputRegs, 5256 const TargetRegisterInfo &TRI) const { 5257 if (isOutReg) { 5258 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5259 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5260 } 5261 if (isInReg) { 5262 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5263 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5264 } 5265 } 5266 5267 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5268 /// corresponds to. If there is no Value* for this operand, it returns 5269 /// MVT::Other. 5270 EVT getCallOperandValEVT(LLVMContext &Context, 5271 const TargetLowering &TLI, 5272 const TargetData *TD) const { 5273 if (CallOperandVal == 0) return MVT::Other; 5274 5275 if (isa<BasicBlock>(CallOperandVal)) 5276 return TLI.getPointerTy(); 5277 5278 const llvm::Type *OpTy = CallOperandVal->getType(); 5279 5280 // If this is an indirect operand, the operand is a pointer to the 5281 // accessed type. 5282 if (isIndirect) { 5283 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5284 if (!PtrTy) 5285 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5286 OpTy = PtrTy->getElementType(); 5287 } 5288 5289 // If OpTy is not a single value, it may be a struct/union that we 5290 // can tile with integers. 5291 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5292 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5293 switch (BitSize) { 5294 default: break; 5295 case 1: 5296 case 8: 5297 case 16: 5298 case 32: 5299 case 64: 5300 case 128: 5301 OpTy = IntegerType::get(Context, BitSize); 5302 break; 5303 } 5304 } 5305 5306 return TLI.getValueType(OpTy, true); 5307 } 5308 5309private: 5310 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5311 /// specified set. 5312 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5313 const TargetRegisterInfo &TRI) { 5314 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5315 Regs.insert(Reg); 5316 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5317 for (; *Aliases; ++Aliases) 5318 Regs.insert(*Aliases); 5319 } 5320}; 5321 5322typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5323 5324} // end llvm namespace. 5325 5326/// isAllocatableRegister - If the specified register is safe to allocate, 5327/// i.e. it isn't a stack pointer or some other special register, return the 5328/// register class for the register. Otherwise, return null. 5329static const TargetRegisterClass * 5330isAllocatableRegister(unsigned Reg, MachineFunction &MF, 5331 const TargetLowering &TLI, 5332 const TargetRegisterInfo *TRI) { 5333 EVT FoundVT = MVT::Other; 5334 const TargetRegisterClass *FoundRC = 0; 5335 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 5336 E = TRI->regclass_end(); RCI != E; ++RCI) { 5337 EVT ThisVT = MVT::Other; 5338 5339 const TargetRegisterClass *RC = *RCI; 5340 // If none of the value types for this register class are valid, we 5341 // can't use it. For example, 64-bit reg classes on 32-bit targets. 5342 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 5343 I != E; ++I) { 5344 if (TLI.isTypeLegal(*I)) { 5345 // If we have already found this register in a different register class, 5346 // choose the one with the largest VT specified. For example, on 5347 // PowerPC, we favor f64 register classes over f32. 5348 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 5349 ThisVT = *I; 5350 break; 5351 } 5352 } 5353 } 5354 5355 if (ThisVT == MVT::Other) continue; 5356 5357 // NOTE: This isn't ideal. In particular, this might allocate the 5358 // frame pointer in functions that need it (due to them not being taken 5359 // out of allocation, because a variable sized allocation hasn't been seen 5360 // yet). This is a slight code pessimization, but should still work. 5361 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 5362 E = RC->allocation_order_end(MF); I != E; ++I) 5363 if (*I == Reg) { 5364 // We found a matching register class. Keep looking at others in case 5365 // we find one with larger registers that this physreg is also in. 5366 FoundRC = RC; 5367 FoundVT = ThisVT; 5368 break; 5369 } 5370 } 5371 return FoundRC; 5372} 5373 5374/// GetRegistersForValue - Assign registers (virtual or physical) for the 5375/// specified operand. We prefer to assign virtual registers, to allow the 5376/// register allocator to handle the assignment process. However, if the asm 5377/// uses features that we can't model on machineinstrs, we have SDISel do the 5378/// allocation. This produces generally horrible, but correct, code. 5379/// 5380/// OpInfo describes the operand. 5381/// Input and OutputRegs are the set of already allocated physical registers. 5382/// 5383void SelectionDAGBuilder:: 5384GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, 5385 std::set<unsigned> &OutputRegs, 5386 std::set<unsigned> &InputRegs) { 5387 LLVMContext &Context = FuncInfo.Fn->getContext(); 5388 5389 // Compute whether this value requires an input register, an output register, 5390 // or both. 5391 bool isOutReg = false; 5392 bool isInReg = false; 5393 switch (OpInfo.Type) { 5394 case InlineAsm::isOutput: 5395 isOutReg = true; 5396 5397 // If there is an input constraint that matches this, we need to reserve 5398 // the input register so no other inputs allocate to it. 5399 isInReg = OpInfo.hasMatchingInput(); 5400 break; 5401 case InlineAsm::isInput: 5402 isInReg = true; 5403 isOutReg = false; 5404 break; 5405 case InlineAsm::isClobber: 5406 isOutReg = true; 5407 isInReg = true; 5408 break; 5409 } 5410 5411 5412 MachineFunction &MF = DAG.getMachineFunction(); 5413 SmallVector<unsigned, 4> Regs; 5414 5415 // If this is a constraint for a single physreg, or a constraint for a 5416 // register class, find it. 5417 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5418 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5419 OpInfo.ConstraintVT); 5420 5421 unsigned NumRegs = 1; 5422 if (OpInfo.ConstraintVT != MVT::Other) { 5423 // If this is a FP input in an integer register (or visa versa) insert a bit 5424 // cast of the input value. More generally, handle any case where the input 5425 // value disagrees with the register class we plan to stick this in. 5426 if (OpInfo.Type == InlineAsm::isInput && 5427 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5428 // Try to convert to the first EVT that the reg class contains. If the 5429 // types are identical size, use a bitcast to convert (e.g. two differing 5430 // vector types). 5431 EVT RegVT = *PhysReg.second->vt_begin(); 5432 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5433 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 5434 RegVT, OpInfo.CallOperand); 5435 OpInfo.ConstraintVT = RegVT; 5436 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5437 // If the input is a FP value and we want it in FP registers, do a 5438 // bitcast to the corresponding integer type. This turns an f64 value 5439 // into i64, which can be passed with two i32 values on a 32-bit 5440 // machine. 5441 RegVT = EVT::getIntegerVT(Context, 5442 OpInfo.ConstraintVT.getSizeInBits()); 5443 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 5444 RegVT, OpInfo.CallOperand); 5445 OpInfo.ConstraintVT = RegVT; 5446 } 5447 } 5448 5449 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5450 } 5451 5452 EVT RegVT; 5453 EVT ValueVT = OpInfo.ConstraintVT; 5454 5455 // If this is a constraint for a specific physical register, like {r17}, 5456 // assign it now. 5457 if (unsigned AssignedReg = PhysReg.first) { 5458 const TargetRegisterClass *RC = PhysReg.second; 5459 if (OpInfo.ConstraintVT == MVT::Other) 5460 ValueVT = *RC->vt_begin(); 5461 5462 // Get the actual register value type. This is important, because the user 5463 // may have asked for (e.g.) the AX register in i32 type. We need to 5464 // remember that AX is actually i16 to get the right extension. 5465 RegVT = *RC->vt_begin(); 5466 5467 // This is a explicit reference to a physical register. 5468 Regs.push_back(AssignedReg); 5469 5470 // If this is an expanded reference, add the rest of the regs to Regs. 5471 if (NumRegs != 1) { 5472 TargetRegisterClass::iterator I = RC->begin(); 5473 for (; *I != AssignedReg; ++I) 5474 assert(I != RC->end() && "Didn't find reg!"); 5475 5476 // Already added the first reg. 5477 --NumRegs; ++I; 5478 for (; NumRegs; --NumRegs, ++I) { 5479 assert(I != RC->end() && "Ran out of registers to allocate!"); 5480 Regs.push_back(*I); 5481 } 5482 } 5483 5484 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5485 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5486 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5487 return; 5488 } 5489 5490 // Otherwise, if this was a reference to an LLVM register class, create vregs 5491 // for this reference. 5492 if (const TargetRegisterClass *RC = PhysReg.second) { 5493 RegVT = *RC->vt_begin(); 5494 if (OpInfo.ConstraintVT == MVT::Other) 5495 ValueVT = RegVT; 5496 5497 // Create the appropriate number of virtual registers. 5498 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5499 for (; NumRegs; --NumRegs) 5500 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5501 5502 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5503 return; 5504 } 5505 5506 // This is a reference to a register class that doesn't directly correspond 5507 // to an LLVM register class. Allocate NumRegs consecutive, available, 5508 // registers from the class. 5509 std::vector<unsigned> RegClassRegs 5510 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 5511 OpInfo.ConstraintVT); 5512 5513 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5514 unsigned NumAllocated = 0; 5515 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 5516 unsigned Reg = RegClassRegs[i]; 5517 // See if this register is available. 5518 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 5519 (isInReg && InputRegs.count(Reg))) { // Already used. 5520 // Make sure we find consecutive registers. 5521 NumAllocated = 0; 5522 continue; 5523 } 5524 5525 // Check to see if this register is allocatable (i.e. don't give out the 5526 // stack pointer). 5527 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); 5528 if (!RC) { // Couldn't allocate this register. 5529 // Reset NumAllocated to make sure we return consecutive registers. 5530 NumAllocated = 0; 5531 continue; 5532 } 5533 5534 // Okay, this register is good, we can use it. 5535 ++NumAllocated; 5536 5537 // If we allocated enough consecutive registers, succeed. 5538 if (NumAllocated == NumRegs) { 5539 unsigned RegStart = (i-NumAllocated)+1; 5540 unsigned RegEnd = i+1; 5541 // Mark all of the allocated registers used. 5542 for (unsigned i = RegStart; i != RegEnd; ++i) 5543 Regs.push_back(RegClassRegs[i]); 5544 5545 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 5546 OpInfo.ConstraintVT); 5547 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5548 return; 5549 } 5550 } 5551 5552 // Otherwise, we couldn't allocate enough registers for this. 5553} 5554 5555/// visitInlineAsm - Handle a call to an InlineAsm object. 5556/// 5557void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5558 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5559 5560 /// ConstraintOperands - Information about all of the constraints. 5561 SDISelAsmOperandInfoVector ConstraintOperands; 5562 5563 std::set<unsigned> OutputRegs, InputRegs; 5564 5565 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS); 5566 bool hasMemory = false; 5567 5568 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5569 unsigned ResNo = 0; // ResNo - The result number of the next output. 5570 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5571 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5572 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5573 5574 EVT OpVT = MVT::Other; 5575 5576 // Compute the value type for each operand. 5577 switch (OpInfo.Type) { 5578 case InlineAsm::isOutput: 5579 // Indirect outputs just consume an argument. 5580 if (OpInfo.isIndirect) { 5581 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5582 break; 5583 } 5584 5585 // The return value of the call is this value. As such, there is no 5586 // corresponding argument. 5587 assert(!CS.getType()->isVoidTy() && 5588 "Bad inline asm!"); 5589 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5590 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5591 } else { 5592 assert(ResNo == 0 && "Asm only has one result!"); 5593 OpVT = TLI.getValueType(CS.getType()); 5594 } 5595 ++ResNo; 5596 break; 5597 case InlineAsm::isInput: 5598 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5599 break; 5600 case InlineAsm::isClobber: 5601 // Nothing to do. 5602 break; 5603 } 5604 5605 // If this is an input or an indirect output, process the call argument. 5606 // BasicBlocks are labels, currently appearing only in asm's. 5607 if (OpInfo.CallOperandVal) { 5608 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5609 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5610 } else { 5611 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5612 } 5613 5614 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5615 } 5616 5617 OpInfo.ConstraintVT = OpVT; 5618 5619 // Indirect operand accesses access memory. 5620 if (OpInfo.isIndirect) 5621 hasMemory = true; 5622 else { 5623 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5624 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]); 5625 if (CType == TargetLowering::C_Memory) { 5626 hasMemory = true; 5627 break; 5628 } 5629 } 5630 } 5631 } 5632 5633 SDValue Chain, Flag; 5634 5635 // We won't need to flush pending loads if this asm doesn't touch 5636 // memory and is nonvolatile. 5637 if (hasMemory || IA->hasSideEffects()) 5638 Chain = getRoot(); 5639 else 5640 Chain = DAG.getRoot(); 5641 5642 // Second pass over the constraints: compute which constraint option to use 5643 // and assign registers to constraints that want a specific physreg. 5644 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5645 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5646 5647 // If this is an output operand with a matching input operand, look up the 5648 // matching input. If their types mismatch, e.g. one is an integer, the 5649 // other is floating point, or their sizes are different, flag it as an 5650 // error. 5651 if (OpInfo.hasMatchingInput()) { 5652 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5653 5654 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5655 if ((OpInfo.ConstraintVT.isInteger() != 5656 Input.ConstraintVT.isInteger()) || 5657 (OpInfo.ConstraintVT.getSizeInBits() != 5658 Input.ConstraintVT.getSizeInBits())) { 5659 report_fatal_error("Unsupported asm: input constraint" 5660 " with a matching output constraint of" 5661 " incompatible type!"); 5662 } 5663 Input.ConstraintVT = OpInfo.ConstraintVT; 5664 } 5665 } 5666 5667 // Compute the constraint code and ConstraintType to use. 5668 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5669 5670 // If this is a memory input, and if the operand is not indirect, do what we 5671 // need to to provide an address for the memory input. 5672 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5673 !OpInfo.isIndirect) { 5674 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && 5675 "Can only indirectify direct input operands!"); 5676 5677 // Memory operands really want the address of the value. If we don't have 5678 // an indirect input, put it in the constpool if we can, otherwise spill 5679 // it to a stack slot. 5680 5681 // If the operand is a float, integer, or vector constant, spill to a 5682 // constant pool entry to get its address. 5683 const Value *OpVal = OpInfo.CallOperandVal; 5684 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5685 isa<ConstantVector>(OpVal)) { 5686 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5687 TLI.getPointerTy()); 5688 } else { 5689 // Otherwise, create a stack slot and emit a store to it before the 5690 // asm. 5691 const Type *Ty = OpVal->getType(); 5692 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5693 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5694 MachineFunction &MF = DAG.getMachineFunction(); 5695 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5696 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5697 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5698 OpInfo.CallOperand, StackSlot, 5699 MachinePointerInfo::getFixedStack(SSFI), 5700 false, false, 0); 5701 OpInfo.CallOperand = StackSlot; 5702 } 5703 5704 // There is no longer a Value* corresponding to this operand. 5705 OpInfo.CallOperandVal = 0; 5706 5707 // It is now an indirect operand. 5708 OpInfo.isIndirect = true; 5709 } 5710 5711 // If this constraint is for a specific register, allocate it before 5712 // anything else. 5713 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5714 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5715 } 5716 5717 // Second pass - Loop over all of the operands, assigning virtual or physregs 5718 // to register class operands. 5719 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5720 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5721 5722 // C_Register operands have already been allocated, Other/Memory don't need 5723 // to be. 5724 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5725 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5726 } 5727 5728 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5729 std::vector<SDValue> AsmNodeOperands; 5730 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5731 AsmNodeOperands.push_back( 5732 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5733 TLI.getPointerTy())); 5734 5735 // If we have a !srcloc metadata node associated with it, we want to attach 5736 // this to the ultimately generated inline asm machineinstr. To do this, we 5737 // pass in the third operand as this (potentially null) inline asm MDNode. 5738 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5739 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5740 5741 // Remember the HasSideEffect and AlignStack bits as operand 3. 5742 unsigned ExtraInfo = 0; 5743 if (IA->hasSideEffects()) 5744 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 5745 if (IA->isAlignStack()) 5746 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 5747 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 5748 TLI.getPointerTy())); 5749 5750 // Loop over all of the inputs, copying the operand values into the 5751 // appropriate registers and processing the output regs. 5752 RegsForValue RetValRegs; 5753 5754 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5755 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5756 5757 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5758 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5759 5760 switch (OpInfo.Type) { 5761 case InlineAsm::isOutput: { 5762 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5763 OpInfo.ConstraintType != TargetLowering::C_Register) { 5764 // Memory output, or 'other' output (e.g. 'X' constraint). 5765 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5766 5767 // Add information to the INLINEASM node to know about this output. 5768 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5769 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5770 TLI.getPointerTy())); 5771 AsmNodeOperands.push_back(OpInfo.CallOperand); 5772 break; 5773 } 5774 5775 // Otherwise, this is a register or register class output. 5776 5777 // Copy the output from the appropriate register. Find a register that 5778 // we can use. 5779 if (OpInfo.AssignedRegs.Regs.empty()) 5780 report_fatal_error("Couldn't allocate output reg for constraint '" + 5781 Twine(OpInfo.ConstraintCode) + "'!"); 5782 5783 // If this is an indirect operand, store through the pointer after the 5784 // asm. 5785 if (OpInfo.isIndirect) { 5786 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5787 OpInfo.CallOperandVal)); 5788 } else { 5789 // This is the result value of the call. 5790 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5791 // Concatenate this output onto the outputs list. 5792 RetValRegs.append(OpInfo.AssignedRegs); 5793 } 5794 5795 // Add information to the INLINEASM node to know that this register is 5796 // set. 5797 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5798 InlineAsm::Kind_RegDefEarlyClobber : 5799 InlineAsm::Kind_RegDef, 5800 false, 5801 0, 5802 DAG, 5803 AsmNodeOperands); 5804 break; 5805 } 5806 case InlineAsm::isInput: { 5807 SDValue InOperandVal = OpInfo.CallOperand; 5808 5809 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5810 // If this is required to match an output register we have already set, 5811 // just use its register. 5812 unsigned OperandNo = OpInfo.getMatchedOperand(); 5813 5814 // Scan until we find the definition we already emitted of this operand. 5815 // When we find it, create a RegsForValue operand. 5816 unsigned CurOp = InlineAsm::Op_FirstOperand; 5817 for (; OperandNo; --OperandNo) { 5818 // Advance to the next operand. 5819 unsigned OpFlag = 5820 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5821 assert((InlineAsm::isRegDefKind(OpFlag) || 5822 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5823 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5824 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5825 } 5826 5827 unsigned OpFlag = 5828 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5829 if (InlineAsm::isRegDefKind(OpFlag) || 5830 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5831 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5832 if (OpInfo.isIndirect) { 5833 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5834 LLVMContext &Ctx = *DAG.getContext(); 5835 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5836 " don't know how to handle tied " 5837 "indirect register inputs"); 5838 } 5839 5840 RegsForValue MatchedRegs; 5841 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5842 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5843 MatchedRegs.RegVTs.push_back(RegVT); 5844 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5845 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5846 i != e; ++i) 5847 MatchedRegs.Regs.push_back 5848 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5849 5850 // Use the produced MatchedRegs object to 5851 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5852 Chain, &Flag); 5853 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 5854 true, OpInfo.getMatchedOperand(), 5855 DAG, AsmNodeOperands); 5856 break; 5857 } 5858 5859 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 5860 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 5861 "Unexpected number of operands"); 5862 // Add information to the INLINEASM node to know about this input. 5863 // See InlineAsm.h isUseOperandTiedToDef. 5864 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 5865 OpInfo.getMatchedOperand()); 5866 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5867 TLI.getPointerTy())); 5868 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5869 break; 5870 } 5871 5872 // Treat indirect 'X' constraint as memory. 5873 if (OpInfo.ConstraintType == TargetLowering::C_Other && 5874 OpInfo.isIndirect) 5875 OpInfo.ConstraintType = TargetLowering::C_Memory; 5876 5877 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5878 std::vector<SDValue> Ops; 5879 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 5880 Ops, DAG); 5881 if (Ops.empty()) 5882 report_fatal_error("Invalid operand for inline asm constraint '" + 5883 Twine(OpInfo.ConstraintCode) + "'!"); 5884 5885 // Add information to the INLINEASM node to know about this input. 5886 unsigned ResOpType = 5887 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 5888 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5889 TLI.getPointerTy())); 5890 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5891 break; 5892 } 5893 5894 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5895 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5896 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5897 "Memory operands expect pointer values"); 5898 5899 // Add information to the INLINEASM node to know about this input. 5900 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5901 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5902 TLI.getPointerTy())); 5903 AsmNodeOperands.push_back(InOperandVal); 5904 break; 5905 } 5906 5907 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5908 OpInfo.ConstraintType == TargetLowering::C_Register) && 5909 "Unknown constraint type!"); 5910 assert(!OpInfo.isIndirect && 5911 "Don't know how to handle indirect register inputs yet!"); 5912 5913 // Copy the input into the appropriate registers. 5914 if (OpInfo.AssignedRegs.Regs.empty() || 5915 !OpInfo.AssignedRegs.areValueTypesLegal(TLI)) 5916 report_fatal_error("Couldn't allocate input reg for constraint '" + 5917 Twine(OpInfo.ConstraintCode) + "'!"); 5918 5919 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5920 Chain, &Flag); 5921 5922 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 5923 DAG, AsmNodeOperands); 5924 break; 5925 } 5926 case InlineAsm::isClobber: { 5927 // Add the clobbered value to the operand list, so that the register 5928 // allocator is aware that the physreg got clobbered. 5929 if (!OpInfo.AssignedRegs.Regs.empty()) 5930 OpInfo.AssignedRegs.AddInlineAsmOperands( 5931 InlineAsm::Kind_RegDefEarlyClobber, 5932 false, 0, DAG, 5933 AsmNodeOperands); 5934 break; 5935 } 5936 } 5937 } 5938 5939 // Finish up input operands. Set the input chain and add the flag last. 5940 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 5941 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5942 5943 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5944 DAG.getVTList(MVT::Other, MVT::Glue), 5945 &AsmNodeOperands[0], AsmNodeOperands.size()); 5946 Flag = Chain.getValue(1); 5947 5948 // If this asm returns a register value, copy the result from that register 5949 // and set it as the value of the call. 5950 if (!RetValRegs.Regs.empty()) { 5951 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5952 Chain, &Flag); 5953 5954 // FIXME: Why don't we do this for inline asms with MRVs? 5955 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5956 EVT ResultType = TLI.getValueType(CS.getType()); 5957 5958 // If any of the results of the inline asm is a vector, it may have the 5959 // wrong width/num elts. This can happen for register classes that can 5960 // contain multiple different value types. The preg or vreg allocated may 5961 // not have the same VT as was expected. Convert it to the right type 5962 // with bit_convert. 5963 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5964 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 5965 ResultType, Val); 5966 5967 } else if (ResultType != Val.getValueType() && 5968 ResultType.isInteger() && Val.getValueType().isInteger()) { 5969 // If a result value was tied to an input value, the computed result may 5970 // have a wider width than the expected result. Extract the relevant 5971 // portion. 5972 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 5973 } 5974 5975 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 5976 } 5977 5978 setValue(CS.getInstruction(), Val); 5979 // Don't need to use this as a chain in this case. 5980 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 5981 return; 5982 } 5983 5984 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 5985 5986 // Process indirect outputs, first output all of the flagged copies out of 5987 // physregs. 5988 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 5989 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 5990 const Value *Ptr = IndirectStoresToEmit[i].second; 5991 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5992 Chain, &Flag); 5993 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 5994 } 5995 5996 // Emit the non-flagged stores from the physregs. 5997 SmallVector<SDValue, 8> OutChains; 5998 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 5999 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6000 StoresToEmit[i].first, 6001 getValue(StoresToEmit[i].second), 6002 MachinePointerInfo(StoresToEmit[i].second), 6003 false, false, 0); 6004 OutChains.push_back(Val); 6005 } 6006 6007 if (!OutChains.empty()) 6008 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6009 &OutChains[0], OutChains.size()); 6010 6011 DAG.setRoot(Chain); 6012} 6013 6014void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6015 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6016 MVT::Other, getRoot(), 6017 getValue(I.getArgOperand(0)), 6018 DAG.getSrcValue(I.getArgOperand(0)))); 6019} 6020 6021void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6022 const TargetData &TD = *TLI.getTargetData(); 6023 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6024 getRoot(), getValue(I.getOperand(0)), 6025 DAG.getSrcValue(I.getOperand(0)), 6026 TD.getABITypeAlignment(I.getType())); 6027 setValue(&I, V); 6028 DAG.setRoot(V.getValue(1)); 6029} 6030 6031void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6032 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6033 MVT::Other, getRoot(), 6034 getValue(I.getArgOperand(0)), 6035 DAG.getSrcValue(I.getArgOperand(0)))); 6036} 6037 6038void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6039 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6040 MVT::Other, getRoot(), 6041 getValue(I.getArgOperand(0)), 6042 getValue(I.getArgOperand(1)), 6043 DAG.getSrcValue(I.getArgOperand(0)), 6044 DAG.getSrcValue(I.getArgOperand(1)))); 6045} 6046 6047/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6048/// implementation, which just calls LowerCall. 6049/// FIXME: When all targets are 6050/// migrated to using LowerCall, this hook should be integrated into SDISel. 6051std::pair<SDValue, SDValue> 6052TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 6053 bool RetSExt, bool RetZExt, bool isVarArg, 6054 bool isInreg, unsigned NumFixedArgs, 6055 CallingConv::ID CallConv, bool isTailCall, 6056 bool isReturnValueUsed, 6057 SDValue Callee, 6058 ArgListTy &Args, SelectionDAG &DAG, 6059 DebugLoc dl) const { 6060 // Handle all of the outgoing arguments. 6061 SmallVector<ISD::OutputArg, 32> Outs; 6062 SmallVector<SDValue, 32> OutVals; 6063 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6064 SmallVector<EVT, 4> ValueVTs; 6065 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6066 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6067 Value != NumValues; ++Value) { 6068 EVT VT = ValueVTs[Value]; 6069 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6070 SDValue Op = SDValue(Args[i].Node.getNode(), 6071 Args[i].Node.getResNo() + Value); 6072 ISD::ArgFlagsTy Flags; 6073 unsigned OriginalAlignment = 6074 getTargetData()->getABITypeAlignment(ArgTy); 6075 6076 if (Args[i].isZExt) 6077 Flags.setZExt(); 6078 if (Args[i].isSExt) 6079 Flags.setSExt(); 6080 if (Args[i].isInReg) 6081 Flags.setInReg(); 6082 if (Args[i].isSRet) 6083 Flags.setSRet(); 6084 if (Args[i].isByVal) { 6085 Flags.setByVal(); 6086 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 6087 const Type *ElementTy = Ty->getElementType(); 6088 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 6089 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy); 6090 // For ByVal, alignment should come from FE. BE will guess if this 6091 // info is not there but there are cases it cannot get right. 6092 if (Args[i].Alignment) 6093 FrameAlign = Args[i].Alignment; 6094 Flags.setByValAlign(FrameAlign); 6095 Flags.setByValSize(FrameSize); 6096 } 6097 if (Args[i].isNest) 6098 Flags.setNest(); 6099 Flags.setOrigAlign(OriginalAlignment); 6100 6101 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6102 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6103 SmallVector<SDValue, 4> Parts(NumParts); 6104 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6105 6106 if (Args[i].isSExt) 6107 ExtendKind = ISD::SIGN_EXTEND; 6108 else if (Args[i].isZExt) 6109 ExtendKind = ISD::ZERO_EXTEND; 6110 6111 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6112 PartVT, ExtendKind); 6113 6114 for (unsigned j = 0; j != NumParts; ++j) { 6115 // if it isn't first piece, alignment must be 1 6116 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6117 i < NumFixedArgs); 6118 if (NumParts > 1 && j == 0) 6119 MyFlags.Flags.setSplit(); 6120 else if (j != 0) 6121 MyFlags.Flags.setOrigAlign(1); 6122 6123 Outs.push_back(MyFlags); 6124 OutVals.push_back(Parts[j]); 6125 } 6126 } 6127 } 6128 6129 // Handle the incoming return values from the call. 6130 SmallVector<ISD::InputArg, 32> Ins; 6131 SmallVector<EVT, 4> RetTys; 6132 ComputeValueVTs(*this, RetTy, RetTys); 6133 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6134 EVT VT = RetTys[I]; 6135 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6136 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6137 for (unsigned i = 0; i != NumRegs; ++i) { 6138 ISD::InputArg MyFlags; 6139 MyFlags.VT = RegisterVT.getSimpleVT(); 6140 MyFlags.Used = isReturnValueUsed; 6141 if (RetSExt) 6142 MyFlags.Flags.setSExt(); 6143 if (RetZExt) 6144 MyFlags.Flags.setZExt(); 6145 if (isInreg) 6146 MyFlags.Flags.setInReg(); 6147 Ins.push_back(MyFlags); 6148 } 6149 } 6150 6151 SmallVector<SDValue, 4> InVals; 6152 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6153 Outs, OutVals, Ins, dl, DAG, InVals); 6154 6155 // Verify that the target's LowerCall behaved as expected. 6156 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6157 "LowerCall didn't return a valid chain!"); 6158 assert((!isTailCall || InVals.empty()) && 6159 "LowerCall emitted a return value for a tail call!"); 6160 assert((isTailCall || InVals.size() == Ins.size()) && 6161 "LowerCall didn't emit the correct number of values!"); 6162 6163 // For a tail call, the return value is merely live-out and there aren't 6164 // any nodes in the DAG representing it. Return a special value to 6165 // indicate that a tail call has been emitted and no more Instructions 6166 // should be processed in the current block. 6167 if (isTailCall) { 6168 DAG.setRoot(Chain); 6169 return std::make_pair(SDValue(), SDValue()); 6170 } 6171 6172 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6173 assert(InVals[i].getNode() && 6174 "LowerCall emitted a null value!"); 6175 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6176 "LowerCall emitted a value with the wrong type!"); 6177 }); 6178 6179 // Collect the legal value parts into potentially illegal values 6180 // that correspond to the original function's return values. 6181 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6182 if (RetSExt) 6183 AssertOp = ISD::AssertSext; 6184 else if (RetZExt) 6185 AssertOp = ISD::AssertZext; 6186 SmallVector<SDValue, 4> ReturnValues; 6187 unsigned CurReg = 0; 6188 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6189 EVT VT = RetTys[I]; 6190 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6191 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6192 6193 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6194 NumRegs, RegisterVT, VT, 6195 AssertOp)); 6196 CurReg += NumRegs; 6197 } 6198 6199 // For a function returning void, there is no return value. We can't create 6200 // such a node, so we just return a null return value in that case. In 6201 // that case, nothing will actualy look at the value. 6202 if (ReturnValues.empty()) 6203 return std::make_pair(SDValue(), Chain); 6204 6205 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6206 DAG.getVTList(&RetTys[0], RetTys.size()), 6207 &ReturnValues[0], ReturnValues.size()); 6208 return std::make_pair(Res, Chain); 6209} 6210 6211void TargetLowering::LowerOperationWrapper(SDNode *N, 6212 SmallVectorImpl<SDValue> &Results, 6213 SelectionDAG &DAG) const { 6214 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6215 if (Res.getNode()) 6216 Results.push_back(Res); 6217} 6218 6219SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6220 llvm_unreachable("LowerOperation not implemented for this target!"); 6221 return SDValue(); 6222} 6223 6224void 6225SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6226 SDValue Op = getNonRegisterValue(V); 6227 assert((Op.getOpcode() != ISD::CopyFromReg || 6228 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6229 "Copy from a reg to the same reg!"); 6230 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6231 6232 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6233 SDValue Chain = DAG.getEntryNode(); 6234 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6235 PendingExports.push_back(Chain); 6236} 6237 6238#include "llvm/CodeGen/SelectionDAGISel.h" 6239 6240void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6241 // If this is the entry block, emit arguments. 6242 const Function &F = *LLVMBB->getParent(); 6243 SelectionDAG &DAG = SDB->DAG; 6244 DebugLoc dl = SDB->getCurDebugLoc(); 6245 const TargetData *TD = TLI.getTargetData(); 6246 SmallVector<ISD::InputArg, 16> Ins; 6247 6248 // Check whether the function can return without sret-demotion. 6249 SmallVector<ISD::OutputArg, 4> Outs; 6250 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6251 Outs, TLI); 6252 6253 if (!FuncInfo->CanLowerReturn) { 6254 // Put in an sret pointer parameter before all the other parameters. 6255 SmallVector<EVT, 1> ValueVTs; 6256 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6257 6258 // NOTE: Assuming that a pointer will never break down to more than one VT 6259 // or one register. 6260 ISD::ArgFlagsTy Flags; 6261 Flags.setSRet(); 6262 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6263 ISD::InputArg RetArg(Flags, RegisterVT, true); 6264 Ins.push_back(RetArg); 6265 } 6266 6267 // Set up the incoming argument description vector. 6268 unsigned Idx = 1; 6269 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6270 I != E; ++I, ++Idx) { 6271 SmallVector<EVT, 4> ValueVTs; 6272 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6273 bool isArgValueUsed = !I->use_empty(); 6274 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6275 Value != NumValues; ++Value) { 6276 EVT VT = ValueVTs[Value]; 6277 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6278 ISD::ArgFlagsTy Flags; 6279 unsigned OriginalAlignment = 6280 TD->getABITypeAlignment(ArgTy); 6281 6282 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6283 Flags.setZExt(); 6284 if (F.paramHasAttr(Idx, Attribute::SExt)) 6285 Flags.setSExt(); 6286 if (F.paramHasAttr(Idx, Attribute::InReg)) 6287 Flags.setInReg(); 6288 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6289 Flags.setSRet(); 6290 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6291 Flags.setByVal(); 6292 const PointerType *Ty = cast<PointerType>(I->getType()); 6293 const Type *ElementTy = Ty->getElementType(); 6294 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6295 unsigned FrameSize = TD->getTypeAllocSize(ElementTy); 6296 // For ByVal, alignment should be passed from FE. BE will guess if 6297 // this info is not there but there are cases it cannot get right. 6298 if (F.getParamAlignment(Idx)) 6299 FrameAlign = F.getParamAlignment(Idx); 6300 Flags.setByValAlign(FrameAlign); 6301 Flags.setByValSize(FrameSize); 6302 } 6303 if (F.paramHasAttr(Idx, Attribute::Nest)) 6304 Flags.setNest(); 6305 Flags.setOrigAlign(OriginalAlignment); 6306 6307 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6308 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6309 for (unsigned i = 0; i != NumRegs; ++i) { 6310 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6311 if (NumRegs > 1 && i == 0) 6312 MyFlags.Flags.setSplit(); 6313 // if it isn't first piece, alignment must be 1 6314 else if (i > 0) 6315 MyFlags.Flags.setOrigAlign(1); 6316 Ins.push_back(MyFlags); 6317 } 6318 } 6319 } 6320 6321 // Call the target to set up the argument values. 6322 SmallVector<SDValue, 8> InVals; 6323 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6324 F.isVarArg(), Ins, 6325 dl, DAG, InVals); 6326 6327 // Verify that the target's LowerFormalArguments behaved as expected. 6328 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6329 "LowerFormalArguments didn't return a valid chain!"); 6330 assert(InVals.size() == Ins.size() && 6331 "LowerFormalArguments didn't emit the correct number of values!"); 6332 DEBUG({ 6333 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6334 assert(InVals[i].getNode() && 6335 "LowerFormalArguments emitted a null value!"); 6336 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6337 "LowerFormalArguments emitted a value with the wrong type!"); 6338 } 6339 }); 6340 6341 // Update the DAG with the new chain value resulting from argument lowering. 6342 DAG.setRoot(NewRoot); 6343 6344 // Set up the argument values. 6345 unsigned i = 0; 6346 Idx = 1; 6347 if (!FuncInfo->CanLowerReturn) { 6348 // Create a virtual register for the sret pointer, and put in a copy 6349 // from the sret argument into it. 6350 SmallVector<EVT, 1> ValueVTs; 6351 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6352 EVT VT = ValueVTs[0]; 6353 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6354 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6355 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6356 RegVT, VT, AssertOp); 6357 6358 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6359 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6360 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6361 FuncInfo->DemoteRegister = SRetReg; 6362 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6363 SRetReg, ArgValue); 6364 DAG.setRoot(NewRoot); 6365 6366 // i indexes lowered arguments. Bump it past the hidden sret argument. 6367 // Idx indexes LLVM arguments. Don't touch it. 6368 ++i; 6369 } 6370 6371 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6372 ++I, ++Idx) { 6373 SmallVector<SDValue, 4> ArgValues; 6374 SmallVector<EVT, 4> ValueVTs; 6375 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6376 unsigned NumValues = ValueVTs.size(); 6377 6378 // If this argument is unused then remember its value. It is used to generate 6379 // debugging information. 6380 if (I->use_empty() && NumValues) 6381 SDB->setUnusedArgValue(I, InVals[i]); 6382 6383 for (unsigned Value = 0; Value != NumValues; ++Value) { 6384 EVT VT = ValueVTs[Value]; 6385 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6386 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6387 6388 if (!I->use_empty()) { 6389 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6390 if (F.paramHasAttr(Idx, Attribute::SExt)) 6391 AssertOp = ISD::AssertSext; 6392 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6393 AssertOp = ISD::AssertZext; 6394 6395 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6396 NumParts, PartVT, VT, 6397 AssertOp)); 6398 } 6399 6400 i += NumParts; 6401 } 6402 6403 // Note down frame index for byval arguments. 6404 if (I->hasByValAttr() && !ArgValues.empty()) 6405 if (FrameIndexSDNode *FI = 6406 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6407 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6408 6409 if (!I->use_empty()) { 6410 SDValue Res; 6411 if (!ArgValues.empty()) 6412 Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6413 SDB->getCurDebugLoc()); 6414 SDB->setValue(I, Res); 6415 6416 // If this argument is live outside of the entry block, insert a copy from 6417 // whereever we got it to the vreg that other BB's will reference it as. 6418 SDB->CopyToExportRegsIfNeeded(I); 6419 } 6420 } 6421 6422 assert(i == InVals.size() && "Argument register count mismatch!"); 6423 6424 // Finally, if the target has anything special to do, allow it to do so. 6425 // FIXME: this should insert code into the DAG! 6426 EmitFunctionEntryCode(); 6427} 6428 6429/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6430/// ensure constants are generated when needed. Remember the virtual registers 6431/// that need to be added to the Machine PHI nodes as input. We cannot just 6432/// directly add them, because expansion might result in multiple MBB's for one 6433/// BB. As such, the start of the BB might correspond to a different MBB than 6434/// the end. 6435/// 6436void 6437SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6438 const TerminatorInst *TI = LLVMBB->getTerminator(); 6439 6440 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6441 6442 // Check successor nodes' PHI nodes that expect a constant to be available 6443 // from this block. 6444 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6445 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6446 if (!isa<PHINode>(SuccBB->begin())) continue; 6447 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6448 6449 // If this terminator has multiple identical successors (common for 6450 // switches), only handle each succ once. 6451 if (!SuccsHandled.insert(SuccMBB)) continue; 6452 6453 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6454 6455 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6456 // nodes and Machine PHI nodes, but the incoming operands have not been 6457 // emitted yet. 6458 for (BasicBlock::const_iterator I = SuccBB->begin(); 6459 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6460 // Ignore dead phi's. 6461 if (PN->use_empty()) continue; 6462 6463 unsigned Reg; 6464 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6465 6466 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6467 unsigned &RegOut = ConstantsOut[C]; 6468 if (RegOut == 0) { 6469 RegOut = FuncInfo.CreateRegs(C->getType()); 6470 CopyValueToVirtualRegister(C, RegOut); 6471 } 6472 Reg = RegOut; 6473 } else { 6474 DenseMap<const Value *, unsigned>::iterator I = 6475 FuncInfo.ValueMap.find(PHIOp); 6476 if (I != FuncInfo.ValueMap.end()) 6477 Reg = I->second; 6478 else { 6479 assert(isa<AllocaInst>(PHIOp) && 6480 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6481 "Didn't codegen value into a register!??"); 6482 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6483 CopyValueToVirtualRegister(PHIOp, Reg); 6484 } 6485 } 6486 6487 // Remember that this register needs to added to the machine PHI node as 6488 // the input for this MBB. 6489 SmallVector<EVT, 4> ValueVTs; 6490 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6491 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6492 EVT VT = ValueVTs[vti]; 6493 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6494 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6495 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6496 Reg += NumRegisters; 6497 } 6498 } 6499 } 6500 ConstantsOut.clear(); 6501} 6502