SelectionDAGBuilder.cpp revision fd9760502d0fc87ac49dac834660a657f6b78370
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/ADT/BitVector.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/Module.h" 32#include "llvm/CodeGen/FastISel.h" 33#include "llvm/CodeGen/GCStrategy.h" 34#include "llvm/CodeGen/GCMetadata.h" 35#include "llvm/CodeGen/MachineFunction.h" 36#include "llvm/CodeGen/MachineFrameInfo.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineJumpTableInfo.h" 39#include "llvm/CodeGen/MachineModuleInfo.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/PseudoSourceValue.h" 42#include "llvm/CodeGen/SelectionDAG.h" 43#include "llvm/CodeGen/DwarfWriter.h" 44#include "llvm/Analysis/DebugInfo.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameInfo.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetIntrinsicInfo.h" 50#include "llvm/Target/TargetLowering.h" 51#include "llvm/Target/TargetOptions.h" 52#include "llvm/Support/Compiler.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72namespace { 73 /// RegsForValue - This struct represents the registers (physical or virtual) 74 /// that a particular set of values is assigned, and the type information 75 /// about the value. The most common situation is to represent one value at a 76 /// time, but struct or array values are handled element-wise as multiple 77 /// values. The splitting of aggregates is performed recursively, so that we 78 /// never have aggregate-typed registers. The values at this point do not 79 /// necessarily have legal types, so each value may require one or more 80 /// registers of some legal type. 81 /// 82 struct RegsForValue { 83 /// TLI - The TargetLowering object. 84 /// 85 const TargetLowering *TLI; 86 87 /// ValueVTs - The value types of the values, which may not be legal, and 88 /// may need be promoted or synthesized from one or more registers. 89 /// 90 SmallVector<EVT, 4> ValueVTs; 91 92 /// RegVTs - The value types of the registers. This is the same size as 93 /// ValueVTs and it records, for each value, what the type of the assigned 94 /// register or registers are. (Individual values are never synthesized 95 /// from more than one type of register.) 96 /// 97 /// With virtual registers, the contents of RegVTs is redundant with TLI's 98 /// getRegisterType member function, however when with physical registers 99 /// it is necessary to have a separate record of the types. 100 /// 101 SmallVector<EVT, 4> RegVTs; 102 103 /// Regs - This list holds the registers assigned to the values. 104 /// Each legal or promoted value requires one register, and each 105 /// expanded value requires multiple registers. 106 /// 107 SmallVector<unsigned, 4> Regs; 108 109 RegsForValue() : TLI(0) {} 110 111 RegsForValue(const TargetLowering &tli, 112 const SmallVector<unsigned, 4> ®s, 113 EVT regvt, EVT valuevt) 114 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 115 RegsForValue(const TargetLowering &tli, 116 const SmallVector<unsigned, 4> ®s, 117 const SmallVector<EVT, 4> ®vts, 118 const SmallVector<EVT, 4> &valuevts) 119 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {} 120 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 121 unsigned Reg, const Type *Ty) : TLI(&tli) { 122 ComputeValueVTs(tli, Ty, ValueVTs); 123 124 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 125 EVT ValueVT = ValueVTs[Value]; 126 unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT); 127 EVT RegisterVT = TLI->getRegisterType(Context, ValueVT); 128 for (unsigned i = 0; i != NumRegs; ++i) 129 Regs.push_back(Reg + i); 130 RegVTs.push_back(RegisterVT); 131 Reg += NumRegs; 132 } 133 } 134 135 /// areValueTypesLegal - Return true if types of all the values are legal. 136 bool areValueTypesLegal() { 137 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 138 EVT RegisterVT = RegVTs[Value]; 139 if (!TLI->isTypeLegal(RegisterVT)) 140 return false; 141 } 142 return true; 143 } 144 145 146 /// append - Add the specified values to this one. 147 void append(const RegsForValue &RHS) { 148 TLI = RHS.TLI; 149 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 150 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 151 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 152 } 153 154 155 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 156 /// this value and returns the result as a ValueVTs value. This uses 157 /// Chain/Flag as the input and updates them for the output Chain/Flag. 158 /// If the Flag pointer is NULL, no flag is used. 159 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, 160 SDValue &Chain, SDValue *Flag) const; 161 162 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 163 /// specified value into the registers specified by this object. This uses 164 /// Chain/Flag as the input and updates them for the output Chain/Flag. 165 /// If the Flag pointer is NULL, no flag is used. 166 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 167 SDValue &Chain, SDValue *Flag) const; 168 169 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 170 /// operand list. This adds the code marker, matching input operand index 171 /// (if applicable), and includes the number of values added into it. 172 void AddInlineAsmOperands(unsigned Code, 173 bool HasMatching, unsigned MatchingIdx, 174 SelectionDAG &DAG, 175 std::vector<SDValue> &Ops) const; 176 }; 177} 178 179/// getCopyFromParts - Create a value that contains the specified legal parts 180/// combined into the value they represent. If the parts combine to a type 181/// larger then ValueVT then AssertOp can be used to specify whether the extra 182/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 183/// (ISD::AssertSext). 184static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, 185 const SDValue *Parts, 186 unsigned NumParts, EVT PartVT, EVT ValueVT, 187 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 188 assert(NumParts > 0 && "No parts to assemble!"); 189 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 190 SDValue Val = Parts[0]; 191 192 if (NumParts > 1) { 193 // Assemble the value from multiple parts. 194 if (!ValueVT.isVector() && ValueVT.isInteger()) { 195 unsigned PartBits = PartVT.getSizeInBits(); 196 unsigned ValueBits = ValueVT.getSizeInBits(); 197 198 // Assemble the power of 2 part. 199 unsigned RoundParts = NumParts & (NumParts - 1) ? 200 1 << Log2_32(NumParts) : NumParts; 201 unsigned RoundBits = PartBits * RoundParts; 202 EVT RoundVT = RoundBits == ValueBits ? 203 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 204 SDValue Lo, Hi; 205 206 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 207 208 if (RoundParts > 2) { 209 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts / 2, 210 PartVT, HalfVT); 211 Hi = getCopyFromParts(DAG, dl, Parts + RoundParts / 2, 212 RoundParts / 2, PartVT, HalfVT); 213 } else { 214 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]); 215 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]); 216 } 217 218 if (TLI.isBigEndian()) 219 std::swap(Lo, Hi); 220 221 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi); 222 223 if (RoundParts < NumParts) { 224 // Assemble the trailing non-power-of-2 part. 225 unsigned OddParts = NumParts - RoundParts; 226 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 227 Hi = getCopyFromParts(DAG, dl, 228 Parts + RoundParts, OddParts, PartVT, OddVT); 229 230 // Combine the round and odd parts. 231 Lo = Val; 232 if (TLI.isBigEndian()) 233 std::swap(Lo, Hi); 234 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 235 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi); 236 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi, 237 DAG.getConstant(Lo.getValueType().getSizeInBits(), 238 TLI.getPointerTy())); 239 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo); 240 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi); 241 } 242 } else if (ValueVT.isVector()) { 243 // Handle a multi-element vector. 244 EVT IntermediateVT, RegisterVT; 245 unsigned NumIntermediates; 246 unsigned NumRegs = 247 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 248 NumIntermediates, RegisterVT); 249 assert(NumRegs == NumParts 250 && "Part count doesn't match vector breakdown!"); 251 NumParts = NumRegs; // Silence a compiler warning. 252 assert(RegisterVT == PartVT 253 && "Part type doesn't match vector breakdown!"); 254 assert(RegisterVT == Parts[0].getValueType() && 255 "Part type doesn't match part!"); 256 257 // Assemble the parts into intermediate operands. 258 SmallVector<SDValue, 8> Ops(NumIntermediates); 259 if (NumIntermediates == NumParts) { 260 // If the register was not expanded, truncate or copy the value, 261 // as appropriate. 262 for (unsigned i = 0; i != NumParts; ++i) 263 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1, 264 PartVT, IntermediateVT); 265 } else if (NumParts > 0) { 266 // If the intermediate type was expanded, build the intermediate 267 // operands from the parts. 268 assert(NumParts % NumIntermediates == 0 && 269 "Must expand into a divisible number of parts!"); 270 unsigned Factor = NumParts / NumIntermediates; 271 for (unsigned i = 0; i != NumIntermediates; ++i) 272 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor, 273 PartVT, IntermediateVT); 274 } 275 276 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 277 // intermediate operands. 278 Val = DAG.getNode(IntermediateVT.isVector() ? 279 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl, 280 ValueVT, &Ops[0], NumIntermediates); 281 } else if (PartVT.isFloatingPoint()) { 282 // FP split into multiple FP parts (for ppcf128) 283 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 284 "Unexpected split"); 285 SDValue Lo, Hi; 286 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]); 287 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]); 288 if (TLI.isBigEndian()) 289 std::swap(Lo, Hi); 290 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi); 291 } else { 292 // FP split into integer parts (soft fp) 293 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 294 !PartVT.isVector() && "Unexpected split"); 295 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 296 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT); 297 } 298 } 299 300 // There is now one part, held in Val. Correct it to match ValueVT. 301 PartVT = Val.getValueType(); 302 303 if (PartVT == ValueVT) 304 return Val; 305 306 if (PartVT.isVector()) { 307 assert(ValueVT.isVector() && "Unknown vector conversion!"); 308 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); 309 } 310 311 if (ValueVT.isVector()) { 312 assert(ValueVT.getVectorElementType() == PartVT && 313 ValueVT.getVectorNumElements() == 1 && 314 "Only trivial scalar-to-vector conversions should get here!"); 315 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val); 316 } 317 318 if (PartVT.isInteger() && 319 ValueVT.isInteger()) { 320 if (ValueVT.bitsLT(PartVT)) { 321 // For a truncate, see if we have any information to 322 // indicate whether the truncated bits will always be 323 // zero or sign-extension. 324 if (AssertOp != ISD::DELETED_NODE) 325 Val = DAG.getNode(AssertOp, dl, PartVT, Val, 326 DAG.getValueType(ValueVT)); 327 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); 328 } else { 329 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val); 330 } 331 } 332 333 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 334 if (ValueVT.bitsLT(Val.getValueType())) { 335 // FP_ROUND's are always exact here. 336 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val, 337 DAG.getIntPtrConstant(1)); 338 } 339 340 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val); 341 } 342 343 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 344 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); 345 346 llvm_unreachable("Unknown mismatch!"); 347 return SDValue(); 348} 349 350/// getCopyToParts - Create a series of nodes that contain the specified value 351/// split into legal parts. If the parts contain more bits than Val, then, for 352/// integers, ExtendKind can be used to specify how to generate the extra bits. 353static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, 354 SDValue Val, SDValue *Parts, unsigned NumParts, 355 EVT PartVT, 356 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 357 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 358 EVT PtrVT = TLI.getPointerTy(); 359 EVT ValueVT = Val.getValueType(); 360 unsigned PartBits = PartVT.getSizeInBits(); 361 unsigned OrigNumParts = NumParts; 362 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 363 364 if (!NumParts) 365 return; 366 367 if (!ValueVT.isVector()) { 368 if (PartVT == ValueVT) { 369 assert(NumParts == 1 && "No-op copy with multiple parts!"); 370 Parts[0] = Val; 371 return; 372 } 373 374 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 375 // If the parts cover more bits than the value has, promote the value. 376 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 377 assert(NumParts == 1 && "Do not know what to promote to!"); 378 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val); 379 } else if (PartVT.isInteger() && ValueVT.isInteger()) { 380 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 381 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val); 382 } else { 383 llvm_unreachable("Unknown mismatch!"); 384 } 385 } else if (PartBits == ValueVT.getSizeInBits()) { 386 // Different types of the same size. 387 assert(NumParts == 1 && PartVT != ValueVT); 388 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val); 389 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 390 // If the parts cover less bits than value has, truncate the value. 391 if (PartVT.isInteger() && ValueVT.isInteger()) { 392 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 393 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); 394 } else { 395 llvm_unreachable("Unknown mismatch!"); 396 } 397 } 398 399 // The value may have changed - recompute ValueVT. 400 ValueVT = Val.getValueType(); 401 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 402 "Failed to tile the value with PartVT!"); 403 404 if (NumParts == 1) { 405 assert(PartVT == ValueVT && "Type conversion failed!"); 406 Parts[0] = Val; 407 return; 408 } 409 410 // Expand the value into multiple parts. 411 if (NumParts & (NumParts - 1)) { 412 // The number of parts is not a power of 2. Split off and copy the tail. 413 assert(PartVT.isInteger() && ValueVT.isInteger() && 414 "Do not know what to expand to!"); 415 unsigned RoundParts = 1 << Log2_32(NumParts); 416 unsigned RoundBits = RoundParts * PartBits; 417 unsigned OddParts = NumParts - RoundParts; 418 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val, 419 DAG.getConstant(RoundBits, 420 TLI.getPointerTy())); 421 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, 422 OddParts, PartVT); 423 424 if (TLI.isBigEndian()) 425 // The odd parts were reversed by getCopyToParts - unreverse them. 426 std::reverse(Parts + RoundParts, Parts + NumParts); 427 428 NumParts = RoundParts; 429 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 430 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); 431 } 432 433 // The number of parts is a power of 2. Repeatedly bisect the value using 434 // EXTRACT_ELEMENT. 435 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl, 436 EVT::getIntegerVT(*DAG.getContext(), 437 ValueVT.getSizeInBits()), 438 Val); 439 440 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 441 for (unsigned i = 0; i < NumParts; i += StepSize) { 442 unsigned ThisBits = StepSize * PartBits / 2; 443 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 444 SDValue &Part0 = Parts[i]; 445 SDValue &Part1 = Parts[i+StepSize/2]; 446 447 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 448 ThisVT, Part0, 449 DAG.getConstant(1, PtrVT)); 450 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 451 ThisVT, Part0, 452 DAG.getConstant(0, PtrVT)); 453 454 if (ThisBits == PartBits && ThisVT != PartVT) { 455 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl, 456 PartVT, Part0); 457 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl, 458 PartVT, Part1); 459 } 460 } 461 } 462 463 if (TLI.isBigEndian()) 464 std::reverse(Parts, Parts + OrigNumParts); 465 466 return; 467 } 468 469 // Vector ValueVT. 470 if (NumParts == 1) { 471 if (PartVT != ValueVT) { 472 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 473 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val); 474 } else { 475 assert(ValueVT.getVectorElementType() == PartVT && 476 ValueVT.getVectorNumElements() == 1 && 477 "Only trivial vector-to-scalar conversions should get here!"); 478 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 479 PartVT, Val, 480 DAG.getConstant(0, PtrVT)); 481 } 482 } 483 484 Parts[0] = Val; 485 return; 486 } 487 488 // Handle a multi-element vector. 489 EVT IntermediateVT, RegisterVT; 490 unsigned NumIntermediates; 491 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 492 IntermediateVT, NumIntermediates, RegisterVT); 493 unsigned NumElements = ValueVT.getVectorNumElements(); 494 495 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 496 NumParts = NumRegs; // Silence a compiler warning. 497 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 498 499 // Split the vector into intermediate operands. 500 SmallVector<SDValue, 8> Ops(NumIntermediates); 501 for (unsigned i = 0; i != NumIntermediates; ++i) { 502 if (IntermediateVT.isVector()) 503 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, 504 IntermediateVT, Val, 505 DAG.getConstant(i * (NumElements / NumIntermediates), 506 PtrVT)); 507 else 508 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 509 IntermediateVT, Val, 510 DAG.getConstant(i, PtrVT)); 511 } 512 513 // Split the intermediate operands into legal parts. 514 if (NumParts == NumIntermediates) { 515 // If the register was not expanded, promote or copy the value, 516 // as appropriate. 517 for (unsigned i = 0; i != NumParts; ++i) 518 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT); 519 } else if (NumParts > 0) { 520 // If the intermediate type was expanded, split each the value into 521 // legal parts. 522 assert(NumParts % NumIntermediates == 0 && 523 "Must expand into a divisible number of parts!"); 524 unsigned Factor = NumParts / NumIntermediates; 525 for (unsigned i = 0; i != NumIntermediates; ++i) 526 getCopyToParts(DAG, dl, Ops[i], &Parts[i*Factor], Factor, PartVT); 527 } 528} 529 530 531void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 532 AA = &aa; 533 GFI = gfi; 534 TD = DAG.getTarget().getTargetData(); 535} 536 537/// clear - Clear out the curret SelectionDAG and the associated 538/// state and prepare this SelectionDAGBuilder object to be used 539/// for a new block. This doesn't clear out information about 540/// additional blocks that are needed to complete switch lowering 541/// or PHI node updating; that information is cleared out as it is 542/// consumed. 543void SelectionDAGBuilder::clear() { 544 NodeMap.clear(); 545 PendingLoads.clear(); 546 PendingExports.clear(); 547 EdgeMapping.clear(); 548 DAG.clear(); 549 CurDebugLoc = DebugLoc::getUnknownLoc(); 550 HasTailCall = false; 551} 552 553/// getRoot - Return the current virtual root of the Selection DAG, 554/// flushing any PendingLoad items. This must be done before emitting 555/// a store or any other node that may need to be ordered after any 556/// prior load instructions. 557/// 558SDValue SelectionDAGBuilder::getRoot() { 559 if (PendingLoads.empty()) 560 return DAG.getRoot(); 561 562 if (PendingLoads.size() == 1) { 563 SDValue Root = PendingLoads[0]; 564 DAG.setRoot(Root); 565 PendingLoads.clear(); 566 return Root; 567 } 568 569 // Otherwise, we have to make a token factor node. 570 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 571 &PendingLoads[0], PendingLoads.size()); 572 PendingLoads.clear(); 573 DAG.setRoot(Root); 574 return Root; 575} 576 577/// getControlRoot - Similar to getRoot, but instead of flushing all the 578/// PendingLoad items, flush all the PendingExports items. It is necessary 579/// to do this before emitting a terminator instruction. 580/// 581SDValue SelectionDAGBuilder::getControlRoot() { 582 SDValue Root = DAG.getRoot(); 583 584 if (PendingExports.empty()) 585 return Root; 586 587 // Turn all of the CopyToReg chains into one factored node. 588 if (Root.getOpcode() != ISD::EntryToken) { 589 unsigned i = 0, e = PendingExports.size(); 590 for (; i != e; ++i) { 591 assert(PendingExports[i].getNode()->getNumOperands() > 1); 592 if (PendingExports[i].getNode()->getOperand(0) == Root) 593 break; // Don't add the root if we already indirectly depend on it. 594 } 595 596 if (i == e) 597 PendingExports.push_back(Root); 598 } 599 600 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 601 &PendingExports[0], 602 PendingExports.size()); 603 PendingExports.clear(); 604 DAG.setRoot(Root); 605 return Root; 606} 607 608void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 609 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 610 DAG.AssignOrdering(Node, SDNodeOrder); 611 612 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 613 AssignOrderingToNode(Node->getOperand(I).getNode()); 614} 615 616void SelectionDAGBuilder::visit(Instruction &I) { 617 visit(I.getOpcode(), I); 618} 619 620void SelectionDAGBuilder::visit(unsigned Opcode, User &I) { 621 // Note: this doesn't use InstVisitor, because it has to work with 622 // ConstantExpr's in addition to instructions. 623 switch (Opcode) { 624 default: llvm_unreachable("Unknown instruction type encountered!"); 625 // Build the switch statement using the Instruction.def file. 626#define HANDLE_INST(NUM, OPCODE, CLASS) \ 627 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 628#include "llvm/Instruction.def" 629 } 630 631 // Assign the ordering to the freshly created DAG nodes. 632 if (NodeMap.count(&I)) { 633 ++SDNodeOrder; 634 AssignOrderingToNode(getValue(&I).getNode()); 635 } 636} 637 638SDValue SelectionDAGBuilder::getValue(const Value *V) { 639 SDValue &N = NodeMap[V]; 640 if (N.getNode()) return N; 641 642 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 643 EVT VT = TLI.getValueType(V->getType(), true); 644 645 if (ConstantInt *CI = dyn_cast<ConstantInt>(C)) 646 return N = DAG.getConstant(*CI, VT); 647 648 if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) 649 return N = DAG.getGlobalAddress(GV, VT); 650 651 if (isa<ConstantPointerNull>(C)) 652 return N = DAG.getConstant(0, TLI.getPointerTy()); 653 654 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 655 return N = DAG.getConstantFP(*CFP, VT); 656 657 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 658 return N = DAG.getUNDEF(VT); 659 660 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 661 visit(CE->getOpcode(), *CE); 662 SDValue N1 = NodeMap[V]; 663 assert(N1.getNode() && "visit didn't populate the ValueMap!"); 664 return N1; 665 } 666 667 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 668 SmallVector<SDValue, 4> Constants; 669 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 670 OI != OE; ++OI) { 671 SDNode *Val = getValue(*OI).getNode(); 672 // If the operand is an empty aggregate, there are no values. 673 if (!Val) continue; 674 // Add each leaf value from the operand to the Constants list 675 // to form a flattened list of all the values. 676 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 677 Constants.push_back(SDValue(Val, i)); 678 } 679 680 return DAG.getMergeValues(&Constants[0], Constants.size(), 681 getCurDebugLoc()); 682 } 683 684 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 685 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 686 "Unknown struct or array constant!"); 687 688 SmallVector<EVT, 4> ValueVTs; 689 ComputeValueVTs(TLI, C->getType(), ValueVTs); 690 unsigned NumElts = ValueVTs.size(); 691 if (NumElts == 0) 692 return SDValue(); // empty struct 693 SmallVector<SDValue, 4> Constants(NumElts); 694 for (unsigned i = 0; i != NumElts; ++i) { 695 EVT EltVT = ValueVTs[i]; 696 if (isa<UndefValue>(C)) 697 Constants[i] = DAG.getUNDEF(EltVT); 698 else if (EltVT.isFloatingPoint()) 699 Constants[i] = DAG.getConstantFP(0, EltVT); 700 else 701 Constants[i] = DAG.getConstant(0, EltVT); 702 } 703 704 return DAG.getMergeValues(&Constants[0], NumElts, 705 getCurDebugLoc()); 706 } 707 708 if (BlockAddress *BA = dyn_cast<BlockAddress>(C)) 709 return DAG.getBlockAddress(BA, VT); 710 711 const VectorType *VecTy = cast<VectorType>(V->getType()); 712 unsigned NumElements = VecTy->getNumElements(); 713 714 // Now that we know the number and type of the elements, get that number of 715 // elements into the Ops array based on what kind of constant it is. 716 SmallVector<SDValue, 16> Ops; 717 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 718 for (unsigned i = 0; i != NumElements; ++i) 719 Ops.push_back(getValue(CP->getOperand(i))); 720 } else { 721 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 722 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 723 724 SDValue Op; 725 if (EltVT.isFloatingPoint()) 726 Op = DAG.getConstantFP(0, EltVT); 727 else 728 Op = DAG.getConstant(0, EltVT); 729 Ops.assign(NumElements, Op); 730 } 731 732 // Create a BUILD_VECTOR node. 733 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 734 VT, &Ops[0], Ops.size()); 735 } 736 737 // If this is a static alloca, generate it as the frameindex instead of 738 // computation. 739 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 740 DenseMap<const AllocaInst*, int>::iterator SI = 741 FuncInfo.StaticAllocaMap.find(AI); 742 if (SI != FuncInfo.StaticAllocaMap.end()) 743 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 744 } 745 746 unsigned InReg = FuncInfo.ValueMap[V]; 747 assert(InReg && "Value not in map!"); 748 749 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 750 SDValue Chain = DAG.getEntryNode(); 751 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL); 752} 753 754/// Get the EVTs and ArgFlags collections that represent the legalized return 755/// type of the given function. This does not require a DAG or a return value, 756/// and is suitable for use before any DAGs for the function are constructed. 757static void getReturnInfo(const Type* ReturnType, 758 Attributes attr, SmallVectorImpl<EVT> &OutVTs, 759 SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags, 760 TargetLowering &TLI, 761 SmallVectorImpl<uint64_t> *Offsets = 0) { 762 SmallVector<EVT, 4> ValueVTs; 763 ComputeValueVTs(TLI, ReturnType, ValueVTs); 764 unsigned NumValues = ValueVTs.size(); 765 if (NumValues == 0) return; 766 unsigned Offset = 0; 767 768 for (unsigned j = 0, f = NumValues; j != f; ++j) { 769 EVT VT = ValueVTs[j]; 770 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 771 772 if (attr & Attribute::SExt) 773 ExtendKind = ISD::SIGN_EXTEND; 774 else if (attr & Attribute::ZExt) 775 ExtendKind = ISD::ZERO_EXTEND; 776 777 // FIXME: C calling convention requires the return type to be promoted to 778 // at least 32-bit. But this is not necessary for non-C calling 779 // conventions. The frontend should mark functions whose return values 780 // require promoting with signext or zeroext attributes. 781 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 782 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 783 if (VT.bitsLT(MinVT)) 784 VT = MinVT; 785 } 786 787 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 788 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 789 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 790 PartVT.getTypeForEVT(ReturnType->getContext())); 791 792 // 'inreg' on function refers to return value 793 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 794 if (attr & Attribute::InReg) 795 Flags.setInReg(); 796 797 // Propagate extension type if any 798 if (attr & Attribute::SExt) 799 Flags.setSExt(); 800 else if (attr & Attribute::ZExt) 801 Flags.setZExt(); 802 803 for (unsigned i = 0; i < NumParts; ++i) { 804 OutVTs.push_back(PartVT); 805 OutFlags.push_back(Flags); 806 if (Offsets) 807 { 808 Offsets->push_back(Offset); 809 Offset += PartSize; 810 } 811 } 812 } 813} 814 815void SelectionDAGBuilder::visitRet(ReturnInst &I) { 816 SDValue Chain = getControlRoot(); 817 SmallVector<ISD::OutputArg, 8> Outs; 818 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 819 820 if (!FLI.CanLowerReturn) { 821 unsigned DemoteReg = FLI.DemoteRegister; 822 const Function *F = I.getParent()->getParent(); 823 824 // Emit a store of the return value through the virtual register. 825 // Leave Outs empty so that LowerReturn won't try to load return 826 // registers the usual way. 827 SmallVector<EVT, 1> PtrValueVTs; 828 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 829 PtrValueVTs); 830 831 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 832 SDValue RetOp = getValue(I.getOperand(0)); 833 834 SmallVector<EVT, 4> ValueVTs; 835 SmallVector<uint64_t, 4> Offsets; 836 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 837 unsigned NumValues = ValueVTs.size(); 838 839 SmallVector<SDValue, 4> Chains(NumValues); 840 EVT PtrVT = PtrValueVTs[0]; 841 for (unsigned i = 0; i != NumValues; ++i) { 842 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, RetPtr, 843 DAG.getConstant(Offsets[i], PtrVT)); 844 Chains[i] = 845 DAG.getStore(Chain, getCurDebugLoc(), 846 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 847 Add, NULL, Offsets[i], false, false, 0); 848 } 849 850 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 851 MVT::Other, &Chains[0], NumValues); 852 } else if (I.getNumOperands() != 0) { 853 SmallVector<EVT, 4> ValueVTs; 854 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 855 unsigned NumValues = ValueVTs.size(); 856 if (NumValues) { 857 SDValue RetOp = getValue(I.getOperand(0)); 858 for (unsigned j = 0, f = NumValues; j != f; ++j) { 859 EVT VT = ValueVTs[j]; 860 861 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 862 863 const Function *F = I.getParent()->getParent(); 864 if (F->paramHasAttr(0, Attribute::SExt)) 865 ExtendKind = ISD::SIGN_EXTEND; 866 else if (F->paramHasAttr(0, Attribute::ZExt)) 867 ExtendKind = ISD::ZERO_EXTEND; 868 869 // FIXME: C calling convention requires the return type to be promoted 870 // to at least 32-bit. But this is not necessary for non-C calling 871 // conventions. The frontend should mark functions whose return values 872 // require promoting with signext or zeroext attributes. 873 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 874 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32); 875 if (VT.bitsLT(MinVT)) 876 VT = MinVT; 877 } 878 879 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 880 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 881 SmallVector<SDValue, 4> Parts(NumParts); 882 getCopyToParts(DAG, getCurDebugLoc(), 883 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 884 &Parts[0], NumParts, PartVT, ExtendKind); 885 886 // 'inreg' on function refers to return value 887 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 888 if (F->paramHasAttr(0, Attribute::InReg)) 889 Flags.setInReg(); 890 891 // Propagate extension type if any 892 if (F->paramHasAttr(0, Attribute::SExt)) 893 Flags.setSExt(); 894 else if (F->paramHasAttr(0, Attribute::ZExt)) 895 Flags.setZExt(); 896 897 for (unsigned i = 0; i < NumParts; ++i) 898 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true)); 899 } 900 } 901 } 902 903 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 904 CallingConv::ID CallConv = 905 DAG.getMachineFunction().getFunction()->getCallingConv(); 906 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 907 Outs, getCurDebugLoc(), DAG); 908 909 // Verify that the target's LowerReturn behaved as expected. 910 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 911 "LowerReturn didn't return a valid chain!"); 912 913 // Update the DAG with the new chain value resulting from return lowering. 914 DAG.setRoot(Chain); 915} 916 917/// CopyToExportRegsIfNeeded - If the given value has virtual registers 918/// created for it, emit nodes to copy the value into the virtual 919/// registers. 920void SelectionDAGBuilder::CopyToExportRegsIfNeeded(Value *V) { 921 if (!V->use_empty()) { 922 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 923 if (VMI != FuncInfo.ValueMap.end()) 924 CopyValueToVirtualRegister(V, VMI->second); 925 } 926} 927 928/// ExportFromCurrentBlock - If this condition isn't known to be exported from 929/// the current basic block, add it to ValueMap now so that we'll get a 930/// CopyTo/FromReg. 931void SelectionDAGBuilder::ExportFromCurrentBlock(Value *V) { 932 // No need to export constants. 933 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 934 935 // Already exported? 936 if (FuncInfo.isExportedInst(V)) return; 937 938 unsigned Reg = FuncInfo.InitializeRegForValue(V); 939 CopyValueToVirtualRegister(V, Reg); 940} 941 942bool SelectionDAGBuilder::isExportableFromCurrentBlock(Value *V, 943 const BasicBlock *FromBB) { 944 // The operands of the setcc have to be in this block. We don't know 945 // how to export them from some other block. 946 if (Instruction *VI = dyn_cast<Instruction>(V)) { 947 // Can export from current BB. 948 if (VI->getParent() == FromBB) 949 return true; 950 951 // Is already exported, noop. 952 return FuncInfo.isExportedInst(V); 953 } 954 955 // If this is an argument, we can export it if the BB is the entry block or 956 // if it is already exported. 957 if (isa<Argument>(V)) { 958 if (FromBB == &FromBB->getParent()->getEntryBlock()) 959 return true; 960 961 // Otherwise, can only export this if it is already exported. 962 return FuncInfo.isExportedInst(V); 963 } 964 965 // Otherwise, constants can always be exported. 966 return true; 967} 968 969static bool InBlock(const Value *V, const BasicBlock *BB) { 970 if (const Instruction *I = dyn_cast<Instruction>(V)) 971 return I->getParent() == BB; 972 return true; 973} 974 975/// getFCmpCondCode - Return the ISD condition code corresponding to 976/// the given LLVM IR floating-point condition code. This includes 977/// consideration of global floating-point math flags. 978/// 979static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) { 980 ISD::CondCode FPC, FOC; 981 switch (Pred) { 982 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 983 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 984 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 985 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 986 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 987 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 988 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 989 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 990 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 991 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 992 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 993 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 994 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 995 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 996 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 997 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 998 default: 999 llvm_unreachable("Invalid FCmp predicate opcode!"); 1000 FOC = FPC = ISD::SETFALSE; 1001 break; 1002 } 1003 if (FiniteOnlyFPMath()) 1004 return FOC; 1005 else 1006 return FPC; 1007} 1008 1009/// getICmpCondCode - Return the ISD condition code corresponding to 1010/// the given LLVM IR integer condition code. 1011/// 1012static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) { 1013 switch (Pred) { 1014 case ICmpInst::ICMP_EQ: return ISD::SETEQ; 1015 case ICmpInst::ICMP_NE: return ISD::SETNE; 1016 case ICmpInst::ICMP_SLE: return ISD::SETLE; 1017 case ICmpInst::ICMP_ULE: return ISD::SETULE; 1018 case ICmpInst::ICMP_SGE: return ISD::SETGE; 1019 case ICmpInst::ICMP_UGE: return ISD::SETUGE; 1020 case ICmpInst::ICMP_SLT: return ISD::SETLT; 1021 case ICmpInst::ICMP_ULT: return ISD::SETULT; 1022 case ICmpInst::ICMP_SGT: return ISD::SETGT; 1023 case ICmpInst::ICMP_UGT: return ISD::SETUGT; 1024 default: 1025 llvm_unreachable("Invalid ICmp predicate opcode!"); 1026 return ISD::SETNE; 1027 } 1028} 1029 1030/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1031/// This function emits a branch and is used at the leaves of an OR or an 1032/// AND operator tree. 1033/// 1034void 1035SelectionDAGBuilder::EmitBranchForMergedCondition(Value *Cond, 1036 MachineBasicBlock *TBB, 1037 MachineBasicBlock *FBB, 1038 MachineBasicBlock *CurBB) { 1039 const BasicBlock *BB = CurBB->getBasicBlock(); 1040 1041 // If the leaf of the tree is a comparison, merge the condition into 1042 // the caseblock. 1043 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1044 // The operands of the cmp have to be in this block. We don't know 1045 // how to export them from some other block. If this is the first block 1046 // of the sequence, no exporting is needed. 1047 if (CurBB == CurMBB || 1048 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1049 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1050 ISD::CondCode Condition; 1051 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1052 Condition = getICmpCondCode(IC->getPredicate()); 1053 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1054 Condition = getFCmpCondCode(FC->getPredicate()); 1055 } else { 1056 Condition = ISD::SETEQ; // silence warning. 1057 llvm_unreachable("Unknown compare instruction"); 1058 } 1059 1060 CaseBlock CB(Condition, BOp->getOperand(0), 1061 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1062 SwitchCases.push_back(CB); 1063 return; 1064 } 1065 } 1066 1067 // Create a CaseBlock record representing this branch. 1068 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1069 NULL, TBB, FBB, CurBB); 1070 SwitchCases.push_back(CB); 1071} 1072 1073/// FindMergedConditions - If Cond is an expression like 1074void SelectionDAGBuilder::FindMergedConditions(Value *Cond, 1075 MachineBasicBlock *TBB, 1076 MachineBasicBlock *FBB, 1077 MachineBasicBlock *CurBB, 1078 unsigned Opc) { 1079 // If this node is not part of the or/and tree, emit it as a branch. 1080 Instruction *BOp = dyn_cast<Instruction>(Cond); 1081 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1082 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1083 BOp->getParent() != CurBB->getBasicBlock() || 1084 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1085 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1086 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB); 1087 return; 1088 } 1089 1090 // Create TmpBB after CurBB. 1091 MachineFunction::iterator BBI = CurBB; 1092 MachineFunction &MF = DAG.getMachineFunction(); 1093 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1094 CurBB->getParent()->insert(++BBI, TmpBB); 1095 1096 if (Opc == Instruction::Or) { 1097 // Codegen X | Y as: 1098 // jmp_if_X TBB 1099 // jmp TmpBB 1100 // TmpBB: 1101 // jmp_if_Y TBB 1102 // jmp FBB 1103 // 1104 1105 // Emit the LHS condition. 1106 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1107 1108 // Emit the RHS condition into TmpBB. 1109 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1110 } else { 1111 assert(Opc == Instruction::And && "Unknown merge op!"); 1112 // Codegen X & Y as: 1113 // jmp_if_X TmpBB 1114 // jmp FBB 1115 // TmpBB: 1116 // jmp_if_Y TBB 1117 // jmp FBB 1118 // 1119 // This requires creation of TmpBB after CurBB. 1120 1121 // Emit the LHS condition. 1122 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1123 1124 // Emit the RHS condition into TmpBB. 1125 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1126 } 1127} 1128 1129/// If the set of cases should be emitted as a series of branches, return true. 1130/// If we should emit this as a bunch of and/or'd together conditions, return 1131/// false. 1132bool 1133SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1134 if (Cases.size() != 2) return true; 1135 1136 // If this is two comparisons of the same values or'd or and'd together, they 1137 // will get folded into a single comparison, so don't emit two blocks. 1138 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1139 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1140 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1141 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1142 return false; 1143 } 1144 1145 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1146 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1147 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1148 Cases[0].CC == Cases[1].CC && 1149 isa<Constant>(Cases[0].CmpRHS) && 1150 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1151 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1152 return false; 1153 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1154 return false; 1155 } 1156 1157 return true; 1158} 1159 1160void SelectionDAGBuilder::visitBr(BranchInst &I) { 1161 // Update machine-CFG edges. 1162 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1163 1164 // Figure out which block is immediately after the current one. 1165 MachineBasicBlock *NextBlock = 0; 1166 MachineFunction::iterator BBI = CurMBB; 1167 if (++BBI != FuncInfo.MF->end()) 1168 NextBlock = BBI; 1169 1170 if (I.isUnconditional()) { 1171 // Update machine-CFG edges. 1172 CurMBB->addSuccessor(Succ0MBB); 1173 1174 // If this is not a fall-through branch, emit the branch. 1175 if (Succ0MBB != NextBlock) 1176 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1177 MVT::Other, getControlRoot(), 1178 DAG.getBasicBlock(Succ0MBB))); 1179 1180 return; 1181 } 1182 1183 // If this condition is one of the special cases we handle, do special stuff 1184 // now. 1185 Value *CondVal = I.getCondition(); 1186 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1187 1188 // If this is a series of conditions that are or'd or and'd together, emit 1189 // this as a sequence of branches instead of setcc's with and/or operations. 1190 // For example, instead of something like: 1191 // cmp A, B 1192 // C = seteq 1193 // cmp D, E 1194 // F = setle 1195 // or C, F 1196 // jnz foo 1197 // Emit: 1198 // cmp A, B 1199 // je foo 1200 // cmp D, E 1201 // jle foo 1202 // 1203 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1204 if (BOp->hasOneUse() && 1205 (BOp->getOpcode() == Instruction::And || 1206 BOp->getOpcode() == Instruction::Or)) { 1207 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1208 // If the compares in later blocks need to use values not currently 1209 // exported from this block, export them now. This block should always 1210 // be the first entry. 1211 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1212 1213 // Allow some cases to be rejected. 1214 if (ShouldEmitAsBranches(SwitchCases)) { 1215 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1216 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1217 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1218 } 1219 1220 // Emit the branch for this block. 1221 visitSwitchCase(SwitchCases[0]); 1222 SwitchCases.erase(SwitchCases.begin()); 1223 return; 1224 } 1225 1226 // Okay, we decided not to do this, remove any inserted MBB's and clear 1227 // SwitchCases. 1228 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1229 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1230 1231 SwitchCases.clear(); 1232 } 1233 } 1234 1235 // Create a CaseBlock record representing this branch. 1236 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1237 NULL, Succ0MBB, Succ1MBB, CurMBB); 1238 1239 // Use visitSwitchCase to actually insert the fast branch sequence for this 1240 // cond branch. 1241 visitSwitchCase(CB); 1242} 1243 1244/// visitSwitchCase - Emits the necessary code to represent a single node in 1245/// the binary search tree resulting from lowering a switch instruction. 1246void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) { 1247 SDValue Cond; 1248 SDValue CondLHS = getValue(CB.CmpLHS); 1249 DebugLoc dl = getCurDebugLoc(); 1250 1251 // Build the setcc now. 1252 if (CB.CmpMHS == NULL) { 1253 // Fold "(X == true)" to X and "(X == false)" to !X to 1254 // handle common cases produced by branch lowering. 1255 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1256 CB.CC == ISD::SETEQ) 1257 Cond = CondLHS; 1258 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1259 CB.CC == ISD::SETEQ) { 1260 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1261 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1262 } else 1263 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1264 } else { 1265 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1266 1267 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1268 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1269 1270 SDValue CmpOp = getValue(CB.CmpMHS); 1271 EVT VT = CmpOp.getValueType(); 1272 1273 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1274 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1275 ISD::SETLE); 1276 } else { 1277 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1278 VT, CmpOp, DAG.getConstant(Low, VT)); 1279 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1280 DAG.getConstant(High-Low, VT), ISD::SETULE); 1281 } 1282 } 1283 1284 // Update successor info 1285 CurMBB->addSuccessor(CB.TrueBB); 1286 CurMBB->addSuccessor(CB.FalseBB); 1287 1288 // Set NextBlock to be the MBB immediately after the current one, if any. 1289 // This is used to avoid emitting unnecessary branches to the next block. 1290 MachineBasicBlock *NextBlock = 0; 1291 MachineFunction::iterator BBI = CurMBB; 1292 if (++BBI != FuncInfo.MF->end()) 1293 NextBlock = BBI; 1294 1295 // If the lhs block is the next block, invert the condition so that we can 1296 // fall through to the lhs instead of the rhs block. 1297 if (CB.TrueBB == NextBlock) { 1298 std::swap(CB.TrueBB, CB.FalseBB); 1299 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1300 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1301 } 1302 1303 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1304 MVT::Other, getControlRoot(), Cond, 1305 DAG.getBasicBlock(CB.TrueBB)); 1306 1307 // If the branch was constant folded, fix up the CFG. 1308 if (BrCond.getOpcode() == ISD::BR) { 1309 CurMBB->removeSuccessor(CB.FalseBB); 1310 } else { 1311 // Otherwise, go ahead and insert the false branch. 1312 if (BrCond == getControlRoot()) 1313 CurMBB->removeSuccessor(CB.TrueBB); 1314 1315 if (CB.FalseBB != NextBlock) 1316 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1317 DAG.getBasicBlock(CB.FalseBB)); 1318 } 1319 1320 DAG.setRoot(BrCond); 1321} 1322 1323/// visitJumpTable - Emit JumpTable node in the current MBB 1324void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1325 // Emit the code for the jump table 1326 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1327 EVT PTy = TLI.getPointerTy(); 1328 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1329 JT.Reg, PTy); 1330 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1331 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1332 MVT::Other, Index.getValue(1), 1333 Table, Index); 1334 DAG.setRoot(BrJumpTable); 1335} 1336 1337/// visitJumpTableHeader - This function emits necessary code to produce index 1338/// in the JumpTable from switch case. 1339void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1340 JumpTableHeader &JTH) { 1341 // Subtract the lowest switch case value from the value being switched on and 1342 // conditional branch to default mbb if the result is greater than the 1343 // difference between smallest and largest cases. 1344 SDValue SwitchOp = getValue(JTH.SValue); 1345 EVT VT = SwitchOp.getValueType(); 1346 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1347 DAG.getConstant(JTH.First, VT)); 1348 1349 // The SDNode we just created, which holds the value being switched on minus 1350 // the smallest case value, needs to be copied to a virtual register so it 1351 // can be used as an index into the jump table in a subsequent basic block. 1352 // This value may be smaller or larger than the target's pointer type, and 1353 // therefore require extension or truncating. 1354 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1355 1356 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1357 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1358 JumpTableReg, SwitchOp); 1359 JT.Reg = JumpTableReg; 1360 1361 // Emit the range check for the jump table, and branch to the default block 1362 // for the switch statement if the value being switched on exceeds the largest 1363 // case in the switch. 1364 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1365 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1366 DAG.getConstant(JTH.Last-JTH.First,VT), 1367 ISD::SETUGT); 1368 1369 // Set NextBlock to be the MBB immediately after the current one, if any. 1370 // This is used to avoid emitting unnecessary branches to the next block. 1371 MachineBasicBlock *NextBlock = 0; 1372 MachineFunction::iterator BBI = CurMBB; 1373 1374 if (++BBI != FuncInfo.MF->end()) 1375 NextBlock = BBI; 1376 1377 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1378 MVT::Other, CopyTo, CMP, 1379 DAG.getBasicBlock(JT.Default)); 1380 1381 if (JT.MBB != NextBlock) 1382 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1383 DAG.getBasicBlock(JT.MBB)); 1384 1385 DAG.setRoot(BrCond); 1386} 1387 1388/// visitBitTestHeader - This function emits necessary code to produce value 1389/// suitable for "bit tests" 1390void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) { 1391 // Subtract the minimum value 1392 SDValue SwitchOp = getValue(B.SValue); 1393 EVT VT = SwitchOp.getValueType(); 1394 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1395 DAG.getConstant(B.First, VT)); 1396 1397 // Check range 1398 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1399 TLI.getSetCCResultType(Sub.getValueType()), 1400 Sub, DAG.getConstant(B.Range, VT), 1401 ISD::SETUGT); 1402 1403 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), 1404 TLI.getPointerTy()); 1405 1406 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy()); 1407 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1408 B.Reg, ShiftOp); 1409 1410 // Set NextBlock to be the MBB immediately after the current one, if any. 1411 // This is used to avoid emitting unnecessary branches to the next block. 1412 MachineBasicBlock *NextBlock = 0; 1413 MachineFunction::iterator BBI = CurMBB; 1414 if (++BBI != FuncInfo.MF->end()) 1415 NextBlock = BBI; 1416 1417 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1418 1419 CurMBB->addSuccessor(B.Default); 1420 CurMBB->addSuccessor(MBB); 1421 1422 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1423 MVT::Other, CopyTo, RangeCmp, 1424 DAG.getBasicBlock(B.Default)); 1425 1426 if (MBB != NextBlock) 1427 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1428 DAG.getBasicBlock(MBB)); 1429 1430 DAG.setRoot(BrRange); 1431} 1432 1433/// visitBitTestCase - this function produces one "bit test" 1434void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB, 1435 unsigned Reg, 1436 BitTestCase &B) { 1437 // Make desired shift 1438 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg, 1439 TLI.getPointerTy()); 1440 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), 1441 TLI.getPointerTy(), 1442 DAG.getConstant(1, TLI.getPointerTy()), 1443 ShiftOp); 1444 1445 // Emit bit tests and jumps 1446 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1447 TLI.getPointerTy(), SwitchVal, 1448 DAG.getConstant(B.Mask, TLI.getPointerTy())); 1449 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(), 1450 TLI.getSetCCResultType(AndOp.getValueType()), 1451 AndOp, DAG.getConstant(0, TLI.getPointerTy()), 1452 ISD::SETNE); 1453 1454 CurMBB->addSuccessor(B.TargetBB); 1455 CurMBB->addSuccessor(NextMBB); 1456 1457 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1458 MVT::Other, getControlRoot(), 1459 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1460 1461 // Set NextBlock to be the MBB immediately after the current one, if any. 1462 // This is used to avoid emitting unnecessary branches to the next block. 1463 MachineBasicBlock *NextBlock = 0; 1464 MachineFunction::iterator BBI = CurMBB; 1465 if (++BBI != FuncInfo.MF->end()) 1466 NextBlock = BBI; 1467 1468 if (NextMBB != NextBlock) 1469 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1470 DAG.getBasicBlock(NextMBB)); 1471 1472 DAG.setRoot(BrAnd); 1473} 1474 1475void SelectionDAGBuilder::visitInvoke(InvokeInst &I) { 1476 // Retrieve successors. 1477 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1478 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1479 1480 const Value *Callee(I.getCalledValue()); 1481 if (isa<InlineAsm>(Callee)) 1482 visitInlineAsm(&I); 1483 else 1484 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1485 1486 // If the value of the invoke is used outside of its defining block, make it 1487 // available as a virtual register. 1488 CopyToExportRegsIfNeeded(&I); 1489 1490 // Update successor info 1491 CurMBB->addSuccessor(Return); 1492 CurMBB->addSuccessor(LandingPad); 1493 1494 // Drop into normal successor. 1495 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1496 MVT::Other, getControlRoot(), 1497 DAG.getBasicBlock(Return))); 1498} 1499 1500void SelectionDAGBuilder::visitUnwind(UnwindInst &I) { 1501} 1502 1503/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1504/// small case ranges). 1505bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1506 CaseRecVector& WorkList, 1507 Value* SV, 1508 MachineBasicBlock* Default) { 1509 Case& BackCase = *(CR.Range.second-1); 1510 1511 // Size is the number of Cases represented by this range. 1512 size_t Size = CR.Range.second - CR.Range.first; 1513 if (Size > 3) 1514 return false; 1515 1516 // Get the MachineFunction which holds the current MBB. This is used when 1517 // inserting any additional MBBs necessary to represent the switch. 1518 MachineFunction *CurMF = FuncInfo.MF; 1519 1520 // Figure out which block is immediately after the current one. 1521 MachineBasicBlock *NextBlock = 0; 1522 MachineFunction::iterator BBI = CR.CaseBB; 1523 1524 if (++BBI != FuncInfo.MF->end()) 1525 NextBlock = BBI; 1526 1527 // TODO: If any two of the cases has the same destination, and if one value 1528 // is the same as the other, but has one bit unset that the other has set, 1529 // use bit manipulation to do two compares at once. For example: 1530 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1531 1532 // Rearrange the case blocks so that the last one falls through if possible. 1533 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1534 // The last case block won't fall through into 'NextBlock' if we emit the 1535 // branches in this order. See if rearranging a case value would help. 1536 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1537 if (I->BB == NextBlock) { 1538 std::swap(*I, BackCase); 1539 break; 1540 } 1541 } 1542 } 1543 1544 // Create a CaseBlock record representing a conditional branch to 1545 // the Case's target mbb if the value being switched on SV is equal 1546 // to C. 1547 MachineBasicBlock *CurBlock = CR.CaseBB; 1548 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1549 MachineBasicBlock *FallThrough; 1550 if (I != E-1) { 1551 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1552 CurMF->insert(BBI, FallThrough); 1553 1554 // Put SV in a virtual register to make it available from the new blocks. 1555 ExportFromCurrentBlock(SV); 1556 } else { 1557 // If the last case doesn't match, go to the default block. 1558 FallThrough = Default; 1559 } 1560 1561 Value *RHS, *LHS, *MHS; 1562 ISD::CondCode CC; 1563 if (I->High == I->Low) { 1564 // This is just small small case range :) containing exactly 1 case 1565 CC = ISD::SETEQ; 1566 LHS = SV; RHS = I->High; MHS = NULL; 1567 } else { 1568 CC = ISD::SETLE; 1569 LHS = I->Low; MHS = SV; RHS = I->High; 1570 } 1571 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1572 1573 // If emitting the first comparison, just call visitSwitchCase to emit the 1574 // code into the current block. Otherwise, push the CaseBlock onto the 1575 // vector to be later processed by SDISel, and insert the node's MBB 1576 // before the next MBB. 1577 if (CurBlock == CurMBB) 1578 visitSwitchCase(CB); 1579 else 1580 SwitchCases.push_back(CB); 1581 1582 CurBlock = FallThrough; 1583 } 1584 1585 return true; 1586} 1587 1588static inline bool areJTsAllowed(const TargetLowering &TLI) { 1589 return !DisableJumpTables && 1590 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1591 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1592} 1593 1594static APInt ComputeRange(const APInt &First, const APInt &Last) { 1595 APInt LastExt(Last), FirstExt(First); 1596 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1597 LastExt.sext(BitWidth); FirstExt.sext(BitWidth); 1598 return (LastExt - FirstExt + 1ULL); 1599} 1600 1601/// handleJTSwitchCase - Emit jumptable for current switch case range 1602bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1603 CaseRecVector& WorkList, 1604 Value* SV, 1605 MachineBasicBlock* Default) { 1606 Case& FrontCase = *CR.Range.first; 1607 Case& BackCase = *(CR.Range.second-1); 1608 1609 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1610 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1611 1612 APInt TSize(First.getBitWidth(), 0); 1613 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1614 I!=E; ++I) 1615 TSize += I->size(); 1616 1617 if (!areJTsAllowed(TLI) || TSize.ult(APInt(First.getBitWidth(), 4))) 1618 return false; 1619 1620 APInt Range = ComputeRange(First, Last); 1621 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1622 if (Density < 0.4) 1623 return false; 1624 1625 DEBUG(dbgs() << "Lowering jump table\n" 1626 << "First entry: " << First << ". Last entry: " << Last << '\n' 1627 << "Range: " << Range 1628 << "Size: " << TSize << ". Density: " << Density << "\n\n"); 1629 1630 // Get the MachineFunction which holds the current MBB. This is used when 1631 // inserting any additional MBBs necessary to represent the switch. 1632 MachineFunction *CurMF = FuncInfo.MF; 1633 1634 // Figure out which block is immediately after the current one. 1635 MachineFunction::iterator BBI = CR.CaseBB; 1636 ++BBI; 1637 1638 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1639 1640 // Create a new basic block to hold the code for loading the address 1641 // of the jump table, and jumping to it. Update successor information; 1642 // we will either branch to the default case for the switch, or the jump 1643 // table. 1644 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1645 CurMF->insert(BBI, JumpTableBB); 1646 CR.CaseBB->addSuccessor(Default); 1647 CR.CaseBB->addSuccessor(JumpTableBB); 1648 1649 // Build a vector of destination BBs, corresponding to each target 1650 // of the jump table. If the value of the jump table slot corresponds to 1651 // a case statement, push the case's BB onto the vector, otherwise, push 1652 // the default BB. 1653 std::vector<MachineBasicBlock*> DestBBs; 1654 APInt TEI = First; 1655 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1656 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 1657 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 1658 1659 if (Low.sle(TEI) && TEI.sle(High)) { 1660 DestBBs.push_back(I->BB); 1661 if (TEI==High) 1662 ++I; 1663 } else { 1664 DestBBs.push_back(Default); 1665 } 1666 } 1667 1668 // Update successor info. Add one edge to each unique successor. 1669 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1670 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1671 E = DestBBs.end(); I != E; ++I) { 1672 if (!SuccsHandled[(*I)->getNumber()]) { 1673 SuccsHandled[(*I)->getNumber()] = true; 1674 JumpTableBB->addSuccessor(*I); 1675 } 1676 } 1677 1678 // Create a jump table index for this jump table. 1679 unsigned JTEncoding = TLI.getJumpTableEncoding(); 1680 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 1681 ->createJumpTableIndex(DestBBs); 1682 1683 // Set the jump table information so that we can codegen it as a second 1684 // MachineBasicBlock 1685 JumpTable JT(-1U, JTI, JumpTableBB, Default); 1686 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB)); 1687 if (CR.CaseBB == CurMBB) 1688 visitJumpTableHeader(JT, JTH); 1689 1690 JTCases.push_back(JumpTableBlock(JTH, JT)); 1691 1692 return true; 1693} 1694 1695/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1696/// 2 subtrees. 1697bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 1698 CaseRecVector& WorkList, 1699 Value* SV, 1700 MachineBasicBlock* Default) { 1701 // Get the MachineFunction which holds the current MBB. This is used when 1702 // inserting any additional MBBs necessary to represent the switch. 1703 MachineFunction *CurMF = FuncInfo.MF; 1704 1705 // Figure out which block is immediately after the current one. 1706 MachineFunction::iterator BBI = CR.CaseBB; 1707 ++BBI; 1708 1709 Case& FrontCase = *CR.Range.first; 1710 Case& BackCase = *(CR.Range.second-1); 1711 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1712 1713 // Size is the number of Cases represented by this range. 1714 unsigned Size = CR.Range.second - CR.Range.first; 1715 1716 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1717 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1718 double FMetric = 0; 1719 CaseItr Pivot = CR.Range.first + Size/2; 1720 1721 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1722 // (heuristically) allow us to emit JumpTable's later. 1723 APInt TSize(First.getBitWidth(), 0); 1724 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1725 I!=E; ++I) 1726 TSize += I->size(); 1727 1728 APInt LSize = FrontCase.size(); 1729 APInt RSize = TSize-LSize; 1730 DEBUG(dbgs() << "Selecting best pivot: \n" 1731 << "First: " << First << ", Last: " << Last <<'\n' 1732 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 1733 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1734 J!=E; ++I, ++J) { 1735 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 1736 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 1737 APInt Range = ComputeRange(LEnd, RBegin); 1738 assert((Range - 2ULL).isNonNegative() && 1739 "Invalid case distance"); 1740 double LDensity = (double)LSize.roundToDouble() / 1741 (LEnd - First + 1ULL).roundToDouble(); 1742 double RDensity = (double)RSize.roundToDouble() / 1743 (Last - RBegin + 1ULL).roundToDouble(); 1744 double Metric = Range.logBase2()*(LDensity+RDensity); 1745 // Should always split in some non-trivial place 1746 DEBUG(dbgs() <<"=>Step\n" 1747 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 1748 << "LDensity: " << LDensity 1749 << ", RDensity: " << RDensity << '\n' 1750 << "Metric: " << Metric << '\n'); 1751 if (FMetric < Metric) { 1752 Pivot = J; 1753 FMetric = Metric; 1754 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 1755 } 1756 1757 LSize += J->size(); 1758 RSize -= J->size(); 1759 } 1760 if (areJTsAllowed(TLI)) { 1761 // If our case is dense we *really* should handle it earlier! 1762 assert((FMetric > 0) && "Should handle dense range earlier!"); 1763 } else { 1764 Pivot = CR.Range.first + Size/2; 1765 } 1766 1767 CaseRange LHSR(CR.Range.first, Pivot); 1768 CaseRange RHSR(Pivot, CR.Range.second); 1769 Constant *C = Pivot->Low; 1770 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1771 1772 // We know that we branch to the LHS if the Value being switched on is 1773 // less than the Pivot value, C. We use this to optimize our binary 1774 // tree a bit, by recognizing that if SV is greater than or equal to the 1775 // LHS's Case Value, and that Case Value is exactly one less than the 1776 // Pivot's Value, then we can branch directly to the LHS's Target, 1777 // rather than creating a leaf node for it. 1778 if ((LHSR.second - LHSR.first) == 1 && 1779 LHSR.first->High == CR.GE && 1780 cast<ConstantInt>(C)->getValue() == 1781 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 1782 TrueBB = LHSR.first->BB; 1783 } else { 1784 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1785 CurMF->insert(BBI, TrueBB); 1786 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1787 1788 // Put SV in a virtual register to make it available from the new blocks. 1789 ExportFromCurrentBlock(SV); 1790 } 1791 1792 // Similar to the optimization above, if the Value being switched on is 1793 // known to be less than the Constant CR.LT, and the current Case Value 1794 // is CR.LT - 1, then we can branch directly to the target block for 1795 // the current Case Value, rather than emitting a RHS leaf node for it. 1796 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1797 cast<ConstantInt>(RHSR.first->Low)->getValue() == 1798 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 1799 FalseBB = RHSR.first->BB; 1800 } else { 1801 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1802 CurMF->insert(BBI, FalseBB); 1803 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1804 1805 // Put SV in a virtual register to make it available from the new blocks. 1806 ExportFromCurrentBlock(SV); 1807 } 1808 1809 // Create a CaseBlock record representing a conditional branch to 1810 // the LHS node if the value being switched on SV is less than C. 1811 // Otherwise, branch to LHS. 1812 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 1813 1814 if (CR.CaseBB == CurMBB) 1815 visitSwitchCase(CB); 1816 else 1817 SwitchCases.push_back(CB); 1818 1819 return true; 1820} 1821 1822/// handleBitTestsSwitchCase - if current case range has few destination and 1823/// range span less, than machine word bitwidth, encode case range into series 1824/// of masks and emit bit tests with these masks. 1825bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 1826 CaseRecVector& WorkList, 1827 Value* SV, 1828 MachineBasicBlock* Default){ 1829 EVT PTy = TLI.getPointerTy(); 1830 unsigned IntPtrBits = PTy.getSizeInBits(); 1831 1832 Case& FrontCase = *CR.Range.first; 1833 Case& BackCase = *(CR.Range.second-1); 1834 1835 // Get the MachineFunction which holds the current MBB. This is used when 1836 // inserting any additional MBBs necessary to represent the switch. 1837 MachineFunction *CurMF = FuncInfo.MF; 1838 1839 // If target does not have legal shift left, do not emit bit tests at all. 1840 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 1841 return false; 1842 1843 size_t numCmps = 0; 1844 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1845 I!=E; ++I) { 1846 // Single case counts one, case range - two. 1847 numCmps += (I->Low == I->High ? 1 : 2); 1848 } 1849 1850 // Count unique destinations 1851 SmallSet<MachineBasicBlock*, 4> Dests; 1852 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1853 Dests.insert(I->BB); 1854 if (Dests.size() > 3) 1855 // Don't bother the code below, if there are too much unique destinations 1856 return false; 1857 } 1858 DEBUG(dbgs() << "Total number of unique destinations: " 1859 << Dests.size() << '\n' 1860 << "Total number of comparisons: " << numCmps << '\n'); 1861 1862 // Compute span of values. 1863 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 1864 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 1865 APInt cmpRange = maxValue - minValue; 1866 1867 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 1868 << "Low bound: " << minValue << '\n' 1869 << "High bound: " << maxValue << '\n'); 1870 1871 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) || 1872 (!(Dests.size() == 1 && numCmps >= 3) && 1873 !(Dests.size() == 2 && numCmps >= 5) && 1874 !(Dests.size() >= 3 && numCmps >= 6))) 1875 return false; 1876 1877 DEBUG(dbgs() << "Emitting bit tests\n"); 1878 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 1879 1880 // Optimize the case where all the case values fit in a 1881 // word without having to subtract minValue. In this case, 1882 // we can optimize away the subtraction. 1883 if (minValue.isNonNegative() && 1884 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) { 1885 cmpRange = maxValue; 1886 } else { 1887 lowBound = minValue; 1888 } 1889 1890 CaseBitsVector CasesBits; 1891 unsigned i, count = 0; 1892 1893 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1894 MachineBasicBlock* Dest = I->BB; 1895 for (i = 0; i < count; ++i) 1896 if (Dest == CasesBits[i].BB) 1897 break; 1898 1899 if (i == count) { 1900 assert((count < 3) && "Too much destinations to test!"); 1901 CasesBits.push_back(CaseBits(0, Dest, 0)); 1902 count++; 1903 } 1904 1905 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 1906 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 1907 1908 uint64_t lo = (lowValue - lowBound).getZExtValue(); 1909 uint64_t hi = (highValue - lowBound).getZExtValue(); 1910 1911 for (uint64_t j = lo; j <= hi; j++) { 1912 CasesBits[i].Mask |= 1ULL << j; 1913 CasesBits[i].Bits++; 1914 } 1915 1916 } 1917 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1918 1919 BitTestInfo BTC; 1920 1921 // Figure out which block is immediately after the current one. 1922 MachineFunction::iterator BBI = CR.CaseBB; 1923 ++BBI; 1924 1925 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1926 1927 DEBUG(dbgs() << "Cases:\n"); 1928 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1929 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 1930 << ", Bits: " << CasesBits[i].Bits 1931 << ", BB: " << CasesBits[i].BB << '\n'); 1932 1933 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1934 CurMF->insert(BBI, CaseBB); 1935 BTC.push_back(BitTestCase(CasesBits[i].Mask, 1936 CaseBB, 1937 CasesBits[i].BB)); 1938 1939 // Put SV in a virtual register to make it available from the new blocks. 1940 ExportFromCurrentBlock(SV); 1941 } 1942 1943 BitTestBlock BTB(lowBound, cmpRange, SV, 1944 -1U, (CR.CaseBB == CurMBB), 1945 CR.CaseBB, Default, BTC); 1946 1947 if (CR.CaseBB == CurMBB) 1948 visitBitTestHeader(BTB); 1949 1950 BitTestCases.push_back(BTB); 1951 1952 return true; 1953} 1954 1955/// Clusterify - Transform simple list of Cases into list of CaseRange's 1956size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 1957 const SwitchInst& SI) { 1958 size_t numCmps = 0; 1959 1960 // Start with "simple" cases 1961 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 1962 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1963 Cases.push_back(Case(SI.getSuccessorValue(i), 1964 SI.getSuccessorValue(i), 1965 SMBB)); 1966 } 1967 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 1968 1969 // Merge case into clusters 1970 if (Cases.size() >= 2) 1971 // Must recompute end() each iteration because it may be 1972 // invalidated by erase if we hold on to it 1973 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) { 1974 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 1975 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 1976 MachineBasicBlock* nextBB = J->BB; 1977 MachineBasicBlock* currentBB = I->BB; 1978 1979 // If the two neighboring cases go to the same destination, merge them 1980 // into a single case. 1981 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 1982 I->High = J->High; 1983 J = Cases.erase(J); 1984 } else { 1985 I = J++; 1986 } 1987 } 1988 1989 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1990 if (I->Low != I->High) 1991 // A range counts double, since it requires two compares. 1992 ++numCmps; 1993 } 1994 1995 return numCmps; 1996} 1997 1998void SelectionDAGBuilder::visitSwitch(SwitchInst &SI) { 1999 // Figure out which block is immediately after the current one. 2000 MachineBasicBlock *NextBlock = 0; 2001 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2002 2003 // If there is only the default destination, branch to it if it is not the 2004 // next basic block. Otherwise, just fall through. 2005 if (SI.getNumOperands() == 2) { 2006 // Update machine-CFG edges. 2007 2008 // If this is not a fall-through branch, emit the branch. 2009 CurMBB->addSuccessor(Default); 2010 if (Default != NextBlock) 2011 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2012 MVT::Other, getControlRoot(), 2013 DAG.getBasicBlock(Default))); 2014 2015 return; 2016 } 2017 2018 // If there are any non-default case statements, create a vector of Cases 2019 // representing each one, and sort the vector so that we can efficiently 2020 // create a binary search tree from them. 2021 CaseVector Cases; 2022 size_t numCmps = Clusterify(Cases, SI); 2023 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2024 << ". Total compares: " << numCmps << '\n'); 2025 numCmps = 0; 2026 2027 // Get the Value to be switched on and default basic blocks, which will be 2028 // inserted into CaseBlock records, representing basic blocks in the binary 2029 // search tree. 2030 Value *SV = SI.getOperand(0); 2031 2032 // Push the initial CaseRec onto the worklist 2033 CaseRecVector WorkList; 2034 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 2035 2036 while (!WorkList.empty()) { 2037 // Grab a record representing a case range to process off the worklist 2038 CaseRec CR = WorkList.back(); 2039 WorkList.pop_back(); 2040 2041 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 2042 continue; 2043 2044 // If the range has few cases (two or less) emit a series of specific 2045 // tests. 2046 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 2047 continue; 2048 2049 // If the switch has more than 5 blocks, and at least 40% dense, and the 2050 // target supports indirect branches, then emit a jump table rather than 2051 // lowering the switch to a binary tree of conditional branches. 2052 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 2053 continue; 2054 2055 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2056 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2057 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 2058 } 2059} 2060 2061void SelectionDAGBuilder::visitIndirectBr(IndirectBrInst &I) { 2062 // Update machine-CFG edges with unique successors. 2063 SmallVector<BasicBlock*, 32> succs; 2064 succs.reserve(I.getNumSuccessors()); 2065 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2066 succs.push_back(I.getSuccessor(i)); 2067 array_pod_sort(succs.begin(), succs.end()); 2068 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2069 for (unsigned i = 0, e = succs.size(); i != e; ++i) 2070 CurMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]); 2071 2072 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2073 MVT::Other, getControlRoot(), 2074 getValue(I.getAddress()))); 2075} 2076 2077void SelectionDAGBuilder::visitFSub(User &I) { 2078 // -0.0 - X --> fneg 2079 const Type *Ty = I.getType(); 2080 if (Ty->isVectorTy()) { 2081 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2082 const VectorType *DestTy = cast<VectorType>(I.getType()); 2083 const Type *ElTy = DestTy->getElementType(); 2084 unsigned VL = DestTy->getNumElements(); 2085 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2086 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2087 if (CV == CNZ) { 2088 SDValue Op2 = getValue(I.getOperand(1)); 2089 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2090 Op2.getValueType(), Op2)); 2091 return; 2092 } 2093 } 2094 } 2095 2096 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2097 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2098 SDValue Op2 = getValue(I.getOperand(1)); 2099 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2100 Op2.getValueType(), Op2)); 2101 return; 2102 } 2103 2104 visitBinary(I, ISD::FSUB); 2105} 2106 2107void SelectionDAGBuilder::visitBinary(User &I, unsigned OpCode) { 2108 SDValue Op1 = getValue(I.getOperand(0)); 2109 SDValue Op2 = getValue(I.getOperand(1)); 2110 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2111 Op1.getValueType(), Op1, Op2)); 2112} 2113 2114void SelectionDAGBuilder::visitShift(User &I, unsigned Opcode) { 2115 SDValue Op1 = getValue(I.getOperand(0)); 2116 SDValue Op2 = getValue(I.getOperand(1)); 2117 if (!I.getType()->isVectorTy() && 2118 Op2.getValueType() != TLI.getShiftAmountTy()) { 2119 // If the operand is smaller than the shift count type, promote it. 2120 EVT PTy = TLI.getPointerTy(); 2121 EVT STy = TLI.getShiftAmountTy(); 2122 if (STy.bitsGT(Op2.getValueType())) 2123 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2124 TLI.getShiftAmountTy(), Op2); 2125 // If the operand is larger than the shift count type but the shift 2126 // count type has enough bits to represent any shift value, truncate 2127 // it now. This is a common case and it exposes the truncate to 2128 // optimization early. 2129 else if (STy.getSizeInBits() >= 2130 Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2131 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2132 TLI.getShiftAmountTy(), Op2); 2133 // Otherwise we'll need to temporarily settle for some other 2134 // convenient type; type legalization will make adjustments as 2135 // needed. 2136 else if (PTy.bitsLT(Op2.getValueType())) 2137 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2138 TLI.getPointerTy(), Op2); 2139 else if (PTy.bitsGT(Op2.getValueType())) 2140 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2141 TLI.getPointerTy(), Op2); 2142 } 2143 2144 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2145 Op1.getValueType(), Op1, Op2)); 2146} 2147 2148void SelectionDAGBuilder::visitICmp(User &I) { 2149 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2150 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2151 predicate = IC->getPredicate(); 2152 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2153 predicate = ICmpInst::Predicate(IC->getPredicate()); 2154 SDValue Op1 = getValue(I.getOperand(0)); 2155 SDValue Op2 = getValue(I.getOperand(1)); 2156 ISD::CondCode Opcode = getICmpCondCode(predicate); 2157 2158 EVT DestVT = TLI.getValueType(I.getType()); 2159 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2160} 2161 2162void SelectionDAGBuilder::visitFCmp(User &I) { 2163 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2164 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2165 predicate = FC->getPredicate(); 2166 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2167 predicate = FCmpInst::Predicate(FC->getPredicate()); 2168 SDValue Op1 = getValue(I.getOperand(0)); 2169 SDValue Op2 = getValue(I.getOperand(1)); 2170 ISD::CondCode Condition = getFCmpCondCode(predicate); 2171 EVT DestVT = TLI.getValueType(I.getType()); 2172 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2173} 2174 2175void SelectionDAGBuilder::visitSelect(User &I) { 2176 SmallVector<EVT, 4> ValueVTs; 2177 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2178 unsigned NumValues = ValueVTs.size(); 2179 if (NumValues == 0) return; 2180 2181 SmallVector<SDValue, 4> Values(NumValues); 2182 SDValue Cond = getValue(I.getOperand(0)); 2183 SDValue TrueVal = getValue(I.getOperand(1)); 2184 SDValue FalseVal = getValue(I.getOperand(2)); 2185 2186 for (unsigned i = 0; i != NumValues; ++i) 2187 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2188 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2189 Cond, 2190 SDValue(TrueVal.getNode(), 2191 TrueVal.getResNo() + i), 2192 SDValue(FalseVal.getNode(), 2193 FalseVal.getResNo() + i)); 2194 2195 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2196 DAG.getVTList(&ValueVTs[0], NumValues), 2197 &Values[0], NumValues)); 2198} 2199 2200void SelectionDAGBuilder::visitTrunc(User &I) { 2201 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2202 SDValue N = getValue(I.getOperand(0)); 2203 EVT DestVT = TLI.getValueType(I.getType()); 2204 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2205} 2206 2207void SelectionDAGBuilder::visitZExt(User &I) { 2208 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2209 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2210 SDValue N = getValue(I.getOperand(0)); 2211 EVT DestVT = TLI.getValueType(I.getType()); 2212 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2213} 2214 2215void SelectionDAGBuilder::visitSExt(User &I) { 2216 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2217 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2218 SDValue N = getValue(I.getOperand(0)); 2219 EVT DestVT = TLI.getValueType(I.getType()); 2220 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2221} 2222 2223void SelectionDAGBuilder::visitFPTrunc(User &I) { 2224 // FPTrunc is never a no-op cast, no need to check 2225 SDValue N = getValue(I.getOperand(0)); 2226 EVT DestVT = TLI.getValueType(I.getType()); 2227 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2228 DestVT, N, DAG.getIntPtrConstant(0))); 2229} 2230 2231void SelectionDAGBuilder::visitFPExt(User &I){ 2232 // FPTrunc is never a no-op cast, no need to check 2233 SDValue N = getValue(I.getOperand(0)); 2234 EVT DestVT = TLI.getValueType(I.getType()); 2235 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2236} 2237 2238void SelectionDAGBuilder::visitFPToUI(User &I) { 2239 // FPToUI is never a no-op cast, no need to check 2240 SDValue N = getValue(I.getOperand(0)); 2241 EVT DestVT = TLI.getValueType(I.getType()); 2242 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2243} 2244 2245void SelectionDAGBuilder::visitFPToSI(User &I) { 2246 // FPToSI is never a no-op cast, no need to check 2247 SDValue N = getValue(I.getOperand(0)); 2248 EVT DestVT = TLI.getValueType(I.getType()); 2249 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2250} 2251 2252void SelectionDAGBuilder::visitUIToFP(User &I) { 2253 // UIToFP is never a no-op cast, no need to check 2254 SDValue N = getValue(I.getOperand(0)); 2255 EVT DestVT = TLI.getValueType(I.getType()); 2256 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2257} 2258 2259void SelectionDAGBuilder::visitSIToFP(User &I){ 2260 // SIToFP is never a no-op cast, no need to check 2261 SDValue N = getValue(I.getOperand(0)); 2262 EVT DestVT = TLI.getValueType(I.getType()); 2263 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2264} 2265 2266void SelectionDAGBuilder::visitPtrToInt(User &I) { 2267 // What to do depends on the size of the integer and the size of the pointer. 2268 // We can either truncate, zero extend, or no-op, accordingly. 2269 SDValue N = getValue(I.getOperand(0)); 2270 EVT SrcVT = N.getValueType(); 2271 EVT DestVT = TLI.getValueType(I.getType()); 2272 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2273} 2274 2275void SelectionDAGBuilder::visitIntToPtr(User &I) { 2276 // What to do depends on the size of the integer and the size of the pointer. 2277 // We can either truncate, zero extend, or no-op, accordingly. 2278 SDValue N = getValue(I.getOperand(0)); 2279 EVT SrcVT = N.getValueType(); 2280 EVT DestVT = TLI.getValueType(I.getType()); 2281 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2282} 2283 2284void SelectionDAGBuilder::visitBitCast(User &I) { 2285 SDValue N = getValue(I.getOperand(0)); 2286 EVT DestVT = TLI.getValueType(I.getType()); 2287 2288 // BitCast assures us that source and destination are the same size so this is 2289 // either a BIT_CONVERT or a no-op. 2290 if (DestVT != N.getValueType()) 2291 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 2292 DestVT, N)); // convert types. 2293 else 2294 setValue(&I, N); // noop cast. 2295} 2296 2297void SelectionDAGBuilder::visitInsertElement(User &I) { 2298 SDValue InVec = getValue(I.getOperand(0)); 2299 SDValue InVal = getValue(I.getOperand(1)); 2300 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2301 TLI.getPointerTy(), 2302 getValue(I.getOperand(2))); 2303 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2304 TLI.getValueType(I.getType()), 2305 InVec, InVal, InIdx)); 2306} 2307 2308void SelectionDAGBuilder::visitExtractElement(User &I) { 2309 SDValue InVec = getValue(I.getOperand(0)); 2310 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2311 TLI.getPointerTy(), 2312 getValue(I.getOperand(1))); 2313 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2314 TLI.getValueType(I.getType()), InVec, InIdx)); 2315} 2316 2317// Utility for visitShuffleVector - Returns true if the mask is mask starting 2318// from SIndx and increasing to the element length (undefs are allowed). 2319static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2320 unsigned MaskNumElts = Mask.size(); 2321 for (unsigned i = 0; i != MaskNumElts; ++i) 2322 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2323 return false; 2324 return true; 2325} 2326 2327void SelectionDAGBuilder::visitShuffleVector(User &I) { 2328 SmallVector<int, 8> Mask; 2329 SDValue Src1 = getValue(I.getOperand(0)); 2330 SDValue Src2 = getValue(I.getOperand(1)); 2331 2332 // Convert the ConstantVector mask operand into an array of ints, with -1 2333 // representing undef values. 2334 SmallVector<Constant*, 8> MaskElts; 2335 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2336 unsigned MaskNumElts = MaskElts.size(); 2337 for (unsigned i = 0; i != MaskNumElts; ++i) { 2338 if (isa<UndefValue>(MaskElts[i])) 2339 Mask.push_back(-1); 2340 else 2341 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2342 } 2343 2344 EVT VT = TLI.getValueType(I.getType()); 2345 EVT SrcVT = Src1.getValueType(); 2346 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2347 2348 if (SrcNumElts == MaskNumElts) { 2349 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2350 &Mask[0])); 2351 return; 2352 } 2353 2354 // Normalize the shuffle vector since mask and vector length don't match. 2355 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2356 // Mask is longer than the source vectors and is a multiple of the source 2357 // vectors. We can use concatenate vector to make the mask and vectors 2358 // lengths match. 2359 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2360 // The shuffle is concatenating two vectors together. 2361 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2362 VT, Src1, Src2)); 2363 return; 2364 } 2365 2366 // Pad both vectors with undefs to make them the same length as the mask. 2367 unsigned NumConcat = MaskNumElts / SrcNumElts; 2368 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2369 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2370 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2371 2372 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2373 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2374 MOps1[0] = Src1; 2375 MOps2[0] = Src2; 2376 2377 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2378 getCurDebugLoc(), VT, 2379 &MOps1[0], NumConcat); 2380 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2381 getCurDebugLoc(), VT, 2382 &MOps2[0], NumConcat); 2383 2384 // Readjust mask for new input vector length. 2385 SmallVector<int, 8> MappedOps; 2386 for (unsigned i = 0; i != MaskNumElts; ++i) { 2387 int Idx = Mask[i]; 2388 if (Idx < (int)SrcNumElts) 2389 MappedOps.push_back(Idx); 2390 else 2391 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2392 } 2393 2394 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2395 &MappedOps[0])); 2396 return; 2397 } 2398 2399 if (SrcNumElts > MaskNumElts) { 2400 // Analyze the access pattern of the vector to see if we can extract 2401 // two subvectors and do the shuffle. The analysis is done by calculating 2402 // the range of elements the mask access on both vectors. 2403 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2404 int MaxRange[2] = {-1, -1}; 2405 2406 for (unsigned i = 0; i != MaskNumElts; ++i) { 2407 int Idx = Mask[i]; 2408 int Input = 0; 2409 if (Idx < 0) 2410 continue; 2411 2412 if (Idx >= (int)SrcNumElts) { 2413 Input = 1; 2414 Idx -= SrcNumElts; 2415 } 2416 if (Idx > MaxRange[Input]) 2417 MaxRange[Input] = Idx; 2418 if (Idx < MinRange[Input]) 2419 MinRange[Input] = Idx; 2420 } 2421 2422 // Check if the access is smaller than the vector size and can we find 2423 // a reasonable extract index. 2424 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2425 // Extract. 2426 int StartIdx[2]; // StartIdx to extract from 2427 for (int Input=0; Input < 2; ++Input) { 2428 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2429 RangeUse[Input] = 0; // Unused 2430 StartIdx[Input] = 0; 2431 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2432 // Fits within range but we should see if we can find a good 2433 // start index that is a multiple of the mask length. 2434 if (MaxRange[Input] < (int)MaskNumElts) { 2435 RangeUse[Input] = 1; // Extract from beginning of the vector 2436 StartIdx[Input] = 0; 2437 } else { 2438 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2439 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2440 StartIdx[Input] + MaskNumElts < SrcNumElts) 2441 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2442 } 2443 } 2444 } 2445 2446 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2447 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2448 return; 2449 } 2450 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2451 // Extract appropriate subvector and generate a vector shuffle 2452 for (int Input=0; Input < 2; ++Input) { 2453 SDValue &Src = Input == 0 ? Src1 : Src2; 2454 if (RangeUse[Input] == 0) 2455 Src = DAG.getUNDEF(VT); 2456 else 2457 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2458 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2459 } 2460 2461 // Calculate new mask. 2462 SmallVector<int, 8> MappedOps; 2463 for (unsigned i = 0; i != MaskNumElts; ++i) { 2464 int Idx = Mask[i]; 2465 if (Idx < 0) 2466 MappedOps.push_back(Idx); 2467 else if (Idx < (int)SrcNumElts) 2468 MappedOps.push_back(Idx - StartIdx[0]); 2469 else 2470 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2471 } 2472 2473 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2474 &MappedOps[0])); 2475 return; 2476 } 2477 } 2478 2479 // We can't use either concat vectors or extract subvectors so fall back to 2480 // replacing the shuffle with extract and build vector. 2481 // to insert and build vector. 2482 EVT EltVT = VT.getVectorElementType(); 2483 EVT PtrVT = TLI.getPointerTy(); 2484 SmallVector<SDValue,8> Ops; 2485 for (unsigned i = 0; i != MaskNumElts; ++i) { 2486 if (Mask[i] < 0) { 2487 Ops.push_back(DAG.getUNDEF(EltVT)); 2488 } else { 2489 int Idx = Mask[i]; 2490 SDValue Res; 2491 2492 if (Idx < (int)SrcNumElts) 2493 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2494 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2495 else 2496 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2497 EltVT, Src2, 2498 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2499 2500 Ops.push_back(Res); 2501 } 2502 } 2503 2504 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2505 VT, &Ops[0], Ops.size())); 2506} 2507 2508void SelectionDAGBuilder::visitInsertValue(InsertValueInst &I) { 2509 const Value *Op0 = I.getOperand(0); 2510 const Value *Op1 = I.getOperand(1); 2511 const Type *AggTy = I.getType(); 2512 const Type *ValTy = Op1->getType(); 2513 bool IntoUndef = isa<UndefValue>(Op0); 2514 bool FromUndef = isa<UndefValue>(Op1); 2515 2516 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2517 I.idx_begin(), I.idx_end()); 2518 2519 SmallVector<EVT, 4> AggValueVTs; 2520 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2521 SmallVector<EVT, 4> ValValueVTs; 2522 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2523 2524 unsigned NumAggValues = AggValueVTs.size(); 2525 unsigned NumValValues = ValValueVTs.size(); 2526 SmallVector<SDValue, 4> Values(NumAggValues); 2527 2528 SDValue Agg = getValue(Op0); 2529 SDValue Val = getValue(Op1); 2530 unsigned i = 0; 2531 // Copy the beginning value(s) from the original aggregate. 2532 for (; i != LinearIndex; ++i) 2533 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2534 SDValue(Agg.getNode(), Agg.getResNo() + i); 2535 // Copy values from the inserted value(s). 2536 for (; i != LinearIndex + NumValValues; ++i) 2537 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2538 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2539 // Copy remaining value(s) from the original aggregate. 2540 for (; i != NumAggValues; ++i) 2541 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2542 SDValue(Agg.getNode(), Agg.getResNo() + i); 2543 2544 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2545 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2546 &Values[0], NumAggValues)); 2547} 2548 2549void SelectionDAGBuilder::visitExtractValue(ExtractValueInst &I) { 2550 const Value *Op0 = I.getOperand(0); 2551 const Type *AggTy = Op0->getType(); 2552 const Type *ValTy = I.getType(); 2553 bool OutOfUndef = isa<UndefValue>(Op0); 2554 2555 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2556 I.idx_begin(), I.idx_end()); 2557 2558 SmallVector<EVT, 4> ValValueVTs; 2559 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2560 2561 unsigned NumValValues = ValValueVTs.size(); 2562 SmallVector<SDValue, 4> Values(NumValValues); 2563 2564 SDValue Agg = getValue(Op0); 2565 // Copy out the selected value(s). 2566 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2567 Values[i - LinearIndex] = 2568 OutOfUndef ? 2569 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2570 SDValue(Agg.getNode(), Agg.getResNo() + i); 2571 2572 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2573 DAG.getVTList(&ValValueVTs[0], NumValValues), 2574 &Values[0], NumValValues)); 2575} 2576 2577void SelectionDAGBuilder::visitGetElementPtr(User &I) { 2578 SDValue N = getValue(I.getOperand(0)); 2579 const Type *Ty = I.getOperand(0)->getType(); 2580 2581 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2582 OI != E; ++OI) { 2583 Value *Idx = *OI; 2584 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2585 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2586 if (Field) { 2587 // N = N + Offset 2588 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2589 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2590 DAG.getIntPtrConstant(Offset)); 2591 } 2592 2593 Ty = StTy->getElementType(Field); 2594 } else if (const UnionType *UnTy = dyn_cast<UnionType>(Ty)) { 2595 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2596 2597 // Offset canonically 0 for unions, but type changes 2598 Ty = UnTy->getElementType(Field); 2599 } else { 2600 Ty = cast<SequentialType>(Ty)->getElementType(); 2601 2602 // If this is a constant subscript, handle it quickly. 2603 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2604 if (CI->getZExtValue() == 0) continue; 2605 uint64_t Offs = 2606 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2607 SDValue OffsVal; 2608 EVT PTy = TLI.getPointerTy(); 2609 unsigned PtrBits = PTy.getSizeInBits(); 2610 if (PtrBits < 64) 2611 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2612 TLI.getPointerTy(), 2613 DAG.getConstant(Offs, MVT::i64)); 2614 else 2615 OffsVal = DAG.getIntPtrConstant(Offs); 2616 2617 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2618 OffsVal); 2619 continue; 2620 } 2621 2622 // N = N + Idx * ElementSize; 2623 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2624 TD->getTypeAllocSize(Ty)); 2625 SDValue IdxN = getValue(Idx); 2626 2627 // If the index is smaller or larger than intptr_t, truncate or extend 2628 // it. 2629 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2630 2631 // If this is a multiply by a power of two, turn it into a shl 2632 // immediately. This is a very common case. 2633 if (ElementSize != 1) { 2634 if (ElementSize.isPowerOf2()) { 2635 unsigned Amt = ElementSize.logBase2(); 2636 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2637 N.getValueType(), IdxN, 2638 DAG.getConstant(Amt, TLI.getPointerTy())); 2639 } else { 2640 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2641 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2642 N.getValueType(), IdxN, Scale); 2643 } 2644 } 2645 2646 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2647 N.getValueType(), N, IdxN); 2648 } 2649 } 2650 2651 setValue(&I, N); 2652} 2653 2654void SelectionDAGBuilder::visitAlloca(AllocaInst &I) { 2655 // If this is a fixed sized alloca in the entry block of the function, 2656 // allocate it statically on the stack. 2657 if (FuncInfo.StaticAllocaMap.count(&I)) 2658 return; // getValue will auto-populate this. 2659 2660 const Type *Ty = I.getAllocatedType(); 2661 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 2662 unsigned Align = 2663 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2664 I.getAlignment()); 2665 2666 SDValue AllocSize = getValue(I.getArraySize()); 2667 2668 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(), 2669 AllocSize, 2670 DAG.getConstant(TySize, AllocSize.getValueType())); 2671 2672 EVT IntPtr = TLI.getPointerTy(); 2673 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 2674 2675 // Handle alignment. If the requested alignment is less than or equal to 2676 // the stack alignment, ignore it. If the size is greater than or equal to 2677 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2678 unsigned StackAlign = 2679 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2680 if (Align <= StackAlign) 2681 Align = 0; 2682 2683 // Round the size of the allocation up to the stack alignment size 2684 // by add SA-1 to the size. 2685 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2686 AllocSize.getValueType(), AllocSize, 2687 DAG.getIntPtrConstant(StackAlign-1)); 2688 2689 // Mask out the low bits for alignment purposes. 2690 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 2691 AllocSize.getValueType(), AllocSize, 2692 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2693 2694 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2695 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 2696 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 2697 VTs, Ops, 3); 2698 setValue(&I, DSA); 2699 DAG.setRoot(DSA.getValue(1)); 2700 2701 // Inform the Frame Information that we have just allocated a variable-sized 2702 // object. 2703 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(); 2704} 2705 2706void SelectionDAGBuilder::visitLoad(LoadInst &I) { 2707 const Value *SV = I.getOperand(0); 2708 SDValue Ptr = getValue(SV); 2709 2710 const Type *Ty = I.getType(); 2711 2712 bool isVolatile = I.isVolatile(); 2713 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2714 unsigned Alignment = I.getAlignment(); 2715 2716 SmallVector<EVT, 4> ValueVTs; 2717 SmallVector<uint64_t, 4> Offsets; 2718 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2719 unsigned NumValues = ValueVTs.size(); 2720 if (NumValues == 0) 2721 return; 2722 2723 SDValue Root; 2724 bool ConstantMemory = false; 2725 if (I.isVolatile()) 2726 // Serialize volatile loads with other side effects. 2727 Root = getRoot(); 2728 else if (AA->pointsToConstantMemory(SV)) { 2729 // Do not serialize (non-volatile) loads of constant memory with anything. 2730 Root = DAG.getEntryNode(); 2731 ConstantMemory = true; 2732 } else { 2733 // Do not serialize non-volatile loads against each other. 2734 Root = DAG.getRoot(); 2735 } 2736 2737 SmallVector<SDValue, 4> Values(NumValues); 2738 SmallVector<SDValue, 4> Chains(NumValues); 2739 EVT PtrVT = Ptr.getValueType(); 2740 for (unsigned i = 0; i != NumValues; ++i) { 2741 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2742 PtrVT, Ptr, 2743 DAG.getConstant(Offsets[i], PtrVT)); 2744 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 2745 A, SV, Offsets[i], isVolatile, 2746 isNonTemporal, Alignment); 2747 2748 Values[i] = L; 2749 Chains[i] = L.getValue(1); 2750 } 2751 2752 if (!ConstantMemory) { 2753 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 2754 MVT::Other, &Chains[0], NumValues); 2755 if (isVolatile) 2756 DAG.setRoot(Chain); 2757 else 2758 PendingLoads.push_back(Chain); 2759 } 2760 2761 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2762 DAG.getVTList(&ValueVTs[0], NumValues), 2763 &Values[0], NumValues)); 2764} 2765 2766void SelectionDAGBuilder::visitStore(StoreInst &I) { 2767 Value *SrcV = I.getOperand(0); 2768 Value *PtrV = I.getOperand(1); 2769 2770 SmallVector<EVT, 4> ValueVTs; 2771 SmallVector<uint64_t, 4> Offsets; 2772 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 2773 unsigned NumValues = ValueVTs.size(); 2774 if (NumValues == 0) 2775 return; 2776 2777 // Get the lowered operands. Note that we do this after 2778 // checking if NumResults is zero, because with zero results 2779 // the operands won't have values in the map. 2780 SDValue Src = getValue(SrcV); 2781 SDValue Ptr = getValue(PtrV); 2782 2783 SDValue Root = getRoot(); 2784 SmallVector<SDValue, 4> Chains(NumValues); 2785 EVT PtrVT = Ptr.getValueType(); 2786 bool isVolatile = I.isVolatile(); 2787 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2788 unsigned Alignment = I.getAlignment(); 2789 2790 for (unsigned i = 0; i != NumValues; ++i) { 2791 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 2792 DAG.getConstant(Offsets[i], PtrVT)); 2793 Chains[i] = DAG.getStore(Root, getCurDebugLoc(), 2794 SDValue(Src.getNode(), Src.getResNo() + i), 2795 Add, PtrV, Offsets[i], isVolatile, 2796 isNonTemporal, Alignment); 2797 } 2798 2799 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 2800 MVT::Other, &Chains[0], NumValues)); 2801} 2802 2803/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2804/// node. 2805void SelectionDAGBuilder::visitTargetIntrinsic(CallInst &I, 2806 unsigned Intrinsic) { 2807 bool HasChain = !I.doesNotAccessMemory(); 2808 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 2809 2810 // Build the operand list. 2811 SmallVector<SDValue, 8> Ops; 2812 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2813 if (OnlyLoad) { 2814 // We don't need to serialize loads against other loads. 2815 Ops.push_back(DAG.getRoot()); 2816 } else { 2817 Ops.push_back(getRoot()); 2818 } 2819 } 2820 2821 // Info is set by getTgtMemInstrinsic 2822 TargetLowering::IntrinsicInfo Info; 2823 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 2824 2825 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 2826 if (!IsTgtIntrinsic) 2827 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2828 2829 // Add all operands of the call to the operand list. 2830 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2831 SDValue Op = getValue(I.getOperand(i)); 2832 assert(TLI.isTypeLegal(Op.getValueType()) && 2833 "Intrinsic uses a non-legal type?"); 2834 Ops.push_back(Op); 2835 } 2836 2837 SmallVector<EVT, 4> ValueVTs; 2838 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2839#ifndef NDEBUG 2840 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 2841 assert(TLI.isTypeLegal(ValueVTs[Val]) && 2842 "Intrinsic uses a non-legal type?"); 2843 } 2844#endif // NDEBUG 2845 2846 if (HasChain) 2847 ValueVTs.push_back(MVT::Other); 2848 2849 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 2850 2851 // Create the node. 2852 SDValue Result; 2853 if (IsTgtIntrinsic) { 2854 // This is target intrinsic that touches memory 2855 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 2856 VTs, &Ops[0], Ops.size(), 2857 Info.memVT, Info.ptrVal, Info.offset, 2858 Info.align, Info.vol, 2859 Info.readMem, Info.writeMem); 2860 } else if (!HasChain) { 2861 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 2862 VTs, &Ops[0], Ops.size()); 2863 } else if (!I.getType()->isVoidTy()) { 2864 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 2865 VTs, &Ops[0], Ops.size()); 2866 } else { 2867 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 2868 VTs, &Ops[0], Ops.size()); 2869 } 2870 2871 if (HasChain) { 2872 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 2873 if (OnlyLoad) 2874 PendingLoads.push_back(Chain); 2875 else 2876 DAG.setRoot(Chain); 2877 } 2878 2879 if (!I.getType()->isVoidTy()) { 2880 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2881 EVT VT = TLI.getValueType(PTy); 2882 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result); 2883 } 2884 2885 setValue(&I, Result); 2886 } 2887} 2888 2889/// GetSignificand - Get the significand and build it into a floating-point 2890/// number with exponent of 1: 2891/// 2892/// Op = (Op & 0x007fffff) | 0x3f800000; 2893/// 2894/// where Op is the hexidecimal representation of floating point value. 2895static SDValue 2896GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 2897 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 2898 DAG.getConstant(0x007fffff, MVT::i32)); 2899 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 2900 DAG.getConstant(0x3f800000, MVT::i32)); 2901 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2); 2902} 2903 2904/// GetExponent - Get the exponent: 2905/// 2906/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 2907/// 2908/// where Op is the hexidecimal representation of floating point value. 2909static SDValue 2910GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 2911 DebugLoc dl) { 2912 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 2913 DAG.getConstant(0x7f800000, MVT::i32)); 2914 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 2915 DAG.getConstant(23, TLI.getPointerTy())); 2916 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 2917 DAG.getConstant(127, MVT::i32)); 2918 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 2919} 2920 2921/// getF32Constant - Get 32-bit floating point constant. 2922static SDValue 2923getF32Constant(SelectionDAG &DAG, unsigned Flt) { 2924 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 2925} 2926 2927/// Inlined utility function to implement binary input atomic intrinsics for 2928/// visitIntrinsicCall: I is a call instruction 2929/// Op is the associated NodeType for I 2930const char * 2931SelectionDAGBuilder::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) { 2932 SDValue Root = getRoot(); 2933 SDValue L = 2934 DAG.getAtomic(Op, getCurDebugLoc(), 2935 getValue(I.getOperand(2)).getValueType().getSimpleVT(), 2936 Root, 2937 getValue(I.getOperand(1)), 2938 getValue(I.getOperand(2)), 2939 I.getOperand(1)); 2940 setValue(&I, L); 2941 DAG.setRoot(L.getValue(1)); 2942 return 0; 2943} 2944 2945// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 2946const char * 2947SelectionDAGBuilder::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) { 2948 SDValue Op1 = getValue(I.getOperand(1)); 2949 SDValue Op2 = getValue(I.getOperand(2)); 2950 2951 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 2952 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 2953 return 0; 2954} 2955 2956/// visitExp - Lower an exp intrinsic. Handles the special sequences for 2957/// limited-precision mode. 2958void 2959SelectionDAGBuilder::visitExp(CallInst &I) { 2960 SDValue result; 2961 DebugLoc dl = getCurDebugLoc(); 2962 2963 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 2964 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 2965 SDValue Op = getValue(I.getOperand(1)); 2966 2967 // Put the exponent in the right bit position for later addition to the 2968 // final result: 2969 // 2970 // #define LOG2OFe 1.4426950f 2971 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 2972 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 2973 getF32Constant(DAG, 0x3fb8aa3b)); 2974 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 2975 2976 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 2977 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 2978 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 2979 2980 // IntegerPartOfX <<= 23; 2981 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 2982 DAG.getConstant(23, TLI.getPointerTy())); 2983 2984 if (LimitFloatPrecision <= 6) { 2985 // For floating-point precision of 6: 2986 // 2987 // TwoToFractionalPartOfX = 2988 // 0.997535578f + 2989 // (0.735607626f + 0.252464424f * x) * x; 2990 // 2991 // error 0.0144103317, which is 6 bits 2992 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 2993 getF32Constant(DAG, 0x3e814304)); 2994 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 2995 getF32Constant(DAG, 0x3f3c50c8)); 2996 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 2997 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 2998 getF32Constant(DAG, 0x3f7f5e7e)); 2999 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5); 3000 3001 // Add the exponent into the result in integer domain. 3002 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3003 TwoToFracPartOfX, IntegerPartOfX); 3004 3005 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6); 3006 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3007 // For floating-point precision of 12: 3008 // 3009 // TwoToFractionalPartOfX = 3010 // 0.999892986f + 3011 // (0.696457318f + 3012 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3013 // 3014 // 0.000107046256 error, which is 13 to 14 bits 3015 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3016 getF32Constant(DAG, 0x3da235e3)); 3017 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3018 getF32Constant(DAG, 0x3e65b8f3)); 3019 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3020 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3021 getF32Constant(DAG, 0x3f324b07)); 3022 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3023 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3024 getF32Constant(DAG, 0x3f7ff8fd)); 3025 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7); 3026 3027 // Add the exponent into the result in integer domain. 3028 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3029 TwoToFracPartOfX, IntegerPartOfX); 3030 3031 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8); 3032 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3033 // For floating-point precision of 18: 3034 // 3035 // TwoToFractionalPartOfX = 3036 // 0.999999982f + 3037 // (0.693148872f + 3038 // (0.240227044f + 3039 // (0.554906021e-1f + 3040 // (0.961591928e-2f + 3041 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3042 // 3043 // error 2.47208000*10^(-7), which is better than 18 bits 3044 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3045 getF32Constant(DAG, 0x3924b03e)); 3046 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3047 getF32Constant(DAG, 0x3ab24b87)); 3048 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3049 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3050 getF32Constant(DAG, 0x3c1d8c17)); 3051 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3052 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3053 getF32Constant(DAG, 0x3d634a1d)); 3054 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3055 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3056 getF32Constant(DAG, 0x3e75fe14)); 3057 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3058 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3059 getF32Constant(DAG, 0x3f317234)); 3060 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3061 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3062 getF32Constant(DAG, 0x3f800000)); 3063 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl, 3064 MVT::i32, t13); 3065 3066 // Add the exponent into the result in integer domain. 3067 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3068 TwoToFracPartOfX, IntegerPartOfX); 3069 3070 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14); 3071 } 3072 } else { 3073 // No special expansion. 3074 result = DAG.getNode(ISD::FEXP, dl, 3075 getValue(I.getOperand(1)).getValueType(), 3076 getValue(I.getOperand(1))); 3077 } 3078 3079 setValue(&I, result); 3080} 3081 3082/// visitLog - Lower a log intrinsic. Handles the special sequences for 3083/// limited-precision mode. 3084void 3085SelectionDAGBuilder::visitLog(CallInst &I) { 3086 SDValue result; 3087 DebugLoc dl = getCurDebugLoc(); 3088 3089 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3090 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3091 SDValue Op = getValue(I.getOperand(1)); 3092 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3093 3094 // Scale the exponent by log(2) [0.69314718f]. 3095 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3096 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3097 getF32Constant(DAG, 0x3f317218)); 3098 3099 // Get the significand and build it into a floating-point number with 3100 // exponent of 1. 3101 SDValue X = GetSignificand(DAG, Op1, dl); 3102 3103 if (LimitFloatPrecision <= 6) { 3104 // For floating-point precision of 6: 3105 // 3106 // LogofMantissa = 3107 // -1.1609546f + 3108 // (1.4034025f - 0.23903021f * x) * x; 3109 // 3110 // error 0.0034276066, which is better than 8 bits 3111 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3112 getF32Constant(DAG, 0xbe74c456)); 3113 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3114 getF32Constant(DAG, 0x3fb3a2b1)); 3115 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3116 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3117 getF32Constant(DAG, 0x3f949a29)); 3118 3119 result = DAG.getNode(ISD::FADD, dl, 3120 MVT::f32, LogOfExponent, LogOfMantissa); 3121 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3122 // For floating-point precision of 12: 3123 // 3124 // LogOfMantissa = 3125 // -1.7417939f + 3126 // (2.8212026f + 3127 // (-1.4699568f + 3128 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3129 // 3130 // error 0.000061011436, which is 14 bits 3131 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3132 getF32Constant(DAG, 0xbd67b6d6)); 3133 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3134 getF32Constant(DAG, 0x3ee4f4b8)); 3135 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3136 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3137 getF32Constant(DAG, 0x3fbc278b)); 3138 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3139 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3140 getF32Constant(DAG, 0x40348e95)); 3141 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3142 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3143 getF32Constant(DAG, 0x3fdef31a)); 3144 3145 result = DAG.getNode(ISD::FADD, dl, 3146 MVT::f32, LogOfExponent, LogOfMantissa); 3147 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3148 // For floating-point precision of 18: 3149 // 3150 // LogOfMantissa = 3151 // -2.1072184f + 3152 // (4.2372794f + 3153 // (-3.7029485f + 3154 // (2.2781945f + 3155 // (-0.87823314f + 3156 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3157 // 3158 // error 0.0000023660568, which is better than 18 bits 3159 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3160 getF32Constant(DAG, 0xbc91e5ac)); 3161 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3162 getF32Constant(DAG, 0x3e4350aa)); 3163 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3164 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3165 getF32Constant(DAG, 0x3f60d3e3)); 3166 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3167 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3168 getF32Constant(DAG, 0x4011cdf0)); 3169 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3170 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3171 getF32Constant(DAG, 0x406cfd1c)); 3172 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3173 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3174 getF32Constant(DAG, 0x408797cb)); 3175 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3176 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3177 getF32Constant(DAG, 0x4006dcab)); 3178 3179 result = DAG.getNode(ISD::FADD, dl, 3180 MVT::f32, LogOfExponent, LogOfMantissa); 3181 } 3182 } else { 3183 // No special expansion. 3184 result = DAG.getNode(ISD::FLOG, dl, 3185 getValue(I.getOperand(1)).getValueType(), 3186 getValue(I.getOperand(1))); 3187 } 3188 3189 setValue(&I, result); 3190} 3191 3192/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3193/// limited-precision mode. 3194void 3195SelectionDAGBuilder::visitLog2(CallInst &I) { 3196 SDValue result; 3197 DebugLoc dl = getCurDebugLoc(); 3198 3199 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3200 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3201 SDValue Op = getValue(I.getOperand(1)); 3202 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3203 3204 // Get the exponent. 3205 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3206 3207 // Get the significand and build it into a floating-point number with 3208 // exponent of 1. 3209 SDValue X = GetSignificand(DAG, Op1, dl); 3210 3211 // Different possible minimax approximations of significand in 3212 // floating-point for various degrees of accuracy over [1,2]. 3213 if (LimitFloatPrecision <= 6) { 3214 // For floating-point precision of 6: 3215 // 3216 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3217 // 3218 // error 0.0049451742, which is more than 7 bits 3219 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3220 getF32Constant(DAG, 0xbeb08fe0)); 3221 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3222 getF32Constant(DAG, 0x40019463)); 3223 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3224 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3225 getF32Constant(DAG, 0x3fd6633d)); 3226 3227 result = DAG.getNode(ISD::FADD, dl, 3228 MVT::f32, LogOfExponent, Log2ofMantissa); 3229 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3230 // For floating-point precision of 12: 3231 // 3232 // Log2ofMantissa = 3233 // -2.51285454f + 3234 // (4.07009056f + 3235 // (-2.12067489f + 3236 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3237 // 3238 // error 0.0000876136000, which is better than 13 bits 3239 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3240 getF32Constant(DAG, 0xbda7262e)); 3241 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3242 getF32Constant(DAG, 0x3f25280b)); 3243 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3244 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3245 getF32Constant(DAG, 0x4007b923)); 3246 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3247 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3248 getF32Constant(DAG, 0x40823e2f)); 3249 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3250 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3251 getF32Constant(DAG, 0x4020d29c)); 3252 3253 result = DAG.getNode(ISD::FADD, dl, 3254 MVT::f32, LogOfExponent, Log2ofMantissa); 3255 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3256 // For floating-point precision of 18: 3257 // 3258 // Log2ofMantissa = 3259 // -3.0400495f + 3260 // (6.1129976f + 3261 // (-5.3420409f + 3262 // (3.2865683f + 3263 // (-1.2669343f + 3264 // (0.27515199f - 3265 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3266 // 3267 // error 0.0000018516, which is better than 18 bits 3268 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3269 getF32Constant(DAG, 0xbcd2769e)); 3270 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3271 getF32Constant(DAG, 0x3e8ce0b9)); 3272 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3273 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3274 getF32Constant(DAG, 0x3fa22ae7)); 3275 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3276 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3277 getF32Constant(DAG, 0x40525723)); 3278 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3279 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3280 getF32Constant(DAG, 0x40aaf200)); 3281 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3282 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3283 getF32Constant(DAG, 0x40c39dad)); 3284 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3285 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3286 getF32Constant(DAG, 0x4042902c)); 3287 3288 result = DAG.getNode(ISD::FADD, dl, 3289 MVT::f32, LogOfExponent, Log2ofMantissa); 3290 } 3291 } else { 3292 // No special expansion. 3293 result = DAG.getNode(ISD::FLOG2, dl, 3294 getValue(I.getOperand(1)).getValueType(), 3295 getValue(I.getOperand(1))); 3296 } 3297 3298 setValue(&I, result); 3299} 3300 3301/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3302/// limited-precision mode. 3303void 3304SelectionDAGBuilder::visitLog10(CallInst &I) { 3305 SDValue result; 3306 DebugLoc dl = getCurDebugLoc(); 3307 3308 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3309 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3310 SDValue Op = getValue(I.getOperand(1)); 3311 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3312 3313 // Scale the exponent by log10(2) [0.30102999f]. 3314 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3315 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3316 getF32Constant(DAG, 0x3e9a209a)); 3317 3318 // Get the significand and build it into a floating-point number with 3319 // exponent of 1. 3320 SDValue X = GetSignificand(DAG, Op1, dl); 3321 3322 if (LimitFloatPrecision <= 6) { 3323 // For floating-point precision of 6: 3324 // 3325 // Log10ofMantissa = 3326 // -0.50419619f + 3327 // (0.60948995f - 0.10380950f * x) * x; 3328 // 3329 // error 0.0014886165, which is 6 bits 3330 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3331 getF32Constant(DAG, 0xbdd49a13)); 3332 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3333 getF32Constant(DAG, 0x3f1c0789)); 3334 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3335 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3336 getF32Constant(DAG, 0x3f011300)); 3337 3338 result = DAG.getNode(ISD::FADD, dl, 3339 MVT::f32, LogOfExponent, Log10ofMantissa); 3340 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3341 // For floating-point precision of 12: 3342 // 3343 // Log10ofMantissa = 3344 // -0.64831180f + 3345 // (0.91751397f + 3346 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3347 // 3348 // error 0.00019228036, which is better than 12 bits 3349 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3350 getF32Constant(DAG, 0x3d431f31)); 3351 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3352 getF32Constant(DAG, 0x3ea21fb2)); 3353 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3354 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3355 getF32Constant(DAG, 0x3f6ae232)); 3356 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3357 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3358 getF32Constant(DAG, 0x3f25f7c3)); 3359 3360 result = DAG.getNode(ISD::FADD, dl, 3361 MVT::f32, LogOfExponent, Log10ofMantissa); 3362 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3363 // For floating-point precision of 18: 3364 // 3365 // Log10ofMantissa = 3366 // -0.84299375f + 3367 // (1.5327582f + 3368 // (-1.0688956f + 3369 // (0.49102474f + 3370 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3371 // 3372 // error 0.0000037995730, which is better than 18 bits 3373 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3374 getF32Constant(DAG, 0x3c5d51ce)); 3375 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3376 getF32Constant(DAG, 0x3e00685a)); 3377 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3378 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3379 getF32Constant(DAG, 0x3efb6798)); 3380 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3381 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3382 getF32Constant(DAG, 0x3f88d192)); 3383 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3384 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3385 getF32Constant(DAG, 0x3fc4316c)); 3386 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3387 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3388 getF32Constant(DAG, 0x3f57ce70)); 3389 3390 result = DAG.getNode(ISD::FADD, dl, 3391 MVT::f32, LogOfExponent, Log10ofMantissa); 3392 } 3393 } else { 3394 // No special expansion. 3395 result = DAG.getNode(ISD::FLOG10, dl, 3396 getValue(I.getOperand(1)).getValueType(), 3397 getValue(I.getOperand(1))); 3398 } 3399 3400 setValue(&I, result); 3401} 3402 3403/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3404/// limited-precision mode. 3405void 3406SelectionDAGBuilder::visitExp2(CallInst &I) { 3407 SDValue result; 3408 DebugLoc dl = getCurDebugLoc(); 3409 3410 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3411 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3412 SDValue Op = getValue(I.getOperand(1)); 3413 3414 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3415 3416 // FractionalPartOfX = x - (float)IntegerPartOfX; 3417 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3418 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3419 3420 // IntegerPartOfX <<= 23; 3421 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3422 DAG.getConstant(23, TLI.getPointerTy())); 3423 3424 if (LimitFloatPrecision <= 6) { 3425 // For floating-point precision of 6: 3426 // 3427 // TwoToFractionalPartOfX = 3428 // 0.997535578f + 3429 // (0.735607626f + 0.252464424f * x) * x; 3430 // 3431 // error 0.0144103317, which is 6 bits 3432 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3433 getF32Constant(DAG, 0x3e814304)); 3434 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3435 getF32Constant(DAG, 0x3f3c50c8)); 3436 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3437 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3438 getF32Constant(DAG, 0x3f7f5e7e)); 3439 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3440 SDValue TwoToFractionalPartOfX = 3441 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3442 3443 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3444 MVT::f32, TwoToFractionalPartOfX); 3445 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3446 // For floating-point precision of 12: 3447 // 3448 // TwoToFractionalPartOfX = 3449 // 0.999892986f + 3450 // (0.696457318f + 3451 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3452 // 3453 // error 0.000107046256, which is 13 to 14 bits 3454 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3455 getF32Constant(DAG, 0x3da235e3)); 3456 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3457 getF32Constant(DAG, 0x3e65b8f3)); 3458 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3459 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3460 getF32Constant(DAG, 0x3f324b07)); 3461 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3462 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3463 getF32Constant(DAG, 0x3f7ff8fd)); 3464 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3465 SDValue TwoToFractionalPartOfX = 3466 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3467 3468 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3469 MVT::f32, TwoToFractionalPartOfX); 3470 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3471 // For floating-point precision of 18: 3472 // 3473 // TwoToFractionalPartOfX = 3474 // 0.999999982f + 3475 // (0.693148872f + 3476 // (0.240227044f + 3477 // (0.554906021e-1f + 3478 // (0.961591928e-2f + 3479 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3480 // error 2.47208000*10^(-7), which is better than 18 bits 3481 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3482 getF32Constant(DAG, 0x3924b03e)); 3483 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3484 getF32Constant(DAG, 0x3ab24b87)); 3485 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3486 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3487 getF32Constant(DAG, 0x3c1d8c17)); 3488 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3489 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3490 getF32Constant(DAG, 0x3d634a1d)); 3491 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3492 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3493 getF32Constant(DAG, 0x3e75fe14)); 3494 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3495 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3496 getF32Constant(DAG, 0x3f317234)); 3497 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3498 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3499 getF32Constant(DAG, 0x3f800000)); 3500 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3501 SDValue TwoToFractionalPartOfX = 3502 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3503 3504 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3505 MVT::f32, TwoToFractionalPartOfX); 3506 } 3507 } else { 3508 // No special expansion. 3509 result = DAG.getNode(ISD::FEXP2, dl, 3510 getValue(I.getOperand(1)).getValueType(), 3511 getValue(I.getOperand(1))); 3512 } 3513 3514 setValue(&I, result); 3515} 3516 3517/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3518/// limited-precision mode with x == 10.0f. 3519void 3520SelectionDAGBuilder::visitPow(CallInst &I) { 3521 SDValue result; 3522 Value *Val = I.getOperand(1); 3523 DebugLoc dl = getCurDebugLoc(); 3524 bool IsExp10 = false; 3525 3526 if (getValue(Val).getValueType() == MVT::f32 && 3527 getValue(I.getOperand(2)).getValueType() == MVT::f32 && 3528 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3529 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3530 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3531 APFloat Ten(10.0f); 3532 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3533 } 3534 } 3535 } 3536 3537 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3538 SDValue Op = getValue(I.getOperand(2)); 3539 3540 // Put the exponent in the right bit position for later addition to the 3541 // final result: 3542 // 3543 // #define LOG2OF10 3.3219281f 3544 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3545 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3546 getF32Constant(DAG, 0x40549a78)); 3547 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3548 3549 // FractionalPartOfX = x - (float)IntegerPartOfX; 3550 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3551 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3552 3553 // IntegerPartOfX <<= 23; 3554 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3555 DAG.getConstant(23, TLI.getPointerTy())); 3556 3557 if (LimitFloatPrecision <= 6) { 3558 // For floating-point precision of 6: 3559 // 3560 // twoToFractionalPartOfX = 3561 // 0.997535578f + 3562 // (0.735607626f + 0.252464424f * x) * x; 3563 // 3564 // error 0.0144103317, which is 6 bits 3565 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3566 getF32Constant(DAG, 0x3e814304)); 3567 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3568 getF32Constant(DAG, 0x3f3c50c8)); 3569 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3570 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3571 getF32Constant(DAG, 0x3f7f5e7e)); 3572 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3573 SDValue TwoToFractionalPartOfX = 3574 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3575 3576 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3577 MVT::f32, TwoToFractionalPartOfX); 3578 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3579 // For floating-point precision of 12: 3580 // 3581 // TwoToFractionalPartOfX = 3582 // 0.999892986f + 3583 // (0.696457318f + 3584 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3585 // 3586 // error 0.000107046256, which is 13 to 14 bits 3587 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3588 getF32Constant(DAG, 0x3da235e3)); 3589 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3590 getF32Constant(DAG, 0x3e65b8f3)); 3591 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3592 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3593 getF32Constant(DAG, 0x3f324b07)); 3594 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3595 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3596 getF32Constant(DAG, 0x3f7ff8fd)); 3597 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3598 SDValue TwoToFractionalPartOfX = 3599 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3600 3601 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3602 MVT::f32, TwoToFractionalPartOfX); 3603 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3604 // For floating-point precision of 18: 3605 // 3606 // TwoToFractionalPartOfX = 3607 // 0.999999982f + 3608 // (0.693148872f + 3609 // (0.240227044f + 3610 // (0.554906021e-1f + 3611 // (0.961591928e-2f + 3612 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3613 // error 2.47208000*10^(-7), which is better than 18 bits 3614 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3615 getF32Constant(DAG, 0x3924b03e)); 3616 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3617 getF32Constant(DAG, 0x3ab24b87)); 3618 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3619 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3620 getF32Constant(DAG, 0x3c1d8c17)); 3621 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3622 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3623 getF32Constant(DAG, 0x3d634a1d)); 3624 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3625 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3626 getF32Constant(DAG, 0x3e75fe14)); 3627 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3628 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3629 getF32Constant(DAG, 0x3f317234)); 3630 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3631 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3632 getF32Constant(DAG, 0x3f800000)); 3633 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3634 SDValue TwoToFractionalPartOfX = 3635 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3636 3637 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3638 MVT::f32, TwoToFractionalPartOfX); 3639 } 3640 } else { 3641 // No special expansion. 3642 result = DAG.getNode(ISD::FPOW, dl, 3643 getValue(I.getOperand(1)).getValueType(), 3644 getValue(I.getOperand(1)), 3645 getValue(I.getOperand(2))); 3646 } 3647 3648 setValue(&I, result); 3649} 3650 3651 3652/// ExpandPowI - Expand a llvm.powi intrinsic. 3653static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 3654 SelectionDAG &DAG) { 3655 // If RHS is a constant, we can expand this out to a multiplication tree, 3656 // otherwise we end up lowering to a call to __powidf2 (for example). When 3657 // optimizing for size, we only want to do this if the expansion would produce 3658 // a small number of multiplies, otherwise we do the full expansion. 3659 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3660 // Get the exponent as a positive value. 3661 unsigned Val = RHSC->getSExtValue(); 3662 if ((int)Val < 0) Val = -Val; 3663 3664 // powi(x, 0) -> 1.0 3665 if (Val == 0) 3666 return DAG.getConstantFP(1.0, LHS.getValueType()); 3667 3668 Function *F = DAG.getMachineFunction().getFunction(); 3669 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 3670 // If optimizing for size, don't insert too many multiplies. This 3671 // inserts up to 5 multiplies. 3672 CountPopulation_32(Val)+Log2_32(Val) < 7) { 3673 // We use the simple binary decomposition method to generate the multiply 3674 // sequence. There are more optimal ways to do this (for example, 3675 // powi(x,15) generates one more multiply than it should), but this has 3676 // the benefit of being both really simple and much better than a libcall. 3677 SDValue Res; // Logically starts equal to 1.0 3678 SDValue CurSquare = LHS; 3679 while (Val) { 3680 if (Val & 1) { 3681 if (Res.getNode()) 3682 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 3683 else 3684 Res = CurSquare; // 1.0*CurSquare. 3685 } 3686 3687 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 3688 CurSquare, CurSquare); 3689 Val >>= 1; 3690 } 3691 3692 // If the original was negative, invert the result, producing 1/(x*x*x). 3693 if (RHSC->getSExtValue() < 0) 3694 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 3695 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 3696 return Res; 3697 } 3698 } 3699 3700 // Otherwise, expand to a libcall. 3701 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 3702} 3703 3704 3705/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 3706/// we want to emit this as a call to a named external function, return the name 3707/// otherwise lower it and return null. 3708const char * 3709SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 3710 DebugLoc dl = getCurDebugLoc(); 3711 SDValue Res; 3712 3713 switch (Intrinsic) { 3714 default: 3715 // By default, turn this into a target intrinsic node. 3716 visitTargetIntrinsic(I, Intrinsic); 3717 return 0; 3718 case Intrinsic::vastart: visitVAStart(I); return 0; 3719 case Intrinsic::vaend: visitVAEnd(I); return 0; 3720 case Intrinsic::vacopy: visitVACopy(I); return 0; 3721 case Intrinsic::returnaddress: 3722 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 3723 getValue(I.getOperand(1)))); 3724 return 0; 3725 case Intrinsic::frameaddress: 3726 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 3727 getValue(I.getOperand(1)))); 3728 return 0; 3729 case Intrinsic::setjmp: 3730 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 3731 case Intrinsic::longjmp: 3732 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 3733 case Intrinsic::memcpy: { 3734 SDValue Op1 = getValue(I.getOperand(1)); 3735 SDValue Op2 = getValue(I.getOperand(2)); 3736 SDValue Op3 = getValue(I.getOperand(3)); 3737 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3738 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false, 3739 I.getOperand(1), 0, I.getOperand(2), 0)); 3740 return 0; 3741 } 3742 case Intrinsic::memset: { 3743 SDValue Op1 = getValue(I.getOperand(1)); 3744 SDValue Op2 = getValue(I.getOperand(2)); 3745 SDValue Op3 = getValue(I.getOperand(3)); 3746 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3747 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, 3748 I.getOperand(1), 0)); 3749 return 0; 3750 } 3751 case Intrinsic::memmove: { 3752 SDValue Op1 = getValue(I.getOperand(1)); 3753 SDValue Op2 = getValue(I.getOperand(2)); 3754 SDValue Op3 = getValue(I.getOperand(3)); 3755 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3756 3757 // If the source and destination are known to not be aliases, we can 3758 // lower memmove as memcpy. 3759 uint64_t Size = -1ULL; 3760 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 3761 Size = C->getZExtValue(); 3762 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) == 3763 AliasAnalysis::NoAlias) { 3764 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false, 3765 I.getOperand(1), 0, I.getOperand(2), 0)); 3766 return 0; 3767 } 3768 3769 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, 3770 I.getOperand(1), 0, I.getOperand(2), 0)); 3771 return 0; 3772 } 3773 case Intrinsic::dbg_declare: { 3774 // FIXME: currently, we get here only if OptLevel != CodeGenOpt::None. 3775 // The real handling of this intrinsic is in FastISel. 3776 if (OptLevel != CodeGenOpt::None) 3777 // FIXME: Variable debug info is not supported here. 3778 return 0; 3779 DwarfWriter *DW = DAG.getDwarfWriter(); 3780 if (!DW) 3781 return 0; 3782 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 3783 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None)) 3784 return 0; 3785 3786 MDNode *Variable = DI.getVariable(); 3787 Value *Address = DI.getAddress(); 3788 if (!Address) 3789 return 0; 3790 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 3791 Address = BCI->getOperand(0); 3792 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 3793 // Don't handle byval struct arguments or VLAs, for example. 3794 if (!AI) 3795 return 0; 3796 DenseMap<const AllocaInst*, int>::iterator SI = 3797 FuncInfo.StaticAllocaMap.find(AI); 3798 if (SI == FuncInfo.StaticAllocaMap.end()) 3799 return 0; // VLAs. 3800 int FI = SI->second; 3801 3802 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) 3803 if (MDNode *Dbg = DI.getMetadata("dbg")) 3804 MMI->setVariableDbgInfo(Variable, FI, Dbg); 3805 return 0; 3806 } 3807 case Intrinsic::dbg_value: { 3808 DwarfWriter *DW = DAG.getDwarfWriter(); 3809 if (!DW) 3810 return 0; 3811 DbgValueInst &DI = cast<DbgValueInst>(I); 3812 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None)) 3813 return 0; 3814 3815 MDNode *Variable = DI.getVariable(); 3816 uint64_t Offset = DI.getOffset(); 3817 Value *V = DI.getValue(); 3818 if (!V) 3819 return 0; 3820 3821 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 3822 // but do not always have a corresponding SDNode built. The SDNodeOrder 3823 // absolute, but not relative, values are different depending on whether 3824 // debug info exists. 3825 ++SDNodeOrder; 3826 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 3827 SDDbgValue* dv = new SDDbgValue(Variable, V, Offset, dl, SDNodeOrder); 3828 DAG.AddDbgValue(dv); 3829 } else { 3830 SDValue &N = NodeMap[V]; 3831 if (N.getNode()) { 3832 SDDbgValue *dv = new SDDbgValue(Variable, N.getNode(), 3833 N.getResNo(), Offset, dl, SDNodeOrder); 3834 DAG.AddDbgValue(dv, N.getNode()); 3835 } else { 3836 // We may expand this to cover more cases. One case where we have no 3837 // data available is an unreferenced parameter; we need this fallback. 3838 SDDbgValue* dv = new SDDbgValue(Variable, 3839 UndefValue::get(V->getType()), 3840 Offset, dl, SDNodeOrder); 3841 DAG.AddDbgValue(dv); 3842 } 3843 } 3844 3845 // Build a debug info table entry. 3846 if (BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 3847 V = BCI->getOperand(0); 3848 AllocaInst *AI = dyn_cast<AllocaInst>(V); 3849 // Don't handle byval struct arguments or VLAs, for example. 3850 if (!AI) 3851 return 0; 3852 DenseMap<const AllocaInst*, int>::iterator SI = 3853 FuncInfo.StaticAllocaMap.find(AI); 3854 if (SI == FuncInfo.StaticAllocaMap.end()) 3855 return 0; // VLAs. 3856 int FI = SI->second; 3857 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) 3858 if (MDNode *Dbg = DI.getMetadata("dbg")) 3859 MMI->setVariableDbgInfo(Variable, FI, Dbg); 3860 return 0; 3861 } 3862 case Intrinsic::eh_exception: { 3863 // Insert the EXCEPTIONADDR instruction. 3864 assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!"); 3865 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 3866 SDValue Ops[1]; 3867 Ops[0] = DAG.getRoot(); 3868 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 3869 setValue(&I, Op); 3870 DAG.setRoot(Op.getValue(1)); 3871 return 0; 3872 } 3873 3874 case Intrinsic::eh_selector: { 3875 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3876 3877 if (CurMBB->isLandingPad()) 3878 AddCatchInfo(I, MMI, CurMBB); 3879 else { 3880#ifndef NDEBUG 3881 FuncInfo.CatchInfoLost.insert(&I); 3882#endif 3883 // FIXME: Mark exception selector register as live in. Hack for PR1508. 3884 unsigned Reg = TLI.getExceptionSelectorRegister(); 3885 if (Reg) CurMBB->addLiveIn(Reg); 3886 } 3887 3888 // Insert the EHSELECTION instruction. 3889 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 3890 SDValue Ops[2]; 3891 Ops[0] = getValue(I.getOperand(1)); 3892 Ops[1] = getRoot(); 3893 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 3894 DAG.setRoot(Op.getValue(1)); 3895 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 3896 return 0; 3897 } 3898 3899 case Intrinsic::eh_typeid_for: { 3900 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3901 3902 if (MMI) { 3903 // Find the type id for the given typeinfo. 3904 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 3905 unsigned TypeID = MMI->getTypeIDFor(GV); 3906 Res = DAG.getConstant(TypeID, MVT::i32); 3907 } else { 3908 // Return something different to eh_selector. 3909 Res = DAG.getConstant(1, MVT::i32); 3910 } 3911 3912 setValue(&I, Res); 3913 return 0; 3914 } 3915 3916 case Intrinsic::eh_return_i32: 3917 case Intrinsic::eh_return_i64: 3918 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 3919 MMI->setCallsEHReturn(true); 3920 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 3921 MVT::Other, 3922 getControlRoot(), 3923 getValue(I.getOperand(1)), 3924 getValue(I.getOperand(2)))); 3925 } else { 3926 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 3927 } 3928 3929 return 0; 3930 case Intrinsic::eh_unwind_init: 3931 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 3932 MMI->setCallsUnwindInit(true); 3933 } 3934 return 0; 3935 case Intrinsic::eh_dwarf_cfa: { 3936 EVT VT = getValue(I.getOperand(1)).getValueType(); 3937 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), dl, 3938 TLI.getPointerTy()); 3939 SDValue Offset = DAG.getNode(ISD::ADD, dl, 3940 TLI.getPointerTy(), 3941 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 3942 TLI.getPointerTy()), 3943 CfaArg); 3944 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 3945 TLI.getPointerTy(), 3946 DAG.getConstant(0, TLI.getPointerTy())); 3947 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 3948 FA, Offset)); 3949 return 0; 3950 } 3951 case Intrinsic::eh_sjlj_callsite: { 3952 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3953 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1)); 3954 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 3955 assert(MMI->getCurrentCallSite() == 0 && "Overlapping call sites!"); 3956 3957 MMI->setCurrentCallSite(CI->getZExtValue()); 3958 return 0; 3959 } 3960 3961 case Intrinsic::convertff: 3962 case Intrinsic::convertfsi: 3963 case Intrinsic::convertfui: 3964 case Intrinsic::convertsif: 3965 case Intrinsic::convertuif: 3966 case Intrinsic::convertss: 3967 case Intrinsic::convertsu: 3968 case Intrinsic::convertus: 3969 case Intrinsic::convertuu: { 3970 ISD::CvtCode Code = ISD::CVT_INVALID; 3971 switch (Intrinsic) { 3972 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 3973 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 3974 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 3975 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 3976 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 3977 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 3978 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 3979 case Intrinsic::convertus: Code = ISD::CVT_US; break; 3980 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 3981 } 3982 EVT DestVT = TLI.getValueType(I.getType()); 3983 Value *Op1 = I.getOperand(1); 3984 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 3985 DAG.getValueType(DestVT), 3986 DAG.getValueType(getValue(Op1).getValueType()), 3987 getValue(I.getOperand(2)), 3988 getValue(I.getOperand(3)), 3989 Code); 3990 setValue(&I, Res); 3991 return 0; 3992 } 3993 case Intrinsic::sqrt: 3994 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 3995 getValue(I.getOperand(1)).getValueType(), 3996 getValue(I.getOperand(1)))); 3997 return 0; 3998 case Intrinsic::powi: 3999 setValue(&I, ExpandPowI(dl, getValue(I.getOperand(1)), 4000 getValue(I.getOperand(2)), DAG)); 4001 return 0; 4002 case Intrinsic::sin: 4003 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4004 getValue(I.getOperand(1)).getValueType(), 4005 getValue(I.getOperand(1)))); 4006 return 0; 4007 case Intrinsic::cos: 4008 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4009 getValue(I.getOperand(1)).getValueType(), 4010 getValue(I.getOperand(1)))); 4011 return 0; 4012 case Intrinsic::log: 4013 visitLog(I); 4014 return 0; 4015 case Intrinsic::log2: 4016 visitLog2(I); 4017 return 0; 4018 case Intrinsic::log10: 4019 visitLog10(I); 4020 return 0; 4021 case Intrinsic::exp: 4022 visitExp(I); 4023 return 0; 4024 case Intrinsic::exp2: 4025 visitExp2(I); 4026 return 0; 4027 case Intrinsic::pow: 4028 visitPow(I); 4029 return 0; 4030 case Intrinsic::convert_to_fp16: 4031 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4032 MVT::i16, getValue(I.getOperand(1)))); 4033 return 0; 4034 case Intrinsic::convert_from_fp16: 4035 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4036 MVT::f32, getValue(I.getOperand(1)))); 4037 return 0; 4038 case Intrinsic::pcmarker: { 4039 SDValue Tmp = getValue(I.getOperand(1)); 4040 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4041 return 0; 4042 } 4043 case Intrinsic::readcyclecounter: { 4044 SDValue Op = getRoot(); 4045 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4046 DAG.getVTList(MVT::i64, MVT::Other), 4047 &Op, 1); 4048 setValue(&I, Res); 4049 DAG.setRoot(Res.getValue(1)); 4050 return 0; 4051 } 4052 case Intrinsic::bswap: 4053 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4054 getValue(I.getOperand(1)).getValueType(), 4055 getValue(I.getOperand(1)))); 4056 return 0; 4057 case Intrinsic::cttz: { 4058 SDValue Arg = getValue(I.getOperand(1)); 4059 EVT Ty = Arg.getValueType(); 4060 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4061 return 0; 4062 } 4063 case Intrinsic::ctlz: { 4064 SDValue Arg = getValue(I.getOperand(1)); 4065 EVT Ty = Arg.getValueType(); 4066 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4067 return 0; 4068 } 4069 case Intrinsic::ctpop: { 4070 SDValue Arg = getValue(I.getOperand(1)); 4071 EVT Ty = Arg.getValueType(); 4072 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4073 return 0; 4074 } 4075 case Intrinsic::stacksave: { 4076 SDValue Op = getRoot(); 4077 Res = DAG.getNode(ISD::STACKSAVE, dl, 4078 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4079 setValue(&I, Res); 4080 DAG.setRoot(Res.getValue(1)); 4081 return 0; 4082 } 4083 case Intrinsic::stackrestore: { 4084 Res = getValue(I.getOperand(1)); 4085 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4086 return 0; 4087 } 4088 case Intrinsic::stackprotector: { 4089 // Emit code into the DAG to store the stack guard onto the stack. 4090 MachineFunction &MF = DAG.getMachineFunction(); 4091 MachineFrameInfo *MFI = MF.getFrameInfo(); 4092 EVT PtrTy = TLI.getPointerTy(); 4093 4094 SDValue Src = getValue(I.getOperand(1)); // The guard's value. 4095 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2)); 4096 4097 int FI = FuncInfo.StaticAllocaMap[Slot]; 4098 MFI->setStackProtectorIndex(FI); 4099 4100 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4101 4102 // Store the stack protector onto the stack. 4103 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4104 PseudoSourceValue::getFixedStack(FI), 4105 0, true, false, 0); 4106 setValue(&I, Res); 4107 DAG.setRoot(Res); 4108 return 0; 4109 } 4110 case Intrinsic::objectsize: { 4111 // If we don't know by now, we're never going to know. 4112 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2)); 4113 4114 assert(CI && "Non-constant type in __builtin_object_size?"); 4115 4116 SDValue Arg = getValue(I.getOperand(0)); 4117 EVT Ty = Arg.getValueType(); 4118 4119 if (CI->getZExtValue() == 0) 4120 Res = DAG.getConstant(-1ULL, Ty); 4121 else 4122 Res = DAG.getConstant(0, Ty); 4123 4124 setValue(&I, Res); 4125 return 0; 4126 } 4127 case Intrinsic::var_annotation: 4128 // Discard annotate attributes 4129 return 0; 4130 4131 case Intrinsic::init_trampoline: { 4132 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts()); 4133 4134 SDValue Ops[6]; 4135 Ops[0] = getRoot(); 4136 Ops[1] = getValue(I.getOperand(1)); 4137 Ops[2] = getValue(I.getOperand(2)); 4138 Ops[3] = getValue(I.getOperand(3)); 4139 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 4140 Ops[5] = DAG.getSrcValue(F); 4141 4142 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4143 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4144 Ops, 6); 4145 4146 setValue(&I, Res); 4147 DAG.setRoot(Res.getValue(1)); 4148 return 0; 4149 } 4150 case Intrinsic::gcroot: 4151 if (GFI) { 4152 Value *Alloca = I.getOperand(1); 4153 Constant *TypeMap = cast<Constant>(I.getOperand(2)); 4154 4155 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4156 GFI->addStackRoot(FI->getIndex(), TypeMap); 4157 } 4158 return 0; 4159 case Intrinsic::gcread: 4160 case Intrinsic::gcwrite: 4161 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4162 return 0; 4163 case Intrinsic::flt_rounds: 4164 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4165 return 0; 4166 case Intrinsic::trap: 4167 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4168 return 0; 4169 case Intrinsic::uadd_with_overflow: 4170 return implVisitAluOverflow(I, ISD::UADDO); 4171 case Intrinsic::sadd_with_overflow: 4172 return implVisitAluOverflow(I, ISD::SADDO); 4173 case Intrinsic::usub_with_overflow: 4174 return implVisitAluOverflow(I, ISD::USUBO); 4175 case Intrinsic::ssub_with_overflow: 4176 return implVisitAluOverflow(I, ISD::SSUBO); 4177 case Intrinsic::umul_with_overflow: 4178 return implVisitAluOverflow(I, ISD::UMULO); 4179 case Intrinsic::smul_with_overflow: 4180 return implVisitAluOverflow(I, ISD::SMULO); 4181 4182 case Intrinsic::prefetch: { 4183 SDValue Ops[4]; 4184 Ops[0] = getRoot(); 4185 Ops[1] = getValue(I.getOperand(1)); 4186 Ops[2] = getValue(I.getOperand(2)); 4187 Ops[3] = getValue(I.getOperand(3)); 4188 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4)); 4189 return 0; 4190 } 4191 4192 case Intrinsic::memory_barrier: { 4193 SDValue Ops[6]; 4194 Ops[0] = getRoot(); 4195 for (int x = 1; x < 6; ++x) 4196 Ops[x] = getValue(I.getOperand(x)); 4197 4198 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4199 return 0; 4200 } 4201 case Intrinsic::atomic_cmp_swap: { 4202 SDValue Root = getRoot(); 4203 SDValue L = 4204 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4205 getValue(I.getOperand(2)).getValueType().getSimpleVT(), 4206 Root, 4207 getValue(I.getOperand(1)), 4208 getValue(I.getOperand(2)), 4209 getValue(I.getOperand(3)), 4210 I.getOperand(1)); 4211 setValue(&I, L); 4212 DAG.setRoot(L.getValue(1)); 4213 return 0; 4214 } 4215 case Intrinsic::atomic_load_add: 4216 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4217 case Intrinsic::atomic_load_sub: 4218 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4219 case Intrinsic::atomic_load_or: 4220 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4221 case Intrinsic::atomic_load_xor: 4222 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4223 case Intrinsic::atomic_load_and: 4224 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4225 case Intrinsic::atomic_load_nand: 4226 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4227 case Intrinsic::atomic_load_max: 4228 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4229 case Intrinsic::atomic_load_min: 4230 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4231 case Intrinsic::atomic_load_umin: 4232 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4233 case Intrinsic::atomic_load_umax: 4234 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4235 case Intrinsic::atomic_swap: 4236 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4237 4238 case Intrinsic::invariant_start: 4239 case Intrinsic::lifetime_start: 4240 // Discard region information. 4241 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4242 return 0; 4243 case Intrinsic::invariant_end: 4244 case Intrinsic::lifetime_end: 4245 // Discard region information. 4246 return 0; 4247 } 4248} 4249 4250/// Test if the given instruction is in a position to be optimized 4251/// with a tail-call. This roughly means that it's in a block with 4252/// a return and there's nothing that needs to be scheduled 4253/// between it and the return. 4254/// 4255/// This function only tests target-independent requirements. 4256static bool 4257isInTailCallPosition(CallSite CS, Attributes CalleeRetAttr, 4258 const TargetLowering &TLI) { 4259 const Instruction *I = CS.getInstruction(); 4260 const BasicBlock *ExitBB = I->getParent(); 4261 const TerminatorInst *Term = ExitBB->getTerminator(); 4262 const ReturnInst *Ret = dyn_cast<ReturnInst>(Term); 4263 const Function *F = ExitBB->getParent(); 4264 4265 // The block must end in a return statement or unreachable. 4266 // 4267 // FIXME: Decline tailcall if it's not guaranteed and if the block ends in 4268 // an unreachable, for now. The way tailcall optimization is currently 4269 // implemented means it will add an epilogue followed by a jump. That is 4270 // not profitable. Also, if the callee is a special function (e.g. 4271 // longjmp on x86), it can end up causing miscompilation that has not 4272 // been fully understood. 4273 if (!Ret && 4274 (!GuaranteedTailCallOpt || !isa<UnreachableInst>(Term))) return false; 4275 4276 // If I will have a chain, make sure no other instruction that will have a 4277 // chain interposes between I and the return. 4278 if (I->mayHaveSideEffects() || I->mayReadFromMemory() || 4279 !I->isSafeToSpeculativelyExecute()) 4280 for (BasicBlock::const_iterator BBI = prior(prior(ExitBB->end())); ; 4281 --BBI) { 4282 if (&*BBI == I) 4283 break; 4284 // Debug info intrinsics do not get in the way of tail call optimization. 4285 if (isa<DbgInfoIntrinsic>(BBI)) 4286 continue; 4287 if (BBI->mayHaveSideEffects() || BBI->mayReadFromMemory() || 4288 !BBI->isSafeToSpeculativelyExecute()) 4289 return false; 4290 } 4291 4292 // If the block ends with a void return or unreachable, it doesn't matter 4293 // what the call's return type is. 4294 if (!Ret || Ret->getNumOperands() == 0) return true; 4295 4296 // If the return value is undef, it doesn't matter what the call's 4297 // return type is. 4298 if (isa<UndefValue>(Ret->getOperand(0))) return true; 4299 4300 // Conservatively require the attributes of the call to match those of 4301 // the return. Ignore noalias because it doesn't affect the call sequence. 4302 unsigned CallerRetAttr = F->getAttributes().getRetAttributes(); 4303 if ((CalleeRetAttr ^ CallerRetAttr) & ~Attribute::NoAlias) 4304 return false; 4305 4306 // It's not safe to eliminate the sign / zero extension of the return value. 4307 if ((CallerRetAttr & Attribute::ZExt) || (CallerRetAttr & Attribute::SExt)) 4308 return false; 4309 4310 // Otherwise, make sure the unmodified return value of I is the return value. 4311 for (const Instruction *U = dyn_cast<Instruction>(Ret->getOperand(0)); ; 4312 U = dyn_cast<Instruction>(U->getOperand(0))) { 4313 if (!U) 4314 return false; 4315 if (!U->hasOneUse()) 4316 return false; 4317 if (U == I) 4318 break; 4319 // Check for a truly no-op truncate. 4320 if (isa<TruncInst>(U) && 4321 TLI.isTruncateFree(U->getOperand(0)->getType(), U->getType())) 4322 continue; 4323 // Check for a truly no-op bitcast. 4324 if (isa<BitCastInst>(U) && 4325 (U->getOperand(0)->getType() == U->getType() || 4326 (U->getOperand(0)->getType()->isPointerTy() && 4327 U->getType()->isPointerTy()))) 4328 continue; 4329 // Otherwise it's not a true no-op. 4330 return false; 4331 } 4332 4333 return true; 4334} 4335 4336void SelectionDAGBuilder::LowerCallTo(CallSite CS, SDValue Callee, 4337 bool isTailCall, 4338 MachineBasicBlock *LandingPad) { 4339 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4340 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4341 const Type *RetTy = FTy->getReturnType(); 4342 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4343 MCSymbol *BeginLabel = 0; 4344 4345 TargetLowering::ArgListTy Args; 4346 TargetLowering::ArgListEntry Entry; 4347 Args.reserve(CS.arg_size()); 4348 4349 // Check whether the function can return without sret-demotion. 4350 SmallVector<EVT, 4> OutVTs; 4351 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags; 4352 SmallVector<uint64_t, 4> Offsets; 4353 getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4354 OutVTs, OutsFlags, TLI, &Offsets); 4355 4356 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4357 FTy->isVarArg(), OutVTs, OutsFlags, DAG); 4358 4359 SDValue DemoteStackSlot; 4360 4361 if (!CanLowerReturn) { 4362 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4363 FTy->getReturnType()); 4364 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4365 FTy->getReturnType()); 4366 MachineFunction &MF = DAG.getMachineFunction(); 4367 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4368 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4369 4370 DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4371 Entry.Node = DemoteStackSlot; 4372 Entry.Ty = StackSlotPtrType; 4373 Entry.isSExt = false; 4374 Entry.isZExt = false; 4375 Entry.isInReg = false; 4376 Entry.isSRet = true; 4377 Entry.isNest = false; 4378 Entry.isByVal = false; 4379 Entry.Alignment = Align; 4380 Args.push_back(Entry); 4381 RetTy = Type::getVoidTy(FTy->getContext()); 4382 } 4383 4384 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4385 i != e; ++i) { 4386 SDValue ArgNode = getValue(*i); 4387 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 4388 4389 unsigned attrInd = i - CS.arg_begin() + 1; 4390 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4391 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4392 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4393 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4394 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4395 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4396 Entry.Alignment = CS.getParamAlignment(attrInd); 4397 Args.push_back(Entry); 4398 } 4399 4400 if (LandingPad && MMI) { 4401 // Insert a label before the invoke call to mark the try range. This can be 4402 // used to detect deletion of the invoke via the MachineModuleInfo. 4403 BeginLabel = MMI->getContext().CreateTempSymbol(); 4404 4405 // For SjLj, keep track of which landing pads go with which invokes 4406 // so as to maintain the ordering of pads in the LSDA. 4407 unsigned CallSiteIndex = MMI->getCurrentCallSite(); 4408 if (CallSiteIndex) { 4409 MMI->setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4410 // Now that the call site is handled, stop tracking it. 4411 MMI->setCurrentCallSite(0); 4412 } 4413 4414 // Both PendingLoads and PendingExports must be flushed here; 4415 // this call might not return. 4416 (void)getRoot(); 4417 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4418 } 4419 4420 // Check if target-independent constraints permit a tail call here. 4421 // Target-dependent constraints are checked within TLI.LowerCallTo. 4422 if (isTailCall && 4423 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4424 isTailCall = false; 4425 4426 std::pair<SDValue,SDValue> Result = 4427 TLI.LowerCallTo(getRoot(), RetTy, 4428 CS.paramHasAttr(0, Attribute::SExt), 4429 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4430 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4431 CS.getCallingConv(), 4432 isTailCall, 4433 !CS.getInstruction()->use_empty(), 4434 Callee, Args, DAG, getCurDebugLoc()); 4435 assert((isTailCall || Result.second.getNode()) && 4436 "Non-null chain expected with non-tail call!"); 4437 assert((Result.second.getNode() || !Result.first.getNode()) && 4438 "Null value expected with tail call!"); 4439 if (Result.first.getNode()) { 4440 setValue(CS.getInstruction(), Result.first); 4441 } else if (!CanLowerReturn && Result.second.getNode()) { 4442 // The instruction result is the result of loading from the 4443 // hidden sret parameter. 4444 SmallVector<EVT, 1> PVTs; 4445 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 4446 4447 ComputeValueVTs(TLI, PtrRetTy, PVTs); 4448 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 4449 EVT PtrVT = PVTs[0]; 4450 unsigned NumValues = OutVTs.size(); 4451 SmallVector<SDValue, 4> Values(NumValues); 4452 SmallVector<SDValue, 4> Chains(NumValues); 4453 4454 for (unsigned i = 0; i < NumValues; ++i) { 4455 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 4456 DemoteStackSlot, 4457 DAG.getConstant(Offsets[i], PtrVT)); 4458 SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second, 4459 Add, NULL, Offsets[i], false, false, 1); 4460 Values[i] = L; 4461 Chains[i] = L.getValue(1); 4462 } 4463 4464 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 4465 MVT::Other, &Chains[0], NumValues); 4466 PendingLoads.push_back(Chain); 4467 4468 // Collect the legal value parts into potentially illegal values 4469 // that correspond to the original function's return values. 4470 SmallVector<EVT, 4> RetTys; 4471 RetTy = FTy->getReturnType(); 4472 ComputeValueVTs(TLI, RetTy, RetTys); 4473 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4474 SmallVector<SDValue, 4> ReturnValues; 4475 unsigned CurReg = 0; 4476 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4477 EVT VT = RetTys[I]; 4478 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 4479 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 4480 4481 SDValue ReturnValue = 4482 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 4483 RegisterVT, VT, AssertOp); 4484 ReturnValues.push_back(ReturnValue); 4485 CurReg += NumRegs; 4486 } 4487 4488 setValue(CS.getInstruction(), 4489 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 4490 DAG.getVTList(&RetTys[0], RetTys.size()), 4491 &ReturnValues[0], ReturnValues.size())); 4492 4493 } 4494 4495 // As a special case, a null chain means that a tail call has been emitted and 4496 // the DAG root is already updated. 4497 if (Result.second.getNode()) 4498 DAG.setRoot(Result.second); 4499 else 4500 HasTailCall = true; 4501 4502 if (LandingPad && MMI) { 4503 // Insert a label at the end of the invoke call to mark the try range. This 4504 // can be used to detect deletion of the invoke via the MachineModuleInfo. 4505 MCSymbol *EndLabel = MMI->getContext().CreateTempSymbol(); 4506 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 4507 4508 // Inform MachineModuleInfo of range. 4509 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 4510 } 4511} 4512 4513/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 4514/// value is equal or not-equal to zero. 4515static bool IsOnlyUsedInZeroEqualityComparison(Value *V) { 4516 for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); 4517 UI != E; ++UI) { 4518 if (ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 4519 if (IC->isEquality()) 4520 if (Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 4521 if (C->isNullValue()) 4522 continue; 4523 // Unknown instruction. 4524 return false; 4525 } 4526 return true; 4527} 4528 4529static SDValue getMemCmpLoad(Value *PtrVal, MVT LoadVT, const Type *LoadTy, 4530 SelectionDAGBuilder &Builder) { 4531 4532 // Check to see if this load can be trivially constant folded, e.g. if the 4533 // input is from a string literal. 4534 if (Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 4535 // Cast pointer to the type we really want to load. 4536 LoadInput = ConstantExpr::getBitCast(LoadInput, 4537 PointerType::getUnqual(LoadTy)); 4538 4539 if (Constant *LoadCst = ConstantFoldLoadFromConstPtr(LoadInput, Builder.TD)) 4540 return Builder.getValue(LoadCst); 4541 } 4542 4543 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 4544 // still constant memory, the input chain can be the entry node. 4545 SDValue Root; 4546 bool ConstantMemory = false; 4547 4548 // Do not serialize (non-volatile) loads of constant memory with anything. 4549 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 4550 Root = Builder.DAG.getEntryNode(); 4551 ConstantMemory = true; 4552 } else { 4553 // Do not serialize non-volatile loads against each other. 4554 Root = Builder.DAG.getRoot(); 4555 } 4556 4557 SDValue Ptr = Builder.getValue(PtrVal); 4558 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 4559 Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/, 4560 false /*volatile*/, 4561 false /*nontemporal*/, 1 /* align=1 */); 4562 4563 if (!ConstantMemory) 4564 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 4565 return LoadVal; 4566} 4567 4568 4569/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 4570/// If so, return true and lower it, otherwise return false and it will be 4571/// lowered like a normal call. 4572bool SelectionDAGBuilder::visitMemCmpCall(CallInst &I) { 4573 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 4574 if (I.getNumOperands() != 4) 4575 return false; 4576 4577 Value *LHS = I.getOperand(1), *RHS = I.getOperand(2); 4578 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 4579 !I.getOperand(3)->getType()->isIntegerTy() || 4580 !I.getType()->isIntegerTy()) 4581 return false; 4582 4583 ConstantInt *Size = dyn_cast<ConstantInt>(I.getOperand(3)); 4584 4585 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 4586 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 4587 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 4588 bool ActuallyDoIt = true; 4589 MVT LoadVT; 4590 const Type *LoadTy; 4591 switch (Size->getZExtValue()) { 4592 default: 4593 LoadVT = MVT::Other; 4594 LoadTy = 0; 4595 ActuallyDoIt = false; 4596 break; 4597 case 2: 4598 LoadVT = MVT::i16; 4599 LoadTy = Type::getInt16Ty(Size->getContext()); 4600 break; 4601 case 4: 4602 LoadVT = MVT::i32; 4603 LoadTy = Type::getInt32Ty(Size->getContext()); 4604 break; 4605 case 8: 4606 LoadVT = MVT::i64; 4607 LoadTy = Type::getInt64Ty(Size->getContext()); 4608 break; 4609 /* 4610 case 16: 4611 LoadVT = MVT::v4i32; 4612 LoadTy = Type::getInt32Ty(Size->getContext()); 4613 LoadTy = VectorType::get(LoadTy, 4); 4614 break; 4615 */ 4616 } 4617 4618 // This turns into unaligned loads. We only do this if the target natively 4619 // supports the MVT we'll be loading or if it is small enough (<= 4) that 4620 // we'll only produce a small number of byte loads. 4621 4622 // Require that we can find a legal MVT, and only do this if the target 4623 // supports unaligned loads of that type. Expanding into byte loads would 4624 // bloat the code. 4625 if (ActuallyDoIt && Size->getZExtValue() > 4) { 4626 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 4627 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 4628 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 4629 ActuallyDoIt = false; 4630 } 4631 4632 if (ActuallyDoIt) { 4633 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 4634 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 4635 4636 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 4637 ISD::SETNE); 4638 EVT CallVT = TLI.getValueType(I.getType(), true); 4639 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 4640 return true; 4641 } 4642 } 4643 4644 4645 return false; 4646} 4647 4648 4649void SelectionDAGBuilder::visitCall(CallInst &I) { 4650 const char *RenameFn = 0; 4651 if (Function *F = I.getCalledFunction()) { 4652 if (F->isDeclaration()) { 4653 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo(); 4654 if (II) { 4655 if (unsigned IID = II->getIntrinsicID(F)) { 4656 RenameFn = visitIntrinsicCall(I, IID); 4657 if (!RenameFn) 4658 return; 4659 } 4660 } 4661 if (unsigned IID = F->getIntrinsicID()) { 4662 RenameFn = visitIntrinsicCall(I, IID); 4663 if (!RenameFn) 4664 return; 4665 } 4666 } 4667 4668 // Check for well-known libc/libm calls. If the function is internal, it 4669 // can't be a library call. 4670 if (!F->hasLocalLinkage() && F->hasName()) { 4671 StringRef Name = F->getName(); 4672 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 4673 if (I.getNumOperands() == 3 && // Basic sanity checks. 4674 I.getOperand(1)->getType()->isFloatingPointTy() && 4675 I.getType() == I.getOperand(1)->getType() && 4676 I.getType() == I.getOperand(2)->getType()) { 4677 SDValue LHS = getValue(I.getOperand(1)); 4678 SDValue RHS = getValue(I.getOperand(2)); 4679 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 4680 LHS.getValueType(), LHS, RHS)); 4681 return; 4682 } 4683 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 4684 if (I.getNumOperands() == 2 && // Basic sanity checks. 4685 I.getOperand(1)->getType()->isFloatingPointTy() && 4686 I.getType() == I.getOperand(1)->getType()) { 4687 SDValue Tmp = getValue(I.getOperand(1)); 4688 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 4689 Tmp.getValueType(), Tmp)); 4690 return; 4691 } 4692 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 4693 if (I.getNumOperands() == 2 && // Basic sanity checks. 4694 I.getOperand(1)->getType()->isFloatingPointTy() && 4695 I.getType() == I.getOperand(1)->getType() && 4696 I.onlyReadsMemory()) { 4697 SDValue Tmp = getValue(I.getOperand(1)); 4698 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 4699 Tmp.getValueType(), Tmp)); 4700 return; 4701 } 4702 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 4703 if (I.getNumOperands() == 2 && // Basic sanity checks. 4704 I.getOperand(1)->getType()->isFloatingPointTy() && 4705 I.getType() == I.getOperand(1)->getType() && 4706 I.onlyReadsMemory()) { 4707 SDValue Tmp = getValue(I.getOperand(1)); 4708 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 4709 Tmp.getValueType(), Tmp)); 4710 return; 4711 } 4712 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 4713 if (I.getNumOperands() == 2 && // Basic sanity checks. 4714 I.getOperand(1)->getType()->isFloatingPointTy() && 4715 I.getType() == I.getOperand(1)->getType() && 4716 I.onlyReadsMemory()) { 4717 SDValue Tmp = getValue(I.getOperand(1)); 4718 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 4719 Tmp.getValueType(), Tmp)); 4720 return; 4721 } 4722 } else if (Name == "memcmp") { 4723 if (visitMemCmpCall(I)) 4724 return; 4725 } 4726 } 4727 } else if (isa<InlineAsm>(I.getOperand(0))) { 4728 visitInlineAsm(&I); 4729 return; 4730 } 4731 4732 SDValue Callee; 4733 if (!RenameFn) 4734 Callee = getValue(I.getOperand(0)); 4735 else 4736 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 4737 4738 // Check if we can potentially perform a tail call. More detailed checking is 4739 // be done within LowerCallTo, after more information about the call is known. 4740 LowerCallTo(&I, Callee, I.isTailCall()); 4741} 4742 4743/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 4744/// this value and returns the result as a ValueVT value. This uses 4745/// Chain/Flag as the input and updates them for the output Chain/Flag. 4746/// If the Flag pointer is NULL, no flag is used. 4747SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, 4748 SDValue &Chain, SDValue *Flag) const { 4749 // Assemble the legal parts into the final values. 4750 SmallVector<SDValue, 4> Values(ValueVTs.size()); 4751 SmallVector<SDValue, 8> Parts; 4752 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 4753 // Copy the legal parts from the registers. 4754 EVT ValueVT = ValueVTs[Value]; 4755 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT); 4756 EVT RegisterVT = RegVTs[Value]; 4757 4758 Parts.resize(NumRegs); 4759 for (unsigned i = 0; i != NumRegs; ++i) { 4760 SDValue P; 4761 if (Flag == 0) { 4762 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 4763 } else { 4764 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 4765 *Flag = P.getValue(2); 4766 } 4767 4768 Chain = P.getValue(1); 4769 4770 // If the source register was virtual and if we know something about it, 4771 // add an assert node. 4772 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && 4773 RegisterVT.isInteger() && !RegisterVT.isVector()) { 4774 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; 4775 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 4776 if (FLI.LiveOutRegInfo.size() > SlotNo) { 4777 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo]; 4778 4779 unsigned RegSize = RegisterVT.getSizeInBits(); 4780 unsigned NumSignBits = LOI.NumSignBits; 4781 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 4782 4783 // FIXME: We capture more information than the dag can represent. For 4784 // now, just use the tightest assertzext/assertsext possible. 4785 bool isSExt = true; 4786 EVT FromVT(MVT::Other); 4787 if (NumSignBits == RegSize) 4788 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 4789 else if (NumZeroBits >= RegSize-1) 4790 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 4791 else if (NumSignBits > RegSize-8) 4792 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 4793 else if (NumZeroBits >= RegSize-8) 4794 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 4795 else if (NumSignBits > RegSize-16) 4796 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 4797 else if (NumZeroBits >= RegSize-16) 4798 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 4799 else if (NumSignBits > RegSize-32) 4800 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 4801 else if (NumZeroBits >= RegSize-32) 4802 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 4803 4804 if (FromVT != MVT::Other) 4805 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 4806 RegisterVT, P, DAG.getValueType(FromVT)); 4807 } 4808 } 4809 4810 Parts[i] = P; 4811 } 4812 4813 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 4814 NumRegs, RegisterVT, ValueVT); 4815 Part += NumRegs; 4816 Parts.clear(); 4817 } 4818 4819 return DAG.getNode(ISD::MERGE_VALUES, dl, 4820 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 4821 &Values[0], ValueVTs.size()); 4822} 4823 4824/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 4825/// specified value into the registers specified by this object. This uses 4826/// Chain/Flag as the input and updates them for the output Chain/Flag. 4827/// If the Flag pointer is NULL, no flag is used. 4828void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 4829 SDValue &Chain, SDValue *Flag) const { 4830 // Get the list of the values's legal parts. 4831 unsigned NumRegs = Regs.size(); 4832 SmallVector<SDValue, 8> Parts(NumRegs); 4833 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 4834 EVT ValueVT = ValueVTs[Value]; 4835 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT); 4836 EVT RegisterVT = RegVTs[Value]; 4837 4838 getCopyToParts(DAG, dl, 4839 Val.getValue(Val.getResNo() + Value), 4840 &Parts[Part], NumParts, RegisterVT); 4841 Part += NumParts; 4842 } 4843 4844 // Copy the parts into the registers. 4845 SmallVector<SDValue, 8> Chains(NumRegs); 4846 for (unsigned i = 0; i != NumRegs; ++i) { 4847 SDValue Part; 4848 if (Flag == 0) { 4849 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 4850 } else { 4851 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 4852 *Flag = Part.getValue(1); 4853 } 4854 4855 Chains[i] = Part.getValue(0); 4856 } 4857 4858 if (NumRegs == 1 || Flag) 4859 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 4860 // flagged to it. That is the CopyToReg nodes and the user are considered 4861 // a single scheduling unit. If we create a TokenFactor and return it as 4862 // chain, then the TokenFactor is both a predecessor (operand) of the 4863 // user as well as a successor (the TF operands are flagged to the user). 4864 // c1, f1 = CopyToReg 4865 // c2, f2 = CopyToReg 4866 // c3 = TokenFactor c1, c2 4867 // ... 4868 // = op c3, ..., f2 4869 Chain = Chains[NumRegs-1]; 4870 else 4871 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 4872} 4873 4874/// AddInlineAsmOperands - Add this value to the specified inlineasm node 4875/// operand list. This adds the code marker and includes the number of 4876/// values added into it. 4877void RegsForValue::AddInlineAsmOperands(unsigned Code, 4878 bool HasMatching,unsigned MatchingIdx, 4879 SelectionDAG &DAG, 4880 std::vector<SDValue> &Ops) const { 4881 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!"); 4882 unsigned Flag = Code | (Regs.size() << 3); 4883 if (HasMatching) 4884 Flag |= 0x80000000 | (MatchingIdx << 16); 4885 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 4886 Ops.push_back(Res); 4887 4888 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 4889 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 4890 EVT RegisterVT = RegVTs[Value]; 4891 for (unsigned i = 0; i != NumRegs; ++i) { 4892 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 4893 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 4894 } 4895 } 4896} 4897 4898/// isAllocatableRegister - If the specified register is safe to allocate, 4899/// i.e. it isn't a stack pointer or some other special register, return the 4900/// register class for the register. Otherwise, return null. 4901static const TargetRegisterClass * 4902isAllocatableRegister(unsigned Reg, MachineFunction &MF, 4903 const TargetLowering &TLI, 4904 const TargetRegisterInfo *TRI) { 4905 EVT FoundVT = MVT::Other; 4906 const TargetRegisterClass *FoundRC = 0; 4907 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 4908 E = TRI->regclass_end(); RCI != E; ++RCI) { 4909 EVT ThisVT = MVT::Other; 4910 4911 const TargetRegisterClass *RC = *RCI; 4912 // If none of the value types for this register class are valid, we 4913 // can't use it. For example, 64-bit reg classes on 32-bit targets. 4914 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 4915 I != E; ++I) { 4916 if (TLI.isTypeLegal(*I)) { 4917 // If we have already found this register in a different register class, 4918 // choose the one with the largest VT specified. For example, on 4919 // PowerPC, we favor f64 register classes over f32. 4920 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 4921 ThisVT = *I; 4922 break; 4923 } 4924 } 4925 } 4926 4927 if (ThisVT == MVT::Other) continue; 4928 4929 // NOTE: This isn't ideal. In particular, this might allocate the 4930 // frame pointer in functions that need it (due to them not being taken 4931 // out of allocation, because a variable sized allocation hasn't been seen 4932 // yet). This is a slight code pessimization, but should still work. 4933 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 4934 E = RC->allocation_order_end(MF); I != E; ++I) 4935 if (*I == Reg) { 4936 // We found a matching register class. Keep looking at others in case 4937 // we find one with larger registers that this physreg is also in. 4938 FoundRC = RC; 4939 FoundVT = ThisVT; 4940 break; 4941 } 4942 } 4943 return FoundRC; 4944} 4945 4946 4947namespace llvm { 4948/// AsmOperandInfo - This contains information for each constraint that we are 4949/// lowering. 4950class VISIBILITY_HIDDEN SDISelAsmOperandInfo : 4951 public TargetLowering::AsmOperandInfo { 4952public: 4953 /// CallOperand - If this is the result output operand or a clobber 4954 /// this is null, otherwise it is the incoming operand to the CallInst. 4955 /// This gets modified as the asm is processed. 4956 SDValue CallOperand; 4957 4958 /// AssignedRegs - If this is a register or register class operand, this 4959 /// contains the set of register corresponding to the operand. 4960 RegsForValue AssignedRegs; 4961 4962 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info) 4963 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 4964 } 4965 4966 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 4967 /// busy in OutputRegs/InputRegs. 4968 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 4969 std::set<unsigned> &OutputRegs, 4970 std::set<unsigned> &InputRegs, 4971 const TargetRegisterInfo &TRI) const { 4972 if (isOutReg) { 4973 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 4974 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 4975 } 4976 if (isInReg) { 4977 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 4978 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 4979 } 4980 } 4981 4982 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 4983 /// corresponds to. If there is no Value* for this operand, it returns 4984 /// MVT::Other. 4985 EVT getCallOperandValEVT(LLVMContext &Context, 4986 const TargetLowering &TLI, 4987 const TargetData *TD) const { 4988 if (CallOperandVal == 0) return MVT::Other; 4989 4990 if (isa<BasicBlock>(CallOperandVal)) 4991 return TLI.getPointerTy(); 4992 4993 const llvm::Type *OpTy = CallOperandVal->getType(); 4994 4995 // If this is an indirect operand, the operand is a pointer to the 4996 // accessed type. 4997 if (isIndirect) { 4998 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 4999 if (!PtrTy) 5000 llvm_report_error("Indirect operand for inline asm not a pointer!"); 5001 OpTy = PtrTy->getElementType(); 5002 } 5003 5004 // If OpTy is not a single value, it may be a struct/union that we 5005 // can tile with integers. 5006 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5007 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5008 switch (BitSize) { 5009 default: break; 5010 case 1: 5011 case 8: 5012 case 16: 5013 case 32: 5014 case 64: 5015 case 128: 5016 OpTy = IntegerType::get(Context, BitSize); 5017 break; 5018 } 5019 } 5020 5021 return TLI.getValueType(OpTy, true); 5022 } 5023 5024private: 5025 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5026 /// specified set. 5027 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5028 const TargetRegisterInfo &TRI) { 5029 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5030 Regs.insert(Reg); 5031 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5032 for (; *Aliases; ++Aliases) 5033 Regs.insert(*Aliases); 5034 } 5035}; 5036} // end llvm namespace. 5037 5038 5039/// GetRegistersForValue - Assign registers (virtual or physical) for the 5040/// specified operand. We prefer to assign virtual registers, to allow the 5041/// register allocator to handle the assignment process. However, if the asm 5042/// uses features that we can't model on machineinstrs, we have SDISel do the 5043/// allocation. This produces generally horrible, but correct, code. 5044/// 5045/// OpInfo describes the operand. 5046/// Input and OutputRegs are the set of already allocated physical registers. 5047/// 5048void SelectionDAGBuilder:: 5049GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, 5050 std::set<unsigned> &OutputRegs, 5051 std::set<unsigned> &InputRegs) { 5052 LLVMContext &Context = FuncInfo.Fn->getContext(); 5053 5054 // Compute whether this value requires an input register, an output register, 5055 // or both. 5056 bool isOutReg = false; 5057 bool isInReg = false; 5058 switch (OpInfo.Type) { 5059 case InlineAsm::isOutput: 5060 isOutReg = true; 5061 5062 // If there is an input constraint that matches this, we need to reserve 5063 // the input register so no other inputs allocate to it. 5064 isInReg = OpInfo.hasMatchingInput(); 5065 break; 5066 case InlineAsm::isInput: 5067 isInReg = true; 5068 isOutReg = false; 5069 break; 5070 case InlineAsm::isClobber: 5071 isOutReg = true; 5072 isInReg = true; 5073 break; 5074 } 5075 5076 5077 MachineFunction &MF = DAG.getMachineFunction(); 5078 SmallVector<unsigned, 4> Regs; 5079 5080 // If this is a constraint for a single physreg, or a constraint for a 5081 // register class, find it. 5082 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5083 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5084 OpInfo.ConstraintVT); 5085 5086 unsigned NumRegs = 1; 5087 if (OpInfo.ConstraintVT != MVT::Other) { 5088 // If this is a FP input in an integer register (or visa versa) insert a bit 5089 // cast of the input value. More generally, handle any case where the input 5090 // value disagrees with the register class we plan to stick this in. 5091 if (OpInfo.Type == InlineAsm::isInput && 5092 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5093 // Try to convert to the first EVT that the reg class contains. If the 5094 // types are identical size, use a bitcast to convert (e.g. two differing 5095 // vector types). 5096 EVT RegVT = *PhysReg.second->vt_begin(); 5097 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5098 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5099 RegVT, OpInfo.CallOperand); 5100 OpInfo.ConstraintVT = RegVT; 5101 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5102 // If the input is a FP value and we want it in FP registers, do a 5103 // bitcast to the corresponding integer type. This turns an f64 value 5104 // into i64, which can be passed with two i32 values on a 32-bit 5105 // machine. 5106 RegVT = EVT::getIntegerVT(Context, 5107 OpInfo.ConstraintVT.getSizeInBits()); 5108 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5109 RegVT, OpInfo.CallOperand); 5110 OpInfo.ConstraintVT = RegVT; 5111 } 5112 } 5113 5114 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5115 } 5116 5117 EVT RegVT; 5118 EVT ValueVT = OpInfo.ConstraintVT; 5119 5120 // If this is a constraint for a specific physical register, like {r17}, 5121 // assign it now. 5122 if (unsigned AssignedReg = PhysReg.first) { 5123 const TargetRegisterClass *RC = PhysReg.second; 5124 if (OpInfo.ConstraintVT == MVT::Other) 5125 ValueVT = *RC->vt_begin(); 5126 5127 // Get the actual register value type. This is important, because the user 5128 // may have asked for (e.g.) the AX register in i32 type. We need to 5129 // remember that AX is actually i16 to get the right extension. 5130 RegVT = *RC->vt_begin(); 5131 5132 // This is a explicit reference to a physical register. 5133 Regs.push_back(AssignedReg); 5134 5135 // If this is an expanded reference, add the rest of the regs to Regs. 5136 if (NumRegs != 1) { 5137 TargetRegisterClass::iterator I = RC->begin(); 5138 for (; *I != AssignedReg; ++I) 5139 assert(I != RC->end() && "Didn't find reg!"); 5140 5141 // Already added the first reg. 5142 --NumRegs; ++I; 5143 for (; NumRegs; --NumRegs, ++I) { 5144 assert(I != RC->end() && "Ran out of registers to allocate!"); 5145 Regs.push_back(*I); 5146 } 5147 } 5148 5149 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); 5150 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5151 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5152 return; 5153 } 5154 5155 // Otherwise, if this was a reference to an LLVM register class, create vregs 5156 // for this reference. 5157 if (const TargetRegisterClass *RC = PhysReg.second) { 5158 RegVT = *RC->vt_begin(); 5159 if (OpInfo.ConstraintVT == MVT::Other) 5160 ValueVT = RegVT; 5161 5162 // Create the appropriate number of virtual registers. 5163 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5164 for (; NumRegs; --NumRegs) 5165 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5166 5167 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); 5168 return; 5169 } 5170 5171 // This is a reference to a register class that doesn't directly correspond 5172 // to an LLVM register class. Allocate NumRegs consecutive, available, 5173 // registers from the class. 5174 std::vector<unsigned> RegClassRegs 5175 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 5176 OpInfo.ConstraintVT); 5177 5178 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5179 unsigned NumAllocated = 0; 5180 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 5181 unsigned Reg = RegClassRegs[i]; 5182 // See if this register is available. 5183 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 5184 (isInReg && InputRegs.count(Reg))) { // Already used. 5185 // Make sure we find consecutive registers. 5186 NumAllocated = 0; 5187 continue; 5188 } 5189 5190 // Check to see if this register is allocatable (i.e. don't give out the 5191 // stack pointer). 5192 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); 5193 if (!RC) { // Couldn't allocate this register. 5194 // Reset NumAllocated to make sure we return consecutive registers. 5195 NumAllocated = 0; 5196 continue; 5197 } 5198 5199 // Okay, this register is good, we can use it. 5200 ++NumAllocated; 5201 5202 // If we allocated enough consecutive registers, succeed. 5203 if (NumAllocated == NumRegs) { 5204 unsigned RegStart = (i-NumAllocated)+1; 5205 unsigned RegEnd = i+1; 5206 // Mark all of the allocated registers used. 5207 for (unsigned i = RegStart; i != RegEnd; ++i) 5208 Regs.push_back(RegClassRegs[i]); 5209 5210 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(), 5211 OpInfo.ConstraintVT); 5212 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5213 return; 5214 } 5215 } 5216 5217 // Otherwise, we couldn't allocate enough registers for this. 5218} 5219 5220/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being 5221/// processed uses a memory 'm' constraint. 5222static bool 5223hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos, 5224 const TargetLowering &TLI) { 5225 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) { 5226 InlineAsm::ConstraintInfo &CI = CInfos[i]; 5227 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) { 5228 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]); 5229 if (CType == TargetLowering::C_Memory) 5230 return true; 5231 } 5232 5233 // Indirect operand accesses access memory. 5234 if (CI.isIndirect) 5235 return true; 5236 } 5237 5238 return false; 5239} 5240 5241/// visitInlineAsm - Handle a call to an InlineAsm object. 5242/// 5243void SelectionDAGBuilder::visitInlineAsm(CallSite CS) { 5244 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5245 5246 /// ConstraintOperands - Information about all of the constraints. 5247 std::vector<SDISelAsmOperandInfo> ConstraintOperands; 5248 5249 std::set<unsigned> OutputRegs, InputRegs; 5250 5251 // Do a prepass over the constraints, canonicalizing them, and building up the 5252 // ConstraintOperands list. 5253 std::vector<InlineAsm::ConstraintInfo> 5254 ConstraintInfos = IA->ParseConstraints(); 5255 5256 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI); 5257 5258 SDValue Chain, Flag; 5259 5260 // We won't need to flush pending loads if this asm doesn't touch 5261 // memory and is nonvolatile. 5262 if (hasMemory || IA->hasSideEffects()) 5263 Chain = getRoot(); 5264 else 5265 Chain = DAG.getRoot(); 5266 5267 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5268 unsigned ResNo = 0; // ResNo - The result number of the next output. 5269 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 5270 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); 5271 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5272 5273 EVT OpVT = MVT::Other; 5274 5275 // Compute the value type for each operand. 5276 switch (OpInfo.Type) { 5277 case InlineAsm::isOutput: 5278 // Indirect outputs just consume an argument. 5279 if (OpInfo.isIndirect) { 5280 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 5281 break; 5282 } 5283 5284 // The return value of the call is this value. As such, there is no 5285 // corresponding argument. 5286 assert(!CS.getType()->isVoidTy() && 5287 "Bad inline asm!"); 5288 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5289 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5290 } else { 5291 assert(ResNo == 0 && "Asm only has one result!"); 5292 OpVT = TLI.getValueType(CS.getType()); 5293 } 5294 ++ResNo; 5295 break; 5296 case InlineAsm::isInput: 5297 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 5298 break; 5299 case InlineAsm::isClobber: 5300 // Nothing to do. 5301 break; 5302 } 5303 5304 // If this is an input or an indirect output, process the call argument. 5305 // BasicBlocks are labels, currently appearing only in asm's. 5306 if (OpInfo.CallOperandVal) { 5307 // Strip bitcasts, if any. This mostly comes up for functions. 5308 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts(); 5309 5310 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5311 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5312 } else { 5313 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5314 } 5315 5316 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5317 } 5318 5319 OpInfo.ConstraintVT = OpVT; 5320 } 5321 5322 // Second pass over the constraints: compute which constraint option to use 5323 // and assign registers to constraints that want a specific physreg. 5324 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 5325 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5326 5327 // If this is an output operand with a matching input operand, look up the 5328 // matching input. If their types mismatch, e.g. one is an integer, the 5329 // other is floating point, or their sizes are different, flag it as an 5330 // error. 5331 if (OpInfo.hasMatchingInput()) { 5332 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5333 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5334 if ((OpInfo.ConstraintVT.isInteger() != 5335 Input.ConstraintVT.isInteger()) || 5336 (OpInfo.ConstraintVT.getSizeInBits() != 5337 Input.ConstraintVT.getSizeInBits())) { 5338 llvm_report_error("Unsupported asm: input constraint" 5339 " with a matching output constraint of incompatible" 5340 " type!"); 5341 } 5342 Input.ConstraintVT = OpInfo.ConstraintVT; 5343 } 5344 } 5345 5346 // Compute the constraint code and ConstraintType to use. 5347 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG); 5348 5349 // If this is a memory input, and if the operand is not indirect, do what we 5350 // need to to provide an address for the memory input. 5351 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5352 !OpInfo.isIndirect) { 5353 assert(OpInfo.Type == InlineAsm::isInput && 5354 "Can only indirectify direct input operands!"); 5355 5356 // Memory operands really want the address of the value. If we don't have 5357 // an indirect input, put it in the constpool if we can, otherwise spill 5358 // it to a stack slot. 5359 5360 // If the operand is a float, integer, or vector constant, spill to a 5361 // constant pool entry to get its address. 5362 Value *OpVal = OpInfo.CallOperandVal; 5363 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5364 isa<ConstantVector>(OpVal)) { 5365 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5366 TLI.getPointerTy()); 5367 } else { 5368 // Otherwise, create a stack slot and emit a store to it before the 5369 // asm. 5370 const Type *Ty = OpVal->getType(); 5371 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5372 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5373 MachineFunction &MF = DAG.getMachineFunction(); 5374 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5375 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5376 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5377 OpInfo.CallOperand, StackSlot, NULL, 0, 5378 false, false, 0); 5379 OpInfo.CallOperand = StackSlot; 5380 } 5381 5382 // There is no longer a Value* corresponding to this operand. 5383 OpInfo.CallOperandVal = 0; 5384 5385 // It is now an indirect operand. 5386 OpInfo.isIndirect = true; 5387 } 5388 5389 // If this constraint is for a specific register, allocate it before 5390 // anything else. 5391 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5392 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5393 } 5394 5395 ConstraintInfos.clear(); 5396 5397 // Second pass - Loop over all of the operands, assigning virtual or physregs 5398 // to register class operands. 5399 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5400 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5401 5402 // C_Register operands have already been allocated, Other/Memory don't need 5403 // to be. 5404 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5405 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5406 } 5407 5408 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5409 std::vector<SDValue> AsmNodeOperands; 5410 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5411 AsmNodeOperands.push_back( 5412 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5413 TLI.getPointerTy())); 5414 5415 5416 // Loop over all of the inputs, copying the operand values into the 5417 // appropriate registers and processing the output regs. 5418 RegsForValue RetValRegs; 5419 5420 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5421 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5422 5423 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5424 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5425 5426 switch (OpInfo.Type) { 5427 case InlineAsm::isOutput: { 5428 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5429 OpInfo.ConstraintType != TargetLowering::C_Register) { 5430 // Memory output, or 'other' output (e.g. 'X' constraint). 5431 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5432 5433 // Add information to the INLINEASM node to know about this output. 5434 unsigned ResOpType = 4/*MEM*/ | (1<<3); 5435 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5436 TLI.getPointerTy())); 5437 AsmNodeOperands.push_back(OpInfo.CallOperand); 5438 break; 5439 } 5440 5441 // Otherwise, this is a register or register class output. 5442 5443 // Copy the output from the appropriate register. Find a register that 5444 // we can use. 5445 if (OpInfo.AssignedRegs.Regs.empty()) { 5446 llvm_report_error("Couldn't allocate output reg for" 5447 " constraint '" + OpInfo.ConstraintCode + "'!"); 5448 } 5449 5450 // If this is an indirect operand, store through the pointer after the 5451 // asm. 5452 if (OpInfo.isIndirect) { 5453 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5454 OpInfo.CallOperandVal)); 5455 } else { 5456 // This is the result value of the call. 5457 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5458 // Concatenate this output onto the outputs list. 5459 RetValRegs.append(OpInfo.AssignedRegs); 5460 } 5461 5462 // Add information to the INLINEASM node to know that this register is 5463 // set. 5464 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5465 6 /* EARLYCLOBBER REGDEF */ : 5466 2 /* REGDEF */ , 5467 false, 5468 0, 5469 DAG, 5470 AsmNodeOperands); 5471 break; 5472 } 5473 case InlineAsm::isInput: { 5474 SDValue InOperandVal = OpInfo.CallOperand; 5475 5476 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5477 // If this is required to match an output register we have already set, 5478 // just use its register. 5479 unsigned OperandNo = OpInfo.getMatchedOperand(); 5480 5481 // Scan until we find the definition we already emitted of this operand. 5482 // When we find it, create a RegsForValue operand. 5483 unsigned CurOp = 2; // The first operand. 5484 for (; OperandNo; --OperandNo) { 5485 // Advance to the next operand. 5486 unsigned OpFlag = 5487 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5488 assert(((OpFlag & 7) == 2 /*REGDEF*/ || 5489 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ || 5490 (OpFlag & 7) == 4 /*MEM*/) && 5491 "Skipped past definitions?"); 5492 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5493 } 5494 5495 unsigned OpFlag = 5496 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5497 if ((OpFlag & 7) == 2 /*REGDEF*/ 5498 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) { 5499 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5500 if (OpInfo.isIndirect) { 5501 llvm_report_error("Don't know how to handle tied indirect " 5502 "register inputs yet!"); 5503 } 5504 RegsForValue MatchedRegs; 5505 MatchedRegs.TLI = &TLI; 5506 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5507 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5508 MatchedRegs.RegVTs.push_back(RegVT); 5509 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5510 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5511 i != e; ++i) 5512 MatchedRegs.Regs.push_back 5513 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5514 5515 // Use the produced MatchedRegs object to 5516 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5517 Chain, &Flag); 5518 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, 5519 true, OpInfo.getMatchedOperand(), 5520 DAG, AsmNodeOperands); 5521 break; 5522 } else { 5523 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!"); 5524 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 && 5525 "Unexpected number of operands"); 5526 // Add information to the INLINEASM node to know about this input. 5527 // See InlineAsm.h isUseOperandTiedToDef. 5528 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16); 5529 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5530 TLI.getPointerTy())); 5531 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5532 break; 5533 } 5534 } 5535 5536 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5537 assert(!OpInfo.isIndirect && 5538 "Don't know how to handle indirect other inputs yet!"); 5539 5540 std::vector<SDValue> Ops; 5541 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 5542 hasMemory, Ops, DAG); 5543 if (Ops.empty()) { 5544 llvm_report_error("Invalid operand for inline asm" 5545 " constraint '" + OpInfo.ConstraintCode + "'!"); 5546 } 5547 5548 // Add information to the INLINEASM node to know about this input. 5549 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 5550 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5551 TLI.getPointerTy())); 5552 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5553 break; 5554 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5555 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5556 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5557 "Memory operands expect pointer values"); 5558 5559 // Add information to the INLINEASM node to know about this input. 5560 unsigned ResOpType = 4/*MEM*/ | (1<<3); 5561 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5562 TLI.getPointerTy())); 5563 AsmNodeOperands.push_back(InOperandVal); 5564 break; 5565 } 5566 5567 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5568 OpInfo.ConstraintType == TargetLowering::C_Register) && 5569 "Unknown constraint type!"); 5570 assert(!OpInfo.isIndirect && 5571 "Don't know how to handle indirect register inputs yet!"); 5572 5573 // Copy the input into the appropriate registers. 5574 if (OpInfo.AssignedRegs.Regs.empty() || 5575 !OpInfo.AssignedRegs.areValueTypesLegal()) { 5576 llvm_report_error("Couldn't allocate input reg for" 5577 " constraint '"+ OpInfo.ConstraintCode +"'!"); 5578 } 5579 5580 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5581 Chain, &Flag); 5582 5583 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0, 5584 DAG, AsmNodeOperands); 5585 break; 5586 } 5587 case InlineAsm::isClobber: { 5588 // Add the clobbered value to the operand list, so that the register 5589 // allocator is aware that the physreg got clobbered. 5590 if (!OpInfo.AssignedRegs.Regs.empty()) 5591 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */, 5592 false, 0, DAG, 5593 AsmNodeOperands); 5594 break; 5595 } 5596 } 5597 } 5598 5599 // Finish up input operands. 5600 AsmNodeOperands[0] = Chain; 5601 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5602 5603 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5604 DAG.getVTList(MVT::Other, MVT::Flag), 5605 &AsmNodeOperands[0], AsmNodeOperands.size()); 5606 Flag = Chain.getValue(1); 5607 5608 // If this asm returns a register value, copy the result from that register 5609 // and set it as the value of the call. 5610 if (!RetValRegs.Regs.empty()) { 5611 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(), 5612 Chain, &Flag); 5613 5614 // FIXME: Why don't we do this for inline asms with MRVs? 5615 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5616 EVT ResultType = TLI.getValueType(CS.getType()); 5617 5618 // If any of the results of the inline asm is a vector, it may have the 5619 // wrong width/num elts. This can happen for register classes that can 5620 // contain multiple different value types. The preg or vreg allocated may 5621 // not have the same VT as was expected. Convert it to the right type 5622 // with bit_convert. 5623 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5624 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5625 ResultType, Val); 5626 5627 } else if (ResultType != Val.getValueType() && 5628 ResultType.isInteger() && Val.getValueType().isInteger()) { 5629 // If a result value was tied to an input value, the computed result may 5630 // have a wider width than the expected result. Extract the relevant 5631 // portion. 5632 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 5633 } 5634 5635 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 5636 } 5637 5638 setValue(CS.getInstruction(), Val); 5639 // Don't need to use this as a chain in this case. 5640 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 5641 return; 5642 } 5643 5644 std::vector<std::pair<SDValue, Value*> > StoresToEmit; 5645 5646 // Process indirect outputs, first output all of the flagged copies out of 5647 // physregs. 5648 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 5649 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 5650 Value *Ptr = IndirectStoresToEmit[i].second; 5651 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(), 5652 Chain, &Flag); 5653 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 5654 5655 } 5656 5657 // Emit the non-flagged stores from the physregs. 5658 SmallVector<SDValue, 8> OutChains; 5659 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 5660 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 5661 StoresToEmit[i].first, 5662 getValue(StoresToEmit[i].second), 5663 StoresToEmit[i].second, 0, 5664 false, false, 0); 5665 OutChains.push_back(Val); 5666 } 5667 5668 if (!OutChains.empty()) 5669 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 5670 &OutChains[0], OutChains.size()); 5671 5672 DAG.setRoot(Chain); 5673} 5674 5675void SelectionDAGBuilder::visitVAStart(CallInst &I) { 5676 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 5677 MVT::Other, getRoot(), 5678 getValue(I.getOperand(1)), 5679 DAG.getSrcValue(I.getOperand(1)))); 5680} 5681 5682void SelectionDAGBuilder::visitVAArg(VAArgInst &I) { 5683 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 5684 getRoot(), getValue(I.getOperand(0)), 5685 DAG.getSrcValue(I.getOperand(0))); 5686 setValue(&I, V); 5687 DAG.setRoot(V.getValue(1)); 5688} 5689 5690void SelectionDAGBuilder::visitVAEnd(CallInst &I) { 5691 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 5692 MVT::Other, getRoot(), 5693 getValue(I.getOperand(1)), 5694 DAG.getSrcValue(I.getOperand(1)))); 5695} 5696 5697void SelectionDAGBuilder::visitVACopy(CallInst &I) { 5698 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 5699 MVT::Other, getRoot(), 5700 getValue(I.getOperand(1)), 5701 getValue(I.getOperand(2)), 5702 DAG.getSrcValue(I.getOperand(1)), 5703 DAG.getSrcValue(I.getOperand(2)))); 5704} 5705 5706/// TargetLowering::LowerCallTo - This is the default LowerCallTo 5707/// implementation, which just calls LowerCall. 5708/// FIXME: When all targets are 5709/// migrated to using LowerCall, this hook should be integrated into SDISel. 5710std::pair<SDValue, SDValue> 5711TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 5712 bool RetSExt, bool RetZExt, bool isVarArg, 5713 bool isInreg, unsigned NumFixedArgs, 5714 CallingConv::ID CallConv, bool isTailCall, 5715 bool isReturnValueUsed, 5716 SDValue Callee, 5717 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) { 5718 // Handle all of the outgoing arguments. 5719 SmallVector<ISD::OutputArg, 32> Outs; 5720 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 5721 SmallVector<EVT, 4> ValueVTs; 5722 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 5723 for (unsigned Value = 0, NumValues = ValueVTs.size(); 5724 Value != NumValues; ++Value) { 5725 EVT VT = ValueVTs[Value]; 5726 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 5727 SDValue Op = SDValue(Args[i].Node.getNode(), 5728 Args[i].Node.getResNo() + Value); 5729 ISD::ArgFlagsTy Flags; 5730 unsigned OriginalAlignment = 5731 getTargetData()->getABITypeAlignment(ArgTy); 5732 5733 if (Args[i].isZExt) 5734 Flags.setZExt(); 5735 if (Args[i].isSExt) 5736 Flags.setSExt(); 5737 if (Args[i].isInReg) 5738 Flags.setInReg(); 5739 if (Args[i].isSRet) 5740 Flags.setSRet(); 5741 if (Args[i].isByVal) { 5742 Flags.setByVal(); 5743 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 5744 const Type *ElementTy = Ty->getElementType(); 5745 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 5746 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy); 5747 // For ByVal, alignment should come from FE. BE will guess if this 5748 // info is not there but there are cases it cannot get right. 5749 if (Args[i].Alignment) 5750 FrameAlign = Args[i].Alignment; 5751 Flags.setByValAlign(FrameAlign); 5752 Flags.setByValSize(FrameSize); 5753 } 5754 if (Args[i].isNest) 5755 Flags.setNest(); 5756 Flags.setOrigAlign(OriginalAlignment); 5757 5758 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 5759 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 5760 SmallVector<SDValue, 4> Parts(NumParts); 5761 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 5762 5763 if (Args[i].isSExt) 5764 ExtendKind = ISD::SIGN_EXTEND; 5765 else if (Args[i].isZExt) 5766 ExtendKind = ISD::ZERO_EXTEND; 5767 5768 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 5769 PartVT, ExtendKind); 5770 5771 for (unsigned j = 0; j != NumParts; ++j) { 5772 // if it isn't first piece, alignment must be 1 5773 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs); 5774 if (NumParts > 1 && j == 0) 5775 MyFlags.Flags.setSplit(); 5776 else if (j != 0) 5777 MyFlags.Flags.setOrigAlign(1); 5778 5779 Outs.push_back(MyFlags); 5780 } 5781 } 5782 } 5783 5784 // Handle the incoming return values from the call. 5785 SmallVector<ISD::InputArg, 32> Ins; 5786 SmallVector<EVT, 4> RetTys; 5787 ComputeValueVTs(*this, RetTy, RetTys); 5788 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5789 EVT VT = RetTys[I]; 5790 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5791 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5792 for (unsigned i = 0; i != NumRegs; ++i) { 5793 ISD::InputArg MyFlags; 5794 MyFlags.VT = RegisterVT; 5795 MyFlags.Used = isReturnValueUsed; 5796 if (RetSExt) 5797 MyFlags.Flags.setSExt(); 5798 if (RetZExt) 5799 MyFlags.Flags.setZExt(); 5800 if (isInreg) 5801 MyFlags.Flags.setInReg(); 5802 Ins.push_back(MyFlags); 5803 } 5804 } 5805 5806 SmallVector<SDValue, 4> InVals; 5807 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 5808 Outs, Ins, dl, DAG, InVals); 5809 5810 // Verify that the target's LowerCall behaved as expected. 5811 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 5812 "LowerCall didn't return a valid chain!"); 5813 assert((!isTailCall || InVals.empty()) && 5814 "LowerCall emitted a return value for a tail call!"); 5815 assert((isTailCall || InVals.size() == Ins.size()) && 5816 "LowerCall didn't emit the correct number of values!"); 5817 5818 // For a tail call, the return value is merely live-out and there aren't 5819 // any nodes in the DAG representing it. Return a special value to 5820 // indicate that a tail call has been emitted and no more Instructions 5821 // should be processed in the current block. 5822 if (isTailCall) { 5823 DAG.setRoot(Chain); 5824 return std::make_pair(SDValue(), SDValue()); 5825 } 5826 5827 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 5828 assert(InVals[i].getNode() && 5829 "LowerCall emitted a null value!"); 5830 assert(Ins[i].VT == InVals[i].getValueType() && 5831 "LowerCall emitted a value with the wrong type!"); 5832 }); 5833 5834 // Collect the legal value parts into potentially illegal values 5835 // that correspond to the original function's return values. 5836 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5837 if (RetSExt) 5838 AssertOp = ISD::AssertSext; 5839 else if (RetZExt) 5840 AssertOp = ISD::AssertZext; 5841 SmallVector<SDValue, 4> ReturnValues; 5842 unsigned CurReg = 0; 5843 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5844 EVT VT = RetTys[I]; 5845 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5846 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5847 5848 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 5849 NumRegs, RegisterVT, VT, 5850 AssertOp)); 5851 CurReg += NumRegs; 5852 } 5853 5854 // For a function returning void, there is no return value. We can't create 5855 // such a node, so we just return a null return value in that case. In 5856 // that case, nothing will actualy look at the value. 5857 if (ReturnValues.empty()) 5858 return std::make_pair(SDValue(), Chain); 5859 5860 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 5861 DAG.getVTList(&RetTys[0], RetTys.size()), 5862 &ReturnValues[0], ReturnValues.size()); 5863 return std::make_pair(Res, Chain); 5864} 5865 5866void TargetLowering::LowerOperationWrapper(SDNode *N, 5867 SmallVectorImpl<SDValue> &Results, 5868 SelectionDAG &DAG) { 5869 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 5870 if (Res.getNode()) 5871 Results.push_back(Res); 5872} 5873 5874SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 5875 llvm_unreachable("LowerOperation not implemented for this target!"); 5876 return SDValue(); 5877} 5878 5879void SelectionDAGBuilder::CopyValueToVirtualRegister(Value *V, unsigned Reg) { 5880 SDValue Op = getValue(V); 5881 assert((Op.getOpcode() != ISD::CopyFromReg || 5882 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 5883 "Copy from a reg to the same reg!"); 5884 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 5885 5886 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 5887 SDValue Chain = DAG.getEntryNode(); 5888 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 5889 PendingExports.push_back(Chain); 5890} 5891 5892#include "llvm/CodeGen/SelectionDAGISel.h" 5893 5894void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) { 5895 // If this is the entry block, emit arguments. 5896 Function &F = *LLVMBB->getParent(); 5897 SelectionDAG &DAG = SDB->DAG; 5898 SDValue OldRoot = DAG.getRoot(); 5899 DebugLoc dl = SDB->getCurDebugLoc(); 5900 const TargetData *TD = TLI.getTargetData(); 5901 SmallVector<ISD::InputArg, 16> Ins; 5902 5903 // Check whether the function can return without sret-demotion. 5904 SmallVector<EVT, 4> OutVTs; 5905 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags; 5906 getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 5907 OutVTs, OutsFlags, TLI); 5908 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 5909 5910 FLI.CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(), F.isVarArg(), 5911 OutVTs, OutsFlags, DAG); 5912 if (!FLI.CanLowerReturn) { 5913 // Put in an sret pointer parameter before all the other parameters. 5914 SmallVector<EVT, 1> ValueVTs; 5915 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 5916 5917 // NOTE: Assuming that a pointer will never break down to more than one VT 5918 // or one register. 5919 ISD::ArgFlagsTy Flags; 5920 Flags.setSRet(); 5921 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), ValueVTs[0]); 5922 ISD::InputArg RetArg(Flags, RegisterVT, true); 5923 Ins.push_back(RetArg); 5924 } 5925 5926 // Set up the incoming argument description vector. 5927 unsigned Idx = 1; 5928 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 5929 I != E; ++I, ++Idx) { 5930 SmallVector<EVT, 4> ValueVTs; 5931 ComputeValueVTs(TLI, I->getType(), ValueVTs); 5932 bool isArgValueUsed = !I->use_empty(); 5933 for (unsigned Value = 0, NumValues = ValueVTs.size(); 5934 Value != NumValues; ++Value) { 5935 EVT VT = ValueVTs[Value]; 5936 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 5937 ISD::ArgFlagsTy Flags; 5938 unsigned OriginalAlignment = 5939 TD->getABITypeAlignment(ArgTy); 5940 5941 if (F.paramHasAttr(Idx, Attribute::ZExt)) 5942 Flags.setZExt(); 5943 if (F.paramHasAttr(Idx, Attribute::SExt)) 5944 Flags.setSExt(); 5945 if (F.paramHasAttr(Idx, Attribute::InReg)) 5946 Flags.setInReg(); 5947 if (F.paramHasAttr(Idx, Attribute::StructRet)) 5948 Flags.setSRet(); 5949 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 5950 Flags.setByVal(); 5951 const PointerType *Ty = cast<PointerType>(I->getType()); 5952 const Type *ElementTy = Ty->getElementType(); 5953 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy); 5954 unsigned FrameSize = TD->getTypeAllocSize(ElementTy); 5955 // For ByVal, alignment should be passed from FE. BE will guess if 5956 // this info is not there but there are cases it cannot get right. 5957 if (F.getParamAlignment(Idx)) 5958 FrameAlign = F.getParamAlignment(Idx); 5959 Flags.setByValAlign(FrameAlign); 5960 Flags.setByValSize(FrameSize); 5961 } 5962 if (F.paramHasAttr(Idx, Attribute::Nest)) 5963 Flags.setNest(); 5964 Flags.setOrigAlign(OriginalAlignment); 5965 5966 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 5967 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 5968 for (unsigned i = 0; i != NumRegs; ++i) { 5969 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 5970 if (NumRegs > 1 && i == 0) 5971 MyFlags.Flags.setSplit(); 5972 // if it isn't first piece, alignment must be 1 5973 else if (i > 0) 5974 MyFlags.Flags.setOrigAlign(1); 5975 Ins.push_back(MyFlags); 5976 } 5977 } 5978 } 5979 5980 // Call the target to set up the argument values. 5981 SmallVector<SDValue, 8> InVals; 5982 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 5983 F.isVarArg(), Ins, 5984 dl, DAG, InVals); 5985 5986 // Verify that the target's LowerFormalArguments behaved as expected. 5987 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 5988 "LowerFormalArguments didn't return a valid chain!"); 5989 assert(InVals.size() == Ins.size() && 5990 "LowerFormalArguments didn't emit the correct number of values!"); 5991 DEBUG({ 5992 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 5993 assert(InVals[i].getNode() && 5994 "LowerFormalArguments emitted a null value!"); 5995 assert(Ins[i].VT == InVals[i].getValueType() && 5996 "LowerFormalArguments emitted a value with the wrong type!"); 5997 } 5998 }); 5999 6000 // Update the DAG with the new chain value resulting from argument lowering. 6001 DAG.setRoot(NewRoot); 6002 6003 // Set up the argument values. 6004 unsigned i = 0; 6005 Idx = 1; 6006 if (!FLI.CanLowerReturn) { 6007 // Create a virtual register for the sret pointer, and put in a copy 6008 // from the sret argument into it. 6009 SmallVector<EVT, 1> ValueVTs; 6010 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6011 EVT VT = ValueVTs[0]; 6012 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6013 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6014 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6015 RegVT, VT, AssertOp); 6016 6017 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6018 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6019 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6020 FLI.DemoteRegister = SRetReg; 6021 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6022 SRetReg, ArgValue); 6023 DAG.setRoot(NewRoot); 6024 6025 // i indexes lowered arguments. Bump it past the hidden sret argument. 6026 // Idx indexes LLVM arguments. Don't touch it. 6027 ++i; 6028 } 6029 6030 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6031 ++I, ++Idx) { 6032 SmallVector<SDValue, 4> ArgValues; 6033 SmallVector<EVT, 4> ValueVTs; 6034 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6035 unsigned NumValues = ValueVTs.size(); 6036 for (unsigned Value = 0; Value != NumValues; ++Value) { 6037 EVT VT = ValueVTs[Value]; 6038 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6039 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6040 6041 if (!I->use_empty()) { 6042 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6043 if (F.paramHasAttr(Idx, Attribute::SExt)) 6044 AssertOp = ISD::AssertSext; 6045 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6046 AssertOp = ISD::AssertZext; 6047 6048 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6049 NumParts, PartVT, VT, 6050 AssertOp)); 6051 } 6052 6053 i += NumParts; 6054 } 6055 6056 if (!I->use_empty()) { 6057 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6058 SDB->getCurDebugLoc()); 6059 SDB->setValue(I, Res); 6060 6061 // If this argument is live outside of the entry block, insert a copy from 6062 // whereever we got it to the vreg that other BB's will reference it as. 6063 SDB->CopyToExportRegsIfNeeded(I); 6064 } 6065 } 6066 6067 assert(i == InVals.size() && "Argument register count mismatch!"); 6068 6069 // Finally, if the target has anything special to do, allow it to do so. 6070 // FIXME: this should insert code into the DAG! 6071 EmitFunctionEntryCode(F, SDB->DAG.getMachineFunction()); 6072} 6073 6074/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6075/// ensure constants are generated when needed. Remember the virtual registers 6076/// that need to be added to the Machine PHI nodes as input. We cannot just 6077/// directly add them, because expansion might result in multiple MBB's for one 6078/// BB. As such, the start of the BB might correspond to a different MBB than 6079/// the end. 6080/// 6081void 6082SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) { 6083 TerminatorInst *TI = LLVMBB->getTerminator(); 6084 6085 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6086 6087 // Check successor nodes' PHI nodes that expect a constant to be available 6088 // from this block. 6089 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6090 BasicBlock *SuccBB = TI->getSuccessor(succ); 6091 if (!isa<PHINode>(SuccBB->begin())) continue; 6092 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB]; 6093 6094 // If this terminator has multiple identical successors (common for 6095 // switches), only handle each succ once. 6096 if (!SuccsHandled.insert(SuccMBB)) continue; 6097 6098 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6099 PHINode *PN; 6100 6101 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6102 // nodes and Machine PHI nodes, but the incoming operands have not been 6103 // emitted yet. 6104 for (BasicBlock::iterator I = SuccBB->begin(); 6105 (PN = dyn_cast<PHINode>(I)); ++I) { 6106 // Ignore dead phi's. 6107 if (PN->use_empty()) continue; 6108 6109 unsigned Reg; 6110 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6111 6112 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 6113 unsigned &RegOut = SDB->ConstantsOut[C]; 6114 if (RegOut == 0) { 6115 RegOut = FuncInfo->CreateRegForValue(C); 6116 SDB->CopyValueToVirtualRegister(C, RegOut); 6117 } 6118 Reg = RegOut; 6119 } else { 6120 Reg = FuncInfo->ValueMap[PHIOp]; 6121 if (Reg == 0) { 6122 assert(isa<AllocaInst>(PHIOp) && 6123 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6124 "Didn't codegen value into a register!??"); 6125 Reg = FuncInfo->CreateRegForValue(PHIOp); 6126 SDB->CopyValueToVirtualRegister(PHIOp, Reg); 6127 } 6128 } 6129 6130 // Remember that this register needs to added to the machine PHI node as 6131 // the input for this MBB. 6132 SmallVector<EVT, 4> ValueVTs; 6133 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6134 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6135 EVT VT = ValueVTs[vti]; 6136 unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6137 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6138 SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6139 Reg += NumRegisters; 6140 } 6141 } 6142 } 6143 SDB->ConstantsOut.clear(); 6144} 6145 6146/// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only 6147/// supports legal types, and it emits MachineInstrs directly instead of 6148/// creating SelectionDAG nodes. 6149/// 6150bool 6151SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, 6152 FastISel *F) { 6153 TerminatorInst *TI = LLVMBB->getTerminator(); 6154 6155 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6156 unsigned OrigNumPHINodesToUpdate = SDB->PHINodesToUpdate.size(); 6157 6158 // Check successor nodes' PHI nodes that expect a constant to be available 6159 // from this block. 6160 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6161 BasicBlock *SuccBB = TI->getSuccessor(succ); 6162 if (!isa<PHINode>(SuccBB->begin())) continue; 6163 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB]; 6164 6165 // If this terminator has multiple identical successors (common for 6166 // switches), only handle each succ once. 6167 if (!SuccsHandled.insert(SuccMBB)) continue; 6168 6169 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6170 PHINode *PN; 6171 6172 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6173 // nodes and Machine PHI nodes, but the incoming operands have not been 6174 // emitted yet. 6175 for (BasicBlock::iterator I = SuccBB->begin(); 6176 (PN = dyn_cast<PHINode>(I)); ++I) { 6177 // Ignore dead phi's. 6178 if (PN->use_empty()) continue; 6179 6180 // Only handle legal types. Two interesting things to note here. First, 6181 // by bailing out early, we may leave behind some dead instructions, 6182 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its 6183 // own moves. Second, this check is necessary becuase FastISel doesn't 6184 // use CreateRegForValue to create registers, so it always creates 6185 // exactly one register for each non-void instruction. 6186 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true); 6187 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) { 6188 // Promote MVT::i1. 6189 if (VT == MVT::i1) 6190 VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT); 6191 else { 6192 SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 6193 return false; 6194 } 6195 } 6196 6197 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6198 6199 unsigned Reg = F->getRegForValue(PHIOp); 6200 if (Reg == 0) { 6201 SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 6202 return false; 6203 } 6204 SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg)); 6205 } 6206 } 6207 6208 return true; 6209} 6210