SelectionDAGISel.cpp revision 014e04a5daeb312b1f0ebc1dd906ffc97c4abc5f
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/Collector.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetData.h" 40#include "llvm/Target/TargetFrameInfo.h" 41#include "llvm/Target/TargetInstrInfo.h" 42#include "llvm/Target/TargetLowering.h" 43#include "llvm/Target/TargetMachine.h" 44#include "llvm/Target/TargetOptions.h" 45#include "llvm/Support/MathExtras.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/Compiler.h" 48#include <algorithm> 49using namespace llvm; 50 51#ifndef NDEBUG 52static cl::opt<bool> 53ViewISelDAGs("view-isel-dags", cl::Hidden, 54 cl::desc("Pop up a window to show isel dags as they are selected")); 55static cl::opt<bool> 56ViewSchedDAGs("view-sched-dags", cl::Hidden, 57 cl::desc("Pop up a window to show sched dags as they are processed")); 58static cl::opt<bool> 59ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 60 cl::desc("Pop up a window to show SUnit dags after they are processed")); 61#else 62static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0; 63#endif 64 65//===---------------------------------------------------------------------===// 66/// 67/// RegisterScheduler class - Track the registration of instruction schedulers. 68/// 69//===---------------------------------------------------------------------===// 70MachinePassRegistry RegisterScheduler::Registry; 71 72//===---------------------------------------------------------------------===// 73/// 74/// ISHeuristic command line option for instruction schedulers. 75/// 76//===---------------------------------------------------------------------===// 77namespace { 78 cl::opt<RegisterScheduler::FunctionPassCtor, false, 79 RegisterPassParser<RegisterScheduler> > 80 ISHeuristic("pre-RA-sched", 81 cl::init(&createDefaultScheduler), 82 cl::desc("Instruction schedulers available (before register" 83 " allocation):")); 84 85 static RegisterScheduler 86 defaultListDAGScheduler("default", " Best scheduler for the target", 87 createDefaultScheduler); 88} // namespace 89 90namespace { struct AsmOperandInfo; } 91 92namespace { 93 /// RegsForValue - This struct represents the physical registers that a 94 /// particular value is assigned and the type information about the value. 95 /// This is needed because values can be promoted into larger registers and 96 /// expanded into multiple smaller registers than the value. 97 struct VISIBILITY_HIDDEN RegsForValue { 98 /// Regs - This list holds the register (for legal and promoted values) 99 /// or register set (for expanded values) that the value should be assigned 100 /// to. 101 std::vector<unsigned> Regs; 102 103 /// RegVT - The value type of each register. 104 /// 105 MVT::ValueType RegVT; 106 107 /// ValueVT - The value type of the LLVM value, which may be promoted from 108 /// RegVT or made from merging the two expanded parts. 109 MVT::ValueType ValueVT; 110 111 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 112 113 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 114 : RegVT(regvt), ValueVT(valuevt) { 115 Regs.push_back(Reg); 116 } 117 RegsForValue(const std::vector<unsigned> ®s, 118 MVT::ValueType regvt, MVT::ValueType valuevt) 119 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 120 } 121 122 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 123 /// this value and returns the result as a ValueVT value. This uses 124 /// Chain/Flag as the input and updates them for the output Chain/Flag. 125 /// If the Flag pointer is NULL, no flag is used. 126 SDOperand getCopyFromRegs(SelectionDAG &DAG, 127 SDOperand &Chain, SDOperand *Flag) const; 128 129 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 130 /// specified value into the registers specified by this object. This uses 131 /// Chain/Flag as the input and updates them for the output Chain/Flag. 132 /// If the Flag pointer is NULL, no flag is used. 133 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 134 SDOperand &Chain, SDOperand *Flag) const; 135 136 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 137 /// operand list. This adds the code marker and includes the number of 138 /// values added into it. 139 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 140 std::vector<SDOperand> &Ops) const; 141 }; 142} 143 144namespace llvm { 145 //===--------------------------------------------------------------------===// 146 /// createDefaultScheduler - This creates an instruction scheduler appropriate 147 /// for the target. 148 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 149 SelectionDAG *DAG, 150 MachineBasicBlock *BB) { 151 TargetLowering &TLI = IS->getTargetLowering(); 152 153 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 154 return createTDListDAGScheduler(IS, DAG, BB); 155 } else { 156 assert(TLI.getSchedulingPreference() == 157 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 158 return createBURRListDAGScheduler(IS, DAG, BB); 159 } 160 } 161 162 163 //===--------------------------------------------------------------------===// 164 /// FunctionLoweringInfo - This contains information that is global to a 165 /// function that is used when lowering a region of the function. 166 class FunctionLoweringInfo { 167 public: 168 TargetLowering &TLI; 169 Function &Fn; 170 MachineFunction &MF; 171 MachineRegisterInfo &RegInfo; 172 173 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 174 175 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 176 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 177 178 /// ValueMap - Since we emit code for the function a basic block at a time, 179 /// we must remember which virtual registers hold the values for 180 /// cross-basic-block values. 181 DenseMap<const Value*, unsigned> ValueMap; 182 183 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 184 /// the entry block. This allows the allocas to be efficiently referenced 185 /// anywhere in the function. 186 std::map<const AllocaInst*, int> StaticAllocaMap; 187 188#ifndef NDEBUG 189 SmallSet<Instruction*, 8> CatchInfoLost; 190 SmallSet<Instruction*, 8> CatchInfoFound; 191#endif 192 193 unsigned MakeReg(MVT::ValueType VT) { 194 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT)); 195 } 196 197 /// isExportedInst - Return true if the specified value is an instruction 198 /// exported from its block. 199 bool isExportedInst(const Value *V) { 200 return ValueMap.count(V); 201 } 202 203 unsigned CreateRegForValue(const Value *V); 204 205 unsigned InitializeRegForValue(const Value *V) { 206 unsigned &R = ValueMap[V]; 207 assert(R == 0 && "Already initialized this value register!"); 208 return R = CreateRegForValue(V); 209 } 210 }; 211} 212 213/// isSelector - Return true if this instruction is a call to the 214/// eh.selector intrinsic. 215static bool isSelector(Instruction *I) { 216 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 217 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 || 218 II->getIntrinsicID() == Intrinsic::eh_selector_i64); 219 return false; 220} 221 222/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 223/// PHI nodes or outside of the basic block that defines it, or used by a 224/// switch instruction, which may expand to multiple basic blocks. 225static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 226 if (isa<PHINode>(I)) return true; 227 BasicBlock *BB = I->getParent(); 228 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 229 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 230 // FIXME: Remove switchinst special case. 231 isa<SwitchInst>(*UI)) 232 return true; 233 return false; 234} 235 236/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 237/// entry block, return true. This includes arguments used by switches, since 238/// the switch may expand into multiple basic blocks. 239static bool isOnlyUsedInEntryBlock(Argument *A) { 240 BasicBlock *Entry = A->getParent()->begin(); 241 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 242 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 243 return false; // Use not in entry block. 244 return true; 245} 246 247FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 248 Function &fn, MachineFunction &mf) 249 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) { 250 251 // Create a vreg for each argument register that is not dead and is used 252 // outside of the entry block for the function. 253 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 254 AI != E; ++AI) 255 if (!isOnlyUsedInEntryBlock(AI)) 256 InitializeRegForValue(AI); 257 258 // Initialize the mapping of values to registers. This is only set up for 259 // instruction values that are used outside of the block that defines 260 // them. 261 Function::iterator BB = Fn.begin(), EB = Fn.end(); 262 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 263 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 264 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 265 const Type *Ty = AI->getAllocatedType(); 266 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 267 unsigned Align = 268 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 269 AI->getAlignment()); 270 271 TySize *= CUI->getZExtValue(); // Get total allocated size. 272 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 273 StaticAllocaMap[AI] = 274 MF.getFrameInfo()->CreateStackObject(TySize, Align); 275 } 276 277 for (; BB != EB; ++BB) 278 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 279 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 280 if (!isa<AllocaInst>(I) || 281 !StaticAllocaMap.count(cast<AllocaInst>(I))) 282 InitializeRegForValue(I); 283 284 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 285 // also creates the initial PHI MachineInstrs, though none of the input 286 // operands are populated. 287 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 288 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 289 MBBMap[BB] = MBB; 290 MF.getBasicBlockList().push_back(MBB); 291 292 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 293 // appropriate. 294 PHINode *PN; 295 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 296 if (PN->use_empty()) continue; 297 298 MVT::ValueType VT = TLI.getValueType(PN->getType()); 299 unsigned NumRegisters = TLI.getNumRegisters(VT); 300 unsigned PHIReg = ValueMap[PN]; 301 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 302 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 303 for (unsigned i = 0; i != NumRegisters; ++i) 304 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 305 } 306 } 307} 308 309/// CreateRegForValue - Allocate the appropriate number of virtual registers of 310/// the correctly promoted or expanded types. Assign these registers 311/// consecutive vreg numbers and return the first assigned number. 312unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 313 MVT::ValueType VT = TLI.getValueType(V->getType()); 314 315 unsigned NumRegisters = TLI.getNumRegisters(VT); 316 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 317 318 unsigned R = MakeReg(RegisterVT); 319 for (unsigned i = 1; i != NumRegisters; ++i) 320 MakeReg(RegisterVT); 321 322 return R; 323} 324 325//===----------------------------------------------------------------------===// 326/// SelectionDAGLowering - This is the common target-independent lowering 327/// implementation that is parameterized by a TargetLowering object. 328/// Also, targets can overload any lowering method. 329/// 330namespace llvm { 331class SelectionDAGLowering { 332 MachineBasicBlock *CurMBB; 333 334 DenseMap<const Value*, SDOperand> NodeMap; 335 336 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 337 /// them up and then emit token factor nodes when possible. This allows us to 338 /// get simple disambiguation between loads without worrying about alias 339 /// analysis. 340 std::vector<SDOperand> PendingLoads; 341 342 /// Case - A struct to record the Value for a switch case, and the 343 /// case's target basic block. 344 struct Case { 345 Constant* Low; 346 Constant* High; 347 MachineBasicBlock* BB; 348 349 Case() : Low(0), High(0), BB(0) { } 350 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 351 Low(low), High(high), BB(bb) { } 352 uint64_t size() const { 353 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 354 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 355 return (rHigh - rLow + 1ULL); 356 } 357 }; 358 359 struct CaseBits { 360 uint64_t Mask; 361 MachineBasicBlock* BB; 362 unsigned Bits; 363 364 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 365 Mask(mask), BB(bb), Bits(bits) { } 366 }; 367 368 typedef std::vector<Case> CaseVector; 369 typedef std::vector<CaseBits> CaseBitsVector; 370 typedef CaseVector::iterator CaseItr; 371 typedef std::pair<CaseItr, CaseItr> CaseRange; 372 373 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 374 /// of conditional branches. 375 struct CaseRec { 376 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 377 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 378 379 /// CaseBB - The MBB in which to emit the compare and branch 380 MachineBasicBlock *CaseBB; 381 /// LT, GE - If nonzero, we know the current case value must be less-than or 382 /// greater-than-or-equal-to these Constants. 383 Constant *LT; 384 Constant *GE; 385 /// Range - A pair of iterators representing the range of case values to be 386 /// processed at this point in the binary search tree. 387 CaseRange Range; 388 }; 389 390 typedef std::vector<CaseRec> CaseRecVector; 391 392 /// The comparison function for sorting the switch case values in the vector. 393 /// WARNING: Case ranges should be disjoint! 394 struct CaseCmp { 395 bool operator () (const Case& C1, const Case& C2) { 396 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 397 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 398 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 399 return CI1->getValue().slt(CI2->getValue()); 400 } 401 }; 402 403 struct CaseBitsCmp { 404 bool operator () (const CaseBits& C1, const CaseBits& C2) { 405 return C1.Bits > C2.Bits; 406 } 407 }; 408 409 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 410 411public: 412 // TLI - This is information that describes the available target features we 413 // need for lowering. This indicates when operations are unavailable, 414 // implemented with a libcall, etc. 415 TargetLowering &TLI; 416 SelectionDAG &DAG; 417 const TargetData *TD; 418 AliasAnalysis &AA; 419 420 /// SwitchCases - Vector of CaseBlock structures used to communicate 421 /// SwitchInst code generation information. 422 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 423 /// JTCases - Vector of JumpTable structures used to communicate 424 /// SwitchInst code generation information. 425 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 426 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 427 428 /// FuncInfo - Information about the function as a whole. 429 /// 430 FunctionLoweringInfo &FuncInfo; 431 432 /// GCI - Garbage collection metadata for the function. 433 CollectorMetadata *GCI; 434 435 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 436 AliasAnalysis &aa, 437 FunctionLoweringInfo &funcinfo, 438 CollectorMetadata *gci) 439 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa), 440 FuncInfo(funcinfo), GCI(gci) { 441 } 442 443 /// getRoot - Return the current virtual root of the Selection DAG. 444 /// 445 SDOperand getRoot() { 446 if (PendingLoads.empty()) 447 return DAG.getRoot(); 448 449 if (PendingLoads.size() == 1) { 450 SDOperand Root = PendingLoads[0]; 451 DAG.setRoot(Root); 452 PendingLoads.clear(); 453 return Root; 454 } 455 456 // Otherwise, we have to make a token factor node. 457 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 458 &PendingLoads[0], PendingLoads.size()); 459 PendingLoads.clear(); 460 DAG.setRoot(Root); 461 return Root; 462 } 463 464 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 465 466 void visit(Instruction &I) { visit(I.getOpcode(), I); } 467 468 void visit(unsigned Opcode, User &I) { 469 // Note: this doesn't use InstVisitor, because it has to work with 470 // ConstantExpr's in addition to instructions. 471 switch (Opcode) { 472 default: assert(0 && "Unknown instruction type encountered!"); 473 abort(); 474 // Build the switch statement using the Instruction.def file. 475#define HANDLE_INST(NUM, OPCODE, CLASS) \ 476 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 477#include "llvm/Instruction.def" 478 } 479 } 480 481 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 482 483 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 484 const Value *SV, SDOperand Root, 485 bool isVolatile, unsigned Alignment); 486 487 SDOperand getValue(const Value *V); 488 489 void setValue(const Value *V, SDOperand NewN) { 490 SDOperand &N = NodeMap[V]; 491 assert(N.Val == 0 && "Already set a value for this node!"); 492 N = NewN; 493 } 494 495 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 496 std::set<unsigned> &OutputRegs, 497 std::set<unsigned> &InputRegs); 498 499 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 500 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 501 unsigned Opc); 502 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 503 void ExportFromCurrentBlock(Value *V); 504 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall, 505 MachineBasicBlock *LandingPad = NULL); 506 507 // Terminator instructions. 508 void visitRet(ReturnInst &I); 509 void visitBr(BranchInst &I); 510 void visitSwitch(SwitchInst &I); 511 void visitUnreachable(UnreachableInst &I) { /* noop */ } 512 513 // Helpers for visitSwitch 514 bool handleSmallSwitchRange(CaseRec& CR, 515 CaseRecVector& WorkList, 516 Value* SV, 517 MachineBasicBlock* Default); 518 bool handleJTSwitchCase(CaseRec& CR, 519 CaseRecVector& WorkList, 520 Value* SV, 521 MachineBasicBlock* Default); 522 bool handleBTSplitSwitchCase(CaseRec& CR, 523 CaseRecVector& WorkList, 524 Value* SV, 525 MachineBasicBlock* Default); 526 bool handleBitTestsSwitchCase(CaseRec& CR, 527 CaseRecVector& WorkList, 528 Value* SV, 529 MachineBasicBlock* Default); 530 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 531 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 532 void visitBitTestCase(MachineBasicBlock* NextMBB, 533 unsigned Reg, 534 SelectionDAGISel::BitTestCase &B); 535 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 536 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 537 SelectionDAGISel::JumpTableHeader &JTH); 538 539 // These all get lowered before this pass. 540 void visitInvoke(InvokeInst &I); 541 void visitUnwind(UnwindInst &I); 542 543 void visitBinary(User &I, unsigned OpCode); 544 void visitShift(User &I, unsigned Opcode); 545 void visitAdd(User &I) { 546 if (I.getType()->isFPOrFPVector()) 547 visitBinary(I, ISD::FADD); 548 else 549 visitBinary(I, ISD::ADD); 550 } 551 void visitSub(User &I); 552 void visitMul(User &I) { 553 if (I.getType()->isFPOrFPVector()) 554 visitBinary(I, ISD::FMUL); 555 else 556 visitBinary(I, ISD::MUL); 557 } 558 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 559 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 560 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 561 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 562 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 563 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 564 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 565 void visitOr (User &I) { visitBinary(I, ISD::OR); } 566 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 567 void visitShl (User &I) { visitShift(I, ISD::SHL); } 568 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 569 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 570 void visitICmp(User &I); 571 void visitFCmp(User &I); 572 // Visit the conversion instructions 573 void visitTrunc(User &I); 574 void visitZExt(User &I); 575 void visitSExt(User &I); 576 void visitFPTrunc(User &I); 577 void visitFPExt(User &I); 578 void visitFPToUI(User &I); 579 void visitFPToSI(User &I); 580 void visitUIToFP(User &I); 581 void visitSIToFP(User &I); 582 void visitPtrToInt(User &I); 583 void visitIntToPtr(User &I); 584 void visitBitCast(User &I); 585 586 void visitExtractElement(User &I); 587 void visitInsertElement(User &I); 588 void visitShuffleVector(User &I); 589 590 void visitGetElementPtr(User &I); 591 void visitSelect(User &I); 592 593 void visitMalloc(MallocInst &I); 594 void visitFree(FreeInst &I); 595 void visitAlloca(AllocaInst &I); 596 void visitLoad(LoadInst &I); 597 void visitStore(StoreInst &I); 598 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 599 void visitCall(CallInst &I); 600 void visitInlineAsm(CallSite CS); 601 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 602 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 603 604 void visitVAStart(CallInst &I); 605 void visitVAArg(VAArgInst &I); 606 void visitVAEnd(CallInst &I); 607 void visitVACopy(CallInst &I); 608 609 void visitMemIntrinsic(CallInst &I, unsigned Op); 610 611 void visitUserOp1(Instruction &I) { 612 assert(0 && "UserOp1 should not exist at instruction selection time!"); 613 abort(); 614 } 615 void visitUserOp2(Instruction &I) { 616 assert(0 && "UserOp2 should not exist at instruction selection time!"); 617 abort(); 618 } 619}; 620} // end namespace llvm 621 622 623/// getCopyFromParts - Create a value that contains the specified legal parts 624/// combined into the value they represent. If the parts combine to a type 625/// larger then ValueVT then AssertOp can be used to specify whether the extra 626/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 627/// (ISD::AssertSext). Likewise TruncExact is used for floating point types to 628/// indicate that the extra bits can be discarded without losing precision. 629static SDOperand getCopyFromParts(SelectionDAG &DAG, 630 const SDOperand *Parts, 631 unsigned NumParts, 632 MVT::ValueType PartVT, 633 MVT::ValueType ValueVT, 634 ISD::NodeType AssertOp = ISD::DELETED_NODE, 635 bool TruncExact = false) { 636 assert(NumParts > 0 && "No parts to assemble!"); 637 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 638 SDOperand Val = Parts[0]; 639 640 if (NumParts > 1) { 641 // Assemble the value from multiple parts. 642 if (!MVT::isVector(ValueVT)) { 643 unsigned PartBits = MVT::getSizeInBits(PartVT); 644 unsigned ValueBits = MVT::getSizeInBits(ValueVT); 645 646 // Assemble the power of 2 part. 647 unsigned RoundParts = NumParts & (NumParts - 1) ? 648 1 << Log2_32(NumParts) : NumParts; 649 unsigned RoundBits = PartBits * RoundParts; 650 MVT::ValueType RoundVT = RoundBits == ValueBits ? 651 ValueVT : MVT::getIntegerType(RoundBits); 652 SDOperand Lo, Hi; 653 654 if (RoundParts > 2) { 655 MVT::ValueType HalfVT = MVT::getIntegerType(RoundBits/2); 656 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT); 657 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2, 658 PartVT, HalfVT); 659 } else { 660 Lo = Parts[0]; 661 Hi = Parts[1]; 662 } 663 if (TLI.isBigEndian()) 664 std::swap(Lo, Hi); 665 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi); 666 667 if (RoundParts < NumParts) { 668 // Assemble the trailing non-power-of-2 part. 669 unsigned OddParts = NumParts - RoundParts; 670 MVT::ValueType OddVT = MVT::getIntegerType(OddParts * PartBits); 671 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT); 672 673 // Combine the round and odd parts. 674 Lo = Val; 675 if (TLI.isBigEndian()) 676 std::swap(Lo, Hi); 677 MVT::ValueType TotalVT = MVT::getIntegerType(NumParts * PartBits); 678 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi); 679 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi, 680 DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()), 681 TLI.getShiftAmountTy())); 682 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo); 683 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi); 684 } 685 } else { 686 // Handle a multi-element vector. 687 MVT::ValueType IntermediateVT, RegisterVT; 688 unsigned NumIntermediates; 689 unsigned NumRegs = 690 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 691 RegisterVT); 692 693 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 694 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 695 assert(RegisterVT == Parts[0].getValueType() && 696 "Part type doesn't match part!"); 697 698 // Assemble the parts into intermediate operands. 699 SmallVector<SDOperand, 8> Ops(NumIntermediates); 700 if (NumIntermediates == NumParts) { 701 // If the register was not expanded, truncate or copy the value, 702 // as appropriate. 703 for (unsigned i = 0; i != NumParts; ++i) 704 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 705 PartVT, IntermediateVT); 706 } else if (NumParts > 0) { 707 // If the intermediate type was expanded, build the intermediate operands 708 // from the parts. 709 assert(NumParts % NumIntermediates == 0 && 710 "Must expand into a divisible number of parts!"); 711 unsigned Factor = NumParts / NumIntermediates; 712 for (unsigned i = 0; i != NumIntermediates; ++i) 713 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 714 PartVT, IntermediateVT); 715 } 716 717 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 718 // operands. 719 Val = DAG.getNode(MVT::isVector(IntermediateVT) ? 720 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, 721 ValueVT, &Ops[0], NumIntermediates); 722 } 723 } 724 725 // There is now one part, held in Val. Correct it to match ValueVT. 726 PartVT = Val.getValueType(); 727 728 if (PartVT == ValueVT) 729 return Val; 730 731 if (MVT::isVector(PartVT)) { 732 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!"); 733 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 734 } 735 736 if (MVT::isVector(ValueVT)) { 737 assert(MVT::getVectorElementType(ValueVT) == PartVT && 738 MVT::getVectorNumElements(ValueVT) == 1 && 739 "Only trivial scalar-to-vector conversions should get here!"); 740 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val); 741 } 742 743 if (MVT::isInteger(PartVT) && 744 MVT::isInteger(ValueVT)) { 745 if (MVT::getSizeInBits(ValueVT) < MVT::getSizeInBits(PartVT)) { 746 // For a truncate, see if we have any information to 747 // indicate whether the truncated bits will always be 748 // zero or sign-extension. 749 if (AssertOp != ISD::DELETED_NODE) 750 Val = DAG.getNode(AssertOp, PartVT, Val, 751 DAG.getValueType(ValueVT)); 752 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 753 } else { 754 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 755 } 756 } 757 758 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) 759 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, 760 DAG.getIntPtrConstant(TruncExact)); 761 762 if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT)) 763 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 764 765 assert(0 && "Unknown mismatch!"); 766} 767 768/// getCopyToParts - Create a series of nodes that contain the specified value 769/// split into legal parts. If the parts contain more bits than Val, then, for 770/// integers, ExtendKind can be used to specify how to generate the extra bits. 771static void getCopyToParts(SelectionDAG &DAG, 772 SDOperand Val, 773 SDOperand *Parts, 774 unsigned NumParts, 775 MVT::ValueType PartVT, 776 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 777 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 778 MVT::ValueType PtrVT = TLI.getPointerTy(); 779 MVT::ValueType ValueVT = Val.getValueType(); 780 unsigned PartBits = MVT::getSizeInBits(PartVT); 781 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 782 783 if (!NumParts) 784 return; 785 786 if (!MVT::isVector(ValueVT)) { 787 if (PartVT == ValueVT) { 788 assert(NumParts == 1 && "No-op copy with multiple parts!"); 789 Parts[0] = Val; 790 return; 791 } 792 793 if (NumParts * PartBits > MVT::getSizeInBits(ValueVT)) { 794 // If the parts cover more bits than the value has, promote the value. 795 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) { 796 assert(NumParts == 1 && "Do not know what to promote to!"); 797 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 798 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 799 ValueVT = MVT::getIntegerType(NumParts * PartBits); 800 Val = DAG.getNode(ExtendKind, ValueVT, Val); 801 } else { 802 assert(0 && "Unknown mismatch!"); 803 } 804 } else if (PartBits == MVT::getSizeInBits(ValueVT)) { 805 // Different types of the same size. 806 assert(NumParts == 1 && PartVT != ValueVT); 807 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 808 } else if (NumParts * PartBits < MVT::getSizeInBits(ValueVT)) { 809 // If the parts cover less bits than value has, truncate the value. 810 if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 811 ValueVT = MVT::getIntegerType(NumParts * PartBits); 812 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 813 } else { 814 assert(0 && "Unknown mismatch!"); 815 } 816 } 817 818 // The value may have changed - recompute ValueVT. 819 ValueVT = Val.getValueType(); 820 assert(NumParts * PartBits == MVT::getSizeInBits(ValueVT) && 821 "Failed to tile the value with PartVT!"); 822 823 if (NumParts == 1) { 824 assert(PartVT == ValueVT && "Type conversion failed!"); 825 Parts[0] = Val; 826 return; 827 } 828 829 // Expand the value into multiple parts. 830 if (NumParts & (NumParts - 1)) { 831 // The number of parts is not a power of 2. Split off and copy the tail. 832 assert(MVT::isInteger(PartVT) && MVT::isInteger(ValueVT) && 833 "Do not know what to expand to!"); 834 unsigned RoundParts = 1 << Log2_32(NumParts); 835 unsigned RoundBits = RoundParts * PartBits; 836 unsigned OddParts = NumParts - RoundParts; 837 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val, 838 DAG.getConstant(RoundBits, 839 TLI.getShiftAmountTy())); 840 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT); 841 if (TLI.isBigEndian()) 842 // The odd parts were reversed by getCopyToParts - unreverse them. 843 std::reverse(Parts + RoundParts, Parts + NumParts); 844 NumParts = RoundParts; 845 ValueVT = MVT::getIntegerType(NumParts * PartBits); 846 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 847 } 848 849 // The number of parts is a power of 2. Repeatedly bisect the value using 850 // EXTRACT_ELEMENT. 851 Parts[0] = Val; 852 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 853 for (unsigned i = 0; i < NumParts; i += StepSize) { 854 unsigned ThisBits = StepSize * PartBits / 2; 855 MVT::ValueType ThisVT = 856 ThisBits == PartBits ? PartVT : MVT::getIntegerType (ThisBits); 857 858 Parts[i+StepSize/2] = 859 DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Parts[i], 860 DAG.getConstant(1, PtrVT)); 861 Parts[i] = 862 DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Parts[i], 863 DAG.getConstant(0, PtrVT)); 864 } 865 } 866 867 if (TLI.isBigEndian()) 868 std::reverse(Parts, Parts + NumParts); 869 870 return; 871 } 872 873 // Vector ValueVT. 874 if (NumParts == 1) { 875 if (PartVT != ValueVT) { 876 if (MVT::isVector(PartVT)) { 877 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 878 } else { 879 assert(MVT::getVectorElementType(ValueVT) == PartVT && 880 MVT::getVectorNumElements(ValueVT) == 1 && 881 "Only trivial vector-to-scalar conversions should get here!"); 882 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val, 883 DAG.getConstant(0, PtrVT)); 884 } 885 } 886 887 Parts[0] = Val; 888 return; 889 } 890 891 // Handle a multi-element vector. 892 MVT::ValueType IntermediateVT, RegisterVT; 893 unsigned NumIntermediates; 894 unsigned NumRegs = 895 DAG.getTargetLoweringInfo() 896 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 897 RegisterVT); 898 unsigned NumElements = MVT::getVectorNumElements(ValueVT); 899 900 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 901 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 902 903 // Split the vector into intermediate operands. 904 SmallVector<SDOperand, 8> Ops(NumIntermediates); 905 for (unsigned i = 0; i != NumIntermediates; ++i) 906 if (MVT::isVector(IntermediateVT)) 907 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 908 IntermediateVT, Val, 909 DAG.getConstant(i * (NumElements / NumIntermediates), 910 PtrVT)); 911 else 912 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 913 IntermediateVT, Val, 914 DAG.getConstant(i, PtrVT)); 915 916 // Split the intermediate operands into legal parts. 917 if (NumParts == NumIntermediates) { 918 // If the register was not expanded, promote or copy the value, 919 // as appropriate. 920 for (unsigned i = 0; i != NumParts; ++i) 921 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 922 } else if (NumParts > 0) { 923 // If the intermediate type was expanded, split each the value into 924 // legal parts. 925 assert(NumParts % NumIntermediates == 0 && 926 "Must expand into a divisible number of parts!"); 927 unsigned Factor = NumParts / NumIntermediates; 928 for (unsigned i = 0; i != NumIntermediates; ++i) 929 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 930 } 931} 932 933 934SDOperand SelectionDAGLowering::getValue(const Value *V) { 935 SDOperand &N = NodeMap[V]; 936 if (N.Val) return N; 937 938 const Type *VTy = V->getType(); 939 MVT::ValueType VT = TLI.getValueType(VTy); 940 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 941 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 942 visit(CE->getOpcode(), *CE); 943 SDOperand N1 = NodeMap[V]; 944 assert(N1.Val && "visit didn't populate the ValueMap!"); 945 return N1; 946 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 947 return N = DAG.getGlobalAddress(GV, VT); 948 } else if (isa<ConstantPointerNull>(C)) { 949 return N = DAG.getConstant(0, TLI.getPointerTy()); 950 } else if (isa<UndefValue>(C)) { 951 if (!isa<VectorType>(VTy)) 952 return N = DAG.getNode(ISD::UNDEF, VT); 953 954 // Create a BUILD_VECTOR of undef nodes. 955 const VectorType *PTy = cast<VectorType>(VTy); 956 unsigned NumElements = PTy->getNumElements(); 957 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 958 959 SmallVector<SDOperand, 8> Ops; 960 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 961 962 // Create a VConstant node with generic Vector type. 963 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 964 return N = DAG.getNode(ISD::BUILD_VECTOR, VT, 965 &Ops[0], Ops.size()); 966 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 967 return N = DAG.getConstantFP(CFP->getValueAPF(), VT); 968 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 969 unsigned NumElements = PTy->getNumElements(); 970 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 971 972 // Now that we know the number and type of the elements, push a 973 // Constant or ConstantFP node onto the ops list for each element of 974 // the vector constant. 975 SmallVector<SDOperand, 8> Ops; 976 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 977 for (unsigned i = 0; i != NumElements; ++i) 978 Ops.push_back(getValue(CP->getOperand(i))); 979 } else { 980 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 981 SDOperand Op; 982 if (MVT::isFloatingPoint(PVT)) 983 Op = DAG.getConstantFP(0, PVT); 984 else 985 Op = DAG.getConstant(0, PVT); 986 Ops.assign(NumElements, Op); 987 } 988 989 // Create a BUILD_VECTOR node. 990 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 991 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], 992 Ops.size()); 993 } else { 994 // Canonicalize all constant ints to be unsigned. 995 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT); 996 } 997 } 998 999 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1000 std::map<const AllocaInst*, int>::iterator SI = 1001 FuncInfo.StaticAllocaMap.find(AI); 1002 if (SI != FuncInfo.StaticAllocaMap.end()) 1003 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1004 } 1005 1006 unsigned InReg = FuncInfo.ValueMap[V]; 1007 assert(InReg && "Value not in map!"); 1008 1009 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 1010 unsigned NumRegs = TLI.getNumRegisters(VT); 1011 1012 std::vector<unsigned> Regs(NumRegs); 1013 for (unsigned i = 0; i != NumRegs; ++i) 1014 Regs[i] = InReg + i; 1015 1016 RegsForValue RFV(Regs, RegisterVT, VT); 1017 SDOperand Chain = DAG.getEntryNode(); 1018 1019 return RFV.getCopyFromRegs(DAG, Chain, NULL); 1020} 1021 1022 1023void SelectionDAGLowering::visitRet(ReturnInst &I) { 1024 if (I.getNumOperands() == 0) { 1025 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 1026 return; 1027 } 1028 SmallVector<SDOperand, 8> NewValues; 1029 NewValues.push_back(getRoot()); 1030 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 1031 SDOperand RetOp = getValue(I.getOperand(i)); 1032 MVT::ValueType VT = RetOp.getValueType(); 1033 1034 // FIXME: C calling convention requires the return type to be promoted to 1035 // at least 32-bit. But this is not necessary for non-C calling conventions. 1036 if (MVT::isInteger(VT)) { 1037 MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32); 1038 if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT)) 1039 VT = MinVT; 1040 } 1041 1042 unsigned NumParts = TLI.getNumRegisters(VT); 1043 MVT::ValueType PartVT = TLI.getRegisterType(VT); 1044 SmallVector<SDOperand, 4> Parts(NumParts); 1045 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1046 1047 const Function *F = I.getParent()->getParent(); 1048 if (F->paramHasAttr(0, ParamAttr::SExt)) 1049 ExtendKind = ISD::SIGN_EXTEND; 1050 else if (F->paramHasAttr(0, ParamAttr::ZExt)) 1051 ExtendKind = ISD::ZERO_EXTEND; 1052 1053 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, ExtendKind); 1054 1055 for (unsigned i = 0; i < NumParts; ++i) { 1056 NewValues.push_back(Parts[i]); 1057 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 1058 } 1059 } 1060 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 1061 &NewValues[0], NewValues.size())); 1062} 1063 1064/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1065/// the current basic block, add it to ValueMap now so that we'll get a 1066/// CopyTo/FromReg. 1067void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 1068 // No need to export constants. 1069 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1070 1071 // Already exported? 1072 if (FuncInfo.isExportedInst(V)) return; 1073 1074 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1075 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 1076} 1077 1078bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 1079 const BasicBlock *FromBB) { 1080 // The operands of the setcc have to be in this block. We don't know 1081 // how to export them from some other block. 1082 if (Instruction *VI = dyn_cast<Instruction>(V)) { 1083 // Can export from current BB. 1084 if (VI->getParent() == FromBB) 1085 return true; 1086 1087 // Is already exported, noop. 1088 return FuncInfo.isExportedInst(V); 1089 } 1090 1091 // If this is an argument, we can export it if the BB is the entry block or 1092 // if it is already exported. 1093 if (isa<Argument>(V)) { 1094 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1095 return true; 1096 1097 // Otherwise, can only export this if it is already exported. 1098 return FuncInfo.isExportedInst(V); 1099 } 1100 1101 // Otherwise, constants can always be exported. 1102 return true; 1103} 1104 1105static bool InBlock(const Value *V, const BasicBlock *BB) { 1106 if (const Instruction *I = dyn_cast<Instruction>(V)) 1107 return I->getParent() == BB; 1108 return true; 1109} 1110 1111/// FindMergedConditions - If Cond is an expression like 1112void SelectionDAGLowering::FindMergedConditions(Value *Cond, 1113 MachineBasicBlock *TBB, 1114 MachineBasicBlock *FBB, 1115 MachineBasicBlock *CurBB, 1116 unsigned Opc) { 1117 // If this node is not part of the or/and tree, emit it as a branch. 1118 Instruction *BOp = dyn_cast<Instruction>(Cond); 1119 1120 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1121 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1122 BOp->getParent() != CurBB->getBasicBlock() || 1123 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1124 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1125 const BasicBlock *BB = CurBB->getBasicBlock(); 1126 1127 // If the leaf of the tree is a comparison, merge the condition into 1128 // the caseblock. 1129 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1130 // The operands of the cmp have to be in this block. We don't know 1131 // how to export them from some other block. If this is the first block 1132 // of the sequence, no exporting is needed. 1133 (CurBB == CurMBB || 1134 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1135 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1136 BOp = cast<Instruction>(Cond); 1137 ISD::CondCode Condition; 1138 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1139 switch (IC->getPredicate()) { 1140 default: assert(0 && "Unknown icmp predicate opcode!"); 1141 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1142 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1143 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1144 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1145 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1146 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1147 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1148 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1149 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1150 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1151 } 1152 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1153 ISD::CondCode FPC, FOC; 1154 switch (FC->getPredicate()) { 1155 default: assert(0 && "Unknown fcmp predicate opcode!"); 1156 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1157 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1158 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1159 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1160 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1161 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1162 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1163 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 1164 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 1165 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1166 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1167 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1168 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1169 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1170 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1171 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1172 } 1173 if (FiniteOnlyFPMath()) 1174 Condition = FOC; 1175 else 1176 Condition = FPC; 1177 } else { 1178 Condition = ISD::SETEQ; // silence warning. 1179 assert(0 && "Unknown compare instruction"); 1180 } 1181 1182 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1183 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1184 SwitchCases.push_back(CB); 1185 return; 1186 } 1187 1188 // Create a CaseBlock record representing this branch. 1189 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1190 NULL, TBB, FBB, CurBB); 1191 SwitchCases.push_back(CB); 1192 return; 1193 } 1194 1195 1196 // Create TmpBB after CurBB. 1197 MachineFunction::iterator BBI = CurBB; 1198 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 1199 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 1200 1201 if (Opc == Instruction::Or) { 1202 // Codegen X | Y as: 1203 // jmp_if_X TBB 1204 // jmp TmpBB 1205 // TmpBB: 1206 // jmp_if_Y TBB 1207 // jmp FBB 1208 // 1209 1210 // Emit the LHS condition. 1211 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1212 1213 // Emit the RHS condition into TmpBB. 1214 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1215 } else { 1216 assert(Opc == Instruction::And && "Unknown merge op!"); 1217 // Codegen X & Y as: 1218 // jmp_if_X TmpBB 1219 // jmp FBB 1220 // TmpBB: 1221 // jmp_if_Y TBB 1222 // jmp FBB 1223 // 1224 // This requires creation of TmpBB after CurBB. 1225 1226 // Emit the LHS condition. 1227 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1228 1229 // Emit the RHS condition into TmpBB. 1230 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1231 } 1232} 1233 1234/// If the set of cases should be emitted as a series of branches, return true. 1235/// If we should emit this as a bunch of and/or'd together conditions, return 1236/// false. 1237static bool 1238ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1239 if (Cases.size() != 2) return true; 1240 1241 // If this is two comparisons of the same values or'd or and'd together, they 1242 // will get folded into a single comparison, so don't emit two blocks. 1243 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1244 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1245 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1246 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1247 return false; 1248 } 1249 1250 return true; 1251} 1252 1253void SelectionDAGLowering::visitBr(BranchInst &I) { 1254 // Update machine-CFG edges. 1255 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1256 1257 // Figure out which block is immediately after the current one. 1258 MachineBasicBlock *NextBlock = 0; 1259 MachineFunction::iterator BBI = CurMBB; 1260 if (++BBI != CurMBB->getParent()->end()) 1261 NextBlock = BBI; 1262 1263 if (I.isUnconditional()) { 1264 // If this is not a fall-through branch, emit the branch. 1265 if (Succ0MBB != NextBlock) 1266 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1267 DAG.getBasicBlock(Succ0MBB))); 1268 1269 // Update machine-CFG edges. 1270 CurMBB->addSuccessor(Succ0MBB); 1271 return; 1272 } 1273 1274 // If this condition is one of the special cases we handle, do special stuff 1275 // now. 1276 Value *CondVal = I.getCondition(); 1277 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1278 1279 // If this is a series of conditions that are or'd or and'd together, emit 1280 // this as a sequence of branches instead of setcc's with and/or operations. 1281 // For example, instead of something like: 1282 // cmp A, B 1283 // C = seteq 1284 // cmp D, E 1285 // F = setle 1286 // or C, F 1287 // jnz foo 1288 // Emit: 1289 // cmp A, B 1290 // je foo 1291 // cmp D, E 1292 // jle foo 1293 // 1294 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1295 if (BOp->hasOneUse() && 1296 (BOp->getOpcode() == Instruction::And || 1297 BOp->getOpcode() == Instruction::Or)) { 1298 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1299 // If the compares in later blocks need to use values not currently 1300 // exported from this block, export them now. This block should always 1301 // be the first entry. 1302 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1303 1304 // Allow some cases to be rejected. 1305 if (ShouldEmitAsBranches(SwitchCases)) { 1306 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1307 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1308 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1309 } 1310 1311 // Emit the branch for this block. 1312 visitSwitchCase(SwitchCases[0]); 1313 SwitchCases.erase(SwitchCases.begin()); 1314 return; 1315 } 1316 1317 // Okay, we decided not to do this, remove any inserted MBB's and clear 1318 // SwitchCases. 1319 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1320 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1321 1322 SwitchCases.clear(); 1323 } 1324 } 1325 1326 // Create a CaseBlock record representing this branch. 1327 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1328 NULL, Succ0MBB, Succ1MBB, CurMBB); 1329 // Use visitSwitchCase to actually insert the fast branch sequence for this 1330 // cond branch. 1331 visitSwitchCase(CB); 1332} 1333 1334/// visitSwitchCase - Emits the necessary code to represent a single node in 1335/// the binary search tree resulting from lowering a switch instruction. 1336void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1337 SDOperand Cond; 1338 SDOperand CondLHS = getValue(CB.CmpLHS); 1339 1340 // Build the setcc now. 1341 if (CB.CmpMHS == NULL) { 1342 // Fold "(X == true)" to X and "(X == false)" to !X to 1343 // handle common cases produced by branch lowering. 1344 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1345 Cond = CondLHS; 1346 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1347 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1348 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1349 } else 1350 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1351 } else { 1352 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1353 1354 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1355 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1356 1357 SDOperand CmpOp = getValue(CB.CmpMHS); 1358 MVT::ValueType VT = CmpOp.getValueType(); 1359 1360 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1361 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1362 } else { 1363 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1364 Cond = DAG.getSetCC(MVT::i1, SUB, 1365 DAG.getConstant(High-Low, VT), ISD::SETULE); 1366 } 1367 1368 } 1369 1370 // Set NextBlock to be the MBB immediately after the current one, if any. 1371 // This is used to avoid emitting unnecessary branches to the next block. 1372 MachineBasicBlock *NextBlock = 0; 1373 MachineFunction::iterator BBI = CurMBB; 1374 if (++BBI != CurMBB->getParent()->end()) 1375 NextBlock = BBI; 1376 1377 // If the lhs block is the next block, invert the condition so that we can 1378 // fall through to the lhs instead of the rhs block. 1379 if (CB.TrueBB == NextBlock) { 1380 std::swap(CB.TrueBB, CB.FalseBB); 1381 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1382 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1383 } 1384 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1385 DAG.getBasicBlock(CB.TrueBB)); 1386 if (CB.FalseBB == NextBlock) 1387 DAG.setRoot(BrCond); 1388 else 1389 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1390 DAG.getBasicBlock(CB.FalseBB))); 1391 // Update successor info 1392 CurMBB->addSuccessor(CB.TrueBB); 1393 CurMBB->addSuccessor(CB.FalseBB); 1394} 1395 1396/// visitJumpTable - Emit JumpTable node in the current MBB 1397void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1398 // Emit the code for the jump table 1399 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1400 MVT::ValueType PTy = TLI.getPointerTy(); 1401 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1402 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1403 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1404 Table, Index)); 1405 return; 1406} 1407 1408/// visitJumpTableHeader - This function emits necessary code to produce index 1409/// in the JumpTable from switch case. 1410void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1411 SelectionDAGISel::JumpTableHeader &JTH) { 1412 // Subtract the lowest switch case value from the value being switched on 1413 // and conditional branch to default mbb if the result is greater than the 1414 // difference between smallest and largest cases. 1415 SDOperand SwitchOp = getValue(JTH.SValue); 1416 MVT::ValueType VT = SwitchOp.getValueType(); 1417 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1418 DAG.getConstant(JTH.First, VT)); 1419 1420 // The SDNode we just created, which holds the value being switched on 1421 // minus the the smallest case value, needs to be copied to a virtual 1422 // register so it can be used as an index into the jump table in a 1423 // subsequent basic block. This value may be smaller or larger than the 1424 // target's pointer type, and therefore require extension or truncating. 1425 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 1426 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1427 else 1428 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1429 1430 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1431 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1432 JT.Reg = JumpTableReg; 1433 1434 // Emit the range check for the jump table, and branch to the default 1435 // block for the switch statement if the value being switched on exceeds 1436 // the largest case in the switch. 1437 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1438 DAG.getConstant(JTH.Last-JTH.First,VT), 1439 ISD::SETUGT); 1440 1441 // Set NextBlock to be the MBB immediately after the current one, if any. 1442 // This is used to avoid emitting unnecessary branches to the next block. 1443 MachineBasicBlock *NextBlock = 0; 1444 MachineFunction::iterator BBI = CurMBB; 1445 if (++BBI != CurMBB->getParent()->end()) 1446 NextBlock = BBI; 1447 1448 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1449 DAG.getBasicBlock(JT.Default)); 1450 1451 if (JT.MBB == NextBlock) 1452 DAG.setRoot(BrCond); 1453 else 1454 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1455 DAG.getBasicBlock(JT.MBB))); 1456 1457 return; 1458} 1459 1460/// visitBitTestHeader - This function emits necessary code to produce value 1461/// suitable for "bit tests" 1462void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1463 // Subtract the minimum value 1464 SDOperand SwitchOp = getValue(B.SValue); 1465 MVT::ValueType VT = SwitchOp.getValueType(); 1466 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1467 DAG.getConstant(B.First, VT)); 1468 1469 // Check range 1470 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1471 DAG.getConstant(B.Range, VT), 1472 ISD::SETUGT); 1473 1474 SDOperand ShiftOp; 1475 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy())) 1476 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1477 else 1478 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1479 1480 // Make desired shift 1481 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1482 DAG.getConstant(1, TLI.getPointerTy()), 1483 ShiftOp); 1484 1485 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1486 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1487 B.Reg = SwitchReg; 1488 1489 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1490 DAG.getBasicBlock(B.Default)); 1491 1492 // Set NextBlock to be the MBB immediately after the current one, if any. 1493 // This is used to avoid emitting unnecessary branches to the next block. 1494 MachineBasicBlock *NextBlock = 0; 1495 MachineFunction::iterator BBI = CurMBB; 1496 if (++BBI != CurMBB->getParent()->end()) 1497 NextBlock = BBI; 1498 1499 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1500 if (MBB == NextBlock) 1501 DAG.setRoot(BrRange); 1502 else 1503 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1504 DAG.getBasicBlock(MBB))); 1505 1506 CurMBB->addSuccessor(B.Default); 1507 CurMBB->addSuccessor(MBB); 1508 1509 return; 1510} 1511 1512/// visitBitTestCase - this function produces one "bit test" 1513void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1514 unsigned Reg, 1515 SelectionDAGISel::BitTestCase &B) { 1516 // Emit bit tests and jumps 1517 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1518 1519 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1520 SwitchVal, 1521 DAG.getConstant(B.Mask, 1522 TLI.getPointerTy())); 1523 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, 1524 DAG.getConstant(0, TLI.getPointerTy()), 1525 ISD::SETNE); 1526 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1527 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1528 1529 // Set NextBlock to be the MBB immediately after the current one, if any. 1530 // This is used to avoid emitting unnecessary branches to the next block. 1531 MachineBasicBlock *NextBlock = 0; 1532 MachineFunction::iterator BBI = CurMBB; 1533 if (++BBI != CurMBB->getParent()->end()) 1534 NextBlock = BBI; 1535 1536 if (NextMBB == NextBlock) 1537 DAG.setRoot(BrAnd); 1538 else 1539 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1540 DAG.getBasicBlock(NextMBB))); 1541 1542 CurMBB->addSuccessor(B.TargetBB); 1543 CurMBB->addSuccessor(NextMBB); 1544 1545 return; 1546} 1547 1548void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1549 // Retrieve successors. 1550 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1551 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1552 1553 if (isa<InlineAsm>(I.getCalledValue())) 1554 visitInlineAsm(&I); 1555 else 1556 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad); 1557 1558 // If the value of the invoke is used outside of its defining block, make it 1559 // available as a virtual register. 1560 if (!I.use_empty()) { 1561 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1562 if (VMI != FuncInfo.ValueMap.end()) 1563 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second)); 1564 } 1565 1566 // Drop into normal successor. 1567 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1568 DAG.getBasicBlock(Return))); 1569 1570 // Update successor info 1571 CurMBB->addSuccessor(Return); 1572 CurMBB->addSuccessor(LandingPad); 1573} 1574 1575void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1576} 1577 1578/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1579/// small case ranges). 1580bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1581 CaseRecVector& WorkList, 1582 Value* SV, 1583 MachineBasicBlock* Default) { 1584 Case& BackCase = *(CR.Range.second-1); 1585 1586 // Size is the number of Cases represented by this range. 1587 unsigned Size = CR.Range.second - CR.Range.first; 1588 if (Size > 3) 1589 return false; 1590 1591 // Get the MachineFunction which holds the current MBB. This is used when 1592 // inserting any additional MBBs necessary to represent the switch. 1593 MachineFunction *CurMF = CurMBB->getParent(); 1594 1595 // Figure out which block is immediately after the current one. 1596 MachineBasicBlock *NextBlock = 0; 1597 MachineFunction::iterator BBI = CR.CaseBB; 1598 1599 if (++BBI != CurMBB->getParent()->end()) 1600 NextBlock = BBI; 1601 1602 // TODO: If any two of the cases has the same destination, and if one value 1603 // is the same as the other, but has one bit unset that the other has set, 1604 // use bit manipulation to do two compares at once. For example: 1605 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1606 1607 // Rearrange the case blocks so that the last one falls through if possible. 1608 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1609 // The last case block won't fall through into 'NextBlock' if we emit the 1610 // branches in this order. See if rearranging a case value would help. 1611 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1612 if (I->BB == NextBlock) { 1613 std::swap(*I, BackCase); 1614 break; 1615 } 1616 } 1617 } 1618 1619 // Create a CaseBlock record representing a conditional branch to 1620 // the Case's target mbb if the value being switched on SV is equal 1621 // to C. 1622 MachineBasicBlock *CurBlock = CR.CaseBB; 1623 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1624 MachineBasicBlock *FallThrough; 1625 if (I != E-1) { 1626 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1627 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1628 } else { 1629 // If the last case doesn't match, go to the default block. 1630 FallThrough = Default; 1631 } 1632 1633 Value *RHS, *LHS, *MHS; 1634 ISD::CondCode CC; 1635 if (I->High == I->Low) { 1636 // This is just small small case range :) containing exactly 1 case 1637 CC = ISD::SETEQ; 1638 LHS = SV; RHS = I->High; MHS = NULL; 1639 } else { 1640 CC = ISD::SETLE; 1641 LHS = I->Low; MHS = SV; RHS = I->High; 1642 } 1643 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1644 I->BB, FallThrough, CurBlock); 1645 1646 // If emitting the first comparison, just call visitSwitchCase to emit the 1647 // code into the current block. Otherwise, push the CaseBlock onto the 1648 // vector to be later processed by SDISel, and insert the node's MBB 1649 // before the next MBB. 1650 if (CurBlock == CurMBB) 1651 visitSwitchCase(CB); 1652 else 1653 SwitchCases.push_back(CB); 1654 1655 CurBlock = FallThrough; 1656 } 1657 1658 return true; 1659} 1660 1661static inline bool areJTsAllowed(const TargetLowering &TLI) { 1662 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1663 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1664} 1665 1666/// handleJTSwitchCase - Emit jumptable for current switch case range 1667bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1668 CaseRecVector& WorkList, 1669 Value* SV, 1670 MachineBasicBlock* Default) { 1671 Case& FrontCase = *CR.Range.first; 1672 Case& BackCase = *(CR.Range.second-1); 1673 1674 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1675 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1676 1677 uint64_t TSize = 0; 1678 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1679 I!=E; ++I) 1680 TSize += I->size(); 1681 1682 if (!areJTsAllowed(TLI) || TSize <= 3) 1683 return false; 1684 1685 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1686 if (Density < 0.4) 1687 return false; 1688 1689 DOUT << "Lowering jump table\n" 1690 << "First entry: " << First << ". Last entry: " << Last << "\n" 1691 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1692 1693 // Get the MachineFunction which holds the current MBB. This is used when 1694 // inserting any additional MBBs necessary to represent the switch. 1695 MachineFunction *CurMF = CurMBB->getParent(); 1696 1697 // Figure out which block is immediately after the current one. 1698 MachineBasicBlock *NextBlock = 0; 1699 MachineFunction::iterator BBI = CR.CaseBB; 1700 1701 if (++BBI != CurMBB->getParent()->end()) 1702 NextBlock = BBI; 1703 1704 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1705 1706 // Create a new basic block to hold the code for loading the address 1707 // of the jump table, and jumping to it. Update successor information; 1708 // we will either branch to the default case for the switch, or the jump 1709 // table. 1710 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1711 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1712 CR.CaseBB->addSuccessor(Default); 1713 CR.CaseBB->addSuccessor(JumpTableBB); 1714 1715 // Build a vector of destination BBs, corresponding to each target 1716 // of the jump table. If the value of the jump table slot corresponds to 1717 // a case statement, push the case's BB onto the vector, otherwise, push 1718 // the default BB. 1719 std::vector<MachineBasicBlock*> DestBBs; 1720 int64_t TEI = First; 1721 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1722 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1723 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1724 1725 if ((Low <= TEI) && (TEI <= High)) { 1726 DestBBs.push_back(I->BB); 1727 if (TEI==High) 1728 ++I; 1729 } else { 1730 DestBBs.push_back(Default); 1731 } 1732 } 1733 1734 // Update successor info. Add one edge to each unique successor. 1735 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1736 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1737 E = DestBBs.end(); I != E; ++I) { 1738 if (!SuccsHandled[(*I)->getNumber()]) { 1739 SuccsHandled[(*I)->getNumber()] = true; 1740 JumpTableBB->addSuccessor(*I); 1741 } 1742 } 1743 1744 // Create a jump table index for this jump table, or return an existing 1745 // one. 1746 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1747 1748 // Set the jump table information so that we can codegen it as a second 1749 // MachineBasicBlock 1750 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1751 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1752 (CR.CaseBB == CurMBB)); 1753 if (CR.CaseBB == CurMBB) 1754 visitJumpTableHeader(JT, JTH); 1755 1756 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1757 1758 return true; 1759} 1760 1761/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1762/// 2 subtrees. 1763bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1764 CaseRecVector& WorkList, 1765 Value* SV, 1766 MachineBasicBlock* Default) { 1767 // Get the MachineFunction which holds the current MBB. This is used when 1768 // inserting any additional MBBs necessary to represent the switch. 1769 MachineFunction *CurMF = CurMBB->getParent(); 1770 1771 // Figure out which block is immediately after the current one. 1772 MachineBasicBlock *NextBlock = 0; 1773 MachineFunction::iterator BBI = CR.CaseBB; 1774 1775 if (++BBI != CurMBB->getParent()->end()) 1776 NextBlock = BBI; 1777 1778 Case& FrontCase = *CR.Range.first; 1779 Case& BackCase = *(CR.Range.second-1); 1780 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1781 1782 // Size is the number of Cases represented by this range. 1783 unsigned Size = CR.Range.second - CR.Range.first; 1784 1785 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1786 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1787 double FMetric = 0; 1788 CaseItr Pivot = CR.Range.first + Size/2; 1789 1790 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1791 // (heuristically) allow us to emit JumpTable's later. 1792 uint64_t TSize = 0; 1793 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1794 I!=E; ++I) 1795 TSize += I->size(); 1796 1797 uint64_t LSize = FrontCase.size(); 1798 uint64_t RSize = TSize-LSize; 1799 DOUT << "Selecting best pivot: \n" 1800 << "First: " << First << ", Last: " << Last <<"\n" 1801 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1802 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1803 J!=E; ++I, ++J) { 1804 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1805 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1806 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1807 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1808 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1809 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1810 // Should always split in some non-trivial place 1811 DOUT <<"=>Step\n" 1812 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1813 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1814 << "Metric: " << Metric << "\n"; 1815 if (FMetric < Metric) { 1816 Pivot = J; 1817 FMetric = Metric; 1818 DOUT << "Current metric set to: " << FMetric << "\n"; 1819 } 1820 1821 LSize += J->size(); 1822 RSize -= J->size(); 1823 } 1824 if (areJTsAllowed(TLI)) { 1825 // If our case is dense we *really* should handle it earlier! 1826 assert((FMetric > 0) && "Should handle dense range earlier!"); 1827 } else { 1828 Pivot = CR.Range.first + Size/2; 1829 } 1830 1831 CaseRange LHSR(CR.Range.first, Pivot); 1832 CaseRange RHSR(Pivot, CR.Range.second); 1833 Constant *C = Pivot->Low; 1834 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1835 1836 // We know that we branch to the LHS if the Value being switched on is 1837 // less than the Pivot value, C. We use this to optimize our binary 1838 // tree a bit, by recognizing that if SV is greater than or equal to the 1839 // LHS's Case Value, and that Case Value is exactly one less than the 1840 // Pivot's Value, then we can branch directly to the LHS's Target, 1841 // rather than creating a leaf node for it. 1842 if ((LHSR.second - LHSR.first) == 1 && 1843 LHSR.first->High == CR.GE && 1844 cast<ConstantInt>(C)->getSExtValue() == 1845 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1846 TrueBB = LHSR.first->BB; 1847 } else { 1848 TrueBB = new MachineBasicBlock(LLVMBB); 1849 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1850 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1851 } 1852 1853 // Similar to the optimization above, if the Value being switched on is 1854 // known to be less than the Constant CR.LT, and the current Case Value 1855 // is CR.LT - 1, then we can branch directly to the target block for 1856 // the current Case Value, rather than emitting a RHS leaf node for it. 1857 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1858 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1859 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1860 FalseBB = RHSR.first->BB; 1861 } else { 1862 FalseBB = new MachineBasicBlock(LLVMBB); 1863 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1864 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1865 } 1866 1867 // Create a CaseBlock record representing a conditional branch to 1868 // the LHS node if the value being switched on SV is less than C. 1869 // Otherwise, branch to LHS. 1870 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1871 TrueBB, FalseBB, CR.CaseBB); 1872 1873 if (CR.CaseBB == CurMBB) 1874 visitSwitchCase(CB); 1875 else 1876 SwitchCases.push_back(CB); 1877 1878 return true; 1879} 1880 1881/// handleBitTestsSwitchCase - if current case range has few destination and 1882/// range span less, than machine word bitwidth, encode case range into series 1883/// of masks and emit bit tests with these masks. 1884bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1885 CaseRecVector& WorkList, 1886 Value* SV, 1887 MachineBasicBlock* Default){ 1888 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); 1889 1890 Case& FrontCase = *CR.Range.first; 1891 Case& BackCase = *(CR.Range.second-1); 1892 1893 // Get the MachineFunction which holds the current MBB. This is used when 1894 // inserting any additional MBBs necessary to represent the switch. 1895 MachineFunction *CurMF = CurMBB->getParent(); 1896 1897 unsigned numCmps = 0; 1898 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1899 I!=E; ++I) { 1900 // Single case counts one, case range - two. 1901 if (I->Low == I->High) 1902 numCmps +=1; 1903 else 1904 numCmps +=2; 1905 } 1906 1907 // Count unique destinations 1908 SmallSet<MachineBasicBlock*, 4> Dests; 1909 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1910 Dests.insert(I->BB); 1911 if (Dests.size() > 3) 1912 // Don't bother the code below, if there are too much unique destinations 1913 return false; 1914 } 1915 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1916 << "Total number of comparisons: " << numCmps << "\n"; 1917 1918 // Compute span of values. 1919 Constant* minValue = FrontCase.Low; 1920 Constant* maxValue = BackCase.High; 1921 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1922 cast<ConstantInt>(minValue)->getSExtValue(); 1923 DOUT << "Compare range: " << range << "\n" 1924 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1925 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1926 1927 if (range>=IntPtrBits || 1928 (!(Dests.size() == 1 && numCmps >= 3) && 1929 !(Dests.size() == 2 && numCmps >= 5) && 1930 !(Dests.size() >= 3 && numCmps >= 6))) 1931 return false; 1932 1933 DOUT << "Emitting bit tests\n"; 1934 int64_t lowBound = 0; 1935 1936 // Optimize the case where all the case values fit in a 1937 // word without having to subtract minValue. In this case, 1938 // we can optimize away the subtraction. 1939 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1940 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1941 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1942 } else { 1943 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1944 } 1945 1946 CaseBitsVector CasesBits; 1947 unsigned i, count = 0; 1948 1949 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1950 MachineBasicBlock* Dest = I->BB; 1951 for (i = 0; i < count; ++i) 1952 if (Dest == CasesBits[i].BB) 1953 break; 1954 1955 if (i == count) { 1956 assert((count < 3) && "Too much destinations to test!"); 1957 CasesBits.push_back(CaseBits(0, Dest, 0)); 1958 count++; 1959 } 1960 1961 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1962 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1963 1964 for (uint64_t j = lo; j <= hi; j++) { 1965 CasesBits[i].Mask |= 1ULL << j; 1966 CasesBits[i].Bits++; 1967 } 1968 1969 } 1970 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1971 1972 SelectionDAGISel::BitTestInfo BTC; 1973 1974 // Figure out which block is immediately after the current one. 1975 MachineFunction::iterator BBI = CR.CaseBB; 1976 ++BBI; 1977 1978 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1979 1980 DOUT << "Cases:\n"; 1981 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1982 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1983 << ", BB: " << CasesBits[i].BB << "\n"; 1984 1985 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1986 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1987 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1988 CaseBB, 1989 CasesBits[i].BB)); 1990 } 1991 1992 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 1993 -1U, (CR.CaseBB == CurMBB), 1994 CR.CaseBB, Default, BTC); 1995 1996 if (CR.CaseBB == CurMBB) 1997 visitBitTestHeader(BTB); 1998 1999 BitTestCases.push_back(BTB); 2000 2001 return true; 2002} 2003 2004 2005// Clusterify - Transform simple list of Cases into list of CaseRange's 2006unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 2007 const SwitchInst& SI) { 2008 unsigned numCmps = 0; 2009 2010 // Start with "simple" cases 2011 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 2012 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2013 Cases.push_back(Case(SI.getSuccessorValue(i), 2014 SI.getSuccessorValue(i), 2015 SMBB)); 2016 } 2017 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2018 2019 // Merge case into clusters 2020 if (Cases.size()>=2) 2021 // Must recompute end() each iteration because it may be 2022 // invalidated by erase if we hold on to it 2023 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 2024 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 2025 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 2026 MachineBasicBlock* nextBB = J->BB; 2027 MachineBasicBlock* currentBB = I->BB; 2028 2029 // If the two neighboring cases go to the same destination, merge them 2030 // into a single case. 2031 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 2032 I->High = J->High; 2033 J = Cases.erase(J); 2034 } else { 2035 I = J++; 2036 } 2037 } 2038 2039 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2040 if (I->Low != I->High) 2041 // A range counts double, since it requires two compares. 2042 ++numCmps; 2043 } 2044 2045 return numCmps; 2046} 2047 2048void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 2049 // Figure out which block is immediately after the current one. 2050 MachineBasicBlock *NextBlock = 0; 2051 MachineFunction::iterator BBI = CurMBB; 2052 2053 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2054 2055 // If there is only the default destination, branch to it if it is not the 2056 // next basic block. Otherwise, just fall through. 2057 if (SI.getNumOperands() == 2) { 2058 // Update machine-CFG edges. 2059 2060 // If this is not a fall-through branch, emit the branch. 2061 if (Default != NextBlock) 2062 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 2063 DAG.getBasicBlock(Default))); 2064 2065 CurMBB->addSuccessor(Default); 2066 return; 2067 } 2068 2069 // If there are any non-default case statements, create a vector of Cases 2070 // representing each one, and sort the vector so that we can efficiently 2071 // create a binary search tree from them. 2072 CaseVector Cases; 2073 unsigned numCmps = Clusterify(Cases, SI); 2074 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 2075 << ". Total compares: " << numCmps << "\n"; 2076 2077 // Get the Value to be switched on and default basic blocks, which will be 2078 // inserted into CaseBlock records, representing basic blocks in the binary 2079 // search tree. 2080 Value *SV = SI.getOperand(0); 2081 2082 // Push the initial CaseRec onto the worklist 2083 CaseRecVector WorkList; 2084 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 2085 2086 while (!WorkList.empty()) { 2087 // Grab a record representing a case range to process off the worklist 2088 CaseRec CR = WorkList.back(); 2089 WorkList.pop_back(); 2090 2091 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 2092 continue; 2093 2094 // If the range has few cases (two or less) emit a series of specific 2095 // tests. 2096 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 2097 continue; 2098 2099 // If the switch has more than 5 blocks, and at least 40% dense, and the 2100 // target supports indirect branches, then emit a jump table rather than 2101 // lowering the switch to a binary tree of conditional branches. 2102 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 2103 continue; 2104 2105 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2106 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2107 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 2108 } 2109} 2110 2111 2112void SelectionDAGLowering::visitSub(User &I) { 2113 // -0.0 - X --> fneg 2114 const Type *Ty = I.getType(); 2115 if (isa<VectorType>(Ty)) { 2116 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2117 const VectorType *DestTy = cast<VectorType>(I.getType()); 2118 const Type *ElTy = DestTy->getElementType(); 2119 if (ElTy->isFloatingPoint()) { 2120 unsigned VL = DestTy->getNumElements(); 2121 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2122 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2123 if (CV == CNZ) { 2124 SDOperand Op2 = getValue(I.getOperand(1)); 2125 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2126 return; 2127 } 2128 } 2129 } 2130 } 2131 if (Ty->isFloatingPoint()) { 2132 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2133 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2134 SDOperand Op2 = getValue(I.getOperand(1)); 2135 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2136 return; 2137 } 2138 } 2139 2140 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2141} 2142 2143void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2144 SDOperand Op1 = getValue(I.getOperand(0)); 2145 SDOperand Op2 = getValue(I.getOperand(1)); 2146 2147 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2148} 2149 2150void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2151 SDOperand Op1 = getValue(I.getOperand(0)); 2152 SDOperand Op2 = getValue(I.getOperand(1)); 2153 2154 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) < 2155 MVT::getSizeInBits(Op2.getValueType())) 2156 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2157 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 2158 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2159 2160 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2161} 2162 2163void SelectionDAGLowering::visitICmp(User &I) { 2164 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2165 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2166 predicate = IC->getPredicate(); 2167 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2168 predicate = ICmpInst::Predicate(IC->getPredicate()); 2169 SDOperand Op1 = getValue(I.getOperand(0)); 2170 SDOperand Op2 = getValue(I.getOperand(1)); 2171 ISD::CondCode Opcode; 2172 switch (predicate) { 2173 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2174 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2175 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2176 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2177 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2178 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2179 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2180 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2181 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2182 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2183 default: 2184 assert(!"Invalid ICmp predicate value"); 2185 Opcode = ISD::SETEQ; 2186 break; 2187 } 2188 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2189} 2190 2191void SelectionDAGLowering::visitFCmp(User &I) { 2192 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2193 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2194 predicate = FC->getPredicate(); 2195 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2196 predicate = FCmpInst::Predicate(FC->getPredicate()); 2197 SDOperand Op1 = getValue(I.getOperand(0)); 2198 SDOperand Op2 = getValue(I.getOperand(1)); 2199 ISD::CondCode Condition, FOC, FPC; 2200 switch (predicate) { 2201 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2202 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2203 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2204 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2205 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2206 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2207 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2208 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 2209 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 2210 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2211 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2212 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2213 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2214 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2215 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2216 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2217 default: 2218 assert(!"Invalid FCmp predicate value"); 2219 FOC = FPC = ISD::SETFALSE; 2220 break; 2221 } 2222 if (FiniteOnlyFPMath()) 2223 Condition = FOC; 2224 else 2225 Condition = FPC; 2226 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2227} 2228 2229void SelectionDAGLowering::visitSelect(User &I) { 2230 SDOperand Cond = getValue(I.getOperand(0)); 2231 SDOperand TrueVal = getValue(I.getOperand(1)); 2232 SDOperand FalseVal = getValue(I.getOperand(2)); 2233 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2234 TrueVal, FalseVal)); 2235} 2236 2237 2238void SelectionDAGLowering::visitTrunc(User &I) { 2239 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2240 SDOperand N = getValue(I.getOperand(0)); 2241 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2242 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2243} 2244 2245void SelectionDAGLowering::visitZExt(User &I) { 2246 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2247 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2248 SDOperand N = getValue(I.getOperand(0)); 2249 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2250 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2251} 2252 2253void SelectionDAGLowering::visitSExt(User &I) { 2254 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2255 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2256 SDOperand N = getValue(I.getOperand(0)); 2257 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2258 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2259} 2260 2261void SelectionDAGLowering::visitFPTrunc(User &I) { 2262 // FPTrunc is never a no-op cast, no need to check 2263 SDOperand N = getValue(I.getOperand(0)); 2264 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2265 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0))); 2266} 2267 2268void SelectionDAGLowering::visitFPExt(User &I){ 2269 // FPTrunc is never a no-op cast, no need to check 2270 SDOperand N = getValue(I.getOperand(0)); 2271 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2272 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2273} 2274 2275void SelectionDAGLowering::visitFPToUI(User &I) { 2276 // FPToUI is never a no-op cast, no need to check 2277 SDOperand N = getValue(I.getOperand(0)); 2278 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2279 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2280} 2281 2282void SelectionDAGLowering::visitFPToSI(User &I) { 2283 // FPToSI is never a no-op cast, no need to check 2284 SDOperand N = getValue(I.getOperand(0)); 2285 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2286 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2287} 2288 2289void SelectionDAGLowering::visitUIToFP(User &I) { 2290 // UIToFP is never a no-op cast, no need to check 2291 SDOperand N = getValue(I.getOperand(0)); 2292 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2293 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2294} 2295 2296void SelectionDAGLowering::visitSIToFP(User &I){ 2297 // UIToFP is never a no-op cast, no need to check 2298 SDOperand N = getValue(I.getOperand(0)); 2299 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2300 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2301} 2302 2303void SelectionDAGLowering::visitPtrToInt(User &I) { 2304 // What to do depends on the size of the integer and the size of the pointer. 2305 // We can either truncate, zero extend, or no-op, accordingly. 2306 SDOperand N = getValue(I.getOperand(0)); 2307 MVT::ValueType SrcVT = N.getValueType(); 2308 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2309 SDOperand Result; 2310 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2311 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2312 else 2313 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2314 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2315 setValue(&I, Result); 2316} 2317 2318void SelectionDAGLowering::visitIntToPtr(User &I) { 2319 // What to do depends on the size of the integer and the size of the pointer. 2320 // We can either truncate, zero extend, or no-op, accordingly. 2321 SDOperand N = getValue(I.getOperand(0)); 2322 MVT::ValueType SrcVT = N.getValueType(); 2323 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2324 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2325 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2326 else 2327 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2328 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2329} 2330 2331void SelectionDAGLowering::visitBitCast(User &I) { 2332 SDOperand N = getValue(I.getOperand(0)); 2333 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2334 2335 // BitCast assures us that source and destination are the same size so this 2336 // is either a BIT_CONVERT or a no-op. 2337 if (DestVT != N.getValueType()) 2338 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2339 else 2340 setValue(&I, N); // noop cast. 2341} 2342 2343void SelectionDAGLowering::visitInsertElement(User &I) { 2344 SDOperand InVec = getValue(I.getOperand(0)); 2345 SDOperand InVal = getValue(I.getOperand(1)); 2346 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2347 getValue(I.getOperand(2))); 2348 2349 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2350 TLI.getValueType(I.getType()), 2351 InVec, InVal, InIdx)); 2352} 2353 2354void SelectionDAGLowering::visitExtractElement(User &I) { 2355 SDOperand InVec = getValue(I.getOperand(0)); 2356 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2357 getValue(I.getOperand(1))); 2358 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2359 TLI.getValueType(I.getType()), InVec, InIdx)); 2360} 2361 2362void SelectionDAGLowering::visitShuffleVector(User &I) { 2363 SDOperand V1 = getValue(I.getOperand(0)); 2364 SDOperand V2 = getValue(I.getOperand(1)); 2365 SDOperand Mask = getValue(I.getOperand(2)); 2366 2367 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2368 TLI.getValueType(I.getType()), 2369 V1, V2, Mask)); 2370} 2371 2372 2373void SelectionDAGLowering::visitGetElementPtr(User &I) { 2374 SDOperand N = getValue(I.getOperand(0)); 2375 const Type *Ty = I.getOperand(0)->getType(); 2376 2377 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2378 OI != E; ++OI) { 2379 Value *Idx = *OI; 2380 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2381 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2382 if (Field) { 2383 // N = N + Offset 2384 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2385 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2386 DAG.getIntPtrConstant(Offset)); 2387 } 2388 Ty = StTy->getElementType(Field); 2389 } else { 2390 Ty = cast<SequentialType>(Ty)->getElementType(); 2391 2392 // If this is a constant subscript, handle it quickly. 2393 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2394 if (CI->getZExtValue() == 0) continue; 2395 uint64_t Offs = 2396 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2397 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2398 DAG.getIntPtrConstant(Offs)); 2399 continue; 2400 } 2401 2402 // N = N + Idx * ElementSize; 2403 uint64_t ElementSize = TD->getABITypeSize(Ty); 2404 SDOperand IdxN = getValue(Idx); 2405 2406 // If the index is smaller or larger than intptr_t, truncate or extend 2407 // it. 2408 if (IdxN.getValueType() < N.getValueType()) { 2409 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2410 } else if (IdxN.getValueType() > N.getValueType()) 2411 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2412 2413 // If this is a multiply by a power of two, turn it into a shl 2414 // immediately. This is a very common case. 2415 if (isPowerOf2_64(ElementSize)) { 2416 unsigned Amt = Log2_64(ElementSize); 2417 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2418 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2419 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2420 continue; 2421 } 2422 2423 SDOperand Scale = DAG.getIntPtrConstant(ElementSize); 2424 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2425 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2426 } 2427 } 2428 setValue(&I, N); 2429} 2430 2431void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2432 // If this is a fixed sized alloca in the entry block of the function, 2433 // allocate it statically on the stack. 2434 if (FuncInfo.StaticAllocaMap.count(&I)) 2435 return; // getValue will auto-populate this. 2436 2437 const Type *Ty = I.getAllocatedType(); 2438 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 2439 unsigned Align = 2440 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2441 I.getAlignment()); 2442 2443 SDOperand AllocSize = getValue(I.getArraySize()); 2444 MVT::ValueType IntPtr = TLI.getPointerTy(); 2445 if (IntPtr < AllocSize.getValueType()) 2446 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2447 else if (IntPtr > AllocSize.getValueType()) 2448 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2449 2450 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2451 DAG.getIntPtrConstant(TySize)); 2452 2453 // Handle alignment. If the requested alignment is less than or equal to 2454 // the stack alignment, ignore it. If the size is greater than or equal to 2455 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2456 unsigned StackAlign = 2457 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2458 if (Align <= StackAlign) 2459 Align = 0; 2460 2461 // Round the size of the allocation up to the stack alignment size 2462 // by add SA-1 to the size. 2463 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2464 DAG.getIntPtrConstant(StackAlign-1)); 2465 // Mask out the low bits for alignment purposes. 2466 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2467 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2468 2469 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2470 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2471 MVT::Other); 2472 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2473 setValue(&I, DSA); 2474 DAG.setRoot(DSA.getValue(1)); 2475 2476 // Inform the Frame Information that we have just allocated a variable-sized 2477 // object. 2478 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2479} 2480 2481void SelectionDAGLowering::visitLoad(LoadInst &I) { 2482 SDOperand Ptr = getValue(I.getOperand(0)); 2483 2484 SDOperand Root; 2485 if (I.isVolatile()) 2486 Root = getRoot(); 2487 else { 2488 // Do not serialize non-volatile loads against each other. 2489 Root = DAG.getRoot(); 2490 } 2491 2492 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2493 Root, I.isVolatile(), I.getAlignment())); 2494} 2495 2496SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2497 const Value *SV, SDOperand Root, 2498 bool isVolatile, 2499 unsigned Alignment) { 2500 SDOperand L = 2501 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2502 isVolatile, Alignment); 2503 2504 if (isVolatile) 2505 DAG.setRoot(L.getValue(1)); 2506 else 2507 PendingLoads.push_back(L.getValue(1)); 2508 2509 return L; 2510} 2511 2512 2513void SelectionDAGLowering::visitStore(StoreInst &I) { 2514 Value *SrcV = I.getOperand(0); 2515 SDOperand Src = getValue(SrcV); 2516 SDOperand Ptr = getValue(I.getOperand(1)); 2517 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2518 I.isVolatile(), I.getAlignment())); 2519} 2520 2521/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2522/// node. 2523void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2524 unsigned Intrinsic) { 2525 bool HasChain = !I.doesNotAccessMemory(); 2526 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 2527 2528 // Build the operand list. 2529 SmallVector<SDOperand, 8> Ops; 2530 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2531 if (OnlyLoad) { 2532 // We don't need to serialize loads against other loads. 2533 Ops.push_back(DAG.getRoot()); 2534 } else { 2535 Ops.push_back(getRoot()); 2536 } 2537 } 2538 2539 // Add the intrinsic ID as an integer operand. 2540 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2541 2542 // Add all operands of the call to the operand list. 2543 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2544 SDOperand Op = getValue(I.getOperand(i)); 2545 assert(TLI.isTypeLegal(Op.getValueType()) && 2546 "Intrinsic uses a non-legal type?"); 2547 Ops.push_back(Op); 2548 } 2549 2550 std::vector<MVT::ValueType> VTs; 2551 if (I.getType() != Type::VoidTy) { 2552 MVT::ValueType VT = TLI.getValueType(I.getType()); 2553 if (MVT::isVector(VT)) { 2554 const VectorType *DestTy = cast<VectorType>(I.getType()); 2555 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2556 2557 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2558 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2559 } 2560 2561 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2562 VTs.push_back(VT); 2563 } 2564 if (HasChain) 2565 VTs.push_back(MVT::Other); 2566 2567 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2568 2569 // Create the node. 2570 SDOperand Result; 2571 if (!HasChain) 2572 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2573 &Ops[0], Ops.size()); 2574 else if (I.getType() != Type::VoidTy) 2575 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2576 &Ops[0], Ops.size()); 2577 else 2578 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2579 &Ops[0], Ops.size()); 2580 2581 if (HasChain) { 2582 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2583 if (OnlyLoad) 2584 PendingLoads.push_back(Chain); 2585 else 2586 DAG.setRoot(Chain); 2587 } 2588 if (I.getType() != Type::VoidTy) { 2589 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2590 MVT::ValueType VT = TLI.getValueType(PTy); 2591 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 2592 } 2593 setValue(&I, Result); 2594 } 2595} 2596 2597/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 2598static GlobalVariable *ExtractTypeInfo (Value *V) { 2599 V = IntrinsicInst::StripPointerCasts(V); 2600 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 2601 assert (GV || isa<ConstantPointerNull>(V) && 2602 "TypeInfo must be a global variable or NULL"); 2603 return GV; 2604} 2605 2606/// addCatchInfo - Extract the personality and type infos from an eh.selector 2607/// call, and add them to the specified machine basic block. 2608static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 2609 MachineBasicBlock *MBB) { 2610 // Inform the MachineModuleInfo of the personality for this landing pad. 2611 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 2612 assert(CE->getOpcode() == Instruction::BitCast && 2613 isa<Function>(CE->getOperand(0)) && 2614 "Personality should be a function"); 2615 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 2616 2617 // Gather all the type infos for this landing pad and pass them along to 2618 // MachineModuleInfo. 2619 std::vector<GlobalVariable *> TyInfo; 2620 unsigned N = I.getNumOperands(); 2621 2622 for (unsigned i = N - 1; i > 2; --i) { 2623 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 2624 unsigned FilterLength = CI->getZExtValue(); 2625 unsigned FirstCatch = i + FilterLength + !FilterLength; 2626 assert (FirstCatch <= N && "Invalid filter length"); 2627 2628 if (FirstCatch < N) { 2629 TyInfo.reserve(N - FirstCatch); 2630 for (unsigned j = FirstCatch; j < N; ++j) 2631 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2632 MMI->addCatchTypeInfo(MBB, TyInfo); 2633 TyInfo.clear(); 2634 } 2635 2636 if (!FilterLength) { 2637 // Cleanup. 2638 MMI->addCleanup(MBB); 2639 } else { 2640 // Filter. 2641 TyInfo.reserve(FilterLength - 1); 2642 for (unsigned j = i + 1; j < FirstCatch; ++j) 2643 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2644 MMI->addFilterTypeInfo(MBB, TyInfo); 2645 TyInfo.clear(); 2646 } 2647 2648 N = i; 2649 } 2650 } 2651 2652 if (N > 3) { 2653 TyInfo.reserve(N - 3); 2654 for (unsigned j = 3; j < N; ++j) 2655 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2656 MMI->addCatchTypeInfo(MBB, TyInfo); 2657 } 2658} 2659 2660/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2661/// we want to emit this as a call to a named external function, return the name 2662/// otherwise lower it and return null. 2663const char * 2664SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2665 switch (Intrinsic) { 2666 default: 2667 // By default, turn this into a target intrinsic node. 2668 visitTargetIntrinsic(I, Intrinsic); 2669 return 0; 2670 case Intrinsic::vastart: visitVAStart(I); return 0; 2671 case Intrinsic::vaend: visitVAEnd(I); return 0; 2672 case Intrinsic::vacopy: visitVACopy(I); return 0; 2673 case Intrinsic::returnaddress: 2674 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2675 getValue(I.getOperand(1)))); 2676 return 0; 2677 case Intrinsic::frameaddress: 2678 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2679 getValue(I.getOperand(1)))); 2680 return 0; 2681 case Intrinsic::setjmp: 2682 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2683 break; 2684 case Intrinsic::longjmp: 2685 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2686 break; 2687 case Intrinsic::memcpy_i32: 2688 case Intrinsic::memcpy_i64: 2689 visitMemIntrinsic(I, ISD::MEMCPY); 2690 return 0; 2691 case Intrinsic::memset_i32: 2692 case Intrinsic::memset_i64: 2693 visitMemIntrinsic(I, ISD::MEMSET); 2694 return 0; 2695 case Intrinsic::memmove_i32: 2696 case Intrinsic::memmove_i64: 2697 visitMemIntrinsic(I, ISD::MEMMOVE); 2698 return 0; 2699 2700 case Intrinsic::dbg_stoppoint: { 2701 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2702 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2703 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2704 SDOperand Ops[5]; 2705 2706 Ops[0] = getRoot(); 2707 Ops[1] = getValue(SPI.getLineValue()); 2708 Ops[2] = getValue(SPI.getColumnValue()); 2709 2710 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2711 assert(DD && "Not a debug information descriptor"); 2712 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2713 2714 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2715 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2716 2717 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2718 } 2719 2720 return 0; 2721 } 2722 case Intrinsic::dbg_region_start: { 2723 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2724 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2725 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2726 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2727 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2728 DAG.getConstant(LabelID, MVT::i32), 2729 DAG.getConstant(0, MVT::i32))); 2730 } 2731 2732 return 0; 2733 } 2734 case Intrinsic::dbg_region_end: { 2735 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2736 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2737 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2738 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2739 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2740 DAG.getConstant(LabelID, MVT::i32), 2741 DAG.getConstant(0, MVT::i32))); 2742 } 2743 2744 return 0; 2745 } 2746 case Intrinsic::dbg_func_start: { 2747 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2748 if (!MMI) return 0; 2749 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2750 Value *SP = FSI.getSubprogram(); 2751 if (SP && MMI->Verify(SP)) { 2752 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is 2753 // what (most?) gdb expects. 2754 DebugInfoDesc *DD = MMI->getDescFor(SP); 2755 assert(DD && "Not a debug information descriptor"); 2756 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD); 2757 const CompileUnitDesc *CompileUnit = Subprogram->getFile(); 2758 unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(), 2759 CompileUnit->getFileName()); 2760 // Record the source line but does create a label. It will be emitted 2761 // at asm emission time. 2762 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile); 2763 } 2764 2765 return 0; 2766 } 2767 case Intrinsic::dbg_declare: { 2768 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2769 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2770 Value *Variable = DI.getVariable(); 2771 if (MMI && Variable && MMI->Verify(Variable)) 2772 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(), 2773 getValue(DI.getAddress()), getValue(Variable))); 2774 return 0; 2775 } 2776 2777 case Intrinsic::eh_exception: { 2778 if (ExceptionHandling) { 2779 if (!CurMBB->isLandingPad()) { 2780 // FIXME: Mark exception register as live in. Hack for PR1508. 2781 unsigned Reg = TLI.getExceptionAddressRegister(); 2782 if (Reg) CurMBB->addLiveIn(Reg); 2783 } 2784 // Insert the EXCEPTIONADDR instruction. 2785 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2786 SDOperand Ops[1]; 2787 Ops[0] = DAG.getRoot(); 2788 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2789 setValue(&I, Op); 2790 DAG.setRoot(Op.getValue(1)); 2791 } else { 2792 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2793 } 2794 return 0; 2795 } 2796 2797 case Intrinsic::eh_selector_i32: 2798 case Intrinsic::eh_selector_i64: { 2799 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2800 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ? 2801 MVT::i32 : MVT::i64); 2802 2803 if (ExceptionHandling && MMI) { 2804 if (CurMBB->isLandingPad()) 2805 addCatchInfo(I, MMI, CurMBB); 2806 else { 2807#ifndef NDEBUG 2808 FuncInfo.CatchInfoLost.insert(&I); 2809#endif 2810 // FIXME: Mark exception selector register as live in. Hack for PR1508. 2811 unsigned Reg = TLI.getExceptionSelectorRegister(); 2812 if (Reg) CurMBB->addLiveIn(Reg); 2813 } 2814 2815 // Insert the EHSELECTION instruction. 2816 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 2817 SDOperand Ops[2]; 2818 Ops[0] = getValue(I.getOperand(1)); 2819 Ops[1] = getRoot(); 2820 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2821 setValue(&I, Op); 2822 DAG.setRoot(Op.getValue(1)); 2823 } else { 2824 setValue(&I, DAG.getConstant(0, VT)); 2825 } 2826 2827 return 0; 2828 } 2829 2830 case Intrinsic::eh_typeid_for_i32: 2831 case Intrinsic::eh_typeid_for_i64: { 2832 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2833 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? 2834 MVT::i32 : MVT::i64); 2835 2836 if (MMI) { 2837 // Find the type id for the given typeinfo. 2838 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 2839 2840 unsigned TypeID = MMI->getTypeIDFor(GV); 2841 setValue(&I, DAG.getConstant(TypeID, VT)); 2842 } else { 2843 // Return something different to eh_selector. 2844 setValue(&I, DAG.getConstant(1, VT)); 2845 } 2846 2847 return 0; 2848 } 2849 2850 case Intrinsic::eh_return: { 2851 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2852 2853 if (MMI && ExceptionHandling) { 2854 MMI->setCallsEHReturn(true); 2855 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, 2856 MVT::Other, 2857 getRoot(), 2858 getValue(I.getOperand(1)), 2859 getValue(I.getOperand(2)))); 2860 } else { 2861 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2862 } 2863 2864 return 0; 2865 } 2866 2867 case Intrinsic::eh_unwind_init: { 2868 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 2869 MMI->setCallsUnwindInit(true); 2870 } 2871 2872 return 0; 2873 } 2874 2875 case Intrinsic::eh_dwarf_cfa: { 2876 if (ExceptionHandling) { 2877 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType(); 2878 SDOperand CfaArg; 2879 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 2880 CfaArg = DAG.getNode(ISD::TRUNCATE, 2881 TLI.getPointerTy(), getValue(I.getOperand(1))); 2882 else 2883 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, 2884 TLI.getPointerTy(), getValue(I.getOperand(1))); 2885 2886 SDOperand Offset = DAG.getNode(ISD::ADD, 2887 TLI.getPointerTy(), 2888 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, 2889 TLI.getPointerTy()), 2890 CfaArg); 2891 setValue(&I, DAG.getNode(ISD::ADD, 2892 TLI.getPointerTy(), 2893 DAG.getNode(ISD::FRAMEADDR, 2894 TLI.getPointerTy(), 2895 DAG.getConstant(0, 2896 TLI.getPointerTy())), 2897 Offset)); 2898 } else { 2899 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2900 } 2901 2902 return 0; 2903 } 2904 2905 case Intrinsic::sqrt: 2906 setValue(&I, DAG.getNode(ISD::FSQRT, 2907 getValue(I.getOperand(1)).getValueType(), 2908 getValue(I.getOperand(1)))); 2909 return 0; 2910 case Intrinsic::powi: 2911 setValue(&I, DAG.getNode(ISD::FPOWI, 2912 getValue(I.getOperand(1)).getValueType(), 2913 getValue(I.getOperand(1)), 2914 getValue(I.getOperand(2)))); 2915 return 0; 2916 case Intrinsic::sin: 2917 setValue(&I, DAG.getNode(ISD::FSIN, 2918 getValue(I.getOperand(1)).getValueType(), 2919 getValue(I.getOperand(1)))); 2920 return 0; 2921 case Intrinsic::cos: 2922 setValue(&I, DAG.getNode(ISD::FCOS, 2923 getValue(I.getOperand(1)).getValueType(), 2924 getValue(I.getOperand(1)))); 2925 return 0; 2926 case Intrinsic::pow: 2927 setValue(&I, DAG.getNode(ISD::FPOW, 2928 getValue(I.getOperand(1)).getValueType(), 2929 getValue(I.getOperand(1)), 2930 getValue(I.getOperand(2)))); 2931 return 0; 2932 case Intrinsic::pcmarker: { 2933 SDOperand Tmp = getValue(I.getOperand(1)); 2934 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2935 return 0; 2936 } 2937 case Intrinsic::readcyclecounter: { 2938 SDOperand Op = getRoot(); 2939 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2940 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2941 &Op, 1); 2942 setValue(&I, Tmp); 2943 DAG.setRoot(Tmp.getValue(1)); 2944 return 0; 2945 } 2946 case Intrinsic::part_select: { 2947 // Currently not implemented: just abort 2948 assert(0 && "part_select intrinsic not implemented"); 2949 abort(); 2950 } 2951 case Intrinsic::part_set: { 2952 // Currently not implemented: just abort 2953 assert(0 && "part_set intrinsic not implemented"); 2954 abort(); 2955 } 2956 case Intrinsic::bswap: 2957 setValue(&I, DAG.getNode(ISD::BSWAP, 2958 getValue(I.getOperand(1)).getValueType(), 2959 getValue(I.getOperand(1)))); 2960 return 0; 2961 case Intrinsic::cttz: { 2962 SDOperand Arg = getValue(I.getOperand(1)); 2963 MVT::ValueType Ty = Arg.getValueType(); 2964 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2965 setValue(&I, result); 2966 return 0; 2967 } 2968 case Intrinsic::ctlz: { 2969 SDOperand Arg = getValue(I.getOperand(1)); 2970 MVT::ValueType Ty = Arg.getValueType(); 2971 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2972 setValue(&I, result); 2973 return 0; 2974 } 2975 case Intrinsic::ctpop: { 2976 SDOperand Arg = getValue(I.getOperand(1)); 2977 MVT::ValueType Ty = Arg.getValueType(); 2978 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2979 setValue(&I, result); 2980 return 0; 2981 } 2982 case Intrinsic::stacksave: { 2983 SDOperand Op = getRoot(); 2984 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2985 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2986 setValue(&I, Tmp); 2987 DAG.setRoot(Tmp.getValue(1)); 2988 return 0; 2989 } 2990 case Intrinsic::stackrestore: { 2991 SDOperand Tmp = getValue(I.getOperand(1)); 2992 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2993 return 0; 2994 } 2995 case Intrinsic::prefetch: 2996 // FIXME: Currently discarding prefetches. 2997 return 0; 2998 2999 case Intrinsic::var_annotation: 3000 // Discard annotate attributes 3001 return 0; 3002 3003 case Intrinsic::init_trampoline: { 3004 const Function *F = 3005 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2))); 3006 3007 SDOperand Ops[6]; 3008 Ops[0] = getRoot(); 3009 Ops[1] = getValue(I.getOperand(1)); 3010 Ops[2] = getValue(I.getOperand(2)); 3011 Ops[3] = getValue(I.getOperand(3)); 3012 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 3013 Ops[5] = DAG.getSrcValue(F); 3014 3015 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE, 3016 DAG.getNodeValueTypes(TLI.getPointerTy(), 3017 MVT::Other), 2, 3018 Ops, 6); 3019 3020 setValue(&I, Tmp); 3021 DAG.setRoot(Tmp.getValue(1)); 3022 return 0; 3023 } 3024 3025 case Intrinsic::gcroot: 3026 if (GCI) { 3027 Value *Alloca = I.getOperand(1); 3028 Constant *TypeMap = cast<Constant>(I.getOperand(2)); 3029 3030 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val); 3031 GCI->addStackRoot(FI->getIndex(), TypeMap); 3032 } 3033 return 0; 3034 3035 case Intrinsic::gcread: 3036 case Intrinsic::gcwrite: 3037 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!"); 3038 return 0; 3039 3040 case Intrinsic::flt_rounds: { 3041 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32)); 3042 return 0; 3043 } 3044 3045 case Intrinsic::trap: { 3046 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot())); 3047 return 0; 3048 } 3049 } 3050} 3051 3052 3053void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee, 3054 bool IsTailCall, 3055 MachineBasicBlock *LandingPad) { 3056 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 3057 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 3058 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3059 unsigned BeginLabel = 0, EndLabel = 0; 3060 3061 TargetLowering::ArgListTy Args; 3062 TargetLowering::ArgListEntry Entry; 3063 Args.reserve(CS.arg_size()); 3064 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 3065 i != e; ++i) { 3066 SDOperand ArgNode = getValue(*i); 3067 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 3068 3069 unsigned attrInd = i - CS.arg_begin() + 1; 3070 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt); 3071 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt); 3072 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg); 3073 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet); 3074 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest); 3075 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal); 3076 Args.push_back(Entry); 3077 } 3078 3079 bool MarkTryRange = LandingPad || 3080 // C++ requires special handling of 'nounwind' calls. 3081 (CS.doesNotThrow()); 3082 3083 if (MarkTryRange && ExceptionHandling && MMI) { 3084 // Insert a label before the invoke call to mark the try range. This can be 3085 // used to detect deletion of the invoke via the MachineModuleInfo. 3086 BeginLabel = MMI->NextLabelID(); 3087 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 3088 DAG.getConstant(BeginLabel, MVT::i32), 3089 DAG.getConstant(1, MVT::i32))); 3090 } 3091 3092 std::pair<SDOperand,SDOperand> Result = 3093 TLI.LowerCallTo(getRoot(), CS.getType(), 3094 CS.paramHasAttr(0, ParamAttr::SExt), 3095 FTy->isVarArg(), CS.getCallingConv(), IsTailCall, 3096 Callee, Args, DAG); 3097 if (CS.getType() != Type::VoidTy) 3098 setValue(CS.getInstruction(), Result.first); 3099 DAG.setRoot(Result.second); 3100 3101 if (MarkTryRange && ExceptionHandling && MMI) { 3102 // Insert a label at the end of the invoke call to mark the try range. This 3103 // can be used to detect deletion of the invoke via the MachineModuleInfo. 3104 EndLabel = MMI->NextLabelID(); 3105 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 3106 DAG.getConstant(EndLabel, MVT::i32), 3107 DAG.getConstant(1, MVT::i32))); 3108 3109 // Inform MachineModuleInfo of range. 3110 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 3111 } 3112} 3113 3114 3115void SelectionDAGLowering::visitCall(CallInst &I) { 3116 const char *RenameFn = 0; 3117 if (Function *F = I.getCalledFunction()) { 3118 if (F->isDeclaration()) { 3119 if (unsigned IID = F->getIntrinsicID()) { 3120 RenameFn = visitIntrinsicCall(I, IID); 3121 if (!RenameFn) 3122 return; 3123 } 3124 } 3125 3126 // Check for well-known libc/libm calls. If the function is internal, it 3127 // can't be a library call. 3128 unsigned NameLen = F->getNameLen(); 3129 if (!F->hasInternalLinkage() && NameLen) { 3130 const char *NameStr = F->getNameStart(); 3131 if (NameStr[0] == 'c' && 3132 ((NameLen == 8 && !strcmp(NameStr, "copysign")) || 3133 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) { 3134 if (I.getNumOperands() == 3 && // Basic sanity checks. 3135 I.getOperand(1)->getType()->isFloatingPoint() && 3136 I.getType() == I.getOperand(1)->getType() && 3137 I.getType() == I.getOperand(2)->getType()) { 3138 SDOperand LHS = getValue(I.getOperand(1)); 3139 SDOperand RHS = getValue(I.getOperand(2)); 3140 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 3141 LHS, RHS)); 3142 return; 3143 } 3144 } else if (NameStr[0] == 'f' && 3145 ((NameLen == 4 && !strcmp(NameStr, "fabs")) || 3146 (NameLen == 5 && !strcmp(NameStr, "fabsf")) || 3147 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) { 3148 if (I.getNumOperands() == 2 && // Basic sanity checks. 3149 I.getOperand(1)->getType()->isFloatingPoint() && 3150 I.getType() == I.getOperand(1)->getType()) { 3151 SDOperand Tmp = getValue(I.getOperand(1)); 3152 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 3153 return; 3154 } 3155 } else if (NameStr[0] == 's' && 3156 ((NameLen == 3 && !strcmp(NameStr, "sin")) || 3157 (NameLen == 4 && !strcmp(NameStr, "sinf")) || 3158 (NameLen == 4 && !strcmp(NameStr, "sinl")))) { 3159 if (I.getNumOperands() == 2 && // Basic sanity checks. 3160 I.getOperand(1)->getType()->isFloatingPoint() && 3161 I.getType() == I.getOperand(1)->getType()) { 3162 SDOperand Tmp = getValue(I.getOperand(1)); 3163 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 3164 return; 3165 } 3166 } else if (NameStr[0] == 'c' && 3167 ((NameLen == 3 && !strcmp(NameStr, "cos")) || 3168 (NameLen == 4 && !strcmp(NameStr, "cosf")) || 3169 (NameLen == 4 && !strcmp(NameStr, "cosl")))) { 3170 if (I.getNumOperands() == 2 && // Basic sanity checks. 3171 I.getOperand(1)->getType()->isFloatingPoint() && 3172 I.getType() == I.getOperand(1)->getType()) { 3173 SDOperand Tmp = getValue(I.getOperand(1)); 3174 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 3175 return; 3176 } 3177 } 3178 } 3179 } else if (isa<InlineAsm>(I.getOperand(0))) { 3180 visitInlineAsm(&I); 3181 return; 3182 } 3183 3184 SDOperand Callee; 3185 if (!RenameFn) 3186 Callee = getValue(I.getOperand(0)); 3187 else 3188 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 3189 3190 LowerCallTo(&I, Callee, I.isTailCall()); 3191} 3192 3193 3194/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 3195/// this value and returns the result as a ValueVT value. This uses 3196/// Chain/Flag as the input and updates them for the output Chain/Flag. 3197/// If the Flag pointer is NULL, no flag is used. 3198SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 3199 SDOperand &Chain, SDOperand *Flag)const{ 3200 // Copy the legal parts from the registers. 3201 unsigned NumParts = Regs.size(); 3202 SmallVector<SDOperand, 8> Parts(NumParts); 3203 for (unsigned i = 0; i != NumParts; ++i) { 3204 SDOperand Part = Flag ? 3205 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) : 3206 DAG.getCopyFromReg(Chain, Regs[i], RegVT); 3207 Chain = Part.getValue(1); 3208 if (Flag) 3209 *Flag = Part.getValue(2); 3210 Parts[i] = Part; 3211 } 3212 3213 // Assemble the legal parts into the final value. 3214 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT); 3215} 3216 3217/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 3218/// specified value into the registers specified by this object. This uses 3219/// Chain/Flag as the input and updates them for the output Chain/Flag. 3220/// If the Flag pointer is NULL, no flag is used. 3221void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 3222 SDOperand &Chain, SDOperand *Flag) const { 3223 // Get the list of the values's legal parts. 3224 unsigned NumParts = Regs.size(); 3225 SmallVector<SDOperand, 8> Parts(NumParts); 3226 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT); 3227 3228 // Copy the parts into the registers. 3229 for (unsigned i = 0; i != NumParts; ++i) { 3230 SDOperand Part = Flag ? 3231 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) : 3232 DAG.getCopyToReg(Chain, Regs[i], Parts[i]); 3233 Chain = Part.getValue(0); 3234 if (Flag) 3235 *Flag = Part.getValue(1); 3236 } 3237} 3238 3239/// AddInlineAsmOperands - Add this value to the specified inlineasm node 3240/// operand list. This adds the code marker and includes the number of 3241/// values added into it. 3242void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 3243 std::vector<SDOperand> &Ops) const { 3244 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3245 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3246 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 3247 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 3248} 3249 3250/// isAllocatableRegister - If the specified register is safe to allocate, 3251/// i.e. it isn't a stack pointer or some other special register, return the 3252/// register class for the register. Otherwise, return null. 3253static const TargetRegisterClass * 3254isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3255 const TargetLowering &TLI, 3256 const TargetRegisterInfo *TRI) { 3257 MVT::ValueType FoundVT = MVT::Other; 3258 const TargetRegisterClass *FoundRC = 0; 3259 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 3260 E = TRI->regclass_end(); RCI != E; ++RCI) { 3261 MVT::ValueType ThisVT = MVT::Other; 3262 3263 const TargetRegisterClass *RC = *RCI; 3264 // If none of the the value types for this register class are valid, we 3265 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3266 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3267 I != E; ++I) { 3268 if (TLI.isTypeLegal(*I)) { 3269 // If we have already found this register in a different register class, 3270 // choose the one with the largest VT specified. For example, on 3271 // PowerPC, we favor f64 register classes over f32. 3272 if (FoundVT == MVT::Other || 3273 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 3274 ThisVT = *I; 3275 break; 3276 } 3277 } 3278 } 3279 3280 if (ThisVT == MVT::Other) continue; 3281 3282 // NOTE: This isn't ideal. In particular, this might allocate the 3283 // frame pointer in functions that need it (due to them not being taken 3284 // out of allocation, because a variable sized allocation hasn't been seen 3285 // yet). This is a slight code pessimization, but should still work. 3286 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3287 E = RC->allocation_order_end(MF); I != E; ++I) 3288 if (*I == Reg) { 3289 // We found a matching register class. Keep looking at others in case 3290 // we find one with larger registers that this physreg is also in. 3291 FoundRC = RC; 3292 FoundVT = ThisVT; 3293 break; 3294 } 3295 } 3296 return FoundRC; 3297} 3298 3299 3300namespace { 3301/// AsmOperandInfo - This contains information for each constraint that we are 3302/// lowering. 3303struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 3304 /// ConstraintCode - This contains the actual string for the code, like "m". 3305 std::string ConstraintCode; 3306 3307 /// ConstraintType - Information about the constraint code, e.g. Register, 3308 /// RegisterClass, Memory, Other, Unknown. 3309 TargetLowering::ConstraintType ConstraintType; 3310 3311 /// CallOperand/CallOperandval - If this is the result output operand or a 3312 /// clobber, this is null, otherwise it is the incoming operand to the 3313 /// CallInst. This gets modified as the asm is processed. 3314 SDOperand CallOperand; 3315 Value *CallOperandVal; 3316 3317 /// ConstraintVT - The ValueType for the operand value. 3318 MVT::ValueType ConstraintVT; 3319 3320 /// AssignedRegs - If this is a register or register class operand, this 3321 /// contains the set of register corresponding to the operand. 3322 RegsForValue AssignedRegs; 3323 3324 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3325 : InlineAsm::ConstraintInfo(info), 3326 ConstraintType(TargetLowering::C_Unknown), 3327 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) { 3328 } 3329 3330 void ComputeConstraintToUse(const TargetLowering &TLI); 3331 3332 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3333 /// busy in OutputRegs/InputRegs. 3334 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3335 std::set<unsigned> &OutputRegs, 3336 std::set<unsigned> &InputRegs) const { 3337 if (isOutReg) 3338 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3339 if (isInReg) 3340 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3341 } 3342}; 3343} // end anon namespace. 3344 3345/// getConstraintGenerality - Return an integer indicating how general CT is. 3346static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3347 switch (CT) { 3348 default: assert(0 && "Unknown constraint type!"); 3349 case TargetLowering::C_Other: 3350 case TargetLowering::C_Unknown: 3351 return 0; 3352 case TargetLowering::C_Register: 3353 return 1; 3354 case TargetLowering::C_RegisterClass: 3355 return 2; 3356 case TargetLowering::C_Memory: 3357 return 3; 3358 } 3359} 3360 3361void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) { 3362 assert(!Codes.empty() && "Must have at least one constraint"); 3363 3364 std::string *Current = &Codes[0]; 3365 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current); 3366 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common. 3367 ConstraintCode = *Current; 3368 ConstraintType = CurType; 3369 } else { 3370 unsigned CurGenerality = getConstraintGenerality(CurType); 3371 3372 // If we have multiple constraints, try to pick the most general one ahead 3373 // of time. This isn't a wonderful solution, but handles common cases. 3374 for (unsigned j = 1, e = Codes.size(); j != e; ++j) { 3375 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]); 3376 unsigned ThisGenerality = getConstraintGenerality(ThisType); 3377 if (ThisGenerality > CurGenerality) { 3378 // This constraint letter is more general than the previous one, 3379 // use it. 3380 CurType = ThisType; 3381 Current = &Codes[j]; 3382 CurGenerality = ThisGenerality; 3383 } 3384 } 3385 3386 ConstraintCode = *Current; 3387 ConstraintType = CurType; 3388 } 3389 3390 if (ConstraintCode == "X") { 3391 if (isa<BasicBlock>(CallOperandVal) || isa<ConstantInt>(CallOperandVal)) 3392 return; 3393 // This matches anything. Labels and constants we handle elsewhere 3394 // ('X' is the only thing that matches labels). Otherwise, try to 3395 // resolve it to something we know about by looking at the actual 3396 // operand type. 3397 std::string s = ""; 3398 TLI.lowerXConstraint(ConstraintVT, s); 3399 if (s!="") { 3400 ConstraintCode = s; 3401 ConstraintType = TLI.getConstraintType(ConstraintCode); 3402 } 3403 } 3404} 3405 3406 3407void SelectionDAGLowering:: 3408GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 3409 std::set<unsigned> &OutputRegs, 3410 std::set<unsigned> &InputRegs) { 3411 // Compute whether this value requires an input register, an output register, 3412 // or both. 3413 bool isOutReg = false; 3414 bool isInReg = false; 3415 switch (OpInfo.Type) { 3416 case InlineAsm::isOutput: 3417 isOutReg = true; 3418 3419 // If this is an early-clobber output, or if there is an input 3420 // constraint that matches this, we need to reserve the input register 3421 // so no other inputs allocate to it. 3422 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3423 break; 3424 case InlineAsm::isInput: 3425 isInReg = true; 3426 isOutReg = false; 3427 break; 3428 case InlineAsm::isClobber: 3429 isOutReg = true; 3430 isInReg = true; 3431 break; 3432 } 3433 3434 3435 MachineFunction &MF = DAG.getMachineFunction(); 3436 std::vector<unsigned> Regs; 3437 3438 // If this is a constraint for a single physreg, or a constraint for a 3439 // register class, find it. 3440 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3441 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3442 OpInfo.ConstraintVT); 3443 3444 unsigned NumRegs = 1; 3445 if (OpInfo.ConstraintVT != MVT::Other) 3446 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3447 MVT::ValueType RegVT; 3448 MVT::ValueType ValueVT = OpInfo.ConstraintVT; 3449 3450 3451 // If this is a constraint for a specific physical register, like {r17}, 3452 // assign it now. 3453 if (PhysReg.first) { 3454 if (OpInfo.ConstraintVT == MVT::Other) 3455 ValueVT = *PhysReg.second->vt_begin(); 3456 3457 // Get the actual register value type. This is important, because the user 3458 // may have asked for (e.g.) the AX register in i32 type. We need to 3459 // remember that AX is actually i16 to get the right extension. 3460 RegVT = *PhysReg.second->vt_begin(); 3461 3462 // This is a explicit reference to a physical register. 3463 Regs.push_back(PhysReg.first); 3464 3465 // If this is an expanded reference, add the rest of the regs to Regs. 3466 if (NumRegs != 1) { 3467 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3468 TargetRegisterClass::iterator E = PhysReg.second->end(); 3469 for (; *I != PhysReg.first; ++I) 3470 assert(I != E && "Didn't find reg!"); 3471 3472 // Already added the first reg. 3473 --NumRegs; ++I; 3474 for (; NumRegs; --NumRegs, ++I) { 3475 assert(I != E && "Ran out of registers to allocate!"); 3476 Regs.push_back(*I); 3477 } 3478 } 3479 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3480 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3481 return; 3482 } 3483 3484 // Otherwise, if this was a reference to an LLVM register class, create vregs 3485 // for this reference. 3486 std::vector<unsigned> RegClassRegs; 3487 const TargetRegisterClass *RC = PhysReg.second; 3488 if (RC) { 3489 // If this is an early clobber or tied register, our regalloc doesn't know 3490 // how to maintain the constraint. If it isn't, go ahead and create vreg 3491 // and let the regalloc do the right thing. 3492 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 3493 // If there is some other early clobber and this is an input register, 3494 // then we are forced to pre-allocate the input reg so it doesn't 3495 // conflict with the earlyclobber. 3496 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 3497 RegVT = *PhysReg.second->vt_begin(); 3498 3499 if (OpInfo.ConstraintVT == MVT::Other) 3500 ValueVT = RegVT; 3501 3502 // Create the appropriate number of virtual registers. 3503 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 3504 for (; NumRegs; --NumRegs) 3505 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second)); 3506 3507 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3508 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3509 return; 3510 } 3511 3512 // Otherwise, we can't allocate it. Let the code below figure out how to 3513 // maintain these constraints. 3514 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3515 3516 } else { 3517 // This is a reference to a register class that doesn't directly correspond 3518 // to an LLVM register class. Allocate NumRegs consecutive, available, 3519 // registers from the class. 3520 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3521 OpInfo.ConstraintVT); 3522 } 3523 3524 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 3525 unsigned NumAllocated = 0; 3526 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3527 unsigned Reg = RegClassRegs[i]; 3528 // See if this register is available. 3529 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3530 (isInReg && InputRegs.count(Reg))) { // Already used. 3531 // Make sure we find consecutive registers. 3532 NumAllocated = 0; 3533 continue; 3534 } 3535 3536 // Check to see if this register is allocatable (i.e. don't give out the 3537 // stack pointer). 3538 if (RC == 0) { 3539 RC = isAllocatableRegister(Reg, MF, TLI, TRI); 3540 if (!RC) { // Couldn't allocate this register. 3541 // Reset NumAllocated to make sure we return consecutive registers. 3542 NumAllocated = 0; 3543 continue; 3544 } 3545 } 3546 3547 // Okay, this register is good, we can use it. 3548 ++NumAllocated; 3549 3550 // If we allocated enough consecutive registers, succeed. 3551 if (NumAllocated == NumRegs) { 3552 unsigned RegStart = (i-NumAllocated)+1; 3553 unsigned RegEnd = i+1; 3554 // Mark all of the allocated registers used. 3555 for (unsigned i = RegStart; i != RegEnd; ++i) 3556 Regs.push_back(RegClassRegs[i]); 3557 3558 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 3559 OpInfo.ConstraintVT); 3560 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3561 return; 3562 } 3563 } 3564 3565 // Otherwise, we couldn't allocate enough registers for this. 3566 return; 3567} 3568 3569 3570/// visitInlineAsm - Handle a call to an InlineAsm object. 3571/// 3572void SelectionDAGLowering::visitInlineAsm(CallSite CS) { 3573 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 3574 3575 /// ConstraintOperands - Information about all of the constraints. 3576 std::vector<AsmOperandInfo> ConstraintOperands; 3577 3578 SDOperand Chain = getRoot(); 3579 SDOperand Flag; 3580 3581 std::set<unsigned> OutputRegs, InputRegs; 3582 3583 // Do a prepass over the constraints, canonicalizing them, and building up the 3584 // ConstraintOperands list. 3585 std::vector<InlineAsm::ConstraintInfo> 3586 ConstraintInfos = IA->ParseConstraints(); 3587 3588 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 3589 // constraint. If so, we can't let the register allocator allocate any input 3590 // registers, because it will not know to avoid the earlyclobbered output reg. 3591 bool SawEarlyClobber = false; 3592 3593 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 3594 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3595 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 3596 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 3597 3598 MVT::ValueType OpVT = MVT::Other; 3599 3600 // Compute the value type for each operand. 3601 switch (OpInfo.Type) { 3602 case InlineAsm::isOutput: 3603 if (!OpInfo.isIndirect) { 3604 // The return value of the call is this value. As such, there is no 3605 // corresponding argument. 3606 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 3607 OpVT = TLI.getValueType(CS.getType()); 3608 } else { 3609 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 3610 } 3611 break; 3612 case InlineAsm::isInput: 3613 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 3614 break; 3615 case InlineAsm::isClobber: 3616 // Nothing to do. 3617 break; 3618 } 3619 3620 // If this is an input or an indirect output, process the call argument. 3621 // BasicBlocks are labels, currently appearing only in asm's. 3622 if (OpInfo.CallOperandVal) { 3623 if (isa<BasicBlock>(OpInfo.CallOperandVal)) 3624 OpInfo.CallOperand = 3625 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>( 3626 OpInfo.CallOperandVal)]); 3627 else { 3628 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 3629 const Type *OpTy = OpInfo.CallOperandVal->getType(); 3630 // If this is an indirect operand, the operand is a pointer to the 3631 // accessed type. 3632 if (OpInfo.isIndirect) 3633 OpTy = cast<PointerType>(OpTy)->getElementType(); 3634 3635 // If OpTy is not a first-class value, it may be a struct/union that we 3636 // can tile with integers. 3637 if (!OpTy->isFirstClassType() && OpTy->isSized()) { 3638 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3639 switch (BitSize) { 3640 default: break; 3641 case 1: 3642 case 8: 3643 case 16: 3644 case 32: 3645 case 64: 3646 OpTy = IntegerType::get(BitSize); 3647 break; 3648 } 3649 } 3650 3651 OpVT = TLI.getValueType(OpTy, true); 3652 } 3653 } 3654 3655 OpInfo.ConstraintVT = OpVT; 3656 3657 // Compute the constraint code and ConstraintType to use. 3658 OpInfo.ComputeConstraintToUse(TLI); 3659 3660 // Keep track of whether we see an earlyclobber. 3661 SawEarlyClobber |= OpInfo.isEarlyClobber; 3662 3663 // If this is a memory input, and if the operand is not indirect, do what we 3664 // need to to provide an address for the memory input. 3665 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 3666 !OpInfo.isIndirect) { 3667 assert(OpInfo.Type == InlineAsm::isInput && 3668 "Can only indirectify direct input operands!"); 3669 3670 // Memory operands really want the address of the value. If we don't have 3671 // an indirect input, put it in the constpool if we can, otherwise spill 3672 // it to a stack slot. 3673 3674 // If the operand is a float, integer, or vector constant, spill to a 3675 // constant pool entry to get its address. 3676 Value *OpVal = OpInfo.CallOperandVal; 3677 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 3678 isa<ConstantVector>(OpVal)) { 3679 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 3680 TLI.getPointerTy()); 3681 } else { 3682 // Otherwise, create a stack slot and emit a store to it before the 3683 // asm. 3684 const Type *Ty = OpVal->getType(); 3685 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 3686 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3687 MachineFunction &MF = DAG.getMachineFunction(); 3688 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3689 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3690 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 3691 OpInfo.CallOperand = StackSlot; 3692 } 3693 3694 // There is no longer a Value* corresponding to this operand. 3695 OpInfo.CallOperandVal = 0; 3696 // It is now an indirect operand. 3697 OpInfo.isIndirect = true; 3698 } 3699 3700 // If this constraint is for a specific register, allocate it before 3701 // anything else. 3702 if (OpInfo.ConstraintType == TargetLowering::C_Register) 3703 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3704 } 3705 ConstraintInfos.clear(); 3706 3707 3708 // Second pass - Loop over all of the operands, assigning virtual or physregs 3709 // to registerclass operands. 3710 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3711 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3712 3713 // C_Register operands have already been allocated, Other/Memory don't need 3714 // to be. 3715 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 3716 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3717 } 3718 3719 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 3720 std::vector<SDOperand> AsmNodeOperands; 3721 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3722 AsmNodeOperands.push_back( 3723 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 3724 3725 3726 // Loop over all of the inputs, copying the operand values into the 3727 // appropriate registers and processing the output regs. 3728 RegsForValue RetValRegs; 3729 3730 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 3731 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3732 3733 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3734 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3735 3736 switch (OpInfo.Type) { 3737 case InlineAsm::isOutput: { 3738 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 3739 OpInfo.ConstraintType != TargetLowering::C_Register) { 3740 // Memory output, or 'other' output (e.g. 'X' constraint). 3741 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 3742 3743 // Add information to the INLINEASM node to know about this output. 3744 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3745 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3746 TLI.getPointerTy())); 3747 AsmNodeOperands.push_back(OpInfo.CallOperand); 3748 break; 3749 } 3750 3751 // Otherwise, this is a register or register class output. 3752 3753 // Copy the output from the appropriate register. Find a register that 3754 // we can use. 3755 if (OpInfo.AssignedRegs.Regs.empty()) { 3756 cerr << "Couldn't allocate output reg for contraint '" 3757 << OpInfo.ConstraintCode << "'!\n"; 3758 exit(1); 3759 } 3760 3761 if (!OpInfo.isIndirect) { 3762 // This is the result value of the call. 3763 assert(RetValRegs.Regs.empty() && 3764 "Cannot have multiple output constraints yet!"); 3765 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 3766 RetValRegs = OpInfo.AssignedRegs; 3767 } else { 3768 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 3769 OpInfo.CallOperandVal)); 3770 } 3771 3772 // Add information to the INLINEASM node to know that this register is 3773 // set. 3774 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 3775 AsmNodeOperands); 3776 break; 3777 } 3778 case InlineAsm::isInput: { 3779 SDOperand InOperandVal = OpInfo.CallOperand; 3780 3781 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 3782 // If this is required to match an output register we have already set, 3783 // just use its register. 3784 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 3785 3786 // Scan until we find the definition we already emitted of this operand. 3787 // When we find it, create a RegsForValue operand. 3788 unsigned CurOp = 2; // The first operand. 3789 for (; OperandNo; --OperandNo) { 3790 // Advance to the next operand. 3791 unsigned NumOps = 3792 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3793 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3794 (NumOps & 7) == 4 /*MEM*/) && 3795 "Skipped past definitions?"); 3796 CurOp += (NumOps>>3)+1; 3797 } 3798 3799 unsigned NumOps = 3800 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3801 if ((NumOps & 7) == 2 /*REGDEF*/) { 3802 // Add NumOps>>3 registers to MatchedRegs. 3803 RegsForValue MatchedRegs; 3804 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3805 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3806 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3807 unsigned Reg = 3808 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3809 MatchedRegs.Regs.push_back(Reg); 3810 } 3811 3812 // Use the produced MatchedRegs object to 3813 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3814 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3815 break; 3816 } else { 3817 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3818 assert(0 && "matching constraints for memory operands unimp"); 3819 } 3820 } 3821 3822 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 3823 assert(!OpInfo.isIndirect && 3824 "Don't know how to handle indirect other inputs yet!"); 3825 3826 std::vector<SDOperand> Ops; 3827 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 3828 Ops, DAG); 3829 if (Ops.empty()) { 3830 cerr << "Invalid operand for inline asm constraint '" 3831 << OpInfo.ConstraintCode << "'!\n"; 3832 exit(1); 3833 } 3834 3835 // Add information to the INLINEASM node to know about this input. 3836 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 3837 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3838 TLI.getPointerTy())); 3839 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 3840 break; 3841 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 3842 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 3843 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 3844 "Memory operands expect pointer values"); 3845 3846 // Add information to the INLINEASM node to know about this input. 3847 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3848 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3849 TLI.getPointerTy())); 3850 AsmNodeOperands.push_back(InOperandVal); 3851 break; 3852 } 3853 3854 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 3855 OpInfo.ConstraintType == TargetLowering::C_Register) && 3856 "Unknown constraint type!"); 3857 assert(!OpInfo.isIndirect && 3858 "Don't know how to handle indirect register inputs yet!"); 3859 3860 // Copy the input into the appropriate registers. 3861 assert(!OpInfo.AssignedRegs.Regs.empty() && 3862 "Couldn't allocate input reg!"); 3863 3864 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3865 3866 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 3867 AsmNodeOperands); 3868 break; 3869 } 3870 case InlineAsm::isClobber: { 3871 // Add the clobbered value to the operand list, so that the register 3872 // allocator is aware that the physreg got clobbered. 3873 if (!OpInfo.AssignedRegs.Regs.empty()) 3874 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 3875 AsmNodeOperands); 3876 break; 3877 } 3878 } 3879 } 3880 3881 // Finish up input operands. 3882 AsmNodeOperands[0] = Chain; 3883 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3884 3885 Chain = DAG.getNode(ISD::INLINEASM, 3886 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3887 &AsmNodeOperands[0], AsmNodeOperands.size()); 3888 Flag = Chain.getValue(1); 3889 3890 // If this asm returns a register value, copy the result from that register 3891 // and set it as the value of the call. 3892 if (!RetValRegs.Regs.empty()) { 3893 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 3894 3895 // If the result of the inline asm is a vector, it may have the wrong 3896 // width/num elts. Make sure to convert it to the right type with 3897 // bit_convert. 3898 if (MVT::isVector(Val.getValueType())) { 3899 const VectorType *VTy = cast<VectorType>(CS.getType()); 3900 MVT::ValueType DesiredVT = TLI.getValueType(VTy); 3901 3902 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val); 3903 } 3904 3905 setValue(CS.getInstruction(), Val); 3906 } 3907 3908 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 3909 3910 // Process indirect outputs, first output all of the flagged copies out of 3911 // physregs. 3912 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 3913 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 3914 Value *Ptr = IndirectStoresToEmit[i].second; 3915 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 3916 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 3917 } 3918 3919 // Emit the non-flagged stores from the physregs. 3920 SmallVector<SDOperand, 8> OutChains; 3921 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 3922 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 3923 getValue(StoresToEmit[i].second), 3924 StoresToEmit[i].second, 0)); 3925 if (!OutChains.empty()) 3926 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3927 &OutChains[0], OutChains.size()); 3928 DAG.setRoot(Chain); 3929} 3930 3931 3932void SelectionDAGLowering::visitMalloc(MallocInst &I) { 3933 SDOperand Src = getValue(I.getOperand(0)); 3934 3935 MVT::ValueType IntPtr = TLI.getPointerTy(); 3936 3937 if (IntPtr < Src.getValueType()) 3938 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 3939 else if (IntPtr > Src.getValueType()) 3940 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 3941 3942 // Scale the source by the type size. 3943 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType()); 3944 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 3945 Src, DAG.getIntPtrConstant(ElementSize)); 3946 3947 TargetLowering::ArgListTy Args; 3948 TargetLowering::ArgListEntry Entry; 3949 Entry.Node = Src; 3950 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3951 Args.push_back(Entry); 3952 3953 std::pair<SDOperand,SDOperand> Result = 3954 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true, 3955 DAG.getExternalSymbol("malloc", IntPtr), 3956 Args, DAG); 3957 setValue(&I, Result.first); // Pointers always fit in registers 3958 DAG.setRoot(Result.second); 3959} 3960 3961void SelectionDAGLowering::visitFree(FreeInst &I) { 3962 TargetLowering::ArgListTy Args; 3963 TargetLowering::ArgListEntry Entry; 3964 Entry.Node = getValue(I.getOperand(0)); 3965 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3966 Args.push_back(Entry); 3967 MVT::ValueType IntPtr = TLI.getPointerTy(); 3968 std::pair<SDOperand,SDOperand> Result = 3969 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true, 3970 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 3971 DAG.setRoot(Result.second); 3972} 3973 3974// EmitInstrWithCustomInserter - This method should be implemented by targets 3975// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 3976// instructions are special in various ways, which require special support to 3977// insert. The specified MachineInstr is created but not inserted into any 3978// basic blocks, and the scheduler passes ownership of it to this method. 3979MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 3980 MachineBasicBlock *MBB) { 3981 cerr << "If a target marks an instruction with " 3982 << "'usesCustomDAGSchedInserter', it must implement " 3983 << "TargetLowering::EmitInstrWithCustomInserter!\n"; 3984 abort(); 3985 return 0; 3986} 3987 3988void SelectionDAGLowering::visitVAStart(CallInst &I) { 3989 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 3990 getValue(I.getOperand(1)), 3991 DAG.getSrcValue(I.getOperand(1)))); 3992} 3993 3994void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 3995 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 3996 getValue(I.getOperand(0)), 3997 DAG.getSrcValue(I.getOperand(0))); 3998 setValue(&I, V); 3999 DAG.setRoot(V.getValue(1)); 4000} 4001 4002void SelectionDAGLowering::visitVAEnd(CallInst &I) { 4003 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 4004 getValue(I.getOperand(1)), 4005 DAG.getSrcValue(I.getOperand(1)))); 4006} 4007 4008void SelectionDAGLowering::visitVACopy(CallInst &I) { 4009 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 4010 getValue(I.getOperand(1)), 4011 getValue(I.getOperand(2)), 4012 DAG.getSrcValue(I.getOperand(1)), 4013 DAG.getSrcValue(I.getOperand(2)))); 4014} 4015 4016/// TargetLowering::LowerArguments - This is the default LowerArguments 4017/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 4018/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 4019/// integrated into SDISel. 4020std::vector<SDOperand> 4021TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 4022 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 4023 std::vector<SDOperand> Ops; 4024 Ops.push_back(DAG.getRoot()); 4025 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 4026 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 4027 4028 // Add one result value for each formal argument. 4029 std::vector<MVT::ValueType> RetVals; 4030 unsigned j = 1; 4031 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 4032 I != E; ++I, ++j) { 4033 MVT::ValueType VT = getValueType(I->getType()); 4034 unsigned Flags = ISD::ParamFlags::NoFlagSet; 4035 unsigned OriginalAlignment = 4036 getTargetData()->getABITypeAlignment(I->getType()); 4037 4038 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 4039 // that is zero extended! 4040 if (F.paramHasAttr(j, ParamAttr::ZExt)) 4041 Flags &= ~(ISD::ParamFlags::SExt); 4042 if (F.paramHasAttr(j, ParamAttr::SExt)) 4043 Flags |= ISD::ParamFlags::SExt; 4044 if (F.paramHasAttr(j, ParamAttr::InReg)) 4045 Flags |= ISD::ParamFlags::InReg; 4046 if (F.paramHasAttr(j, ParamAttr::StructRet)) 4047 Flags |= ISD::ParamFlags::StructReturn; 4048 if (F.paramHasAttr(j, ParamAttr::ByVal)) { 4049 Flags |= ISD::ParamFlags::ByVal; 4050 const PointerType *Ty = cast<PointerType>(I->getType()); 4051 const Type *ElementTy = Ty->getElementType(); 4052 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy)); 4053 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); 4054 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs); 4055 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs); 4056 } 4057 if (F.paramHasAttr(j, ParamAttr::Nest)) 4058 Flags |= ISD::ParamFlags::Nest; 4059 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs); 4060 4061 MVT::ValueType RegisterVT = getRegisterType(VT); 4062 unsigned NumRegs = getNumRegisters(VT); 4063 for (unsigned i = 0; i != NumRegs; ++i) { 4064 RetVals.push_back(RegisterVT); 4065 // if it isn't first piece, alignment must be 1 4066 if (i > 0) 4067 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 4068 (1 << ISD::ParamFlags::OrigAlignmentOffs); 4069 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4070 } 4071 } 4072 4073 RetVals.push_back(MVT::Other); 4074 4075 // Create the node. 4076 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 4077 DAG.getNodeValueTypes(RetVals), RetVals.size(), 4078 &Ops[0], Ops.size()).Val; 4079 unsigned NumArgRegs = Result->getNumValues() - 1; 4080 DAG.setRoot(SDOperand(Result, NumArgRegs)); 4081 4082 // Set up the return result vector. 4083 Ops.clear(); 4084 unsigned i = 0; 4085 unsigned Idx = 1; 4086 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 4087 ++I, ++Idx) { 4088 MVT::ValueType VT = getValueType(I->getType()); 4089 MVT::ValueType PartVT = getRegisterType(VT); 4090 4091 unsigned NumParts = getNumRegisters(VT); 4092 SmallVector<SDOperand, 4> Parts(NumParts); 4093 for (unsigned j = 0; j != NumParts; ++j) 4094 Parts[j] = SDOperand(Result, i++); 4095 4096 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4097 if (F.paramHasAttr(Idx, ParamAttr::SExt)) 4098 AssertOp = ISD::AssertSext; 4099 else if (F.paramHasAttr(Idx, ParamAttr::ZExt)) 4100 AssertOp = ISD::AssertZext; 4101 4102 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT, 4103 AssertOp, true)); 4104 } 4105 assert(i == NumArgRegs && "Argument register count mismatch!"); 4106 return Ops; 4107} 4108 4109 4110/// TargetLowering::LowerCallTo - This is the default LowerCallTo 4111/// implementation, which just inserts an ISD::CALL node, which is later custom 4112/// lowered by the target to something concrete. FIXME: When all targets are 4113/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 4114std::pair<SDOperand, SDOperand> 4115TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 4116 bool RetTyIsSigned, bool isVarArg, 4117 unsigned CallingConv, bool isTailCall, 4118 SDOperand Callee, 4119 ArgListTy &Args, SelectionDAG &DAG) { 4120 SmallVector<SDOperand, 32> Ops; 4121 Ops.push_back(Chain); // Op#0 - Chain 4122 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 4123 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 4124 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 4125 Ops.push_back(Callee); 4126 4127 // Handle all of the outgoing arguments. 4128 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 4129 MVT::ValueType VT = getValueType(Args[i].Ty); 4130 SDOperand Op = Args[i].Node; 4131 unsigned Flags = ISD::ParamFlags::NoFlagSet; 4132 unsigned OriginalAlignment = 4133 getTargetData()->getABITypeAlignment(Args[i].Ty); 4134 4135 if (Args[i].isSExt) 4136 Flags |= ISD::ParamFlags::SExt; 4137 if (Args[i].isZExt) 4138 Flags |= ISD::ParamFlags::ZExt; 4139 if (Args[i].isInReg) 4140 Flags |= ISD::ParamFlags::InReg; 4141 if (Args[i].isSRet) 4142 Flags |= ISD::ParamFlags::StructReturn; 4143 if (Args[i].isByVal) { 4144 Flags |= ISD::ParamFlags::ByVal; 4145 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 4146 const Type *ElementTy = Ty->getElementType(); 4147 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy)); 4148 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); 4149 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs); 4150 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs); 4151 } 4152 if (Args[i].isNest) 4153 Flags |= ISD::ParamFlags::Nest; 4154 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs; 4155 4156 MVT::ValueType PartVT = getRegisterType(VT); 4157 unsigned NumParts = getNumRegisters(VT); 4158 SmallVector<SDOperand, 4> Parts(NumParts); 4159 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 4160 4161 if (Args[i].isSExt) 4162 ExtendKind = ISD::SIGN_EXTEND; 4163 else if (Args[i].isZExt) 4164 ExtendKind = ISD::ZERO_EXTEND; 4165 4166 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind); 4167 4168 for (unsigned i = 0; i != NumParts; ++i) { 4169 // if it isn't first piece, alignment must be 1 4170 unsigned MyFlags = Flags; 4171 if (i != 0) 4172 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) | 4173 (1 << ISD::ParamFlags::OrigAlignmentOffs); 4174 4175 Ops.push_back(Parts[i]); 4176 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32)); 4177 } 4178 } 4179 4180 // Figure out the result value types. 4181 MVT::ValueType VT = getValueType(RetTy); 4182 MVT::ValueType RegisterVT = getRegisterType(VT); 4183 unsigned NumRegs = getNumRegisters(VT); 4184 SmallVector<MVT::ValueType, 4> RetTys(NumRegs); 4185 for (unsigned i = 0; i != NumRegs; ++i) 4186 RetTys[i] = RegisterVT; 4187 4188 RetTys.push_back(MVT::Other); // Always has a chain. 4189 4190 // Create the CALL node. 4191 SDOperand Res = DAG.getNode(ISD::CALL, 4192 DAG.getVTList(&RetTys[0], NumRegs + 1), 4193 &Ops[0], Ops.size()); 4194 Chain = Res.getValue(NumRegs); 4195 4196 // Gather up the call result into a single value. 4197 if (RetTy != Type::VoidTy) { 4198 ISD::NodeType AssertOp = ISD::AssertSext; 4199 if (!RetTyIsSigned) 4200 AssertOp = ISD::AssertZext; 4201 SmallVector<SDOperand, 4> Results(NumRegs); 4202 for (unsigned i = 0; i != NumRegs; ++i) 4203 Results[i] = Res.getValue(i); 4204 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp); 4205 } 4206 4207 return std::make_pair(Res, Chain); 4208} 4209 4210SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4211 assert(0 && "LowerOperation not implemented for this target!"); 4212 abort(); 4213 return SDOperand(); 4214} 4215 4216SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 4217 SelectionDAG &DAG) { 4218 assert(0 && "CustomPromoteOperation not implemented for this target!"); 4219 abort(); 4220 return SDOperand(); 4221} 4222 4223/// getMemsetValue - Vectorized representation of the memset value 4224/// operand. 4225static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 4226 SelectionDAG &DAG) { 4227 MVT::ValueType CurVT = VT; 4228 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 4229 uint64_t Val = C->getValue() & 255; 4230 unsigned Shift = 8; 4231 while (CurVT != MVT::i8) { 4232 Val = (Val << Shift) | Val; 4233 Shift <<= 1; 4234 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4235 } 4236 return DAG.getConstant(Val, VT); 4237 } else { 4238 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4239 unsigned Shift = 8; 4240 while (CurVT != MVT::i8) { 4241 Value = 4242 DAG.getNode(ISD::OR, VT, 4243 DAG.getNode(ISD::SHL, VT, Value, 4244 DAG.getConstant(Shift, MVT::i8)), Value); 4245 Shift <<= 1; 4246 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4247 } 4248 4249 return Value; 4250 } 4251} 4252 4253/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4254/// used when a memcpy is turned into a memset when the source is a constant 4255/// string ptr. 4256static SDOperand getMemsetStringVal(MVT::ValueType VT, 4257 SelectionDAG &DAG, TargetLowering &TLI, 4258 std::string &Str, unsigned Offset) { 4259 uint64_t Val = 0; 4260 unsigned MSB = MVT::getSizeInBits(VT) / 8; 4261 if (TLI.isLittleEndian()) 4262 Offset = Offset + MSB - 1; 4263 for (unsigned i = 0; i != MSB; ++i) { 4264 Val = (Val << 8) | (unsigned char)Str[Offset]; 4265 Offset += TLI.isLittleEndian() ? -1 : 1; 4266 } 4267 return DAG.getConstant(Val, VT); 4268} 4269 4270/// getMemBasePlusOffset - Returns base and offset node for the 4271static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4272 SelectionDAG &DAG, TargetLowering &TLI) { 4273 MVT::ValueType VT = Base.getValueType(); 4274 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4275} 4276 4277/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4278/// to replace the memset / memcpy is below the threshold. It also returns the 4279/// types of the sequence of memory ops to perform memset / memcpy. 4280static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4281 unsigned Limit, uint64_t Size, 4282 unsigned Align, TargetLowering &TLI) { 4283 MVT::ValueType VT; 4284 4285 if (TLI.allowsUnalignedMemoryAccesses()) { 4286 VT = MVT::i64; 4287 } else { 4288 switch (Align & 7) { 4289 case 0: 4290 VT = MVT::i64; 4291 break; 4292 case 4: 4293 VT = MVT::i32; 4294 break; 4295 case 2: 4296 VT = MVT::i16; 4297 break; 4298 default: 4299 VT = MVT::i8; 4300 break; 4301 } 4302 } 4303 4304 MVT::ValueType LVT = MVT::i64; 4305 while (!TLI.isTypeLegal(LVT)) 4306 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4307 assert(MVT::isInteger(LVT)); 4308 4309 if (VT > LVT) 4310 VT = LVT; 4311 4312 unsigned NumMemOps = 0; 4313 while (Size != 0) { 4314 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4315 while (VTSize > Size) { 4316 VT = (MVT::ValueType)((unsigned)VT - 1); 4317 VTSize >>= 1; 4318 } 4319 assert(MVT::isInteger(VT)); 4320 4321 if (++NumMemOps > Limit) 4322 return false; 4323 MemOps.push_back(VT); 4324 Size -= VTSize; 4325 } 4326 4327 return true; 4328} 4329 4330void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4331 SDOperand Op1 = getValue(I.getOperand(1)); 4332 SDOperand Op2 = getValue(I.getOperand(2)); 4333 SDOperand Op3 = getValue(I.getOperand(3)); 4334 SDOperand Op4 = getValue(I.getOperand(4)); 4335 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4336 if (Align == 0) Align = 1; 4337 4338 // If the source and destination are known to not be aliases, we can 4339 // lower memmove as memcpy. 4340 if (Op == ISD::MEMMOVE) { 4341 uint64_t Size = -1ULL; 4342 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 4343 Size = C->getValue(); 4344 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) == 4345 AliasAnalysis::NoAlias) 4346 Op = ISD::MEMCPY; 4347 } 4348 4349 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4350 std::vector<MVT::ValueType> MemOps; 4351 4352 // Expand memset / memcpy to a series of load / store ops 4353 // if the size operand falls below a certain threshold. 4354 SmallVector<SDOperand, 8> OutChains; 4355 switch (Op) { 4356 default: break; // Do nothing for now. 4357 case ISD::MEMSET: { 4358 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4359 Size->getValue(), Align, TLI)) { 4360 unsigned NumMemOps = MemOps.size(); 4361 unsigned Offset = 0; 4362 for (unsigned i = 0; i < NumMemOps; i++) { 4363 MVT::ValueType VT = MemOps[i]; 4364 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4365 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4366 SDOperand Store = DAG.getStore(getRoot(), Value, 4367 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4368 I.getOperand(1), Offset); 4369 OutChains.push_back(Store); 4370 Offset += VTSize; 4371 } 4372 } 4373 break; 4374 } 4375 case ISD::MEMCPY: { 4376 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4377 Size->getValue(), Align, TLI)) { 4378 unsigned NumMemOps = MemOps.size(); 4379 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4380 GlobalAddressSDNode *G = NULL; 4381 std::string Str; 4382 bool CopyFromStr = false; 4383 4384 if (Op2.getOpcode() == ISD::GlobalAddress) 4385 G = cast<GlobalAddressSDNode>(Op2); 4386 else if (Op2.getOpcode() == ISD::ADD && 4387 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4388 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4389 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4390 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4391 } 4392 if (G) { 4393 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4394 if (GV && GV->isConstant()) { 4395 Str = GV->getStringValue(false); 4396 if (!Str.empty()) { 4397 CopyFromStr = true; 4398 SrcOff += SrcDelta; 4399 } 4400 } 4401 } 4402 4403 for (unsigned i = 0; i < NumMemOps; i++) { 4404 MVT::ValueType VT = MemOps[i]; 4405 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4406 SDOperand Value, Chain, Store; 4407 4408 if (CopyFromStr) { 4409 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4410 Chain = getRoot(); 4411 Store = 4412 DAG.getStore(Chain, Value, 4413 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4414 I.getOperand(1), DstOff); 4415 } else { 4416 Value = DAG.getLoad(VT, getRoot(), 4417 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4418 I.getOperand(2), SrcOff, false, Align); 4419 Chain = Value.getValue(1); 4420 Store = 4421 DAG.getStore(Chain, Value, 4422 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4423 I.getOperand(1), DstOff, false, Align); 4424 } 4425 OutChains.push_back(Store); 4426 SrcOff += VTSize; 4427 DstOff += VTSize; 4428 } 4429 } 4430 break; 4431 } 4432 } 4433 4434 if (!OutChains.empty()) { 4435 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4436 &OutChains[0], OutChains.size())); 4437 return; 4438 } 4439 } 4440 4441 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1); 4442 SDOperand Node; 4443 switch(Op) { 4444 default: 4445 assert(0 && "Unknown Op"); 4446 case ISD::MEMCPY: 4447 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4448 break; 4449 case ISD::MEMMOVE: 4450 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4451 break; 4452 case ISD::MEMSET: 4453 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4454 break; 4455 } 4456 DAG.setRoot(Node); 4457} 4458 4459//===----------------------------------------------------------------------===// 4460// SelectionDAGISel code 4461//===----------------------------------------------------------------------===// 4462 4463unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4464 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 4465} 4466 4467void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4468 AU.addRequired<AliasAnalysis>(); 4469 AU.addRequired<CollectorModuleMetadata>(); 4470 AU.setPreservesAll(); 4471} 4472 4473 4474 4475bool SelectionDAGISel::runOnFunction(Function &Fn) { 4476 // Get alias analysis for load/store combining. 4477 AA = &getAnalysis<AliasAnalysis>(); 4478 4479 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4480 if (MF.getFunction()->hasCollector()) 4481 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction()); 4482 else 4483 GCI = 0; 4484 RegInfo = &MF.getRegInfo(); 4485 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4486 4487 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4488 4489 if (ExceptionHandling) 4490 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4491 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4492 // Mark landing pad. 4493 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4494 4495 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4496 SelectBasicBlock(I, MF, FuncInfo); 4497 4498 // Add function live-ins to entry block live-in set. 4499 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4500 BB = FuncInfo.MBBMap[EntryBB]; 4501 if (!RegInfo->livein_empty()) 4502 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 4503 E = RegInfo->livein_end(); I != E; ++I) 4504 BB->addLiveIn(I->first); 4505 4506#ifndef NDEBUG 4507 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4508 "Not all catch info was assigned to a landing pad!"); 4509#endif 4510 4511 return true; 4512} 4513 4514SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4515 unsigned Reg) { 4516 SDOperand Op = getValue(V); 4517 assert((Op.getOpcode() != ISD::CopyFromReg || 4518 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4519 "Copy from a reg to the same reg!"); 4520 4521 MVT::ValueType SrcVT = Op.getValueType(); 4522 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT); 4523 unsigned NumRegs = TLI.getNumRegisters(SrcVT); 4524 SmallVector<SDOperand, 8> Regs(NumRegs); 4525 SmallVector<SDOperand, 8> Chains(NumRegs); 4526 4527 // Copy the value by legal parts into sequential virtual registers. 4528 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT); 4529 for (unsigned i = 0; i != NumRegs; ++i) 4530 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); 4531 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 4532} 4533 4534void SelectionDAGISel:: 4535LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4536 std::vector<SDOperand> &UnorderedChains) { 4537 // If this is the entry block, emit arguments. 4538 Function &F = *LLVMBB->getParent(); 4539 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4540 SDOperand OldRoot = SDL.DAG.getRoot(); 4541 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4542 4543 unsigned a = 0; 4544 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4545 AI != E; ++AI, ++a) 4546 if (!AI->use_empty()) { 4547 SDL.setValue(AI, Args[a]); 4548 4549 // If this argument is live outside of the entry block, insert a copy from 4550 // whereever we got it to the vreg that other BB's will reference it as. 4551 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4552 if (VMI != FuncInfo.ValueMap.end()) { 4553 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4554 UnorderedChains.push_back(Copy); 4555 } 4556 } 4557 4558 // Finally, if the target has anything special to do, allow it to do so. 4559 // FIXME: this should insert code into the DAG! 4560 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4561} 4562 4563static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4564 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4565 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4566 if (isSelector(I)) { 4567 // Apply the catch info to DestBB. 4568 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4569#ifndef NDEBUG 4570 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 4571 FLI.CatchInfoFound.insert(I); 4572#endif 4573 } 4574} 4575 4576/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 4577/// DAG and fixes their tailcall attribute operand. 4578static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 4579 TargetLowering& TLI) { 4580 SDNode * Ret = NULL; 4581 SDOperand Terminator = DAG.getRoot(); 4582 4583 // Find RET node. 4584 if (Terminator.getOpcode() == ISD::RET) { 4585 Ret = Terminator.Val; 4586 } 4587 4588 // Fix tail call attribute of CALL nodes. 4589 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 4590 BI = prior(DAG.allnodes_end()); BI != BE; --BI) { 4591 if (BI->getOpcode() == ISD::CALL) { 4592 SDOperand OpRet(Ret, 0); 4593 SDOperand OpCall(static_cast<SDNode*>(BI), 0); 4594 bool isMarkedTailCall = 4595 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0; 4596 // If CALL node has tail call attribute set to true and the call is not 4597 // eligible (no RET or the target rejects) the attribute is fixed to 4598 // false. The TargetLowering::IsEligibleForTailCallOptimization function 4599 // must correctly identify tail call optimizable calls. 4600 if (isMarkedTailCall && 4601 (Ret==NULL || 4602 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) { 4603 SmallVector<SDOperand, 32> Ops; 4604 unsigned idx=0; 4605 for(SDNode::op_iterator I =OpCall.Val->op_begin(), 4606 E=OpCall.Val->op_end(); I!=E; I++, idx++) { 4607 if (idx!=3) 4608 Ops.push_back(*I); 4609 else 4610 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy())); 4611 } 4612 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 4613 } 4614 } 4615 } 4616} 4617 4618void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4619 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4620 FunctionLoweringInfo &FuncInfo) { 4621 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI); 4622 4623 std::vector<SDOperand> UnorderedChains; 4624 4625 // Lower any arguments needed in this block if this is the entry block. 4626 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4627 LowerArguments(LLVMBB, SDL, UnorderedChains); 4628 4629 BB = FuncInfo.MBBMap[LLVMBB]; 4630 SDL.setCurrentBasicBlock(BB); 4631 4632 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4633 4634 if (ExceptionHandling && MMI && BB->isLandingPad()) { 4635 // Add a label to mark the beginning of the landing pad. Deletion of the 4636 // landing pad can thus be detected via the MachineModuleInfo. 4637 unsigned LabelID = MMI->addLandingPad(BB); 4638 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 4639 DAG.getConstant(LabelID, MVT::i32), 4640 DAG.getConstant(1, MVT::i32))); 4641 4642 // Mark exception register as live in. 4643 unsigned Reg = TLI.getExceptionAddressRegister(); 4644 if (Reg) BB->addLiveIn(Reg); 4645 4646 // Mark exception selector register as live in. 4647 Reg = TLI.getExceptionSelectorRegister(); 4648 if (Reg) BB->addLiveIn(Reg); 4649 4650 // FIXME: Hack around an exception handling flaw (PR1508): the personality 4651 // function and list of typeids logically belong to the invoke (or, if you 4652 // like, the basic block containing the invoke), and need to be associated 4653 // with it in the dwarf exception handling tables. Currently however the 4654 // information is provided by an intrinsic (eh.selector) that can be moved 4655 // to unexpected places by the optimizers: if the unwind edge is critical, 4656 // then breaking it can result in the intrinsics being in the successor of 4657 // the landing pad, not the landing pad itself. This results in exceptions 4658 // not being caught because no typeids are associated with the invoke. 4659 // This may not be the only way things can go wrong, but it is the only way 4660 // we try to work around for the moment. 4661 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 4662 4663 if (Br && Br->isUnconditional()) { // Critical edge? 4664 BasicBlock::iterator I, E; 4665 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 4666 if (isSelector(I)) 4667 break; 4668 4669 if (I == E) 4670 // No catch info found - try to extract some from the successor. 4671 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 4672 } 4673 } 4674 4675 // Lower all of the non-terminator instructions. 4676 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4677 I != E; ++I) 4678 SDL.visit(*I); 4679 4680 // Ensure that all instructions which are used outside of their defining 4681 // blocks are available as virtual registers. Invoke is handled elsewhere. 4682 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4683 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 4684 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4685 if (VMI != FuncInfo.ValueMap.end()) 4686 UnorderedChains.push_back( 4687 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4688 } 4689 4690 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4691 // ensure constants are generated when needed. Remember the virtual registers 4692 // that need to be added to the Machine PHI nodes as input. We cannot just 4693 // directly add them, because expansion might result in multiple MBB's for one 4694 // BB. As such, the start of the BB might correspond to a different MBB than 4695 // the end. 4696 // 4697 TerminatorInst *TI = LLVMBB->getTerminator(); 4698 4699 // Emit constants only once even if used by multiple PHI nodes. 4700 std::map<Constant*, unsigned> ConstantsOut; 4701 4702 // Vector bool would be better, but vector<bool> is really slow. 4703 std::vector<unsigned char> SuccsHandled; 4704 if (TI->getNumSuccessors()) 4705 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4706 4707 // Check successor nodes' PHI nodes that expect a constant to be available 4708 // from this block. 4709 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4710 BasicBlock *SuccBB = TI->getSuccessor(succ); 4711 if (!isa<PHINode>(SuccBB->begin())) continue; 4712 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4713 4714 // If this terminator has multiple identical successors (common for 4715 // switches), only handle each succ once. 4716 unsigned SuccMBBNo = SuccMBB->getNumber(); 4717 if (SuccsHandled[SuccMBBNo]) continue; 4718 SuccsHandled[SuccMBBNo] = true; 4719 4720 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4721 PHINode *PN; 4722 4723 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4724 // nodes and Machine PHI nodes, but the incoming operands have not been 4725 // emitted yet. 4726 for (BasicBlock::iterator I = SuccBB->begin(); 4727 (PN = dyn_cast<PHINode>(I)); ++I) { 4728 // Ignore dead phi's. 4729 if (PN->use_empty()) continue; 4730 4731 unsigned Reg; 4732 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4733 4734 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4735 unsigned &RegOut = ConstantsOut[C]; 4736 if (RegOut == 0) { 4737 RegOut = FuncInfo.CreateRegForValue(C); 4738 UnorderedChains.push_back( 4739 SDL.CopyValueToVirtualRegister(C, RegOut)); 4740 } 4741 Reg = RegOut; 4742 } else { 4743 Reg = FuncInfo.ValueMap[PHIOp]; 4744 if (Reg == 0) { 4745 assert(isa<AllocaInst>(PHIOp) && 4746 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4747 "Didn't codegen value into a register!??"); 4748 Reg = FuncInfo.CreateRegForValue(PHIOp); 4749 UnorderedChains.push_back( 4750 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4751 } 4752 } 4753 4754 // Remember that this register needs to added to the machine PHI node as 4755 // the input for this MBB. 4756 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4757 unsigned NumRegisters = TLI.getNumRegisters(VT); 4758 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 4759 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4760 } 4761 } 4762 ConstantsOut.clear(); 4763 4764 // Turn all of the unordered chains into one factored node. 4765 if (!UnorderedChains.empty()) { 4766 SDOperand Root = SDL.getRoot(); 4767 if (Root.getOpcode() != ISD::EntryToken) { 4768 unsigned i = 0, e = UnorderedChains.size(); 4769 for (; i != e; ++i) { 4770 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4771 if (UnorderedChains[i].Val->getOperand(0) == Root) 4772 break; // Don't add the root if we already indirectly depend on it. 4773 } 4774 4775 if (i == e) 4776 UnorderedChains.push_back(Root); 4777 } 4778 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4779 &UnorderedChains[0], UnorderedChains.size())); 4780 } 4781 4782 // Lower the terminator after the copies are emitted. 4783 SDL.visit(*LLVMBB->getTerminator()); 4784 4785 // Copy over any CaseBlock records that may now exist due to SwitchInst 4786 // lowering, as well as any jump table information. 4787 SwitchCases.clear(); 4788 SwitchCases = SDL.SwitchCases; 4789 JTCases.clear(); 4790 JTCases = SDL.JTCases; 4791 BitTestCases.clear(); 4792 BitTestCases = SDL.BitTestCases; 4793 4794 // Make sure the root of the DAG is up-to-date. 4795 DAG.setRoot(SDL.getRoot()); 4796 4797 // Check whether calls in this block are real tail calls. Fix up CALL nodes 4798 // with correct tailcall attribute so that the target can rely on the tailcall 4799 // attribute indicating whether the call is really eligible for tail call 4800 // optimization. 4801 CheckDAGForTailCallsAndFixThem(DAG, TLI); 4802} 4803 4804void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4805 DOUT << "Lowered selection DAG:\n"; 4806 DEBUG(DAG.dump()); 4807 4808 // Run the DAG combiner in pre-legalize mode. 4809 DAG.Combine(false, *AA); 4810 4811 DOUT << "Optimized lowered selection DAG:\n"; 4812 DEBUG(DAG.dump()); 4813 4814 // Second step, hack on the DAG until it only uses operations and types that 4815 // the target supports. 4816#if 0 // Enable this some day. 4817 DAG.LegalizeTypes(); 4818 // Someday even later, enable a dag combine pass here. 4819#endif 4820 DAG.Legalize(); 4821 4822 DOUT << "Legalized selection DAG:\n"; 4823 DEBUG(DAG.dump()); 4824 4825 // Run the DAG combiner in post-legalize mode. 4826 DAG.Combine(true, *AA); 4827 4828 DOUT << "Optimized legalized selection DAG:\n"; 4829 DEBUG(DAG.dump()); 4830 4831 if (ViewISelDAGs) DAG.viewGraph(); 4832 4833 // Third, instruction select all of the operations to machine code, adding the 4834 // code to the MachineBasicBlock. 4835 InstructionSelectBasicBlock(DAG); 4836 4837 DOUT << "Selected machine code:\n"; 4838 DEBUG(BB->dump()); 4839} 4840 4841void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4842 FunctionLoweringInfo &FuncInfo) { 4843 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4844 { 4845 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4846 CurDAG = &DAG; 4847 4848 // First step, lower LLVM code to some DAG. This DAG may use operations and 4849 // types that are not supported by the target. 4850 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4851 4852 // Second step, emit the lowered DAG as machine code. 4853 CodeGenAndEmitDAG(DAG); 4854 } 4855 4856 DOUT << "Total amount of phi nodes to update: " 4857 << PHINodesToUpdate.size() << "\n"; 4858 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4859 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4860 << ", " << PHINodesToUpdate[i].second << ")\n";); 4861 4862 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4863 // PHI nodes in successors. 4864 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4865 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4866 MachineInstr *PHI = PHINodesToUpdate[i].first; 4867 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4868 "This is not a machine PHI node that we are updating!"); 4869 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 4870 false)); 4871 PHI->addOperand(MachineOperand::CreateMBB(BB)); 4872 } 4873 return; 4874 } 4875 4876 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4877 // Lower header first, if it wasn't already lowered 4878 if (!BitTestCases[i].Emitted) { 4879 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4880 CurDAG = &HSDAG; 4881 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); 4882 // Set the current basic block to the mbb we wish to insert the code into 4883 BB = BitTestCases[i].Parent; 4884 HSDL.setCurrentBasicBlock(BB); 4885 // Emit the code 4886 HSDL.visitBitTestHeader(BitTestCases[i]); 4887 HSDAG.setRoot(HSDL.getRoot()); 4888 CodeGenAndEmitDAG(HSDAG); 4889 } 4890 4891 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4892 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4893 CurDAG = &BSDAG; 4894 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI); 4895 // Set the current basic block to the mbb we wish to insert the code into 4896 BB = BitTestCases[i].Cases[j].ThisBB; 4897 BSDL.setCurrentBasicBlock(BB); 4898 // Emit the code 4899 if (j+1 != ej) 4900 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 4901 BitTestCases[i].Reg, 4902 BitTestCases[i].Cases[j]); 4903 else 4904 BSDL.visitBitTestCase(BitTestCases[i].Default, 4905 BitTestCases[i].Reg, 4906 BitTestCases[i].Cases[j]); 4907 4908 4909 BSDAG.setRoot(BSDL.getRoot()); 4910 CodeGenAndEmitDAG(BSDAG); 4911 } 4912 4913 // Update PHI Nodes 4914 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4915 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4916 MachineBasicBlock *PHIBB = PHI->getParent(); 4917 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4918 "This is not a machine PHI node that we are updating!"); 4919 // This is "default" BB. We have two jumps to it. From "header" BB and 4920 // from last "case" BB. 4921 if (PHIBB == BitTestCases[i].Default) { 4922 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 4923 false)); 4924 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent)); 4925 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 4926 false)); 4927 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases. 4928 back().ThisBB)); 4929 } 4930 // One of "cases" BB. 4931 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4932 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 4933 if (cBB->succ_end() != 4934 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 4935 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 4936 false)); 4937 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 4938 } 4939 } 4940 } 4941 } 4942 4943 // If the JumpTable record is filled in, then we need to emit a jump table. 4944 // Updating the PHI nodes is tricky in this case, since we need to determine 4945 // whether the PHI is a successor of the range check MBB or the jump table MBB 4946 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 4947 // Lower header first, if it wasn't already lowered 4948 if (!JTCases[i].first.Emitted) { 4949 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4950 CurDAG = &HSDAG; 4951 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); 4952 // Set the current basic block to the mbb we wish to insert the code into 4953 BB = JTCases[i].first.HeaderBB; 4954 HSDL.setCurrentBasicBlock(BB); 4955 // Emit the code 4956 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 4957 HSDAG.setRoot(HSDL.getRoot()); 4958 CodeGenAndEmitDAG(HSDAG); 4959 } 4960 4961 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4962 CurDAG = &JSDAG; 4963 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI); 4964 // Set the current basic block to the mbb we wish to insert the code into 4965 BB = JTCases[i].second.MBB; 4966 JSDL.setCurrentBasicBlock(BB); 4967 // Emit the code 4968 JSDL.visitJumpTable(JTCases[i].second); 4969 JSDAG.setRoot(JSDL.getRoot()); 4970 CodeGenAndEmitDAG(JSDAG); 4971 4972 // Update PHI Nodes 4973 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4974 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4975 MachineBasicBlock *PHIBB = PHI->getParent(); 4976 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4977 "This is not a machine PHI node that we are updating!"); 4978 // "default" BB. We can go there only from header BB. 4979 if (PHIBB == JTCases[i].second.Default) { 4980 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 4981 false)); 4982 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB)); 4983 } 4984 // JT BB. Just iterate over successors here 4985 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 4986 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 4987 false)); 4988 PHI->addOperand(MachineOperand::CreateMBB(BB)); 4989 } 4990 } 4991 } 4992 4993 // If the switch block involved a branch to one of the actual successors, we 4994 // need to update PHI nodes in that block. 4995 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4996 MachineInstr *PHI = PHINodesToUpdate[i].first; 4997 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4998 "This is not a machine PHI node that we are updating!"); 4999 if (BB->isSuccessor(PHI->getParent())) { 5000 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 5001 false)); 5002 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5003 } 5004 } 5005 5006 // If we generated any switch lowering information, build and codegen any 5007 // additional DAGs necessary. 5008 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 5009 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 5010 CurDAG = &SDAG; 5011 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI); 5012 5013 // Set the current basic block to the mbb we wish to insert the code into 5014 BB = SwitchCases[i].ThisBB; 5015 SDL.setCurrentBasicBlock(BB); 5016 5017 // Emit the code 5018 SDL.visitSwitchCase(SwitchCases[i]); 5019 SDAG.setRoot(SDL.getRoot()); 5020 CodeGenAndEmitDAG(SDAG); 5021 5022 // Handle any PHI nodes in successors of this chunk, as if we were coming 5023 // from the original BB before switch expansion. Note that PHI nodes can 5024 // occur multiple times in PHINodesToUpdate. We have to be very careful to 5025 // handle them the right number of times. 5026 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 5027 for (MachineBasicBlock::iterator Phi = BB->begin(); 5028 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 5029 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 5030 for (unsigned pn = 0; ; ++pn) { 5031 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 5032 if (PHINodesToUpdate[pn].first == Phi) { 5033 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn]. 5034 second, false)); 5035 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB)); 5036 break; 5037 } 5038 } 5039 } 5040 5041 // Don't process RHS if same block as LHS. 5042 if (BB == SwitchCases[i].FalseBB) 5043 SwitchCases[i].FalseBB = 0; 5044 5045 // If we haven't handled the RHS, do so now. Otherwise, we're done. 5046 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 5047 SwitchCases[i].FalseBB = 0; 5048 } 5049 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 5050 } 5051} 5052 5053 5054//===----------------------------------------------------------------------===// 5055/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 5056/// target node in the graph. 5057void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 5058 if (ViewSchedDAGs) DAG.viewGraph(); 5059 5060 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 5061 5062 if (!Ctor) { 5063 Ctor = ISHeuristic; 5064 RegisterScheduler::setDefault(Ctor); 5065 } 5066 5067 ScheduleDAG *SL = Ctor(this, &DAG, BB); 5068 BB = SL->Run(); 5069 5070 if (ViewSUnitDAGs) SL->viewGraph(); 5071 5072 delete SL; 5073} 5074 5075 5076HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 5077 return new HazardRecognizer(); 5078} 5079 5080//===----------------------------------------------------------------------===// 5081// Helper functions used by the generated instruction selector. 5082//===----------------------------------------------------------------------===// 5083// Calls to these methods are generated by tblgen. 5084 5085/// CheckAndMask - The isel is trying to match something like (and X, 255). If 5086/// the dag combiner simplified the 255, we still want to match. RHS is the 5087/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 5088/// specified in the .td file (e.g. 255). 5089bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 5090 int64_t DesiredMaskS) const { 5091 uint64_t ActualMask = RHS->getValue(); 5092 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 5093 5094 // If the actual mask exactly matches, success! 5095 if (ActualMask == DesiredMask) 5096 return true; 5097 5098 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5099 if (ActualMask & ~DesiredMask) 5100 return false; 5101 5102 // Otherwise, the DAG Combiner may have proven that the value coming in is 5103 // either already zero or is not demanded. Check for known zero input bits. 5104 uint64_t NeededMask = DesiredMask & ~ActualMask; 5105 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 5106 return true; 5107 5108 // TODO: check to see if missing bits are just not demanded. 5109 5110 // Otherwise, this pattern doesn't match. 5111 return false; 5112} 5113 5114/// CheckOrMask - The isel is trying to match something like (or X, 255). If 5115/// the dag combiner simplified the 255, we still want to match. RHS is the 5116/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 5117/// specified in the .td file (e.g. 255). 5118bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 5119 int64_t DesiredMaskS) const { 5120 uint64_t ActualMask = RHS->getValue(); 5121 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 5122 5123 // If the actual mask exactly matches, success! 5124 if (ActualMask == DesiredMask) 5125 return true; 5126 5127 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5128 if (ActualMask & ~DesiredMask) 5129 return false; 5130 5131 // Otherwise, the DAG Combiner may have proven that the value coming in is 5132 // either already zero or is not demanded. Check for known zero input bits. 5133 uint64_t NeededMask = DesiredMask & ~ActualMask; 5134 5135 uint64_t KnownZero, KnownOne; 5136 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 5137 5138 // If all the missing bits in the or are already known to be set, match! 5139 if ((NeededMask & KnownOne) == NeededMask) 5140 return true; 5141 5142 // TODO: check to see if missing bits are just not demanded. 5143 5144 // Otherwise, this pattern doesn't match. 5145 return false; 5146} 5147 5148 5149/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 5150/// by tblgen. Others should not call it. 5151void SelectionDAGISel:: 5152SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 5153 std::vector<SDOperand> InOps; 5154 std::swap(InOps, Ops); 5155 5156 Ops.push_back(InOps[0]); // input chain. 5157 Ops.push_back(InOps[1]); // input asm string. 5158 5159 unsigned i = 2, e = InOps.size(); 5160 if (InOps[e-1].getValueType() == MVT::Flag) 5161 --e; // Don't process a flag operand if it is here. 5162 5163 while (i != e) { 5164 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 5165 if ((Flags & 7) != 4 /*MEM*/) { 5166 // Just skip over this operand, copying the operands verbatim. 5167 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 5168 i += (Flags >> 3) + 1; 5169 } else { 5170 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 5171 // Otherwise, this is a memory operand. Ask the target to select it. 5172 std::vector<SDOperand> SelOps; 5173 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 5174 cerr << "Could not match memory address. Inline asm failure!\n"; 5175 exit(1); 5176 } 5177 5178 // Add this to the output node. 5179 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 5180 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 5181 IntPtrTy)); 5182 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 5183 i += 2; 5184 } 5185 } 5186 5187 // Add the flag input back if present. 5188 if (e != InOps.size()) 5189 Ops.push_back(InOps.back()); 5190} 5191 5192char SelectionDAGISel::ID = 0; 5193