SelectionDAGISel.cpp revision 021f3280fe791722c668cb96b02f473f2f76f925
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "ScheduleDAGSDNodes.h" 17#include "SelectionDAGBuilder.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/Statistic.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/BranchProbabilityInfo.h" 22#include "llvm/Analysis/CFG.h" 23#include "llvm/Analysis/TargetTransformInfo.h" 24#include "llvm/CodeGen/FastISel.h" 25#include "llvm/CodeGen/FunctionLoweringInfo.h" 26#include "llvm/CodeGen/GCMetadata.h" 27#include "llvm/CodeGen/GCStrategy.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineModuleInfo.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/DebugInfo.h" 37#include "llvm/IR/Constants.h" 38#include "llvm/IR/Function.h" 39#include "llvm/IR/InlineAsm.h" 40#include "llvm/IR/Instructions.h" 41#include "llvm/IR/IntrinsicInst.h" 42#include "llvm/IR/Intrinsics.h" 43#include "llvm/IR/LLVMContext.h" 44#include "llvm/IR/Module.h" 45#include "llvm/Support/Compiler.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/ErrorHandling.h" 48#include "llvm/Support/Timer.h" 49#include "llvm/Support/raw_ostream.h" 50#include "llvm/Target/TargetInstrInfo.h" 51#include "llvm/Target/TargetIntrinsicInfo.h" 52#include "llvm/Target/TargetLibraryInfo.h" 53#include "llvm/Target/TargetLowering.h" 54#include "llvm/Target/TargetMachine.h" 55#include "llvm/Target/TargetOptions.h" 56#include "llvm/Target/TargetRegisterInfo.h" 57#include "llvm/Target/TargetSubtargetInfo.h" 58#include "llvm/Transforms/Utils/BasicBlockUtils.h" 59#include <algorithm> 60using namespace llvm; 61 62STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 63STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 64STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 65STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 66STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 67STATISTIC(NumEntryBlocks, "Number of entry blocks encountered"); 68STATISTIC(NumFastIselFailLowerArguments, 69 "Number of entry blocks where fast isel failed to lower arguments"); 70 71#ifndef NDEBUG 72static cl::opt<bool> 73EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 74 cl::desc("Enable extra verbose messages in the \"fast\" " 75 "instruction selector")); 76 77 // Terminators 78STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 79STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 80STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 81STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 82STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 83STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 84STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 85 86 // Standard binary operators... 87STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 88STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 89STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 90STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 91STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 92STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 93STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 94STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 95STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 96STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 97STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 98STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 99 100 // Logical operators... 101STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 102STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 103STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 104 105 // Memory instructions... 106STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 107STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 108STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 109STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 110STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 111STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 112STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 113 114 // Convert instructions... 115STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 116STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 117STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 118STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 119STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 120STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 121STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 122STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 123STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 124STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 125STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 126STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 127 128 // Other instructions... 129STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 130STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 131STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 132STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 133STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 134STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 135STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 136STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 137STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 138STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 139STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 140STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 141STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 142STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 143STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 144#endif 145 146static cl::opt<bool> 147EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 148 cl::desc("Enable verbose messages in the \"fast\" " 149 "instruction selector")); 150static cl::opt<bool> 151EnableFastISelAbort("fast-isel-abort", cl::Hidden, 152 cl::desc("Enable abort calls when \"fast\" instruction selection " 153 "fails to lower an instruction")); 154static cl::opt<bool> 155EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden, 156 cl::desc("Enable abort calls when \"fast\" instruction selection " 157 "fails to lower a formal argument")); 158 159static cl::opt<bool> 160UseMBPI("use-mbpi", 161 cl::desc("use Machine Branch Probability Info"), 162 cl::init(true), cl::Hidden); 163 164#ifndef NDEBUG 165static cl::opt<bool> 166ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 167 cl::desc("Pop up a window to show dags before the first " 168 "dag combine pass")); 169static cl::opt<bool> 170ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 171 cl::desc("Pop up a window to show dags before legalize types")); 172static cl::opt<bool> 173ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 174 cl::desc("Pop up a window to show dags before legalize")); 175static cl::opt<bool> 176ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 177 cl::desc("Pop up a window to show dags before the second " 178 "dag combine pass")); 179static cl::opt<bool> 180ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 181 cl::desc("Pop up a window to show dags before the post legalize types" 182 " dag combine pass")); 183static cl::opt<bool> 184ViewISelDAGs("view-isel-dags", cl::Hidden, 185 cl::desc("Pop up a window to show isel dags as they are selected")); 186static cl::opt<bool> 187ViewSchedDAGs("view-sched-dags", cl::Hidden, 188 cl::desc("Pop up a window to show sched dags as they are processed")); 189static cl::opt<bool> 190ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 191 cl::desc("Pop up a window to show SUnit dags after they are processed")); 192#else 193static const bool ViewDAGCombine1 = false, 194 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 195 ViewDAGCombine2 = false, 196 ViewDAGCombineLT = false, 197 ViewISelDAGs = false, ViewSchedDAGs = false, 198 ViewSUnitDAGs = false; 199#endif 200 201//===---------------------------------------------------------------------===// 202/// 203/// RegisterScheduler class - Track the registration of instruction schedulers. 204/// 205//===---------------------------------------------------------------------===// 206MachinePassRegistry RegisterScheduler::Registry; 207 208//===---------------------------------------------------------------------===// 209/// 210/// ISHeuristic command line option for instruction schedulers. 211/// 212//===---------------------------------------------------------------------===// 213static cl::opt<RegisterScheduler::FunctionPassCtor, false, 214 RegisterPassParser<RegisterScheduler> > 215ISHeuristic("pre-RA-sched", 216 cl::init(&createDefaultScheduler), 217 cl::desc("Instruction schedulers available (before register" 218 " allocation):")); 219 220static RegisterScheduler 221defaultListDAGScheduler("default", "Best scheduler for the target", 222 createDefaultScheduler); 223 224namespace llvm { 225 //===--------------------------------------------------------------------===// 226 /// createDefaultScheduler - This creates an instruction scheduler appropriate 227 /// for the target. 228 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 229 CodeGenOpt::Level OptLevel) { 230 const TargetLowering *TLI = IS->getTargetLowering(); 231 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 232 233 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() || 234 TLI->getSchedulingPreference() == Sched::Source) 235 return createSourceListDAGScheduler(IS, OptLevel); 236 if (TLI->getSchedulingPreference() == Sched::RegPressure) 237 return createBURRListDAGScheduler(IS, OptLevel); 238 if (TLI->getSchedulingPreference() == Sched::Hybrid) 239 return createHybridListDAGScheduler(IS, OptLevel); 240 if (TLI->getSchedulingPreference() == Sched::VLIW) 241 return createVLIWDAGScheduler(IS, OptLevel); 242 assert(TLI->getSchedulingPreference() == Sched::ILP && 243 "Unknown sched type!"); 244 return createILPListDAGScheduler(IS, OptLevel); 245 } 246} 247 248// EmitInstrWithCustomInserter - This method should be implemented by targets 249// that mark instructions with the 'usesCustomInserter' flag. These 250// instructions are special in various ways, which require special support to 251// insert. The specified MachineInstr is created but not inserted into any 252// basic blocks, and this method is called to expand it into a sequence of 253// instructions, potentially also creating new basic blocks and control flow. 254// When new basic blocks are inserted and the edges from MBB to its successors 255// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 256// DenseMap. 257MachineBasicBlock * 258TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 259 MachineBasicBlock *MBB) const { 260#ifndef NDEBUG 261 dbgs() << "If a target marks an instruction with " 262 "'usesCustomInserter', it must implement " 263 "TargetLowering::EmitInstrWithCustomInserter!"; 264#endif 265 llvm_unreachable(0); 266} 267 268void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 269 SDNode *Node) const { 270 assert(!MI->hasPostISelHook() && 271 "If a target marks an instruction with 'hasPostISelHook', " 272 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 273} 274 275//===----------------------------------------------------------------------===// 276// SelectionDAGISel code 277//===----------------------------------------------------------------------===// 278 279SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, 280 CodeGenOpt::Level OL) : 281 MachineFunctionPass(ID), TM(tm), 282 FuncInfo(new FunctionLoweringInfo(TM)), 283 CurDAG(new SelectionDAG(tm, OL)), 284 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 285 GFI(), 286 OptLevel(OL), 287 DAGSize(0) { 288 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 289 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 290 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 291 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 292 } 293 294SelectionDAGISel::~SelectionDAGISel() { 295 delete SDB; 296 delete CurDAG; 297 delete FuncInfo; 298} 299 300void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 301 AU.addRequired<AliasAnalysis>(); 302 AU.addPreserved<AliasAnalysis>(); 303 AU.addRequired<GCModuleInfo>(); 304 AU.addPreserved<GCModuleInfo>(); 305 AU.addRequired<TargetLibraryInfo>(); 306 if (UseMBPI && OptLevel != CodeGenOpt::None) 307 AU.addRequired<BranchProbabilityInfo>(); 308 MachineFunctionPass::getAnalysisUsage(AU); 309} 310 311/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 312/// may trap on it. In this case we have to split the edge so that the path 313/// through the predecessor block that doesn't go to the phi block doesn't 314/// execute the possibly trapping instruction. 315/// 316/// This is required for correctness, so it must be done at -O0. 317/// 318static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 319 // Loop for blocks with phi nodes. 320 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 321 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 322 if (PN == 0) continue; 323 324 ReprocessBlock: 325 // For each block with a PHI node, check to see if any of the input values 326 // are potentially trapping constant expressions. Constant expressions are 327 // the only potentially trapping value that can occur as the argument to a 328 // PHI. 329 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 330 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 331 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 332 if (CE == 0 || !CE->canTrap()) continue; 333 334 // The only case we have to worry about is when the edge is critical. 335 // Since this block has a PHI Node, we assume it has multiple input 336 // edges: check to see if the pred has multiple successors. 337 BasicBlock *Pred = PN->getIncomingBlock(i); 338 if (Pred->getTerminator()->getNumSuccessors() == 1) 339 continue; 340 341 // Okay, we have to split this edge. 342 SplitCriticalEdge(Pred->getTerminator(), 343 GetSuccessorNumber(Pred, BB), SDISel, true); 344 goto ReprocessBlock; 345 } 346 } 347} 348 349bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 350 // Do some sanity-checking on the command-line options. 351 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 352 "-fast-isel-verbose requires -fast-isel"); 353 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 354 "-fast-isel-abort requires -fast-isel"); 355 356 const Function &Fn = *mf.getFunction(); 357 const TargetInstrInfo &TII = *TM.getInstrInfo(); 358 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 359 360 MF = &mf; 361 RegInfo = &MF->getRegInfo(); 362 AA = &getAnalysis<AliasAnalysis>(); 363 LibInfo = &getAnalysis<TargetLibraryInfo>(); 364 TTI = getAnalysisIfAvailable<TargetTransformInfo>(); 365 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 366 367 TargetSubtargetInfo &ST = 368 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 369 ST.resetSubtargetFeatures(MF); 370 TM.resetTargetOptions(MF); 371 372 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 373 374 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 375 376 CurDAG->init(*MF, TTI); 377 FuncInfo->set(Fn, *MF); 378 379 if (UseMBPI && OptLevel != CodeGenOpt::None) 380 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 381 else 382 FuncInfo->BPI = 0; 383 384 SDB->init(GFI, *AA, LibInfo); 385 386 MF->setHasMSInlineAsm(false); 387 SelectAllBasicBlocks(Fn); 388 389 // If the first basic block in the function has live ins that need to be 390 // copied into vregs, emit the copies into the top of the block before 391 // emitting the code for the block. 392 MachineBasicBlock *EntryMBB = MF->begin(); 393 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 394 395 DenseMap<unsigned, unsigned> LiveInMap; 396 if (!FuncInfo->ArgDbgValues.empty()) 397 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 398 E = RegInfo->livein_end(); LI != E; ++LI) 399 if (LI->second) 400 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 401 402 // Insert DBG_VALUE instructions for function arguments to the entry block. 403 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 404 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 405 bool hasFI = MI->getOperand(0).isFI(); 406 unsigned Reg = hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg(); 407 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 408 EntryMBB->insert(EntryMBB->begin(), MI); 409 else { 410 MachineInstr *Def = RegInfo->getVRegDef(Reg); 411 MachineBasicBlock::iterator InsertPos = Def; 412 // FIXME: VR def may not be in entry block. 413 Def->getParent()->insert(llvm::next(InsertPos), MI); 414 } 415 416 // If Reg is live-in then update debug info to track its copy in a vreg. 417 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 418 if (LDI != LiveInMap.end()) { 419 assert(!hasFI && "There's no handling of frame pointer updating here yet " 420 "- add if needed"); 421 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 422 MachineBasicBlock::iterator InsertPos = Def; 423 const MDNode *Variable = 424 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 425 bool IsIndirect = MI->getOperand(1).isImm(); 426 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; 427 // Def is never a terminator here, so it is ok to increment InsertPos. 428 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 429 TII.get(TargetOpcode::DBG_VALUE), 430 IsIndirect, 431 LDI->second, Offset, Variable); 432 433 // If this vreg is directly copied into an exported register then 434 // that COPY instructions also need DBG_VALUE, if it is the only 435 // user of LDI->second. 436 MachineInstr *CopyUseMI = NULL; 437 for (MachineRegisterInfo::use_iterator 438 UI = RegInfo->use_begin(LDI->second); 439 MachineInstr *UseMI = UI.skipInstruction();) { 440 if (UseMI->isDebugValue()) continue; 441 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 442 CopyUseMI = UseMI; continue; 443 } 444 // Otherwise this is another use or second copy use. 445 CopyUseMI = NULL; break; 446 } 447 if (CopyUseMI) { 448 MachineInstr *NewMI = 449 BuildMI(*MF, CopyUseMI->getDebugLoc(), 450 TII.get(TargetOpcode::DBG_VALUE), 451 IsIndirect, 452 CopyUseMI->getOperand(0).getReg(), 453 Offset, Variable); 454 MachineBasicBlock::iterator Pos = CopyUseMI; 455 EntryMBB->insertAfter(Pos, NewMI); 456 } 457 } 458 } 459 460 // Determine if there are any calls in this machine function. 461 MachineFrameInfo *MFI = MF->getFrameInfo(); 462 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E; 463 ++I) { 464 465 if (MFI->hasCalls() && MF->hasMSInlineAsm()) 466 break; 467 468 const MachineBasicBlock *MBB = I; 469 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end(); 470 II != IE; ++II) { 471 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 472 if ((MCID.isCall() && !MCID.isReturn()) || 473 II->isStackAligningInlineAsm()) { 474 MFI->setHasCalls(true); 475 } 476 if (II->isMSInlineAsm()) { 477 MF->setHasMSInlineAsm(true); 478 } 479 } 480 } 481 482 // Determine if there is a call to setjmp in the machine function. 483 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 484 485 // Replace forward-declared registers with the registers containing 486 // the desired value. 487 MachineRegisterInfo &MRI = MF->getRegInfo(); 488 for (DenseMap<unsigned, unsigned>::iterator 489 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 490 I != E; ++I) { 491 unsigned From = I->first; 492 unsigned To = I->second; 493 // If To is also scheduled to be replaced, find what its ultimate 494 // replacement is. 495 for (;;) { 496 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 497 if (J == E) break; 498 To = J->second; 499 } 500 // Make sure the new register has a sufficiently constrained register class. 501 if (TargetRegisterInfo::isVirtualRegister(From) && 502 TargetRegisterInfo::isVirtualRegister(To)) 503 MRI.constrainRegClass(To, MRI.getRegClass(From)); 504 // Replace it. 505 MRI.replaceRegWith(From, To); 506 } 507 508 // Freeze the set of reserved registers now that MachineFrameInfo has been 509 // set up. All the information required by getReservedRegs() should be 510 // available now. 511 MRI.freezeReservedRegs(*MF); 512 513 // Release function-specific state. SDB and CurDAG are already cleared 514 // at this point. 515 FuncInfo->clear(); 516 517 return true; 518} 519 520void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 521 BasicBlock::const_iterator End, 522 bool &HadTailCall) { 523 // Lower all of the non-terminator instructions. If a call is emitted 524 // as a tail call, cease emitting nodes for this block. Terminators 525 // are handled below. 526 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 527 SDB->visit(*I); 528 529 // Make sure the root of the DAG is up-to-date. 530 CurDAG->setRoot(SDB->getControlRoot()); 531 HadTailCall = SDB->HasTailCall; 532 SDB->clear(); 533 534 // Final step, emit the lowered DAG as machine code. 535 CodeGenAndEmitDAG(); 536} 537 538void SelectionDAGISel::ComputeLiveOutVRegInfo() { 539 SmallPtrSet<SDNode*, 128> VisitedNodes; 540 SmallVector<SDNode*, 128> Worklist; 541 542 Worklist.push_back(CurDAG->getRoot().getNode()); 543 544 APInt KnownZero; 545 APInt KnownOne; 546 547 do { 548 SDNode *N = Worklist.pop_back_val(); 549 550 // If we've already seen this node, ignore it. 551 if (!VisitedNodes.insert(N)) 552 continue; 553 554 // Otherwise, add all chain operands to the worklist. 555 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 556 if (N->getOperand(i).getValueType() == MVT::Other) 557 Worklist.push_back(N->getOperand(i).getNode()); 558 559 // If this is a CopyToReg with a vreg dest, process it. 560 if (N->getOpcode() != ISD::CopyToReg) 561 continue; 562 563 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 564 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 565 continue; 566 567 // Ignore non-scalar or non-integer values. 568 SDValue Src = N->getOperand(2); 569 EVT SrcVT = Src.getValueType(); 570 if (!SrcVT.isInteger() || SrcVT.isVector()) 571 continue; 572 573 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 574 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 575 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 576 } while (!Worklist.empty()); 577} 578 579void SelectionDAGISel::CodeGenAndEmitDAG() { 580 std::string GroupName; 581 if (TimePassesIsEnabled) 582 GroupName = "Instruction Selection and Scheduling"; 583 std::string BlockName; 584 int BlockNumber = -1; 585 (void)BlockNumber; 586#ifdef NDEBUG 587 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 588 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 589 ViewSUnitDAGs) 590#endif 591 { 592 BlockNumber = FuncInfo->MBB->getNumber(); 593 BlockName = MF->getName().str() + ":" + 594 FuncInfo->MBB->getBasicBlock()->getName().str(); 595 } 596 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 597 << " '" << BlockName << "'\n"; CurDAG->dump()); 598 599 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 600 601 // Run the DAG combiner in pre-legalize mode. 602 { 603 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 604 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 605 } 606 607 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 608 << " '" << BlockName << "'\n"; CurDAG->dump()); 609 610 // Second step, hack on the DAG until it only uses operations and types that 611 // the target supports. 612 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 613 BlockName); 614 615 bool Changed; 616 { 617 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 618 Changed = CurDAG->LegalizeTypes(); 619 } 620 621 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 622 << " '" << BlockName << "'\n"; CurDAG->dump()); 623 624 if (Changed) { 625 if (ViewDAGCombineLT) 626 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 627 628 // Run the DAG combiner in post-type-legalize mode. 629 { 630 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 631 TimePassesIsEnabled); 632 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 633 } 634 635 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 636 << " '" << BlockName << "'\n"; CurDAG->dump()); 637 638 } 639 640 { 641 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 642 Changed = CurDAG->LegalizeVectors(); 643 } 644 645 if (Changed) { 646 { 647 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 648 CurDAG->LegalizeTypes(); 649 } 650 651 if (ViewDAGCombineLT) 652 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 653 654 // Run the DAG combiner in post-type-legalize mode. 655 { 656 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 657 TimePassesIsEnabled); 658 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 659 } 660 661 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 662 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 663 } 664 665 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 666 667 { 668 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 669 CurDAG->Legalize(); 670 } 671 672 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 673 << " '" << BlockName << "'\n"; CurDAG->dump()); 674 675 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 676 677 // Run the DAG combiner in post-legalize mode. 678 { 679 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 680 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 681 } 682 683 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 684 << " '" << BlockName << "'\n"; CurDAG->dump()); 685 686 if (OptLevel != CodeGenOpt::None) 687 ComputeLiveOutVRegInfo(); 688 689 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 690 691 // Third, instruction select all of the operations to machine code, adding the 692 // code to the MachineBasicBlock. 693 { 694 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 695 DoInstructionSelection(); 696 } 697 698 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 699 << " '" << BlockName << "'\n"; CurDAG->dump()); 700 701 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 702 703 // Schedule machine code. 704 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 705 { 706 NamedRegionTimer T("Instruction Scheduling", GroupName, 707 TimePassesIsEnabled); 708 Scheduler->Run(CurDAG, FuncInfo->MBB); 709 } 710 711 if (ViewSUnitDAGs) Scheduler->viewGraph(); 712 713 // Emit machine code to BB. This can change 'BB' to the last block being 714 // inserted into. 715 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 716 { 717 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 718 719 // FuncInfo->InsertPt is passed by reference and set to the end of the 720 // scheduled instructions. 721 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 722 } 723 724 // If the block was split, make sure we update any references that are used to 725 // update PHI nodes later on. 726 if (FirstMBB != LastMBB) 727 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 728 729 // Free the scheduler state. 730 { 731 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 732 TimePassesIsEnabled); 733 delete Scheduler; 734 } 735 736 // Free the SelectionDAG state, now that we're finished with it. 737 CurDAG->clear(); 738} 739 740namespace { 741/// ISelUpdater - helper class to handle updates of the instruction selection 742/// graph. 743class ISelUpdater : public SelectionDAG::DAGUpdateListener { 744 SelectionDAG::allnodes_iterator &ISelPosition; 745public: 746 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 747 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 748 749 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 750 /// deleted is the current ISelPosition node, update ISelPosition. 751 /// 752 virtual void NodeDeleted(SDNode *N, SDNode *E) { 753 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 754 ++ISelPosition; 755 } 756}; 757} // end anonymous namespace 758 759void SelectionDAGISel::DoInstructionSelection() { 760 DEBUG(dbgs() << "===== Instruction selection begins: BB#" 761 << FuncInfo->MBB->getNumber() 762 << " '" << FuncInfo->MBB->getName() << "'\n"); 763 764 PreprocessISelDAG(); 765 766 // Select target instructions for the DAG. 767 { 768 // Number all nodes with a topological order and set DAGSize. 769 DAGSize = CurDAG->AssignTopologicalOrder(); 770 771 // Create a dummy node (which is not added to allnodes), that adds 772 // a reference to the root node, preventing it from being deleted, 773 // and tracking any changes of the root. 774 HandleSDNode Dummy(CurDAG->getRoot()); 775 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 776 ++ISelPosition; 777 778 // Make sure that ISelPosition gets properly updated when nodes are deleted 779 // in calls made from this function. 780 ISelUpdater ISU(*CurDAG, ISelPosition); 781 782 // The AllNodes list is now topological-sorted. Visit the 783 // nodes by starting at the end of the list (the root of the 784 // graph) and preceding back toward the beginning (the entry 785 // node). 786 while (ISelPosition != CurDAG->allnodes_begin()) { 787 SDNode *Node = --ISelPosition; 788 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 789 // but there are currently some corner cases that it misses. Also, this 790 // makes it theoretically possible to disable the DAGCombiner. 791 if (Node->use_empty()) 792 continue; 793 794 SDNode *ResNode = Select(Node); 795 796 // FIXME: This is pretty gross. 'Select' should be changed to not return 797 // anything at all and this code should be nuked with a tactical strike. 798 799 // If node should not be replaced, continue with the next one. 800 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 801 continue; 802 // Replace node. 803 if (ResNode) { 804 ReplaceUses(Node, ResNode); 805 } 806 807 // If after the replacement this node is not used any more, 808 // remove this dead node. 809 if (Node->use_empty()) // Don't delete EntryToken, etc. 810 CurDAG->RemoveDeadNode(Node); 811 } 812 813 CurDAG->setRoot(Dummy.getValue()); 814 } 815 816 DEBUG(dbgs() << "===== Instruction selection ends:\n"); 817 818 PostprocessISelDAG(); 819} 820 821/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 822/// do other setup for EH landing-pad blocks. 823void SelectionDAGISel::PrepareEHLandingPad() { 824 MachineBasicBlock *MBB = FuncInfo->MBB; 825 826 // Add a label to mark the beginning of the landing pad. Deletion of the 827 // landing pad can thus be detected via the MachineModuleInfo. 828 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 829 830 // Assign the call site to the landing pad's begin label. 831 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 832 833 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 834 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 835 .addSym(Label); 836 837 // Mark exception register as live in. 838 const TargetLowering *TLI = getTargetLowering(); 839 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy()); 840 if (unsigned Reg = TLI->getExceptionPointerRegister()) 841 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC); 842 843 // Mark exception selector register as live in. 844 if (unsigned Reg = TLI->getExceptionSelectorRegister()) 845 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC); 846} 847 848/// isFoldedOrDeadInstruction - Return true if the specified instruction is 849/// side-effect free and is either dead or folded into a generated instruction. 850/// Return false if it needs to be emitted. 851static bool isFoldedOrDeadInstruction(const Instruction *I, 852 FunctionLoweringInfo *FuncInfo) { 853 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 854 !isa<TerminatorInst>(I) && // Terminators aren't folded. 855 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 856 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 857 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 858} 859 860#ifndef NDEBUG 861// Collect per Instruction statistics for fast-isel misses. Only those 862// instructions that cause the bail are accounted for. It does not account for 863// instructions higher in the block. Thus, summing the per instructions stats 864// will not add up to what is reported by NumFastIselFailures. 865static void collectFailStats(const Instruction *I) { 866 switch (I->getOpcode()) { 867 default: assert (0 && "<Invalid operator> "); 868 869 // Terminators 870 case Instruction::Ret: NumFastIselFailRet++; return; 871 case Instruction::Br: NumFastIselFailBr++; return; 872 case Instruction::Switch: NumFastIselFailSwitch++; return; 873 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 874 case Instruction::Invoke: NumFastIselFailInvoke++; return; 875 case Instruction::Resume: NumFastIselFailResume++; return; 876 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 877 878 // Standard binary operators... 879 case Instruction::Add: NumFastIselFailAdd++; return; 880 case Instruction::FAdd: NumFastIselFailFAdd++; return; 881 case Instruction::Sub: NumFastIselFailSub++; return; 882 case Instruction::FSub: NumFastIselFailFSub++; return; 883 case Instruction::Mul: NumFastIselFailMul++; return; 884 case Instruction::FMul: NumFastIselFailFMul++; return; 885 case Instruction::UDiv: NumFastIselFailUDiv++; return; 886 case Instruction::SDiv: NumFastIselFailSDiv++; return; 887 case Instruction::FDiv: NumFastIselFailFDiv++; return; 888 case Instruction::URem: NumFastIselFailURem++; return; 889 case Instruction::SRem: NumFastIselFailSRem++; return; 890 case Instruction::FRem: NumFastIselFailFRem++; return; 891 892 // Logical operators... 893 case Instruction::And: NumFastIselFailAnd++; return; 894 case Instruction::Or: NumFastIselFailOr++; return; 895 case Instruction::Xor: NumFastIselFailXor++; return; 896 897 // Memory instructions... 898 case Instruction::Alloca: NumFastIselFailAlloca++; return; 899 case Instruction::Load: NumFastIselFailLoad++; return; 900 case Instruction::Store: NumFastIselFailStore++; return; 901 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 902 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 903 case Instruction::Fence: NumFastIselFailFence++; return; 904 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 905 906 // Convert instructions... 907 case Instruction::Trunc: NumFastIselFailTrunc++; return; 908 case Instruction::ZExt: NumFastIselFailZExt++; return; 909 case Instruction::SExt: NumFastIselFailSExt++; return; 910 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 911 case Instruction::FPExt: NumFastIselFailFPExt++; return; 912 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 913 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 914 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 915 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 916 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 917 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 918 case Instruction::BitCast: NumFastIselFailBitCast++; return; 919 920 // Other instructions... 921 case Instruction::ICmp: NumFastIselFailICmp++; return; 922 case Instruction::FCmp: NumFastIselFailFCmp++; return; 923 case Instruction::PHI: NumFastIselFailPHI++; return; 924 case Instruction::Select: NumFastIselFailSelect++; return; 925 case Instruction::Call: NumFastIselFailCall++; return; 926 case Instruction::Shl: NumFastIselFailShl++; return; 927 case Instruction::LShr: NumFastIselFailLShr++; return; 928 case Instruction::AShr: NumFastIselFailAShr++; return; 929 case Instruction::VAArg: NumFastIselFailVAArg++; return; 930 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 931 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 932 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 933 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 934 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 935 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 936 } 937} 938#endif 939 940void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 941 // Initialize the Fast-ISel state, if needed. 942 FastISel *FastIS = 0; 943 if (TM.Options.EnableFastISel) 944 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo); 945 946 // Iterate over all basic blocks in the function. 947 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 948 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 949 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 950 const BasicBlock *LLVMBB = *I; 951 952 if (OptLevel != CodeGenOpt::None) { 953 bool AllPredsVisited = true; 954 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 955 PI != PE; ++PI) { 956 if (!FuncInfo->VisitedBBs.count(*PI)) { 957 AllPredsVisited = false; 958 break; 959 } 960 } 961 962 if (AllPredsVisited) { 963 for (BasicBlock::const_iterator I = LLVMBB->begin(); 964 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 965 FuncInfo->ComputePHILiveOutRegInfo(PN); 966 } else { 967 for (BasicBlock::const_iterator I = LLVMBB->begin(); 968 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 969 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 970 } 971 972 FuncInfo->VisitedBBs.insert(LLVMBB); 973 } 974 975 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 976 BasicBlock::const_iterator const End = LLVMBB->end(); 977 BasicBlock::const_iterator BI = End; 978 979 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 980 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 981 982 // Setup an EH landing-pad block. 983 FuncInfo->ExceptionPointerVirtReg = 0; 984 FuncInfo->ExceptionSelectorVirtReg = 0; 985 if (FuncInfo->MBB->isLandingPad()) 986 PrepareEHLandingPad(); 987 988 // Before doing SelectionDAG ISel, see if FastISel has been requested. 989 if (FastIS) { 990 FastIS->startNewBlock(); 991 992 // Emit code for any incoming arguments. This must happen before 993 // beginning FastISel on the entry block. 994 if (LLVMBB == &Fn.getEntryBlock()) { 995 ++NumEntryBlocks; 996 997 // Lower any arguments needed in this block if this is the entry block. 998 if (!FastIS->LowerArguments()) { 999 // Fast isel failed to lower these arguments 1000 ++NumFastIselFailLowerArguments; 1001 if (EnableFastISelAbortArgs) 1002 llvm_unreachable("FastISel didn't lower all arguments"); 1003 1004 // Use SelectionDAG argument lowering 1005 LowerArguments(Fn); 1006 CurDAG->setRoot(SDB->getControlRoot()); 1007 SDB->clear(); 1008 CodeGenAndEmitDAG(); 1009 } 1010 1011 // If we inserted any instructions at the beginning, make a note of 1012 // where they are, so we can be sure to emit subsequent instructions 1013 // after them. 1014 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1015 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 1016 else 1017 FastIS->setLastLocalValue(0); 1018 } 1019 1020 unsigned NumFastIselRemaining = std::distance(Begin, End); 1021 // Do FastISel on as many instructions as possible. 1022 for (; BI != Begin; --BI) { 1023 const Instruction *Inst = llvm::prior(BI); 1024 1025 // If we no longer require this instruction, skip it. 1026 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1027 --NumFastIselRemaining; 1028 continue; 1029 } 1030 1031 // Bottom-up: reset the insert pos at the top, after any local-value 1032 // instructions. 1033 FastIS->recomputeInsertPt(); 1034 1035 // Try to select the instruction with FastISel. 1036 if (FastIS->SelectInstruction(Inst)) { 1037 --NumFastIselRemaining; 1038 ++NumFastIselSuccess; 1039 // If fast isel succeeded, skip over all the folded instructions, and 1040 // then see if there is a load right before the selected instructions. 1041 // Try to fold the load if so. 1042 const Instruction *BeforeInst = Inst; 1043 while (BeforeInst != Begin) { 1044 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 1045 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1046 break; 1047 } 1048 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1049 BeforeInst->hasOneUse() && 1050 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) { 1051 // If we succeeded, don't re-select the load. 1052 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 1053 --NumFastIselRemaining; 1054 ++NumFastIselSuccess; 1055 } 1056 continue; 1057 } 1058 1059#ifndef NDEBUG 1060 if (EnableFastISelVerbose2) 1061 collectFailStats(Inst); 1062#endif 1063 1064 // Then handle certain instructions as single-LLVM-Instruction blocks. 1065 if (isa<CallInst>(Inst)) { 1066 1067 if (EnableFastISelVerbose || EnableFastISelAbort) { 1068 dbgs() << "FastISel missed call: "; 1069 Inst->dump(); 1070 } 1071 1072 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1073 unsigned &R = FuncInfo->ValueMap[Inst]; 1074 if (!R) 1075 R = FuncInfo->CreateRegs(Inst->getType()); 1076 } 1077 1078 bool HadTailCall = false; 1079 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1080 SelectBasicBlock(Inst, BI, HadTailCall); 1081 1082 // If the call was emitted as a tail call, we're done with the block. 1083 // We also need to delete any previously emitted instructions. 1084 if (HadTailCall) { 1085 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1086 --BI; 1087 break; 1088 } 1089 1090 // Recompute NumFastIselRemaining as Selection DAG instruction 1091 // selection may have handled the call, input args, etc. 1092 unsigned RemainingNow = std::distance(Begin, BI); 1093 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1094 NumFastIselRemaining = RemainingNow; 1095 continue; 1096 } 1097 1098 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1099 // Don't abort, and use a different message for terminator misses. 1100 NumFastIselFailures += NumFastIselRemaining; 1101 if (EnableFastISelVerbose || EnableFastISelAbort) { 1102 dbgs() << "FastISel missed terminator: "; 1103 Inst->dump(); 1104 } 1105 } else { 1106 NumFastIselFailures += NumFastIselRemaining; 1107 if (EnableFastISelVerbose || EnableFastISelAbort) { 1108 dbgs() << "FastISel miss: "; 1109 Inst->dump(); 1110 } 1111 if (EnableFastISelAbort) 1112 // The "fast" selector couldn't handle something and bailed. 1113 // For the purpose of debugging, just abort. 1114 llvm_unreachable("FastISel didn't select the entire block"); 1115 } 1116 break; 1117 } 1118 1119 FastIS->recomputeInsertPt(); 1120 } else { 1121 // Lower any arguments needed in this block if this is the entry block. 1122 if (LLVMBB == &Fn.getEntryBlock()) { 1123 ++NumEntryBlocks; 1124 LowerArguments(Fn); 1125 } 1126 } 1127 1128 if (Begin != BI) 1129 ++NumDAGBlocks; 1130 else 1131 ++NumFastIselBlocks; 1132 1133 if (Begin != BI) { 1134 // Run SelectionDAG instruction selection on the remainder of the block 1135 // not handled by FastISel. If FastISel is not run, this is the entire 1136 // block. 1137 bool HadTailCall; 1138 SelectBasicBlock(Begin, BI, HadTailCall); 1139 } 1140 1141 FinishBasicBlock(); 1142 FuncInfo->PHINodesToUpdate.clear(); 1143 } 1144 1145 delete FastIS; 1146 SDB->clearDanglingDebugInfo(); 1147 SDB->SPDescriptor.resetPerFunctionState(); 1148} 1149 1150/// Given that the input MI is before a partial terminator sequence TSeq, return 1151/// true if M + TSeq also a partial terminator sequence. 1152/// 1153/// A Terminator sequence is a sequence of MachineInstrs which at this point in 1154/// lowering copy vregs into physical registers, which are then passed into 1155/// terminator instructors so we can satisfy ABI constraints. A partial 1156/// terminator sequence is an improper subset of a terminator sequence (i.e. it 1157/// may be the whole terminator sequence). 1158static bool MIIsInTerminatorSequence(const MachineInstr *MI) { 1159 // If we do not have a copy or an implicit def, we return true if and only if 1160 // MI is a debug value. 1161 if (!MI->isCopy() && !MI->isImplicitDef()) 1162 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the 1163 // physical registers if there is debug info associated with the terminator 1164 // of our mbb. We want to include said debug info in our terminator 1165 // sequence, so we return true in that case. 1166 return MI->isDebugValue(); 1167 1168 // If we are not defining a register that is a physical register via a copy or 1169 // are defining a register via an implicit def, we have left the terminator 1170 // sequence. 1171 MachineInstr::const_mop_iterator OPI = MI->operands_begin(); 1172 if (!OPI->isReg() || !OPI->isDef() || 1173 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) && 1174 !MI->isImplicitDef())) 1175 return false; 1176 1177 return true; 1178} 1179 1180/// Find the split point at which to splice the end of BB into its success stack 1181/// protector check machine basic block. 1182/// 1183/// On many platforms, due to ABI constraints, terminators, even before register 1184/// allocation, use physical registers. This creates an issue for us since 1185/// physical registers at this point can not travel across basic 1186/// blocks. Luckily, selectiondag always moves physical registers into vregs 1187/// when they enter functions and moves them through a sequence of copies back 1188/// into the physical registers right before the terminator creating a 1189/// ``Terminator Sequence''. This function is searching for the beginning of the 1190/// terminator sequence so that we can ensure that we splice off not just the 1191/// terminator, but additionally the copies that move the vregs into the 1192/// physical registers. 1193static MachineBasicBlock::iterator 1194FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) { 1195 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator(); 1196 // 1197 if (SplitPoint == BB->begin()) 1198 return SplitPoint; 1199 1200 MachineBasicBlock::iterator Start = BB->begin(); 1201 MachineBasicBlock::iterator Previous = SplitPoint; 1202 --Previous; 1203 1204 while (MIIsInTerminatorSequence(Previous)) { 1205 SplitPoint = Previous; 1206 if (Previous == Start) 1207 break; 1208 --Previous; 1209 } 1210 1211 return SplitPoint; 1212} 1213 1214void 1215SelectionDAGISel::FinishBasicBlock() { 1216 1217 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1218 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1219 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1220 dbgs() << "Node " << i << " : (" 1221 << FuncInfo->PHINodesToUpdate[i].first 1222 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1223 1224 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() && 1225 SDB->JTCases.empty() && 1226 SDB->BitTestCases.empty(); 1227 1228 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1229 // PHI nodes in successors. 1230 if (MustUpdatePHINodes) { 1231 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1232 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1233 assert(PHI->isPHI() && 1234 "This is not a machine PHI node that we are updating!"); 1235 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1236 continue; 1237 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1238 } 1239 } 1240 1241 // Handle stack protector. 1242 if (SDB->SPDescriptor.shouldEmitStackProtector()) { 1243 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB(); 1244 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB(); 1245 1246 // Find the split point to split the parent mbb. At the same time copy all 1247 // physical registers used in the tail of parent mbb into virtual registers 1248 // before the split point and back into physical registers after the split 1249 // point. This prevents us needing to deal with Live-ins and many other 1250 // register allocation issues caused by us splitting the parent mbb. The 1251 // register allocator will clean up said virtual copies later on. 1252 MachineBasicBlock::iterator SplitPoint = 1253 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc()); 1254 1255 // Splice the terminator of ParentMBB into SuccessMBB. 1256 SuccessMBB->splice(SuccessMBB->end(), ParentMBB, 1257 SplitPoint, 1258 ParentMBB->end()); 1259 1260 // Add compare/jump on neq/jump to the parent BB. 1261 FuncInfo->MBB = ParentMBB; 1262 FuncInfo->InsertPt = ParentMBB->end(); 1263 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB); 1264 CurDAG->setRoot(SDB->getRoot()); 1265 SDB->clear(); 1266 CodeGenAndEmitDAG(); 1267 1268 // CodeGen Failure MBB if we have not codegened it yet. 1269 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB(); 1270 if (!FailureMBB->size()) { 1271 FuncInfo->MBB = FailureMBB; 1272 FuncInfo->InsertPt = FailureMBB->end(); 1273 SDB->visitSPDescriptorFailure(SDB->SPDescriptor); 1274 CurDAG->setRoot(SDB->getRoot()); 1275 SDB->clear(); 1276 CodeGenAndEmitDAG(); 1277 } 1278 1279 // Clear the Per-BB State. 1280 SDB->SPDescriptor.resetPerBBState(); 1281 } 1282 1283 // If we updated PHI Nodes, return early. 1284 if (MustUpdatePHINodes) 1285 return; 1286 1287 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1288 // Lower header first, if it wasn't already lowered 1289 if (!SDB->BitTestCases[i].Emitted) { 1290 // Set the current basic block to the mbb we wish to insert the code into 1291 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1292 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1293 // Emit the code 1294 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1295 CurDAG->setRoot(SDB->getRoot()); 1296 SDB->clear(); 1297 CodeGenAndEmitDAG(); 1298 } 1299 1300 uint32_t UnhandledWeight = 0; 1301 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1302 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1303 1304 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1305 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1306 // Set the current basic block to the mbb we wish to insert the code into 1307 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1308 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1309 // Emit the code 1310 if (j+1 != ej) 1311 SDB->visitBitTestCase(SDB->BitTestCases[i], 1312 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1313 UnhandledWeight, 1314 SDB->BitTestCases[i].Reg, 1315 SDB->BitTestCases[i].Cases[j], 1316 FuncInfo->MBB); 1317 else 1318 SDB->visitBitTestCase(SDB->BitTestCases[i], 1319 SDB->BitTestCases[i].Default, 1320 UnhandledWeight, 1321 SDB->BitTestCases[i].Reg, 1322 SDB->BitTestCases[i].Cases[j], 1323 FuncInfo->MBB); 1324 1325 1326 CurDAG->setRoot(SDB->getRoot()); 1327 SDB->clear(); 1328 CodeGenAndEmitDAG(); 1329 } 1330 1331 // Update PHI Nodes 1332 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1333 pi != pe; ++pi) { 1334 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1335 MachineBasicBlock *PHIBB = PHI->getParent(); 1336 assert(PHI->isPHI() && 1337 "This is not a machine PHI node that we are updating!"); 1338 // This is "default" BB. We have two jumps to it. From "header" BB and 1339 // from last "case" BB. 1340 if (PHIBB == SDB->BitTestCases[i].Default) 1341 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1342 .addMBB(SDB->BitTestCases[i].Parent) 1343 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1344 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1345 // One of "cases" BB. 1346 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1347 j != ej; ++j) { 1348 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1349 if (cBB->isSuccessor(PHIBB)) 1350 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1351 } 1352 } 1353 } 1354 SDB->BitTestCases.clear(); 1355 1356 // If the JumpTable record is filled in, then we need to emit a jump table. 1357 // Updating the PHI nodes is tricky in this case, since we need to determine 1358 // whether the PHI is a successor of the range check MBB or the jump table MBB 1359 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1360 // Lower header first, if it wasn't already lowered 1361 if (!SDB->JTCases[i].first.Emitted) { 1362 // Set the current basic block to the mbb we wish to insert the code into 1363 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1364 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1365 // Emit the code 1366 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1367 FuncInfo->MBB); 1368 CurDAG->setRoot(SDB->getRoot()); 1369 SDB->clear(); 1370 CodeGenAndEmitDAG(); 1371 } 1372 1373 // Set the current basic block to the mbb we wish to insert the code into 1374 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1375 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1376 // Emit the code 1377 SDB->visitJumpTable(SDB->JTCases[i].second); 1378 CurDAG->setRoot(SDB->getRoot()); 1379 SDB->clear(); 1380 CodeGenAndEmitDAG(); 1381 1382 // Update PHI Nodes 1383 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1384 pi != pe; ++pi) { 1385 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1386 MachineBasicBlock *PHIBB = PHI->getParent(); 1387 assert(PHI->isPHI() && 1388 "This is not a machine PHI node that we are updating!"); 1389 // "default" BB. We can go there only from header BB. 1390 if (PHIBB == SDB->JTCases[i].second.Default) 1391 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1392 .addMBB(SDB->JTCases[i].first.HeaderBB); 1393 // JT BB. Just iterate over successors here 1394 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1395 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1396 } 1397 } 1398 SDB->JTCases.clear(); 1399 1400 // If the switch block involved a branch to one of the actual successors, we 1401 // need to update PHI nodes in that block. 1402 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1403 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1404 assert(PHI->isPHI() && 1405 "This is not a machine PHI node that we are updating!"); 1406 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 1407 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1408 } 1409 1410 // If we generated any switch lowering information, build and codegen any 1411 // additional DAGs necessary. 1412 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1413 // Set the current basic block to the mbb we wish to insert the code into 1414 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1415 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1416 1417 // Determine the unique successors. 1418 SmallVector<MachineBasicBlock *, 2> Succs; 1419 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1420 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1421 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1422 1423 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1424 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1425 CurDAG->setRoot(SDB->getRoot()); 1426 SDB->clear(); 1427 CodeGenAndEmitDAG(); 1428 1429 // Remember the last block, now that any splitting is done, for use in 1430 // populating PHI nodes in successors. 1431 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1432 1433 // Handle any PHI nodes in successors of this chunk, as if we were coming 1434 // from the original BB before switch expansion. Note that PHI nodes can 1435 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1436 // handle them the right number of times. 1437 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1438 FuncInfo->MBB = Succs[i]; 1439 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1440 // FuncInfo->MBB may have been removed from the CFG if a branch was 1441 // constant folded. 1442 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1443 for (MachineBasicBlock::iterator 1444 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1445 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1446 MachineInstrBuilder PHI(*MF, MBBI); 1447 // This value for this PHI node is recorded in PHINodesToUpdate. 1448 for (unsigned pn = 0; ; ++pn) { 1449 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1450 "Didn't find PHI entry!"); 1451 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1452 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1453 break; 1454 } 1455 } 1456 } 1457 } 1458 } 1459 } 1460 SDB->SwitchCases.clear(); 1461} 1462 1463 1464/// Create the scheduler. If a specific scheduler was specified 1465/// via the SchedulerRegistry, use it, otherwise select the 1466/// one preferred by the target. 1467/// 1468ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1469 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1470 1471 if (!Ctor) { 1472 Ctor = ISHeuristic; 1473 RegisterScheduler::setDefault(Ctor); 1474 } 1475 1476 return Ctor(this, OptLevel); 1477} 1478 1479//===----------------------------------------------------------------------===// 1480// Helper functions used by the generated instruction selector. 1481//===----------------------------------------------------------------------===// 1482// Calls to these methods are generated by tblgen. 1483 1484/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1485/// the dag combiner simplified the 255, we still want to match. RHS is the 1486/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1487/// specified in the .td file (e.g. 255). 1488bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1489 int64_t DesiredMaskS) const { 1490 const APInt &ActualMask = RHS->getAPIntValue(); 1491 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1492 1493 // If the actual mask exactly matches, success! 1494 if (ActualMask == DesiredMask) 1495 return true; 1496 1497 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1498 if (ActualMask.intersects(~DesiredMask)) 1499 return false; 1500 1501 // Otherwise, the DAG Combiner may have proven that the value coming in is 1502 // either already zero or is not demanded. Check for known zero input bits. 1503 APInt NeededMask = DesiredMask & ~ActualMask; 1504 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1505 return true; 1506 1507 // TODO: check to see if missing bits are just not demanded. 1508 1509 // Otherwise, this pattern doesn't match. 1510 return false; 1511} 1512 1513/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1514/// the dag combiner simplified the 255, we still want to match. RHS is the 1515/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1516/// specified in the .td file (e.g. 255). 1517bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1518 int64_t DesiredMaskS) const { 1519 const APInt &ActualMask = RHS->getAPIntValue(); 1520 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1521 1522 // If the actual mask exactly matches, success! 1523 if (ActualMask == DesiredMask) 1524 return true; 1525 1526 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1527 if (ActualMask.intersects(~DesiredMask)) 1528 return false; 1529 1530 // Otherwise, the DAG Combiner may have proven that the value coming in is 1531 // either already zero or is not demanded. Check for known zero input bits. 1532 APInt NeededMask = DesiredMask & ~ActualMask; 1533 1534 APInt KnownZero, KnownOne; 1535 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 1536 1537 // If all the missing bits in the or are already known to be set, match! 1538 if ((NeededMask & KnownOne) == NeededMask) 1539 return true; 1540 1541 // TODO: check to see if missing bits are just not demanded. 1542 1543 // Otherwise, this pattern doesn't match. 1544 return false; 1545} 1546 1547 1548/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1549/// by tblgen. Others should not call it. 1550void SelectionDAGISel:: 1551SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1552 std::vector<SDValue> InOps; 1553 std::swap(InOps, Ops); 1554 1555 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1556 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1557 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1558 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1559 1560 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1561 if (InOps[e-1].getValueType() == MVT::Glue) 1562 --e; // Don't process a glue operand if it is here. 1563 1564 while (i != e) { 1565 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1566 if (!InlineAsm::isMemKind(Flags)) { 1567 // Just skip over this operand, copying the operands verbatim. 1568 Ops.insert(Ops.end(), InOps.begin()+i, 1569 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1570 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1571 } else { 1572 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1573 "Memory operand with multiple values?"); 1574 // Otherwise, this is a memory operand. Ask the target to select it. 1575 std::vector<SDValue> SelOps; 1576 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1577 report_fatal_error("Could not match memory address. Inline asm" 1578 " failure!"); 1579 1580 // Add this to the output node. 1581 unsigned NewFlags = 1582 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1583 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1584 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1585 i += 2; 1586 } 1587 } 1588 1589 // Add the glue input back if present. 1590 if (e != InOps.size()) 1591 Ops.push_back(InOps.back()); 1592} 1593 1594/// findGlueUse - Return use of MVT::Glue value produced by the specified 1595/// SDNode. 1596/// 1597static SDNode *findGlueUse(SDNode *N) { 1598 unsigned FlagResNo = N->getNumValues()-1; 1599 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1600 SDUse &Use = I.getUse(); 1601 if (Use.getResNo() == FlagResNo) 1602 return Use.getUser(); 1603 } 1604 return NULL; 1605} 1606 1607/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1608/// This function recursively traverses up the operand chain, ignoring 1609/// certain nodes. 1610static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1611 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1612 bool IgnoreChains) { 1613 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1614 // greater than all of its (recursive) operands. If we scan to a point where 1615 // 'use' is smaller than the node we're scanning for, then we know we will 1616 // never find it. 1617 // 1618 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1619 // happen because we scan down to newly selected nodes in the case of glue 1620 // uses. 1621 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1622 return false; 1623 1624 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1625 // won't fail if we scan it again. 1626 if (!Visited.insert(Use)) 1627 return false; 1628 1629 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1630 // Ignore chain uses, they are validated by HandleMergeInputChains. 1631 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1632 continue; 1633 1634 SDNode *N = Use->getOperand(i).getNode(); 1635 if (N == Def) { 1636 if (Use == ImmedUse || Use == Root) 1637 continue; // We are not looking for immediate use. 1638 assert(N != Root); 1639 return true; 1640 } 1641 1642 // Traverse up the operand chain. 1643 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1644 return true; 1645 } 1646 return false; 1647} 1648 1649/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1650/// operand node N of U during instruction selection that starts at Root. 1651bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1652 SDNode *Root) const { 1653 if (OptLevel == CodeGenOpt::None) return false; 1654 return N.hasOneUse(); 1655} 1656 1657/// IsLegalToFold - Returns true if the specific operand node N of 1658/// U can be folded during instruction selection that starts at Root. 1659bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1660 CodeGenOpt::Level OptLevel, 1661 bool IgnoreChains) { 1662 if (OptLevel == CodeGenOpt::None) return false; 1663 1664 // If Root use can somehow reach N through a path that that doesn't contain 1665 // U then folding N would create a cycle. e.g. In the following 1666 // diagram, Root can reach N through X. If N is folded into into Root, then 1667 // X is both a predecessor and a successor of U. 1668 // 1669 // [N*] // 1670 // ^ ^ // 1671 // / \ // 1672 // [U*] [X]? // 1673 // ^ ^ // 1674 // \ / // 1675 // \ / // 1676 // [Root*] // 1677 // 1678 // * indicates nodes to be folded together. 1679 // 1680 // If Root produces glue, then it gets (even more) interesting. Since it 1681 // will be "glued" together with its glue use in the scheduler, we need to 1682 // check if it might reach N. 1683 // 1684 // [N*] // 1685 // ^ ^ // 1686 // / \ // 1687 // [U*] [X]? // 1688 // ^ ^ // 1689 // \ \ // 1690 // \ | // 1691 // [Root*] | // 1692 // ^ | // 1693 // f | // 1694 // | / // 1695 // [Y] / // 1696 // ^ / // 1697 // f / // 1698 // | / // 1699 // [GU] // 1700 // 1701 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1702 // (call it Fold), then X is a predecessor of GU and a successor of 1703 // Fold. But since Fold and GU are glued together, this will create 1704 // a cycle in the scheduling graph. 1705 1706 // If the node has glue, walk down the graph to the "lowest" node in the 1707 // glueged set. 1708 EVT VT = Root->getValueType(Root->getNumValues()-1); 1709 while (VT == MVT::Glue) { 1710 SDNode *GU = findGlueUse(Root); 1711 if (GU == NULL) 1712 break; 1713 Root = GU; 1714 VT = Root->getValueType(Root->getNumValues()-1); 1715 1716 // If our query node has a glue result with a use, we've walked up it. If 1717 // the user (which has already been selected) has a chain or indirectly uses 1718 // the chain, our WalkChainUsers predicate will not consider it. Because of 1719 // this, we cannot ignore chains in this predicate. 1720 IgnoreChains = false; 1721 } 1722 1723 1724 SmallPtrSet<SDNode*, 16> Visited; 1725 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1726} 1727 1728SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1729 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1730 SelectInlineAsmMemoryOperands(Ops); 1731 1732 EVT VTs[] = { MVT::Other, MVT::Glue }; 1733 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), 1734 VTs, &Ops[0], Ops.size()); 1735 New->setNodeId(-1); 1736 return New.getNode(); 1737} 1738 1739SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1740 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1741} 1742 1743/// GetVBR - decode a vbr encoding whose top bit is set. 1744LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1745GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1746 assert(Val >= 128 && "Not a VBR"); 1747 Val &= 127; // Remove first vbr bit. 1748 1749 unsigned Shift = 7; 1750 uint64_t NextBits; 1751 do { 1752 NextBits = MatcherTable[Idx++]; 1753 Val |= (NextBits&127) << Shift; 1754 Shift += 7; 1755 } while (NextBits & 128); 1756 1757 return Val; 1758} 1759 1760 1761/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1762/// interior glue and chain results to use the new glue and chain results. 1763void SelectionDAGISel:: 1764UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1765 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1766 SDValue InputGlue, 1767 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1768 bool isMorphNodeTo) { 1769 SmallVector<SDNode*, 4> NowDeadNodes; 1770 1771 // Now that all the normal results are replaced, we replace the chain and 1772 // glue results if present. 1773 if (!ChainNodesMatched.empty()) { 1774 assert(InputChain.getNode() != 0 && 1775 "Matched input chains but didn't produce a chain"); 1776 // Loop over all of the nodes we matched that produced a chain result. 1777 // Replace all the chain results with the final chain we ended up with. 1778 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1779 SDNode *ChainNode = ChainNodesMatched[i]; 1780 1781 // If this node was already deleted, don't look at it. 1782 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1783 continue; 1784 1785 // Don't replace the results of the root node if we're doing a 1786 // MorphNodeTo. 1787 if (ChainNode == NodeToMatch && isMorphNodeTo) 1788 continue; 1789 1790 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1791 if (ChainVal.getValueType() == MVT::Glue) 1792 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1793 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1794 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1795 1796 // If the node became dead and we haven't already seen it, delete it. 1797 if (ChainNode->use_empty() && 1798 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1799 NowDeadNodes.push_back(ChainNode); 1800 } 1801 } 1802 1803 // If the result produces glue, update any glue results in the matched 1804 // pattern with the glue result. 1805 if (InputGlue.getNode() != 0) { 1806 // Handle any interior nodes explicitly marked. 1807 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1808 SDNode *FRN = GlueResultNodesMatched[i]; 1809 1810 // If this node was already deleted, don't look at it. 1811 if (FRN->getOpcode() == ISD::DELETED_NODE) 1812 continue; 1813 1814 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1815 "Doesn't have a glue result"); 1816 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1817 InputGlue); 1818 1819 // If the node became dead and we haven't already seen it, delete it. 1820 if (FRN->use_empty() && 1821 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1822 NowDeadNodes.push_back(FRN); 1823 } 1824 } 1825 1826 if (!NowDeadNodes.empty()) 1827 CurDAG->RemoveDeadNodes(NowDeadNodes); 1828 1829 DEBUG(dbgs() << "ISEL: Match complete!\n"); 1830} 1831 1832enum ChainResult { 1833 CR_Simple, 1834 CR_InducesCycle, 1835 CR_LeadsToInteriorNode 1836}; 1837 1838/// WalkChainUsers - Walk down the users of the specified chained node that is 1839/// part of the pattern we're matching, looking at all of the users we find. 1840/// This determines whether something is an interior node, whether we have a 1841/// non-pattern node in between two pattern nodes (which prevent folding because 1842/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1843/// between pattern nodes (in which case the TF becomes part of the pattern). 1844/// 1845/// The walk we do here is guaranteed to be small because we quickly get down to 1846/// already selected nodes "below" us. 1847static ChainResult 1848WalkChainUsers(const SDNode *ChainedNode, 1849 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1850 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1851 ChainResult Result = CR_Simple; 1852 1853 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1854 E = ChainedNode->use_end(); UI != E; ++UI) { 1855 // Make sure the use is of the chain, not some other value we produce. 1856 if (UI.getUse().getValueType() != MVT::Other) continue; 1857 1858 SDNode *User = *UI; 1859 1860 // If we see an already-selected machine node, then we've gone beyond the 1861 // pattern that we're selecting down into the already selected chunk of the 1862 // DAG. 1863 if (User->isMachineOpcode() || 1864 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1865 continue; 1866 1867 unsigned UserOpcode = User->getOpcode(); 1868 if (UserOpcode == ISD::CopyToReg || 1869 UserOpcode == ISD::CopyFromReg || 1870 UserOpcode == ISD::INLINEASM || 1871 UserOpcode == ISD::EH_LABEL || 1872 UserOpcode == ISD::LIFETIME_START || 1873 UserOpcode == ISD::LIFETIME_END) { 1874 // If their node ID got reset to -1 then they've already been selected. 1875 // Treat them like a MachineOpcode. 1876 if (User->getNodeId() == -1) 1877 continue; 1878 } 1879 1880 // If we have a TokenFactor, we handle it specially. 1881 if (User->getOpcode() != ISD::TokenFactor) { 1882 // If the node isn't a token factor and isn't part of our pattern, then it 1883 // must be a random chained node in between two nodes we're selecting. 1884 // This happens when we have something like: 1885 // x = load ptr 1886 // call 1887 // y = x+4 1888 // store y -> ptr 1889 // Because we structurally match the load/store as a read/modify/write, 1890 // but the call is chained between them. We cannot fold in this case 1891 // because it would induce a cycle in the graph. 1892 if (!std::count(ChainedNodesInPattern.begin(), 1893 ChainedNodesInPattern.end(), User)) 1894 return CR_InducesCycle; 1895 1896 // Otherwise we found a node that is part of our pattern. For example in: 1897 // x = load ptr 1898 // y = x+4 1899 // store y -> ptr 1900 // This would happen when we're scanning down from the load and see the 1901 // store as a user. Record that there is a use of ChainedNode that is 1902 // part of the pattern and keep scanning uses. 1903 Result = CR_LeadsToInteriorNode; 1904 InteriorChainedNodes.push_back(User); 1905 continue; 1906 } 1907 1908 // If we found a TokenFactor, there are two cases to consider: first if the 1909 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1910 // uses of the TF are in our pattern) we just want to ignore it. Second, 1911 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1912 // [Load chain] 1913 // ^ 1914 // | 1915 // [Load] 1916 // ^ ^ 1917 // | \ DAG's like cheese 1918 // / \ do you? 1919 // / | 1920 // [TokenFactor] [Op] 1921 // ^ ^ 1922 // | | 1923 // \ / 1924 // \ / 1925 // [Store] 1926 // 1927 // In this case, the TokenFactor becomes part of our match and we rewrite it 1928 // as a new TokenFactor. 1929 // 1930 // To distinguish these two cases, do a recursive walk down the uses. 1931 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1932 case CR_Simple: 1933 // If the uses of the TokenFactor are just already-selected nodes, ignore 1934 // it, it is "below" our pattern. 1935 continue; 1936 case CR_InducesCycle: 1937 // If the uses of the TokenFactor lead to nodes that are not part of our 1938 // pattern that are not selected, folding would turn this into a cycle, 1939 // bail out now. 1940 return CR_InducesCycle; 1941 case CR_LeadsToInteriorNode: 1942 break; // Otherwise, keep processing. 1943 } 1944 1945 // Okay, we know we're in the interesting interior case. The TokenFactor 1946 // is now going to be considered part of the pattern so that we rewrite its 1947 // uses (it may have uses that are not part of the pattern) with the 1948 // ultimate chain result of the generated code. We will also add its chain 1949 // inputs as inputs to the ultimate TokenFactor we create. 1950 Result = CR_LeadsToInteriorNode; 1951 ChainedNodesInPattern.push_back(User); 1952 InteriorChainedNodes.push_back(User); 1953 continue; 1954 } 1955 1956 return Result; 1957} 1958 1959/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1960/// operation for when the pattern matched at least one node with a chains. The 1961/// input vector contains a list of all of the chained nodes that we match. We 1962/// must determine if this is a valid thing to cover (i.e. matching it won't 1963/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1964/// be used as the input node chain for the generated nodes. 1965static SDValue 1966HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1967 SelectionDAG *CurDAG) { 1968 // Walk all of the chained nodes we've matched, recursively scanning down the 1969 // users of the chain result. This adds any TokenFactor nodes that are caught 1970 // in between chained nodes to the chained and interior nodes list. 1971 SmallVector<SDNode*, 3> InteriorChainedNodes; 1972 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1973 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1974 InteriorChainedNodes) == CR_InducesCycle) 1975 return SDValue(); // Would induce a cycle. 1976 } 1977 1978 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1979 // that we are interested in. Form our input TokenFactor node. 1980 SmallVector<SDValue, 3> InputChains; 1981 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1982 // Add the input chain of this node to the InputChains list (which will be 1983 // the operands of the generated TokenFactor) if it's not an interior node. 1984 SDNode *N = ChainNodesMatched[i]; 1985 if (N->getOpcode() != ISD::TokenFactor) { 1986 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1987 continue; 1988 1989 // Otherwise, add the input chain. 1990 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1991 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1992 InputChains.push_back(InChain); 1993 continue; 1994 } 1995 1996 // If we have a token factor, we want to add all inputs of the token factor 1997 // that are not part of the pattern we're matching. 1998 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1999 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 2000 N->getOperand(op).getNode())) 2001 InputChains.push_back(N->getOperand(op)); 2002 } 2003 } 2004 2005 SDValue Res; 2006 if (InputChains.size() == 1) 2007 return InputChains[0]; 2008 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]), 2009 MVT::Other, &InputChains[0], InputChains.size()); 2010} 2011 2012/// MorphNode - Handle morphing a node in place for the selector. 2013SDNode *SelectionDAGISel:: 2014MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 2015 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 2016 // It is possible we're using MorphNodeTo to replace a node with no 2017 // normal results with one that has a normal result (or we could be 2018 // adding a chain) and the input could have glue and chains as well. 2019 // In this case we need to shift the operands down. 2020 // FIXME: This is a horrible hack and broken in obscure cases, no worse 2021 // than the old isel though. 2022 int OldGlueResultNo = -1, OldChainResultNo = -1; 2023 2024 unsigned NTMNumResults = Node->getNumValues(); 2025 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 2026 OldGlueResultNo = NTMNumResults-1; 2027 if (NTMNumResults != 1 && 2028 Node->getValueType(NTMNumResults-2) == MVT::Other) 2029 OldChainResultNo = NTMNumResults-2; 2030 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 2031 OldChainResultNo = NTMNumResults-1; 2032 2033 // Call the underlying SelectionDAG routine to do the transmogrification. Note 2034 // that this deletes operands of the old node that become dead. 2035 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 2036 2037 // MorphNodeTo can operate in two ways: if an existing node with the 2038 // specified operands exists, it can just return it. Otherwise, it 2039 // updates the node in place to have the requested operands. 2040 if (Res == Node) { 2041 // If we updated the node in place, reset the node ID. To the isel, 2042 // this should be just like a newly allocated machine node. 2043 Res->setNodeId(-1); 2044 } 2045 2046 unsigned ResNumResults = Res->getNumValues(); 2047 // Move the glue if needed. 2048 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 2049 (unsigned)OldGlueResultNo != ResNumResults-1) 2050 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 2051 SDValue(Res, ResNumResults-1)); 2052 2053 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 2054 --ResNumResults; 2055 2056 // Move the chain reference if needed. 2057 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 2058 (unsigned)OldChainResultNo != ResNumResults-1) 2059 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 2060 SDValue(Res, ResNumResults-1)); 2061 2062 // Otherwise, no replacement happened because the node already exists. Replace 2063 // Uses of the old node with the new one. 2064 if (Res != Node) 2065 CurDAG->ReplaceAllUsesWith(Node, Res); 2066 2067 return Res; 2068} 2069 2070/// CheckSame - Implements OP_CheckSame. 2071LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2072CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2073 SDValue N, 2074 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2075 // Accept if it is exactly the same as a previously recorded node. 2076 unsigned RecNo = MatcherTable[MatcherIndex++]; 2077 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2078 return N == RecordedNodes[RecNo].first; 2079} 2080 2081/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2082LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2083CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2084 const SelectionDAGISel &SDISel) { 2085 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 2086} 2087 2088/// CheckNodePredicate - Implements OP_CheckNodePredicate. 2089LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2090CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2091 const SelectionDAGISel &SDISel, SDNode *N) { 2092 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2093} 2094 2095LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2096CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2097 SDNode *N) { 2098 uint16_t Opc = MatcherTable[MatcherIndex++]; 2099 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2100 return N->getOpcode() == Opc; 2101} 2102 2103LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2104CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2105 SDValue N, const TargetLowering *TLI) { 2106 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2107 if (N.getValueType() == VT) return true; 2108 2109 // Handle the case when VT is iPTR. 2110 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(); 2111} 2112 2113LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2114CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2115 SDValue N, const TargetLowering *TLI, 2116 unsigned ChildNo) { 2117 if (ChildNo >= N.getNumOperands()) 2118 return false; // Match fails if out of range child #. 2119 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2120} 2121 2122LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2123CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2124 SDValue N) { 2125 return cast<CondCodeSDNode>(N)->get() == 2126 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2127} 2128 2129LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2130CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2131 SDValue N, const TargetLowering *TLI) { 2132 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2133 if (cast<VTSDNode>(N)->getVT() == VT) 2134 return true; 2135 2136 // Handle the case when VT is iPTR. 2137 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(); 2138} 2139 2140LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2141CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2142 SDValue N) { 2143 int64_t Val = MatcherTable[MatcherIndex++]; 2144 if (Val & 128) 2145 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2146 2147 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2148 return C != 0 && C->getSExtValue() == Val; 2149} 2150 2151LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2152CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2153 SDValue N, const SelectionDAGISel &SDISel) { 2154 int64_t Val = MatcherTable[MatcherIndex++]; 2155 if (Val & 128) 2156 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2157 2158 if (N->getOpcode() != ISD::AND) return false; 2159 2160 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2161 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2162} 2163 2164LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2165CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2166 SDValue N, const SelectionDAGISel &SDISel) { 2167 int64_t Val = MatcherTable[MatcherIndex++]; 2168 if (Val & 128) 2169 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2170 2171 if (N->getOpcode() != ISD::OR) return false; 2172 2173 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2174 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2175} 2176 2177/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2178/// scope, evaluate the current node. If the current predicate is known to 2179/// fail, set Result=true and return anything. If the current predicate is 2180/// known to pass, set Result=false and return the MatcherIndex to continue 2181/// with. If the current predicate is unknown, set Result=false and return the 2182/// MatcherIndex to continue with. 2183static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2184 unsigned Index, SDValue N, 2185 bool &Result, 2186 const SelectionDAGISel &SDISel, 2187 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2188 switch (Table[Index++]) { 2189 default: 2190 Result = false; 2191 return Index-1; // Could not evaluate this predicate. 2192 case SelectionDAGISel::OPC_CheckSame: 2193 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2194 return Index; 2195 case SelectionDAGISel::OPC_CheckPatternPredicate: 2196 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2197 return Index; 2198 case SelectionDAGISel::OPC_CheckPredicate: 2199 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2200 return Index; 2201 case SelectionDAGISel::OPC_CheckOpcode: 2202 Result = !::CheckOpcode(Table, Index, N.getNode()); 2203 return Index; 2204 case SelectionDAGISel::OPC_CheckType: 2205 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering()); 2206 return Index; 2207 case SelectionDAGISel::OPC_CheckChild0Type: 2208 case SelectionDAGISel::OPC_CheckChild1Type: 2209 case SelectionDAGISel::OPC_CheckChild2Type: 2210 case SelectionDAGISel::OPC_CheckChild3Type: 2211 case SelectionDAGISel::OPC_CheckChild4Type: 2212 case SelectionDAGISel::OPC_CheckChild5Type: 2213 case SelectionDAGISel::OPC_CheckChild6Type: 2214 case SelectionDAGISel::OPC_CheckChild7Type: 2215 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(), 2216 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2217 return Index; 2218 case SelectionDAGISel::OPC_CheckCondCode: 2219 Result = !::CheckCondCode(Table, Index, N); 2220 return Index; 2221 case SelectionDAGISel::OPC_CheckValueType: 2222 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering()); 2223 return Index; 2224 case SelectionDAGISel::OPC_CheckInteger: 2225 Result = !::CheckInteger(Table, Index, N); 2226 return Index; 2227 case SelectionDAGISel::OPC_CheckAndImm: 2228 Result = !::CheckAndImm(Table, Index, N, SDISel); 2229 return Index; 2230 case SelectionDAGISel::OPC_CheckOrImm: 2231 Result = !::CheckOrImm(Table, Index, N, SDISel); 2232 return Index; 2233 } 2234} 2235 2236namespace { 2237 2238struct MatchScope { 2239 /// FailIndex - If this match fails, this is the index to continue with. 2240 unsigned FailIndex; 2241 2242 /// NodeStack - The node stack when the scope was formed. 2243 SmallVector<SDValue, 4> NodeStack; 2244 2245 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2246 unsigned NumRecordedNodes; 2247 2248 /// NumMatchedMemRefs - The number of matched memref entries. 2249 unsigned NumMatchedMemRefs; 2250 2251 /// InputChain/InputGlue - The current chain/glue 2252 SDValue InputChain, InputGlue; 2253 2254 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2255 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2256}; 2257 2258} 2259 2260SDNode *SelectionDAGISel:: 2261SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2262 unsigned TableSize) { 2263 // FIXME: Should these even be selected? Handle these cases in the caller? 2264 switch (NodeToMatch->getOpcode()) { 2265 default: 2266 break; 2267 case ISD::EntryToken: // These nodes remain the same. 2268 case ISD::BasicBlock: 2269 case ISD::Register: 2270 case ISD::RegisterMask: 2271 //case ISD::VALUETYPE: 2272 //case ISD::CONDCODE: 2273 case ISD::HANDLENODE: 2274 case ISD::MDNODE_SDNODE: 2275 case ISD::TargetConstant: 2276 case ISD::TargetConstantFP: 2277 case ISD::TargetConstantPool: 2278 case ISD::TargetFrameIndex: 2279 case ISD::TargetExternalSymbol: 2280 case ISD::TargetBlockAddress: 2281 case ISD::TargetJumpTable: 2282 case ISD::TargetGlobalTLSAddress: 2283 case ISD::TargetGlobalAddress: 2284 case ISD::TokenFactor: 2285 case ISD::CopyFromReg: 2286 case ISD::CopyToReg: 2287 case ISD::EH_LABEL: 2288 case ISD::LIFETIME_START: 2289 case ISD::LIFETIME_END: 2290 NodeToMatch->setNodeId(-1); // Mark selected. 2291 return 0; 2292 case ISD::AssertSext: 2293 case ISD::AssertZext: 2294 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2295 NodeToMatch->getOperand(0)); 2296 return 0; 2297 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2298 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2299 } 2300 2301 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2302 2303 // Set up the node stack with NodeToMatch as the only node on the stack. 2304 SmallVector<SDValue, 8> NodeStack; 2305 SDValue N = SDValue(NodeToMatch, 0); 2306 NodeStack.push_back(N); 2307 2308 // MatchScopes - Scopes used when matching, if a match failure happens, this 2309 // indicates where to continue checking. 2310 SmallVector<MatchScope, 8> MatchScopes; 2311 2312 // RecordedNodes - This is the set of nodes that have been recorded by the 2313 // state machine. The second value is the parent of the node, or null if the 2314 // root is recorded. 2315 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2316 2317 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2318 // pattern. 2319 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2320 2321 // These are the current input chain and glue for use when generating nodes. 2322 // Various Emit operations change these. For example, emitting a copytoreg 2323 // uses and updates these. 2324 SDValue InputChain, InputGlue; 2325 2326 // ChainNodesMatched - If a pattern matches nodes that have input/output 2327 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2328 // which ones they are. The result is captured into this list so that we can 2329 // update the chain results when the pattern is complete. 2330 SmallVector<SDNode*, 3> ChainNodesMatched; 2331 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2332 2333 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: "; 2334 NodeToMatch->dump(CurDAG); 2335 dbgs() << '\n'); 2336 2337 // Determine where to start the interpreter. Normally we start at opcode #0, 2338 // but if the state machine starts with an OPC_SwitchOpcode, then we 2339 // accelerate the first lookup (which is guaranteed to be hot) with the 2340 // OpcodeOffset table. 2341 unsigned MatcherIndex = 0; 2342 2343 if (!OpcodeOffset.empty()) { 2344 // Already computed the OpcodeOffset table, just index into it. 2345 if (N.getOpcode() < OpcodeOffset.size()) 2346 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2347 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2348 2349 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2350 // Otherwise, the table isn't computed, but the state machine does start 2351 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2352 // is the first time we're selecting an instruction. 2353 unsigned Idx = 1; 2354 while (1) { 2355 // Get the size of this case. 2356 unsigned CaseSize = MatcherTable[Idx++]; 2357 if (CaseSize & 128) 2358 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2359 if (CaseSize == 0) break; 2360 2361 // Get the opcode, add the index to the table. 2362 uint16_t Opc = MatcherTable[Idx++]; 2363 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2364 if (Opc >= OpcodeOffset.size()) 2365 OpcodeOffset.resize((Opc+1)*2); 2366 OpcodeOffset[Opc] = Idx; 2367 Idx += CaseSize; 2368 } 2369 2370 // Okay, do the lookup for the first opcode. 2371 if (N.getOpcode() < OpcodeOffset.size()) 2372 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2373 } 2374 2375 while (1) { 2376 assert(MatcherIndex < TableSize && "Invalid index"); 2377#ifndef NDEBUG 2378 unsigned CurrentOpcodeIndex = MatcherIndex; 2379#endif 2380 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2381 switch (Opcode) { 2382 case OPC_Scope: { 2383 // Okay, the semantics of this operation are that we should push a scope 2384 // then evaluate the first child. However, pushing a scope only to have 2385 // the first check fail (which then pops it) is inefficient. If we can 2386 // determine immediately that the first check (or first several) will 2387 // immediately fail, don't even bother pushing a scope for them. 2388 unsigned FailIndex; 2389 2390 while (1) { 2391 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2392 if (NumToSkip & 128) 2393 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2394 // Found the end of the scope with no match. 2395 if (NumToSkip == 0) { 2396 FailIndex = 0; 2397 break; 2398 } 2399 2400 FailIndex = MatcherIndex+NumToSkip; 2401 2402 unsigned MatcherIndexOfPredicate = MatcherIndex; 2403 (void)MatcherIndexOfPredicate; // silence warning. 2404 2405 // If we can't evaluate this predicate without pushing a scope (e.g. if 2406 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2407 // push the scope and evaluate the full predicate chain. 2408 bool Result; 2409 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2410 Result, *this, RecordedNodes); 2411 if (!Result) 2412 break; 2413 2414 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at " 2415 << "index " << MatcherIndexOfPredicate 2416 << ", continuing at " << FailIndex << "\n"); 2417 ++NumDAGIselRetries; 2418 2419 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2420 // move to the next case. 2421 MatcherIndex = FailIndex; 2422 } 2423 2424 // If the whole scope failed to match, bail. 2425 if (FailIndex == 0) break; 2426 2427 // Push a MatchScope which indicates where to go if the first child fails 2428 // to match. 2429 MatchScope NewEntry; 2430 NewEntry.FailIndex = FailIndex; 2431 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2432 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2433 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2434 NewEntry.InputChain = InputChain; 2435 NewEntry.InputGlue = InputGlue; 2436 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2437 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2438 MatchScopes.push_back(NewEntry); 2439 continue; 2440 } 2441 case OPC_RecordNode: { 2442 // Remember this node, it may end up being an operand in the pattern. 2443 SDNode *Parent = 0; 2444 if (NodeStack.size() > 1) 2445 Parent = NodeStack[NodeStack.size()-2].getNode(); 2446 RecordedNodes.push_back(std::make_pair(N, Parent)); 2447 continue; 2448 } 2449 2450 case OPC_RecordChild0: case OPC_RecordChild1: 2451 case OPC_RecordChild2: case OPC_RecordChild3: 2452 case OPC_RecordChild4: case OPC_RecordChild5: 2453 case OPC_RecordChild6: case OPC_RecordChild7: { 2454 unsigned ChildNo = Opcode-OPC_RecordChild0; 2455 if (ChildNo >= N.getNumOperands()) 2456 break; // Match fails if out of range child #. 2457 2458 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2459 N.getNode())); 2460 continue; 2461 } 2462 case OPC_RecordMemRef: 2463 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2464 continue; 2465 2466 case OPC_CaptureGlueInput: 2467 // If the current node has an input glue, capture it in InputGlue. 2468 if (N->getNumOperands() != 0 && 2469 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2470 InputGlue = N->getOperand(N->getNumOperands()-1); 2471 continue; 2472 2473 case OPC_MoveChild: { 2474 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2475 if (ChildNo >= N.getNumOperands()) 2476 break; // Match fails if out of range child #. 2477 N = N.getOperand(ChildNo); 2478 NodeStack.push_back(N); 2479 continue; 2480 } 2481 2482 case OPC_MoveParent: 2483 // Pop the current node off the NodeStack. 2484 NodeStack.pop_back(); 2485 assert(!NodeStack.empty() && "Node stack imbalance!"); 2486 N = NodeStack.back(); 2487 continue; 2488 2489 case OPC_CheckSame: 2490 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2491 continue; 2492 case OPC_CheckPatternPredicate: 2493 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2494 continue; 2495 case OPC_CheckPredicate: 2496 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2497 N.getNode())) 2498 break; 2499 continue; 2500 case OPC_CheckComplexPat: { 2501 unsigned CPNum = MatcherTable[MatcherIndex++]; 2502 unsigned RecNo = MatcherTable[MatcherIndex++]; 2503 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2504 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2505 RecordedNodes[RecNo].first, CPNum, 2506 RecordedNodes)) 2507 break; 2508 continue; 2509 } 2510 case OPC_CheckOpcode: 2511 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2512 continue; 2513 2514 case OPC_CheckType: 2515 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2516 break; 2517 continue; 2518 2519 case OPC_SwitchOpcode: { 2520 unsigned CurNodeOpcode = N.getOpcode(); 2521 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2522 unsigned CaseSize; 2523 while (1) { 2524 // Get the size of this case. 2525 CaseSize = MatcherTable[MatcherIndex++]; 2526 if (CaseSize & 128) 2527 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2528 if (CaseSize == 0) break; 2529 2530 uint16_t Opc = MatcherTable[MatcherIndex++]; 2531 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2532 2533 // If the opcode matches, then we will execute this case. 2534 if (CurNodeOpcode == Opc) 2535 break; 2536 2537 // Otherwise, skip over this case. 2538 MatcherIndex += CaseSize; 2539 } 2540 2541 // If no cases matched, bail out. 2542 if (CaseSize == 0) break; 2543 2544 // Otherwise, execute the case we found. 2545 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart 2546 << " to " << MatcherIndex << "\n"); 2547 continue; 2548 } 2549 2550 case OPC_SwitchType: { 2551 MVT CurNodeVT = N.getSimpleValueType(); 2552 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2553 unsigned CaseSize; 2554 while (1) { 2555 // Get the size of this case. 2556 CaseSize = MatcherTable[MatcherIndex++]; 2557 if (CaseSize & 128) 2558 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2559 if (CaseSize == 0) break; 2560 2561 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2562 if (CaseVT == MVT::iPTR) 2563 CaseVT = getTargetLowering()->getPointerTy(); 2564 2565 // If the VT matches, then we will execute this case. 2566 if (CurNodeVT == CaseVT) 2567 break; 2568 2569 // Otherwise, skip over this case. 2570 MatcherIndex += CaseSize; 2571 } 2572 2573 // If no cases matched, bail out. 2574 if (CaseSize == 0) break; 2575 2576 // Otherwise, execute the case we found. 2577 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2578 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2579 continue; 2580 } 2581 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2582 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2583 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2584 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2585 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(), 2586 Opcode-OPC_CheckChild0Type)) 2587 break; 2588 continue; 2589 case OPC_CheckCondCode: 2590 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2591 continue; 2592 case OPC_CheckValueType: 2593 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2594 break; 2595 continue; 2596 case OPC_CheckInteger: 2597 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2598 continue; 2599 case OPC_CheckAndImm: 2600 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2601 continue; 2602 case OPC_CheckOrImm: 2603 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2604 continue; 2605 2606 case OPC_CheckFoldableChainNode: { 2607 assert(NodeStack.size() != 1 && "No parent node"); 2608 // Verify that all intermediate nodes between the root and this one have 2609 // a single use. 2610 bool HasMultipleUses = false; 2611 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2612 if (!NodeStack[i].hasOneUse()) { 2613 HasMultipleUses = true; 2614 break; 2615 } 2616 if (HasMultipleUses) break; 2617 2618 // Check to see that the target thinks this is profitable to fold and that 2619 // we can fold it without inducing cycles in the graph. 2620 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2621 NodeToMatch) || 2622 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2623 NodeToMatch, OptLevel, 2624 true/*We validate our own chains*/)) 2625 break; 2626 2627 continue; 2628 } 2629 case OPC_EmitInteger: { 2630 MVT::SimpleValueType VT = 2631 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2632 int64_t Val = MatcherTable[MatcherIndex++]; 2633 if (Val & 128) 2634 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2635 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2636 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2637 continue; 2638 } 2639 case OPC_EmitRegister: { 2640 MVT::SimpleValueType VT = 2641 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2642 unsigned RegNo = MatcherTable[MatcherIndex++]; 2643 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2644 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2645 continue; 2646 } 2647 case OPC_EmitRegister2: { 2648 // For targets w/ more than 256 register names, the register enum 2649 // values are stored in two bytes in the matcher table (just like 2650 // opcodes). 2651 MVT::SimpleValueType VT = 2652 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2653 unsigned RegNo = MatcherTable[MatcherIndex++]; 2654 RegNo |= MatcherTable[MatcherIndex++] << 8; 2655 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2656 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2657 continue; 2658 } 2659 2660 case OPC_EmitConvertToTarget: { 2661 // Convert from IMM/FPIMM to target version. 2662 unsigned RecNo = MatcherTable[MatcherIndex++]; 2663 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2664 SDValue Imm = RecordedNodes[RecNo].first; 2665 2666 if (Imm->getOpcode() == ISD::Constant) { 2667 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 2668 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true); 2669 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2670 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2671 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true); 2672 } 2673 2674 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2675 continue; 2676 } 2677 2678 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2679 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2680 // These are space-optimized forms of OPC_EmitMergeInputChains. 2681 assert(InputChain.getNode() == 0 && 2682 "EmitMergeInputChains should be the first chain producing node"); 2683 assert(ChainNodesMatched.empty() && 2684 "Should only have one EmitMergeInputChains per match"); 2685 2686 // Read all of the chained nodes. 2687 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2688 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2689 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2690 2691 // FIXME: What if other value results of the node have uses not matched 2692 // by this pattern? 2693 if (ChainNodesMatched.back() != NodeToMatch && 2694 !RecordedNodes[RecNo].first.hasOneUse()) { 2695 ChainNodesMatched.clear(); 2696 break; 2697 } 2698 2699 // Merge the input chains if they are not intra-pattern references. 2700 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2701 2702 if (InputChain.getNode() == 0) 2703 break; // Failed to merge. 2704 continue; 2705 } 2706 2707 case OPC_EmitMergeInputChains: { 2708 assert(InputChain.getNode() == 0 && 2709 "EmitMergeInputChains should be the first chain producing node"); 2710 // This node gets a list of nodes we matched in the input that have 2711 // chains. We want to token factor all of the input chains to these nodes 2712 // together. However, if any of the input chains is actually one of the 2713 // nodes matched in this pattern, then we have an intra-match reference. 2714 // Ignore these because the newly token factored chain should not refer to 2715 // the old nodes. 2716 unsigned NumChains = MatcherTable[MatcherIndex++]; 2717 assert(NumChains != 0 && "Can't TF zero chains"); 2718 2719 assert(ChainNodesMatched.empty() && 2720 "Should only have one EmitMergeInputChains per match"); 2721 2722 // Read all of the chained nodes. 2723 for (unsigned i = 0; i != NumChains; ++i) { 2724 unsigned RecNo = MatcherTable[MatcherIndex++]; 2725 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2726 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2727 2728 // FIXME: What if other value results of the node have uses not matched 2729 // by this pattern? 2730 if (ChainNodesMatched.back() != NodeToMatch && 2731 !RecordedNodes[RecNo].first.hasOneUse()) { 2732 ChainNodesMatched.clear(); 2733 break; 2734 } 2735 } 2736 2737 // If the inner loop broke out, the match fails. 2738 if (ChainNodesMatched.empty()) 2739 break; 2740 2741 // Merge the input chains if they are not intra-pattern references. 2742 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2743 2744 if (InputChain.getNode() == 0) 2745 break; // Failed to merge. 2746 2747 continue; 2748 } 2749 2750 case OPC_EmitCopyToReg: { 2751 unsigned RecNo = MatcherTable[MatcherIndex++]; 2752 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2753 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2754 2755 if (InputChain.getNode() == 0) 2756 InputChain = CurDAG->getEntryNode(); 2757 2758 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch), 2759 DestPhysReg, RecordedNodes[RecNo].first, 2760 InputGlue); 2761 2762 InputGlue = InputChain.getValue(1); 2763 continue; 2764 } 2765 2766 case OPC_EmitNodeXForm: { 2767 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2768 unsigned RecNo = MatcherTable[MatcherIndex++]; 2769 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2770 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2771 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2772 continue; 2773 } 2774 2775 case OPC_EmitNode: 2776 case OPC_MorphNodeTo: { 2777 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2778 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2779 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2780 // Get the result VT list. 2781 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2782 SmallVector<EVT, 4> VTs; 2783 for (unsigned i = 0; i != NumVTs; ++i) { 2784 MVT::SimpleValueType VT = 2785 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2786 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy; 2787 VTs.push_back(VT); 2788 } 2789 2790 if (EmitNodeInfo & OPFL_Chain) 2791 VTs.push_back(MVT::Other); 2792 if (EmitNodeInfo & OPFL_GlueOutput) 2793 VTs.push_back(MVT::Glue); 2794 2795 // This is hot code, so optimize the two most common cases of 1 and 2 2796 // results. 2797 SDVTList VTList; 2798 if (VTs.size() == 1) 2799 VTList = CurDAG->getVTList(VTs[0]); 2800 else if (VTs.size() == 2) 2801 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2802 else 2803 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2804 2805 // Get the operand list. 2806 unsigned NumOps = MatcherTable[MatcherIndex++]; 2807 SmallVector<SDValue, 8> Ops; 2808 for (unsigned i = 0; i != NumOps; ++i) { 2809 unsigned RecNo = MatcherTable[MatcherIndex++]; 2810 if (RecNo & 128) 2811 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2812 2813 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2814 Ops.push_back(RecordedNodes[RecNo].first); 2815 } 2816 2817 // If there are variadic operands to add, handle them now. 2818 if (EmitNodeInfo & OPFL_VariadicInfo) { 2819 // Determine the start index to copy from. 2820 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2821 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2822 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2823 "Invalid variadic node"); 2824 // Copy all of the variadic operands, not including a potential glue 2825 // input. 2826 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2827 i != e; ++i) { 2828 SDValue V = NodeToMatch->getOperand(i); 2829 if (V.getValueType() == MVT::Glue) break; 2830 Ops.push_back(V); 2831 } 2832 } 2833 2834 // If this has chain/glue inputs, add them. 2835 if (EmitNodeInfo & OPFL_Chain) 2836 Ops.push_back(InputChain); 2837 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2838 Ops.push_back(InputGlue); 2839 2840 // Create the node. 2841 SDNode *Res = 0; 2842 if (Opcode != OPC_MorphNodeTo) { 2843 // If this is a normal EmitNode command, just create the new node and 2844 // add the results to the RecordedNodes list. 2845 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch), 2846 VTList, Ops); 2847 2848 // Add all the non-glue/non-chain results to the RecordedNodes list. 2849 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2850 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2851 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2852 (SDNode*) 0)); 2853 } 2854 2855 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 2856 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2857 EmitNodeInfo); 2858 } else { 2859 // NodeToMatch was eliminated by CSE when the target changed the DAG. 2860 // We will visit the equivalent node later. 2861 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 2862 return 0; 2863 } 2864 2865 // If the node had chain/glue results, update our notion of the current 2866 // chain and glue. 2867 if (EmitNodeInfo & OPFL_GlueOutput) { 2868 InputGlue = SDValue(Res, VTs.size()-1); 2869 if (EmitNodeInfo & OPFL_Chain) 2870 InputChain = SDValue(Res, VTs.size()-2); 2871 } else if (EmitNodeInfo & OPFL_Chain) 2872 InputChain = SDValue(Res, VTs.size()-1); 2873 2874 // If the OPFL_MemRefs glue is set on this node, slap all of the 2875 // accumulated memrefs onto it. 2876 // 2877 // FIXME: This is vastly incorrect for patterns with multiple outputs 2878 // instructions that access memory and for ComplexPatterns that match 2879 // loads. 2880 if (EmitNodeInfo & OPFL_MemRefs) { 2881 // Only attach load or store memory operands if the generated 2882 // instruction may load or store. 2883 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2884 bool mayLoad = MCID.mayLoad(); 2885 bool mayStore = MCID.mayStore(); 2886 2887 unsigned NumMemRefs = 0; 2888 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 2889 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2890 if ((*I)->isLoad()) { 2891 if (mayLoad) 2892 ++NumMemRefs; 2893 } else if ((*I)->isStore()) { 2894 if (mayStore) 2895 ++NumMemRefs; 2896 } else { 2897 ++NumMemRefs; 2898 } 2899 } 2900 2901 MachineSDNode::mmo_iterator MemRefs = 2902 MF->allocateMemRefsArray(NumMemRefs); 2903 2904 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 2905 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 2906 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2907 if ((*I)->isLoad()) { 2908 if (mayLoad) 2909 *MemRefsPos++ = *I; 2910 } else if ((*I)->isStore()) { 2911 if (mayStore) 2912 *MemRefsPos++ = *I; 2913 } else { 2914 *MemRefsPos++ = *I; 2915 } 2916 } 2917 2918 cast<MachineSDNode>(Res) 2919 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 2920 } 2921 2922 DEBUG(dbgs() << " " 2923 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2924 << " node: "; Res->dump(CurDAG); dbgs() << "\n"); 2925 2926 // If this was a MorphNodeTo then we're completely done! 2927 if (Opcode == OPC_MorphNodeTo) { 2928 // Update chain and glue uses. 2929 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2930 InputGlue, GlueResultNodesMatched, true); 2931 return Res; 2932 } 2933 2934 continue; 2935 } 2936 2937 case OPC_MarkGlueResults: { 2938 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2939 2940 // Read and remember all the glue-result nodes. 2941 for (unsigned i = 0; i != NumNodes; ++i) { 2942 unsigned RecNo = MatcherTable[MatcherIndex++]; 2943 if (RecNo & 128) 2944 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2945 2946 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2947 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2948 } 2949 continue; 2950 } 2951 2952 case OPC_CompleteMatch: { 2953 // The match has been completed, and any new nodes (if any) have been 2954 // created. Patch up references to the matched dag to use the newly 2955 // created nodes. 2956 unsigned NumResults = MatcherTable[MatcherIndex++]; 2957 2958 for (unsigned i = 0; i != NumResults; ++i) { 2959 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2960 if (ResSlot & 128) 2961 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2962 2963 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2964 SDValue Res = RecordedNodes[ResSlot].first; 2965 2966 assert(i < NodeToMatch->getNumValues() && 2967 NodeToMatch->getValueType(i) != MVT::Other && 2968 NodeToMatch->getValueType(i) != MVT::Glue && 2969 "Invalid number of results to complete!"); 2970 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2971 NodeToMatch->getValueType(i) == MVT::iPTR || 2972 Res.getValueType() == MVT::iPTR || 2973 NodeToMatch->getValueType(i).getSizeInBits() == 2974 Res.getValueType().getSizeInBits()) && 2975 "invalid replacement"); 2976 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2977 } 2978 2979 // If the root node defines glue, add it to the glue nodes to update list. 2980 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2981 GlueResultNodesMatched.push_back(NodeToMatch); 2982 2983 // Update chain and glue uses. 2984 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2985 InputGlue, GlueResultNodesMatched, false); 2986 2987 assert(NodeToMatch->use_empty() && 2988 "Didn't replace all uses of the node?"); 2989 2990 // FIXME: We just return here, which interacts correctly with SelectRoot 2991 // above. We should fix this to not return an SDNode* anymore. 2992 return 0; 2993 } 2994 } 2995 2996 // If the code reached this point, then the match failed. See if there is 2997 // another child to try in the current 'Scope', otherwise pop it until we 2998 // find a case to check. 2999 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 3000 ++NumDAGIselRetries; 3001 while (1) { 3002 if (MatchScopes.empty()) { 3003 CannotYetSelect(NodeToMatch); 3004 return 0; 3005 } 3006 3007 // Restore the interpreter state back to the point where the scope was 3008 // formed. 3009 MatchScope &LastScope = MatchScopes.back(); 3010 RecordedNodes.resize(LastScope.NumRecordedNodes); 3011 NodeStack.clear(); 3012 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 3013 N = NodeStack.back(); 3014 3015 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 3016 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 3017 MatcherIndex = LastScope.FailIndex; 3018 3019 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); 3020 3021 InputChain = LastScope.InputChain; 3022 InputGlue = LastScope.InputGlue; 3023 if (!LastScope.HasChainNodesMatched) 3024 ChainNodesMatched.clear(); 3025 if (!LastScope.HasGlueResultNodesMatched) 3026 GlueResultNodesMatched.clear(); 3027 3028 // Check to see what the offset is at the new MatcherIndex. If it is zero 3029 // we have reached the end of this scope, otherwise we have another child 3030 // in the current scope to try. 3031 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 3032 if (NumToSkip & 128) 3033 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 3034 3035 // If we have another child in this scope to match, update FailIndex and 3036 // try it. 3037 if (NumToSkip != 0) { 3038 LastScope.FailIndex = MatcherIndex+NumToSkip; 3039 break; 3040 } 3041 3042 // End of this scope, pop it and try the next child in the containing 3043 // scope. 3044 MatchScopes.pop_back(); 3045 } 3046 } 3047} 3048 3049 3050 3051void SelectionDAGISel::CannotYetSelect(SDNode *N) { 3052 std::string msg; 3053 raw_string_ostream Msg(msg); 3054 Msg << "Cannot select: "; 3055 3056 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 3057 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 3058 N->getOpcode() != ISD::INTRINSIC_VOID) { 3059 N->printrFull(Msg, CurDAG); 3060 Msg << "\nIn function: " << MF->getName(); 3061 } else { 3062 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 3063 unsigned iid = 3064 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 3065 if (iid < Intrinsic::num_intrinsics) 3066 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 3067 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 3068 Msg << "target intrinsic %" << TII->getName(iid); 3069 else 3070 Msg << "unknown intrinsic #" << iid; 3071 } 3072 report_fatal_error(Msg.str()); 3073} 3074 3075char SelectionDAGISel::ID = 0; 3076