SelectionDAGISel.cpp revision 081ce940e7351e90fff829320b7dc6738a6b3815
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/MachineModuleInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/CodeGen/SSARegMap.h" 37#include "llvm/Target/MRegisterInfo.h" 38#include "llvm/Target/TargetData.h" 39#include "llvm/Target/TargetFrameInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Compiler.h" 47#include <algorithm> 48using namespace llvm; 49 50#ifndef NDEBUG 51static cl::opt<bool> 52ViewISelDAGs("view-isel-dags", cl::Hidden, 53 cl::desc("Pop up a window to show isel dags as they are selected")); 54static cl::opt<bool> 55ViewSchedDAGs("view-sched-dags", cl::Hidden, 56 cl::desc("Pop up a window to show sched dags as they are processed")); 57static cl::opt<bool> 58ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 59 cl::desc("Pop up a window to show SUnit dags after they are processed")); 60#else 61static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0; 62#endif 63 64//===---------------------------------------------------------------------===// 65/// 66/// RegisterScheduler class - Track the registration of instruction schedulers. 67/// 68//===---------------------------------------------------------------------===// 69MachinePassRegistry RegisterScheduler::Registry; 70 71//===---------------------------------------------------------------------===// 72/// 73/// ISHeuristic command line option for instruction schedulers. 74/// 75//===---------------------------------------------------------------------===// 76namespace { 77 cl::opt<RegisterScheduler::FunctionPassCtor, false, 78 RegisterPassParser<RegisterScheduler> > 79 ISHeuristic("pre-RA-sched", 80 cl::init(&createDefaultScheduler), 81 cl::desc("Instruction schedulers available (before register allocation):")); 82 83 static RegisterScheduler 84 defaultListDAGScheduler("default", " Best scheduler for the target", 85 createDefaultScheduler); 86} // namespace 87 88namespace { struct AsmOperandInfo; } 89 90namespace { 91 /// RegsForValue - This struct represents the physical registers that a 92 /// particular value is assigned and the type information about the value. 93 /// This is needed because values can be promoted into larger registers and 94 /// expanded into multiple smaller registers than the value. 95 struct VISIBILITY_HIDDEN RegsForValue { 96 /// Regs - This list holds the register (for legal and promoted values) 97 /// or register set (for expanded values) that the value should be assigned 98 /// to. 99 std::vector<unsigned> Regs; 100 101 /// RegVT - The value type of each register. 102 /// 103 MVT::ValueType RegVT; 104 105 /// ValueVT - The value type of the LLVM value, which may be promoted from 106 /// RegVT or made from merging the two expanded parts. 107 MVT::ValueType ValueVT; 108 109 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 110 111 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 112 : RegVT(regvt), ValueVT(valuevt) { 113 Regs.push_back(Reg); 114 } 115 RegsForValue(const std::vector<unsigned> ®s, 116 MVT::ValueType regvt, MVT::ValueType valuevt) 117 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 118 } 119 120 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 121 /// this value and returns the result as a ValueVT value. This uses 122 /// Chain/Flag as the input and updates them for the output Chain/Flag. 123 /// If the Flag pointer is NULL, no flag is used. 124 SDOperand getCopyFromRegs(SelectionDAG &DAG, 125 SDOperand &Chain, SDOperand *Flag) const; 126 127 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 128 /// specified value into the registers specified by this object. This uses 129 /// Chain/Flag as the input and updates them for the output Chain/Flag. 130 /// If the Flag pointer is NULL, no flag is used. 131 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 132 SDOperand &Chain, SDOperand *Flag) const; 133 134 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 135 /// operand list. This adds the code marker and includes the number of 136 /// values added into it. 137 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 138 std::vector<SDOperand> &Ops) const; 139 }; 140} 141 142namespace llvm { 143 //===--------------------------------------------------------------------===// 144 /// createDefaultScheduler - This creates an instruction scheduler appropriate 145 /// for the target. 146 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 147 SelectionDAG *DAG, 148 MachineBasicBlock *BB) { 149 TargetLowering &TLI = IS->getTargetLowering(); 150 151 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 152 return createTDListDAGScheduler(IS, DAG, BB); 153 } else { 154 assert(TLI.getSchedulingPreference() == 155 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 156 return createBURRListDAGScheduler(IS, DAG, BB); 157 } 158 } 159 160 161 //===--------------------------------------------------------------------===// 162 /// FunctionLoweringInfo - This contains information that is global to a 163 /// function that is used when lowering a region of the function. 164 class FunctionLoweringInfo { 165 public: 166 TargetLowering &TLI; 167 Function &Fn; 168 MachineFunction &MF; 169 SSARegMap *RegMap; 170 171 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 172 173 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 174 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 175 176 /// ValueMap - Since we emit code for the function a basic block at a time, 177 /// we must remember which virtual registers hold the values for 178 /// cross-basic-block values. 179 DenseMap<const Value*, unsigned> ValueMap; 180 181 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 182 /// the entry block. This allows the allocas to be efficiently referenced 183 /// anywhere in the function. 184 std::map<const AllocaInst*, int> StaticAllocaMap; 185 186#ifndef NDEBUG 187 SmallSet<Instruction*, 8> CatchInfoLost; 188 SmallSet<Instruction*, 8> CatchInfoFound; 189#endif 190 191 unsigned MakeReg(MVT::ValueType VT) { 192 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 193 } 194 195 /// isExportedInst - Return true if the specified value is an instruction 196 /// exported from its block. 197 bool isExportedInst(const Value *V) { 198 return ValueMap.count(V); 199 } 200 201 unsigned CreateRegForValue(const Value *V); 202 203 unsigned InitializeRegForValue(const Value *V) { 204 unsigned &R = ValueMap[V]; 205 assert(R == 0 && "Already initialized this value register!"); 206 return R = CreateRegForValue(V); 207 } 208 }; 209} 210 211/// isSelector - Return true if this instruction is a call to the 212/// eh.selector intrinsic. 213static bool isSelector(Instruction *I) { 214 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 215 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 || 216 II->getIntrinsicID() == Intrinsic::eh_selector_i64); 217 return false; 218} 219 220/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 221/// PHI nodes or outside of the basic block that defines it, or used by a 222/// switch instruction, which may expand to multiple basic blocks. 223static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 224 if (isa<PHINode>(I)) return true; 225 BasicBlock *BB = I->getParent(); 226 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 227 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 228 // FIXME: Remove switchinst special case. 229 isa<SwitchInst>(*UI)) 230 return true; 231 return false; 232} 233 234/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 235/// entry block, return true. This includes arguments used by switches, since 236/// the switch may expand into multiple basic blocks. 237static bool isOnlyUsedInEntryBlock(Argument *A) { 238 BasicBlock *Entry = A->getParent()->begin(); 239 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 240 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 241 return false; // Use not in entry block. 242 return true; 243} 244 245FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 246 Function &fn, MachineFunction &mf) 247 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 248 249 // Create a vreg for each argument register that is not dead and is used 250 // outside of the entry block for the function. 251 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 252 AI != E; ++AI) 253 if (!isOnlyUsedInEntryBlock(AI)) 254 InitializeRegForValue(AI); 255 256 // Initialize the mapping of values to registers. This is only set up for 257 // instruction values that are used outside of the block that defines 258 // them. 259 Function::iterator BB = Fn.begin(), EB = Fn.end(); 260 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 261 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 262 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 263 const Type *Ty = AI->getAllocatedType(); 264 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 265 unsigned Align = 266 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 267 AI->getAlignment()); 268 269 TySize *= CUI->getZExtValue(); // Get total allocated size. 270 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 271 StaticAllocaMap[AI] = 272 MF.getFrameInfo()->CreateStackObject(TySize, Align); 273 } 274 275 for (; BB != EB; ++BB) 276 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 277 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 278 if (!isa<AllocaInst>(I) || 279 !StaticAllocaMap.count(cast<AllocaInst>(I))) 280 InitializeRegForValue(I); 281 282 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 283 // also creates the initial PHI MachineInstrs, though none of the input 284 // operands are populated. 285 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 286 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 287 MBBMap[BB] = MBB; 288 MF.getBasicBlockList().push_back(MBB); 289 290 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 291 // appropriate. 292 PHINode *PN; 293 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 294 if (PN->use_empty()) continue; 295 296 MVT::ValueType VT = TLI.getValueType(PN->getType()); 297 unsigned NumRegisters = TLI.getNumRegisters(VT); 298 unsigned PHIReg = ValueMap[PN]; 299 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 300 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 301 for (unsigned i = 0; i != NumRegisters; ++i) 302 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 303 } 304 } 305} 306 307/// CreateRegForValue - Allocate the appropriate number of virtual registers of 308/// the correctly promoted or expanded types. Assign these registers 309/// consecutive vreg numbers and return the first assigned number. 310unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 311 MVT::ValueType VT = TLI.getValueType(V->getType()); 312 313 unsigned NumRegisters = TLI.getNumRegisters(VT); 314 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 315 316 unsigned R = MakeReg(RegisterVT); 317 for (unsigned i = 1; i != NumRegisters; ++i) 318 MakeReg(RegisterVT); 319 320 return R; 321} 322 323//===----------------------------------------------------------------------===// 324/// SelectionDAGLowering - This is the common target-independent lowering 325/// implementation that is parameterized by a TargetLowering object. 326/// Also, targets can overload any lowering method. 327/// 328namespace llvm { 329class SelectionDAGLowering { 330 MachineBasicBlock *CurMBB; 331 332 DenseMap<const Value*, SDOperand> NodeMap; 333 334 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 335 /// them up and then emit token factor nodes when possible. This allows us to 336 /// get simple disambiguation between loads without worrying about alias 337 /// analysis. 338 std::vector<SDOperand> PendingLoads; 339 340 /// Case - A struct to record the Value for a switch case, and the 341 /// case's target basic block. 342 struct Case { 343 Constant* Low; 344 Constant* High; 345 MachineBasicBlock* BB; 346 347 Case() : Low(0), High(0), BB(0) { } 348 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 349 Low(low), High(high), BB(bb) { } 350 uint64_t size() const { 351 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 352 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 353 return (rHigh - rLow + 1ULL); 354 } 355 }; 356 357 struct CaseBits { 358 uint64_t Mask; 359 MachineBasicBlock* BB; 360 unsigned Bits; 361 362 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 363 Mask(mask), BB(bb), Bits(bits) { } 364 }; 365 366 typedef std::vector<Case> CaseVector; 367 typedef std::vector<CaseBits> CaseBitsVector; 368 typedef CaseVector::iterator CaseItr; 369 typedef std::pair<CaseItr, CaseItr> CaseRange; 370 371 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 372 /// of conditional branches. 373 struct CaseRec { 374 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 375 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 376 377 /// CaseBB - The MBB in which to emit the compare and branch 378 MachineBasicBlock *CaseBB; 379 /// LT, GE - If nonzero, we know the current case value must be less-than or 380 /// greater-than-or-equal-to these Constants. 381 Constant *LT; 382 Constant *GE; 383 /// Range - A pair of iterators representing the range of case values to be 384 /// processed at this point in the binary search tree. 385 CaseRange Range; 386 }; 387 388 typedef std::vector<CaseRec> CaseRecVector; 389 390 /// The comparison function for sorting the switch case values in the vector. 391 /// WARNING: Case ranges should be disjoint! 392 struct CaseCmp { 393 bool operator () (const Case& C1, const Case& C2) { 394 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 395 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 396 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 397 return CI1->getValue().slt(CI2->getValue()); 398 } 399 }; 400 401 struct CaseBitsCmp { 402 bool operator () (const CaseBits& C1, const CaseBits& C2) { 403 return C1.Bits > C2.Bits; 404 } 405 }; 406 407 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 408 409public: 410 // TLI - This is information that describes the available target features we 411 // need for lowering. This indicates when operations are unavailable, 412 // implemented with a libcall, etc. 413 TargetLowering &TLI; 414 SelectionDAG &DAG; 415 const TargetData *TD; 416 AliasAnalysis &AA; 417 418 /// SwitchCases - Vector of CaseBlock structures used to communicate 419 /// SwitchInst code generation information. 420 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 421 /// JTCases - Vector of JumpTable structures used to communicate 422 /// SwitchInst code generation information. 423 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 424 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 425 426 /// FuncInfo - Information about the function as a whole. 427 /// 428 FunctionLoweringInfo &FuncInfo; 429 430 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 431 AliasAnalysis &aa, 432 FunctionLoweringInfo &funcinfo) 433 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa), 434 FuncInfo(funcinfo) { 435 } 436 437 /// getRoot - Return the current virtual root of the Selection DAG. 438 /// 439 SDOperand getRoot() { 440 if (PendingLoads.empty()) 441 return DAG.getRoot(); 442 443 if (PendingLoads.size() == 1) { 444 SDOperand Root = PendingLoads[0]; 445 DAG.setRoot(Root); 446 PendingLoads.clear(); 447 return Root; 448 } 449 450 // Otherwise, we have to make a token factor node. 451 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 452 &PendingLoads[0], PendingLoads.size()); 453 PendingLoads.clear(); 454 DAG.setRoot(Root); 455 return Root; 456 } 457 458 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 459 460 void visit(Instruction &I) { visit(I.getOpcode(), I); } 461 462 void visit(unsigned Opcode, User &I) { 463 // Note: this doesn't use InstVisitor, because it has to work with 464 // ConstantExpr's in addition to instructions. 465 switch (Opcode) { 466 default: assert(0 && "Unknown instruction type encountered!"); 467 abort(); 468 // Build the switch statement using the Instruction.def file. 469#define HANDLE_INST(NUM, OPCODE, CLASS) \ 470 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 471#include "llvm/Instruction.def" 472 } 473 } 474 475 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 476 477 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 478 const Value *SV, SDOperand Root, 479 bool isVolatile, unsigned Alignment); 480 481 SDOperand getIntPtrConstant(uint64_t Val) { 482 return DAG.getConstant(Val, TLI.getPointerTy()); 483 } 484 485 SDOperand getValue(const Value *V); 486 487 void setValue(const Value *V, SDOperand NewN) { 488 SDOperand &N = NodeMap[V]; 489 assert(N.Val == 0 && "Already set a value for this node!"); 490 N = NewN; 491 } 492 493 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 494 std::set<unsigned> &OutputRegs, 495 std::set<unsigned> &InputRegs); 496 497 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 498 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 499 unsigned Opc); 500 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 501 void ExportFromCurrentBlock(Value *V); 502 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall, 503 MachineBasicBlock *LandingPad = NULL); 504 505 // Terminator instructions. 506 void visitRet(ReturnInst &I); 507 void visitBr(BranchInst &I); 508 void visitSwitch(SwitchInst &I); 509 void visitUnreachable(UnreachableInst &I) { /* noop */ } 510 511 // Helpers for visitSwitch 512 bool handleSmallSwitchRange(CaseRec& CR, 513 CaseRecVector& WorkList, 514 Value* SV, 515 MachineBasicBlock* Default); 516 bool handleJTSwitchCase(CaseRec& CR, 517 CaseRecVector& WorkList, 518 Value* SV, 519 MachineBasicBlock* Default); 520 bool handleBTSplitSwitchCase(CaseRec& CR, 521 CaseRecVector& WorkList, 522 Value* SV, 523 MachineBasicBlock* Default); 524 bool handleBitTestsSwitchCase(CaseRec& CR, 525 CaseRecVector& WorkList, 526 Value* SV, 527 MachineBasicBlock* Default); 528 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 529 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 530 void visitBitTestCase(MachineBasicBlock* NextMBB, 531 unsigned Reg, 532 SelectionDAGISel::BitTestCase &B); 533 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 534 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 535 SelectionDAGISel::JumpTableHeader &JTH); 536 537 // These all get lowered before this pass. 538 void visitInvoke(InvokeInst &I); 539 void visitUnwind(UnwindInst &I); 540 541 void visitBinary(User &I, unsigned OpCode); 542 void visitShift(User &I, unsigned Opcode); 543 void visitAdd(User &I) { 544 if (I.getType()->isFPOrFPVector()) 545 visitBinary(I, ISD::FADD); 546 else 547 visitBinary(I, ISD::ADD); 548 } 549 void visitSub(User &I); 550 void visitMul(User &I) { 551 if (I.getType()->isFPOrFPVector()) 552 visitBinary(I, ISD::FMUL); 553 else 554 visitBinary(I, ISD::MUL); 555 } 556 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 557 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 558 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 559 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 560 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 561 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 562 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 563 void visitOr (User &I) { visitBinary(I, ISD::OR); } 564 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 565 void visitShl (User &I) { visitShift(I, ISD::SHL); } 566 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 567 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 568 void visitICmp(User &I); 569 void visitFCmp(User &I); 570 // Visit the conversion instructions 571 void visitTrunc(User &I); 572 void visitZExt(User &I); 573 void visitSExt(User &I); 574 void visitFPTrunc(User &I); 575 void visitFPExt(User &I); 576 void visitFPToUI(User &I); 577 void visitFPToSI(User &I); 578 void visitUIToFP(User &I); 579 void visitSIToFP(User &I); 580 void visitPtrToInt(User &I); 581 void visitIntToPtr(User &I); 582 void visitBitCast(User &I); 583 584 void visitExtractElement(User &I); 585 void visitInsertElement(User &I); 586 void visitShuffleVector(User &I); 587 588 void visitGetElementPtr(User &I); 589 void visitSelect(User &I); 590 591 void visitMalloc(MallocInst &I); 592 void visitFree(FreeInst &I); 593 void visitAlloca(AllocaInst &I); 594 void visitLoad(LoadInst &I); 595 void visitStore(StoreInst &I); 596 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 597 void visitCall(CallInst &I); 598 void visitInlineAsm(CallSite CS); 599 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 600 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 601 602 void visitVAStart(CallInst &I); 603 void visitVAArg(VAArgInst &I); 604 void visitVAEnd(CallInst &I); 605 void visitVACopy(CallInst &I); 606 607 void visitMemIntrinsic(CallInst &I, unsigned Op); 608 609 void visitUserOp1(Instruction &I) { 610 assert(0 && "UserOp1 should not exist at instruction selection time!"); 611 abort(); 612 } 613 void visitUserOp2(Instruction &I) { 614 assert(0 && "UserOp2 should not exist at instruction selection time!"); 615 abort(); 616 } 617}; 618} // end namespace llvm 619 620 621/// getCopyFromParts - Create a value that contains the 622/// specified legal parts combined into the value they represent. 623static SDOperand getCopyFromParts(SelectionDAG &DAG, 624 const SDOperand *Parts, 625 unsigned NumParts, 626 MVT::ValueType PartVT, 627 MVT::ValueType ValueVT, 628 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 629 if (!MVT::isVector(ValueVT) || NumParts == 1) { 630 SDOperand Val = Parts[0]; 631 632 // If the value was expanded, copy from the top part. 633 if (NumParts > 1) { 634 assert(NumParts == 2 && 635 "Cannot expand to more than 2 elts yet!"); 636 SDOperand Hi = Parts[1]; 637 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 638 std::swap(Val, Hi); 639 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 640 } 641 642 // Otherwise, if the value was promoted or extended, truncate it to the 643 // appropriate type. 644 if (PartVT == ValueVT) 645 return Val; 646 647 if (MVT::isVector(PartVT)) { 648 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!"); 649 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 650 } 651 652 if (MVT::isVector(ValueVT)) { 653 assert(NumParts == 1 && 654 MVT::getVectorElementType(ValueVT) == PartVT && 655 MVT::getVectorNumElements(ValueVT) == 1 && 656 "Only trivial scalar-to-vector conversions should get here!"); 657 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val); 658 } 659 660 if (MVT::isInteger(PartVT) && 661 MVT::isInteger(ValueVT)) { 662 if (ValueVT < PartVT) { 663 // For a truncate, see if we have any information to 664 // indicate whether the truncated bits will always be 665 // zero or sign-extension. 666 if (AssertOp != ISD::DELETED_NODE) 667 Val = DAG.getNode(AssertOp, PartVT, Val, 668 DAG.getValueType(ValueVT)); 669 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 670 } else { 671 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 672 } 673 } 674 675 if (MVT::isFloatingPoint(PartVT) && 676 MVT::isFloatingPoint(ValueVT)) 677 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 678 679 if (MVT::getSizeInBits(PartVT) == 680 MVT::getSizeInBits(ValueVT)) 681 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 682 683 assert(0 && "Unknown mismatch!"); 684 } 685 686 // Handle a multi-element vector. 687 MVT::ValueType IntermediateVT, RegisterVT; 688 unsigned NumIntermediates; 689 unsigned NumRegs = 690 DAG.getTargetLoweringInfo() 691 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 692 RegisterVT); 693 694 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 695 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 696 assert(RegisterVT == Parts[0].getValueType() && 697 "Part type doesn't match part!"); 698 699 // Assemble the parts into intermediate operands. 700 SmallVector<SDOperand, 8> Ops(NumIntermediates); 701 if (NumIntermediates == NumParts) { 702 // If the register was not expanded, truncate or copy the value, 703 // as appropriate. 704 for (unsigned i = 0; i != NumParts; ++i) 705 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 706 PartVT, IntermediateVT); 707 } else if (NumParts > 0) { 708 // If the intermediate type was expanded, build the intermediate operands 709 // from the parts. 710 assert(NumParts % NumIntermediates == 0 && 711 "Must expand into a divisible number of parts!"); 712 unsigned Factor = NumParts / NumIntermediates; 713 for (unsigned i = 0; i != NumIntermediates; ++i) 714 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 715 PartVT, IntermediateVT); 716 } 717 718 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 719 // operands. 720 return DAG.getNode(MVT::isVector(IntermediateVT) ? 721 ISD::CONCAT_VECTORS : 722 ISD::BUILD_VECTOR, 723 ValueVT, &Ops[0], NumIntermediates); 724} 725 726/// getCopyToParts - Create a series of nodes that contain the 727/// specified value split into legal parts. 728static void getCopyToParts(SelectionDAG &DAG, 729 SDOperand Val, 730 SDOperand *Parts, 731 unsigned NumParts, 732 MVT::ValueType PartVT) { 733 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 734 MVT::ValueType PtrVT = TLI.getPointerTy(); 735 MVT::ValueType ValueVT = Val.getValueType(); 736 737 if (!MVT::isVector(ValueVT) || NumParts == 1) { 738 // If the value was expanded, copy from the parts. 739 if (NumParts > 1) { 740 for (unsigned i = 0; i != NumParts; ++i) 741 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val, 742 DAG.getConstant(i, PtrVT)); 743 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 744 std::reverse(Parts, Parts + NumParts); 745 return; 746 } 747 748 // If there is a single part and the types differ, this must be 749 // a promotion. 750 if (PartVT != ValueVT) { 751 if (MVT::isVector(PartVT)) { 752 assert(MVT::isVector(ValueVT) && 753 "Not a vector-vector cast?"); 754 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 755 } else if (MVT::isVector(ValueVT)) { 756 assert(NumParts == 1 && 757 MVT::getVectorElementType(ValueVT) == PartVT && 758 MVT::getVectorNumElements(ValueVT) == 1 && 759 "Only trivial vector-to-scalar conversions should get here!"); 760 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val, 761 DAG.getConstant(0, PtrVT)); 762 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 763 if (PartVT < ValueVT) 764 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val); 765 else 766 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val); 767 } else if (MVT::isFloatingPoint(PartVT) && 768 MVT::isFloatingPoint(ValueVT)) { 769 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 770 } else if (MVT::getSizeInBits(PartVT) == 771 MVT::getSizeInBits(ValueVT)) { 772 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 773 } else { 774 assert(0 && "Unknown mismatch!"); 775 } 776 } 777 Parts[0] = Val; 778 return; 779 } 780 781 // Handle a multi-element vector. 782 MVT::ValueType IntermediateVT, RegisterVT; 783 unsigned NumIntermediates; 784 unsigned NumRegs = 785 DAG.getTargetLoweringInfo() 786 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 787 RegisterVT); 788 unsigned NumElements = MVT::getVectorNumElements(ValueVT); 789 790 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 791 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 792 793 // Split the vector into intermediate operands. 794 SmallVector<SDOperand, 8> Ops(NumIntermediates); 795 for (unsigned i = 0; i != NumIntermediates; ++i) 796 if (MVT::isVector(IntermediateVT)) 797 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 798 IntermediateVT, Val, 799 DAG.getConstant(i * (NumElements / NumIntermediates), 800 PtrVT)); 801 else 802 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 803 IntermediateVT, Val, 804 DAG.getConstant(i, PtrVT)); 805 806 // Split the intermediate operands into legal parts. 807 if (NumParts == NumIntermediates) { 808 // If the register was not expanded, promote or copy the value, 809 // as appropriate. 810 for (unsigned i = 0; i != NumParts; ++i) 811 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 812 } else if (NumParts > 0) { 813 // If the intermediate type was expanded, split each the value into 814 // legal parts. 815 assert(NumParts % NumIntermediates == 0 && 816 "Must expand into a divisible number of parts!"); 817 unsigned Factor = NumParts / NumIntermediates; 818 for (unsigned i = 0; i != NumIntermediates; ++i) 819 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 820 } 821} 822 823 824SDOperand SelectionDAGLowering::getValue(const Value *V) { 825 SDOperand &N = NodeMap[V]; 826 if (N.Val) return N; 827 828 const Type *VTy = V->getType(); 829 MVT::ValueType VT = TLI.getValueType(VTy); 830 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 831 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 832 visit(CE->getOpcode(), *CE); 833 SDOperand N1 = NodeMap[V]; 834 assert(N1.Val && "visit didn't populate the ValueMap!"); 835 return N1; 836 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 837 return N = DAG.getGlobalAddress(GV, VT); 838 } else if (isa<ConstantPointerNull>(C)) { 839 return N = DAG.getConstant(0, TLI.getPointerTy()); 840 } else if (isa<UndefValue>(C)) { 841 if (!isa<VectorType>(VTy)) 842 return N = DAG.getNode(ISD::UNDEF, VT); 843 844 // Create a BUILD_VECTOR of undef nodes. 845 const VectorType *PTy = cast<VectorType>(VTy); 846 unsigned NumElements = PTy->getNumElements(); 847 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 848 849 SmallVector<SDOperand, 8> Ops; 850 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 851 852 // Create a VConstant node with generic Vector type. 853 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 854 return N = DAG.getNode(ISD::BUILD_VECTOR, VT, 855 &Ops[0], Ops.size()); 856 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 857 return N = DAG.getConstantFP(CFP->getValueAPF(), VT); 858 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 859 unsigned NumElements = PTy->getNumElements(); 860 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 861 862 // Now that we know the number and type of the elements, push a 863 // Constant or ConstantFP node onto the ops list for each element of 864 // the vector constant. 865 SmallVector<SDOperand, 8> Ops; 866 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 867 for (unsigned i = 0; i != NumElements; ++i) 868 Ops.push_back(getValue(CP->getOperand(i))); 869 } else { 870 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 871 SDOperand Op; 872 if (MVT::isFloatingPoint(PVT)) 873 Op = DAG.getConstantFP(0, PVT); 874 else 875 Op = DAG.getConstant(0, PVT); 876 Ops.assign(NumElements, Op); 877 } 878 879 // Create a BUILD_VECTOR node. 880 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 881 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], 882 Ops.size()); 883 } else { 884 // Canonicalize all constant ints to be unsigned. 885 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT); 886 } 887 } 888 889 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 890 std::map<const AllocaInst*, int>::iterator SI = 891 FuncInfo.StaticAllocaMap.find(AI); 892 if (SI != FuncInfo.StaticAllocaMap.end()) 893 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 894 } 895 896 unsigned InReg = FuncInfo.ValueMap[V]; 897 assert(InReg && "Value not in map!"); 898 899 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 900 unsigned NumRegs = TLI.getNumRegisters(VT); 901 902 std::vector<unsigned> Regs(NumRegs); 903 for (unsigned i = 0; i != NumRegs; ++i) 904 Regs[i] = InReg + i; 905 906 RegsForValue RFV(Regs, RegisterVT, VT); 907 SDOperand Chain = DAG.getEntryNode(); 908 909 return RFV.getCopyFromRegs(DAG, Chain, NULL); 910} 911 912 913void SelectionDAGLowering::visitRet(ReturnInst &I) { 914 if (I.getNumOperands() == 0) { 915 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 916 return; 917 } 918 SmallVector<SDOperand, 8> NewValues; 919 NewValues.push_back(getRoot()); 920 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 921 SDOperand RetOp = getValue(I.getOperand(i)); 922 923 // If this is an integer return value, we need to promote it ourselves to 924 // the full width of a register, since getCopyToParts and Legalize will use 925 // ANY_EXTEND rather than sign/zero. 926 // FIXME: C calling convention requires the return type to be promoted to 927 // at least 32-bit. But this is not necessary for non-C calling conventions. 928 if (MVT::isInteger(RetOp.getValueType()) && 929 RetOp.getValueType() < MVT::i64) { 930 MVT::ValueType TmpVT; 931 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 932 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 933 else 934 TmpVT = MVT::i32; 935 const Function *F = I.getParent()->getParent(); 936 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 937 if (F->paramHasAttr(0, ParamAttr::SExt)) 938 ExtendKind = ISD::SIGN_EXTEND; 939 if (F->paramHasAttr(0, ParamAttr::ZExt)) 940 ExtendKind = ISD::ZERO_EXTEND; 941 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp); 942 NewValues.push_back(RetOp); 943 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 944 } else { 945 MVT::ValueType VT = RetOp.getValueType(); 946 unsigned NumParts = TLI.getNumRegisters(VT); 947 MVT::ValueType PartVT = TLI.getRegisterType(VT); 948 SmallVector<SDOperand, 4> Parts(NumParts); 949 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT); 950 for (unsigned i = 0; i < NumParts; ++i) { 951 NewValues.push_back(Parts[i]); 952 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 953 } 954 } 955 } 956 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 957 &NewValues[0], NewValues.size())); 958} 959 960/// ExportFromCurrentBlock - If this condition isn't known to be exported from 961/// the current basic block, add it to ValueMap now so that we'll get a 962/// CopyTo/FromReg. 963void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 964 // No need to export constants. 965 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 966 967 // Already exported? 968 if (FuncInfo.isExportedInst(V)) return; 969 970 unsigned Reg = FuncInfo.InitializeRegForValue(V); 971 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 972} 973 974bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 975 const BasicBlock *FromBB) { 976 // The operands of the setcc have to be in this block. We don't know 977 // how to export them from some other block. 978 if (Instruction *VI = dyn_cast<Instruction>(V)) { 979 // Can export from current BB. 980 if (VI->getParent() == FromBB) 981 return true; 982 983 // Is already exported, noop. 984 return FuncInfo.isExportedInst(V); 985 } 986 987 // If this is an argument, we can export it if the BB is the entry block or 988 // if it is already exported. 989 if (isa<Argument>(V)) { 990 if (FromBB == &FromBB->getParent()->getEntryBlock()) 991 return true; 992 993 // Otherwise, can only export this if it is already exported. 994 return FuncInfo.isExportedInst(V); 995 } 996 997 // Otherwise, constants can always be exported. 998 return true; 999} 1000 1001static bool InBlock(const Value *V, const BasicBlock *BB) { 1002 if (const Instruction *I = dyn_cast<Instruction>(V)) 1003 return I->getParent() == BB; 1004 return true; 1005} 1006 1007/// FindMergedConditions - If Cond is an expression like 1008void SelectionDAGLowering::FindMergedConditions(Value *Cond, 1009 MachineBasicBlock *TBB, 1010 MachineBasicBlock *FBB, 1011 MachineBasicBlock *CurBB, 1012 unsigned Opc) { 1013 // If this node is not part of the or/and tree, emit it as a branch. 1014 Instruction *BOp = dyn_cast<Instruction>(Cond); 1015 1016 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1017 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1018 BOp->getParent() != CurBB->getBasicBlock() || 1019 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1020 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1021 const BasicBlock *BB = CurBB->getBasicBlock(); 1022 1023 // If the leaf of the tree is a comparison, merge the condition into 1024 // the caseblock. 1025 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1026 // The operands of the cmp have to be in this block. We don't know 1027 // how to export them from some other block. If this is the first block 1028 // of the sequence, no exporting is needed. 1029 (CurBB == CurMBB || 1030 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1031 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1032 BOp = cast<Instruction>(Cond); 1033 ISD::CondCode Condition; 1034 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1035 switch (IC->getPredicate()) { 1036 default: assert(0 && "Unknown icmp predicate opcode!"); 1037 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1038 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1039 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1040 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1041 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1042 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1043 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1044 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1045 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1046 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1047 } 1048 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1049 ISD::CondCode FPC, FOC; 1050 switch (FC->getPredicate()) { 1051 default: assert(0 && "Unknown fcmp predicate opcode!"); 1052 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1053 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1054 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1055 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1056 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1057 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1058 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1059 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 1060 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 1061 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1062 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1063 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1064 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1065 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1066 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1067 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1068 } 1069 if (FiniteOnlyFPMath()) 1070 Condition = FOC; 1071 else 1072 Condition = FPC; 1073 } else { 1074 Condition = ISD::SETEQ; // silence warning. 1075 assert(0 && "Unknown compare instruction"); 1076 } 1077 1078 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1079 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1080 SwitchCases.push_back(CB); 1081 return; 1082 } 1083 1084 // Create a CaseBlock record representing this branch. 1085 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1086 NULL, TBB, FBB, CurBB); 1087 SwitchCases.push_back(CB); 1088 return; 1089 } 1090 1091 1092 // Create TmpBB after CurBB. 1093 MachineFunction::iterator BBI = CurBB; 1094 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 1095 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 1096 1097 if (Opc == Instruction::Or) { 1098 // Codegen X | Y as: 1099 // jmp_if_X TBB 1100 // jmp TmpBB 1101 // TmpBB: 1102 // jmp_if_Y TBB 1103 // jmp FBB 1104 // 1105 1106 // Emit the LHS condition. 1107 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1108 1109 // Emit the RHS condition into TmpBB. 1110 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1111 } else { 1112 assert(Opc == Instruction::And && "Unknown merge op!"); 1113 // Codegen X & Y as: 1114 // jmp_if_X TmpBB 1115 // jmp FBB 1116 // TmpBB: 1117 // jmp_if_Y TBB 1118 // jmp FBB 1119 // 1120 // This requires creation of TmpBB after CurBB. 1121 1122 // Emit the LHS condition. 1123 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1124 1125 // Emit the RHS condition into TmpBB. 1126 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1127 } 1128} 1129 1130/// If the set of cases should be emitted as a series of branches, return true. 1131/// If we should emit this as a bunch of and/or'd together conditions, return 1132/// false. 1133static bool 1134ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1135 if (Cases.size() != 2) return true; 1136 1137 // If this is two comparisons of the same values or'd or and'd together, they 1138 // will get folded into a single comparison, so don't emit two blocks. 1139 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1140 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1141 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1142 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1143 return false; 1144 } 1145 1146 return true; 1147} 1148 1149void SelectionDAGLowering::visitBr(BranchInst &I) { 1150 // Update machine-CFG edges. 1151 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1152 1153 // Figure out which block is immediately after the current one. 1154 MachineBasicBlock *NextBlock = 0; 1155 MachineFunction::iterator BBI = CurMBB; 1156 if (++BBI != CurMBB->getParent()->end()) 1157 NextBlock = BBI; 1158 1159 if (I.isUnconditional()) { 1160 // If this is not a fall-through branch, emit the branch. 1161 if (Succ0MBB != NextBlock) 1162 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1163 DAG.getBasicBlock(Succ0MBB))); 1164 1165 // Update machine-CFG edges. 1166 CurMBB->addSuccessor(Succ0MBB); 1167 1168 return; 1169 } 1170 1171 // If this condition is one of the special cases we handle, do special stuff 1172 // now. 1173 Value *CondVal = I.getCondition(); 1174 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1175 1176 // If this is a series of conditions that are or'd or and'd together, emit 1177 // this as a sequence of branches instead of setcc's with and/or operations. 1178 // For example, instead of something like: 1179 // cmp A, B 1180 // C = seteq 1181 // cmp D, E 1182 // F = setle 1183 // or C, F 1184 // jnz foo 1185 // Emit: 1186 // cmp A, B 1187 // je foo 1188 // cmp D, E 1189 // jle foo 1190 // 1191 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1192 if (BOp->hasOneUse() && 1193 (BOp->getOpcode() == Instruction::And || 1194 BOp->getOpcode() == Instruction::Or)) { 1195 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1196 // If the compares in later blocks need to use values not currently 1197 // exported from this block, export them now. This block should always 1198 // be the first entry. 1199 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1200 1201 // Allow some cases to be rejected. 1202 if (ShouldEmitAsBranches(SwitchCases)) { 1203 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1204 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1205 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1206 } 1207 1208 // Emit the branch for this block. 1209 visitSwitchCase(SwitchCases[0]); 1210 SwitchCases.erase(SwitchCases.begin()); 1211 return; 1212 } 1213 1214 // Okay, we decided not to do this, remove any inserted MBB's and clear 1215 // SwitchCases. 1216 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1217 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1218 1219 SwitchCases.clear(); 1220 } 1221 } 1222 1223 // Create a CaseBlock record representing this branch. 1224 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1225 NULL, Succ0MBB, Succ1MBB, CurMBB); 1226 // Use visitSwitchCase to actually insert the fast branch sequence for this 1227 // cond branch. 1228 visitSwitchCase(CB); 1229} 1230 1231/// visitSwitchCase - Emits the necessary code to represent a single node in 1232/// the binary search tree resulting from lowering a switch instruction. 1233void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1234 SDOperand Cond; 1235 SDOperand CondLHS = getValue(CB.CmpLHS); 1236 1237 // Build the setcc now. 1238 if (CB.CmpMHS == NULL) { 1239 // Fold "(X == true)" to X and "(X == false)" to !X to 1240 // handle common cases produced by branch lowering. 1241 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1242 Cond = CondLHS; 1243 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1244 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1245 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1246 } else 1247 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1248 } else { 1249 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1250 1251 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1252 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1253 1254 SDOperand CmpOp = getValue(CB.CmpMHS); 1255 MVT::ValueType VT = CmpOp.getValueType(); 1256 1257 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1258 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1259 } else { 1260 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1261 Cond = DAG.getSetCC(MVT::i1, SUB, 1262 DAG.getConstant(High-Low, VT), ISD::SETULE); 1263 } 1264 1265 } 1266 1267 // Set NextBlock to be the MBB immediately after the current one, if any. 1268 // This is used to avoid emitting unnecessary branches to the next block. 1269 MachineBasicBlock *NextBlock = 0; 1270 MachineFunction::iterator BBI = CurMBB; 1271 if (++BBI != CurMBB->getParent()->end()) 1272 NextBlock = BBI; 1273 1274 // If the lhs block is the next block, invert the condition so that we can 1275 // fall through to the lhs instead of the rhs block. 1276 if (CB.TrueBB == NextBlock) { 1277 std::swap(CB.TrueBB, CB.FalseBB); 1278 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1279 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1280 } 1281 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1282 DAG.getBasicBlock(CB.TrueBB)); 1283 if (CB.FalseBB == NextBlock) 1284 DAG.setRoot(BrCond); 1285 else 1286 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1287 DAG.getBasicBlock(CB.FalseBB))); 1288 // Update successor info 1289 CurMBB->addSuccessor(CB.TrueBB); 1290 CurMBB->addSuccessor(CB.FalseBB); 1291} 1292 1293/// visitJumpTable - Emit JumpTable node in the current MBB 1294void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1295 // Emit the code for the jump table 1296 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1297 MVT::ValueType PTy = TLI.getPointerTy(); 1298 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1299 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1300 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1301 Table, Index)); 1302 return; 1303} 1304 1305/// visitJumpTableHeader - This function emits necessary code to produce index 1306/// in the JumpTable from switch case. 1307void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1308 SelectionDAGISel::JumpTableHeader &JTH) { 1309 // Subtract the lowest switch case value from the value being switched on 1310 // and conditional branch to default mbb if the result is greater than the 1311 // difference between smallest and largest cases. 1312 SDOperand SwitchOp = getValue(JTH.SValue); 1313 MVT::ValueType VT = SwitchOp.getValueType(); 1314 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1315 DAG.getConstant(JTH.First, VT)); 1316 1317 // The SDNode we just created, which holds the value being switched on 1318 // minus the the smallest case value, needs to be copied to a virtual 1319 // register so it can be used as an index into the jump table in a 1320 // subsequent basic block. This value may be smaller or larger than the 1321 // target's pointer type, and therefore require extension or truncating. 1322 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 1323 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1324 else 1325 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1326 1327 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1328 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1329 JT.Reg = JumpTableReg; 1330 1331 // Emit the range check for the jump table, and branch to the default 1332 // block for the switch statement if the value being switched on exceeds 1333 // the largest case in the switch. 1334 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1335 DAG.getConstant(JTH.Last-JTH.First,VT), 1336 ISD::SETUGT); 1337 1338 // Set NextBlock to be the MBB immediately after the current one, if any. 1339 // This is used to avoid emitting unnecessary branches to the next block. 1340 MachineBasicBlock *NextBlock = 0; 1341 MachineFunction::iterator BBI = CurMBB; 1342 if (++BBI != CurMBB->getParent()->end()) 1343 NextBlock = BBI; 1344 1345 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1346 DAG.getBasicBlock(JT.Default)); 1347 1348 if (JT.MBB == NextBlock) 1349 DAG.setRoot(BrCond); 1350 else 1351 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1352 DAG.getBasicBlock(JT.MBB))); 1353 1354 return; 1355} 1356 1357/// visitBitTestHeader - This function emits necessary code to produce value 1358/// suitable for "bit tests" 1359void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1360 // Subtract the minimum value 1361 SDOperand SwitchOp = getValue(B.SValue); 1362 MVT::ValueType VT = SwitchOp.getValueType(); 1363 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1364 DAG.getConstant(B.First, VT)); 1365 1366 // Check range 1367 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1368 DAG.getConstant(B.Range, VT), 1369 ISD::SETUGT); 1370 1371 SDOperand ShiftOp; 1372 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy())) 1373 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1374 else 1375 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1376 1377 // Make desired shift 1378 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1379 DAG.getConstant(1, TLI.getPointerTy()), 1380 ShiftOp); 1381 1382 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1383 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1384 B.Reg = SwitchReg; 1385 1386 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1387 DAG.getBasicBlock(B.Default)); 1388 1389 // Set NextBlock to be the MBB immediately after the current one, if any. 1390 // This is used to avoid emitting unnecessary branches to the next block. 1391 MachineBasicBlock *NextBlock = 0; 1392 MachineFunction::iterator BBI = CurMBB; 1393 if (++BBI != CurMBB->getParent()->end()) 1394 NextBlock = BBI; 1395 1396 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1397 if (MBB == NextBlock) 1398 DAG.setRoot(BrRange); 1399 else 1400 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1401 DAG.getBasicBlock(MBB))); 1402 1403 CurMBB->addSuccessor(B.Default); 1404 CurMBB->addSuccessor(MBB); 1405 1406 return; 1407} 1408 1409/// visitBitTestCase - this function produces one "bit test" 1410void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1411 unsigned Reg, 1412 SelectionDAGISel::BitTestCase &B) { 1413 // Emit bit tests and jumps 1414 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1415 1416 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1417 SwitchVal, 1418 DAG.getConstant(B.Mask, 1419 TLI.getPointerTy())); 1420 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, 1421 DAG.getConstant(0, TLI.getPointerTy()), 1422 ISD::SETNE); 1423 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1424 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1425 1426 // Set NextBlock to be the MBB immediately after the current one, if any. 1427 // This is used to avoid emitting unnecessary branches to the next block. 1428 MachineBasicBlock *NextBlock = 0; 1429 MachineFunction::iterator BBI = CurMBB; 1430 if (++BBI != CurMBB->getParent()->end()) 1431 NextBlock = BBI; 1432 1433 if (NextMBB == NextBlock) 1434 DAG.setRoot(BrAnd); 1435 else 1436 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1437 DAG.getBasicBlock(NextMBB))); 1438 1439 CurMBB->addSuccessor(B.TargetBB); 1440 CurMBB->addSuccessor(NextMBB); 1441 1442 return; 1443} 1444 1445void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1446 // Retrieve successors. 1447 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1448 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1449 1450 if (isa<InlineAsm>(I.getCalledValue())) 1451 visitInlineAsm(&I); 1452 else 1453 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad); 1454 1455 // If the value of the invoke is used outside of its defining block, make it 1456 // available as a virtual register. 1457 if (!I.use_empty()) { 1458 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1459 if (VMI != FuncInfo.ValueMap.end()) 1460 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second)); 1461 } 1462 1463 // Drop into normal successor. 1464 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1465 DAG.getBasicBlock(Return))); 1466 1467 // Update successor info 1468 CurMBB->addSuccessor(Return); 1469 CurMBB->addSuccessor(LandingPad); 1470} 1471 1472void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1473} 1474 1475/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1476/// small case ranges). 1477bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1478 CaseRecVector& WorkList, 1479 Value* SV, 1480 MachineBasicBlock* Default) { 1481 Case& BackCase = *(CR.Range.second-1); 1482 1483 // Size is the number of Cases represented by this range. 1484 unsigned Size = CR.Range.second - CR.Range.first; 1485 if (Size > 3) 1486 return false; 1487 1488 // Get the MachineFunction which holds the current MBB. This is used when 1489 // inserting any additional MBBs necessary to represent the switch. 1490 MachineFunction *CurMF = CurMBB->getParent(); 1491 1492 // Figure out which block is immediately after the current one. 1493 MachineBasicBlock *NextBlock = 0; 1494 MachineFunction::iterator BBI = CR.CaseBB; 1495 1496 if (++BBI != CurMBB->getParent()->end()) 1497 NextBlock = BBI; 1498 1499 // TODO: If any two of the cases has the same destination, and if one value 1500 // is the same as the other, but has one bit unset that the other has set, 1501 // use bit manipulation to do two compares at once. For example: 1502 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1503 1504 // Rearrange the case blocks so that the last one falls through if possible. 1505 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1506 // The last case block won't fall through into 'NextBlock' if we emit the 1507 // branches in this order. See if rearranging a case value would help. 1508 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1509 if (I->BB == NextBlock) { 1510 std::swap(*I, BackCase); 1511 break; 1512 } 1513 } 1514 } 1515 1516 // Create a CaseBlock record representing a conditional branch to 1517 // the Case's target mbb if the value being switched on SV is equal 1518 // to C. 1519 MachineBasicBlock *CurBlock = CR.CaseBB; 1520 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1521 MachineBasicBlock *FallThrough; 1522 if (I != E-1) { 1523 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1524 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1525 } else { 1526 // If the last case doesn't match, go to the default block. 1527 FallThrough = Default; 1528 } 1529 1530 Value *RHS, *LHS, *MHS; 1531 ISD::CondCode CC; 1532 if (I->High == I->Low) { 1533 // This is just small small case range :) containing exactly 1 case 1534 CC = ISD::SETEQ; 1535 LHS = SV; RHS = I->High; MHS = NULL; 1536 } else { 1537 CC = ISD::SETLE; 1538 LHS = I->Low; MHS = SV; RHS = I->High; 1539 } 1540 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1541 I->BB, FallThrough, CurBlock); 1542 1543 // If emitting the first comparison, just call visitSwitchCase to emit the 1544 // code into the current block. Otherwise, push the CaseBlock onto the 1545 // vector to be later processed by SDISel, and insert the node's MBB 1546 // before the next MBB. 1547 if (CurBlock == CurMBB) 1548 visitSwitchCase(CB); 1549 else 1550 SwitchCases.push_back(CB); 1551 1552 CurBlock = FallThrough; 1553 } 1554 1555 return true; 1556} 1557 1558static inline bool areJTsAllowed(const TargetLowering &TLI) { 1559 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1560 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1561} 1562 1563/// handleJTSwitchCase - Emit jumptable for current switch case range 1564bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1565 CaseRecVector& WorkList, 1566 Value* SV, 1567 MachineBasicBlock* Default) { 1568 Case& FrontCase = *CR.Range.first; 1569 Case& BackCase = *(CR.Range.second-1); 1570 1571 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1572 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1573 1574 uint64_t TSize = 0; 1575 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1576 I!=E; ++I) 1577 TSize += I->size(); 1578 1579 if (!areJTsAllowed(TLI) || TSize <= 3) 1580 return false; 1581 1582 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1583 if (Density < 0.4) 1584 return false; 1585 1586 DOUT << "Lowering jump table\n" 1587 << "First entry: " << First << ". Last entry: " << Last << "\n" 1588 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1589 1590 // Get the MachineFunction which holds the current MBB. This is used when 1591 // inserting any additional MBBs necessary to represent the switch. 1592 MachineFunction *CurMF = CurMBB->getParent(); 1593 1594 // Figure out which block is immediately after the current one. 1595 MachineBasicBlock *NextBlock = 0; 1596 MachineFunction::iterator BBI = CR.CaseBB; 1597 1598 if (++BBI != CurMBB->getParent()->end()) 1599 NextBlock = BBI; 1600 1601 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1602 1603 // Create a new basic block to hold the code for loading the address 1604 // of the jump table, and jumping to it. Update successor information; 1605 // we will either branch to the default case for the switch, or the jump 1606 // table. 1607 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1608 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1609 CR.CaseBB->addSuccessor(Default); 1610 CR.CaseBB->addSuccessor(JumpTableBB); 1611 1612 // Build a vector of destination BBs, corresponding to each target 1613 // of the jump table. If the value of the jump table slot corresponds to 1614 // a case statement, push the case's BB onto the vector, otherwise, push 1615 // the default BB. 1616 std::vector<MachineBasicBlock*> DestBBs; 1617 int64_t TEI = First; 1618 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1619 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1620 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1621 1622 if ((Low <= TEI) && (TEI <= High)) { 1623 DestBBs.push_back(I->BB); 1624 if (TEI==High) 1625 ++I; 1626 } else { 1627 DestBBs.push_back(Default); 1628 } 1629 } 1630 1631 // Update successor info. Add one edge to each unique successor. 1632 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1633 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1634 E = DestBBs.end(); I != E; ++I) { 1635 if (!SuccsHandled[(*I)->getNumber()]) { 1636 SuccsHandled[(*I)->getNumber()] = true; 1637 JumpTableBB->addSuccessor(*I); 1638 } 1639 } 1640 1641 // Create a jump table index for this jump table, or return an existing 1642 // one. 1643 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1644 1645 // Set the jump table information so that we can codegen it as a second 1646 // MachineBasicBlock 1647 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1648 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1649 (CR.CaseBB == CurMBB)); 1650 if (CR.CaseBB == CurMBB) 1651 visitJumpTableHeader(JT, JTH); 1652 1653 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1654 1655 return true; 1656} 1657 1658/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1659/// 2 subtrees. 1660bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1661 CaseRecVector& WorkList, 1662 Value* SV, 1663 MachineBasicBlock* Default) { 1664 // Get the MachineFunction which holds the current MBB. This is used when 1665 // inserting any additional MBBs necessary to represent the switch. 1666 MachineFunction *CurMF = CurMBB->getParent(); 1667 1668 // Figure out which block is immediately after the current one. 1669 MachineBasicBlock *NextBlock = 0; 1670 MachineFunction::iterator BBI = CR.CaseBB; 1671 1672 if (++BBI != CurMBB->getParent()->end()) 1673 NextBlock = BBI; 1674 1675 Case& FrontCase = *CR.Range.first; 1676 Case& BackCase = *(CR.Range.second-1); 1677 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1678 1679 // Size is the number of Cases represented by this range. 1680 unsigned Size = CR.Range.second - CR.Range.first; 1681 1682 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1683 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1684 double FMetric = 0; 1685 CaseItr Pivot = CR.Range.first + Size/2; 1686 1687 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1688 // (heuristically) allow us to emit JumpTable's later. 1689 uint64_t TSize = 0; 1690 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1691 I!=E; ++I) 1692 TSize += I->size(); 1693 1694 uint64_t LSize = FrontCase.size(); 1695 uint64_t RSize = TSize-LSize; 1696 DOUT << "Selecting best pivot: \n" 1697 << "First: " << First << ", Last: " << Last <<"\n" 1698 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1699 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1700 J!=E; ++I, ++J) { 1701 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1702 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1703 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1704 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1705 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1706 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1707 // Should always split in some non-trivial place 1708 DOUT <<"=>Step\n" 1709 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1710 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1711 << "Metric: " << Metric << "\n"; 1712 if (FMetric < Metric) { 1713 Pivot = J; 1714 FMetric = Metric; 1715 DOUT << "Current metric set to: " << FMetric << "\n"; 1716 } 1717 1718 LSize += J->size(); 1719 RSize -= J->size(); 1720 } 1721 if (areJTsAllowed(TLI)) { 1722 // If our case is dense we *really* should handle it earlier! 1723 assert((FMetric > 0) && "Should handle dense range earlier!"); 1724 } else { 1725 Pivot = CR.Range.first + Size/2; 1726 } 1727 1728 CaseRange LHSR(CR.Range.first, Pivot); 1729 CaseRange RHSR(Pivot, CR.Range.second); 1730 Constant *C = Pivot->Low; 1731 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1732 1733 // We know that we branch to the LHS if the Value being switched on is 1734 // less than the Pivot value, C. We use this to optimize our binary 1735 // tree a bit, by recognizing that if SV is greater than or equal to the 1736 // LHS's Case Value, and that Case Value is exactly one less than the 1737 // Pivot's Value, then we can branch directly to the LHS's Target, 1738 // rather than creating a leaf node for it. 1739 if ((LHSR.second - LHSR.first) == 1 && 1740 LHSR.first->High == CR.GE && 1741 cast<ConstantInt>(C)->getSExtValue() == 1742 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1743 TrueBB = LHSR.first->BB; 1744 } else { 1745 TrueBB = new MachineBasicBlock(LLVMBB); 1746 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1747 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1748 } 1749 1750 // Similar to the optimization above, if the Value being switched on is 1751 // known to be less than the Constant CR.LT, and the current Case Value 1752 // is CR.LT - 1, then we can branch directly to the target block for 1753 // the current Case Value, rather than emitting a RHS leaf node for it. 1754 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1755 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1756 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1757 FalseBB = RHSR.first->BB; 1758 } else { 1759 FalseBB = new MachineBasicBlock(LLVMBB); 1760 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1761 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1762 } 1763 1764 // Create a CaseBlock record representing a conditional branch to 1765 // the LHS node if the value being switched on SV is less than C. 1766 // Otherwise, branch to LHS. 1767 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1768 TrueBB, FalseBB, CR.CaseBB); 1769 1770 if (CR.CaseBB == CurMBB) 1771 visitSwitchCase(CB); 1772 else 1773 SwitchCases.push_back(CB); 1774 1775 return true; 1776} 1777 1778/// handleBitTestsSwitchCase - if current case range has few destination and 1779/// range span less, than machine word bitwidth, encode case range into series 1780/// of masks and emit bit tests with these masks. 1781bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1782 CaseRecVector& WorkList, 1783 Value* SV, 1784 MachineBasicBlock* Default){ 1785 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); 1786 1787 Case& FrontCase = *CR.Range.first; 1788 Case& BackCase = *(CR.Range.second-1); 1789 1790 // Get the MachineFunction which holds the current MBB. This is used when 1791 // inserting any additional MBBs necessary to represent the switch. 1792 MachineFunction *CurMF = CurMBB->getParent(); 1793 1794 unsigned numCmps = 0; 1795 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1796 I!=E; ++I) { 1797 // Single case counts one, case range - two. 1798 if (I->Low == I->High) 1799 numCmps +=1; 1800 else 1801 numCmps +=2; 1802 } 1803 1804 // Count unique destinations 1805 SmallSet<MachineBasicBlock*, 4> Dests; 1806 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1807 Dests.insert(I->BB); 1808 if (Dests.size() > 3) 1809 // Don't bother the code below, if there are too much unique destinations 1810 return false; 1811 } 1812 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1813 << "Total number of comparisons: " << numCmps << "\n"; 1814 1815 // Compute span of values. 1816 Constant* minValue = FrontCase.Low; 1817 Constant* maxValue = BackCase.High; 1818 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1819 cast<ConstantInt>(minValue)->getSExtValue(); 1820 DOUT << "Compare range: " << range << "\n" 1821 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1822 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1823 1824 if (range>=IntPtrBits || 1825 (!(Dests.size() == 1 && numCmps >= 3) && 1826 !(Dests.size() == 2 && numCmps >= 5) && 1827 !(Dests.size() >= 3 && numCmps >= 6))) 1828 return false; 1829 1830 DOUT << "Emitting bit tests\n"; 1831 int64_t lowBound = 0; 1832 1833 // Optimize the case where all the case values fit in a 1834 // word without having to subtract minValue. In this case, 1835 // we can optimize away the subtraction. 1836 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1837 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1838 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1839 } else { 1840 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1841 } 1842 1843 CaseBitsVector CasesBits; 1844 unsigned i, count = 0; 1845 1846 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1847 MachineBasicBlock* Dest = I->BB; 1848 for (i = 0; i < count; ++i) 1849 if (Dest == CasesBits[i].BB) 1850 break; 1851 1852 if (i == count) { 1853 assert((count < 3) && "Too much destinations to test!"); 1854 CasesBits.push_back(CaseBits(0, Dest, 0)); 1855 count++; 1856 } 1857 1858 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1859 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1860 1861 for (uint64_t j = lo; j <= hi; j++) { 1862 CasesBits[i].Mask |= 1ULL << j; 1863 CasesBits[i].Bits++; 1864 } 1865 1866 } 1867 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1868 1869 SelectionDAGISel::BitTestInfo BTC; 1870 1871 // Figure out which block is immediately after the current one. 1872 MachineFunction::iterator BBI = CR.CaseBB; 1873 ++BBI; 1874 1875 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1876 1877 DOUT << "Cases:\n"; 1878 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1879 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1880 << ", BB: " << CasesBits[i].BB << "\n"; 1881 1882 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1883 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1884 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1885 CaseBB, 1886 CasesBits[i].BB)); 1887 } 1888 1889 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 1890 -1U, (CR.CaseBB == CurMBB), 1891 CR.CaseBB, Default, BTC); 1892 1893 if (CR.CaseBB == CurMBB) 1894 visitBitTestHeader(BTB); 1895 1896 BitTestCases.push_back(BTB); 1897 1898 return true; 1899} 1900 1901 1902// Clusterify - Transform simple list of Cases into list of CaseRange's 1903unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 1904 const SwitchInst& SI) { 1905 unsigned numCmps = 0; 1906 1907 // Start with "simple" cases 1908 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 1909 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1910 Cases.push_back(Case(SI.getSuccessorValue(i), 1911 SI.getSuccessorValue(i), 1912 SMBB)); 1913 } 1914 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 1915 1916 // Merge case into clusters 1917 if (Cases.size()>=2) 1918 // Must recompute end() each iteration because it may be 1919 // invalidated by erase if we hold on to it 1920 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 1921 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 1922 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 1923 MachineBasicBlock* nextBB = J->BB; 1924 MachineBasicBlock* currentBB = I->BB; 1925 1926 // If the two neighboring cases go to the same destination, merge them 1927 // into a single case. 1928 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 1929 I->High = J->High; 1930 J = Cases.erase(J); 1931 } else { 1932 I = J++; 1933 } 1934 } 1935 1936 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1937 if (I->Low != I->High) 1938 // A range counts double, since it requires two compares. 1939 ++numCmps; 1940 } 1941 1942 return numCmps; 1943} 1944 1945void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 1946 // Figure out which block is immediately after the current one. 1947 MachineBasicBlock *NextBlock = 0; 1948 MachineFunction::iterator BBI = CurMBB; 1949 1950 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 1951 1952 // If there is only the default destination, branch to it if it is not the 1953 // next basic block. Otherwise, just fall through. 1954 if (SI.getNumOperands() == 2) { 1955 // Update machine-CFG edges. 1956 1957 // If this is not a fall-through branch, emit the branch. 1958 if (Default != NextBlock) 1959 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1960 DAG.getBasicBlock(Default))); 1961 1962 CurMBB->addSuccessor(Default); 1963 return; 1964 } 1965 1966 // If there are any non-default case statements, create a vector of Cases 1967 // representing each one, and sort the vector so that we can efficiently 1968 // create a binary search tree from them. 1969 CaseVector Cases; 1970 unsigned numCmps = Clusterify(Cases, SI); 1971 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 1972 << ". Total compares: " << numCmps << "\n"; 1973 1974 // Get the Value to be switched on and default basic blocks, which will be 1975 // inserted into CaseBlock records, representing basic blocks in the binary 1976 // search tree. 1977 Value *SV = SI.getOperand(0); 1978 1979 // Push the initial CaseRec onto the worklist 1980 CaseRecVector WorkList; 1981 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1982 1983 while (!WorkList.empty()) { 1984 // Grab a record representing a case range to process off the worklist 1985 CaseRec CR = WorkList.back(); 1986 WorkList.pop_back(); 1987 1988 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 1989 continue; 1990 1991 // If the range has few cases (two or less) emit a series of specific 1992 // tests. 1993 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 1994 continue; 1995 1996 // If the switch has more than 5 blocks, and at least 40% dense, and the 1997 // target supports indirect branches, then emit a jump table rather than 1998 // lowering the switch to a binary tree of conditional branches. 1999 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 2000 continue; 2001 2002 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2003 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2004 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 2005 } 2006} 2007 2008 2009void SelectionDAGLowering::visitSub(User &I) { 2010 // -0.0 - X --> fneg 2011 const Type *Ty = I.getType(); 2012 if (isa<VectorType>(Ty)) { 2013 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2014 const VectorType *DestTy = cast<VectorType>(I.getType()); 2015 const Type *ElTy = DestTy->getElementType(); 2016 if (ElTy->isFloatingPoint()) { 2017 unsigned VL = DestTy->getNumElements(); 2018 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2019 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2020 if (CV == CNZ) { 2021 SDOperand Op2 = getValue(I.getOperand(1)); 2022 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2023 return; 2024 } 2025 } 2026 } 2027 } 2028 if (Ty->isFloatingPoint()) { 2029 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2030 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2031 SDOperand Op2 = getValue(I.getOperand(1)); 2032 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2033 return; 2034 } 2035 } 2036 2037 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2038} 2039 2040void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2041 SDOperand Op1 = getValue(I.getOperand(0)); 2042 SDOperand Op2 = getValue(I.getOperand(1)); 2043 2044 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2045} 2046 2047void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2048 SDOperand Op1 = getValue(I.getOperand(0)); 2049 SDOperand Op2 = getValue(I.getOperand(1)); 2050 2051 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) < 2052 MVT::getSizeInBits(Op2.getValueType())) 2053 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2054 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 2055 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2056 2057 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2058} 2059 2060void SelectionDAGLowering::visitICmp(User &I) { 2061 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2062 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2063 predicate = IC->getPredicate(); 2064 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2065 predicate = ICmpInst::Predicate(IC->getPredicate()); 2066 SDOperand Op1 = getValue(I.getOperand(0)); 2067 SDOperand Op2 = getValue(I.getOperand(1)); 2068 ISD::CondCode Opcode; 2069 switch (predicate) { 2070 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2071 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2072 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2073 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2074 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2075 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2076 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2077 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2078 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2079 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2080 default: 2081 assert(!"Invalid ICmp predicate value"); 2082 Opcode = ISD::SETEQ; 2083 break; 2084 } 2085 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2086} 2087 2088void SelectionDAGLowering::visitFCmp(User &I) { 2089 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2090 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2091 predicate = FC->getPredicate(); 2092 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2093 predicate = FCmpInst::Predicate(FC->getPredicate()); 2094 SDOperand Op1 = getValue(I.getOperand(0)); 2095 SDOperand Op2 = getValue(I.getOperand(1)); 2096 ISD::CondCode Condition, FOC, FPC; 2097 switch (predicate) { 2098 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2099 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2100 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2101 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2102 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2103 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2104 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2105 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 2106 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 2107 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2108 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2109 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2110 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2111 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2112 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2113 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2114 default: 2115 assert(!"Invalid FCmp predicate value"); 2116 FOC = FPC = ISD::SETFALSE; 2117 break; 2118 } 2119 if (FiniteOnlyFPMath()) 2120 Condition = FOC; 2121 else 2122 Condition = FPC; 2123 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2124} 2125 2126void SelectionDAGLowering::visitSelect(User &I) { 2127 SDOperand Cond = getValue(I.getOperand(0)); 2128 SDOperand TrueVal = getValue(I.getOperand(1)); 2129 SDOperand FalseVal = getValue(I.getOperand(2)); 2130 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2131 TrueVal, FalseVal)); 2132} 2133 2134 2135void SelectionDAGLowering::visitTrunc(User &I) { 2136 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2137 SDOperand N = getValue(I.getOperand(0)); 2138 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2139 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2140} 2141 2142void SelectionDAGLowering::visitZExt(User &I) { 2143 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2144 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2145 SDOperand N = getValue(I.getOperand(0)); 2146 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2147 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2148} 2149 2150void SelectionDAGLowering::visitSExt(User &I) { 2151 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2152 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2153 SDOperand N = getValue(I.getOperand(0)); 2154 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2155 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2156} 2157 2158void SelectionDAGLowering::visitFPTrunc(User &I) { 2159 // FPTrunc is never a no-op cast, no need to check 2160 SDOperand N = getValue(I.getOperand(0)); 2161 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2162 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 2163} 2164 2165void SelectionDAGLowering::visitFPExt(User &I){ 2166 // FPTrunc is never a no-op cast, no need to check 2167 SDOperand N = getValue(I.getOperand(0)); 2168 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2169 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2170} 2171 2172void SelectionDAGLowering::visitFPToUI(User &I) { 2173 // FPToUI is never a no-op cast, no need to check 2174 SDOperand N = getValue(I.getOperand(0)); 2175 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2176 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2177} 2178 2179void SelectionDAGLowering::visitFPToSI(User &I) { 2180 // FPToSI is never a no-op cast, no need to check 2181 SDOperand N = getValue(I.getOperand(0)); 2182 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2183 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2184} 2185 2186void SelectionDAGLowering::visitUIToFP(User &I) { 2187 // UIToFP is never a no-op cast, no need to check 2188 SDOperand N = getValue(I.getOperand(0)); 2189 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2190 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2191} 2192 2193void SelectionDAGLowering::visitSIToFP(User &I){ 2194 // UIToFP is never a no-op cast, no need to check 2195 SDOperand N = getValue(I.getOperand(0)); 2196 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2197 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2198} 2199 2200void SelectionDAGLowering::visitPtrToInt(User &I) { 2201 // What to do depends on the size of the integer and the size of the pointer. 2202 // We can either truncate, zero extend, or no-op, accordingly. 2203 SDOperand N = getValue(I.getOperand(0)); 2204 MVT::ValueType SrcVT = N.getValueType(); 2205 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2206 SDOperand Result; 2207 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2208 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2209 else 2210 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2211 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2212 setValue(&I, Result); 2213} 2214 2215void SelectionDAGLowering::visitIntToPtr(User &I) { 2216 // What to do depends on the size of the integer and the size of the pointer. 2217 // We can either truncate, zero extend, or no-op, accordingly. 2218 SDOperand N = getValue(I.getOperand(0)); 2219 MVT::ValueType SrcVT = N.getValueType(); 2220 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2221 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2222 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2223 else 2224 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2225 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2226} 2227 2228void SelectionDAGLowering::visitBitCast(User &I) { 2229 SDOperand N = getValue(I.getOperand(0)); 2230 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2231 2232 // BitCast assures us that source and destination are the same size so this 2233 // is either a BIT_CONVERT or a no-op. 2234 if (DestVT != N.getValueType()) 2235 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2236 else 2237 setValue(&I, N); // noop cast. 2238} 2239 2240void SelectionDAGLowering::visitInsertElement(User &I) { 2241 SDOperand InVec = getValue(I.getOperand(0)); 2242 SDOperand InVal = getValue(I.getOperand(1)); 2243 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2244 getValue(I.getOperand(2))); 2245 2246 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2247 TLI.getValueType(I.getType()), 2248 InVec, InVal, InIdx)); 2249} 2250 2251void SelectionDAGLowering::visitExtractElement(User &I) { 2252 SDOperand InVec = getValue(I.getOperand(0)); 2253 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2254 getValue(I.getOperand(1))); 2255 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2256 TLI.getValueType(I.getType()), InVec, InIdx)); 2257} 2258 2259void SelectionDAGLowering::visitShuffleVector(User &I) { 2260 SDOperand V1 = getValue(I.getOperand(0)); 2261 SDOperand V2 = getValue(I.getOperand(1)); 2262 SDOperand Mask = getValue(I.getOperand(2)); 2263 2264 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2265 TLI.getValueType(I.getType()), 2266 V1, V2, Mask)); 2267} 2268 2269 2270void SelectionDAGLowering::visitGetElementPtr(User &I) { 2271 SDOperand N = getValue(I.getOperand(0)); 2272 const Type *Ty = I.getOperand(0)->getType(); 2273 2274 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2275 OI != E; ++OI) { 2276 Value *Idx = *OI; 2277 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2278 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2279 if (Field) { 2280 // N = N + Offset 2281 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2282 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2283 getIntPtrConstant(Offset)); 2284 } 2285 Ty = StTy->getElementType(Field); 2286 } else { 2287 Ty = cast<SequentialType>(Ty)->getElementType(); 2288 2289 // If this is a constant subscript, handle it quickly. 2290 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2291 if (CI->getZExtValue() == 0) continue; 2292 uint64_t Offs = 2293 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2294 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 2295 continue; 2296 } 2297 2298 // N = N + Idx * ElementSize; 2299 uint64_t ElementSize = TD->getABITypeSize(Ty); 2300 SDOperand IdxN = getValue(Idx); 2301 2302 // If the index is smaller or larger than intptr_t, truncate or extend 2303 // it. 2304 if (IdxN.getValueType() < N.getValueType()) { 2305 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2306 } else if (IdxN.getValueType() > N.getValueType()) 2307 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2308 2309 // If this is a multiply by a power of two, turn it into a shl 2310 // immediately. This is a very common case. 2311 if (isPowerOf2_64(ElementSize)) { 2312 unsigned Amt = Log2_64(ElementSize); 2313 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2314 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2315 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2316 continue; 2317 } 2318 2319 SDOperand Scale = getIntPtrConstant(ElementSize); 2320 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2321 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2322 } 2323 } 2324 setValue(&I, N); 2325} 2326 2327void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2328 // If this is a fixed sized alloca in the entry block of the function, 2329 // allocate it statically on the stack. 2330 if (FuncInfo.StaticAllocaMap.count(&I)) 2331 return; // getValue will auto-populate this. 2332 2333 const Type *Ty = I.getAllocatedType(); 2334 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 2335 unsigned Align = 2336 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2337 I.getAlignment()); 2338 2339 SDOperand AllocSize = getValue(I.getArraySize()); 2340 MVT::ValueType IntPtr = TLI.getPointerTy(); 2341 if (IntPtr < AllocSize.getValueType()) 2342 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2343 else if (IntPtr > AllocSize.getValueType()) 2344 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2345 2346 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2347 getIntPtrConstant(TySize)); 2348 2349 // Handle alignment. If the requested alignment is less than or equal to 2350 // the stack alignment, ignore it. If the size is greater than or equal to 2351 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2352 unsigned StackAlign = 2353 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2354 if (Align <= StackAlign) 2355 Align = 0; 2356 2357 // Round the size of the allocation up to the stack alignment size 2358 // by add SA-1 to the size. 2359 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2360 getIntPtrConstant(StackAlign-1)); 2361 // Mask out the low bits for alignment purposes. 2362 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2363 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2364 2365 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 2366 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2367 MVT::Other); 2368 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2369 setValue(&I, DSA); 2370 DAG.setRoot(DSA.getValue(1)); 2371 2372 // Inform the Frame Information that we have just allocated a variable-sized 2373 // object. 2374 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2375} 2376 2377void SelectionDAGLowering::visitLoad(LoadInst &I) { 2378 SDOperand Ptr = getValue(I.getOperand(0)); 2379 2380 SDOperand Root; 2381 if (I.isVolatile()) 2382 Root = getRoot(); 2383 else { 2384 // Do not serialize non-volatile loads against each other. 2385 Root = DAG.getRoot(); 2386 } 2387 2388 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2389 Root, I.isVolatile(), I.getAlignment())); 2390} 2391 2392SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2393 const Value *SV, SDOperand Root, 2394 bool isVolatile, 2395 unsigned Alignment) { 2396 SDOperand L = 2397 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2398 isVolatile, Alignment); 2399 2400 if (isVolatile) 2401 DAG.setRoot(L.getValue(1)); 2402 else 2403 PendingLoads.push_back(L.getValue(1)); 2404 2405 return L; 2406} 2407 2408 2409void SelectionDAGLowering::visitStore(StoreInst &I) { 2410 Value *SrcV = I.getOperand(0); 2411 SDOperand Src = getValue(SrcV); 2412 SDOperand Ptr = getValue(I.getOperand(1)); 2413 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2414 I.isVolatile(), I.getAlignment())); 2415} 2416 2417/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2418/// node. 2419void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2420 unsigned Intrinsic) { 2421 bool HasChain = !I.doesNotAccessMemory(); 2422 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 2423 2424 // Build the operand list. 2425 SmallVector<SDOperand, 8> Ops; 2426 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2427 if (OnlyLoad) { 2428 // We don't need to serialize loads against other loads. 2429 Ops.push_back(DAG.getRoot()); 2430 } else { 2431 Ops.push_back(getRoot()); 2432 } 2433 } 2434 2435 // Add the intrinsic ID as an integer operand. 2436 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2437 2438 // Add all operands of the call to the operand list. 2439 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2440 SDOperand Op = getValue(I.getOperand(i)); 2441 assert(TLI.isTypeLegal(Op.getValueType()) && 2442 "Intrinsic uses a non-legal type?"); 2443 Ops.push_back(Op); 2444 } 2445 2446 std::vector<MVT::ValueType> VTs; 2447 if (I.getType() != Type::VoidTy) { 2448 MVT::ValueType VT = TLI.getValueType(I.getType()); 2449 if (MVT::isVector(VT)) { 2450 const VectorType *DestTy = cast<VectorType>(I.getType()); 2451 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2452 2453 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2454 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2455 } 2456 2457 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2458 VTs.push_back(VT); 2459 } 2460 if (HasChain) 2461 VTs.push_back(MVT::Other); 2462 2463 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2464 2465 // Create the node. 2466 SDOperand Result; 2467 if (!HasChain) 2468 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2469 &Ops[0], Ops.size()); 2470 else if (I.getType() != Type::VoidTy) 2471 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2472 &Ops[0], Ops.size()); 2473 else 2474 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2475 &Ops[0], Ops.size()); 2476 2477 if (HasChain) { 2478 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2479 if (OnlyLoad) 2480 PendingLoads.push_back(Chain); 2481 else 2482 DAG.setRoot(Chain); 2483 } 2484 if (I.getType() != Type::VoidTy) { 2485 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2486 MVT::ValueType VT = TLI.getValueType(PTy); 2487 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 2488 } 2489 setValue(&I, Result); 2490 } 2491} 2492 2493/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 2494static GlobalVariable *ExtractTypeInfo (Value *V) { 2495 V = IntrinsicInst::StripPointerCasts(V); 2496 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 2497 assert (GV || isa<ConstantPointerNull>(V) && 2498 "TypeInfo must be a global variable or NULL"); 2499 return GV; 2500} 2501 2502/// addCatchInfo - Extract the personality and type infos from an eh.selector 2503/// call, and add them to the specified machine basic block. 2504static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 2505 MachineBasicBlock *MBB) { 2506 // Inform the MachineModuleInfo of the personality for this landing pad. 2507 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 2508 assert(CE->getOpcode() == Instruction::BitCast && 2509 isa<Function>(CE->getOperand(0)) && 2510 "Personality should be a function"); 2511 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 2512 2513 // Gather all the type infos for this landing pad and pass them along to 2514 // MachineModuleInfo. 2515 std::vector<GlobalVariable *> TyInfo; 2516 unsigned N = I.getNumOperands(); 2517 2518 for (unsigned i = N - 1; i > 2; --i) { 2519 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 2520 unsigned FilterLength = CI->getZExtValue(); 2521 unsigned FirstCatch = i + FilterLength + !FilterLength; 2522 assert (FirstCatch <= N && "Invalid filter length"); 2523 2524 if (FirstCatch < N) { 2525 TyInfo.reserve(N - FirstCatch); 2526 for (unsigned j = FirstCatch; j < N; ++j) 2527 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2528 MMI->addCatchTypeInfo(MBB, TyInfo); 2529 TyInfo.clear(); 2530 } 2531 2532 if (!FilterLength) { 2533 // Cleanup. 2534 MMI->addCleanup(MBB); 2535 } else { 2536 // Filter. 2537 TyInfo.reserve(FilterLength - 1); 2538 for (unsigned j = i + 1; j < FirstCatch; ++j) 2539 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2540 MMI->addFilterTypeInfo(MBB, TyInfo); 2541 TyInfo.clear(); 2542 } 2543 2544 N = i; 2545 } 2546 } 2547 2548 if (N > 3) { 2549 TyInfo.reserve(N - 3); 2550 for (unsigned j = 3; j < N; ++j) 2551 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2552 MMI->addCatchTypeInfo(MBB, TyInfo); 2553 } 2554} 2555 2556/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2557/// we want to emit this as a call to a named external function, return the name 2558/// otherwise lower it and return null. 2559const char * 2560SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2561 switch (Intrinsic) { 2562 default: 2563 // By default, turn this into a target intrinsic node. 2564 visitTargetIntrinsic(I, Intrinsic); 2565 return 0; 2566 case Intrinsic::vastart: visitVAStart(I); return 0; 2567 case Intrinsic::vaend: visitVAEnd(I); return 0; 2568 case Intrinsic::vacopy: visitVACopy(I); return 0; 2569 case Intrinsic::returnaddress: 2570 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2571 getValue(I.getOperand(1)))); 2572 return 0; 2573 case Intrinsic::frameaddress: 2574 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2575 getValue(I.getOperand(1)))); 2576 return 0; 2577 case Intrinsic::setjmp: 2578 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2579 break; 2580 case Intrinsic::longjmp: 2581 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2582 break; 2583 case Intrinsic::memcpy_i32: 2584 case Intrinsic::memcpy_i64: 2585 visitMemIntrinsic(I, ISD::MEMCPY); 2586 return 0; 2587 case Intrinsic::memset_i32: 2588 case Intrinsic::memset_i64: 2589 visitMemIntrinsic(I, ISD::MEMSET); 2590 return 0; 2591 case Intrinsic::memmove_i32: 2592 case Intrinsic::memmove_i64: 2593 visitMemIntrinsic(I, ISD::MEMMOVE); 2594 return 0; 2595 2596 case Intrinsic::dbg_stoppoint: { 2597 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2598 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2599 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2600 SDOperand Ops[5]; 2601 2602 Ops[0] = getRoot(); 2603 Ops[1] = getValue(SPI.getLineValue()); 2604 Ops[2] = getValue(SPI.getColumnValue()); 2605 2606 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2607 assert(DD && "Not a debug information descriptor"); 2608 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2609 2610 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2611 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2612 2613 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2614 } 2615 2616 return 0; 2617 } 2618 case Intrinsic::dbg_region_start: { 2619 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2620 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2621 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2622 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2623 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2624 DAG.getConstant(LabelID, MVT::i32))); 2625 } 2626 2627 return 0; 2628 } 2629 case Intrinsic::dbg_region_end: { 2630 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2631 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2632 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2633 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2634 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2635 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2636 } 2637 2638 return 0; 2639 } 2640 case Intrinsic::dbg_func_start: { 2641 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2642 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2643 if (MMI && FSI.getSubprogram() && 2644 MMI->Verify(FSI.getSubprogram())) { 2645 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram()); 2646 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2647 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2648 } 2649 2650 return 0; 2651 } 2652 case Intrinsic::dbg_declare: { 2653 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2654 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2655 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) { 2656 SDOperand AddressOp = getValue(DI.getAddress()); 2657 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 2658 MMI->RecordVariable(DI.getVariable(), FI->getIndex()); 2659 } 2660 2661 return 0; 2662 } 2663 2664 case Intrinsic::eh_exception: { 2665 if (ExceptionHandling) { 2666 if (!CurMBB->isLandingPad()) { 2667 // FIXME: Mark exception register as live in. Hack for PR1508. 2668 unsigned Reg = TLI.getExceptionAddressRegister(); 2669 if (Reg) CurMBB->addLiveIn(Reg); 2670 } 2671 // Insert the EXCEPTIONADDR instruction. 2672 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2673 SDOperand Ops[1]; 2674 Ops[0] = DAG.getRoot(); 2675 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2676 setValue(&I, Op); 2677 DAG.setRoot(Op.getValue(1)); 2678 } else { 2679 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2680 } 2681 return 0; 2682 } 2683 2684 case Intrinsic::eh_selector_i32: 2685 case Intrinsic::eh_selector_i64: { 2686 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2687 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ? 2688 MVT::i32 : MVT::i64); 2689 2690 if (ExceptionHandling && MMI) { 2691 if (CurMBB->isLandingPad()) 2692 addCatchInfo(I, MMI, CurMBB); 2693 else { 2694#ifndef NDEBUG 2695 FuncInfo.CatchInfoLost.insert(&I); 2696#endif 2697 // FIXME: Mark exception selector register as live in. Hack for PR1508. 2698 unsigned Reg = TLI.getExceptionSelectorRegister(); 2699 if (Reg) CurMBB->addLiveIn(Reg); 2700 } 2701 2702 // Insert the EHSELECTION instruction. 2703 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 2704 SDOperand Ops[2]; 2705 Ops[0] = getValue(I.getOperand(1)); 2706 Ops[1] = getRoot(); 2707 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2708 setValue(&I, Op); 2709 DAG.setRoot(Op.getValue(1)); 2710 } else { 2711 setValue(&I, DAG.getConstant(0, VT)); 2712 } 2713 2714 return 0; 2715 } 2716 2717 case Intrinsic::eh_typeid_for_i32: 2718 case Intrinsic::eh_typeid_for_i64: { 2719 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2720 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? 2721 MVT::i32 : MVT::i64); 2722 2723 if (MMI) { 2724 // Find the type id for the given typeinfo. 2725 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 2726 2727 unsigned TypeID = MMI->getTypeIDFor(GV); 2728 setValue(&I, DAG.getConstant(TypeID, VT)); 2729 } else { 2730 // Return something different to eh_selector. 2731 setValue(&I, DAG.getConstant(1, VT)); 2732 } 2733 2734 return 0; 2735 } 2736 2737 case Intrinsic::eh_return: { 2738 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2739 2740 if (MMI && ExceptionHandling) { 2741 MMI->setCallsEHReturn(true); 2742 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, 2743 MVT::Other, 2744 getRoot(), 2745 getValue(I.getOperand(1)), 2746 getValue(I.getOperand(2)))); 2747 } else { 2748 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2749 } 2750 2751 return 0; 2752 } 2753 2754 case Intrinsic::eh_unwind_init: { 2755 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 2756 MMI->setCallsUnwindInit(true); 2757 } 2758 2759 return 0; 2760 } 2761 2762 case Intrinsic::eh_dwarf_cfa: { 2763 if (ExceptionHandling) { 2764 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType(); 2765 SDOperand CfaArg; 2766 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 2767 CfaArg = DAG.getNode(ISD::TRUNCATE, 2768 TLI.getPointerTy(), getValue(I.getOperand(1))); 2769 else 2770 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, 2771 TLI.getPointerTy(), getValue(I.getOperand(1))); 2772 2773 SDOperand Offset = DAG.getNode(ISD::ADD, 2774 TLI.getPointerTy(), 2775 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, 2776 TLI.getPointerTy()), 2777 CfaArg); 2778 setValue(&I, DAG.getNode(ISD::ADD, 2779 TLI.getPointerTy(), 2780 DAG.getNode(ISD::FRAMEADDR, 2781 TLI.getPointerTy(), 2782 DAG.getConstant(0, 2783 TLI.getPointerTy())), 2784 Offset)); 2785 } else { 2786 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2787 } 2788 2789 return 0; 2790 } 2791 2792 case Intrinsic::sqrt: 2793 setValue(&I, DAG.getNode(ISD::FSQRT, 2794 getValue(I.getOperand(1)).getValueType(), 2795 getValue(I.getOperand(1)))); 2796 return 0; 2797 case Intrinsic::powi: 2798 setValue(&I, DAG.getNode(ISD::FPOWI, 2799 getValue(I.getOperand(1)).getValueType(), 2800 getValue(I.getOperand(1)), 2801 getValue(I.getOperand(2)))); 2802 return 0; 2803 case Intrinsic::sin: 2804 setValue(&I, DAG.getNode(ISD::FSIN, 2805 getValue(I.getOperand(1)).getValueType(), 2806 getValue(I.getOperand(1)))); 2807 return 0; 2808 case Intrinsic::cos: 2809 setValue(&I, DAG.getNode(ISD::FCOS, 2810 getValue(I.getOperand(1)).getValueType(), 2811 getValue(I.getOperand(1)))); 2812 return 0; 2813 case Intrinsic::pow: 2814 setValue(&I, DAG.getNode(ISD::FPOW, 2815 getValue(I.getOperand(1)).getValueType(), 2816 getValue(I.getOperand(1)), 2817 getValue(I.getOperand(2)))); 2818 return 0; 2819 case Intrinsic::pcmarker: { 2820 SDOperand Tmp = getValue(I.getOperand(1)); 2821 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2822 return 0; 2823 } 2824 case Intrinsic::readcyclecounter: { 2825 SDOperand Op = getRoot(); 2826 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2827 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2828 &Op, 1); 2829 setValue(&I, Tmp); 2830 DAG.setRoot(Tmp.getValue(1)); 2831 return 0; 2832 } 2833 case Intrinsic::part_select: { 2834 // Currently not implemented: just abort 2835 assert(0 && "part_select intrinsic not implemented"); 2836 abort(); 2837 } 2838 case Intrinsic::part_set: { 2839 // Currently not implemented: just abort 2840 assert(0 && "part_set intrinsic not implemented"); 2841 abort(); 2842 } 2843 case Intrinsic::bswap: 2844 setValue(&I, DAG.getNode(ISD::BSWAP, 2845 getValue(I.getOperand(1)).getValueType(), 2846 getValue(I.getOperand(1)))); 2847 return 0; 2848 case Intrinsic::cttz: { 2849 SDOperand Arg = getValue(I.getOperand(1)); 2850 MVT::ValueType Ty = Arg.getValueType(); 2851 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2852 setValue(&I, result); 2853 return 0; 2854 } 2855 case Intrinsic::ctlz: { 2856 SDOperand Arg = getValue(I.getOperand(1)); 2857 MVT::ValueType Ty = Arg.getValueType(); 2858 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2859 setValue(&I, result); 2860 return 0; 2861 } 2862 case Intrinsic::ctpop: { 2863 SDOperand Arg = getValue(I.getOperand(1)); 2864 MVT::ValueType Ty = Arg.getValueType(); 2865 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2866 setValue(&I, result); 2867 return 0; 2868 } 2869 case Intrinsic::stacksave: { 2870 SDOperand Op = getRoot(); 2871 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2872 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2873 setValue(&I, Tmp); 2874 DAG.setRoot(Tmp.getValue(1)); 2875 return 0; 2876 } 2877 case Intrinsic::stackrestore: { 2878 SDOperand Tmp = getValue(I.getOperand(1)); 2879 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2880 return 0; 2881 } 2882 case Intrinsic::prefetch: 2883 // FIXME: Currently discarding prefetches. 2884 return 0; 2885 2886 case Intrinsic::var_annotation: 2887 // Discard annotate attributes 2888 return 0; 2889 2890 case Intrinsic::init_trampoline: { 2891 const Function *F = 2892 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2))); 2893 2894 SDOperand Ops[6]; 2895 Ops[0] = getRoot(); 2896 Ops[1] = getValue(I.getOperand(1)); 2897 Ops[2] = getValue(I.getOperand(2)); 2898 Ops[3] = getValue(I.getOperand(3)); 2899 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 2900 Ops[5] = DAG.getSrcValue(F); 2901 2902 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE, 2903 DAG.getNodeValueTypes(TLI.getPointerTy(), 2904 MVT::Other), 2, 2905 Ops, 6); 2906 2907 setValue(&I, Tmp); 2908 DAG.setRoot(Tmp.getValue(1)); 2909 return 0; 2910 } 2911 case Intrinsic::flt_rounds: { 2912 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS, MVT::i32)); 2913 return 0; 2914 } 2915 } 2916} 2917 2918 2919void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee, 2920 bool IsTailCall, 2921 MachineBasicBlock *LandingPad) { 2922 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 2923 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 2924 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2925 unsigned BeginLabel = 0, EndLabel = 0; 2926 2927 TargetLowering::ArgListTy Args; 2928 TargetLowering::ArgListEntry Entry; 2929 Args.reserve(CS.arg_size()); 2930 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 2931 i != e; ++i) { 2932 SDOperand ArgNode = getValue(*i); 2933 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 2934 2935 unsigned attrInd = i - CS.arg_begin() + 1; 2936 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt); 2937 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt); 2938 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg); 2939 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet); 2940 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest); 2941 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal); 2942 Args.push_back(Entry); 2943 } 2944 2945 bool MarkTryRange = LandingPad || 2946 // C++ requires special handling of 'nounwind' calls. 2947 (CS.doesNotThrow()); 2948 2949 if (MarkTryRange && ExceptionHandling && MMI) { 2950 // Insert a label before the invoke call to mark the try range. This can be 2951 // used to detect deletion of the invoke via the MachineModuleInfo. 2952 BeginLabel = MMI->NextLabelID(); 2953 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2954 DAG.getConstant(BeginLabel, MVT::i32))); 2955 } 2956 2957 std::pair<SDOperand,SDOperand> Result = 2958 TLI.LowerCallTo(getRoot(), CS.getType(), 2959 CS.paramHasAttr(0, ParamAttr::SExt), 2960 FTy->isVarArg(), CS.getCallingConv(), IsTailCall, 2961 Callee, Args, DAG); 2962 if (CS.getType() != Type::VoidTy) 2963 setValue(CS.getInstruction(), Result.first); 2964 DAG.setRoot(Result.second); 2965 2966 if (MarkTryRange && ExceptionHandling && MMI) { 2967 // Insert a label at the end of the invoke call to mark the try range. This 2968 // can be used to detect deletion of the invoke via the MachineModuleInfo. 2969 EndLabel = MMI->NextLabelID(); 2970 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2971 DAG.getConstant(EndLabel, MVT::i32))); 2972 2973 // Inform MachineModuleInfo of range. 2974 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 2975 } 2976} 2977 2978 2979void SelectionDAGLowering::visitCall(CallInst &I) { 2980 const char *RenameFn = 0; 2981 if (Function *F = I.getCalledFunction()) { 2982 if (F->isDeclaration()) { 2983 if (unsigned IID = F->getIntrinsicID()) { 2984 RenameFn = visitIntrinsicCall(I, IID); 2985 if (!RenameFn) 2986 return; 2987 } 2988 } 2989 2990 // Check for well-known libc/libm calls. If the function is internal, it 2991 // can't be a library call. 2992 unsigned NameLen = F->getNameLen(); 2993 if (!F->hasInternalLinkage() && NameLen) { 2994 const char *NameStr = F->getNameStart(); 2995 if (NameStr[0] == 'c' && 2996 ((NameLen == 8 && !strcmp(NameStr, "copysign")) || 2997 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) { 2998 if (I.getNumOperands() == 3 && // Basic sanity checks. 2999 I.getOperand(1)->getType()->isFloatingPoint() && 3000 I.getType() == I.getOperand(1)->getType() && 3001 I.getType() == I.getOperand(2)->getType()) { 3002 SDOperand LHS = getValue(I.getOperand(1)); 3003 SDOperand RHS = getValue(I.getOperand(2)); 3004 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 3005 LHS, RHS)); 3006 return; 3007 } 3008 } else if (NameStr[0] == 'f' && 3009 ((NameLen == 4 && !strcmp(NameStr, "fabs")) || 3010 (NameLen == 5 && !strcmp(NameStr, "fabsf")) || 3011 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) { 3012 if (I.getNumOperands() == 2 && // Basic sanity checks. 3013 I.getOperand(1)->getType()->isFloatingPoint() && 3014 I.getType() == I.getOperand(1)->getType()) { 3015 SDOperand Tmp = getValue(I.getOperand(1)); 3016 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 3017 return; 3018 } 3019 } else if (NameStr[0] == 's' && 3020 ((NameLen == 3 && !strcmp(NameStr, "sin")) || 3021 (NameLen == 4 && !strcmp(NameStr, "sinf")) || 3022 (NameLen == 4 && !strcmp(NameStr, "sinl")))) { 3023 if (I.getNumOperands() == 2 && // Basic sanity checks. 3024 I.getOperand(1)->getType()->isFloatingPoint() && 3025 I.getType() == I.getOperand(1)->getType()) { 3026 SDOperand Tmp = getValue(I.getOperand(1)); 3027 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 3028 return; 3029 } 3030 } else if (NameStr[0] == 'c' && 3031 ((NameLen == 3 && !strcmp(NameStr, "cos")) || 3032 (NameLen == 4 && !strcmp(NameStr, "cosf")) || 3033 (NameLen == 4 && !strcmp(NameStr, "cosl")))) { 3034 if (I.getNumOperands() == 2 && // Basic sanity checks. 3035 I.getOperand(1)->getType()->isFloatingPoint() && 3036 I.getType() == I.getOperand(1)->getType()) { 3037 SDOperand Tmp = getValue(I.getOperand(1)); 3038 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 3039 return; 3040 } 3041 } 3042 } 3043 } else if (isa<InlineAsm>(I.getOperand(0))) { 3044 visitInlineAsm(&I); 3045 return; 3046 } 3047 3048 SDOperand Callee; 3049 if (!RenameFn) 3050 Callee = getValue(I.getOperand(0)); 3051 else 3052 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 3053 3054 LowerCallTo(&I, Callee, I.isTailCall()); 3055} 3056 3057 3058/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 3059/// this value and returns the result as a ValueVT value. This uses 3060/// Chain/Flag as the input and updates them for the output Chain/Flag. 3061/// If the Flag pointer is NULL, no flag is used. 3062SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 3063 SDOperand &Chain, SDOperand *Flag)const{ 3064 // Copy the legal parts from the registers. 3065 unsigned NumParts = Regs.size(); 3066 SmallVector<SDOperand, 8> Parts(NumParts); 3067 for (unsigned i = 0; i != NumParts; ++i) { 3068 SDOperand Part = Flag ? 3069 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) : 3070 DAG.getCopyFromReg(Chain, Regs[i], RegVT); 3071 Chain = Part.getValue(1); 3072 if (Flag) 3073 *Flag = Part.getValue(2); 3074 Parts[i] = Part; 3075 } 3076 3077 // Assemble the legal parts into the final value. 3078 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT); 3079} 3080 3081/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 3082/// specified value into the registers specified by this object. This uses 3083/// Chain/Flag as the input and updates them for the output Chain/Flag. 3084/// If the Flag pointer is NULL, no flag is used. 3085void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 3086 SDOperand &Chain, SDOperand *Flag) const { 3087 // Get the list of the values's legal parts. 3088 unsigned NumParts = Regs.size(); 3089 SmallVector<SDOperand, 8> Parts(NumParts); 3090 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT); 3091 3092 // Copy the parts into the registers. 3093 for (unsigned i = 0; i != NumParts; ++i) { 3094 SDOperand Part = Flag ? 3095 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) : 3096 DAG.getCopyToReg(Chain, Regs[i], Parts[i]); 3097 Chain = Part.getValue(0); 3098 if (Flag) 3099 *Flag = Part.getValue(1); 3100 } 3101} 3102 3103/// AddInlineAsmOperands - Add this value to the specified inlineasm node 3104/// operand list. This adds the code marker and includes the number of 3105/// values added into it. 3106void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 3107 std::vector<SDOperand> &Ops) const { 3108 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3109 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3110 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 3111 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 3112} 3113 3114/// isAllocatableRegister - If the specified register is safe to allocate, 3115/// i.e. it isn't a stack pointer or some other special register, return the 3116/// register class for the register. Otherwise, return null. 3117static const TargetRegisterClass * 3118isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3119 const TargetLowering &TLI, const MRegisterInfo *MRI) { 3120 MVT::ValueType FoundVT = MVT::Other; 3121 const TargetRegisterClass *FoundRC = 0; 3122 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 3123 E = MRI->regclass_end(); RCI != E; ++RCI) { 3124 MVT::ValueType ThisVT = MVT::Other; 3125 3126 const TargetRegisterClass *RC = *RCI; 3127 // If none of the the value types for this register class are valid, we 3128 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3129 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3130 I != E; ++I) { 3131 if (TLI.isTypeLegal(*I)) { 3132 // If we have already found this register in a different register class, 3133 // choose the one with the largest VT specified. For example, on 3134 // PowerPC, we favor f64 register classes over f32. 3135 if (FoundVT == MVT::Other || 3136 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 3137 ThisVT = *I; 3138 break; 3139 } 3140 } 3141 } 3142 3143 if (ThisVT == MVT::Other) continue; 3144 3145 // NOTE: This isn't ideal. In particular, this might allocate the 3146 // frame pointer in functions that need it (due to them not being taken 3147 // out of allocation, because a variable sized allocation hasn't been seen 3148 // yet). This is a slight code pessimization, but should still work. 3149 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3150 E = RC->allocation_order_end(MF); I != E; ++I) 3151 if (*I == Reg) { 3152 // We found a matching register class. Keep looking at others in case 3153 // we find one with larger registers that this physreg is also in. 3154 FoundRC = RC; 3155 FoundVT = ThisVT; 3156 break; 3157 } 3158 } 3159 return FoundRC; 3160} 3161 3162 3163namespace { 3164/// AsmOperandInfo - This contains information for each constraint that we are 3165/// lowering. 3166struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 3167 /// ConstraintCode - This contains the actual string for the code, like "m". 3168 std::string ConstraintCode; 3169 3170 /// ConstraintType - Information about the constraint code, e.g. Register, 3171 /// RegisterClass, Memory, Other, Unknown. 3172 TargetLowering::ConstraintType ConstraintType; 3173 3174 /// CallOperand/CallOperandval - If this is the result output operand or a 3175 /// clobber, this is null, otherwise it is the incoming operand to the 3176 /// CallInst. This gets modified as the asm is processed. 3177 SDOperand CallOperand; 3178 Value *CallOperandVal; 3179 3180 /// ConstraintVT - The ValueType for the operand value. 3181 MVT::ValueType ConstraintVT; 3182 3183 /// AssignedRegs - If this is a register or register class operand, this 3184 /// contains the set of register corresponding to the operand. 3185 RegsForValue AssignedRegs; 3186 3187 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3188 : InlineAsm::ConstraintInfo(info), 3189 ConstraintType(TargetLowering::C_Unknown), 3190 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) { 3191 } 3192 3193 void ComputeConstraintToUse(const TargetLowering &TLI); 3194 3195 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3196 /// busy in OutputRegs/InputRegs. 3197 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3198 std::set<unsigned> &OutputRegs, 3199 std::set<unsigned> &InputRegs) const { 3200 if (isOutReg) 3201 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3202 if (isInReg) 3203 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3204 } 3205}; 3206} // end anon namespace. 3207 3208/// getConstraintGenerality - Return an integer indicating how general CT is. 3209static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3210 switch (CT) { 3211 default: assert(0 && "Unknown constraint type!"); 3212 case TargetLowering::C_Other: 3213 case TargetLowering::C_Unknown: 3214 return 0; 3215 case TargetLowering::C_Register: 3216 return 1; 3217 case TargetLowering::C_RegisterClass: 3218 return 2; 3219 case TargetLowering::C_Memory: 3220 return 3; 3221 } 3222} 3223 3224void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) { 3225 assert(!Codes.empty() && "Must have at least one constraint"); 3226 3227 std::string *Current = &Codes[0]; 3228 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current); 3229 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common. 3230 ConstraintCode = *Current; 3231 ConstraintType = CurType; 3232 return; 3233 } 3234 3235 unsigned CurGenerality = getConstraintGenerality(CurType); 3236 3237 // If we have multiple constraints, try to pick the most general one ahead 3238 // of time. This isn't a wonderful solution, but handles common cases. 3239 for (unsigned j = 1, e = Codes.size(); j != e; ++j) { 3240 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]); 3241 unsigned ThisGenerality = getConstraintGenerality(ThisType); 3242 if (ThisGenerality > CurGenerality) { 3243 // This constraint letter is more general than the previous one, 3244 // use it. 3245 CurType = ThisType; 3246 Current = &Codes[j]; 3247 CurGenerality = ThisGenerality; 3248 } 3249 } 3250 3251 ConstraintCode = *Current; 3252 ConstraintType = CurType; 3253} 3254 3255 3256void SelectionDAGLowering:: 3257GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 3258 std::set<unsigned> &OutputRegs, 3259 std::set<unsigned> &InputRegs) { 3260 // Compute whether this value requires an input register, an output register, 3261 // or both. 3262 bool isOutReg = false; 3263 bool isInReg = false; 3264 switch (OpInfo.Type) { 3265 case InlineAsm::isOutput: 3266 isOutReg = true; 3267 3268 // If this is an early-clobber output, or if there is an input 3269 // constraint that matches this, we need to reserve the input register 3270 // so no other inputs allocate to it. 3271 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3272 break; 3273 case InlineAsm::isInput: 3274 isInReg = true; 3275 isOutReg = false; 3276 break; 3277 case InlineAsm::isClobber: 3278 isOutReg = true; 3279 isInReg = true; 3280 break; 3281 } 3282 3283 3284 MachineFunction &MF = DAG.getMachineFunction(); 3285 std::vector<unsigned> Regs; 3286 3287 // If this is a constraint for a single physreg, or a constraint for a 3288 // register class, find it. 3289 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3290 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3291 OpInfo.ConstraintVT); 3292 3293 unsigned NumRegs = 1; 3294 if (OpInfo.ConstraintVT != MVT::Other) 3295 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3296 MVT::ValueType RegVT; 3297 MVT::ValueType ValueVT = OpInfo.ConstraintVT; 3298 3299 3300 // If this is a constraint for a specific physical register, like {r17}, 3301 // assign it now. 3302 if (PhysReg.first) { 3303 if (OpInfo.ConstraintVT == MVT::Other) 3304 ValueVT = *PhysReg.second->vt_begin(); 3305 3306 // Get the actual register value type. This is important, because the user 3307 // may have asked for (e.g.) the AX register in i32 type. We need to 3308 // remember that AX is actually i16 to get the right extension. 3309 RegVT = *PhysReg.second->vt_begin(); 3310 3311 // This is a explicit reference to a physical register. 3312 Regs.push_back(PhysReg.first); 3313 3314 // If this is an expanded reference, add the rest of the regs to Regs. 3315 if (NumRegs != 1) { 3316 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3317 TargetRegisterClass::iterator E = PhysReg.second->end(); 3318 for (; *I != PhysReg.first; ++I) 3319 assert(I != E && "Didn't find reg!"); 3320 3321 // Already added the first reg. 3322 --NumRegs; ++I; 3323 for (; NumRegs; --NumRegs, ++I) { 3324 assert(I != E && "Ran out of registers to allocate!"); 3325 Regs.push_back(*I); 3326 } 3327 } 3328 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3329 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3330 return; 3331 } 3332 3333 // Otherwise, if this was a reference to an LLVM register class, create vregs 3334 // for this reference. 3335 std::vector<unsigned> RegClassRegs; 3336 const TargetRegisterClass *RC = PhysReg.second; 3337 if (RC) { 3338 // If this is an early clobber or tied register, our regalloc doesn't know 3339 // how to maintain the constraint. If it isn't, go ahead and create vreg 3340 // and let the regalloc do the right thing. 3341 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 3342 // If there is some other early clobber and this is an input register, 3343 // then we are forced to pre-allocate the input reg so it doesn't 3344 // conflict with the earlyclobber. 3345 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 3346 RegVT = *PhysReg.second->vt_begin(); 3347 3348 if (OpInfo.ConstraintVT == MVT::Other) 3349 ValueVT = RegVT; 3350 3351 // Create the appropriate number of virtual registers. 3352 SSARegMap *RegMap = MF.getSSARegMap(); 3353 for (; NumRegs; --NumRegs) 3354 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second)); 3355 3356 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3357 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3358 return; 3359 } 3360 3361 // Otherwise, we can't allocate it. Let the code below figure out how to 3362 // maintain these constraints. 3363 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3364 3365 } else { 3366 // This is a reference to a register class that doesn't directly correspond 3367 // to an LLVM register class. Allocate NumRegs consecutive, available, 3368 // registers from the class. 3369 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3370 OpInfo.ConstraintVT); 3371 } 3372 3373 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 3374 unsigned NumAllocated = 0; 3375 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3376 unsigned Reg = RegClassRegs[i]; 3377 // See if this register is available. 3378 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3379 (isInReg && InputRegs.count(Reg))) { // Already used. 3380 // Make sure we find consecutive registers. 3381 NumAllocated = 0; 3382 continue; 3383 } 3384 3385 // Check to see if this register is allocatable (i.e. don't give out the 3386 // stack pointer). 3387 if (RC == 0) { 3388 RC = isAllocatableRegister(Reg, MF, TLI, MRI); 3389 if (!RC) { // Couldn't allocate this register. 3390 // Reset NumAllocated to make sure we return consecutive registers. 3391 NumAllocated = 0; 3392 continue; 3393 } 3394 } 3395 3396 // Okay, this register is good, we can use it. 3397 ++NumAllocated; 3398 3399 // If we allocated enough consecutive registers, succeed. 3400 if (NumAllocated == NumRegs) { 3401 unsigned RegStart = (i-NumAllocated)+1; 3402 unsigned RegEnd = i+1; 3403 // Mark all of the allocated registers used. 3404 for (unsigned i = RegStart; i != RegEnd; ++i) 3405 Regs.push_back(RegClassRegs[i]); 3406 3407 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 3408 OpInfo.ConstraintVT); 3409 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3410 return; 3411 } 3412 } 3413 3414 // Otherwise, we couldn't allocate enough registers for this. 3415 return; 3416} 3417 3418 3419/// visitInlineAsm - Handle a call to an InlineAsm object. 3420/// 3421void SelectionDAGLowering::visitInlineAsm(CallSite CS) { 3422 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 3423 3424 /// ConstraintOperands - Information about all of the constraints. 3425 std::vector<AsmOperandInfo> ConstraintOperands; 3426 3427 SDOperand Chain = getRoot(); 3428 SDOperand Flag; 3429 3430 std::set<unsigned> OutputRegs, InputRegs; 3431 3432 // Do a prepass over the constraints, canonicalizing them, and building up the 3433 // ConstraintOperands list. 3434 std::vector<InlineAsm::ConstraintInfo> 3435 ConstraintInfos = IA->ParseConstraints(); 3436 3437 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 3438 // constraint. If so, we can't let the register allocator allocate any input 3439 // registers, because it will not know to avoid the earlyclobbered output reg. 3440 bool SawEarlyClobber = false; 3441 3442 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 3443 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3444 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 3445 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 3446 3447 MVT::ValueType OpVT = MVT::Other; 3448 3449 // Compute the value type for each operand. 3450 switch (OpInfo.Type) { 3451 case InlineAsm::isOutput: 3452 if (!OpInfo.isIndirect) { 3453 // The return value of the call is this value. As such, there is no 3454 // corresponding argument. 3455 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 3456 OpVT = TLI.getValueType(CS.getType()); 3457 } else { 3458 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 3459 } 3460 break; 3461 case InlineAsm::isInput: 3462 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 3463 break; 3464 case InlineAsm::isClobber: 3465 // Nothing to do. 3466 break; 3467 } 3468 3469 // If this is an input or an indirect output, process the call argument. 3470 // BasicBlocks are labels, currently appearing only in asm's. 3471 if (OpInfo.CallOperandVal) { 3472 if (isa<BasicBlock>(OpInfo.CallOperandVal)) 3473 OpInfo.CallOperand = 3474 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(OpInfo.CallOperandVal)]); 3475 else { 3476 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 3477 const Type *OpTy = OpInfo.CallOperandVal->getType(); 3478 // If this is an indirect operand, the operand is a pointer to the 3479 // accessed type. 3480 if (OpInfo.isIndirect) 3481 OpTy = cast<PointerType>(OpTy)->getElementType(); 3482 3483 // If OpTy is not a first-class value, it may be a struct/union that we 3484 // can tile with integers. 3485 if (!OpTy->isFirstClassType() && OpTy->isSized()) { 3486 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3487 switch (BitSize) { 3488 default: break; 3489 case 1: 3490 case 8: 3491 case 16: 3492 case 32: 3493 case 64: 3494 OpTy = IntegerType::get(BitSize); 3495 break; 3496 } 3497 } 3498 3499 OpVT = TLI.getValueType(OpTy, true); 3500 } 3501 } 3502 3503 OpInfo.ConstraintVT = OpVT; 3504 3505 // Compute the constraint code and ConstraintType to use. 3506 OpInfo.ComputeConstraintToUse(TLI); 3507 3508 // Keep track of whether we see an earlyclobber. 3509 SawEarlyClobber |= OpInfo.isEarlyClobber; 3510 3511 // If this is a memory input, and if the operand is not indirect, do what we 3512 // need to to provide an address for the memory input. 3513 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 3514 !OpInfo.isIndirect) { 3515 assert(OpInfo.Type == InlineAsm::isInput && 3516 "Can only indirectify direct input operands!"); 3517 3518 // Memory operands really want the address of the value. If we don't have 3519 // an indirect input, put it in the constpool if we can, otherwise spill 3520 // it to a stack slot. 3521 3522 // If the operand is a float, integer, or vector constant, spill to a 3523 // constant pool entry to get its address. 3524 Value *OpVal = OpInfo.CallOperandVal; 3525 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 3526 isa<ConstantVector>(OpVal)) { 3527 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 3528 TLI.getPointerTy()); 3529 } else { 3530 // Otherwise, create a stack slot and emit a store to it before the 3531 // asm. 3532 const Type *Ty = OpVal->getType(); 3533 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 3534 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3535 MachineFunction &MF = DAG.getMachineFunction(); 3536 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3537 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3538 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 3539 OpInfo.CallOperand = StackSlot; 3540 } 3541 3542 // There is no longer a Value* corresponding to this operand. 3543 OpInfo.CallOperandVal = 0; 3544 // It is now an indirect operand. 3545 OpInfo.isIndirect = true; 3546 } 3547 3548 // If this constraint is for a specific register, allocate it before 3549 // anything else. 3550 if (OpInfo.ConstraintType == TargetLowering::C_Register) 3551 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3552 } 3553 ConstraintInfos.clear(); 3554 3555 3556 // Second pass - Loop over all of the operands, assigning virtual or physregs 3557 // to registerclass operands. 3558 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3559 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3560 3561 // C_Register operands have already been allocated, Other/Memory don't need 3562 // to be. 3563 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 3564 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3565 } 3566 3567 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 3568 std::vector<SDOperand> AsmNodeOperands; 3569 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3570 AsmNodeOperands.push_back( 3571 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 3572 3573 3574 // Loop over all of the inputs, copying the operand values into the 3575 // appropriate registers and processing the output regs. 3576 RegsForValue RetValRegs; 3577 3578 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 3579 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3580 3581 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3582 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3583 3584 switch (OpInfo.Type) { 3585 case InlineAsm::isOutput: { 3586 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 3587 OpInfo.ConstraintType != TargetLowering::C_Register) { 3588 // Memory output, or 'other' output (e.g. 'X' constraint). 3589 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 3590 3591 // Add information to the INLINEASM node to know about this output. 3592 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3593 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3594 TLI.getPointerTy())); 3595 AsmNodeOperands.push_back(OpInfo.CallOperand); 3596 break; 3597 } 3598 3599 // Otherwise, this is a register or register class output. 3600 3601 // Copy the output from the appropriate register. Find a register that 3602 // we can use. 3603 if (OpInfo.AssignedRegs.Regs.empty()) { 3604 cerr << "Couldn't allocate output reg for contraint '" 3605 << OpInfo.ConstraintCode << "'!\n"; 3606 exit(1); 3607 } 3608 3609 if (!OpInfo.isIndirect) { 3610 // This is the result value of the call. 3611 assert(RetValRegs.Regs.empty() && 3612 "Cannot have multiple output constraints yet!"); 3613 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 3614 RetValRegs = OpInfo.AssignedRegs; 3615 } else { 3616 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 3617 OpInfo.CallOperandVal)); 3618 } 3619 3620 // Add information to the INLINEASM node to know that this register is 3621 // set. 3622 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 3623 AsmNodeOperands); 3624 break; 3625 } 3626 case InlineAsm::isInput: { 3627 SDOperand InOperandVal = OpInfo.CallOperand; 3628 3629 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 3630 // If this is required to match an output register we have already set, 3631 // just use its register. 3632 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 3633 3634 // Scan until we find the definition we already emitted of this operand. 3635 // When we find it, create a RegsForValue operand. 3636 unsigned CurOp = 2; // The first operand. 3637 for (; OperandNo; --OperandNo) { 3638 // Advance to the next operand. 3639 unsigned NumOps = 3640 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3641 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3642 (NumOps & 7) == 4 /*MEM*/) && 3643 "Skipped past definitions?"); 3644 CurOp += (NumOps>>3)+1; 3645 } 3646 3647 unsigned NumOps = 3648 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3649 if ((NumOps & 7) == 2 /*REGDEF*/) { 3650 // Add NumOps>>3 registers to MatchedRegs. 3651 RegsForValue MatchedRegs; 3652 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3653 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3654 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3655 unsigned Reg = 3656 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3657 MatchedRegs.Regs.push_back(Reg); 3658 } 3659 3660 // Use the produced MatchedRegs object to 3661 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3662 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3663 break; 3664 } else { 3665 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3666 assert(0 && "matching constraints for memory operands unimp"); 3667 } 3668 } 3669 3670 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 3671 assert(!OpInfo.isIndirect && 3672 "Don't know how to handle indirect other inputs yet!"); 3673 3674 std::vector<SDOperand> Ops; 3675 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 3676 Ops, DAG); 3677 if (Ops.empty()) { 3678 cerr << "Invalid operand for inline asm constraint '" 3679 << OpInfo.ConstraintCode << "'!\n"; 3680 exit(1); 3681 } 3682 3683 // Add information to the INLINEASM node to know about this input. 3684 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 3685 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3686 TLI.getPointerTy())); 3687 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 3688 break; 3689 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 3690 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 3691 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 3692 "Memory operands expect pointer values"); 3693 3694 // Add information to the INLINEASM node to know about this input. 3695 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3696 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3697 TLI.getPointerTy())); 3698 AsmNodeOperands.push_back(InOperandVal); 3699 break; 3700 } 3701 3702 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 3703 OpInfo.ConstraintType == TargetLowering::C_Register) && 3704 "Unknown constraint type!"); 3705 assert(!OpInfo.isIndirect && 3706 "Don't know how to handle indirect register inputs yet!"); 3707 3708 // Copy the input into the appropriate registers. 3709 assert(!OpInfo.AssignedRegs.Regs.empty() && 3710 "Couldn't allocate input reg!"); 3711 3712 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3713 3714 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 3715 AsmNodeOperands); 3716 break; 3717 } 3718 case InlineAsm::isClobber: { 3719 // Add the clobbered value to the operand list, so that the register 3720 // allocator is aware that the physreg got clobbered. 3721 if (!OpInfo.AssignedRegs.Regs.empty()) 3722 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 3723 AsmNodeOperands); 3724 break; 3725 } 3726 } 3727 } 3728 3729 // Finish up input operands. 3730 AsmNodeOperands[0] = Chain; 3731 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3732 3733 Chain = DAG.getNode(ISD::INLINEASM, 3734 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3735 &AsmNodeOperands[0], AsmNodeOperands.size()); 3736 Flag = Chain.getValue(1); 3737 3738 // If this asm returns a register value, copy the result from that register 3739 // and set it as the value of the call. 3740 if (!RetValRegs.Regs.empty()) { 3741 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 3742 3743 // If the result of the inline asm is a vector, it may have the wrong 3744 // width/num elts. Make sure to convert it to the right type with 3745 // bit_convert. 3746 if (MVT::isVector(Val.getValueType())) { 3747 const VectorType *VTy = cast<VectorType>(CS.getType()); 3748 MVT::ValueType DesiredVT = TLI.getValueType(VTy); 3749 3750 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val); 3751 } 3752 3753 setValue(CS.getInstruction(), Val); 3754 } 3755 3756 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 3757 3758 // Process indirect outputs, first output all of the flagged copies out of 3759 // physregs. 3760 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 3761 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 3762 Value *Ptr = IndirectStoresToEmit[i].second; 3763 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 3764 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 3765 } 3766 3767 // Emit the non-flagged stores from the physregs. 3768 SmallVector<SDOperand, 8> OutChains; 3769 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 3770 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 3771 getValue(StoresToEmit[i].second), 3772 StoresToEmit[i].second, 0)); 3773 if (!OutChains.empty()) 3774 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3775 &OutChains[0], OutChains.size()); 3776 DAG.setRoot(Chain); 3777} 3778 3779 3780void SelectionDAGLowering::visitMalloc(MallocInst &I) { 3781 SDOperand Src = getValue(I.getOperand(0)); 3782 3783 MVT::ValueType IntPtr = TLI.getPointerTy(); 3784 3785 if (IntPtr < Src.getValueType()) 3786 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 3787 else if (IntPtr > Src.getValueType()) 3788 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 3789 3790 // Scale the source by the type size. 3791 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType()); 3792 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 3793 Src, getIntPtrConstant(ElementSize)); 3794 3795 TargetLowering::ArgListTy Args; 3796 TargetLowering::ArgListEntry Entry; 3797 Entry.Node = Src; 3798 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3799 Args.push_back(Entry); 3800 3801 std::pair<SDOperand,SDOperand> Result = 3802 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true, 3803 DAG.getExternalSymbol("malloc", IntPtr), 3804 Args, DAG); 3805 setValue(&I, Result.first); // Pointers always fit in registers 3806 DAG.setRoot(Result.second); 3807} 3808 3809void SelectionDAGLowering::visitFree(FreeInst &I) { 3810 TargetLowering::ArgListTy Args; 3811 TargetLowering::ArgListEntry Entry; 3812 Entry.Node = getValue(I.getOperand(0)); 3813 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3814 Args.push_back(Entry); 3815 MVT::ValueType IntPtr = TLI.getPointerTy(); 3816 std::pair<SDOperand,SDOperand> Result = 3817 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true, 3818 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 3819 DAG.setRoot(Result.second); 3820} 3821 3822// InsertAtEndOfBasicBlock - This method should be implemented by targets that 3823// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 3824// instructions are special in various ways, which require special support to 3825// insert. The specified MachineInstr is created but not inserted into any 3826// basic blocks, and the scheduler passes ownership of it to this method. 3827MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3828 MachineBasicBlock *MBB) { 3829 cerr << "If a target marks an instruction with " 3830 << "'usesCustomDAGSchedInserter', it must implement " 3831 << "TargetLowering::InsertAtEndOfBasicBlock!\n"; 3832 abort(); 3833 return 0; 3834} 3835 3836void SelectionDAGLowering::visitVAStart(CallInst &I) { 3837 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 3838 getValue(I.getOperand(1)), 3839 DAG.getSrcValue(I.getOperand(1)))); 3840} 3841 3842void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 3843 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 3844 getValue(I.getOperand(0)), 3845 DAG.getSrcValue(I.getOperand(0))); 3846 setValue(&I, V); 3847 DAG.setRoot(V.getValue(1)); 3848} 3849 3850void SelectionDAGLowering::visitVAEnd(CallInst &I) { 3851 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 3852 getValue(I.getOperand(1)), 3853 DAG.getSrcValue(I.getOperand(1)))); 3854} 3855 3856void SelectionDAGLowering::visitVACopy(CallInst &I) { 3857 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 3858 getValue(I.getOperand(1)), 3859 getValue(I.getOperand(2)), 3860 DAG.getSrcValue(I.getOperand(1)), 3861 DAG.getSrcValue(I.getOperand(2)))); 3862} 3863 3864/// TargetLowering::LowerArguments - This is the default LowerArguments 3865/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 3866/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 3867/// integrated into SDISel. 3868std::vector<SDOperand> 3869TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 3870 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 3871 std::vector<SDOperand> Ops; 3872 Ops.push_back(DAG.getRoot()); 3873 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 3874 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 3875 3876 // Add one result value for each formal argument. 3877 std::vector<MVT::ValueType> RetVals; 3878 unsigned j = 1; 3879 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 3880 I != E; ++I, ++j) { 3881 MVT::ValueType VT = getValueType(I->getType()); 3882 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3883 unsigned OriginalAlignment = 3884 getTargetData()->getABITypeAlignment(I->getType()); 3885 3886 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 3887 // that is zero extended! 3888 if (F.paramHasAttr(j, ParamAttr::ZExt)) 3889 Flags &= ~(ISD::ParamFlags::SExt); 3890 if (F.paramHasAttr(j, ParamAttr::SExt)) 3891 Flags |= ISD::ParamFlags::SExt; 3892 if (F.paramHasAttr(j, ParamAttr::InReg)) 3893 Flags |= ISD::ParamFlags::InReg; 3894 if (F.paramHasAttr(j, ParamAttr::StructRet)) 3895 Flags |= ISD::ParamFlags::StructReturn; 3896 if (F.paramHasAttr(j, ParamAttr::ByVal)) { 3897 Flags |= ISD::ParamFlags::ByVal; 3898 const PointerType *Ty = cast<PointerType>(I->getType()); 3899 const StructType *STy = cast<StructType>(Ty->getElementType()); 3900 unsigned StructAlign = 3901 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy)); 3902 unsigned StructSize = getTargetData()->getABITypeSize(STy); 3903 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs); 3904 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs); 3905 } 3906 if (F.paramHasAttr(j, ParamAttr::Nest)) 3907 Flags |= ISD::ParamFlags::Nest; 3908 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs); 3909 3910 switch (getTypeAction(VT)) { 3911 default: assert(0 && "Unknown type action!"); 3912 case Legal: 3913 RetVals.push_back(VT); 3914 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3915 break; 3916 case Promote: 3917 RetVals.push_back(getTypeToTransformTo(VT)); 3918 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3919 break; 3920 case Expand: { 3921 // If this is an illegal type, it needs to be broken up to fit into 3922 // registers. 3923 MVT::ValueType RegisterVT = getRegisterType(VT); 3924 unsigned NumRegs = getNumRegisters(VT); 3925 for (unsigned i = 0; i != NumRegs; ++i) { 3926 RetVals.push_back(RegisterVT); 3927 // if it isn't first piece, alignment must be 1 3928 if (i > 0) 3929 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3930 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3931 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3932 } 3933 break; 3934 } 3935 } 3936 } 3937 3938 RetVals.push_back(MVT::Other); 3939 3940 // Create the node. 3941 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 3942 DAG.getNodeValueTypes(RetVals), RetVals.size(), 3943 &Ops[0], Ops.size()).Val; 3944 unsigned NumArgRegs = Result->getNumValues() - 1; 3945 DAG.setRoot(SDOperand(Result, NumArgRegs)); 3946 3947 // Set up the return result vector. 3948 Ops.clear(); 3949 unsigned i = 0; 3950 unsigned Idx = 1; 3951 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 3952 ++I, ++Idx) { 3953 MVT::ValueType VT = getValueType(I->getType()); 3954 3955 switch (getTypeAction(VT)) { 3956 default: assert(0 && "Unknown type action!"); 3957 case Legal: 3958 Ops.push_back(SDOperand(Result, i++)); 3959 break; 3960 case Promote: { 3961 SDOperand Op(Result, i++); 3962 if (MVT::isInteger(VT)) { 3963 if (F.paramHasAttr(Idx, ParamAttr::SExt)) 3964 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, 3965 DAG.getValueType(VT)); 3966 else if (F.paramHasAttr(Idx, ParamAttr::ZExt)) 3967 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, 3968 DAG.getValueType(VT)); 3969 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3970 } else { 3971 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3972 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 3973 } 3974 Ops.push_back(Op); 3975 break; 3976 } 3977 case Expand: { 3978 MVT::ValueType PartVT = getRegisterType(VT); 3979 unsigned NumParts = getNumRegisters(VT); 3980 SmallVector<SDOperand, 4> Parts(NumParts); 3981 for (unsigned j = 0; j != NumParts; ++j) 3982 Parts[j] = SDOperand(Result, i++); 3983 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT)); 3984 break; 3985 } 3986 } 3987 } 3988 assert(i == NumArgRegs && "Argument register count mismatch!"); 3989 return Ops; 3990} 3991 3992 3993/// TargetLowering::LowerCallTo - This is the default LowerCallTo 3994/// implementation, which just inserts an ISD::CALL node, which is later custom 3995/// lowered by the target to something concrete. FIXME: When all targets are 3996/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 3997std::pair<SDOperand, SDOperand> 3998TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 3999 bool RetTyIsSigned, bool isVarArg, 4000 unsigned CallingConv, bool isTailCall, 4001 SDOperand Callee, 4002 ArgListTy &Args, SelectionDAG &DAG) { 4003 SmallVector<SDOperand, 32> Ops; 4004 Ops.push_back(Chain); // Op#0 - Chain 4005 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 4006 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 4007 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 4008 Ops.push_back(Callee); 4009 4010 // Handle all of the outgoing arguments. 4011 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 4012 MVT::ValueType VT = getValueType(Args[i].Ty); 4013 SDOperand Op = Args[i].Node; 4014 unsigned Flags = ISD::ParamFlags::NoFlagSet; 4015 unsigned OriginalAlignment = 4016 getTargetData()->getABITypeAlignment(Args[i].Ty); 4017 4018 if (Args[i].isSExt) 4019 Flags |= ISD::ParamFlags::SExt; 4020 if (Args[i].isZExt) 4021 Flags |= ISD::ParamFlags::ZExt; 4022 if (Args[i].isInReg) 4023 Flags |= ISD::ParamFlags::InReg; 4024 if (Args[i].isSRet) 4025 Flags |= ISD::ParamFlags::StructReturn; 4026 if (Args[i].isByVal) { 4027 Flags |= ISD::ParamFlags::ByVal; 4028 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 4029 const StructType *STy = cast<StructType>(Ty->getElementType()); 4030 unsigned StructAlign = 4031 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy)); 4032 unsigned StructSize = getTargetData()->getABITypeSize(STy); 4033 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs); 4034 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs); 4035 } 4036 if (Args[i].isNest) 4037 Flags |= ISD::ParamFlags::Nest; 4038 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs; 4039 4040 switch (getTypeAction(VT)) { 4041 default: assert(0 && "Unknown type action!"); 4042 case Legal: 4043 Ops.push_back(Op); 4044 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4045 break; 4046 case Promote: 4047 if (MVT::isInteger(VT)) { 4048 unsigned ExtOp; 4049 if (Args[i].isSExt) 4050 ExtOp = ISD::SIGN_EXTEND; 4051 else if (Args[i].isZExt) 4052 ExtOp = ISD::ZERO_EXTEND; 4053 else 4054 ExtOp = ISD::ANY_EXTEND; 4055 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 4056 } else { 4057 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 4058 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 4059 } 4060 Ops.push_back(Op); 4061 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4062 break; 4063 case Expand: { 4064 MVT::ValueType PartVT = getRegisterType(VT); 4065 unsigned NumParts = getNumRegisters(VT); 4066 SmallVector<SDOperand, 4> Parts(NumParts); 4067 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT); 4068 for (unsigned i = 0; i != NumParts; ++i) { 4069 // if it isn't first piece, alignment must be 1 4070 unsigned MyFlags = Flags; 4071 if (i != 0) 4072 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) | 4073 (1 << ISD::ParamFlags::OrigAlignmentOffs); 4074 4075 Ops.push_back(Parts[i]); 4076 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32)); 4077 } 4078 break; 4079 } 4080 } 4081 } 4082 4083 // Figure out the result value types. 4084 MVT::ValueType VT = getValueType(RetTy); 4085 MVT::ValueType RegisterVT = getRegisterType(VT); 4086 unsigned NumRegs = getNumRegisters(VT); 4087 SmallVector<MVT::ValueType, 4> RetTys(NumRegs); 4088 for (unsigned i = 0; i != NumRegs; ++i) 4089 RetTys[i] = RegisterVT; 4090 4091 RetTys.push_back(MVT::Other); // Always has a chain. 4092 4093 // Create the CALL node. 4094 SDOperand Res = DAG.getNode(ISD::CALL, 4095 DAG.getVTList(&RetTys[0], NumRegs + 1), 4096 &Ops[0], Ops.size()); 4097 Chain = Res.getValue(NumRegs); 4098 4099 // Gather up the call result into a single value. 4100 if (RetTy != Type::VoidTy) { 4101 ISD::NodeType AssertOp = ISD::AssertSext; 4102 if (!RetTyIsSigned) 4103 AssertOp = ISD::AssertZext; 4104 SmallVector<SDOperand, 4> Results(NumRegs); 4105 for (unsigned i = 0; i != NumRegs; ++i) 4106 Results[i] = Res.getValue(i); 4107 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp); 4108 } 4109 4110 return std::make_pair(Res, Chain); 4111} 4112 4113SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4114 assert(0 && "LowerOperation not implemented for this target!"); 4115 abort(); 4116 return SDOperand(); 4117} 4118 4119SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 4120 SelectionDAG &DAG) { 4121 assert(0 && "CustomPromoteOperation not implemented for this target!"); 4122 abort(); 4123 return SDOperand(); 4124} 4125 4126/// getMemsetValue - Vectorized representation of the memset value 4127/// operand. 4128static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 4129 SelectionDAG &DAG) { 4130 MVT::ValueType CurVT = VT; 4131 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 4132 uint64_t Val = C->getValue() & 255; 4133 unsigned Shift = 8; 4134 while (CurVT != MVT::i8) { 4135 Val = (Val << Shift) | Val; 4136 Shift <<= 1; 4137 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4138 } 4139 return DAG.getConstant(Val, VT); 4140 } else { 4141 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4142 unsigned Shift = 8; 4143 while (CurVT != MVT::i8) { 4144 Value = 4145 DAG.getNode(ISD::OR, VT, 4146 DAG.getNode(ISD::SHL, VT, Value, 4147 DAG.getConstant(Shift, MVT::i8)), Value); 4148 Shift <<= 1; 4149 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4150 } 4151 4152 return Value; 4153 } 4154} 4155 4156/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4157/// used when a memcpy is turned into a memset when the source is a constant 4158/// string ptr. 4159static SDOperand getMemsetStringVal(MVT::ValueType VT, 4160 SelectionDAG &DAG, TargetLowering &TLI, 4161 std::string &Str, unsigned Offset) { 4162 uint64_t Val = 0; 4163 unsigned MSB = MVT::getSizeInBits(VT) / 8; 4164 if (TLI.isLittleEndian()) 4165 Offset = Offset + MSB - 1; 4166 for (unsigned i = 0; i != MSB; ++i) { 4167 Val = (Val << 8) | (unsigned char)Str[Offset]; 4168 Offset += TLI.isLittleEndian() ? -1 : 1; 4169 } 4170 return DAG.getConstant(Val, VT); 4171} 4172 4173/// getMemBasePlusOffset - Returns base and offset node for the 4174static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4175 SelectionDAG &DAG, TargetLowering &TLI) { 4176 MVT::ValueType VT = Base.getValueType(); 4177 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4178} 4179 4180/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4181/// to replace the memset / memcpy is below the threshold. It also returns the 4182/// types of the sequence of memory ops to perform memset / memcpy. 4183static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4184 unsigned Limit, uint64_t Size, 4185 unsigned Align, TargetLowering &TLI) { 4186 MVT::ValueType VT; 4187 4188 if (TLI.allowsUnalignedMemoryAccesses()) { 4189 VT = MVT::i64; 4190 } else { 4191 switch (Align & 7) { 4192 case 0: 4193 VT = MVT::i64; 4194 break; 4195 case 4: 4196 VT = MVT::i32; 4197 break; 4198 case 2: 4199 VT = MVT::i16; 4200 break; 4201 default: 4202 VT = MVT::i8; 4203 break; 4204 } 4205 } 4206 4207 MVT::ValueType LVT = MVT::i64; 4208 while (!TLI.isTypeLegal(LVT)) 4209 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4210 assert(MVT::isInteger(LVT)); 4211 4212 if (VT > LVT) 4213 VT = LVT; 4214 4215 unsigned NumMemOps = 0; 4216 while (Size != 0) { 4217 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4218 while (VTSize > Size) { 4219 VT = (MVT::ValueType)((unsigned)VT - 1); 4220 VTSize >>= 1; 4221 } 4222 assert(MVT::isInteger(VT)); 4223 4224 if (++NumMemOps > Limit) 4225 return false; 4226 MemOps.push_back(VT); 4227 Size -= VTSize; 4228 } 4229 4230 return true; 4231} 4232 4233void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4234 SDOperand Op1 = getValue(I.getOperand(1)); 4235 SDOperand Op2 = getValue(I.getOperand(2)); 4236 SDOperand Op3 = getValue(I.getOperand(3)); 4237 SDOperand Op4 = getValue(I.getOperand(4)); 4238 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4239 if (Align == 0) Align = 1; 4240 4241 // If the source and destination are known to not be aliases, we can 4242 // lower memmove as memcpy. 4243 if (Op == ISD::MEMMOVE) { 4244 uint64_t Size = -1ULL; 4245 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 4246 Size = C->getValue(); 4247 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) == 4248 AliasAnalysis::NoAlias) 4249 Op = ISD::MEMCPY; 4250 } 4251 4252 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4253 std::vector<MVT::ValueType> MemOps; 4254 4255 // Expand memset / memcpy to a series of load / store ops 4256 // if the size operand falls below a certain threshold. 4257 SmallVector<SDOperand, 8> OutChains; 4258 switch (Op) { 4259 default: break; // Do nothing for now. 4260 case ISD::MEMSET: { 4261 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4262 Size->getValue(), Align, TLI)) { 4263 unsigned NumMemOps = MemOps.size(); 4264 unsigned Offset = 0; 4265 for (unsigned i = 0; i < NumMemOps; i++) { 4266 MVT::ValueType VT = MemOps[i]; 4267 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4268 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4269 SDOperand Store = DAG.getStore(getRoot(), Value, 4270 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4271 I.getOperand(1), Offset); 4272 OutChains.push_back(Store); 4273 Offset += VTSize; 4274 } 4275 } 4276 break; 4277 } 4278 case ISD::MEMCPY: { 4279 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4280 Size->getValue(), Align, TLI)) { 4281 unsigned NumMemOps = MemOps.size(); 4282 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4283 GlobalAddressSDNode *G = NULL; 4284 std::string Str; 4285 bool CopyFromStr = false; 4286 4287 if (Op2.getOpcode() == ISD::GlobalAddress) 4288 G = cast<GlobalAddressSDNode>(Op2); 4289 else if (Op2.getOpcode() == ISD::ADD && 4290 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4291 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4292 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4293 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4294 } 4295 if (G) { 4296 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4297 if (GV && GV->isConstant()) { 4298 Str = GV->getStringValue(false); 4299 if (!Str.empty()) { 4300 CopyFromStr = true; 4301 SrcOff += SrcDelta; 4302 } 4303 } 4304 } 4305 4306 for (unsigned i = 0; i < NumMemOps; i++) { 4307 MVT::ValueType VT = MemOps[i]; 4308 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4309 SDOperand Value, Chain, Store; 4310 4311 if (CopyFromStr) { 4312 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4313 Chain = getRoot(); 4314 Store = 4315 DAG.getStore(Chain, Value, 4316 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4317 I.getOperand(1), DstOff); 4318 } else { 4319 Value = DAG.getLoad(VT, getRoot(), 4320 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4321 I.getOperand(2), SrcOff, false, Align); 4322 Chain = Value.getValue(1); 4323 Store = 4324 DAG.getStore(Chain, Value, 4325 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4326 I.getOperand(1), DstOff, false, Align); 4327 } 4328 OutChains.push_back(Store); 4329 SrcOff += VTSize; 4330 DstOff += VTSize; 4331 } 4332 } 4333 break; 4334 } 4335 } 4336 4337 if (!OutChains.empty()) { 4338 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4339 &OutChains[0], OutChains.size())); 4340 return; 4341 } 4342 } 4343 4344 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1); 4345 SDOperand Node; 4346 switch(Op) { 4347 default: 4348 assert(0 && "Unknown Op"); 4349 case ISD::MEMCPY: 4350 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4351 break; 4352 case ISD::MEMMOVE: 4353 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4354 break; 4355 case ISD::MEMSET: 4356 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4357 break; 4358 } 4359 DAG.setRoot(Node); 4360} 4361 4362//===----------------------------------------------------------------------===// 4363// SelectionDAGISel code 4364//===----------------------------------------------------------------------===// 4365 4366unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4367 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 4368} 4369 4370void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4371 AU.addRequired<AliasAnalysis>(); 4372 AU.setPreservesAll(); 4373} 4374 4375 4376 4377bool SelectionDAGISel::runOnFunction(Function &Fn) { 4378 // Get alias analysis for load/store combining. 4379 AA = &getAnalysis<AliasAnalysis>(); 4380 4381 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4382 RegMap = MF.getSSARegMap(); 4383 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4384 4385 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4386 4387 if (ExceptionHandling) 4388 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4389 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4390 // Mark landing pad. 4391 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4392 4393 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4394 SelectBasicBlock(I, MF, FuncInfo); 4395 4396 // Add function live-ins to entry block live-in set. 4397 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4398 BB = FuncInfo.MBBMap[EntryBB]; 4399 if (!MF.livein_empty()) 4400 for (MachineFunction::livein_iterator I = MF.livein_begin(), 4401 E = MF.livein_end(); I != E; ++I) 4402 BB->addLiveIn(I->first); 4403 4404#ifndef NDEBUG 4405 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4406 "Not all catch info was assigned to a landing pad!"); 4407#endif 4408 4409 return true; 4410} 4411 4412SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4413 unsigned Reg) { 4414 SDOperand Op = getValue(V); 4415 assert((Op.getOpcode() != ISD::CopyFromReg || 4416 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4417 "Copy from a reg to the same reg!"); 4418 4419 MVT::ValueType SrcVT = Op.getValueType(); 4420 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT); 4421 unsigned NumRegs = TLI.getNumRegisters(SrcVT); 4422 SmallVector<SDOperand, 8> Regs(NumRegs); 4423 SmallVector<SDOperand, 8> Chains(NumRegs); 4424 4425 // Copy the value by legal parts into sequential virtual registers. 4426 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT); 4427 for (unsigned i = 0; i != NumRegs; ++i) 4428 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); 4429 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 4430} 4431 4432void SelectionDAGISel:: 4433LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4434 std::vector<SDOperand> &UnorderedChains) { 4435 // If this is the entry block, emit arguments. 4436 Function &F = *LLVMBB->getParent(); 4437 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4438 SDOperand OldRoot = SDL.DAG.getRoot(); 4439 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4440 4441 unsigned a = 0; 4442 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4443 AI != E; ++AI, ++a) 4444 if (!AI->use_empty()) { 4445 SDL.setValue(AI, Args[a]); 4446 4447 // If this argument is live outside of the entry block, insert a copy from 4448 // whereever we got it to the vreg that other BB's will reference it as. 4449 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4450 if (VMI != FuncInfo.ValueMap.end()) { 4451 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4452 UnorderedChains.push_back(Copy); 4453 } 4454 } 4455 4456 // Finally, if the target has anything special to do, allow it to do so. 4457 // FIXME: this should insert code into the DAG! 4458 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4459} 4460 4461static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4462 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4463 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4464 if (isSelector(I)) { 4465 // Apply the catch info to DestBB. 4466 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4467#ifndef NDEBUG 4468 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 4469 FLI.CatchInfoFound.insert(I); 4470#endif 4471 } 4472} 4473 4474/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 4475/// DAG and fixes their tailcall attribute operand. 4476static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 4477 TargetLowering& TLI) { 4478 SDNode * Ret = NULL; 4479 SDOperand Terminator = DAG.getRoot(); 4480 4481 // Find RET node. 4482 if (Terminator.getOpcode() == ISD::RET) { 4483 Ret = Terminator.Val; 4484 } 4485 4486 // Fix tail call attribute of CALL nodes. 4487 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 4488 BI = prior(DAG.allnodes_end()); BI != BE; --BI) { 4489 if (BI->getOpcode() == ISD::CALL) { 4490 SDOperand OpRet(Ret, 0); 4491 SDOperand OpCall(static_cast<SDNode*>(BI), 0); 4492 bool isMarkedTailCall = 4493 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0; 4494 // If CALL node has tail call attribute set to true and the call is not 4495 // eligible (no RET or the target rejects) the attribute is fixed to 4496 // false. The TargetLowering::IsEligibleForTailCallOptimization function 4497 // must correctly identify tail call optimizable calls. 4498 if (isMarkedTailCall && 4499 (Ret==NULL || 4500 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) { 4501 SmallVector<SDOperand, 32> Ops; 4502 unsigned idx=0; 4503 for(SDNode::op_iterator I =OpCall.Val->op_begin(), 4504 E=OpCall.Val->op_end(); I!=E; I++, idx++) { 4505 if (idx!=3) 4506 Ops.push_back(*I); 4507 else 4508 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy())); 4509 } 4510 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 4511 } 4512 } 4513 } 4514} 4515 4516void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4517 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4518 FunctionLoweringInfo &FuncInfo) { 4519 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo); 4520 4521 std::vector<SDOperand> UnorderedChains; 4522 4523 // Lower any arguments needed in this block if this is the entry block. 4524 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4525 LowerArguments(LLVMBB, SDL, UnorderedChains); 4526 4527 BB = FuncInfo.MBBMap[LLVMBB]; 4528 SDL.setCurrentBasicBlock(BB); 4529 4530 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4531 4532 if (ExceptionHandling && MMI && BB->isLandingPad()) { 4533 // Add a label to mark the beginning of the landing pad. Deletion of the 4534 // landing pad can thus be detected via the MachineModuleInfo. 4535 unsigned LabelID = MMI->addLandingPad(BB); 4536 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 4537 DAG.getConstant(LabelID, MVT::i32))); 4538 4539 // Mark exception register as live in. 4540 unsigned Reg = TLI.getExceptionAddressRegister(); 4541 if (Reg) BB->addLiveIn(Reg); 4542 4543 // Mark exception selector register as live in. 4544 Reg = TLI.getExceptionSelectorRegister(); 4545 if (Reg) BB->addLiveIn(Reg); 4546 4547 // FIXME: Hack around an exception handling flaw (PR1508): the personality 4548 // function and list of typeids logically belong to the invoke (or, if you 4549 // like, the basic block containing the invoke), and need to be associated 4550 // with it in the dwarf exception handling tables. Currently however the 4551 // information is provided by an intrinsic (eh.selector) that can be moved 4552 // to unexpected places by the optimizers: if the unwind edge is critical, 4553 // then breaking it can result in the intrinsics being in the successor of 4554 // the landing pad, not the landing pad itself. This results in exceptions 4555 // not being caught because no typeids are associated with the invoke. 4556 // This may not be the only way things can go wrong, but it is the only way 4557 // we try to work around for the moment. 4558 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 4559 4560 if (Br && Br->isUnconditional()) { // Critical edge? 4561 BasicBlock::iterator I, E; 4562 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 4563 if (isSelector(I)) 4564 break; 4565 4566 if (I == E) 4567 // No catch info found - try to extract some from the successor. 4568 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 4569 } 4570 } 4571 4572 // Lower all of the non-terminator instructions. 4573 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4574 I != E; ++I) 4575 SDL.visit(*I); 4576 4577 // Ensure that all instructions which are used outside of their defining 4578 // blocks are available as virtual registers. Invoke is handled elsewhere. 4579 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4580 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 4581 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4582 if (VMI != FuncInfo.ValueMap.end()) 4583 UnorderedChains.push_back( 4584 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4585 } 4586 4587 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4588 // ensure constants are generated when needed. Remember the virtual registers 4589 // that need to be added to the Machine PHI nodes as input. We cannot just 4590 // directly add them, because expansion might result in multiple MBB's for one 4591 // BB. As such, the start of the BB might correspond to a different MBB than 4592 // the end. 4593 // 4594 TerminatorInst *TI = LLVMBB->getTerminator(); 4595 4596 // Emit constants only once even if used by multiple PHI nodes. 4597 std::map<Constant*, unsigned> ConstantsOut; 4598 4599 // Vector bool would be better, but vector<bool> is really slow. 4600 std::vector<unsigned char> SuccsHandled; 4601 if (TI->getNumSuccessors()) 4602 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4603 4604 // Check successor nodes' PHI nodes that expect a constant to be available 4605 // from this block. 4606 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4607 BasicBlock *SuccBB = TI->getSuccessor(succ); 4608 if (!isa<PHINode>(SuccBB->begin())) continue; 4609 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4610 4611 // If this terminator has multiple identical successors (common for 4612 // switches), only handle each succ once. 4613 unsigned SuccMBBNo = SuccMBB->getNumber(); 4614 if (SuccsHandled[SuccMBBNo]) continue; 4615 SuccsHandled[SuccMBBNo] = true; 4616 4617 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4618 PHINode *PN; 4619 4620 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4621 // nodes and Machine PHI nodes, but the incoming operands have not been 4622 // emitted yet. 4623 for (BasicBlock::iterator I = SuccBB->begin(); 4624 (PN = dyn_cast<PHINode>(I)); ++I) { 4625 // Ignore dead phi's. 4626 if (PN->use_empty()) continue; 4627 4628 unsigned Reg; 4629 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4630 4631 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4632 unsigned &RegOut = ConstantsOut[C]; 4633 if (RegOut == 0) { 4634 RegOut = FuncInfo.CreateRegForValue(C); 4635 UnorderedChains.push_back( 4636 SDL.CopyValueToVirtualRegister(C, RegOut)); 4637 } 4638 Reg = RegOut; 4639 } else { 4640 Reg = FuncInfo.ValueMap[PHIOp]; 4641 if (Reg == 0) { 4642 assert(isa<AllocaInst>(PHIOp) && 4643 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4644 "Didn't codegen value into a register!??"); 4645 Reg = FuncInfo.CreateRegForValue(PHIOp); 4646 UnorderedChains.push_back( 4647 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4648 } 4649 } 4650 4651 // Remember that this register needs to added to the machine PHI node as 4652 // the input for this MBB. 4653 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4654 unsigned NumRegisters = TLI.getNumRegisters(VT); 4655 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 4656 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4657 } 4658 } 4659 ConstantsOut.clear(); 4660 4661 // Turn all of the unordered chains into one factored node. 4662 if (!UnorderedChains.empty()) { 4663 SDOperand Root = SDL.getRoot(); 4664 if (Root.getOpcode() != ISD::EntryToken) { 4665 unsigned i = 0, e = UnorderedChains.size(); 4666 for (; i != e; ++i) { 4667 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4668 if (UnorderedChains[i].Val->getOperand(0) == Root) 4669 break; // Don't add the root if we already indirectly depend on it. 4670 } 4671 4672 if (i == e) 4673 UnorderedChains.push_back(Root); 4674 } 4675 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4676 &UnorderedChains[0], UnorderedChains.size())); 4677 } 4678 4679 // Lower the terminator after the copies are emitted. 4680 SDL.visit(*LLVMBB->getTerminator()); 4681 4682 // Copy over any CaseBlock records that may now exist due to SwitchInst 4683 // lowering, as well as any jump table information. 4684 SwitchCases.clear(); 4685 SwitchCases = SDL.SwitchCases; 4686 JTCases.clear(); 4687 JTCases = SDL.JTCases; 4688 BitTestCases.clear(); 4689 BitTestCases = SDL.BitTestCases; 4690 4691 // Make sure the root of the DAG is up-to-date. 4692 DAG.setRoot(SDL.getRoot()); 4693 4694 // Check whether calls in this block are real tail calls. Fix up CALL nodes 4695 // with correct tailcall attribute so that the target can rely on the tailcall 4696 // attribute indicating whether the call is really eligible for tail call 4697 // optimization. 4698 CheckDAGForTailCallsAndFixThem(DAG, TLI); 4699} 4700 4701void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4702 DOUT << "Lowered selection DAG:\n"; 4703 DEBUG(DAG.dump()); 4704 4705 // Run the DAG combiner in pre-legalize mode. 4706 DAG.Combine(false, *AA); 4707 4708 DOUT << "Optimized lowered selection DAG:\n"; 4709 DEBUG(DAG.dump()); 4710 4711 // Second step, hack on the DAG until it only uses operations and types that 4712 // the target supports. 4713#if 0 // Enable this some day. 4714 DAG.LegalizeTypes(); 4715 // Someday even later, enable a dag combine pass here. 4716#endif 4717 DAG.Legalize(); 4718 4719 DOUT << "Legalized selection DAG:\n"; 4720 DEBUG(DAG.dump()); 4721 4722 // Run the DAG combiner in post-legalize mode. 4723 DAG.Combine(true, *AA); 4724 4725 DOUT << "Optimized legalized selection DAG:\n"; 4726 DEBUG(DAG.dump()); 4727 4728 if (ViewISelDAGs) DAG.viewGraph(); 4729 4730 // Third, instruction select all of the operations to machine code, adding the 4731 // code to the MachineBasicBlock. 4732 InstructionSelectBasicBlock(DAG); 4733 4734 DOUT << "Selected machine code:\n"; 4735 DEBUG(BB->dump()); 4736} 4737 4738void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4739 FunctionLoweringInfo &FuncInfo) { 4740 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4741 { 4742 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4743 CurDAG = &DAG; 4744 4745 // First step, lower LLVM code to some DAG. This DAG may use operations and 4746 // types that are not supported by the target. 4747 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4748 4749 // Second step, emit the lowered DAG as machine code. 4750 CodeGenAndEmitDAG(DAG); 4751 } 4752 4753 DOUT << "Total amount of phi nodes to update: " 4754 << PHINodesToUpdate.size() << "\n"; 4755 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4756 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4757 << ", " << PHINodesToUpdate[i].second << ")\n";); 4758 4759 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4760 // PHI nodes in successors. 4761 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4762 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4763 MachineInstr *PHI = PHINodesToUpdate[i].first; 4764 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4765 "This is not a machine PHI node that we are updating!"); 4766 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4767 PHI->addMachineBasicBlockOperand(BB); 4768 } 4769 return; 4770 } 4771 4772 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4773 // Lower header first, if it wasn't already lowered 4774 if (!BitTestCases[i].Emitted) { 4775 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4776 CurDAG = &HSDAG; 4777 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo); 4778 // Set the current basic block to the mbb we wish to insert the code into 4779 BB = BitTestCases[i].Parent; 4780 HSDL.setCurrentBasicBlock(BB); 4781 // Emit the code 4782 HSDL.visitBitTestHeader(BitTestCases[i]); 4783 HSDAG.setRoot(HSDL.getRoot()); 4784 CodeGenAndEmitDAG(HSDAG); 4785 } 4786 4787 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4788 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4789 CurDAG = &BSDAG; 4790 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo); 4791 // Set the current basic block to the mbb we wish to insert the code into 4792 BB = BitTestCases[i].Cases[j].ThisBB; 4793 BSDL.setCurrentBasicBlock(BB); 4794 // Emit the code 4795 if (j+1 != ej) 4796 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 4797 BitTestCases[i].Reg, 4798 BitTestCases[i].Cases[j]); 4799 else 4800 BSDL.visitBitTestCase(BitTestCases[i].Default, 4801 BitTestCases[i].Reg, 4802 BitTestCases[i].Cases[j]); 4803 4804 4805 BSDAG.setRoot(BSDL.getRoot()); 4806 CodeGenAndEmitDAG(BSDAG); 4807 } 4808 4809 // Update PHI Nodes 4810 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4811 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4812 MachineBasicBlock *PHIBB = PHI->getParent(); 4813 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4814 "This is not a machine PHI node that we are updating!"); 4815 // This is "default" BB. We have two jumps to it. From "header" BB and 4816 // from last "case" BB. 4817 if (PHIBB == BitTestCases[i].Default) { 4818 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4819 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent); 4820 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4821 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB); 4822 } 4823 // One of "cases" BB. 4824 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4825 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 4826 if (cBB->succ_end() != 4827 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 4828 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4829 PHI->addMachineBasicBlockOperand(cBB); 4830 } 4831 } 4832 } 4833 } 4834 4835 // If the JumpTable record is filled in, then we need to emit a jump table. 4836 // Updating the PHI nodes is tricky in this case, since we need to determine 4837 // whether the PHI is a successor of the range check MBB or the jump table MBB 4838 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 4839 // Lower header first, if it wasn't already lowered 4840 if (!JTCases[i].first.Emitted) { 4841 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4842 CurDAG = &HSDAG; 4843 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo); 4844 // Set the current basic block to the mbb we wish to insert the code into 4845 BB = JTCases[i].first.HeaderBB; 4846 HSDL.setCurrentBasicBlock(BB); 4847 // Emit the code 4848 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 4849 HSDAG.setRoot(HSDL.getRoot()); 4850 CodeGenAndEmitDAG(HSDAG); 4851 } 4852 4853 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4854 CurDAG = &JSDAG; 4855 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo); 4856 // Set the current basic block to the mbb we wish to insert the code into 4857 BB = JTCases[i].second.MBB; 4858 JSDL.setCurrentBasicBlock(BB); 4859 // Emit the code 4860 JSDL.visitJumpTable(JTCases[i].second); 4861 JSDAG.setRoot(JSDL.getRoot()); 4862 CodeGenAndEmitDAG(JSDAG); 4863 4864 // Update PHI Nodes 4865 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4866 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4867 MachineBasicBlock *PHIBB = PHI->getParent(); 4868 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4869 "This is not a machine PHI node that we are updating!"); 4870 // "default" BB. We can go there only from header BB. 4871 if (PHIBB == JTCases[i].second.Default) { 4872 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4873 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB); 4874 } 4875 // JT BB. Just iterate over successors here 4876 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 4877 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4878 PHI->addMachineBasicBlockOperand(BB); 4879 } 4880 } 4881 } 4882 4883 // If the switch block involved a branch to one of the actual successors, we 4884 // need to update PHI nodes in that block. 4885 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4886 MachineInstr *PHI = PHINodesToUpdate[i].first; 4887 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4888 "This is not a machine PHI node that we are updating!"); 4889 if (BB->isSuccessor(PHI->getParent())) { 4890 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4891 PHI->addMachineBasicBlockOperand(BB); 4892 } 4893 } 4894 4895 // If we generated any switch lowering information, build and codegen any 4896 // additional DAGs necessary. 4897 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 4898 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4899 CurDAG = &SDAG; 4900 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo); 4901 4902 // Set the current basic block to the mbb we wish to insert the code into 4903 BB = SwitchCases[i].ThisBB; 4904 SDL.setCurrentBasicBlock(BB); 4905 4906 // Emit the code 4907 SDL.visitSwitchCase(SwitchCases[i]); 4908 SDAG.setRoot(SDL.getRoot()); 4909 CodeGenAndEmitDAG(SDAG); 4910 4911 // Handle any PHI nodes in successors of this chunk, as if we were coming 4912 // from the original BB before switch expansion. Note that PHI nodes can 4913 // occur multiple times in PHINodesToUpdate. We have to be very careful to 4914 // handle them the right number of times. 4915 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 4916 for (MachineBasicBlock::iterator Phi = BB->begin(); 4917 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 4918 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 4919 for (unsigned pn = 0; ; ++pn) { 4920 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 4921 if (PHINodesToUpdate[pn].first == Phi) { 4922 Phi->addRegOperand(PHINodesToUpdate[pn].second, false); 4923 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB); 4924 break; 4925 } 4926 } 4927 } 4928 4929 // Don't process RHS if same block as LHS. 4930 if (BB == SwitchCases[i].FalseBB) 4931 SwitchCases[i].FalseBB = 0; 4932 4933 // If we haven't handled the RHS, do so now. Otherwise, we're done. 4934 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 4935 SwitchCases[i].FalseBB = 0; 4936 } 4937 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 4938 } 4939} 4940 4941 4942//===----------------------------------------------------------------------===// 4943/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 4944/// target node in the graph. 4945void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 4946 if (ViewSchedDAGs) DAG.viewGraph(); 4947 4948 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 4949 4950 if (!Ctor) { 4951 Ctor = ISHeuristic; 4952 RegisterScheduler::setDefault(Ctor); 4953 } 4954 4955 ScheduleDAG *SL = Ctor(this, &DAG, BB); 4956 BB = SL->Run(); 4957 4958 if (ViewSUnitDAGs) SL->viewGraph(); 4959 4960 delete SL; 4961} 4962 4963 4964HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 4965 return new HazardRecognizer(); 4966} 4967 4968//===----------------------------------------------------------------------===// 4969// Helper functions used by the generated instruction selector. 4970//===----------------------------------------------------------------------===// 4971// Calls to these methods are generated by tblgen. 4972 4973/// CheckAndMask - The isel is trying to match something like (and X, 255). If 4974/// the dag combiner simplified the 255, we still want to match. RHS is the 4975/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 4976/// specified in the .td file (e.g. 255). 4977bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 4978 int64_t DesiredMaskS) const { 4979 uint64_t ActualMask = RHS->getValue(); 4980 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4981 4982 // If the actual mask exactly matches, success! 4983 if (ActualMask == DesiredMask) 4984 return true; 4985 4986 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4987 if (ActualMask & ~DesiredMask) 4988 return false; 4989 4990 // Otherwise, the DAG Combiner may have proven that the value coming in is 4991 // either already zero or is not demanded. Check for known zero input bits. 4992 uint64_t NeededMask = DesiredMask & ~ActualMask; 4993 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 4994 return true; 4995 4996 // TODO: check to see if missing bits are just not demanded. 4997 4998 // Otherwise, this pattern doesn't match. 4999 return false; 5000} 5001 5002/// CheckOrMask - The isel is trying to match something like (or X, 255). If 5003/// the dag combiner simplified the 255, we still want to match. RHS is the 5004/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 5005/// specified in the .td file (e.g. 255). 5006bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 5007 int64_t DesiredMaskS) const { 5008 uint64_t ActualMask = RHS->getValue(); 5009 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 5010 5011 // If the actual mask exactly matches, success! 5012 if (ActualMask == DesiredMask) 5013 return true; 5014 5015 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5016 if (ActualMask & ~DesiredMask) 5017 return false; 5018 5019 // Otherwise, the DAG Combiner may have proven that the value coming in is 5020 // either already zero or is not demanded. Check for known zero input bits. 5021 uint64_t NeededMask = DesiredMask & ~ActualMask; 5022 5023 uint64_t KnownZero, KnownOne; 5024 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 5025 5026 // If all the missing bits in the or are already known to be set, match! 5027 if ((NeededMask & KnownOne) == NeededMask) 5028 return true; 5029 5030 // TODO: check to see if missing bits are just not demanded. 5031 5032 // Otherwise, this pattern doesn't match. 5033 return false; 5034} 5035 5036 5037/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 5038/// by tblgen. Others should not call it. 5039void SelectionDAGISel:: 5040SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 5041 std::vector<SDOperand> InOps; 5042 std::swap(InOps, Ops); 5043 5044 Ops.push_back(InOps[0]); // input chain. 5045 Ops.push_back(InOps[1]); // input asm string. 5046 5047 unsigned i = 2, e = InOps.size(); 5048 if (InOps[e-1].getValueType() == MVT::Flag) 5049 --e; // Don't process a flag operand if it is here. 5050 5051 while (i != e) { 5052 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 5053 if ((Flags & 7) != 4 /*MEM*/) { 5054 // Just skip over this operand, copying the operands verbatim. 5055 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 5056 i += (Flags >> 3) + 1; 5057 } else { 5058 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 5059 // Otherwise, this is a memory operand. Ask the target to select it. 5060 std::vector<SDOperand> SelOps; 5061 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 5062 cerr << "Could not match memory address. Inline asm failure!\n"; 5063 exit(1); 5064 } 5065 5066 // Add this to the output node. 5067 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 5068 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 5069 IntPtrTy)); 5070 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 5071 i += 2; 5072 } 5073 } 5074 5075 // Add the flag input back if present. 5076 if (e != InOps.size()) 5077 Ops.push_back(InOps.back()); 5078} 5079 5080char SelectionDAGISel::ID = 0; 5081