SelectionDAGISel.cpp revision 0a0da619eb7a072836cf2c5debee1c5c7c8f5496
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "ScheduleDAGSDNodes.h" 17#include "SelectionDAGBuilder.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/Statistic.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/BranchProbabilityInfo.h" 22#include "llvm/Analysis/CFG.h" 23#include "llvm/Analysis/TargetTransformInfo.h" 24#include "llvm/CodeGen/FastISel.h" 25#include "llvm/CodeGen/FunctionLoweringInfo.h" 26#include "llvm/CodeGen/GCMetadata.h" 27#include "llvm/CodeGen/GCStrategy.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineModuleInfo.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/DebugInfo.h" 37#include "llvm/IR/Constants.h" 38#include "llvm/IR/Function.h" 39#include "llvm/IR/InlineAsm.h" 40#include "llvm/IR/Instructions.h" 41#include "llvm/IR/IntrinsicInst.h" 42#include "llvm/IR/Intrinsics.h" 43#include "llvm/IR/LLVMContext.h" 44#include "llvm/IR/Module.h" 45#include "llvm/Support/Compiler.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/ErrorHandling.h" 48#include "llvm/Support/Timer.h" 49#include "llvm/Support/raw_ostream.h" 50#include "llvm/Target/TargetInstrInfo.h" 51#include "llvm/Target/TargetIntrinsicInfo.h" 52#include "llvm/Target/TargetLibraryInfo.h" 53#include "llvm/Target/TargetLowering.h" 54#include "llvm/Target/TargetMachine.h" 55#include "llvm/Target/TargetOptions.h" 56#include "llvm/Target/TargetRegisterInfo.h" 57#include "llvm/Target/TargetSubtargetInfo.h" 58#include "llvm/Transforms/Utils/BasicBlockUtils.h" 59#include <algorithm> 60using namespace llvm; 61 62STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 63STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 64STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 65STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 66STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 67STATISTIC(NumEntryBlocks, "Number of entry blocks encountered"); 68STATISTIC(NumFastIselFailLowerArguments, 69 "Number of entry blocks where fast isel failed to lower arguments"); 70 71#ifndef NDEBUG 72static cl::opt<bool> 73EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 74 cl::desc("Enable extra verbose messages in the \"fast\" " 75 "instruction selector")); 76 77 // Terminators 78STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 79STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 80STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 81STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 82STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 83STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 84STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 85 86 // Standard binary operators... 87STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 88STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 89STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 90STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 91STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 92STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 93STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 94STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 95STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 96STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 97STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 98STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 99 100 // Logical operators... 101STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 102STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 103STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 104 105 // Memory instructions... 106STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 107STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 108STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 109STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 110STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 111STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 112STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 113 114 // Convert instructions... 115STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 116STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 117STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 118STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 119STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 120STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 121STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 122STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 123STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 124STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 125STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 126STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 127 128 // Other instructions... 129STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 130STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 131STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 132STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 133STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 134STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 135STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 136STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 137STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 138STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 139STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 140STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 141STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 142STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 143STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 144#endif 145 146static cl::opt<bool> 147EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 148 cl::desc("Enable verbose messages in the \"fast\" " 149 "instruction selector")); 150static cl::opt<bool> 151EnableFastISelAbort("fast-isel-abort", cl::Hidden, 152 cl::desc("Enable abort calls when \"fast\" instruction selection " 153 "fails to lower an instruction")); 154static cl::opt<bool> 155EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden, 156 cl::desc("Enable abort calls when \"fast\" instruction selection " 157 "fails to lower a formal argument")); 158 159static cl::opt<bool> 160UseMBPI("use-mbpi", 161 cl::desc("use Machine Branch Probability Info"), 162 cl::init(true), cl::Hidden); 163 164#ifndef NDEBUG 165static cl::opt<bool> 166ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 167 cl::desc("Pop up a window to show dags before the first " 168 "dag combine pass")); 169static cl::opt<bool> 170ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 171 cl::desc("Pop up a window to show dags before legalize types")); 172static cl::opt<bool> 173ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 174 cl::desc("Pop up a window to show dags before legalize")); 175static cl::opt<bool> 176ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 177 cl::desc("Pop up a window to show dags before the second " 178 "dag combine pass")); 179static cl::opt<bool> 180ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 181 cl::desc("Pop up a window to show dags before the post legalize types" 182 " dag combine pass")); 183static cl::opt<bool> 184ViewISelDAGs("view-isel-dags", cl::Hidden, 185 cl::desc("Pop up a window to show isel dags as they are selected")); 186static cl::opt<bool> 187ViewSchedDAGs("view-sched-dags", cl::Hidden, 188 cl::desc("Pop up a window to show sched dags as they are processed")); 189static cl::opt<bool> 190ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 191 cl::desc("Pop up a window to show SUnit dags after they are processed")); 192#else 193static const bool ViewDAGCombine1 = false, 194 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 195 ViewDAGCombine2 = false, 196 ViewDAGCombineLT = false, 197 ViewISelDAGs = false, ViewSchedDAGs = false, 198 ViewSUnitDAGs = false; 199#endif 200 201//===---------------------------------------------------------------------===// 202/// 203/// RegisterScheduler class - Track the registration of instruction schedulers. 204/// 205//===---------------------------------------------------------------------===// 206MachinePassRegistry RegisterScheduler::Registry; 207 208//===---------------------------------------------------------------------===// 209/// 210/// ISHeuristic command line option for instruction schedulers. 211/// 212//===---------------------------------------------------------------------===// 213static cl::opt<RegisterScheduler::FunctionPassCtor, false, 214 RegisterPassParser<RegisterScheduler> > 215ISHeuristic("pre-RA-sched", 216 cl::init(&createDefaultScheduler), 217 cl::desc("Instruction schedulers available (before register" 218 " allocation):")); 219 220static RegisterScheduler 221defaultListDAGScheduler("default", "Best scheduler for the target", 222 createDefaultScheduler); 223 224namespace llvm { 225 //===--------------------------------------------------------------------===// 226 /// \brief This struct is used by SelectionDAGISel to temporarily override 227 /// the optimization level on a per-function basis. 228 class OptLevelChanger { 229 SelectionDAGISel &IS; 230 CodeGenOpt::Level SavedOptLevel; 231 232 public: 233 OptLevelChanger(SelectionDAGISel &ISel, 234 CodeGenOpt::Level NewOptLevel) : IS(ISel) { 235 SavedOptLevel = IS.OptLevel; 236 if (NewOptLevel == SavedOptLevel) 237 return; 238 IS.OptLevel = NewOptLevel; 239 IS.TM.setOptLevel(NewOptLevel); 240 DEBUG(dbgs() << "\nChanging optimization level for Function " 241 << IS.MF->getFunction()->getName() << "\n"); 242 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel 243 << " ; After: -O" << NewOptLevel << "\n"); 244 } 245 246 ~OptLevelChanger() { 247 if (IS.OptLevel == SavedOptLevel) 248 return; 249 DEBUG(dbgs() << "\nRestoring optimization level for Function " 250 << IS.MF->getFunction()->getName() << "\n"); 251 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel 252 << " ; After: -O" << SavedOptLevel << "\n"); 253 IS.OptLevel = SavedOptLevel; 254 IS.TM.setOptLevel(SavedOptLevel); 255 } 256 }; 257 258 //===--------------------------------------------------------------------===// 259 /// createDefaultScheduler - This creates an instruction scheduler appropriate 260 /// for the target. 261 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 262 CodeGenOpt::Level OptLevel) { 263 const TargetLowering *TLI = IS->getTargetLowering(); 264 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 265 266 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() || 267 TLI->getSchedulingPreference() == Sched::Source) 268 return createSourceListDAGScheduler(IS, OptLevel); 269 if (TLI->getSchedulingPreference() == Sched::RegPressure) 270 return createBURRListDAGScheduler(IS, OptLevel); 271 if (TLI->getSchedulingPreference() == Sched::Hybrid) 272 return createHybridListDAGScheduler(IS, OptLevel); 273 if (TLI->getSchedulingPreference() == Sched::VLIW) 274 return createVLIWDAGScheduler(IS, OptLevel); 275 assert(TLI->getSchedulingPreference() == Sched::ILP && 276 "Unknown sched type!"); 277 return createILPListDAGScheduler(IS, OptLevel); 278 } 279} 280 281// EmitInstrWithCustomInserter - This method should be implemented by targets 282// that mark instructions with the 'usesCustomInserter' flag. These 283// instructions are special in various ways, which require special support to 284// insert. The specified MachineInstr is created but not inserted into any 285// basic blocks, and this method is called to expand it into a sequence of 286// instructions, potentially also creating new basic blocks and control flow. 287// When new basic blocks are inserted and the edges from MBB to its successors 288// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 289// DenseMap. 290MachineBasicBlock * 291TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 292 MachineBasicBlock *MBB) const { 293#ifndef NDEBUG 294 dbgs() << "If a target marks an instruction with " 295 "'usesCustomInserter', it must implement " 296 "TargetLowering::EmitInstrWithCustomInserter!"; 297#endif 298 llvm_unreachable(0); 299} 300 301void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 302 SDNode *Node) const { 303 assert(!MI->hasPostISelHook() && 304 "If a target marks an instruction with 'hasPostISelHook', " 305 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 306} 307 308//===----------------------------------------------------------------------===// 309// SelectionDAGISel code 310//===----------------------------------------------------------------------===// 311 312SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, 313 CodeGenOpt::Level OL) : 314 MachineFunctionPass(ID), TM(tm), 315 FuncInfo(new FunctionLoweringInfo(TM)), 316 CurDAG(new SelectionDAG(tm, OL)), 317 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 318 GFI(), 319 OptLevel(OL), 320 DAGSize(0) { 321 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 322 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 323 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 324 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 325 } 326 327SelectionDAGISel::~SelectionDAGISel() { 328 delete SDB; 329 delete CurDAG; 330 delete FuncInfo; 331} 332 333void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 334 AU.addRequired<AliasAnalysis>(); 335 AU.addPreserved<AliasAnalysis>(); 336 AU.addRequired<GCModuleInfo>(); 337 AU.addPreserved<GCModuleInfo>(); 338 AU.addRequired<TargetLibraryInfo>(); 339 if (UseMBPI && OptLevel != CodeGenOpt::None) 340 AU.addRequired<BranchProbabilityInfo>(); 341 MachineFunctionPass::getAnalysisUsage(AU); 342} 343 344/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 345/// may trap on it. In this case we have to split the edge so that the path 346/// through the predecessor block that doesn't go to the phi block doesn't 347/// execute the possibly trapping instruction. 348/// 349/// This is required for correctness, so it must be done at -O0. 350/// 351static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 352 // Loop for blocks with phi nodes. 353 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 354 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 355 if (PN == 0) continue; 356 357 ReprocessBlock: 358 // For each block with a PHI node, check to see if any of the input values 359 // are potentially trapping constant expressions. Constant expressions are 360 // the only potentially trapping value that can occur as the argument to a 361 // PHI. 362 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 363 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 364 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 365 if (CE == 0 || !CE->canTrap()) continue; 366 367 // The only case we have to worry about is when the edge is critical. 368 // Since this block has a PHI Node, we assume it has multiple input 369 // edges: check to see if the pred has multiple successors. 370 BasicBlock *Pred = PN->getIncomingBlock(i); 371 if (Pred->getTerminator()->getNumSuccessors() == 1) 372 continue; 373 374 // Okay, we have to split this edge. 375 SplitCriticalEdge(Pred->getTerminator(), 376 GetSuccessorNumber(Pred, BB), SDISel, true); 377 goto ReprocessBlock; 378 } 379 } 380} 381 382bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 383 // Do some sanity-checking on the command-line options. 384 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 385 "-fast-isel-verbose requires -fast-isel"); 386 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 387 "-fast-isel-abort requires -fast-isel"); 388 389 const Function &Fn = *mf.getFunction(); 390 const TargetInstrInfo &TII = *TM.getInstrInfo(); 391 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 392 393 MF = &mf; 394 RegInfo = &MF->getRegInfo(); 395 AA = &getAnalysis<AliasAnalysis>(); 396 LibInfo = &getAnalysis<TargetLibraryInfo>(); 397 TTI = getAnalysisIfAvailable<TargetTransformInfo>(); 398 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 399 400 TargetSubtargetInfo &ST = 401 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 402 ST.resetSubtargetFeatures(MF); 403 TM.resetTargetOptions(MF); 404 405 // Reset OptLevel to None for optnone functions. 406 CodeGenOpt::Level NewOptLevel = OptLevel; 407 if (Fn.hasFnAttribute(Attribute::OptimizeNone)) 408 NewOptLevel = CodeGenOpt::None; 409 OptLevelChanger OLC(*this, NewOptLevel); 410 411 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 412 413 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 414 415 CurDAG->init(*MF, TTI); 416 FuncInfo->set(Fn, *MF); 417 418 if (UseMBPI && OptLevel != CodeGenOpt::None) 419 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 420 else 421 FuncInfo->BPI = 0; 422 423 SDB->init(GFI, *AA, LibInfo); 424 425 MF->setHasMSInlineAsm(false); 426 SelectAllBasicBlocks(Fn); 427 428 // If the first basic block in the function has live ins that need to be 429 // copied into vregs, emit the copies into the top of the block before 430 // emitting the code for the block. 431 MachineBasicBlock *EntryMBB = MF->begin(); 432 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 433 434 DenseMap<unsigned, unsigned> LiveInMap; 435 if (!FuncInfo->ArgDbgValues.empty()) 436 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 437 E = RegInfo->livein_end(); LI != E; ++LI) 438 if (LI->second) 439 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 440 441 // Insert DBG_VALUE instructions for function arguments to the entry block. 442 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 443 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 444 bool hasFI = MI->getOperand(0).isFI(); 445 unsigned Reg = hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg(); 446 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 447 EntryMBB->insert(EntryMBB->begin(), MI); 448 else { 449 MachineInstr *Def = RegInfo->getVRegDef(Reg); 450 if (Def) { 451 MachineBasicBlock::iterator InsertPos = Def; 452 // FIXME: VR def may not be in entry block. 453 Def->getParent()->insert(llvm::next(InsertPos), MI); 454 } else 455 DEBUG(dbgs() << "Dropping debug info for dead vreg" 456 << TargetRegisterInfo::virtReg2Index(Reg) << "\n"); 457 } 458 459 // If Reg is live-in then update debug info to track its copy in a vreg. 460 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 461 if (LDI != LiveInMap.end()) { 462 assert(!hasFI && "There's no handling of frame pointer updating here yet " 463 "- add if needed"); 464 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 465 MachineBasicBlock::iterator InsertPos = Def; 466 const MDNode *Variable = 467 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 468 bool IsIndirect = MI->isIndirectDebugValue(); 469 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; 470 // Def is never a terminator here, so it is ok to increment InsertPos. 471 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 472 TII.get(TargetOpcode::DBG_VALUE), 473 IsIndirect, 474 LDI->second, Offset, Variable); 475 476 // If this vreg is directly copied into an exported register then 477 // that COPY instructions also need DBG_VALUE, if it is the only 478 // user of LDI->second. 479 MachineInstr *CopyUseMI = NULL; 480 for (MachineRegisterInfo::use_iterator 481 UI = RegInfo->use_begin(LDI->second); 482 MachineInstr *UseMI = UI.skipInstruction();) { 483 if (UseMI->isDebugValue()) continue; 484 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 485 CopyUseMI = UseMI; continue; 486 } 487 // Otherwise this is another use or second copy use. 488 CopyUseMI = NULL; break; 489 } 490 if (CopyUseMI) { 491 MachineInstr *NewMI = 492 BuildMI(*MF, CopyUseMI->getDebugLoc(), 493 TII.get(TargetOpcode::DBG_VALUE), 494 IsIndirect, 495 CopyUseMI->getOperand(0).getReg(), 496 Offset, Variable); 497 MachineBasicBlock::iterator Pos = CopyUseMI; 498 EntryMBB->insertAfter(Pos, NewMI); 499 } 500 } 501 } 502 503 // Determine if there are any calls in this machine function. 504 MachineFrameInfo *MFI = MF->getFrameInfo(); 505 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E; 506 ++I) { 507 508 if (MFI->hasCalls() && MF->hasMSInlineAsm()) 509 break; 510 511 const MachineBasicBlock *MBB = I; 512 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end(); 513 II != IE; ++II) { 514 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 515 if ((MCID.isCall() && !MCID.isReturn()) || 516 II->isStackAligningInlineAsm()) { 517 MFI->setHasCalls(true); 518 } 519 if (II->isMSInlineAsm()) { 520 MF->setHasMSInlineAsm(true); 521 } 522 } 523 } 524 525 // Determine if there is a call to setjmp in the machine function. 526 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 527 528 // Replace forward-declared registers with the registers containing 529 // the desired value. 530 MachineRegisterInfo &MRI = MF->getRegInfo(); 531 for (DenseMap<unsigned, unsigned>::iterator 532 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 533 I != E; ++I) { 534 unsigned From = I->first; 535 unsigned To = I->second; 536 // If To is also scheduled to be replaced, find what its ultimate 537 // replacement is. 538 for (;;) { 539 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 540 if (J == E) break; 541 To = J->second; 542 } 543 // Make sure the new register has a sufficiently constrained register class. 544 if (TargetRegisterInfo::isVirtualRegister(From) && 545 TargetRegisterInfo::isVirtualRegister(To)) 546 MRI.constrainRegClass(To, MRI.getRegClass(From)); 547 // Replace it. 548 MRI.replaceRegWith(From, To); 549 } 550 551 // Freeze the set of reserved registers now that MachineFrameInfo has been 552 // set up. All the information required by getReservedRegs() should be 553 // available now. 554 MRI.freezeReservedRegs(*MF); 555 556 // Release function-specific state. SDB and CurDAG are already cleared 557 // at this point. 558 FuncInfo->clear(); 559 560 return true; 561} 562 563void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 564 BasicBlock::const_iterator End, 565 bool &HadTailCall) { 566 // Lower all of the non-terminator instructions. If a call is emitted 567 // as a tail call, cease emitting nodes for this block. Terminators 568 // are handled below. 569 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 570 SDB->visit(*I); 571 572 // Make sure the root of the DAG is up-to-date. 573 CurDAG->setRoot(SDB->getControlRoot()); 574 HadTailCall = SDB->HasTailCall; 575 SDB->clear(); 576 577 // Final step, emit the lowered DAG as machine code. 578 CodeGenAndEmitDAG(); 579} 580 581void SelectionDAGISel::ComputeLiveOutVRegInfo() { 582 SmallPtrSet<SDNode*, 128> VisitedNodes; 583 SmallVector<SDNode*, 128> Worklist; 584 585 Worklist.push_back(CurDAG->getRoot().getNode()); 586 587 APInt KnownZero; 588 APInt KnownOne; 589 590 do { 591 SDNode *N = Worklist.pop_back_val(); 592 593 // If we've already seen this node, ignore it. 594 if (!VisitedNodes.insert(N)) 595 continue; 596 597 // Otherwise, add all chain operands to the worklist. 598 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 599 if (N->getOperand(i).getValueType() == MVT::Other) 600 Worklist.push_back(N->getOperand(i).getNode()); 601 602 // If this is a CopyToReg with a vreg dest, process it. 603 if (N->getOpcode() != ISD::CopyToReg) 604 continue; 605 606 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 607 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 608 continue; 609 610 // Ignore non-scalar or non-integer values. 611 SDValue Src = N->getOperand(2); 612 EVT SrcVT = Src.getValueType(); 613 if (!SrcVT.isInteger() || SrcVT.isVector()) 614 continue; 615 616 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 617 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 618 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 619 } while (!Worklist.empty()); 620} 621 622void SelectionDAGISel::CodeGenAndEmitDAG() { 623 std::string GroupName; 624 if (TimePassesIsEnabled) 625 GroupName = "Instruction Selection and Scheduling"; 626 std::string BlockName; 627 int BlockNumber = -1; 628 (void)BlockNumber; 629#ifdef NDEBUG 630 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 631 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 632 ViewSUnitDAGs) 633#endif 634 { 635 BlockNumber = FuncInfo->MBB->getNumber(); 636 BlockName = MF->getName().str() + ":" + 637 FuncInfo->MBB->getBasicBlock()->getName().str(); 638 } 639 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 640 << " '" << BlockName << "'\n"; CurDAG->dump()); 641 642 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 643 644 // Run the DAG combiner in pre-legalize mode. 645 { 646 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 647 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 648 } 649 650 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 651 << " '" << BlockName << "'\n"; CurDAG->dump()); 652 653 // Second step, hack on the DAG until it only uses operations and types that 654 // the target supports. 655 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 656 BlockName); 657 658 bool Changed; 659 { 660 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 661 Changed = CurDAG->LegalizeTypes(); 662 } 663 664 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 665 << " '" << BlockName << "'\n"; CurDAG->dump()); 666 667 if (Changed) { 668 if (ViewDAGCombineLT) 669 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 670 671 // Run the DAG combiner in post-type-legalize mode. 672 { 673 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 674 TimePassesIsEnabled); 675 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 676 } 677 678 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 679 << " '" << BlockName << "'\n"; CurDAG->dump()); 680 681 } 682 683 { 684 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 685 Changed = CurDAG->LegalizeVectors(); 686 } 687 688 if (Changed) { 689 { 690 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 691 CurDAG->LegalizeTypes(); 692 } 693 694 if (ViewDAGCombineLT) 695 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 696 697 // Run the DAG combiner in post-type-legalize mode. 698 { 699 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 700 TimePassesIsEnabled); 701 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 702 } 703 704 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 705 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 706 } 707 708 CurDAG->NewNodesMustHaveLegalTypes = true; 709 710 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 711 712 { 713 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 714 CurDAG->Legalize(); 715 } 716 717 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 718 << " '" << BlockName << "'\n"; CurDAG->dump()); 719 720 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 721 722 // Run the DAG combiner in post-legalize mode. 723 { 724 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 725 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 726 } 727 728 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 729 << " '" << BlockName << "'\n"; CurDAG->dump()); 730 731 if (OptLevel != CodeGenOpt::None) 732 ComputeLiveOutVRegInfo(); 733 734 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 735 736 // Third, instruction select all of the operations to machine code, adding the 737 // code to the MachineBasicBlock. 738 { 739 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 740 DoInstructionSelection(); 741 } 742 743 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 744 << " '" << BlockName << "'\n"; CurDAG->dump()); 745 746 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 747 748 // Schedule machine code. 749 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 750 { 751 NamedRegionTimer T("Instruction Scheduling", GroupName, 752 TimePassesIsEnabled); 753 Scheduler->Run(CurDAG, FuncInfo->MBB); 754 } 755 756 if (ViewSUnitDAGs) Scheduler->viewGraph(); 757 758 // Emit machine code to BB. This can change 'BB' to the last block being 759 // inserted into. 760 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 761 { 762 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 763 764 // FuncInfo->InsertPt is passed by reference and set to the end of the 765 // scheduled instructions. 766 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 767 } 768 769 // If the block was split, make sure we update any references that are used to 770 // update PHI nodes later on. 771 if (FirstMBB != LastMBB) 772 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 773 774 // Free the scheduler state. 775 { 776 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 777 TimePassesIsEnabled); 778 delete Scheduler; 779 } 780 781 // Free the SelectionDAG state, now that we're finished with it. 782 CurDAG->clear(); 783} 784 785namespace { 786/// ISelUpdater - helper class to handle updates of the instruction selection 787/// graph. 788class ISelUpdater : public SelectionDAG::DAGUpdateListener { 789 SelectionDAG::allnodes_iterator &ISelPosition; 790public: 791 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 792 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 793 794 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 795 /// deleted is the current ISelPosition node, update ISelPosition. 796 /// 797 virtual void NodeDeleted(SDNode *N, SDNode *E) { 798 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 799 ++ISelPosition; 800 } 801}; 802} // end anonymous namespace 803 804void SelectionDAGISel::DoInstructionSelection() { 805 DEBUG(dbgs() << "===== Instruction selection begins: BB#" 806 << FuncInfo->MBB->getNumber() 807 << " '" << FuncInfo->MBB->getName() << "'\n"); 808 809 PreprocessISelDAG(); 810 811 // Select target instructions for the DAG. 812 { 813 // Number all nodes with a topological order and set DAGSize. 814 DAGSize = CurDAG->AssignTopologicalOrder(); 815 816 // Create a dummy node (which is not added to allnodes), that adds 817 // a reference to the root node, preventing it from being deleted, 818 // and tracking any changes of the root. 819 HandleSDNode Dummy(CurDAG->getRoot()); 820 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 821 ++ISelPosition; 822 823 // Make sure that ISelPosition gets properly updated when nodes are deleted 824 // in calls made from this function. 825 ISelUpdater ISU(*CurDAG, ISelPosition); 826 827 // The AllNodes list is now topological-sorted. Visit the 828 // nodes by starting at the end of the list (the root of the 829 // graph) and preceding back toward the beginning (the entry 830 // node). 831 while (ISelPosition != CurDAG->allnodes_begin()) { 832 SDNode *Node = --ISelPosition; 833 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 834 // but there are currently some corner cases that it misses. Also, this 835 // makes it theoretically possible to disable the DAGCombiner. 836 if (Node->use_empty()) 837 continue; 838 839 SDNode *ResNode = Select(Node); 840 841 // FIXME: This is pretty gross. 'Select' should be changed to not return 842 // anything at all and this code should be nuked with a tactical strike. 843 844 // If node should not be replaced, continue with the next one. 845 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 846 continue; 847 // Replace node. 848 if (ResNode) { 849 ReplaceUses(Node, ResNode); 850 } 851 852 // If after the replacement this node is not used any more, 853 // remove this dead node. 854 if (Node->use_empty()) // Don't delete EntryToken, etc. 855 CurDAG->RemoveDeadNode(Node); 856 } 857 858 CurDAG->setRoot(Dummy.getValue()); 859 } 860 861 DEBUG(dbgs() << "===== Instruction selection ends:\n"); 862 863 PostprocessISelDAG(); 864} 865 866/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 867/// do other setup for EH landing-pad blocks. 868void SelectionDAGISel::PrepareEHLandingPad() { 869 MachineBasicBlock *MBB = FuncInfo->MBB; 870 871 // Add a label to mark the beginning of the landing pad. Deletion of the 872 // landing pad can thus be detected via the MachineModuleInfo. 873 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 874 875 // Assign the call site to the landing pad's begin label. 876 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 877 878 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 879 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 880 .addSym(Label); 881 882 // Mark exception register as live in. 883 const TargetLowering *TLI = getTargetLowering(); 884 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy()); 885 if (unsigned Reg = TLI->getExceptionPointerRegister()) 886 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC); 887 888 // Mark exception selector register as live in. 889 if (unsigned Reg = TLI->getExceptionSelectorRegister()) 890 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC); 891} 892 893/// isFoldedOrDeadInstruction - Return true if the specified instruction is 894/// side-effect free and is either dead or folded into a generated instruction. 895/// Return false if it needs to be emitted. 896static bool isFoldedOrDeadInstruction(const Instruction *I, 897 FunctionLoweringInfo *FuncInfo) { 898 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 899 !isa<TerminatorInst>(I) && // Terminators aren't folded. 900 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 901 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 902 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 903} 904 905#ifndef NDEBUG 906// Collect per Instruction statistics for fast-isel misses. Only those 907// instructions that cause the bail are accounted for. It does not account for 908// instructions higher in the block. Thus, summing the per instructions stats 909// will not add up to what is reported by NumFastIselFailures. 910static void collectFailStats(const Instruction *I) { 911 switch (I->getOpcode()) { 912 default: assert (0 && "<Invalid operator> "); 913 914 // Terminators 915 case Instruction::Ret: NumFastIselFailRet++; return; 916 case Instruction::Br: NumFastIselFailBr++; return; 917 case Instruction::Switch: NumFastIselFailSwitch++; return; 918 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 919 case Instruction::Invoke: NumFastIselFailInvoke++; return; 920 case Instruction::Resume: NumFastIselFailResume++; return; 921 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 922 923 // Standard binary operators... 924 case Instruction::Add: NumFastIselFailAdd++; return; 925 case Instruction::FAdd: NumFastIselFailFAdd++; return; 926 case Instruction::Sub: NumFastIselFailSub++; return; 927 case Instruction::FSub: NumFastIselFailFSub++; return; 928 case Instruction::Mul: NumFastIselFailMul++; return; 929 case Instruction::FMul: NumFastIselFailFMul++; return; 930 case Instruction::UDiv: NumFastIselFailUDiv++; return; 931 case Instruction::SDiv: NumFastIselFailSDiv++; return; 932 case Instruction::FDiv: NumFastIselFailFDiv++; return; 933 case Instruction::URem: NumFastIselFailURem++; return; 934 case Instruction::SRem: NumFastIselFailSRem++; return; 935 case Instruction::FRem: NumFastIselFailFRem++; return; 936 937 // Logical operators... 938 case Instruction::And: NumFastIselFailAnd++; return; 939 case Instruction::Or: NumFastIselFailOr++; return; 940 case Instruction::Xor: NumFastIselFailXor++; return; 941 942 // Memory instructions... 943 case Instruction::Alloca: NumFastIselFailAlloca++; return; 944 case Instruction::Load: NumFastIselFailLoad++; return; 945 case Instruction::Store: NumFastIselFailStore++; return; 946 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 947 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 948 case Instruction::Fence: NumFastIselFailFence++; return; 949 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 950 951 // Convert instructions... 952 case Instruction::Trunc: NumFastIselFailTrunc++; return; 953 case Instruction::ZExt: NumFastIselFailZExt++; return; 954 case Instruction::SExt: NumFastIselFailSExt++; return; 955 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 956 case Instruction::FPExt: NumFastIselFailFPExt++; return; 957 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 958 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 959 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 960 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 961 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 962 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 963 case Instruction::BitCast: NumFastIselFailBitCast++; return; 964 965 // Other instructions... 966 case Instruction::ICmp: NumFastIselFailICmp++; return; 967 case Instruction::FCmp: NumFastIselFailFCmp++; return; 968 case Instruction::PHI: NumFastIselFailPHI++; return; 969 case Instruction::Select: NumFastIselFailSelect++; return; 970 case Instruction::Call: NumFastIselFailCall++; return; 971 case Instruction::Shl: NumFastIselFailShl++; return; 972 case Instruction::LShr: NumFastIselFailLShr++; return; 973 case Instruction::AShr: NumFastIselFailAShr++; return; 974 case Instruction::VAArg: NumFastIselFailVAArg++; return; 975 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 976 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 977 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 978 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 979 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 980 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 981 } 982} 983#endif 984 985void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 986 // Initialize the Fast-ISel state, if needed. 987 FastISel *FastIS = 0; 988 if (TM.Options.EnableFastISel || Fn.hasFnAttribute(Attribute::OptimizeNone)) 989 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo); 990 991 // Iterate over all basic blocks in the function. 992 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 993 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 994 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 995 const BasicBlock *LLVMBB = *I; 996 997 if (OptLevel != CodeGenOpt::None) { 998 bool AllPredsVisited = true; 999 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 1000 PI != PE; ++PI) { 1001 if (!FuncInfo->VisitedBBs.count(*PI)) { 1002 AllPredsVisited = false; 1003 break; 1004 } 1005 } 1006 1007 if (AllPredsVisited) { 1008 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1009 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1010 FuncInfo->ComputePHILiveOutRegInfo(PN); 1011 } else { 1012 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1013 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1014 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 1015 } 1016 1017 FuncInfo->VisitedBBs.insert(LLVMBB); 1018 } 1019 1020 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 1021 BasicBlock::const_iterator const End = LLVMBB->end(); 1022 BasicBlock::const_iterator BI = End; 1023 1024 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 1025 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1026 1027 // Setup an EH landing-pad block. 1028 FuncInfo->ExceptionPointerVirtReg = 0; 1029 FuncInfo->ExceptionSelectorVirtReg = 0; 1030 if (FuncInfo->MBB->isLandingPad()) 1031 PrepareEHLandingPad(); 1032 1033 // Before doing SelectionDAG ISel, see if FastISel has been requested. 1034 if (FastIS) { 1035 FastIS->startNewBlock(); 1036 1037 // Emit code for any incoming arguments. This must happen before 1038 // beginning FastISel on the entry block. 1039 if (LLVMBB == &Fn.getEntryBlock()) { 1040 ++NumEntryBlocks; 1041 1042 // Lower any arguments needed in this block if this is the entry block. 1043 if (!FastIS->LowerArguments()) { 1044 // Fast isel failed to lower these arguments 1045 ++NumFastIselFailLowerArguments; 1046 if (EnableFastISelAbortArgs) 1047 llvm_unreachable("FastISel didn't lower all arguments"); 1048 1049 // Use SelectionDAG argument lowering 1050 LowerArguments(Fn); 1051 CurDAG->setRoot(SDB->getControlRoot()); 1052 SDB->clear(); 1053 CodeGenAndEmitDAG(); 1054 } 1055 1056 // If we inserted any instructions at the beginning, make a note of 1057 // where they are, so we can be sure to emit subsequent instructions 1058 // after them. 1059 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1060 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 1061 else 1062 FastIS->setLastLocalValue(0); 1063 } 1064 1065 unsigned NumFastIselRemaining = std::distance(Begin, End); 1066 // Do FastISel on as many instructions as possible. 1067 for (; BI != Begin; --BI) { 1068 const Instruction *Inst = llvm::prior(BI); 1069 1070 // If we no longer require this instruction, skip it. 1071 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1072 --NumFastIselRemaining; 1073 continue; 1074 } 1075 1076 // Bottom-up: reset the insert pos at the top, after any local-value 1077 // instructions. 1078 FastIS->recomputeInsertPt(); 1079 1080 // Try to select the instruction with FastISel. 1081 if (FastIS->SelectInstruction(Inst)) { 1082 --NumFastIselRemaining; 1083 ++NumFastIselSuccess; 1084 // If fast isel succeeded, skip over all the folded instructions, and 1085 // then see if there is a load right before the selected instructions. 1086 // Try to fold the load if so. 1087 const Instruction *BeforeInst = Inst; 1088 while (BeforeInst != Begin) { 1089 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 1090 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1091 break; 1092 } 1093 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1094 BeforeInst->hasOneUse() && 1095 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) { 1096 // If we succeeded, don't re-select the load. 1097 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 1098 --NumFastIselRemaining; 1099 ++NumFastIselSuccess; 1100 } 1101 continue; 1102 } 1103 1104#ifndef NDEBUG 1105 if (EnableFastISelVerbose2) 1106 collectFailStats(Inst); 1107#endif 1108 1109 // Then handle certain instructions as single-LLVM-Instruction blocks. 1110 if (isa<CallInst>(Inst)) { 1111 1112 if (EnableFastISelVerbose || EnableFastISelAbort) { 1113 dbgs() << "FastISel missed call: "; 1114 Inst->dump(); 1115 } 1116 1117 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1118 unsigned &R = FuncInfo->ValueMap[Inst]; 1119 if (!R) 1120 R = FuncInfo->CreateRegs(Inst->getType()); 1121 } 1122 1123 bool HadTailCall = false; 1124 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1125 SelectBasicBlock(Inst, BI, HadTailCall); 1126 1127 // If the call was emitted as a tail call, we're done with the block. 1128 // We also need to delete any previously emitted instructions. 1129 if (HadTailCall) { 1130 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1131 --BI; 1132 break; 1133 } 1134 1135 // Recompute NumFastIselRemaining as Selection DAG instruction 1136 // selection may have handled the call, input args, etc. 1137 unsigned RemainingNow = std::distance(Begin, BI); 1138 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1139 NumFastIselRemaining = RemainingNow; 1140 continue; 1141 } 1142 1143 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1144 // Don't abort, and use a different message for terminator misses. 1145 NumFastIselFailures += NumFastIselRemaining; 1146 if (EnableFastISelVerbose || EnableFastISelAbort) { 1147 dbgs() << "FastISel missed terminator: "; 1148 Inst->dump(); 1149 } 1150 } else { 1151 NumFastIselFailures += NumFastIselRemaining; 1152 if (EnableFastISelVerbose || EnableFastISelAbort) { 1153 dbgs() << "FastISel miss: "; 1154 Inst->dump(); 1155 } 1156 if (EnableFastISelAbort) 1157 // The "fast" selector couldn't handle something and bailed. 1158 // For the purpose of debugging, just abort. 1159 llvm_unreachable("FastISel didn't select the entire block"); 1160 } 1161 break; 1162 } 1163 1164 FastIS->recomputeInsertPt(); 1165 } else { 1166 // Lower any arguments needed in this block if this is the entry block. 1167 if (LLVMBB == &Fn.getEntryBlock()) { 1168 ++NumEntryBlocks; 1169 LowerArguments(Fn); 1170 } 1171 } 1172 1173 if (Begin != BI) 1174 ++NumDAGBlocks; 1175 else 1176 ++NumFastIselBlocks; 1177 1178 if (Begin != BI) { 1179 // Run SelectionDAG instruction selection on the remainder of the block 1180 // not handled by FastISel. If FastISel is not run, this is the entire 1181 // block. 1182 bool HadTailCall; 1183 SelectBasicBlock(Begin, BI, HadTailCall); 1184 } 1185 1186 FinishBasicBlock(); 1187 FuncInfo->PHINodesToUpdate.clear(); 1188 } 1189 1190 delete FastIS; 1191 SDB->clearDanglingDebugInfo(); 1192 SDB->SPDescriptor.resetPerFunctionState(); 1193} 1194 1195/// Given that the input MI is before a partial terminator sequence TSeq, return 1196/// true if M + TSeq also a partial terminator sequence. 1197/// 1198/// A Terminator sequence is a sequence of MachineInstrs which at this point in 1199/// lowering copy vregs into physical registers, which are then passed into 1200/// terminator instructors so we can satisfy ABI constraints. A partial 1201/// terminator sequence is an improper subset of a terminator sequence (i.e. it 1202/// may be the whole terminator sequence). 1203static bool MIIsInTerminatorSequence(const MachineInstr *MI) { 1204 // If we do not have a copy or an implicit def, we return true if and only if 1205 // MI is a debug value. 1206 if (!MI->isCopy() && !MI->isImplicitDef()) 1207 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the 1208 // physical registers if there is debug info associated with the terminator 1209 // of our mbb. We want to include said debug info in our terminator 1210 // sequence, so we return true in that case. 1211 return MI->isDebugValue(); 1212 1213 // We have left the terminator sequence if we are not doing one of the 1214 // following: 1215 // 1216 // 1. Copying a vreg into a physical register. 1217 // 2. Copying a vreg into a vreg. 1218 // 3. Defining a register via an implicit def. 1219 1220 // OPI should always be a register definition... 1221 MachineInstr::const_mop_iterator OPI = MI->operands_begin(); 1222 if (!OPI->isReg() || !OPI->isDef()) 1223 return false; 1224 1225 // Defining any register via an implicit def is always ok. 1226 if (MI->isImplicitDef()) 1227 return true; 1228 1229 // Grab the copy source... 1230 MachineInstr::const_mop_iterator OPI2 = OPI; 1231 ++OPI2; 1232 assert(OPI2 != MI->operands_end() 1233 && "Should have a copy implying we should have 2 arguments."); 1234 1235 // Make sure that the copy dest is not a vreg when the copy source is a 1236 // physical register. 1237 if (!OPI2->isReg() || 1238 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) && 1239 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg()))) 1240 return false; 1241 1242 return true; 1243} 1244 1245/// Find the split point at which to splice the end of BB into its success stack 1246/// protector check machine basic block. 1247/// 1248/// On many platforms, due to ABI constraints, terminators, even before register 1249/// allocation, use physical registers. This creates an issue for us since 1250/// physical registers at this point can not travel across basic 1251/// blocks. Luckily, selectiondag always moves physical registers into vregs 1252/// when they enter functions and moves them through a sequence of copies back 1253/// into the physical registers right before the terminator creating a 1254/// ``Terminator Sequence''. This function is searching for the beginning of the 1255/// terminator sequence so that we can ensure that we splice off not just the 1256/// terminator, but additionally the copies that move the vregs into the 1257/// physical registers. 1258static MachineBasicBlock::iterator 1259FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) { 1260 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator(); 1261 // 1262 if (SplitPoint == BB->begin()) 1263 return SplitPoint; 1264 1265 MachineBasicBlock::iterator Start = BB->begin(); 1266 MachineBasicBlock::iterator Previous = SplitPoint; 1267 --Previous; 1268 1269 while (MIIsInTerminatorSequence(Previous)) { 1270 SplitPoint = Previous; 1271 if (Previous == Start) 1272 break; 1273 --Previous; 1274 } 1275 1276 return SplitPoint; 1277} 1278 1279void 1280SelectionDAGISel::FinishBasicBlock() { 1281 1282 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1283 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1284 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1285 dbgs() << "Node " << i << " : (" 1286 << FuncInfo->PHINodesToUpdate[i].first 1287 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1288 1289 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() && 1290 SDB->JTCases.empty() && 1291 SDB->BitTestCases.empty(); 1292 1293 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1294 // PHI nodes in successors. 1295 if (MustUpdatePHINodes) { 1296 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1297 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1298 assert(PHI->isPHI() && 1299 "This is not a machine PHI node that we are updating!"); 1300 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1301 continue; 1302 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1303 } 1304 } 1305 1306 // Handle stack protector. 1307 if (SDB->SPDescriptor.shouldEmitStackProtector()) { 1308 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB(); 1309 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB(); 1310 1311 // Find the split point to split the parent mbb. At the same time copy all 1312 // physical registers used in the tail of parent mbb into virtual registers 1313 // before the split point and back into physical registers after the split 1314 // point. This prevents us needing to deal with Live-ins and many other 1315 // register allocation issues caused by us splitting the parent mbb. The 1316 // register allocator will clean up said virtual copies later on. 1317 MachineBasicBlock::iterator SplitPoint = 1318 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc()); 1319 1320 // Splice the terminator of ParentMBB into SuccessMBB. 1321 SuccessMBB->splice(SuccessMBB->end(), ParentMBB, 1322 SplitPoint, 1323 ParentMBB->end()); 1324 1325 // Add compare/jump on neq/jump to the parent BB. 1326 FuncInfo->MBB = ParentMBB; 1327 FuncInfo->InsertPt = ParentMBB->end(); 1328 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB); 1329 CurDAG->setRoot(SDB->getRoot()); 1330 SDB->clear(); 1331 CodeGenAndEmitDAG(); 1332 1333 // CodeGen Failure MBB if we have not codegened it yet. 1334 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB(); 1335 if (!FailureMBB->size()) { 1336 FuncInfo->MBB = FailureMBB; 1337 FuncInfo->InsertPt = FailureMBB->end(); 1338 SDB->visitSPDescriptorFailure(SDB->SPDescriptor); 1339 CurDAG->setRoot(SDB->getRoot()); 1340 SDB->clear(); 1341 CodeGenAndEmitDAG(); 1342 } 1343 1344 // Clear the Per-BB State. 1345 SDB->SPDescriptor.resetPerBBState(); 1346 } 1347 1348 // If we updated PHI Nodes, return early. 1349 if (MustUpdatePHINodes) 1350 return; 1351 1352 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1353 // Lower header first, if it wasn't already lowered 1354 if (!SDB->BitTestCases[i].Emitted) { 1355 // Set the current basic block to the mbb we wish to insert the code into 1356 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1357 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1358 // Emit the code 1359 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1360 CurDAG->setRoot(SDB->getRoot()); 1361 SDB->clear(); 1362 CodeGenAndEmitDAG(); 1363 } 1364 1365 uint32_t UnhandledWeight = 0; 1366 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1367 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1368 1369 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1370 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1371 // Set the current basic block to the mbb we wish to insert the code into 1372 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1373 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1374 // Emit the code 1375 if (j+1 != ej) 1376 SDB->visitBitTestCase(SDB->BitTestCases[i], 1377 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1378 UnhandledWeight, 1379 SDB->BitTestCases[i].Reg, 1380 SDB->BitTestCases[i].Cases[j], 1381 FuncInfo->MBB); 1382 else 1383 SDB->visitBitTestCase(SDB->BitTestCases[i], 1384 SDB->BitTestCases[i].Default, 1385 UnhandledWeight, 1386 SDB->BitTestCases[i].Reg, 1387 SDB->BitTestCases[i].Cases[j], 1388 FuncInfo->MBB); 1389 1390 1391 CurDAG->setRoot(SDB->getRoot()); 1392 SDB->clear(); 1393 CodeGenAndEmitDAG(); 1394 } 1395 1396 // Update PHI Nodes 1397 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1398 pi != pe; ++pi) { 1399 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1400 MachineBasicBlock *PHIBB = PHI->getParent(); 1401 assert(PHI->isPHI() && 1402 "This is not a machine PHI node that we are updating!"); 1403 // This is "default" BB. We have two jumps to it. From "header" BB and 1404 // from last "case" BB. 1405 if (PHIBB == SDB->BitTestCases[i].Default) 1406 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1407 .addMBB(SDB->BitTestCases[i].Parent) 1408 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1409 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1410 // One of "cases" BB. 1411 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1412 j != ej; ++j) { 1413 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1414 if (cBB->isSuccessor(PHIBB)) 1415 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1416 } 1417 } 1418 } 1419 SDB->BitTestCases.clear(); 1420 1421 // If the JumpTable record is filled in, then we need to emit a jump table. 1422 // Updating the PHI nodes is tricky in this case, since we need to determine 1423 // whether the PHI is a successor of the range check MBB or the jump table MBB 1424 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1425 // Lower header first, if it wasn't already lowered 1426 if (!SDB->JTCases[i].first.Emitted) { 1427 // Set the current basic block to the mbb we wish to insert the code into 1428 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1429 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1430 // Emit the code 1431 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1432 FuncInfo->MBB); 1433 CurDAG->setRoot(SDB->getRoot()); 1434 SDB->clear(); 1435 CodeGenAndEmitDAG(); 1436 } 1437 1438 // Set the current basic block to the mbb we wish to insert the code into 1439 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1440 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1441 // Emit the code 1442 SDB->visitJumpTable(SDB->JTCases[i].second); 1443 CurDAG->setRoot(SDB->getRoot()); 1444 SDB->clear(); 1445 CodeGenAndEmitDAG(); 1446 1447 // Update PHI Nodes 1448 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1449 pi != pe; ++pi) { 1450 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1451 MachineBasicBlock *PHIBB = PHI->getParent(); 1452 assert(PHI->isPHI() && 1453 "This is not a machine PHI node that we are updating!"); 1454 // "default" BB. We can go there only from header BB. 1455 if (PHIBB == SDB->JTCases[i].second.Default) 1456 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1457 .addMBB(SDB->JTCases[i].first.HeaderBB); 1458 // JT BB. Just iterate over successors here 1459 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1460 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1461 } 1462 } 1463 SDB->JTCases.clear(); 1464 1465 // If the switch block involved a branch to one of the actual successors, we 1466 // need to update PHI nodes in that block. 1467 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1468 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1469 assert(PHI->isPHI() && 1470 "This is not a machine PHI node that we are updating!"); 1471 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 1472 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1473 } 1474 1475 // If we generated any switch lowering information, build and codegen any 1476 // additional DAGs necessary. 1477 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1478 // Set the current basic block to the mbb we wish to insert the code into 1479 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1480 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1481 1482 // Determine the unique successors. 1483 SmallVector<MachineBasicBlock *, 2> Succs; 1484 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1485 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1486 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1487 1488 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1489 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1490 CurDAG->setRoot(SDB->getRoot()); 1491 SDB->clear(); 1492 CodeGenAndEmitDAG(); 1493 1494 // Remember the last block, now that any splitting is done, for use in 1495 // populating PHI nodes in successors. 1496 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1497 1498 // Handle any PHI nodes in successors of this chunk, as if we were coming 1499 // from the original BB before switch expansion. Note that PHI nodes can 1500 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1501 // handle them the right number of times. 1502 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1503 FuncInfo->MBB = Succs[i]; 1504 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1505 // FuncInfo->MBB may have been removed from the CFG if a branch was 1506 // constant folded. 1507 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1508 for (MachineBasicBlock::iterator 1509 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1510 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1511 MachineInstrBuilder PHI(*MF, MBBI); 1512 // This value for this PHI node is recorded in PHINodesToUpdate. 1513 for (unsigned pn = 0; ; ++pn) { 1514 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1515 "Didn't find PHI entry!"); 1516 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1517 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1518 break; 1519 } 1520 } 1521 } 1522 } 1523 } 1524 } 1525 SDB->SwitchCases.clear(); 1526} 1527 1528 1529/// Create the scheduler. If a specific scheduler was specified 1530/// via the SchedulerRegistry, use it, otherwise select the 1531/// one preferred by the target. 1532/// 1533ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1534 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1535 1536 if (!Ctor) { 1537 Ctor = ISHeuristic; 1538 RegisterScheduler::setDefault(Ctor); 1539 } 1540 1541 return Ctor(this, OptLevel); 1542} 1543 1544//===----------------------------------------------------------------------===// 1545// Helper functions used by the generated instruction selector. 1546//===----------------------------------------------------------------------===// 1547// Calls to these methods are generated by tblgen. 1548 1549/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1550/// the dag combiner simplified the 255, we still want to match. RHS is the 1551/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1552/// specified in the .td file (e.g. 255). 1553bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1554 int64_t DesiredMaskS) const { 1555 const APInt &ActualMask = RHS->getAPIntValue(); 1556 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1557 1558 // If the actual mask exactly matches, success! 1559 if (ActualMask == DesiredMask) 1560 return true; 1561 1562 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1563 if (ActualMask.intersects(~DesiredMask)) 1564 return false; 1565 1566 // Otherwise, the DAG Combiner may have proven that the value coming in is 1567 // either already zero or is not demanded. Check for known zero input bits. 1568 APInt NeededMask = DesiredMask & ~ActualMask; 1569 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1570 return true; 1571 1572 // TODO: check to see if missing bits are just not demanded. 1573 1574 // Otherwise, this pattern doesn't match. 1575 return false; 1576} 1577 1578/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1579/// the dag combiner simplified the 255, we still want to match. RHS is the 1580/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1581/// specified in the .td file (e.g. 255). 1582bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1583 int64_t DesiredMaskS) const { 1584 const APInt &ActualMask = RHS->getAPIntValue(); 1585 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1586 1587 // If the actual mask exactly matches, success! 1588 if (ActualMask == DesiredMask) 1589 return true; 1590 1591 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1592 if (ActualMask.intersects(~DesiredMask)) 1593 return false; 1594 1595 // Otherwise, the DAG Combiner may have proven that the value coming in is 1596 // either already zero or is not demanded. Check for known zero input bits. 1597 APInt NeededMask = DesiredMask & ~ActualMask; 1598 1599 APInt KnownZero, KnownOne; 1600 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 1601 1602 // If all the missing bits in the or are already known to be set, match! 1603 if ((NeededMask & KnownOne) == NeededMask) 1604 return true; 1605 1606 // TODO: check to see if missing bits are just not demanded. 1607 1608 // Otherwise, this pattern doesn't match. 1609 return false; 1610} 1611 1612 1613/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1614/// by tblgen. Others should not call it. 1615void SelectionDAGISel:: 1616SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1617 std::vector<SDValue> InOps; 1618 std::swap(InOps, Ops); 1619 1620 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1621 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1622 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1623 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1624 1625 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1626 if (InOps[e-1].getValueType() == MVT::Glue) 1627 --e; // Don't process a glue operand if it is here. 1628 1629 while (i != e) { 1630 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1631 if (!InlineAsm::isMemKind(Flags)) { 1632 // Just skip over this operand, copying the operands verbatim. 1633 Ops.insert(Ops.end(), InOps.begin()+i, 1634 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1635 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1636 } else { 1637 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1638 "Memory operand with multiple values?"); 1639 // Otherwise, this is a memory operand. Ask the target to select it. 1640 std::vector<SDValue> SelOps; 1641 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1642 report_fatal_error("Could not match memory address. Inline asm" 1643 " failure!"); 1644 1645 // Add this to the output node. 1646 unsigned NewFlags = 1647 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1648 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1649 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1650 i += 2; 1651 } 1652 } 1653 1654 // Add the glue input back if present. 1655 if (e != InOps.size()) 1656 Ops.push_back(InOps.back()); 1657} 1658 1659/// findGlueUse - Return use of MVT::Glue value produced by the specified 1660/// SDNode. 1661/// 1662static SDNode *findGlueUse(SDNode *N) { 1663 unsigned FlagResNo = N->getNumValues()-1; 1664 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1665 SDUse &Use = I.getUse(); 1666 if (Use.getResNo() == FlagResNo) 1667 return Use.getUser(); 1668 } 1669 return NULL; 1670} 1671 1672/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1673/// This function recursively traverses up the operand chain, ignoring 1674/// certain nodes. 1675static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1676 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1677 bool IgnoreChains) { 1678 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1679 // greater than all of its (recursive) operands. If we scan to a point where 1680 // 'use' is smaller than the node we're scanning for, then we know we will 1681 // never find it. 1682 // 1683 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1684 // happen because we scan down to newly selected nodes in the case of glue 1685 // uses. 1686 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1687 return false; 1688 1689 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1690 // won't fail if we scan it again. 1691 if (!Visited.insert(Use)) 1692 return false; 1693 1694 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1695 // Ignore chain uses, they are validated by HandleMergeInputChains. 1696 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1697 continue; 1698 1699 SDNode *N = Use->getOperand(i).getNode(); 1700 if (N == Def) { 1701 if (Use == ImmedUse || Use == Root) 1702 continue; // We are not looking for immediate use. 1703 assert(N != Root); 1704 return true; 1705 } 1706 1707 // Traverse up the operand chain. 1708 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1709 return true; 1710 } 1711 return false; 1712} 1713 1714/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1715/// operand node N of U during instruction selection that starts at Root. 1716bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1717 SDNode *Root) const { 1718 if (OptLevel == CodeGenOpt::None) return false; 1719 return N.hasOneUse(); 1720} 1721 1722/// IsLegalToFold - Returns true if the specific operand node N of 1723/// U can be folded during instruction selection that starts at Root. 1724bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1725 CodeGenOpt::Level OptLevel, 1726 bool IgnoreChains) { 1727 if (OptLevel == CodeGenOpt::None) return false; 1728 1729 // If Root use can somehow reach N through a path that that doesn't contain 1730 // U then folding N would create a cycle. e.g. In the following 1731 // diagram, Root can reach N through X. If N is folded into into Root, then 1732 // X is both a predecessor and a successor of U. 1733 // 1734 // [N*] // 1735 // ^ ^ // 1736 // / \ // 1737 // [U*] [X]? // 1738 // ^ ^ // 1739 // \ / // 1740 // \ / // 1741 // [Root*] // 1742 // 1743 // * indicates nodes to be folded together. 1744 // 1745 // If Root produces glue, then it gets (even more) interesting. Since it 1746 // will be "glued" together with its glue use in the scheduler, we need to 1747 // check if it might reach N. 1748 // 1749 // [N*] // 1750 // ^ ^ // 1751 // / \ // 1752 // [U*] [X]? // 1753 // ^ ^ // 1754 // \ \ // 1755 // \ | // 1756 // [Root*] | // 1757 // ^ | // 1758 // f | // 1759 // | / // 1760 // [Y] / // 1761 // ^ / // 1762 // f / // 1763 // | / // 1764 // [GU] // 1765 // 1766 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1767 // (call it Fold), then X is a predecessor of GU and a successor of 1768 // Fold. But since Fold and GU are glued together, this will create 1769 // a cycle in the scheduling graph. 1770 1771 // If the node has glue, walk down the graph to the "lowest" node in the 1772 // glueged set. 1773 EVT VT = Root->getValueType(Root->getNumValues()-1); 1774 while (VT == MVT::Glue) { 1775 SDNode *GU = findGlueUse(Root); 1776 if (GU == NULL) 1777 break; 1778 Root = GU; 1779 VT = Root->getValueType(Root->getNumValues()-1); 1780 1781 // If our query node has a glue result with a use, we've walked up it. If 1782 // the user (which has already been selected) has a chain or indirectly uses 1783 // the chain, our WalkChainUsers predicate will not consider it. Because of 1784 // this, we cannot ignore chains in this predicate. 1785 IgnoreChains = false; 1786 } 1787 1788 1789 SmallPtrSet<SDNode*, 16> Visited; 1790 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1791} 1792 1793SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1794 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1795 SelectInlineAsmMemoryOperands(Ops); 1796 1797 EVT VTs[] = { MVT::Other, MVT::Glue }; 1798 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), 1799 VTs, &Ops[0], Ops.size()); 1800 New->setNodeId(-1); 1801 return New.getNode(); 1802} 1803 1804SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1805 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1806} 1807 1808/// GetVBR - decode a vbr encoding whose top bit is set. 1809LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1810GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1811 assert(Val >= 128 && "Not a VBR"); 1812 Val &= 127; // Remove first vbr bit. 1813 1814 unsigned Shift = 7; 1815 uint64_t NextBits; 1816 do { 1817 NextBits = MatcherTable[Idx++]; 1818 Val |= (NextBits&127) << Shift; 1819 Shift += 7; 1820 } while (NextBits & 128); 1821 1822 return Val; 1823} 1824 1825 1826/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1827/// interior glue and chain results to use the new glue and chain results. 1828void SelectionDAGISel:: 1829UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1830 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1831 SDValue InputGlue, 1832 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1833 bool isMorphNodeTo) { 1834 SmallVector<SDNode*, 4> NowDeadNodes; 1835 1836 // Now that all the normal results are replaced, we replace the chain and 1837 // glue results if present. 1838 if (!ChainNodesMatched.empty()) { 1839 assert(InputChain.getNode() != 0 && 1840 "Matched input chains but didn't produce a chain"); 1841 // Loop over all of the nodes we matched that produced a chain result. 1842 // Replace all the chain results with the final chain we ended up with. 1843 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1844 SDNode *ChainNode = ChainNodesMatched[i]; 1845 1846 // If this node was already deleted, don't look at it. 1847 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1848 continue; 1849 1850 // Don't replace the results of the root node if we're doing a 1851 // MorphNodeTo. 1852 if (ChainNode == NodeToMatch && isMorphNodeTo) 1853 continue; 1854 1855 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1856 if (ChainVal.getValueType() == MVT::Glue) 1857 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1858 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1859 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1860 1861 // If the node became dead and we haven't already seen it, delete it. 1862 if (ChainNode->use_empty() && 1863 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1864 NowDeadNodes.push_back(ChainNode); 1865 } 1866 } 1867 1868 // If the result produces glue, update any glue results in the matched 1869 // pattern with the glue result. 1870 if (InputGlue.getNode() != 0) { 1871 // Handle any interior nodes explicitly marked. 1872 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1873 SDNode *FRN = GlueResultNodesMatched[i]; 1874 1875 // If this node was already deleted, don't look at it. 1876 if (FRN->getOpcode() == ISD::DELETED_NODE) 1877 continue; 1878 1879 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1880 "Doesn't have a glue result"); 1881 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1882 InputGlue); 1883 1884 // If the node became dead and we haven't already seen it, delete it. 1885 if (FRN->use_empty() && 1886 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1887 NowDeadNodes.push_back(FRN); 1888 } 1889 } 1890 1891 if (!NowDeadNodes.empty()) 1892 CurDAG->RemoveDeadNodes(NowDeadNodes); 1893 1894 DEBUG(dbgs() << "ISEL: Match complete!\n"); 1895} 1896 1897enum ChainResult { 1898 CR_Simple, 1899 CR_InducesCycle, 1900 CR_LeadsToInteriorNode 1901}; 1902 1903/// WalkChainUsers - Walk down the users of the specified chained node that is 1904/// part of the pattern we're matching, looking at all of the users we find. 1905/// This determines whether something is an interior node, whether we have a 1906/// non-pattern node in between two pattern nodes (which prevent folding because 1907/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1908/// between pattern nodes (in which case the TF becomes part of the pattern). 1909/// 1910/// The walk we do here is guaranteed to be small because we quickly get down to 1911/// already selected nodes "below" us. 1912static ChainResult 1913WalkChainUsers(const SDNode *ChainedNode, 1914 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1915 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1916 ChainResult Result = CR_Simple; 1917 1918 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1919 E = ChainedNode->use_end(); UI != E; ++UI) { 1920 // Make sure the use is of the chain, not some other value we produce. 1921 if (UI.getUse().getValueType() != MVT::Other) continue; 1922 1923 SDNode *User = *UI; 1924 1925 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1926 continue; 1927 1928 // If we see an already-selected machine node, then we've gone beyond the 1929 // pattern that we're selecting down into the already selected chunk of the 1930 // DAG. 1931 unsigned UserOpcode = User->getOpcode(); 1932 if (User->isMachineOpcode() || 1933 UserOpcode == ISD::CopyToReg || 1934 UserOpcode == ISD::CopyFromReg || 1935 UserOpcode == ISD::INLINEASM || 1936 UserOpcode == ISD::EH_LABEL || 1937 UserOpcode == ISD::LIFETIME_START || 1938 UserOpcode == ISD::LIFETIME_END) { 1939 // If their node ID got reset to -1 then they've already been selected. 1940 // Treat them like a MachineOpcode. 1941 if (User->getNodeId() == -1) 1942 continue; 1943 } 1944 1945 // If we have a TokenFactor, we handle it specially. 1946 if (User->getOpcode() != ISD::TokenFactor) { 1947 // If the node isn't a token factor and isn't part of our pattern, then it 1948 // must be a random chained node in between two nodes we're selecting. 1949 // This happens when we have something like: 1950 // x = load ptr 1951 // call 1952 // y = x+4 1953 // store y -> ptr 1954 // Because we structurally match the load/store as a read/modify/write, 1955 // but the call is chained between them. We cannot fold in this case 1956 // because it would induce a cycle in the graph. 1957 if (!std::count(ChainedNodesInPattern.begin(), 1958 ChainedNodesInPattern.end(), User)) 1959 return CR_InducesCycle; 1960 1961 // Otherwise we found a node that is part of our pattern. For example in: 1962 // x = load ptr 1963 // y = x+4 1964 // store y -> ptr 1965 // This would happen when we're scanning down from the load and see the 1966 // store as a user. Record that there is a use of ChainedNode that is 1967 // part of the pattern and keep scanning uses. 1968 Result = CR_LeadsToInteriorNode; 1969 InteriorChainedNodes.push_back(User); 1970 continue; 1971 } 1972 1973 // If we found a TokenFactor, there are two cases to consider: first if the 1974 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1975 // uses of the TF are in our pattern) we just want to ignore it. Second, 1976 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1977 // [Load chain] 1978 // ^ 1979 // | 1980 // [Load] 1981 // ^ ^ 1982 // | \ DAG's like cheese 1983 // / \ do you? 1984 // / | 1985 // [TokenFactor] [Op] 1986 // ^ ^ 1987 // | | 1988 // \ / 1989 // \ / 1990 // [Store] 1991 // 1992 // In this case, the TokenFactor becomes part of our match and we rewrite it 1993 // as a new TokenFactor. 1994 // 1995 // To distinguish these two cases, do a recursive walk down the uses. 1996 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1997 case CR_Simple: 1998 // If the uses of the TokenFactor are just already-selected nodes, ignore 1999 // it, it is "below" our pattern. 2000 continue; 2001 case CR_InducesCycle: 2002 // If the uses of the TokenFactor lead to nodes that are not part of our 2003 // pattern that are not selected, folding would turn this into a cycle, 2004 // bail out now. 2005 return CR_InducesCycle; 2006 case CR_LeadsToInteriorNode: 2007 break; // Otherwise, keep processing. 2008 } 2009 2010 // Okay, we know we're in the interesting interior case. The TokenFactor 2011 // is now going to be considered part of the pattern so that we rewrite its 2012 // uses (it may have uses that are not part of the pattern) with the 2013 // ultimate chain result of the generated code. We will also add its chain 2014 // inputs as inputs to the ultimate TokenFactor we create. 2015 Result = CR_LeadsToInteriorNode; 2016 ChainedNodesInPattern.push_back(User); 2017 InteriorChainedNodes.push_back(User); 2018 continue; 2019 } 2020 2021 return Result; 2022} 2023 2024/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 2025/// operation for when the pattern matched at least one node with a chains. The 2026/// input vector contains a list of all of the chained nodes that we match. We 2027/// must determine if this is a valid thing to cover (i.e. matching it won't 2028/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 2029/// be used as the input node chain for the generated nodes. 2030static SDValue 2031HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 2032 SelectionDAG *CurDAG) { 2033 // Walk all of the chained nodes we've matched, recursively scanning down the 2034 // users of the chain result. This adds any TokenFactor nodes that are caught 2035 // in between chained nodes to the chained and interior nodes list. 2036 SmallVector<SDNode*, 3> InteriorChainedNodes; 2037 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2038 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 2039 InteriorChainedNodes) == CR_InducesCycle) 2040 return SDValue(); // Would induce a cycle. 2041 } 2042 2043 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 2044 // that we are interested in. Form our input TokenFactor node. 2045 SmallVector<SDValue, 3> InputChains; 2046 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2047 // Add the input chain of this node to the InputChains list (which will be 2048 // the operands of the generated TokenFactor) if it's not an interior node. 2049 SDNode *N = ChainNodesMatched[i]; 2050 if (N->getOpcode() != ISD::TokenFactor) { 2051 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 2052 continue; 2053 2054 // Otherwise, add the input chain. 2055 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 2056 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 2057 InputChains.push_back(InChain); 2058 continue; 2059 } 2060 2061 // If we have a token factor, we want to add all inputs of the token factor 2062 // that are not part of the pattern we're matching. 2063 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 2064 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 2065 N->getOperand(op).getNode())) 2066 InputChains.push_back(N->getOperand(op)); 2067 } 2068 } 2069 2070 if (InputChains.size() == 1) 2071 return InputChains[0]; 2072 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]), 2073 MVT::Other, &InputChains[0], InputChains.size()); 2074} 2075 2076/// MorphNode - Handle morphing a node in place for the selector. 2077SDNode *SelectionDAGISel:: 2078MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 2079 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 2080 // It is possible we're using MorphNodeTo to replace a node with no 2081 // normal results with one that has a normal result (or we could be 2082 // adding a chain) and the input could have glue and chains as well. 2083 // In this case we need to shift the operands down. 2084 // FIXME: This is a horrible hack and broken in obscure cases, no worse 2085 // than the old isel though. 2086 int OldGlueResultNo = -1, OldChainResultNo = -1; 2087 2088 unsigned NTMNumResults = Node->getNumValues(); 2089 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 2090 OldGlueResultNo = NTMNumResults-1; 2091 if (NTMNumResults != 1 && 2092 Node->getValueType(NTMNumResults-2) == MVT::Other) 2093 OldChainResultNo = NTMNumResults-2; 2094 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 2095 OldChainResultNo = NTMNumResults-1; 2096 2097 // Call the underlying SelectionDAG routine to do the transmogrification. Note 2098 // that this deletes operands of the old node that become dead. 2099 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 2100 2101 // MorphNodeTo can operate in two ways: if an existing node with the 2102 // specified operands exists, it can just return it. Otherwise, it 2103 // updates the node in place to have the requested operands. 2104 if (Res == Node) { 2105 // If we updated the node in place, reset the node ID. To the isel, 2106 // this should be just like a newly allocated machine node. 2107 Res->setNodeId(-1); 2108 } 2109 2110 unsigned ResNumResults = Res->getNumValues(); 2111 // Move the glue if needed. 2112 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 2113 (unsigned)OldGlueResultNo != ResNumResults-1) 2114 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 2115 SDValue(Res, ResNumResults-1)); 2116 2117 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 2118 --ResNumResults; 2119 2120 // Move the chain reference if needed. 2121 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 2122 (unsigned)OldChainResultNo != ResNumResults-1) 2123 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 2124 SDValue(Res, ResNumResults-1)); 2125 2126 // Otherwise, no replacement happened because the node already exists. Replace 2127 // Uses of the old node with the new one. 2128 if (Res != Node) 2129 CurDAG->ReplaceAllUsesWith(Node, Res); 2130 2131 return Res; 2132} 2133 2134/// CheckSame - Implements OP_CheckSame. 2135LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2136CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2137 SDValue N, 2138 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2139 // Accept if it is exactly the same as a previously recorded node. 2140 unsigned RecNo = MatcherTable[MatcherIndex++]; 2141 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2142 return N == RecordedNodes[RecNo].first; 2143} 2144 2145/// CheckChildSame - Implements OP_CheckChildXSame. 2146LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2147CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2148 SDValue N, 2149 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes, 2150 unsigned ChildNo) { 2151 if (ChildNo >= N.getNumOperands()) 2152 return false; // Match fails if out of range child #. 2153 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo), 2154 RecordedNodes); 2155} 2156 2157/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2158LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2159CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2160 const SelectionDAGISel &SDISel) { 2161 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 2162} 2163 2164/// CheckNodePredicate - Implements OP_CheckNodePredicate. 2165LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2166CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2167 const SelectionDAGISel &SDISel, SDNode *N) { 2168 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2169} 2170 2171LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2172CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2173 SDNode *N) { 2174 uint16_t Opc = MatcherTable[MatcherIndex++]; 2175 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2176 return N->getOpcode() == Opc; 2177} 2178 2179LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2180CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2181 SDValue N, const TargetLowering *TLI) { 2182 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2183 if (N.getValueType() == VT) return true; 2184 2185 // Handle the case when VT is iPTR. 2186 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(); 2187} 2188 2189LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2190CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2191 SDValue N, const TargetLowering *TLI, 2192 unsigned ChildNo) { 2193 if (ChildNo >= N.getNumOperands()) 2194 return false; // Match fails if out of range child #. 2195 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2196} 2197 2198LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2199CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2200 SDValue N) { 2201 return cast<CondCodeSDNode>(N)->get() == 2202 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2203} 2204 2205LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2206CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2207 SDValue N, const TargetLowering *TLI) { 2208 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2209 if (cast<VTSDNode>(N)->getVT() == VT) 2210 return true; 2211 2212 // Handle the case when VT is iPTR. 2213 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(); 2214} 2215 2216LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2217CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2218 SDValue N) { 2219 int64_t Val = MatcherTable[MatcherIndex++]; 2220 if (Val & 128) 2221 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2222 2223 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2224 return C != 0 && C->getSExtValue() == Val; 2225} 2226 2227LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2228CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2229 SDValue N, const SelectionDAGISel &SDISel) { 2230 int64_t Val = MatcherTable[MatcherIndex++]; 2231 if (Val & 128) 2232 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2233 2234 if (N->getOpcode() != ISD::AND) return false; 2235 2236 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2237 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2238} 2239 2240LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2241CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2242 SDValue N, const SelectionDAGISel &SDISel) { 2243 int64_t Val = MatcherTable[MatcherIndex++]; 2244 if (Val & 128) 2245 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2246 2247 if (N->getOpcode() != ISD::OR) return false; 2248 2249 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2250 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2251} 2252 2253/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2254/// scope, evaluate the current node. If the current predicate is known to 2255/// fail, set Result=true and return anything. If the current predicate is 2256/// known to pass, set Result=false and return the MatcherIndex to continue 2257/// with. If the current predicate is unknown, set Result=false and return the 2258/// MatcherIndex to continue with. 2259static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2260 unsigned Index, SDValue N, 2261 bool &Result, 2262 const SelectionDAGISel &SDISel, 2263 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2264 switch (Table[Index++]) { 2265 default: 2266 Result = false; 2267 return Index-1; // Could not evaluate this predicate. 2268 case SelectionDAGISel::OPC_CheckSame: 2269 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2270 return Index; 2271 case SelectionDAGISel::OPC_CheckChild0Same: 2272 case SelectionDAGISel::OPC_CheckChild1Same: 2273 case SelectionDAGISel::OPC_CheckChild2Same: 2274 case SelectionDAGISel::OPC_CheckChild3Same: 2275 Result = !::CheckChildSame(Table, Index, N, RecordedNodes, 2276 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same); 2277 return Index; 2278 case SelectionDAGISel::OPC_CheckPatternPredicate: 2279 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2280 return Index; 2281 case SelectionDAGISel::OPC_CheckPredicate: 2282 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2283 return Index; 2284 case SelectionDAGISel::OPC_CheckOpcode: 2285 Result = !::CheckOpcode(Table, Index, N.getNode()); 2286 return Index; 2287 case SelectionDAGISel::OPC_CheckType: 2288 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering()); 2289 return Index; 2290 case SelectionDAGISel::OPC_CheckChild0Type: 2291 case SelectionDAGISel::OPC_CheckChild1Type: 2292 case SelectionDAGISel::OPC_CheckChild2Type: 2293 case SelectionDAGISel::OPC_CheckChild3Type: 2294 case SelectionDAGISel::OPC_CheckChild4Type: 2295 case SelectionDAGISel::OPC_CheckChild5Type: 2296 case SelectionDAGISel::OPC_CheckChild6Type: 2297 case SelectionDAGISel::OPC_CheckChild7Type: 2298 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(), 2299 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2300 return Index; 2301 case SelectionDAGISel::OPC_CheckCondCode: 2302 Result = !::CheckCondCode(Table, Index, N); 2303 return Index; 2304 case SelectionDAGISel::OPC_CheckValueType: 2305 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering()); 2306 return Index; 2307 case SelectionDAGISel::OPC_CheckInteger: 2308 Result = !::CheckInteger(Table, Index, N); 2309 return Index; 2310 case SelectionDAGISel::OPC_CheckAndImm: 2311 Result = !::CheckAndImm(Table, Index, N, SDISel); 2312 return Index; 2313 case SelectionDAGISel::OPC_CheckOrImm: 2314 Result = !::CheckOrImm(Table, Index, N, SDISel); 2315 return Index; 2316 } 2317} 2318 2319namespace { 2320 2321struct MatchScope { 2322 /// FailIndex - If this match fails, this is the index to continue with. 2323 unsigned FailIndex; 2324 2325 /// NodeStack - The node stack when the scope was formed. 2326 SmallVector<SDValue, 4> NodeStack; 2327 2328 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2329 unsigned NumRecordedNodes; 2330 2331 /// NumMatchedMemRefs - The number of matched memref entries. 2332 unsigned NumMatchedMemRefs; 2333 2334 /// InputChain/InputGlue - The current chain/glue 2335 SDValue InputChain, InputGlue; 2336 2337 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2338 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2339}; 2340 2341} 2342 2343SDNode *SelectionDAGISel:: 2344SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2345 unsigned TableSize) { 2346 // FIXME: Should these even be selected? Handle these cases in the caller? 2347 switch (NodeToMatch->getOpcode()) { 2348 default: 2349 break; 2350 case ISD::EntryToken: // These nodes remain the same. 2351 case ISD::BasicBlock: 2352 case ISD::Register: 2353 case ISD::RegisterMask: 2354 //case ISD::VALUETYPE: 2355 //case ISD::CONDCODE: 2356 case ISD::HANDLENODE: 2357 case ISD::MDNODE_SDNODE: 2358 case ISD::TargetConstant: 2359 case ISD::TargetConstantFP: 2360 case ISD::TargetConstantPool: 2361 case ISD::TargetFrameIndex: 2362 case ISD::TargetExternalSymbol: 2363 case ISD::TargetBlockAddress: 2364 case ISD::TargetJumpTable: 2365 case ISD::TargetGlobalTLSAddress: 2366 case ISD::TargetGlobalAddress: 2367 case ISD::TokenFactor: 2368 case ISD::CopyFromReg: 2369 case ISD::CopyToReg: 2370 case ISD::EH_LABEL: 2371 case ISD::LIFETIME_START: 2372 case ISD::LIFETIME_END: 2373 NodeToMatch->setNodeId(-1); // Mark selected. 2374 return 0; 2375 case ISD::AssertSext: 2376 case ISD::AssertZext: 2377 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2378 NodeToMatch->getOperand(0)); 2379 return 0; 2380 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2381 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2382 } 2383 2384 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2385 2386 // Set up the node stack with NodeToMatch as the only node on the stack. 2387 SmallVector<SDValue, 8> NodeStack; 2388 SDValue N = SDValue(NodeToMatch, 0); 2389 NodeStack.push_back(N); 2390 2391 // MatchScopes - Scopes used when matching, if a match failure happens, this 2392 // indicates where to continue checking. 2393 SmallVector<MatchScope, 8> MatchScopes; 2394 2395 // RecordedNodes - This is the set of nodes that have been recorded by the 2396 // state machine. The second value is the parent of the node, or null if the 2397 // root is recorded. 2398 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2399 2400 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2401 // pattern. 2402 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2403 2404 // These are the current input chain and glue for use when generating nodes. 2405 // Various Emit operations change these. For example, emitting a copytoreg 2406 // uses and updates these. 2407 SDValue InputChain, InputGlue; 2408 2409 // ChainNodesMatched - If a pattern matches nodes that have input/output 2410 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2411 // which ones they are. The result is captured into this list so that we can 2412 // update the chain results when the pattern is complete. 2413 SmallVector<SDNode*, 3> ChainNodesMatched; 2414 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2415 2416 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: "; 2417 NodeToMatch->dump(CurDAG); 2418 dbgs() << '\n'); 2419 2420 // Determine where to start the interpreter. Normally we start at opcode #0, 2421 // but if the state machine starts with an OPC_SwitchOpcode, then we 2422 // accelerate the first lookup (which is guaranteed to be hot) with the 2423 // OpcodeOffset table. 2424 unsigned MatcherIndex = 0; 2425 2426 if (!OpcodeOffset.empty()) { 2427 // Already computed the OpcodeOffset table, just index into it. 2428 if (N.getOpcode() < OpcodeOffset.size()) 2429 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2430 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2431 2432 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2433 // Otherwise, the table isn't computed, but the state machine does start 2434 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2435 // is the first time we're selecting an instruction. 2436 unsigned Idx = 1; 2437 while (1) { 2438 // Get the size of this case. 2439 unsigned CaseSize = MatcherTable[Idx++]; 2440 if (CaseSize & 128) 2441 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2442 if (CaseSize == 0) break; 2443 2444 // Get the opcode, add the index to the table. 2445 uint16_t Opc = MatcherTable[Idx++]; 2446 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2447 if (Opc >= OpcodeOffset.size()) 2448 OpcodeOffset.resize((Opc+1)*2); 2449 OpcodeOffset[Opc] = Idx; 2450 Idx += CaseSize; 2451 } 2452 2453 // Okay, do the lookup for the first opcode. 2454 if (N.getOpcode() < OpcodeOffset.size()) 2455 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2456 } 2457 2458 while (1) { 2459 assert(MatcherIndex < TableSize && "Invalid index"); 2460#ifndef NDEBUG 2461 unsigned CurrentOpcodeIndex = MatcherIndex; 2462#endif 2463 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2464 switch (Opcode) { 2465 case OPC_Scope: { 2466 // Okay, the semantics of this operation are that we should push a scope 2467 // then evaluate the first child. However, pushing a scope only to have 2468 // the first check fail (which then pops it) is inefficient. If we can 2469 // determine immediately that the first check (or first several) will 2470 // immediately fail, don't even bother pushing a scope for them. 2471 unsigned FailIndex; 2472 2473 while (1) { 2474 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2475 if (NumToSkip & 128) 2476 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2477 // Found the end of the scope with no match. 2478 if (NumToSkip == 0) { 2479 FailIndex = 0; 2480 break; 2481 } 2482 2483 FailIndex = MatcherIndex+NumToSkip; 2484 2485 unsigned MatcherIndexOfPredicate = MatcherIndex; 2486 (void)MatcherIndexOfPredicate; // silence warning. 2487 2488 // If we can't evaluate this predicate without pushing a scope (e.g. if 2489 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2490 // push the scope and evaluate the full predicate chain. 2491 bool Result; 2492 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2493 Result, *this, RecordedNodes); 2494 if (!Result) 2495 break; 2496 2497 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at " 2498 << "index " << MatcherIndexOfPredicate 2499 << ", continuing at " << FailIndex << "\n"); 2500 ++NumDAGIselRetries; 2501 2502 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2503 // move to the next case. 2504 MatcherIndex = FailIndex; 2505 } 2506 2507 // If the whole scope failed to match, bail. 2508 if (FailIndex == 0) break; 2509 2510 // Push a MatchScope which indicates where to go if the first child fails 2511 // to match. 2512 MatchScope NewEntry; 2513 NewEntry.FailIndex = FailIndex; 2514 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2515 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2516 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2517 NewEntry.InputChain = InputChain; 2518 NewEntry.InputGlue = InputGlue; 2519 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2520 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2521 MatchScopes.push_back(NewEntry); 2522 continue; 2523 } 2524 case OPC_RecordNode: { 2525 // Remember this node, it may end up being an operand in the pattern. 2526 SDNode *Parent = 0; 2527 if (NodeStack.size() > 1) 2528 Parent = NodeStack[NodeStack.size()-2].getNode(); 2529 RecordedNodes.push_back(std::make_pair(N, Parent)); 2530 continue; 2531 } 2532 2533 case OPC_RecordChild0: case OPC_RecordChild1: 2534 case OPC_RecordChild2: case OPC_RecordChild3: 2535 case OPC_RecordChild4: case OPC_RecordChild5: 2536 case OPC_RecordChild6: case OPC_RecordChild7: { 2537 unsigned ChildNo = Opcode-OPC_RecordChild0; 2538 if (ChildNo >= N.getNumOperands()) 2539 break; // Match fails if out of range child #. 2540 2541 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2542 N.getNode())); 2543 continue; 2544 } 2545 case OPC_RecordMemRef: 2546 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2547 continue; 2548 2549 case OPC_CaptureGlueInput: 2550 // If the current node has an input glue, capture it in InputGlue. 2551 if (N->getNumOperands() != 0 && 2552 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2553 InputGlue = N->getOperand(N->getNumOperands()-1); 2554 continue; 2555 2556 case OPC_MoveChild: { 2557 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2558 if (ChildNo >= N.getNumOperands()) 2559 break; // Match fails if out of range child #. 2560 N = N.getOperand(ChildNo); 2561 NodeStack.push_back(N); 2562 continue; 2563 } 2564 2565 case OPC_MoveParent: 2566 // Pop the current node off the NodeStack. 2567 NodeStack.pop_back(); 2568 assert(!NodeStack.empty() && "Node stack imbalance!"); 2569 N = NodeStack.back(); 2570 continue; 2571 2572 case OPC_CheckSame: 2573 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2574 continue; 2575 2576 case OPC_CheckChild0Same: case OPC_CheckChild1Same: 2577 case OPC_CheckChild2Same: case OPC_CheckChild3Same: 2578 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes, 2579 Opcode-OPC_CheckChild0Same)) 2580 break; 2581 continue; 2582 2583 case OPC_CheckPatternPredicate: 2584 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2585 continue; 2586 case OPC_CheckPredicate: 2587 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2588 N.getNode())) 2589 break; 2590 continue; 2591 case OPC_CheckComplexPat: { 2592 unsigned CPNum = MatcherTable[MatcherIndex++]; 2593 unsigned RecNo = MatcherTable[MatcherIndex++]; 2594 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2595 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2596 RecordedNodes[RecNo].first, CPNum, 2597 RecordedNodes)) 2598 break; 2599 continue; 2600 } 2601 case OPC_CheckOpcode: 2602 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2603 continue; 2604 2605 case OPC_CheckType: 2606 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2607 break; 2608 continue; 2609 2610 case OPC_SwitchOpcode: { 2611 unsigned CurNodeOpcode = N.getOpcode(); 2612 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2613 unsigned CaseSize; 2614 while (1) { 2615 // Get the size of this case. 2616 CaseSize = MatcherTable[MatcherIndex++]; 2617 if (CaseSize & 128) 2618 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2619 if (CaseSize == 0) break; 2620 2621 uint16_t Opc = MatcherTable[MatcherIndex++]; 2622 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2623 2624 // If the opcode matches, then we will execute this case. 2625 if (CurNodeOpcode == Opc) 2626 break; 2627 2628 // Otherwise, skip over this case. 2629 MatcherIndex += CaseSize; 2630 } 2631 2632 // If no cases matched, bail out. 2633 if (CaseSize == 0) break; 2634 2635 // Otherwise, execute the case we found. 2636 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart 2637 << " to " << MatcherIndex << "\n"); 2638 continue; 2639 } 2640 2641 case OPC_SwitchType: { 2642 MVT CurNodeVT = N.getSimpleValueType(); 2643 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2644 unsigned CaseSize; 2645 while (1) { 2646 // Get the size of this case. 2647 CaseSize = MatcherTable[MatcherIndex++]; 2648 if (CaseSize & 128) 2649 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2650 if (CaseSize == 0) break; 2651 2652 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2653 if (CaseVT == MVT::iPTR) 2654 CaseVT = getTargetLowering()->getPointerTy(); 2655 2656 // If the VT matches, then we will execute this case. 2657 if (CurNodeVT == CaseVT) 2658 break; 2659 2660 // Otherwise, skip over this case. 2661 MatcherIndex += CaseSize; 2662 } 2663 2664 // If no cases matched, bail out. 2665 if (CaseSize == 0) break; 2666 2667 // Otherwise, execute the case we found. 2668 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2669 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2670 continue; 2671 } 2672 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2673 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2674 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2675 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2676 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(), 2677 Opcode-OPC_CheckChild0Type)) 2678 break; 2679 continue; 2680 case OPC_CheckCondCode: 2681 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2682 continue; 2683 case OPC_CheckValueType: 2684 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2685 break; 2686 continue; 2687 case OPC_CheckInteger: 2688 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2689 continue; 2690 case OPC_CheckAndImm: 2691 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2692 continue; 2693 case OPC_CheckOrImm: 2694 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2695 continue; 2696 2697 case OPC_CheckFoldableChainNode: { 2698 assert(NodeStack.size() != 1 && "No parent node"); 2699 // Verify that all intermediate nodes between the root and this one have 2700 // a single use. 2701 bool HasMultipleUses = false; 2702 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2703 if (!NodeStack[i].hasOneUse()) { 2704 HasMultipleUses = true; 2705 break; 2706 } 2707 if (HasMultipleUses) break; 2708 2709 // Check to see that the target thinks this is profitable to fold and that 2710 // we can fold it without inducing cycles in the graph. 2711 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2712 NodeToMatch) || 2713 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2714 NodeToMatch, OptLevel, 2715 true/*We validate our own chains*/)) 2716 break; 2717 2718 continue; 2719 } 2720 case OPC_EmitInteger: { 2721 MVT::SimpleValueType VT = 2722 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2723 int64_t Val = MatcherTable[MatcherIndex++]; 2724 if (Val & 128) 2725 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2726 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2727 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2728 continue; 2729 } 2730 case OPC_EmitRegister: { 2731 MVT::SimpleValueType VT = 2732 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2733 unsigned RegNo = MatcherTable[MatcherIndex++]; 2734 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2735 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2736 continue; 2737 } 2738 case OPC_EmitRegister2: { 2739 // For targets w/ more than 256 register names, the register enum 2740 // values are stored in two bytes in the matcher table (just like 2741 // opcodes). 2742 MVT::SimpleValueType VT = 2743 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2744 unsigned RegNo = MatcherTable[MatcherIndex++]; 2745 RegNo |= MatcherTable[MatcherIndex++] << 8; 2746 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2747 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2748 continue; 2749 } 2750 2751 case OPC_EmitConvertToTarget: { 2752 // Convert from IMM/FPIMM to target version. 2753 unsigned RecNo = MatcherTable[MatcherIndex++]; 2754 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget"); 2755 SDValue Imm = RecordedNodes[RecNo].first; 2756 2757 if (Imm->getOpcode() == ISD::Constant) { 2758 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 2759 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true); 2760 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2761 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2762 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true); 2763 } 2764 2765 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2766 continue; 2767 } 2768 2769 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2770 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2771 // These are space-optimized forms of OPC_EmitMergeInputChains. 2772 assert(InputChain.getNode() == 0 && 2773 "EmitMergeInputChains should be the first chain producing node"); 2774 assert(ChainNodesMatched.empty() && 2775 "Should only have one EmitMergeInputChains per match"); 2776 2777 // Read all of the chained nodes. 2778 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2779 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains"); 2780 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2781 2782 // FIXME: What if other value results of the node have uses not matched 2783 // by this pattern? 2784 if (ChainNodesMatched.back() != NodeToMatch && 2785 !RecordedNodes[RecNo].first.hasOneUse()) { 2786 ChainNodesMatched.clear(); 2787 break; 2788 } 2789 2790 // Merge the input chains if they are not intra-pattern references. 2791 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2792 2793 if (InputChain.getNode() == 0) 2794 break; // Failed to merge. 2795 continue; 2796 } 2797 2798 case OPC_EmitMergeInputChains: { 2799 assert(InputChain.getNode() == 0 && 2800 "EmitMergeInputChains should be the first chain producing node"); 2801 // This node gets a list of nodes we matched in the input that have 2802 // chains. We want to token factor all of the input chains to these nodes 2803 // together. However, if any of the input chains is actually one of the 2804 // nodes matched in this pattern, then we have an intra-match reference. 2805 // Ignore these because the newly token factored chain should not refer to 2806 // the old nodes. 2807 unsigned NumChains = MatcherTable[MatcherIndex++]; 2808 assert(NumChains != 0 && "Can't TF zero chains"); 2809 2810 assert(ChainNodesMatched.empty() && 2811 "Should only have one EmitMergeInputChains per match"); 2812 2813 // Read all of the chained nodes. 2814 for (unsigned i = 0; i != NumChains; ++i) { 2815 unsigned RecNo = MatcherTable[MatcherIndex++]; 2816 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains"); 2817 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2818 2819 // FIXME: What if other value results of the node have uses not matched 2820 // by this pattern? 2821 if (ChainNodesMatched.back() != NodeToMatch && 2822 !RecordedNodes[RecNo].first.hasOneUse()) { 2823 ChainNodesMatched.clear(); 2824 break; 2825 } 2826 } 2827 2828 // If the inner loop broke out, the match fails. 2829 if (ChainNodesMatched.empty()) 2830 break; 2831 2832 // Merge the input chains if they are not intra-pattern references. 2833 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2834 2835 if (InputChain.getNode() == 0) 2836 break; // Failed to merge. 2837 2838 continue; 2839 } 2840 2841 case OPC_EmitCopyToReg: { 2842 unsigned RecNo = MatcherTable[MatcherIndex++]; 2843 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg"); 2844 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2845 2846 if (InputChain.getNode() == 0) 2847 InputChain = CurDAG->getEntryNode(); 2848 2849 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch), 2850 DestPhysReg, RecordedNodes[RecNo].first, 2851 InputGlue); 2852 2853 InputGlue = InputChain.getValue(1); 2854 continue; 2855 } 2856 2857 case OPC_EmitNodeXForm: { 2858 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2859 unsigned RecNo = MatcherTable[MatcherIndex++]; 2860 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm"); 2861 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2862 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2863 continue; 2864 } 2865 2866 case OPC_EmitNode: 2867 case OPC_MorphNodeTo: { 2868 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2869 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2870 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2871 // Get the result VT list. 2872 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2873 SmallVector<EVT, 4> VTs; 2874 for (unsigned i = 0; i != NumVTs; ++i) { 2875 MVT::SimpleValueType VT = 2876 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2877 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy; 2878 VTs.push_back(VT); 2879 } 2880 2881 if (EmitNodeInfo & OPFL_Chain) 2882 VTs.push_back(MVT::Other); 2883 if (EmitNodeInfo & OPFL_GlueOutput) 2884 VTs.push_back(MVT::Glue); 2885 2886 // This is hot code, so optimize the two most common cases of 1 and 2 2887 // results. 2888 SDVTList VTList; 2889 if (VTs.size() == 1) 2890 VTList = CurDAG->getVTList(VTs[0]); 2891 else if (VTs.size() == 2) 2892 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2893 else 2894 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2895 2896 // Get the operand list. 2897 unsigned NumOps = MatcherTable[MatcherIndex++]; 2898 SmallVector<SDValue, 8> Ops; 2899 for (unsigned i = 0; i != NumOps; ++i) { 2900 unsigned RecNo = MatcherTable[MatcherIndex++]; 2901 if (RecNo & 128) 2902 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2903 2904 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2905 Ops.push_back(RecordedNodes[RecNo].first); 2906 } 2907 2908 // If there are variadic operands to add, handle them now. 2909 if (EmitNodeInfo & OPFL_VariadicInfo) { 2910 // Determine the start index to copy from. 2911 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2912 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2913 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2914 "Invalid variadic node"); 2915 // Copy all of the variadic operands, not including a potential glue 2916 // input. 2917 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2918 i != e; ++i) { 2919 SDValue V = NodeToMatch->getOperand(i); 2920 if (V.getValueType() == MVT::Glue) break; 2921 Ops.push_back(V); 2922 } 2923 } 2924 2925 // If this has chain/glue inputs, add them. 2926 if (EmitNodeInfo & OPFL_Chain) 2927 Ops.push_back(InputChain); 2928 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2929 Ops.push_back(InputGlue); 2930 2931 // Create the node. 2932 SDNode *Res = 0; 2933 if (Opcode != OPC_MorphNodeTo) { 2934 // If this is a normal EmitNode command, just create the new node and 2935 // add the results to the RecordedNodes list. 2936 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch), 2937 VTList, Ops); 2938 2939 // Add all the non-glue/non-chain results to the RecordedNodes list. 2940 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2941 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2942 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2943 (SDNode*) 0)); 2944 } 2945 2946 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 2947 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2948 EmitNodeInfo); 2949 } else { 2950 // NodeToMatch was eliminated by CSE when the target changed the DAG. 2951 // We will visit the equivalent node later. 2952 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 2953 return 0; 2954 } 2955 2956 // If the node had chain/glue results, update our notion of the current 2957 // chain and glue. 2958 if (EmitNodeInfo & OPFL_GlueOutput) { 2959 InputGlue = SDValue(Res, VTs.size()-1); 2960 if (EmitNodeInfo & OPFL_Chain) 2961 InputChain = SDValue(Res, VTs.size()-2); 2962 } else if (EmitNodeInfo & OPFL_Chain) 2963 InputChain = SDValue(Res, VTs.size()-1); 2964 2965 // If the OPFL_MemRefs glue is set on this node, slap all of the 2966 // accumulated memrefs onto it. 2967 // 2968 // FIXME: This is vastly incorrect for patterns with multiple outputs 2969 // instructions that access memory and for ComplexPatterns that match 2970 // loads. 2971 if (EmitNodeInfo & OPFL_MemRefs) { 2972 // Only attach load or store memory operands if the generated 2973 // instruction may load or store. 2974 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2975 bool mayLoad = MCID.mayLoad(); 2976 bool mayStore = MCID.mayStore(); 2977 2978 unsigned NumMemRefs = 0; 2979 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 2980 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2981 if ((*I)->isLoad()) { 2982 if (mayLoad) 2983 ++NumMemRefs; 2984 } else if ((*I)->isStore()) { 2985 if (mayStore) 2986 ++NumMemRefs; 2987 } else { 2988 ++NumMemRefs; 2989 } 2990 } 2991 2992 MachineSDNode::mmo_iterator MemRefs = 2993 MF->allocateMemRefsArray(NumMemRefs); 2994 2995 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 2996 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 2997 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2998 if ((*I)->isLoad()) { 2999 if (mayLoad) 3000 *MemRefsPos++ = *I; 3001 } else if ((*I)->isStore()) { 3002 if (mayStore) 3003 *MemRefsPos++ = *I; 3004 } else { 3005 *MemRefsPos++ = *I; 3006 } 3007 } 3008 3009 cast<MachineSDNode>(Res) 3010 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 3011 } 3012 3013 DEBUG(dbgs() << " " 3014 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 3015 << " node: "; Res->dump(CurDAG); dbgs() << "\n"); 3016 3017 // If this was a MorphNodeTo then we're completely done! 3018 if (Opcode == OPC_MorphNodeTo) { 3019 // Update chain and glue uses. 3020 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 3021 InputGlue, GlueResultNodesMatched, true); 3022 return Res; 3023 } 3024 3025 continue; 3026 } 3027 3028 case OPC_MarkGlueResults: { 3029 unsigned NumNodes = MatcherTable[MatcherIndex++]; 3030 3031 // Read and remember all the glue-result nodes. 3032 for (unsigned i = 0; i != NumNodes; ++i) { 3033 unsigned RecNo = MatcherTable[MatcherIndex++]; 3034 if (RecNo & 128) 3035 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 3036 3037 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults"); 3038 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 3039 } 3040 continue; 3041 } 3042 3043 case OPC_CompleteMatch: { 3044 // The match has been completed, and any new nodes (if any) have been 3045 // created. Patch up references to the matched dag to use the newly 3046 // created nodes. 3047 unsigned NumResults = MatcherTable[MatcherIndex++]; 3048 3049 for (unsigned i = 0; i != NumResults; ++i) { 3050 unsigned ResSlot = MatcherTable[MatcherIndex++]; 3051 if (ResSlot & 128) 3052 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 3053 3054 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch"); 3055 SDValue Res = RecordedNodes[ResSlot].first; 3056 3057 assert(i < NodeToMatch->getNumValues() && 3058 NodeToMatch->getValueType(i) != MVT::Other && 3059 NodeToMatch->getValueType(i) != MVT::Glue && 3060 "Invalid number of results to complete!"); 3061 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 3062 NodeToMatch->getValueType(i) == MVT::iPTR || 3063 Res.getValueType() == MVT::iPTR || 3064 NodeToMatch->getValueType(i).getSizeInBits() == 3065 Res.getValueType().getSizeInBits()) && 3066 "invalid replacement"); 3067 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 3068 } 3069 3070 // If the root node defines glue, add it to the glue nodes to update list. 3071 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 3072 GlueResultNodesMatched.push_back(NodeToMatch); 3073 3074 // Update chain and glue uses. 3075 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 3076 InputGlue, GlueResultNodesMatched, false); 3077 3078 assert(NodeToMatch->use_empty() && 3079 "Didn't replace all uses of the node?"); 3080 3081 // FIXME: We just return here, which interacts correctly with SelectRoot 3082 // above. We should fix this to not return an SDNode* anymore. 3083 return 0; 3084 } 3085 } 3086 3087 // If the code reached this point, then the match failed. See if there is 3088 // another child to try in the current 'Scope', otherwise pop it until we 3089 // find a case to check. 3090 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 3091 ++NumDAGIselRetries; 3092 while (1) { 3093 if (MatchScopes.empty()) { 3094 CannotYetSelect(NodeToMatch); 3095 return 0; 3096 } 3097 3098 // Restore the interpreter state back to the point where the scope was 3099 // formed. 3100 MatchScope &LastScope = MatchScopes.back(); 3101 RecordedNodes.resize(LastScope.NumRecordedNodes); 3102 NodeStack.clear(); 3103 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 3104 N = NodeStack.back(); 3105 3106 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 3107 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 3108 MatcherIndex = LastScope.FailIndex; 3109 3110 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); 3111 3112 InputChain = LastScope.InputChain; 3113 InputGlue = LastScope.InputGlue; 3114 if (!LastScope.HasChainNodesMatched) 3115 ChainNodesMatched.clear(); 3116 if (!LastScope.HasGlueResultNodesMatched) 3117 GlueResultNodesMatched.clear(); 3118 3119 // Check to see what the offset is at the new MatcherIndex. If it is zero 3120 // we have reached the end of this scope, otherwise we have another child 3121 // in the current scope to try. 3122 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 3123 if (NumToSkip & 128) 3124 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 3125 3126 // If we have another child in this scope to match, update FailIndex and 3127 // try it. 3128 if (NumToSkip != 0) { 3129 LastScope.FailIndex = MatcherIndex+NumToSkip; 3130 break; 3131 } 3132 3133 // End of this scope, pop it and try the next child in the containing 3134 // scope. 3135 MatchScopes.pop_back(); 3136 } 3137 } 3138} 3139 3140 3141 3142void SelectionDAGISel::CannotYetSelect(SDNode *N) { 3143 std::string msg; 3144 raw_string_ostream Msg(msg); 3145 Msg << "Cannot select: "; 3146 3147 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 3148 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 3149 N->getOpcode() != ISD::INTRINSIC_VOID) { 3150 N->printrFull(Msg, CurDAG); 3151 Msg << "\nIn function: " << MF->getName(); 3152 } else { 3153 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 3154 unsigned iid = 3155 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 3156 if (iid < Intrinsic::num_intrinsics) 3157 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 3158 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 3159 Msg << "target intrinsic %" << TII->getName(iid); 3160 else 3161 Msg << "unknown intrinsic #" << iid; 3162 } 3163 report_fatal_error(Msg.str()); 3164} 3165 3166char SelectionDAGISel::ID = 0; 3167