SelectionDAGISel.cpp revision 0ab86bed697bb390c97bd73a66cc4945ec75275b
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/FastISel.h" 32#include "llvm/CodeGen/GCStrategy.h" 33#include "llvm/CodeGen/GCMetadata.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineFunctionAnalysis.h" 36#include "llvm/CodeGen/MachineFrameInfo.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineJumpTableInfo.h" 39#include "llvm/CodeGen/MachineModuleInfo.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 42#include "llvm/CodeGen/SchedulerRegistry.h" 43#include "llvm/CodeGen/SelectionDAG.h" 44#include "llvm/CodeGen/DwarfWriter.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameInfo.h" 48#include "llvm/Target/TargetIntrinsicInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetLowering.h" 51#include "llvm/Target/TargetMachine.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/Timer.h" 58#include "llvm/Support/raw_ostream.h" 59#include "llvm/ADT/Statistic.h" 60#include <algorithm> 61using namespace llvm; 62 63STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 64STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 65 66static cl::opt<bool> 67EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 68 cl::desc("Enable verbose messages in the \"fast\" " 69 "instruction selector")); 70static cl::opt<bool> 71EnableFastISelAbort("fast-isel-abort", cl::Hidden, 72 cl::desc("Enable abort calls when \"fast\" instruction fails")); 73static cl::opt<bool> 74SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 75 cl::desc("Schedule copies of livein registers"), 76 cl::init(false)); 77 78#ifndef NDEBUG 79static cl::opt<bool> 80ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before the first " 82 "dag combine pass")); 83static cl::opt<bool> 84ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 85 cl::desc("Pop up a window to show dags before legalize types")); 86static cl::opt<bool> 87ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 88 cl::desc("Pop up a window to show dags before legalize")); 89static cl::opt<bool> 90ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 91 cl::desc("Pop up a window to show dags before the second " 92 "dag combine pass")); 93static cl::opt<bool> 94ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 95 cl::desc("Pop up a window to show dags before the post legalize types" 96 " dag combine pass")); 97static cl::opt<bool> 98ViewISelDAGs("view-isel-dags", cl::Hidden, 99 cl::desc("Pop up a window to show isel dags as they are selected")); 100static cl::opt<bool> 101ViewSchedDAGs("view-sched-dags", cl::Hidden, 102 cl::desc("Pop up a window to show sched dags as they are processed")); 103static cl::opt<bool> 104ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 105 cl::desc("Pop up a window to show SUnit dags after they are processed")); 106#else 107static const bool ViewDAGCombine1 = false, 108 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 109 ViewDAGCombine2 = false, 110 ViewDAGCombineLT = false, 111 ViewISelDAGs = false, ViewSchedDAGs = false, 112 ViewSUnitDAGs = false; 113#endif 114 115//===---------------------------------------------------------------------===// 116/// 117/// RegisterScheduler class - Track the registration of instruction schedulers. 118/// 119//===---------------------------------------------------------------------===// 120MachinePassRegistry RegisterScheduler::Registry; 121 122//===---------------------------------------------------------------------===// 123/// 124/// ISHeuristic command line option for instruction schedulers. 125/// 126//===---------------------------------------------------------------------===// 127static cl::opt<RegisterScheduler::FunctionPassCtor, false, 128 RegisterPassParser<RegisterScheduler> > 129ISHeuristic("pre-RA-sched", 130 cl::init(&createDefaultScheduler), 131 cl::desc("Instruction schedulers available (before register" 132 " allocation):")); 133 134static RegisterScheduler 135defaultListDAGScheduler("default", "Best scheduler for the target", 136 createDefaultScheduler); 137 138namespace llvm { 139 //===--------------------------------------------------------------------===// 140 /// createDefaultScheduler - This creates an instruction scheduler appropriate 141 /// for the target. 142 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 143 CodeGenOpt::Level OptLevel) { 144 const TargetLowering &TLI = IS->getTargetLowering(); 145 146 if (OptLevel == CodeGenOpt::None) 147 return createFastDAGScheduler(IS, OptLevel); 148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 149 return createTDListDAGScheduler(IS, OptLevel); 150 assert(TLI.getSchedulingPreference() == 151 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 152 return createBURRListDAGScheduler(IS, OptLevel); 153 } 154} 155 156// EmitInstrWithCustomInserter - This method should be implemented by targets 157// that mark instructions with the 'usesCustomInserter' flag. These 158// instructions are special in various ways, which require special support to 159// insert. The specified MachineInstr is created but not inserted into any 160// basic blocks, and this method is called to expand it into a sequence of 161// instructions, potentially also creating new basic blocks and control flow. 162// When new basic blocks are inserted and the edges from MBB to its successors 163// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 164// DenseMap. 165MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 166 MachineBasicBlock *MBB, 167 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 168#ifndef NDEBUG 169 dbgs() << "If a target marks an instruction with " 170 "'usesCustomInserter', it must implement " 171 "TargetLowering::EmitInstrWithCustomInserter!"; 172#endif 173 llvm_unreachable(0); 174 return 0; 175} 176 177/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 178/// physical register has only a single copy use, then coalesced the copy 179/// if possible. 180static void EmitLiveInCopy(MachineBasicBlock *MBB, 181 MachineBasicBlock::iterator &InsertPos, 182 unsigned VirtReg, unsigned PhysReg, 183 const TargetRegisterClass *RC, 184 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 185 const MachineRegisterInfo &MRI, 186 const TargetRegisterInfo &TRI, 187 const TargetInstrInfo &TII) { 188 unsigned NumUses = 0; 189 MachineInstr *UseMI = NULL; 190 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 191 UE = MRI.use_end(); UI != UE; ++UI) { 192 UseMI = &*UI; 193 if (++NumUses > 1) 194 break; 195 } 196 197 // If the number of uses is not one, or the use is not a move instruction, 198 // don't coalesce. Also, only coalesce away a virtual register to virtual 199 // register copy. 200 bool Coalesced = false; 201 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 202 if (NumUses == 1 && 203 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 204 TargetRegisterInfo::isVirtualRegister(DstReg)) { 205 VirtReg = DstReg; 206 Coalesced = true; 207 } 208 209 // Now find an ideal location to insert the copy. 210 MachineBasicBlock::iterator Pos = InsertPos; 211 while (Pos != MBB->begin()) { 212 MachineInstr *PrevMI = prior(Pos); 213 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 214 // copyRegToReg might emit multiple instructions to do a copy. 215 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 216 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 217 // This is what the BB looks like right now: 218 // r1024 = mov r0 219 // ... 220 // r1 = mov r1024 221 // 222 // We want to insert "r1025 = mov r1". Inserting this copy below the 223 // move to r1024 makes it impossible for that move to be coalesced. 224 // 225 // r1025 = mov r1 226 // r1024 = mov r0 227 // ... 228 // r1 = mov 1024 229 // r2 = mov 1025 230 break; // Woot! Found a good location. 231 --Pos; 232 } 233 234 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 235 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 236 (void) Emitted; 237 238 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 239 if (Coalesced) { 240 if (&*InsertPos == UseMI) ++InsertPos; 241 MBB->erase(UseMI); 242 } 243} 244 245/// EmitLiveInCopies - If this is the first basic block in the function, 246/// and if it has live ins that need to be copied into vregs, emit the 247/// copies into the block. 248static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 249 const MachineRegisterInfo &MRI, 250 const TargetRegisterInfo &TRI, 251 const TargetInstrInfo &TII) { 252 if (SchedLiveInCopies) { 253 // Emit the copies at a heuristically-determined location in the block. 254 DenseMap<MachineInstr*, unsigned> CopyRegMap; 255 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 256 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 257 E = MRI.livein_end(); LI != E; ++LI) 258 if (LI->second) { 259 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 260 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 261 RC, CopyRegMap, MRI, TRI, TII); 262 } 263 } else { 264 // Emit the copies into the top of the block. 265 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 266 E = MRI.livein_end(); LI != E; ++LI) 267 if (LI->second) { 268 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 269 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 270 LI->second, LI->first, RC, RC); 271 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 272 (void) Emitted; 273 } 274 } 275} 276 277//===----------------------------------------------------------------------===// 278// SelectionDAGISel code 279//===----------------------------------------------------------------------===// 280 281SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 282 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 283 FuncInfo(new FunctionLoweringInfo(TLI)), 284 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 285 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 286 GFI(), 287 OptLevel(OL), 288 DAGSize(0) 289{} 290 291SelectionDAGISel::~SelectionDAGISel() { 292 delete SDB; 293 delete CurDAG; 294 delete FuncInfo; 295} 296 297unsigned SelectionDAGISel::MakeReg(EVT VT) { 298 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 299} 300 301void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 302 AU.addRequired<AliasAnalysis>(); 303 AU.addPreserved<AliasAnalysis>(); 304 AU.addRequired<GCModuleInfo>(); 305 AU.addPreserved<GCModuleInfo>(); 306 AU.addRequired<DwarfWriter>(); 307 AU.addPreserved<DwarfWriter>(); 308 MachineFunctionPass::getAnalysisUsage(AU); 309} 310 311bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 312 Function &Fn = *mf.getFunction(); 313 314 // Do some sanity-checking on the command-line options. 315 assert((!EnableFastISelVerbose || EnableFastISel) && 316 "-fast-isel-verbose requires -fast-isel"); 317 assert((!EnableFastISelAbort || EnableFastISel) && 318 "-fast-isel-abort requires -fast-isel"); 319 320 // Get alias analysis for load/store combining. 321 AA = &getAnalysis<AliasAnalysis>(); 322 323 MF = &mf; 324 const TargetInstrInfo &TII = *TM.getInstrInfo(); 325 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 326 327 if (Fn.hasGC()) 328 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 329 else 330 GFI = 0; 331 RegInfo = &MF->getRegInfo(); 332 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 333 334 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 335 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 336 CurDAG->init(*MF, MMI, DW); 337 FuncInfo->set(Fn, *MF, EnableFastISel); 338 SDB->init(GFI, *AA); 339 340 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 341 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 342 // Mark landing pad. 343 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 344 345 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 346 347 // If the first basic block in the function has live ins that need to be 348 // copied into vregs, emit the copies into the top of the block before 349 // emitting the code for the block. 350 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 351 352 // Add function live-ins to entry block live-in set. 353 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 354 E = RegInfo->livein_end(); I != E; ++I) 355 MF->begin()->addLiveIn(I->first); 356 357#ifndef NDEBUG 358 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 359 "Not all catch info was assigned to a landing pad!"); 360#endif 361 362 FuncInfo->clear(); 363 364 return true; 365} 366 367/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 368/// attached with this instruction. 369static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB, 370 FastISel *FastIS, MachineFunction *MF) { 371 MDNode *Dbg = I->getDbgMetadata(); 372 if (Dbg == 0) return; 373 374 DILocation DILoc(Dbg); 375 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo()); 376 377 SDB->setCurDebugLoc(Loc); 378 379 if (FastIS) 380 FastIS->setCurDebugLoc(Loc); 381 382 // If the function doesn't have a default debug location yet, set 383 // it. This is kind of a hack. 384 if (MF->getDefaultDebugLoc().isUnknown()) 385 MF->setDefaultDebugLoc(Loc); 386} 387 388/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 389static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 390 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc()); 391 if (FastIS) 392 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc()); 393} 394 395void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 396 BasicBlock::iterator Begin, 397 BasicBlock::iterator End, 398 bool &HadTailCall) { 399 SDB->setCurrentBasicBlock(BB); 400 401 // Lower all of the non-terminator instructions. If a call is emitted 402 // as a tail call, cease emitting nodes for this block. 403 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 404 SetDebugLoc(I, SDB, 0, MF); 405 406 if (!isa<TerminatorInst>(I)) { 407 SDB->visit(*I); 408 409 // Set the current debug location back to "unknown" so that it doesn't 410 // spuriously apply to subsequent instructions. 411 ResetDebugLoc(SDB, 0); 412 } 413 } 414 415 if (!SDB->HasTailCall) { 416 // Ensure that all instructions which are used outside of their defining 417 // blocks are available as virtual registers. Invoke is handled elsewhere. 418 for (BasicBlock::iterator I = Begin; I != End; ++I) 419 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 420 SDB->CopyToExportRegsIfNeeded(I); 421 422 // Handle PHI nodes in successor blocks. 423 if (End == LLVMBB->end()) { 424 HandlePHINodesInSuccessorBlocks(LLVMBB); 425 426 // Lower the terminator after the copies are emitted. 427 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF); 428 SDB->visit(*LLVMBB->getTerminator()); 429 ResetDebugLoc(SDB, 0); 430 } 431 } 432 433 // Make sure the root of the DAG is up-to-date. 434 CurDAG->setRoot(SDB->getControlRoot()); 435 436 // Final step, emit the lowered DAG as machine code. 437 CodeGenAndEmitDAG(); 438 HadTailCall = SDB->HasTailCall; 439 SDB->clear(); 440} 441 442namespace { 443/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 444/// nodes from the worklist. 445class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 446 SmallVector<SDNode*, 128> &Worklist; 447 SmallPtrSet<SDNode*, 128> &InWorklist; 448public: 449 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 450 SmallPtrSet<SDNode*, 128> &inwl) 451 : Worklist(wl), InWorklist(inwl) {} 452 453 void RemoveFromWorklist(SDNode *N) { 454 if (!InWorklist.erase(N)) return; 455 456 SmallVector<SDNode*, 128>::iterator I = 457 std::find(Worklist.begin(), Worklist.end(), N); 458 assert(I != Worklist.end() && "Not in worklist"); 459 460 *I = Worklist.back(); 461 Worklist.pop_back(); 462 } 463 464 virtual void NodeDeleted(SDNode *N, SDNode *E) { 465 RemoveFromWorklist(N); 466 } 467 468 virtual void NodeUpdated(SDNode *N) { 469 // Ignore updates. 470 } 471}; 472} 473 474/// TrivialTruncElim - Eliminate some trivial nops that can result from 475/// ShrinkDemandedOps: (trunc (ext n)) -> n. 476static bool TrivialTruncElim(SDValue Op, 477 TargetLowering::TargetLoweringOpt &TLO) { 478 SDValue N0 = Op.getOperand(0); 479 EVT VT = Op.getValueType(); 480 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 481 N0.getOpcode() == ISD::SIGN_EXTEND || 482 N0.getOpcode() == ISD::ANY_EXTEND) && 483 N0.getOperand(0).getValueType() == VT) { 484 return TLO.CombineTo(Op, N0.getOperand(0)); 485 } 486 return false; 487} 488 489/// ShrinkDemandedOps - A late transformation pass that shrink expressions 490/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 491/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 492void SelectionDAGISel::ShrinkDemandedOps() { 493 SmallVector<SDNode*, 128> Worklist; 494 SmallPtrSet<SDNode*, 128> InWorklist; 495 496 // Add all the dag nodes to the worklist. 497 Worklist.reserve(CurDAG->allnodes_size()); 498 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 499 E = CurDAG->allnodes_end(); I != E; ++I) { 500 Worklist.push_back(I); 501 InWorklist.insert(I); 502 } 503 504 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true); 505 while (!Worklist.empty()) { 506 SDNode *N = Worklist.pop_back_val(); 507 InWorklist.erase(N); 508 509 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 510 // Deleting this node may make its operands dead, add them to the worklist 511 // if they aren't already there. 512 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 513 if (InWorklist.insert(N->getOperand(i).getNode())) 514 Worklist.push_back(N->getOperand(i).getNode()); 515 516 CurDAG->DeleteNode(N); 517 continue; 518 } 519 520 // Run ShrinkDemandedOp on scalar binary operations. 521 if (N->getNumValues() != 1 || 522 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 523 continue; 524 525 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 526 APInt Demanded = APInt::getAllOnesValue(BitWidth); 527 APInt KnownZero, KnownOne; 528 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 529 KnownZero, KnownOne, TLO) && 530 (N->getOpcode() != ISD::TRUNCATE || 531 !TrivialTruncElim(SDValue(N, 0), TLO))) 532 continue; 533 534 // Revisit the node. 535 assert(!InWorklist.count(N) && "Already in worklist"); 536 Worklist.push_back(N); 537 InWorklist.insert(N); 538 539 // Replace the old value with the new one. 540 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 541 TLO.Old.getNode()->dump(CurDAG); 542 errs() << "\nWith: "; 543 TLO.New.getNode()->dump(CurDAG); 544 errs() << '\n'); 545 546 if (InWorklist.insert(TLO.New.getNode())) 547 Worklist.push_back(TLO.New.getNode()); 548 549 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 550 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 551 552 if (!TLO.Old.getNode()->use_empty()) continue; 553 554 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 555 i != e; ++i) { 556 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 557 if (OpNode->hasOneUse()) { 558 // Add OpNode to the end of the list to revisit. 559 DeadNodes.RemoveFromWorklist(OpNode); 560 Worklist.push_back(OpNode); 561 InWorklist.insert(OpNode); 562 } 563 } 564 565 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 566 CurDAG->DeleteNode(TLO.Old.getNode()); 567 } 568} 569 570void SelectionDAGISel::ComputeLiveOutVRegInfo() { 571 SmallPtrSet<SDNode*, 128> VisitedNodes; 572 SmallVector<SDNode*, 128> Worklist; 573 574 Worklist.push_back(CurDAG->getRoot().getNode()); 575 576 APInt Mask; 577 APInt KnownZero; 578 APInt KnownOne; 579 580 do { 581 SDNode *N = Worklist.pop_back_val(); 582 583 // If we've already seen this node, ignore it. 584 if (!VisitedNodes.insert(N)) 585 continue; 586 587 // Otherwise, add all chain operands to the worklist. 588 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 589 if (N->getOperand(i).getValueType() == MVT::Other) 590 Worklist.push_back(N->getOperand(i).getNode()); 591 592 // If this is a CopyToReg with a vreg dest, process it. 593 if (N->getOpcode() != ISD::CopyToReg) 594 continue; 595 596 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 597 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 598 continue; 599 600 // Ignore non-scalar or non-integer values. 601 SDValue Src = N->getOperand(2); 602 EVT SrcVT = Src.getValueType(); 603 if (!SrcVT.isInteger() || SrcVT.isVector()) 604 continue; 605 606 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 607 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 608 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 609 610 // Only install this information if it tells us something. 611 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 612 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 613 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 614 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 615 FunctionLoweringInfo::LiveOutInfo &LOI = 616 FuncInfo->LiveOutRegInfo[DestReg]; 617 LOI.NumSignBits = NumSignBits; 618 LOI.KnownOne = KnownOne; 619 LOI.KnownZero = KnownZero; 620 } 621 } while (!Worklist.empty()); 622} 623 624void SelectionDAGISel::CodeGenAndEmitDAG() { 625 std::string GroupName; 626 if (TimePassesIsEnabled) 627 GroupName = "Instruction Selection and Scheduling"; 628 std::string BlockName; 629 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 630 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 631 ViewSUnitDAGs) 632 BlockName = MF->getFunction()->getNameStr() + ":" + 633 BB->getBasicBlock()->getNameStr(); 634 635 DEBUG(dbgs() << "Initial selection DAG:\n"); 636 DEBUG(CurDAG->dump()); 637 638 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 639 640 // Run the DAG combiner in pre-legalize mode. 641 if (TimePassesIsEnabled) { 642 NamedRegionTimer T("DAG Combining 1", GroupName); 643 CurDAG->Combine(Unrestricted, *AA, OptLevel); 644 } else { 645 CurDAG->Combine(Unrestricted, *AA, OptLevel); 646 } 647 648 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 649 DEBUG(CurDAG->dump()); 650 651 // Second step, hack on the DAG until it only uses operations and types that 652 // the target supports. 653 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 654 BlockName); 655 656 bool Changed; 657 if (TimePassesIsEnabled) { 658 NamedRegionTimer T("Type Legalization", GroupName); 659 Changed = CurDAG->LegalizeTypes(); 660 } else { 661 Changed = CurDAG->LegalizeTypes(); 662 } 663 664 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 665 DEBUG(CurDAG->dump()); 666 667 if (Changed) { 668 if (ViewDAGCombineLT) 669 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 670 671 // Run the DAG combiner in post-type-legalize mode. 672 if (TimePassesIsEnabled) { 673 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 674 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 675 } else { 676 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 677 } 678 679 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 680 DEBUG(CurDAG->dump()); 681 } 682 683 if (TimePassesIsEnabled) { 684 NamedRegionTimer T("Vector Legalization", GroupName); 685 Changed = CurDAG->LegalizeVectors(); 686 } else { 687 Changed = CurDAG->LegalizeVectors(); 688 } 689 690 if (Changed) { 691 if (TimePassesIsEnabled) { 692 NamedRegionTimer T("Type Legalization 2", GroupName); 693 CurDAG->LegalizeTypes(); 694 } else { 695 CurDAG->LegalizeTypes(); 696 } 697 698 if (ViewDAGCombineLT) 699 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 700 701 // Run the DAG combiner in post-type-legalize mode. 702 if (TimePassesIsEnabled) { 703 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 704 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 705 } else { 706 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 707 } 708 709 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 710 DEBUG(CurDAG->dump()); 711 } 712 713 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 714 715 if (TimePassesIsEnabled) { 716 NamedRegionTimer T("DAG Legalization", GroupName); 717 CurDAG->Legalize(OptLevel); 718 } else { 719 CurDAG->Legalize(OptLevel); 720 } 721 722 DEBUG(dbgs() << "Legalized selection DAG:\n"); 723 DEBUG(CurDAG->dump()); 724 725 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 726 727 // Run the DAG combiner in post-legalize mode. 728 if (TimePassesIsEnabled) { 729 NamedRegionTimer T("DAG Combining 2", GroupName); 730 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 731 } else { 732 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 733 } 734 735 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 736 DEBUG(CurDAG->dump()); 737 738 if (OptLevel != CodeGenOpt::None) { 739 ShrinkDemandedOps(); 740 ComputeLiveOutVRegInfo(); 741 } 742 743 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 744 745 // Third, instruction select all of the operations to machine code, adding the 746 // code to the MachineBasicBlock. 747 if (TimePassesIsEnabled) { 748 NamedRegionTimer T("Instruction Selection", GroupName); 749 DoInstructionSelection(); 750 } else { 751 DoInstructionSelection(); 752 } 753 754 DEBUG(dbgs() << "Selected selection DAG:\n"); 755 DEBUG(CurDAG->dump()); 756 757 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 758 759 // Schedule machine code. 760 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 761 if (TimePassesIsEnabled) { 762 NamedRegionTimer T("Instruction Scheduling", GroupName); 763 Scheduler->Run(CurDAG, BB, BB->end()); 764 } else { 765 Scheduler->Run(CurDAG, BB, BB->end()); 766 } 767 768 if (ViewSUnitDAGs) Scheduler->viewGraph(); 769 770 // Emit machine code to BB. This can change 'BB' to the last block being 771 // inserted into. 772 if (TimePassesIsEnabled) { 773 NamedRegionTimer T("Instruction Creation", GroupName); 774 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 775 } else { 776 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 777 } 778 779 // Free the scheduler state. 780 if (TimePassesIsEnabled) { 781 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 782 delete Scheduler; 783 } else { 784 delete Scheduler; 785 } 786 787 DEBUG(dbgs() << "Selected machine code:\n"); 788 DEBUG(BB->dump()); 789} 790 791void SelectionDAGISel::DoInstructionSelection() { 792 DEBUG(errs() << "===== Instruction selection begins:\n"); 793 794 PreprocessISelDAG(); 795 796 // Select target instructions for the DAG. 797 { 798 // Number all nodes with a topological order and set DAGSize. 799 DAGSize = CurDAG->AssignTopologicalOrder(); 800 801 // Create a dummy node (which is not added to allnodes), that adds 802 // a reference to the root node, preventing it from being deleted, 803 // and tracking any changes of the root. 804 HandleSDNode Dummy(CurDAG->getRoot()); 805 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 806 ++ISelPosition; 807 808 // The AllNodes list is now topological-sorted. Visit the 809 // nodes by starting at the end of the list (the root of the 810 // graph) and preceding back toward the beginning (the entry 811 // node). 812 while (ISelPosition != CurDAG->allnodes_begin()) { 813 SDNode *Node = --ISelPosition; 814 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 815 // but there are currently some corner cases that it misses. Also, this 816 // makes it theoretically possible to disable the DAGCombiner. 817 if (Node->use_empty()) 818 continue; 819 820 SDNode *ResNode = Select(Node); 821 822 // FIXME: This is pretty gross. 'Select' should be changed to not return 823 // anything at all and this code should be nuked with a tactical strike. 824 825 // If node should not be replaced, continue with the next one. 826 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 827 continue; 828 // Replace node. 829 if (ResNode) 830 ReplaceUses(Node, ResNode); 831 832 // If after the replacement this node is not used any more, 833 // remove this dead node. 834 if (Node->use_empty()) { // Don't delete EntryToken, etc. 835 ISelUpdater ISU(ISelPosition); 836 CurDAG->RemoveDeadNode(Node, &ISU); 837 } 838 } 839 840 CurDAG->setRoot(Dummy.getValue()); 841 } 842 DEBUG(errs() << "===== Instruction selection ends:\n"); 843 844 PostprocessISelDAG(); 845} 846 847 848void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 849 MachineFunction &MF, 850 MachineModuleInfo *MMI, 851 DwarfWriter *DW, 852 const TargetInstrInfo &TII) { 853 // Initialize the Fast-ISel state, if needed. 854 FastISel *FastIS = 0; 855 if (EnableFastISel) 856 FastIS = TLI.createFastISel(MF, MMI, DW, 857 FuncInfo->ValueMap, 858 FuncInfo->MBBMap, 859 FuncInfo->StaticAllocaMap 860#ifndef NDEBUG 861 , FuncInfo->CatchInfoLost 862#endif 863 ); 864 865 // Iterate over all basic blocks in the function. 866 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 867 BasicBlock *LLVMBB = &*I; 868 BB = FuncInfo->MBBMap[LLVMBB]; 869 870 BasicBlock::iterator const Begin = LLVMBB->begin(); 871 BasicBlock::iterator const End = LLVMBB->end(); 872 BasicBlock::iterator BI = Begin; 873 874 // Lower any arguments needed in this block if this is the entry block. 875 bool SuppressFastISel = false; 876 if (LLVMBB == &Fn.getEntryBlock()) { 877 LowerArguments(LLVMBB); 878 879 // If any of the arguments has the byval attribute, forgo 880 // fast-isel in the entry block. 881 if (FastIS) { 882 unsigned j = 1; 883 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 884 I != E; ++I, ++j) 885 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 886 if (EnableFastISelVerbose || EnableFastISelAbort) 887 dbgs() << "FastISel skips entry block due to byval argument\n"; 888 SuppressFastISel = true; 889 break; 890 } 891 } 892 } 893 894 if (MMI && BB->isLandingPad()) { 895 // Add a label to mark the beginning of the landing pad. Deletion of the 896 // landing pad can thus be detected via the MachineModuleInfo. 897 MCSymbol *Label = MMI->addLandingPad(BB); 898 899 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL); 900 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 901 902 // Mark exception register as live in. 903 unsigned Reg = TLI.getExceptionAddressRegister(); 904 if (Reg) BB->addLiveIn(Reg); 905 906 // Mark exception selector register as live in. 907 Reg = TLI.getExceptionSelectorRegister(); 908 if (Reg) BB->addLiveIn(Reg); 909 910 // FIXME: Hack around an exception handling flaw (PR1508): the personality 911 // function and list of typeids logically belong to the invoke (or, if you 912 // like, the basic block containing the invoke), and need to be associated 913 // with it in the dwarf exception handling tables. Currently however the 914 // information is provided by an intrinsic (eh.selector) that can be moved 915 // to unexpected places by the optimizers: if the unwind edge is critical, 916 // then breaking it can result in the intrinsics being in the successor of 917 // the landing pad, not the landing pad itself. This results 918 // in exceptions not being caught because no typeids are associated with 919 // the invoke. This may not be the only way things can go wrong, but it 920 // is the only way we try to work around for the moment. 921 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 922 923 if (Br && Br->isUnconditional()) { // Critical edge? 924 BasicBlock::iterator I, E; 925 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 926 if (isa<EHSelectorInst>(I)) 927 break; 928 929 if (I == E) 930 // No catch info found - try to extract some from the successor. 931 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 932 } 933 } 934 935 // Before doing SelectionDAG ISel, see if FastISel has been requested. 936 if (FastIS && !SuppressFastISel) { 937 // Emit code for any incoming arguments. This must happen before 938 // beginning FastISel on the entry block. 939 if (LLVMBB == &Fn.getEntryBlock()) { 940 CurDAG->setRoot(SDB->getControlRoot()); 941 CodeGenAndEmitDAG(); 942 SDB->clear(); 943 } 944 FastIS->startNewBlock(BB); 945 // Do FastISel on as many instructions as possible. 946 for (; BI != End; ++BI) { 947 // Just before the terminator instruction, insert instructions to 948 // feed PHI nodes in successor blocks. 949 if (isa<TerminatorInst>(BI)) 950 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 951 ++NumFastIselFailures; 952 ResetDebugLoc(SDB, FastIS); 953 if (EnableFastISelVerbose || EnableFastISelAbort) { 954 dbgs() << "FastISel miss: "; 955 BI->dump(); 956 } 957 assert(!EnableFastISelAbort && 958 "FastISel didn't handle a PHI in a successor"); 959 break; 960 } 961 962 SetDebugLoc(BI, SDB, FastIS, &MF); 963 964 // Try to select the instruction with FastISel. 965 if (FastIS->SelectInstruction(BI)) { 966 ResetDebugLoc(SDB, FastIS); 967 continue; 968 } 969 970 // Clear out the debug location so that it doesn't carry over to 971 // unrelated instructions. 972 ResetDebugLoc(SDB, FastIS); 973 974 // Then handle certain instructions as single-LLVM-Instruction blocks. 975 if (isa<CallInst>(BI)) { 976 ++NumFastIselFailures; 977 if (EnableFastISelVerbose || EnableFastISelAbort) { 978 dbgs() << "FastISel missed call: "; 979 BI->dump(); 980 } 981 982 if (!BI->getType()->isVoidTy()) { 983 unsigned &R = FuncInfo->ValueMap[BI]; 984 if (!R) 985 R = FuncInfo->CreateRegForValue(BI); 986 } 987 988 bool HadTailCall = false; 989 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 990 991 // If the call was emitted as a tail call, we're done with the block. 992 if (HadTailCall) { 993 BI = End; 994 break; 995 } 996 997 // If the instruction was codegen'd with multiple blocks, 998 // inform the FastISel object where to resume inserting. 999 FastIS->setCurrentBlock(BB); 1000 continue; 1001 } 1002 1003 // Otherwise, give up on FastISel for the rest of the block. 1004 // For now, be a little lenient about non-branch terminators. 1005 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 1006 ++NumFastIselFailures; 1007 if (EnableFastISelVerbose || EnableFastISelAbort) { 1008 dbgs() << "FastISel miss: "; 1009 BI->dump(); 1010 } 1011 if (EnableFastISelAbort) 1012 // The "fast" selector couldn't handle something and bailed. 1013 // For the purpose of debugging, just abort. 1014 llvm_unreachable("FastISel didn't select the entire block"); 1015 } 1016 break; 1017 } 1018 } 1019 1020 // Run SelectionDAG instruction selection on the remainder of the block 1021 // not handled by FastISel. If FastISel is not run, this is the entire 1022 // block. 1023 if (BI != End) { 1024 bool HadTailCall; 1025 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 1026 } 1027 1028 FinishBasicBlock(); 1029 } 1030 1031 delete FastIS; 1032} 1033 1034void 1035SelectionDAGISel::FinishBasicBlock() { 1036 1037 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 1038 DEBUG(BB->dump()); 1039 1040 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1041 << SDB->PHINodesToUpdate.size() << "\n"); 1042 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 1043 dbgs() << "Node " << i << " : (" 1044 << SDB->PHINodesToUpdate[i].first 1045 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 1046 1047 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1048 // PHI nodes in successors. 1049 if (SDB->SwitchCases.empty() && 1050 SDB->JTCases.empty() && 1051 SDB->BitTestCases.empty()) { 1052 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1053 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1054 assert(PHI->isPHI() && 1055 "This is not a machine PHI node that we are updating!"); 1056 if (!BB->isSuccessor(PHI->getParent())) 1057 continue; 1058 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1059 false)); 1060 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1061 } 1062 SDB->PHINodesToUpdate.clear(); 1063 return; 1064 } 1065 1066 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1067 // Lower header first, if it wasn't already lowered 1068 if (!SDB->BitTestCases[i].Emitted) { 1069 // Set the current basic block to the mbb we wish to insert the code into 1070 BB = SDB->BitTestCases[i].Parent; 1071 SDB->setCurrentBasicBlock(BB); 1072 // Emit the code 1073 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 1074 CurDAG->setRoot(SDB->getRoot()); 1075 CodeGenAndEmitDAG(); 1076 SDB->clear(); 1077 } 1078 1079 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1080 // Set the current basic block to the mbb we wish to insert the code into 1081 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 1082 SDB->setCurrentBasicBlock(BB); 1083 // Emit the code 1084 if (j+1 != ej) 1085 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 1086 SDB->BitTestCases[i].Reg, 1087 SDB->BitTestCases[i].Cases[j]); 1088 else 1089 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 1090 SDB->BitTestCases[i].Reg, 1091 SDB->BitTestCases[i].Cases[j]); 1092 1093 1094 CurDAG->setRoot(SDB->getRoot()); 1095 CodeGenAndEmitDAG(); 1096 SDB->clear(); 1097 } 1098 1099 // Update PHI Nodes 1100 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1101 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1102 MachineBasicBlock *PHIBB = PHI->getParent(); 1103 assert(PHI->isPHI() && 1104 "This is not a machine PHI node that we are updating!"); 1105 // This is "default" BB. We have two jumps to it. From "header" BB and 1106 // from last "case" BB. 1107 if (PHIBB == SDB->BitTestCases[i].Default) { 1108 PHI->addOperand(MachineOperand:: 1109 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1110 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1111 PHI->addOperand(MachineOperand:: 1112 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1113 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1114 back().ThisBB)); 1115 } 1116 // One of "cases" BB. 1117 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1118 j != ej; ++j) { 1119 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1120 if (cBB->isSuccessor(PHIBB)) { 1121 PHI->addOperand(MachineOperand:: 1122 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1123 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1124 } 1125 } 1126 } 1127 } 1128 SDB->BitTestCases.clear(); 1129 1130 // If the JumpTable record is filled in, then we need to emit a jump table. 1131 // Updating the PHI nodes is tricky in this case, since we need to determine 1132 // whether the PHI is a successor of the range check MBB or the jump table MBB 1133 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1134 // Lower header first, if it wasn't already lowered 1135 if (!SDB->JTCases[i].first.Emitted) { 1136 // Set the current basic block to the mbb we wish to insert the code into 1137 BB = SDB->JTCases[i].first.HeaderBB; 1138 SDB->setCurrentBasicBlock(BB); 1139 // Emit the code 1140 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 1141 CurDAG->setRoot(SDB->getRoot()); 1142 CodeGenAndEmitDAG(); 1143 SDB->clear(); 1144 } 1145 1146 // Set the current basic block to the mbb we wish to insert the code into 1147 BB = SDB->JTCases[i].second.MBB; 1148 SDB->setCurrentBasicBlock(BB); 1149 // Emit the code 1150 SDB->visitJumpTable(SDB->JTCases[i].second); 1151 CurDAG->setRoot(SDB->getRoot()); 1152 CodeGenAndEmitDAG(); 1153 SDB->clear(); 1154 1155 // Update PHI Nodes 1156 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1157 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1158 MachineBasicBlock *PHIBB = PHI->getParent(); 1159 assert(PHI->isPHI() && 1160 "This is not a machine PHI node that we are updating!"); 1161 // "default" BB. We can go there only from header BB. 1162 if (PHIBB == SDB->JTCases[i].second.Default) { 1163 PHI->addOperand 1164 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1165 PHI->addOperand 1166 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1167 } 1168 // JT BB. Just iterate over successors here 1169 if (BB->isSuccessor(PHIBB)) { 1170 PHI->addOperand 1171 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1172 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1173 } 1174 } 1175 } 1176 SDB->JTCases.clear(); 1177 1178 // If the switch block involved a branch to one of the actual successors, we 1179 // need to update PHI nodes in that block. 1180 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1181 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1182 assert(PHI->isPHI() && 1183 "This is not a machine PHI node that we are updating!"); 1184 if (BB->isSuccessor(PHI->getParent())) { 1185 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1186 false)); 1187 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1188 } 1189 } 1190 1191 // If we generated any switch lowering information, build and codegen any 1192 // additional DAGs necessary. 1193 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1194 // Set the current basic block to the mbb we wish to insert the code into 1195 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1196 SDB->setCurrentBasicBlock(BB); 1197 1198 // Emit the code 1199 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1200 CurDAG->setRoot(SDB->getRoot()); 1201 CodeGenAndEmitDAG(); 1202 1203 // Handle any PHI nodes in successors of this chunk, as if we were coming 1204 // from the original BB before switch expansion. Note that PHI nodes can 1205 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1206 // handle them the right number of times. 1207 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1208 // If new BB's are created during scheduling, the edges may have been 1209 // updated. That is, the edge from ThisBB to BB may have been split and 1210 // BB's predecessor is now another block. 1211 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1212 SDB->EdgeMapping.find(BB); 1213 if (EI != SDB->EdgeMapping.end()) 1214 ThisBB = EI->second; 1215 1216 // BB may have been removed from the CFG if a branch was constant folded. 1217 if (ThisBB->isSuccessor(BB)) { 1218 for (MachineBasicBlock::iterator Phi = BB->begin(); 1219 Phi != BB->end() && Phi->isPHI(); 1220 ++Phi) { 1221 // This value for this PHI node is recorded in PHINodesToUpdate. 1222 for (unsigned pn = 0; ; ++pn) { 1223 assert(pn != SDB->PHINodesToUpdate.size() && 1224 "Didn't find PHI entry!"); 1225 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1226 Phi->addOperand(MachineOperand:: 1227 CreateReg(SDB->PHINodesToUpdate[pn].second, 1228 false)); 1229 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1230 break; 1231 } 1232 } 1233 } 1234 } 1235 1236 // Don't process RHS if same block as LHS. 1237 if (BB == SDB->SwitchCases[i].FalseBB) 1238 SDB->SwitchCases[i].FalseBB = 0; 1239 1240 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1241 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1242 SDB->SwitchCases[i].FalseBB = 0; 1243 } 1244 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1245 SDB->clear(); 1246 } 1247 SDB->SwitchCases.clear(); 1248 1249 SDB->PHINodesToUpdate.clear(); 1250} 1251 1252 1253/// Create the scheduler. If a specific scheduler was specified 1254/// via the SchedulerRegistry, use it, otherwise select the 1255/// one preferred by the target. 1256/// 1257ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1258 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1259 1260 if (!Ctor) { 1261 Ctor = ISHeuristic; 1262 RegisterScheduler::setDefault(Ctor); 1263 } 1264 1265 return Ctor(this, OptLevel); 1266} 1267 1268ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1269 return new ScheduleHazardRecognizer(); 1270} 1271 1272//===----------------------------------------------------------------------===// 1273// Helper functions used by the generated instruction selector. 1274//===----------------------------------------------------------------------===// 1275// Calls to these methods are generated by tblgen. 1276 1277/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1278/// the dag combiner simplified the 255, we still want to match. RHS is the 1279/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1280/// specified in the .td file (e.g. 255). 1281bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1282 int64_t DesiredMaskS) const { 1283 const APInt &ActualMask = RHS->getAPIntValue(); 1284 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1285 1286 // If the actual mask exactly matches, success! 1287 if (ActualMask == DesiredMask) 1288 return true; 1289 1290 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1291 if (ActualMask.intersects(~DesiredMask)) 1292 return false; 1293 1294 // Otherwise, the DAG Combiner may have proven that the value coming in is 1295 // either already zero or is not demanded. Check for known zero input bits. 1296 APInt NeededMask = DesiredMask & ~ActualMask; 1297 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1298 return true; 1299 1300 // TODO: check to see if missing bits are just not demanded. 1301 1302 // Otherwise, this pattern doesn't match. 1303 return false; 1304} 1305 1306/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1307/// the dag combiner simplified the 255, we still want to match. RHS is the 1308/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1309/// specified in the .td file (e.g. 255). 1310bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1311 int64_t DesiredMaskS) const { 1312 const APInt &ActualMask = RHS->getAPIntValue(); 1313 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1314 1315 // If the actual mask exactly matches, success! 1316 if (ActualMask == DesiredMask) 1317 return true; 1318 1319 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1320 if (ActualMask.intersects(~DesiredMask)) 1321 return false; 1322 1323 // Otherwise, the DAG Combiner may have proven that the value coming in is 1324 // either already zero or is not demanded. Check for known zero input bits. 1325 APInt NeededMask = DesiredMask & ~ActualMask; 1326 1327 APInt KnownZero, KnownOne; 1328 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1329 1330 // If all the missing bits in the or are already known to be set, match! 1331 if ((NeededMask & KnownOne) == NeededMask) 1332 return true; 1333 1334 // TODO: check to see if missing bits are just not demanded. 1335 1336 // Otherwise, this pattern doesn't match. 1337 return false; 1338} 1339 1340 1341/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1342/// by tblgen. Others should not call it. 1343void SelectionDAGISel:: 1344SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1345 std::vector<SDValue> InOps; 1346 std::swap(InOps, Ops); 1347 1348 Ops.push_back(InOps[0]); // input chain. 1349 Ops.push_back(InOps[1]); // input asm string. 1350 1351 unsigned i = 2, e = InOps.size(); 1352 if (InOps[e-1].getValueType() == MVT::Flag) 1353 --e; // Don't process a flag operand if it is here. 1354 1355 while (i != e) { 1356 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1357 if ((Flags & 7) != 4 /*MEM*/) { 1358 // Just skip over this operand, copying the operands verbatim. 1359 Ops.insert(Ops.end(), InOps.begin()+i, 1360 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1361 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1362 } else { 1363 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1364 "Memory operand with multiple values?"); 1365 // Otherwise, this is a memory operand. Ask the target to select it. 1366 std::vector<SDValue> SelOps; 1367 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1368 llvm_report_error("Could not match memory address. Inline asm" 1369 " failure!"); 1370 } 1371 1372 // Add this to the output node. 1373 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1374 MVT::i32)); 1375 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1376 i += 2; 1377 } 1378 } 1379 1380 // Add the flag input back if present. 1381 if (e != InOps.size()) 1382 Ops.push_back(InOps.back()); 1383} 1384 1385/// findFlagUse - Return use of EVT::Flag value produced by the specified 1386/// SDNode. 1387/// 1388static SDNode *findFlagUse(SDNode *N) { 1389 unsigned FlagResNo = N->getNumValues()-1; 1390 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1391 SDUse &Use = I.getUse(); 1392 if (Use.getResNo() == FlagResNo) 1393 return Use.getUser(); 1394 } 1395 return NULL; 1396} 1397 1398/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1399/// This function recursively traverses up the operand chain, ignoring 1400/// certain nodes. 1401static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1402 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1403 bool IgnoreChains) { 1404 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1405 // greater than all of its (recursive) operands. If we scan to a point where 1406 // 'use' is smaller than the node we're scanning for, then we know we will 1407 // never find it. 1408 // 1409 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1410 // happen because we scan down to newly selected nodes in the case of flag 1411 // uses. 1412 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1413 return false; 1414 1415 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1416 // won't fail if we scan it again. 1417 if (!Visited.insert(Use)) 1418 return false; 1419 1420 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1421 // Ignore chain uses, they are validated by HandleMergeInputChains. 1422 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1423 continue; 1424 1425 SDNode *N = Use->getOperand(i).getNode(); 1426 if (N == Def) { 1427 if (Use == ImmedUse || Use == Root) 1428 continue; // We are not looking for immediate use. 1429 assert(N != Root); 1430 return true; 1431 } 1432 1433 // Traverse up the operand chain. 1434 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1435 return true; 1436 } 1437 return false; 1438} 1439 1440/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1441/// operand node N of U during instruction selection that starts at Root. 1442bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1443 SDNode *Root) const { 1444 if (OptLevel == CodeGenOpt::None) return false; 1445 return N.hasOneUse(); 1446} 1447 1448/// IsLegalToFold - Returns true if the specific operand node N of 1449/// U can be folded during instruction selection that starts at Root. 1450bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1451 bool IgnoreChains) const { 1452 if (OptLevel == CodeGenOpt::None) return false; 1453 1454 // If Root use can somehow reach N through a path that that doesn't contain 1455 // U then folding N would create a cycle. e.g. In the following 1456 // diagram, Root can reach N through X. If N is folded into into Root, then 1457 // X is both a predecessor and a successor of U. 1458 // 1459 // [N*] // 1460 // ^ ^ // 1461 // / \ // 1462 // [U*] [X]? // 1463 // ^ ^ // 1464 // \ / // 1465 // \ / // 1466 // [Root*] // 1467 // 1468 // * indicates nodes to be folded together. 1469 // 1470 // If Root produces a flag, then it gets (even more) interesting. Since it 1471 // will be "glued" together with its flag use in the scheduler, we need to 1472 // check if it might reach N. 1473 // 1474 // [N*] // 1475 // ^ ^ // 1476 // / \ // 1477 // [U*] [X]? // 1478 // ^ ^ // 1479 // \ \ // 1480 // \ | // 1481 // [Root*] | // 1482 // ^ | // 1483 // f | // 1484 // | / // 1485 // [Y] / // 1486 // ^ / // 1487 // f / // 1488 // | / // 1489 // [FU] // 1490 // 1491 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1492 // (call it Fold), then X is a predecessor of FU and a successor of 1493 // Fold. But since Fold and FU are flagged together, this will create 1494 // a cycle in the scheduling graph. 1495 1496 // If the node has flags, walk down the graph to the "lowest" node in the 1497 // flagged set. 1498 EVT VT = Root->getValueType(Root->getNumValues()-1); 1499 while (VT == MVT::Flag) { 1500 SDNode *FU = findFlagUse(Root); 1501 if (FU == NULL) 1502 break; 1503 Root = FU; 1504 VT = Root->getValueType(Root->getNumValues()-1); 1505 1506 // If our query node has a flag result with a use, we've walked up it. If 1507 // the user (which has already been selected) has a chain or indirectly uses 1508 // the chain, our WalkChainUsers predicate will not consider it. Because of 1509 // this, we cannot ignore chains in this predicate. 1510 IgnoreChains = false; 1511 } 1512 1513 1514 SmallPtrSet<SDNode*, 16> Visited; 1515 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1516} 1517 1518SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1519 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1520 SelectInlineAsmMemoryOperands(Ops); 1521 1522 std::vector<EVT> VTs; 1523 VTs.push_back(MVT::Other); 1524 VTs.push_back(MVT::Flag); 1525 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1526 VTs, &Ops[0], Ops.size()); 1527 New->setNodeId(-1); 1528 return New.getNode(); 1529} 1530 1531SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1532 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1533} 1534 1535/// GetVBR - decode a vbr encoding whose top bit is set. 1536ALWAYS_INLINE static uint64_t 1537GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1538 assert(Val >= 128 && "Not a VBR"); 1539 Val &= 127; // Remove first vbr bit. 1540 1541 unsigned Shift = 7; 1542 uint64_t NextBits; 1543 do { 1544 NextBits = MatcherTable[Idx++]; 1545 Val |= (NextBits&127) << Shift; 1546 Shift += 7; 1547 } while (NextBits & 128); 1548 1549 return Val; 1550} 1551 1552 1553/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1554/// interior flag and chain results to use the new flag and chain results. 1555void SelectionDAGISel:: 1556UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1557 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1558 SDValue InputFlag, 1559 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1560 bool isMorphNodeTo) { 1561 SmallVector<SDNode*, 4> NowDeadNodes; 1562 1563 ISelUpdater ISU(ISelPosition); 1564 1565 // Now that all the normal results are replaced, we replace the chain and 1566 // flag results if present. 1567 if (!ChainNodesMatched.empty()) { 1568 assert(InputChain.getNode() != 0 && 1569 "Matched input chains but didn't produce a chain"); 1570 // Loop over all of the nodes we matched that produced a chain result. 1571 // Replace all the chain results with the final chain we ended up with. 1572 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1573 SDNode *ChainNode = ChainNodesMatched[i]; 1574 1575 // If this node was already deleted, don't look at it. 1576 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1577 continue; 1578 1579 // Don't replace the results of the root node if we're doing a 1580 // MorphNodeTo. 1581 if (ChainNode == NodeToMatch && isMorphNodeTo) 1582 continue; 1583 1584 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1585 if (ChainVal.getValueType() == MVT::Flag) 1586 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1587 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1588 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1589 1590 // If the node became dead and we haven't already seen it, delete it. 1591 if (ChainNode->use_empty() && 1592 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1593 NowDeadNodes.push_back(ChainNode); 1594 } 1595 } 1596 1597 // If the result produces a flag, update any flag results in the matched 1598 // pattern with the flag result. 1599 if (InputFlag.getNode() != 0) { 1600 // Handle any interior nodes explicitly marked. 1601 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1602 SDNode *FRN = FlagResultNodesMatched[i]; 1603 1604 // If this node was already deleted, don't look at it. 1605 if (FRN->getOpcode() == ISD::DELETED_NODE) 1606 continue; 1607 1608 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1609 "Doesn't have a flag result"); 1610 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1611 InputFlag, &ISU); 1612 1613 // If the node became dead and we haven't already seen it, delete it. 1614 if (FRN->use_empty() && 1615 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1616 NowDeadNodes.push_back(FRN); 1617 } 1618 } 1619 1620 if (!NowDeadNodes.empty()) 1621 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1622 1623 DEBUG(errs() << "ISEL: Match complete!\n"); 1624} 1625 1626enum ChainResult { 1627 CR_Simple, 1628 CR_InducesCycle, 1629 CR_LeadsToInteriorNode 1630}; 1631 1632/// WalkChainUsers - Walk down the users of the specified chained node that is 1633/// part of the pattern we're matching, looking at all of the users we find. 1634/// This determines whether something is an interior node, whether we have a 1635/// non-pattern node in between two pattern nodes (which prevent folding because 1636/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1637/// between pattern nodes (in which case the TF becomes part of the pattern). 1638/// 1639/// The walk we do here is guaranteed to be small because we quickly get down to 1640/// already selected nodes "below" us. 1641static ChainResult 1642WalkChainUsers(SDNode *ChainedNode, 1643 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1644 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1645 ChainResult Result = CR_Simple; 1646 1647 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1648 E = ChainedNode->use_end(); UI != E; ++UI) { 1649 // Make sure the use is of the chain, not some other value we produce. 1650 if (UI.getUse().getValueType() != MVT::Other) continue; 1651 1652 SDNode *User = *UI; 1653 1654 // If we see an already-selected machine node, then we've gone beyond the 1655 // pattern that we're selecting down into the already selected chunk of the 1656 // DAG. 1657 if (User->isMachineOpcode() || 1658 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1659 continue; 1660 1661 if (User->getOpcode() == ISD::CopyToReg || 1662 User->getOpcode() == ISD::CopyFromReg || 1663 User->getOpcode() == ISD::INLINEASM || 1664 User->getOpcode() == ISD::EH_LABEL) { 1665 // If their node ID got reset to -1 then they've already been selected. 1666 // Treat them like a MachineOpcode. 1667 if (User->getNodeId() == -1) 1668 continue; 1669 } 1670 1671 // If we have a TokenFactor, we handle it specially. 1672 if (User->getOpcode() != ISD::TokenFactor) { 1673 // If the node isn't a token factor and isn't part of our pattern, then it 1674 // must be a random chained node in between two nodes we're selecting. 1675 // This happens when we have something like: 1676 // x = load ptr 1677 // call 1678 // y = x+4 1679 // store y -> ptr 1680 // Because we structurally match the load/store as a read/modify/write, 1681 // but the call is chained between them. We cannot fold in this case 1682 // because it would induce a cycle in the graph. 1683 if (!std::count(ChainedNodesInPattern.begin(), 1684 ChainedNodesInPattern.end(), User)) 1685 return CR_InducesCycle; 1686 1687 // Otherwise we found a node that is part of our pattern. For example in: 1688 // x = load ptr 1689 // y = x+4 1690 // store y -> ptr 1691 // This would happen when we're scanning down from the load and see the 1692 // store as a user. Record that there is a use of ChainedNode that is 1693 // part of the pattern and keep scanning uses. 1694 Result = CR_LeadsToInteriorNode; 1695 InteriorChainedNodes.push_back(User); 1696 continue; 1697 } 1698 1699 // If we found a TokenFactor, there are two cases to consider: first if the 1700 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1701 // uses of the TF are in our pattern) we just want to ignore it. Second, 1702 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1703 // [Load chain] 1704 // ^ 1705 // | 1706 // [Load] 1707 // ^ ^ 1708 // | \ DAG's like cheese 1709 // / \ do you? 1710 // / | 1711 // [TokenFactor] [Op] 1712 // ^ ^ 1713 // | | 1714 // \ / 1715 // \ / 1716 // [Store] 1717 // 1718 // In this case, the TokenFactor becomes part of our match and we rewrite it 1719 // as a new TokenFactor. 1720 // 1721 // To distinguish these two cases, do a recursive walk down the uses. 1722 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1723 case CR_Simple: 1724 // If the uses of the TokenFactor are just already-selected nodes, ignore 1725 // it, it is "below" our pattern. 1726 continue; 1727 case CR_InducesCycle: 1728 // If the uses of the TokenFactor lead to nodes that are not part of our 1729 // pattern that are not selected, folding would turn this into a cycle, 1730 // bail out now. 1731 return CR_InducesCycle; 1732 case CR_LeadsToInteriorNode: 1733 break; // Otherwise, keep processing. 1734 } 1735 1736 // Okay, we know we're in the interesting interior case. The TokenFactor 1737 // is now going to be considered part of the pattern so that we rewrite its 1738 // uses (it may have uses that are not part of the pattern) with the 1739 // ultimate chain result of the generated code. We will also add its chain 1740 // inputs as inputs to the ultimate TokenFactor we create. 1741 Result = CR_LeadsToInteriorNode; 1742 ChainedNodesInPattern.push_back(User); 1743 InteriorChainedNodes.push_back(User); 1744 continue; 1745 } 1746 1747 return Result; 1748} 1749 1750/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1751/// operation for when the pattern matched at least one node with a chains. The 1752/// input vector contains a list of all of the chained nodes that we match. We 1753/// must determine if this is a valid thing to cover (i.e. matching it won't 1754/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1755/// be used as the input node chain for the generated nodes. 1756static SDValue 1757HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1758 SelectionDAG *CurDAG) { 1759 // Walk all of the chained nodes we've matched, recursively scanning down the 1760 // users of the chain result. This adds any TokenFactor nodes that are caught 1761 // in between chained nodes to the chained and interior nodes list. 1762 SmallVector<SDNode*, 3> InteriorChainedNodes; 1763 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1764 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1765 InteriorChainedNodes) == CR_InducesCycle) 1766 return SDValue(); // Would induce a cycle. 1767 } 1768 1769 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1770 // that we are interested in. Form our input TokenFactor node. 1771 SmallVector<SDValue, 3> InputChains; 1772 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1773 // Add the input chain of this node to the InputChains list (which will be 1774 // the operands of the generated TokenFactor) if it's not an interior node. 1775 SDNode *N = ChainNodesMatched[i]; 1776 if (N->getOpcode() != ISD::TokenFactor) { 1777 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1778 continue; 1779 1780 // Otherwise, add the input chain. 1781 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1782 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1783 InputChains.push_back(InChain); 1784 continue; 1785 } 1786 1787 // If we have a token factor, we want to add all inputs of the token factor 1788 // that are not part of the pattern we're matching. 1789 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1790 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1791 N->getOperand(op).getNode())) 1792 InputChains.push_back(N->getOperand(op)); 1793 } 1794 } 1795 1796 SDValue Res; 1797 if (InputChains.size() == 1) 1798 return InputChains[0]; 1799 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1800 MVT::Other, &InputChains[0], InputChains.size()); 1801} 1802 1803/// MorphNode - Handle morphing a node in place for the selector. 1804SDNode *SelectionDAGISel:: 1805MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1806 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1807 // It is possible we're using MorphNodeTo to replace a node with no 1808 // normal results with one that has a normal result (or we could be 1809 // adding a chain) and the input could have flags and chains as well. 1810 // In this case we need to shift the operands down. 1811 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1812 // than the old isel though. 1813 int OldFlagResultNo = -1, OldChainResultNo = -1; 1814 1815 unsigned NTMNumResults = Node->getNumValues(); 1816 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1817 OldFlagResultNo = NTMNumResults-1; 1818 if (NTMNumResults != 1 && 1819 Node->getValueType(NTMNumResults-2) == MVT::Other) 1820 OldChainResultNo = NTMNumResults-2; 1821 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1822 OldChainResultNo = NTMNumResults-1; 1823 1824 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1825 // that this deletes operands of the old node that become dead. 1826 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1827 1828 // MorphNodeTo can operate in two ways: if an existing node with the 1829 // specified operands exists, it can just return it. Otherwise, it 1830 // updates the node in place to have the requested operands. 1831 if (Res == Node) { 1832 // If we updated the node in place, reset the node ID. To the isel, 1833 // this should be just like a newly allocated machine node. 1834 Res->setNodeId(-1); 1835 } 1836 1837 unsigned ResNumResults = Res->getNumValues(); 1838 // Move the flag if needed. 1839 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1840 (unsigned)OldFlagResultNo != ResNumResults-1) 1841 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1842 SDValue(Res, ResNumResults-1)); 1843 1844 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1845 --ResNumResults; 1846 1847 // Move the chain reference if needed. 1848 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1849 (unsigned)OldChainResultNo != ResNumResults-1) 1850 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1851 SDValue(Res, ResNumResults-1)); 1852 1853 // Otherwise, no replacement happened because the node already exists. Replace 1854 // Uses of the old node with the new one. 1855 if (Res != Node) 1856 CurDAG->ReplaceAllUsesWith(Node, Res); 1857 1858 return Res; 1859} 1860 1861/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1862ALWAYS_INLINE static bool 1863CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1864 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1865 // Accept if it is exactly the same as a previously recorded node. 1866 unsigned RecNo = MatcherTable[MatcherIndex++]; 1867 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1868 return N == RecordedNodes[RecNo]; 1869} 1870 1871/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1872ALWAYS_INLINE static bool 1873CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1874 SelectionDAGISel &SDISel) { 1875 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1876} 1877 1878/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1879ALWAYS_INLINE static bool 1880CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1881 SelectionDAGISel &SDISel, SDNode *N) { 1882 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1883} 1884 1885ALWAYS_INLINE static bool 1886CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1887 SDNode *N) { 1888 uint16_t Opc = MatcherTable[MatcherIndex++]; 1889 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1890 return N->getOpcode() == Opc; 1891} 1892 1893ALWAYS_INLINE static bool 1894CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1895 SDValue N, const TargetLowering &TLI) { 1896 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1897 if (N.getValueType() == VT) return true; 1898 1899 // Handle the case when VT is iPTR. 1900 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1901} 1902 1903ALWAYS_INLINE static bool 1904CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1905 SDValue N, const TargetLowering &TLI, 1906 unsigned ChildNo) { 1907 if (ChildNo >= N.getNumOperands()) 1908 return false; // Match fails if out of range child #. 1909 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1910} 1911 1912 1913ALWAYS_INLINE static bool 1914CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1915 SDValue N) { 1916 return cast<CondCodeSDNode>(N)->get() == 1917 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1918} 1919 1920ALWAYS_INLINE static bool 1921CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1922 SDValue N, const TargetLowering &TLI) { 1923 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1924 if (cast<VTSDNode>(N)->getVT() == VT) 1925 return true; 1926 1927 // Handle the case when VT is iPTR. 1928 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1929} 1930 1931ALWAYS_INLINE static bool 1932CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1933 SDValue N) { 1934 int64_t Val = MatcherTable[MatcherIndex++]; 1935 if (Val & 128) 1936 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1937 1938 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1939 return C != 0 && C->getSExtValue() == Val; 1940} 1941 1942ALWAYS_INLINE static bool 1943CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1944 SDValue N, SelectionDAGISel &SDISel) { 1945 int64_t Val = MatcherTable[MatcherIndex++]; 1946 if (Val & 128) 1947 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1948 1949 if (N->getOpcode() != ISD::AND) return false; 1950 1951 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1952 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1953} 1954 1955ALWAYS_INLINE static bool 1956CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1957 SDValue N, SelectionDAGISel &SDISel) { 1958 int64_t Val = MatcherTable[MatcherIndex++]; 1959 if (Val & 128) 1960 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1961 1962 if (N->getOpcode() != ISD::OR) return false; 1963 1964 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1965 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1966} 1967 1968/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1969/// scope, evaluate the current node. If the current predicate is known to 1970/// fail, set Result=true and return anything. If the current predicate is 1971/// known to pass, set Result=false and return the MatcherIndex to continue 1972/// with. If the current predicate is unknown, set Result=false and return the 1973/// MatcherIndex to continue with. 1974static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1975 unsigned Index, SDValue N, 1976 bool &Result, SelectionDAGISel &SDISel, 1977 SmallVectorImpl<SDValue> &RecordedNodes){ 1978 switch (Table[Index++]) { 1979 default: 1980 Result = false; 1981 return Index-1; // Could not evaluate this predicate. 1982 case SelectionDAGISel::OPC_CheckSame: 1983 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1984 return Index; 1985 case SelectionDAGISel::OPC_CheckPatternPredicate: 1986 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1987 return Index; 1988 case SelectionDAGISel::OPC_CheckPredicate: 1989 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1990 return Index; 1991 case SelectionDAGISel::OPC_CheckOpcode: 1992 Result = !::CheckOpcode(Table, Index, N.getNode()); 1993 return Index; 1994 case SelectionDAGISel::OPC_CheckType: 1995 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1996 return Index; 1997 case SelectionDAGISel::OPC_CheckChild0Type: 1998 case SelectionDAGISel::OPC_CheckChild1Type: 1999 case SelectionDAGISel::OPC_CheckChild2Type: 2000 case SelectionDAGISel::OPC_CheckChild3Type: 2001 case SelectionDAGISel::OPC_CheckChild4Type: 2002 case SelectionDAGISel::OPC_CheckChild5Type: 2003 case SelectionDAGISel::OPC_CheckChild6Type: 2004 case SelectionDAGISel::OPC_CheckChild7Type: 2005 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 2006 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2007 return Index; 2008 case SelectionDAGISel::OPC_CheckCondCode: 2009 Result = !::CheckCondCode(Table, Index, N); 2010 return Index; 2011 case SelectionDAGISel::OPC_CheckValueType: 2012 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2013 return Index; 2014 case SelectionDAGISel::OPC_CheckInteger: 2015 Result = !::CheckInteger(Table, Index, N); 2016 return Index; 2017 case SelectionDAGISel::OPC_CheckAndImm: 2018 Result = !::CheckAndImm(Table, Index, N, SDISel); 2019 return Index; 2020 case SelectionDAGISel::OPC_CheckOrImm: 2021 Result = !::CheckOrImm(Table, Index, N, SDISel); 2022 return Index; 2023 } 2024} 2025 2026 2027struct MatchScope { 2028 /// FailIndex - If this match fails, this is the index to continue with. 2029 unsigned FailIndex; 2030 2031 /// NodeStack - The node stack when the scope was formed. 2032 SmallVector<SDValue, 4> NodeStack; 2033 2034 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2035 unsigned NumRecordedNodes; 2036 2037 /// NumMatchedMemRefs - The number of matched memref entries. 2038 unsigned NumMatchedMemRefs; 2039 2040 /// InputChain/InputFlag - The current chain/flag 2041 SDValue InputChain, InputFlag; 2042 2043 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2044 bool HasChainNodesMatched, HasFlagResultNodesMatched; 2045}; 2046 2047SDNode *SelectionDAGISel:: 2048SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2049 unsigned TableSize) { 2050 // FIXME: Should these even be selected? Handle these cases in the caller? 2051 switch (NodeToMatch->getOpcode()) { 2052 default: 2053 break; 2054 case ISD::EntryToken: // These nodes remain the same. 2055 case ISD::BasicBlock: 2056 case ISD::Register: 2057 //case ISD::VALUETYPE: 2058 //case ISD::CONDCODE: 2059 case ISD::HANDLENODE: 2060 case ISD::TargetConstant: 2061 case ISD::TargetConstantFP: 2062 case ISD::TargetConstantPool: 2063 case ISD::TargetFrameIndex: 2064 case ISD::TargetExternalSymbol: 2065 case ISD::TargetBlockAddress: 2066 case ISD::TargetJumpTable: 2067 case ISD::TargetGlobalTLSAddress: 2068 case ISD::TargetGlobalAddress: 2069 case ISD::TokenFactor: 2070 case ISD::CopyFromReg: 2071 case ISD::CopyToReg: 2072 case ISD::EH_LABEL: 2073 NodeToMatch->setNodeId(-1); // Mark selected. 2074 return 0; 2075 case ISD::AssertSext: 2076 case ISD::AssertZext: 2077 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2078 NodeToMatch->getOperand(0)); 2079 return 0; 2080 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2081 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2082 } 2083 2084 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2085 2086 // Set up the node stack with NodeToMatch as the only node on the stack. 2087 SmallVector<SDValue, 8> NodeStack; 2088 SDValue N = SDValue(NodeToMatch, 0); 2089 NodeStack.push_back(N); 2090 2091 // MatchScopes - Scopes used when matching, if a match failure happens, this 2092 // indicates where to continue checking. 2093 SmallVector<MatchScope, 8> MatchScopes; 2094 2095 // RecordedNodes - This is the set of nodes that have been recorded by the 2096 // state machine. 2097 SmallVector<SDValue, 8> RecordedNodes; 2098 2099 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2100 // pattern. 2101 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2102 2103 // These are the current input chain and flag for use when generating nodes. 2104 // Various Emit operations change these. For example, emitting a copytoreg 2105 // uses and updates these. 2106 SDValue InputChain, InputFlag; 2107 2108 // ChainNodesMatched - If a pattern matches nodes that have input/output 2109 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2110 // which ones they are. The result is captured into this list so that we can 2111 // update the chain results when the pattern is complete. 2112 SmallVector<SDNode*, 3> ChainNodesMatched; 2113 SmallVector<SDNode*, 3> FlagResultNodesMatched; 2114 2115 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2116 NodeToMatch->dump(CurDAG); 2117 errs() << '\n'); 2118 2119 // Determine where to start the interpreter. Normally we start at opcode #0, 2120 // but if the state machine starts with an OPC_SwitchOpcode, then we 2121 // accelerate the first lookup (which is guaranteed to be hot) with the 2122 // OpcodeOffset table. 2123 unsigned MatcherIndex = 0; 2124 2125 if (!OpcodeOffset.empty()) { 2126 // Already computed the OpcodeOffset table, just index into it. 2127 if (N.getOpcode() < OpcodeOffset.size()) 2128 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2129 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2130 2131 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2132 // Otherwise, the table isn't computed, but the state machine does start 2133 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2134 // is the first time we're selecting an instruction. 2135 unsigned Idx = 1; 2136 while (1) { 2137 // Get the size of this case. 2138 unsigned CaseSize = MatcherTable[Idx++]; 2139 if (CaseSize & 128) 2140 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2141 if (CaseSize == 0) break; 2142 2143 // Get the opcode, add the index to the table. 2144 uint16_t Opc = MatcherTable[Idx++]; 2145 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2146 if (Opc >= OpcodeOffset.size()) 2147 OpcodeOffset.resize((Opc+1)*2); 2148 OpcodeOffset[Opc] = Idx; 2149 Idx += CaseSize; 2150 } 2151 2152 // Okay, do the lookup for the first opcode. 2153 if (N.getOpcode() < OpcodeOffset.size()) 2154 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2155 } 2156 2157 while (1) { 2158 assert(MatcherIndex < TableSize && "Invalid index"); 2159#ifndef NDEBUG 2160 unsigned CurrentOpcodeIndex = MatcherIndex; 2161#endif 2162 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2163 switch (Opcode) { 2164 case OPC_Scope: { 2165 // Okay, the semantics of this operation are that we should push a scope 2166 // then evaluate the first child. However, pushing a scope only to have 2167 // the first check fail (which then pops it) is inefficient. If we can 2168 // determine immediately that the first check (or first several) will 2169 // immediately fail, don't even bother pushing a scope for them. 2170 unsigned FailIndex; 2171 2172 while (1) { 2173 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2174 if (NumToSkip & 128) 2175 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2176 // Found the end of the scope with no match. 2177 if (NumToSkip == 0) { 2178 FailIndex = 0; 2179 break; 2180 } 2181 2182 FailIndex = MatcherIndex+NumToSkip; 2183 2184 unsigned MatcherIndexOfPredicate = MatcherIndex; 2185 (void)MatcherIndexOfPredicate; // silence warning. 2186 2187 // If we can't evaluate this predicate without pushing a scope (e.g. if 2188 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2189 // push the scope and evaluate the full predicate chain. 2190 bool Result; 2191 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2192 Result, *this, RecordedNodes); 2193 if (!Result) 2194 break; 2195 2196 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2197 << "index " << MatcherIndexOfPredicate 2198 << ", continuing at " << FailIndex << "\n"); 2199 ++NumDAGIselRetries; 2200 2201 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2202 // move to the next case. 2203 MatcherIndex = FailIndex; 2204 } 2205 2206 // If the whole scope failed to match, bail. 2207 if (FailIndex == 0) break; 2208 2209 // Push a MatchScope which indicates where to go if the first child fails 2210 // to match. 2211 MatchScope NewEntry; 2212 NewEntry.FailIndex = FailIndex; 2213 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2214 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2215 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2216 NewEntry.InputChain = InputChain; 2217 NewEntry.InputFlag = InputFlag; 2218 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2219 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2220 MatchScopes.push_back(NewEntry); 2221 continue; 2222 } 2223 case OPC_RecordNode: 2224 // Remember this node, it may end up being an operand in the pattern. 2225 RecordedNodes.push_back(N); 2226 continue; 2227 2228 case OPC_RecordChild0: case OPC_RecordChild1: 2229 case OPC_RecordChild2: case OPC_RecordChild3: 2230 case OPC_RecordChild4: case OPC_RecordChild5: 2231 case OPC_RecordChild6: case OPC_RecordChild7: { 2232 unsigned ChildNo = Opcode-OPC_RecordChild0; 2233 if (ChildNo >= N.getNumOperands()) 2234 break; // Match fails if out of range child #. 2235 2236 RecordedNodes.push_back(N->getOperand(ChildNo)); 2237 continue; 2238 } 2239 case OPC_RecordMemRef: 2240 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2241 continue; 2242 2243 case OPC_CaptureFlagInput: 2244 // If the current node has an input flag, capture it in InputFlag. 2245 if (N->getNumOperands() != 0 && 2246 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2247 InputFlag = N->getOperand(N->getNumOperands()-1); 2248 continue; 2249 2250 case OPC_MoveChild: { 2251 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2252 if (ChildNo >= N.getNumOperands()) 2253 break; // Match fails if out of range child #. 2254 N = N.getOperand(ChildNo); 2255 NodeStack.push_back(N); 2256 continue; 2257 } 2258 2259 case OPC_MoveParent: 2260 // Pop the current node off the NodeStack. 2261 NodeStack.pop_back(); 2262 assert(!NodeStack.empty() && "Node stack imbalance!"); 2263 N = NodeStack.back(); 2264 continue; 2265 2266 case OPC_CheckSame: 2267 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2268 continue; 2269 case OPC_CheckPatternPredicate: 2270 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2271 continue; 2272 case OPC_CheckPredicate: 2273 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2274 N.getNode())) 2275 break; 2276 continue; 2277 case OPC_CheckComplexPat: { 2278 unsigned CPNum = MatcherTable[MatcherIndex++]; 2279 unsigned RecNo = MatcherTable[MatcherIndex++]; 2280 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2281 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2282 RecordedNodes)) 2283 break; 2284 continue; 2285 } 2286 case OPC_CheckOpcode: 2287 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2288 continue; 2289 2290 case OPC_CheckType: 2291 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2292 continue; 2293 2294 case OPC_SwitchOpcode: { 2295 unsigned CurNodeOpcode = N.getOpcode(); 2296 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2297 unsigned CaseSize; 2298 while (1) { 2299 // Get the size of this case. 2300 CaseSize = MatcherTable[MatcherIndex++]; 2301 if (CaseSize & 128) 2302 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2303 if (CaseSize == 0) break; 2304 2305 uint16_t Opc = MatcherTable[MatcherIndex++]; 2306 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2307 2308 // If the opcode matches, then we will execute this case. 2309 if (CurNodeOpcode == Opc) 2310 break; 2311 2312 // Otherwise, skip over this case. 2313 MatcherIndex += CaseSize; 2314 } 2315 2316 // If no cases matched, bail out. 2317 if (CaseSize == 0) break; 2318 2319 // Otherwise, execute the case we found. 2320 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2321 << " to " << MatcherIndex << "\n"); 2322 continue; 2323 } 2324 2325 case OPC_SwitchType: { 2326 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2327 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2328 unsigned CaseSize; 2329 while (1) { 2330 // Get the size of this case. 2331 CaseSize = MatcherTable[MatcherIndex++]; 2332 if (CaseSize & 128) 2333 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2334 if (CaseSize == 0) break; 2335 2336 MVT::SimpleValueType CaseVT = 2337 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2338 if (CaseVT == MVT::iPTR) 2339 CaseVT = TLI.getPointerTy().SimpleTy; 2340 2341 // If the VT matches, then we will execute this case. 2342 if (CurNodeVT == CaseVT) 2343 break; 2344 2345 // Otherwise, skip over this case. 2346 MatcherIndex += CaseSize; 2347 } 2348 2349 // If no cases matched, bail out. 2350 if (CaseSize == 0) break; 2351 2352 // Otherwise, execute the case we found. 2353 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2354 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2355 continue; 2356 } 2357 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2358 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2359 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2360 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2361 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2362 Opcode-OPC_CheckChild0Type)) 2363 break; 2364 continue; 2365 case OPC_CheckCondCode: 2366 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2367 continue; 2368 case OPC_CheckValueType: 2369 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2370 continue; 2371 case OPC_CheckInteger: 2372 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2373 continue; 2374 case OPC_CheckAndImm: 2375 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2376 continue; 2377 case OPC_CheckOrImm: 2378 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2379 continue; 2380 2381 case OPC_CheckFoldableChainNode: { 2382 assert(NodeStack.size() != 1 && "No parent node"); 2383 // Verify that all intermediate nodes between the root and this one have 2384 // a single use. 2385 bool HasMultipleUses = false; 2386 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2387 if (!NodeStack[i].hasOneUse()) { 2388 HasMultipleUses = true; 2389 break; 2390 } 2391 if (HasMultipleUses) break; 2392 2393 // Check to see that the target thinks this is profitable to fold and that 2394 // we can fold it without inducing cycles in the graph. 2395 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2396 NodeToMatch) || 2397 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2398 NodeToMatch, true/*We validate our own chains*/)) 2399 break; 2400 2401 continue; 2402 } 2403 case OPC_EmitInteger: { 2404 MVT::SimpleValueType VT = 2405 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2406 int64_t Val = MatcherTable[MatcherIndex++]; 2407 if (Val & 128) 2408 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2409 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2410 continue; 2411 } 2412 case OPC_EmitRegister: { 2413 MVT::SimpleValueType VT = 2414 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2415 unsigned RegNo = MatcherTable[MatcherIndex++]; 2416 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2417 continue; 2418 } 2419 2420 case OPC_EmitConvertToTarget: { 2421 // Convert from IMM/FPIMM to target version. 2422 unsigned RecNo = MatcherTable[MatcherIndex++]; 2423 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2424 SDValue Imm = RecordedNodes[RecNo]; 2425 2426 if (Imm->getOpcode() == ISD::Constant) { 2427 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2428 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2429 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2430 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2431 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2432 } 2433 2434 RecordedNodes.push_back(Imm); 2435 continue; 2436 } 2437 2438 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2439 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2440 // These are space-optimized forms of OPC_EmitMergeInputChains. 2441 assert(InputChain.getNode() == 0 && 2442 "EmitMergeInputChains should be the first chain producing node"); 2443 assert(ChainNodesMatched.empty() && 2444 "Should only have one EmitMergeInputChains per match"); 2445 2446 // Read all of the chained nodes. 2447 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2448 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2449 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2450 2451 // FIXME: What if other value results of the node have uses not matched 2452 // by this pattern? 2453 if (ChainNodesMatched.back() != NodeToMatch && 2454 !RecordedNodes[RecNo].hasOneUse()) { 2455 ChainNodesMatched.clear(); 2456 break; 2457 } 2458 2459 // Merge the input chains if they are not intra-pattern references. 2460 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2461 2462 if (InputChain.getNode() == 0) 2463 break; // Failed to merge. 2464 continue; 2465 } 2466 2467 case OPC_EmitMergeInputChains: { 2468 assert(InputChain.getNode() == 0 && 2469 "EmitMergeInputChains should be the first chain producing node"); 2470 // This node gets a list of nodes we matched in the input that have 2471 // chains. We want to token factor all of the input chains to these nodes 2472 // together. However, if any of the input chains is actually one of the 2473 // nodes matched in this pattern, then we have an intra-match reference. 2474 // Ignore these because the newly token factored chain should not refer to 2475 // the old nodes. 2476 unsigned NumChains = MatcherTable[MatcherIndex++]; 2477 assert(NumChains != 0 && "Can't TF zero chains"); 2478 2479 assert(ChainNodesMatched.empty() && 2480 "Should only have one EmitMergeInputChains per match"); 2481 2482 // Read all of the chained nodes. 2483 for (unsigned i = 0; i != NumChains; ++i) { 2484 unsigned RecNo = MatcherTable[MatcherIndex++]; 2485 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2486 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2487 2488 // FIXME: What if other value results of the node have uses not matched 2489 // by this pattern? 2490 if (ChainNodesMatched.back() != NodeToMatch && 2491 !RecordedNodes[RecNo].hasOneUse()) { 2492 ChainNodesMatched.clear(); 2493 break; 2494 } 2495 } 2496 2497 // If the inner loop broke out, the match fails. 2498 if (ChainNodesMatched.empty()) 2499 break; 2500 2501 // Merge the input chains if they are not intra-pattern references. 2502 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2503 2504 if (InputChain.getNode() == 0) 2505 break; // Failed to merge. 2506 2507 continue; 2508 } 2509 2510 case OPC_EmitCopyToReg: { 2511 unsigned RecNo = MatcherTable[MatcherIndex++]; 2512 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2513 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2514 2515 if (InputChain.getNode() == 0) 2516 InputChain = CurDAG->getEntryNode(); 2517 2518 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2519 DestPhysReg, RecordedNodes[RecNo], 2520 InputFlag); 2521 2522 InputFlag = InputChain.getValue(1); 2523 continue; 2524 } 2525 2526 case OPC_EmitNodeXForm: { 2527 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2528 unsigned RecNo = MatcherTable[MatcherIndex++]; 2529 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2530 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2531 continue; 2532 } 2533 2534 case OPC_EmitNode: 2535 case OPC_MorphNodeTo: { 2536 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2537 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2538 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2539 // Get the result VT list. 2540 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2541 SmallVector<EVT, 4> VTs; 2542 for (unsigned i = 0; i != NumVTs; ++i) { 2543 MVT::SimpleValueType VT = 2544 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2545 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2546 VTs.push_back(VT); 2547 } 2548 2549 if (EmitNodeInfo & OPFL_Chain) 2550 VTs.push_back(MVT::Other); 2551 if (EmitNodeInfo & OPFL_FlagOutput) 2552 VTs.push_back(MVT::Flag); 2553 2554 // This is hot code, so optimize the two most common cases of 1 and 2 2555 // results. 2556 SDVTList VTList; 2557 if (VTs.size() == 1) 2558 VTList = CurDAG->getVTList(VTs[0]); 2559 else if (VTs.size() == 2) 2560 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2561 else 2562 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2563 2564 // Get the operand list. 2565 unsigned NumOps = MatcherTable[MatcherIndex++]; 2566 SmallVector<SDValue, 8> Ops; 2567 for (unsigned i = 0; i != NumOps; ++i) { 2568 unsigned RecNo = MatcherTable[MatcherIndex++]; 2569 if (RecNo & 128) 2570 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2571 2572 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2573 Ops.push_back(RecordedNodes[RecNo]); 2574 } 2575 2576 // If there are variadic operands to add, handle them now. 2577 if (EmitNodeInfo & OPFL_VariadicInfo) { 2578 // Determine the start index to copy from. 2579 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2580 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2581 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2582 "Invalid variadic node"); 2583 // Copy all of the variadic operands, not including a potential flag 2584 // input. 2585 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2586 i != e; ++i) { 2587 SDValue V = NodeToMatch->getOperand(i); 2588 if (V.getValueType() == MVT::Flag) break; 2589 Ops.push_back(V); 2590 } 2591 } 2592 2593 // If this has chain/flag inputs, add them. 2594 if (EmitNodeInfo & OPFL_Chain) 2595 Ops.push_back(InputChain); 2596 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2597 Ops.push_back(InputFlag); 2598 2599 // Create the node. 2600 SDNode *Res = 0; 2601 if (Opcode != OPC_MorphNodeTo) { 2602 // If this is a normal EmitNode command, just create the new node and 2603 // add the results to the RecordedNodes list. 2604 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2605 VTList, Ops.data(), Ops.size()); 2606 2607 // Add all the non-flag/non-chain results to the RecordedNodes list. 2608 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2609 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2610 RecordedNodes.push_back(SDValue(Res, i)); 2611 } 2612 2613 } else { 2614 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2615 EmitNodeInfo); 2616 } 2617 2618 // If the node had chain/flag results, update our notion of the current 2619 // chain and flag. 2620 if (EmitNodeInfo & OPFL_FlagOutput) { 2621 InputFlag = SDValue(Res, VTs.size()-1); 2622 if (EmitNodeInfo & OPFL_Chain) 2623 InputChain = SDValue(Res, VTs.size()-2); 2624 } else if (EmitNodeInfo & OPFL_Chain) 2625 InputChain = SDValue(Res, VTs.size()-1); 2626 2627 // If the OPFL_MemRefs flag is set on this node, slap all of the 2628 // accumulated memrefs onto it. 2629 // 2630 // FIXME: This is vastly incorrect for patterns with multiple outputs 2631 // instructions that access memory and for ComplexPatterns that match 2632 // loads. 2633 if (EmitNodeInfo & OPFL_MemRefs) { 2634 MachineSDNode::mmo_iterator MemRefs = 2635 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2636 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2637 cast<MachineSDNode>(Res) 2638 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2639 } 2640 2641 DEBUG(errs() << " " 2642 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2643 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2644 2645 // If this was a MorphNodeTo then we're completely done! 2646 if (Opcode == OPC_MorphNodeTo) { 2647 // Update chain and flag uses. 2648 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2649 InputFlag, FlagResultNodesMatched, true); 2650 return Res; 2651 } 2652 2653 continue; 2654 } 2655 2656 case OPC_MarkFlagResults: { 2657 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2658 2659 // Read and remember all the flag-result nodes. 2660 for (unsigned i = 0; i != NumNodes; ++i) { 2661 unsigned RecNo = MatcherTable[MatcherIndex++]; 2662 if (RecNo & 128) 2663 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2664 2665 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2666 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2667 } 2668 continue; 2669 } 2670 2671 case OPC_CompleteMatch: { 2672 // The match has been completed, and any new nodes (if any) have been 2673 // created. Patch up references to the matched dag to use the newly 2674 // created nodes. 2675 unsigned NumResults = MatcherTable[MatcherIndex++]; 2676 2677 for (unsigned i = 0; i != NumResults; ++i) { 2678 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2679 if (ResSlot & 128) 2680 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2681 2682 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2683 SDValue Res = RecordedNodes[ResSlot]; 2684 2685 assert(i < NodeToMatch->getNumValues() && 2686 NodeToMatch->getValueType(i) != MVT::Other && 2687 NodeToMatch->getValueType(i) != MVT::Flag && 2688 "Invalid number of results to complete!"); 2689 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2690 NodeToMatch->getValueType(i) == MVT::iPTR || 2691 Res.getValueType() == MVT::iPTR || 2692 NodeToMatch->getValueType(i).getSizeInBits() == 2693 Res.getValueType().getSizeInBits()) && 2694 "invalid replacement"); 2695 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2696 } 2697 2698 // If the root node defines a flag, add it to the flag nodes to update 2699 // list. 2700 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2701 FlagResultNodesMatched.push_back(NodeToMatch); 2702 2703 // Update chain and flag uses. 2704 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2705 InputFlag, FlagResultNodesMatched, false); 2706 2707 assert(NodeToMatch->use_empty() && 2708 "Didn't replace all uses of the node?"); 2709 2710 // FIXME: We just return here, which interacts correctly with SelectRoot 2711 // above. We should fix this to not return an SDNode* anymore. 2712 return 0; 2713 } 2714 } 2715 2716 // If the code reached this point, then the match failed. See if there is 2717 // another child to try in the current 'Scope', otherwise pop it until we 2718 // find a case to check. 2719 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2720 ++NumDAGIselRetries; 2721 while (1) { 2722 if (MatchScopes.empty()) { 2723 CannotYetSelect(NodeToMatch); 2724 return 0; 2725 } 2726 2727 // Restore the interpreter state back to the point where the scope was 2728 // formed. 2729 MatchScope &LastScope = MatchScopes.back(); 2730 RecordedNodes.resize(LastScope.NumRecordedNodes); 2731 NodeStack.clear(); 2732 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2733 N = NodeStack.back(); 2734 2735 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2736 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2737 MatcherIndex = LastScope.FailIndex; 2738 2739 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2740 2741 InputChain = LastScope.InputChain; 2742 InputFlag = LastScope.InputFlag; 2743 if (!LastScope.HasChainNodesMatched) 2744 ChainNodesMatched.clear(); 2745 if (!LastScope.HasFlagResultNodesMatched) 2746 FlagResultNodesMatched.clear(); 2747 2748 // Check to see what the offset is at the new MatcherIndex. If it is zero 2749 // we have reached the end of this scope, otherwise we have another child 2750 // in the current scope to try. 2751 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2752 if (NumToSkip & 128) 2753 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2754 2755 // If we have another child in this scope to match, update FailIndex and 2756 // try it. 2757 if (NumToSkip != 0) { 2758 LastScope.FailIndex = MatcherIndex+NumToSkip; 2759 break; 2760 } 2761 2762 // End of this scope, pop it and try the next child in the containing 2763 // scope. 2764 MatchScopes.pop_back(); 2765 } 2766 } 2767} 2768 2769 2770 2771void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2772 std::string msg; 2773 raw_string_ostream Msg(msg); 2774 Msg << "Cannot yet select: "; 2775 2776 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2777 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2778 N->getOpcode() != ISD::INTRINSIC_VOID) { 2779 N->printrFull(Msg, CurDAG); 2780 } else { 2781 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2782 unsigned iid = 2783 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2784 if (iid < Intrinsic::num_intrinsics) 2785 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2786 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2787 Msg << "target intrinsic %" << TII->getName(iid); 2788 else 2789 Msg << "unknown intrinsic #" << iid; 2790 } 2791 llvm_report_error(Msg.str()); 2792} 2793 2794char SelectionDAGISel::ID = 0; 2795