SelectionDAGISel.cpp revision 139f50a1a8d985bd950d88cef54a7ee560de9cb9
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "ScheduleDAGSDNodes.h" 17#include "SelectionDAGBuilder.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/Statistic.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/BranchProbabilityInfo.h" 22#include "llvm/Analysis/TargetTransformInfo.h" 23#include "llvm/CodeGen/FastISel.h" 24#include "llvm/CodeGen/FunctionLoweringInfo.h" 25#include "llvm/CodeGen/GCMetadata.h" 26#include "llvm/CodeGen/GCStrategy.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/MachineModuleInfo.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 33#include "llvm/CodeGen/SchedulerRegistry.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/DebugInfo.h" 36#include "llvm/IR/Constants.h" 37#include "llvm/IR/Function.h" 38#include "llvm/IR/InlineAsm.h" 39#include "llvm/IR/Instructions.h" 40#include "llvm/IR/IntrinsicInst.h" 41#include "llvm/IR/Intrinsics.h" 42#include "llvm/IR/LLVMContext.h" 43#include "llvm/IR/Module.h" 44#include "llvm/Support/Compiler.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/Timer.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLibraryInfo.h" 52#include "llvm/Target/TargetLowering.h" 53#include "llvm/Target/TargetMachine.h" 54#include "llvm/Target/TargetOptions.h" 55#include "llvm/Target/TargetRegisterInfo.h" 56#include "llvm/Target/TargetSubtargetInfo.h" 57#include "llvm/Transforms/Utils/BasicBlockUtils.h" 58#include <algorithm> 59using namespace llvm; 60 61STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 62STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 63 64#ifndef NDEBUG 65STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 66STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 67STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 68 69static cl::opt<bool> 70EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 71 cl::desc("Enable extra verbose messages in the \"fast\" " 72 "instruction selector")); 73 // Terminators 74STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 75STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 76STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 77STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 78STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 79STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 80STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 81 82 // Standard binary operators... 83STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 84STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 85STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 86STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 87STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 88STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 89STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 90STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 91STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 92STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 93STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 94STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 95 96 // Logical operators... 97STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 98STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 99STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 100 101 // Memory instructions... 102STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 103STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 104STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 105STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 106STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 107STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 108STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 109 110 // Convert instructions... 111STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 112STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 113STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 114STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 115STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 116STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 117STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 118STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 119STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 120STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 121STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 122STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 123 124 // Other instructions... 125STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 126STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 127STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 128STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 129STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 130STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 131STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 132STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 133STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 134STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 135STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 136STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 137STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 138STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 139STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 140#endif 141 142static cl::opt<bool> 143EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 144 cl::desc("Enable verbose messages in the \"fast\" " 145 "instruction selector")); 146static cl::opt<bool> 147EnableFastISelAbort("fast-isel-abort", cl::Hidden, 148 cl::desc("Enable abort calls when \"fast\" instruction selection " 149 "fails to lower an instruction")); 150static cl::opt<bool> 151EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden, 152 cl::desc("Enable abort calls when \"fast\" instruction selection " 153 "fails to lower a formal argument")); 154 155static cl::opt<bool> 156UseMBPI("use-mbpi", 157 cl::desc("use Machine Branch Probability Info"), 158 cl::init(true), cl::Hidden); 159 160#ifndef NDEBUG 161static cl::opt<bool> 162ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 163 cl::desc("Pop up a window to show dags before the first " 164 "dag combine pass")); 165static cl::opt<bool> 166ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 167 cl::desc("Pop up a window to show dags before legalize types")); 168static cl::opt<bool> 169ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 170 cl::desc("Pop up a window to show dags before legalize")); 171static cl::opt<bool> 172ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 173 cl::desc("Pop up a window to show dags before the second " 174 "dag combine pass")); 175static cl::opt<bool> 176ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 177 cl::desc("Pop up a window to show dags before the post legalize types" 178 " dag combine pass")); 179static cl::opt<bool> 180ViewISelDAGs("view-isel-dags", cl::Hidden, 181 cl::desc("Pop up a window to show isel dags as they are selected")); 182static cl::opt<bool> 183ViewSchedDAGs("view-sched-dags", cl::Hidden, 184 cl::desc("Pop up a window to show sched dags as they are processed")); 185static cl::opt<bool> 186ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 187 cl::desc("Pop up a window to show SUnit dags after they are processed")); 188#else 189static const bool ViewDAGCombine1 = false, 190 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 191 ViewDAGCombine2 = false, 192 ViewDAGCombineLT = false, 193 ViewISelDAGs = false, ViewSchedDAGs = false, 194 ViewSUnitDAGs = false; 195#endif 196 197//===---------------------------------------------------------------------===// 198/// 199/// RegisterScheduler class - Track the registration of instruction schedulers. 200/// 201//===---------------------------------------------------------------------===// 202MachinePassRegistry RegisterScheduler::Registry; 203 204//===---------------------------------------------------------------------===// 205/// 206/// ISHeuristic command line option for instruction schedulers. 207/// 208//===---------------------------------------------------------------------===// 209static cl::opt<RegisterScheduler::FunctionPassCtor, false, 210 RegisterPassParser<RegisterScheduler> > 211ISHeuristic("pre-RA-sched", 212 cl::init(&createDefaultScheduler), 213 cl::desc("Instruction schedulers available (before register" 214 " allocation):")); 215 216static RegisterScheduler 217defaultListDAGScheduler("default", "Best scheduler for the target", 218 createDefaultScheduler); 219 220namespace llvm { 221 //===--------------------------------------------------------------------===// 222 /// createDefaultScheduler - This creates an instruction scheduler appropriate 223 /// for the target. 224 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 225 CodeGenOpt::Level OptLevel) { 226 const TargetLowering &TLI = IS->getTargetLowering(); 227 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 228 229 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() || 230 TLI.getSchedulingPreference() == Sched::Source) 231 return createSourceListDAGScheduler(IS, OptLevel); 232 if (TLI.getSchedulingPreference() == Sched::RegPressure) 233 return createBURRListDAGScheduler(IS, OptLevel); 234 if (TLI.getSchedulingPreference() == Sched::Hybrid) 235 return createHybridListDAGScheduler(IS, OptLevel); 236 if (TLI.getSchedulingPreference() == Sched::VLIW) 237 return createVLIWDAGScheduler(IS, OptLevel); 238 assert(TLI.getSchedulingPreference() == Sched::ILP && 239 "Unknown sched type!"); 240 return createILPListDAGScheduler(IS, OptLevel); 241 } 242} 243 244// EmitInstrWithCustomInserter - This method should be implemented by targets 245// that mark instructions with the 'usesCustomInserter' flag. These 246// instructions are special in various ways, which require special support to 247// insert. The specified MachineInstr is created but not inserted into any 248// basic blocks, and this method is called to expand it into a sequence of 249// instructions, potentially also creating new basic blocks and control flow. 250// When new basic blocks are inserted and the edges from MBB to its successors 251// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 252// DenseMap. 253MachineBasicBlock * 254TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 255 MachineBasicBlock *MBB) const { 256#ifndef NDEBUG 257 dbgs() << "If a target marks an instruction with " 258 "'usesCustomInserter', it must implement " 259 "TargetLowering::EmitInstrWithCustomInserter!"; 260#endif 261 llvm_unreachable(0); 262} 263 264void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 265 SDNode *Node) const { 266 assert(!MI->hasPostISelHook() && 267 "If a target marks an instruction with 'hasPostISelHook', " 268 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 269} 270 271//===----------------------------------------------------------------------===// 272// SelectionDAGISel code 273//===----------------------------------------------------------------------===// 274 275SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, 276 CodeGenOpt::Level OL) : 277 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 278 FuncInfo(new FunctionLoweringInfo(TLI)), 279 CurDAG(new SelectionDAG(tm, OL)), 280 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 281 GFI(), 282 OptLevel(OL), 283 DAGSize(0) { 284 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 285 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 286 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 287 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 288 } 289 290SelectionDAGISel::~SelectionDAGISel() { 291 delete SDB; 292 delete CurDAG; 293 delete FuncInfo; 294} 295 296void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 297 AU.addRequired<AliasAnalysis>(); 298 AU.addPreserved<AliasAnalysis>(); 299 AU.addRequired<GCModuleInfo>(); 300 AU.addPreserved<GCModuleInfo>(); 301 AU.addRequired<TargetLibraryInfo>(); 302 if (UseMBPI && OptLevel != CodeGenOpt::None) 303 AU.addRequired<BranchProbabilityInfo>(); 304 MachineFunctionPass::getAnalysisUsage(AU); 305} 306 307/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 308/// may trap on it. In this case we have to split the edge so that the path 309/// through the predecessor block that doesn't go to the phi block doesn't 310/// execute the possibly trapping instruction. 311/// 312/// This is required for correctness, so it must be done at -O0. 313/// 314static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 315 // Loop for blocks with phi nodes. 316 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 317 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 318 if (PN == 0) continue; 319 320 ReprocessBlock: 321 // For each block with a PHI node, check to see if any of the input values 322 // are potentially trapping constant expressions. Constant expressions are 323 // the only potentially trapping value that can occur as the argument to a 324 // PHI. 325 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 326 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 327 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 328 if (CE == 0 || !CE->canTrap()) continue; 329 330 // The only case we have to worry about is when the edge is critical. 331 // Since this block has a PHI Node, we assume it has multiple input 332 // edges: check to see if the pred has multiple successors. 333 BasicBlock *Pred = PN->getIncomingBlock(i); 334 if (Pred->getTerminator()->getNumSuccessors() == 1) 335 continue; 336 337 // Okay, we have to split this edge. 338 SplitCriticalEdge(Pred->getTerminator(), 339 GetSuccessorNumber(Pred, BB), SDISel, true); 340 goto ReprocessBlock; 341 } 342 } 343} 344 345bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 346 // Do some sanity-checking on the command-line options. 347 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 348 "-fast-isel-verbose requires -fast-isel"); 349 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 350 "-fast-isel-abort requires -fast-isel"); 351 352 const Function &Fn = *mf.getFunction(); 353 const TargetInstrInfo &TII = *TM.getInstrInfo(); 354 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 355 356 MF = &mf; 357 RegInfo = &MF->getRegInfo(); 358 AA = &getAnalysis<AliasAnalysis>(); 359 LibInfo = &getAnalysis<TargetLibraryInfo>(); 360 TTI = getAnalysisIfAvailable<TargetTransformInfo>(); 361 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 362 363 TargetSubtargetInfo &ST = 364 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 365 ST.resetSubtargetFeatures(MF); 366 367 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 368 369 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 370 371 CurDAG->init(*MF, TTI); 372 FuncInfo->set(Fn, *MF); 373 374 if (UseMBPI && OptLevel != CodeGenOpt::None) 375 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 376 else 377 FuncInfo->BPI = 0; 378 379 SDB->init(GFI, *AA, LibInfo); 380 381 MF->setHasMSInlineAsm(false); 382 SelectAllBasicBlocks(Fn); 383 384 // If the first basic block in the function has live ins that need to be 385 // copied into vregs, emit the copies into the top of the block before 386 // emitting the code for the block. 387 MachineBasicBlock *EntryMBB = MF->begin(); 388 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 389 390 DenseMap<unsigned, unsigned> LiveInMap; 391 if (!FuncInfo->ArgDbgValues.empty()) 392 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 393 E = RegInfo->livein_end(); LI != E; ++LI) 394 if (LI->second) 395 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 396 397 // Insert DBG_VALUE instructions for function arguments to the entry block. 398 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 399 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 400 unsigned Reg = MI->getOperand(0).getReg(); 401 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 402 EntryMBB->insert(EntryMBB->begin(), MI); 403 else { 404 MachineInstr *Def = RegInfo->getVRegDef(Reg); 405 MachineBasicBlock::iterator InsertPos = Def; 406 // FIXME: VR def may not be in entry block. 407 Def->getParent()->insert(llvm::next(InsertPos), MI); 408 } 409 410 // If Reg is live-in then update debug info to track its copy in a vreg. 411 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 412 if (LDI != LiveInMap.end()) { 413 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 414 MachineBasicBlock::iterator InsertPos = Def; 415 const MDNode *Variable = 416 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 417 unsigned Offset = MI->getOperand(1).getImm(); 418 // Def is never a terminator here, so it is ok to increment InsertPos. 419 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 420 TII.get(TargetOpcode::DBG_VALUE)) 421 .addReg(LDI->second, RegState::Debug) 422 .addImm(Offset).addMetadata(Variable); 423 424 // If this vreg is directly copied into an exported register then 425 // that COPY instructions also need DBG_VALUE, if it is the only 426 // user of LDI->second. 427 MachineInstr *CopyUseMI = NULL; 428 for (MachineRegisterInfo::use_iterator 429 UI = RegInfo->use_begin(LDI->second); 430 MachineInstr *UseMI = UI.skipInstruction();) { 431 if (UseMI->isDebugValue()) continue; 432 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 433 CopyUseMI = UseMI; continue; 434 } 435 // Otherwise this is another use or second copy use. 436 CopyUseMI = NULL; break; 437 } 438 if (CopyUseMI) { 439 MachineInstr *NewMI = 440 BuildMI(*MF, CopyUseMI->getDebugLoc(), 441 TII.get(TargetOpcode::DBG_VALUE)) 442 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 443 .addImm(Offset).addMetadata(Variable); 444 MachineBasicBlock::iterator Pos = CopyUseMI; 445 EntryMBB->insertAfter(Pos, NewMI); 446 } 447 } 448 } 449 450 // Determine if there are any calls in this machine function. 451 MachineFrameInfo *MFI = MF->getFrameInfo(); 452 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E; 453 ++I) { 454 455 if (MFI->hasCalls() && MF->hasMSInlineAsm()) 456 break; 457 458 const MachineBasicBlock *MBB = I; 459 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end(); 460 II != IE; ++II) { 461 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 462 if ((MCID.isCall() && !MCID.isReturn()) || 463 II->isStackAligningInlineAsm()) { 464 MFI->setHasCalls(true); 465 } 466 if (II->isMSInlineAsm()) { 467 MF->setHasMSInlineAsm(true); 468 } 469 } 470 } 471 472 // Determine if there is a call to setjmp in the machine function. 473 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 474 475 // Replace forward-declared registers with the registers containing 476 // the desired value. 477 MachineRegisterInfo &MRI = MF->getRegInfo(); 478 for (DenseMap<unsigned, unsigned>::iterator 479 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 480 I != E; ++I) { 481 unsigned From = I->first; 482 unsigned To = I->second; 483 // If To is also scheduled to be replaced, find what its ultimate 484 // replacement is. 485 for (;;) { 486 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 487 if (J == E) break; 488 To = J->second; 489 } 490 // Replace it. 491 MRI.replaceRegWith(From, To); 492 } 493 494 // Freeze the set of reserved registers now that MachineFrameInfo has been 495 // set up. All the information required by getReservedRegs() should be 496 // available now. 497 MRI.freezeReservedRegs(*MF); 498 499 // Release function-specific state. SDB and CurDAG are already cleared 500 // at this point. 501 FuncInfo->clear(); 502 503 return true; 504} 505 506void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 507 BasicBlock::const_iterator End, 508 bool &HadTailCall) { 509 // Lower all of the non-terminator instructions. If a call is emitted 510 // as a tail call, cease emitting nodes for this block. Terminators 511 // are handled below. 512 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 513 SDB->visit(*I); 514 515 // Make sure the root of the DAG is up-to-date. 516 CurDAG->setRoot(SDB->getControlRoot()); 517 HadTailCall = SDB->HasTailCall; 518 SDB->clear(); 519 520 // Final step, emit the lowered DAG as machine code. 521 CodeGenAndEmitDAG(); 522} 523 524void SelectionDAGISel::ComputeLiveOutVRegInfo() { 525 SmallPtrSet<SDNode*, 128> VisitedNodes; 526 SmallVector<SDNode*, 128> Worklist; 527 528 Worklist.push_back(CurDAG->getRoot().getNode()); 529 530 APInt KnownZero; 531 APInt KnownOne; 532 533 do { 534 SDNode *N = Worklist.pop_back_val(); 535 536 // If we've already seen this node, ignore it. 537 if (!VisitedNodes.insert(N)) 538 continue; 539 540 // Otherwise, add all chain operands to the worklist. 541 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 542 if (N->getOperand(i).getValueType() == MVT::Other) 543 Worklist.push_back(N->getOperand(i).getNode()); 544 545 // If this is a CopyToReg with a vreg dest, process it. 546 if (N->getOpcode() != ISD::CopyToReg) 547 continue; 548 549 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 550 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 551 continue; 552 553 // Ignore non-scalar or non-integer values. 554 SDValue Src = N->getOperand(2); 555 EVT SrcVT = Src.getValueType(); 556 if (!SrcVT.isInteger() || SrcVT.isVector()) 557 continue; 558 559 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 560 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 561 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 562 } while (!Worklist.empty()); 563} 564 565void SelectionDAGISel::CodeGenAndEmitDAG() { 566 std::string GroupName; 567 if (TimePassesIsEnabled) 568 GroupName = "Instruction Selection and Scheduling"; 569 std::string BlockName; 570 int BlockNumber = -1; 571 (void)BlockNumber; 572#ifdef NDEBUG 573 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 574 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 575 ViewSUnitDAGs) 576#endif 577 { 578 BlockNumber = FuncInfo->MBB->getNumber(); 579 BlockName = MF->getName().str() + ":" + 580 FuncInfo->MBB->getBasicBlock()->getName().str(); 581 } 582 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 583 << " '" << BlockName << "'\n"; CurDAG->dump()); 584 585 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 586 587 // Run the DAG combiner in pre-legalize mode. 588 { 589 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 590 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 591 } 592 593 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 594 << " '" << BlockName << "'\n"; CurDAG->dump()); 595 596 // Second step, hack on the DAG until it only uses operations and types that 597 // the target supports. 598 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 599 BlockName); 600 601 bool Changed; 602 { 603 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 604 Changed = CurDAG->LegalizeTypes(); 605 } 606 607 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 608 << " '" << BlockName << "'\n"; CurDAG->dump()); 609 610 if (Changed) { 611 if (ViewDAGCombineLT) 612 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 613 614 // Run the DAG combiner in post-type-legalize mode. 615 { 616 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 617 TimePassesIsEnabled); 618 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 619 } 620 621 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 622 << " '" << BlockName << "'\n"; CurDAG->dump()); 623 } 624 625 { 626 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 627 Changed = CurDAG->LegalizeVectors(); 628 } 629 630 if (Changed) { 631 { 632 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 633 CurDAG->LegalizeTypes(); 634 } 635 636 if (ViewDAGCombineLT) 637 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 638 639 // Run the DAG combiner in post-type-legalize mode. 640 { 641 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 642 TimePassesIsEnabled); 643 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 644 } 645 646 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 647 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 648 } 649 650 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 651 652 { 653 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 654 CurDAG->Legalize(); 655 } 656 657 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 658 << " '" << BlockName << "'\n"; CurDAG->dump()); 659 660 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 661 662 // Run the DAG combiner in post-legalize mode. 663 { 664 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 665 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 666 } 667 668 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 669 << " '" << BlockName << "'\n"; CurDAG->dump()); 670 671 if (OptLevel != CodeGenOpt::None) 672 ComputeLiveOutVRegInfo(); 673 674 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 675 676 // Third, instruction select all of the operations to machine code, adding the 677 // code to the MachineBasicBlock. 678 { 679 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 680 DoInstructionSelection(); 681 } 682 683 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 684 << " '" << BlockName << "'\n"; CurDAG->dump()); 685 686 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 687 688 // Schedule machine code. 689 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 690 { 691 NamedRegionTimer T("Instruction Scheduling", GroupName, 692 TimePassesIsEnabled); 693 Scheduler->Run(CurDAG, FuncInfo->MBB); 694 } 695 696 if (ViewSUnitDAGs) Scheduler->viewGraph(); 697 698 // Emit machine code to BB. This can change 'BB' to the last block being 699 // inserted into. 700 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 701 { 702 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 703 704 // FuncInfo->InsertPt is passed by reference and set to the end of the 705 // scheduled instructions. 706 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 707 } 708 709 // If the block was split, make sure we update any references that are used to 710 // update PHI nodes later on. 711 if (FirstMBB != LastMBB) 712 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 713 714 // Free the scheduler state. 715 { 716 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 717 TimePassesIsEnabled); 718 delete Scheduler; 719 } 720 721 // Free the SelectionDAG state, now that we're finished with it. 722 CurDAG->clear(); 723} 724 725namespace { 726/// ISelUpdater - helper class to handle updates of the instruction selection 727/// graph. 728class ISelUpdater : public SelectionDAG::DAGUpdateListener { 729 SelectionDAG::allnodes_iterator &ISelPosition; 730public: 731 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 732 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 733 734 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 735 /// deleted is the current ISelPosition node, update ISelPosition. 736 /// 737 virtual void NodeDeleted(SDNode *N, SDNode *E) { 738 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 739 ++ISelPosition; 740 } 741}; 742} // end anonymous namespace 743 744void SelectionDAGISel::DoInstructionSelection() { 745 DEBUG(errs() << "===== Instruction selection begins: BB#" 746 << FuncInfo->MBB->getNumber() 747 << " '" << FuncInfo->MBB->getName() << "'\n"); 748 749 PreprocessISelDAG(); 750 751 // Select target instructions for the DAG. 752 { 753 // Number all nodes with a topological order and set DAGSize. 754 DAGSize = CurDAG->AssignTopologicalOrder(); 755 756 // Create a dummy node (which is not added to allnodes), that adds 757 // a reference to the root node, preventing it from being deleted, 758 // and tracking any changes of the root. 759 HandleSDNode Dummy(CurDAG->getRoot()); 760 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 761 ++ISelPosition; 762 763 // Make sure that ISelPosition gets properly updated when nodes are deleted 764 // in calls made from this function. 765 ISelUpdater ISU(*CurDAG, ISelPosition); 766 767 // The AllNodes list is now topological-sorted. Visit the 768 // nodes by starting at the end of the list (the root of the 769 // graph) and preceding back toward the beginning (the entry 770 // node). 771 while (ISelPosition != CurDAG->allnodes_begin()) { 772 SDNode *Node = --ISelPosition; 773 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 774 // but there are currently some corner cases that it misses. Also, this 775 // makes it theoretically possible to disable the DAGCombiner. 776 if (Node->use_empty()) 777 continue; 778 779 SDNode *ResNode = Select(Node); 780 781 // FIXME: This is pretty gross. 'Select' should be changed to not return 782 // anything at all and this code should be nuked with a tactical strike. 783 784 // If node should not be replaced, continue with the next one. 785 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 786 continue; 787 // Replace node. 788 if (ResNode) 789 ReplaceUses(Node, ResNode); 790 791 // If after the replacement this node is not used any more, 792 // remove this dead node. 793 if (Node->use_empty()) // Don't delete EntryToken, etc. 794 CurDAG->RemoveDeadNode(Node); 795 } 796 797 CurDAG->setRoot(Dummy.getValue()); 798 } 799 800 DEBUG(errs() << "===== Instruction selection ends:\n"); 801 802 PostprocessISelDAG(); 803} 804 805/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 806/// do other setup for EH landing-pad blocks. 807void SelectionDAGISel::PrepareEHLandingPad() { 808 MachineBasicBlock *MBB = FuncInfo->MBB; 809 810 // Add a label to mark the beginning of the landing pad. Deletion of the 811 // landing pad can thus be detected via the MachineModuleInfo. 812 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 813 814 // Assign the call site to the landing pad's begin label. 815 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 816 817 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 818 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 819 .addSym(Label); 820 821 // Mark exception register as live in. 822 unsigned Reg = TLI.getExceptionPointerRegister(); 823 if (Reg) MBB->addLiveIn(Reg); 824 825 // Mark exception selector register as live in. 826 Reg = TLI.getExceptionSelectorRegister(); 827 if (Reg) MBB->addLiveIn(Reg); 828} 829 830/// TryToFoldFastISelLoad - We're checking to see if we can fold the specified 831/// load into the specified FoldInst. Note that we could have a sequence where 832/// multiple LLVM IR instructions are folded into the same machineinstr. For 833/// example we could have: 834/// A: x = load i32 *P 835/// B: y = icmp A, 42 836/// C: br y, ... 837/// 838/// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and 839/// any other folded instructions) because it is between A and C. 840/// 841/// If we succeed in folding the load into the operation, return true. 842/// 843bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI, 844 const Instruction *FoldInst, 845 FastISel *FastIS) { 846 // We know that the load has a single use, but don't know what it is. If it 847 // isn't one of the folded instructions, then we can't succeed here. Handle 848 // this by scanning the single-use users of the load until we get to FoldInst. 849 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs. 850 851 const Instruction *TheUser = LI->use_back(); 852 while (TheUser != FoldInst && // Scan up until we find FoldInst. 853 // Stay in the right block. 854 TheUser->getParent() == FoldInst->getParent() && 855 --MaxUsers) { // Don't scan too far. 856 // If there are multiple or no uses of this instruction, then bail out. 857 if (!TheUser->hasOneUse()) 858 return false; 859 860 TheUser = TheUser->use_back(); 861 } 862 863 // If we didn't find the fold instruction, then we failed to collapse the 864 // sequence. 865 if (TheUser != FoldInst) 866 return false; 867 868 // Don't try to fold volatile loads. Target has to deal with alignment 869 // constraints. 870 if (LI->isVolatile()) return false; 871 872 // Figure out which vreg this is going into. If there is no assigned vreg yet 873 // then there actually was no reference to it. Perhaps the load is referenced 874 // by a dead instruction. 875 unsigned LoadReg = FastIS->getRegForValue(LI); 876 if (LoadReg == 0) 877 return false; 878 879 // Check to see what the uses of this vreg are. If it has no uses, or more 880 // than one use (at the machine instr level) then we can't fold it. 881 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg); 882 if (RI == RegInfo->reg_end()) 883 return false; 884 885 // See if there is exactly one use of the vreg. If there are multiple uses, 886 // then the instruction got lowered to multiple machine instructions or the 887 // use of the loaded value ended up being multiple operands of the result, in 888 // either case, we can't fold this. 889 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI; 890 if (PostRI != RegInfo->reg_end()) 891 return false; 892 893 assert(RI.getOperand().isUse() && 894 "The only use of the vreg must be a use, we haven't emitted the def!"); 895 896 MachineInstr *User = &*RI; 897 898 // Set the insertion point properly. Folding the load can cause generation of 899 // other random instructions (like sign extends) for addressing modes, make 900 // sure they get inserted in a logical place before the new instruction. 901 FuncInfo->InsertPt = User; 902 FuncInfo->MBB = User->getParent(); 903 904 // Ask the target to try folding the load. 905 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI); 906} 907 908/// isFoldedOrDeadInstruction - Return true if the specified instruction is 909/// side-effect free and is either dead or folded into a generated instruction. 910/// Return false if it needs to be emitted. 911static bool isFoldedOrDeadInstruction(const Instruction *I, 912 FunctionLoweringInfo *FuncInfo) { 913 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 914 !isa<TerminatorInst>(I) && // Terminators aren't folded. 915 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 916 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 917 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 918} 919 920#ifndef NDEBUG 921// Collect per Instruction statistics for fast-isel misses. Only those 922// instructions that cause the bail are accounted for. It does not account for 923// instructions higher in the block. Thus, summing the per instructions stats 924// will not add up to what is reported by NumFastIselFailures. 925static void collectFailStats(const Instruction *I) { 926 switch (I->getOpcode()) { 927 default: assert (0 && "<Invalid operator> "); 928 929 // Terminators 930 case Instruction::Ret: NumFastIselFailRet++; return; 931 case Instruction::Br: NumFastIselFailBr++; return; 932 case Instruction::Switch: NumFastIselFailSwitch++; return; 933 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 934 case Instruction::Invoke: NumFastIselFailInvoke++; return; 935 case Instruction::Resume: NumFastIselFailResume++; return; 936 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 937 938 // Standard binary operators... 939 case Instruction::Add: NumFastIselFailAdd++; return; 940 case Instruction::FAdd: NumFastIselFailFAdd++; return; 941 case Instruction::Sub: NumFastIselFailSub++; return; 942 case Instruction::FSub: NumFastIselFailFSub++; return; 943 case Instruction::Mul: NumFastIselFailMul++; return; 944 case Instruction::FMul: NumFastIselFailFMul++; return; 945 case Instruction::UDiv: NumFastIselFailUDiv++; return; 946 case Instruction::SDiv: NumFastIselFailSDiv++; return; 947 case Instruction::FDiv: NumFastIselFailFDiv++; return; 948 case Instruction::URem: NumFastIselFailURem++; return; 949 case Instruction::SRem: NumFastIselFailSRem++; return; 950 case Instruction::FRem: NumFastIselFailFRem++; return; 951 952 // Logical operators... 953 case Instruction::And: NumFastIselFailAnd++; return; 954 case Instruction::Or: NumFastIselFailOr++; return; 955 case Instruction::Xor: NumFastIselFailXor++; return; 956 957 // Memory instructions... 958 case Instruction::Alloca: NumFastIselFailAlloca++; return; 959 case Instruction::Load: NumFastIselFailLoad++; return; 960 case Instruction::Store: NumFastIselFailStore++; return; 961 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 962 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 963 case Instruction::Fence: NumFastIselFailFence++; return; 964 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 965 966 // Convert instructions... 967 case Instruction::Trunc: NumFastIselFailTrunc++; return; 968 case Instruction::ZExt: NumFastIselFailZExt++; return; 969 case Instruction::SExt: NumFastIselFailSExt++; return; 970 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 971 case Instruction::FPExt: NumFastIselFailFPExt++; return; 972 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 973 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 974 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 975 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 976 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 977 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 978 case Instruction::BitCast: NumFastIselFailBitCast++; return; 979 980 // Other instructions... 981 case Instruction::ICmp: NumFastIselFailICmp++; return; 982 case Instruction::FCmp: NumFastIselFailFCmp++; return; 983 case Instruction::PHI: NumFastIselFailPHI++; return; 984 case Instruction::Select: NumFastIselFailSelect++; return; 985 case Instruction::Call: NumFastIselFailCall++; return; 986 case Instruction::Shl: NumFastIselFailShl++; return; 987 case Instruction::LShr: NumFastIselFailLShr++; return; 988 case Instruction::AShr: NumFastIselFailAShr++; return; 989 case Instruction::VAArg: NumFastIselFailVAArg++; return; 990 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 991 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 992 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 993 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 994 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 995 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 996 } 997} 998#endif 999 1000void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 1001 // Initialize the Fast-ISel state, if needed. 1002 FastISel *FastIS = 0; 1003 if (TM.Options.EnableFastISel) 1004 FastIS = TLI.createFastISel(*FuncInfo, LibInfo); 1005 1006 // Iterate over all basic blocks in the function. 1007 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 1008 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 1009 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 1010 const BasicBlock *LLVMBB = *I; 1011 1012 if (OptLevel != CodeGenOpt::None) { 1013 bool AllPredsVisited = true; 1014 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 1015 PI != PE; ++PI) { 1016 if (!FuncInfo->VisitedBBs.count(*PI)) { 1017 AllPredsVisited = false; 1018 break; 1019 } 1020 } 1021 1022 if (AllPredsVisited) { 1023 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1024 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1025 FuncInfo->ComputePHILiveOutRegInfo(PN); 1026 } else { 1027 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1028 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1029 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 1030 } 1031 1032 FuncInfo->VisitedBBs.insert(LLVMBB); 1033 } 1034 1035 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 1036 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1037 1038 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 1039 BasicBlock::const_iterator const End = LLVMBB->end(); 1040 BasicBlock::const_iterator BI = End; 1041 1042 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1043 1044 // Setup an EH landing-pad block. 1045 if (FuncInfo->MBB->isLandingPad()) 1046 PrepareEHLandingPad(); 1047 1048 // Before doing SelectionDAG ISel, see if FastISel has been requested. 1049 if (FastIS) { 1050 FastIS->startNewBlock(); 1051 1052 // Emit code for any incoming arguments. This must happen before 1053 // beginning FastISel on the entry block. 1054 if (LLVMBB == &Fn.getEntryBlock()) { 1055 // Lower any arguments needed in this block if this is the entry block. 1056 if (!FastIS->LowerArguments()) { 1057 1058 if (EnableFastISelAbortArgs) 1059 // The "fast" selector couldn't lower these arguments. For the 1060 // purpose of debugging, just abort. 1061 llvm_unreachable("FastISel didn't lower all arguments"); 1062 1063 // Call target indepedent SDISel argument lowering code if the target 1064 // specific routine is not successful. 1065 LowerArguments(LLVMBB); 1066 CurDAG->setRoot(SDB->getControlRoot()); 1067 SDB->clear(); 1068 CodeGenAndEmitDAG(); 1069 } 1070 1071 // If we inserted any instructions at the beginning, make a note of 1072 // where they are, so we can be sure to emit subsequent instructions 1073 // after them. 1074 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1075 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 1076 else 1077 FastIS->setLastLocalValue(0); 1078 } 1079 1080 unsigned NumFastIselRemaining = std::distance(Begin, End); 1081 (void) NumFastIselRemaining; 1082 // Do FastISel on as many instructions as possible. 1083 for (; BI != Begin; --BI) { 1084 const Instruction *Inst = llvm::prior(BI); 1085 1086 // If we no longer require this instruction, skip it. 1087 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1088 --NumFastIselRemaining; 1089 continue; 1090 } 1091 1092 // Bottom-up: reset the insert pos at the top, after any local-value 1093 // instructions. 1094 FastIS->recomputeInsertPt(); 1095 1096 // Try to select the instruction with FastISel. 1097 if (FastIS->SelectInstruction(Inst)) { 1098 --NumFastIselRemaining; 1099 DEBUG(++NumFastIselSuccess); 1100 // If fast isel succeeded, skip over all the folded instructions, and 1101 // then see if there is a load right before the selected instructions. 1102 // Try to fold the load if so. 1103 const Instruction *BeforeInst = Inst; 1104 while (BeforeInst != Begin) { 1105 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 1106 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1107 break; 1108 } 1109 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1110 BeforeInst->hasOneUse() && 1111 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) { 1112 // If we succeeded, don't re-select the load. 1113 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 1114 --NumFastIselRemaining; 1115 DEBUG(++NumFastIselSuccess); 1116 } 1117 continue; 1118 } 1119 1120#ifndef NDEBUG 1121 if (EnableFastISelVerbose2) 1122 collectFailStats(Inst); 1123#endif 1124 1125 // Then handle certain instructions as single-LLVM-Instruction blocks. 1126 if (isa<CallInst>(Inst)) { 1127 1128 if (EnableFastISelVerbose || EnableFastISelAbort) { 1129 dbgs() << "FastISel missed call: "; 1130 Inst->dump(); 1131 } 1132 1133 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1134 unsigned &R = FuncInfo->ValueMap[Inst]; 1135 if (!R) 1136 R = FuncInfo->CreateRegs(Inst->getType()); 1137 } 1138 1139 bool HadTailCall = false; 1140 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1141 SelectBasicBlock(Inst, BI, HadTailCall); 1142 1143 // If the call was emitted as a tail call, we're done with the block. 1144 // We also need to delete any previously emitted instructions. 1145 if (HadTailCall) { 1146 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1147 --BI; 1148 break; 1149 } 1150 1151 // Recompute NumFastIselRemaining as Selection DAG instruction 1152 // selection may have handled the call, input args, etc. 1153 unsigned RemainingNow = std::distance(Begin, BI); 1154 (void) RemainingNow; 1155 DEBUG(NumFastIselFailures += NumFastIselRemaining - RemainingNow); 1156 DEBUG(NumFastIselRemaining = RemainingNow); 1157 continue; 1158 } 1159 1160 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1161 // Don't abort, and use a different message for terminator misses. 1162 DEBUG(NumFastIselFailures += NumFastIselRemaining); 1163 if (EnableFastISelVerbose || EnableFastISelAbort) { 1164 dbgs() << "FastISel missed terminator: "; 1165 Inst->dump(); 1166 } 1167 } else { 1168 DEBUG(NumFastIselFailures += NumFastIselRemaining); 1169 if (EnableFastISelVerbose || EnableFastISelAbort) { 1170 dbgs() << "FastISel miss: "; 1171 Inst->dump(); 1172 } 1173 if (EnableFastISelAbort) 1174 // The "fast" selector couldn't handle something and bailed. 1175 // For the purpose of debugging, just abort. 1176 llvm_unreachable("FastISel didn't select the entire block"); 1177 } 1178 break; 1179 } 1180 1181 FastIS->recomputeInsertPt(); 1182 } else { 1183 // Lower any arguments needed in this block if this is the entry block. 1184 if (LLVMBB == &Fn.getEntryBlock()) 1185 LowerArguments(LLVMBB); 1186 } 1187 1188 if (Begin != BI) 1189 ++NumDAGBlocks; 1190 else 1191 ++NumFastIselBlocks; 1192 1193 if (Begin != BI) { 1194 // Run SelectionDAG instruction selection on the remainder of the block 1195 // not handled by FastISel. If FastISel is not run, this is the entire 1196 // block. 1197 bool HadTailCall; 1198 SelectBasicBlock(Begin, BI, HadTailCall); 1199 } 1200 1201 FinishBasicBlock(); 1202 FuncInfo->PHINodesToUpdate.clear(); 1203 } 1204 1205 delete FastIS; 1206 SDB->clearDanglingDebugInfo(); 1207} 1208 1209void 1210SelectionDAGISel::FinishBasicBlock() { 1211 1212 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1213 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1214 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1215 dbgs() << "Node " << i << " : (" 1216 << FuncInfo->PHINodesToUpdate[i].first 1217 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1218 1219 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1220 // PHI nodes in successors. 1221 if (SDB->SwitchCases.empty() && 1222 SDB->JTCases.empty() && 1223 SDB->BitTestCases.empty()) { 1224 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1225 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1226 assert(PHI->isPHI() && 1227 "This is not a machine PHI node that we are updating!"); 1228 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1229 continue; 1230 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1231 } 1232 return; 1233 } 1234 1235 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1236 // Lower header first, if it wasn't already lowered 1237 if (!SDB->BitTestCases[i].Emitted) { 1238 // Set the current basic block to the mbb we wish to insert the code into 1239 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1240 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1241 // Emit the code 1242 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1243 CurDAG->setRoot(SDB->getRoot()); 1244 SDB->clear(); 1245 CodeGenAndEmitDAG(); 1246 } 1247 1248 uint32_t UnhandledWeight = 0; 1249 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1250 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1251 1252 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1253 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1254 // Set the current basic block to the mbb we wish to insert the code into 1255 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1256 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1257 // Emit the code 1258 if (j+1 != ej) 1259 SDB->visitBitTestCase(SDB->BitTestCases[i], 1260 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1261 UnhandledWeight, 1262 SDB->BitTestCases[i].Reg, 1263 SDB->BitTestCases[i].Cases[j], 1264 FuncInfo->MBB); 1265 else 1266 SDB->visitBitTestCase(SDB->BitTestCases[i], 1267 SDB->BitTestCases[i].Default, 1268 UnhandledWeight, 1269 SDB->BitTestCases[i].Reg, 1270 SDB->BitTestCases[i].Cases[j], 1271 FuncInfo->MBB); 1272 1273 1274 CurDAG->setRoot(SDB->getRoot()); 1275 SDB->clear(); 1276 CodeGenAndEmitDAG(); 1277 } 1278 1279 // Update PHI Nodes 1280 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1281 pi != pe; ++pi) { 1282 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1283 MachineBasicBlock *PHIBB = PHI->getParent(); 1284 assert(PHI->isPHI() && 1285 "This is not a machine PHI node that we are updating!"); 1286 // This is "default" BB. We have two jumps to it. From "header" BB and 1287 // from last "case" BB. 1288 if (PHIBB == SDB->BitTestCases[i].Default) 1289 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1290 .addMBB(SDB->BitTestCases[i].Parent) 1291 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1292 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1293 // One of "cases" BB. 1294 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1295 j != ej; ++j) { 1296 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1297 if (cBB->isSuccessor(PHIBB)) 1298 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1299 } 1300 } 1301 } 1302 SDB->BitTestCases.clear(); 1303 1304 // If the JumpTable record is filled in, then we need to emit a jump table. 1305 // Updating the PHI nodes is tricky in this case, since we need to determine 1306 // whether the PHI is a successor of the range check MBB or the jump table MBB 1307 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1308 // Lower header first, if it wasn't already lowered 1309 if (!SDB->JTCases[i].first.Emitted) { 1310 // Set the current basic block to the mbb we wish to insert the code into 1311 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1312 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1313 // Emit the code 1314 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1315 FuncInfo->MBB); 1316 CurDAG->setRoot(SDB->getRoot()); 1317 SDB->clear(); 1318 CodeGenAndEmitDAG(); 1319 } 1320 1321 // Set the current basic block to the mbb we wish to insert the code into 1322 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1323 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1324 // Emit the code 1325 SDB->visitJumpTable(SDB->JTCases[i].second); 1326 CurDAG->setRoot(SDB->getRoot()); 1327 SDB->clear(); 1328 CodeGenAndEmitDAG(); 1329 1330 // Update PHI Nodes 1331 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1332 pi != pe; ++pi) { 1333 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1334 MachineBasicBlock *PHIBB = PHI->getParent(); 1335 assert(PHI->isPHI() && 1336 "This is not a machine PHI node that we are updating!"); 1337 // "default" BB. We can go there only from header BB. 1338 if (PHIBB == SDB->JTCases[i].second.Default) 1339 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1340 .addMBB(SDB->JTCases[i].first.HeaderBB); 1341 // JT BB. Just iterate over successors here 1342 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1343 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1344 } 1345 } 1346 SDB->JTCases.clear(); 1347 1348 // If the switch block involved a branch to one of the actual successors, we 1349 // need to update PHI nodes in that block. 1350 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1351 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1352 assert(PHI->isPHI() && 1353 "This is not a machine PHI node that we are updating!"); 1354 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 1355 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1356 } 1357 1358 // If we generated any switch lowering information, build and codegen any 1359 // additional DAGs necessary. 1360 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1361 // Set the current basic block to the mbb we wish to insert the code into 1362 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1363 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1364 1365 // Determine the unique successors. 1366 SmallVector<MachineBasicBlock *, 2> Succs; 1367 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1368 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1369 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1370 1371 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1372 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1373 CurDAG->setRoot(SDB->getRoot()); 1374 SDB->clear(); 1375 CodeGenAndEmitDAG(); 1376 1377 // Remember the last block, now that any splitting is done, for use in 1378 // populating PHI nodes in successors. 1379 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1380 1381 // Handle any PHI nodes in successors of this chunk, as if we were coming 1382 // from the original BB before switch expansion. Note that PHI nodes can 1383 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1384 // handle them the right number of times. 1385 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1386 FuncInfo->MBB = Succs[i]; 1387 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1388 // FuncInfo->MBB may have been removed from the CFG if a branch was 1389 // constant folded. 1390 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1391 for (MachineBasicBlock::iterator 1392 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1393 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1394 MachineInstrBuilder PHI(*MF, MBBI); 1395 // This value for this PHI node is recorded in PHINodesToUpdate. 1396 for (unsigned pn = 0; ; ++pn) { 1397 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1398 "Didn't find PHI entry!"); 1399 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1400 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1401 break; 1402 } 1403 } 1404 } 1405 } 1406 } 1407 } 1408 SDB->SwitchCases.clear(); 1409} 1410 1411 1412/// Create the scheduler. If a specific scheduler was specified 1413/// via the SchedulerRegistry, use it, otherwise select the 1414/// one preferred by the target. 1415/// 1416ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1417 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1418 1419 if (!Ctor) { 1420 Ctor = ISHeuristic; 1421 RegisterScheduler::setDefault(Ctor); 1422 } 1423 1424 return Ctor(this, OptLevel); 1425} 1426 1427//===----------------------------------------------------------------------===// 1428// Helper functions used by the generated instruction selector. 1429//===----------------------------------------------------------------------===// 1430// Calls to these methods are generated by tblgen. 1431 1432/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1433/// the dag combiner simplified the 255, we still want to match. RHS is the 1434/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1435/// specified in the .td file (e.g. 255). 1436bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1437 int64_t DesiredMaskS) const { 1438 const APInt &ActualMask = RHS->getAPIntValue(); 1439 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1440 1441 // If the actual mask exactly matches, success! 1442 if (ActualMask == DesiredMask) 1443 return true; 1444 1445 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1446 if (ActualMask.intersects(~DesiredMask)) 1447 return false; 1448 1449 // Otherwise, the DAG Combiner may have proven that the value coming in is 1450 // either already zero or is not demanded. Check for known zero input bits. 1451 APInt NeededMask = DesiredMask & ~ActualMask; 1452 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1453 return true; 1454 1455 // TODO: check to see if missing bits are just not demanded. 1456 1457 // Otherwise, this pattern doesn't match. 1458 return false; 1459} 1460 1461/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1462/// the dag combiner simplified the 255, we still want to match. RHS is the 1463/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1464/// specified in the .td file (e.g. 255). 1465bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1466 int64_t DesiredMaskS) const { 1467 const APInt &ActualMask = RHS->getAPIntValue(); 1468 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1469 1470 // If the actual mask exactly matches, success! 1471 if (ActualMask == DesiredMask) 1472 return true; 1473 1474 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1475 if (ActualMask.intersects(~DesiredMask)) 1476 return false; 1477 1478 // Otherwise, the DAG Combiner may have proven that the value coming in is 1479 // either already zero or is not demanded. Check for known zero input bits. 1480 APInt NeededMask = DesiredMask & ~ActualMask; 1481 1482 APInt KnownZero, KnownOne; 1483 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 1484 1485 // If all the missing bits in the or are already known to be set, match! 1486 if ((NeededMask & KnownOne) == NeededMask) 1487 return true; 1488 1489 // TODO: check to see if missing bits are just not demanded. 1490 1491 // Otherwise, this pattern doesn't match. 1492 return false; 1493} 1494 1495 1496/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1497/// by tblgen. Others should not call it. 1498void SelectionDAGISel:: 1499SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1500 std::vector<SDValue> InOps; 1501 std::swap(InOps, Ops); 1502 1503 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1504 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1505 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1506 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1507 1508 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1509 if (InOps[e-1].getValueType() == MVT::Glue) 1510 --e; // Don't process a glue operand if it is here. 1511 1512 while (i != e) { 1513 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1514 if (!InlineAsm::isMemKind(Flags)) { 1515 // Just skip over this operand, copying the operands verbatim. 1516 Ops.insert(Ops.end(), InOps.begin()+i, 1517 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1518 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1519 } else { 1520 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1521 "Memory operand with multiple values?"); 1522 // Otherwise, this is a memory operand. Ask the target to select it. 1523 std::vector<SDValue> SelOps; 1524 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1525 report_fatal_error("Could not match memory address. Inline asm" 1526 " failure!"); 1527 1528 // Add this to the output node. 1529 unsigned NewFlags = 1530 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1531 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1532 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1533 i += 2; 1534 } 1535 } 1536 1537 // Add the glue input back if present. 1538 if (e != InOps.size()) 1539 Ops.push_back(InOps.back()); 1540} 1541 1542/// findGlueUse - Return use of MVT::Glue value produced by the specified 1543/// SDNode. 1544/// 1545static SDNode *findGlueUse(SDNode *N) { 1546 unsigned FlagResNo = N->getNumValues()-1; 1547 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1548 SDUse &Use = I.getUse(); 1549 if (Use.getResNo() == FlagResNo) 1550 return Use.getUser(); 1551 } 1552 return NULL; 1553} 1554 1555/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1556/// This function recursively traverses up the operand chain, ignoring 1557/// certain nodes. 1558static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1559 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1560 bool IgnoreChains) { 1561 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1562 // greater than all of its (recursive) operands. If we scan to a point where 1563 // 'use' is smaller than the node we're scanning for, then we know we will 1564 // never find it. 1565 // 1566 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1567 // happen because we scan down to newly selected nodes in the case of glue 1568 // uses. 1569 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1570 return false; 1571 1572 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1573 // won't fail if we scan it again. 1574 if (!Visited.insert(Use)) 1575 return false; 1576 1577 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1578 // Ignore chain uses, they are validated by HandleMergeInputChains. 1579 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1580 continue; 1581 1582 SDNode *N = Use->getOperand(i).getNode(); 1583 if (N == Def) { 1584 if (Use == ImmedUse || Use == Root) 1585 continue; // We are not looking for immediate use. 1586 assert(N != Root); 1587 return true; 1588 } 1589 1590 // Traverse up the operand chain. 1591 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1592 return true; 1593 } 1594 return false; 1595} 1596 1597/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1598/// operand node N of U during instruction selection that starts at Root. 1599bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1600 SDNode *Root) const { 1601 if (OptLevel == CodeGenOpt::None) return false; 1602 return N.hasOneUse(); 1603} 1604 1605/// IsLegalToFold - Returns true if the specific operand node N of 1606/// U can be folded during instruction selection that starts at Root. 1607bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1608 CodeGenOpt::Level OptLevel, 1609 bool IgnoreChains) { 1610 if (OptLevel == CodeGenOpt::None) return false; 1611 1612 // If Root use can somehow reach N through a path that that doesn't contain 1613 // U then folding N would create a cycle. e.g. In the following 1614 // diagram, Root can reach N through X. If N is folded into into Root, then 1615 // X is both a predecessor and a successor of U. 1616 // 1617 // [N*] // 1618 // ^ ^ // 1619 // / \ // 1620 // [U*] [X]? // 1621 // ^ ^ // 1622 // \ / // 1623 // \ / // 1624 // [Root*] // 1625 // 1626 // * indicates nodes to be folded together. 1627 // 1628 // If Root produces glue, then it gets (even more) interesting. Since it 1629 // will be "glued" together with its glue use in the scheduler, we need to 1630 // check if it might reach N. 1631 // 1632 // [N*] // 1633 // ^ ^ // 1634 // / \ // 1635 // [U*] [X]? // 1636 // ^ ^ // 1637 // \ \ // 1638 // \ | // 1639 // [Root*] | // 1640 // ^ | // 1641 // f | // 1642 // | / // 1643 // [Y] / // 1644 // ^ / // 1645 // f / // 1646 // | / // 1647 // [GU] // 1648 // 1649 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1650 // (call it Fold), then X is a predecessor of GU and a successor of 1651 // Fold. But since Fold and GU are glued together, this will create 1652 // a cycle in the scheduling graph. 1653 1654 // If the node has glue, walk down the graph to the "lowest" node in the 1655 // glueged set. 1656 EVT VT = Root->getValueType(Root->getNumValues()-1); 1657 while (VT == MVT::Glue) { 1658 SDNode *GU = findGlueUse(Root); 1659 if (GU == NULL) 1660 break; 1661 Root = GU; 1662 VT = Root->getValueType(Root->getNumValues()-1); 1663 1664 // If our query node has a glue result with a use, we've walked up it. If 1665 // the user (which has already been selected) has a chain or indirectly uses 1666 // the chain, our WalkChainUsers predicate will not consider it. Because of 1667 // this, we cannot ignore chains in this predicate. 1668 IgnoreChains = false; 1669 } 1670 1671 1672 SmallPtrSet<SDNode*, 16> Visited; 1673 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1674} 1675 1676SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1677 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1678 SelectInlineAsmMemoryOperands(Ops); 1679 1680 std::vector<EVT> VTs; 1681 VTs.push_back(MVT::Other); 1682 VTs.push_back(MVT::Glue); 1683 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1684 VTs, &Ops[0], Ops.size()); 1685 New->setNodeId(-1); 1686 return New.getNode(); 1687} 1688 1689SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1690 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1691} 1692 1693/// GetVBR - decode a vbr encoding whose top bit is set. 1694LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1695GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1696 assert(Val >= 128 && "Not a VBR"); 1697 Val &= 127; // Remove first vbr bit. 1698 1699 unsigned Shift = 7; 1700 uint64_t NextBits; 1701 do { 1702 NextBits = MatcherTable[Idx++]; 1703 Val |= (NextBits&127) << Shift; 1704 Shift += 7; 1705 } while (NextBits & 128); 1706 1707 return Val; 1708} 1709 1710 1711/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1712/// interior glue and chain results to use the new glue and chain results. 1713void SelectionDAGISel:: 1714UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1715 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1716 SDValue InputGlue, 1717 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1718 bool isMorphNodeTo) { 1719 SmallVector<SDNode*, 4> NowDeadNodes; 1720 1721 // Now that all the normal results are replaced, we replace the chain and 1722 // glue results if present. 1723 if (!ChainNodesMatched.empty()) { 1724 assert(InputChain.getNode() != 0 && 1725 "Matched input chains but didn't produce a chain"); 1726 // Loop over all of the nodes we matched that produced a chain result. 1727 // Replace all the chain results with the final chain we ended up with. 1728 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1729 SDNode *ChainNode = ChainNodesMatched[i]; 1730 1731 // If this node was already deleted, don't look at it. 1732 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1733 continue; 1734 1735 // Don't replace the results of the root node if we're doing a 1736 // MorphNodeTo. 1737 if (ChainNode == NodeToMatch && isMorphNodeTo) 1738 continue; 1739 1740 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1741 if (ChainVal.getValueType() == MVT::Glue) 1742 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1743 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1744 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1745 1746 // If the node became dead and we haven't already seen it, delete it. 1747 if (ChainNode->use_empty() && 1748 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1749 NowDeadNodes.push_back(ChainNode); 1750 } 1751 } 1752 1753 // If the result produces glue, update any glue results in the matched 1754 // pattern with the glue result. 1755 if (InputGlue.getNode() != 0) { 1756 // Handle any interior nodes explicitly marked. 1757 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1758 SDNode *FRN = GlueResultNodesMatched[i]; 1759 1760 // If this node was already deleted, don't look at it. 1761 if (FRN->getOpcode() == ISD::DELETED_NODE) 1762 continue; 1763 1764 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1765 "Doesn't have a glue result"); 1766 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1767 InputGlue); 1768 1769 // If the node became dead and we haven't already seen it, delete it. 1770 if (FRN->use_empty() && 1771 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1772 NowDeadNodes.push_back(FRN); 1773 } 1774 } 1775 1776 if (!NowDeadNodes.empty()) 1777 CurDAG->RemoveDeadNodes(NowDeadNodes); 1778 1779 DEBUG(errs() << "ISEL: Match complete!\n"); 1780} 1781 1782enum ChainResult { 1783 CR_Simple, 1784 CR_InducesCycle, 1785 CR_LeadsToInteriorNode 1786}; 1787 1788/// WalkChainUsers - Walk down the users of the specified chained node that is 1789/// part of the pattern we're matching, looking at all of the users we find. 1790/// This determines whether something is an interior node, whether we have a 1791/// non-pattern node in between two pattern nodes (which prevent folding because 1792/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1793/// between pattern nodes (in which case the TF becomes part of the pattern). 1794/// 1795/// The walk we do here is guaranteed to be small because we quickly get down to 1796/// already selected nodes "below" us. 1797static ChainResult 1798WalkChainUsers(const SDNode *ChainedNode, 1799 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1800 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1801 ChainResult Result = CR_Simple; 1802 1803 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1804 E = ChainedNode->use_end(); UI != E; ++UI) { 1805 // Make sure the use is of the chain, not some other value we produce. 1806 if (UI.getUse().getValueType() != MVT::Other) continue; 1807 1808 SDNode *User = *UI; 1809 1810 // If we see an already-selected machine node, then we've gone beyond the 1811 // pattern that we're selecting down into the already selected chunk of the 1812 // DAG. 1813 if (User->isMachineOpcode() || 1814 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1815 continue; 1816 1817 unsigned UserOpcode = User->getOpcode(); 1818 if (UserOpcode == ISD::CopyToReg || 1819 UserOpcode == ISD::CopyFromReg || 1820 UserOpcode == ISD::INLINEASM || 1821 UserOpcode == ISD::EH_LABEL || 1822 UserOpcode == ISD::LIFETIME_START || 1823 UserOpcode == ISD::LIFETIME_END) { 1824 // If their node ID got reset to -1 then they've already been selected. 1825 // Treat them like a MachineOpcode. 1826 if (User->getNodeId() == -1) 1827 continue; 1828 } 1829 1830 // If we have a TokenFactor, we handle it specially. 1831 if (User->getOpcode() != ISD::TokenFactor) { 1832 // If the node isn't a token factor and isn't part of our pattern, then it 1833 // must be a random chained node in between two nodes we're selecting. 1834 // This happens when we have something like: 1835 // x = load ptr 1836 // call 1837 // y = x+4 1838 // store y -> ptr 1839 // Because we structurally match the load/store as a read/modify/write, 1840 // but the call is chained between them. We cannot fold in this case 1841 // because it would induce a cycle in the graph. 1842 if (!std::count(ChainedNodesInPattern.begin(), 1843 ChainedNodesInPattern.end(), User)) 1844 return CR_InducesCycle; 1845 1846 // Otherwise we found a node that is part of our pattern. For example in: 1847 // x = load ptr 1848 // y = x+4 1849 // store y -> ptr 1850 // This would happen when we're scanning down from the load and see the 1851 // store as a user. Record that there is a use of ChainedNode that is 1852 // part of the pattern and keep scanning uses. 1853 Result = CR_LeadsToInteriorNode; 1854 InteriorChainedNodes.push_back(User); 1855 continue; 1856 } 1857 1858 // If we found a TokenFactor, there are two cases to consider: first if the 1859 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1860 // uses of the TF are in our pattern) we just want to ignore it. Second, 1861 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1862 // [Load chain] 1863 // ^ 1864 // | 1865 // [Load] 1866 // ^ ^ 1867 // | \ DAG's like cheese 1868 // / \ do you? 1869 // / | 1870 // [TokenFactor] [Op] 1871 // ^ ^ 1872 // | | 1873 // \ / 1874 // \ / 1875 // [Store] 1876 // 1877 // In this case, the TokenFactor becomes part of our match and we rewrite it 1878 // as a new TokenFactor. 1879 // 1880 // To distinguish these two cases, do a recursive walk down the uses. 1881 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1882 case CR_Simple: 1883 // If the uses of the TokenFactor are just already-selected nodes, ignore 1884 // it, it is "below" our pattern. 1885 continue; 1886 case CR_InducesCycle: 1887 // If the uses of the TokenFactor lead to nodes that are not part of our 1888 // pattern that are not selected, folding would turn this into a cycle, 1889 // bail out now. 1890 return CR_InducesCycle; 1891 case CR_LeadsToInteriorNode: 1892 break; // Otherwise, keep processing. 1893 } 1894 1895 // Okay, we know we're in the interesting interior case. The TokenFactor 1896 // is now going to be considered part of the pattern so that we rewrite its 1897 // uses (it may have uses that are not part of the pattern) with the 1898 // ultimate chain result of the generated code. We will also add its chain 1899 // inputs as inputs to the ultimate TokenFactor we create. 1900 Result = CR_LeadsToInteriorNode; 1901 ChainedNodesInPattern.push_back(User); 1902 InteriorChainedNodes.push_back(User); 1903 continue; 1904 } 1905 1906 return Result; 1907} 1908 1909/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1910/// operation for when the pattern matched at least one node with a chains. The 1911/// input vector contains a list of all of the chained nodes that we match. We 1912/// must determine if this is a valid thing to cover (i.e. matching it won't 1913/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1914/// be used as the input node chain for the generated nodes. 1915static SDValue 1916HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1917 SelectionDAG *CurDAG) { 1918 // Walk all of the chained nodes we've matched, recursively scanning down the 1919 // users of the chain result. This adds any TokenFactor nodes that are caught 1920 // in between chained nodes to the chained and interior nodes list. 1921 SmallVector<SDNode*, 3> InteriorChainedNodes; 1922 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1923 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1924 InteriorChainedNodes) == CR_InducesCycle) 1925 return SDValue(); // Would induce a cycle. 1926 } 1927 1928 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1929 // that we are interested in. Form our input TokenFactor node. 1930 SmallVector<SDValue, 3> InputChains; 1931 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1932 // Add the input chain of this node to the InputChains list (which will be 1933 // the operands of the generated TokenFactor) if it's not an interior node. 1934 SDNode *N = ChainNodesMatched[i]; 1935 if (N->getOpcode() != ISD::TokenFactor) { 1936 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1937 continue; 1938 1939 // Otherwise, add the input chain. 1940 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1941 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1942 InputChains.push_back(InChain); 1943 continue; 1944 } 1945 1946 // If we have a token factor, we want to add all inputs of the token factor 1947 // that are not part of the pattern we're matching. 1948 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1949 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1950 N->getOperand(op).getNode())) 1951 InputChains.push_back(N->getOperand(op)); 1952 } 1953 } 1954 1955 SDValue Res; 1956 if (InputChains.size() == 1) 1957 return InputChains[0]; 1958 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1959 MVT::Other, &InputChains[0], InputChains.size()); 1960} 1961 1962/// MorphNode - Handle morphing a node in place for the selector. 1963SDNode *SelectionDAGISel:: 1964MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1965 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1966 // It is possible we're using MorphNodeTo to replace a node with no 1967 // normal results with one that has a normal result (or we could be 1968 // adding a chain) and the input could have glue and chains as well. 1969 // In this case we need to shift the operands down. 1970 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1971 // than the old isel though. 1972 int OldGlueResultNo = -1, OldChainResultNo = -1; 1973 1974 unsigned NTMNumResults = Node->getNumValues(); 1975 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 1976 OldGlueResultNo = NTMNumResults-1; 1977 if (NTMNumResults != 1 && 1978 Node->getValueType(NTMNumResults-2) == MVT::Other) 1979 OldChainResultNo = NTMNumResults-2; 1980 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1981 OldChainResultNo = NTMNumResults-1; 1982 1983 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1984 // that this deletes operands of the old node that become dead. 1985 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1986 1987 // MorphNodeTo can operate in two ways: if an existing node with the 1988 // specified operands exists, it can just return it. Otherwise, it 1989 // updates the node in place to have the requested operands. 1990 if (Res == Node) { 1991 // If we updated the node in place, reset the node ID. To the isel, 1992 // this should be just like a newly allocated machine node. 1993 Res->setNodeId(-1); 1994 } 1995 1996 unsigned ResNumResults = Res->getNumValues(); 1997 // Move the glue if needed. 1998 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 1999 (unsigned)OldGlueResultNo != ResNumResults-1) 2000 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 2001 SDValue(Res, ResNumResults-1)); 2002 2003 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 2004 --ResNumResults; 2005 2006 // Move the chain reference if needed. 2007 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 2008 (unsigned)OldChainResultNo != ResNumResults-1) 2009 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 2010 SDValue(Res, ResNumResults-1)); 2011 2012 // Otherwise, no replacement happened because the node already exists. Replace 2013 // Uses of the old node with the new one. 2014 if (Res != Node) 2015 CurDAG->ReplaceAllUsesWith(Node, Res); 2016 2017 return Res; 2018} 2019 2020/// CheckSame - Implements OP_CheckSame. 2021LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2022CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2023 SDValue N, 2024 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2025 // Accept if it is exactly the same as a previously recorded node. 2026 unsigned RecNo = MatcherTable[MatcherIndex++]; 2027 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2028 return N == RecordedNodes[RecNo].first; 2029} 2030 2031/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2032LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2033CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2034 const SelectionDAGISel &SDISel) { 2035 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 2036} 2037 2038/// CheckNodePredicate - Implements OP_CheckNodePredicate. 2039LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2040CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2041 const SelectionDAGISel &SDISel, SDNode *N) { 2042 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2043} 2044 2045LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2046CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2047 SDNode *N) { 2048 uint16_t Opc = MatcherTable[MatcherIndex++]; 2049 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2050 return N->getOpcode() == Opc; 2051} 2052 2053LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2054CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2055 SDValue N, const TargetLowering &TLI) { 2056 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2057 if (N.getValueType() == VT) return true; 2058 2059 // Handle the case when VT is iPTR. 2060 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 2061} 2062 2063LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2064CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2065 SDValue N, const TargetLowering &TLI, 2066 unsigned ChildNo) { 2067 if (ChildNo >= N.getNumOperands()) 2068 return false; // Match fails if out of range child #. 2069 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2070} 2071 2072 2073LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2074CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2075 SDValue N) { 2076 return cast<CondCodeSDNode>(N)->get() == 2077 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2078} 2079 2080LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2081CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2082 SDValue N, const TargetLowering &TLI) { 2083 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2084 if (cast<VTSDNode>(N)->getVT() == VT) 2085 return true; 2086 2087 // Handle the case when VT is iPTR. 2088 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 2089} 2090 2091LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2092CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2093 SDValue N) { 2094 int64_t Val = MatcherTable[MatcherIndex++]; 2095 if (Val & 128) 2096 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2097 2098 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2099 return C != 0 && C->getSExtValue() == Val; 2100} 2101 2102LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2103CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2104 SDValue N, const SelectionDAGISel &SDISel) { 2105 int64_t Val = MatcherTable[MatcherIndex++]; 2106 if (Val & 128) 2107 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2108 2109 if (N->getOpcode() != ISD::AND) return false; 2110 2111 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2112 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2113} 2114 2115LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2116CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2117 SDValue N, const SelectionDAGISel &SDISel) { 2118 int64_t Val = MatcherTable[MatcherIndex++]; 2119 if (Val & 128) 2120 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2121 2122 if (N->getOpcode() != ISD::OR) return false; 2123 2124 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2125 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2126} 2127 2128/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2129/// scope, evaluate the current node. If the current predicate is known to 2130/// fail, set Result=true and return anything. If the current predicate is 2131/// known to pass, set Result=false and return the MatcherIndex to continue 2132/// with. If the current predicate is unknown, set Result=false and return the 2133/// MatcherIndex to continue with. 2134static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2135 unsigned Index, SDValue N, 2136 bool &Result, 2137 const SelectionDAGISel &SDISel, 2138 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2139 switch (Table[Index++]) { 2140 default: 2141 Result = false; 2142 return Index-1; // Could not evaluate this predicate. 2143 case SelectionDAGISel::OPC_CheckSame: 2144 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2145 return Index; 2146 case SelectionDAGISel::OPC_CheckPatternPredicate: 2147 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2148 return Index; 2149 case SelectionDAGISel::OPC_CheckPredicate: 2150 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2151 return Index; 2152 case SelectionDAGISel::OPC_CheckOpcode: 2153 Result = !::CheckOpcode(Table, Index, N.getNode()); 2154 return Index; 2155 case SelectionDAGISel::OPC_CheckType: 2156 Result = !::CheckType(Table, Index, N, SDISel.TLI); 2157 return Index; 2158 case SelectionDAGISel::OPC_CheckChild0Type: 2159 case SelectionDAGISel::OPC_CheckChild1Type: 2160 case SelectionDAGISel::OPC_CheckChild2Type: 2161 case SelectionDAGISel::OPC_CheckChild3Type: 2162 case SelectionDAGISel::OPC_CheckChild4Type: 2163 case SelectionDAGISel::OPC_CheckChild5Type: 2164 case SelectionDAGISel::OPC_CheckChild6Type: 2165 case SelectionDAGISel::OPC_CheckChild7Type: 2166 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 2167 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2168 return Index; 2169 case SelectionDAGISel::OPC_CheckCondCode: 2170 Result = !::CheckCondCode(Table, Index, N); 2171 return Index; 2172 case SelectionDAGISel::OPC_CheckValueType: 2173 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2174 return Index; 2175 case SelectionDAGISel::OPC_CheckInteger: 2176 Result = !::CheckInteger(Table, Index, N); 2177 return Index; 2178 case SelectionDAGISel::OPC_CheckAndImm: 2179 Result = !::CheckAndImm(Table, Index, N, SDISel); 2180 return Index; 2181 case SelectionDAGISel::OPC_CheckOrImm: 2182 Result = !::CheckOrImm(Table, Index, N, SDISel); 2183 return Index; 2184 } 2185} 2186 2187namespace { 2188 2189struct MatchScope { 2190 /// FailIndex - If this match fails, this is the index to continue with. 2191 unsigned FailIndex; 2192 2193 /// NodeStack - The node stack when the scope was formed. 2194 SmallVector<SDValue, 4> NodeStack; 2195 2196 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2197 unsigned NumRecordedNodes; 2198 2199 /// NumMatchedMemRefs - The number of matched memref entries. 2200 unsigned NumMatchedMemRefs; 2201 2202 /// InputChain/InputGlue - The current chain/glue 2203 SDValue InputChain, InputGlue; 2204 2205 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2206 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2207}; 2208 2209} 2210 2211SDNode *SelectionDAGISel:: 2212SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2213 unsigned TableSize) { 2214 // FIXME: Should these even be selected? Handle these cases in the caller? 2215 switch (NodeToMatch->getOpcode()) { 2216 default: 2217 break; 2218 case ISD::EntryToken: // These nodes remain the same. 2219 case ISD::BasicBlock: 2220 case ISD::Register: 2221 case ISD::RegisterMask: 2222 //case ISD::VALUETYPE: 2223 //case ISD::CONDCODE: 2224 case ISD::HANDLENODE: 2225 case ISD::MDNODE_SDNODE: 2226 case ISD::TargetConstant: 2227 case ISD::TargetConstantFP: 2228 case ISD::TargetConstantPool: 2229 case ISD::TargetFrameIndex: 2230 case ISD::TargetExternalSymbol: 2231 case ISD::TargetBlockAddress: 2232 case ISD::TargetJumpTable: 2233 case ISD::TargetGlobalTLSAddress: 2234 case ISD::TargetGlobalAddress: 2235 case ISD::TokenFactor: 2236 case ISD::CopyFromReg: 2237 case ISD::CopyToReg: 2238 case ISD::EH_LABEL: 2239 case ISD::LIFETIME_START: 2240 case ISD::LIFETIME_END: 2241 NodeToMatch->setNodeId(-1); // Mark selected. 2242 return 0; 2243 case ISD::AssertSext: 2244 case ISD::AssertZext: 2245 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2246 NodeToMatch->getOperand(0)); 2247 return 0; 2248 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2249 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2250 } 2251 2252 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2253 2254 // Set up the node stack with NodeToMatch as the only node on the stack. 2255 SmallVector<SDValue, 8> NodeStack; 2256 SDValue N = SDValue(NodeToMatch, 0); 2257 NodeStack.push_back(N); 2258 2259 // MatchScopes - Scopes used when matching, if a match failure happens, this 2260 // indicates where to continue checking. 2261 SmallVector<MatchScope, 8> MatchScopes; 2262 2263 // RecordedNodes - This is the set of nodes that have been recorded by the 2264 // state machine. The second value is the parent of the node, or null if the 2265 // root is recorded. 2266 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2267 2268 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2269 // pattern. 2270 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2271 2272 // These are the current input chain and glue for use when generating nodes. 2273 // Various Emit operations change these. For example, emitting a copytoreg 2274 // uses and updates these. 2275 SDValue InputChain, InputGlue; 2276 2277 // ChainNodesMatched - If a pattern matches nodes that have input/output 2278 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2279 // which ones they are. The result is captured into this list so that we can 2280 // update the chain results when the pattern is complete. 2281 SmallVector<SDNode*, 3> ChainNodesMatched; 2282 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2283 2284 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2285 NodeToMatch->dump(CurDAG); 2286 errs() << '\n'); 2287 2288 // Determine where to start the interpreter. Normally we start at opcode #0, 2289 // but if the state machine starts with an OPC_SwitchOpcode, then we 2290 // accelerate the first lookup (which is guaranteed to be hot) with the 2291 // OpcodeOffset table. 2292 unsigned MatcherIndex = 0; 2293 2294 if (!OpcodeOffset.empty()) { 2295 // Already computed the OpcodeOffset table, just index into it. 2296 if (N.getOpcode() < OpcodeOffset.size()) 2297 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2298 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2299 2300 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2301 // Otherwise, the table isn't computed, but the state machine does start 2302 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2303 // is the first time we're selecting an instruction. 2304 unsigned Idx = 1; 2305 while (1) { 2306 // Get the size of this case. 2307 unsigned CaseSize = MatcherTable[Idx++]; 2308 if (CaseSize & 128) 2309 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2310 if (CaseSize == 0) break; 2311 2312 // Get the opcode, add the index to the table. 2313 uint16_t Opc = MatcherTable[Idx++]; 2314 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2315 if (Opc >= OpcodeOffset.size()) 2316 OpcodeOffset.resize((Opc+1)*2); 2317 OpcodeOffset[Opc] = Idx; 2318 Idx += CaseSize; 2319 } 2320 2321 // Okay, do the lookup for the first opcode. 2322 if (N.getOpcode() < OpcodeOffset.size()) 2323 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2324 } 2325 2326 while (1) { 2327 assert(MatcherIndex < TableSize && "Invalid index"); 2328#ifndef NDEBUG 2329 unsigned CurrentOpcodeIndex = MatcherIndex; 2330#endif 2331 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2332 switch (Opcode) { 2333 case OPC_Scope: { 2334 // Okay, the semantics of this operation are that we should push a scope 2335 // then evaluate the first child. However, pushing a scope only to have 2336 // the first check fail (which then pops it) is inefficient. If we can 2337 // determine immediately that the first check (or first several) will 2338 // immediately fail, don't even bother pushing a scope for them. 2339 unsigned FailIndex; 2340 2341 while (1) { 2342 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2343 if (NumToSkip & 128) 2344 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2345 // Found the end of the scope with no match. 2346 if (NumToSkip == 0) { 2347 FailIndex = 0; 2348 break; 2349 } 2350 2351 FailIndex = MatcherIndex+NumToSkip; 2352 2353 unsigned MatcherIndexOfPredicate = MatcherIndex; 2354 (void)MatcherIndexOfPredicate; // silence warning. 2355 2356 // If we can't evaluate this predicate without pushing a scope (e.g. if 2357 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2358 // push the scope and evaluate the full predicate chain. 2359 bool Result; 2360 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2361 Result, *this, RecordedNodes); 2362 if (!Result) 2363 break; 2364 2365 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2366 << "index " << MatcherIndexOfPredicate 2367 << ", continuing at " << FailIndex << "\n"); 2368 DEBUG(++NumDAGIselRetries); 2369 2370 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2371 // move to the next case. 2372 MatcherIndex = FailIndex; 2373 } 2374 2375 // If the whole scope failed to match, bail. 2376 if (FailIndex == 0) break; 2377 2378 // Push a MatchScope which indicates where to go if the first child fails 2379 // to match. 2380 MatchScope NewEntry; 2381 NewEntry.FailIndex = FailIndex; 2382 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2383 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2384 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2385 NewEntry.InputChain = InputChain; 2386 NewEntry.InputGlue = InputGlue; 2387 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2388 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2389 MatchScopes.push_back(NewEntry); 2390 continue; 2391 } 2392 case OPC_RecordNode: { 2393 // Remember this node, it may end up being an operand in the pattern. 2394 SDNode *Parent = 0; 2395 if (NodeStack.size() > 1) 2396 Parent = NodeStack[NodeStack.size()-2].getNode(); 2397 RecordedNodes.push_back(std::make_pair(N, Parent)); 2398 continue; 2399 } 2400 2401 case OPC_RecordChild0: case OPC_RecordChild1: 2402 case OPC_RecordChild2: case OPC_RecordChild3: 2403 case OPC_RecordChild4: case OPC_RecordChild5: 2404 case OPC_RecordChild6: case OPC_RecordChild7: { 2405 unsigned ChildNo = Opcode-OPC_RecordChild0; 2406 if (ChildNo >= N.getNumOperands()) 2407 break; // Match fails if out of range child #. 2408 2409 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2410 N.getNode())); 2411 continue; 2412 } 2413 case OPC_RecordMemRef: 2414 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2415 continue; 2416 2417 case OPC_CaptureGlueInput: 2418 // If the current node has an input glue, capture it in InputGlue. 2419 if (N->getNumOperands() != 0 && 2420 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2421 InputGlue = N->getOperand(N->getNumOperands()-1); 2422 continue; 2423 2424 case OPC_MoveChild: { 2425 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2426 if (ChildNo >= N.getNumOperands()) 2427 break; // Match fails if out of range child #. 2428 N = N.getOperand(ChildNo); 2429 NodeStack.push_back(N); 2430 continue; 2431 } 2432 2433 case OPC_MoveParent: 2434 // Pop the current node off the NodeStack. 2435 NodeStack.pop_back(); 2436 assert(!NodeStack.empty() && "Node stack imbalance!"); 2437 N = NodeStack.back(); 2438 continue; 2439 2440 case OPC_CheckSame: 2441 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2442 continue; 2443 case OPC_CheckPatternPredicate: 2444 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2445 continue; 2446 case OPC_CheckPredicate: 2447 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2448 N.getNode())) 2449 break; 2450 continue; 2451 case OPC_CheckComplexPat: { 2452 unsigned CPNum = MatcherTable[MatcherIndex++]; 2453 unsigned RecNo = MatcherTable[MatcherIndex++]; 2454 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2455 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2456 RecordedNodes[RecNo].first, CPNum, 2457 RecordedNodes)) 2458 break; 2459 continue; 2460 } 2461 case OPC_CheckOpcode: 2462 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2463 continue; 2464 2465 case OPC_CheckType: 2466 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2467 continue; 2468 2469 case OPC_SwitchOpcode: { 2470 unsigned CurNodeOpcode = N.getOpcode(); 2471 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2472 unsigned CaseSize; 2473 while (1) { 2474 // Get the size of this case. 2475 CaseSize = MatcherTable[MatcherIndex++]; 2476 if (CaseSize & 128) 2477 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2478 if (CaseSize == 0) break; 2479 2480 uint16_t Opc = MatcherTable[MatcherIndex++]; 2481 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2482 2483 // If the opcode matches, then we will execute this case. 2484 if (CurNodeOpcode == Opc) 2485 break; 2486 2487 // Otherwise, skip over this case. 2488 MatcherIndex += CaseSize; 2489 } 2490 2491 // If no cases matched, bail out. 2492 if (CaseSize == 0) break; 2493 2494 // Otherwise, execute the case we found. 2495 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2496 << " to " << MatcherIndex << "\n"); 2497 continue; 2498 } 2499 2500 case OPC_SwitchType: { 2501 MVT CurNodeVT = N.getValueType().getSimpleVT(); 2502 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2503 unsigned CaseSize; 2504 while (1) { 2505 // Get the size of this case. 2506 CaseSize = MatcherTable[MatcherIndex++]; 2507 if (CaseSize & 128) 2508 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2509 if (CaseSize == 0) break; 2510 2511 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2512 if (CaseVT == MVT::iPTR) 2513 CaseVT = TLI.getPointerTy(); 2514 2515 // If the VT matches, then we will execute this case. 2516 if (CurNodeVT == CaseVT) 2517 break; 2518 2519 // Otherwise, skip over this case. 2520 MatcherIndex += CaseSize; 2521 } 2522 2523 // If no cases matched, bail out. 2524 if (CaseSize == 0) break; 2525 2526 // Otherwise, execute the case we found. 2527 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2528 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2529 continue; 2530 } 2531 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2532 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2533 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2534 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2535 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2536 Opcode-OPC_CheckChild0Type)) 2537 break; 2538 continue; 2539 case OPC_CheckCondCode: 2540 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2541 continue; 2542 case OPC_CheckValueType: 2543 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2544 continue; 2545 case OPC_CheckInteger: 2546 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2547 continue; 2548 case OPC_CheckAndImm: 2549 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2550 continue; 2551 case OPC_CheckOrImm: 2552 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2553 continue; 2554 2555 case OPC_CheckFoldableChainNode: { 2556 assert(NodeStack.size() != 1 && "No parent node"); 2557 // Verify that all intermediate nodes between the root and this one have 2558 // a single use. 2559 bool HasMultipleUses = false; 2560 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2561 if (!NodeStack[i].hasOneUse()) { 2562 HasMultipleUses = true; 2563 break; 2564 } 2565 if (HasMultipleUses) break; 2566 2567 // Check to see that the target thinks this is profitable to fold and that 2568 // we can fold it without inducing cycles in the graph. 2569 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2570 NodeToMatch) || 2571 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2572 NodeToMatch, OptLevel, 2573 true/*We validate our own chains*/)) 2574 break; 2575 2576 continue; 2577 } 2578 case OPC_EmitInteger: { 2579 MVT::SimpleValueType VT = 2580 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2581 int64_t Val = MatcherTable[MatcherIndex++]; 2582 if (Val & 128) 2583 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2584 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2585 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2586 continue; 2587 } 2588 case OPC_EmitRegister: { 2589 MVT::SimpleValueType VT = 2590 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2591 unsigned RegNo = MatcherTable[MatcherIndex++]; 2592 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2593 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2594 continue; 2595 } 2596 case OPC_EmitRegister2: { 2597 // For targets w/ more than 256 register names, the register enum 2598 // values are stored in two bytes in the matcher table (just like 2599 // opcodes). 2600 MVT::SimpleValueType VT = 2601 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2602 unsigned RegNo = MatcherTable[MatcherIndex++]; 2603 RegNo |= MatcherTable[MatcherIndex++] << 8; 2604 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2605 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2606 continue; 2607 } 2608 2609 case OPC_EmitConvertToTarget: { 2610 // Convert from IMM/FPIMM to target version. 2611 unsigned RecNo = MatcherTable[MatcherIndex++]; 2612 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2613 SDValue Imm = RecordedNodes[RecNo].first; 2614 2615 if (Imm->getOpcode() == ISD::Constant) { 2616 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2617 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2618 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2619 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2620 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2621 } 2622 2623 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2624 continue; 2625 } 2626 2627 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2628 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2629 // These are space-optimized forms of OPC_EmitMergeInputChains. 2630 assert(InputChain.getNode() == 0 && 2631 "EmitMergeInputChains should be the first chain producing node"); 2632 assert(ChainNodesMatched.empty() && 2633 "Should only have one EmitMergeInputChains per match"); 2634 2635 // Read all of the chained nodes. 2636 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2637 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2638 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2639 2640 // FIXME: What if other value results of the node have uses not matched 2641 // by this pattern? 2642 if (ChainNodesMatched.back() != NodeToMatch && 2643 !RecordedNodes[RecNo].first.hasOneUse()) { 2644 ChainNodesMatched.clear(); 2645 break; 2646 } 2647 2648 // Merge the input chains if they are not intra-pattern references. 2649 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2650 2651 if (InputChain.getNode() == 0) 2652 break; // Failed to merge. 2653 continue; 2654 } 2655 2656 case OPC_EmitMergeInputChains: { 2657 assert(InputChain.getNode() == 0 && 2658 "EmitMergeInputChains should be the first chain producing node"); 2659 // This node gets a list of nodes we matched in the input that have 2660 // chains. We want to token factor all of the input chains to these nodes 2661 // together. However, if any of the input chains is actually one of the 2662 // nodes matched in this pattern, then we have an intra-match reference. 2663 // Ignore these because the newly token factored chain should not refer to 2664 // the old nodes. 2665 unsigned NumChains = MatcherTable[MatcherIndex++]; 2666 assert(NumChains != 0 && "Can't TF zero chains"); 2667 2668 assert(ChainNodesMatched.empty() && 2669 "Should only have one EmitMergeInputChains per match"); 2670 2671 // Read all of the chained nodes. 2672 for (unsigned i = 0; i != NumChains; ++i) { 2673 unsigned RecNo = MatcherTable[MatcherIndex++]; 2674 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2675 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2676 2677 // FIXME: What if other value results of the node have uses not matched 2678 // by this pattern? 2679 if (ChainNodesMatched.back() != NodeToMatch && 2680 !RecordedNodes[RecNo].first.hasOneUse()) { 2681 ChainNodesMatched.clear(); 2682 break; 2683 } 2684 } 2685 2686 // If the inner loop broke out, the match fails. 2687 if (ChainNodesMatched.empty()) 2688 break; 2689 2690 // Merge the input chains if they are not intra-pattern references. 2691 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2692 2693 if (InputChain.getNode() == 0) 2694 break; // Failed to merge. 2695 2696 continue; 2697 } 2698 2699 case OPC_EmitCopyToReg: { 2700 unsigned RecNo = MatcherTable[MatcherIndex++]; 2701 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2702 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2703 2704 if (InputChain.getNode() == 0) 2705 InputChain = CurDAG->getEntryNode(); 2706 2707 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2708 DestPhysReg, RecordedNodes[RecNo].first, 2709 InputGlue); 2710 2711 InputGlue = InputChain.getValue(1); 2712 continue; 2713 } 2714 2715 case OPC_EmitNodeXForm: { 2716 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2717 unsigned RecNo = MatcherTable[MatcherIndex++]; 2718 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2719 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2720 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2721 continue; 2722 } 2723 2724 case OPC_EmitNode: 2725 case OPC_MorphNodeTo: { 2726 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2727 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2728 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2729 // Get the result VT list. 2730 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2731 SmallVector<EVT, 4> VTs; 2732 for (unsigned i = 0; i != NumVTs; ++i) { 2733 MVT::SimpleValueType VT = 2734 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2735 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2736 VTs.push_back(VT); 2737 } 2738 2739 if (EmitNodeInfo & OPFL_Chain) 2740 VTs.push_back(MVT::Other); 2741 if (EmitNodeInfo & OPFL_GlueOutput) 2742 VTs.push_back(MVT::Glue); 2743 2744 // This is hot code, so optimize the two most common cases of 1 and 2 2745 // results. 2746 SDVTList VTList; 2747 if (VTs.size() == 1) 2748 VTList = CurDAG->getVTList(VTs[0]); 2749 else if (VTs.size() == 2) 2750 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2751 else 2752 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2753 2754 // Get the operand list. 2755 unsigned NumOps = MatcherTable[MatcherIndex++]; 2756 SmallVector<SDValue, 8> Ops; 2757 for (unsigned i = 0; i != NumOps; ++i) { 2758 unsigned RecNo = MatcherTable[MatcherIndex++]; 2759 if (RecNo & 128) 2760 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2761 2762 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2763 Ops.push_back(RecordedNodes[RecNo].first); 2764 } 2765 2766 // If there are variadic operands to add, handle them now. 2767 if (EmitNodeInfo & OPFL_VariadicInfo) { 2768 // Determine the start index to copy from. 2769 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2770 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2771 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2772 "Invalid variadic node"); 2773 // Copy all of the variadic operands, not including a potential glue 2774 // input. 2775 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2776 i != e; ++i) { 2777 SDValue V = NodeToMatch->getOperand(i); 2778 if (V.getValueType() == MVT::Glue) break; 2779 Ops.push_back(V); 2780 } 2781 } 2782 2783 // If this has chain/glue inputs, add them. 2784 if (EmitNodeInfo & OPFL_Chain) 2785 Ops.push_back(InputChain); 2786 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2787 Ops.push_back(InputGlue); 2788 2789 // Create the node. 2790 SDNode *Res = 0; 2791 if (Opcode != OPC_MorphNodeTo) { 2792 // If this is a normal EmitNode command, just create the new node and 2793 // add the results to the RecordedNodes list. 2794 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2795 VTList, Ops.data(), Ops.size()); 2796 2797 // Add all the non-glue/non-chain results to the RecordedNodes list. 2798 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2799 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2800 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2801 (SDNode*) 0)); 2802 } 2803 2804 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 2805 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2806 EmitNodeInfo); 2807 } else { 2808 // NodeToMatch was eliminated by CSE when the target changed the DAG. 2809 // We will visit the equivalent node later. 2810 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 2811 return 0; 2812 } 2813 2814 // If the node had chain/glue results, update our notion of the current 2815 // chain and glue. 2816 if (EmitNodeInfo & OPFL_GlueOutput) { 2817 InputGlue = SDValue(Res, VTs.size()-1); 2818 if (EmitNodeInfo & OPFL_Chain) 2819 InputChain = SDValue(Res, VTs.size()-2); 2820 } else if (EmitNodeInfo & OPFL_Chain) 2821 InputChain = SDValue(Res, VTs.size()-1); 2822 2823 // If the OPFL_MemRefs glue is set on this node, slap all of the 2824 // accumulated memrefs onto it. 2825 // 2826 // FIXME: This is vastly incorrect for patterns with multiple outputs 2827 // instructions that access memory and for ComplexPatterns that match 2828 // loads. 2829 if (EmitNodeInfo & OPFL_MemRefs) { 2830 // Only attach load or store memory operands if the generated 2831 // instruction may load or store. 2832 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2833 bool mayLoad = MCID.mayLoad(); 2834 bool mayStore = MCID.mayStore(); 2835 2836 unsigned NumMemRefs = 0; 2837 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2838 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2839 if ((*I)->isLoad()) { 2840 if (mayLoad) 2841 ++NumMemRefs; 2842 } else if ((*I)->isStore()) { 2843 if (mayStore) 2844 ++NumMemRefs; 2845 } else { 2846 ++NumMemRefs; 2847 } 2848 } 2849 2850 MachineSDNode::mmo_iterator MemRefs = 2851 MF->allocateMemRefsArray(NumMemRefs); 2852 2853 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 2854 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2855 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2856 if ((*I)->isLoad()) { 2857 if (mayLoad) 2858 *MemRefsPos++ = *I; 2859 } else if ((*I)->isStore()) { 2860 if (mayStore) 2861 *MemRefsPos++ = *I; 2862 } else { 2863 *MemRefsPos++ = *I; 2864 } 2865 } 2866 2867 cast<MachineSDNode>(Res) 2868 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 2869 } 2870 2871 DEBUG(errs() << " " 2872 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2873 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2874 2875 // If this was a MorphNodeTo then we're completely done! 2876 if (Opcode == OPC_MorphNodeTo) { 2877 // Update chain and glue uses. 2878 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2879 InputGlue, GlueResultNodesMatched, true); 2880 return Res; 2881 } 2882 2883 continue; 2884 } 2885 2886 case OPC_MarkGlueResults: { 2887 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2888 2889 // Read and remember all the glue-result nodes. 2890 for (unsigned i = 0; i != NumNodes; ++i) { 2891 unsigned RecNo = MatcherTable[MatcherIndex++]; 2892 if (RecNo & 128) 2893 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2894 2895 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2896 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2897 } 2898 continue; 2899 } 2900 2901 case OPC_CompleteMatch: { 2902 // The match has been completed, and any new nodes (if any) have been 2903 // created. Patch up references to the matched dag to use the newly 2904 // created nodes. 2905 unsigned NumResults = MatcherTable[MatcherIndex++]; 2906 2907 for (unsigned i = 0; i != NumResults; ++i) { 2908 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2909 if (ResSlot & 128) 2910 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2911 2912 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2913 SDValue Res = RecordedNodes[ResSlot].first; 2914 2915 assert(i < NodeToMatch->getNumValues() && 2916 NodeToMatch->getValueType(i) != MVT::Other && 2917 NodeToMatch->getValueType(i) != MVT::Glue && 2918 "Invalid number of results to complete!"); 2919 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2920 NodeToMatch->getValueType(i) == MVT::iPTR || 2921 Res.getValueType() == MVT::iPTR || 2922 NodeToMatch->getValueType(i).getSizeInBits() == 2923 Res.getValueType().getSizeInBits()) && 2924 "invalid replacement"); 2925 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2926 } 2927 2928 // If the root node defines glue, add it to the glue nodes to update list. 2929 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2930 GlueResultNodesMatched.push_back(NodeToMatch); 2931 2932 // Update chain and glue uses. 2933 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2934 InputGlue, GlueResultNodesMatched, false); 2935 2936 assert(NodeToMatch->use_empty() && 2937 "Didn't replace all uses of the node?"); 2938 2939 // FIXME: We just return here, which interacts correctly with SelectRoot 2940 // above. We should fix this to not return an SDNode* anymore. 2941 return 0; 2942 } 2943 } 2944 2945 // If the code reached this point, then the match failed. See if there is 2946 // another child to try in the current 'Scope', otherwise pop it until we 2947 // find a case to check. 2948 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2949 DEBUG(++NumDAGIselRetries); 2950 while (1) { 2951 if (MatchScopes.empty()) { 2952 CannotYetSelect(NodeToMatch); 2953 return 0; 2954 } 2955 2956 // Restore the interpreter state back to the point where the scope was 2957 // formed. 2958 MatchScope &LastScope = MatchScopes.back(); 2959 RecordedNodes.resize(LastScope.NumRecordedNodes); 2960 NodeStack.clear(); 2961 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2962 N = NodeStack.back(); 2963 2964 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2965 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2966 MatcherIndex = LastScope.FailIndex; 2967 2968 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2969 2970 InputChain = LastScope.InputChain; 2971 InputGlue = LastScope.InputGlue; 2972 if (!LastScope.HasChainNodesMatched) 2973 ChainNodesMatched.clear(); 2974 if (!LastScope.HasGlueResultNodesMatched) 2975 GlueResultNodesMatched.clear(); 2976 2977 // Check to see what the offset is at the new MatcherIndex. If it is zero 2978 // we have reached the end of this scope, otherwise we have another child 2979 // in the current scope to try. 2980 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2981 if (NumToSkip & 128) 2982 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2983 2984 // If we have another child in this scope to match, update FailIndex and 2985 // try it. 2986 if (NumToSkip != 0) { 2987 LastScope.FailIndex = MatcherIndex+NumToSkip; 2988 break; 2989 } 2990 2991 // End of this scope, pop it and try the next child in the containing 2992 // scope. 2993 MatchScopes.pop_back(); 2994 } 2995 } 2996} 2997 2998 2999 3000void SelectionDAGISel::CannotYetSelect(SDNode *N) { 3001 std::string msg; 3002 raw_string_ostream Msg(msg); 3003 Msg << "Cannot select: "; 3004 3005 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 3006 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 3007 N->getOpcode() != ISD::INTRINSIC_VOID) { 3008 N->printrFull(Msg, CurDAG); 3009 Msg << "\nIn function: " << MF->getName(); 3010 } else { 3011 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 3012 unsigned iid = 3013 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 3014 if (iid < Intrinsic::num_intrinsics) 3015 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 3016 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 3017 Msg << "target intrinsic %" << TII->getName(iid); 3018 else 3019 Msg << "unknown intrinsic #" << iid; 3020 } 3021 report_fatal_error(Msg.str()); 3022} 3023 3024char SelectionDAGISel::ID = 0; 3025