SelectionDAGISel.cpp revision 19e57025d458d3cb50804fd821fd89b868a819bd
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/CodeGen/FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/Module.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetIntrinsicInfo.h" 42#include "llvm/Target/TargetInstrInfo.h" 43#include "llvm/Target/TargetLowering.h" 44#include "llvm/Target/TargetMachine.h" 45#include "llvm/Target/TargetOptions.h" 46#include "llvm/Support/Compiler.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/Timer.h" 50#include "llvm/Support/raw_ostream.h" 51#include "llvm/ADT/Statistic.h" 52#include <algorithm> 53using namespace llvm; 54 55STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 56STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 57 58static cl::opt<bool> 59EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 60 cl::desc("Enable verbose messages in the \"fast\" " 61 "instruction selector")); 62static cl::opt<bool> 63EnableFastISelAbort("fast-isel-abort", cl::Hidden, 64 cl::desc("Enable abort calls when \"fast\" instruction fails")); 65 66#ifndef NDEBUG 67static cl::opt<bool> 68ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 69 cl::desc("Pop up a window to show dags before the first " 70 "dag combine pass")); 71static cl::opt<bool> 72ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 73 cl::desc("Pop up a window to show dags before legalize types")); 74static cl::opt<bool> 75ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 76 cl::desc("Pop up a window to show dags before legalize")); 77static cl::opt<bool> 78ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 79 cl::desc("Pop up a window to show dags before the second " 80 "dag combine pass")); 81static cl::opt<bool> 82ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 83 cl::desc("Pop up a window to show dags before the post legalize types" 84 " dag combine pass")); 85static cl::opt<bool> 86ViewISelDAGs("view-isel-dags", cl::Hidden, 87 cl::desc("Pop up a window to show isel dags as they are selected")); 88static cl::opt<bool> 89ViewSchedDAGs("view-sched-dags", cl::Hidden, 90 cl::desc("Pop up a window to show sched dags as they are processed")); 91static cl::opt<bool> 92ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 93 cl::desc("Pop up a window to show SUnit dags after they are processed")); 94#else 95static const bool ViewDAGCombine1 = false, 96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 97 ViewDAGCombine2 = false, 98 ViewDAGCombineLT = false, 99 ViewISelDAGs = false, ViewSchedDAGs = false, 100 ViewSUnitDAGs = false; 101#endif 102 103//===---------------------------------------------------------------------===// 104/// 105/// RegisterScheduler class - Track the registration of instruction schedulers. 106/// 107//===---------------------------------------------------------------------===// 108MachinePassRegistry RegisterScheduler::Registry; 109 110//===---------------------------------------------------------------------===// 111/// 112/// ISHeuristic command line option for instruction schedulers. 113/// 114//===---------------------------------------------------------------------===// 115static cl::opt<RegisterScheduler::FunctionPassCtor, false, 116 RegisterPassParser<RegisterScheduler> > 117ISHeuristic("pre-RA-sched", 118 cl::init(&createDefaultScheduler), 119 cl::desc("Instruction schedulers available (before register" 120 " allocation):")); 121 122static RegisterScheduler 123defaultListDAGScheduler("default", "Best scheduler for the target", 124 createDefaultScheduler); 125 126namespace llvm { 127 //===--------------------------------------------------------------------===// 128 /// createDefaultScheduler - This creates an instruction scheduler appropriate 129 /// for the target. 130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 131 CodeGenOpt::Level OptLevel) { 132 const TargetLowering &TLI = IS->getTargetLowering(); 133 134 if (OptLevel == CodeGenOpt::None) 135 return createSourceListDAGScheduler(IS, OptLevel); 136 if (TLI.getSchedulingPreference() == Sched::Latency) 137 return createTDListDAGScheduler(IS, OptLevel); 138 if (TLI.getSchedulingPreference() == Sched::RegPressure) 139 return createBURRListDAGScheduler(IS, OptLevel); 140 if (TLI.getSchedulingPreference() == Sched::Hybrid) 141 return createHybridListDAGScheduler(IS, OptLevel); 142 assert(TLI.getSchedulingPreference() == Sched::ILP && 143 "Unknown sched type!"); 144 return createILPListDAGScheduler(IS, OptLevel); 145 } 146} 147 148// EmitInstrWithCustomInserter - This method should be implemented by targets 149// that mark instructions with the 'usesCustomInserter' flag. These 150// instructions are special in various ways, which require special support to 151// insert. The specified MachineInstr is created but not inserted into any 152// basic blocks, and this method is called to expand it into a sequence of 153// instructions, potentially also creating new basic blocks and control flow. 154// When new basic blocks are inserted and the edges from MBB to its successors 155// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 156// DenseMap. 157MachineBasicBlock * 158TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 159 MachineBasicBlock *MBB) const { 160#ifndef NDEBUG 161 dbgs() << "If a target marks an instruction with " 162 "'usesCustomInserter', it must implement " 163 "TargetLowering::EmitInstrWithCustomInserter!"; 164#endif 165 llvm_unreachable(0); 166 return 0; 167} 168 169//===----------------------------------------------------------------------===// 170// SelectionDAGISel code 171//===----------------------------------------------------------------------===// 172 173SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) : 174 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 175 FuncInfo(new FunctionLoweringInfo(TLI)), 176 CurDAG(new SelectionDAG(tm)), 177 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 178 GFI(), 179 OptLevel(OL), 180 DAGSize(0) { 181 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 182 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 183 } 184 185SelectionDAGISel::~SelectionDAGISel() { 186 delete SDB; 187 delete CurDAG; 188 delete FuncInfo; 189} 190 191void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 192 AU.addRequired<AliasAnalysis>(); 193 AU.addPreserved<AliasAnalysis>(); 194 AU.addRequired<GCModuleInfo>(); 195 AU.addPreserved<GCModuleInfo>(); 196 MachineFunctionPass::getAnalysisUsage(AU); 197} 198 199/// FunctionCallsSetJmp - Return true if the function has a call to setjmp or 200/// other function that gcc recognizes as "returning twice". This is used to 201/// limit code-gen optimizations on the machine function. 202/// 203/// FIXME: Remove after <rdar://problem/8031714> is fixed. 204static bool FunctionCallsSetJmp(const Function *F) { 205 const Module *M = F->getParent(); 206 static const char *ReturnsTwiceFns[] = { 207 "setjmp", 208 "sigsetjmp", 209 "setjmp_syscall", 210 "savectx", 211 "qsetjmp", 212 "vfork", 213 "getcontext" 214 }; 215#define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *) 216 217 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I) 218 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) { 219 if (!Callee->use_empty()) 220 for (Value::const_use_iterator 221 I = Callee->use_begin(), E = Callee->use_end(); 222 I != E; ++I) 223 if (const CallInst *CI = dyn_cast<CallInst>(*I)) 224 if (CI->getParent()->getParent() == F) 225 return true; 226 } 227 228 return false; 229#undef NUM_RETURNS_TWICE_FNS 230} 231 232bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 233 // Do some sanity-checking on the command-line options. 234 assert((!EnableFastISelVerbose || EnableFastISel) && 235 "-fast-isel-verbose requires -fast-isel"); 236 assert((!EnableFastISelAbort || EnableFastISel) && 237 "-fast-isel-abort requires -fast-isel"); 238 239 const Function &Fn = *mf.getFunction(); 240 const TargetInstrInfo &TII = *TM.getInstrInfo(); 241 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 242 243 MF = &mf; 244 RegInfo = &MF->getRegInfo(); 245 AA = &getAnalysis<AliasAnalysis>(); 246 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 247 248 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 249 250 CurDAG->init(*MF); 251 FuncInfo->set(Fn, *MF); 252 SDB->init(GFI, *AA); 253 254 SelectAllBasicBlocks(Fn); 255 256 // If the first basic block in the function has live ins that need to be 257 // copied into vregs, emit the copies into the top of the block before 258 // emitting the code for the block. 259 MachineBasicBlock *EntryMBB = MF->begin(); 260 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 261 262 DenseMap<unsigned, unsigned> LiveInMap; 263 if (!FuncInfo->ArgDbgValues.empty()) 264 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 265 E = RegInfo->livein_end(); LI != E; ++LI) 266 if (LI->second) 267 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 268 269 // Insert DBG_VALUE instructions for function arguments to the entry block. 270 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 271 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 272 unsigned Reg = MI->getOperand(0).getReg(); 273 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 274 EntryMBB->insert(EntryMBB->begin(), MI); 275 else { 276 MachineInstr *Def = RegInfo->getVRegDef(Reg); 277 MachineBasicBlock::iterator InsertPos = Def; 278 // FIXME: VR def may not be in entry block. 279 Def->getParent()->insert(llvm::next(InsertPos), MI); 280 } 281 282 // If Reg is live-in then update debug info to track its copy in a vreg. 283 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 284 if (LDI != LiveInMap.end()) { 285 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 286 MachineBasicBlock::iterator InsertPos = Def; 287 const MDNode *Variable = 288 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 289 unsigned Offset = MI->getOperand(1).getImm(); 290 // Def is never a terminator here, so it is ok to increment InsertPos. 291 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 292 TII.get(TargetOpcode::DBG_VALUE)) 293 .addReg(LDI->second, RegState::Debug) 294 .addImm(Offset).addMetadata(Variable); 295 296 // If this vreg is directly copied into an exported register then 297 // that COPY instructions also need DBG_VALUE, if it is the only 298 // user of LDI->second. 299 MachineInstr *CopyUseMI = NULL; 300 for (MachineRegisterInfo::use_iterator 301 UI = RegInfo->use_begin(LDI->second); 302 MachineInstr *UseMI = UI.skipInstruction();) { 303 if (UseMI->isDebugValue()) continue; 304 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 305 CopyUseMI = UseMI; continue; 306 } 307 // Otherwise this is another use or second copy use. 308 CopyUseMI = NULL; break; 309 } 310 if (CopyUseMI) { 311 MachineInstr *NewMI = 312 BuildMI(*MF, CopyUseMI->getDebugLoc(), 313 TII.get(TargetOpcode::DBG_VALUE)) 314 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 315 .addImm(Offset).addMetadata(Variable); 316 EntryMBB->insertAfter(CopyUseMI, NewMI); 317 } 318 } 319 } 320 321 // Determine if there are any calls in this machine function. 322 MachineFrameInfo *MFI = MF->getFrameInfo(); 323 if (!MFI->hasCalls()) { 324 for (MachineFunction::const_iterator 325 I = MF->begin(), E = MF->end(); I != E; ++I) { 326 const MachineBasicBlock *MBB = I; 327 for (MachineBasicBlock::const_iterator 328 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 329 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode()); 330 331 // Operand 1 of an inline asm instruction indicates whether the asm 332 // needs stack or not. 333 if ((II->isInlineAsm() && II->getOperand(1).getImm()) || 334 (TID.isCall() && !TID.isReturn())) { 335 MFI->setHasCalls(true); 336 goto done; 337 } 338 } 339 } 340 done:; 341 } 342 343 // Determine if there is a call to setjmp in the machine function. 344 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn)); 345 346 // Replace forward-declared registers with the registers containing 347 // the desired value. 348 MachineRegisterInfo &MRI = MF->getRegInfo(); 349 for (DenseMap<unsigned, unsigned>::iterator 350 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 351 I != E; ++I) { 352 unsigned From = I->first; 353 unsigned To = I->second; 354 // If To is also scheduled to be replaced, find what its ultimate 355 // replacement is. 356 for (;;) { 357 DenseMap<unsigned, unsigned>::iterator J = 358 FuncInfo->RegFixups.find(To); 359 if (J == E) break; 360 To = J->second; 361 } 362 // Replace it. 363 MRI.replaceRegWith(From, To); 364 } 365 366 // Release function-specific state. SDB and CurDAG are already cleared 367 // at this point. 368 FuncInfo->clear(); 369 370 return true; 371} 372 373void 374SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 375 BasicBlock::const_iterator End, 376 bool &HadTailCall) { 377 // Lower all of the non-terminator instructions. If a call is emitted 378 // as a tail call, cease emitting nodes for this block. Terminators 379 // are handled below. 380 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 381 SDB->visit(*I); 382 383 // Make sure the root of the DAG is up-to-date. 384 CurDAG->setRoot(SDB->getControlRoot()); 385 HadTailCall = SDB->HasTailCall; 386 SDB->clear(); 387 388 // Final step, emit the lowered DAG as machine code. 389 CodeGenAndEmitDAG(); 390} 391 392void SelectionDAGISel::ComputeLiveOutVRegInfo() { 393 SmallPtrSet<SDNode*, 128> VisitedNodes; 394 SmallVector<SDNode*, 128> Worklist; 395 396 Worklist.push_back(CurDAG->getRoot().getNode()); 397 398 APInt Mask; 399 APInt KnownZero; 400 APInt KnownOne; 401 402 do { 403 SDNode *N = Worklist.pop_back_val(); 404 405 // If we've already seen this node, ignore it. 406 if (!VisitedNodes.insert(N)) 407 continue; 408 409 // Otherwise, add all chain operands to the worklist. 410 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 411 if (N->getOperand(i).getValueType() == MVT::Other) 412 Worklist.push_back(N->getOperand(i).getNode()); 413 414 // If this is a CopyToReg with a vreg dest, process it. 415 if (N->getOpcode() != ISD::CopyToReg) 416 continue; 417 418 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 419 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 420 continue; 421 422 // Ignore non-scalar or non-integer values. 423 SDValue Src = N->getOperand(2); 424 EVT SrcVT = Src.getValueType(); 425 if (!SrcVT.isInteger() || SrcVT.isVector()) 426 continue; 427 428 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 429 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 430 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 431 432 // Only install this information if it tells us something. 433 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 434 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 435 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 436 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 437 FunctionLoweringInfo::LiveOutInfo &LOI = 438 FuncInfo->LiveOutRegInfo[DestReg]; 439 LOI.NumSignBits = NumSignBits; 440 LOI.KnownOne = KnownOne; 441 LOI.KnownZero = KnownZero; 442 } 443 } while (!Worklist.empty()); 444} 445 446void SelectionDAGISel::CodeGenAndEmitDAG() { 447 std::string GroupName; 448 if (TimePassesIsEnabled) 449 GroupName = "Instruction Selection and Scheduling"; 450 std::string BlockName; 451 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 452 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 453 ViewSUnitDAGs) 454 BlockName = MF->getFunction()->getNameStr() + ":" + 455 FuncInfo->MBB->getBasicBlock()->getNameStr(); 456 457 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump()); 458 459 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 460 461 // Run the DAG combiner in pre-legalize mode. 462 { 463 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 464 CurDAG->Combine(Unrestricted, *AA, OptLevel); 465 } 466 467 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump()); 468 469 // Second step, hack on the DAG until it only uses operations and types that 470 // the target supports. 471 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 472 BlockName); 473 474 bool Changed; 475 { 476 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 477 Changed = CurDAG->LegalizeTypes(); 478 } 479 480 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump()); 481 482 if (Changed) { 483 if (ViewDAGCombineLT) 484 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 485 486 // Run the DAG combiner in post-type-legalize mode. 487 { 488 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 489 TimePassesIsEnabled); 490 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 491 } 492 493 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"; 494 CurDAG->dump()); 495 } 496 497 { 498 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 499 Changed = CurDAG->LegalizeVectors(); 500 } 501 502 if (Changed) { 503 { 504 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 505 CurDAG->LegalizeTypes(); 506 } 507 508 if (ViewDAGCombineLT) 509 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 510 511 // Run the DAG combiner in post-type-legalize mode. 512 { 513 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 514 TimePassesIsEnabled); 515 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 516 } 517 518 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"; 519 CurDAG->dump()); 520 } 521 522 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 523 524 { 525 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 526 CurDAG->Legalize(OptLevel); 527 } 528 529 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump()); 530 531 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 532 533 // Run the DAG combiner in post-legalize mode. 534 { 535 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 536 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 537 } 538 539 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump()); 540 541 if (OptLevel != CodeGenOpt::None) 542 ComputeLiveOutVRegInfo(); 543 544 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 545 546 // Third, instruction select all of the operations to machine code, adding the 547 // code to the MachineBasicBlock. 548 { 549 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 550 DoInstructionSelection(); 551 } 552 553 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump()); 554 555 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 556 557 // Schedule machine code. 558 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 559 { 560 NamedRegionTimer T("Instruction Scheduling", GroupName, 561 TimePassesIsEnabled); 562 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt); 563 } 564 565 if (ViewSUnitDAGs) Scheduler->viewGraph(); 566 567 // Emit machine code to BB. This can change 'BB' to the last block being 568 // inserted into. 569 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 570 { 571 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 572 573 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(); 574 FuncInfo->InsertPt = Scheduler->InsertPos; 575 } 576 577 // If the block was split, make sure we update any references that are used to 578 // update PHI nodes later on. 579 if (FirstMBB != LastMBB) 580 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 581 582 // Free the scheduler state. 583 { 584 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 585 TimePassesIsEnabled); 586 delete Scheduler; 587 } 588 589 // Free the SelectionDAG state, now that we're finished with it. 590 CurDAG->clear(); 591} 592 593void SelectionDAGISel::DoInstructionSelection() { 594 DEBUG(errs() << "===== Instruction selection begins:\n"); 595 596 PreprocessISelDAG(); 597 598 // Select target instructions for the DAG. 599 { 600 // Number all nodes with a topological order and set DAGSize. 601 DAGSize = CurDAG->AssignTopologicalOrder(); 602 603 // Create a dummy node (which is not added to allnodes), that adds 604 // a reference to the root node, preventing it from being deleted, 605 // and tracking any changes of the root. 606 HandleSDNode Dummy(CurDAG->getRoot()); 607 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 608 ++ISelPosition; 609 610 // The AllNodes list is now topological-sorted. Visit the 611 // nodes by starting at the end of the list (the root of the 612 // graph) and preceding back toward the beginning (the entry 613 // node). 614 while (ISelPosition != CurDAG->allnodes_begin()) { 615 SDNode *Node = --ISelPosition; 616 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 617 // but there are currently some corner cases that it misses. Also, this 618 // makes it theoretically possible to disable the DAGCombiner. 619 if (Node->use_empty()) 620 continue; 621 622 SDNode *ResNode = Select(Node); 623 624 // FIXME: This is pretty gross. 'Select' should be changed to not return 625 // anything at all and this code should be nuked with a tactical strike. 626 627 // If node should not be replaced, continue with the next one. 628 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 629 continue; 630 // Replace node. 631 if (ResNode) 632 ReplaceUses(Node, ResNode); 633 634 // If after the replacement this node is not used any more, 635 // remove this dead node. 636 if (Node->use_empty()) { // Don't delete EntryToken, etc. 637 ISelUpdater ISU(ISelPosition); 638 CurDAG->RemoveDeadNode(Node, &ISU); 639 } 640 } 641 642 CurDAG->setRoot(Dummy.getValue()); 643 } 644 645 DEBUG(errs() << "===== Instruction selection ends:\n"); 646 647 PostprocessISelDAG(); 648} 649 650/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 651/// do other setup for EH landing-pad blocks. 652void SelectionDAGISel::PrepareEHLandingPad() { 653 // Add a label to mark the beginning of the landing pad. Deletion of the 654 // landing pad can thus be detected via the MachineModuleInfo. 655 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB); 656 657 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 658 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 659 .addSym(Label); 660 661 // Mark exception register as live in. 662 unsigned Reg = TLI.getExceptionAddressRegister(); 663 if (Reg) FuncInfo->MBB->addLiveIn(Reg); 664 665 // Mark exception selector register as live in. 666 Reg = TLI.getExceptionSelectorRegister(); 667 if (Reg) FuncInfo->MBB->addLiveIn(Reg); 668 669 // FIXME: Hack around an exception handling flaw (PR1508): the personality 670 // function and list of typeids logically belong to the invoke (or, if you 671 // like, the basic block containing the invoke), and need to be associated 672 // with it in the dwarf exception handling tables. Currently however the 673 // information is provided by an intrinsic (eh.selector) that can be moved 674 // to unexpected places by the optimizers: if the unwind edge is critical, 675 // then breaking it can result in the intrinsics being in the successor of 676 // the landing pad, not the landing pad itself. This results 677 // in exceptions not being caught because no typeids are associated with 678 // the invoke. This may not be the only way things can go wrong, but it 679 // is the only way we try to work around for the moment. 680 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock(); 681 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 682 683 if (Br && Br->isUnconditional()) { // Critical edge? 684 BasicBlock::const_iterator I, E; 685 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 686 if (isa<EHSelectorInst>(I)) 687 break; 688 689 if (I == E) 690 // No catch info found - try to extract some from the successor. 691 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 692 } 693} 694 695 696 697 698bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI, 699 FastISel *FastIS) { 700 // Don't try to fold volatile loads. Target has to deal with alignment 701 // constraints. 702 if (LI->isVolatile()) return false; 703 704 // Figure out which vreg this is going into. 705 unsigned LoadReg = FastIS->getRegForValue(LI); 706 assert(LoadReg && "Load isn't already assigned a vreg? "); 707 708 // Check to see what the uses of this vreg are. If it has no uses, or more 709 // than one use (at the machine instr level) then we can't fold it. 710 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg); 711 if (RI == RegInfo->reg_end()) 712 return false; 713 714 // See if there is exactly one use of the vreg. If there are multiple uses, 715 // then the instruction got lowered to multiple machine instructions or the 716 // use of the loaded value ended up being multiple operands of the result, in 717 // either case, we can't fold this. 718 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI; 719 if (PostRI != RegInfo->reg_end()) 720 return false; 721 722 assert(RI.getOperand().isUse() && 723 "The only use of the vreg must be a use, we haven't emitted the def!"); 724 725 // Ask the target to try folding the load. 726 return FastIS->TryToFoldLoad(&*RI, RI.getOperandNo(), LI); 727} 728 729 730 731 732void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 733 // Initialize the Fast-ISel state, if needed. 734 FastISel *FastIS = 0; 735 if (EnableFastISel) 736 FastIS = TLI.createFastISel(*FuncInfo); 737 738 // Iterate over all basic blocks in the function. 739 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 740 const BasicBlock *LLVMBB = &*I; 741 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 742 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 743 744 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 745 BasicBlock::const_iterator const End = LLVMBB->end(); 746 BasicBlock::const_iterator BI = End; 747 748 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 749 750 // Setup an EH landing-pad block. 751 if (FuncInfo->MBB->isLandingPad()) 752 PrepareEHLandingPad(); 753 754 // Lower any arguments needed in this block if this is the entry block. 755 if (LLVMBB == &Fn.getEntryBlock()) 756 LowerArguments(LLVMBB); 757 758 // Before doing SelectionDAG ISel, see if FastISel has been requested. 759 if (FastIS) { 760 FastIS->startNewBlock(); 761 762 // Emit code for any incoming arguments. This must happen before 763 // beginning FastISel on the entry block. 764 if (LLVMBB == &Fn.getEntryBlock()) { 765 CurDAG->setRoot(SDB->getControlRoot()); 766 SDB->clear(); 767 CodeGenAndEmitDAG(); 768 769 // If we inserted any instructions at the beginning, make a note of 770 // where they are, so we can be sure to emit subsequent instructions 771 // after them. 772 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 773 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 774 else 775 FastIS->setLastLocalValue(0); 776 } 777 778 // Do FastISel on as many instructions as possible. 779 for (; BI != Begin; --BI) { 780 const Instruction *Inst = llvm::prior(BI); 781 782 // If we no longer require this instruction, skip it. 783 if (!Inst->mayWriteToMemory() && 784 !isa<TerminatorInst>(Inst) && 785 !isa<DbgInfoIntrinsic>(Inst) && 786 !FuncInfo->isExportedInst(Inst)) 787 continue; 788 789 // Bottom-up: reset the insert pos at the top, after any local-value 790 // instructions. 791 FastIS->recomputeInsertPt(); 792 793 // Try to select the instruction with FastISel. 794 if (FastIS->SelectInstruction(Inst)) { 795 // If fast isel succeeded, check to see if there is a single-use 796 // non-volatile load right before the selected instruction, and see if 797 // the load is used by the instruction. If so, try to fold it. 798 const Instruction *BeforeInst = 0; 799 if (Inst != Begin) 800 BeforeInst = llvm::prior(llvm::prior(BI)); 801 if (BeforeInst && isa<LoadInst>(BeforeInst) && 802 BeforeInst->hasOneUse() && *BeforeInst->use_begin() == Inst && 803 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), FastIS)) { 804 // If we succeeded, don't re-select the load. 805 --BI; 806 } 807 continue; 808 } 809 810 // Then handle certain instructions as single-LLVM-Instruction blocks. 811 if (isa<CallInst>(Inst)) { 812 ++NumFastIselFailures; 813 if (EnableFastISelVerbose || EnableFastISelAbort) { 814 dbgs() << "FastISel missed call: "; 815 Inst->dump(); 816 } 817 818 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 819 unsigned &R = FuncInfo->ValueMap[Inst]; 820 if (!R) 821 R = FuncInfo->CreateRegs(Inst->getType()); 822 } 823 824 bool HadTailCall = false; 825 SelectBasicBlock(Inst, BI, HadTailCall); 826 827 // If the call was emitted as a tail call, we're done with the block. 828 if (HadTailCall) { 829 --BI; 830 break; 831 } 832 833 continue; 834 } 835 836 // Otherwise, give up on FastISel for the rest of the block. 837 // For now, be a little lenient about non-branch terminators. 838 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) { 839 ++NumFastIselFailures; 840 if (EnableFastISelVerbose || EnableFastISelAbort) { 841 dbgs() << "FastISel miss: "; 842 Inst->dump(); 843 } 844 if (EnableFastISelAbort) 845 // The "fast" selector couldn't handle something and bailed. 846 // For the purpose of debugging, just abort. 847 llvm_unreachable("FastISel didn't select the entire block"); 848 } 849 break; 850 } 851 852 FastIS->recomputeInsertPt(); 853 } 854 855 // Run SelectionDAG instruction selection on the remainder of the block 856 // not handled by FastISel. If FastISel is not run, this is the entire 857 // block. 858 bool HadTailCall; 859 SelectBasicBlock(Begin, BI, HadTailCall); 860 861 FinishBasicBlock(); 862 FuncInfo->PHINodesToUpdate.clear(); 863 } 864 865 delete FastIS; 866} 867 868void 869SelectionDAGISel::FinishBasicBlock() { 870 871 DEBUG(dbgs() << "Total amount of phi nodes to update: " 872 << FuncInfo->PHINodesToUpdate.size() << "\n"; 873 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 874 dbgs() << "Node " << i << " : (" 875 << FuncInfo->PHINodesToUpdate[i].first 876 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 877 878 // Next, now that we know what the last MBB the LLVM BB expanded is, update 879 // PHI nodes in successors. 880 if (SDB->SwitchCases.empty() && 881 SDB->JTCases.empty() && 882 SDB->BitTestCases.empty()) { 883 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 884 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 885 assert(PHI->isPHI() && 886 "This is not a machine PHI node that we are updating!"); 887 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 888 continue; 889 PHI->addOperand( 890 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 891 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 892 } 893 return; 894 } 895 896 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 897 // Lower header first, if it wasn't already lowered 898 if (!SDB->BitTestCases[i].Emitted) { 899 // Set the current basic block to the mbb we wish to insert the code into 900 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 901 FuncInfo->InsertPt = FuncInfo->MBB->end(); 902 // Emit the code 903 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 904 CurDAG->setRoot(SDB->getRoot()); 905 SDB->clear(); 906 CodeGenAndEmitDAG(); 907 } 908 909 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 910 // Set the current basic block to the mbb we wish to insert the code into 911 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 912 FuncInfo->InsertPt = FuncInfo->MBB->end(); 913 // Emit the code 914 if (j+1 != ej) 915 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 916 SDB->BitTestCases[i].Reg, 917 SDB->BitTestCases[i].Cases[j], 918 FuncInfo->MBB); 919 else 920 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 921 SDB->BitTestCases[i].Reg, 922 SDB->BitTestCases[i].Cases[j], 923 FuncInfo->MBB); 924 925 926 CurDAG->setRoot(SDB->getRoot()); 927 SDB->clear(); 928 CodeGenAndEmitDAG(); 929 } 930 931 // Update PHI Nodes 932 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 933 pi != pe; ++pi) { 934 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 935 MachineBasicBlock *PHIBB = PHI->getParent(); 936 assert(PHI->isPHI() && 937 "This is not a machine PHI node that we are updating!"); 938 // This is "default" BB. We have two jumps to it. From "header" BB and 939 // from last "case" BB. 940 if (PHIBB == SDB->BitTestCases[i].Default) { 941 PHI->addOperand(MachineOperand:: 942 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 943 false)); 944 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 945 PHI->addOperand(MachineOperand:: 946 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 947 false)); 948 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 949 back().ThisBB)); 950 } 951 // One of "cases" BB. 952 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 953 j != ej; ++j) { 954 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 955 if (cBB->isSuccessor(PHIBB)) { 956 PHI->addOperand(MachineOperand:: 957 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 958 false)); 959 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 960 } 961 } 962 } 963 } 964 SDB->BitTestCases.clear(); 965 966 // If the JumpTable record is filled in, then we need to emit a jump table. 967 // Updating the PHI nodes is tricky in this case, since we need to determine 968 // whether the PHI is a successor of the range check MBB or the jump table MBB 969 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 970 // Lower header first, if it wasn't already lowered 971 if (!SDB->JTCases[i].first.Emitted) { 972 // Set the current basic block to the mbb we wish to insert the code into 973 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 974 FuncInfo->InsertPt = FuncInfo->MBB->end(); 975 // Emit the code 976 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 977 FuncInfo->MBB); 978 CurDAG->setRoot(SDB->getRoot()); 979 SDB->clear(); 980 CodeGenAndEmitDAG(); 981 } 982 983 // Set the current basic block to the mbb we wish to insert the code into 984 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 985 FuncInfo->InsertPt = FuncInfo->MBB->end(); 986 // Emit the code 987 SDB->visitJumpTable(SDB->JTCases[i].second); 988 CurDAG->setRoot(SDB->getRoot()); 989 SDB->clear(); 990 CodeGenAndEmitDAG(); 991 992 // Update PHI Nodes 993 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 994 pi != pe; ++pi) { 995 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 996 MachineBasicBlock *PHIBB = PHI->getParent(); 997 assert(PHI->isPHI() && 998 "This is not a machine PHI node that we are updating!"); 999 // "default" BB. We can go there only from header BB. 1000 if (PHIBB == SDB->JTCases[i].second.Default) { 1001 PHI->addOperand 1002 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1003 false)); 1004 PHI->addOperand 1005 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1006 } 1007 // JT BB. Just iterate over successors here 1008 if (FuncInfo->MBB->isSuccessor(PHIBB)) { 1009 PHI->addOperand 1010 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1011 false)); 1012 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1013 } 1014 } 1015 } 1016 SDB->JTCases.clear(); 1017 1018 // If the switch block involved a branch to one of the actual successors, we 1019 // need to update PHI nodes in that block. 1020 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1021 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1022 assert(PHI->isPHI() && 1023 "This is not a machine PHI node that we are updating!"); 1024 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) { 1025 PHI->addOperand( 1026 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1027 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1028 } 1029 } 1030 1031 // If we generated any switch lowering information, build and codegen any 1032 // additional DAGs necessary. 1033 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1034 // Set the current basic block to the mbb we wish to insert the code into 1035 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1036 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1037 1038 // Determine the unique successors. 1039 SmallVector<MachineBasicBlock *, 2> Succs; 1040 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1041 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1042 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1043 1044 // Emit the code. Note that this could result in ThisBB being split, so 1045 // we need to check for updates. 1046 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1047 CurDAG->setRoot(SDB->getRoot()); 1048 SDB->clear(); 1049 CodeGenAndEmitDAG(); 1050 ThisBB = FuncInfo->MBB; 1051 1052 // Handle any PHI nodes in successors of this chunk, as if we were coming 1053 // from the original BB before switch expansion. Note that PHI nodes can 1054 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1055 // handle them the right number of times. 1056 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1057 FuncInfo->MBB = Succs[i]; 1058 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1059 // FuncInfo->MBB may have been removed from the CFG if a branch was 1060 // constant folded. 1061 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1062 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin(); 1063 Phi != FuncInfo->MBB->end() && Phi->isPHI(); 1064 ++Phi) { 1065 // This value for this PHI node is recorded in PHINodesToUpdate. 1066 for (unsigned pn = 0; ; ++pn) { 1067 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1068 "Didn't find PHI entry!"); 1069 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 1070 Phi->addOperand(MachineOperand:: 1071 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 1072 false)); 1073 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1074 break; 1075 } 1076 } 1077 } 1078 } 1079 } 1080 } 1081 SDB->SwitchCases.clear(); 1082} 1083 1084 1085/// Create the scheduler. If a specific scheduler was specified 1086/// via the SchedulerRegistry, use it, otherwise select the 1087/// one preferred by the target. 1088/// 1089ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1090 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1091 1092 if (!Ctor) { 1093 Ctor = ISHeuristic; 1094 RegisterScheduler::setDefault(Ctor); 1095 } 1096 1097 return Ctor(this, OptLevel); 1098} 1099 1100ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1101 return new ScheduleHazardRecognizer(); 1102} 1103 1104//===----------------------------------------------------------------------===// 1105// Helper functions used by the generated instruction selector. 1106//===----------------------------------------------------------------------===// 1107// Calls to these methods are generated by tblgen. 1108 1109/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1110/// the dag combiner simplified the 255, we still want to match. RHS is the 1111/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1112/// specified in the .td file (e.g. 255). 1113bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1114 int64_t DesiredMaskS) const { 1115 const APInt &ActualMask = RHS->getAPIntValue(); 1116 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1117 1118 // If the actual mask exactly matches, success! 1119 if (ActualMask == DesiredMask) 1120 return true; 1121 1122 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1123 if (ActualMask.intersects(~DesiredMask)) 1124 return false; 1125 1126 // Otherwise, the DAG Combiner may have proven that the value coming in is 1127 // either already zero or is not demanded. Check for known zero input bits. 1128 APInt NeededMask = DesiredMask & ~ActualMask; 1129 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1130 return true; 1131 1132 // TODO: check to see if missing bits are just not demanded. 1133 1134 // Otherwise, this pattern doesn't match. 1135 return false; 1136} 1137 1138/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1139/// the dag combiner simplified the 255, we still want to match. RHS is the 1140/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1141/// specified in the .td file (e.g. 255). 1142bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1143 int64_t DesiredMaskS) const { 1144 const APInt &ActualMask = RHS->getAPIntValue(); 1145 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1146 1147 // If the actual mask exactly matches, success! 1148 if (ActualMask == DesiredMask) 1149 return true; 1150 1151 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1152 if (ActualMask.intersects(~DesiredMask)) 1153 return false; 1154 1155 // Otherwise, the DAG Combiner may have proven that the value coming in is 1156 // either already zero or is not demanded. Check for known zero input bits. 1157 APInt NeededMask = DesiredMask & ~ActualMask; 1158 1159 APInt KnownZero, KnownOne; 1160 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1161 1162 // If all the missing bits in the or are already known to be set, match! 1163 if ((NeededMask & KnownOne) == NeededMask) 1164 return true; 1165 1166 // TODO: check to see if missing bits are just not demanded. 1167 1168 // Otherwise, this pattern doesn't match. 1169 return false; 1170} 1171 1172 1173/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1174/// by tblgen. Others should not call it. 1175void SelectionDAGISel:: 1176SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1177 std::vector<SDValue> InOps; 1178 std::swap(InOps, Ops); 1179 1180 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1181 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1182 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1183 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3 1184 1185 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1186 if (InOps[e-1].getValueType() == MVT::Flag) 1187 --e; // Don't process a flag operand if it is here. 1188 1189 while (i != e) { 1190 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1191 if (!InlineAsm::isMemKind(Flags)) { 1192 // Just skip over this operand, copying the operands verbatim. 1193 Ops.insert(Ops.end(), InOps.begin()+i, 1194 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1195 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1196 } else { 1197 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1198 "Memory operand with multiple values?"); 1199 // Otherwise, this is a memory operand. Ask the target to select it. 1200 std::vector<SDValue> SelOps; 1201 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1202 report_fatal_error("Could not match memory address. Inline asm" 1203 " failure!"); 1204 1205 // Add this to the output node. 1206 unsigned NewFlags = 1207 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1208 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1209 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1210 i += 2; 1211 } 1212 } 1213 1214 // Add the flag input back if present. 1215 if (e != InOps.size()) 1216 Ops.push_back(InOps.back()); 1217} 1218 1219/// findFlagUse - Return use of EVT::Flag value produced by the specified 1220/// SDNode. 1221/// 1222static SDNode *findFlagUse(SDNode *N) { 1223 unsigned FlagResNo = N->getNumValues()-1; 1224 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1225 SDUse &Use = I.getUse(); 1226 if (Use.getResNo() == FlagResNo) 1227 return Use.getUser(); 1228 } 1229 return NULL; 1230} 1231 1232/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1233/// This function recursively traverses up the operand chain, ignoring 1234/// certain nodes. 1235static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1236 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1237 bool IgnoreChains) { 1238 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1239 // greater than all of its (recursive) operands. If we scan to a point where 1240 // 'use' is smaller than the node we're scanning for, then we know we will 1241 // never find it. 1242 // 1243 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1244 // happen because we scan down to newly selected nodes in the case of flag 1245 // uses. 1246 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1247 return false; 1248 1249 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1250 // won't fail if we scan it again. 1251 if (!Visited.insert(Use)) 1252 return false; 1253 1254 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1255 // Ignore chain uses, they are validated by HandleMergeInputChains. 1256 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1257 continue; 1258 1259 SDNode *N = Use->getOperand(i).getNode(); 1260 if (N == Def) { 1261 if (Use == ImmedUse || Use == Root) 1262 continue; // We are not looking for immediate use. 1263 assert(N != Root); 1264 return true; 1265 } 1266 1267 // Traverse up the operand chain. 1268 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1269 return true; 1270 } 1271 return false; 1272} 1273 1274/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1275/// operand node N of U during instruction selection that starts at Root. 1276bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1277 SDNode *Root) const { 1278 if (OptLevel == CodeGenOpt::None) return false; 1279 return N.hasOneUse(); 1280} 1281 1282/// IsLegalToFold - Returns true if the specific operand node N of 1283/// U can be folded during instruction selection that starts at Root. 1284bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1285 CodeGenOpt::Level OptLevel, 1286 bool IgnoreChains) { 1287 if (OptLevel == CodeGenOpt::None) return false; 1288 1289 // If Root use can somehow reach N through a path that that doesn't contain 1290 // U then folding N would create a cycle. e.g. In the following 1291 // diagram, Root can reach N through X. If N is folded into into Root, then 1292 // X is both a predecessor and a successor of U. 1293 // 1294 // [N*] // 1295 // ^ ^ // 1296 // / \ // 1297 // [U*] [X]? // 1298 // ^ ^ // 1299 // \ / // 1300 // \ / // 1301 // [Root*] // 1302 // 1303 // * indicates nodes to be folded together. 1304 // 1305 // If Root produces a flag, then it gets (even more) interesting. Since it 1306 // will be "glued" together with its flag use in the scheduler, we need to 1307 // check if it might reach N. 1308 // 1309 // [N*] // 1310 // ^ ^ // 1311 // / \ // 1312 // [U*] [X]? // 1313 // ^ ^ // 1314 // \ \ // 1315 // \ | // 1316 // [Root*] | // 1317 // ^ | // 1318 // f | // 1319 // | / // 1320 // [Y] / // 1321 // ^ / // 1322 // f / // 1323 // | / // 1324 // [FU] // 1325 // 1326 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1327 // (call it Fold), then X is a predecessor of FU and a successor of 1328 // Fold. But since Fold and FU are flagged together, this will create 1329 // a cycle in the scheduling graph. 1330 1331 // If the node has flags, walk down the graph to the "lowest" node in the 1332 // flagged set. 1333 EVT VT = Root->getValueType(Root->getNumValues()-1); 1334 while (VT == MVT::Flag) { 1335 SDNode *FU = findFlagUse(Root); 1336 if (FU == NULL) 1337 break; 1338 Root = FU; 1339 VT = Root->getValueType(Root->getNumValues()-1); 1340 1341 // If our query node has a flag result with a use, we've walked up it. If 1342 // the user (which has already been selected) has a chain or indirectly uses 1343 // the chain, our WalkChainUsers predicate will not consider it. Because of 1344 // this, we cannot ignore chains in this predicate. 1345 IgnoreChains = false; 1346 } 1347 1348 1349 SmallPtrSet<SDNode*, 16> Visited; 1350 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1351} 1352 1353SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1354 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1355 SelectInlineAsmMemoryOperands(Ops); 1356 1357 std::vector<EVT> VTs; 1358 VTs.push_back(MVT::Other); 1359 VTs.push_back(MVT::Flag); 1360 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1361 VTs, &Ops[0], Ops.size()); 1362 New->setNodeId(-1); 1363 return New.getNode(); 1364} 1365 1366SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1367 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1368} 1369 1370/// GetVBR - decode a vbr encoding whose top bit is set. 1371LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1372GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1373 assert(Val >= 128 && "Not a VBR"); 1374 Val &= 127; // Remove first vbr bit. 1375 1376 unsigned Shift = 7; 1377 uint64_t NextBits; 1378 do { 1379 NextBits = MatcherTable[Idx++]; 1380 Val |= (NextBits&127) << Shift; 1381 Shift += 7; 1382 } while (NextBits & 128); 1383 1384 return Val; 1385} 1386 1387 1388/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1389/// interior flag and chain results to use the new flag and chain results. 1390void SelectionDAGISel:: 1391UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1392 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1393 SDValue InputFlag, 1394 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1395 bool isMorphNodeTo) { 1396 SmallVector<SDNode*, 4> NowDeadNodes; 1397 1398 ISelUpdater ISU(ISelPosition); 1399 1400 // Now that all the normal results are replaced, we replace the chain and 1401 // flag results if present. 1402 if (!ChainNodesMatched.empty()) { 1403 assert(InputChain.getNode() != 0 && 1404 "Matched input chains but didn't produce a chain"); 1405 // Loop over all of the nodes we matched that produced a chain result. 1406 // Replace all the chain results with the final chain we ended up with. 1407 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1408 SDNode *ChainNode = ChainNodesMatched[i]; 1409 1410 // If this node was already deleted, don't look at it. 1411 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1412 continue; 1413 1414 // Don't replace the results of the root node if we're doing a 1415 // MorphNodeTo. 1416 if (ChainNode == NodeToMatch && isMorphNodeTo) 1417 continue; 1418 1419 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1420 if (ChainVal.getValueType() == MVT::Flag) 1421 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1422 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1423 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1424 1425 // If the node became dead and we haven't already seen it, delete it. 1426 if (ChainNode->use_empty() && 1427 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1428 NowDeadNodes.push_back(ChainNode); 1429 } 1430 } 1431 1432 // If the result produces a flag, update any flag results in the matched 1433 // pattern with the flag result. 1434 if (InputFlag.getNode() != 0) { 1435 // Handle any interior nodes explicitly marked. 1436 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1437 SDNode *FRN = FlagResultNodesMatched[i]; 1438 1439 // If this node was already deleted, don't look at it. 1440 if (FRN->getOpcode() == ISD::DELETED_NODE) 1441 continue; 1442 1443 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1444 "Doesn't have a flag result"); 1445 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1446 InputFlag, &ISU); 1447 1448 // If the node became dead and we haven't already seen it, delete it. 1449 if (FRN->use_empty() && 1450 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1451 NowDeadNodes.push_back(FRN); 1452 } 1453 } 1454 1455 if (!NowDeadNodes.empty()) 1456 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1457 1458 DEBUG(errs() << "ISEL: Match complete!\n"); 1459} 1460 1461enum ChainResult { 1462 CR_Simple, 1463 CR_InducesCycle, 1464 CR_LeadsToInteriorNode 1465}; 1466 1467/// WalkChainUsers - Walk down the users of the specified chained node that is 1468/// part of the pattern we're matching, looking at all of the users we find. 1469/// This determines whether something is an interior node, whether we have a 1470/// non-pattern node in between two pattern nodes (which prevent folding because 1471/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1472/// between pattern nodes (in which case the TF becomes part of the pattern). 1473/// 1474/// The walk we do here is guaranteed to be small because we quickly get down to 1475/// already selected nodes "below" us. 1476static ChainResult 1477WalkChainUsers(SDNode *ChainedNode, 1478 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1479 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1480 ChainResult Result = CR_Simple; 1481 1482 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1483 E = ChainedNode->use_end(); UI != E; ++UI) { 1484 // Make sure the use is of the chain, not some other value we produce. 1485 if (UI.getUse().getValueType() != MVT::Other) continue; 1486 1487 SDNode *User = *UI; 1488 1489 // If we see an already-selected machine node, then we've gone beyond the 1490 // pattern that we're selecting down into the already selected chunk of the 1491 // DAG. 1492 if (User->isMachineOpcode() || 1493 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1494 continue; 1495 1496 if (User->getOpcode() == ISD::CopyToReg || 1497 User->getOpcode() == ISD::CopyFromReg || 1498 User->getOpcode() == ISD::INLINEASM || 1499 User->getOpcode() == ISD::EH_LABEL) { 1500 // If their node ID got reset to -1 then they've already been selected. 1501 // Treat them like a MachineOpcode. 1502 if (User->getNodeId() == -1) 1503 continue; 1504 } 1505 1506 // If we have a TokenFactor, we handle it specially. 1507 if (User->getOpcode() != ISD::TokenFactor) { 1508 // If the node isn't a token factor and isn't part of our pattern, then it 1509 // must be a random chained node in between two nodes we're selecting. 1510 // This happens when we have something like: 1511 // x = load ptr 1512 // call 1513 // y = x+4 1514 // store y -> ptr 1515 // Because we structurally match the load/store as a read/modify/write, 1516 // but the call is chained between them. We cannot fold in this case 1517 // because it would induce a cycle in the graph. 1518 if (!std::count(ChainedNodesInPattern.begin(), 1519 ChainedNodesInPattern.end(), User)) 1520 return CR_InducesCycle; 1521 1522 // Otherwise we found a node that is part of our pattern. For example in: 1523 // x = load ptr 1524 // y = x+4 1525 // store y -> ptr 1526 // This would happen when we're scanning down from the load and see the 1527 // store as a user. Record that there is a use of ChainedNode that is 1528 // part of the pattern and keep scanning uses. 1529 Result = CR_LeadsToInteriorNode; 1530 InteriorChainedNodes.push_back(User); 1531 continue; 1532 } 1533 1534 // If we found a TokenFactor, there are two cases to consider: first if the 1535 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1536 // uses of the TF are in our pattern) we just want to ignore it. Second, 1537 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1538 // [Load chain] 1539 // ^ 1540 // | 1541 // [Load] 1542 // ^ ^ 1543 // | \ DAG's like cheese 1544 // / \ do you? 1545 // / | 1546 // [TokenFactor] [Op] 1547 // ^ ^ 1548 // | | 1549 // \ / 1550 // \ / 1551 // [Store] 1552 // 1553 // In this case, the TokenFactor becomes part of our match and we rewrite it 1554 // as a new TokenFactor. 1555 // 1556 // To distinguish these two cases, do a recursive walk down the uses. 1557 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1558 case CR_Simple: 1559 // If the uses of the TokenFactor are just already-selected nodes, ignore 1560 // it, it is "below" our pattern. 1561 continue; 1562 case CR_InducesCycle: 1563 // If the uses of the TokenFactor lead to nodes that are not part of our 1564 // pattern that are not selected, folding would turn this into a cycle, 1565 // bail out now. 1566 return CR_InducesCycle; 1567 case CR_LeadsToInteriorNode: 1568 break; // Otherwise, keep processing. 1569 } 1570 1571 // Okay, we know we're in the interesting interior case. The TokenFactor 1572 // is now going to be considered part of the pattern so that we rewrite its 1573 // uses (it may have uses that are not part of the pattern) with the 1574 // ultimate chain result of the generated code. We will also add its chain 1575 // inputs as inputs to the ultimate TokenFactor we create. 1576 Result = CR_LeadsToInteriorNode; 1577 ChainedNodesInPattern.push_back(User); 1578 InteriorChainedNodes.push_back(User); 1579 continue; 1580 } 1581 1582 return Result; 1583} 1584 1585/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1586/// operation for when the pattern matched at least one node with a chains. The 1587/// input vector contains a list of all of the chained nodes that we match. We 1588/// must determine if this is a valid thing to cover (i.e. matching it won't 1589/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1590/// be used as the input node chain for the generated nodes. 1591static SDValue 1592HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1593 SelectionDAG *CurDAG) { 1594 // Walk all of the chained nodes we've matched, recursively scanning down the 1595 // users of the chain result. This adds any TokenFactor nodes that are caught 1596 // in between chained nodes to the chained and interior nodes list. 1597 SmallVector<SDNode*, 3> InteriorChainedNodes; 1598 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1599 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1600 InteriorChainedNodes) == CR_InducesCycle) 1601 return SDValue(); // Would induce a cycle. 1602 } 1603 1604 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1605 // that we are interested in. Form our input TokenFactor node. 1606 SmallVector<SDValue, 3> InputChains; 1607 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1608 // Add the input chain of this node to the InputChains list (which will be 1609 // the operands of the generated TokenFactor) if it's not an interior node. 1610 SDNode *N = ChainNodesMatched[i]; 1611 if (N->getOpcode() != ISD::TokenFactor) { 1612 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1613 continue; 1614 1615 // Otherwise, add the input chain. 1616 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1617 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1618 InputChains.push_back(InChain); 1619 continue; 1620 } 1621 1622 // If we have a token factor, we want to add all inputs of the token factor 1623 // that are not part of the pattern we're matching. 1624 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1625 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1626 N->getOperand(op).getNode())) 1627 InputChains.push_back(N->getOperand(op)); 1628 } 1629 } 1630 1631 SDValue Res; 1632 if (InputChains.size() == 1) 1633 return InputChains[0]; 1634 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1635 MVT::Other, &InputChains[0], InputChains.size()); 1636} 1637 1638/// MorphNode - Handle morphing a node in place for the selector. 1639SDNode *SelectionDAGISel:: 1640MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1641 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1642 // It is possible we're using MorphNodeTo to replace a node with no 1643 // normal results with one that has a normal result (or we could be 1644 // adding a chain) and the input could have flags and chains as well. 1645 // In this case we need to shift the operands down. 1646 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1647 // than the old isel though. 1648 int OldFlagResultNo = -1, OldChainResultNo = -1; 1649 1650 unsigned NTMNumResults = Node->getNumValues(); 1651 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1652 OldFlagResultNo = NTMNumResults-1; 1653 if (NTMNumResults != 1 && 1654 Node->getValueType(NTMNumResults-2) == MVT::Other) 1655 OldChainResultNo = NTMNumResults-2; 1656 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1657 OldChainResultNo = NTMNumResults-1; 1658 1659 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1660 // that this deletes operands of the old node that become dead. 1661 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1662 1663 // MorphNodeTo can operate in two ways: if an existing node with the 1664 // specified operands exists, it can just return it. Otherwise, it 1665 // updates the node in place to have the requested operands. 1666 if (Res == Node) { 1667 // If we updated the node in place, reset the node ID. To the isel, 1668 // this should be just like a newly allocated machine node. 1669 Res->setNodeId(-1); 1670 } 1671 1672 unsigned ResNumResults = Res->getNumValues(); 1673 // Move the flag if needed. 1674 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1675 (unsigned)OldFlagResultNo != ResNumResults-1) 1676 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1677 SDValue(Res, ResNumResults-1)); 1678 1679 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1680 --ResNumResults; 1681 1682 // Move the chain reference if needed. 1683 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1684 (unsigned)OldChainResultNo != ResNumResults-1) 1685 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1686 SDValue(Res, ResNumResults-1)); 1687 1688 // Otherwise, no replacement happened because the node already exists. Replace 1689 // Uses of the old node with the new one. 1690 if (Res != Node) 1691 CurDAG->ReplaceAllUsesWith(Node, Res); 1692 1693 return Res; 1694} 1695 1696/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1697LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1698CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1699 SDValue N, 1700 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1701 // Accept if it is exactly the same as a previously recorded node. 1702 unsigned RecNo = MatcherTable[MatcherIndex++]; 1703 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1704 return N == RecordedNodes[RecNo].first; 1705} 1706 1707/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1708LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1709CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1710 SelectionDAGISel &SDISel) { 1711 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1712} 1713 1714/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1715LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1716CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1717 SelectionDAGISel &SDISel, SDNode *N) { 1718 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1719} 1720 1721LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1722CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1723 SDNode *N) { 1724 uint16_t Opc = MatcherTable[MatcherIndex++]; 1725 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1726 return N->getOpcode() == Opc; 1727} 1728 1729LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1730CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1731 SDValue N, const TargetLowering &TLI) { 1732 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1733 if (N.getValueType() == VT) return true; 1734 1735 // Handle the case when VT is iPTR. 1736 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1737} 1738 1739LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1740CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1741 SDValue N, const TargetLowering &TLI, 1742 unsigned ChildNo) { 1743 if (ChildNo >= N.getNumOperands()) 1744 return false; // Match fails if out of range child #. 1745 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1746} 1747 1748 1749LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1750CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1751 SDValue N) { 1752 return cast<CondCodeSDNode>(N)->get() == 1753 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1754} 1755 1756LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1757CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1758 SDValue N, const TargetLowering &TLI) { 1759 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1760 if (cast<VTSDNode>(N)->getVT() == VT) 1761 return true; 1762 1763 // Handle the case when VT is iPTR. 1764 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1765} 1766 1767LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1768CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1769 SDValue N) { 1770 int64_t Val = MatcherTable[MatcherIndex++]; 1771 if (Val & 128) 1772 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1773 1774 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1775 return C != 0 && C->getSExtValue() == Val; 1776} 1777 1778LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1779CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1780 SDValue N, SelectionDAGISel &SDISel) { 1781 int64_t Val = MatcherTable[MatcherIndex++]; 1782 if (Val & 128) 1783 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1784 1785 if (N->getOpcode() != ISD::AND) return false; 1786 1787 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1788 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1789} 1790 1791LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1792CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1793 SDValue N, SelectionDAGISel &SDISel) { 1794 int64_t Val = MatcherTable[MatcherIndex++]; 1795 if (Val & 128) 1796 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1797 1798 if (N->getOpcode() != ISD::OR) return false; 1799 1800 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1801 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1802} 1803 1804/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1805/// scope, evaluate the current node. If the current predicate is known to 1806/// fail, set Result=true and return anything. If the current predicate is 1807/// known to pass, set Result=false and return the MatcherIndex to continue 1808/// with. If the current predicate is unknown, set Result=false and return the 1809/// MatcherIndex to continue with. 1810static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1811 unsigned Index, SDValue N, 1812 bool &Result, SelectionDAGISel &SDISel, 1813 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1814 switch (Table[Index++]) { 1815 default: 1816 Result = false; 1817 return Index-1; // Could not evaluate this predicate. 1818 case SelectionDAGISel::OPC_CheckSame: 1819 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1820 return Index; 1821 case SelectionDAGISel::OPC_CheckPatternPredicate: 1822 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1823 return Index; 1824 case SelectionDAGISel::OPC_CheckPredicate: 1825 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1826 return Index; 1827 case SelectionDAGISel::OPC_CheckOpcode: 1828 Result = !::CheckOpcode(Table, Index, N.getNode()); 1829 return Index; 1830 case SelectionDAGISel::OPC_CheckType: 1831 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1832 return Index; 1833 case SelectionDAGISel::OPC_CheckChild0Type: 1834 case SelectionDAGISel::OPC_CheckChild1Type: 1835 case SelectionDAGISel::OPC_CheckChild2Type: 1836 case SelectionDAGISel::OPC_CheckChild3Type: 1837 case SelectionDAGISel::OPC_CheckChild4Type: 1838 case SelectionDAGISel::OPC_CheckChild5Type: 1839 case SelectionDAGISel::OPC_CheckChild6Type: 1840 case SelectionDAGISel::OPC_CheckChild7Type: 1841 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1842 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1843 return Index; 1844 case SelectionDAGISel::OPC_CheckCondCode: 1845 Result = !::CheckCondCode(Table, Index, N); 1846 return Index; 1847 case SelectionDAGISel::OPC_CheckValueType: 1848 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1849 return Index; 1850 case SelectionDAGISel::OPC_CheckInteger: 1851 Result = !::CheckInteger(Table, Index, N); 1852 return Index; 1853 case SelectionDAGISel::OPC_CheckAndImm: 1854 Result = !::CheckAndImm(Table, Index, N, SDISel); 1855 return Index; 1856 case SelectionDAGISel::OPC_CheckOrImm: 1857 Result = !::CheckOrImm(Table, Index, N, SDISel); 1858 return Index; 1859 } 1860} 1861 1862namespace { 1863 1864struct MatchScope { 1865 /// FailIndex - If this match fails, this is the index to continue with. 1866 unsigned FailIndex; 1867 1868 /// NodeStack - The node stack when the scope was formed. 1869 SmallVector<SDValue, 4> NodeStack; 1870 1871 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1872 unsigned NumRecordedNodes; 1873 1874 /// NumMatchedMemRefs - The number of matched memref entries. 1875 unsigned NumMatchedMemRefs; 1876 1877 /// InputChain/InputFlag - The current chain/flag 1878 SDValue InputChain, InputFlag; 1879 1880 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1881 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1882}; 1883 1884} 1885 1886SDNode *SelectionDAGISel:: 1887SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1888 unsigned TableSize) { 1889 // FIXME: Should these even be selected? Handle these cases in the caller? 1890 switch (NodeToMatch->getOpcode()) { 1891 default: 1892 break; 1893 case ISD::EntryToken: // These nodes remain the same. 1894 case ISD::BasicBlock: 1895 case ISD::Register: 1896 //case ISD::VALUETYPE: 1897 //case ISD::CONDCODE: 1898 case ISD::HANDLENODE: 1899 case ISD::MDNODE_SDNODE: 1900 case ISD::TargetConstant: 1901 case ISD::TargetConstantFP: 1902 case ISD::TargetConstantPool: 1903 case ISD::TargetFrameIndex: 1904 case ISD::TargetExternalSymbol: 1905 case ISD::TargetBlockAddress: 1906 case ISD::TargetJumpTable: 1907 case ISD::TargetGlobalTLSAddress: 1908 case ISD::TargetGlobalAddress: 1909 case ISD::TokenFactor: 1910 case ISD::CopyFromReg: 1911 case ISD::CopyToReg: 1912 case ISD::EH_LABEL: 1913 NodeToMatch->setNodeId(-1); // Mark selected. 1914 return 0; 1915 case ISD::AssertSext: 1916 case ISD::AssertZext: 1917 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1918 NodeToMatch->getOperand(0)); 1919 return 0; 1920 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1921 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1922 } 1923 1924 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1925 1926 // Set up the node stack with NodeToMatch as the only node on the stack. 1927 SmallVector<SDValue, 8> NodeStack; 1928 SDValue N = SDValue(NodeToMatch, 0); 1929 NodeStack.push_back(N); 1930 1931 // MatchScopes - Scopes used when matching, if a match failure happens, this 1932 // indicates where to continue checking. 1933 SmallVector<MatchScope, 8> MatchScopes; 1934 1935 // RecordedNodes - This is the set of nodes that have been recorded by the 1936 // state machine. The second value is the parent of the node, or null if the 1937 // root is recorded. 1938 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 1939 1940 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1941 // pattern. 1942 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1943 1944 // These are the current input chain and flag for use when generating nodes. 1945 // Various Emit operations change these. For example, emitting a copytoreg 1946 // uses and updates these. 1947 SDValue InputChain, InputFlag; 1948 1949 // ChainNodesMatched - If a pattern matches nodes that have input/output 1950 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1951 // which ones they are. The result is captured into this list so that we can 1952 // update the chain results when the pattern is complete. 1953 SmallVector<SDNode*, 3> ChainNodesMatched; 1954 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1955 1956 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1957 NodeToMatch->dump(CurDAG); 1958 errs() << '\n'); 1959 1960 // Determine where to start the interpreter. Normally we start at opcode #0, 1961 // but if the state machine starts with an OPC_SwitchOpcode, then we 1962 // accelerate the first lookup (which is guaranteed to be hot) with the 1963 // OpcodeOffset table. 1964 unsigned MatcherIndex = 0; 1965 1966 if (!OpcodeOffset.empty()) { 1967 // Already computed the OpcodeOffset table, just index into it. 1968 if (N.getOpcode() < OpcodeOffset.size()) 1969 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1970 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1971 1972 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1973 // Otherwise, the table isn't computed, but the state machine does start 1974 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1975 // is the first time we're selecting an instruction. 1976 unsigned Idx = 1; 1977 while (1) { 1978 // Get the size of this case. 1979 unsigned CaseSize = MatcherTable[Idx++]; 1980 if (CaseSize & 128) 1981 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1982 if (CaseSize == 0) break; 1983 1984 // Get the opcode, add the index to the table. 1985 uint16_t Opc = MatcherTable[Idx++]; 1986 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 1987 if (Opc >= OpcodeOffset.size()) 1988 OpcodeOffset.resize((Opc+1)*2); 1989 OpcodeOffset[Opc] = Idx; 1990 Idx += CaseSize; 1991 } 1992 1993 // Okay, do the lookup for the first opcode. 1994 if (N.getOpcode() < OpcodeOffset.size()) 1995 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1996 } 1997 1998 while (1) { 1999 assert(MatcherIndex < TableSize && "Invalid index"); 2000#ifndef NDEBUG 2001 unsigned CurrentOpcodeIndex = MatcherIndex; 2002#endif 2003 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2004 switch (Opcode) { 2005 case OPC_Scope: { 2006 // Okay, the semantics of this operation are that we should push a scope 2007 // then evaluate the first child. However, pushing a scope only to have 2008 // the first check fail (which then pops it) is inefficient. If we can 2009 // determine immediately that the first check (or first several) will 2010 // immediately fail, don't even bother pushing a scope for them. 2011 unsigned FailIndex; 2012 2013 while (1) { 2014 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2015 if (NumToSkip & 128) 2016 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2017 // Found the end of the scope with no match. 2018 if (NumToSkip == 0) { 2019 FailIndex = 0; 2020 break; 2021 } 2022 2023 FailIndex = MatcherIndex+NumToSkip; 2024 2025 unsigned MatcherIndexOfPredicate = MatcherIndex; 2026 (void)MatcherIndexOfPredicate; // silence warning. 2027 2028 // If we can't evaluate this predicate without pushing a scope (e.g. if 2029 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2030 // push the scope and evaluate the full predicate chain. 2031 bool Result; 2032 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2033 Result, *this, RecordedNodes); 2034 if (!Result) 2035 break; 2036 2037 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2038 << "index " << MatcherIndexOfPredicate 2039 << ", continuing at " << FailIndex << "\n"); 2040 ++NumDAGIselRetries; 2041 2042 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2043 // move to the next case. 2044 MatcherIndex = FailIndex; 2045 } 2046 2047 // If the whole scope failed to match, bail. 2048 if (FailIndex == 0) break; 2049 2050 // Push a MatchScope which indicates where to go if the first child fails 2051 // to match. 2052 MatchScope NewEntry; 2053 NewEntry.FailIndex = FailIndex; 2054 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2055 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2056 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2057 NewEntry.InputChain = InputChain; 2058 NewEntry.InputFlag = InputFlag; 2059 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2060 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2061 MatchScopes.push_back(NewEntry); 2062 continue; 2063 } 2064 case OPC_RecordNode: { 2065 // Remember this node, it may end up being an operand in the pattern. 2066 SDNode *Parent = 0; 2067 if (NodeStack.size() > 1) 2068 Parent = NodeStack[NodeStack.size()-2].getNode(); 2069 RecordedNodes.push_back(std::make_pair(N, Parent)); 2070 continue; 2071 } 2072 2073 case OPC_RecordChild0: case OPC_RecordChild1: 2074 case OPC_RecordChild2: case OPC_RecordChild3: 2075 case OPC_RecordChild4: case OPC_RecordChild5: 2076 case OPC_RecordChild6: case OPC_RecordChild7: { 2077 unsigned ChildNo = Opcode-OPC_RecordChild0; 2078 if (ChildNo >= N.getNumOperands()) 2079 break; // Match fails if out of range child #. 2080 2081 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2082 N.getNode())); 2083 continue; 2084 } 2085 case OPC_RecordMemRef: 2086 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2087 continue; 2088 2089 case OPC_CaptureFlagInput: 2090 // If the current node has an input flag, capture it in InputFlag. 2091 if (N->getNumOperands() != 0 && 2092 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2093 InputFlag = N->getOperand(N->getNumOperands()-1); 2094 continue; 2095 2096 case OPC_MoveChild: { 2097 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2098 if (ChildNo >= N.getNumOperands()) 2099 break; // Match fails if out of range child #. 2100 N = N.getOperand(ChildNo); 2101 NodeStack.push_back(N); 2102 continue; 2103 } 2104 2105 case OPC_MoveParent: 2106 // Pop the current node off the NodeStack. 2107 NodeStack.pop_back(); 2108 assert(!NodeStack.empty() && "Node stack imbalance!"); 2109 N = NodeStack.back(); 2110 continue; 2111 2112 case OPC_CheckSame: 2113 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2114 continue; 2115 case OPC_CheckPatternPredicate: 2116 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2117 continue; 2118 case OPC_CheckPredicate: 2119 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2120 N.getNode())) 2121 break; 2122 continue; 2123 case OPC_CheckComplexPat: { 2124 unsigned CPNum = MatcherTable[MatcherIndex++]; 2125 unsigned RecNo = MatcherTable[MatcherIndex++]; 2126 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2127 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2128 RecordedNodes[RecNo].first, CPNum, 2129 RecordedNodes)) 2130 break; 2131 continue; 2132 } 2133 case OPC_CheckOpcode: 2134 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2135 continue; 2136 2137 case OPC_CheckType: 2138 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2139 continue; 2140 2141 case OPC_SwitchOpcode: { 2142 unsigned CurNodeOpcode = N.getOpcode(); 2143 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2144 unsigned CaseSize; 2145 while (1) { 2146 // Get the size of this case. 2147 CaseSize = MatcherTable[MatcherIndex++]; 2148 if (CaseSize & 128) 2149 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2150 if (CaseSize == 0) break; 2151 2152 uint16_t Opc = MatcherTable[MatcherIndex++]; 2153 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2154 2155 // If the opcode matches, then we will execute this case. 2156 if (CurNodeOpcode == Opc) 2157 break; 2158 2159 // Otherwise, skip over this case. 2160 MatcherIndex += CaseSize; 2161 } 2162 2163 // If no cases matched, bail out. 2164 if (CaseSize == 0) break; 2165 2166 // Otherwise, execute the case we found. 2167 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2168 << " to " << MatcherIndex << "\n"); 2169 continue; 2170 } 2171 2172 case OPC_SwitchType: { 2173 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2174 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2175 unsigned CaseSize; 2176 while (1) { 2177 // Get the size of this case. 2178 CaseSize = MatcherTable[MatcherIndex++]; 2179 if (CaseSize & 128) 2180 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2181 if (CaseSize == 0) break; 2182 2183 MVT::SimpleValueType CaseVT = 2184 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2185 if (CaseVT == MVT::iPTR) 2186 CaseVT = TLI.getPointerTy().SimpleTy; 2187 2188 // If the VT matches, then we will execute this case. 2189 if (CurNodeVT == CaseVT) 2190 break; 2191 2192 // Otherwise, skip over this case. 2193 MatcherIndex += CaseSize; 2194 } 2195 2196 // If no cases matched, bail out. 2197 if (CaseSize == 0) break; 2198 2199 // Otherwise, execute the case we found. 2200 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2201 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2202 continue; 2203 } 2204 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2205 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2206 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2207 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2208 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2209 Opcode-OPC_CheckChild0Type)) 2210 break; 2211 continue; 2212 case OPC_CheckCondCode: 2213 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2214 continue; 2215 case OPC_CheckValueType: 2216 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2217 continue; 2218 case OPC_CheckInteger: 2219 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2220 continue; 2221 case OPC_CheckAndImm: 2222 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2223 continue; 2224 case OPC_CheckOrImm: 2225 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2226 continue; 2227 2228 case OPC_CheckFoldableChainNode: { 2229 assert(NodeStack.size() != 1 && "No parent node"); 2230 // Verify that all intermediate nodes between the root and this one have 2231 // a single use. 2232 bool HasMultipleUses = false; 2233 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2234 if (!NodeStack[i].hasOneUse()) { 2235 HasMultipleUses = true; 2236 break; 2237 } 2238 if (HasMultipleUses) break; 2239 2240 // Check to see that the target thinks this is profitable to fold and that 2241 // we can fold it without inducing cycles in the graph. 2242 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2243 NodeToMatch) || 2244 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2245 NodeToMatch, OptLevel, 2246 true/*We validate our own chains*/)) 2247 break; 2248 2249 continue; 2250 } 2251 case OPC_EmitInteger: { 2252 MVT::SimpleValueType VT = 2253 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2254 int64_t Val = MatcherTable[MatcherIndex++]; 2255 if (Val & 128) 2256 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2257 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2258 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2259 continue; 2260 } 2261 case OPC_EmitRegister: { 2262 MVT::SimpleValueType VT = 2263 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2264 unsigned RegNo = MatcherTable[MatcherIndex++]; 2265 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2266 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2267 continue; 2268 } 2269 2270 case OPC_EmitConvertToTarget: { 2271 // Convert from IMM/FPIMM to target version. 2272 unsigned RecNo = MatcherTable[MatcherIndex++]; 2273 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2274 SDValue Imm = RecordedNodes[RecNo].first; 2275 2276 if (Imm->getOpcode() == ISD::Constant) { 2277 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2278 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2279 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2280 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2281 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2282 } 2283 2284 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2285 continue; 2286 } 2287 2288 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2289 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2290 // These are space-optimized forms of OPC_EmitMergeInputChains. 2291 assert(InputChain.getNode() == 0 && 2292 "EmitMergeInputChains should be the first chain producing node"); 2293 assert(ChainNodesMatched.empty() && 2294 "Should only have one EmitMergeInputChains per match"); 2295 2296 // Read all of the chained nodes. 2297 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2298 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2299 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2300 2301 // FIXME: What if other value results of the node have uses not matched 2302 // by this pattern? 2303 if (ChainNodesMatched.back() != NodeToMatch && 2304 !RecordedNodes[RecNo].first.hasOneUse()) { 2305 ChainNodesMatched.clear(); 2306 break; 2307 } 2308 2309 // Merge the input chains if they are not intra-pattern references. 2310 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2311 2312 if (InputChain.getNode() == 0) 2313 break; // Failed to merge. 2314 continue; 2315 } 2316 2317 case OPC_EmitMergeInputChains: { 2318 assert(InputChain.getNode() == 0 && 2319 "EmitMergeInputChains should be the first chain producing node"); 2320 // This node gets a list of nodes we matched in the input that have 2321 // chains. We want to token factor all of the input chains to these nodes 2322 // together. However, if any of the input chains is actually one of the 2323 // nodes matched in this pattern, then we have an intra-match reference. 2324 // Ignore these because the newly token factored chain should not refer to 2325 // the old nodes. 2326 unsigned NumChains = MatcherTable[MatcherIndex++]; 2327 assert(NumChains != 0 && "Can't TF zero chains"); 2328 2329 assert(ChainNodesMatched.empty() && 2330 "Should only have one EmitMergeInputChains per match"); 2331 2332 // Read all of the chained nodes. 2333 for (unsigned i = 0; i != NumChains; ++i) { 2334 unsigned RecNo = MatcherTable[MatcherIndex++]; 2335 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2336 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2337 2338 // FIXME: What if other value results of the node have uses not matched 2339 // by this pattern? 2340 if (ChainNodesMatched.back() != NodeToMatch && 2341 !RecordedNodes[RecNo].first.hasOneUse()) { 2342 ChainNodesMatched.clear(); 2343 break; 2344 } 2345 } 2346 2347 // If the inner loop broke out, the match fails. 2348 if (ChainNodesMatched.empty()) 2349 break; 2350 2351 // Merge the input chains if they are not intra-pattern references. 2352 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2353 2354 if (InputChain.getNode() == 0) 2355 break; // Failed to merge. 2356 2357 continue; 2358 } 2359 2360 case OPC_EmitCopyToReg: { 2361 unsigned RecNo = MatcherTable[MatcherIndex++]; 2362 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2363 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2364 2365 if (InputChain.getNode() == 0) 2366 InputChain = CurDAG->getEntryNode(); 2367 2368 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2369 DestPhysReg, RecordedNodes[RecNo].first, 2370 InputFlag); 2371 2372 InputFlag = InputChain.getValue(1); 2373 continue; 2374 } 2375 2376 case OPC_EmitNodeXForm: { 2377 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2378 unsigned RecNo = MatcherTable[MatcherIndex++]; 2379 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2380 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2381 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2382 continue; 2383 } 2384 2385 case OPC_EmitNode: 2386 case OPC_MorphNodeTo: { 2387 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2388 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2389 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2390 // Get the result VT list. 2391 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2392 SmallVector<EVT, 4> VTs; 2393 for (unsigned i = 0; i != NumVTs; ++i) { 2394 MVT::SimpleValueType VT = 2395 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2396 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2397 VTs.push_back(VT); 2398 } 2399 2400 if (EmitNodeInfo & OPFL_Chain) 2401 VTs.push_back(MVT::Other); 2402 if (EmitNodeInfo & OPFL_FlagOutput) 2403 VTs.push_back(MVT::Flag); 2404 2405 // This is hot code, so optimize the two most common cases of 1 and 2 2406 // results. 2407 SDVTList VTList; 2408 if (VTs.size() == 1) 2409 VTList = CurDAG->getVTList(VTs[0]); 2410 else if (VTs.size() == 2) 2411 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2412 else 2413 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2414 2415 // Get the operand list. 2416 unsigned NumOps = MatcherTable[MatcherIndex++]; 2417 SmallVector<SDValue, 8> Ops; 2418 for (unsigned i = 0; i != NumOps; ++i) { 2419 unsigned RecNo = MatcherTable[MatcherIndex++]; 2420 if (RecNo & 128) 2421 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2422 2423 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2424 Ops.push_back(RecordedNodes[RecNo].first); 2425 } 2426 2427 // If there are variadic operands to add, handle them now. 2428 if (EmitNodeInfo & OPFL_VariadicInfo) { 2429 // Determine the start index to copy from. 2430 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2431 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2432 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2433 "Invalid variadic node"); 2434 // Copy all of the variadic operands, not including a potential flag 2435 // input. 2436 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2437 i != e; ++i) { 2438 SDValue V = NodeToMatch->getOperand(i); 2439 if (V.getValueType() == MVT::Flag) break; 2440 Ops.push_back(V); 2441 } 2442 } 2443 2444 // If this has chain/flag inputs, add them. 2445 if (EmitNodeInfo & OPFL_Chain) 2446 Ops.push_back(InputChain); 2447 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2448 Ops.push_back(InputFlag); 2449 2450 // Create the node. 2451 SDNode *Res = 0; 2452 if (Opcode != OPC_MorphNodeTo) { 2453 // If this is a normal EmitNode command, just create the new node and 2454 // add the results to the RecordedNodes list. 2455 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2456 VTList, Ops.data(), Ops.size()); 2457 2458 // Add all the non-flag/non-chain results to the RecordedNodes list. 2459 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2460 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2461 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2462 (SDNode*) 0)); 2463 } 2464 2465 } else { 2466 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2467 EmitNodeInfo); 2468 } 2469 2470 // If the node had chain/flag results, update our notion of the current 2471 // chain and flag. 2472 if (EmitNodeInfo & OPFL_FlagOutput) { 2473 InputFlag = SDValue(Res, VTs.size()-1); 2474 if (EmitNodeInfo & OPFL_Chain) 2475 InputChain = SDValue(Res, VTs.size()-2); 2476 } else if (EmitNodeInfo & OPFL_Chain) 2477 InputChain = SDValue(Res, VTs.size()-1); 2478 2479 // If the OPFL_MemRefs flag is set on this node, slap all of the 2480 // accumulated memrefs onto it. 2481 // 2482 // FIXME: This is vastly incorrect for patterns with multiple outputs 2483 // instructions that access memory and for ComplexPatterns that match 2484 // loads. 2485 if (EmitNodeInfo & OPFL_MemRefs) { 2486 MachineSDNode::mmo_iterator MemRefs = 2487 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2488 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2489 cast<MachineSDNode>(Res) 2490 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2491 } 2492 2493 DEBUG(errs() << " " 2494 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2495 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2496 2497 // If this was a MorphNodeTo then we're completely done! 2498 if (Opcode == OPC_MorphNodeTo) { 2499 // Update chain and flag uses. 2500 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2501 InputFlag, FlagResultNodesMatched, true); 2502 return Res; 2503 } 2504 2505 continue; 2506 } 2507 2508 case OPC_MarkFlagResults: { 2509 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2510 2511 // Read and remember all the flag-result nodes. 2512 for (unsigned i = 0; i != NumNodes; ++i) { 2513 unsigned RecNo = MatcherTable[MatcherIndex++]; 2514 if (RecNo & 128) 2515 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2516 2517 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2518 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2519 } 2520 continue; 2521 } 2522 2523 case OPC_CompleteMatch: { 2524 // The match has been completed, and any new nodes (if any) have been 2525 // created. Patch up references to the matched dag to use the newly 2526 // created nodes. 2527 unsigned NumResults = MatcherTable[MatcherIndex++]; 2528 2529 for (unsigned i = 0; i != NumResults; ++i) { 2530 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2531 if (ResSlot & 128) 2532 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2533 2534 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2535 SDValue Res = RecordedNodes[ResSlot].first; 2536 2537 assert(i < NodeToMatch->getNumValues() && 2538 NodeToMatch->getValueType(i) != MVT::Other && 2539 NodeToMatch->getValueType(i) != MVT::Flag && 2540 "Invalid number of results to complete!"); 2541 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2542 NodeToMatch->getValueType(i) == MVT::iPTR || 2543 Res.getValueType() == MVT::iPTR || 2544 NodeToMatch->getValueType(i).getSizeInBits() == 2545 Res.getValueType().getSizeInBits()) && 2546 "invalid replacement"); 2547 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2548 } 2549 2550 // If the root node defines a flag, add it to the flag nodes to update 2551 // list. 2552 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2553 FlagResultNodesMatched.push_back(NodeToMatch); 2554 2555 // Update chain and flag uses. 2556 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2557 InputFlag, FlagResultNodesMatched, false); 2558 2559 assert(NodeToMatch->use_empty() && 2560 "Didn't replace all uses of the node?"); 2561 2562 // FIXME: We just return here, which interacts correctly with SelectRoot 2563 // above. We should fix this to not return an SDNode* anymore. 2564 return 0; 2565 } 2566 } 2567 2568 // If the code reached this point, then the match failed. See if there is 2569 // another child to try in the current 'Scope', otherwise pop it until we 2570 // find a case to check. 2571 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2572 ++NumDAGIselRetries; 2573 while (1) { 2574 if (MatchScopes.empty()) { 2575 CannotYetSelect(NodeToMatch); 2576 return 0; 2577 } 2578 2579 // Restore the interpreter state back to the point where the scope was 2580 // formed. 2581 MatchScope &LastScope = MatchScopes.back(); 2582 RecordedNodes.resize(LastScope.NumRecordedNodes); 2583 NodeStack.clear(); 2584 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2585 N = NodeStack.back(); 2586 2587 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2588 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2589 MatcherIndex = LastScope.FailIndex; 2590 2591 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2592 2593 InputChain = LastScope.InputChain; 2594 InputFlag = LastScope.InputFlag; 2595 if (!LastScope.HasChainNodesMatched) 2596 ChainNodesMatched.clear(); 2597 if (!LastScope.HasFlagResultNodesMatched) 2598 FlagResultNodesMatched.clear(); 2599 2600 // Check to see what the offset is at the new MatcherIndex. If it is zero 2601 // we have reached the end of this scope, otherwise we have another child 2602 // in the current scope to try. 2603 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2604 if (NumToSkip & 128) 2605 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2606 2607 // If we have another child in this scope to match, update FailIndex and 2608 // try it. 2609 if (NumToSkip != 0) { 2610 LastScope.FailIndex = MatcherIndex+NumToSkip; 2611 break; 2612 } 2613 2614 // End of this scope, pop it and try the next child in the containing 2615 // scope. 2616 MatchScopes.pop_back(); 2617 } 2618 } 2619} 2620 2621 2622 2623void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2624 std::string msg; 2625 raw_string_ostream Msg(msg); 2626 Msg << "Cannot yet select: "; 2627 2628 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2629 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2630 N->getOpcode() != ISD::INTRINSIC_VOID) { 2631 N->printrFull(Msg, CurDAG); 2632 } else { 2633 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2634 unsigned iid = 2635 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2636 if (iid < Intrinsic::num_intrinsics) 2637 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2638 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2639 Msg << "target intrinsic %" << TII->getName(iid); 2640 else 2641 Msg << "unknown intrinsic #" << iid; 2642 } 2643 report_fatal_error(Msg.str()); 2644} 2645 2646char SelectionDAGISel::ID = 0; 2647