SelectionDAGISel.cpp revision 1cee581edc39c1c21f28ef723046e7ee53cd9549
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/CodeGen/FastISel.h" 29#include "llvm/CodeGen/GCStrategy.h" 30#include "llvm/CodeGen/GCMetadata.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetIntrinsicInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/Compiler.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/Timer.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/ADT/Statistic.h" 50#include <algorithm> 51using namespace llvm; 52 53STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 54STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 55 56static cl::opt<bool> 57EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 58 cl::desc("Enable verbose messages in the \"fast\" " 59 "instruction selector")); 60static cl::opt<bool> 61EnableFastISelAbort("fast-isel-abort", cl::Hidden, 62 cl::desc("Enable abort calls when \"fast\" instruction fails")); 63 64#ifndef NDEBUG 65static cl::opt<bool> 66ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 67 cl::desc("Pop up a window to show dags before the first " 68 "dag combine pass")); 69static cl::opt<bool> 70ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 71 cl::desc("Pop up a window to show dags before legalize types")); 72static cl::opt<bool> 73ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 74 cl::desc("Pop up a window to show dags before legalize")); 75static cl::opt<bool> 76ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the second " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before the post legalize types" 82 " dag combine pass")); 83static cl::opt<bool> 84ViewISelDAGs("view-isel-dags", cl::Hidden, 85 cl::desc("Pop up a window to show isel dags as they are selected")); 86static cl::opt<bool> 87ViewSchedDAGs("view-sched-dags", cl::Hidden, 88 cl::desc("Pop up a window to show sched dags as they are processed")); 89static cl::opt<bool> 90ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 91 cl::desc("Pop up a window to show SUnit dags after they are processed")); 92#else 93static const bool ViewDAGCombine1 = false, 94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 95 ViewDAGCombine2 = false, 96 ViewDAGCombineLT = false, 97 ViewISelDAGs = false, ViewSchedDAGs = false, 98 ViewSUnitDAGs = false; 99#endif 100 101//===---------------------------------------------------------------------===// 102/// 103/// RegisterScheduler class - Track the registration of instruction schedulers. 104/// 105//===---------------------------------------------------------------------===// 106MachinePassRegistry RegisterScheduler::Registry; 107 108//===---------------------------------------------------------------------===// 109/// 110/// ISHeuristic command line option for instruction schedulers. 111/// 112//===---------------------------------------------------------------------===// 113static cl::opt<RegisterScheduler::FunctionPassCtor, false, 114 RegisterPassParser<RegisterScheduler> > 115ISHeuristic("pre-RA-sched", 116 cl::init(&createDefaultScheduler), 117 cl::desc("Instruction schedulers available (before register" 118 " allocation):")); 119 120static RegisterScheduler 121defaultListDAGScheduler("default", "Best scheduler for the target", 122 createDefaultScheduler); 123 124namespace llvm { 125 //===--------------------------------------------------------------------===// 126 /// createDefaultScheduler - This creates an instruction scheduler appropriate 127 /// for the target. 128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 129 CodeGenOpt::Level OptLevel) { 130 const TargetLowering &TLI = IS->getTargetLowering(); 131 132 if (OptLevel == CodeGenOpt::None) 133 return createFastDAGScheduler(IS, OptLevel); 134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 135 return createTDListDAGScheduler(IS, OptLevel); 136 assert(TLI.getSchedulingPreference() == 137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 138 return createBURRListDAGScheduler(IS, OptLevel); 139 } 140} 141 142// EmitInstrWithCustomInserter - This method should be implemented by targets 143// that mark instructions with the 'usesCustomInserter' flag. These 144// instructions are special in various ways, which require special support to 145// insert. The specified MachineInstr is created but not inserted into any 146// basic blocks, and this method is called to expand it into a sequence of 147// instructions, potentially also creating new basic blocks and control flow. 148// When new basic blocks are inserted and the edges from MBB to its successors 149// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 150// DenseMap. 151MachineBasicBlock * 152TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 153 MachineBasicBlock *MBB) const { 154#ifndef NDEBUG 155 dbgs() << "If a target marks an instruction with " 156 "'usesCustomInserter', it must implement " 157 "TargetLowering::EmitInstrWithCustomInserter!"; 158#endif 159 llvm_unreachable(0); 160 return 0; 161} 162 163//===----------------------------------------------------------------------===// 164// SelectionDAGISel code 165//===----------------------------------------------------------------------===// 166 167SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) : 168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 169 FuncInfo(new FunctionLoweringInfo(TLI)), 170 CurDAG(new SelectionDAG(tm, *FuncInfo)), 171 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 172 GFI(), 173 OptLevel(OL), 174 DAGSize(0) 175{} 176 177SelectionDAGISel::~SelectionDAGISel() { 178 delete SDB; 179 delete CurDAG; 180 delete FuncInfo; 181} 182 183void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 184 AU.addRequired<AliasAnalysis>(); 185 AU.addPreserved<AliasAnalysis>(); 186 AU.addRequired<GCModuleInfo>(); 187 AU.addPreserved<GCModuleInfo>(); 188 MachineFunctionPass::getAnalysisUsage(AU); 189} 190 191bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 192 // Do some sanity-checking on the command-line options. 193 assert((!EnableFastISelVerbose || EnableFastISel) && 194 "-fast-isel-verbose requires -fast-isel"); 195 assert((!EnableFastISelAbort || EnableFastISel) && 196 "-fast-isel-abort requires -fast-isel"); 197 198 const Function &Fn = *mf.getFunction(); 199 const TargetInstrInfo &TII = *TM.getInstrInfo(); 200 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 201 202 MF = &mf; 203 RegInfo = &MF->getRegInfo(); 204 AA = &getAnalysis<AliasAnalysis>(); 205 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 206 207 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 208 209 CurDAG->init(*MF); 210 FuncInfo->set(Fn, *MF, EnableFastISel); 211 SDB->init(GFI, *AA); 212 213 SelectAllBasicBlocks(Fn); 214 215 // If the first basic block in the function has live ins that need to be 216 // copied into vregs, emit the copies into the top of the block before 217 // emitting the code for the block. 218 MachineBasicBlock *EntryMBB = MF->begin(); 219 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 220 221 // Insert DBG_VALUE instructions for function arguments to the entry block. 222 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 223 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 224 unsigned Reg = MI->getOperand(0).getReg(); 225 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 226 EntryMBB->insert(EntryMBB->begin(), MI); 227 else { 228 MachineInstr *Def = RegInfo->getVRegDef(Reg); 229 MachineBasicBlock::iterator InsertPos = Def; 230 EntryMBB->insert(llvm::next(InsertPos), MI); 231 } 232 } 233 234 // Release function-specific state. SDB and CurDAG are already cleared 235 // at this point. 236 FuncInfo->clear(); 237 238 return true; 239} 240 241MachineBasicBlock * 242SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB, 243 const BasicBlock *LLVMBB, 244 BasicBlock::const_iterator Begin, 245 BasicBlock::const_iterator End, 246 bool &HadTailCall) { 247 // Lower all of the non-terminator instructions. If a call is emitted 248 // as a tail call, cease emitting nodes for this block. Terminators 249 // are handled below. 250 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 251 SDB->visit(*I); 252 253 // Make sure the root of the DAG is up-to-date. 254 CurDAG->setRoot(SDB->getControlRoot()); 255 HadTailCall = SDB->HasTailCall; 256 SDB->clear(); 257 258 // Final step, emit the lowered DAG as machine code. 259 return CodeGenAndEmitDAG(BB); 260} 261 262namespace { 263/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 264/// nodes from the worklist. 265class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 266 SmallVector<SDNode*, 128> &Worklist; 267 SmallPtrSet<SDNode*, 128> &InWorklist; 268public: 269 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 270 SmallPtrSet<SDNode*, 128> &inwl) 271 : Worklist(wl), InWorklist(inwl) {} 272 273 void RemoveFromWorklist(SDNode *N) { 274 if (!InWorklist.erase(N)) return; 275 276 SmallVector<SDNode*, 128>::iterator I = 277 std::find(Worklist.begin(), Worklist.end(), N); 278 assert(I != Worklist.end() && "Not in worklist"); 279 280 *I = Worklist.back(); 281 Worklist.pop_back(); 282 } 283 284 virtual void NodeDeleted(SDNode *N, SDNode *E) { 285 RemoveFromWorklist(N); 286 } 287 288 virtual void NodeUpdated(SDNode *N) { 289 // Ignore updates. 290 } 291}; 292} 293 294/// TrivialTruncElim - Eliminate some trivial nops that can result from 295/// ShrinkDemandedOps: (trunc (ext n)) -> n. 296static bool TrivialTruncElim(SDValue Op, 297 TargetLowering::TargetLoweringOpt &TLO) { 298 SDValue N0 = Op.getOperand(0); 299 EVT VT = Op.getValueType(); 300 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 301 N0.getOpcode() == ISD::SIGN_EXTEND || 302 N0.getOpcode() == ISD::ANY_EXTEND) && 303 N0.getOperand(0).getValueType() == VT) { 304 return TLO.CombineTo(Op, N0.getOperand(0)); 305 } 306 return false; 307} 308 309/// ShrinkDemandedOps - A late transformation pass that shrink expressions 310/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 311/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 312void SelectionDAGISel::ShrinkDemandedOps() { 313 SmallVector<SDNode*, 128> Worklist; 314 SmallPtrSet<SDNode*, 128> InWorklist; 315 316 // Add all the dag nodes to the worklist. 317 Worklist.reserve(CurDAG->allnodes_size()); 318 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 319 E = CurDAG->allnodes_end(); I != E; ++I) { 320 Worklist.push_back(I); 321 InWorklist.insert(I); 322 } 323 324 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true); 325 while (!Worklist.empty()) { 326 SDNode *N = Worklist.pop_back_val(); 327 InWorklist.erase(N); 328 329 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 330 // Deleting this node may make its operands dead, add them to the worklist 331 // if they aren't already there. 332 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 333 if (InWorklist.insert(N->getOperand(i).getNode())) 334 Worklist.push_back(N->getOperand(i).getNode()); 335 336 CurDAG->DeleteNode(N); 337 continue; 338 } 339 340 // Run ShrinkDemandedOp on scalar binary operations. 341 if (N->getNumValues() != 1 || 342 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 343 continue; 344 345 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 346 APInt Demanded = APInt::getAllOnesValue(BitWidth); 347 APInt KnownZero, KnownOne; 348 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 349 KnownZero, KnownOne, TLO) && 350 (N->getOpcode() != ISD::TRUNCATE || 351 !TrivialTruncElim(SDValue(N, 0), TLO))) 352 continue; 353 354 // Revisit the node. 355 assert(!InWorklist.count(N) && "Already in worklist"); 356 Worklist.push_back(N); 357 InWorklist.insert(N); 358 359 // Replace the old value with the new one. 360 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 361 TLO.Old.getNode()->dump(CurDAG); 362 errs() << "\nWith: "; 363 TLO.New.getNode()->dump(CurDAG); 364 errs() << '\n'); 365 366 if (InWorklist.insert(TLO.New.getNode())) 367 Worklist.push_back(TLO.New.getNode()); 368 369 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 370 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 371 372 if (!TLO.Old.getNode()->use_empty()) continue; 373 374 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 375 i != e; ++i) { 376 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 377 if (OpNode->hasOneUse()) { 378 // Add OpNode to the end of the list to revisit. 379 DeadNodes.RemoveFromWorklist(OpNode); 380 Worklist.push_back(OpNode); 381 InWorklist.insert(OpNode); 382 } 383 } 384 385 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 386 CurDAG->DeleteNode(TLO.Old.getNode()); 387 } 388} 389 390void SelectionDAGISel::ComputeLiveOutVRegInfo() { 391 SmallPtrSet<SDNode*, 128> VisitedNodes; 392 SmallVector<SDNode*, 128> Worklist; 393 394 Worklist.push_back(CurDAG->getRoot().getNode()); 395 396 APInt Mask; 397 APInt KnownZero; 398 APInt KnownOne; 399 400 do { 401 SDNode *N = Worklist.pop_back_val(); 402 403 // If we've already seen this node, ignore it. 404 if (!VisitedNodes.insert(N)) 405 continue; 406 407 // Otherwise, add all chain operands to the worklist. 408 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 409 if (N->getOperand(i).getValueType() == MVT::Other) 410 Worklist.push_back(N->getOperand(i).getNode()); 411 412 // If this is a CopyToReg with a vreg dest, process it. 413 if (N->getOpcode() != ISD::CopyToReg) 414 continue; 415 416 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 417 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 418 continue; 419 420 // Ignore non-scalar or non-integer values. 421 SDValue Src = N->getOperand(2); 422 EVT SrcVT = Src.getValueType(); 423 if (!SrcVT.isInteger() || SrcVT.isVector()) 424 continue; 425 426 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 427 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 428 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 429 430 // Only install this information if it tells us something. 431 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 432 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 433 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 434 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 435 FunctionLoweringInfo::LiveOutInfo &LOI = 436 FuncInfo->LiveOutRegInfo[DestReg]; 437 LOI.NumSignBits = NumSignBits; 438 LOI.KnownOne = KnownOne; 439 LOI.KnownZero = KnownZero; 440 } 441 } while (!Worklist.empty()); 442} 443 444MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) { 445 std::string GroupName; 446 if (TimePassesIsEnabled) 447 GroupName = "Instruction Selection and Scheduling"; 448 std::string BlockName; 449 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 450 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 451 ViewSUnitDAGs) 452 BlockName = MF->getFunction()->getNameStr() + ":" + 453 BB->getBasicBlock()->getNameStr(); 454 455 DEBUG(dbgs() << "Initial selection DAG:\n"); 456 DEBUG(CurDAG->dump()); 457 458 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 459 460 // Run the DAG combiner in pre-legalize mode. 461 if (TimePassesIsEnabled) { 462 NamedRegionTimer T("DAG Combining 1", GroupName); 463 CurDAG->Combine(Unrestricted, *AA, OptLevel); 464 } else { 465 CurDAG->Combine(Unrestricted, *AA, OptLevel); 466 } 467 468 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 469 DEBUG(CurDAG->dump()); 470 471 // Second step, hack on the DAG until it only uses operations and types that 472 // the target supports. 473 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 474 BlockName); 475 476 bool Changed; 477 if (TimePassesIsEnabled) { 478 NamedRegionTimer T("Type Legalization", GroupName); 479 Changed = CurDAG->LegalizeTypes(); 480 } else { 481 Changed = CurDAG->LegalizeTypes(); 482 } 483 484 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 485 DEBUG(CurDAG->dump()); 486 487 if (Changed) { 488 if (ViewDAGCombineLT) 489 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 490 491 // Run the DAG combiner in post-type-legalize mode. 492 if (TimePassesIsEnabled) { 493 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 494 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 495 } else { 496 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 497 } 498 499 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 500 DEBUG(CurDAG->dump()); 501 } 502 503 if (TimePassesIsEnabled) { 504 NamedRegionTimer T("Vector Legalization", GroupName); 505 Changed = CurDAG->LegalizeVectors(); 506 } else { 507 Changed = CurDAG->LegalizeVectors(); 508 } 509 510 if (Changed) { 511 if (TimePassesIsEnabled) { 512 NamedRegionTimer T("Type Legalization 2", GroupName); 513 CurDAG->LegalizeTypes(); 514 } else { 515 CurDAG->LegalizeTypes(); 516 } 517 518 if (ViewDAGCombineLT) 519 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 520 521 // Run the DAG combiner in post-type-legalize mode. 522 if (TimePassesIsEnabled) { 523 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 524 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 525 } else { 526 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 527 } 528 529 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 530 DEBUG(CurDAG->dump()); 531 } 532 533 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 534 535 if (TimePassesIsEnabled) { 536 NamedRegionTimer T("DAG Legalization", GroupName); 537 CurDAG->Legalize(OptLevel); 538 } else { 539 CurDAG->Legalize(OptLevel); 540 } 541 542 DEBUG(dbgs() << "Legalized selection DAG:\n"); 543 DEBUG(CurDAG->dump()); 544 545 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 546 547 // Run the DAG combiner in post-legalize mode. 548 if (TimePassesIsEnabled) { 549 NamedRegionTimer T("DAG Combining 2", GroupName); 550 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 551 } else { 552 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 553 } 554 555 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 556 DEBUG(CurDAG->dump()); 557 558 if (OptLevel != CodeGenOpt::None) { 559 ShrinkDemandedOps(); 560 ComputeLiveOutVRegInfo(); 561 } 562 563 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 564 565 // Third, instruction select all of the operations to machine code, adding the 566 // code to the MachineBasicBlock. 567 if (TimePassesIsEnabled) { 568 NamedRegionTimer T("Instruction Selection", GroupName); 569 DoInstructionSelection(); 570 } else { 571 DoInstructionSelection(); 572 } 573 574 DEBUG(dbgs() << "Selected selection DAG:\n"); 575 DEBUG(CurDAG->dump()); 576 577 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 578 579 // Schedule machine code. 580 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 581 if (TimePassesIsEnabled) { 582 NamedRegionTimer T("Instruction Scheduling", GroupName); 583 Scheduler->Run(CurDAG, BB, BB->end()); 584 } else { 585 Scheduler->Run(CurDAG, BB, BB->end()); 586 } 587 588 if (ViewSUnitDAGs) Scheduler->viewGraph(); 589 590 // Emit machine code to BB. This can change 'BB' to the last block being 591 // inserted into. 592 if (TimePassesIsEnabled) { 593 NamedRegionTimer T("Instruction Creation", GroupName); 594 BB = Scheduler->EmitSchedule(); 595 } else { 596 BB = Scheduler->EmitSchedule(); 597 } 598 599 // Free the scheduler state. 600 if (TimePassesIsEnabled) { 601 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 602 delete Scheduler; 603 } else { 604 delete Scheduler; 605 } 606 607 // Free the SelectionDAG state, now that we're finished with it. 608 CurDAG->clear(); 609 610 return BB; 611} 612 613void SelectionDAGISel::DoInstructionSelection() { 614 DEBUG(errs() << "===== Instruction selection begins:\n"); 615 616 PreprocessISelDAG(); 617 618 // Select target instructions for the DAG. 619 { 620 // Number all nodes with a topological order and set DAGSize. 621 DAGSize = CurDAG->AssignTopologicalOrder(); 622 623 // Create a dummy node (which is not added to allnodes), that adds 624 // a reference to the root node, preventing it from being deleted, 625 // and tracking any changes of the root. 626 HandleSDNode Dummy(CurDAG->getRoot()); 627 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 628 ++ISelPosition; 629 630 // The AllNodes list is now topological-sorted. Visit the 631 // nodes by starting at the end of the list (the root of the 632 // graph) and preceding back toward the beginning (the entry 633 // node). 634 while (ISelPosition != CurDAG->allnodes_begin()) { 635 SDNode *Node = --ISelPosition; 636 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 637 // but there are currently some corner cases that it misses. Also, this 638 // makes it theoretically possible to disable the DAGCombiner. 639 if (Node->use_empty()) 640 continue; 641 642 SDNode *ResNode = Select(Node); 643 644 // FIXME: This is pretty gross. 'Select' should be changed to not return 645 // anything at all and this code should be nuked with a tactical strike. 646 647 // If node should not be replaced, continue with the next one. 648 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 649 continue; 650 // Replace node. 651 if (ResNode) 652 ReplaceUses(Node, ResNode); 653 654 // If after the replacement this node is not used any more, 655 // remove this dead node. 656 if (Node->use_empty()) { // Don't delete EntryToken, etc. 657 ISelUpdater ISU(ISelPosition); 658 CurDAG->RemoveDeadNode(Node, &ISU); 659 } 660 } 661 662 CurDAG->setRoot(Dummy.getValue()); 663 } 664 DEBUG(errs() << "===== Instruction selection ends:\n"); 665 666 PostprocessISelDAG(); 667} 668 669/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 670/// do other setup for EH landing-pad blocks. 671void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) { 672 // Add a label to mark the beginning of the landing pad. Deletion of the 673 // landing pad can thus be detected via the MachineModuleInfo. 674 MCSymbol *Label = MF->getMMI().addLandingPad(BB); 675 676 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 677 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 678 679 // Mark exception register as live in. 680 unsigned Reg = TLI.getExceptionAddressRegister(); 681 if (Reg) BB->addLiveIn(Reg); 682 683 // Mark exception selector register as live in. 684 Reg = TLI.getExceptionSelectorRegister(); 685 if (Reg) BB->addLiveIn(Reg); 686 687 // FIXME: Hack around an exception handling flaw (PR1508): the personality 688 // function and list of typeids logically belong to the invoke (or, if you 689 // like, the basic block containing the invoke), and need to be associated 690 // with it in the dwarf exception handling tables. Currently however the 691 // information is provided by an intrinsic (eh.selector) that can be moved 692 // to unexpected places by the optimizers: if the unwind edge is critical, 693 // then breaking it can result in the intrinsics being in the successor of 694 // the landing pad, not the landing pad itself. This results 695 // in exceptions not being caught because no typeids are associated with 696 // the invoke. This may not be the only way things can go wrong, but it 697 // is the only way we try to work around for the moment. 698 const BasicBlock *LLVMBB = BB->getBasicBlock(); 699 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 700 701 if (Br && Br->isUnconditional()) { // Critical edge? 702 BasicBlock::const_iterator I, E; 703 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 704 if (isa<EHSelectorInst>(I)) 705 break; 706 707 if (I == E) 708 // No catch info found - try to extract some from the successor. 709 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 710 } 711} 712 713void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 714 // Initialize the Fast-ISel state, if needed. 715 FastISel *FastIS = 0; 716 if (EnableFastISel) 717 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 718 FuncInfo->StaticAllocaMap, 719 FuncInfo->PHINodesToUpdate 720#ifndef NDEBUG 721 , FuncInfo->CatchInfoLost 722#endif 723 ); 724 725 // Iterate over all basic blocks in the function. 726 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 727 const BasicBlock *LLVMBB = &*I; 728 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB]; 729 730 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 731 BasicBlock::const_iterator const End = LLVMBB->end(); 732 BasicBlock::const_iterator BI = Begin; 733 734 // Lower any arguments needed in this block if this is the entry block. 735 bool SuppressFastISel = false; 736 if (LLVMBB == &Fn.getEntryBlock()) { 737 LowerArguments(LLVMBB); 738 739 // If any of the arguments has the byval attribute, forgo 740 // fast-isel in the entry block. 741 if (FastIS) { 742 unsigned j = 1; 743 for (Function::const_arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 744 I != E; ++I, ++j) 745 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 746 if (EnableFastISelVerbose || EnableFastISelAbort) 747 dbgs() << "FastISel skips entry block due to byval argument\n"; 748 SuppressFastISel = true; 749 break; 750 } 751 } 752 } 753 754 // Setup an EH landing-pad block. 755 if (BB->isLandingPad()) 756 PrepareEHLandingPad(BB); 757 758 // Before doing SelectionDAG ISel, see if FastISel has been requested. 759 if (FastIS && !SuppressFastISel) { 760 // Emit code for any incoming arguments. This must happen before 761 // beginning FastISel on the entry block. 762 if (LLVMBB == &Fn.getEntryBlock()) { 763 CurDAG->setRoot(SDB->getControlRoot()); 764 SDB->clear(); 765 BB = CodeGenAndEmitDAG(BB); 766 } 767 FastIS->startNewBlock(BB); 768 // Do FastISel on as many instructions as possible. 769 for (; BI != End; ++BI) { 770 // Try to select the instruction with FastISel. 771 if (FastIS->SelectInstruction(BI)) 772 continue; 773 774 // Then handle certain instructions as single-LLVM-Instruction blocks. 775 if (isa<CallInst>(BI)) { 776 ++NumFastIselFailures; 777 if (EnableFastISelVerbose || EnableFastISelAbort) { 778 dbgs() << "FastISel missed call: "; 779 BI->dump(); 780 } 781 782 if (!BI->getType()->isVoidTy() && !BI->use_empty()) { 783 unsigned &R = FuncInfo->ValueMap[BI]; 784 if (!R) 785 R = FuncInfo->CreateRegForValue(BI); 786 } 787 788 bool HadTailCall = false; 789 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall); 790 791 // If the call was emitted as a tail call, we're done with the block. 792 if (HadTailCall) { 793 BI = End; 794 break; 795 } 796 797 // If the instruction was codegen'd with multiple blocks, 798 // inform the FastISel object where to resume inserting. 799 FastIS->setCurrentBlock(BB); 800 continue; 801 } 802 803 // Otherwise, give up on FastISel for the rest of the block. 804 // For now, be a little lenient about non-branch terminators. 805 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 806 ++NumFastIselFailures; 807 if (EnableFastISelVerbose || EnableFastISelAbort) { 808 dbgs() << "FastISel miss: "; 809 BI->dump(); 810 } 811 if (EnableFastISelAbort) 812 // The "fast" selector couldn't handle something and bailed. 813 // For the purpose of debugging, just abort. 814 llvm_unreachable("FastISel didn't select the entire block"); 815 } 816 break; 817 } 818 } 819 820 // Run SelectionDAG instruction selection on the remainder of the block 821 // not handled by FastISel. If FastISel is not run, this is the entire 822 // block. 823 if (BI != End) { 824 bool HadTailCall; 825 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall); 826 } 827 828 FinishBasicBlock(BB); 829 FuncInfo->PHINodesToUpdate.clear(); 830 } 831 832 delete FastIS; 833} 834 835void 836SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) { 837 838 DEBUG(dbgs() << "Total amount of phi nodes to update: " 839 << FuncInfo->PHINodesToUpdate.size() << "\n"); 840 DEBUG(for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 841 dbgs() << "Node " << i << " : (" 842 << FuncInfo->PHINodesToUpdate[i].first 843 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 844 845 // Next, now that we know what the last MBB the LLVM BB expanded is, update 846 // PHI nodes in successors. 847 if (SDB->SwitchCases.empty() && 848 SDB->JTCases.empty() && 849 SDB->BitTestCases.empty()) { 850 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 851 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 852 assert(PHI->isPHI() && 853 "This is not a machine PHI node that we are updating!"); 854 if (!BB->isSuccessor(PHI->getParent())) 855 continue; 856 PHI->addOperand( 857 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 858 PHI->addOperand(MachineOperand::CreateMBB(BB)); 859 } 860 return; 861 } 862 863 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 864 // Lower header first, if it wasn't already lowered 865 if (!SDB->BitTestCases[i].Emitted) { 866 // Set the current basic block to the mbb we wish to insert the code into 867 BB = SDB->BitTestCases[i].Parent; 868 // Emit the code 869 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB); 870 CurDAG->setRoot(SDB->getRoot()); 871 SDB->clear(); 872 BB = CodeGenAndEmitDAG(BB); 873 } 874 875 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 876 // Set the current basic block to the mbb we wish to insert the code into 877 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 878 // Emit the code 879 if (j+1 != ej) 880 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 881 SDB->BitTestCases[i].Reg, 882 SDB->BitTestCases[i].Cases[j], 883 BB); 884 else 885 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 886 SDB->BitTestCases[i].Reg, 887 SDB->BitTestCases[i].Cases[j], 888 BB); 889 890 891 CurDAG->setRoot(SDB->getRoot()); 892 SDB->clear(); 893 BB = CodeGenAndEmitDAG(BB); 894 } 895 896 // Update PHI Nodes 897 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 898 pi != pe; ++pi) { 899 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 900 MachineBasicBlock *PHIBB = PHI->getParent(); 901 assert(PHI->isPHI() && 902 "This is not a machine PHI node that we are updating!"); 903 // This is "default" BB. We have two jumps to it. From "header" BB and 904 // from last "case" BB. 905 if (PHIBB == SDB->BitTestCases[i].Default) { 906 PHI->addOperand(MachineOperand:: 907 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 908 false)); 909 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 910 PHI->addOperand(MachineOperand:: 911 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 912 false)); 913 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 914 back().ThisBB)); 915 } 916 // One of "cases" BB. 917 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 918 j != ej; ++j) { 919 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 920 if (cBB->isSuccessor(PHIBB)) { 921 PHI->addOperand(MachineOperand:: 922 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 923 false)); 924 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 925 } 926 } 927 } 928 } 929 SDB->BitTestCases.clear(); 930 931 // If the JumpTable record is filled in, then we need to emit a jump table. 932 // Updating the PHI nodes is tricky in this case, since we need to determine 933 // whether the PHI is a successor of the range check MBB or the jump table MBB 934 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 935 // Lower header first, if it wasn't already lowered 936 if (!SDB->JTCases[i].first.Emitted) { 937 // Set the current basic block to the mbb we wish to insert the code into 938 BB = SDB->JTCases[i].first.HeaderBB; 939 // Emit the code 940 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 941 BB); 942 CurDAG->setRoot(SDB->getRoot()); 943 SDB->clear(); 944 BB = CodeGenAndEmitDAG(BB); 945 } 946 947 // Set the current basic block to the mbb we wish to insert the code into 948 BB = SDB->JTCases[i].second.MBB; 949 // Emit the code 950 SDB->visitJumpTable(SDB->JTCases[i].second); 951 CurDAG->setRoot(SDB->getRoot()); 952 SDB->clear(); 953 BB = CodeGenAndEmitDAG(BB); 954 955 // Update PHI Nodes 956 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 957 pi != pe; ++pi) { 958 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 959 MachineBasicBlock *PHIBB = PHI->getParent(); 960 assert(PHI->isPHI() && 961 "This is not a machine PHI node that we are updating!"); 962 // "default" BB. We can go there only from header BB. 963 if (PHIBB == SDB->JTCases[i].second.Default) { 964 PHI->addOperand 965 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 966 false)); 967 PHI->addOperand 968 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 969 } 970 // JT BB. Just iterate over successors here 971 if (BB->isSuccessor(PHIBB)) { 972 PHI->addOperand 973 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 974 false)); 975 PHI->addOperand(MachineOperand::CreateMBB(BB)); 976 } 977 } 978 } 979 SDB->JTCases.clear(); 980 981 // If the switch block involved a branch to one of the actual successors, we 982 // need to update PHI nodes in that block. 983 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 984 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 985 assert(PHI->isPHI() && 986 "This is not a machine PHI node that we are updating!"); 987 if (BB->isSuccessor(PHI->getParent())) { 988 PHI->addOperand( 989 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 990 PHI->addOperand(MachineOperand::CreateMBB(BB)); 991 } 992 } 993 994 // If we generated any switch lowering information, build and codegen any 995 // additional DAGs necessary. 996 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 997 // Set the current basic block to the mbb we wish to insert the code into 998 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 999 1000 // Determine the unique successors. 1001 SmallVector<MachineBasicBlock *, 2> Succs; 1002 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1003 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1004 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1005 1006 // Emit the code. Note that this could result in ThisBB being split, so 1007 // we need to check for updates. 1008 SDB->visitSwitchCase(SDB->SwitchCases[i], BB); 1009 CurDAG->setRoot(SDB->getRoot()); 1010 SDB->clear(); 1011 ThisBB = CodeGenAndEmitDAG(BB); 1012 1013 // Handle any PHI nodes in successors of this chunk, as if we were coming 1014 // from the original BB before switch expansion. Note that PHI nodes can 1015 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1016 // handle them the right number of times. 1017 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1018 BB = Succs[i]; 1019 // BB may have been removed from the CFG if a branch was constant folded. 1020 if (ThisBB->isSuccessor(BB)) { 1021 for (MachineBasicBlock::iterator Phi = BB->begin(); 1022 Phi != BB->end() && Phi->isPHI(); 1023 ++Phi) { 1024 // This value for this PHI node is recorded in PHINodesToUpdate. 1025 for (unsigned pn = 0; ; ++pn) { 1026 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1027 "Didn't find PHI entry!"); 1028 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 1029 Phi->addOperand(MachineOperand:: 1030 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 1031 false)); 1032 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1033 break; 1034 } 1035 } 1036 } 1037 } 1038 } 1039 } 1040 SDB->SwitchCases.clear(); 1041} 1042 1043 1044/// Create the scheduler. If a specific scheduler was specified 1045/// via the SchedulerRegistry, use it, otherwise select the 1046/// one preferred by the target. 1047/// 1048ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1049 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1050 1051 if (!Ctor) { 1052 Ctor = ISHeuristic; 1053 RegisterScheduler::setDefault(Ctor); 1054 } 1055 1056 return Ctor(this, OptLevel); 1057} 1058 1059ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1060 return new ScheduleHazardRecognizer(); 1061} 1062 1063//===----------------------------------------------------------------------===// 1064// Helper functions used by the generated instruction selector. 1065//===----------------------------------------------------------------------===// 1066// Calls to these methods are generated by tblgen. 1067 1068/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1069/// the dag combiner simplified the 255, we still want to match. RHS is the 1070/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1071/// specified in the .td file (e.g. 255). 1072bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1073 int64_t DesiredMaskS) const { 1074 const APInt &ActualMask = RHS->getAPIntValue(); 1075 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1076 1077 // If the actual mask exactly matches, success! 1078 if (ActualMask == DesiredMask) 1079 return true; 1080 1081 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1082 if (ActualMask.intersects(~DesiredMask)) 1083 return false; 1084 1085 // Otherwise, the DAG Combiner may have proven that the value coming in is 1086 // either already zero or is not demanded. Check for known zero input bits. 1087 APInt NeededMask = DesiredMask & ~ActualMask; 1088 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1089 return true; 1090 1091 // TODO: check to see if missing bits are just not demanded. 1092 1093 // Otherwise, this pattern doesn't match. 1094 return false; 1095} 1096 1097/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1098/// the dag combiner simplified the 255, we still want to match. RHS is the 1099/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1100/// specified in the .td file (e.g. 255). 1101bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1102 int64_t DesiredMaskS) const { 1103 const APInt &ActualMask = RHS->getAPIntValue(); 1104 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1105 1106 // If the actual mask exactly matches, success! 1107 if (ActualMask == DesiredMask) 1108 return true; 1109 1110 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1111 if (ActualMask.intersects(~DesiredMask)) 1112 return false; 1113 1114 // Otherwise, the DAG Combiner may have proven that the value coming in is 1115 // either already zero or is not demanded. Check for known zero input bits. 1116 APInt NeededMask = DesiredMask & ~ActualMask; 1117 1118 APInt KnownZero, KnownOne; 1119 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1120 1121 // If all the missing bits in the or are already known to be set, match! 1122 if ((NeededMask & KnownOne) == NeededMask) 1123 return true; 1124 1125 // TODO: check to see if missing bits are just not demanded. 1126 1127 // Otherwise, this pattern doesn't match. 1128 return false; 1129} 1130 1131 1132/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1133/// by tblgen. Others should not call it. 1134void SelectionDAGISel:: 1135SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1136 std::vector<SDValue> InOps; 1137 std::swap(InOps, Ops); 1138 1139 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1140 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1141 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1142 1143 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1144 if (InOps[e-1].getValueType() == MVT::Flag) 1145 --e; // Don't process a flag operand if it is here. 1146 1147 while (i != e) { 1148 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1149 if (!InlineAsm::isMemKind(Flags)) { 1150 // Just skip over this operand, copying the operands verbatim. 1151 Ops.insert(Ops.end(), InOps.begin()+i, 1152 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1153 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1154 } else { 1155 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1156 "Memory operand with multiple values?"); 1157 // Otherwise, this is a memory operand. Ask the target to select it. 1158 std::vector<SDValue> SelOps; 1159 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1160 report_fatal_error("Could not match memory address. Inline asm" 1161 " failure!"); 1162 1163 // Add this to the output node. 1164 unsigned NewFlags = 1165 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1166 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1167 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1168 i += 2; 1169 } 1170 } 1171 1172 // Add the flag input back if present. 1173 if (e != InOps.size()) 1174 Ops.push_back(InOps.back()); 1175} 1176 1177/// findFlagUse - Return use of EVT::Flag value produced by the specified 1178/// SDNode. 1179/// 1180static SDNode *findFlagUse(SDNode *N) { 1181 unsigned FlagResNo = N->getNumValues()-1; 1182 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1183 SDUse &Use = I.getUse(); 1184 if (Use.getResNo() == FlagResNo) 1185 return Use.getUser(); 1186 } 1187 return NULL; 1188} 1189 1190/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1191/// This function recursively traverses up the operand chain, ignoring 1192/// certain nodes. 1193static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1194 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1195 bool IgnoreChains) { 1196 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1197 // greater than all of its (recursive) operands. If we scan to a point where 1198 // 'use' is smaller than the node we're scanning for, then we know we will 1199 // never find it. 1200 // 1201 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1202 // happen because we scan down to newly selected nodes in the case of flag 1203 // uses. 1204 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1205 return false; 1206 1207 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1208 // won't fail if we scan it again. 1209 if (!Visited.insert(Use)) 1210 return false; 1211 1212 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1213 // Ignore chain uses, they are validated by HandleMergeInputChains. 1214 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1215 continue; 1216 1217 SDNode *N = Use->getOperand(i).getNode(); 1218 if (N == Def) { 1219 if (Use == ImmedUse || Use == Root) 1220 continue; // We are not looking for immediate use. 1221 assert(N != Root); 1222 return true; 1223 } 1224 1225 // Traverse up the operand chain. 1226 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1227 return true; 1228 } 1229 return false; 1230} 1231 1232/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1233/// operand node N of U during instruction selection that starts at Root. 1234bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1235 SDNode *Root) const { 1236 if (OptLevel == CodeGenOpt::None) return false; 1237 return N.hasOneUse(); 1238} 1239 1240/// IsLegalToFold - Returns true if the specific operand node N of 1241/// U can be folded during instruction selection that starts at Root. 1242bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1243 CodeGenOpt::Level OptLevel, 1244 bool IgnoreChains) { 1245 if (OptLevel == CodeGenOpt::None) return false; 1246 1247 // If Root use can somehow reach N through a path that that doesn't contain 1248 // U then folding N would create a cycle. e.g. In the following 1249 // diagram, Root can reach N through X. If N is folded into into Root, then 1250 // X is both a predecessor and a successor of U. 1251 // 1252 // [N*] // 1253 // ^ ^ // 1254 // / \ // 1255 // [U*] [X]? // 1256 // ^ ^ // 1257 // \ / // 1258 // \ / // 1259 // [Root*] // 1260 // 1261 // * indicates nodes to be folded together. 1262 // 1263 // If Root produces a flag, then it gets (even more) interesting. Since it 1264 // will be "glued" together with its flag use in the scheduler, we need to 1265 // check if it might reach N. 1266 // 1267 // [N*] // 1268 // ^ ^ // 1269 // / \ // 1270 // [U*] [X]? // 1271 // ^ ^ // 1272 // \ \ // 1273 // \ | // 1274 // [Root*] | // 1275 // ^ | // 1276 // f | // 1277 // | / // 1278 // [Y] / // 1279 // ^ / // 1280 // f / // 1281 // | / // 1282 // [FU] // 1283 // 1284 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1285 // (call it Fold), then X is a predecessor of FU and a successor of 1286 // Fold. But since Fold and FU are flagged together, this will create 1287 // a cycle in the scheduling graph. 1288 1289 // If the node has flags, walk down the graph to the "lowest" node in the 1290 // flagged set. 1291 EVT VT = Root->getValueType(Root->getNumValues()-1); 1292 while (VT == MVT::Flag) { 1293 SDNode *FU = findFlagUse(Root); 1294 if (FU == NULL) 1295 break; 1296 Root = FU; 1297 VT = Root->getValueType(Root->getNumValues()-1); 1298 1299 // If our query node has a flag result with a use, we've walked up it. If 1300 // the user (which has already been selected) has a chain or indirectly uses 1301 // the chain, our WalkChainUsers predicate will not consider it. Because of 1302 // this, we cannot ignore chains in this predicate. 1303 IgnoreChains = false; 1304 } 1305 1306 1307 SmallPtrSet<SDNode*, 16> Visited; 1308 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1309} 1310 1311SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1312 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1313 SelectInlineAsmMemoryOperands(Ops); 1314 1315 std::vector<EVT> VTs; 1316 VTs.push_back(MVT::Other); 1317 VTs.push_back(MVT::Flag); 1318 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1319 VTs, &Ops[0], Ops.size()); 1320 New->setNodeId(-1); 1321 return New.getNode(); 1322} 1323 1324SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1325 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1326} 1327 1328/// GetVBR - decode a vbr encoding whose top bit is set. 1329ALWAYS_INLINE static uint64_t 1330GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1331 assert(Val >= 128 && "Not a VBR"); 1332 Val &= 127; // Remove first vbr bit. 1333 1334 unsigned Shift = 7; 1335 uint64_t NextBits; 1336 do { 1337 NextBits = MatcherTable[Idx++]; 1338 Val |= (NextBits&127) << Shift; 1339 Shift += 7; 1340 } while (NextBits & 128); 1341 1342 return Val; 1343} 1344 1345 1346/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1347/// interior flag and chain results to use the new flag and chain results. 1348void SelectionDAGISel:: 1349UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1350 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1351 SDValue InputFlag, 1352 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1353 bool isMorphNodeTo) { 1354 SmallVector<SDNode*, 4> NowDeadNodes; 1355 1356 ISelUpdater ISU(ISelPosition); 1357 1358 // Now that all the normal results are replaced, we replace the chain and 1359 // flag results if present. 1360 if (!ChainNodesMatched.empty()) { 1361 assert(InputChain.getNode() != 0 && 1362 "Matched input chains but didn't produce a chain"); 1363 // Loop over all of the nodes we matched that produced a chain result. 1364 // Replace all the chain results with the final chain we ended up with. 1365 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1366 SDNode *ChainNode = ChainNodesMatched[i]; 1367 1368 // If this node was already deleted, don't look at it. 1369 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1370 continue; 1371 1372 // Don't replace the results of the root node if we're doing a 1373 // MorphNodeTo. 1374 if (ChainNode == NodeToMatch && isMorphNodeTo) 1375 continue; 1376 1377 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1378 if (ChainVal.getValueType() == MVT::Flag) 1379 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1380 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1381 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1382 1383 // If the node became dead and we haven't already seen it, delete it. 1384 if (ChainNode->use_empty() && 1385 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1386 NowDeadNodes.push_back(ChainNode); 1387 } 1388 } 1389 1390 // If the result produces a flag, update any flag results in the matched 1391 // pattern with the flag result. 1392 if (InputFlag.getNode() != 0) { 1393 // Handle any interior nodes explicitly marked. 1394 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1395 SDNode *FRN = FlagResultNodesMatched[i]; 1396 1397 // If this node was already deleted, don't look at it. 1398 if (FRN->getOpcode() == ISD::DELETED_NODE) 1399 continue; 1400 1401 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1402 "Doesn't have a flag result"); 1403 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1404 InputFlag, &ISU); 1405 1406 // If the node became dead and we haven't already seen it, delete it. 1407 if (FRN->use_empty() && 1408 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1409 NowDeadNodes.push_back(FRN); 1410 } 1411 } 1412 1413 if (!NowDeadNodes.empty()) 1414 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1415 1416 DEBUG(errs() << "ISEL: Match complete!\n"); 1417} 1418 1419enum ChainResult { 1420 CR_Simple, 1421 CR_InducesCycle, 1422 CR_LeadsToInteriorNode 1423}; 1424 1425/// WalkChainUsers - Walk down the users of the specified chained node that is 1426/// part of the pattern we're matching, looking at all of the users we find. 1427/// This determines whether something is an interior node, whether we have a 1428/// non-pattern node in between two pattern nodes (which prevent folding because 1429/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1430/// between pattern nodes (in which case the TF becomes part of the pattern). 1431/// 1432/// The walk we do here is guaranteed to be small because we quickly get down to 1433/// already selected nodes "below" us. 1434static ChainResult 1435WalkChainUsers(SDNode *ChainedNode, 1436 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1437 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1438 ChainResult Result = CR_Simple; 1439 1440 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1441 E = ChainedNode->use_end(); UI != E; ++UI) { 1442 // Make sure the use is of the chain, not some other value we produce. 1443 if (UI.getUse().getValueType() != MVT::Other) continue; 1444 1445 SDNode *User = *UI; 1446 1447 // If we see an already-selected machine node, then we've gone beyond the 1448 // pattern that we're selecting down into the already selected chunk of the 1449 // DAG. 1450 if (User->isMachineOpcode() || 1451 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1452 continue; 1453 1454 if (User->getOpcode() == ISD::CopyToReg || 1455 User->getOpcode() == ISD::CopyFromReg || 1456 User->getOpcode() == ISD::INLINEASM || 1457 User->getOpcode() == ISD::EH_LABEL) { 1458 // If their node ID got reset to -1 then they've already been selected. 1459 // Treat them like a MachineOpcode. 1460 if (User->getNodeId() == -1) 1461 continue; 1462 } 1463 1464 // If we have a TokenFactor, we handle it specially. 1465 if (User->getOpcode() != ISD::TokenFactor) { 1466 // If the node isn't a token factor and isn't part of our pattern, then it 1467 // must be a random chained node in between two nodes we're selecting. 1468 // This happens when we have something like: 1469 // x = load ptr 1470 // call 1471 // y = x+4 1472 // store y -> ptr 1473 // Because we structurally match the load/store as a read/modify/write, 1474 // but the call is chained between them. We cannot fold in this case 1475 // because it would induce a cycle in the graph. 1476 if (!std::count(ChainedNodesInPattern.begin(), 1477 ChainedNodesInPattern.end(), User)) 1478 return CR_InducesCycle; 1479 1480 // Otherwise we found a node that is part of our pattern. For example in: 1481 // x = load ptr 1482 // y = x+4 1483 // store y -> ptr 1484 // This would happen when we're scanning down from the load and see the 1485 // store as a user. Record that there is a use of ChainedNode that is 1486 // part of the pattern and keep scanning uses. 1487 Result = CR_LeadsToInteriorNode; 1488 InteriorChainedNodes.push_back(User); 1489 continue; 1490 } 1491 1492 // If we found a TokenFactor, there are two cases to consider: first if the 1493 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1494 // uses of the TF are in our pattern) we just want to ignore it. Second, 1495 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1496 // [Load chain] 1497 // ^ 1498 // | 1499 // [Load] 1500 // ^ ^ 1501 // | \ DAG's like cheese 1502 // / \ do you? 1503 // / | 1504 // [TokenFactor] [Op] 1505 // ^ ^ 1506 // | | 1507 // \ / 1508 // \ / 1509 // [Store] 1510 // 1511 // In this case, the TokenFactor becomes part of our match and we rewrite it 1512 // as a new TokenFactor. 1513 // 1514 // To distinguish these two cases, do a recursive walk down the uses. 1515 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1516 case CR_Simple: 1517 // If the uses of the TokenFactor are just already-selected nodes, ignore 1518 // it, it is "below" our pattern. 1519 continue; 1520 case CR_InducesCycle: 1521 // If the uses of the TokenFactor lead to nodes that are not part of our 1522 // pattern that are not selected, folding would turn this into a cycle, 1523 // bail out now. 1524 return CR_InducesCycle; 1525 case CR_LeadsToInteriorNode: 1526 break; // Otherwise, keep processing. 1527 } 1528 1529 // Okay, we know we're in the interesting interior case. The TokenFactor 1530 // is now going to be considered part of the pattern so that we rewrite its 1531 // uses (it may have uses that are not part of the pattern) with the 1532 // ultimate chain result of the generated code. We will also add its chain 1533 // inputs as inputs to the ultimate TokenFactor we create. 1534 Result = CR_LeadsToInteriorNode; 1535 ChainedNodesInPattern.push_back(User); 1536 InteriorChainedNodes.push_back(User); 1537 continue; 1538 } 1539 1540 return Result; 1541} 1542 1543/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1544/// operation for when the pattern matched at least one node with a chains. The 1545/// input vector contains a list of all of the chained nodes that we match. We 1546/// must determine if this is a valid thing to cover (i.e. matching it won't 1547/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1548/// be used as the input node chain for the generated nodes. 1549static SDValue 1550HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1551 SelectionDAG *CurDAG) { 1552 // Walk all of the chained nodes we've matched, recursively scanning down the 1553 // users of the chain result. This adds any TokenFactor nodes that are caught 1554 // in between chained nodes to the chained and interior nodes list. 1555 SmallVector<SDNode*, 3> InteriorChainedNodes; 1556 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1557 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1558 InteriorChainedNodes) == CR_InducesCycle) 1559 return SDValue(); // Would induce a cycle. 1560 } 1561 1562 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1563 // that we are interested in. Form our input TokenFactor node. 1564 SmallVector<SDValue, 3> InputChains; 1565 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1566 // Add the input chain of this node to the InputChains list (which will be 1567 // the operands of the generated TokenFactor) if it's not an interior node. 1568 SDNode *N = ChainNodesMatched[i]; 1569 if (N->getOpcode() != ISD::TokenFactor) { 1570 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1571 continue; 1572 1573 // Otherwise, add the input chain. 1574 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1575 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1576 InputChains.push_back(InChain); 1577 continue; 1578 } 1579 1580 // If we have a token factor, we want to add all inputs of the token factor 1581 // that are not part of the pattern we're matching. 1582 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1583 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1584 N->getOperand(op).getNode())) 1585 InputChains.push_back(N->getOperand(op)); 1586 } 1587 } 1588 1589 SDValue Res; 1590 if (InputChains.size() == 1) 1591 return InputChains[0]; 1592 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1593 MVT::Other, &InputChains[0], InputChains.size()); 1594} 1595 1596/// MorphNode - Handle morphing a node in place for the selector. 1597SDNode *SelectionDAGISel:: 1598MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1599 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1600 // It is possible we're using MorphNodeTo to replace a node with no 1601 // normal results with one that has a normal result (or we could be 1602 // adding a chain) and the input could have flags and chains as well. 1603 // In this case we need to shift the operands down. 1604 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1605 // than the old isel though. 1606 int OldFlagResultNo = -1, OldChainResultNo = -1; 1607 1608 unsigned NTMNumResults = Node->getNumValues(); 1609 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1610 OldFlagResultNo = NTMNumResults-1; 1611 if (NTMNumResults != 1 && 1612 Node->getValueType(NTMNumResults-2) == MVT::Other) 1613 OldChainResultNo = NTMNumResults-2; 1614 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1615 OldChainResultNo = NTMNumResults-1; 1616 1617 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1618 // that this deletes operands of the old node that become dead. 1619 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1620 1621 // MorphNodeTo can operate in two ways: if an existing node with the 1622 // specified operands exists, it can just return it. Otherwise, it 1623 // updates the node in place to have the requested operands. 1624 if (Res == Node) { 1625 // If we updated the node in place, reset the node ID. To the isel, 1626 // this should be just like a newly allocated machine node. 1627 Res->setNodeId(-1); 1628 } 1629 1630 unsigned ResNumResults = Res->getNumValues(); 1631 // Move the flag if needed. 1632 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1633 (unsigned)OldFlagResultNo != ResNumResults-1) 1634 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1635 SDValue(Res, ResNumResults-1)); 1636 1637 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1638 --ResNumResults; 1639 1640 // Move the chain reference if needed. 1641 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1642 (unsigned)OldChainResultNo != ResNumResults-1) 1643 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1644 SDValue(Res, ResNumResults-1)); 1645 1646 // Otherwise, no replacement happened because the node already exists. Replace 1647 // Uses of the old node with the new one. 1648 if (Res != Node) 1649 CurDAG->ReplaceAllUsesWith(Node, Res); 1650 1651 return Res; 1652} 1653 1654/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1655ALWAYS_INLINE static bool 1656CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1657 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1658 // Accept if it is exactly the same as a previously recorded node. 1659 unsigned RecNo = MatcherTable[MatcherIndex++]; 1660 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1661 return N == RecordedNodes[RecNo]; 1662} 1663 1664/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1665ALWAYS_INLINE static bool 1666CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1667 SelectionDAGISel &SDISel) { 1668 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1669} 1670 1671/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1672ALWAYS_INLINE static bool 1673CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1674 SelectionDAGISel &SDISel, SDNode *N) { 1675 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1676} 1677 1678ALWAYS_INLINE static bool 1679CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1680 SDNode *N) { 1681 uint16_t Opc = MatcherTable[MatcherIndex++]; 1682 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1683 return N->getOpcode() == Opc; 1684} 1685 1686ALWAYS_INLINE static bool 1687CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1688 SDValue N, const TargetLowering &TLI) { 1689 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1690 if (N.getValueType() == VT) return true; 1691 1692 // Handle the case when VT is iPTR. 1693 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1694} 1695 1696ALWAYS_INLINE static bool 1697CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1698 SDValue N, const TargetLowering &TLI, 1699 unsigned ChildNo) { 1700 if (ChildNo >= N.getNumOperands()) 1701 return false; // Match fails if out of range child #. 1702 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1703} 1704 1705 1706ALWAYS_INLINE static bool 1707CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1708 SDValue N) { 1709 return cast<CondCodeSDNode>(N)->get() == 1710 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1711} 1712 1713ALWAYS_INLINE static bool 1714CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1715 SDValue N, const TargetLowering &TLI) { 1716 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1717 if (cast<VTSDNode>(N)->getVT() == VT) 1718 return true; 1719 1720 // Handle the case when VT is iPTR. 1721 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1722} 1723 1724ALWAYS_INLINE static bool 1725CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1726 SDValue N) { 1727 int64_t Val = MatcherTable[MatcherIndex++]; 1728 if (Val & 128) 1729 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1730 1731 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1732 return C != 0 && C->getSExtValue() == Val; 1733} 1734 1735ALWAYS_INLINE static bool 1736CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1737 SDValue N, SelectionDAGISel &SDISel) { 1738 int64_t Val = MatcherTable[MatcherIndex++]; 1739 if (Val & 128) 1740 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1741 1742 if (N->getOpcode() != ISD::AND) return false; 1743 1744 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1745 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1746} 1747 1748ALWAYS_INLINE static bool 1749CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1750 SDValue N, SelectionDAGISel &SDISel) { 1751 int64_t Val = MatcherTable[MatcherIndex++]; 1752 if (Val & 128) 1753 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1754 1755 if (N->getOpcode() != ISD::OR) return false; 1756 1757 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1758 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1759} 1760 1761/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1762/// scope, evaluate the current node. If the current predicate is known to 1763/// fail, set Result=true and return anything. If the current predicate is 1764/// known to pass, set Result=false and return the MatcherIndex to continue 1765/// with. If the current predicate is unknown, set Result=false and return the 1766/// MatcherIndex to continue with. 1767static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1768 unsigned Index, SDValue N, 1769 bool &Result, SelectionDAGISel &SDISel, 1770 SmallVectorImpl<SDValue> &RecordedNodes){ 1771 switch (Table[Index++]) { 1772 default: 1773 Result = false; 1774 return Index-1; // Could not evaluate this predicate. 1775 case SelectionDAGISel::OPC_CheckSame: 1776 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1777 return Index; 1778 case SelectionDAGISel::OPC_CheckPatternPredicate: 1779 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1780 return Index; 1781 case SelectionDAGISel::OPC_CheckPredicate: 1782 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1783 return Index; 1784 case SelectionDAGISel::OPC_CheckOpcode: 1785 Result = !::CheckOpcode(Table, Index, N.getNode()); 1786 return Index; 1787 case SelectionDAGISel::OPC_CheckType: 1788 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1789 return Index; 1790 case SelectionDAGISel::OPC_CheckChild0Type: 1791 case SelectionDAGISel::OPC_CheckChild1Type: 1792 case SelectionDAGISel::OPC_CheckChild2Type: 1793 case SelectionDAGISel::OPC_CheckChild3Type: 1794 case SelectionDAGISel::OPC_CheckChild4Type: 1795 case SelectionDAGISel::OPC_CheckChild5Type: 1796 case SelectionDAGISel::OPC_CheckChild6Type: 1797 case SelectionDAGISel::OPC_CheckChild7Type: 1798 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1799 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1800 return Index; 1801 case SelectionDAGISel::OPC_CheckCondCode: 1802 Result = !::CheckCondCode(Table, Index, N); 1803 return Index; 1804 case SelectionDAGISel::OPC_CheckValueType: 1805 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1806 return Index; 1807 case SelectionDAGISel::OPC_CheckInteger: 1808 Result = !::CheckInteger(Table, Index, N); 1809 return Index; 1810 case SelectionDAGISel::OPC_CheckAndImm: 1811 Result = !::CheckAndImm(Table, Index, N, SDISel); 1812 return Index; 1813 case SelectionDAGISel::OPC_CheckOrImm: 1814 Result = !::CheckOrImm(Table, Index, N, SDISel); 1815 return Index; 1816 } 1817} 1818 1819namespace { 1820 1821struct MatchScope { 1822 /// FailIndex - If this match fails, this is the index to continue with. 1823 unsigned FailIndex; 1824 1825 /// NodeStack - The node stack when the scope was formed. 1826 SmallVector<SDValue, 4> NodeStack; 1827 1828 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1829 unsigned NumRecordedNodes; 1830 1831 /// NumMatchedMemRefs - The number of matched memref entries. 1832 unsigned NumMatchedMemRefs; 1833 1834 /// InputChain/InputFlag - The current chain/flag 1835 SDValue InputChain, InputFlag; 1836 1837 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1838 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1839}; 1840 1841} 1842 1843SDNode *SelectionDAGISel:: 1844SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1845 unsigned TableSize) { 1846 // FIXME: Should these even be selected? Handle these cases in the caller? 1847 switch (NodeToMatch->getOpcode()) { 1848 default: 1849 break; 1850 case ISD::EntryToken: // These nodes remain the same. 1851 case ISD::BasicBlock: 1852 case ISD::Register: 1853 //case ISD::VALUETYPE: 1854 //case ISD::CONDCODE: 1855 case ISD::HANDLENODE: 1856 case ISD::MDNODE_SDNODE: 1857 case ISD::TargetConstant: 1858 case ISD::TargetConstantFP: 1859 case ISD::TargetConstantPool: 1860 case ISD::TargetFrameIndex: 1861 case ISD::TargetExternalSymbol: 1862 case ISD::TargetBlockAddress: 1863 case ISD::TargetJumpTable: 1864 case ISD::TargetGlobalTLSAddress: 1865 case ISD::TargetGlobalAddress: 1866 case ISD::TokenFactor: 1867 case ISD::CopyFromReg: 1868 case ISD::CopyToReg: 1869 case ISD::EH_LABEL: 1870 NodeToMatch->setNodeId(-1); // Mark selected. 1871 return 0; 1872 case ISD::AssertSext: 1873 case ISD::AssertZext: 1874 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1875 NodeToMatch->getOperand(0)); 1876 return 0; 1877 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1878 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1879 } 1880 1881 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1882 1883 // Set up the node stack with NodeToMatch as the only node on the stack. 1884 SmallVector<SDValue, 8> NodeStack; 1885 SDValue N = SDValue(NodeToMatch, 0); 1886 NodeStack.push_back(N); 1887 1888 // MatchScopes - Scopes used when matching, if a match failure happens, this 1889 // indicates where to continue checking. 1890 SmallVector<MatchScope, 8> MatchScopes; 1891 1892 // RecordedNodes - This is the set of nodes that have been recorded by the 1893 // state machine. 1894 SmallVector<SDValue, 8> RecordedNodes; 1895 1896 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1897 // pattern. 1898 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1899 1900 // These are the current input chain and flag for use when generating nodes. 1901 // Various Emit operations change these. For example, emitting a copytoreg 1902 // uses and updates these. 1903 SDValue InputChain, InputFlag; 1904 1905 // ChainNodesMatched - If a pattern matches nodes that have input/output 1906 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1907 // which ones they are. The result is captured into this list so that we can 1908 // update the chain results when the pattern is complete. 1909 SmallVector<SDNode*, 3> ChainNodesMatched; 1910 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1911 1912 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1913 NodeToMatch->dump(CurDAG); 1914 errs() << '\n'); 1915 1916 // Determine where to start the interpreter. Normally we start at opcode #0, 1917 // but if the state machine starts with an OPC_SwitchOpcode, then we 1918 // accelerate the first lookup (which is guaranteed to be hot) with the 1919 // OpcodeOffset table. 1920 unsigned MatcherIndex = 0; 1921 1922 if (!OpcodeOffset.empty()) { 1923 // Already computed the OpcodeOffset table, just index into it. 1924 if (N.getOpcode() < OpcodeOffset.size()) 1925 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1926 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1927 1928 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1929 // Otherwise, the table isn't computed, but the state machine does start 1930 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1931 // is the first time we're selecting an instruction. 1932 unsigned Idx = 1; 1933 while (1) { 1934 // Get the size of this case. 1935 unsigned CaseSize = MatcherTable[Idx++]; 1936 if (CaseSize & 128) 1937 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1938 if (CaseSize == 0) break; 1939 1940 // Get the opcode, add the index to the table. 1941 uint16_t Opc = MatcherTable[Idx++]; 1942 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 1943 if (Opc >= OpcodeOffset.size()) 1944 OpcodeOffset.resize((Opc+1)*2); 1945 OpcodeOffset[Opc] = Idx; 1946 Idx += CaseSize; 1947 } 1948 1949 // Okay, do the lookup for the first opcode. 1950 if (N.getOpcode() < OpcodeOffset.size()) 1951 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1952 } 1953 1954 while (1) { 1955 assert(MatcherIndex < TableSize && "Invalid index"); 1956#ifndef NDEBUG 1957 unsigned CurrentOpcodeIndex = MatcherIndex; 1958#endif 1959 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 1960 switch (Opcode) { 1961 case OPC_Scope: { 1962 // Okay, the semantics of this operation are that we should push a scope 1963 // then evaluate the first child. However, pushing a scope only to have 1964 // the first check fail (which then pops it) is inefficient. If we can 1965 // determine immediately that the first check (or first several) will 1966 // immediately fail, don't even bother pushing a scope for them. 1967 unsigned FailIndex; 1968 1969 while (1) { 1970 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 1971 if (NumToSkip & 128) 1972 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 1973 // Found the end of the scope with no match. 1974 if (NumToSkip == 0) { 1975 FailIndex = 0; 1976 break; 1977 } 1978 1979 FailIndex = MatcherIndex+NumToSkip; 1980 1981 unsigned MatcherIndexOfPredicate = MatcherIndex; 1982 (void)MatcherIndexOfPredicate; // silence warning. 1983 1984 // If we can't evaluate this predicate without pushing a scope (e.g. if 1985 // it is a 'MoveParent') or if the predicate succeeds on this node, we 1986 // push the scope and evaluate the full predicate chain. 1987 bool Result; 1988 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 1989 Result, *this, RecordedNodes); 1990 if (!Result) 1991 break; 1992 1993 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 1994 << "index " << MatcherIndexOfPredicate 1995 << ", continuing at " << FailIndex << "\n"); 1996 ++NumDAGIselRetries; 1997 1998 // Otherwise, we know that this case of the Scope is guaranteed to fail, 1999 // move to the next case. 2000 MatcherIndex = FailIndex; 2001 } 2002 2003 // If the whole scope failed to match, bail. 2004 if (FailIndex == 0) break; 2005 2006 // Push a MatchScope which indicates where to go if the first child fails 2007 // to match. 2008 MatchScope NewEntry; 2009 NewEntry.FailIndex = FailIndex; 2010 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2011 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2012 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2013 NewEntry.InputChain = InputChain; 2014 NewEntry.InputFlag = InputFlag; 2015 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2016 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2017 MatchScopes.push_back(NewEntry); 2018 continue; 2019 } 2020 case OPC_RecordNode: 2021 // Remember this node, it may end up being an operand in the pattern. 2022 RecordedNodes.push_back(N); 2023 continue; 2024 2025 case OPC_RecordChild0: case OPC_RecordChild1: 2026 case OPC_RecordChild2: case OPC_RecordChild3: 2027 case OPC_RecordChild4: case OPC_RecordChild5: 2028 case OPC_RecordChild6: case OPC_RecordChild7: { 2029 unsigned ChildNo = Opcode-OPC_RecordChild0; 2030 if (ChildNo >= N.getNumOperands()) 2031 break; // Match fails if out of range child #. 2032 2033 RecordedNodes.push_back(N->getOperand(ChildNo)); 2034 continue; 2035 } 2036 case OPC_RecordMemRef: 2037 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2038 continue; 2039 2040 case OPC_CaptureFlagInput: 2041 // If the current node has an input flag, capture it in InputFlag. 2042 if (N->getNumOperands() != 0 && 2043 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2044 InputFlag = N->getOperand(N->getNumOperands()-1); 2045 continue; 2046 2047 case OPC_MoveChild: { 2048 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2049 if (ChildNo >= N.getNumOperands()) 2050 break; // Match fails if out of range child #. 2051 N = N.getOperand(ChildNo); 2052 NodeStack.push_back(N); 2053 continue; 2054 } 2055 2056 case OPC_MoveParent: 2057 // Pop the current node off the NodeStack. 2058 NodeStack.pop_back(); 2059 assert(!NodeStack.empty() && "Node stack imbalance!"); 2060 N = NodeStack.back(); 2061 continue; 2062 2063 case OPC_CheckSame: 2064 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2065 continue; 2066 case OPC_CheckPatternPredicate: 2067 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2068 continue; 2069 case OPC_CheckPredicate: 2070 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2071 N.getNode())) 2072 break; 2073 continue; 2074 case OPC_CheckComplexPat: { 2075 unsigned CPNum = MatcherTable[MatcherIndex++]; 2076 unsigned RecNo = MatcherTable[MatcherIndex++]; 2077 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2078 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2079 RecordedNodes)) 2080 break; 2081 continue; 2082 } 2083 case OPC_CheckOpcode: 2084 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2085 continue; 2086 2087 case OPC_CheckType: 2088 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2089 continue; 2090 2091 case OPC_SwitchOpcode: { 2092 unsigned CurNodeOpcode = N.getOpcode(); 2093 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2094 unsigned CaseSize; 2095 while (1) { 2096 // Get the size of this case. 2097 CaseSize = MatcherTable[MatcherIndex++]; 2098 if (CaseSize & 128) 2099 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2100 if (CaseSize == 0) break; 2101 2102 uint16_t Opc = MatcherTable[MatcherIndex++]; 2103 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2104 2105 // If the opcode matches, then we will execute this case. 2106 if (CurNodeOpcode == Opc) 2107 break; 2108 2109 // Otherwise, skip over this case. 2110 MatcherIndex += CaseSize; 2111 } 2112 2113 // If no cases matched, bail out. 2114 if (CaseSize == 0) break; 2115 2116 // Otherwise, execute the case we found. 2117 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2118 << " to " << MatcherIndex << "\n"); 2119 continue; 2120 } 2121 2122 case OPC_SwitchType: { 2123 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2124 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2125 unsigned CaseSize; 2126 while (1) { 2127 // Get the size of this case. 2128 CaseSize = MatcherTable[MatcherIndex++]; 2129 if (CaseSize & 128) 2130 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2131 if (CaseSize == 0) break; 2132 2133 MVT::SimpleValueType CaseVT = 2134 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2135 if (CaseVT == MVT::iPTR) 2136 CaseVT = TLI.getPointerTy().SimpleTy; 2137 2138 // If the VT matches, then we will execute this case. 2139 if (CurNodeVT == CaseVT) 2140 break; 2141 2142 // Otherwise, skip over this case. 2143 MatcherIndex += CaseSize; 2144 } 2145 2146 // If no cases matched, bail out. 2147 if (CaseSize == 0) break; 2148 2149 // Otherwise, execute the case we found. 2150 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2151 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2152 continue; 2153 } 2154 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2155 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2156 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2157 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2158 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2159 Opcode-OPC_CheckChild0Type)) 2160 break; 2161 continue; 2162 case OPC_CheckCondCode: 2163 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2164 continue; 2165 case OPC_CheckValueType: 2166 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2167 continue; 2168 case OPC_CheckInteger: 2169 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2170 continue; 2171 case OPC_CheckAndImm: 2172 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2173 continue; 2174 case OPC_CheckOrImm: 2175 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2176 continue; 2177 2178 case OPC_CheckFoldableChainNode: { 2179 assert(NodeStack.size() != 1 && "No parent node"); 2180 // Verify that all intermediate nodes between the root and this one have 2181 // a single use. 2182 bool HasMultipleUses = false; 2183 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2184 if (!NodeStack[i].hasOneUse()) { 2185 HasMultipleUses = true; 2186 break; 2187 } 2188 if (HasMultipleUses) break; 2189 2190 // Check to see that the target thinks this is profitable to fold and that 2191 // we can fold it without inducing cycles in the graph. 2192 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2193 NodeToMatch) || 2194 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2195 NodeToMatch, OptLevel, 2196 true/*We validate our own chains*/)) 2197 break; 2198 2199 continue; 2200 } 2201 case OPC_EmitInteger: { 2202 MVT::SimpleValueType VT = 2203 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2204 int64_t Val = MatcherTable[MatcherIndex++]; 2205 if (Val & 128) 2206 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2207 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2208 continue; 2209 } 2210 case OPC_EmitRegister: { 2211 MVT::SimpleValueType VT = 2212 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2213 unsigned RegNo = MatcherTable[MatcherIndex++]; 2214 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2215 continue; 2216 } 2217 2218 case OPC_EmitConvertToTarget: { 2219 // Convert from IMM/FPIMM to target version. 2220 unsigned RecNo = MatcherTable[MatcherIndex++]; 2221 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2222 SDValue Imm = RecordedNodes[RecNo]; 2223 2224 if (Imm->getOpcode() == ISD::Constant) { 2225 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2226 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2227 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2228 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2229 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2230 } 2231 2232 RecordedNodes.push_back(Imm); 2233 continue; 2234 } 2235 2236 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2237 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2238 // These are space-optimized forms of OPC_EmitMergeInputChains. 2239 assert(InputChain.getNode() == 0 && 2240 "EmitMergeInputChains should be the first chain producing node"); 2241 assert(ChainNodesMatched.empty() && 2242 "Should only have one EmitMergeInputChains per match"); 2243 2244 // Read all of the chained nodes. 2245 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2246 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2247 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2248 2249 // FIXME: What if other value results of the node have uses not matched 2250 // by this pattern? 2251 if (ChainNodesMatched.back() != NodeToMatch && 2252 !RecordedNodes[RecNo].hasOneUse()) { 2253 ChainNodesMatched.clear(); 2254 break; 2255 } 2256 2257 // Merge the input chains if they are not intra-pattern references. 2258 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2259 2260 if (InputChain.getNode() == 0) 2261 break; // Failed to merge. 2262 continue; 2263 } 2264 2265 case OPC_EmitMergeInputChains: { 2266 assert(InputChain.getNode() == 0 && 2267 "EmitMergeInputChains should be the first chain producing node"); 2268 // This node gets a list of nodes we matched in the input that have 2269 // chains. We want to token factor all of the input chains to these nodes 2270 // together. However, if any of the input chains is actually one of the 2271 // nodes matched in this pattern, then we have an intra-match reference. 2272 // Ignore these because the newly token factored chain should not refer to 2273 // the old nodes. 2274 unsigned NumChains = MatcherTable[MatcherIndex++]; 2275 assert(NumChains != 0 && "Can't TF zero chains"); 2276 2277 assert(ChainNodesMatched.empty() && 2278 "Should only have one EmitMergeInputChains per match"); 2279 2280 // Read all of the chained nodes. 2281 for (unsigned i = 0; i != NumChains; ++i) { 2282 unsigned RecNo = MatcherTable[MatcherIndex++]; 2283 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2284 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2285 2286 // FIXME: What if other value results of the node have uses not matched 2287 // by this pattern? 2288 if (ChainNodesMatched.back() != NodeToMatch && 2289 !RecordedNodes[RecNo].hasOneUse()) { 2290 ChainNodesMatched.clear(); 2291 break; 2292 } 2293 } 2294 2295 // If the inner loop broke out, the match fails. 2296 if (ChainNodesMatched.empty()) 2297 break; 2298 2299 // Merge the input chains if they are not intra-pattern references. 2300 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2301 2302 if (InputChain.getNode() == 0) 2303 break; // Failed to merge. 2304 2305 continue; 2306 } 2307 2308 case OPC_EmitCopyToReg: { 2309 unsigned RecNo = MatcherTable[MatcherIndex++]; 2310 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2311 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2312 2313 if (InputChain.getNode() == 0) 2314 InputChain = CurDAG->getEntryNode(); 2315 2316 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2317 DestPhysReg, RecordedNodes[RecNo], 2318 InputFlag); 2319 2320 InputFlag = InputChain.getValue(1); 2321 continue; 2322 } 2323 2324 case OPC_EmitNodeXForm: { 2325 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2326 unsigned RecNo = MatcherTable[MatcherIndex++]; 2327 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2328 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2329 continue; 2330 } 2331 2332 case OPC_EmitNode: 2333 case OPC_MorphNodeTo: { 2334 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2335 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2336 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2337 // Get the result VT list. 2338 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2339 SmallVector<EVT, 4> VTs; 2340 for (unsigned i = 0; i != NumVTs; ++i) { 2341 MVT::SimpleValueType VT = 2342 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2343 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2344 VTs.push_back(VT); 2345 } 2346 2347 if (EmitNodeInfo & OPFL_Chain) 2348 VTs.push_back(MVT::Other); 2349 if (EmitNodeInfo & OPFL_FlagOutput) 2350 VTs.push_back(MVT::Flag); 2351 2352 // This is hot code, so optimize the two most common cases of 1 and 2 2353 // results. 2354 SDVTList VTList; 2355 if (VTs.size() == 1) 2356 VTList = CurDAG->getVTList(VTs[0]); 2357 else if (VTs.size() == 2) 2358 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2359 else 2360 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2361 2362 // Get the operand list. 2363 unsigned NumOps = MatcherTable[MatcherIndex++]; 2364 SmallVector<SDValue, 8> Ops; 2365 for (unsigned i = 0; i != NumOps; ++i) { 2366 unsigned RecNo = MatcherTable[MatcherIndex++]; 2367 if (RecNo & 128) 2368 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2369 2370 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2371 Ops.push_back(RecordedNodes[RecNo]); 2372 } 2373 2374 // If there are variadic operands to add, handle them now. 2375 if (EmitNodeInfo & OPFL_VariadicInfo) { 2376 // Determine the start index to copy from. 2377 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2378 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2379 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2380 "Invalid variadic node"); 2381 // Copy all of the variadic operands, not including a potential flag 2382 // input. 2383 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2384 i != e; ++i) { 2385 SDValue V = NodeToMatch->getOperand(i); 2386 if (V.getValueType() == MVT::Flag) break; 2387 Ops.push_back(V); 2388 } 2389 } 2390 2391 // If this has chain/flag inputs, add them. 2392 if (EmitNodeInfo & OPFL_Chain) 2393 Ops.push_back(InputChain); 2394 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2395 Ops.push_back(InputFlag); 2396 2397 // Create the node. 2398 SDNode *Res = 0; 2399 if (Opcode != OPC_MorphNodeTo) { 2400 // If this is a normal EmitNode command, just create the new node and 2401 // add the results to the RecordedNodes list. 2402 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2403 VTList, Ops.data(), Ops.size()); 2404 2405 // Add all the non-flag/non-chain results to the RecordedNodes list. 2406 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2407 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2408 RecordedNodes.push_back(SDValue(Res, i)); 2409 } 2410 2411 } else { 2412 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2413 EmitNodeInfo); 2414 } 2415 2416 // If the node had chain/flag results, update our notion of the current 2417 // chain and flag. 2418 if (EmitNodeInfo & OPFL_FlagOutput) { 2419 InputFlag = SDValue(Res, VTs.size()-1); 2420 if (EmitNodeInfo & OPFL_Chain) 2421 InputChain = SDValue(Res, VTs.size()-2); 2422 } else if (EmitNodeInfo & OPFL_Chain) 2423 InputChain = SDValue(Res, VTs.size()-1); 2424 2425 // If the OPFL_MemRefs flag is set on this node, slap all of the 2426 // accumulated memrefs onto it. 2427 // 2428 // FIXME: This is vastly incorrect for patterns with multiple outputs 2429 // instructions that access memory and for ComplexPatterns that match 2430 // loads. 2431 if (EmitNodeInfo & OPFL_MemRefs) { 2432 MachineSDNode::mmo_iterator MemRefs = 2433 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2434 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2435 cast<MachineSDNode>(Res) 2436 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2437 } 2438 2439 DEBUG(errs() << " " 2440 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2441 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2442 2443 // If this was a MorphNodeTo then we're completely done! 2444 if (Opcode == OPC_MorphNodeTo) { 2445 // Update chain and flag uses. 2446 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2447 InputFlag, FlagResultNodesMatched, true); 2448 return Res; 2449 } 2450 2451 continue; 2452 } 2453 2454 case OPC_MarkFlagResults: { 2455 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2456 2457 // Read and remember all the flag-result nodes. 2458 for (unsigned i = 0; i != NumNodes; ++i) { 2459 unsigned RecNo = MatcherTable[MatcherIndex++]; 2460 if (RecNo & 128) 2461 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2462 2463 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2464 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2465 } 2466 continue; 2467 } 2468 2469 case OPC_CompleteMatch: { 2470 // The match has been completed, and any new nodes (if any) have been 2471 // created. Patch up references to the matched dag to use the newly 2472 // created nodes. 2473 unsigned NumResults = MatcherTable[MatcherIndex++]; 2474 2475 for (unsigned i = 0; i != NumResults; ++i) { 2476 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2477 if (ResSlot & 128) 2478 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2479 2480 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2481 SDValue Res = RecordedNodes[ResSlot]; 2482 2483 assert(i < NodeToMatch->getNumValues() && 2484 NodeToMatch->getValueType(i) != MVT::Other && 2485 NodeToMatch->getValueType(i) != MVT::Flag && 2486 "Invalid number of results to complete!"); 2487 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2488 NodeToMatch->getValueType(i) == MVT::iPTR || 2489 Res.getValueType() == MVT::iPTR || 2490 NodeToMatch->getValueType(i).getSizeInBits() == 2491 Res.getValueType().getSizeInBits()) && 2492 "invalid replacement"); 2493 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2494 } 2495 2496 // If the root node defines a flag, add it to the flag nodes to update 2497 // list. 2498 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2499 FlagResultNodesMatched.push_back(NodeToMatch); 2500 2501 // Update chain and flag uses. 2502 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2503 InputFlag, FlagResultNodesMatched, false); 2504 2505 assert(NodeToMatch->use_empty() && 2506 "Didn't replace all uses of the node?"); 2507 2508 // FIXME: We just return here, which interacts correctly with SelectRoot 2509 // above. We should fix this to not return an SDNode* anymore. 2510 return 0; 2511 } 2512 } 2513 2514 // If the code reached this point, then the match failed. See if there is 2515 // another child to try in the current 'Scope', otherwise pop it until we 2516 // find a case to check. 2517 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2518 ++NumDAGIselRetries; 2519 while (1) { 2520 if (MatchScopes.empty()) { 2521 CannotYetSelect(NodeToMatch); 2522 return 0; 2523 } 2524 2525 // Restore the interpreter state back to the point where the scope was 2526 // formed. 2527 MatchScope &LastScope = MatchScopes.back(); 2528 RecordedNodes.resize(LastScope.NumRecordedNodes); 2529 NodeStack.clear(); 2530 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2531 N = NodeStack.back(); 2532 2533 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2534 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2535 MatcherIndex = LastScope.FailIndex; 2536 2537 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2538 2539 InputChain = LastScope.InputChain; 2540 InputFlag = LastScope.InputFlag; 2541 if (!LastScope.HasChainNodesMatched) 2542 ChainNodesMatched.clear(); 2543 if (!LastScope.HasFlagResultNodesMatched) 2544 FlagResultNodesMatched.clear(); 2545 2546 // Check to see what the offset is at the new MatcherIndex. If it is zero 2547 // we have reached the end of this scope, otherwise we have another child 2548 // in the current scope to try. 2549 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2550 if (NumToSkip & 128) 2551 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2552 2553 // If we have another child in this scope to match, update FailIndex and 2554 // try it. 2555 if (NumToSkip != 0) { 2556 LastScope.FailIndex = MatcherIndex+NumToSkip; 2557 break; 2558 } 2559 2560 // End of this scope, pop it and try the next child in the containing 2561 // scope. 2562 MatchScopes.pop_back(); 2563 } 2564 } 2565} 2566 2567 2568 2569void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2570 std::string msg; 2571 raw_string_ostream Msg(msg); 2572 Msg << "Cannot yet select: "; 2573 2574 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2575 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2576 N->getOpcode() != ISD::INTRINSIC_VOID) { 2577 N->printrFull(Msg, CurDAG); 2578 } else { 2579 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2580 unsigned iid = 2581 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2582 if (iid < Intrinsic::num_intrinsics) 2583 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2584 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2585 Msg << "target intrinsic %" << TII->getName(iid); 2586 else 2587 Msg << "unknown intrinsic #" << iid; 2588 } 2589 report_fatal_error(Msg.str()); 2590} 2591 2592char SelectionDAGISel::ID = 0; 2593