SelectionDAGISel.cpp revision 2046e12f022ad098fe84776d55f4ea1a5e342c85
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/MachineModuleInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/CodeGen/SSARegMap.h" 37#include "llvm/Target/MRegisterInfo.h" 38#include "llvm/Target/TargetData.h" 39#include "llvm/Target/TargetFrameInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Compiler.h" 47#include <algorithm> 48using namespace llvm; 49 50#ifndef NDEBUG 51static cl::opt<bool> 52ViewISelDAGs("view-isel-dags", cl::Hidden, 53 cl::desc("Pop up a window to show isel dags as they are selected")); 54static cl::opt<bool> 55ViewSchedDAGs("view-sched-dags", cl::Hidden, 56 cl::desc("Pop up a window to show sched dags as they are processed")); 57#else 58static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0; 59#endif 60 61//===---------------------------------------------------------------------===// 62/// 63/// RegisterScheduler class - Track the registration of instruction schedulers. 64/// 65//===---------------------------------------------------------------------===// 66MachinePassRegistry RegisterScheduler::Registry; 67 68//===---------------------------------------------------------------------===// 69/// 70/// ISHeuristic command line option for instruction schedulers. 71/// 72//===---------------------------------------------------------------------===// 73namespace { 74 cl::opt<RegisterScheduler::FunctionPassCtor, false, 75 RegisterPassParser<RegisterScheduler> > 76 ISHeuristic("sched", 77 cl::init(&createDefaultScheduler), 78 cl::desc("Instruction schedulers available:")); 79 80 static RegisterScheduler 81 defaultListDAGScheduler("default", " Best scheduler for the target", 82 createDefaultScheduler); 83} // namespace 84 85namespace { struct AsmOperandInfo; } 86 87namespace { 88 /// RegsForValue - This struct represents the physical registers that a 89 /// particular value is assigned and the type information about the value. 90 /// This is needed because values can be promoted into larger registers and 91 /// expanded into multiple smaller registers than the value. 92 struct VISIBILITY_HIDDEN RegsForValue { 93 /// Regs - This list hold the register (for legal and promoted values) 94 /// or register set (for expanded values) that the value should be assigned 95 /// to. 96 std::vector<unsigned> Regs; 97 98 /// RegVT - The value type of each register. 99 /// 100 MVT::ValueType RegVT; 101 102 /// ValueVT - The value type of the LLVM value, which may be promoted from 103 /// RegVT or made from merging the two expanded parts. 104 MVT::ValueType ValueVT; 105 106 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 107 108 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 109 : RegVT(regvt), ValueVT(valuevt) { 110 Regs.push_back(Reg); 111 } 112 RegsForValue(const std::vector<unsigned> ®s, 113 MVT::ValueType regvt, MVT::ValueType valuevt) 114 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 115 } 116 117 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 118 /// this value and returns the result as a ValueVT value. This uses 119 /// Chain/Flag as the input and updates them for the output Chain/Flag. 120 SDOperand getCopyFromRegs(SelectionDAG &DAG, 121 SDOperand &Chain, SDOperand &Flag) const; 122 123 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 124 /// specified value into the registers specified by this object. This uses 125 /// Chain/Flag as the input and updates them for the output Chain/Flag. 126 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 127 SDOperand &Chain, SDOperand &Flag, 128 MVT::ValueType PtrVT) const; 129 130 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 131 /// operand list. This adds the code marker and includes the number of 132 /// values added into it. 133 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 134 std::vector<SDOperand> &Ops) const; 135 }; 136} 137 138namespace llvm { 139 //===--------------------------------------------------------------------===// 140 /// createDefaultScheduler - This creates an instruction scheduler appropriate 141 /// for the target. 142 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 143 SelectionDAG *DAG, 144 MachineBasicBlock *BB) { 145 TargetLowering &TLI = IS->getTargetLowering(); 146 147 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 148 return createTDListDAGScheduler(IS, DAG, BB); 149 } else { 150 assert(TLI.getSchedulingPreference() == 151 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 152 return createBURRListDAGScheduler(IS, DAG, BB); 153 } 154 } 155 156 157 //===--------------------------------------------------------------------===// 158 /// FunctionLoweringInfo - This contains information that is global to a 159 /// function that is used when lowering a region of the function. 160 class FunctionLoweringInfo { 161 public: 162 TargetLowering &TLI; 163 Function &Fn; 164 MachineFunction &MF; 165 SSARegMap *RegMap; 166 167 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 168 169 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 170 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 171 172 /// ValueMap - Since we emit code for the function a basic block at a time, 173 /// we must remember which virtual registers hold the values for 174 /// cross-basic-block values. 175 DenseMap<const Value*, unsigned> ValueMap; 176 177 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 178 /// the entry block. This allows the allocas to be efficiently referenced 179 /// anywhere in the function. 180 std::map<const AllocaInst*, int> StaticAllocaMap; 181 182 unsigned MakeReg(MVT::ValueType VT) { 183 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 184 } 185 186 /// isExportedInst - Return true if the specified value is an instruction 187 /// exported from its block. 188 bool isExportedInst(const Value *V) { 189 return ValueMap.count(V); 190 } 191 192 unsigned CreateRegForValue(const Value *V); 193 194 unsigned InitializeRegForValue(const Value *V) { 195 unsigned &R = ValueMap[V]; 196 assert(R == 0 && "Already initialized this value register!"); 197 return R = CreateRegForValue(V); 198 } 199 }; 200} 201 202/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 203/// PHI nodes or outside of the basic block that defines it, or used by a 204/// switch instruction, which may expand to multiple basic blocks. 205static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 206 if (isa<PHINode>(I)) return true; 207 BasicBlock *BB = I->getParent(); 208 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 209 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 210 // FIXME: Remove switchinst special case. 211 isa<SwitchInst>(*UI)) 212 return true; 213 return false; 214} 215 216/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 217/// entry block, return true. This includes arguments used by switches, since 218/// the switch may expand into multiple basic blocks. 219static bool isOnlyUsedInEntryBlock(Argument *A) { 220 BasicBlock *Entry = A->getParent()->begin(); 221 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 222 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 223 return false; // Use not in entry block. 224 return true; 225} 226 227FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 228 Function &fn, MachineFunction &mf) 229 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 230 231 // Create a vreg for each argument register that is not dead and is used 232 // outside of the entry block for the function. 233 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 234 AI != E; ++AI) 235 if (!isOnlyUsedInEntryBlock(AI)) 236 InitializeRegForValue(AI); 237 238 // Initialize the mapping of values to registers. This is only set up for 239 // instruction values that are used outside of the block that defines 240 // them. 241 Function::iterator BB = Fn.begin(), EB = Fn.end(); 242 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 243 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 244 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 245 const Type *Ty = AI->getAllocatedType(); 246 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 247 unsigned Align = 248 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 249 AI->getAlignment()); 250 251 TySize *= CUI->getZExtValue(); // Get total allocated size. 252 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 253 StaticAllocaMap[AI] = 254 MF.getFrameInfo()->CreateStackObject(TySize, Align); 255 } 256 257 for (; BB != EB; ++BB) 258 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 259 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 260 if (!isa<AllocaInst>(I) || 261 !StaticAllocaMap.count(cast<AllocaInst>(I))) 262 InitializeRegForValue(I); 263 264 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 265 // also creates the initial PHI MachineInstrs, though none of the input 266 // operands are populated. 267 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 268 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 269 MBBMap[BB] = MBB; 270 MF.getBasicBlockList().push_back(MBB); 271 272 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 273 // appropriate. 274 PHINode *PN; 275 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 276 if (PN->use_empty()) continue; 277 278 MVT::ValueType VT = TLI.getValueType(PN->getType()); 279 unsigned NumElements; 280 if (VT != MVT::Vector) 281 NumElements = TLI.getNumElements(VT); 282 else { 283 MVT::ValueType VT1,VT2; 284 NumElements = 285 TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()), 286 VT1, VT2); 287 } 288 unsigned PHIReg = ValueMap[PN]; 289 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 290 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 291 for (unsigned i = 0; i != NumElements; ++i) 292 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 293 } 294 } 295} 296 297/// CreateRegForValue - Allocate the appropriate number of virtual registers of 298/// the correctly promoted or expanded types. Assign these registers 299/// consecutive vreg numbers and return the first assigned number. 300unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 301 MVT::ValueType VT = TLI.getValueType(V->getType()); 302 303 // The number of multiples of registers that we need, to, e.g., split up 304 // a <2 x int64> -> 4 x i32 registers. 305 unsigned NumVectorRegs = 1; 306 307 // If this is a vector type, figure out what type it will decompose into 308 // and how many of the elements it will use. 309 if (VT == MVT::Vector) { 310 const VectorType *PTy = cast<VectorType>(V->getType()); 311 unsigned NumElts = PTy->getNumElements(); 312 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType()); 313 MVT::ValueType VecTy = MVT::getVectorType(EltTy, NumElts); 314 315 // Divide the input until we get to a supported size. This will always 316 // end with a scalar if the target doesn't support vectors. 317 while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) { 318 NumElts >>= 1; 319 NumVectorRegs <<= 1; 320 VecTy = MVT::getVectorType(EltTy, NumElts); 321 } 322 323 // Check that VecTy isn't a 1-element vector. 324 if (NumElts == 1 && VecTy == MVT::Other) 325 VT = EltTy; 326 else 327 VT = VecTy; 328 } 329 330 // The common case is that we will only create one register for this 331 // value. If we have that case, create and return the virtual register. 332 unsigned NV = TLI.getNumElements(VT); 333 if (NV == 1) { 334 // If we are promoting this value, pick the next largest supported type. 335 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT); 336 unsigned Reg = MakeReg(PromotedType); 337 // If this is a vector of supported or promoted types (e.g. 4 x i16), 338 // create all of the registers. 339 for (unsigned i = 1; i != NumVectorRegs; ++i) 340 MakeReg(PromotedType); 341 return Reg; 342 } 343 344 // If this value is represented with multiple target registers, make sure 345 // to create enough consecutive registers of the right (smaller) type. 346 VT = TLI.getTypeToExpandTo(VT); 347 unsigned R = MakeReg(VT); 348 for (unsigned i = 1; i != NV*NumVectorRegs; ++i) 349 MakeReg(VT); 350 return R; 351} 352 353//===----------------------------------------------------------------------===// 354/// SelectionDAGLowering - This is the common target-independent lowering 355/// implementation that is parameterized by a TargetLowering object. 356/// Also, targets can overload any lowering method. 357/// 358namespace llvm { 359class SelectionDAGLowering { 360 MachineBasicBlock *CurMBB; 361 362 DenseMap<const Value*, SDOperand> NodeMap; 363 364 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 365 /// them up and then emit token factor nodes when possible. This allows us to 366 /// get simple disambiguation between loads without worrying about alias 367 /// analysis. 368 std::vector<SDOperand> PendingLoads; 369 370 /// Case - A struct to record the Value for a switch case, and the 371 /// case's target basic block. 372 struct Case { 373 Constant* Low; 374 Constant* High; 375 MachineBasicBlock* BB; 376 377 Case() : Low(0), High(0), BB(0) { } 378 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 379 Low(low), High(high), BB(bb) { } 380 uint64_t size() const { 381 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 382 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 383 return (rHigh - rLow + 1ULL); 384 } 385 }; 386 387 struct CaseBits { 388 uint64_t Mask; 389 MachineBasicBlock* BB; 390 unsigned Bits; 391 392 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 393 Mask(mask), BB(bb), Bits(bits) { } 394 }; 395 396 typedef std::vector<Case> CaseVector; 397 typedef std::vector<CaseBits> CaseBitsVector; 398 typedef CaseVector::iterator CaseItr; 399 typedef std::pair<CaseItr, CaseItr> CaseRange; 400 401 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 402 /// of conditional branches. 403 struct CaseRec { 404 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 405 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 406 407 /// CaseBB - The MBB in which to emit the compare and branch 408 MachineBasicBlock *CaseBB; 409 /// LT, GE - If nonzero, we know the current case value must be less-than or 410 /// greater-than-or-equal-to these Constants. 411 Constant *LT; 412 Constant *GE; 413 /// Range - A pair of iterators representing the range of case values to be 414 /// processed at this point in the binary search tree. 415 CaseRange Range; 416 }; 417 418 typedef std::vector<CaseRec> CaseRecVector; 419 420 /// The comparison function for sorting the switch case values in the vector. 421 /// WARNING: Case ranges should be disjoint! 422 struct CaseCmp { 423 bool operator () (const Case& C1, const Case& C2) { 424 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 425 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 426 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 427 return CI1->getValue().slt(CI2->getValue()); 428 } 429 }; 430 431 struct CaseBitsCmp { 432 bool operator () (const CaseBits& C1, const CaseBits& C2) { 433 return C1.Bits > C2.Bits; 434 } 435 }; 436 437 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 438 439public: 440 // TLI - This is information that describes the available target features we 441 // need for lowering. This indicates when operations are unavailable, 442 // implemented with a libcall, etc. 443 TargetLowering &TLI; 444 SelectionDAG &DAG; 445 const TargetData *TD; 446 447 /// SwitchCases - Vector of CaseBlock structures used to communicate 448 /// SwitchInst code generation information. 449 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 450 /// JTCases - Vector of JumpTable structures used to communicate 451 /// SwitchInst code generation information. 452 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 453 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 454 455 /// FuncInfo - Information about the function as a whole. 456 /// 457 FunctionLoweringInfo &FuncInfo; 458 459 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 460 FunctionLoweringInfo &funcinfo) 461 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), 462 FuncInfo(funcinfo) { 463 } 464 465 /// getRoot - Return the current virtual root of the Selection DAG. 466 /// 467 SDOperand getRoot() { 468 if (PendingLoads.empty()) 469 return DAG.getRoot(); 470 471 if (PendingLoads.size() == 1) { 472 SDOperand Root = PendingLoads[0]; 473 DAG.setRoot(Root); 474 PendingLoads.clear(); 475 return Root; 476 } 477 478 // Otherwise, we have to make a token factor node. 479 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 480 &PendingLoads[0], PendingLoads.size()); 481 PendingLoads.clear(); 482 DAG.setRoot(Root); 483 return Root; 484 } 485 486 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 487 488 void visit(Instruction &I) { visit(I.getOpcode(), I); } 489 490 void visit(unsigned Opcode, User &I) { 491 // Note: this doesn't use InstVisitor, because it has to work with 492 // ConstantExpr's in addition to instructions. 493 switch (Opcode) { 494 default: assert(0 && "Unknown instruction type encountered!"); 495 abort(); 496 // Build the switch statement using the Instruction.def file. 497#define HANDLE_INST(NUM, OPCODE, CLASS) \ 498 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 499#include "llvm/Instruction.def" 500 } 501 } 502 503 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 504 505 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 506 const Value *SV, SDOperand Root, 507 bool isVolatile, unsigned Alignment); 508 509 SDOperand getIntPtrConstant(uint64_t Val) { 510 return DAG.getConstant(Val, TLI.getPointerTy()); 511 } 512 513 SDOperand getValue(const Value *V); 514 515 void setValue(const Value *V, SDOperand NewN) { 516 SDOperand &N = NodeMap[V]; 517 assert(N.Val == 0 && "Already set a value for this node!"); 518 N = NewN; 519 } 520 521 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 522 std::set<unsigned> &OutputRegs, 523 std::set<unsigned> &InputRegs); 524 525 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 526 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 527 unsigned Opc); 528 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 529 void ExportFromCurrentBlock(Value *V); 530 void LowerCallTo(Instruction &I, 531 const Type *CalledValueTy, unsigned CallingConv, 532 bool IsTailCall, SDOperand Callee, unsigned OpIdx, 533 MachineBasicBlock *LandingPad = NULL); 534 535 // Terminator instructions. 536 void visitRet(ReturnInst &I); 537 void visitBr(BranchInst &I); 538 void visitSwitch(SwitchInst &I); 539 void visitUnreachable(UnreachableInst &I) { /* noop */ } 540 541 // Helpers for visitSwitch 542 bool handleSmallSwitchRange(CaseRec& CR, 543 CaseRecVector& WorkList, 544 Value* SV, 545 MachineBasicBlock* Default); 546 bool handleJTSwitchCase(CaseRec& CR, 547 CaseRecVector& WorkList, 548 Value* SV, 549 MachineBasicBlock* Default); 550 bool handleBTSplitSwitchCase(CaseRec& CR, 551 CaseRecVector& WorkList, 552 Value* SV, 553 MachineBasicBlock* Default); 554 bool handleBitTestsSwitchCase(CaseRec& CR, 555 CaseRecVector& WorkList, 556 Value* SV, 557 MachineBasicBlock* Default); 558 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 559 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 560 void visitBitTestCase(MachineBasicBlock* NextMBB, 561 unsigned Reg, 562 SelectionDAGISel::BitTestCase &B); 563 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 564 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 565 SelectionDAGISel::JumpTableHeader &JTH); 566 567 // These all get lowered before this pass. 568 void visitInvoke(InvokeInst &I); 569 void visitUnwind(UnwindInst &I); 570 571 void visitScalarBinary(User &I, unsigned OpCode); 572 void visitVectorBinary(User &I, unsigned OpCode); 573 void visitEitherBinary(User &I, unsigned ScalarOp, unsigned VectorOp); 574 void visitShift(User &I, unsigned Opcode); 575 void visitAdd(User &I) { 576 if (isa<VectorType>(I.getType())) 577 visitVectorBinary(I, ISD::VADD); 578 else if (I.getType()->isFloatingPoint()) 579 visitScalarBinary(I, ISD::FADD); 580 else 581 visitScalarBinary(I, ISD::ADD); 582 } 583 void visitSub(User &I); 584 void visitMul(User &I) { 585 if (isa<VectorType>(I.getType())) 586 visitVectorBinary(I, ISD::VMUL); 587 else if (I.getType()->isFloatingPoint()) 588 visitScalarBinary(I, ISD::FMUL); 589 else 590 visitScalarBinary(I, ISD::MUL); 591 } 592 void visitURem(User &I) { visitScalarBinary(I, ISD::UREM); } 593 void visitSRem(User &I) { visitScalarBinary(I, ISD::SREM); } 594 void visitFRem(User &I) { visitScalarBinary(I, ISD::FREM); } 595 void visitUDiv(User &I) { visitEitherBinary(I, ISD::UDIV, ISD::VUDIV); } 596 void visitSDiv(User &I) { visitEitherBinary(I, ISD::SDIV, ISD::VSDIV); } 597 void visitFDiv(User &I) { visitEitherBinary(I, ISD::FDIV, ISD::VSDIV); } 598 void visitAnd (User &I) { visitEitherBinary(I, ISD::AND, ISD::VAND ); } 599 void visitOr (User &I) { visitEitherBinary(I, ISD::OR, ISD::VOR ); } 600 void visitXor (User &I) { visitEitherBinary(I, ISD::XOR, ISD::VXOR ); } 601 void visitShl (User &I) { visitShift(I, ISD::SHL); } 602 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 603 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 604 void visitICmp(User &I); 605 void visitFCmp(User &I); 606 // Visit the conversion instructions 607 void visitTrunc(User &I); 608 void visitZExt(User &I); 609 void visitSExt(User &I); 610 void visitFPTrunc(User &I); 611 void visitFPExt(User &I); 612 void visitFPToUI(User &I); 613 void visitFPToSI(User &I); 614 void visitUIToFP(User &I); 615 void visitSIToFP(User &I); 616 void visitPtrToInt(User &I); 617 void visitIntToPtr(User &I); 618 void visitBitCast(User &I); 619 620 void visitExtractElement(User &I); 621 void visitInsertElement(User &I); 622 void visitShuffleVector(User &I); 623 624 void visitGetElementPtr(User &I); 625 void visitSelect(User &I); 626 627 void visitMalloc(MallocInst &I); 628 void visitFree(FreeInst &I); 629 void visitAlloca(AllocaInst &I); 630 void visitLoad(LoadInst &I); 631 void visitStore(StoreInst &I); 632 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 633 void visitCall(CallInst &I); 634 void visitInlineAsm(CallInst &I); 635 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 636 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 637 638 void visitVAStart(CallInst &I); 639 void visitVAArg(VAArgInst &I); 640 void visitVAEnd(CallInst &I); 641 void visitVACopy(CallInst &I); 642 643 void visitMemIntrinsic(CallInst &I, unsigned Op); 644 645 void visitUserOp1(Instruction &I) { 646 assert(0 && "UserOp1 should not exist at instruction selection time!"); 647 abort(); 648 } 649 void visitUserOp2(Instruction &I) { 650 assert(0 && "UserOp2 should not exist at instruction selection time!"); 651 abort(); 652 } 653}; 654} // end namespace llvm 655 656SDOperand SelectionDAGLowering::getValue(const Value *V) { 657 SDOperand &N = NodeMap[V]; 658 if (N.Val) return N; 659 660 const Type *VTy = V->getType(); 661 MVT::ValueType VT = TLI.getValueType(VTy); 662 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 663 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 664 visit(CE->getOpcode(), *CE); 665 SDOperand N1 = NodeMap[V]; 666 assert(N1.Val && "visit didn't populate the ValueMap!"); 667 return N1; 668 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 669 return N = DAG.getGlobalAddress(GV, VT); 670 } else if (isa<ConstantPointerNull>(C)) { 671 return N = DAG.getConstant(0, TLI.getPointerTy()); 672 } else if (isa<UndefValue>(C)) { 673 if (!isa<VectorType>(VTy)) 674 return N = DAG.getNode(ISD::UNDEF, VT); 675 676 // Create a VBUILD_VECTOR of undef nodes. 677 const VectorType *PTy = cast<VectorType>(VTy); 678 unsigned NumElements = PTy->getNumElements(); 679 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 680 681 SmallVector<SDOperand, 8> Ops; 682 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 683 684 // Create a VConstant node with generic Vector type. 685 Ops.push_back(DAG.getConstant(NumElements, MVT::i32)); 686 Ops.push_back(DAG.getValueType(PVT)); 687 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 688 &Ops[0], Ops.size()); 689 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 690 return N = DAG.getConstantFP(CFP->getValue(), VT); 691 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 692 unsigned NumElements = PTy->getNumElements(); 693 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 694 695 // Now that we know the number and type of the elements, push a 696 // Constant or ConstantFP node onto the ops list for each element of 697 // the packed constant. 698 SmallVector<SDOperand, 8> Ops; 699 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 700 for (unsigned i = 0; i != NumElements; ++i) 701 Ops.push_back(getValue(CP->getOperand(i))); 702 } else { 703 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!"); 704 SDOperand Op; 705 if (MVT::isFloatingPoint(PVT)) 706 Op = DAG.getConstantFP(0, PVT); 707 else 708 Op = DAG.getConstant(0, PVT); 709 Ops.assign(NumElements, Op); 710 } 711 712 // Create a VBUILD_VECTOR node with generic Vector type. 713 Ops.push_back(DAG.getConstant(NumElements, MVT::i32)); 714 Ops.push_back(DAG.getValueType(PVT)); 715 return NodeMap[V] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], 716 Ops.size()); 717 } else { 718 // Canonicalize all constant ints to be unsigned. 719 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT); 720 } 721 } 722 723 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 724 std::map<const AllocaInst*, int>::iterator SI = 725 FuncInfo.StaticAllocaMap.find(AI); 726 if (SI != FuncInfo.StaticAllocaMap.end()) 727 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 728 } 729 730 unsigned InReg = FuncInfo.ValueMap[V]; 731 assert(InReg && "Value not in map!"); 732 733 // If this type is not legal, make it so now. 734 if (VT != MVT::Vector) { 735 if (TLI.getTypeAction(VT) == TargetLowering::Expand) { 736 // Source must be expanded. This input value is actually coming from the 737 // register pair InReg and InReg+1. 738 MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT); 739 unsigned NumVals = TLI.getNumElements(VT); 740 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); 741 if (NumVals == 1) 742 N = DAG.getNode(ISD::BIT_CONVERT, VT, N); 743 else { 744 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!"); 745 N = DAG.getNode(ISD::BUILD_PAIR, VT, N, 746 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT)); 747 } 748 } else { 749 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT); 750 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); 751 if (TLI.getTypeAction(VT) == TargetLowering::Promote) // Promotion case 752 N = MVT::isFloatingPoint(VT) 753 ? DAG.getNode(ISD::FP_ROUND, VT, N) 754 : DAG.getNode(ISD::TRUNCATE, VT, N); 755 } 756 } else { 757 // Otherwise, if this is a vector, make it available as a generic vector 758 // here. 759 MVT::ValueType PTyElementVT, PTyLegalElementVT; 760 const VectorType *PTy = cast<VectorType>(VTy); 761 unsigned NE = TLI.getVectorTypeBreakdown(PTy, PTyElementVT, 762 PTyLegalElementVT); 763 764 // Build a VBUILD_VECTOR with the input registers. 765 SmallVector<SDOperand, 8> Ops; 766 if (PTyElementVT == PTyLegalElementVT) { 767 // If the value types are legal, just VBUILD the CopyFromReg nodes. 768 for (unsigned i = 0; i != NE; ++i) 769 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 770 PTyElementVT)); 771 } else if (PTyElementVT < PTyLegalElementVT) { 772 // If the register was promoted, use TRUNCATE or FP_ROUND as appropriate. 773 for (unsigned i = 0; i != NE; ++i) { 774 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 775 PTyLegalElementVT); 776 if (MVT::isFloatingPoint(PTyElementVT)) 777 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op); 778 else 779 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op); 780 Ops.push_back(Op); 781 } 782 } else { 783 // If the register was expanded, use BUILD_PAIR. 784 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!"); 785 for (unsigned i = 0; i != NE; ++i) { 786 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 787 PTyLegalElementVT); 788 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 789 PTyLegalElementVT); 790 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, PTyElementVT, Op0, Op1)); 791 } 792 } 793 794 Ops.push_back(DAG.getConstant(NE, MVT::i32)); 795 Ops.push_back(DAG.getValueType(PTyElementVT)); 796 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 797 798 // Finally, use a VBIT_CONVERT to make this available as the appropriate 799 // vector type. 800 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, 801 DAG.getConstant(PTy->getNumElements(), 802 MVT::i32), 803 DAG.getValueType(TLI.getValueType(PTy->getElementType()))); 804 } 805 806 return N; 807} 808 809 810void SelectionDAGLowering::visitRet(ReturnInst &I) { 811 if (I.getNumOperands() == 0) { 812 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 813 return; 814 } 815 SmallVector<SDOperand, 8> NewValues; 816 NewValues.push_back(getRoot()); 817 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 818 SDOperand RetOp = getValue(I.getOperand(i)); 819 820 // If this is an integer return value, we need to promote it ourselves to 821 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather 822 // than sign/zero. 823 // FIXME: C calling convention requires the return type to be promoted to 824 // at least 32-bit. But this is not necessary for non-C calling conventions. 825 if (MVT::isInteger(RetOp.getValueType()) && 826 RetOp.getValueType() < MVT::i64) { 827 MVT::ValueType TmpVT; 828 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 829 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 830 else 831 TmpVT = MVT::i32; 832 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType(); 833 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 834 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 835 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt)) 836 ExtendKind = ISD::SIGN_EXTEND; 837 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt)) 838 ExtendKind = ISD::ZERO_EXTEND; 839 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp); 840 } 841 NewValues.push_back(RetOp); 842 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 843 } 844 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 845 &NewValues[0], NewValues.size())); 846} 847 848/// ExportFromCurrentBlock - If this condition isn't known to be exported from 849/// the current basic block, add it to ValueMap now so that we'll get a 850/// CopyTo/FromReg. 851void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 852 // No need to export constants. 853 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 854 855 // Already exported? 856 if (FuncInfo.isExportedInst(V)) return; 857 858 unsigned Reg = FuncInfo.InitializeRegForValue(V); 859 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 860} 861 862bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 863 const BasicBlock *FromBB) { 864 // The operands of the setcc have to be in this block. We don't know 865 // how to export them from some other block. 866 if (Instruction *VI = dyn_cast<Instruction>(V)) { 867 // Can export from current BB. 868 if (VI->getParent() == FromBB) 869 return true; 870 871 // Is already exported, noop. 872 return FuncInfo.isExportedInst(V); 873 } 874 875 // If this is an argument, we can export it if the BB is the entry block or 876 // if it is already exported. 877 if (isa<Argument>(V)) { 878 if (FromBB == &FromBB->getParent()->getEntryBlock()) 879 return true; 880 881 // Otherwise, can only export this if it is already exported. 882 return FuncInfo.isExportedInst(V); 883 } 884 885 // Otherwise, constants can always be exported. 886 return true; 887} 888 889static bool InBlock(const Value *V, const BasicBlock *BB) { 890 if (const Instruction *I = dyn_cast<Instruction>(V)) 891 return I->getParent() == BB; 892 return true; 893} 894 895/// FindMergedConditions - If Cond is an expression like 896void SelectionDAGLowering::FindMergedConditions(Value *Cond, 897 MachineBasicBlock *TBB, 898 MachineBasicBlock *FBB, 899 MachineBasicBlock *CurBB, 900 unsigned Opc) { 901 // If this node is not part of the or/and tree, emit it as a branch. 902 Instruction *BOp = dyn_cast<Instruction>(Cond); 903 904 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 905 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 906 BOp->getParent() != CurBB->getBasicBlock() || 907 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 908 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 909 const BasicBlock *BB = CurBB->getBasicBlock(); 910 911 // If the leaf of the tree is a comparison, merge the condition into 912 // the caseblock. 913 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 914 // The operands of the cmp have to be in this block. We don't know 915 // how to export them from some other block. If this is the first block 916 // of the sequence, no exporting is needed. 917 (CurBB == CurMBB || 918 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 919 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 920 BOp = cast<Instruction>(Cond); 921 ISD::CondCode Condition; 922 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 923 switch (IC->getPredicate()) { 924 default: assert(0 && "Unknown icmp predicate opcode!"); 925 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 926 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 927 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 928 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 929 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 930 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 931 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 932 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 933 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 934 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 935 } 936 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 937 ISD::CondCode FPC, FOC; 938 switch (FC->getPredicate()) { 939 default: assert(0 && "Unknown fcmp predicate opcode!"); 940 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 941 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 942 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 943 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 944 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 945 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 946 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 947 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 948 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 949 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 950 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 951 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 952 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 953 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 954 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 955 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 956 } 957 if (FiniteOnlyFPMath()) 958 Condition = FOC; 959 else 960 Condition = FPC; 961 } else { 962 Condition = ISD::SETEQ; // silence warning. 963 assert(0 && "Unknown compare instruction"); 964 } 965 966 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 967 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 968 SwitchCases.push_back(CB); 969 return; 970 } 971 972 // Create a CaseBlock record representing this branch. 973 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 974 NULL, TBB, FBB, CurBB); 975 SwitchCases.push_back(CB); 976 return; 977 } 978 979 980 // Create TmpBB after CurBB. 981 MachineFunction::iterator BBI = CurBB; 982 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 983 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 984 985 if (Opc == Instruction::Or) { 986 // Codegen X | Y as: 987 // jmp_if_X TBB 988 // jmp TmpBB 989 // TmpBB: 990 // jmp_if_Y TBB 991 // jmp FBB 992 // 993 994 // Emit the LHS condition. 995 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 996 997 // Emit the RHS condition into TmpBB. 998 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 999 } else { 1000 assert(Opc == Instruction::And && "Unknown merge op!"); 1001 // Codegen X & Y as: 1002 // jmp_if_X TmpBB 1003 // jmp FBB 1004 // TmpBB: 1005 // jmp_if_Y TBB 1006 // jmp FBB 1007 // 1008 // This requires creation of TmpBB after CurBB. 1009 1010 // Emit the LHS condition. 1011 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1012 1013 // Emit the RHS condition into TmpBB. 1014 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1015 } 1016} 1017 1018/// If the set of cases should be emitted as a series of branches, return true. 1019/// If we should emit this as a bunch of and/or'd together conditions, return 1020/// false. 1021static bool 1022ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1023 if (Cases.size() != 2) return true; 1024 1025 // If this is two comparisons of the same values or'd or and'd together, they 1026 // will get folded into a single comparison, so don't emit two blocks. 1027 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1028 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1029 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1030 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1031 return false; 1032 } 1033 1034 return true; 1035} 1036 1037void SelectionDAGLowering::visitBr(BranchInst &I) { 1038 // Update machine-CFG edges. 1039 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1040 1041 // Figure out which block is immediately after the current one. 1042 MachineBasicBlock *NextBlock = 0; 1043 MachineFunction::iterator BBI = CurMBB; 1044 if (++BBI != CurMBB->getParent()->end()) 1045 NextBlock = BBI; 1046 1047 if (I.isUnconditional()) { 1048 // If this is not a fall-through branch, emit the branch. 1049 if (Succ0MBB != NextBlock) 1050 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1051 DAG.getBasicBlock(Succ0MBB))); 1052 1053 // Update machine-CFG edges. 1054 CurMBB->addSuccessor(Succ0MBB); 1055 1056 return; 1057 } 1058 1059 // If this condition is one of the special cases we handle, do special stuff 1060 // now. 1061 Value *CondVal = I.getCondition(); 1062 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1063 1064 // If this is a series of conditions that are or'd or and'd together, emit 1065 // this as a sequence of branches instead of setcc's with and/or operations. 1066 // For example, instead of something like: 1067 // cmp A, B 1068 // C = seteq 1069 // cmp D, E 1070 // F = setle 1071 // or C, F 1072 // jnz foo 1073 // Emit: 1074 // cmp A, B 1075 // je foo 1076 // cmp D, E 1077 // jle foo 1078 // 1079 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1080 if (BOp->hasOneUse() && 1081 (BOp->getOpcode() == Instruction::And || 1082 BOp->getOpcode() == Instruction::Or)) { 1083 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1084 // If the compares in later blocks need to use values not currently 1085 // exported from this block, export them now. This block should always 1086 // be the first entry. 1087 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1088 1089 // Allow some cases to be rejected. 1090 if (ShouldEmitAsBranches(SwitchCases)) { 1091 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1092 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1093 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1094 } 1095 1096 // Emit the branch for this block. 1097 visitSwitchCase(SwitchCases[0]); 1098 SwitchCases.erase(SwitchCases.begin()); 1099 return; 1100 } 1101 1102 // Okay, we decided not to do this, remove any inserted MBB's and clear 1103 // SwitchCases. 1104 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1105 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1106 1107 SwitchCases.clear(); 1108 } 1109 } 1110 1111 // Create a CaseBlock record representing this branch. 1112 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1113 NULL, Succ0MBB, Succ1MBB, CurMBB); 1114 // Use visitSwitchCase to actually insert the fast branch sequence for this 1115 // cond branch. 1116 visitSwitchCase(CB); 1117} 1118 1119/// visitSwitchCase - Emits the necessary code to represent a single node in 1120/// the binary search tree resulting from lowering a switch instruction. 1121void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1122 SDOperand Cond; 1123 SDOperand CondLHS = getValue(CB.CmpLHS); 1124 1125 // Build the setcc now. 1126 if (CB.CmpMHS == NULL) { 1127 // Fold "(X == true)" to X and "(X == false)" to !X to 1128 // handle common cases produced by branch lowering. 1129 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1130 Cond = CondLHS; 1131 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1132 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1133 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1134 } else 1135 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1136 } else { 1137 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1138 1139 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1140 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1141 1142 SDOperand CmpOp = getValue(CB.CmpMHS); 1143 MVT::ValueType VT = CmpOp.getValueType(); 1144 1145 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1146 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1147 } else { 1148 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1149 Cond = DAG.getSetCC(MVT::i1, SUB, 1150 DAG.getConstant(High-Low, VT), ISD::SETULE); 1151 } 1152 1153 } 1154 1155 // Set NextBlock to be the MBB immediately after the current one, if any. 1156 // This is used to avoid emitting unnecessary branches to the next block. 1157 MachineBasicBlock *NextBlock = 0; 1158 MachineFunction::iterator BBI = CurMBB; 1159 if (++BBI != CurMBB->getParent()->end()) 1160 NextBlock = BBI; 1161 1162 // If the lhs block is the next block, invert the condition so that we can 1163 // fall through to the lhs instead of the rhs block. 1164 if (CB.TrueBB == NextBlock) { 1165 std::swap(CB.TrueBB, CB.FalseBB); 1166 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1167 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1168 } 1169 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1170 DAG.getBasicBlock(CB.TrueBB)); 1171 if (CB.FalseBB == NextBlock) 1172 DAG.setRoot(BrCond); 1173 else 1174 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1175 DAG.getBasicBlock(CB.FalseBB))); 1176 // Update successor info 1177 CurMBB->addSuccessor(CB.TrueBB); 1178 CurMBB->addSuccessor(CB.FalseBB); 1179} 1180 1181/// visitJumpTable - Emit JumpTable node in the current MBB 1182void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1183 // Emit the code for the jump table 1184 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1185 MVT::ValueType PTy = TLI.getPointerTy(); 1186 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1187 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1188 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1189 Table, Index)); 1190 return; 1191} 1192 1193/// visitJumpTableHeader - This function emits necessary code to produce index 1194/// in the JumpTable from switch case. 1195void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1196 SelectionDAGISel::JumpTableHeader &JTH) { 1197 // Subtract the lowest switch case value from the value being switched on 1198 // and conditional branch to default mbb if the result is greater than the 1199 // difference between smallest and largest cases. 1200 SDOperand SwitchOp = getValue(JTH.SValue); 1201 MVT::ValueType VT = SwitchOp.getValueType(); 1202 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1203 DAG.getConstant(JTH.First, VT)); 1204 1205 // The SDNode we just created, which holds the value being switched on 1206 // minus the the smallest case value, needs to be copied to a virtual 1207 // register so it can be used as an index into the jump table in a 1208 // subsequent basic block. This value may be smaller or larger than the 1209 // target's pointer type, and therefore require extension or truncating. 1210 if (VT > TLI.getPointerTy()) 1211 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1212 else 1213 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1214 1215 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1216 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1217 JT.Reg = JumpTableReg; 1218 1219 // Emit the range check for the jump table, and branch to the default 1220 // block for the switch statement if the value being switched on exceeds 1221 // the largest case in the switch. 1222 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1223 DAG.getConstant(JTH.Last-JTH.First,VT), 1224 ISD::SETUGT); 1225 1226 // Set NextBlock to be the MBB immediately after the current one, if any. 1227 // This is used to avoid emitting unnecessary branches to the next block. 1228 MachineBasicBlock *NextBlock = 0; 1229 MachineFunction::iterator BBI = CurMBB; 1230 if (++BBI != CurMBB->getParent()->end()) 1231 NextBlock = BBI; 1232 1233 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1234 DAG.getBasicBlock(JT.Default)); 1235 1236 if (JT.MBB == NextBlock) 1237 DAG.setRoot(BrCond); 1238 else 1239 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1240 DAG.getBasicBlock(JT.MBB))); 1241 1242 return; 1243} 1244 1245/// visitBitTestHeader - This function emits necessary code to produce value 1246/// suitable for "bit tests" 1247void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1248 // Subtract the minimum value 1249 SDOperand SwitchOp = getValue(B.SValue); 1250 MVT::ValueType VT = SwitchOp.getValueType(); 1251 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1252 DAG.getConstant(B.First, VT)); 1253 1254 // Check range 1255 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1256 DAG.getConstant(B.Range, VT), 1257 ISD::SETUGT); 1258 1259 SDOperand ShiftOp; 1260 if (VT > TLI.getShiftAmountTy()) 1261 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1262 else 1263 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1264 1265 // Make desired shift 1266 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1267 DAG.getConstant(1, TLI.getPointerTy()), 1268 ShiftOp); 1269 1270 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1271 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1272 B.Reg = SwitchReg; 1273 1274 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1275 DAG.getBasicBlock(B.Default)); 1276 1277 // Set NextBlock to be the MBB immediately after the current one, if any. 1278 // This is used to avoid emitting unnecessary branches to the next block. 1279 MachineBasicBlock *NextBlock = 0; 1280 MachineFunction::iterator BBI = CurMBB; 1281 if (++BBI != CurMBB->getParent()->end()) 1282 NextBlock = BBI; 1283 1284 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1285 if (MBB == NextBlock) 1286 DAG.setRoot(BrRange); 1287 else 1288 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1289 DAG.getBasicBlock(MBB))); 1290 1291 CurMBB->addSuccessor(B.Default); 1292 CurMBB->addSuccessor(MBB); 1293 1294 return; 1295} 1296 1297/// visitBitTestCase - this function produces one "bit test" 1298void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1299 unsigned Reg, 1300 SelectionDAGISel::BitTestCase &B) { 1301 // Emit bit tests and jumps 1302 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1303 1304 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1305 SwitchVal, 1306 DAG.getConstant(B.Mask, 1307 TLI.getPointerTy())); 1308 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, 1309 DAG.getConstant(0, TLI.getPointerTy()), 1310 ISD::SETNE); 1311 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1312 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1313 1314 // Set NextBlock to be the MBB immediately after the current one, if any. 1315 // This is used to avoid emitting unnecessary branches to the next block. 1316 MachineBasicBlock *NextBlock = 0; 1317 MachineFunction::iterator BBI = CurMBB; 1318 if (++BBI != CurMBB->getParent()->end()) 1319 NextBlock = BBI; 1320 1321 if (NextMBB == NextBlock) 1322 DAG.setRoot(BrAnd); 1323 else 1324 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1325 DAG.getBasicBlock(NextMBB))); 1326 1327 CurMBB->addSuccessor(B.TargetBB); 1328 CurMBB->addSuccessor(NextMBB); 1329 1330 return; 1331} 1332 1333void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1334 // Retrieve successors. 1335 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1336 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1337 1338 LowerCallTo(I, I.getCalledValue()->getType(), 1339 I.getCallingConv(), 1340 false, 1341 getValue(I.getOperand(0)), 1342 3, LandingPad); 1343 1344 // If the value of the invoke is used outside of its defining block, make it 1345 // available as a virtual register. 1346 if (!I.use_empty()) { 1347 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1348 if (VMI != FuncInfo.ValueMap.end()) 1349 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second)); 1350 } 1351 1352 // Drop into normal successor. 1353 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1354 DAG.getBasicBlock(Return))); 1355 1356 // Update successor info 1357 CurMBB->addSuccessor(Return); 1358 CurMBB->addSuccessor(LandingPad); 1359} 1360 1361void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1362} 1363 1364/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1365/// small case ranges). 1366bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1367 CaseRecVector& WorkList, 1368 Value* SV, 1369 MachineBasicBlock* Default) { 1370 Case& BackCase = *(CR.Range.second-1); 1371 1372 // Size is the number of Cases represented by this range. 1373 unsigned Size = CR.Range.second - CR.Range.first; 1374 if (Size > 3) 1375 return false; 1376 1377 // Get the MachineFunction which holds the current MBB. This is used when 1378 // inserting any additional MBBs necessary to represent the switch. 1379 MachineFunction *CurMF = CurMBB->getParent(); 1380 1381 // Figure out which block is immediately after the current one. 1382 MachineBasicBlock *NextBlock = 0; 1383 MachineFunction::iterator BBI = CR.CaseBB; 1384 1385 if (++BBI != CurMBB->getParent()->end()) 1386 NextBlock = BBI; 1387 1388 // TODO: If any two of the cases has the same destination, and if one value 1389 // is the same as the other, but has one bit unset that the other has set, 1390 // use bit manipulation to do two compares at once. For example: 1391 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1392 1393 // Rearrange the case blocks so that the last one falls through if possible. 1394 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1395 // The last case block won't fall through into 'NextBlock' if we emit the 1396 // branches in this order. See if rearranging a case value would help. 1397 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1398 if (I->BB == NextBlock) { 1399 std::swap(*I, BackCase); 1400 break; 1401 } 1402 } 1403 } 1404 1405 // Create a CaseBlock record representing a conditional branch to 1406 // the Case's target mbb if the value being switched on SV is equal 1407 // to C. 1408 MachineBasicBlock *CurBlock = CR.CaseBB; 1409 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1410 MachineBasicBlock *FallThrough; 1411 if (I != E-1) { 1412 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1413 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1414 } else { 1415 // If the last case doesn't match, go to the default block. 1416 FallThrough = Default; 1417 } 1418 1419 Value *RHS, *LHS, *MHS; 1420 ISD::CondCode CC; 1421 if (I->High == I->Low) { 1422 // This is just small small case range :) containing exactly 1 case 1423 CC = ISD::SETEQ; 1424 LHS = SV; RHS = I->High; MHS = NULL; 1425 } else { 1426 CC = ISD::SETLE; 1427 LHS = I->Low; MHS = SV; RHS = I->High; 1428 } 1429 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1430 I->BB, FallThrough, CurBlock); 1431 1432 // If emitting the first comparison, just call visitSwitchCase to emit the 1433 // code into the current block. Otherwise, push the CaseBlock onto the 1434 // vector to be later processed by SDISel, and insert the node's MBB 1435 // before the next MBB. 1436 if (CurBlock == CurMBB) 1437 visitSwitchCase(CB); 1438 else 1439 SwitchCases.push_back(CB); 1440 1441 CurBlock = FallThrough; 1442 } 1443 1444 return true; 1445} 1446 1447static inline bool areJTsAllowed(const TargetLowering &TLI) { 1448 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1449 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1450} 1451 1452/// handleJTSwitchCase - Emit jumptable for current switch case range 1453bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1454 CaseRecVector& WorkList, 1455 Value* SV, 1456 MachineBasicBlock* Default) { 1457 Case& FrontCase = *CR.Range.first; 1458 Case& BackCase = *(CR.Range.second-1); 1459 1460 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1461 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1462 1463 uint64_t TSize = 0; 1464 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1465 I!=E; ++I) 1466 TSize += I->size(); 1467 1468 if (!areJTsAllowed(TLI) || TSize <= 3) 1469 return false; 1470 1471 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1472 if (Density < 0.4) 1473 return false; 1474 1475 DOUT << "Lowering jump table\n" 1476 << "First entry: " << First << ". Last entry: " << Last << "\n" 1477 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1478 1479 // Get the MachineFunction which holds the current MBB. This is used when 1480 // inserting any additional MBBs necessary to represent the switch. 1481 MachineFunction *CurMF = CurMBB->getParent(); 1482 1483 // Figure out which block is immediately after the current one. 1484 MachineBasicBlock *NextBlock = 0; 1485 MachineFunction::iterator BBI = CR.CaseBB; 1486 1487 if (++BBI != CurMBB->getParent()->end()) 1488 NextBlock = BBI; 1489 1490 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1491 1492 // Create a new basic block to hold the code for loading the address 1493 // of the jump table, and jumping to it. Update successor information; 1494 // we will either branch to the default case for the switch, or the jump 1495 // table. 1496 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1497 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1498 CR.CaseBB->addSuccessor(Default); 1499 CR.CaseBB->addSuccessor(JumpTableBB); 1500 1501 // Build a vector of destination BBs, corresponding to each target 1502 // of the jump table. If the value of the jump table slot corresponds to 1503 // a case statement, push the case's BB onto the vector, otherwise, push 1504 // the default BB. 1505 std::vector<MachineBasicBlock*> DestBBs; 1506 int64_t TEI = First; 1507 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1508 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1509 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1510 1511 if ((Low <= TEI) && (TEI <= High)) { 1512 DestBBs.push_back(I->BB); 1513 if (TEI==High) 1514 ++I; 1515 } else { 1516 DestBBs.push_back(Default); 1517 } 1518 } 1519 1520 // Update successor info. Add one edge to each unique successor. 1521 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1522 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1523 E = DestBBs.end(); I != E; ++I) { 1524 if (!SuccsHandled[(*I)->getNumber()]) { 1525 SuccsHandled[(*I)->getNumber()] = true; 1526 JumpTableBB->addSuccessor(*I); 1527 } 1528 } 1529 1530 // Create a jump table index for this jump table, or return an existing 1531 // one. 1532 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1533 1534 // Set the jump table information so that we can codegen it as a second 1535 // MachineBasicBlock 1536 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1537 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1538 (CR.CaseBB == CurMBB)); 1539 if (CR.CaseBB == CurMBB) 1540 visitJumpTableHeader(JT, JTH); 1541 1542 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1543 1544 return true; 1545} 1546 1547/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1548/// 2 subtrees. 1549bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1550 CaseRecVector& WorkList, 1551 Value* SV, 1552 MachineBasicBlock* Default) { 1553 // Get the MachineFunction which holds the current MBB. This is used when 1554 // inserting any additional MBBs necessary to represent the switch. 1555 MachineFunction *CurMF = CurMBB->getParent(); 1556 1557 // Figure out which block is immediately after the current one. 1558 MachineBasicBlock *NextBlock = 0; 1559 MachineFunction::iterator BBI = CR.CaseBB; 1560 1561 if (++BBI != CurMBB->getParent()->end()) 1562 NextBlock = BBI; 1563 1564 Case& FrontCase = *CR.Range.first; 1565 Case& BackCase = *(CR.Range.second-1); 1566 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1567 1568 // Size is the number of Cases represented by this range. 1569 unsigned Size = CR.Range.second - CR.Range.first; 1570 1571 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1572 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1573 double FMetric = 0; 1574 CaseItr Pivot = CR.Range.first + Size/2; 1575 1576 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1577 // (heuristically) allow us to emit JumpTable's later. 1578 uint64_t TSize = 0; 1579 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1580 I!=E; ++I) 1581 TSize += I->size(); 1582 1583 uint64_t LSize = FrontCase.size(); 1584 uint64_t RSize = TSize-LSize; 1585 DOUT << "Selecting best pivot: \n" 1586 << "First: " << First << ", Last: " << Last <<"\n" 1587 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1588 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1589 J!=E; ++I, ++J) { 1590 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1591 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1592 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1593 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1594 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1595 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1596 // Should always split in some non-trivial place 1597 DOUT <<"=>Step\n" 1598 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1599 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1600 << "Metric: " << Metric << "\n"; 1601 if (FMetric < Metric) { 1602 Pivot = J; 1603 FMetric = Metric; 1604 DOUT << "Current metric set to: " << FMetric << "\n"; 1605 } 1606 1607 LSize += J->size(); 1608 RSize -= J->size(); 1609 } 1610 if (areJTsAllowed(TLI)) { 1611 // If our case is dense we *really* should handle it earlier! 1612 assert((FMetric > 0) && "Should handle dense range earlier!"); 1613 } else { 1614 Pivot = CR.Range.first + Size/2; 1615 } 1616 1617 CaseRange LHSR(CR.Range.first, Pivot); 1618 CaseRange RHSR(Pivot, CR.Range.second); 1619 Constant *C = Pivot->Low; 1620 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1621 1622 // We know that we branch to the LHS if the Value being switched on is 1623 // less than the Pivot value, C. We use this to optimize our binary 1624 // tree a bit, by recognizing that if SV is greater than or equal to the 1625 // LHS's Case Value, and that Case Value is exactly one less than the 1626 // Pivot's Value, then we can branch directly to the LHS's Target, 1627 // rather than creating a leaf node for it. 1628 if ((LHSR.second - LHSR.first) == 1 && 1629 LHSR.first->High == CR.GE && 1630 cast<ConstantInt>(C)->getSExtValue() == 1631 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1632 TrueBB = LHSR.first->BB; 1633 } else { 1634 TrueBB = new MachineBasicBlock(LLVMBB); 1635 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1636 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1637 } 1638 1639 // Similar to the optimization above, if the Value being switched on is 1640 // known to be less than the Constant CR.LT, and the current Case Value 1641 // is CR.LT - 1, then we can branch directly to the target block for 1642 // the current Case Value, rather than emitting a RHS leaf node for it. 1643 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1644 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1645 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1646 FalseBB = RHSR.first->BB; 1647 } else { 1648 FalseBB = new MachineBasicBlock(LLVMBB); 1649 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1650 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1651 } 1652 1653 // Create a CaseBlock record representing a conditional branch to 1654 // the LHS node if the value being switched on SV is less than C. 1655 // Otherwise, branch to LHS. 1656 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1657 TrueBB, FalseBB, CR.CaseBB); 1658 1659 if (CR.CaseBB == CurMBB) 1660 visitSwitchCase(CB); 1661 else 1662 SwitchCases.push_back(CB); 1663 1664 return true; 1665} 1666 1667/// handleBitTestsSwitchCase - if current case range has few destination and 1668/// range span less, than machine word bitwidth, encode case range into series 1669/// of masks and emit bit tests with these masks. 1670bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1671 CaseRecVector& WorkList, 1672 Value* SV, 1673 MachineBasicBlock* Default){ 1674 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); 1675 1676 Case& FrontCase = *CR.Range.first; 1677 Case& BackCase = *(CR.Range.second-1); 1678 1679 // Get the MachineFunction which holds the current MBB. This is used when 1680 // inserting any additional MBBs necessary to represent the switch. 1681 MachineFunction *CurMF = CurMBB->getParent(); 1682 1683 unsigned numCmps = 0; 1684 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1685 I!=E; ++I) { 1686 // Single case counts one, case range - two. 1687 if (I->Low == I->High) 1688 numCmps +=1; 1689 else 1690 numCmps +=2; 1691 } 1692 1693 // Count unique destinations 1694 SmallSet<MachineBasicBlock*, 4> Dests; 1695 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1696 Dests.insert(I->BB); 1697 if (Dests.size() > 3) 1698 // Don't bother the code below, if there are too much unique destinations 1699 return false; 1700 } 1701 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1702 << "Total number of comparisons: " << numCmps << "\n"; 1703 1704 // Compute span of values. 1705 Constant* minValue = FrontCase.Low; 1706 Constant* maxValue = BackCase.High; 1707 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1708 cast<ConstantInt>(minValue)->getSExtValue(); 1709 DOUT << "Compare range: " << range << "\n" 1710 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1711 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1712 1713 if (range>=IntPtrBits || 1714 (!(Dests.size() == 1 && numCmps >= 3) && 1715 !(Dests.size() == 2 && numCmps >= 5) && 1716 !(Dests.size() >= 3 && numCmps >= 6))) 1717 return false; 1718 1719 DOUT << "Emitting bit tests\n"; 1720 int64_t lowBound = 0; 1721 1722 // Optimize the case where all the case values fit in a 1723 // word without having to subtract minValue. In this case, 1724 // we can optimize away the subtraction. 1725 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1726 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1727 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1728 } else { 1729 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1730 } 1731 1732 CaseBitsVector CasesBits; 1733 unsigned i, count = 0; 1734 1735 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1736 MachineBasicBlock* Dest = I->BB; 1737 for (i = 0; i < count; ++i) 1738 if (Dest == CasesBits[i].BB) 1739 break; 1740 1741 if (i == count) { 1742 assert((count < 3) && "Too much destinations to test!"); 1743 CasesBits.push_back(CaseBits(0, Dest, 0)); 1744 count++; 1745 } 1746 1747 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1748 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1749 1750 for (uint64_t j = lo; j <= hi; j++) { 1751 CasesBits[i].Mask |= 1ULL << j; 1752 CasesBits[i].Bits++; 1753 } 1754 1755 } 1756 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1757 1758 SelectionDAGISel::BitTestInfo BTC; 1759 1760 // Figure out which block is immediately after the current one. 1761 MachineFunction::iterator BBI = CR.CaseBB; 1762 ++BBI; 1763 1764 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1765 1766 DOUT << "Cases:\n"; 1767 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1768 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1769 << ", BB: " << CasesBits[i].BB << "\n"; 1770 1771 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1772 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1773 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1774 CaseBB, 1775 CasesBits[i].BB)); 1776 } 1777 1778 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 1779 -1U, (CR.CaseBB == CurMBB), 1780 CR.CaseBB, Default, BTC); 1781 1782 if (CR.CaseBB == CurMBB) 1783 visitBitTestHeader(BTB); 1784 1785 BitTestCases.push_back(BTB); 1786 1787 return true; 1788} 1789 1790 1791// Clusterify - Transform simple list of Cases into list of CaseRange's 1792unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 1793 const SwitchInst& SI) { 1794 unsigned numCmps = 0; 1795 1796 // Start with "simple" cases 1797 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 1798 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1799 Cases.push_back(Case(SI.getSuccessorValue(i), 1800 SI.getSuccessorValue(i), 1801 SMBB)); 1802 } 1803 sort(Cases.begin(), Cases.end(), CaseCmp()); 1804 1805 // Merge case into clusters 1806 if (Cases.size()>=2) 1807 for (CaseItr I=Cases.begin(), J=++(Cases.begin()), E=Cases.end(); J!=E; ) { 1808 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 1809 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 1810 MachineBasicBlock* nextBB = J->BB; 1811 MachineBasicBlock* currentBB = I->BB; 1812 1813 // If the two neighboring cases go to the same destination, merge them 1814 // into a single case. 1815 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 1816 I->High = J->High; 1817 J = Cases.erase(J); 1818 } else { 1819 I = J++; 1820 } 1821 } 1822 1823 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1824 if (I->Low != I->High) 1825 // A range counts double, since it requires two compares. 1826 ++numCmps; 1827 } 1828 1829 return numCmps; 1830} 1831 1832void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 1833 // Figure out which block is immediately after the current one. 1834 MachineBasicBlock *NextBlock = 0; 1835 MachineFunction::iterator BBI = CurMBB; 1836 1837 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 1838 1839 // If there is only the default destination, branch to it if it is not the 1840 // next basic block. Otherwise, just fall through. 1841 if (SI.getNumOperands() == 2) { 1842 // Update machine-CFG edges. 1843 1844 // If this is not a fall-through branch, emit the branch. 1845 if (Default != NextBlock) 1846 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1847 DAG.getBasicBlock(Default))); 1848 1849 CurMBB->addSuccessor(Default); 1850 return; 1851 } 1852 1853 // If there are any non-default case statements, create a vector of Cases 1854 // representing each one, and sort the vector so that we can efficiently 1855 // create a binary search tree from them. 1856 CaseVector Cases; 1857 unsigned numCmps = Clusterify(Cases, SI); 1858 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 1859 << ". Total compares: " << numCmps << "\n"; 1860 1861 // Get the Value to be switched on and default basic blocks, which will be 1862 // inserted into CaseBlock records, representing basic blocks in the binary 1863 // search tree. 1864 Value *SV = SI.getOperand(0); 1865 1866 // Push the initial CaseRec onto the worklist 1867 CaseRecVector WorkList; 1868 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1869 1870 while (!WorkList.empty()) { 1871 // Grab a record representing a case range to process off the worklist 1872 CaseRec CR = WorkList.back(); 1873 WorkList.pop_back(); 1874 1875 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 1876 continue; 1877 1878 // If the range has few cases (two or less) emit a series of specific 1879 // tests. 1880 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 1881 continue; 1882 1883 // If the switch has more than 5 blocks, and at least 40% dense, and the 1884 // target supports indirect branches, then emit a jump table rather than 1885 // lowering the switch to a binary tree of conditional branches. 1886 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 1887 continue; 1888 1889 // Emit binary tree. We need to pick a pivot, and push left and right ranges 1890 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 1891 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 1892 } 1893} 1894 1895 1896void SelectionDAGLowering::visitSub(User &I) { 1897 // -0.0 - X --> fneg 1898 const Type *Ty = I.getType(); 1899 if (isa<VectorType>(Ty)) { 1900 visitVectorBinary(I, ISD::VSUB); 1901 } else if (Ty->isFloatingPoint()) { 1902 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 1903 if (CFP->isExactlyValue(-0.0)) { 1904 SDOperand Op2 = getValue(I.getOperand(1)); 1905 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 1906 return; 1907 } 1908 visitScalarBinary(I, ISD::FSUB); 1909 } else 1910 visitScalarBinary(I, ISD::SUB); 1911} 1912 1913void SelectionDAGLowering::visitScalarBinary(User &I, unsigned OpCode) { 1914 SDOperand Op1 = getValue(I.getOperand(0)); 1915 SDOperand Op2 = getValue(I.getOperand(1)); 1916 1917 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 1918} 1919 1920void 1921SelectionDAGLowering::visitVectorBinary(User &I, unsigned OpCode) { 1922 assert(isa<VectorType>(I.getType())); 1923 const VectorType *Ty = cast<VectorType>(I.getType()); 1924 SDOperand Typ = DAG.getValueType(TLI.getValueType(Ty->getElementType())); 1925 1926 setValue(&I, DAG.getNode(OpCode, MVT::Vector, 1927 getValue(I.getOperand(0)), 1928 getValue(I.getOperand(1)), 1929 DAG.getConstant(Ty->getNumElements(), MVT::i32), 1930 Typ)); 1931} 1932 1933void SelectionDAGLowering::visitEitherBinary(User &I, unsigned ScalarOp, 1934 unsigned VectorOp) { 1935 if (isa<VectorType>(I.getType())) 1936 visitVectorBinary(I, VectorOp); 1937 else 1938 visitScalarBinary(I, ScalarOp); 1939} 1940 1941void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 1942 SDOperand Op1 = getValue(I.getOperand(0)); 1943 SDOperand Op2 = getValue(I.getOperand(1)); 1944 1945 if (TLI.getShiftAmountTy() < Op2.getValueType()) 1946 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 1947 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 1948 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 1949 1950 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 1951} 1952 1953void SelectionDAGLowering::visitICmp(User &I) { 1954 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 1955 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 1956 predicate = IC->getPredicate(); 1957 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 1958 predicate = ICmpInst::Predicate(IC->getPredicate()); 1959 SDOperand Op1 = getValue(I.getOperand(0)); 1960 SDOperand Op2 = getValue(I.getOperand(1)); 1961 ISD::CondCode Opcode; 1962 switch (predicate) { 1963 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 1964 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 1965 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 1966 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 1967 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 1968 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 1969 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 1970 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 1971 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 1972 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 1973 default: 1974 assert(!"Invalid ICmp predicate value"); 1975 Opcode = ISD::SETEQ; 1976 break; 1977 } 1978 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 1979} 1980 1981void SelectionDAGLowering::visitFCmp(User &I) { 1982 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 1983 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 1984 predicate = FC->getPredicate(); 1985 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 1986 predicate = FCmpInst::Predicate(FC->getPredicate()); 1987 SDOperand Op1 = getValue(I.getOperand(0)); 1988 SDOperand Op2 = getValue(I.getOperand(1)); 1989 ISD::CondCode Condition, FOC, FPC; 1990 switch (predicate) { 1991 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1992 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1993 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1994 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1995 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1996 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1997 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1998 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 1999 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 2000 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2001 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2002 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2003 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2004 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2005 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2006 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2007 default: 2008 assert(!"Invalid FCmp predicate value"); 2009 FOC = FPC = ISD::SETFALSE; 2010 break; 2011 } 2012 if (FiniteOnlyFPMath()) 2013 Condition = FOC; 2014 else 2015 Condition = FPC; 2016 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2017} 2018 2019void SelectionDAGLowering::visitSelect(User &I) { 2020 SDOperand Cond = getValue(I.getOperand(0)); 2021 SDOperand TrueVal = getValue(I.getOperand(1)); 2022 SDOperand FalseVal = getValue(I.getOperand(2)); 2023 if (!isa<VectorType>(I.getType())) { 2024 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2025 TrueVal, FalseVal)); 2026 } else { 2027 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal, 2028 *(TrueVal.Val->op_end()-2), 2029 *(TrueVal.Val->op_end()-1))); 2030 } 2031} 2032 2033 2034void SelectionDAGLowering::visitTrunc(User &I) { 2035 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2036 SDOperand N = getValue(I.getOperand(0)); 2037 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2038 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2039} 2040 2041void SelectionDAGLowering::visitZExt(User &I) { 2042 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2043 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2044 SDOperand N = getValue(I.getOperand(0)); 2045 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2046 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2047} 2048 2049void SelectionDAGLowering::visitSExt(User &I) { 2050 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2051 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2052 SDOperand N = getValue(I.getOperand(0)); 2053 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2054 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2055} 2056 2057void SelectionDAGLowering::visitFPTrunc(User &I) { 2058 // FPTrunc is never a no-op cast, no need to check 2059 SDOperand N = getValue(I.getOperand(0)); 2060 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2061 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 2062} 2063 2064void SelectionDAGLowering::visitFPExt(User &I){ 2065 // FPTrunc is never a no-op cast, no need to check 2066 SDOperand N = getValue(I.getOperand(0)); 2067 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2068 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2069} 2070 2071void SelectionDAGLowering::visitFPToUI(User &I) { 2072 // FPToUI is never a no-op cast, no need to check 2073 SDOperand N = getValue(I.getOperand(0)); 2074 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2075 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2076} 2077 2078void SelectionDAGLowering::visitFPToSI(User &I) { 2079 // FPToSI is never a no-op cast, no need to check 2080 SDOperand N = getValue(I.getOperand(0)); 2081 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2082 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2083} 2084 2085void SelectionDAGLowering::visitUIToFP(User &I) { 2086 // UIToFP is never a no-op cast, no need to check 2087 SDOperand N = getValue(I.getOperand(0)); 2088 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2089 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2090} 2091 2092void SelectionDAGLowering::visitSIToFP(User &I){ 2093 // UIToFP is never a no-op cast, no need to check 2094 SDOperand N = getValue(I.getOperand(0)); 2095 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2096 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2097} 2098 2099void SelectionDAGLowering::visitPtrToInt(User &I) { 2100 // What to do depends on the size of the integer and the size of the pointer. 2101 // We can either truncate, zero extend, or no-op, accordingly. 2102 SDOperand N = getValue(I.getOperand(0)); 2103 MVT::ValueType SrcVT = N.getValueType(); 2104 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2105 SDOperand Result; 2106 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2107 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2108 else 2109 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2110 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2111 setValue(&I, Result); 2112} 2113 2114void SelectionDAGLowering::visitIntToPtr(User &I) { 2115 // What to do depends on the size of the integer and the size of the pointer. 2116 // We can either truncate, zero extend, or no-op, accordingly. 2117 SDOperand N = getValue(I.getOperand(0)); 2118 MVT::ValueType SrcVT = N.getValueType(); 2119 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2120 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2121 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2122 else 2123 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2124 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2125} 2126 2127void SelectionDAGLowering::visitBitCast(User &I) { 2128 SDOperand N = getValue(I.getOperand(0)); 2129 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2130 if (DestVT == MVT::Vector) { 2131 // This is a cast to a vector from something else. 2132 // Get information about the output vector. 2133 const VectorType *DestTy = cast<VectorType>(I.getType()); 2134 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2135 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N, 2136 DAG.getConstant(DestTy->getNumElements(),MVT::i32), 2137 DAG.getValueType(EltVT))); 2138 return; 2139 } 2140 MVT::ValueType SrcVT = N.getValueType(); 2141 if (SrcVT == MVT::Vector) { 2142 // This is a cast from a vctor to something else. 2143 // Get information about the input vector. 2144 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N)); 2145 return; 2146 } 2147 2148 // BitCast assures us that source and destination are the same size so this 2149 // is either a BIT_CONVERT or a no-op. 2150 if (DestVT != N.getValueType()) 2151 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2152 else 2153 setValue(&I, N); // noop cast. 2154} 2155 2156void SelectionDAGLowering::visitInsertElement(User &I) { 2157 SDOperand InVec = getValue(I.getOperand(0)); 2158 SDOperand InVal = getValue(I.getOperand(1)); 2159 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2160 getValue(I.getOperand(2))); 2161 2162 SDOperand Num = *(InVec.Val->op_end()-2); 2163 SDOperand Typ = *(InVec.Val->op_end()-1); 2164 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector, 2165 InVec, InVal, InIdx, Num, Typ)); 2166} 2167 2168void SelectionDAGLowering::visitExtractElement(User &I) { 2169 SDOperand InVec = getValue(I.getOperand(0)); 2170 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2171 getValue(I.getOperand(1))); 2172 SDOperand Typ = *(InVec.Val->op_end()-1); 2173 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, 2174 TLI.getValueType(I.getType()), InVec, InIdx)); 2175} 2176 2177void SelectionDAGLowering::visitShuffleVector(User &I) { 2178 SDOperand V1 = getValue(I.getOperand(0)); 2179 SDOperand V2 = getValue(I.getOperand(1)); 2180 SDOperand Mask = getValue(I.getOperand(2)); 2181 2182 SDOperand Num = *(V1.Val->op_end()-2); 2183 SDOperand Typ = *(V2.Val->op_end()-1); 2184 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 2185 V1, V2, Mask, Num, Typ)); 2186} 2187 2188 2189void SelectionDAGLowering::visitGetElementPtr(User &I) { 2190 SDOperand N = getValue(I.getOperand(0)); 2191 const Type *Ty = I.getOperand(0)->getType(); 2192 2193 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2194 OI != E; ++OI) { 2195 Value *Idx = *OI; 2196 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2197 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2198 if (Field) { 2199 // N = N + Offset 2200 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2201 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2202 getIntPtrConstant(Offset)); 2203 } 2204 Ty = StTy->getElementType(Field); 2205 } else { 2206 Ty = cast<SequentialType>(Ty)->getElementType(); 2207 2208 // If this is a constant subscript, handle it quickly. 2209 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2210 if (CI->getZExtValue() == 0) continue; 2211 uint64_t Offs = 2212 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2213 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 2214 continue; 2215 } 2216 2217 // N = N + Idx * ElementSize; 2218 uint64_t ElementSize = TD->getTypeSize(Ty); 2219 SDOperand IdxN = getValue(Idx); 2220 2221 // If the index is smaller or larger than intptr_t, truncate or extend 2222 // it. 2223 if (IdxN.getValueType() < N.getValueType()) { 2224 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2225 } else if (IdxN.getValueType() > N.getValueType()) 2226 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2227 2228 // If this is a multiply by a power of two, turn it into a shl 2229 // immediately. This is a very common case. 2230 if (isPowerOf2_64(ElementSize)) { 2231 unsigned Amt = Log2_64(ElementSize); 2232 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2233 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2234 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2235 continue; 2236 } 2237 2238 SDOperand Scale = getIntPtrConstant(ElementSize); 2239 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2240 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2241 } 2242 } 2243 setValue(&I, N); 2244} 2245 2246void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2247 // If this is a fixed sized alloca in the entry block of the function, 2248 // allocate it statically on the stack. 2249 if (FuncInfo.StaticAllocaMap.count(&I)) 2250 return; // getValue will auto-populate this. 2251 2252 const Type *Ty = I.getAllocatedType(); 2253 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 2254 unsigned Align = 2255 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2256 I.getAlignment()); 2257 2258 SDOperand AllocSize = getValue(I.getArraySize()); 2259 MVT::ValueType IntPtr = TLI.getPointerTy(); 2260 if (IntPtr < AllocSize.getValueType()) 2261 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2262 else if (IntPtr > AllocSize.getValueType()) 2263 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2264 2265 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2266 getIntPtrConstant(TySize)); 2267 2268 // Handle alignment. If the requested alignment is less than or equal to the 2269 // stack alignment, ignore it and round the size of the allocation up to the 2270 // stack alignment size. If the size is greater than the stack alignment, we 2271 // note this in the DYNAMIC_STACKALLOC node. 2272 unsigned StackAlign = 2273 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2274 if (Align <= StackAlign) { 2275 Align = 0; 2276 // Add SA-1 to the size. 2277 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2278 getIntPtrConstant(StackAlign-1)); 2279 // Mask out the low bits for alignment purposes. 2280 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2281 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2282 } 2283 2284 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 2285 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2286 MVT::Other); 2287 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2288 setValue(&I, DSA); 2289 DAG.setRoot(DSA.getValue(1)); 2290 2291 // Inform the Frame Information that we have just allocated a variable-sized 2292 // object. 2293 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2294} 2295 2296void SelectionDAGLowering::visitLoad(LoadInst &I) { 2297 SDOperand Ptr = getValue(I.getOperand(0)); 2298 2299 SDOperand Root; 2300 if (I.isVolatile()) 2301 Root = getRoot(); 2302 else { 2303 // Do not serialize non-volatile loads against each other. 2304 Root = DAG.getRoot(); 2305 } 2306 2307 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2308 Root, I.isVolatile(), I.getAlignment())); 2309} 2310 2311SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2312 const Value *SV, SDOperand Root, 2313 bool isVolatile, 2314 unsigned Alignment) { 2315 SDOperand L; 2316 if (const VectorType *PTy = dyn_cast<VectorType>(Ty)) { 2317 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 2318 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, 2319 DAG.getSrcValue(SV)); 2320 } else { 2321 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2322 isVolatile, Alignment); 2323 } 2324 2325 if (isVolatile) 2326 DAG.setRoot(L.getValue(1)); 2327 else 2328 PendingLoads.push_back(L.getValue(1)); 2329 2330 return L; 2331} 2332 2333 2334void SelectionDAGLowering::visitStore(StoreInst &I) { 2335 Value *SrcV = I.getOperand(0); 2336 SDOperand Src = getValue(SrcV); 2337 SDOperand Ptr = getValue(I.getOperand(1)); 2338 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2339 I.isVolatile(), I.getAlignment())); 2340} 2341 2342/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot 2343/// access memory and has no other side effects at all. 2344static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) { 2345#define GET_NO_MEMORY_INTRINSICS 2346#include "llvm/Intrinsics.gen" 2347#undef GET_NO_MEMORY_INTRINSICS 2348 return false; 2349} 2350 2351// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't 2352// have any side-effects or if it only reads memory. 2353static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) { 2354#define GET_SIDE_EFFECT_INFO 2355#include "llvm/Intrinsics.gen" 2356#undef GET_SIDE_EFFECT_INFO 2357 return false; 2358} 2359 2360/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2361/// node. 2362void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2363 unsigned Intrinsic) { 2364 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic); 2365 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic); 2366 2367 // Build the operand list. 2368 SmallVector<SDOperand, 8> Ops; 2369 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2370 if (OnlyLoad) { 2371 // We don't need to serialize loads against other loads. 2372 Ops.push_back(DAG.getRoot()); 2373 } else { 2374 Ops.push_back(getRoot()); 2375 } 2376 } 2377 2378 // Add the intrinsic ID as an integer operand. 2379 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2380 2381 // Add all operands of the call to the operand list. 2382 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2383 SDOperand Op = getValue(I.getOperand(i)); 2384 2385 // If this is a vector type, force it to the right vector type. 2386 if (Op.getValueType() == MVT::Vector) { 2387 const VectorType *OpTy = cast<VectorType>(I.getOperand(i)->getType()); 2388 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType()); 2389 2390 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements()); 2391 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?"); 2392 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op); 2393 } 2394 2395 assert(TLI.isTypeLegal(Op.getValueType()) && 2396 "Intrinsic uses a non-legal type?"); 2397 Ops.push_back(Op); 2398 } 2399 2400 std::vector<MVT::ValueType> VTs; 2401 if (I.getType() != Type::VoidTy) { 2402 MVT::ValueType VT = TLI.getValueType(I.getType()); 2403 if (VT == MVT::Vector) { 2404 const VectorType *DestTy = cast<VectorType>(I.getType()); 2405 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2406 2407 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2408 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2409 } 2410 2411 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2412 VTs.push_back(VT); 2413 } 2414 if (HasChain) 2415 VTs.push_back(MVT::Other); 2416 2417 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2418 2419 // Create the node. 2420 SDOperand Result; 2421 if (!HasChain) 2422 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2423 &Ops[0], Ops.size()); 2424 else if (I.getType() != Type::VoidTy) 2425 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2426 &Ops[0], Ops.size()); 2427 else 2428 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2429 &Ops[0], Ops.size()); 2430 2431 if (HasChain) { 2432 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2433 if (OnlyLoad) 2434 PendingLoads.push_back(Chain); 2435 else 2436 DAG.setRoot(Chain); 2437 } 2438 if (I.getType() != Type::VoidTy) { 2439 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2440 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType()); 2441 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 2442 DAG.getConstant(PTy->getNumElements(), MVT::i32), 2443 DAG.getValueType(EVT)); 2444 } 2445 setValue(&I, Result); 2446 } 2447} 2448 2449/// ExtractGlobalVariable - If C is a global variable, or a bitcast of one 2450/// (possibly constant folded), return it. Otherwise return NULL. 2451static GlobalVariable *ExtractGlobalVariable (Constant *C) { 2452 if (GlobalVariable *GV = dyn_cast<GlobalVariable>(C)) 2453 return GV; 2454 else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 2455 if (CE->getOpcode() == Instruction::BitCast) 2456 return dyn_cast<GlobalVariable>(CE->getOperand(0)); 2457 else if (CE->getOpcode() == Instruction::GetElementPtr) { 2458 for (unsigned i = 1, e = CE->getNumOperands(); i != e; ++i) 2459 if (!CE->getOperand(i)->isNullValue()) 2460 return NULL; 2461 return dyn_cast<GlobalVariable>(CE->getOperand(0)); 2462 } 2463 } 2464 return NULL; 2465} 2466 2467/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2468/// we want to emit this as a call to a named external function, return the name 2469/// otherwise lower it and return null. 2470const char * 2471SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2472 switch (Intrinsic) { 2473 default: 2474 // By default, turn this into a target intrinsic node. 2475 visitTargetIntrinsic(I, Intrinsic); 2476 return 0; 2477 case Intrinsic::vastart: visitVAStart(I); return 0; 2478 case Intrinsic::vaend: visitVAEnd(I); return 0; 2479 case Intrinsic::vacopy: visitVACopy(I); return 0; 2480 case Intrinsic::returnaddress: 2481 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2482 getValue(I.getOperand(1)))); 2483 return 0; 2484 case Intrinsic::frameaddress: 2485 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2486 getValue(I.getOperand(1)))); 2487 return 0; 2488 case Intrinsic::setjmp: 2489 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2490 break; 2491 case Intrinsic::longjmp: 2492 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2493 break; 2494 case Intrinsic::memcpy_i32: 2495 case Intrinsic::memcpy_i64: 2496 visitMemIntrinsic(I, ISD::MEMCPY); 2497 return 0; 2498 case Intrinsic::memset_i32: 2499 case Intrinsic::memset_i64: 2500 visitMemIntrinsic(I, ISD::MEMSET); 2501 return 0; 2502 case Intrinsic::memmove_i32: 2503 case Intrinsic::memmove_i64: 2504 visitMemIntrinsic(I, ISD::MEMMOVE); 2505 return 0; 2506 2507 case Intrinsic::dbg_stoppoint: { 2508 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2509 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2510 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2511 SDOperand Ops[5]; 2512 2513 Ops[0] = getRoot(); 2514 Ops[1] = getValue(SPI.getLineValue()); 2515 Ops[2] = getValue(SPI.getColumnValue()); 2516 2517 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2518 assert(DD && "Not a debug information descriptor"); 2519 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2520 2521 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2522 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2523 2524 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2525 } 2526 2527 return 0; 2528 } 2529 case Intrinsic::dbg_region_start: { 2530 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2531 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2532 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2533 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2534 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2535 DAG.getConstant(LabelID, MVT::i32))); 2536 } 2537 2538 return 0; 2539 } 2540 case Intrinsic::dbg_region_end: { 2541 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2542 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2543 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2544 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2545 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2546 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2547 } 2548 2549 return 0; 2550 } 2551 case Intrinsic::dbg_func_start: { 2552 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2553 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2554 if (MMI && FSI.getSubprogram() && 2555 MMI->Verify(FSI.getSubprogram())) { 2556 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram()); 2557 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2558 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2559 } 2560 2561 return 0; 2562 } 2563 case Intrinsic::dbg_declare: { 2564 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2565 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2566 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) { 2567 SDOperand AddressOp = getValue(DI.getAddress()); 2568 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 2569 MMI->RecordVariable(DI.getVariable(), FI->getIndex()); 2570 } 2571 2572 return 0; 2573 } 2574 2575 case Intrinsic::eh_exception: { 2576 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2577 2578 if (MMI) { 2579 // Mark exception register as live in. 2580 unsigned Reg = TLI.getExceptionAddressRegister(); 2581 if (Reg) CurMBB->addLiveIn(Reg); 2582 2583 // Insert the EXCEPTIONADDR instruction. 2584 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2585 SDOperand Ops[1]; 2586 Ops[0] = DAG.getRoot(); 2587 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2588 setValue(&I, Op); 2589 DAG.setRoot(Op.getValue(1)); 2590 } else { 2591 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2592 } 2593 return 0; 2594 } 2595 2596 case Intrinsic::eh_selector: 2597 case Intrinsic::eh_filter:{ 2598 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2599 2600 if (MMI) { 2601 // Inform the MachineModuleInfo of the personality for this landing pad. 2602 ConstantExpr *CE = dyn_cast<ConstantExpr>(I.getOperand(2)); 2603 assert(CE && CE->getOpcode() == Instruction::BitCast && 2604 isa<Function>(CE->getOperand(0)) && 2605 "Personality should be a function"); 2606 MMI->addPersonality(CurMBB, cast<Function>(CE->getOperand(0))); 2607 2608 // Gather all the type infos for this landing pad and pass them along to 2609 // MachineModuleInfo. 2610 std::vector<GlobalVariable *> TyInfo; 2611 for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) { 2612 Constant *C = cast<Constant>(I.getOperand(i)); 2613 GlobalVariable *GV = ExtractGlobalVariable(C); 2614 assert (GV || isa<ConstantPointerNull>(C) && 2615 "TypeInfo must be a global variable or NULL"); 2616 TyInfo.push_back(GV); 2617 } 2618 if (Intrinsic == Intrinsic::eh_filter) 2619 MMI->addFilterTypeInfo(CurMBB, TyInfo); 2620 else 2621 MMI->addCatchTypeInfo(CurMBB, TyInfo); 2622 2623 // Mark exception selector register as live in. 2624 unsigned Reg = TLI.getExceptionSelectorRegister(); 2625 if (Reg) CurMBB->addLiveIn(Reg); 2626 2627 // Insert the EHSELECTION instruction. 2628 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2629 SDOperand Ops[2]; 2630 Ops[0] = getValue(I.getOperand(1)); 2631 Ops[1] = getRoot(); 2632 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2633 setValue(&I, Op); 2634 DAG.setRoot(Op.getValue(1)); 2635 } else { 2636 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2637 } 2638 2639 return 0; 2640 } 2641 2642 case Intrinsic::eh_typeid_for: { 2643 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2644 2645 if (MMI) { 2646 // Find the type id for the given typeinfo. 2647 Constant *C = cast<Constant>(I.getOperand(1)); 2648 GlobalVariable *GV = ExtractGlobalVariable(C); 2649 assert (GV || isa<ConstantPointerNull>(C) && 2650 "TypeInfo must be a global variable or NULL"); 2651 2652 unsigned TypeID = MMI->getTypeIDFor(GV); 2653 setValue(&I, DAG.getConstant(TypeID, MVT::i32)); 2654 } else { 2655 setValue(&I, DAG.getConstant(0, MVT::i32)); 2656 } 2657 2658 return 0; 2659 } 2660 2661 case Intrinsic::sqrt_f32: 2662 case Intrinsic::sqrt_f64: 2663 setValue(&I, DAG.getNode(ISD::FSQRT, 2664 getValue(I.getOperand(1)).getValueType(), 2665 getValue(I.getOperand(1)))); 2666 return 0; 2667 case Intrinsic::powi_f32: 2668 case Intrinsic::powi_f64: 2669 setValue(&I, DAG.getNode(ISD::FPOWI, 2670 getValue(I.getOperand(1)).getValueType(), 2671 getValue(I.getOperand(1)), 2672 getValue(I.getOperand(2)))); 2673 return 0; 2674 case Intrinsic::pcmarker: { 2675 SDOperand Tmp = getValue(I.getOperand(1)); 2676 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2677 return 0; 2678 } 2679 case Intrinsic::readcyclecounter: { 2680 SDOperand Op = getRoot(); 2681 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2682 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2683 &Op, 1); 2684 setValue(&I, Tmp); 2685 DAG.setRoot(Tmp.getValue(1)); 2686 return 0; 2687 } 2688 case Intrinsic::part_select: { 2689 // Currently not implemented: just abort 2690 assert(0 && "part_select intrinsic not implemented"); 2691 abort(); 2692 } 2693 case Intrinsic::part_set: { 2694 // Currently not implemented: just abort 2695 assert(0 && "part_set intrinsic not implemented"); 2696 abort(); 2697 } 2698 case Intrinsic::bswap: 2699 setValue(&I, DAG.getNode(ISD::BSWAP, 2700 getValue(I.getOperand(1)).getValueType(), 2701 getValue(I.getOperand(1)))); 2702 return 0; 2703 case Intrinsic::cttz: { 2704 SDOperand Arg = getValue(I.getOperand(1)); 2705 MVT::ValueType Ty = Arg.getValueType(); 2706 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2707 if (Ty < MVT::i32) 2708 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2709 else if (Ty > MVT::i32) 2710 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2711 setValue(&I, result); 2712 return 0; 2713 } 2714 case Intrinsic::ctlz: { 2715 SDOperand Arg = getValue(I.getOperand(1)); 2716 MVT::ValueType Ty = Arg.getValueType(); 2717 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2718 if (Ty < MVT::i32) 2719 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2720 else if (Ty > MVT::i32) 2721 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2722 setValue(&I, result); 2723 return 0; 2724 } 2725 case Intrinsic::ctpop: { 2726 SDOperand Arg = getValue(I.getOperand(1)); 2727 MVT::ValueType Ty = Arg.getValueType(); 2728 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2729 if (Ty < MVT::i32) 2730 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2731 else if (Ty > MVT::i32) 2732 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2733 setValue(&I, result); 2734 return 0; 2735 } 2736 case Intrinsic::stacksave: { 2737 SDOperand Op = getRoot(); 2738 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2739 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2740 setValue(&I, Tmp); 2741 DAG.setRoot(Tmp.getValue(1)); 2742 return 0; 2743 } 2744 case Intrinsic::stackrestore: { 2745 SDOperand Tmp = getValue(I.getOperand(1)); 2746 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2747 return 0; 2748 } 2749 case Intrinsic::prefetch: 2750 // FIXME: Currently discarding prefetches. 2751 return 0; 2752 } 2753} 2754 2755 2756void SelectionDAGLowering::LowerCallTo(Instruction &I, 2757 const Type *CalledValueTy, 2758 unsigned CallingConv, 2759 bool IsTailCall, 2760 SDOperand Callee, unsigned OpIdx, 2761 MachineBasicBlock *LandingPad) { 2762 const PointerType *PT = cast<PointerType>(CalledValueTy); 2763 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 2764 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 2765 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2766 unsigned BeginLabel = 0, EndLabel = 0; 2767 2768 TargetLowering::ArgListTy Args; 2769 TargetLowering::ArgListEntry Entry; 2770 Args.reserve(I.getNumOperands()); 2771 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) { 2772 Value *Arg = I.getOperand(i); 2773 SDOperand ArgNode = getValue(Arg); 2774 Entry.Node = ArgNode; Entry.Ty = Arg->getType(); 2775 2776 unsigned attrInd = i - OpIdx + 1; 2777 Entry.isSExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::SExt); 2778 Entry.isZExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ZExt); 2779 Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg); 2780 Entry.isSRet = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet); 2781 Args.push_back(Entry); 2782 } 2783 2784 if (ExceptionHandling && MMI) { 2785 // Insert a label before the invoke call to mark the try range. This can be 2786 // used to detect deletion of the invoke via the MachineModuleInfo. 2787 BeginLabel = MMI->NextLabelID(); 2788 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2789 DAG.getConstant(BeginLabel, MVT::i32))); 2790 } 2791 2792 std::pair<SDOperand,SDOperand> Result = 2793 TLI.LowerCallTo(getRoot(), I.getType(), 2794 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt), 2795 FTy->isVarArg(), CallingConv, IsTailCall, 2796 Callee, Args, DAG); 2797 if (I.getType() != Type::VoidTy) 2798 setValue(&I, Result.first); 2799 DAG.setRoot(Result.second); 2800 2801 if (ExceptionHandling && MMI) { 2802 // Insert a label at the end of the invoke call to mark the try range. This 2803 // can be used to detect deletion of the invoke via the MachineModuleInfo. 2804 EndLabel = MMI->NextLabelID(); 2805 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2806 DAG.getConstant(EndLabel, MVT::i32))); 2807 2808 // Inform MachineModuleInfo of range. 2809 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 2810 } 2811} 2812 2813 2814void SelectionDAGLowering::visitCall(CallInst &I) { 2815 const char *RenameFn = 0; 2816 if (Function *F = I.getCalledFunction()) { 2817 if (F->isDeclaration()) 2818 if (unsigned IID = F->getIntrinsicID()) { 2819 RenameFn = visitIntrinsicCall(I, IID); 2820 if (!RenameFn) 2821 return; 2822 } else { // Not an LLVM intrinsic. 2823 const std::string &Name = F->getName(); 2824 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) { 2825 if (I.getNumOperands() == 3 && // Basic sanity checks. 2826 I.getOperand(1)->getType()->isFloatingPoint() && 2827 I.getType() == I.getOperand(1)->getType() && 2828 I.getType() == I.getOperand(2)->getType()) { 2829 SDOperand LHS = getValue(I.getOperand(1)); 2830 SDOperand RHS = getValue(I.getOperand(2)); 2831 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 2832 LHS, RHS)); 2833 return; 2834 } 2835 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) { 2836 if (I.getNumOperands() == 2 && // Basic sanity checks. 2837 I.getOperand(1)->getType()->isFloatingPoint() && 2838 I.getType() == I.getOperand(1)->getType()) { 2839 SDOperand Tmp = getValue(I.getOperand(1)); 2840 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 2841 return; 2842 } 2843 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) { 2844 if (I.getNumOperands() == 2 && // Basic sanity checks. 2845 I.getOperand(1)->getType()->isFloatingPoint() && 2846 I.getType() == I.getOperand(1)->getType()) { 2847 SDOperand Tmp = getValue(I.getOperand(1)); 2848 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 2849 return; 2850 } 2851 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) { 2852 if (I.getNumOperands() == 2 && // Basic sanity checks. 2853 I.getOperand(1)->getType()->isFloatingPoint() && 2854 I.getType() == I.getOperand(1)->getType()) { 2855 SDOperand Tmp = getValue(I.getOperand(1)); 2856 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 2857 return; 2858 } 2859 } 2860 } 2861 } else if (isa<InlineAsm>(I.getOperand(0))) { 2862 visitInlineAsm(I); 2863 return; 2864 } 2865 2866 SDOperand Callee; 2867 if (!RenameFn) 2868 Callee = getValue(I.getOperand(0)); 2869 else 2870 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 2871 2872 LowerCallTo(I, I.getCalledValue()->getType(), 2873 I.getCallingConv(), 2874 I.isTailCall(), 2875 Callee, 2876 1); 2877} 2878 2879 2880SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 2881 SDOperand &Chain, SDOperand &Flag)const{ 2882 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag); 2883 Chain = Val.getValue(1); 2884 Flag = Val.getValue(2); 2885 2886 // If the result was expanded, copy from the top part. 2887 if (Regs.size() > 1) { 2888 assert(Regs.size() == 2 && 2889 "Cannot expand to more than 2 elts yet!"); 2890 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag); 2891 Chain = Hi.getValue(1); 2892 Flag = Hi.getValue(2); 2893 if (DAG.getTargetLoweringInfo().isLittleEndian()) 2894 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 2895 else 2896 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val); 2897 } 2898 2899 // Otherwise, if the return value was promoted or extended, truncate it to the 2900 // appropriate type. 2901 if (RegVT == ValueVT) 2902 return Val; 2903 2904 if (MVT::isVector(RegVT)) { 2905 assert(ValueVT == MVT::Vector && "Unknown vector conversion!"); 2906 return DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val, 2907 DAG.getConstant(MVT::getVectorNumElements(RegVT), 2908 MVT::i32), 2909 DAG.getValueType(MVT::getVectorBaseType(RegVT))); 2910 } 2911 2912 if (MVT::isInteger(RegVT)) { 2913 if (ValueVT < RegVT) 2914 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 2915 else 2916 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 2917 } 2918 2919 assert(MVT::isFloatingPoint(RegVT) && MVT::isFloatingPoint(ValueVT)); 2920 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 2921} 2922 2923/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 2924/// specified value into the registers specified by this object. This uses 2925/// Chain/Flag as the input and updates them for the output Chain/Flag. 2926void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 2927 SDOperand &Chain, SDOperand &Flag, 2928 MVT::ValueType PtrVT) const { 2929 if (Regs.size() == 1) { 2930 // If there is a single register and the types differ, this must be 2931 // a promotion. 2932 if (RegVT != ValueVT) { 2933 if (MVT::isVector(RegVT)) { 2934 assert(Val.getValueType() == MVT::Vector &&"Not a vector-vector cast?"); 2935 Val = DAG.getNode(ISD::VBIT_CONVERT, RegVT, Val); 2936 } else if (MVT::isInteger(RegVT) && MVT::isInteger(Val.getValueType())) { 2937 if (RegVT < ValueVT) 2938 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val); 2939 else 2940 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val); 2941 } else if (MVT::isFloatingPoint(RegVT) && 2942 MVT::isFloatingPoint(Val.getValueType())) { 2943 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val); 2944 } else if (MVT::getSizeInBits(RegVT) == 2945 MVT::getSizeInBits(Val.getValueType())) { 2946 Val = DAG.getNode(ISD::BIT_CONVERT, RegVT, Val); 2947 } else { 2948 assert(0 && "Unknown mismatch!"); 2949 } 2950 } 2951 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag); 2952 Flag = Chain.getValue(1); 2953 } else { 2954 std::vector<unsigned> R(Regs); 2955 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 2956 std::reverse(R.begin(), R.end()); 2957 2958 for (unsigned i = 0, e = R.size(); i != e; ++i) { 2959 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val, 2960 DAG.getConstant(i, PtrVT)); 2961 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag); 2962 Flag = Chain.getValue(1); 2963 } 2964 } 2965} 2966 2967/// AddInlineAsmOperands - Add this value to the specified inlineasm node 2968/// operand list. This adds the code marker and includes the number of 2969/// values added into it. 2970void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 2971 std::vector<SDOperand> &Ops) const { 2972 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 2973 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 2974 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 2975 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 2976} 2977 2978/// isAllocatableRegister - If the specified register is safe to allocate, 2979/// i.e. it isn't a stack pointer or some other special register, return the 2980/// register class for the register. Otherwise, return null. 2981static const TargetRegisterClass * 2982isAllocatableRegister(unsigned Reg, MachineFunction &MF, 2983 const TargetLowering &TLI, const MRegisterInfo *MRI) { 2984 MVT::ValueType FoundVT = MVT::Other; 2985 const TargetRegisterClass *FoundRC = 0; 2986 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 2987 E = MRI->regclass_end(); RCI != E; ++RCI) { 2988 MVT::ValueType ThisVT = MVT::Other; 2989 2990 const TargetRegisterClass *RC = *RCI; 2991 // If none of the the value types for this register class are valid, we 2992 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2993 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2994 I != E; ++I) { 2995 if (TLI.isTypeLegal(*I)) { 2996 // If we have already found this register in a different register class, 2997 // choose the one with the largest VT specified. For example, on 2998 // PowerPC, we favor f64 register classes over f32. 2999 if (FoundVT == MVT::Other || 3000 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 3001 ThisVT = *I; 3002 break; 3003 } 3004 } 3005 } 3006 3007 if (ThisVT == MVT::Other) continue; 3008 3009 // NOTE: This isn't ideal. In particular, this might allocate the 3010 // frame pointer in functions that need it (due to them not being taken 3011 // out of allocation, because a variable sized allocation hasn't been seen 3012 // yet). This is a slight code pessimization, but should still work. 3013 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3014 E = RC->allocation_order_end(MF); I != E; ++I) 3015 if (*I == Reg) { 3016 // We found a matching register class. Keep looking at others in case 3017 // we find one with larger registers that this physreg is also in. 3018 FoundRC = RC; 3019 FoundVT = ThisVT; 3020 break; 3021 } 3022 } 3023 return FoundRC; 3024} 3025 3026 3027namespace { 3028/// AsmOperandInfo - This contains information for each constraint that we are 3029/// lowering. 3030struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 3031 /// ConstraintCode - This contains the actual string for the code, like "m". 3032 std::string ConstraintCode; 3033 3034 /// ConstraintType - Information about the constraint code, e.g. Register, 3035 /// RegisterClass, Memory, Other, Unknown. 3036 TargetLowering::ConstraintType ConstraintType; 3037 3038 /// CallOperand/CallOperandval - If this is the result output operand or a 3039 /// clobber, this is null, otherwise it is the incoming operand to the 3040 /// CallInst. This gets modified as the asm is processed. 3041 SDOperand CallOperand; 3042 Value *CallOperandVal; 3043 3044 /// ConstraintVT - The ValueType for the operand value. 3045 MVT::ValueType ConstraintVT; 3046 3047 /// AssignedRegs - If this is a register or register class operand, this 3048 /// contains the set of register corresponding to the operand. 3049 RegsForValue AssignedRegs; 3050 3051 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3052 : InlineAsm::ConstraintInfo(info), 3053 ConstraintType(TargetLowering::C_Unknown), 3054 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) { 3055 } 3056 3057 void ComputeConstraintToUse(const TargetLowering &TLI); 3058 3059 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3060 /// busy in OutputRegs/InputRegs. 3061 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3062 std::set<unsigned> &OutputRegs, 3063 std::set<unsigned> &InputRegs) const { 3064 if (isOutReg) 3065 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3066 if (isInReg) 3067 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3068 } 3069}; 3070} // end anon namespace. 3071 3072/// getConstraintGenerality - Return an integer indicating how general CT is. 3073static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3074 switch (CT) { 3075 default: assert(0 && "Unknown constraint type!"); 3076 case TargetLowering::C_Other: 3077 case TargetLowering::C_Unknown: 3078 return 0; 3079 case TargetLowering::C_Register: 3080 return 1; 3081 case TargetLowering::C_RegisterClass: 3082 return 2; 3083 case TargetLowering::C_Memory: 3084 return 3; 3085 } 3086} 3087 3088void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) { 3089 assert(!Codes.empty() && "Must have at least one constraint"); 3090 3091 std::string *Current = &Codes[0]; 3092 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current); 3093 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common. 3094 ConstraintCode = *Current; 3095 ConstraintType = CurType; 3096 return; 3097 } 3098 3099 unsigned CurGenerality = getConstraintGenerality(CurType); 3100 3101 // If we have multiple constraints, try to pick the most general one ahead 3102 // of time. This isn't a wonderful solution, but handles common cases. 3103 for (unsigned j = 1, e = Codes.size(); j != e; ++j) { 3104 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]); 3105 unsigned ThisGenerality = getConstraintGenerality(ThisType); 3106 if (ThisGenerality > CurGenerality) { 3107 // This constraint letter is more general than the previous one, 3108 // use it. 3109 CurType = ThisType; 3110 Current = &Codes[j]; 3111 CurGenerality = ThisGenerality; 3112 } 3113 } 3114 3115 ConstraintCode = *Current; 3116 ConstraintType = CurType; 3117} 3118 3119 3120void SelectionDAGLowering:: 3121GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 3122 std::set<unsigned> &OutputRegs, 3123 std::set<unsigned> &InputRegs) { 3124 // Compute whether this value requires an input register, an output register, 3125 // or both. 3126 bool isOutReg = false; 3127 bool isInReg = false; 3128 switch (OpInfo.Type) { 3129 case InlineAsm::isOutput: 3130 isOutReg = true; 3131 3132 // If this is an early-clobber output, or if there is an input 3133 // constraint that matches this, we need to reserve the input register 3134 // so no other inputs allocate to it. 3135 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3136 break; 3137 case InlineAsm::isInput: 3138 isInReg = true; 3139 isOutReg = false; 3140 break; 3141 case InlineAsm::isClobber: 3142 isOutReg = true; 3143 isInReg = true; 3144 break; 3145 } 3146 3147 3148 MachineFunction &MF = DAG.getMachineFunction(); 3149 std::vector<unsigned> Regs; 3150 3151 // If this is a constraint for a single physreg, or a constraint for a 3152 // register class, find it. 3153 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3154 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3155 OpInfo.ConstraintVT); 3156 3157 unsigned NumRegs = 1; 3158 if (OpInfo.ConstraintVT != MVT::Other) 3159 NumRegs = TLI.getNumElements(OpInfo.ConstraintVT); 3160 MVT::ValueType RegVT; 3161 MVT::ValueType ValueVT = OpInfo.ConstraintVT; 3162 3163 3164 // If this is a constraint for a specific physical register, like {r17}, 3165 // assign it now. 3166 if (PhysReg.first) { 3167 if (OpInfo.ConstraintVT == MVT::Other) 3168 ValueVT = *PhysReg.second->vt_begin(); 3169 3170 // Get the actual register value type. This is important, because the user 3171 // may have asked for (e.g.) the AX register in i32 type. We need to 3172 // remember that AX is actually i16 to get the right extension. 3173 RegVT = *PhysReg.second->vt_begin(); 3174 3175 // This is a explicit reference to a physical register. 3176 Regs.push_back(PhysReg.first); 3177 3178 // If this is an expanded reference, add the rest of the regs to Regs. 3179 if (NumRegs != 1) { 3180 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3181 TargetRegisterClass::iterator E = PhysReg.second->end(); 3182 for (; *I != PhysReg.first; ++I) 3183 assert(I != E && "Didn't find reg!"); 3184 3185 // Already added the first reg. 3186 --NumRegs; ++I; 3187 for (; NumRegs; --NumRegs, ++I) { 3188 assert(I != E && "Ran out of registers to allocate!"); 3189 Regs.push_back(*I); 3190 } 3191 } 3192 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3193 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3194 return; 3195 } 3196 3197 // Otherwise, if this was a reference to an LLVM register class, create vregs 3198 // for this reference. 3199 std::vector<unsigned> RegClassRegs; 3200 if (PhysReg.second) { 3201 // If this is an early clobber or tied register, our regalloc doesn't know 3202 // how to maintain the constraint. If it isn't, go ahead and create vreg 3203 // and let the regalloc do the right thing. 3204 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 3205 // If there is some other early clobber and this is an input register, 3206 // then we are forced to pre-allocate the input reg so it doesn't 3207 // conflict with the earlyclobber. 3208 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 3209 RegVT = *PhysReg.second->vt_begin(); 3210 3211 if (OpInfo.ConstraintVT == MVT::Other) 3212 ValueVT = RegVT; 3213 3214 // Create the appropriate number of virtual registers. 3215 SSARegMap *RegMap = MF.getSSARegMap(); 3216 for (; NumRegs; --NumRegs) 3217 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second)); 3218 3219 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3220 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3221 return; 3222 } 3223 3224 // Otherwise, we can't allocate it. Let the code below figure out how to 3225 // maintain these constraints. 3226 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3227 3228 } else { 3229 // This is a reference to a register class that doesn't directly correspond 3230 // to an LLVM register class. Allocate NumRegs consecutive, available, 3231 // registers from the class. 3232 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3233 OpInfo.ConstraintVT); 3234 } 3235 3236 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 3237 unsigned NumAllocated = 0; 3238 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3239 unsigned Reg = RegClassRegs[i]; 3240 // See if this register is available. 3241 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3242 (isInReg && InputRegs.count(Reg))) { // Already used. 3243 // Make sure we find consecutive registers. 3244 NumAllocated = 0; 3245 continue; 3246 } 3247 3248 // Check to see if this register is allocatable (i.e. don't give out the 3249 // stack pointer). 3250 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI); 3251 if (!RC) { 3252 // Make sure we find consecutive registers. 3253 NumAllocated = 0; 3254 continue; 3255 } 3256 3257 // Okay, this register is good, we can use it. 3258 ++NumAllocated; 3259 3260 // If we allocated enough consecutive registers, succeed. 3261 if (NumAllocated == NumRegs) { 3262 unsigned RegStart = (i-NumAllocated)+1; 3263 unsigned RegEnd = i+1; 3264 // Mark all of the allocated registers used. 3265 for (unsigned i = RegStart; i != RegEnd; ++i) 3266 Regs.push_back(RegClassRegs[i]); 3267 3268 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 3269 OpInfo.ConstraintVT); 3270 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3271 return; 3272 } 3273 } 3274 3275 // Otherwise, we couldn't allocate enough registers for this. 3276 return; 3277} 3278 3279 3280/// visitInlineAsm - Handle a call to an InlineAsm object. 3281/// 3282void SelectionDAGLowering::visitInlineAsm(CallInst &I) { 3283 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0)); 3284 3285 /// ConstraintOperands - Information about all of the constraints. 3286 std::vector<AsmOperandInfo> ConstraintOperands; 3287 3288 SDOperand Chain = getRoot(); 3289 SDOperand Flag; 3290 3291 std::set<unsigned> OutputRegs, InputRegs; 3292 3293 // Do a prepass over the constraints, canonicalizing them, and building up the 3294 // ConstraintOperands list. 3295 std::vector<InlineAsm::ConstraintInfo> 3296 ConstraintInfos = IA->ParseConstraints(); 3297 3298 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 3299 // constraint. If so, we can't let the register allocator allocate any input 3300 // registers, because it will not know to avoid the earlyclobbered output reg. 3301 bool SawEarlyClobber = false; 3302 3303 unsigned OpNo = 1; // OpNo - The operand of the CallInst. 3304 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3305 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 3306 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 3307 3308 MVT::ValueType OpVT = MVT::Other; 3309 3310 // Compute the value type for each operand. 3311 switch (OpInfo.Type) { 3312 case InlineAsm::isOutput: 3313 if (!OpInfo.isIndirect) { 3314 // The return value of the call is this value. As such, there is no 3315 // corresponding argument. 3316 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3317 OpVT = TLI.getValueType(I.getType()); 3318 } else { 3319 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3320 } 3321 break; 3322 case InlineAsm::isInput: 3323 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3324 break; 3325 case InlineAsm::isClobber: 3326 // Nothing to do. 3327 break; 3328 } 3329 3330 // If this is an input or an indirect output, process the call argument. 3331 if (OpInfo.CallOperandVal) { 3332 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 3333 const Type *OpTy = OpInfo.CallOperandVal->getType(); 3334 // If this is an indirect operand, the operand is a pointer to the 3335 // accessed type. 3336 if (OpInfo.isIndirect) 3337 OpTy = cast<PointerType>(OpTy)->getElementType(); 3338 3339 // If OpTy is not a first-class value, it may be a struct/union that we 3340 // can tile with integers. 3341 if (!OpTy->isFirstClassType() && OpTy->isSized()) { 3342 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3343 switch (BitSize) { 3344 default: break; 3345 case 1: 3346 case 8: 3347 case 16: 3348 case 32: 3349 case 64: 3350 OpTy = IntegerType::get(BitSize); 3351 break; 3352 } 3353 } 3354 3355 OpVT = TLI.getValueType(OpTy, true); 3356 } 3357 3358 OpInfo.ConstraintVT = OpVT; 3359 3360 // Compute the constraint code and ConstraintType to use. 3361 OpInfo.ComputeConstraintToUse(TLI); 3362 3363 // Keep track of whether we see an earlyclobber. 3364 SawEarlyClobber |= OpInfo.isEarlyClobber; 3365 3366 // If this is a memory input, and if the operand is not indirect, do what we 3367 // need to to provide an address for the memory input. 3368 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 3369 !OpInfo.isIndirect) { 3370 assert(OpInfo.Type == InlineAsm::isInput && 3371 "Can only indirectify direct input operands!"); 3372 3373 // Memory operands really want the address of the value. If we don't have 3374 // an indirect input, put it in the constpool if we can, otherwise spill 3375 // it to a stack slot. 3376 3377 // If the operand is a float, integer, or vector constant, spill to a 3378 // constant pool entry to get its address. 3379 Value *OpVal = OpInfo.CallOperandVal; 3380 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 3381 isa<ConstantVector>(OpVal)) { 3382 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 3383 TLI.getPointerTy()); 3384 } else { 3385 // Otherwise, create a stack slot and emit a store to it before the 3386 // asm. 3387 const Type *Ty = OpVal->getType(); 3388 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3389 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3390 MachineFunction &MF = DAG.getMachineFunction(); 3391 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3392 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3393 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 3394 OpInfo.CallOperand = StackSlot; 3395 } 3396 3397 // There is no longer a Value* corresponding to this operand. 3398 OpInfo.CallOperandVal = 0; 3399 // It is now an indirect operand. 3400 OpInfo.isIndirect = true; 3401 } 3402 3403 // If this constraint is for a specific register, allocate it before 3404 // anything else. 3405 if (OpInfo.ConstraintType == TargetLowering::C_Register) 3406 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3407 } 3408 ConstraintInfos.clear(); 3409 3410 3411 // Second pass - Loop over all of the operands, assigning virtual or physregs 3412 // to registerclass operands. 3413 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3414 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3415 3416 // C_Register operands have already been allocated, Other/Memory don't need 3417 // to be. 3418 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 3419 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3420 } 3421 3422 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 3423 std::vector<SDOperand> AsmNodeOperands; 3424 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3425 AsmNodeOperands.push_back( 3426 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 3427 3428 3429 // Loop over all of the inputs, copying the operand values into the 3430 // appropriate registers and processing the output regs. 3431 RegsForValue RetValRegs; 3432 3433 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 3434 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3435 3436 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3437 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3438 3439 switch (OpInfo.Type) { 3440 case InlineAsm::isOutput: { 3441 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 3442 OpInfo.ConstraintType != TargetLowering::C_Register) { 3443 // Memory output, or 'other' output (e.g. 'X' constraint). 3444 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 3445 3446 // Add information to the INLINEASM node to know about this output. 3447 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3448 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3449 TLI.getPointerTy())); 3450 AsmNodeOperands.push_back(OpInfo.CallOperand); 3451 break; 3452 } 3453 3454 // Otherwise, this is a register or register class output. 3455 3456 // Copy the output from the appropriate register. Find a register that 3457 // we can use. 3458 if (OpInfo.AssignedRegs.Regs.empty()) { 3459 cerr << "Couldn't allocate output reg for contraint '" 3460 << OpInfo.ConstraintCode << "'!\n"; 3461 exit(1); 3462 } 3463 3464 if (!OpInfo.isIndirect) { 3465 // This is the result value of the call. 3466 assert(RetValRegs.Regs.empty() && 3467 "Cannot have multiple output constraints yet!"); 3468 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3469 RetValRegs = OpInfo.AssignedRegs; 3470 } else { 3471 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 3472 OpInfo.CallOperandVal)); 3473 } 3474 3475 // Add information to the INLINEASM node to know that this register is 3476 // set. 3477 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 3478 AsmNodeOperands); 3479 break; 3480 } 3481 case InlineAsm::isInput: { 3482 SDOperand InOperandVal = OpInfo.CallOperand; 3483 3484 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 3485 // If this is required to match an output register we have already set, 3486 // just use its register. 3487 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 3488 3489 // Scan until we find the definition we already emitted of this operand. 3490 // When we find it, create a RegsForValue operand. 3491 unsigned CurOp = 2; // The first operand. 3492 for (; OperandNo; --OperandNo) { 3493 // Advance to the next operand. 3494 unsigned NumOps = 3495 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3496 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3497 (NumOps & 7) == 4 /*MEM*/) && 3498 "Skipped past definitions?"); 3499 CurOp += (NumOps>>3)+1; 3500 } 3501 3502 unsigned NumOps = 3503 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3504 if ((NumOps & 7) == 2 /*REGDEF*/) { 3505 // Add NumOps>>3 registers to MatchedRegs. 3506 RegsForValue MatchedRegs; 3507 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3508 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3509 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3510 unsigned Reg = 3511 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3512 MatchedRegs.Regs.push_back(Reg); 3513 } 3514 3515 // Use the produced MatchedRegs object to 3516 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, 3517 TLI.getPointerTy()); 3518 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3519 break; 3520 } else { 3521 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3522 assert(0 && "matching constraints for memory operands unimp"); 3523 } 3524 } 3525 3526 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 3527 assert(!OpInfo.isIndirect && 3528 "Don't know how to handle indirect other inputs yet!"); 3529 3530 InOperandVal = TLI.isOperandValidForConstraint(InOperandVal, 3531 OpInfo.ConstraintCode[0], 3532 DAG); 3533 if (!InOperandVal.Val) { 3534 cerr << "Invalid operand for inline asm constraint '" 3535 << OpInfo.ConstraintCode << "'!\n"; 3536 exit(1); 3537 } 3538 3539 // Add information to the INLINEASM node to know about this input. 3540 unsigned ResOpType = 3 /*IMM*/ | (1 << 3); 3541 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3542 TLI.getPointerTy())); 3543 AsmNodeOperands.push_back(InOperandVal); 3544 break; 3545 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 3546 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 3547 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 3548 "Memory operands expect pointer values"); 3549 3550 // Add information to the INLINEASM node to know about this input. 3551 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3552 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3553 TLI.getPointerTy())); 3554 AsmNodeOperands.push_back(InOperandVal); 3555 break; 3556 } 3557 3558 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 3559 OpInfo.ConstraintType == TargetLowering::C_Register) && 3560 "Unknown constraint type!"); 3561 assert(!OpInfo.isIndirect && 3562 "Don't know how to handle indirect register inputs yet!"); 3563 3564 // Copy the input into the appropriate registers. 3565 assert(!OpInfo.AssignedRegs.Regs.empty() && 3566 "Couldn't allocate input reg!"); 3567 3568 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, 3569 TLI.getPointerTy()); 3570 3571 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 3572 AsmNodeOperands); 3573 break; 3574 } 3575 case InlineAsm::isClobber: { 3576 // Add the clobbered value to the operand list, so that the register 3577 // allocator is aware that the physreg got clobbered. 3578 if (!OpInfo.AssignedRegs.Regs.empty()) 3579 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 3580 AsmNodeOperands); 3581 break; 3582 } 3583 } 3584 } 3585 3586 // Finish up input operands. 3587 AsmNodeOperands[0] = Chain; 3588 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3589 3590 Chain = DAG.getNode(ISD::INLINEASM, 3591 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3592 &AsmNodeOperands[0], AsmNodeOperands.size()); 3593 Flag = Chain.getValue(1); 3594 3595 // If this asm returns a register value, copy the result from that register 3596 // and set it as the value of the call. 3597 if (!RetValRegs.Regs.empty()) { 3598 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, Flag); 3599 3600 // If the result of the inline asm is a vector, it may have the wrong 3601 // width/num elts. Make sure to convert it to the right type with 3602 // vbit_convert. 3603 if (Val.getValueType() == MVT::Vector) { 3604 const VectorType *VTy = cast<VectorType>(I.getType()); 3605 unsigned DesiredNumElts = VTy->getNumElements(); 3606 MVT::ValueType DesiredEltVT = TLI.getValueType(VTy->getElementType()); 3607 3608 Val = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val, 3609 DAG.getConstant(DesiredNumElts, MVT::i32), 3610 DAG.getValueType(DesiredEltVT)); 3611 } 3612 3613 setValue(&I, Val); 3614 } 3615 3616 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 3617 3618 // Process indirect outputs, first output all of the flagged copies out of 3619 // physregs. 3620 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 3621 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 3622 Value *Ptr = IndirectStoresToEmit[i].second; 3623 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag); 3624 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 3625 } 3626 3627 // Emit the non-flagged stores from the physregs. 3628 SmallVector<SDOperand, 8> OutChains; 3629 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 3630 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 3631 getValue(StoresToEmit[i].second), 3632 StoresToEmit[i].second, 0)); 3633 if (!OutChains.empty()) 3634 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3635 &OutChains[0], OutChains.size()); 3636 DAG.setRoot(Chain); 3637} 3638 3639 3640void SelectionDAGLowering::visitMalloc(MallocInst &I) { 3641 SDOperand Src = getValue(I.getOperand(0)); 3642 3643 MVT::ValueType IntPtr = TLI.getPointerTy(); 3644 3645 if (IntPtr < Src.getValueType()) 3646 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 3647 else if (IntPtr > Src.getValueType()) 3648 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 3649 3650 // Scale the source by the type size. 3651 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType()); 3652 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 3653 Src, getIntPtrConstant(ElementSize)); 3654 3655 TargetLowering::ArgListTy Args; 3656 TargetLowering::ArgListEntry Entry; 3657 Entry.Node = Src; 3658 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3659 Args.push_back(Entry); 3660 3661 std::pair<SDOperand,SDOperand> Result = 3662 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true, 3663 DAG.getExternalSymbol("malloc", IntPtr), 3664 Args, DAG); 3665 setValue(&I, Result.first); // Pointers always fit in registers 3666 DAG.setRoot(Result.second); 3667} 3668 3669void SelectionDAGLowering::visitFree(FreeInst &I) { 3670 TargetLowering::ArgListTy Args; 3671 TargetLowering::ArgListEntry Entry; 3672 Entry.Node = getValue(I.getOperand(0)); 3673 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3674 Args.push_back(Entry); 3675 MVT::ValueType IntPtr = TLI.getPointerTy(); 3676 std::pair<SDOperand,SDOperand> Result = 3677 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true, 3678 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 3679 DAG.setRoot(Result.second); 3680} 3681 3682// InsertAtEndOfBasicBlock - This method should be implemented by targets that 3683// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 3684// instructions are special in various ways, which require special support to 3685// insert. The specified MachineInstr is created but not inserted into any 3686// basic blocks, and the scheduler passes ownership of it to this method. 3687MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3688 MachineBasicBlock *MBB) { 3689 cerr << "If a target marks an instruction with " 3690 << "'usesCustomDAGSchedInserter', it must implement " 3691 << "TargetLowering::InsertAtEndOfBasicBlock!\n"; 3692 abort(); 3693 return 0; 3694} 3695 3696void SelectionDAGLowering::visitVAStart(CallInst &I) { 3697 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 3698 getValue(I.getOperand(1)), 3699 DAG.getSrcValue(I.getOperand(1)))); 3700} 3701 3702void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 3703 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 3704 getValue(I.getOperand(0)), 3705 DAG.getSrcValue(I.getOperand(0))); 3706 setValue(&I, V); 3707 DAG.setRoot(V.getValue(1)); 3708} 3709 3710void SelectionDAGLowering::visitVAEnd(CallInst &I) { 3711 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 3712 getValue(I.getOperand(1)), 3713 DAG.getSrcValue(I.getOperand(1)))); 3714} 3715 3716void SelectionDAGLowering::visitVACopy(CallInst &I) { 3717 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 3718 getValue(I.getOperand(1)), 3719 getValue(I.getOperand(2)), 3720 DAG.getSrcValue(I.getOperand(1)), 3721 DAG.getSrcValue(I.getOperand(2)))); 3722} 3723 3724/// ExpandScalarFormalArgs - Recursively expand the formal_argument node, either 3725/// bit_convert it or join a pair of them with a BUILD_PAIR when appropriate. 3726static SDOperand ExpandScalarFormalArgs(MVT::ValueType VT, SDNode *Arg, 3727 unsigned &i, SelectionDAG &DAG, 3728 TargetLowering &TLI) { 3729 if (TLI.getTypeAction(VT) != TargetLowering::Expand) 3730 return SDOperand(Arg, i++); 3731 3732 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT); 3733 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT); 3734 if (NumVals == 1) { 3735 return DAG.getNode(ISD::BIT_CONVERT, VT, 3736 ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI)); 3737 } else if (NumVals == 2) { 3738 SDOperand Lo = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI); 3739 SDOperand Hi = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI); 3740 if (!TLI.isLittleEndian()) 3741 std::swap(Lo, Hi); 3742 return DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 3743 } else { 3744 // Value scalarized into many values. Unimp for now. 3745 assert(0 && "Cannot expand i64 -> i16 yet!"); 3746 } 3747 return SDOperand(); 3748} 3749 3750/// TargetLowering::LowerArguments - This is the default LowerArguments 3751/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 3752/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 3753/// integrated into SDISel. 3754std::vector<SDOperand> 3755TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 3756 const FunctionType *FTy = F.getFunctionType(); 3757 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 3758 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 3759 std::vector<SDOperand> Ops; 3760 Ops.push_back(DAG.getRoot()); 3761 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 3762 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 3763 3764 // Add one result value for each formal argument. 3765 std::vector<MVT::ValueType> RetVals; 3766 unsigned j = 1; 3767 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 3768 I != E; ++I, ++j) { 3769 MVT::ValueType VT = getValueType(I->getType()); 3770 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3771 unsigned OriginalAlignment = 3772 getTargetData()->getABITypeAlignment(I->getType()); 3773 3774 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 3775 // that is zero extended! 3776 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt)) 3777 Flags &= ~(ISD::ParamFlags::SExt); 3778 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt)) 3779 Flags |= ISD::ParamFlags::SExt; 3780 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg)) 3781 Flags |= ISD::ParamFlags::InReg; 3782 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet)) 3783 Flags |= ISD::ParamFlags::StructReturn; 3784 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs); 3785 3786 switch (getTypeAction(VT)) { 3787 default: assert(0 && "Unknown type action!"); 3788 case Legal: 3789 RetVals.push_back(VT); 3790 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3791 break; 3792 case Promote: 3793 RetVals.push_back(getTypeToTransformTo(VT)); 3794 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3795 break; 3796 case Expand: 3797 if (VT != MVT::Vector) { 3798 // If this is a large integer, it needs to be broken up into small 3799 // integers. Figure out what the destination type is and how many small 3800 // integers it turns into. 3801 MVT::ValueType NVT = getTypeToExpandTo(VT); 3802 unsigned NumVals = getNumElements(VT); 3803 for (unsigned i = 0; i != NumVals; ++i) { 3804 RetVals.push_back(NVT); 3805 // if it isn't first piece, alignment must be 1 3806 if (i > 0) 3807 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3808 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3809 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3810 } 3811 } else { 3812 // Otherwise, this is a vector type. We only support legal vectors 3813 // right now. 3814 unsigned NumElems = cast<VectorType>(I->getType())->getNumElements(); 3815 const Type *EltTy = cast<VectorType>(I->getType())->getElementType(); 3816 3817 // Figure out if there is a Packed type corresponding to this Vector 3818 // type. If so, convert to the vector type. 3819 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 3820 if (TVT != MVT::Other && isTypeLegal(TVT)) { 3821 RetVals.push_back(TVT); 3822 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3823 } else { 3824 assert(0 && "Don't support illegal by-val vector arguments yet!"); 3825 } 3826 } 3827 break; 3828 } 3829 } 3830 3831 RetVals.push_back(MVT::Other); 3832 3833 // Create the node. 3834 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 3835 DAG.getNodeValueTypes(RetVals), RetVals.size(), 3836 &Ops[0], Ops.size()).Val; 3837 3838 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1)); 3839 3840 // Set up the return result vector. 3841 Ops.clear(); 3842 unsigned i = 0; 3843 unsigned Idx = 1; 3844 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 3845 ++I, ++Idx) { 3846 MVT::ValueType VT = getValueType(I->getType()); 3847 3848 switch (getTypeAction(VT)) { 3849 default: assert(0 && "Unknown type action!"); 3850 case Legal: 3851 Ops.push_back(SDOperand(Result, i++)); 3852 break; 3853 case Promote: { 3854 SDOperand Op(Result, i++); 3855 if (MVT::isInteger(VT)) { 3856 if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt)) 3857 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, 3858 DAG.getValueType(VT)); 3859 else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt)) 3860 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, 3861 DAG.getValueType(VT)); 3862 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3863 } else { 3864 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3865 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 3866 } 3867 Ops.push_back(Op); 3868 break; 3869 } 3870 case Expand: 3871 if (VT != MVT::Vector) { 3872 // If this is a large integer or a floating point node that needs to be 3873 // expanded, it needs to be reassembled from small integers. Figure out 3874 // what the source elt type is and how many small integers it is. 3875 Ops.push_back(ExpandScalarFormalArgs(VT, Result, i, DAG, *this)); 3876 } else { 3877 // Otherwise, this is a vector type. We only support legal vectors 3878 // right now. 3879 const VectorType *PTy = cast<VectorType>(I->getType()); 3880 unsigned NumElems = PTy->getNumElements(); 3881 const Type *EltTy = PTy->getElementType(); 3882 3883 // Figure out if there is a Packed type corresponding to this Vector 3884 // type. If so, convert to the vector type. 3885 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 3886 if (TVT != MVT::Other && isTypeLegal(TVT)) { 3887 SDOperand N = SDOperand(Result, i++); 3888 // Handle copies from generic vectors to registers. 3889 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, 3890 DAG.getConstant(NumElems, MVT::i32), 3891 DAG.getValueType(getValueType(EltTy))); 3892 Ops.push_back(N); 3893 } else { 3894 assert(0 && "Don't support illegal by-val vector arguments yet!"); 3895 abort(); 3896 } 3897 } 3898 break; 3899 } 3900 } 3901 return Ops; 3902} 3903 3904 3905/// ExpandScalarCallArgs - Recursively expand call argument node by 3906/// bit_converting it or extract a pair of elements from the larger node. 3907static void ExpandScalarCallArgs(MVT::ValueType VT, SDOperand Arg, 3908 unsigned Flags, 3909 SmallVector<SDOperand, 32> &Ops, 3910 SelectionDAG &DAG, 3911 TargetLowering &TLI, 3912 bool isFirst = true) { 3913 3914 if (TLI.getTypeAction(VT) != TargetLowering::Expand) { 3915 // if it isn't first piece, alignment must be 1 3916 if (!isFirst) 3917 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3918 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3919 Ops.push_back(Arg); 3920 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3921 return; 3922 } 3923 3924 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT); 3925 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT); 3926 if (NumVals == 1) { 3927 Arg = DAG.getNode(ISD::BIT_CONVERT, EVT, Arg); 3928 ExpandScalarCallArgs(EVT, Arg, Flags, Ops, DAG, TLI, isFirst); 3929 } else if (NumVals == 2) { 3930 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg, 3931 DAG.getConstant(0, TLI.getPointerTy())); 3932 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg, 3933 DAG.getConstant(1, TLI.getPointerTy())); 3934 if (!TLI.isLittleEndian()) 3935 std::swap(Lo, Hi); 3936 ExpandScalarCallArgs(EVT, Lo, Flags, Ops, DAG, TLI, isFirst); 3937 ExpandScalarCallArgs(EVT, Hi, Flags, Ops, DAG, TLI, false); 3938 } else { 3939 // Value scalarized into many values. Unimp for now. 3940 assert(0 && "Cannot expand i64 -> i16 yet!"); 3941 } 3942} 3943 3944/// TargetLowering::LowerCallTo - This is the default LowerCallTo 3945/// implementation, which just inserts an ISD::CALL node, which is later custom 3946/// lowered by the target to something concrete. FIXME: When all targets are 3947/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 3948std::pair<SDOperand, SDOperand> 3949TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 3950 bool RetTyIsSigned, bool isVarArg, 3951 unsigned CallingConv, bool isTailCall, 3952 SDOperand Callee, 3953 ArgListTy &Args, SelectionDAG &DAG) { 3954 SmallVector<SDOperand, 32> Ops; 3955 Ops.push_back(Chain); // Op#0 - Chain 3956 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 3957 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 3958 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 3959 Ops.push_back(Callee); 3960 3961 // Handle all of the outgoing arguments. 3962 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 3963 MVT::ValueType VT = getValueType(Args[i].Ty); 3964 SDOperand Op = Args[i].Node; 3965 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3966 unsigned OriginalAlignment = 3967 getTargetData()->getABITypeAlignment(Args[i].Ty); 3968 3969 if (Args[i].isSExt) 3970 Flags |= ISD::ParamFlags::SExt; 3971 if (Args[i].isZExt) 3972 Flags |= ISD::ParamFlags::ZExt; 3973 if (Args[i].isInReg) 3974 Flags |= ISD::ParamFlags::InReg; 3975 if (Args[i].isSRet) 3976 Flags |= ISD::ParamFlags::StructReturn; 3977 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs; 3978 3979 switch (getTypeAction(VT)) { 3980 default: assert(0 && "Unknown type action!"); 3981 case Legal: 3982 Ops.push_back(Op); 3983 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3984 break; 3985 case Promote: 3986 if (MVT::isInteger(VT)) { 3987 unsigned ExtOp; 3988 if (Args[i].isSExt) 3989 ExtOp = ISD::SIGN_EXTEND; 3990 else if (Args[i].isZExt) 3991 ExtOp = ISD::ZERO_EXTEND; 3992 else 3993 ExtOp = ISD::ANY_EXTEND; 3994 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 3995 } else { 3996 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3997 // A true promotion would change the size of the argument. 3998 // Instead, pretend this is an int. If FP objects are not 3999 // passed the same as ints, the original type should be Legal 4000 // and we should not get here. 4001 Op = DAG.getNode(ISD::BIT_CONVERT, 4002 VT==MVT::f32 ? MVT::i32 : 4003 (VT==MVT::f64 ? MVT::i64 : 4004 MVT::Other), 4005 Op); 4006 } 4007 Ops.push_back(Op); 4008 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4009 break; 4010 case Expand: 4011 if (VT != MVT::Vector) { 4012 // If this is a large integer, it needs to be broken down into small 4013 // integers. Figure out what the source elt type is and how many small 4014 // integers it is. 4015 ExpandScalarCallArgs(VT, Op, Flags, Ops, DAG, *this); 4016 } else { 4017 // Otherwise, this is a vector type. We only support legal vectors 4018 // right now. 4019 const VectorType *PTy = cast<VectorType>(Args[i].Ty); 4020 unsigned NumElems = PTy->getNumElements(); 4021 const Type *EltTy = PTy->getElementType(); 4022 4023 // Figure out if there is a Packed type corresponding to this Vector 4024 // type. If so, convert to the vector type. 4025 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 4026 if (TVT != MVT::Other && isTypeLegal(TVT)) { 4027 // Insert a VBIT_CONVERT of the MVT::Vector type to the vector type. 4028 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op); 4029 Ops.push_back(Op); 4030 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4031 } else { 4032 assert(0 && "Don't support illegal by-val vector call args yet!"); 4033 abort(); 4034 } 4035 } 4036 break; 4037 } 4038 } 4039 4040 // Figure out the result value types. 4041 SmallVector<MVT::ValueType, 4> RetTys; 4042 4043 if (RetTy != Type::VoidTy) { 4044 MVT::ValueType VT = getValueType(RetTy); 4045 switch (getTypeAction(VT)) { 4046 default: assert(0 && "Unknown type action!"); 4047 case Legal: 4048 RetTys.push_back(VT); 4049 break; 4050 case Promote: 4051 RetTys.push_back(getTypeToTransformTo(VT)); 4052 break; 4053 case Expand: 4054 if (VT != MVT::Vector) { 4055 // If this is a large integer, it needs to be reassembled from small 4056 // integers. Figure out what the source elt type is and how many small 4057 // integers it is. 4058 MVT::ValueType NVT = getTypeToExpandTo(VT); 4059 unsigned NumVals = getNumElements(VT); 4060 for (unsigned i = 0; i != NumVals; ++i) 4061 RetTys.push_back(NVT); 4062 } else { 4063 // Otherwise, this is a vector type. We only support legal vectors 4064 // right now. 4065 const VectorType *PTy = cast<VectorType>(RetTy); 4066 unsigned NumElems = PTy->getNumElements(); 4067 const Type *EltTy = PTy->getElementType(); 4068 4069 // Figure out if there is a Packed type corresponding to this Vector 4070 // type. If so, convert to the vector type. 4071 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 4072 if (TVT != MVT::Other && isTypeLegal(TVT)) { 4073 RetTys.push_back(TVT); 4074 } else { 4075 assert(0 && "Don't support illegal by-val vector call results yet!"); 4076 abort(); 4077 } 4078 } 4079 } 4080 } 4081 4082 RetTys.push_back(MVT::Other); // Always has a chain. 4083 4084 // Finally, create the CALL node. 4085 SDOperand Res = DAG.getNode(ISD::CALL, 4086 DAG.getVTList(&RetTys[0], RetTys.size()), 4087 &Ops[0], Ops.size()); 4088 4089 // This returns a pair of operands. The first element is the 4090 // return value for the function (if RetTy is not VoidTy). The second 4091 // element is the outgoing token chain. 4092 SDOperand ResVal; 4093 if (RetTys.size() != 1) { 4094 MVT::ValueType VT = getValueType(RetTy); 4095 if (RetTys.size() == 2) { 4096 ResVal = Res; 4097 4098 // If this value was promoted, truncate it down. 4099 if (ResVal.getValueType() != VT) { 4100 if (VT == MVT::Vector) { 4101 // Insert a VBIT_CONVERT to convert from the packed result type to the 4102 // MVT::Vector type. 4103 unsigned NumElems = cast<VectorType>(RetTy)->getNumElements(); 4104 const Type *EltTy = cast<VectorType>(RetTy)->getElementType(); 4105 4106 // Figure out if there is a Packed type corresponding to this Vector 4107 // type. If so, convert to the vector type. 4108 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy),NumElems); 4109 if (TVT != MVT::Other && isTypeLegal(TVT)) { 4110 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a 4111 // "N x PTyElementVT" MVT::Vector type. 4112 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal, 4113 DAG.getConstant(NumElems, MVT::i32), 4114 DAG.getValueType(getValueType(EltTy))); 4115 } else { 4116 abort(); 4117 } 4118 } else if (MVT::isInteger(VT)) { 4119 unsigned AssertOp = ISD::AssertSext; 4120 if (!RetTyIsSigned) 4121 AssertOp = ISD::AssertZext; 4122 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal, 4123 DAG.getValueType(VT)); 4124 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal); 4125 } else { 4126 assert(MVT::isFloatingPoint(VT)); 4127 if (getTypeAction(VT) == Expand) 4128 ResVal = DAG.getNode(ISD::BIT_CONVERT, VT, ResVal); 4129 else 4130 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal); 4131 } 4132 } 4133 } else if (RetTys.size() == 3) { 4134 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT, 4135 Res.getValue(0), Res.getValue(1)); 4136 4137 } else { 4138 assert(0 && "Case not handled yet!"); 4139 } 4140 } 4141 4142 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1)); 4143} 4144 4145SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4146 assert(0 && "LowerOperation not implemented for this target!"); 4147 abort(); 4148 return SDOperand(); 4149} 4150 4151SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 4152 SelectionDAG &DAG) { 4153 assert(0 && "CustomPromoteOperation not implemented for this target!"); 4154 abort(); 4155 return SDOperand(); 4156} 4157 4158/// getMemsetValue - Vectorized representation of the memset value 4159/// operand. 4160static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 4161 SelectionDAG &DAG) { 4162 MVT::ValueType CurVT = VT; 4163 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 4164 uint64_t Val = C->getValue() & 255; 4165 unsigned Shift = 8; 4166 while (CurVT != MVT::i8) { 4167 Val = (Val << Shift) | Val; 4168 Shift <<= 1; 4169 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4170 } 4171 return DAG.getConstant(Val, VT); 4172 } else { 4173 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4174 unsigned Shift = 8; 4175 while (CurVT != MVT::i8) { 4176 Value = 4177 DAG.getNode(ISD::OR, VT, 4178 DAG.getNode(ISD::SHL, VT, Value, 4179 DAG.getConstant(Shift, MVT::i8)), Value); 4180 Shift <<= 1; 4181 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4182 } 4183 4184 return Value; 4185 } 4186} 4187 4188/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4189/// used when a memcpy is turned into a memset when the source is a constant 4190/// string ptr. 4191static SDOperand getMemsetStringVal(MVT::ValueType VT, 4192 SelectionDAG &DAG, TargetLowering &TLI, 4193 std::string &Str, unsigned Offset) { 4194 uint64_t Val = 0; 4195 unsigned MSB = MVT::getSizeInBits(VT) / 8; 4196 if (TLI.isLittleEndian()) 4197 Offset = Offset + MSB - 1; 4198 for (unsigned i = 0; i != MSB; ++i) { 4199 Val = (Val << 8) | (unsigned char)Str[Offset]; 4200 Offset += TLI.isLittleEndian() ? -1 : 1; 4201 } 4202 return DAG.getConstant(Val, VT); 4203} 4204 4205/// getMemBasePlusOffset - Returns base and offset node for the 4206static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4207 SelectionDAG &DAG, TargetLowering &TLI) { 4208 MVT::ValueType VT = Base.getValueType(); 4209 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4210} 4211 4212/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4213/// to replace the memset / memcpy is below the threshold. It also returns the 4214/// types of the sequence of memory ops to perform memset / memcpy. 4215static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4216 unsigned Limit, uint64_t Size, 4217 unsigned Align, TargetLowering &TLI) { 4218 MVT::ValueType VT; 4219 4220 if (TLI.allowsUnalignedMemoryAccesses()) { 4221 VT = MVT::i64; 4222 } else { 4223 switch (Align & 7) { 4224 case 0: 4225 VT = MVT::i64; 4226 break; 4227 case 4: 4228 VT = MVT::i32; 4229 break; 4230 case 2: 4231 VT = MVT::i16; 4232 break; 4233 default: 4234 VT = MVT::i8; 4235 break; 4236 } 4237 } 4238 4239 MVT::ValueType LVT = MVT::i64; 4240 while (!TLI.isTypeLegal(LVT)) 4241 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4242 assert(MVT::isInteger(LVT)); 4243 4244 if (VT > LVT) 4245 VT = LVT; 4246 4247 unsigned NumMemOps = 0; 4248 while (Size != 0) { 4249 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4250 while (VTSize > Size) { 4251 VT = (MVT::ValueType)((unsigned)VT - 1); 4252 VTSize >>= 1; 4253 } 4254 assert(MVT::isInteger(VT)); 4255 4256 if (++NumMemOps > Limit) 4257 return false; 4258 MemOps.push_back(VT); 4259 Size -= VTSize; 4260 } 4261 4262 return true; 4263} 4264 4265void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4266 SDOperand Op1 = getValue(I.getOperand(1)); 4267 SDOperand Op2 = getValue(I.getOperand(2)); 4268 SDOperand Op3 = getValue(I.getOperand(3)); 4269 SDOperand Op4 = getValue(I.getOperand(4)); 4270 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4271 if (Align == 0) Align = 1; 4272 4273 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4274 std::vector<MVT::ValueType> MemOps; 4275 4276 // Expand memset / memcpy to a series of load / store ops 4277 // if the size operand falls below a certain threshold. 4278 SmallVector<SDOperand, 8> OutChains; 4279 switch (Op) { 4280 default: break; // Do nothing for now. 4281 case ISD::MEMSET: { 4282 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4283 Size->getValue(), Align, TLI)) { 4284 unsigned NumMemOps = MemOps.size(); 4285 unsigned Offset = 0; 4286 for (unsigned i = 0; i < NumMemOps; i++) { 4287 MVT::ValueType VT = MemOps[i]; 4288 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4289 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4290 SDOperand Store = DAG.getStore(getRoot(), Value, 4291 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4292 I.getOperand(1), Offset); 4293 OutChains.push_back(Store); 4294 Offset += VTSize; 4295 } 4296 } 4297 break; 4298 } 4299 case ISD::MEMCPY: { 4300 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4301 Size->getValue(), Align, TLI)) { 4302 unsigned NumMemOps = MemOps.size(); 4303 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4304 GlobalAddressSDNode *G = NULL; 4305 std::string Str; 4306 bool CopyFromStr = false; 4307 4308 if (Op2.getOpcode() == ISD::GlobalAddress) 4309 G = cast<GlobalAddressSDNode>(Op2); 4310 else if (Op2.getOpcode() == ISD::ADD && 4311 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4312 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4313 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4314 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4315 } 4316 if (G) { 4317 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4318 if (GV && GV->isConstant()) { 4319 Str = GV->getStringValue(false); 4320 if (!Str.empty()) { 4321 CopyFromStr = true; 4322 SrcOff += SrcDelta; 4323 } 4324 } 4325 } 4326 4327 for (unsigned i = 0; i < NumMemOps; i++) { 4328 MVT::ValueType VT = MemOps[i]; 4329 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4330 SDOperand Value, Chain, Store; 4331 4332 if (CopyFromStr) { 4333 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4334 Chain = getRoot(); 4335 Store = 4336 DAG.getStore(Chain, Value, 4337 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4338 I.getOperand(1), DstOff); 4339 } else { 4340 Value = DAG.getLoad(VT, getRoot(), 4341 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4342 I.getOperand(2), SrcOff); 4343 Chain = Value.getValue(1); 4344 Store = 4345 DAG.getStore(Chain, Value, 4346 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4347 I.getOperand(1), DstOff); 4348 } 4349 OutChains.push_back(Store); 4350 SrcOff += VTSize; 4351 DstOff += VTSize; 4352 } 4353 } 4354 break; 4355 } 4356 } 4357 4358 if (!OutChains.empty()) { 4359 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4360 &OutChains[0], OutChains.size())); 4361 return; 4362 } 4363 } 4364 4365 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4)); 4366} 4367 4368//===----------------------------------------------------------------------===// 4369// SelectionDAGISel code 4370//===----------------------------------------------------------------------===// 4371 4372unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4373 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 4374} 4375 4376void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4377 AU.addRequired<AliasAnalysis>(); 4378 AU.setPreservesAll(); 4379} 4380 4381 4382 4383bool SelectionDAGISel::runOnFunction(Function &Fn) { 4384 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4385 RegMap = MF.getSSARegMap(); 4386 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4387 4388 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4389 4390 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4391 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) { 4392 // Mark landing pad. 4393 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[Invoke->getSuccessor(1)]; 4394 LandingPad->setIsLandingPad(); 4395 } 4396 4397 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4398 SelectBasicBlock(I, MF, FuncInfo); 4399 4400 // Add function live-ins to entry block live-in set. 4401 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4402 BB = FuncInfo.MBBMap[EntryBB]; 4403 if (!MF.livein_empty()) 4404 for (MachineFunction::livein_iterator I = MF.livein_begin(), 4405 E = MF.livein_end(); I != E; ++I) 4406 BB->addLiveIn(I->first); 4407 4408 return true; 4409} 4410 4411SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4412 unsigned Reg) { 4413 SDOperand Op = getValue(V); 4414 assert((Op.getOpcode() != ISD::CopyFromReg || 4415 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4416 "Copy from a reg to the same reg!"); 4417 4418 // If this type is not legal, we must make sure to not create an invalid 4419 // register use. 4420 MVT::ValueType SrcVT = Op.getValueType(); 4421 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT); 4422 if (SrcVT == DestVT) { 4423 return DAG.getCopyToReg(getRoot(), Reg, Op); 4424 } else if (SrcVT == MVT::Vector) { 4425 // Handle copies from generic vectors to registers. 4426 MVT::ValueType PTyElementVT, PTyLegalElementVT; 4427 unsigned NE = TLI.getVectorTypeBreakdown(cast<VectorType>(V->getType()), 4428 PTyElementVT, PTyLegalElementVT); 4429 4430 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT" 4431 // MVT::Vector type. 4432 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op, 4433 DAG.getConstant(NE, MVT::i32), 4434 DAG.getValueType(PTyElementVT)); 4435 4436 // Loop over all of the elements of the resultant vector, 4437 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then 4438 // copying them into output registers. 4439 SmallVector<SDOperand, 8> OutChains; 4440 SDOperand Root = getRoot(); 4441 for (unsigned i = 0; i != NE; ++i) { 4442 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT, 4443 Op, DAG.getConstant(i, TLI.getPointerTy())); 4444 if (PTyElementVT == PTyLegalElementVT) { 4445 // Elements are legal. 4446 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); 4447 } else if (PTyLegalElementVT > PTyElementVT) { 4448 // Elements are promoted. 4449 if (MVT::isFloatingPoint(PTyLegalElementVT)) 4450 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt); 4451 else 4452 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt); 4453 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); 4454 } else { 4455 // Elements are expanded. 4456 // The src value is expanded into multiple registers. 4457 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, 4458 Elt, DAG.getConstant(0, TLI.getPointerTy())); 4459 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, 4460 Elt, DAG.getConstant(1, TLI.getPointerTy())); 4461 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo)); 4462 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi)); 4463 } 4464 } 4465 return DAG.getNode(ISD::TokenFactor, MVT::Other, 4466 &OutChains[0], OutChains.size()); 4467 } else if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) { 4468 // The src value is promoted to the register. 4469 if (MVT::isFloatingPoint(SrcVT)) 4470 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op); 4471 else 4472 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op); 4473 return DAG.getCopyToReg(getRoot(), Reg, Op); 4474 } else { 4475 DestVT = TLI.getTypeToExpandTo(SrcVT); 4476 unsigned NumVals = TLI.getNumElements(SrcVT); 4477 if (NumVals == 1) 4478 return DAG.getCopyToReg(getRoot(), Reg, 4479 DAG.getNode(ISD::BIT_CONVERT, DestVT, Op)); 4480 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!"); 4481 // The src value is expanded into multiple registers. 4482 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 4483 Op, DAG.getConstant(0, TLI.getPointerTy())); 4484 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 4485 Op, DAG.getConstant(1, TLI.getPointerTy())); 4486 Op = DAG.getCopyToReg(getRoot(), Reg, Lo); 4487 return DAG.getCopyToReg(Op, Reg+1, Hi); 4488 } 4489} 4490 4491void SelectionDAGISel:: 4492LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4493 std::vector<SDOperand> &UnorderedChains) { 4494 // If this is the entry block, emit arguments. 4495 Function &F = *LLVMBB->getParent(); 4496 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4497 SDOperand OldRoot = SDL.DAG.getRoot(); 4498 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4499 4500 unsigned a = 0; 4501 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4502 AI != E; ++AI, ++a) 4503 if (!AI->use_empty()) { 4504 SDL.setValue(AI, Args[a]); 4505 4506 // If this argument is live outside of the entry block, insert a copy from 4507 // whereever we got it to the vreg that other BB's will reference it as. 4508 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4509 if (VMI != FuncInfo.ValueMap.end()) { 4510 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4511 UnorderedChains.push_back(Copy); 4512 } 4513 } 4514 4515 // Finally, if the target has anything special to do, allow it to do so. 4516 // FIXME: this should insert code into the DAG! 4517 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4518} 4519 4520void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4521 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4522 FunctionLoweringInfo &FuncInfo) { 4523 SelectionDAGLowering SDL(DAG, TLI, FuncInfo); 4524 4525 std::vector<SDOperand> UnorderedChains; 4526 4527 // Lower any arguments needed in this block if this is the entry block. 4528 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4529 LowerArguments(LLVMBB, SDL, UnorderedChains); 4530 4531 BB = FuncInfo.MBBMap[LLVMBB]; 4532 SDL.setCurrentBasicBlock(BB); 4533 4534 if (ExceptionHandling && BB->isLandingPad()) { 4535 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4536 4537 if (MMI) { 4538 // Add a label to mark the beginning of the landing pad. Deletion of the 4539 // landing pad can thus be detected via the MachineModuleInfo. 4540 unsigned LabelID = MMI->addLandingPad(BB); 4541 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 4542 DAG.getConstant(LabelID, MVT::i32))); 4543 } 4544 } 4545 4546 // Lower all of the non-terminator instructions. 4547 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4548 I != E; ++I) 4549 SDL.visit(*I); 4550 4551 // Ensure that all instructions which are used outside of their defining 4552 // blocks are available as virtual registers. Invoke is handled elsewhere. 4553 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4554 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 4555 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4556 if (VMI != FuncInfo.ValueMap.end()) 4557 UnorderedChains.push_back( 4558 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4559 } 4560 4561 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4562 // ensure constants are generated when needed. Remember the virtual registers 4563 // that need to be added to the Machine PHI nodes as input. We cannot just 4564 // directly add them, because expansion might result in multiple MBB's for one 4565 // BB. As such, the start of the BB might correspond to a different MBB than 4566 // the end. 4567 // 4568 TerminatorInst *TI = LLVMBB->getTerminator(); 4569 4570 // Emit constants only once even if used by multiple PHI nodes. 4571 std::map<Constant*, unsigned> ConstantsOut; 4572 4573 // Vector bool would be better, but vector<bool> is really slow. 4574 std::vector<unsigned char> SuccsHandled; 4575 if (TI->getNumSuccessors()) 4576 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4577 4578 // Check successor nodes PHI nodes that expect a constant to be available from 4579 // this block. 4580 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4581 BasicBlock *SuccBB = TI->getSuccessor(succ); 4582 if (!isa<PHINode>(SuccBB->begin())) continue; 4583 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4584 4585 // If this terminator has multiple identical successors (common for 4586 // switches), only handle each succ once. 4587 unsigned SuccMBBNo = SuccMBB->getNumber(); 4588 if (SuccsHandled[SuccMBBNo]) continue; 4589 SuccsHandled[SuccMBBNo] = true; 4590 4591 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4592 PHINode *PN; 4593 4594 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4595 // nodes and Machine PHI nodes, but the incoming operands have not been 4596 // emitted yet. 4597 for (BasicBlock::iterator I = SuccBB->begin(); 4598 (PN = dyn_cast<PHINode>(I)); ++I) { 4599 // Ignore dead phi's. 4600 if (PN->use_empty()) continue; 4601 4602 unsigned Reg; 4603 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4604 4605 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4606 unsigned &RegOut = ConstantsOut[C]; 4607 if (RegOut == 0) { 4608 RegOut = FuncInfo.CreateRegForValue(C); 4609 UnorderedChains.push_back( 4610 SDL.CopyValueToVirtualRegister(C, RegOut)); 4611 } 4612 Reg = RegOut; 4613 } else { 4614 Reg = FuncInfo.ValueMap[PHIOp]; 4615 if (Reg == 0) { 4616 assert(isa<AllocaInst>(PHIOp) && 4617 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4618 "Didn't codegen value into a register!??"); 4619 Reg = FuncInfo.CreateRegForValue(PHIOp); 4620 UnorderedChains.push_back( 4621 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4622 } 4623 } 4624 4625 // Remember that this register needs to added to the machine PHI node as 4626 // the input for this MBB. 4627 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4628 unsigned NumElements; 4629 if (VT != MVT::Vector) 4630 NumElements = TLI.getNumElements(VT); 4631 else { 4632 MVT::ValueType VT1,VT2; 4633 NumElements = 4634 TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()), 4635 VT1, VT2); 4636 } 4637 for (unsigned i = 0, e = NumElements; i != e; ++i) 4638 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4639 } 4640 } 4641 ConstantsOut.clear(); 4642 4643 // Turn all of the unordered chains into one factored node. 4644 if (!UnorderedChains.empty()) { 4645 SDOperand Root = SDL.getRoot(); 4646 if (Root.getOpcode() != ISD::EntryToken) { 4647 unsigned i = 0, e = UnorderedChains.size(); 4648 for (; i != e; ++i) { 4649 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4650 if (UnorderedChains[i].Val->getOperand(0) == Root) 4651 break; // Don't add the root if we already indirectly depend on it. 4652 } 4653 4654 if (i == e) 4655 UnorderedChains.push_back(Root); 4656 } 4657 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4658 &UnorderedChains[0], UnorderedChains.size())); 4659 } 4660 4661 // Lower the terminator after the copies are emitted. 4662 SDL.visit(*LLVMBB->getTerminator()); 4663 4664 // Copy over any CaseBlock records that may now exist due to SwitchInst 4665 // lowering, as well as any jump table information. 4666 SwitchCases.clear(); 4667 SwitchCases = SDL.SwitchCases; 4668 JTCases.clear(); 4669 JTCases = SDL.JTCases; 4670 BitTestCases.clear(); 4671 BitTestCases = SDL.BitTestCases; 4672 4673 // Make sure the root of the DAG is up-to-date. 4674 DAG.setRoot(SDL.getRoot()); 4675} 4676 4677void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4678 // Get alias analysis for load/store combining. 4679 AliasAnalysis &AA = getAnalysis<AliasAnalysis>(); 4680 4681 // Run the DAG combiner in pre-legalize mode. 4682 DAG.Combine(false, AA); 4683 4684 DOUT << "Lowered selection DAG:\n"; 4685 DEBUG(DAG.dump()); 4686 4687 // Second step, hack on the DAG until it only uses operations and types that 4688 // the target supports. 4689 DAG.Legalize(); 4690 4691 DOUT << "Legalized selection DAG:\n"; 4692 DEBUG(DAG.dump()); 4693 4694 // Run the DAG combiner in post-legalize mode. 4695 DAG.Combine(true, AA); 4696 4697 if (ViewISelDAGs) DAG.viewGraph(); 4698 4699 // Third, instruction select all of the operations to machine code, adding the 4700 // code to the MachineBasicBlock. 4701 InstructionSelectBasicBlock(DAG); 4702 4703 DOUT << "Selected machine code:\n"; 4704 DEBUG(BB->dump()); 4705} 4706 4707void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4708 FunctionLoweringInfo &FuncInfo) { 4709 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4710 { 4711 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4712 CurDAG = &DAG; 4713 4714 // First step, lower LLVM code to some DAG. This DAG may use operations and 4715 // types that are not supported by the target. 4716 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4717 4718 // Second step, emit the lowered DAG as machine code. 4719 CodeGenAndEmitDAG(DAG); 4720 } 4721 4722 DOUT << "Total amount of phi nodes to update: " 4723 << PHINodesToUpdate.size() << "\n"; 4724 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4725 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4726 << ", " << PHINodesToUpdate[i].second << ")\n";); 4727 4728 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4729 // PHI nodes in successors. 4730 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4731 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4732 MachineInstr *PHI = PHINodesToUpdate[i].first; 4733 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4734 "This is not a machine PHI node that we are updating!"); 4735 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4736 PHI->addMachineBasicBlockOperand(BB); 4737 } 4738 return; 4739 } 4740 4741 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4742 // Lower header first, if it wasn't already lowered 4743 if (!BitTestCases[i].Emitted) { 4744 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4745 CurDAG = &HSDAG; 4746 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo); 4747 // Set the current basic block to the mbb we wish to insert the code into 4748 BB = BitTestCases[i].Parent; 4749 HSDL.setCurrentBasicBlock(BB); 4750 // Emit the code 4751 HSDL.visitBitTestHeader(BitTestCases[i]); 4752 HSDAG.setRoot(HSDL.getRoot()); 4753 CodeGenAndEmitDAG(HSDAG); 4754 } 4755 4756 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4757 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4758 CurDAG = &BSDAG; 4759 SelectionDAGLowering BSDL(BSDAG, TLI, FuncInfo); 4760 // Set the current basic block to the mbb we wish to insert the code into 4761 BB = BitTestCases[i].Cases[j].ThisBB; 4762 BSDL.setCurrentBasicBlock(BB); 4763 // Emit the code 4764 if (j+1 != ej) 4765 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 4766 BitTestCases[i].Reg, 4767 BitTestCases[i].Cases[j]); 4768 else 4769 BSDL.visitBitTestCase(BitTestCases[i].Default, 4770 BitTestCases[i].Reg, 4771 BitTestCases[i].Cases[j]); 4772 4773 4774 BSDAG.setRoot(BSDL.getRoot()); 4775 CodeGenAndEmitDAG(BSDAG); 4776 } 4777 4778 // Update PHI Nodes 4779 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4780 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4781 MachineBasicBlock *PHIBB = PHI->getParent(); 4782 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4783 "This is not a machine PHI node that we are updating!"); 4784 // This is "default" BB. We have two jumps to it. From "header" BB and 4785 // from last "case" BB. 4786 if (PHIBB == BitTestCases[i].Default) { 4787 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4788 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent); 4789 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4790 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB); 4791 } 4792 // One of "cases" BB. 4793 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4794 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 4795 if (cBB->succ_end() != 4796 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 4797 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4798 PHI->addMachineBasicBlockOperand(cBB); 4799 } 4800 } 4801 } 4802 } 4803 4804 // If the JumpTable record is filled in, then we need to emit a jump table. 4805 // Updating the PHI nodes is tricky in this case, since we need to determine 4806 // whether the PHI is a successor of the range check MBB or the jump table MBB 4807 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 4808 // Lower header first, if it wasn't already lowered 4809 if (!JTCases[i].first.Emitted) { 4810 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4811 CurDAG = &HSDAG; 4812 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo); 4813 // Set the current basic block to the mbb we wish to insert the code into 4814 BB = JTCases[i].first.HeaderBB; 4815 HSDL.setCurrentBasicBlock(BB); 4816 // Emit the code 4817 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 4818 HSDAG.setRoot(HSDL.getRoot()); 4819 CodeGenAndEmitDAG(HSDAG); 4820 } 4821 4822 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4823 CurDAG = &JSDAG; 4824 SelectionDAGLowering JSDL(JSDAG, TLI, FuncInfo); 4825 // Set the current basic block to the mbb we wish to insert the code into 4826 BB = JTCases[i].second.MBB; 4827 JSDL.setCurrentBasicBlock(BB); 4828 // Emit the code 4829 JSDL.visitJumpTable(JTCases[i].second); 4830 JSDAG.setRoot(JSDL.getRoot()); 4831 CodeGenAndEmitDAG(JSDAG); 4832 4833 // Update PHI Nodes 4834 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4835 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4836 MachineBasicBlock *PHIBB = PHI->getParent(); 4837 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4838 "This is not a machine PHI node that we are updating!"); 4839 // "default" BB. We can go there only from header BB. 4840 if (PHIBB == JTCases[i].second.Default) { 4841 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4842 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB); 4843 } 4844 // JT BB. Just iterate over successors here 4845 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 4846 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4847 PHI->addMachineBasicBlockOperand(BB); 4848 } 4849 } 4850 } 4851 4852 // If the switch block involved a branch to one of the actual successors, we 4853 // need to update PHI nodes in that block. 4854 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4855 MachineInstr *PHI = PHINodesToUpdate[i].first; 4856 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4857 "This is not a machine PHI node that we are updating!"); 4858 if (BB->isSuccessor(PHI->getParent())) { 4859 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4860 PHI->addMachineBasicBlockOperand(BB); 4861 } 4862 } 4863 4864 // If we generated any switch lowering information, build and codegen any 4865 // additional DAGs necessary. 4866 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 4867 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4868 CurDAG = &SDAG; 4869 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 4870 4871 // Set the current basic block to the mbb we wish to insert the code into 4872 BB = SwitchCases[i].ThisBB; 4873 SDL.setCurrentBasicBlock(BB); 4874 4875 // Emit the code 4876 SDL.visitSwitchCase(SwitchCases[i]); 4877 SDAG.setRoot(SDL.getRoot()); 4878 CodeGenAndEmitDAG(SDAG); 4879 4880 // Handle any PHI nodes in successors of this chunk, as if we were coming 4881 // from the original BB before switch expansion. Note that PHI nodes can 4882 // occur multiple times in PHINodesToUpdate. We have to be very careful to 4883 // handle them the right number of times. 4884 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 4885 for (MachineBasicBlock::iterator Phi = BB->begin(); 4886 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 4887 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 4888 for (unsigned pn = 0; ; ++pn) { 4889 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 4890 if (PHINodesToUpdate[pn].first == Phi) { 4891 Phi->addRegOperand(PHINodesToUpdate[pn].second, false); 4892 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB); 4893 break; 4894 } 4895 } 4896 } 4897 4898 // Don't process RHS if same block as LHS. 4899 if (BB == SwitchCases[i].FalseBB) 4900 SwitchCases[i].FalseBB = 0; 4901 4902 // If we haven't handled the RHS, do so now. Otherwise, we're done. 4903 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 4904 SwitchCases[i].FalseBB = 0; 4905 } 4906 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 4907 } 4908} 4909 4910 4911//===----------------------------------------------------------------------===// 4912/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 4913/// target node in the graph. 4914void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 4915 if (ViewSchedDAGs) DAG.viewGraph(); 4916 4917 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 4918 4919 if (!Ctor) { 4920 Ctor = ISHeuristic; 4921 RegisterScheduler::setDefault(Ctor); 4922 } 4923 4924 ScheduleDAG *SL = Ctor(this, &DAG, BB); 4925 BB = SL->Run(); 4926 delete SL; 4927} 4928 4929 4930HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 4931 return new HazardRecognizer(); 4932} 4933 4934//===----------------------------------------------------------------------===// 4935// Helper functions used by the generated instruction selector. 4936//===----------------------------------------------------------------------===// 4937// Calls to these methods are generated by tblgen. 4938 4939/// CheckAndMask - The isel is trying to match something like (and X, 255). If 4940/// the dag combiner simplified the 255, we still want to match. RHS is the 4941/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 4942/// specified in the .td file (e.g. 255). 4943bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 4944 int64_t DesiredMaskS) { 4945 uint64_t ActualMask = RHS->getValue(); 4946 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4947 4948 // If the actual mask exactly matches, success! 4949 if (ActualMask == DesiredMask) 4950 return true; 4951 4952 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4953 if (ActualMask & ~DesiredMask) 4954 return false; 4955 4956 // Otherwise, the DAG Combiner may have proven that the value coming in is 4957 // either already zero or is not demanded. Check for known zero input bits. 4958 uint64_t NeededMask = DesiredMask & ~ActualMask; 4959 if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask)) 4960 return true; 4961 4962 // TODO: check to see if missing bits are just not demanded. 4963 4964 // Otherwise, this pattern doesn't match. 4965 return false; 4966} 4967 4968/// CheckOrMask - The isel is trying to match something like (or X, 255). If 4969/// the dag combiner simplified the 255, we still want to match. RHS is the 4970/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 4971/// specified in the .td file (e.g. 255). 4972bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 4973 int64_t DesiredMaskS) { 4974 uint64_t ActualMask = RHS->getValue(); 4975 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4976 4977 // If the actual mask exactly matches, success! 4978 if (ActualMask == DesiredMask) 4979 return true; 4980 4981 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4982 if (ActualMask & ~DesiredMask) 4983 return false; 4984 4985 // Otherwise, the DAG Combiner may have proven that the value coming in is 4986 // either already zero or is not demanded. Check for known zero input bits. 4987 uint64_t NeededMask = DesiredMask & ~ActualMask; 4988 4989 uint64_t KnownZero, KnownOne; 4990 getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 4991 4992 // If all the missing bits in the or are already known to be set, match! 4993 if ((NeededMask & KnownOne) == NeededMask) 4994 return true; 4995 4996 // TODO: check to see if missing bits are just not demanded. 4997 4998 // Otherwise, this pattern doesn't match. 4999 return false; 5000} 5001 5002 5003/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 5004/// by tblgen. Others should not call it. 5005void SelectionDAGISel:: 5006SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 5007 std::vector<SDOperand> InOps; 5008 std::swap(InOps, Ops); 5009 5010 Ops.push_back(InOps[0]); // input chain. 5011 Ops.push_back(InOps[1]); // input asm string. 5012 5013 unsigned i = 2, e = InOps.size(); 5014 if (InOps[e-1].getValueType() == MVT::Flag) 5015 --e; // Don't process a flag operand if it is here. 5016 5017 while (i != e) { 5018 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 5019 if ((Flags & 7) != 4 /*MEM*/) { 5020 // Just skip over this operand, copying the operands verbatim. 5021 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 5022 i += (Flags >> 3) + 1; 5023 } else { 5024 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 5025 // Otherwise, this is a memory operand. Ask the target to select it. 5026 std::vector<SDOperand> SelOps; 5027 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 5028 cerr << "Could not match memory address. Inline asm failure!\n"; 5029 exit(1); 5030 } 5031 5032 // Add this to the output node. 5033 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 5034 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 5035 IntPtrTy)); 5036 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 5037 i += 2; 5038 } 5039 } 5040 5041 // Add the flag input back if present. 5042 if (e != InOps.size()) 5043 Ops.push_back(InOps.back()); 5044} 5045 5046char SelectionDAGISel::ID = 0; 5047