SelectionDAGISel.cpp revision 2048b85c7c2c987874b9423e682ec8e60b60574b
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/FastISel.h" 32#include "llvm/CodeGen/GCStrategy.h" 33#include "llvm/CodeGen/GCMetadata.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineFunctionAnalysis.h" 36#include "llvm/CodeGen/MachineFrameInfo.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineJumpTableInfo.h" 39#include "llvm/CodeGen/MachineModuleInfo.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 42#include "llvm/CodeGen/SchedulerRegistry.h" 43#include "llvm/CodeGen/SelectionDAG.h" 44#include "llvm/CodeGen/DwarfWriter.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameInfo.h" 48#include "llvm/Target/TargetIntrinsicInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetLowering.h" 51#include "llvm/Target/TargetMachine.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/Timer.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62static cl::opt<bool> 63DisableLegalizeTypes("disable-legalize-types", cl::Hidden); 64static cl::opt<bool> 65EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 66 cl::desc("Enable verbose messages in the \"fast\" " 67 "instruction selector")); 68static cl::opt<bool> 69EnableFastISelAbort("fast-isel-abort", cl::Hidden, 70 cl::desc("Enable abort calls when \"fast\" instruction fails")); 71static cl::opt<bool> 72SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 73 cl::desc("Schedule copies of livein registers"), 74 cl::init(false)); 75 76#ifndef NDEBUG 77static cl::opt<bool> 78ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 79 cl::desc("Pop up a window to show dags before the first " 80 "dag combine pass")); 81static cl::opt<bool> 82ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 83 cl::desc("Pop up a window to show dags before legalize types")); 84static cl::opt<bool> 85ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 86 cl::desc("Pop up a window to show dags before legalize")); 87static cl::opt<bool> 88ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 89 cl::desc("Pop up a window to show dags before the second " 90 "dag combine pass")); 91static cl::opt<bool> 92ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 93 cl::desc("Pop up a window to show dags before the post legalize types" 94 " dag combine pass")); 95static cl::opt<bool> 96ViewISelDAGs("view-isel-dags", cl::Hidden, 97 cl::desc("Pop up a window to show isel dags as they are selected")); 98static cl::opt<bool> 99ViewSchedDAGs("view-sched-dags", cl::Hidden, 100 cl::desc("Pop up a window to show sched dags as they are processed")); 101static cl::opt<bool> 102ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 103 cl::desc("Pop up a window to show SUnit dags after they are processed")); 104#else 105static const bool ViewDAGCombine1 = false, 106 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 107 ViewDAGCombine2 = false, 108 ViewDAGCombineLT = false, 109 ViewISelDAGs = false, ViewSchedDAGs = false, 110 ViewSUnitDAGs = false; 111#endif 112 113//===---------------------------------------------------------------------===// 114/// 115/// RegisterScheduler class - Track the registration of instruction schedulers. 116/// 117//===---------------------------------------------------------------------===// 118MachinePassRegistry RegisterScheduler::Registry; 119 120//===---------------------------------------------------------------------===// 121/// 122/// ISHeuristic command line option for instruction schedulers. 123/// 124//===---------------------------------------------------------------------===// 125static cl::opt<RegisterScheduler::FunctionPassCtor, false, 126 RegisterPassParser<RegisterScheduler> > 127ISHeuristic("pre-RA-sched", 128 cl::init(&createDefaultScheduler), 129 cl::desc("Instruction schedulers available (before register" 130 " allocation):")); 131 132static RegisterScheduler 133defaultListDAGScheduler("default", "Best scheduler for the target", 134 createDefaultScheduler); 135 136namespace llvm { 137 //===--------------------------------------------------------------------===// 138 /// createDefaultScheduler - This creates an instruction scheduler appropriate 139 /// for the target. 140 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 141 CodeGenOpt::Level OptLevel) { 142 const TargetLowering &TLI = IS->getTargetLowering(); 143 144 if (OptLevel == CodeGenOpt::None) 145 return createFastDAGScheduler(IS, OptLevel); 146 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 147 return createTDListDAGScheduler(IS, OptLevel); 148 assert(TLI.getSchedulingPreference() == 149 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 150 return createBURRListDAGScheduler(IS, OptLevel); 151 } 152} 153 154// EmitInstrWithCustomInserter - This method should be implemented by targets 155// that mark instructions with the 'usesCustomInserter' flag. These 156// instructions are special in various ways, which require special support to 157// insert. The specified MachineInstr is created but not inserted into any 158// basic blocks, and this method is called to expand it into a sequence of 159// instructions, potentially also creating new basic blocks and control flow. 160// When new basic blocks are inserted and the edges from MBB to its successors 161// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 162// DenseMap. 163MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 164 MachineBasicBlock *MBB, 165 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 166#ifndef NDEBUG 167 errs() << "If a target marks an instruction with " 168 "'usesCustomInserter', it must implement " 169 "TargetLowering::EmitInstrWithCustomInserter!"; 170#endif 171 llvm_unreachable(0); 172 return 0; 173} 174 175/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 176/// physical register has only a single copy use, then coalesced the copy 177/// if possible. 178static void EmitLiveInCopy(MachineBasicBlock *MBB, 179 MachineBasicBlock::iterator &InsertPos, 180 unsigned VirtReg, unsigned PhysReg, 181 const TargetRegisterClass *RC, 182 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 183 const MachineRegisterInfo &MRI, 184 const TargetRegisterInfo &TRI, 185 const TargetInstrInfo &TII) { 186 unsigned NumUses = 0; 187 MachineInstr *UseMI = NULL; 188 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 189 UE = MRI.use_end(); UI != UE; ++UI) { 190 UseMI = &*UI; 191 if (++NumUses > 1) 192 break; 193 } 194 195 // If the number of uses is not one, or the use is not a move instruction, 196 // don't coalesce. Also, only coalesce away a virtual register to virtual 197 // register copy. 198 bool Coalesced = false; 199 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 200 if (NumUses == 1 && 201 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 202 TargetRegisterInfo::isVirtualRegister(DstReg)) { 203 VirtReg = DstReg; 204 Coalesced = true; 205 } 206 207 // Now find an ideal location to insert the copy. 208 MachineBasicBlock::iterator Pos = InsertPos; 209 while (Pos != MBB->begin()) { 210 MachineInstr *PrevMI = prior(Pos); 211 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 212 // copyRegToReg might emit multiple instructions to do a copy. 213 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 214 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 215 // This is what the BB looks like right now: 216 // r1024 = mov r0 217 // ... 218 // r1 = mov r1024 219 // 220 // We want to insert "r1025 = mov r1". Inserting this copy below the 221 // move to r1024 makes it impossible for that move to be coalesced. 222 // 223 // r1025 = mov r1 224 // r1024 = mov r0 225 // ... 226 // r1 = mov 1024 227 // r2 = mov 1025 228 break; // Woot! Found a good location. 229 --Pos; 230 } 231 232 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 233 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 234 (void) Emitted; 235 236 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 237 if (Coalesced) { 238 if (&*InsertPos == UseMI) ++InsertPos; 239 MBB->erase(UseMI); 240 } 241} 242 243/// EmitLiveInCopies - If this is the first basic block in the function, 244/// and if it has live ins that need to be copied into vregs, emit the 245/// copies into the block. 246static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 247 const MachineRegisterInfo &MRI, 248 const TargetRegisterInfo &TRI, 249 const TargetInstrInfo &TII) { 250 if (SchedLiveInCopies) { 251 // Emit the copies at a heuristically-determined location in the block. 252 DenseMap<MachineInstr*, unsigned> CopyRegMap; 253 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 254 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 255 E = MRI.livein_end(); LI != E; ++LI) 256 if (LI->second) { 257 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 258 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 259 RC, CopyRegMap, MRI, TRI, TII); 260 } 261 } else { 262 // Emit the copies into the top of the block. 263 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 264 E = MRI.livein_end(); LI != E; ++LI) 265 if (LI->second) { 266 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 267 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 268 LI->second, LI->first, RC, RC); 269 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 270 (void) Emitted; 271 } 272 } 273} 274 275//===----------------------------------------------------------------------===// 276// SelectionDAGISel code 277//===----------------------------------------------------------------------===// 278 279SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 280 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 281 FuncInfo(new FunctionLoweringInfo(TLI)), 282 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 283 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 284 GFI(), 285 OptLevel(OL), 286 DAGSize(0) 287{} 288 289SelectionDAGISel::~SelectionDAGISel() { 290 delete SDB; 291 delete CurDAG; 292 delete FuncInfo; 293} 294 295unsigned SelectionDAGISel::MakeReg(EVT VT) { 296 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 297} 298 299void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 300 AU.addRequired<AliasAnalysis>(); 301 AU.addPreserved<AliasAnalysis>(); 302 AU.addRequired<GCModuleInfo>(); 303 AU.addPreserved<GCModuleInfo>(); 304 AU.addRequired<DwarfWriter>(); 305 AU.addPreserved<DwarfWriter>(); 306 MachineFunctionPass::getAnalysisUsage(AU); 307} 308 309bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 310 Function &Fn = *mf.getFunction(); 311 312 // Do some sanity-checking on the command-line options. 313 assert((!EnableFastISelVerbose || EnableFastISel) && 314 "-fast-isel-verbose requires -fast-isel"); 315 assert((!EnableFastISelAbort || EnableFastISel) && 316 "-fast-isel-abort requires -fast-isel"); 317 318 // Get alias analysis for load/store combining. 319 AA = &getAnalysis<AliasAnalysis>(); 320 321 MF = &mf; 322 const TargetInstrInfo &TII = *TM.getInstrInfo(); 323 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 324 325 if (Fn.hasGC()) 326 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 327 else 328 GFI = 0; 329 RegInfo = &MF->getRegInfo(); 330 DEBUG(errs() << "\n\n\n=== " << Fn.getName() << "\n"); 331 332 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 333 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 334 CurDAG->init(*MF, MMI, DW); 335 FuncInfo->set(Fn, *MF, EnableFastISel); 336 SDB->init(GFI, *AA); 337 338 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 339 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 340 // Mark landing pad. 341 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 342 343 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 344 345 // If the first basic block in the function has live ins that need to be 346 // copied into vregs, emit the copies into the top of the block before 347 // emitting the code for the block. 348 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 349 350 // Add function live-ins to entry block live-in set. 351 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 352 E = RegInfo->livein_end(); I != E; ++I) 353 MF->begin()->addLiveIn(I->first); 354 355#ifndef NDEBUG 356 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 357 "Not all catch info was assigned to a landing pad!"); 358#endif 359 360 FuncInfo->clear(); 361 362 return true; 363} 364 365static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 366 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 367 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 368 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) { 369 // Apply the catch info to DestBB. 370 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]); 371#ifndef NDEBUG 372 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 373 FLI.CatchInfoFound.insert(EHSel); 374#endif 375 } 376} 377 378void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 379 BasicBlock::iterator Begin, 380 BasicBlock::iterator End, 381 bool &HadTailCall) { 382 SDB->setCurrentBasicBlock(BB); 383 MetadataContext &TheMetadata = LLVMBB->getParent()->getContext().getMetadata(); 384 unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); 385 386 // Lower all of the non-terminator instructions. If a call is emitted 387 // as a tail call, cease emitting nodes for this block. 388 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 389 if (MDDbgKind) { 390 // Update DebugLoc if debug information is attached with this 391 // instruction. 392 if (!isa<DbgInfoIntrinsic>(I)) 393 if (MDNode *Dbg = TheMetadata.getMD(MDDbgKind, I)) { 394 DILocation DILoc(Dbg); 395 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo()); 396 SDB->setCurDebugLoc(Loc); 397 if (MF->getDefaultDebugLoc().isUnknown()) 398 MF->setDefaultDebugLoc(Loc); 399 } 400 } 401 if (!isa<TerminatorInst>(I)) 402 SDB->visit(*I); 403 } 404 405 if (!SDB->HasTailCall) { 406 // Ensure that all instructions which are used outside of their defining 407 // blocks are available as virtual registers. Invoke is handled elsewhere. 408 for (BasicBlock::iterator I = Begin; I != End; ++I) 409 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 410 SDB->CopyToExportRegsIfNeeded(I); 411 412 // Handle PHI nodes in successor blocks. 413 if (End == LLVMBB->end()) { 414 HandlePHINodesInSuccessorBlocks(LLVMBB); 415 416 // Lower the terminator after the copies are emitted. 417 SDB->visit(*LLVMBB->getTerminator()); 418 } 419 } 420 421 // Make sure the root of the DAG is up-to-date. 422 CurDAG->setRoot(SDB->getControlRoot()); 423 424 // Final step, emit the lowered DAG as machine code. 425 CodeGenAndEmitDAG(); 426 HadTailCall = SDB->HasTailCall; 427 SDB->clear(); 428} 429 430void SelectionDAGISel::ComputeLiveOutVRegInfo() { 431 SmallPtrSet<SDNode*, 128> VisitedNodes; 432 SmallVector<SDNode*, 128> Worklist; 433 434 Worklist.push_back(CurDAG->getRoot().getNode()); 435 436 APInt Mask; 437 APInt KnownZero; 438 APInt KnownOne; 439 440 while (!Worklist.empty()) { 441 SDNode *N = Worklist.back(); 442 Worklist.pop_back(); 443 444 // If we've already seen this node, ignore it. 445 if (!VisitedNodes.insert(N)) 446 continue; 447 448 // Otherwise, add all chain operands to the worklist. 449 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 450 if (N->getOperand(i).getValueType() == MVT::Other) 451 Worklist.push_back(N->getOperand(i).getNode()); 452 453 // If this is a CopyToReg with a vreg dest, process it. 454 if (N->getOpcode() != ISD::CopyToReg) 455 continue; 456 457 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 458 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 459 continue; 460 461 // Ignore non-scalar or non-integer values. 462 SDValue Src = N->getOperand(2); 463 EVT SrcVT = Src.getValueType(); 464 if (!SrcVT.isInteger() || SrcVT.isVector()) 465 continue; 466 467 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 468 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 469 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 470 471 // Only install this information if it tells us something. 472 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 473 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 474 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 475 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 476 FunctionLoweringInfo::LiveOutInfo &LOI = 477 FuncInfo->LiveOutRegInfo[DestReg]; 478 LOI.NumSignBits = NumSignBits; 479 LOI.KnownOne = KnownOne; 480 LOI.KnownZero = KnownZero; 481 } 482 } 483} 484 485void SelectionDAGISel::CodeGenAndEmitDAG() { 486 std::string GroupName; 487 if (TimePassesIsEnabled) 488 GroupName = "Instruction Selection and Scheduling"; 489 std::string BlockName; 490 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 491 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 492 ViewSUnitDAGs) 493 BlockName = MF->getFunction()->getNameStr() + ":" + 494 BB->getBasicBlock()->getNameStr(); 495 496 DEBUG(errs() << "Initial selection DAG:\n"); 497 DEBUG(CurDAG->dump()); 498 499 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 500 501 // Run the DAG combiner in pre-legalize mode. 502 if (TimePassesIsEnabled) { 503 NamedRegionTimer T("DAG Combining 1", GroupName); 504 CurDAG->Combine(Unrestricted, *AA, OptLevel); 505 } else { 506 CurDAG->Combine(Unrestricted, *AA, OptLevel); 507 } 508 509 DEBUG(errs() << "Optimized lowered selection DAG:\n"); 510 DEBUG(CurDAG->dump()); 511 512 // Second step, hack on the DAG until it only uses operations and types that 513 // the target supports. 514 if (!DisableLegalizeTypes) { 515 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 516 BlockName); 517 518 bool Changed; 519 if (TimePassesIsEnabled) { 520 NamedRegionTimer T("Type Legalization", GroupName); 521 Changed = CurDAG->LegalizeTypes(); 522 } else { 523 Changed = CurDAG->LegalizeTypes(); 524 } 525 526 DEBUG(errs() << "Type-legalized selection DAG:\n"); 527 DEBUG(CurDAG->dump()); 528 529 if (Changed) { 530 if (ViewDAGCombineLT) 531 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 532 533 // Run the DAG combiner in post-type-legalize mode. 534 if (TimePassesIsEnabled) { 535 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 536 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 537 } else { 538 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 539 } 540 541 DEBUG(errs() << "Optimized type-legalized selection DAG:\n"); 542 DEBUG(CurDAG->dump()); 543 } 544 545 if (TimePassesIsEnabled) { 546 NamedRegionTimer T("Vector Legalization", GroupName); 547 Changed = CurDAG->LegalizeVectors(); 548 } else { 549 Changed = CurDAG->LegalizeVectors(); 550 } 551 552 if (Changed) { 553 if (TimePassesIsEnabled) { 554 NamedRegionTimer T("Type Legalization 2", GroupName); 555 Changed = CurDAG->LegalizeTypes(); 556 } else { 557 Changed = CurDAG->LegalizeTypes(); 558 } 559 560 if (ViewDAGCombineLT) 561 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 562 563 // Run the DAG combiner in post-type-legalize mode. 564 if (TimePassesIsEnabled) { 565 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 566 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 567 } else { 568 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 569 } 570 571 DEBUG(errs() << "Optimized vector-legalized selection DAG:\n"); 572 DEBUG(CurDAG->dump()); 573 } 574 } 575 576 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 577 578 if (TimePassesIsEnabled) { 579 NamedRegionTimer T("DAG Legalization", GroupName); 580 CurDAG->Legalize(DisableLegalizeTypes, OptLevel); 581 } else { 582 CurDAG->Legalize(DisableLegalizeTypes, OptLevel); 583 } 584 585 DEBUG(errs() << "Legalized selection DAG:\n"); 586 DEBUG(CurDAG->dump()); 587 588 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 589 590 // Run the DAG combiner in post-legalize mode. 591 if (TimePassesIsEnabled) { 592 NamedRegionTimer T("DAG Combining 2", GroupName); 593 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 594 } else { 595 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 596 } 597 598 DEBUG(errs() << "Optimized legalized selection DAG:\n"); 599 DEBUG(CurDAG->dump()); 600 601 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 602 603 if (OptLevel != CodeGenOpt::None) 604 ComputeLiveOutVRegInfo(); 605 606 // Third, instruction select all of the operations to machine code, adding the 607 // code to the MachineBasicBlock. 608 if (TimePassesIsEnabled) { 609 NamedRegionTimer T("Instruction Selection", GroupName); 610 InstructionSelect(); 611 } else { 612 InstructionSelect(); 613 } 614 615 DEBUG(errs() << "Selected selection DAG:\n"); 616 DEBUG(CurDAG->dump()); 617 618 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 619 620 // Schedule machine code. 621 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 622 if (TimePassesIsEnabled) { 623 NamedRegionTimer T("Instruction Scheduling", GroupName); 624 Scheduler->Run(CurDAG, BB, BB->end()); 625 } else { 626 Scheduler->Run(CurDAG, BB, BB->end()); 627 } 628 629 if (ViewSUnitDAGs) Scheduler->viewGraph(); 630 631 // Emit machine code to BB. This can change 'BB' to the last block being 632 // inserted into. 633 if (TimePassesIsEnabled) { 634 NamedRegionTimer T("Instruction Creation", GroupName); 635 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 636 } else { 637 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 638 } 639 640 // Free the scheduler state. 641 if (TimePassesIsEnabled) { 642 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 643 delete Scheduler; 644 } else { 645 delete Scheduler; 646 } 647 648 DEBUG(errs() << "Selected machine code:\n"); 649 DEBUG(BB->dump()); 650} 651 652void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 653 MachineFunction &MF, 654 MachineModuleInfo *MMI, 655 DwarfWriter *DW, 656 const TargetInstrInfo &TII) { 657 // Initialize the Fast-ISel state, if needed. 658 FastISel *FastIS = 0; 659 if (EnableFastISel) 660 FastIS = TLI.createFastISel(MF, MMI, DW, 661 FuncInfo->ValueMap, 662 FuncInfo->MBBMap, 663 FuncInfo->StaticAllocaMap 664#ifndef NDEBUG 665 , FuncInfo->CatchInfoLost 666#endif 667 ); 668 669 MetadataContext &TheMetadata = Fn.getContext().getMetadata(); 670 unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); 671 672 // Iterate over all basic blocks in the function. 673 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 674 BasicBlock *LLVMBB = &*I; 675 BB = FuncInfo->MBBMap[LLVMBB]; 676 677 BasicBlock::iterator const Begin = LLVMBB->begin(); 678 BasicBlock::iterator const End = LLVMBB->end(); 679 BasicBlock::iterator BI = Begin; 680 681 // Lower any arguments needed in this block if this is the entry block. 682 bool SuppressFastISel = false; 683 if (LLVMBB == &Fn.getEntryBlock()) { 684 LowerArguments(LLVMBB); 685 686 // If any of the arguments has the byval attribute, forgo 687 // fast-isel in the entry block. 688 if (FastIS) { 689 unsigned j = 1; 690 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 691 I != E; ++I, ++j) 692 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 693 if (EnableFastISelVerbose || EnableFastISelAbort) 694 errs() << "FastISel skips entry block due to byval argument\n"; 695 SuppressFastISel = true; 696 break; 697 } 698 } 699 } 700 701 if (MMI && BB->isLandingPad()) { 702 // Add a label to mark the beginning of the landing pad. Deletion of the 703 // landing pad can thus be detected via the MachineModuleInfo. 704 unsigned LabelID = MMI->addLandingPad(BB); 705 706 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL); 707 BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID); 708 709 // Mark exception register as live in. 710 unsigned Reg = TLI.getExceptionAddressRegister(); 711 if (Reg) BB->addLiveIn(Reg); 712 713 // Mark exception selector register as live in. 714 Reg = TLI.getExceptionSelectorRegister(); 715 if (Reg) BB->addLiveIn(Reg); 716 717 // FIXME: Hack around an exception handling flaw (PR1508): the personality 718 // function and list of typeids logically belong to the invoke (or, if you 719 // like, the basic block containing the invoke), and need to be associated 720 // with it in the dwarf exception handling tables. Currently however the 721 // information is provided by an intrinsic (eh.selector) that can be moved 722 // to unexpected places by the optimizers: if the unwind edge is critical, 723 // then breaking it can result in the intrinsics being in the successor of 724 // the landing pad, not the landing pad itself. This results in exceptions 725 // not being caught because no typeids are associated with the invoke. 726 // This may not be the only way things can go wrong, but it is the only way 727 // we try to work around for the moment. 728 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 729 730 if (Br && Br->isUnconditional()) { // Critical edge? 731 BasicBlock::iterator I, E; 732 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 733 if (isa<EHSelectorInst>(I)) 734 break; 735 736 if (I == E) 737 // No catch info found - try to extract some from the successor. 738 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 739 } 740 } 741 742 // Before doing SelectionDAG ISel, see if FastISel has been requested. 743 if (FastIS && !SuppressFastISel) { 744 // Emit code for any incoming arguments. This must happen before 745 // beginning FastISel on the entry block. 746 if (LLVMBB == &Fn.getEntryBlock()) { 747 CurDAG->setRoot(SDB->getControlRoot()); 748 CodeGenAndEmitDAG(); 749 SDB->clear(); 750 } 751 FastIS->startNewBlock(BB); 752 // Do FastISel on as many instructions as possible. 753 for (; BI != End; ++BI) { 754 if (MDDbgKind) { 755 // Update DebugLoc if debug information is attached with this 756 // instruction. 757 if (!isa<DbgInfoIntrinsic>(BI)) 758 if (MDNode *Dbg = TheMetadata.getMD(MDDbgKind, BI)) { 759 DILocation DILoc(Dbg); 760 DebugLoc Loc = ExtractDebugLocation(DILoc, 761 MF.getDebugLocInfo()); 762 FastIS->setCurDebugLoc(Loc); 763 if (MF.getDefaultDebugLoc().isUnknown()) 764 MF.setDefaultDebugLoc(Loc); 765 } 766 } 767 768 // Just before the terminator instruction, insert instructions to 769 // feed PHI nodes in successor blocks. 770 if (isa<TerminatorInst>(BI)) 771 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 772 if (EnableFastISelVerbose || EnableFastISelAbort) { 773 errs() << "FastISel miss: "; 774 BI->dump(); 775 } 776 assert(!EnableFastISelAbort && 777 "FastISel didn't handle a PHI in a successor"); 778 break; 779 } 780 781 // First try normal tablegen-generated "fast" selection. 782 if (FastIS->SelectInstruction(BI)) 783 continue; 784 785 // Next, try calling the target to attempt to handle the instruction. 786 if (FastIS->TargetSelectInstruction(BI)) 787 continue; 788 789 // Then handle certain instructions as single-LLVM-Instruction blocks. 790 if (isa<CallInst>(BI)) { 791 if (EnableFastISelVerbose || EnableFastISelAbort) { 792 errs() << "FastISel missed call: "; 793 BI->dump(); 794 } 795 796 if (BI->getType() != Type::getVoidTy(*CurDAG->getContext())) { 797 unsigned &R = FuncInfo->ValueMap[BI]; 798 if (!R) 799 R = FuncInfo->CreateRegForValue(BI); 800 } 801 802 SDB->setCurDebugLoc(FastIS->getCurDebugLoc()); 803 804 bool HadTailCall = false; 805 SelectBasicBlock(LLVMBB, BI, next(BI), HadTailCall); 806 807 // If the call was emitted as a tail call, we're done with the block. 808 if (HadTailCall) { 809 BI = End; 810 break; 811 } 812 813 // If the instruction was codegen'd with multiple blocks, 814 // inform the FastISel object where to resume inserting. 815 FastIS->setCurrentBlock(BB); 816 continue; 817 } 818 819 // Otherwise, give up on FastISel for the rest of the block. 820 // For now, be a little lenient about non-branch terminators. 821 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 822 if (EnableFastISelVerbose || EnableFastISelAbort) { 823 errs() << "FastISel miss: "; 824 BI->dump(); 825 } 826 if (EnableFastISelAbort) 827 // The "fast" selector couldn't handle something and bailed. 828 // For the purpose of debugging, just abort. 829 llvm_unreachable("FastISel didn't select the entire block"); 830 } 831 break; 832 } 833 } 834 835 // Run SelectionDAG instruction selection on the remainder of the block 836 // not handled by FastISel. If FastISel is not run, this is the entire 837 // block. 838 if (BI != End) { 839 // If FastISel is run and it has known DebugLoc then use it. 840 if (FastIS && !FastIS->getCurDebugLoc().isUnknown()) 841 SDB->setCurDebugLoc(FastIS->getCurDebugLoc()); 842 bool HadTailCall; 843 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 844 } 845 846 FinishBasicBlock(); 847 } 848 849 delete FastIS; 850} 851 852void 853SelectionDAGISel::FinishBasicBlock() { 854 855 DEBUG(errs() << "Target-post-processed machine code:\n"); 856 DEBUG(BB->dump()); 857 858 DEBUG(errs() << "Total amount of phi nodes to update: " 859 << SDB->PHINodesToUpdate.size() << "\n"); 860 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 861 errs() << "Node " << i << " : (" 862 << SDB->PHINodesToUpdate[i].first 863 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 864 865 // Next, now that we know what the last MBB the LLVM BB expanded is, update 866 // PHI nodes in successors. 867 if (SDB->SwitchCases.empty() && 868 SDB->JTCases.empty() && 869 SDB->BitTestCases.empty()) { 870 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 871 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 872 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 873 "This is not a machine PHI node that we are updating!"); 874 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 875 false)); 876 PHI->addOperand(MachineOperand::CreateMBB(BB)); 877 } 878 SDB->PHINodesToUpdate.clear(); 879 return; 880 } 881 882 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 883 // Lower header first, if it wasn't already lowered 884 if (!SDB->BitTestCases[i].Emitted) { 885 // Set the current basic block to the mbb we wish to insert the code into 886 BB = SDB->BitTestCases[i].Parent; 887 SDB->setCurrentBasicBlock(BB); 888 // Emit the code 889 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 890 CurDAG->setRoot(SDB->getRoot()); 891 CodeGenAndEmitDAG(); 892 SDB->clear(); 893 } 894 895 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 896 // Set the current basic block to the mbb we wish to insert the code into 897 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 898 SDB->setCurrentBasicBlock(BB); 899 // Emit the code 900 if (j+1 != ej) 901 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 902 SDB->BitTestCases[i].Reg, 903 SDB->BitTestCases[i].Cases[j]); 904 else 905 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 906 SDB->BitTestCases[i].Reg, 907 SDB->BitTestCases[i].Cases[j]); 908 909 910 CurDAG->setRoot(SDB->getRoot()); 911 CodeGenAndEmitDAG(); 912 SDB->clear(); 913 } 914 915 // Update PHI Nodes 916 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 917 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 918 MachineBasicBlock *PHIBB = PHI->getParent(); 919 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 920 "This is not a machine PHI node that we are updating!"); 921 // This is "default" BB. We have two jumps to it. From "header" BB and 922 // from last "case" BB. 923 if (PHIBB == SDB->BitTestCases[i].Default) { 924 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, 925 false)); 926 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 927 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, 928 false)); 929 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 930 back().ThisBB)); 931 } 932 // One of "cases" BB. 933 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 934 j != ej; ++j) { 935 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 936 if (cBB->succ_end() != 937 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 938 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, 939 false)); 940 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 941 } 942 } 943 } 944 } 945 SDB->BitTestCases.clear(); 946 947 // If the JumpTable record is filled in, then we need to emit a jump table. 948 // Updating the PHI nodes is tricky in this case, since we need to determine 949 // whether the PHI is a successor of the range check MBB or the jump table MBB 950 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 951 // Lower header first, if it wasn't already lowered 952 if (!SDB->JTCases[i].first.Emitted) { 953 // Set the current basic block to the mbb we wish to insert the code into 954 BB = SDB->JTCases[i].first.HeaderBB; 955 SDB->setCurrentBasicBlock(BB); 956 // Emit the code 957 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 958 CurDAG->setRoot(SDB->getRoot()); 959 CodeGenAndEmitDAG(); 960 SDB->clear(); 961 } 962 963 // Set the current basic block to the mbb we wish to insert the code into 964 BB = SDB->JTCases[i].second.MBB; 965 SDB->setCurrentBasicBlock(BB); 966 // Emit the code 967 SDB->visitJumpTable(SDB->JTCases[i].second); 968 CurDAG->setRoot(SDB->getRoot()); 969 CodeGenAndEmitDAG(); 970 SDB->clear(); 971 972 // Update PHI Nodes 973 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 974 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 975 MachineBasicBlock *PHIBB = PHI->getParent(); 976 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 977 "This is not a machine PHI node that we are updating!"); 978 // "default" BB. We can go there only from header BB. 979 if (PHIBB == SDB->JTCases[i].second.Default) { 980 PHI->addOperand 981 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 982 PHI->addOperand 983 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 984 } 985 // JT BB. Just iterate over successors here 986 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 987 PHI->addOperand 988 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 989 PHI->addOperand(MachineOperand::CreateMBB(BB)); 990 } 991 } 992 } 993 SDB->JTCases.clear(); 994 995 // If the switch block involved a branch to one of the actual successors, we 996 // need to update PHI nodes in that block. 997 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 998 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 999 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 1000 "This is not a machine PHI node that we are updating!"); 1001 if (BB->isSuccessor(PHI->getParent())) { 1002 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1003 false)); 1004 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1005 } 1006 } 1007 1008 // If we generated any switch lowering information, build and codegen any 1009 // additional DAGs necessary. 1010 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1011 // Set the current basic block to the mbb we wish to insert the code into 1012 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1013 SDB->setCurrentBasicBlock(BB); 1014 1015 // Emit the code 1016 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1017 CurDAG->setRoot(SDB->getRoot()); 1018 CodeGenAndEmitDAG(); 1019 1020 // Handle any PHI nodes in successors of this chunk, as if we were coming 1021 // from the original BB before switch expansion. Note that PHI nodes can 1022 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1023 // handle them the right number of times. 1024 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1025 // If new BB's are created during scheduling, the edges may have been 1026 // updated. That is, the edge from ThisBB to BB may have been split and 1027 // BB's predecessor is now another block. 1028 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1029 SDB->EdgeMapping.find(BB); 1030 if (EI != SDB->EdgeMapping.end()) 1031 ThisBB = EI->second; 1032 for (MachineBasicBlock::iterator Phi = BB->begin(); 1033 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 1034 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 1035 for (unsigned pn = 0; ; ++pn) { 1036 assert(pn != SDB->PHINodesToUpdate.size() && 1037 "Didn't find PHI entry!"); 1038 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1039 Phi->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pn]. 1040 second, false)); 1041 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1042 break; 1043 } 1044 } 1045 } 1046 1047 // Don't process RHS if same block as LHS. 1048 if (BB == SDB->SwitchCases[i].FalseBB) 1049 SDB->SwitchCases[i].FalseBB = 0; 1050 1051 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1052 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1053 SDB->SwitchCases[i].FalseBB = 0; 1054 } 1055 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1056 SDB->clear(); 1057 } 1058 SDB->SwitchCases.clear(); 1059 1060 SDB->PHINodesToUpdate.clear(); 1061} 1062 1063 1064/// Create the scheduler. If a specific scheduler was specified 1065/// via the SchedulerRegistry, use it, otherwise select the 1066/// one preferred by the target. 1067/// 1068ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1069 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1070 1071 if (!Ctor) { 1072 Ctor = ISHeuristic; 1073 RegisterScheduler::setDefault(Ctor); 1074 } 1075 1076 return Ctor(this, OptLevel); 1077} 1078 1079ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1080 return new ScheduleHazardRecognizer(); 1081} 1082 1083//===----------------------------------------------------------------------===// 1084// Helper functions used by the generated instruction selector. 1085//===----------------------------------------------------------------------===// 1086// Calls to these methods are generated by tblgen. 1087 1088/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1089/// the dag combiner simplified the 255, we still want to match. RHS is the 1090/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1091/// specified in the .td file (e.g. 255). 1092bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1093 int64_t DesiredMaskS) const { 1094 const APInt &ActualMask = RHS->getAPIntValue(); 1095 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1096 1097 // If the actual mask exactly matches, success! 1098 if (ActualMask == DesiredMask) 1099 return true; 1100 1101 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1102 if (ActualMask.intersects(~DesiredMask)) 1103 return false; 1104 1105 // Otherwise, the DAG Combiner may have proven that the value coming in is 1106 // either already zero or is not demanded. Check for known zero input bits. 1107 APInt NeededMask = DesiredMask & ~ActualMask; 1108 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1109 return true; 1110 1111 // TODO: check to see if missing bits are just not demanded. 1112 1113 // Otherwise, this pattern doesn't match. 1114 return false; 1115} 1116 1117/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1118/// the dag combiner simplified the 255, we still want to match. RHS is the 1119/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1120/// specified in the .td file (e.g. 255). 1121bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1122 int64_t DesiredMaskS) const { 1123 const APInt &ActualMask = RHS->getAPIntValue(); 1124 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1125 1126 // If the actual mask exactly matches, success! 1127 if (ActualMask == DesiredMask) 1128 return true; 1129 1130 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1131 if (ActualMask.intersects(~DesiredMask)) 1132 return false; 1133 1134 // Otherwise, the DAG Combiner may have proven that the value coming in is 1135 // either already zero or is not demanded. Check for known zero input bits. 1136 APInt NeededMask = DesiredMask & ~ActualMask; 1137 1138 APInt KnownZero, KnownOne; 1139 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1140 1141 // If all the missing bits in the or are already known to be set, match! 1142 if ((NeededMask & KnownOne) == NeededMask) 1143 return true; 1144 1145 // TODO: check to see if missing bits are just not demanded. 1146 1147 // Otherwise, this pattern doesn't match. 1148 return false; 1149} 1150 1151 1152/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1153/// by tblgen. Others should not call it. 1154void SelectionDAGISel:: 1155SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1156 std::vector<SDValue> InOps; 1157 std::swap(InOps, Ops); 1158 1159 Ops.push_back(InOps[0]); // input chain. 1160 Ops.push_back(InOps[1]); // input asm string. 1161 1162 unsigned i = 2, e = InOps.size(); 1163 if (InOps[e-1].getValueType() == MVT::Flag) 1164 --e; // Don't process a flag operand if it is here. 1165 1166 while (i != e) { 1167 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1168 if ((Flags & 7) != 4 /*MEM*/) { 1169 // Just skip over this operand, copying the operands verbatim. 1170 Ops.insert(Ops.end(), InOps.begin()+i, 1171 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1172 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1173 } else { 1174 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1175 "Memory operand with multiple values?"); 1176 // Otherwise, this is a memory operand. Ask the target to select it. 1177 std::vector<SDValue> SelOps; 1178 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1179 llvm_report_error("Could not match memory address. Inline asm" 1180 " failure!"); 1181 } 1182 1183 // Add this to the output node. 1184 EVT IntPtrTy = TLI.getPointerTy(); 1185 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1186 IntPtrTy)); 1187 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1188 i += 2; 1189 } 1190 } 1191 1192 // Add the flag input back if present. 1193 if (e != InOps.size()) 1194 Ops.push_back(InOps.back()); 1195} 1196 1197/// findFlagUse - Return use of EVT::Flag value produced by the specified 1198/// SDNode. 1199/// 1200static SDNode *findFlagUse(SDNode *N) { 1201 unsigned FlagResNo = N->getNumValues()-1; 1202 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1203 SDUse &Use = I.getUse(); 1204 if (Use.getResNo() == FlagResNo) 1205 return Use.getUser(); 1206 } 1207 return NULL; 1208} 1209 1210/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1211/// This function recursively traverses up the operand chain, ignoring 1212/// certain nodes. 1213static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1214 SDNode *Root, 1215 SmallPtrSet<SDNode*, 16> &Visited) { 1216 if (Use->getNodeId() < Def->getNodeId() || 1217 !Visited.insert(Use)) 1218 return false; 1219 1220 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1221 SDNode *N = Use->getOperand(i).getNode(); 1222 if (N == Def) { 1223 if (Use == ImmedUse || Use == Root) 1224 continue; // We are not looking for immediate use. 1225 assert(N != Root); 1226 return true; 1227 } 1228 1229 // Traverse up the operand chain. 1230 if (findNonImmUse(N, Def, ImmedUse, Root, Visited)) 1231 return true; 1232 } 1233 return false; 1234} 1235 1236/// isNonImmUse - Start searching from Root up the DAG to check is Def can 1237/// be reached. Return true if that's the case. However, ignore direct uses 1238/// by ImmedUse (which would be U in the example illustrated in 1239/// IsLegalAndProfitableToFold) and by Root (which can happen in the store 1240/// case). 1241/// FIXME: to be really generic, we should allow direct use by any node 1242/// that is being folded. But realisticly since we only fold loads which 1243/// have one non-chain use, we only need to watch out for load/op/store 1244/// and load/op/cmp case where the root (store / cmp) may reach the load via 1245/// its chain operand. 1246static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) { 1247 SmallPtrSet<SDNode*, 16> Visited; 1248 return findNonImmUse(Root, Def, ImmedUse, Root, Visited); 1249} 1250 1251/// IsLegalAndProfitableToFold - Returns true if the specific operand node N of 1252/// U can be folded during instruction selection that starts at Root and 1253/// folding N is profitable. 1254bool SelectionDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U, 1255 SDNode *Root) const { 1256 if (OptLevel == CodeGenOpt::None) return false; 1257 1258 // If Root use can somehow reach N through a path that that doesn't contain 1259 // U then folding N would create a cycle. e.g. In the following 1260 // diagram, Root can reach N through X. If N is folded into into Root, then 1261 // X is both a predecessor and a successor of U. 1262 // 1263 // [N*] // 1264 // ^ ^ // 1265 // / \ // 1266 // [U*] [X]? // 1267 // ^ ^ // 1268 // \ / // 1269 // \ / // 1270 // [Root*] // 1271 // 1272 // * indicates nodes to be folded together. 1273 // 1274 // If Root produces a flag, then it gets (even more) interesting. Since it 1275 // will be "glued" together with its flag use in the scheduler, we need to 1276 // check if it might reach N. 1277 // 1278 // [N*] // 1279 // ^ ^ // 1280 // / \ // 1281 // [U*] [X]? // 1282 // ^ ^ // 1283 // \ \ // 1284 // \ | // 1285 // [Root*] | // 1286 // ^ | // 1287 // f | // 1288 // | / // 1289 // [Y] / // 1290 // ^ / // 1291 // f / // 1292 // | / // 1293 // [FU] // 1294 // 1295 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1296 // (call it Fold), then X is a predecessor of FU and a successor of 1297 // Fold. But since Fold and FU are flagged together, this will create 1298 // a cycle in the scheduling graph. 1299 1300 EVT VT = Root->getValueType(Root->getNumValues()-1); 1301 while (VT == MVT::Flag) { 1302 SDNode *FU = findFlagUse(Root); 1303 if (FU == NULL) 1304 break; 1305 Root = FU; 1306 VT = Root->getValueType(Root->getNumValues()-1); 1307 } 1308 1309 return !isNonImmUse(Root, N, U); 1310} 1311 1312SDNode *SelectionDAGISel::Select_INLINEASM(SDValue N) { 1313 std::vector<SDValue> Ops(N.getNode()->op_begin(), N.getNode()->op_end()); 1314 SelectInlineAsmMemoryOperands(Ops); 1315 1316 std::vector<EVT> VTs; 1317 VTs.push_back(MVT::Other); 1318 VTs.push_back(MVT::Flag); 1319 SDValue New = CurDAG->getNode(ISD::INLINEASM, N.getDebugLoc(), 1320 VTs, &Ops[0], Ops.size()); 1321 return New.getNode(); 1322} 1323 1324SDNode *SelectionDAGISel::Select_UNDEF(const SDValue &N) { 1325 return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::IMPLICIT_DEF, 1326 N.getValueType()); 1327} 1328 1329SDNode *SelectionDAGISel::Select_DBG_LABEL(const SDValue &N) { 1330 SDValue Chain = N.getOperand(0); 1331 unsigned C = cast<LabelSDNode>(N)->getLabelID(); 1332 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32); 1333 return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::DBG_LABEL, 1334 MVT::Other, Tmp, Chain); 1335} 1336 1337SDNode *SelectionDAGISel::Select_EH_LABEL(const SDValue &N) { 1338 SDValue Chain = N.getOperand(0); 1339 unsigned C = cast<LabelSDNode>(N)->getLabelID(); 1340 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32); 1341 return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::EH_LABEL, 1342 MVT::Other, Tmp, Chain); 1343} 1344 1345void SelectionDAGISel::CannotYetSelect(SDValue N) { 1346 std::string msg; 1347 raw_string_ostream Msg(msg); 1348 Msg << "Cannot yet select: "; 1349 N.getNode()->print(Msg, CurDAG); 1350 llvm_report_error(Msg.str()); 1351} 1352 1353void SelectionDAGISel::CannotYetSelectIntrinsic(SDValue N) { 1354 errs() << "Cannot yet select: "; 1355 unsigned iid = 1356 cast<ConstantSDNode>(N.getOperand(N.getOperand(0).getValueType() == MVT::Other))->getZExtValue(); 1357 if (iid < Intrinsic::num_intrinsics) 1358 llvm_report_error("Cannot yet select: intrinsic %" + Intrinsic::getName((Intrinsic::ID)iid)); 1359 else if (const TargetIntrinsicInfo *tii = TM.getIntrinsicInfo()) 1360 llvm_report_error(Twine("Cannot yet select: target intrinsic %") + 1361 tii->getName(iid)); 1362} 1363 1364char SelectionDAGISel::ID = 0; 1365