SelectionDAGISel.cpp revision 23a1d0c1613002073e4340deb34449a61826c93c
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/Collector.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetData.h" 40#include "llvm/Target/TargetFrameInfo.h" 41#include "llvm/Target/TargetInstrInfo.h" 42#include "llvm/Target/TargetLowering.h" 43#include "llvm/Target/TargetMachine.h" 44#include "llvm/Target/TargetOptions.h" 45#include "llvm/Support/MathExtras.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/Compiler.h" 48#include <algorithm> 49using namespace llvm; 50 51#ifndef NDEBUG 52static cl::opt<bool> 53ViewISelDAGs("view-isel-dags", cl::Hidden, 54 cl::desc("Pop up a window to show isel dags as they are selected")); 55static cl::opt<bool> 56ViewSchedDAGs("view-sched-dags", cl::Hidden, 57 cl::desc("Pop up a window to show sched dags as they are processed")); 58static cl::opt<bool> 59ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 60 cl::desc("Pop up a window to show SUnit dags after they are processed")); 61#else 62static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0; 63#endif 64 65//===---------------------------------------------------------------------===// 66/// 67/// RegisterScheduler class - Track the registration of instruction schedulers. 68/// 69//===---------------------------------------------------------------------===// 70MachinePassRegistry RegisterScheduler::Registry; 71 72//===---------------------------------------------------------------------===// 73/// 74/// ISHeuristic command line option for instruction schedulers. 75/// 76//===---------------------------------------------------------------------===// 77namespace { 78 cl::opt<RegisterScheduler::FunctionPassCtor, false, 79 RegisterPassParser<RegisterScheduler> > 80 ISHeuristic("pre-RA-sched", 81 cl::init(&createDefaultScheduler), 82 cl::desc("Instruction schedulers available (before register" 83 " allocation):")); 84 85 static RegisterScheduler 86 defaultListDAGScheduler("default", " Best scheduler for the target", 87 createDefaultScheduler); 88} // namespace 89 90namespace { struct SDISelAsmOperandInfo; } 91 92namespace { 93 /// RegsForValue - This struct represents the physical registers that a 94 /// particular value is assigned and the type information about the value. 95 /// This is needed because values can be promoted into larger registers and 96 /// expanded into multiple smaller registers than the value. 97 struct VISIBILITY_HIDDEN RegsForValue { 98 /// Regs - This list holds the register (for legal and promoted values) 99 /// or register set (for expanded values) that the value should be assigned 100 /// to. 101 std::vector<unsigned> Regs; 102 103 /// RegVT - The value type of each register. 104 /// 105 MVT::ValueType RegVT; 106 107 /// ValueVT - The value type of the LLVM value, which may be promoted from 108 /// RegVT or made from merging the two expanded parts. 109 MVT::ValueType ValueVT; 110 111 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 112 113 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 114 : RegVT(regvt), ValueVT(valuevt) { 115 Regs.push_back(Reg); 116 } 117 RegsForValue(const std::vector<unsigned> ®s, 118 MVT::ValueType regvt, MVT::ValueType valuevt) 119 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 120 } 121 122 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 123 /// this value and returns the result as a ValueVT value. This uses 124 /// Chain/Flag as the input and updates them for the output Chain/Flag. 125 /// If the Flag pointer is NULL, no flag is used. 126 SDOperand getCopyFromRegs(SelectionDAG &DAG, 127 SDOperand &Chain, SDOperand *Flag) const; 128 129 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 130 /// specified value into the registers specified by this object. This uses 131 /// Chain/Flag as the input and updates them for the output Chain/Flag. 132 /// If the Flag pointer is NULL, no flag is used. 133 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 134 SDOperand &Chain, SDOperand *Flag) const; 135 136 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 137 /// operand list. This adds the code marker and includes the number of 138 /// values added into it. 139 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 140 std::vector<SDOperand> &Ops) const; 141 }; 142} 143 144namespace llvm { 145 //===--------------------------------------------------------------------===// 146 /// createDefaultScheduler - This creates an instruction scheduler appropriate 147 /// for the target. 148 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 149 SelectionDAG *DAG, 150 MachineBasicBlock *BB) { 151 TargetLowering &TLI = IS->getTargetLowering(); 152 153 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 154 return createTDListDAGScheduler(IS, DAG, BB); 155 } else { 156 assert(TLI.getSchedulingPreference() == 157 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 158 return createBURRListDAGScheduler(IS, DAG, BB); 159 } 160 } 161 162 163 //===--------------------------------------------------------------------===// 164 /// FunctionLoweringInfo - This contains information that is global to a 165 /// function that is used when lowering a region of the function. 166 class FunctionLoweringInfo { 167 public: 168 TargetLowering &TLI; 169 Function &Fn; 170 MachineFunction &MF; 171 MachineRegisterInfo &RegInfo; 172 173 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 174 175 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 176 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 177 178 /// ValueMap - Since we emit code for the function a basic block at a time, 179 /// we must remember which virtual registers hold the values for 180 /// cross-basic-block values. 181 DenseMap<const Value*, unsigned> ValueMap; 182 183 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 184 /// the entry block. This allows the allocas to be efficiently referenced 185 /// anywhere in the function. 186 std::map<const AllocaInst*, int> StaticAllocaMap; 187 188#ifndef NDEBUG 189 SmallSet<Instruction*, 8> CatchInfoLost; 190 SmallSet<Instruction*, 8> CatchInfoFound; 191#endif 192 193 unsigned MakeReg(MVT::ValueType VT) { 194 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT)); 195 } 196 197 /// isExportedInst - Return true if the specified value is an instruction 198 /// exported from its block. 199 bool isExportedInst(const Value *V) { 200 return ValueMap.count(V); 201 } 202 203 unsigned CreateRegForValue(const Value *V); 204 205 unsigned InitializeRegForValue(const Value *V) { 206 unsigned &R = ValueMap[V]; 207 assert(R == 0 && "Already initialized this value register!"); 208 return R = CreateRegForValue(V); 209 } 210 }; 211} 212 213/// isSelector - Return true if this instruction is a call to the 214/// eh.selector intrinsic. 215static bool isSelector(Instruction *I) { 216 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 217 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 || 218 II->getIntrinsicID() == Intrinsic::eh_selector_i64); 219 return false; 220} 221 222/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 223/// PHI nodes or outside of the basic block that defines it, or used by a 224/// switch or atomic instruction, which may expand to multiple basic blocks. 225static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 226 if (isa<PHINode>(I)) return true; 227 BasicBlock *BB = I->getParent(); 228 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 229 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 230 // FIXME: Remove switchinst special case. 231 isa<SwitchInst>(*UI)) 232 return true; 233 return false; 234} 235 236/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 237/// entry block, return true. This includes arguments used by switches, since 238/// the switch may expand into multiple basic blocks. 239static bool isOnlyUsedInEntryBlock(Argument *A) { 240 BasicBlock *Entry = A->getParent()->begin(); 241 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 242 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 243 return false; // Use not in entry block. 244 return true; 245} 246 247FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 248 Function &fn, MachineFunction &mf) 249 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) { 250 251 // Create a vreg for each argument register that is not dead and is used 252 // outside of the entry block for the function. 253 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 254 AI != E; ++AI) 255 if (!isOnlyUsedInEntryBlock(AI)) 256 InitializeRegForValue(AI); 257 258 // Initialize the mapping of values to registers. This is only set up for 259 // instruction values that are used outside of the block that defines 260 // them. 261 Function::iterator BB = Fn.begin(), EB = Fn.end(); 262 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 263 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 264 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 265 const Type *Ty = AI->getAllocatedType(); 266 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 267 unsigned Align = 268 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 269 AI->getAlignment()); 270 271 TySize *= CUI->getZExtValue(); // Get total allocated size. 272 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 273 StaticAllocaMap[AI] = 274 MF.getFrameInfo()->CreateStackObject(TySize, Align); 275 } 276 277 for (; BB != EB; ++BB) 278 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 279 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 280 if (!isa<AllocaInst>(I) || 281 !StaticAllocaMap.count(cast<AllocaInst>(I))) 282 InitializeRegForValue(I); 283 284 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 285 // also creates the initial PHI MachineInstrs, though none of the input 286 // operands are populated. 287 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 288 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 289 MBBMap[BB] = MBB; 290 MF.getBasicBlockList().push_back(MBB); 291 292 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 293 // appropriate. 294 PHINode *PN; 295 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 296 if (PN->use_empty()) continue; 297 298 MVT::ValueType VT = TLI.getValueType(PN->getType()); 299 unsigned NumRegisters = TLI.getNumRegisters(VT); 300 unsigned PHIReg = ValueMap[PN]; 301 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 302 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 303 for (unsigned i = 0; i != NumRegisters; ++i) 304 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 305 } 306 } 307} 308 309/// CreateRegForValue - Allocate the appropriate number of virtual registers of 310/// the correctly promoted or expanded types. Assign these registers 311/// consecutive vreg numbers and return the first assigned number. 312unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 313 MVT::ValueType VT = TLI.getValueType(V->getType()); 314 315 unsigned NumRegisters = TLI.getNumRegisters(VT); 316 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 317 318 unsigned R = MakeReg(RegisterVT); 319 for (unsigned i = 1; i != NumRegisters; ++i) 320 MakeReg(RegisterVT); 321 322 return R; 323} 324 325//===----------------------------------------------------------------------===// 326/// SelectionDAGLowering - This is the common target-independent lowering 327/// implementation that is parameterized by a TargetLowering object. 328/// Also, targets can overload any lowering method. 329/// 330namespace llvm { 331class SelectionDAGLowering { 332 MachineBasicBlock *CurMBB; 333 334 DenseMap<const Value*, SDOperand> NodeMap; 335 336 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 337 /// them up and then emit token factor nodes when possible. This allows us to 338 /// get simple disambiguation between loads without worrying about alias 339 /// analysis. 340 std::vector<SDOperand> PendingLoads; 341 342 /// Case - A struct to record the Value for a switch case, and the 343 /// case's target basic block. 344 struct Case { 345 Constant* Low; 346 Constant* High; 347 MachineBasicBlock* BB; 348 349 Case() : Low(0), High(0), BB(0) { } 350 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 351 Low(low), High(high), BB(bb) { } 352 uint64_t size() const { 353 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 354 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 355 return (rHigh - rLow + 1ULL); 356 } 357 }; 358 359 struct CaseBits { 360 uint64_t Mask; 361 MachineBasicBlock* BB; 362 unsigned Bits; 363 364 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 365 Mask(mask), BB(bb), Bits(bits) { } 366 }; 367 368 typedef std::vector<Case> CaseVector; 369 typedef std::vector<CaseBits> CaseBitsVector; 370 typedef CaseVector::iterator CaseItr; 371 typedef std::pair<CaseItr, CaseItr> CaseRange; 372 373 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 374 /// of conditional branches. 375 struct CaseRec { 376 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 377 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 378 379 /// CaseBB - The MBB in which to emit the compare and branch 380 MachineBasicBlock *CaseBB; 381 /// LT, GE - If nonzero, we know the current case value must be less-than or 382 /// greater-than-or-equal-to these Constants. 383 Constant *LT; 384 Constant *GE; 385 /// Range - A pair of iterators representing the range of case values to be 386 /// processed at this point in the binary search tree. 387 CaseRange Range; 388 }; 389 390 typedef std::vector<CaseRec> CaseRecVector; 391 392 /// The comparison function for sorting the switch case values in the vector. 393 /// WARNING: Case ranges should be disjoint! 394 struct CaseCmp { 395 bool operator () (const Case& C1, const Case& C2) { 396 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 397 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 398 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 399 return CI1->getValue().slt(CI2->getValue()); 400 } 401 }; 402 403 struct CaseBitsCmp { 404 bool operator () (const CaseBits& C1, const CaseBits& C2) { 405 return C1.Bits > C2.Bits; 406 } 407 }; 408 409 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 410 411public: 412 // TLI - This is information that describes the available target features we 413 // need for lowering. This indicates when operations are unavailable, 414 // implemented with a libcall, etc. 415 TargetLowering &TLI; 416 SelectionDAG &DAG; 417 const TargetData *TD; 418 AliasAnalysis &AA; 419 420 /// SwitchCases - Vector of CaseBlock structures used to communicate 421 /// SwitchInst code generation information. 422 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 423 /// JTCases - Vector of JumpTable structures used to communicate 424 /// SwitchInst code generation information. 425 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 426 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 427 428 /// FuncInfo - Information about the function as a whole. 429 /// 430 FunctionLoweringInfo &FuncInfo; 431 432 /// GCI - Garbage collection metadata for the function. 433 CollectorMetadata *GCI; 434 435 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 436 AliasAnalysis &aa, 437 FunctionLoweringInfo &funcinfo, 438 CollectorMetadata *gci) 439 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa), 440 FuncInfo(funcinfo), GCI(gci) { 441 } 442 443 /// getRoot - Return the current virtual root of the Selection DAG. 444 /// 445 SDOperand getRoot() { 446 if (PendingLoads.empty()) 447 return DAG.getRoot(); 448 449 if (PendingLoads.size() == 1) { 450 SDOperand Root = PendingLoads[0]; 451 DAG.setRoot(Root); 452 PendingLoads.clear(); 453 return Root; 454 } 455 456 // Otherwise, we have to make a token factor node. 457 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 458 &PendingLoads[0], PendingLoads.size()); 459 PendingLoads.clear(); 460 DAG.setRoot(Root); 461 return Root; 462 } 463 464 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 465 466 void visit(Instruction &I) { visit(I.getOpcode(), I); } 467 468 void visit(unsigned Opcode, User &I) { 469 // Note: this doesn't use InstVisitor, because it has to work with 470 // ConstantExpr's in addition to instructions. 471 switch (Opcode) { 472 default: assert(0 && "Unknown instruction type encountered!"); 473 abort(); 474 // Build the switch statement using the Instruction.def file. 475#define HANDLE_INST(NUM, OPCODE, CLASS) \ 476 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 477#include "llvm/Instruction.def" 478 } 479 } 480 481 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 482 483 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 484 const Value *SV, SDOperand Root, 485 bool isVolatile, unsigned Alignment); 486 487 SDOperand getValue(const Value *V); 488 489 void setValue(const Value *V, SDOperand NewN) { 490 SDOperand &N = NodeMap[V]; 491 assert(N.Val == 0 && "Already set a value for this node!"); 492 N = NewN; 493 } 494 495 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber, 496 std::set<unsigned> &OutputRegs, 497 std::set<unsigned> &InputRegs); 498 499 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 500 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 501 unsigned Opc); 502 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 503 void ExportFromCurrentBlock(Value *V); 504 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall, 505 MachineBasicBlock *LandingPad = NULL); 506 507 // Terminator instructions. 508 void visitRet(ReturnInst &I); 509 void visitBr(BranchInst &I); 510 void visitSwitch(SwitchInst &I); 511 void visitUnreachable(UnreachableInst &I) { /* noop */ } 512 513 // Helpers for visitSwitch 514 bool handleSmallSwitchRange(CaseRec& CR, 515 CaseRecVector& WorkList, 516 Value* SV, 517 MachineBasicBlock* Default); 518 bool handleJTSwitchCase(CaseRec& CR, 519 CaseRecVector& WorkList, 520 Value* SV, 521 MachineBasicBlock* Default); 522 bool handleBTSplitSwitchCase(CaseRec& CR, 523 CaseRecVector& WorkList, 524 Value* SV, 525 MachineBasicBlock* Default); 526 bool handleBitTestsSwitchCase(CaseRec& CR, 527 CaseRecVector& WorkList, 528 Value* SV, 529 MachineBasicBlock* Default); 530 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 531 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 532 void visitBitTestCase(MachineBasicBlock* NextMBB, 533 unsigned Reg, 534 SelectionDAGISel::BitTestCase &B); 535 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 536 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 537 SelectionDAGISel::JumpTableHeader &JTH); 538 539 // These all get lowered before this pass. 540 void visitInvoke(InvokeInst &I); 541 void visitUnwind(UnwindInst &I); 542 543 void visitBinary(User &I, unsigned OpCode); 544 void visitShift(User &I, unsigned Opcode); 545 void visitAdd(User &I) { 546 if (I.getType()->isFPOrFPVector()) 547 visitBinary(I, ISD::FADD); 548 else 549 visitBinary(I, ISD::ADD); 550 } 551 void visitSub(User &I); 552 void visitMul(User &I) { 553 if (I.getType()->isFPOrFPVector()) 554 visitBinary(I, ISD::FMUL); 555 else 556 visitBinary(I, ISD::MUL); 557 } 558 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 559 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 560 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 561 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 562 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 563 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 564 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 565 void visitOr (User &I) { visitBinary(I, ISD::OR); } 566 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 567 void visitShl (User &I) { visitShift(I, ISD::SHL); } 568 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 569 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 570 void visitICmp(User &I); 571 void visitFCmp(User &I); 572 // Visit the conversion instructions 573 void visitTrunc(User &I); 574 void visitZExt(User &I); 575 void visitSExt(User &I); 576 void visitFPTrunc(User &I); 577 void visitFPExt(User &I); 578 void visitFPToUI(User &I); 579 void visitFPToSI(User &I); 580 void visitUIToFP(User &I); 581 void visitSIToFP(User &I); 582 void visitPtrToInt(User &I); 583 void visitIntToPtr(User &I); 584 void visitBitCast(User &I); 585 586 void visitExtractElement(User &I); 587 void visitInsertElement(User &I); 588 void visitShuffleVector(User &I); 589 590 void visitGetElementPtr(User &I); 591 void visitSelect(User &I); 592 593 void visitMalloc(MallocInst &I); 594 void visitFree(FreeInst &I); 595 void visitAlloca(AllocaInst &I); 596 void visitLoad(LoadInst &I); 597 void visitStore(StoreInst &I); 598 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 599 void visitCall(CallInst &I); 600 void visitInlineAsm(CallSite CS); 601 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 602 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 603 604 void visitVAStart(CallInst &I); 605 void visitVAArg(VAArgInst &I); 606 void visitVAEnd(CallInst &I); 607 void visitVACopy(CallInst &I); 608 609 void visitMemIntrinsic(CallInst &I, unsigned Op); 610 611 void visitGetResult(GetResultInst &I); 612 613 void visitUserOp1(Instruction &I) { 614 assert(0 && "UserOp1 should not exist at instruction selection time!"); 615 abort(); 616 } 617 void visitUserOp2(Instruction &I) { 618 assert(0 && "UserOp2 should not exist at instruction selection time!"); 619 abort(); 620 } 621}; 622} // end namespace llvm 623 624 625/// getCopyFromParts - Create a value that contains the specified legal parts 626/// combined into the value they represent. If the parts combine to a type 627/// larger then ValueVT then AssertOp can be used to specify whether the extra 628/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 629/// (ISD::AssertSext). 630static SDOperand getCopyFromParts(SelectionDAG &DAG, 631 const SDOperand *Parts, 632 unsigned NumParts, 633 MVT::ValueType PartVT, 634 MVT::ValueType ValueVT, 635 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 636 assert(NumParts > 0 && "No parts to assemble!"); 637 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 638 SDOperand Val = Parts[0]; 639 640 if (NumParts > 1) { 641 // Assemble the value from multiple parts. 642 if (!MVT::isVector(ValueVT)) { 643 unsigned PartBits = MVT::getSizeInBits(PartVT); 644 unsigned ValueBits = MVT::getSizeInBits(ValueVT); 645 646 // Assemble the power of 2 part. 647 unsigned RoundParts = NumParts & (NumParts - 1) ? 648 1 << Log2_32(NumParts) : NumParts; 649 unsigned RoundBits = PartBits * RoundParts; 650 MVT::ValueType RoundVT = RoundBits == ValueBits ? 651 ValueVT : MVT::getIntegerType(RoundBits); 652 SDOperand Lo, Hi; 653 654 if (RoundParts > 2) { 655 MVT::ValueType HalfVT = MVT::getIntegerType(RoundBits/2); 656 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT); 657 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2, 658 PartVT, HalfVT); 659 } else { 660 Lo = Parts[0]; 661 Hi = Parts[1]; 662 } 663 if (TLI.isBigEndian()) 664 std::swap(Lo, Hi); 665 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi); 666 667 if (RoundParts < NumParts) { 668 // Assemble the trailing non-power-of-2 part. 669 unsigned OddParts = NumParts - RoundParts; 670 MVT::ValueType OddVT = MVT::getIntegerType(OddParts * PartBits); 671 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT); 672 673 // Combine the round and odd parts. 674 Lo = Val; 675 if (TLI.isBigEndian()) 676 std::swap(Lo, Hi); 677 MVT::ValueType TotalVT = MVT::getIntegerType(NumParts * PartBits); 678 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi); 679 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi, 680 DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()), 681 TLI.getShiftAmountTy())); 682 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo); 683 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi); 684 } 685 } else { 686 // Handle a multi-element vector. 687 MVT::ValueType IntermediateVT, RegisterVT; 688 unsigned NumIntermediates; 689 unsigned NumRegs = 690 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 691 RegisterVT); 692 693 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 694 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 695 assert(RegisterVT == Parts[0].getValueType() && 696 "Part type doesn't match part!"); 697 698 // Assemble the parts into intermediate operands. 699 SmallVector<SDOperand, 8> Ops(NumIntermediates); 700 if (NumIntermediates == NumParts) { 701 // If the register was not expanded, truncate or copy the value, 702 // as appropriate. 703 for (unsigned i = 0; i != NumParts; ++i) 704 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 705 PartVT, IntermediateVT); 706 } else if (NumParts > 0) { 707 // If the intermediate type was expanded, build the intermediate operands 708 // from the parts. 709 assert(NumParts % NumIntermediates == 0 && 710 "Must expand into a divisible number of parts!"); 711 unsigned Factor = NumParts / NumIntermediates; 712 for (unsigned i = 0; i != NumIntermediates; ++i) 713 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 714 PartVT, IntermediateVT); 715 } 716 717 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 718 // operands. 719 Val = DAG.getNode(MVT::isVector(IntermediateVT) ? 720 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, 721 ValueVT, &Ops[0], NumIntermediates); 722 } 723 } 724 725 // There is now one part, held in Val. Correct it to match ValueVT. 726 PartVT = Val.getValueType(); 727 728 if (PartVT == ValueVT) 729 return Val; 730 731 if (MVT::isVector(PartVT)) { 732 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!"); 733 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 734 } 735 736 if (MVT::isVector(ValueVT)) { 737 assert(MVT::getVectorElementType(ValueVT) == PartVT && 738 MVT::getVectorNumElements(ValueVT) == 1 && 739 "Only trivial scalar-to-vector conversions should get here!"); 740 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val); 741 } 742 743 if (MVT::isInteger(PartVT) && 744 MVT::isInteger(ValueVT)) { 745 if (MVT::getSizeInBits(ValueVT) < MVT::getSizeInBits(PartVT)) { 746 // For a truncate, see if we have any information to 747 // indicate whether the truncated bits will always be 748 // zero or sign-extension. 749 if (AssertOp != ISD::DELETED_NODE) 750 Val = DAG.getNode(AssertOp, PartVT, Val, 751 DAG.getValueType(ValueVT)); 752 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 753 } else { 754 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 755 } 756 } 757 758 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) { 759 if (ValueVT < Val.getValueType()) 760 // FP_ROUND's are always exact here. 761 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, 762 DAG.getIntPtrConstant(1)); 763 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val); 764 } 765 766 if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT)) 767 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 768 769 assert(0 && "Unknown mismatch!"); 770} 771 772/// getCopyToParts - Create a series of nodes that contain the specified value 773/// split into legal parts. If the parts contain more bits than Val, then, for 774/// integers, ExtendKind can be used to specify how to generate the extra bits. 775static void getCopyToParts(SelectionDAG &DAG, 776 SDOperand Val, 777 SDOperand *Parts, 778 unsigned NumParts, 779 MVT::ValueType PartVT, 780 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 781 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 782 MVT::ValueType PtrVT = TLI.getPointerTy(); 783 MVT::ValueType ValueVT = Val.getValueType(); 784 unsigned PartBits = MVT::getSizeInBits(PartVT); 785 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 786 787 if (!NumParts) 788 return; 789 790 if (!MVT::isVector(ValueVT)) { 791 if (PartVT == ValueVT) { 792 assert(NumParts == 1 && "No-op copy with multiple parts!"); 793 Parts[0] = Val; 794 return; 795 } 796 797 if (NumParts * PartBits > MVT::getSizeInBits(ValueVT)) { 798 // If the parts cover more bits than the value has, promote the value. 799 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) { 800 assert(NumParts == 1 && "Do not know what to promote to!"); 801 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 802 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 803 ValueVT = MVT::getIntegerType(NumParts * PartBits); 804 Val = DAG.getNode(ExtendKind, ValueVT, Val); 805 } else { 806 assert(0 && "Unknown mismatch!"); 807 } 808 } else if (PartBits == MVT::getSizeInBits(ValueVT)) { 809 // Different types of the same size. 810 assert(NumParts == 1 && PartVT != ValueVT); 811 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 812 } else if (NumParts * PartBits < MVT::getSizeInBits(ValueVT)) { 813 // If the parts cover less bits than value has, truncate the value. 814 if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 815 ValueVT = MVT::getIntegerType(NumParts * PartBits); 816 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 817 } else { 818 assert(0 && "Unknown mismatch!"); 819 } 820 } 821 822 // The value may have changed - recompute ValueVT. 823 ValueVT = Val.getValueType(); 824 assert(NumParts * PartBits == MVT::getSizeInBits(ValueVT) && 825 "Failed to tile the value with PartVT!"); 826 827 if (NumParts == 1) { 828 assert(PartVT == ValueVT && "Type conversion failed!"); 829 Parts[0] = Val; 830 return; 831 } 832 833 // Expand the value into multiple parts. 834 if (NumParts & (NumParts - 1)) { 835 // The number of parts is not a power of 2. Split off and copy the tail. 836 assert(MVT::isInteger(PartVT) && MVT::isInteger(ValueVT) && 837 "Do not know what to expand to!"); 838 unsigned RoundParts = 1 << Log2_32(NumParts); 839 unsigned RoundBits = RoundParts * PartBits; 840 unsigned OddParts = NumParts - RoundParts; 841 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val, 842 DAG.getConstant(RoundBits, 843 TLI.getShiftAmountTy())); 844 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT); 845 if (TLI.isBigEndian()) 846 // The odd parts were reversed by getCopyToParts - unreverse them. 847 std::reverse(Parts + RoundParts, Parts + NumParts); 848 NumParts = RoundParts; 849 ValueVT = MVT::getIntegerType(NumParts * PartBits); 850 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 851 } 852 853 // The number of parts is a power of 2. Repeatedly bisect the value using 854 // EXTRACT_ELEMENT. 855 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, 856 MVT::getIntegerType(MVT::getSizeInBits(ValueVT)), 857 Val); 858 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 859 for (unsigned i = 0; i < NumParts; i += StepSize) { 860 unsigned ThisBits = StepSize * PartBits / 2; 861 MVT::ValueType ThisVT = MVT::getIntegerType (ThisBits); 862 SDOperand &Part0 = Parts[i]; 863 SDOperand &Part1 = Parts[i+StepSize/2]; 864 865 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0, 866 DAG.getConstant(1, PtrVT)); 867 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0, 868 DAG.getConstant(0, PtrVT)); 869 870 if (ThisBits == PartBits && ThisVT != PartVT) { 871 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0); 872 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1); 873 } 874 } 875 } 876 877 if (TLI.isBigEndian()) 878 std::reverse(Parts, Parts + NumParts); 879 880 return; 881 } 882 883 // Vector ValueVT. 884 if (NumParts == 1) { 885 if (PartVT != ValueVT) { 886 if (MVT::isVector(PartVT)) { 887 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 888 } else { 889 assert(MVT::getVectorElementType(ValueVT) == PartVT && 890 MVT::getVectorNumElements(ValueVT) == 1 && 891 "Only trivial vector-to-scalar conversions should get here!"); 892 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val, 893 DAG.getConstant(0, PtrVT)); 894 } 895 } 896 897 Parts[0] = Val; 898 return; 899 } 900 901 // Handle a multi-element vector. 902 MVT::ValueType IntermediateVT, RegisterVT; 903 unsigned NumIntermediates; 904 unsigned NumRegs = 905 DAG.getTargetLoweringInfo() 906 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 907 RegisterVT); 908 unsigned NumElements = MVT::getVectorNumElements(ValueVT); 909 910 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 911 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 912 913 // Split the vector into intermediate operands. 914 SmallVector<SDOperand, 8> Ops(NumIntermediates); 915 for (unsigned i = 0; i != NumIntermediates; ++i) 916 if (MVT::isVector(IntermediateVT)) 917 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 918 IntermediateVT, Val, 919 DAG.getConstant(i * (NumElements / NumIntermediates), 920 PtrVT)); 921 else 922 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 923 IntermediateVT, Val, 924 DAG.getConstant(i, PtrVT)); 925 926 // Split the intermediate operands into legal parts. 927 if (NumParts == NumIntermediates) { 928 // If the register was not expanded, promote or copy the value, 929 // as appropriate. 930 for (unsigned i = 0; i != NumParts; ++i) 931 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 932 } else if (NumParts > 0) { 933 // If the intermediate type was expanded, split each the value into 934 // legal parts. 935 assert(NumParts % NumIntermediates == 0 && 936 "Must expand into a divisible number of parts!"); 937 unsigned Factor = NumParts / NumIntermediates; 938 for (unsigned i = 0; i != NumIntermediates; ++i) 939 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 940 } 941} 942 943 944SDOperand SelectionDAGLowering::getValue(const Value *V) { 945 SDOperand &N = NodeMap[V]; 946 if (N.Val) return N; 947 948 const Type *VTy = V->getType(); 949 MVT::ValueType VT = TLI.getValueType(VTy); 950 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 951 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 952 visit(CE->getOpcode(), *CE); 953 SDOperand N1 = NodeMap[V]; 954 assert(N1.Val && "visit didn't populate the ValueMap!"); 955 return N1; 956 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 957 return N = DAG.getGlobalAddress(GV, VT); 958 } else if (isa<ConstantPointerNull>(C)) { 959 return N = DAG.getConstant(0, TLI.getPointerTy()); 960 } else if (isa<UndefValue>(C)) { 961 if (!isa<VectorType>(VTy)) 962 return N = DAG.getNode(ISD::UNDEF, VT); 963 964 // Create a BUILD_VECTOR of undef nodes. 965 const VectorType *PTy = cast<VectorType>(VTy); 966 unsigned NumElements = PTy->getNumElements(); 967 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 968 969 SmallVector<SDOperand, 8> Ops; 970 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 971 972 // Create a VConstant node with generic Vector type. 973 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 974 return N = DAG.getNode(ISD::BUILD_VECTOR, VT, 975 &Ops[0], Ops.size()); 976 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 977 return N = DAG.getConstantFP(CFP->getValueAPF(), VT); 978 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 979 unsigned NumElements = PTy->getNumElements(); 980 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 981 982 // Now that we know the number and type of the elements, push a 983 // Constant or ConstantFP node onto the ops list for each element of 984 // the vector constant. 985 SmallVector<SDOperand, 8> Ops; 986 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 987 for (unsigned i = 0; i != NumElements; ++i) 988 Ops.push_back(getValue(CP->getOperand(i))); 989 } else { 990 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 991 SDOperand Op; 992 if (MVT::isFloatingPoint(PVT)) 993 Op = DAG.getConstantFP(0, PVT); 994 else 995 Op = DAG.getConstant(0, PVT); 996 Ops.assign(NumElements, Op); 997 } 998 999 // Create a BUILD_VECTOR node. 1000 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 1001 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], 1002 Ops.size()); 1003 } else { 1004 // Canonicalize all constant ints to be unsigned. 1005 return N = DAG.getConstant(cast<ConstantInt>(C)->getValue(),VT); 1006 } 1007 } 1008 1009 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1010 std::map<const AllocaInst*, int>::iterator SI = 1011 FuncInfo.StaticAllocaMap.find(AI); 1012 if (SI != FuncInfo.StaticAllocaMap.end()) 1013 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1014 } 1015 1016 unsigned InReg = FuncInfo.ValueMap[V]; 1017 assert(InReg && "Value not in map!"); 1018 1019 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 1020 unsigned NumRegs = TLI.getNumRegisters(VT); 1021 1022 std::vector<unsigned> Regs(NumRegs); 1023 for (unsigned i = 0; i != NumRegs; ++i) 1024 Regs[i] = InReg + i; 1025 1026 RegsForValue RFV(Regs, RegisterVT, VT); 1027 SDOperand Chain = DAG.getEntryNode(); 1028 1029 return RFV.getCopyFromRegs(DAG, Chain, NULL); 1030} 1031 1032 1033void SelectionDAGLowering::visitRet(ReturnInst &I) { 1034 if (I.getNumOperands() == 0) { 1035 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 1036 return; 1037 } 1038 SmallVector<SDOperand, 8> NewValues; 1039 NewValues.push_back(getRoot()); 1040 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 1041 SDOperand RetOp = getValue(I.getOperand(i)); 1042 MVT::ValueType VT = RetOp.getValueType(); 1043 1044 // FIXME: C calling convention requires the return type to be promoted to 1045 // at least 32-bit. But this is not necessary for non-C calling conventions. 1046 if (MVT::isInteger(VT)) { 1047 MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32); 1048 if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT)) 1049 VT = MinVT; 1050 } 1051 1052 unsigned NumParts = TLI.getNumRegisters(VT); 1053 MVT::ValueType PartVT = TLI.getRegisterType(VT); 1054 SmallVector<SDOperand, 4> Parts(NumParts); 1055 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1056 1057 const Function *F = I.getParent()->getParent(); 1058 if (F->paramHasAttr(0, ParamAttr::SExt)) 1059 ExtendKind = ISD::SIGN_EXTEND; 1060 else if (F->paramHasAttr(0, ParamAttr::ZExt)) 1061 ExtendKind = ISD::ZERO_EXTEND; 1062 1063 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, ExtendKind); 1064 1065 for (unsigned i = 0; i < NumParts; ++i) { 1066 NewValues.push_back(Parts[i]); 1067 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 1068 } 1069 } 1070 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 1071 &NewValues[0], NewValues.size())); 1072} 1073 1074/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1075/// the current basic block, add it to ValueMap now so that we'll get a 1076/// CopyTo/FromReg. 1077void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 1078 // No need to export constants. 1079 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1080 1081 // Already exported? 1082 if (FuncInfo.isExportedInst(V)) return; 1083 1084 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1085 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 1086} 1087 1088bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 1089 const BasicBlock *FromBB) { 1090 // The operands of the setcc have to be in this block. We don't know 1091 // how to export them from some other block. 1092 if (Instruction *VI = dyn_cast<Instruction>(V)) { 1093 // Can export from current BB. 1094 if (VI->getParent() == FromBB) 1095 return true; 1096 1097 // Is already exported, noop. 1098 return FuncInfo.isExportedInst(V); 1099 } 1100 1101 // If this is an argument, we can export it if the BB is the entry block or 1102 // if it is already exported. 1103 if (isa<Argument>(V)) { 1104 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1105 return true; 1106 1107 // Otherwise, can only export this if it is already exported. 1108 return FuncInfo.isExportedInst(V); 1109 } 1110 1111 // Otherwise, constants can always be exported. 1112 return true; 1113} 1114 1115static bool InBlock(const Value *V, const BasicBlock *BB) { 1116 if (const Instruction *I = dyn_cast<Instruction>(V)) 1117 return I->getParent() == BB; 1118 return true; 1119} 1120 1121/// FindMergedConditions - If Cond is an expression like 1122void SelectionDAGLowering::FindMergedConditions(Value *Cond, 1123 MachineBasicBlock *TBB, 1124 MachineBasicBlock *FBB, 1125 MachineBasicBlock *CurBB, 1126 unsigned Opc) { 1127 // If this node is not part of the or/and tree, emit it as a branch. 1128 Instruction *BOp = dyn_cast<Instruction>(Cond); 1129 1130 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1131 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1132 BOp->getParent() != CurBB->getBasicBlock() || 1133 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1134 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1135 const BasicBlock *BB = CurBB->getBasicBlock(); 1136 1137 // If the leaf of the tree is a comparison, merge the condition into 1138 // the caseblock. 1139 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1140 // The operands of the cmp have to be in this block. We don't know 1141 // how to export them from some other block. If this is the first block 1142 // of the sequence, no exporting is needed. 1143 (CurBB == CurMBB || 1144 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1145 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1146 BOp = cast<Instruction>(Cond); 1147 ISD::CondCode Condition; 1148 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1149 switch (IC->getPredicate()) { 1150 default: assert(0 && "Unknown icmp predicate opcode!"); 1151 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1152 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1153 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1154 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1155 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1156 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1157 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1158 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1159 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1160 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1161 } 1162 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1163 ISD::CondCode FPC, FOC; 1164 switch (FC->getPredicate()) { 1165 default: assert(0 && "Unknown fcmp predicate opcode!"); 1166 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1167 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1168 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1169 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1170 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1171 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1172 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1173 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 1174 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 1175 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1176 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1177 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1178 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1179 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1180 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1181 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1182 } 1183 if (FiniteOnlyFPMath()) 1184 Condition = FOC; 1185 else 1186 Condition = FPC; 1187 } else { 1188 Condition = ISD::SETEQ; // silence warning. 1189 assert(0 && "Unknown compare instruction"); 1190 } 1191 1192 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1193 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1194 SwitchCases.push_back(CB); 1195 return; 1196 } 1197 1198 // Create a CaseBlock record representing this branch. 1199 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1200 NULL, TBB, FBB, CurBB); 1201 SwitchCases.push_back(CB); 1202 return; 1203 } 1204 1205 1206 // Create TmpBB after CurBB. 1207 MachineFunction::iterator BBI = CurBB; 1208 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 1209 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 1210 1211 if (Opc == Instruction::Or) { 1212 // Codegen X | Y as: 1213 // jmp_if_X TBB 1214 // jmp TmpBB 1215 // TmpBB: 1216 // jmp_if_Y TBB 1217 // jmp FBB 1218 // 1219 1220 // Emit the LHS condition. 1221 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1222 1223 // Emit the RHS condition into TmpBB. 1224 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1225 } else { 1226 assert(Opc == Instruction::And && "Unknown merge op!"); 1227 // Codegen X & Y as: 1228 // jmp_if_X TmpBB 1229 // jmp FBB 1230 // TmpBB: 1231 // jmp_if_Y TBB 1232 // jmp FBB 1233 // 1234 // This requires creation of TmpBB after CurBB. 1235 1236 // Emit the LHS condition. 1237 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1238 1239 // Emit the RHS condition into TmpBB. 1240 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1241 } 1242} 1243 1244/// If the set of cases should be emitted as a series of branches, return true. 1245/// If we should emit this as a bunch of and/or'd together conditions, return 1246/// false. 1247static bool 1248ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1249 if (Cases.size() != 2) return true; 1250 1251 // If this is two comparisons of the same values or'd or and'd together, they 1252 // will get folded into a single comparison, so don't emit two blocks. 1253 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1254 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1255 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1256 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1257 return false; 1258 } 1259 1260 return true; 1261} 1262 1263void SelectionDAGLowering::visitBr(BranchInst &I) { 1264 // Update machine-CFG edges. 1265 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1266 1267 // Figure out which block is immediately after the current one. 1268 MachineBasicBlock *NextBlock = 0; 1269 MachineFunction::iterator BBI = CurMBB; 1270 if (++BBI != CurMBB->getParent()->end()) 1271 NextBlock = BBI; 1272 1273 if (I.isUnconditional()) { 1274 // If this is not a fall-through branch, emit the branch. 1275 if (Succ0MBB != NextBlock) 1276 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1277 DAG.getBasicBlock(Succ0MBB))); 1278 1279 // Update machine-CFG edges. 1280 CurMBB->addSuccessor(Succ0MBB); 1281 return; 1282 } 1283 1284 // If this condition is one of the special cases we handle, do special stuff 1285 // now. 1286 Value *CondVal = I.getCondition(); 1287 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1288 1289 // If this is a series of conditions that are or'd or and'd together, emit 1290 // this as a sequence of branches instead of setcc's with and/or operations. 1291 // For example, instead of something like: 1292 // cmp A, B 1293 // C = seteq 1294 // cmp D, E 1295 // F = setle 1296 // or C, F 1297 // jnz foo 1298 // Emit: 1299 // cmp A, B 1300 // je foo 1301 // cmp D, E 1302 // jle foo 1303 // 1304 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1305 if (BOp->hasOneUse() && 1306 (BOp->getOpcode() == Instruction::And || 1307 BOp->getOpcode() == Instruction::Or)) { 1308 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1309 // If the compares in later blocks need to use values not currently 1310 // exported from this block, export them now. This block should always 1311 // be the first entry. 1312 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1313 1314 // Allow some cases to be rejected. 1315 if (ShouldEmitAsBranches(SwitchCases)) { 1316 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1317 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1318 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1319 } 1320 1321 // Emit the branch for this block. 1322 visitSwitchCase(SwitchCases[0]); 1323 SwitchCases.erase(SwitchCases.begin()); 1324 return; 1325 } 1326 1327 // Okay, we decided not to do this, remove any inserted MBB's and clear 1328 // SwitchCases. 1329 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1330 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1331 1332 SwitchCases.clear(); 1333 } 1334 } 1335 1336 // Create a CaseBlock record representing this branch. 1337 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1338 NULL, Succ0MBB, Succ1MBB, CurMBB); 1339 // Use visitSwitchCase to actually insert the fast branch sequence for this 1340 // cond branch. 1341 visitSwitchCase(CB); 1342} 1343 1344/// visitSwitchCase - Emits the necessary code to represent a single node in 1345/// the binary search tree resulting from lowering a switch instruction. 1346void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1347 SDOperand Cond; 1348 SDOperand CondLHS = getValue(CB.CmpLHS); 1349 1350 // Build the setcc now. 1351 if (CB.CmpMHS == NULL) { 1352 // Fold "(X == true)" to X and "(X == false)" to !X to 1353 // handle common cases produced by branch lowering. 1354 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1355 Cond = CondLHS; 1356 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1357 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1358 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1359 } else 1360 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1361 } else { 1362 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1363 1364 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1365 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1366 1367 SDOperand CmpOp = getValue(CB.CmpMHS); 1368 MVT::ValueType VT = CmpOp.getValueType(); 1369 1370 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1371 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1372 } else { 1373 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1374 Cond = DAG.getSetCC(MVT::i1, SUB, 1375 DAG.getConstant(High-Low, VT), ISD::SETULE); 1376 } 1377 1378 } 1379 1380 // Set NextBlock to be the MBB immediately after the current one, if any. 1381 // This is used to avoid emitting unnecessary branches to the next block. 1382 MachineBasicBlock *NextBlock = 0; 1383 MachineFunction::iterator BBI = CurMBB; 1384 if (++BBI != CurMBB->getParent()->end()) 1385 NextBlock = BBI; 1386 1387 // If the lhs block is the next block, invert the condition so that we can 1388 // fall through to the lhs instead of the rhs block. 1389 if (CB.TrueBB == NextBlock) { 1390 std::swap(CB.TrueBB, CB.FalseBB); 1391 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1392 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1393 } 1394 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1395 DAG.getBasicBlock(CB.TrueBB)); 1396 if (CB.FalseBB == NextBlock) 1397 DAG.setRoot(BrCond); 1398 else 1399 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1400 DAG.getBasicBlock(CB.FalseBB))); 1401 // Update successor info 1402 CurMBB->addSuccessor(CB.TrueBB); 1403 CurMBB->addSuccessor(CB.FalseBB); 1404} 1405 1406/// visitJumpTable - Emit JumpTable node in the current MBB 1407void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1408 // Emit the code for the jump table 1409 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1410 MVT::ValueType PTy = TLI.getPointerTy(); 1411 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1412 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1413 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1414 Table, Index)); 1415 return; 1416} 1417 1418/// visitJumpTableHeader - This function emits necessary code to produce index 1419/// in the JumpTable from switch case. 1420void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1421 SelectionDAGISel::JumpTableHeader &JTH) { 1422 // Subtract the lowest switch case value from the value being switched on 1423 // and conditional branch to default mbb if the result is greater than the 1424 // difference between smallest and largest cases. 1425 SDOperand SwitchOp = getValue(JTH.SValue); 1426 MVT::ValueType VT = SwitchOp.getValueType(); 1427 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1428 DAG.getConstant(JTH.First, VT)); 1429 1430 // The SDNode we just created, which holds the value being switched on 1431 // minus the the smallest case value, needs to be copied to a virtual 1432 // register so it can be used as an index into the jump table in a 1433 // subsequent basic block. This value may be smaller or larger than the 1434 // target's pointer type, and therefore require extension or truncating. 1435 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 1436 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1437 else 1438 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1439 1440 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1441 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1442 JT.Reg = JumpTableReg; 1443 1444 // Emit the range check for the jump table, and branch to the default 1445 // block for the switch statement if the value being switched on exceeds 1446 // the largest case in the switch. 1447 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB, 1448 DAG.getConstant(JTH.Last-JTH.First,VT), 1449 ISD::SETUGT); 1450 1451 // Set NextBlock to be the MBB immediately after the current one, if any. 1452 // This is used to avoid emitting unnecessary branches to the next block. 1453 MachineBasicBlock *NextBlock = 0; 1454 MachineFunction::iterator BBI = CurMBB; 1455 if (++BBI != CurMBB->getParent()->end()) 1456 NextBlock = BBI; 1457 1458 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1459 DAG.getBasicBlock(JT.Default)); 1460 1461 if (JT.MBB == NextBlock) 1462 DAG.setRoot(BrCond); 1463 else 1464 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1465 DAG.getBasicBlock(JT.MBB))); 1466 1467 return; 1468} 1469 1470/// visitBitTestHeader - This function emits necessary code to produce value 1471/// suitable for "bit tests" 1472void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1473 // Subtract the minimum value 1474 SDOperand SwitchOp = getValue(B.SValue); 1475 MVT::ValueType VT = SwitchOp.getValueType(); 1476 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1477 DAG.getConstant(B.First, VT)); 1478 1479 // Check range 1480 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB, 1481 DAG.getConstant(B.Range, VT), 1482 ISD::SETUGT); 1483 1484 SDOperand ShiftOp; 1485 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy())) 1486 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1487 else 1488 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1489 1490 // Make desired shift 1491 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1492 DAG.getConstant(1, TLI.getPointerTy()), 1493 ShiftOp); 1494 1495 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1496 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1497 B.Reg = SwitchReg; 1498 1499 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1500 DAG.getBasicBlock(B.Default)); 1501 1502 // Set NextBlock to be the MBB immediately after the current one, if any. 1503 // This is used to avoid emitting unnecessary branches to the next block. 1504 MachineBasicBlock *NextBlock = 0; 1505 MachineFunction::iterator BBI = CurMBB; 1506 if (++BBI != CurMBB->getParent()->end()) 1507 NextBlock = BBI; 1508 1509 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1510 if (MBB == NextBlock) 1511 DAG.setRoot(BrRange); 1512 else 1513 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1514 DAG.getBasicBlock(MBB))); 1515 1516 CurMBB->addSuccessor(B.Default); 1517 CurMBB->addSuccessor(MBB); 1518 1519 return; 1520} 1521 1522/// visitBitTestCase - this function produces one "bit test" 1523void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1524 unsigned Reg, 1525 SelectionDAGISel::BitTestCase &B) { 1526 // Emit bit tests and jumps 1527 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1528 1529 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1530 SwitchVal, 1531 DAG.getConstant(B.Mask, 1532 TLI.getPointerTy())); 1533 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp, 1534 DAG.getConstant(0, TLI.getPointerTy()), 1535 ISD::SETNE); 1536 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1537 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1538 1539 // Set NextBlock to be the MBB immediately after the current one, if any. 1540 // This is used to avoid emitting unnecessary branches to the next block. 1541 MachineBasicBlock *NextBlock = 0; 1542 MachineFunction::iterator BBI = CurMBB; 1543 if (++BBI != CurMBB->getParent()->end()) 1544 NextBlock = BBI; 1545 1546 if (NextMBB == NextBlock) 1547 DAG.setRoot(BrAnd); 1548 else 1549 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1550 DAG.getBasicBlock(NextMBB))); 1551 1552 CurMBB->addSuccessor(B.TargetBB); 1553 CurMBB->addSuccessor(NextMBB); 1554 1555 return; 1556} 1557 1558void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1559 // Retrieve successors. 1560 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1561 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1562 1563 if (isa<InlineAsm>(I.getCalledValue())) 1564 visitInlineAsm(&I); 1565 else 1566 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad); 1567 1568 // If the value of the invoke is used outside of its defining block, make it 1569 // available as a virtual register. 1570 if (!I.use_empty()) { 1571 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1572 if (VMI != FuncInfo.ValueMap.end()) 1573 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second)); 1574 } 1575 1576 // Drop into normal successor. 1577 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1578 DAG.getBasicBlock(Return))); 1579 1580 // Update successor info 1581 CurMBB->addSuccessor(Return); 1582 CurMBB->addSuccessor(LandingPad); 1583} 1584 1585void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1586} 1587 1588/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1589/// small case ranges). 1590bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1591 CaseRecVector& WorkList, 1592 Value* SV, 1593 MachineBasicBlock* Default) { 1594 Case& BackCase = *(CR.Range.second-1); 1595 1596 // Size is the number of Cases represented by this range. 1597 unsigned Size = CR.Range.second - CR.Range.first; 1598 if (Size > 3) 1599 return false; 1600 1601 // Get the MachineFunction which holds the current MBB. This is used when 1602 // inserting any additional MBBs necessary to represent the switch. 1603 MachineFunction *CurMF = CurMBB->getParent(); 1604 1605 // Figure out which block is immediately after the current one. 1606 MachineBasicBlock *NextBlock = 0; 1607 MachineFunction::iterator BBI = CR.CaseBB; 1608 1609 if (++BBI != CurMBB->getParent()->end()) 1610 NextBlock = BBI; 1611 1612 // TODO: If any two of the cases has the same destination, and if one value 1613 // is the same as the other, but has one bit unset that the other has set, 1614 // use bit manipulation to do two compares at once. For example: 1615 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1616 1617 // Rearrange the case blocks so that the last one falls through if possible. 1618 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1619 // The last case block won't fall through into 'NextBlock' if we emit the 1620 // branches in this order. See if rearranging a case value would help. 1621 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1622 if (I->BB == NextBlock) { 1623 std::swap(*I, BackCase); 1624 break; 1625 } 1626 } 1627 } 1628 1629 // Create a CaseBlock record representing a conditional branch to 1630 // the Case's target mbb if the value being switched on SV is equal 1631 // to C. 1632 MachineBasicBlock *CurBlock = CR.CaseBB; 1633 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1634 MachineBasicBlock *FallThrough; 1635 if (I != E-1) { 1636 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1637 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1638 } else { 1639 // If the last case doesn't match, go to the default block. 1640 FallThrough = Default; 1641 } 1642 1643 Value *RHS, *LHS, *MHS; 1644 ISD::CondCode CC; 1645 if (I->High == I->Low) { 1646 // This is just small small case range :) containing exactly 1 case 1647 CC = ISD::SETEQ; 1648 LHS = SV; RHS = I->High; MHS = NULL; 1649 } else { 1650 CC = ISD::SETLE; 1651 LHS = I->Low; MHS = SV; RHS = I->High; 1652 } 1653 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1654 I->BB, FallThrough, CurBlock); 1655 1656 // If emitting the first comparison, just call visitSwitchCase to emit the 1657 // code into the current block. Otherwise, push the CaseBlock onto the 1658 // vector to be later processed by SDISel, and insert the node's MBB 1659 // before the next MBB. 1660 if (CurBlock == CurMBB) 1661 visitSwitchCase(CB); 1662 else 1663 SwitchCases.push_back(CB); 1664 1665 CurBlock = FallThrough; 1666 } 1667 1668 return true; 1669} 1670 1671static inline bool areJTsAllowed(const TargetLowering &TLI) { 1672 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1673 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1674} 1675 1676/// handleJTSwitchCase - Emit jumptable for current switch case range 1677bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1678 CaseRecVector& WorkList, 1679 Value* SV, 1680 MachineBasicBlock* Default) { 1681 Case& FrontCase = *CR.Range.first; 1682 Case& BackCase = *(CR.Range.second-1); 1683 1684 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1685 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1686 1687 uint64_t TSize = 0; 1688 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1689 I!=E; ++I) 1690 TSize += I->size(); 1691 1692 if (!areJTsAllowed(TLI) || TSize <= 3) 1693 return false; 1694 1695 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1696 if (Density < 0.4) 1697 return false; 1698 1699 DOUT << "Lowering jump table\n" 1700 << "First entry: " << First << ". Last entry: " << Last << "\n" 1701 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1702 1703 // Get the MachineFunction which holds the current MBB. This is used when 1704 // inserting any additional MBBs necessary to represent the switch. 1705 MachineFunction *CurMF = CurMBB->getParent(); 1706 1707 // Figure out which block is immediately after the current one. 1708 MachineBasicBlock *NextBlock = 0; 1709 MachineFunction::iterator BBI = CR.CaseBB; 1710 1711 if (++BBI != CurMBB->getParent()->end()) 1712 NextBlock = BBI; 1713 1714 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1715 1716 // Create a new basic block to hold the code for loading the address 1717 // of the jump table, and jumping to it. Update successor information; 1718 // we will either branch to the default case for the switch, or the jump 1719 // table. 1720 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1721 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1722 CR.CaseBB->addSuccessor(Default); 1723 CR.CaseBB->addSuccessor(JumpTableBB); 1724 1725 // Build a vector of destination BBs, corresponding to each target 1726 // of the jump table. If the value of the jump table slot corresponds to 1727 // a case statement, push the case's BB onto the vector, otherwise, push 1728 // the default BB. 1729 std::vector<MachineBasicBlock*> DestBBs; 1730 int64_t TEI = First; 1731 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1732 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1733 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1734 1735 if ((Low <= TEI) && (TEI <= High)) { 1736 DestBBs.push_back(I->BB); 1737 if (TEI==High) 1738 ++I; 1739 } else { 1740 DestBBs.push_back(Default); 1741 } 1742 } 1743 1744 // Update successor info. Add one edge to each unique successor. 1745 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1746 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1747 E = DestBBs.end(); I != E; ++I) { 1748 if (!SuccsHandled[(*I)->getNumber()]) { 1749 SuccsHandled[(*I)->getNumber()] = true; 1750 JumpTableBB->addSuccessor(*I); 1751 } 1752 } 1753 1754 // Create a jump table index for this jump table, or return an existing 1755 // one. 1756 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1757 1758 // Set the jump table information so that we can codegen it as a second 1759 // MachineBasicBlock 1760 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1761 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1762 (CR.CaseBB == CurMBB)); 1763 if (CR.CaseBB == CurMBB) 1764 visitJumpTableHeader(JT, JTH); 1765 1766 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1767 1768 return true; 1769} 1770 1771/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1772/// 2 subtrees. 1773bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1774 CaseRecVector& WorkList, 1775 Value* SV, 1776 MachineBasicBlock* Default) { 1777 // Get the MachineFunction which holds the current MBB. This is used when 1778 // inserting any additional MBBs necessary to represent the switch. 1779 MachineFunction *CurMF = CurMBB->getParent(); 1780 1781 // Figure out which block is immediately after the current one. 1782 MachineBasicBlock *NextBlock = 0; 1783 MachineFunction::iterator BBI = CR.CaseBB; 1784 1785 if (++BBI != CurMBB->getParent()->end()) 1786 NextBlock = BBI; 1787 1788 Case& FrontCase = *CR.Range.first; 1789 Case& BackCase = *(CR.Range.second-1); 1790 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1791 1792 // Size is the number of Cases represented by this range. 1793 unsigned Size = CR.Range.second - CR.Range.first; 1794 1795 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1796 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1797 double FMetric = 0; 1798 CaseItr Pivot = CR.Range.first + Size/2; 1799 1800 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1801 // (heuristically) allow us to emit JumpTable's later. 1802 uint64_t TSize = 0; 1803 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1804 I!=E; ++I) 1805 TSize += I->size(); 1806 1807 uint64_t LSize = FrontCase.size(); 1808 uint64_t RSize = TSize-LSize; 1809 DOUT << "Selecting best pivot: \n" 1810 << "First: " << First << ", Last: " << Last <<"\n" 1811 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1812 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1813 J!=E; ++I, ++J) { 1814 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1815 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1816 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1817 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1818 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1819 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1820 // Should always split in some non-trivial place 1821 DOUT <<"=>Step\n" 1822 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1823 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1824 << "Metric: " << Metric << "\n"; 1825 if (FMetric < Metric) { 1826 Pivot = J; 1827 FMetric = Metric; 1828 DOUT << "Current metric set to: " << FMetric << "\n"; 1829 } 1830 1831 LSize += J->size(); 1832 RSize -= J->size(); 1833 } 1834 if (areJTsAllowed(TLI)) { 1835 // If our case is dense we *really* should handle it earlier! 1836 assert((FMetric > 0) && "Should handle dense range earlier!"); 1837 } else { 1838 Pivot = CR.Range.first + Size/2; 1839 } 1840 1841 CaseRange LHSR(CR.Range.first, Pivot); 1842 CaseRange RHSR(Pivot, CR.Range.second); 1843 Constant *C = Pivot->Low; 1844 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1845 1846 // We know that we branch to the LHS if the Value being switched on is 1847 // less than the Pivot value, C. We use this to optimize our binary 1848 // tree a bit, by recognizing that if SV is greater than or equal to the 1849 // LHS's Case Value, and that Case Value is exactly one less than the 1850 // Pivot's Value, then we can branch directly to the LHS's Target, 1851 // rather than creating a leaf node for it. 1852 if ((LHSR.second - LHSR.first) == 1 && 1853 LHSR.first->High == CR.GE && 1854 cast<ConstantInt>(C)->getSExtValue() == 1855 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1856 TrueBB = LHSR.first->BB; 1857 } else { 1858 TrueBB = new MachineBasicBlock(LLVMBB); 1859 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1860 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1861 } 1862 1863 // Similar to the optimization above, if the Value being switched on is 1864 // known to be less than the Constant CR.LT, and the current Case Value 1865 // is CR.LT - 1, then we can branch directly to the target block for 1866 // the current Case Value, rather than emitting a RHS leaf node for it. 1867 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1868 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1869 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1870 FalseBB = RHSR.first->BB; 1871 } else { 1872 FalseBB = new MachineBasicBlock(LLVMBB); 1873 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1874 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1875 } 1876 1877 // Create a CaseBlock record representing a conditional branch to 1878 // the LHS node if the value being switched on SV is less than C. 1879 // Otherwise, branch to LHS. 1880 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1881 TrueBB, FalseBB, CR.CaseBB); 1882 1883 if (CR.CaseBB == CurMBB) 1884 visitSwitchCase(CB); 1885 else 1886 SwitchCases.push_back(CB); 1887 1888 return true; 1889} 1890 1891/// handleBitTestsSwitchCase - if current case range has few destination and 1892/// range span less, than machine word bitwidth, encode case range into series 1893/// of masks and emit bit tests with these masks. 1894bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1895 CaseRecVector& WorkList, 1896 Value* SV, 1897 MachineBasicBlock* Default){ 1898 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); 1899 1900 Case& FrontCase = *CR.Range.first; 1901 Case& BackCase = *(CR.Range.second-1); 1902 1903 // Get the MachineFunction which holds the current MBB. This is used when 1904 // inserting any additional MBBs necessary to represent the switch. 1905 MachineFunction *CurMF = CurMBB->getParent(); 1906 1907 unsigned numCmps = 0; 1908 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1909 I!=E; ++I) { 1910 // Single case counts one, case range - two. 1911 if (I->Low == I->High) 1912 numCmps +=1; 1913 else 1914 numCmps +=2; 1915 } 1916 1917 // Count unique destinations 1918 SmallSet<MachineBasicBlock*, 4> Dests; 1919 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1920 Dests.insert(I->BB); 1921 if (Dests.size() > 3) 1922 // Don't bother the code below, if there are too much unique destinations 1923 return false; 1924 } 1925 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1926 << "Total number of comparisons: " << numCmps << "\n"; 1927 1928 // Compute span of values. 1929 Constant* minValue = FrontCase.Low; 1930 Constant* maxValue = BackCase.High; 1931 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1932 cast<ConstantInt>(minValue)->getSExtValue(); 1933 DOUT << "Compare range: " << range << "\n" 1934 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1935 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1936 1937 if (range>=IntPtrBits || 1938 (!(Dests.size() == 1 && numCmps >= 3) && 1939 !(Dests.size() == 2 && numCmps >= 5) && 1940 !(Dests.size() >= 3 && numCmps >= 6))) 1941 return false; 1942 1943 DOUT << "Emitting bit tests\n"; 1944 int64_t lowBound = 0; 1945 1946 // Optimize the case where all the case values fit in a 1947 // word without having to subtract minValue. In this case, 1948 // we can optimize away the subtraction. 1949 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1950 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1951 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1952 } else { 1953 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1954 } 1955 1956 CaseBitsVector CasesBits; 1957 unsigned i, count = 0; 1958 1959 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1960 MachineBasicBlock* Dest = I->BB; 1961 for (i = 0; i < count; ++i) 1962 if (Dest == CasesBits[i].BB) 1963 break; 1964 1965 if (i == count) { 1966 assert((count < 3) && "Too much destinations to test!"); 1967 CasesBits.push_back(CaseBits(0, Dest, 0)); 1968 count++; 1969 } 1970 1971 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1972 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1973 1974 for (uint64_t j = lo; j <= hi; j++) { 1975 CasesBits[i].Mask |= 1ULL << j; 1976 CasesBits[i].Bits++; 1977 } 1978 1979 } 1980 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1981 1982 SelectionDAGISel::BitTestInfo BTC; 1983 1984 // Figure out which block is immediately after the current one. 1985 MachineFunction::iterator BBI = CR.CaseBB; 1986 ++BBI; 1987 1988 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1989 1990 DOUT << "Cases:\n"; 1991 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1992 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1993 << ", BB: " << CasesBits[i].BB << "\n"; 1994 1995 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1996 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1997 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1998 CaseBB, 1999 CasesBits[i].BB)); 2000 } 2001 2002 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 2003 -1U, (CR.CaseBB == CurMBB), 2004 CR.CaseBB, Default, BTC); 2005 2006 if (CR.CaseBB == CurMBB) 2007 visitBitTestHeader(BTB); 2008 2009 BitTestCases.push_back(BTB); 2010 2011 return true; 2012} 2013 2014 2015// Clusterify - Transform simple list of Cases into list of CaseRange's 2016unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 2017 const SwitchInst& SI) { 2018 unsigned numCmps = 0; 2019 2020 // Start with "simple" cases 2021 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 2022 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2023 Cases.push_back(Case(SI.getSuccessorValue(i), 2024 SI.getSuccessorValue(i), 2025 SMBB)); 2026 } 2027 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2028 2029 // Merge case into clusters 2030 if (Cases.size()>=2) 2031 // Must recompute end() each iteration because it may be 2032 // invalidated by erase if we hold on to it 2033 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 2034 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 2035 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 2036 MachineBasicBlock* nextBB = J->BB; 2037 MachineBasicBlock* currentBB = I->BB; 2038 2039 // If the two neighboring cases go to the same destination, merge them 2040 // into a single case. 2041 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 2042 I->High = J->High; 2043 J = Cases.erase(J); 2044 } else { 2045 I = J++; 2046 } 2047 } 2048 2049 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2050 if (I->Low != I->High) 2051 // A range counts double, since it requires two compares. 2052 ++numCmps; 2053 } 2054 2055 return numCmps; 2056} 2057 2058void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 2059 // Figure out which block is immediately after the current one. 2060 MachineBasicBlock *NextBlock = 0; 2061 MachineFunction::iterator BBI = CurMBB; 2062 2063 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2064 2065 // If there is only the default destination, branch to it if it is not the 2066 // next basic block. Otherwise, just fall through. 2067 if (SI.getNumOperands() == 2) { 2068 // Update machine-CFG edges. 2069 2070 // If this is not a fall-through branch, emit the branch. 2071 if (Default != NextBlock) 2072 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 2073 DAG.getBasicBlock(Default))); 2074 2075 CurMBB->addSuccessor(Default); 2076 return; 2077 } 2078 2079 // If there are any non-default case statements, create a vector of Cases 2080 // representing each one, and sort the vector so that we can efficiently 2081 // create a binary search tree from them. 2082 CaseVector Cases; 2083 unsigned numCmps = Clusterify(Cases, SI); 2084 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 2085 << ". Total compares: " << numCmps << "\n"; 2086 2087 // Get the Value to be switched on and default basic blocks, which will be 2088 // inserted into CaseBlock records, representing basic blocks in the binary 2089 // search tree. 2090 Value *SV = SI.getOperand(0); 2091 2092 // Push the initial CaseRec onto the worklist 2093 CaseRecVector WorkList; 2094 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 2095 2096 while (!WorkList.empty()) { 2097 // Grab a record representing a case range to process off the worklist 2098 CaseRec CR = WorkList.back(); 2099 WorkList.pop_back(); 2100 2101 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 2102 continue; 2103 2104 // If the range has few cases (two or less) emit a series of specific 2105 // tests. 2106 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 2107 continue; 2108 2109 // If the switch has more than 5 blocks, and at least 40% dense, and the 2110 // target supports indirect branches, then emit a jump table rather than 2111 // lowering the switch to a binary tree of conditional branches. 2112 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 2113 continue; 2114 2115 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2116 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2117 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 2118 } 2119} 2120 2121 2122void SelectionDAGLowering::visitSub(User &I) { 2123 // -0.0 - X --> fneg 2124 const Type *Ty = I.getType(); 2125 if (isa<VectorType>(Ty)) { 2126 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2127 const VectorType *DestTy = cast<VectorType>(I.getType()); 2128 const Type *ElTy = DestTy->getElementType(); 2129 if (ElTy->isFloatingPoint()) { 2130 unsigned VL = DestTy->getNumElements(); 2131 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2132 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2133 if (CV == CNZ) { 2134 SDOperand Op2 = getValue(I.getOperand(1)); 2135 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2136 return; 2137 } 2138 } 2139 } 2140 } 2141 if (Ty->isFloatingPoint()) { 2142 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2143 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2144 SDOperand Op2 = getValue(I.getOperand(1)); 2145 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2146 return; 2147 } 2148 } 2149 2150 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2151} 2152 2153void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2154 SDOperand Op1 = getValue(I.getOperand(0)); 2155 SDOperand Op2 = getValue(I.getOperand(1)); 2156 2157 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2158} 2159 2160void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2161 SDOperand Op1 = getValue(I.getOperand(0)); 2162 SDOperand Op2 = getValue(I.getOperand(1)); 2163 2164 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) < 2165 MVT::getSizeInBits(Op2.getValueType())) 2166 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2167 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 2168 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2169 2170 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2171} 2172 2173void SelectionDAGLowering::visitICmp(User &I) { 2174 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2175 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2176 predicate = IC->getPredicate(); 2177 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2178 predicate = ICmpInst::Predicate(IC->getPredicate()); 2179 SDOperand Op1 = getValue(I.getOperand(0)); 2180 SDOperand Op2 = getValue(I.getOperand(1)); 2181 ISD::CondCode Opcode; 2182 switch (predicate) { 2183 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2184 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2185 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2186 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2187 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2188 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2189 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2190 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2191 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2192 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2193 default: 2194 assert(!"Invalid ICmp predicate value"); 2195 Opcode = ISD::SETEQ; 2196 break; 2197 } 2198 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2199} 2200 2201void SelectionDAGLowering::visitFCmp(User &I) { 2202 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2203 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2204 predicate = FC->getPredicate(); 2205 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2206 predicate = FCmpInst::Predicate(FC->getPredicate()); 2207 SDOperand Op1 = getValue(I.getOperand(0)); 2208 SDOperand Op2 = getValue(I.getOperand(1)); 2209 ISD::CondCode Condition, FOC, FPC; 2210 switch (predicate) { 2211 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2212 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2213 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2214 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2215 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2216 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2217 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2218 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 2219 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 2220 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2221 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2222 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2223 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2224 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2225 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2226 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2227 default: 2228 assert(!"Invalid FCmp predicate value"); 2229 FOC = FPC = ISD::SETFALSE; 2230 break; 2231 } 2232 if (FiniteOnlyFPMath()) 2233 Condition = FOC; 2234 else 2235 Condition = FPC; 2236 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2237} 2238 2239void SelectionDAGLowering::visitSelect(User &I) { 2240 SDOperand Cond = getValue(I.getOperand(0)); 2241 SDOperand TrueVal = getValue(I.getOperand(1)); 2242 SDOperand FalseVal = getValue(I.getOperand(2)); 2243 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2244 TrueVal, FalseVal)); 2245} 2246 2247 2248void SelectionDAGLowering::visitTrunc(User &I) { 2249 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2250 SDOperand N = getValue(I.getOperand(0)); 2251 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2252 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2253} 2254 2255void SelectionDAGLowering::visitZExt(User &I) { 2256 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2257 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2258 SDOperand N = getValue(I.getOperand(0)); 2259 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2260 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2261} 2262 2263void SelectionDAGLowering::visitSExt(User &I) { 2264 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2265 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2266 SDOperand N = getValue(I.getOperand(0)); 2267 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2268 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2269} 2270 2271void SelectionDAGLowering::visitFPTrunc(User &I) { 2272 // FPTrunc is never a no-op cast, no need to check 2273 SDOperand N = getValue(I.getOperand(0)); 2274 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2275 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0))); 2276} 2277 2278void SelectionDAGLowering::visitFPExt(User &I){ 2279 // FPTrunc is never a no-op cast, no need to check 2280 SDOperand N = getValue(I.getOperand(0)); 2281 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2282 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2283} 2284 2285void SelectionDAGLowering::visitFPToUI(User &I) { 2286 // FPToUI is never a no-op cast, no need to check 2287 SDOperand N = getValue(I.getOperand(0)); 2288 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2289 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2290} 2291 2292void SelectionDAGLowering::visitFPToSI(User &I) { 2293 // FPToSI is never a no-op cast, no need to check 2294 SDOperand N = getValue(I.getOperand(0)); 2295 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2296 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2297} 2298 2299void SelectionDAGLowering::visitUIToFP(User &I) { 2300 // UIToFP is never a no-op cast, no need to check 2301 SDOperand N = getValue(I.getOperand(0)); 2302 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2303 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2304} 2305 2306void SelectionDAGLowering::visitSIToFP(User &I){ 2307 // UIToFP is never a no-op cast, no need to check 2308 SDOperand N = getValue(I.getOperand(0)); 2309 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2310 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2311} 2312 2313void SelectionDAGLowering::visitPtrToInt(User &I) { 2314 // What to do depends on the size of the integer and the size of the pointer. 2315 // We can either truncate, zero extend, or no-op, accordingly. 2316 SDOperand N = getValue(I.getOperand(0)); 2317 MVT::ValueType SrcVT = N.getValueType(); 2318 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2319 SDOperand Result; 2320 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2321 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2322 else 2323 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2324 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2325 setValue(&I, Result); 2326} 2327 2328void SelectionDAGLowering::visitIntToPtr(User &I) { 2329 // What to do depends on the size of the integer and the size of the pointer. 2330 // We can either truncate, zero extend, or no-op, accordingly. 2331 SDOperand N = getValue(I.getOperand(0)); 2332 MVT::ValueType SrcVT = N.getValueType(); 2333 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2334 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2335 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2336 else 2337 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2338 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2339} 2340 2341void SelectionDAGLowering::visitBitCast(User &I) { 2342 SDOperand N = getValue(I.getOperand(0)); 2343 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2344 2345 // BitCast assures us that source and destination are the same size so this 2346 // is either a BIT_CONVERT or a no-op. 2347 if (DestVT != N.getValueType()) 2348 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2349 else 2350 setValue(&I, N); // noop cast. 2351} 2352 2353void SelectionDAGLowering::visitInsertElement(User &I) { 2354 SDOperand InVec = getValue(I.getOperand(0)); 2355 SDOperand InVal = getValue(I.getOperand(1)); 2356 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2357 getValue(I.getOperand(2))); 2358 2359 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2360 TLI.getValueType(I.getType()), 2361 InVec, InVal, InIdx)); 2362} 2363 2364void SelectionDAGLowering::visitExtractElement(User &I) { 2365 SDOperand InVec = getValue(I.getOperand(0)); 2366 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2367 getValue(I.getOperand(1))); 2368 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2369 TLI.getValueType(I.getType()), InVec, InIdx)); 2370} 2371 2372void SelectionDAGLowering::visitShuffleVector(User &I) { 2373 SDOperand V1 = getValue(I.getOperand(0)); 2374 SDOperand V2 = getValue(I.getOperand(1)); 2375 SDOperand Mask = getValue(I.getOperand(2)); 2376 2377 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2378 TLI.getValueType(I.getType()), 2379 V1, V2, Mask)); 2380} 2381 2382 2383void SelectionDAGLowering::visitGetElementPtr(User &I) { 2384 SDOperand N = getValue(I.getOperand(0)); 2385 const Type *Ty = I.getOperand(0)->getType(); 2386 2387 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2388 OI != E; ++OI) { 2389 Value *Idx = *OI; 2390 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2391 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2392 if (Field) { 2393 // N = N + Offset 2394 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2395 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2396 DAG.getIntPtrConstant(Offset)); 2397 } 2398 Ty = StTy->getElementType(Field); 2399 } else { 2400 Ty = cast<SequentialType>(Ty)->getElementType(); 2401 2402 // If this is a constant subscript, handle it quickly. 2403 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2404 if (CI->getZExtValue() == 0) continue; 2405 uint64_t Offs = 2406 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2407 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2408 DAG.getIntPtrConstant(Offs)); 2409 continue; 2410 } 2411 2412 // N = N + Idx * ElementSize; 2413 uint64_t ElementSize = TD->getABITypeSize(Ty); 2414 SDOperand IdxN = getValue(Idx); 2415 2416 // If the index is smaller or larger than intptr_t, truncate or extend 2417 // it. 2418 if (IdxN.getValueType() < N.getValueType()) { 2419 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2420 } else if (IdxN.getValueType() > N.getValueType()) 2421 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2422 2423 // If this is a multiply by a power of two, turn it into a shl 2424 // immediately. This is a very common case. 2425 if (isPowerOf2_64(ElementSize)) { 2426 unsigned Amt = Log2_64(ElementSize); 2427 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2428 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2429 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2430 continue; 2431 } 2432 2433 SDOperand Scale = DAG.getIntPtrConstant(ElementSize); 2434 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2435 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2436 } 2437 } 2438 setValue(&I, N); 2439} 2440 2441void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2442 // If this is a fixed sized alloca in the entry block of the function, 2443 // allocate it statically on the stack. 2444 if (FuncInfo.StaticAllocaMap.count(&I)) 2445 return; // getValue will auto-populate this. 2446 2447 const Type *Ty = I.getAllocatedType(); 2448 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 2449 unsigned Align = 2450 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2451 I.getAlignment()); 2452 2453 SDOperand AllocSize = getValue(I.getArraySize()); 2454 MVT::ValueType IntPtr = TLI.getPointerTy(); 2455 if (IntPtr < AllocSize.getValueType()) 2456 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2457 else if (IntPtr > AllocSize.getValueType()) 2458 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2459 2460 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2461 DAG.getIntPtrConstant(TySize)); 2462 2463 // Handle alignment. If the requested alignment is less than or equal to 2464 // the stack alignment, ignore it. If the size is greater than or equal to 2465 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2466 unsigned StackAlign = 2467 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2468 if (Align <= StackAlign) 2469 Align = 0; 2470 2471 // Round the size of the allocation up to the stack alignment size 2472 // by add SA-1 to the size. 2473 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2474 DAG.getIntPtrConstant(StackAlign-1)); 2475 // Mask out the low bits for alignment purposes. 2476 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2477 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2478 2479 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2480 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2481 MVT::Other); 2482 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2483 setValue(&I, DSA); 2484 DAG.setRoot(DSA.getValue(1)); 2485 2486 // Inform the Frame Information that we have just allocated a variable-sized 2487 // object. 2488 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2489} 2490 2491void SelectionDAGLowering::visitLoad(LoadInst &I) { 2492 SDOperand Ptr = getValue(I.getOperand(0)); 2493 2494 SDOperand Root; 2495 if (I.isVolatile()) 2496 Root = getRoot(); 2497 else { 2498 // Do not serialize non-volatile loads against each other. 2499 Root = DAG.getRoot(); 2500 } 2501 2502 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2503 Root, I.isVolatile(), I.getAlignment())); 2504} 2505 2506SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2507 const Value *SV, SDOperand Root, 2508 bool isVolatile, 2509 unsigned Alignment) { 2510 SDOperand L = 2511 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2512 isVolatile, Alignment); 2513 2514 if (isVolatile) 2515 DAG.setRoot(L.getValue(1)); 2516 else 2517 PendingLoads.push_back(L.getValue(1)); 2518 2519 return L; 2520} 2521 2522 2523void SelectionDAGLowering::visitStore(StoreInst &I) { 2524 Value *SrcV = I.getOperand(0); 2525 SDOperand Src = getValue(SrcV); 2526 SDOperand Ptr = getValue(I.getOperand(1)); 2527 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2528 I.isVolatile(), I.getAlignment())); 2529} 2530 2531/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2532/// node. 2533void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2534 unsigned Intrinsic) { 2535 bool HasChain = !I.doesNotAccessMemory(); 2536 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 2537 2538 // Build the operand list. 2539 SmallVector<SDOperand, 8> Ops; 2540 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2541 if (OnlyLoad) { 2542 // We don't need to serialize loads against other loads. 2543 Ops.push_back(DAG.getRoot()); 2544 } else { 2545 Ops.push_back(getRoot()); 2546 } 2547 } 2548 2549 // Add the intrinsic ID as an integer operand. 2550 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2551 2552 // Add all operands of the call to the operand list. 2553 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2554 SDOperand Op = getValue(I.getOperand(i)); 2555 assert(TLI.isTypeLegal(Op.getValueType()) && 2556 "Intrinsic uses a non-legal type?"); 2557 Ops.push_back(Op); 2558 } 2559 2560 std::vector<MVT::ValueType> VTs; 2561 if (I.getType() != Type::VoidTy) { 2562 MVT::ValueType VT = TLI.getValueType(I.getType()); 2563 if (MVT::isVector(VT)) { 2564 const VectorType *DestTy = cast<VectorType>(I.getType()); 2565 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2566 2567 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2568 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2569 } 2570 2571 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2572 VTs.push_back(VT); 2573 } 2574 if (HasChain) 2575 VTs.push_back(MVT::Other); 2576 2577 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2578 2579 // Create the node. 2580 SDOperand Result; 2581 if (!HasChain) 2582 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2583 &Ops[0], Ops.size()); 2584 else if (I.getType() != Type::VoidTy) 2585 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2586 &Ops[0], Ops.size()); 2587 else 2588 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2589 &Ops[0], Ops.size()); 2590 2591 if (HasChain) { 2592 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2593 if (OnlyLoad) 2594 PendingLoads.push_back(Chain); 2595 else 2596 DAG.setRoot(Chain); 2597 } 2598 if (I.getType() != Type::VoidTy) { 2599 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2600 MVT::ValueType VT = TLI.getValueType(PTy); 2601 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 2602 } 2603 setValue(&I, Result); 2604 } 2605} 2606 2607/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 2608static GlobalVariable *ExtractTypeInfo (Value *V) { 2609 V = IntrinsicInst::StripPointerCasts(V); 2610 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 2611 assert ((GV || isa<ConstantPointerNull>(V)) && 2612 "TypeInfo must be a global variable or NULL"); 2613 return GV; 2614} 2615 2616/// addCatchInfo - Extract the personality and type infos from an eh.selector 2617/// call, and add them to the specified machine basic block. 2618static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 2619 MachineBasicBlock *MBB) { 2620 // Inform the MachineModuleInfo of the personality for this landing pad. 2621 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 2622 assert(CE->getOpcode() == Instruction::BitCast && 2623 isa<Function>(CE->getOperand(0)) && 2624 "Personality should be a function"); 2625 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 2626 2627 // Gather all the type infos for this landing pad and pass them along to 2628 // MachineModuleInfo. 2629 std::vector<GlobalVariable *> TyInfo; 2630 unsigned N = I.getNumOperands(); 2631 2632 for (unsigned i = N - 1; i > 2; --i) { 2633 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 2634 unsigned FilterLength = CI->getZExtValue(); 2635 unsigned FirstCatch = i + FilterLength + !FilterLength; 2636 assert (FirstCatch <= N && "Invalid filter length"); 2637 2638 if (FirstCatch < N) { 2639 TyInfo.reserve(N - FirstCatch); 2640 for (unsigned j = FirstCatch; j < N; ++j) 2641 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2642 MMI->addCatchTypeInfo(MBB, TyInfo); 2643 TyInfo.clear(); 2644 } 2645 2646 if (!FilterLength) { 2647 // Cleanup. 2648 MMI->addCleanup(MBB); 2649 } else { 2650 // Filter. 2651 TyInfo.reserve(FilterLength - 1); 2652 for (unsigned j = i + 1; j < FirstCatch; ++j) 2653 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2654 MMI->addFilterTypeInfo(MBB, TyInfo); 2655 TyInfo.clear(); 2656 } 2657 2658 N = i; 2659 } 2660 } 2661 2662 if (N > 3) { 2663 TyInfo.reserve(N - 3); 2664 for (unsigned j = 3; j < N; ++j) 2665 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2666 MMI->addCatchTypeInfo(MBB, TyInfo); 2667 } 2668} 2669 2670/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2671/// we want to emit this as a call to a named external function, return the name 2672/// otherwise lower it and return null. 2673const char * 2674SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2675 switch (Intrinsic) { 2676 default: 2677 // By default, turn this into a target intrinsic node. 2678 visitTargetIntrinsic(I, Intrinsic); 2679 return 0; 2680 case Intrinsic::vastart: visitVAStart(I); return 0; 2681 case Intrinsic::vaend: visitVAEnd(I); return 0; 2682 case Intrinsic::vacopy: visitVACopy(I); return 0; 2683 case Intrinsic::returnaddress: 2684 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2685 getValue(I.getOperand(1)))); 2686 return 0; 2687 case Intrinsic::frameaddress: 2688 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2689 getValue(I.getOperand(1)))); 2690 return 0; 2691 case Intrinsic::setjmp: 2692 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2693 break; 2694 case Intrinsic::longjmp: 2695 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2696 break; 2697 case Intrinsic::memcpy_i32: 2698 case Intrinsic::memcpy_i64: 2699 visitMemIntrinsic(I, ISD::MEMCPY); 2700 return 0; 2701 case Intrinsic::memset_i32: 2702 case Intrinsic::memset_i64: 2703 visitMemIntrinsic(I, ISD::MEMSET); 2704 return 0; 2705 case Intrinsic::memmove_i32: 2706 case Intrinsic::memmove_i64: 2707 visitMemIntrinsic(I, ISD::MEMMOVE); 2708 return 0; 2709 2710 case Intrinsic::dbg_stoppoint: { 2711 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2712 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2713 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2714 SDOperand Ops[5]; 2715 2716 Ops[0] = getRoot(); 2717 Ops[1] = getValue(SPI.getLineValue()); 2718 Ops[2] = getValue(SPI.getColumnValue()); 2719 2720 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2721 assert(DD && "Not a debug information descriptor"); 2722 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2723 2724 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2725 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2726 2727 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2728 } 2729 2730 return 0; 2731 } 2732 case Intrinsic::dbg_region_start: { 2733 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2734 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2735 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2736 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2737 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2738 DAG.getConstant(LabelID, MVT::i32), 2739 DAG.getConstant(0, MVT::i32))); 2740 } 2741 2742 return 0; 2743 } 2744 case Intrinsic::dbg_region_end: { 2745 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2746 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2747 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2748 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2749 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2750 DAG.getConstant(LabelID, MVT::i32), 2751 DAG.getConstant(0, MVT::i32))); 2752 } 2753 2754 return 0; 2755 } 2756 case Intrinsic::dbg_func_start: { 2757 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2758 if (!MMI) return 0; 2759 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2760 Value *SP = FSI.getSubprogram(); 2761 if (SP && MMI->Verify(SP)) { 2762 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is 2763 // what (most?) gdb expects. 2764 DebugInfoDesc *DD = MMI->getDescFor(SP); 2765 assert(DD && "Not a debug information descriptor"); 2766 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD); 2767 const CompileUnitDesc *CompileUnit = Subprogram->getFile(); 2768 unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(), 2769 CompileUnit->getFileName()); 2770 // Record the source line but does create a label. It will be emitted 2771 // at asm emission time. 2772 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile); 2773 } 2774 2775 return 0; 2776 } 2777 case Intrinsic::dbg_declare: { 2778 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2779 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2780 Value *Variable = DI.getVariable(); 2781 if (MMI && Variable && MMI->Verify(Variable)) 2782 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(), 2783 getValue(DI.getAddress()), getValue(Variable))); 2784 return 0; 2785 } 2786 2787 case Intrinsic::eh_exception: { 2788 if (ExceptionHandling) { 2789 if (!CurMBB->isLandingPad()) { 2790 // FIXME: Mark exception register as live in. Hack for PR1508. 2791 unsigned Reg = TLI.getExceptionAddressRegister(); 2792 if (Reg) CurMBB->addLiveIn(Reg); 2793 } 2794 // Insert the EXCEPTIONADDR instruction. 2795 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2796 SDOperand Ops[1]; 2797 Ops[0] = DAG.getRoot(); 2798 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2799 setValue(&I, Op); 2800 DAG.setRoot(Op.getValue(1)); 2801 } else { 2802 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2803 } 2804 return 0; 2805 } 2806 2807 case Intrinsic::eh_selector_i32: 2808 case Intrinsic::eh_selector_i64: { 2809 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2810 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ? 2811 MVT::i32 : MVT::i64); 2812 2813 if (ExceptionHandling && MMI) { 2814 if (CurMBB->isLandingPad()) 2815 addCatchInfo(I, MMI, CurMBB); 2816 else { 2817#ifndef NDEBUG 2818 FuncInfo.CatchInfoLost.insert(&I); 2819#endif 2820 // FIXME: Mark exception selector register as live in. Hack for PR1508. 2821 unsigned Reg = TLI.getExceptionSelectorRegister(); 2822 if (Reg) CurMBB->addLiveIn(Reg); 2823 } 2824 2825 // Insert the EHSELECTION instruction. 2826 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 2827 SDOperand Ops[2]; 2828 Ops[0] = getValue(I.getOperand(1)); 2829 Ops[1] = getRoot(); 2830 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2831 setValue(&I, Op); 2832 DAG.setRoot(Op.getValue(1)); 2833 } else { 2834 setValue(&I, DAG.getConstant(0, VT)); 2835 } 2836 2837 return 0; 2838 } 2839 2840 case Intrinsic::eh_typeid_for_i32: 2841 case Intrinsic::eh_typeid_for_i64: { 2842 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2843 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? 2844 MVT::i32 : MVT::i64); 2845 2846 if (MMI) { 2847 // Find the type id for the given typeinfo. 2848 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 2849 2850 unsigned TypeID = MMI->getTypeIDFor(GV); 2851 setValue(&I, DAG.getConstant(TypeID, VT)); 2852 } else { 2853 // Return something different to eh_selector. 2854 setValue(&I, DAG.getConstant(1, VT)); 2855 } 2856 2857 return 0; 2858 } 2859 2860 case Intrinsic::eh_return: { 2861 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2862 2863 if (MMI && ExceptionHandling) { 2864 MMI->setCallsEHReturn(true); 2865 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, 2866 MVT::Other, 2867 getRoot(), 2868 getValue(I.getOperand(1)), 2869 getValue(I.getOperand(2)))); 2870 } else { 2871 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2872 } 2873 2874 return 0; 2875 } 2876 2877 case Intrinsic::eh_unwind_init: { 2878 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 2879 MMI->setCallsUnwindInit(true); 2880 } 2881 2882 return 0; 2883 } 2884 2885 case Intrinsic::eh_dwarf_cfa: { 2886 if (ExceptionHandling) { 2887 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType(); 2888 SDOperand CfaArg; 2889 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 2890 CfaArg = DAG.getNode(ISD::TRUNCATE, 2891 TLI.getPointerTy(), getValue(I.getOperand(1))); 2892 else 2893 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, 2894 TLI.getPointerTy(), getValue(I.getOperand(1))); 2895 2896 SDOperand Offset = DAG.getNode(ISD::ADD, 2897 TLI.getPointerTy(), 2898 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, 2899 TLI.getPointerTy()), 2900 CfaArg); 2901 setValue(&I, DAG.getNode(ISD::ADD, 2902 TLI.getPointerTy(), 2903 DAG.getNode(ISD::FRAMEADDR, 2904 TLI.getPointerTy(), 2905 DAG.getConstant(0, 2906 TLI.getPointerTy())), 2907 Offset)); 2908 } else { 2909 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2910 } 2911 2912 return 0; 2913 } 2914 2915 case Intrinsic::sqrt: 2916 setValue(&I, DAG.getNode(ISD::FSQRT, 2917 getValue(I.getOperand(1)).getValueType(), 2918 getValue(I.getOperand(1)))); 2919 return 0; 2920 case Intrinsic::powi: 2921 setValue(&I, DAG.getNode(ISD::FPOWI, 2922 getValue(I.getOperand(1)).getValueType(), 2923 getValue(I.getOperand(1)), 2924 getValue(I.getOperand(2)))); 2925 return 0; 2926 case Intrinsic::sin: 2927 setValue(&I, DAG.getNode(ISD::FSIN, 2928 getValue(I.getOperand(1)).getValueType(), 2929 getValue(I.getOperand(1)))); 2930 return 0; 2931 case Intrinsic::cos: 2932 setValue(&I, DAG.getNode(ISD::FCOS, 2933 getValue(I.getOperand(1)).getValueType(), 2934 getValue(I.getOperand(1)))); 2935 return 0; 2936 case Intrinsic::pow: 2937 setValue(&I, DAG.getNode(ISD::FPOW, 2938 getValue(I.getOperand(1)).getValueType(), 2939 getValue(I.getOperand(1)), 2940 getValue(I.getOperand(2)))); 2941 return 0; 2942 case Intrinsic::pcmarker: { 2943 SDOperand Tmp = getValue(I.getOperand(1)); 2944 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2945 return 0; 2946 } 2947 case Intrinsic::readcyclecounter: { 2948 SDOperand Op = getRoot(); 2949 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2950 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2951 &Op, 1); 2952 setValue(&I, Tmp); 2953 DAG.setRoot(Tmp.getValue(1)); 2954 return 0; 2955 } 2956 case Intrinsic::part_select: { 2957 // Currently not implemented: just abort 2958 assert(0 && "part_select intrinsic not implemented"); 2959 abort(); 2960 } 2961 case Intrinsic::part_set: { 2962 // Currently not implemented: just abort 2963 assert(0 && "part_set intrinsic not implemented"); 2964 abort(); 2965 } 2966 case Intrinsic::bswap: 2967 setValue(&I, DAG.getNode(ISD::BSWAP, 2968 getValue(I.getOperand(1)).getValueType(), 2969 getValue(I.getOperand(1)))); 2970 return 0; 2971 case Intrinsic::cttz: { 2972 SDOperand Arg = getValue(I.getOperand(1)); 2973 MVT::ValueType Ty = Arg.getValueType(); 2974 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2975 setValue(&I, result); 2976 return 0; 2977 } 2978 case Intrinsic::ctlz: { 2979 SDOperand Arg = getValue(I.getOperand(1)); 2980 MVT::ValueType Ty = Arg.getValueType(); 2981 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2982 setValue(&I, result); 2983 return 0; 2984 } 2985 case Intrinsic::ctpop: { 2986 SDOperand Arg = getValue(I.getOperand(1)); 2987 MVT::ValueType Ty = Arg.getValueType(); 2988 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2989 setValue(&I, result); 2990 return 0; 2991 } 2992 case Intrinsic::stacksave: { 2993 SDOperand Op = getRoot(); 2994 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2995 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2996 setValue(&I, Tmp); 2997 DAG.setRoot(Tmp.getValue(1)); 2998 return 0; 2999 } 3000 case Intrinsic::stackrestore: { 3001 SDOperand Tmp = getValue(I.getOperand(1)); 3002 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 3003 return 0; 3004 } 3005 case Intrinsic::var_annotation: 3006 // Discard annotate attributes 3007 return 0; 3008 3009 case Intrinsic::init_trampoline: { 3010 const Function *F = 3011 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2))); 3012 3013 SDOperand Ops[6]; 3014 Ops[0] = getRoot(); 3015 Ops[1] = getValue(I.getOperand(1)); 3016 Ops[2] = getValue(I.getOperand(2)); 3017 Ops[3] = getValue(I.getOperand(3)); 3018 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 3019 Ops[5] = DAG.getSrcValue(F); 3020 3021 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE, 3022 DAG.getNodeValueTypes(TLI.getPointerTy(), 3023 MVT::Other), 2, 3024 Ops, 6); 3025 3026 setValue(&I, Tmp); 3027 DAG.setRoot(Tmp.getValue(1)); 3028 return 0; 3029 } 3030 3031 case Intrinsic::gcroot: 3032 if (GCI) { 3033 Value *Alloca = I.getOperand(1); 3034 Constant *TypeMap = cast<Constant>(I.getOperand(2)); 3035 3036 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val); 3037 GCI->addStackRoot(FI->getIndex(), TypeMap); 3038 } 3039 return 0; 3040 3041 case Intrinsic::gcread: 3042 case Intrinsic::gcwrite: 3043 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!"); 3044 return 0; 3045 3046 case Intrinsic::flt_rounds: { 3047 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32)); 3048 return 0; 3049 } 3050 3051 case Intrinsic::trap: { 3052 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot())); 3053 return 0; 3054 } 3055 case Intrinsic::prefetch: { 3056 SDOperand Ops[4]; 3057 Ops[0] = getRoot(); 3058 Ops[1] = getValue(I.getOperand(1)); 3059 Ops[2] = getValue(I.getOperand(2)); 3060 Ops[3] = getValue(I.getOperand(3)); 3061 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4)); 3062 return 0; 3063 } 3064 3065 case Intrinsic::memory_barrier: { 3066 SDOperand Ops[6]; 3067 Ops[0] = getRoot(); 3068 for (int x = 1; x < 6; ++x) 3069 Ops[x] = getValue(I.getOperand(x)); 3070 3071 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6)); 3072 return 0; 3073 } 3074 case Intrinsic::atomic_lcs: { 3075 SDOperand Root = getRoot(); 3076 SDOperand O3 = getValue(I.getOperand(3)); 3077 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LCS, Root, 3078 getValue(I.getOperand(1)), 3079 getValue(I.getOperand(2)), 3080 O3, O3.getValueType()); 3081 setValue(&I, L); 3082 DAG.setRoot(L.getValue(1)); 3083 return 0; 3084 } 3085 case Intrinsic::atomic_las: { 3086 SDOperand Root = getRoot(); 3087 SDOperand O2 = getValue(I.getOperand(2)); 3088 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LAS, Root, 3089 getValue(I.getOperand(1)), 3090 O2, O2.getValueType()); 3091 setValue(&I, L); 3092 DAG.setRoot(L.getValue(1)); 3093 return 0; 3094 } 3095 case Intrinsic::atomic_swap: { 3096 SDOperand Root = getRoot(); 3097 SDOperand O2 = getValue(I.getOperand(2)); 3098 SDOperand L = DAG.getAtomic(ISD::ATOMIC_SWAP, Root, 3099 getValue(I.getOperand(1)), 3100 O2, O2.getValueType()); 3101 setValue(&I, L); 3102 DAG.setRoot(L.getValue(1)); 3103 return 0; 3104 } 3105 3106 } 3107} 3108 3109 3110void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee, 3111 bool IsTailCall, 3112 MachineBasicBlock *LandingPad) { 3113 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 3114 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 3115 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3116 unsigned BeginLabel = 0, EndLabel = 0; 3117 3118 TargetLowering::ArgListTy Args; 3119 TargetLowering::ArgListEntry Entry; 3120 Args.reserve(CS.arg_size()); 3121 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 3122 i != e; ++i) { 3123 SDOperand ArgNode = getValue(*i); 3124 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 3125 3126 unsigned attrInd = i - CS.arg_begin() + 1; 3127 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt); 3128 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt); 3129 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg); 3130 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet); 3131 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest); 3132 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal); 3133 Entry.Alignment = CS.getParamAlignment(attrInd); 3134 Args.push_back(Entry); 3135 } 3136 3137 if (LandingPad && ExceptionHandling && MMI) { 3138 // Insert a label before the invoke call to mark the try range. This can be 3139 // used to detect deletion of the invoke via the MachineModuleInfo. 3140 BeginLabel = MMI->NextLabelID(); 3141 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 3142 DAG.getConstant(BeginLabel, MVT::i32), 3143 DAG.getConstant(1, MVT::i32))); 3144 } 3145 3146 std::pair<SDOperand,SDOperand> Result = 3147 TLI.LowerCallTo(getRoot(), CS.getType(), 3148 CS.paramHasAttr(0, ParamAttr::SExt), 3149 CS.paramHasAttr(0, ParamAttr::ZExt), 3150 FTy->isVarArg(), CS.getCallingConv(), IsTailCall, 3151 Callee, Args, DAG); 3152 if (CS.getType() != Type::VoidTy) 3153 setValue(CS.getInstruction(), Result.first); 3154 DAG.setRoot(Result.second); 3155 3156 if (LandingPad && ExceptionHandling && MMI) { 3157 // Insert a label at the end of the invoke call to mark the try range. This 3158 // can be used to detect deletion of the invoke via the MachineModuleInfo. 3159 EndLabel = MMI->NextLabelID(); 3160 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 3161 DAG.getConstant(EndLabel, MVT::i32), 3162 DAG.getConstant(1, MVT::i32))); 3163 3164 // Inform MachineModuleInfo of range. 3165 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 3166 } 3167} 3168 3169 3170void SelectionDAGLowering::visitCall(CallInst &I) { 3171 const char *RenameFn = 0; 3172 if (Function *F = I.getCalledFunction()) { 3173 if (F->isDeclaration()) { 3174 if (unsigned IID = F->getIntrinsicID()) { 3175 RenameFn = visitIntrinsicCall(I, IID); 3176 if (!RenameFn) 3177 return; 3178 } 3179 } 3180 3181 // Check for well-known libc/libm calls. If the function is internal, it 3182 // can't be a library call. 3183 unsigned NameLen = F->getNameLen(); 3184 if (!F->hasInternalLinkage() && NameLen) { 3185 const char *NameStr = F->getNameStart(); 3186 if (NameStr[0] == 'c' && 3187 ((NameLen == 8 && !strcmp(NameStr, "copysign")) || 3188 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) { 3189 if (I.getNumOperands() == 3 && // Basic sanity checks. 3190 I.getOperand(1)->getType()->isFloatingPoint() && 3191 I.getType() == I.getOperand(1)->getType() && 3192 I.getType() == I.getOperand(2)->getType()) { 3193 SDOperand LHS = getValue(I.getOperand(1)); 3194 SDOperand RHS = getValue(I.getOperand(2)); 3195 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 3196 LHS, RHS)); 3197 return; 3198 } 3199 } else if (NameStr[0] == 'f' && 3200 ((NameLen == 4 && !strcmp(NameStr, "fabs")) || 3201 (NameLen == 5 && !strcmp(NameStr, "fabsf")) || 3202 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) { 3203 if (I.getNumOperands() == 2 && // Basic sanity checks. 3204 I.getOperand(1)->getType()->isFloatingPoint() && 3205 I.getType() == I.getOperand(1)->getType()) { 3206 SDOperand Tmp = getValue(I.getOperand(1)); 3207 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 3208 return; 3209 } 3210 } else if (NameStr[0] == 's' && 3211 ((NameLen == 3 && !strcmp(NameStr, "sin")) || 3212 (NameLen == 4 && !strcmp(NameStr, "sinf")) || 3213 (NameLen == 4 && !strcmp(NameStr, "sinl")))) { 3214 if (I.getNumOperands() == 2 && // Basic sanity checks. 3215 I.getOperand(1)->getType()->isFloatingPoint() && 3216 I.getType() == I.getOperand(1)->getType()) { 3217 SDOperand Tmp = getValue(I.getOperand(1)); 3218 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 3219 return; 3220 } 3221 } else if (NameStr[0] == 'c' && 3222 ((NameLen == 3 && !strcmp(NameStr, "cos")) || 3223 (NameLen == 4 && !strcmp(NameStr, "cosf")) || 3224 (NameLen == 4 && !strcmp(NameStr, "cosl")))) { 3225 if (I.getNumOperands() == 2 && // Basic sanity checks. 3226 I.getOperand(1)->getType()->isFloatingPoint() && 3227 I.getType() == I.getOperand(1)->getType()) { 3228 SDOperand Tmp = getValue(I.getOperand(1)); 3229 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 3230 return; 3231 } 3232 } 3233 } 3234 } else if (isa<InlineAsm>(I.getOperand(0))) { 3235 visitInlineAsm(&I); 3236 return; 3237 } 3238 3239 SDOperand Callee; 3240 if (!RenameFn) 3241 Callee = getValue(I.getOperand(0)); 3242 else 3243 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 3244 3245 LowerCallTo(&I, Callee, I.isTailCall()); 3246} 3247 3248 3249void SelectionDAGLowering::visitGetResult(GetResultInst &I) { 3250 SDOperand Call = getValue(I.getOperand(0)); 3251 setValue(&I, SDOperand(Call.Val, I.getIndex())); 3252} 3253 3254 3255/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 3256/// this value and returns the result as a ValueVT value. This uses 3257/// Chain/Flag as the input and updates them for the output Chain/Flag. 3258/// If the Flag pointer is NULL, no flag is used. 3259SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 3260 SDOperand &Chain, SDOperand *Flag)const{ 3261 // Copy the legal parts from the registers. 3262 unsigned NumParts = Regs.size(); 3263 SmallVector<SDOperand, 8> Parts(NumParts); 3264 for (unsigned i = 0; i != NumParts; ++i) { 3265 SDOperand Part = Flag ? 3266 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) : 3267 DAG.getCopyFromReg(Chain, Regs[i], RegVT); 3268 Chain = Part.getValue(1); 3269 if (Flag) 3270 *Flag = Part.getValue(2); 3271 Parts[i] = Part; 3272 } 3273 3274 // Assemble the legal parts into the final value. 3275 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT); 3276} 3277 3278/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 3279/// specified value into the registers specified by this object. This uses 3280/// Chain/Flag as the input and updates them for the output Chain/Flag. 3281/// If the Flag pointer is NULL, no flag is used. 3282void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 3283 SDOperand &Chain, SDOperand *Flag) const { 3284 // Get the list of the values's legal parts. 3285 unsigned NumParts = Regs.size(); 3286 SmallVector<SDOperand, 8> Parts(NumParts); 3287 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT); 3288 3289 // Copy the parts into the registers. 3290 for (unsigned i = 0; i != NumParts; ++i) { 3291 SDOperand Part = Flag ? 3292 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) : 3293 DAG.getCopyToReg(Chain, Regs[i], Parts[i]); 3294 Chain = Part.getValue(0); 3295 if (Flag) 3296 *Flag = Part.getValue(1); 3297 } 3298} 3299 3300/// AddInlineAsmOperands - Add this value to the specified inlineasm node 3301/// operand list. This adds the code marker and includes the number of 3302/// values added into it. 3303void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 3304 std::vector<SDOperand> &Ops) const { 3305 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3306 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3307 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 3308 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 3309} 3310 3311/// isAllocatableRegister - If the specified register is safe to allocate, 3312/// i.e. it isn't a stack pointer or some other special register, return the 3313/// register class for the register. Otherwise, return null. 3314static const TargetRegisterClass * 3315isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3316 const TargetLowering &TLI, 3317 const TargetRegisterInfo *TRI) { 3318 MVT::ValueType FoundVT = MVT::Other; 3319 const TargetRegisterClass *FoundRC = 0; 3320 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 3321 E = TRI->regclass_end(); RCI != E; ++RCI) { 3322 MVT::ValueType ThisVT = MVT::Other; 3323 3324 const TargetRegisterClass *RC = *RCI; 3325 // If none of the the value types for this register class are valid, we 3326 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3327 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3328 I != E; ++I) { 3329 if (TLI.isTypeLegal(*I)) { 3330 // If we have already found this register in a different register class, 3331 // choose the one with the largest VT specified. For example, on 3332 // PowerPC, we favor f64 register classes over f32. 3333 if (FoundVT == MVT::Other || 3334 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 3335 ThisVT = *I; 3336 break; 3337 } 3338 } 3339 } 3340 3341 if (ThisVT == MVT::Other) continue; 3342 3343 // NOTE: This isn't ideal. In particular, this might allocate the 3344 // frame pointer in functions that need it (due to them not being taken 3345 // out of allocation, because a variable sized allocation hasn't been seen 3346 // yet). This is a slight code pessimization, but should still work. 3347 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3348 E = RC->allocation_order_end(MF); I != E; ++I) 3349 if (*I == Reg) { 3350 // We found a matching register class. Keep looking at others in case 3351 // we find one with larger registers that this physreg is also in. 3352 FoundRC = RC; 3353 FoundVT = ThisVT; 3354 break; 3355 } 3356 } 3357 return FoundRC; 3358} 3359 3360 3361namespace { 3362/// AsmOperandInfo - This contains information for each constraint that we are 3363/// lowering. 3364struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 3365 /// CallOperand - If this is the result output operand or a clobber 3366 /// this is null, otherwise it is the incoming operand to the CallInst. 3367 /// This gets modified as the asm is processed. 3368 SDOperand CallOperand; 3369 3370 /// AssignedRegs - If this is a register or register class operand, this 3371 /// contains the set of register corresponding to the operand. 3372 RegsForValue AssignedRegs; 3373 3374 SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3375 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 3376 } 3377 3378 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3379 /// busy in OutputRegs/InputRegs. 3380 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3381 std::set<unsigned> &OutputRegs, 3382 std::set<unsigned> &InputRegs, 3383 const TargetRegisterInfo &TRI) const { 3384 if (isOutReg) { 3385 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 3386 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 3387 } 3388 if (isInReg) { 3389 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 3390 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 3391 } 3392 } 3393 3394private: 3395 /// MarkRegAndAliases - Mark the specified register and all aliases in the 3396 /// specified set. 3397 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 3398 const TargetRegisterInfo &TRI) { 3399 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 3400 Regs.insert(Reg); 3401 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 3402 for (; *Aliases; ++Aliases) 3403 Regs.insert(*Aliases); 3404 } 3405}; 3406} // end anon namespace. 3407 3408 3409/// GetRegistersForValue - Assign registers (virtual or physical) for the 3410/// specified operand. We prefer to assign virtual registers, to allow the 3411/// register allocator handle the assignment process. However, if the asm uses 3412/// features that we can't model on machineinstrs, we have SDISel do the 3413/// allocation. This produces generally horrible, but correct, code. 3414/// 3415/// OpInfo describes the operand. 3416/// HasEarlyClobber is true if there are any early clobber constraints (=&r) 3417/// or any explicitly clobbered registers. 3418/// Input and OutputRegs are the set of already allocated physical registers. 3419/// 3420void SelectionDAGLowering:: 3421GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber, 3422 std::set<unsigned> &OutputRegs, 3423 std::set<unsigned> &InputRegs) { 3424 // Compute whether this value requires an input register, an output register, 3425 // or both. 3426 bool isOutReg = false; 3427 bool isInReg = false; 3428 switch (OpInfo.Type) { 3429 case InlineAsm::isOutput: 3430 isOutReg = true; 3431 3432 // If this is an early-clobber output, or if there is an input 3433 // constraint that matches this, we need to reserve the input register 3434 // so no other inputs allocate to it. 3435 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3436 break; 3437 case InlineAsm::isInput: 3438 isInReg = true; 3439 isOutReg = false; 3440 break; 3441 case InlineAsm::isClobber: 3442 isOutReg = true; 3443 isInReg = true; 3444 break; 3445 } 3446 3447 3448 MachineFunction &MF = DAG.getMachineFunction(); 3449 std::vector<unsigned> Regs; 3450 3451 // If this is a constraint for a single physreg, or a constraint for a 3452 // register class, find it. 3453 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3454 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3455 OpInfo.ConstraintVT); 3456 3457 unsigned NumRegs = 1; 3458 if (OpInfo.ConstraintVT != MVT::Other) 3459 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3460 MVT::ValueType RegVT; 3461 MVT::ValueType ValueVT = OpInfo.ConstraintVT; 3462 3463 3464 // If this is a constraint for a specific physical register, like {r17}, 3465 // assign it now. 3466 if (PhysReg.first) { 3467 if (OpInfo.ConstraintVT == MVT::Other) 3468 ValueVT = *PhysReg.second->vt_begin(); 3469 3470 // Get the actual register value type. This is important, because the user 3471 // may have asked for (e.g.) the AX register in i32 type. We need to 3472 // remember that AX is actually i16 to get the right extension. 3473 RegVT = *PhysReg.second->vt_begin(); 3474 3475 // This is a explicit reference to a physical register. 3476 Regs.push_back(PhysReg.first); 3477 3478 // If this is an expanded reference, add the rest of the regs to Regs. 3479 if (NumRegs != 1) { 3480 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3481 TargetRegisterClass::iterator E = PhysReg.second->end(); 3482 for (; *I != PhysReg.first; ++I) 3483 assert(I != E && "Didn't find reg!"); 3484 3485 // Already added the first reg. 3486 --NumRegs; ++I; 3487 for (; NumRegs; --NumRegs, ++I) { 3488 assert(I != E && "Ran out of registers to allocate!"); 3489 Regs.push_back(*I); 3490 } 3491 } 3492 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3493 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 3494 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 3495 return; 3496 } 3497 3498 // Otherwise, if this was a reference to an LLVM register class, create vregs 3499 // for this reference. 3500 std::vector<unsigned> RegClassRegs; 3501 const TargetRegisterClass *RC = PhysReg.second; 3502 if (RC) { 3503 // If this is an early clobber or tied register, our regalloc doesn't know 3504 // how to maintain the constraint. If it isn't, go ahead and create vreg 3505 // and let the regalloc do the right thing. 3506 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 3507 // If there is some other early clobber and this is an input register, 3508 // then we are forced to pre-allocate the input reg so it doesn't 3509 // conflict with the earlyclobber. 3510 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 3511 RegVT = *PhysReg.second->vt_begin(); 3512 3513 if (OpInfo.ConstraintVT == MVT::Other) 3514 ValueVT = RegVT; 3515 3516 // Create the appropriate number of virtual registers. 3517 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 3518 for (; NumRegs; --NumRegs) 3519 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second)); 3520 3521 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3522 return; 3523 } 3524 3525 // Otherwise, we can't allocate it. Let the code below figure out how to 3526 // maintain these constraints. 3527 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3528 3529 } else { 3530 // This is a reference to a register class that doesn't directly correspond 3531 // to an LLVM register class. Allocate NumRegs consecutive, available, 3532 // registers from the class. 3533 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3534 OpInfo.ConstraintVT); 3535 } 3536 3537 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 3538 unsigned NumAllocated = 0; 3539 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3540 unsigned Reg = RegClassRegs[i]; 3541 // See if this register is available. 3542 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3543 (isInReg && InputRegs.count(Reg))) { // Already used. 3544 // Make sure we find consecutive registers. 3545 NumAllocated = 0; 3546 continue; 3547 } 3548 3549 // Check to see if this register is allocatable (i.e. don't give out the 3550 // stack pointer). 3551 if (RC == 0) { 3552 RC = isAllocatableRegister(Reg, MF, TLI, TRI); 3553 if (!RC) { // Couldn't allocate this register. 3554 // Reset NumAllocated to make sure we return consecutive registers. 3555 NumAllocated = 0; 3556 continue; 3557 } 3558 } 3559 3560 // Okay, this register is good, we can use it. 3561 ++NumAllocated; 3562 3563 // If we allocated enough consecutive registers, succeed. 3564 if (NumAllocated == NumRegs) { 3565 unsigned RegStart = (i-NumAllocated)+1; 3566 unsigned RegEnd = i+1; 3567 // Mark all of the allocated registers used. 3568 for (unsigned i = RegStart; i != RegEnd; ++i) 3569 Regs.push_back(RegClassRegs[i]); 3570 3571 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 3572 OpInfo.ConstraintVT); 3573 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 3574 return; 3575 } 3576 } 3577 3578 // Otherwise, we couldn't allocate enough registers for this. 3579 return; 3580} 3581 3582 3583/// visitInlineAsm - Handle a call to an InlineAsm object. 3584/// 3585void SelectionDAGLowering::visitInlineAsm(CallSite CS) { 3586 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 3587 3588 /// ConstraintOperands - Information about all of the constraints. 3589 std::vector<SDISelAsmOperandInfo> ConstraintOperands; 3590 3591 SDOperand Chain = getRoot(); 3592 SDOperand Flag; 3593 3594 std::set<unsigned> OutputRegs, InputRegs; 3595 3596 // Do a prepass over the constraints, canonicalizing them, and building up the 3597 // ConstraintOperands list. 3598 std::vector<InlineAsm::ConstraintInfo> 3599 ConstraintInfos = IA->ParseConstraints(); 3600 3601 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 3602 // constraint. If so, we can't let the register allocator allocate any input 3603 // registers, because it will not know to avoid the earlyclobbered output reg. 3604 bool SawEarlyClobber = false; 3605 3606 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 3607 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3608 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); 3609 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 3610 3611 MVT::ValueType OpVT = MVT::Other; 3612 3613 // Compute the value type for each operand. 3614 switch (OpInfo.Type) { 3615 case InlineAsm::isOutput: 3616 if (!OpInfo.isIndirect) { 3617 // The return value of the call is this value. As such, there is no 3618 // corresponding argument. 3619 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 3620 OpVT = TLI.getValueType(CS.getType()); 3621 } else { 3622 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 3623 } 3624 break; 3625 case InlineAsm::isInput: 3626 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 3627 break; 3628 case InlineAsm::isClobber: 3629 // Nothing to do. 3630 break; 3631 } 3632 3633 // If this is an input or an indirect output, process the call argument. 3634 // BasicBlocks are labels, currently appearing only in asm's. 3635 if (OpInfo.CallOperandVal) { 3636 if (isa<BasicBlock>(OpInfo.CallOperandVal)) 3637 OpInfo.CallOperand = 3638 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>( 3639 OpInfo.CallOperandVal)]); 3640 else { 3641 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 3642 const Type *OpTy = OpInfo.CallOperandVal->getType(); 3643 // If this is an indirect operand, the operand is a pointer to the 3644 // accessed type. 3645 if (OpInfo.isIndirect) 3646 OpTy = cast<PointerType>(OpTy)->getElementType(); 3647 3648 // If OpTy is not a first-class value, it may be a struct/union that we 3649 // can tile with integers. 3650 if (!OpTy->isFirstClassType() && OpTy->isSized()) { 3651 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3652 switch (BitSize) { 3653 default: break; 3654 case 1: 3655 case 8: 3656 case 16: 3657 case 32: 3658 case 64: 3659 OpTy = IntegerType::get(BitSize); 3660 break; 3661 } 3662 } 3663 3664 OpVT = TLI.getValueType(OpTy, true); 3665 } 3666 } 3667 3668 OpInfo.ConstraintVT = OpVT; 3669 3670 // Compute the constraint code and ConstraintType to use. 3671 OpInfo.ComputeConstraintToUse(TLI); 3672 3673 // Keep track of whether we see an earlyclobber. 3674 SawEarlyClobber |= OpInfo.isEarlyClobber; 3675 3676 // If we see a clobber of a register, it is an early clobber. 3677 if (!SawEarlyClobber && 3678 OpInfo.Type == InlineAsm::isClobber && 3679 OpInfo.ConstraintType == TargetLowering::C_Register) { 3680 // Note that we want to ignore things that we don't trick here, like 3681 // dirflag, fpsr, flags, etc. 3682 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3683 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3684 OpInfo.ConstraintVT); 3685 if (PhysReg.first || PhysReg.second) { 3686 // This is a register we know of. 3687 SawEarlyClobber = true; 3688 } 3689 } 3690 3691 // If this is a memory input, and if the operand is not indirect, do what we 3692 // need to to provide an address for the memory input. 3693 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 3694 !OpInfo.isIndirect) { 3695 assert(OpInfo.Type == InlineAsm::isInput && 3696 "Can only indirectify direct input operands!"); 3697 3698 // Memory operands really want the address of the value. If we don't have 3699 // an indirect input, put it in the constpool if we can, otherwise spill 3700 // it to a stack slot. 3701 3702 // If the operand is a float, integer, or vector constant, spill to a 3703 // constant pool entry to get its address. 3704 Value *OpVal = OpInfo.CallOperandVal; 3705 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 3706 isa<ConstantVector>(OpVal)) { 3707 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 3708 TLI.getPointerTy()); 3709 } else { 3710 // Otherwise, create a stack slot and emit a store to it before the 3711 // asm. 3712 const Type *Ty = OpVal->getType(); 3713 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 3714 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3715 MachineFunction &MF = DAG.getMachineFunction(); 3716 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3717 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3718 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 3719 OpInfo.CallOperand = StackSlot; 3720 } 3721 3722 // There is no longer a Value* corresponding to this operand. 3723 OpInfo.CallOperandVal = 0; 3724 // It is now an indirect operand. 3725 OpInfo.isIndirect = true; 3726 } 3727 3728 // If this constraint is for a specific register, allocate it before 3729 // anything else. 3730 if (OpInfo.ConstraintType == TargetLowering::C_Register) 3731 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3732 } 3733 ConstraintInfos.clear(); 3734 3735 3736 // Second pass - Loop over all of the operands, assigning virtual or physregs 3737 // to registerclass operands. 3738 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3739 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 3740 3741 // C_Register operands have already been allocated, Other/Memory don't need 3742 // to be. 3743 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 3744 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3745 } 3746 3747 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 3748 std::vector<SDOperand> AsmNodeOperands; 3749 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3750 AsmNodeOperands.push_back( 3751 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 3752 3753 3754 // Loop over all of the inputs, copying the operand values into the 3755 // appropriate registers and processing the output regs. 3756 RegsForValue RetValRegs; 3757 3758 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 3759 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3760 3761 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3762 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 3763 3764 switch (OpInfo.Type) { 3765 case InlineAsm::isOutput: { 3766 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 3767 OpInfo.ConstraintType != TargetLowering::C_Register) { 3768 // Memory output, or 'other' output (e.g. 'X' constraint). 3769 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 3770 3771 // Add information to the INLINEASM node to know about this output. 3772 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3773 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3774 TLI.getPointerTy())); 3775 AsmNodeOperands.push_back(OpInfo.CallOperand); 3776 break; 3777 } 3778 3779 // Otherwise, this is a register or register class output. 3780 3781 // Copy the output from the appropriate register. Find a register that 3782 // we can use. 3783 if (OpInfo.AssignedRegs.Regs.empty()) { 3784 cerr << "Couldn't allocate output reg for contraint '" 3785 << OpInfo.ConstraintCode << "'!\n"; 3786 exit(1); 3787 } 3788 3789 if (!OpInfo.isIndirect) { 3790 // This is the result value of the call. 3791 assert(RetValRegs.Regs.empty() && 3792 "Cannot have multiple output constraints yet!"); 3793 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 3794 RetValRegs = OpInfo.AssignedRegs; 3795 } else { 3796 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 3797 OpInfo.CallOperandVal)); 3798 } 3799 3800 // Add information to the INLINEASM node to know that this register is 3801 // set. 3802 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 3803 AsmNodeOperands); 3804 break; 3805 } 3806 case InlineAsm::isInput: { 3807 SDOperand InOperandVal = OpInfo.CallOperand; 3808 3809 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 3810 // If this is required to match an output register we have already set, 3811 // just use its register. 3812 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 3813 3814 // Scan until we find the definition we already emitted of this operand. 3815 // When we find it, create a RegsForValue operand. 3816 unsigned CurOp = 2; // The first operand. 3817 for (; OperandNo; --OperandNo) { 3818 // Advance to the next operand. 3819 unsigned NumOps = 3820 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3821 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3822 (NumOps & 7) == 4 /*MEM*/) && 3823 "Skipped past definitions?"); 3824 CurOp += (NumOps>>3)+1; 3825 } 3826 3827 unsigned NumOps = 3828 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3829 if ((NumOps & 7) == 2 /*REGDEF*/) { 3830 // Add NumOps>>3 registers to MatchedRegs. 3831 RegsForValue MatchedRegs; 3832 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3833 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3834 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3835 unsigned Reg = 3836 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3837 MatchedRegs.Regs.push_back(Reg); 3838 } 3839 3840 // Use the produced MatchedRegs object to 3841 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3842 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3843 break; 3844 } else { 3845 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3846 assert((NumOps >> 3) == 1 && "Unexpected number of operands"); 3847 // Add information to the INLINEASM node to know about this input. 3848 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3849 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3850 TLI.getPointerTy())); 3851 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 3852 break; 3853 } 3854 } 3855 3856 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 3857 assert(!OpInfo.isIndirect && 3858 "Don't know how to handle indirect other inputs yet!"); 3859 3860 std::vector<SDOperand> Ops; 3861 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 3862 Ops, DAG); 3863 if (Ops.empty()) { 3864 cerr << "Invalid operand for inline asm constraint '" 3865 << OpInfo.ConstraintCode << "'!\n"; 3866 exit(1); 3867 } 3868 3869 // Add information to the INLINEASM node to know about this input. 3870 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 3871 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3872 TLI.getPointerTy())); 3873 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 3874 break; 3875 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 3876 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 3877 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 3878 "Memory operands expect pointer values"); 3879 3880 // Add information to the INLINEASM node to know about this input. 3881 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3882 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3883 TLI.getPointerTy())); 3884 AsmNodeOperands.push_back(InOperandVal); 3885 break; 3886 } 3887 3888 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 3889 OpInfo.ConstraintType == TargetLowering::C_Register) && 3890 "Unknown constraint type!"); 3891 assert(!OpInfo.isIndirect && 3892 "Don't know how to handle indirect register inputs yet!"); 3893 3894 // Copy the input into the appropriate registers. 3895 assert(!OpInfo.AssignedRegs.Regs.empty() && 3896 "Couldn't allocate input reg!"); 3897 3898 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3899 3900 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 3901 AsmNodeOperands); 3902 break; 3903 } 3904 case InlineAsm::isClobber: { 3905 // Add the clobbered value to the operand list, so that the register 3906 // allocator is aware that the physreg got clobbered. 3907 if (!OpInfo.AssignedRegs.Regs.empty()) 3908 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 3909 AsmNodeOperands); 3910 break; 3911 } 3912 } 3913 } 3914 3915 // Finish up input operands. 3916 AsmNodeOperands[0] = Chain; 3917 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3918 3919 Chain = DAG.getNode(ISD::INLINEASM, 3920 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3921 &AsmNodeOperands[0], AsmNodeOperands.size()); 3922 Flag = Chain.getValue(1); 3923 3924 // If this asm returns a register value, copy the result from that register 3925 // and set it as the value of the call. 3926 if (!RetValRegs.Regs.empty()) { 3927 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 3928 3929 // If the result of the inline asm is a vector, it may have the wrong 3930 // width/num elts. Make sure to convert it to the right type with 3931 // bit_convert. 3932 if (MVT::isVector(Val.getValueType())) { 3933 const VectorType *VTy = cast<VectorType>(CS.getType()); 3934 MVT::ValueType DesiredVT = TLI.getValueType(VTy); 3935 3936 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val); 3937 } 3938 3939 setValue(CS.getInstruction(), Val); 3940 } 3941 3942 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 3943 3944 // Process indirect outputs, first output all of the flagged copies out of 3945 // physregs. 3946 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 3947 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 3948 Value *Ptr = IndirectStoresToEmit[i].second; 3949 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 3950 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 3951 } 3952 3953 // Emit the non-flagged stores from the physregs. 3954 SmallVector<SDOperand, 8> OutChains; 3955 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 3956 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 3957 getValue(StoresToEmit[i].second), 3958 StoresToEmit[i].second, 0)); 3959 if (!OutChains.empty()) 3960 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3961 &OutChains[0], OutChains.size()); 3962 DAG.setRoot(Chain); 3963} 3964 3965 3966void SelectionDAGLowering::visitMalloc(MallocInst &I) { 3967 SDOperand Src = getValue(I.getOperand(0)); 3968 3969 MVT::ValueType IntPtr = TLI.getPointerTy(); 3970 3971 if (IntPtr < Src.getValueType()) 3972 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 3973 else if (IntPtr > Src.getValueType()) 3974 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 3975 3976 // Scale the source by the type size. 3977 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType()); 3978 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 3979 Src, DAG.getIntPtrConstant(ElementSize)); 3980 3981 TargetLowering::ArgListTy Args; 3982 TargetLowering::ArgListEntry Entry; 3983 Entry.Node = Src; 3984 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3985 Args.push_back(Entry); 3986 3987 std::pair<SDOperand,SDOperand> Result = 3988 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C, 3989 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG); 3990 setValue(&I, Result.first); // Pointers always fit in registers 3991 DAG.setRoot(Result.second); 3992} 3993 3994void SelectionDAGLowering::visitFree(FreeInst &I) { 3995 TargetLowering::ArgListTy Args; 3996 TargetLowering::ArgListEntry Entry; 3997 Entry.Node = getValue(I.getOperand(0)); 3998 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3999 Args.push_back(Entry); 4000 MVT::ValueType IntPtr = TLI.getPointerTy(); 4001 std::pair<SDOperand,SDOperand> Result = 4002 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, 4003 CallingConv::C, true, 4004 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 4005 DAG.setRoot(Result.second); 4006} 4007 4008// EmitInstrWithCustomInserter - This method should be implemented by targets 4009// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 4010// instructions are special in various ways, which require special support to 4011// insert. The specified MachineInstr is created but not inserted into any 4012// basic blocks, and the scheduler passes ownership of it to this method. 4013MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4014 MachineBasicBlock *MBB) { 4015 cerr << "If a target marks an instruction with " 4016 << "'usesCustomDAGSchedInserter', it must implement " 4017 << "TargetLowering::EmitInstrWithCustomInserter!\n"; 4018 abort(); 4019 return 0; 4020} 4021 4022void SelectionDAGLowering::visitVAStart(CallInst &I) { 4023 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 4024 getValue(I.getOperand(1)), 4025 DAG.getSrcValue(I.getOperand(1)))); 4026} 4027 4028void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 4029 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 4030 getValue(I.getOperand(0)), 4031 DAG.getSrcValue(I.getOperand(0))); 4032 setValue(&I, V); 4033 DAG.setRoot(V.getValue(1)); 4034} 4035 4036void SelectionDAGLowering::visitVAEnd(CallInst &I) { 4037 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 4038 getValue(I.getOperand(1)), 4039 DAG.getSrcValue(I.getOperand(1)))); 4040} 4041 4042void SelectionDAGLowering::visitVACopy(CallInst &I) { 4043 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 4044 getValue(I.getOperand(1)), 4045 getValue(I.getOperand(2)), 4046 DAG.getSrcValue(I.getOperand(1)), 4047 DAG.getSrcValue(I.getOperand(2)))); 4048} 4049 4050/// TargetLowering::LowerArguments - This is the default LowerArguments 4051/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 4052/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 4053/// integrated into SDISel. 4054std::vector<SDOperand> 4055TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 4056 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 4057 std::vector<SDOperand> Ops; 4058 Ops.push_back(DAG.getRoot()); 4059 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 4060 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 4061 4062 // Add one result value for each formal argument. 4063 std::vector<MVT::ValueType> RetVals; 4064 unsigned j = 1; 4065 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 4066 I != E; ++I, ++j) { 4067 MVT::ValueType VT = getValueType(I->getType()); 4068 ISD::ParamFlags::ParamFlagsTy Flags = ISD::ParamFlags::NoFlagSet; 4069 unsigned OriginalAlignment = 4070 getTargetData()->getABITypeAlignment(I->getType()); 4071 4072 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 4073 // that is zero extended! 4074 if (F.paramHasAttr(j, ParamAttr::ZExt)) 4075 Flags &= ~(ISD::ParamFlags::SExt); 4076 if (F.paramHasAttr(j, ParamAttr::SExt)) 4077 Flags |= ISD::ParamFlags::SExt; 4078 if (F.paramHasAttr(j, ParamAttr::InReg)) 4079 Flags |= ISD::ParamFlags::InReg; 4080 if (F.paramHasAttr(j, ParamAttr::StructRet)) 4081 Flags |= ISD::ParamFlags::StructReturn; 4082 if (F.paramHasAttr(j, ParamAttr::ByVal)) { 4083 Flags |= ISD::ParamFlags::ByVal; 4084 const PointerType *Ty = cast<PointerType>(I->getType()); 4085 const Type *ElementTy = Ty->getElementType(); 4086 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy)); 4087 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); 4088 // For ByVal, alignment should be passed from FE. BE will guess if 4089 // this info is not there but there are cases it cannot get right. 4090 if (F.getParamAlignment(j)) 4091 FrameAlign = Log2_32(F.getParamAlignment(j)); 4092 Flags |= ((ISD::ParamFlags::ParamFlagsTy)FrameAlign 4093 << ISD::ParamFlags::ByValAlignOffs); 4094 Flags |= ((ISD::ParamFlags::ParamFlagsTy)FrameSize 4095 << ISD::ParamFlags::ByValSizeOffs); 4096 } 4097 if (F.paramHasAttr(j, ParamAttr::Nest)) 4098 Flags |= ISD::ParamFlags::Nest; 4099 Flags |= ((ISD::ParamFlags::ParamFlagsTy)OriginalAlignment 4100 << ISD::ParamFlags::OrigAlignmentOffs); 4101 4102 MVT::ValueType RegisterVT = getRegisterType(VT); 4103 unsigned NumRegs = getNumRegisters(VT); 4104 for (unsigned i = 0; i != NumRegs; ++i) { 4105 RetVals.push_back(RegisterVT); 4106 // if it isn't first piece, alignment must be 1 4107 if (i > 0) 4108 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 4109 (ISD::ParamFlags::One << ISD::ParamFlags::OrigAlignmentOffs); 4110 Ops.push_back(DAG.getConstant(Flags, MVT::i64)); 4111 } 4112 } 4113 4114 RetVals.push_back(MVT::Other); 4115 4116 // Create the node. 4117 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 4118 DAG.getVTList(&RetVals[0], RetVals.size()), 4119 &Ops[0], Ops.size()).Val; 4120 4121 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but 4122 // allows exposing the loads that may be part of the argument access to the 4123 // first DAGCombiner pass. 4124 SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG); 4125 4126 // The number of results should match up, except that the lowered one may have 4127 // an extra flag result. 4128 assert((Result->getNumValues() == TmpRes.Val->getNumValues() || 4129 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() && 4130 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag)) 4131 && "Lowering produced unexpected number of results!"); 4132 Result = TmpRes.Val; 4133 4134 unsigned NumArgRegs = Result->getNumValues() - 1; 4135 DAG.setRoot(SDOperand(Result, NumArgRegs)); 4136 4137 // Set up the return result vector. 4138 Ops.clear(); 4139 unsigned i = 0; 4140 unsigned Idx = 1; 4141 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 4142 ++I, ++Idx) { 4143 MVT::ValueType VT = getValueType(I->getType()); 4144 MVT::ValueType PartVT = getRegisterType(VT); 4145 4146 unsigned NumParts = getNumRegisters(VT); 4147 SmallVector<SDOperand, 4> Parts(NumParts); 4148 for (unsigned j = 0; j != NumParts; ++j) 4149 Parts[j] = SDOperand(Result, i++); 4150 4151 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4152 if (F.paramHasAttr(Idx, ParamAttr::SExt)) 4153 AssertOp = ISD::AssertSext; 4154 else if (F.paramHasAttr(Idx, ParamAttr::ZExt)) 4155 AssertOp = ISD::AssertZext; 4156 4157 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT, 4158 AssertOp)); 4159 } 4160 assert(i == NumArgRegs && "Argument register count mismatch!"); 4161 return Ops; 4162} 4163 4164 4165/// TargetLowering::LowerCallTo - This is the default LowerCallTo 4166/// implementation, which just inserts an ISD::CALL node, which is later custom 4167/// lowered by the target to something concrete. FIXME: When all targets are 4168/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 4169std::pair<SDOperand, SDOperand> 4170TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 4171 bool RetSExt, bool RetZExt, bool isVarArg, 4172 unsigned CallingConv, bool isTailCall, 4173 SDOperand Callee, 4174 ArgListTy &Args, SelectionDAG &DAG) { 4175 SmallVector<SDOperand, 32> Ops; 4176 Ops.push_back(Chain); // Op#0 - Chain 4177 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 4178 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 4179 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 4180 Ops.push_back(Callee); 4181 4182 // Handle all of the outgoing arguments. 4183 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 4184 MVT::ValueType VT = getValueType(Args[i].Ty); 4185 SDOperand Op = Args[i].Node; 4186 ISD::ParamFlags::ParamFlagsTy Flags = ISD::ParamFlags::NoFlagSet; 4187 unsigned OriginalAlignment = 4188 getTargetData()->getABITypeAlignment(Args[i].Ty); 4189 4190 if (Args[i].isSExt) 4191 Flags |= ISD::ParamFlags::SExt; 4192 if (Args[i].isZExt) 4193 Flags |= ISD::ParamFlags::ZExt; 4194 if (Args[i].isInReg) 4195 Flags |= ISD::ParamFlags::InReg; 4196 if (Args[i].isSRet) 4197 Flags |= ISD::ParamFlags::StructReturn; 4198 if (Args[i].isByVal) { 4199 Flags |= ISD::ParamFlags::ByVal; 4200 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 4201 const Type *ElementTy = Ty->getElementType(); 4202 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy)); 4203 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); 4204 // For ByVal, alignment should come from FE. BE will guess if this 4205 // info is not there but there are cases it cannot get right. 4206 if (Args[i].Alignment) 4207 FrameAlign = Log2_32(Args[i].Alignment); 4208 Flags |= ((ISD::ParamFlags::ParamFlagsTy)FrameAlign 4209 << ISD::ParamFlags::ByValAlignOffs); 4210 Flags |= ((ISD::ParamFlags::ParamFlagsTy)FrameSize 4211 << ISD::ParamFlags::ByValSizeOffs); 4212 } 4213 if (Args[i].isNest) 4214 Flags |= ISD::ParamFlags::Nest; 4215 Flags |= ((ISD::ParamFlags::ParamFlagsTy)OriginalAlignment) 4216 << ISD::ParamFlags::OrigAlignmentOffs; 4217 4218 MVT::ValueType PartVT = getRegisterType(VT); 4219 unsigned NumParts = getNumRegisters(VT); 4220 SmallVector<SDOperand, 4> Parts(NumParts); 4221 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 4222 4223 if (Args[i].isSExt) 4224 ExtendKind = ISD::SIGN_EXTEND; 4225 else if (Args[i].isZExt) 4226 ExtendKind = ISD::ZERO_EXTEND; 4227 4228 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind); 4229 4230 for (unsigned i = 0; i != NumParts; ++i) { 4231 // if it isn't first piece, alignment must be 1 4232 ISD::ParamFlags::ParamFlagsTy MyFlags = Flags; 4233 if (i != 0) 4234 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) | 4235 (ISD::ParamFlags::One << ISD::ParamFlags::OrigAlignmentOffs); 4236 4237 Ops.push_back(Parts[i]); 4238 Ops.push_back(DAG.getConstant(MyFlags, MVT::i64)); 4239 } 4240 } 4241 4242 // Figure out the result value types. We start by making a list of 4243 // the high-level LLVM return types. 4244 SmallVector<const Type *, 4> LLVMRetTys; 4245 if (const StructType *ST = dyn_cast<StructType>(RetTy)) 4246 // A struct return type in the LLVM IR means we have multiple return values. 4247 LLVMRetTys.insert(LLVMRetTys.end(), ST->element_begin(), ST->element_end()); 4248 else 4249 LLVMRetTys.push_back(RetTy); 4250 4251 // Then we translate that to a list of lowered codegen result types. 4252 SmallVector<MVT::ValueType, 4> LoweredRetTys; 4253 SmallVector<MVT::ValueType, 4> RetTys; 4254 for (unsigned I = 0, E = LLVMRetTys.size(); I != E; ++I) { 4255 MVT::ValueType VT = getValueType(LLVMRetTys[I]); 4256 RetTys.push_back(VT); 4257 4258 MVT::ValueType RegisterVT = getRegisterType(VT); 4259 unsigned NumRegs = getNumRegisters(VT); 4260 for (unsigned i = 0; i != NumRegs; ++i) 4261 LoweredRetTys.push_back(RegisterVT); 4262 } 4263 4264 LoweredRetTys.push_back(MVT::Other); // Always has a chain. 4265 4266 // Create the CALL node. 4267 SDOperand Res = DAG.getNode(ISD::CALL, 4268 DAG.getVTList(&LoweredRetTys[0], 4269 LoweredRetTys.size()), 4270 &Ops[0], Ops.size()); 4271 Chain = Res.getValue(LoweredRetTys.size() - 1); 4272 4273 // Gather up the call result into a single value. 4274 if (RetTy != Type::VoidTy) { 4275 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4276 4277 if (RetSExt) 4278 AssertOp = ISD::AssertSext; 4279 else if (RetZExt) 4280 AssertOp = ISD::AssertZext; 4281 4282 SmallVector<SDOperand, 4> ReturnValues; 4283 unsigned RegNo = 0; 4284 for (unsigned I = 0, E = LLVMRetTys.size(); I != E; ++I) { 4285 MVT::ValueType VT = getValueType(LLVMRetTys[I]); 4286 MVT::ValueType RegisterVT = getRegisterType(VT); 4287 unsigned NumRegs = getNumRegisters(VT); 4288 unsigned RegNoEnd = NumRegs + RegNo; 4289 SmallVector<SDOperand, 4> Results; 4290 for (; RegNo != RegNoEnd; ++RegNo) 4291 Results.push_back(Res.getValue(RegNo)); 4292 SDOperand ReturnValue = 4293 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, 4294 AssertOp); 4295 ReturnValues.push_back(ReturnValue); 4296 } 4297 Res = ReturnValues.size() == 1 ? ReturnValues.front() : 4298 DAG.getNode(ISD::MERGE_VALUES, 4299 DAG.getVTList(&RetTys[0], RetTys.size()), 4300 &ReturnValues[0], ReturnValues.size()); 4301 } 4302 4303 return std::make_pair(Res, Chain); 4304} 4305 4306SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4307 assert(0 && "LowerOperation not implemented for this target!"); 4308 abort(); 4309 return SDOperand(); 4310} 4311 4312SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 4313 SelectionDAG &DAG) { 4314 assert(0 && "CustomPromoteOperation not implemented for this target!"); 4315 abort(); 4316 return SDOperand(); 4317} 4318 4319/// getMemsetValue - Vectorized representation of the memset value 4320/// operand. 4321static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 4322 SelectionDAG &DAG) { 4323 MVT::ValueType CurVT = VT; 4324 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 4325 uint64_t Val = C->getValue() & 255; 4326 unsigned Shift = 8; 4327 while (CurVT != MVT::i8) { 4328 Val = (Val << Shift) | Val; 4329 Shift <<= 1; 4330 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4331 } 4332 return DAG.getConstant(Val, VT); 4333 } else { 4334 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4335 unsigned Shift = 8; 4336 while (CurVT != MVT::i8) { 4337 Value = 4338 DAG.getNode(ISD::OR, VT, 4339 DAG.getNode(ISD::SHL, VT, Value, 4340 DAG.getConstant(Shift, MVT::i8)), Value); 4341 Shift <<= 1; 4342 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4343 } 4344 4345 return Value; 4346 } 4347} 4348 4349/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4350/// used when a memcpy is turned into a memset when the source is a constant 4351/// string ptr. 4352static SDOperand getMemsetStringVal(MVT::ValueType VT, 4353 SelectionDAG &DAG, TargetLowering &TLI, 4354 std::string &Str, unsigned Offset) { 4355 uint64_t Val = 0; 4356 unsigned MSB = MVT::getSizeInBits(VT) / 8; 4357 if (TLI.isLittleEndian()) 4358 Offset = Offset + MSB - 1; 4359 for (unsigned i = 0; i != MSB; ++i) { 4360 Val = (Val << 8) | (unsigned char)Str[Offset]; 4361 Offset += TLI.isLittleEndian() ? -1 : 1; 4362 } 4363 return DAG.getConstant(Val, VT); 4364} 4365 4366/// getMemBasePlusOffset - Returns base and offset node for the 4367static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4368 SelectionDAG &DAG, TargetLowering &TLI) { 4369 MVT::ValueType VT = Base.getValueType(); 4370 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4371} 4372 4373/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4374/// to replace the memset / memcpy is below the threshold. It also returns the 4375/// types of the sequence of memory ops to perform memset / memcpy. 4376static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4377 unsigned Limit, uint64_t Size, 4378 unsigned Align, TargetLowering &TLI) { 4379 MVT::ValueType VT; 4380 4381 if (TLI.allowsUnalignedMemoryAccesses()) { 4382 VT = MVT::i64; 4383 } else { 4384 switch (Align & 7) { 4385 case 0: 4386 VT = MVT::i64; 4387 break; 4388 case 4: 4389 VT = MVT::i32; 4390 break; 4391 case 2: 4392 VT = MVT::i16; 4393 break; 4394 default: 4395 VT = MVT::i8; 4396 break; 4397 } 4398 } 4399 4400 MVT::ValueType LVT = MVT::i64; 4401 while (!TLI.isTypeLegal(LVT)) 4402 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4403 assert(MVT::isInteger(LVT)); 4404 4405 if (VT > LVT) 4406 VT = LVT; 4407 4408 unsigned NumMemOps = 0; 4409 while (Size != 0) { 4410 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4411 while (VTSize > Size) { 4412 VT = (MVT::ValueType)((unsigned)VT - 1); 4413 VTSize >>= 1; 4414 } 4415 assert(MVT::isInteger(VT)); 4416 4417 if (++NumMemOps > Limit) 4418 return false; 4419 MemOps.push_back(VT); 4420 Size -= VTSize; 4421 } 4422 4423 return true; 4424} 4425 4426void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4427 SDOperand Op1 = getValue(I.getOperand(1)); 4428 SDOperand Op2 = getValue(I.getOperand(2)); 4429 SDOperand Op3 = getValue(I.getOperand(3)); 4430 SDOperand Op4 = getValue(I.getOperand(4)); 4431 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4432 if (Align == 0) Align = 1; 4433 4434 // If the source and destination are known to not be aliases, we can 4435 // lower memmove as memcpy. 4436 if (Op == ISD::MEMMOVE) { 4437 uint64_t Size = -1ULL; 4438 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 4439 Size = C->getValue(); 4440 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) == 4441 AliasAnalysis::NoAlias) 4442 Op = ISD::MEMCPY; 4443 } 4444 4445 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4446 std::vector<MVT::ValueType> MemOps; 4447 4448 // Expand memset / memcpy to a series of load / store ops 4449 // if the size operand falls below a certain threshold. 4450 SmallVector<SDOperand, 8> OutChains; 4451 switch (Op) { 4452 default: break; // Do nothing for now. 4453 case ISD::MEMSET: { 4454 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4455 Size->getValue(), Align, TLI)) { 4456 unsigned NumMemOps = MemOps.size(); 4457 unsigned Offset = 0; 4458 for (unsigned i = 0; i < NumMemOps; i++) { 4459 MVT::ValueType VT = MemOps[i]; 4460 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4461 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4462 SDOperand Store = DAG.getStore(getRoot(), Value, 4463 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4464 I.getOperand(1), Offset); 4465 OutChains.push_back(Store); 4466 Offset += VTSize; 4467 } 4468 } 4469 break; 4470 } 4471 case ISD::MEMCPY: { 4472 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4473 Size->getValue(), Align, TLI)) { 4474 unsigned NumMemOps = MemOps.size(); 4475 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4476 GlobalAddressSDNode *G = NULL; 4477 std::string Str; 4478 bool CopyFromStr = false; 4479 4480 if (Op2.getOpcode() == ISD::GlobalAddress) 4481 G = cast<GlobalAddressSDNode>(Op2); 4482 else if (Op2.getOpcode() == ISD::ADD && 4483 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4484 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4485 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4486 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4487 } 4488 if (G) { 4489 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4490 if (GV && GV->isConstant()) { 4491 Str = GV->getStringValue(false); 4492 if (!Str.empty()) { 4493 CopyFromStr = true; 4494 SrcOff += SrcDelta; 4495 } 4496 } 4497 } 4498 4499 for (unsigned i = 0; i < NumMemOps; i++) { 4500 MVT::ValueType VT = MemOps[i]; 4501 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4502 SDOperand Value, Chain, Store; 4503 4504 if (CopyFromStr) { 4505 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4506 Chain = getRoot(); 4507 Store = 4508 DAG.getStore(Chain, Value, 4509 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4510 I.getOperand(1), DstOff); 4511 } else { 4512 Value = DAG.getLoad(VT, getRoot(), 4513 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4514 I.getOperand(2), SrcOff, false, Align); 4515 Chain = Value.getValue(1); 4516 Store = 4517 DAG.getStore(Chain, Value, 4518 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4519 I.getOperand(1), DstOff, false, Align); 4520 } 4521 OutChains.push_back(Store); 4522 SrcOff += VTSize; 4523 DstOff += VTSize; 4524 } 4525 } 4526 break; 4527 } 4528 } 4529 4530 if (!OutChains.empty()) { 4531 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4532 &OutChains[0], OutChains.size())); 4533 return; 4534 } 4535 } 4536 4537 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1); 4538 SDOperand Node; 4539 switch(Op) { 4540 default: 4541 assert(0 && "Unknown Op"); 4542 case ISD::MEMCPY: 4543 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4544 break; 4545 case ISD::MEMMOVE: 4546 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4547 break; 4548 case ISD::MEMSET: 4549 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4550 break; 4551 } 4552 DAG.setRoot(Node); 4553} 4554 4555//===----------------------------------------------------------------------===// 4556// SelectionDAGISel code 4557//===----------------------------------------------------------------------===// 4558 4559unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4560 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 4561} 4562 4563void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4564 AU.addRequired<AliasAnalysis>(); 4565 AU.addRequired<CollectorModuleMetadata>(); 4566 AU.setPreservesAll(); 4567} 4568 4569 4570 4571bool SelectionDAGISel::runOnFunction(Function &Fn) { 4572 // Get alias analysis for load/store combining. 4573 AA = &getAnalysis<AliasAnalysis>(); 4574 4575 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4576 if (MF.getFunction()->hasCollector()) 4577 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction()); 4578 else 4579 GCI = 0; 4580 RegInfo = &MF.getRegInfo(); 4581 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4582 4583 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4584 4585 if (ExceptionHandling) 4586 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4587 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4588 // Mark landing pad. 4589 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4590 4591 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4592 SelectBasicBlock(I, MF, FuncInfo); 4593 4594 // Add function live-ins to entry block live-in set. 4595 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4596 BB = FuncInfo.MBBMap[EntryBB]; 4597 if (!RegInfo->livein_empty()) 4598 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 4599 E = RegInfo->livein_end(); I != E; ++I) 4600 BB->addLiveIn(I->first); 4601 4602#ifndef NDEBUG 4603 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4604 "Not all catch info was assigned to a landing pad!"); 4605#endif 4606 4607 return true; 4608} 4609 4610SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4611 unsigned Reg) { 4612 SDOperand Op = getValue(V); 4613 assert((Op.getOpcode() != ISD::CopyFromReg || 4614 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4615 "Copy from a reg to the same reg!"); 4616 4617 MVT::ValueType SrcVT = Op.getValueType(); 4618 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT); 4619 unsigned NumRegs = TLI.getNumRegisters(SrcVT); 4620 SmallVector<SDOperand, 8> Regs(NumRegs); 4621 SmallVector<SDOperand, 8> Chains(NumRegs); 4622 4623 // Copy the value by legal parts into sequential virtual registers. 4624 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT); 4625 for (unsigned i = 0; i != NumRegs; ++i) 4626 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); 4627 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 4628} 4629 4630void SelectionDAGISel:: 4631LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4632 std::vector<SDOperand> &UnorderedChains) { 4633 // If this is the entry block, emit arguments. 4634 Function &F = *LLVMBB->getParent(); 4635 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4636 SDOperand OldRoot = SDL.DAG.getRoot(); 4637 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4638 4639 unsigned a = 0; 4640 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4641 AI != E; ++AI, ++a) 4642 if (!AI->use_empty()) { 4643 SDL.setValue(AI, Args[a]); 4644 4645 // If this argument is live outside of the entry block, insert a copy from 4646 // whereever we got it to the vreg that other BB's will reference it as. 4647 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4648 if (VMI != FuncInfo.ValueMap.end()) { 4649 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4650 UnorderedChains.push_back(Copy); 4651 } 4652 } 4653 4654 // Finally, if the target has anything special to do, allow it to do so. 4655 // FIXME: this should insert code into the DAG! 4656 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4657} 4658 4659static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4660 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4661 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4662 if (isSelector(I)) { 4663 // Apply the catch info to DestBB. 4664 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4665#ifndef NDEBUG 4666 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 4667 FLI.CatchInfoFound.insert(I); 4668#endif 4669 } 4670} 4671 4672/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 4673/// DAG and fixes their tailcall attribute operand. 4674static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 4675 TargetLowering& TLI) { 4676 SDNode * Ret = NULL; 4677 SDOperand Terminator = DAG.getRoot(); 4678 4679 // Find RET node. 4680 if (Terminator.getOpcode() == ISD::RET) { 4681 Ret = Terminator.Val; 4682 } 4683 4684 // Fix tail call attribute of CALL nodes. 4685 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 4686 BI = prior(DAG.allnodes_end()); BI != BE; --BI) { 4687 if (BI->getOpcode() == ISD::CALL) { 4688 SDOperand OpRet(Ret, 0); 4689 SDOperand OpCall(static_cast<SDNode*>(BI), 0); 4690 bool isMarkedTailCall = 4691 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0; 4692 // If CALL node has tail call attribute set to true and the call is not 4693 // eligible (no RET or the target rejects) the attribute is fixed to 4694 // false. The TargetLowering::IsEligibleForTailCallOptimization function 4695 // must correctly identify tail call optimizable calls. 4696 if (isMarkedTailCall && 4697 (Ret==NULL || 4698 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) { 4699 SmallVector<SDOperand, 32> Ops; 4700 unsigned idx=0; 4701 for(SDNode::op_iterator I =OpCall.Val->op_begin(), 4702 E=OpCall.Val->op_end(); I!=E; I++, idx++) { 4703 if (idx!=3) 4704 Ops.push_back(*I); 4705 else 4706 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy())); 4707 } 4708 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 4709 } 4710 } 4711 } 4712} 4713 4714void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4715 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4716 FunctionLoweringInfo &FuncInfo) { 4717 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI); 4718 4719 std::vector<SDOperand> UnorderedChains; 4720 4721 // Lower any arguments needed in this block if this is the entry block. 4722 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4723 LowerArguments(LLVMBB, SDL, UnorderedChains); 4724 4725 BB = FuncInfo.MBBMap[LLVMBB]; 4726 SDL.setCurrentBasicBlock(BB); 4727 4728 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4729 4730 if (ExceptionHandling && MMI && BB->isLandingPad()) { 4731 // Add a label to mark the beginning of the landing pad. Deletion of the 4732 // landing pad can thus be detected via the MachineModuleInfo. 4733 unsigned LabelID = MMI->addLandingPad(BB); 4734 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 4735 DAG.getConstant(LabelID, MVT::i32), 4736 DAG.getConstant(1, MVT::i32))); 4737 4738 // Mark exception register as live in. 4739 unsigned Reg = TLI.getExceptionAddressRegister(); 4740 if (Reg) BB->addLiveIn(Reg); 4741 4742 // Mark exception selector register as live in. 4743 Reg = TLI.getExceptionSelectorRegister(); 4744 if (Reg) BB->addLiveIn(Reg); 4745 4746 // FIXME: Hack around an exception handling flaw (PR1508): the personality 4747 // function and list of typeids logically belong to the invoke (or, if you 4748 // like, the basic block containing the invoke), and need to be associated 4749 // with it in the dwarf exception handling tables. Currently however the 4750 // information is provided by an intrinsic (eh.selector) that can be moved 4751 // to unexpected places by the optimizers: if the unwind edge is critical, 4752 // then breaking it can result in the intrinsics being in the successor of 4753 // the landing pad, not the landing pad itself. This results in exceptions 4754 // not being caught because no typeids are associated with the invoke. 4755 // This may not be the only way things can go wrong, but it is the only way 4756 // we try to work around for the moment. 4757 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 4758 4759 if (Br && Br->isUnconditional()) { // Critical edge? 4760 BasicBlock::iterator I, E; 4761 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 4762 if (isSelector(I)) 4763 break; 4764 4765 if (I == E) 4766 // No catch info found - try to extract some from the successor. 4767 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 4768 } 4769 } 4770 4771 // Lower all of the non-terminator instructions. 4772 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4773 I != E; ++I) 4774 SDL.visit(*I); 4775 4776 // Ensure that all instructions which are used outside of their defining 4777 // blocks are available as virtual registers. Invoke is handled elsewhere. 4778 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4779 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 4780 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4781 if (VMI != FuncInfo.ValueMap.end()) 4782 UnorderedChains.push_back( 4783 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4784 } 4785 4786 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4787 // ensure constants are generated when needed. Remember the virtual registers 4788 // that need to be added to the Machine PHI nodes as input. We cannot just 4789 // directly add them, because expansion might result in multiple MBB's for one 4790 // BB. As such, the start of the BB might correspond to a different MBB than 4791 // the end. 4792 // 4793 TerminatorInst *TI = LLVMBB->getTerminator(); 4794 4795 // Emit constants only once even if used by multiple PHI nodes. 4796 std::map<Constant*, unsigned> ConstantsOut; 4797 4798 // Vector bool would be better, but vector<bool> is really slow. 4799 std::vector<unsigned char> SuccsHandled; 4800 if (TI->getNumSuccessors()) 4801 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4802 4803 // Check successor nodes' PHI nodes that expect a constant to be available 4804 // from this block. 4805 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4806 BasicBlock *SuccBB = TI->getSuccessor(succ); 4807 if (!isa<PHINode>(SuccBB->begin())) continue; 4808 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4809 4810 // If this terminator has multiple identical successors (common for 4811 // switches), only handle each succ once. 4812 unsigned SuccMBBNo = SuccMBB->getNumber(); 4813 if (SuccsHandled[SuccMBBNo]) continue; 4814 SuccsHandled[SuccMBBNo] = true; 4815 4816 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4817 PHINode *PN; 4818 4819 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4820 // nodes and Machine PHI nodes, but the incoming operands have not been 4821 // emitted yet. 4822 for (BasicBlock::iterator I = SuccBB->begin(); 4823 (PN = dyn_cast<PHINode>(I)); ++I) { 4824 // Ignore dead phi's. 4825 if (PN->use_empty()) continue; 4826 4827 unsigned Reg; 4828 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4829 4830 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4831 unsigned &RegOut = ConstantsOut[C]; 4832 if (RegOut == 0) { 4833 RegOut = FuncInfo.CreateRegForValue(C); 4834 UnorderedChains.push_back( 4835 SDL.CopyValueToVirtualRegister(C, RegOut)); 4836 } 4837 Reg = RegOut; 4838 } else { 4839 Reg = FuncInfo.ValueMap[PHIOp]; 4840 if (Reg == 0) { 4841 assert(isa<AllocaInst>(PHIOp) && 4842 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4843 "Didn't codegen value into a register!??"); 4844 Reg = FuncInfo.CreateRegForValue(PHIOp); 4845 UnorderedChains.push_back( 4846 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4847 } 4848 } 4849 4850 // Remember that this register needs to added to the machine PHI node as 4851 // the input for this MBB. 4852 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4853 unsigned NumRegisters = TLI.getNumRegisters(VT); 4854 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 4855 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4856 } 4857 } 4858 ConstantsOut.clear(); 4859 4860 // Turn all of the unordered chains into one factored node. 4861 if (!UnorderedChains.empty()) { 4862 SDOperand Root = SDL.getRoot(); 4863 if (Root.getOpcode() != ISD::EntryToken) { 4864 unsigned i = 0, e = UnorderedChains.size(); 4865 for (; i != e; ++i) { 4866 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4867 if (UnorderedChains[i].Val->getOperand(0) == Root) 4868 break; // Don't add the root if we already indirectly depend on it. 4869 } 4870 4871 if (i == e) 4872 UnorderedChains.push_back(Root); 4873 } 4874 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4875 &UnorderedChains[0], UnorderedChains.size())); 4876 } 4877 4878 // Lower the terminator after the copies are emitted. 4879 SDL.visit(*LLVMBB->getTerminator()); 4880 4881 // Copy over any CaseBlock records that may now exist due to SwitchInst 4882 // lowering, as well as any jump table information. 4883 SwitchCases.clear(); 4884 SwitchCases = SDL.SwitchCases; 4885 JTCases.clear(); 4886 JTCases = SDL.JTCases; 4887 BitTestCases.clear(); 4888 BitTestCases = SDL.BitTestCases; 4889 4890 // Make sure the root of the DAG is up-to-date. 4891 DAG.setRoot(SDL.getRoot()); 4892 4893 // Check whether calls in this block are real tail calls. Fix up CALL nodes 4894 // with correct tailcall attribute so that the target can rely on the tailcall 4895 // attribute indicating whether the call is really eligible for tail call 4896 // optimization. 4897 CheckDAGForTailCallsAndFixThem(DAG, TLI); 4898} 4899 4900void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4901 DOUT << "Lowered selection DAG:\n"; 4902 DEBUG(DAG.dump()); 4903 4904 // Run the DAG combiner in pre-legalize mode. 4905 DAG.Combine(false, *AA); 4906 4907 DOUT << "Optimized lowered selection DAG:\n"; 4908 DEBUG(DAG.dump()); 4909 4910 // Second step, hack on the DAG until it only uses operations and types that 4911 // the target supports. 4912#if 0 // Enable this some day. 4913 DAG.LegalizeTypes(); 4914 // Someday even later, enable a dag combine pass here. 4915#endif 4916 DAG.Legalize(); 4917 4918 DOUT << "Legalized selection DAG:\n"; 4919 DEBUG(DAG.dump()); 4920 4921 // Run the DAG combiner in post-legalize mode. 4922 DAG.Combine(true, *AA); 4923 4924 DOUT << "Optimized legalized selection DAG:\n"; 4925 DEBUG(DAG.dump()); 4926 4927 if (ViewISelDAGs) DAG.viewGraph(); 4928 4929 // Third, instruction select all of the operations to machine code, adding the 4930 // code to the MachineBasicBlock. 4931 InstructionSelectBasicBlock(DAG); 4932 4933 DOUT << "Selected machine code:\n"; 4934 DEBUG(BB->dump()); 4935} 4936 4937void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4938 FunctionLoweringInfo &FuncInfo) { 4939 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4940 { 4941 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4942 CurDAG = &DAG; 4943 4944 // First step, lower LLVM code to some DAG. This DAG may use operations and 4945 // types that are not supported by the target. 4946 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4947 4948 // Second step, emit the lowered DAG as machine code. 4949 CodeGenAndEmitDAG(DAG); 4950 } 4951 4952 DOUT << "Total amount of phi nodes to update: " 4953 << PHINodesToUpdate.size() << "\n"; 4954 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4955 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4956 << ", " << PHINodesToUpdate[i].second << ")\n";); 4957 4958 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4959 // PHI nodes in successors. 4960 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4961 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4962 MachineInstr *PHI = PHINodesToUpdate[i].first; 4963 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4964 "This is not a machine PHI node that we are updating!"); 4965 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 4966 false)); 4967 PHI->addOperand(MachineOperand::CreateMBB(BB)); 4968 } 4969 return; 4970 } 4971 4972 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4973 // Lower header first, if it wasn't already lowered 4974 if (!BitTestCases[i].Emitted) { 4975 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4976 CurDAG = &HSDAG; 4977 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); 4978 // Set the current basic block to the mbb we wish to insert the code into 4979 BB = BitTestCases[i].Parent; 4980 HSDL.setCurrentBasicBlock(BB); 4981 // Emit the code 4982 HSDL.visitBitTestHeader(BitTestCases[i]); 4983 HSDAG.setRoot(HSDL.getRoot()); 4984 CodeGenAndEmitDAG(HSDAG); 4985 } 4986 4987 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4988 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4989 CurDAG = &BSDAG; 4990 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI); 4991 // Set the current basic block to the mbb we wish to insert the code into 4992 BB = BitTestCases[i].Cases[j].ThisBB; 4993 BSDL.setCurrentBasicBlock(BB); 4994 // Emit the code 4995 if (j+1 != ej) 4996 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 4997 BitTestCases[i].Reg, 4998 BitTestCases[i].Cases[j]); 4999 else 5000 BSDL.visitBitTestCase(BitTestCases[i].Default, 5001 BitTestCases[i].Reg, 5002 BitTestCases[i].Cases[j]); 5003 5004 5005 BSDAG.setRoot(BSDL.getRoot()); 5006 CodeGenAndEmitDAG(BSDAG); 5007 } 5008 5009 // Update PHI Nodes 5010 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 5011 MachineInstr *PHI = PHINodesToUpdate[pi].first; 5012 MachineBasicBlock *PHIBB = PHI->getParent(); 5013 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5014 "This is not a machine PHI node that we are updating!"); 5015 // This is "default" BB. We have two jumps to it. From "header" BB and 5016 // from last "case" BB. 5017 if (PHIBB == BitTestCases[i].Default) { 5018 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5019 false)); 5020 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent)); 5021 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5022 false)); 5023 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases. 5024 back().ThisBB)); 5025 } 5026 // One of "cases" BB. 5027 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 5028 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 5029 if (cBB->succ_end() != 5030 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 5031 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5032 false)); 5033 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 5034 } 5035 } 5036 } 5037 } 5038 5039 // If the JumpTable record is filled in, then we need to emit a jump table. 5040 // Updating the PHI nodes is tricky in this case, since we need to determine 5041 // whether the PHI is a successor of the range check MBB or the jump table MBB 5042 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 5043 // Lower header first, if it wasn't already lowered 5044 if (!JTCases[i].first.Emitted) { 5045 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 5046 CurDAG = &HSDAG; 5047 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); 5048 // Set the current basic block to the mbb we wish to insert the code into 5049 BB = JTCases[i].first.HeaderBB; 5050 HSDL.setCurrentBasicBlock(BB); 5051 // Emit the code 5052 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 5053 HSDAG.setRoot(HSDL.getRoot()); 5054 CodeGenAndEmitDAG(HSDAG); 5055 } 5056 5057 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 5058 CurDAG = &JSDAG; 5059 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI); 5060 // Set the current basic block to the mbb we wish to insert the code into 5061 BB = JTCases[i].second.MBB; 5062 JSDL.setCurrentBasicBlock(BB); 5063 // Emit the code 5064 JSDL.visitJumpTable(JTCases[i].second); 5065 JSDAG.setRoot(JSDL.getRoot()); 5066 CodeGenAndEmitDAG(JSDAG); 5067 5068 // Update PHI Nodes 5069 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 5070 MachineInstr *PHI = PHINodesToUpdate[pi].first; 5071 MachineBasicBlock *PHIBB = PHI->getParent(); 5072 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5073 "This is not a machine PHI node that we are updating!"); 5074 // "default" BB. We can go there only from header BB. 5075 if (PHIBB == JTCases[i].second.Default) { 5076 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5077 false)); 5078 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB)); 5079 } 5080 // JT BB. Just iterate over successors here 5081 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 5082 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5083 false)); 5084 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5085 } 5086 } 5087 } 5088 5089 // If the switch block involved a branch to one of the actual successors, we 5090 // need to update PHI nodes in that block. 5091 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 5092 MachineInstr *PHI = PHINodesToUpdate[i].first; 5093 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5094 "This is not a machine PHI node that we are updating!"); 5095 if (BB->isSuccessor(PHI->getParent())) { 5096 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 5097 false)); 5098 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5099 } 5100 } 5101 5102 // If we generated any switch lowering information, build and codegen any 5103 // additional DAGs necessary. 5104 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 5105 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 5106 CurDAG = &SDAG; 5107 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI); 5108 5109 // Set the current basic block to the mbb we wish to insert the code into 5110 BB = SwitchCases[i].ThisBB; 5111 SDL.setCurrentBasicBlock(BB); 5112 5113 // Emit the code 5114 SDL.visitSwitchCase(SwitchCases[i]); 5115 SDAG.setRoot(SDL.getRoot()); 5116 CodeGenAndEmitDAG(SDAG); 5117 5118 // Handle any PHI nodes in successors of this chunk, as if we were coming 5119 // from the original BB before switch expansion. Note that PHI nodes can 5120 // occur multiple times in PHINodesToUpdate. We have to be very careful to 5121 // handle them the right number of times. 5122 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 5123 for (MachineBasicBlock::iterator Phi = BB->begin(); 5124 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 5125 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 5126 for (unsigned pn = 0; ; ++pn) { 5127 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 5128 if (PHINodesToUpdate[pn].first == Phi) { 5129 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn]. 5130 second, false)); 5131 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB)); 5132 break; 5133 } 5134 } 5135 } 5136 5137 // Don't process RHS if same block as LHS. 5138 if (BB == SwitchCases[i].FalseBB) 5139 SwitchCases[i].FalseBB = 0; 5140 5141 // If we haven't handled the RHS, do so now. Otherwise, we're done. 5142 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 5143 SwitchCases[i].FalseBB = 0; 5144 } 5145 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 5146 } 5147} 5148 5149 5150//===----------------------------------------------------------------------===// 5151/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 5152/// target node in the graph. 5153void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 5154 if (ViewSchedDAGs) DAG.viewGraph(); 5155 5156 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 5157 5158 if (!Ctor) { 5159 Ctor = ISHeuristic; 5160 RegisterScheduler::setDefault(Ctor); 5161 } 5162 5163 ScheduleDAG *SL = Ctor(this, &DAG, BB); 5164 BB = SL->Run(); 5165 5166 if (ViewSUnitDAGs) SL->viewGraph(); 5167 5168 delete SL; 5169} 5170 5171 5172HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 5173 return new HazardRecognizer(); 5174} 5175 5176//===----------------------------------------------------------------------===// 5177// Helper functions used by the generated instruction selector. 5178//===----------------------------------------------------------------------===// 5179// Calls to these methods are generated by tblgen. 5180 5181/// CheckAndMask - The isel is trying to match something like (and X, 255). If 5182/// the dag combiner simplified the 255, we still want to match. RHS is the 5183/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 5184/// specified in the .td file (e.g. 255). 5185bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 5186 int64_t DesiredMaskS) const { 5187 const APInt &ActualMask = RHS->getAPIntValue(); 5188 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 5189 5190 // If the actual mask exactly matches, success! 5191 if (ActualMask == DesiredMask) 5192 return true; 5193 5194 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5195 if (ActualMask.intersects(~DesiredMask)) 5196 return false; 5197 5198 // Otherwise, the DAG Combiner may have proven that the value coming in is 5199 // either already zero or is not demanded. Check for known zero input bits. 5200 APInt NeededMask = DesiredMask & ~ActualMask; 5201 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 5202 return true; 5203 5204 // TODO: check to see if missing bits are just not demanded. 5205 5206 // Otherwise, this pattern doesn't match. 5207 return false; 5208} 5209 5210/// CheckOrMask - The isel is trying to match something like (or X, 255). If 5211/// the dag combiner simplified the 255, we still want to match. RHS is the 5212/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 5213/// specified in the .td file (e.g. 255). 5214bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 5215 int64_t DesiredMaskS) const { 5216 const APInt &ActualMask = RHS->getAPIntValue(); 5217 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 5218 5219 // If the actual mask exactly matches, success! 5220 if (ActualMask == DesiredMask) 5221 return true; 5222 5223 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5224 if (ActualMask.intersects(~DesiredMask)) 5225 return false; 5226 5227 // Otherwise, the DAG Combiner may have proven that the value coming in is 5228 // either already zero or is not demanded. Check for known zero input bits. 5229 APInt NeededMask = DesiredMask & ~ActualMask; 5230 5231 APInt KnownZero, KnownOne; 5232 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 5233 5234 // If all the missing bits in the or are already known to be set, match! 5235 if ((NeededMask & KnownOne) == NeededMask) 5236 return true; 5237 5238 // TODO: check to see if missing bits are just not demanded. 5239 5240 // Otherwise, this pattern doesn't match. 5241 return false; 5242} 5243 5244 5245/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 5246/// by tblgen. Others should not call it. 5247void SelectionDAGISel:: 5248SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 5249 std::vector<SDOperand> InOps; 5250 std::swap(InOps, Ops); 5251 5252 Ops.push_back(InOps[0]); // input chain. 5253 Ops.push_back(InOps[1]); // input asm string. 5254 5255 unsigned i = 2, e = InOps.size(); 5256 if (InOps[e-1].getValueType() == MVT::Flag) 5257 --e; // Don't process a flag operand if it is here. 5258 5259 while (i != e) { 5260 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 5261 if ((Flags & 7) != 4 /*MEM*/) { 5262 // Just skip over this operand, copying the operands verbatim. 5263 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 5264 i += (Flags >> 3) + 1; 5265 } else { 5266 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 5267 // Otherwise, this is a memory operand. Ask the target to select it. 5268 std::vector<SDOperand> SelOps; 5269 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 5270 cerr << "Could not match memory address. Inline asm failure!\n"; 5271 exit(1); 5272 } 5273 5274 // Add this to the output node. 5275 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 5276 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 5277 IntPtrTy)); 5278 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 5279 i += 2; 5280 } 5281 } 5282 5283 // Add the flag input back if present. 5284 if (e != InOps.size()) 5285 Ops.push_back(InOps.back()); 5286} 5287 5288char SelectionDAGISel::ID = 0; 5289