SelectionDAGISel.cpp revision 2520864773dcb73d76d297605f4bc41c0cf3fa39
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/CodeGen/FastISel.h" 29#include "llvm/CodeGen/GCStrategy.h" 30#include "llvm/CodeGen/GCMetadata.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetIntrinsicInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/Compiler.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/Timer.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/ADT/Statistic.h" 50#include <algorithm> 51using namespace llvm; 52 53STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 54STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 55 56static cl::opt<bool> 57EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 58 cl::desc("Enable verbose messages in the \"fast\" " 59 "instruction selector")); 60static cl::opt<bool> 61EnableFastISelAbort("fast-isel-abort", cl::Hidden, 62 cl::desc("Enable abort calls when \"fast\" instruction fails")); 63 64#ifndef NDEBUG 65static cl::opt<bool> 66ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 67 cl::desc("Pop up a window to show dags before the first " 68 "dag combine pass")); 69static cl::opt<bool> 70ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 71 cl::desc("Pop up a window to show dags before legalize types")); 72static cl::opt<bool> 73ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 74 cl::desc("Pop up a window to show dags before legalize")); 75static cl::opt<bool> 76ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the second " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before the post legalize types" 82 " dag combine pass")); 83static cl::opt<bool> 84ViewISelDAGs("view-isel-dags", cl::Hidden, 85 cl::desc("Pop up a window to show isel dags as they are selected")); 86static cl::opt<bool> 87ViewSchedDAGs("view-sched-dags", cl::Hidden, 88 cl::desc("Pop up a window to show sched dags as they are processed")); 89static cl::opt<bool> 90ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 91 cl::desc("Pop up a window to show SUnit dags after they are processed")); 92#else 93static const bool ViewDAGCombine1 = false, 94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 95 ViewDAGCombine2 = false, 96 ViewDAGCombineLT = false, 97 ViewISelDAGs = false, ViewSchedDAGs = false, 98 ViewSUnitDAGs = false; 99#endif 100 101//===---------------------------------------------------------------------===// 102/// 103/// RegisterScheduler class - Track the registration of instruction schedulers. 104/// 105//===---------------------------------------------------------------------===// 106MachinePassRegistry RegisterScheduler::Registry; 107 108//===---------------------------------------------------------------------===// 109/// 110/// ISHeuristic command line option for instruction schedulers. 111/// 112//===---------------------------------------------------------------------===// 113static cl::opt<RegisterScheduler::FunctionPassCtor, false, 114 RegisterPassParser<RegisterScheduler> > 115ISHeuristic("pre-RA-sched", 116 cl::init(&createDefaultScheduler), 117 cl::desc("Instruction schedulers available (before register" 118 " allocation):")); 119 120static RegisterScheduler 121defaultListDAGScheduler("default", "Best scheduler for the target", 122 createDefaultScheduler); 123 124namespace llvm { 125 //===--------------------------------------------------------------------===// 126 /// createDefaultScheduler - This creates an instruction scheduler appropriate 127 /// for the target. 128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 129 CodeGenOpt::Level OptLevel) { 130 const TargetLowering &TLI = IS->getTargetLowering(); 131 132 if (OptLevel == CodeGenOpt::None) 133 return createFastDAGScheduler(IS, OptLevel); 134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 135 return createTDListDAGScheduler(IS, OptLevel); 136 assert(TLI.getSchedulingPreference() == 137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 138 return createBURRListDAGScheduler(IS, OptLevel); 139 } 140} 141 142// EmitInstrWithCustomInserter - This method should be implemented by targets 143// that mark instructions with the 'usesCustomInserter' flag. These 144// instructions are special in various ways, which require special support to 145// insert. The specified MachineInstr is created but not inserted into any 146// basic blocks, and this method is called to expand it into a sequence of 147// instructions, potentially also creating new basic blocks and control flow. 148// When new basic blocks are inserted and the edges from MBB to its successors 149// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 150// DenseMap. 151MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 152 MachineBasicBlock *MBB, 153 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 154#ifndef NDEBUG 155 dbgs() << "If a target marks an instruction with " 156 "'usesCustomInserter', it must implement " 157 "TargetLowering::EmitInstrWithCustomInserter!"; 158#endif 159 llvm_unreachable(0); 160 return 0; 161} 162 163//===----------------------------------------------------------------------===// 164// SelectionDAGISel code 165//===----------------------------------------------------------------------===// 166 167SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 169 FuncInfo(new FunctionLoweringInfo(TLI)), 170 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 171 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 172 GFI(), 173 OptLevel(OL), 174 DAGSize(0) 175{} 176 177SelectionDAGISel::~SelectionDAGISel() { 178 delete SDB; 179 delete CurDAG; 180 delete FuncInfo; 181} 182 183void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 184 AU.addRequired<AliasAnalysis>(); 185 AU.addPreserved<AliasAnalysis>(); 186 AU.addRequired<GCModuleInfo>(); 187 AU.addPreserved<GCModuleInfo>(); 188 MachineFunctionPass::getAnalysisUsage(AU); 189} 190 191bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 192 // Do some sanity-checking on the command-line options. 193 assert((!EnableFastISelVerbose || EnableFastISel) && 194 "-fast-isel-verbose requires -fast-isel"); 195 assert((!EnableFastISelAbort || EnableFastISel) && 196 "-fast-isel-abort requires -fast-isel"); 197 198 Function &Fn = *mf.getFunction(); 199 const TargetInstrInfo &TII = *TM.getInstrInfo(); 200 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 201 202 MF = &mf; 203 RegInfo = &MF->getRegInfo(); 204 AA = &getAnalysis<AliasAnalysis>(); 205 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 206 207 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 208 209 CurDAG->init(*MF); 210 FuncInfo->set(Fn, *MF, EnableFastISel); 211 SDB->init(GFI, *AA); 212 213 SelectAllBasicBlocks(Fn, *MF, TII); 214 215 // Release function-specific state. SDB and CurDAG are already cleared 216 // at this point. 217 FuncInfo->clear(); 218 219 // If the first basic block in the function has live ins that need to be 220 // copied into vregs, emit the copies into the top of the block before 221 // emitting the code for the block. 222 RegInfo->EmitLiveInCopies(MF->begin(), TRI, TII); 223 224 return true; 225} 226 227/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 228/// attached with this instruction. 229static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB, 230 FastISel *FastIS, MachineFunction *MF) { 231 DebugLoc DL = I->getDebugLoc(); 232 if (DL.isUnknown()) return; 233 234 SDB->setCurDebugLoc(DL); 235 236 if (FastIS) 237 FastIS->setCurDebugLoc(DL); 238 239 // If the function doesn't have a default debug location yet, set 240 // it. This is kind of a hack. 241 if (MF->getDefaultDebugLoc().isUnknown()) 242 MF->setDefaultDebugLoc(DL); 243} 244 245/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 246static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 247 SDB->setCurDebugLoc(DebugLoc()); 248 if (FastIS) 249 FastIS->setCurDebugLoc(DebugLoc()); 250} 251 252void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 253 BasicBlock::iterator Begin, 254 BasicBlock::iterator End, 255 bool &HadTailCall) { 256 SDB->setCurrentBasicBlock(BB); 257 258 // Lower all of the non-terminator instructions. If a call is emitted 259 // as a tail call, cease emitting nodes for this block. 260 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 261 SetDebugLoc(I, SDB, 0, MF); 262 263 // Visit the instruction. Terminators are handled below. 264 if (!isa<TerminatorInst>(I)) 265 SDB->visit(*I); 266 267 ResetDebugLoc(SDB, 0); 268 } 269 270 if (!SDB->HasTailCall) { 271 // Ensure that all instructions which are used outside of their defining 272 // blocks are available as virtual registers. Invoke is handled elsewhere. 273 for (BasicBlock::iterator I = Begin; I != End; ++I) 274 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 275 SDB->CopyToExportRegsIfNeeded(I); 276 277 // Handle PHI nodes in successor blocks. 278 if (End == LLVMBB->end()) { 279 HandlePHINodesInSuccessorBlocks(LLVMBB); 280 281 // Lower the terminator after the copies are emitted. 282 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF); 283 SDB->visit(*LLVMBB->getTerminator()); 284 ResetDebugLoc(SDB, 0); 285 } 286 } 287 288 // Make sure the root of the DAG is up-to-date. 289 CurDAG->setRoot(SDB->getControlRoot()); 290 291 // Final step, emit the lowered DAG as machine code. 292 CodeGenAndEmitDAG(); 293 HadTailCall = SDB->HasTailCall; 294 SDB->clear(); 295} 296 297namespace { 298/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 299/// nodes from the worklist. 300class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 301 SmallVector<SDNode*, 128> &Worklist; 302 SmallPtrSet<SDNode*, 128> &InWorklist; 303public: 304 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 305 SmallPtrSet<SDNode*, 128> &inwl) 306 : Worklist(wl), InWorklist(inwl) {} 307 308 void RemoveFromWorklist(SDNode *N) { 309 if (!InWorklist.erase(N)) return; 310 311 SmallVector<SDNode*, 128>::iterator I = 312 std::find(Worklist.begin(), Worklist.end(), N); 313 assert(I != Worklist.end() && "Not in worklist"); 314 315 *I = Worklist.back(); 316 Worklist.pop_back(); 317 } 318 319 virtual void NodeDeleted(SDNode *N, SDNode *E) { 320 RemoveFromWorklist(N); 321 } 322 323 virtual void NodeUpdated(SDNode *N) { 324 // Ignore updates. 325 } 326}; 327} 328 329/// TrivialTruncElim - Eliminate some trivial nops that can result from 330/// ShrinkDemandedOps: (trunc (ext n)) -> n. 331static bool TrivialTruncElim(SDValue Op, 332 TargetLowering::TargetLoweringOpt &TLO) { 333 SDValue N0 = Op.getOperand(0); 334 EVT VT = Op.getValueType(); 335 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 336 N0.getOpcode() == ISD::SIGN_EXTEND || 337 N0.getOpcode() == ISD::ANY_EXTEND) && 338 N0.getOperand(0).getValueType() == VT) { 339 return TLO.CombineTo(Op, N0.getOperand(0)); 340 } 341 return false; 342} 343 344/// ShrinkDemandedOps - A late transformation pass that shrink expressions 345/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 346/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 347void SelectionDAGISel::ShrinkDemandedOps() { 348 SmallVector<SDNode*, 128> Worklist; 349 SmallPtrSet<SDNode*, 128> InWorklist; 350 351 // Add all the dag nodes to the worklist. 352 Worklist.reserve(CurDAG->allnodes_size()); 353 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 354 E = CurDAG->allnodes_end(); I != E; ++I) { 355 Worklist.push_back(I); 356 InWorklist.insert(I); 357 } 358 359 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true); 360 while (!Worklist.empty()) { 361 SDNode *N = Worklist.pop_back_val(); 362 InWorklist.erase(N); 363 364 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 365 // Deleting this node may make its operands dead, add them to the worklist 366 // if they aren't already there. 367 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 368 if (InWorklist.insert(N->getOperand(i).getNode())) 369 Worklist.push_back(N->getOperand(i).getNode()); 370 371 CurDAG->DeleteNode(N); 372 continue; 373 } 374 375 // Run ShrinkDemandedOp on scalar binary operations. 376 if (N->getNumValues() != 1 || 377 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 378 continue; 379 380 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 381 APInt Demanded = APInt::getAllOnesValue(BitWidth); 382 APInt KnownZero, KnownOne; 383 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 384 KnownZero, KnownOne, TLO) && 385 (N->getOpcode() != ISD::TRUNCATE || 386 !TrivialTruncElim(SDValue(N, 0), TLO))) 387 continue; 388 389 // Revisit the node. 390 assert(!InWorklist.count(N) && "Already in worklist"); 391 Worklist.push_back(N); 392 InWorklist.insert(N); 393 394 // Replace the old value with the new one. 395 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 396 TLO.Old.getNode()->dump(CurDAG); 397 errs() << "\nWith: "; 398 TLO.New.getNode()->dump(CurDAG); 399 errs() << '\n'); 400 401 if (InWorklist.insert(TLO.New.getNode())) 402 Worklist.push_back(TLO.New.getNode()); 403 404 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 405 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 406 407 if (!TLO.Old.getNode()->use_empty()) continue; 408 409 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 410 i != e; ++i) { 411 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 412 if (OpNode->hasOneUse()) { 413 // Add OpNode to the end of the list to revisit. 414 DeadNodes.RemoveFromWorklist(OpNode); 415 Worklist.push_back(OpNode); 416 InWorklist.insert(OpNode); 417 } 418 } 419 420 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 421 CurDAG->DeleteNode(TLO.Old.getNode()); 422 } 423} 424 425void SelectionDAGISel::ComputeLiveOutVRegInfo() { 426 SmallPtrSet<SDNode*, 128> VisitedNodes; 427 SmallVector<SDNode*, 128> Worklist; 428 429 Worklist.push_back(CurDAG->getRoot().getNode()); 430 431 APInt Mask; 432 APInt KnownZero; 433 APInt KnownOne; 434 435 do { 436 SDNode *N = Worklist.pop_back_val(); 437 438 // If we've already seen this node, ignore it. 439 if (!VisitedNodes.insert(N)) 440 continue; 441 442 // Otherwise, add all chain operands to the worklist. 443 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 444 if (N->getOperand(i).getValueType() == MVT::Other) 445 Worklist.push_back(N->getOperand(i).getNode()); 446 447 // If this is a CopyToReg with a vreg dest, process it. 448 if (N->getOpcode() != ISD::CopyToReg) 449 continue; 450 451 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 452 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 453 continue; 454 455 // Ignore non-scalar or non-integer values. 456 SDValue Src = N->getOperand(2); 457 EVT SrcVT = Src.getValueType(); 458 if (!SrcVT.isInteger() || SrcVT.isVector()) 459 continue; 460 461 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 462 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 463 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 464 465 // Only install this information if it tells us something. 466 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 467 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 468 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 469 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 470 FunctionLoweringInfo::LiveOutInfo &LOI = 471 FuncInfo->LiveOutRegInfo[DestReg]; 472 LOI.NumSignBits = NumSignBits; 473 LOI.KnownOne = KnownOne; 474 LOI.KnownZero = KnownZero; 475 } 476 } while (!Worklist.empty()); 477} 478 479void SelectionDAGISel::CodeGenAndEmitDAG() { 480 std::string GroupName; 481 if (TimePassesIsEnabled) 482 GroupName = "Instruction Selection and Scheduling"; 483 std::string BlockName; 484 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 485 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 486 ViewSUnitDAGs) 487 BlockName = MF->getFunction()->getNameStr() + ":" + 488 BB->getBasicBlock()->getNameStr(); 489 490 DEBUG(dbgs() << "Initial selection DAG:\n"); 491 DEBUG(CurDAG->dump()); 492 493 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 494 495 // Run the DAG combiner in pre-legalize mode. 496 if (TimePassesIsEnabled) { 497 NamedRegionTimer T("DAG Combining 1", GroupName); 498 CurDAG->Combine(Unrestricted, *AA, OptLevel); 499 } else { 500 CurDAG->Combine(Unrestricted, *AA, OptLevel); 501 } 502 503 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 504 DEBUG(CurDAG->dump()); 505 506 // Second step, hack on the DAG until it only uses operations and types that 507 // the target supports. 508 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 509 BlockName); 510 511 bool Changed; 512 if (TimePassesIsEnabled) { 513 NamedRegionTimer T("Type Legalization", GroupName); 514 Changed = CurDAG->LegalizeTypes(); 515 } else { 516 Changed = CurDAG->LegalizeTypes(); 517 } 518 519 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 520 DEBUG(CurDAG->dump()); 521 522 if (Changed) { 523 if (ViewDAGCombineLT) 524 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 525 526 // Run the DAG combiner in post-type-legalize mode. 527 if (TimePassesIsEnabled) { 528 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 529 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 530 } else { 531 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 532 } 533 534 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 535 DEBUG(CurDAG->dump()); 536 } 537 538 if (TimePassesIsEnabled) { 539 NamedRegionTimer T("Vector Legalization", GroupName); 540 Changed = CurDAG->LegalizeVectors(); 541 } else { 542 Changed = CurDAG->LegalizeVectors(); 543 } 544 545 if (Changed) { 546 if (TimePassesIsEnabled) { 547 NamedRegionTimer T("Type Legalization 2", GroupName); 548 CurDAG->LegalizeTypes(); 549 } else { 550 CurDAG->LegalizeTypes(); 551 } 552 553 if (ViewDAGCombineLT) 554 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 555 556 // Run the DAG combiner in post-type-legalize mode. 557 if (TimePassesIsEnabled) { 558 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 559 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 560 } else { 561 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 562 } 563 564 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 565 DEBUG(CurDAG->dump()); 566 } 567 568 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 569 570 if (TimePassesIsEnabled) { 571 NamedRegionTimer T("DAG Legalization", GroupName); 572 CurDAG->Legalize(OptLevel); 573 } else { 574 CurDAG->Legalize(OptLevel); 575 } 576 577 DEBUG(dbgs() << "Legalized selection DAG:\n"); 578 DEBUG(CurDAG->dump()); 579 580 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 581 582 // Run the DAG combiner in post-legalize mode. 583 if (TimePassesIsEnabled) { 584 NamedRegionTimer T("DAG Combining 2", GroupName); 585 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 586 } else { 587 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 588 } 589 590 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 591 DEBUG(CurDAG->dump()); 592 593 if (OptLevel != CodeGenOpt::None) { 594 ShrinkDemandedOps(); 595 ComputeLiveOutVRegInfo(); 596 } 597 598 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 599 600 // Third, instruction select all of the operations to machine code, adding the 601 // code to the MachineBasicBlock. 602 if (TimePassesIsEnabled) { 603 NamedRegionTimer T("Instruction Selection", GroupName); 604 DoInstructionSelection(); 605 } else { 606 DoInstructionSelection(); 607 } 608 609 DEBUG(dbgs() << "Selected selection DAG:\n"); 610 DEBUG(CurDAG->dump()); 611 612 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 613 614 // Schedule machine code. 615 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 616 if (TimePassesIsEnabled) { 617 NamedRegionTimer T("Instruction Scheduling", GroupName); 618 Scheduler->Run(CurDAG, BB, BB->end()); 619 } else { 620 Scheduler->Run(CurDAG, BB, BB->end()); 621 } 622 623 if (ViewSUnitDAGs) Scheduler->viewGraph(); 624 625 // Emit machine code to BB. This can change 'BB' to the last block being 626 // inserted into. 627 if (TimePassesIsEnabled) { 628 NamedRegionTimer T("Instruction Creation", GroupName); 629 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 630 } else { 631 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 632 } 633 634 // Free the scheduler state. 635 if (TimePassesIsEnabled) { 636 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 637 delete Scheduler; 638 } else { 639 delete Scheduler; 640 } 641 642 DEBUG(dbgs() << "Selected machine code:\n"); 643 DEBUG(BB->dump()); 644} 645 646void SelectionDAGISel::DoInstructionSelection() { 647 DEBUG(errs() << "===== Instruction selection begins:\n"); 648 649 PreprocessISelDAG(); 650 651 // Select target instructions for the DAG. 652 { 653 // Number all nodes with a topological order and set DAGSize. 654 DAGSize = CurDAG->AssignTopologicalOrder(); 655 656 // Create a dummy node (which is not added to allnodes), that adds 657 // a reference to the root node, preventing it from being deleted, 658 // and tracking any changes of the root. 659 HandleSDNode Dummy(CurDAG->getRoot()); 660 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 661 ++ISelPosition; 662 663 // The AllNodes list is now topological-sorted. Visit the 664 // nodes by starting at the end of the list (the root of the 665 // graph) and preceding back toward the beginning (the entry 666 // node). 667 while (ISelPosition != CurDAG->allnodes_begin()) { 668 SDNode *Node = --ISelPosition; 669 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 670 // but there are currently some corner cases that it misses. Also, this 671 // makes it theoretically possible to disable the DAGCombiner. 672 if (Node->use_empty()) 673 continue; 674 675 SDNode *ResNode = Select(Node); 676 677 // FIXME: This is pretty gross. 'Select' should be changed to not return 678 // anything at all and this code should be nuked with a tactical strike. 679 680 // If node should not be replaced, continue with the next one. 681 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 682 continue; 683 // Replace node. 684 if (ResNode) 685 ReplaceUses(Node, ResNode); 686 687 // If after the replacement this node is not used any more, 688 // remove this dead node. 689 if (Node->use_empty()) { // Don't delete EntryToken, etc. 690 ISelUpdater ISU(ISelPosition); 691 CurDAG->RemoveDeadNode(Node, &ISU); 692 } 693 } 694 695 CurDAG->setRoot(Dummy.getValue()); 696 } 697 DEBUG(errs() << "===== Instruction selection ends:\n"); 698 699 PostprocessISelDAG(); 700} 701 702/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 703/// do other setup for EH landing-pad blocks. 704void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) { 705 // Add a label to mark the beginning of the landing pad. Deletion of the 706 // landing pad can thus be detected via the MachineModuleInfo. 707 MCSymbol *Label = MF->getMMI().addLandingPad(BB); 708 709 const TargetInstrDesc &II = 710 TLI.getTargetMachine().getInstrInfo()->get(TargetOpcode::EH_LABEL); 711 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 712 713 // Mark exception register as live in. 714 unsigned Reg = TLI.getExceptionAddressRegister(); 715 if (Reg) BB->addLiveIn(Reg); 716 717 // Mark exception selector register as live in. 718 Reg = TLI.getExceptionSelectorRegister(); 719 if (Reg) BB->addLiveIn(Reg); 720 721 // FIXME: Hack around an exception handling flaw (PR1508): the personality 722 // function and list of typeids logically belong to the invoke (or, if you 723 // like, the basic block containing the invoke), and need to be associated 724 // with it in the dwarf exception handling tables. Currently however the 725 // information is provided by an intrinsic (eh.selector) that can be moved 726 // to unexpected places by the optimizers: if the unwind edge is critical, 727 // then breaking it can result in the intrinsics being in the successor of 728 // the landing pad, not the landing pad itself. This results 729 // in exceptions not being caught because no typeids are associated with 730 // the invoke. This may not be the only way things can go wrong, but it 731 // is the only way we try to work around for the moment. 732 const BasicBlock *LLVMBB = BB->getBasicBlock(); 733 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 734 735 if (Br && Br->isUnconditional()) { // Critical edge? 736 BasicBlock::const_iterator I, E; 737 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 738 if (isa<EHSelectorInst>(I)) 739 break; 740 741 if (I == E) 742 // No catch info found - try to extract some from the successor. 743 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 744 } 745} 746 747void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 748 MachineFunction &MF, 749 const TargetInstrInfo &TII) { 750 // Initialize the Fast-ISel state, if needed. 751 FastISel *FastIS = 0; 752 if (EnableFastISel) 753 FastIS = TLI.createFastISel(MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 754 FuncInfo->StaticAllocaMap 755#ifndef NDEBUG 756 , FuncInfo->CatchInfoLost 757#endif 758 ); 759 760 // Iterate over all basic blocks in the function. 761 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 762 BasicBlock *LLVMBB = &*I; 763 BB = FuncInfo->MBBMap[LLVMBB]; 764 765 BasicBlock::iterator const Begin = LLVMBB->begin(); 766 BasicBlock::iterator const End = LLVMBB->end(); 767 BasicBlock::iterator BI = Begin; 768 769 // Lower any arguments needed in this block if this is the entry block. 770 bool SuppressFastISel = false; 771 if (LLVMBB == &Fn.getEntryBlock()) { 772 LowerArguments(LLVMBB); 773 774 // If any of the arguments has the byval attribute, forgo 775 // fast-isel in the entry block. 776 if (FastIS) { 777 unsigned j = 1; 778 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 779 I != E; ++I, ++j) 780 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 781 if (EnableFastISelVerbose || EnableFastISelAbort) 782 dbgs() << "FastISel skips entry block due to byval argument\n"; 783 SuppressFastISel = true; 784 break; 785 } 786 } 787 } 788 789 // Setup an EH landing-pad block. 790 if (BB->isLandingPad()) 791 PrepareEHLandingPad(BB); 792 793 // Before doing SelectionDAG ISel, see if FastISel has been requested. 794 if (FastIS && !SuppressFastISel) { 795 // Emit code for any incoming arguments. This must happen before 796 // beginning FastISel on the entry block. 797 if (LLVMBB == &Fn.getEntryBlock()) { 798 CurDAG->setRoot(SDB->getControlRoot()); 799 CodeGenAndEmitDAG(); 800 SDB->clear(); 801 } 802 FastIS->startNewBlock(BB); 803 // Do FastISel on as many instructions as possible. 804 for (; BI != End; ++BI) { 805 // Just before the terminator instruction, insert instructions to 806 // feed PHI nodes in successor blocks. 807 if (isa<TerminatorInst>(BI)) 808 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 809 ++NumFastIselFailures; 810 ResetDebugLoc(SDB, FastIS); 811 if (EnableFastISelVerbose || EnableFastISelAbort) { 812 dbgs() << "FastISel miss: "; 813 BI->dump(); 814 } 815 assert(!EnableFastISelAbort && 816 "FastISel didn't handle a PHI in a successor"); 817 break; 818 } 819 820 SetDebugLoc(BI, SDB, FastIS, &MF); 821 822 // Try to select the instruction with FastISel. 823 if (FastIS->SelectInstruction(BI)) { 824 ResetDebugLoc(SDB, FastIS); 825 continue; 826 } 827 828 // Clear out the debug location so that it doesn't carry over to 829 // unrelated instructions. 830 ResetDebugLoc(SDB, FastIS); 831 832 // Then handle certain instructions as single-LLVM-Instruction blocks. 833 if (isa<CallInst>(BI)) { 834 ++NumFastIselFailures; 835 if (EnableFastISelVerbose || EnableFastISelAbort) { 836 dbgs() << "FastISel missed call: "; 837 BI->dump(); 838 } 839 840 if (!BI->getType()->isVoidTy()) { 841 unsigned &R = FuncInfo->ValueMap[BI]; 842 if (!R) 843 R = FuncInfo->CreateRegForValue(BI); 844 } 845 846 bool HadTailCall = false; 847 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 848 849 // If the call was emitted as a tail call, we're done with the block. 850 if (HadTailCall) { 851 BI = End; 852 break; 853 } 854 855 // If the instruction was codegen'd with multiple blocks, 856 // inform the FastISel object where to resume inserting. 857 FastIS->setCurrentBlock(BB); 858 continue; 859 } 860 861 // Otherwise, give up on FastISel for the rest of the block. 862 // For now, be a little lenient about non-branch terminators. 863 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 864 ++NumFastIselFailures; 865 if (EnableFastISelVerbose || EnableFastISelAbort) { 866 dbgs() << "FastISel miss: "; 867 BI->dump(); 868 } 869 if (EnableFastISelAbort) 870 // The "fast" selector couldn't handle something and bailed. 871 // For the purpose of debugging, just abort. 872 llvm_unreachable("FastISel didn't select the entire block"); 873 } 874 break; 875 } 876 } 877 878 // Run SelectionDAG instruction selection on the remainder of the block 879 // not handled by FastISel. If FastISel is not run, this is the entire 880 // block. 881 if (BI != End) { 882 bool HadTailCall; 883 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 884 } 885 886 FinishBasicBlock(); 887 } 888 889 delete FastIS; 890} 891 892void 893SelectionDAGISel::FinishBasicBlock() { 894 895 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 896 DEBUG(BB->dump()); 897 898 DEBUG(dbgs() << "Total amount of phi nodes to update: " 899 << SDB->PHINodesToUpdate.size() << "\n"); 900 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 901 dbgs() << "Node " << i << " : (" 902 << SDB->PHINodesToUpdate[i].first 903 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 904 905 // Next, now that we know what the last MBB the LLVM BB expanded is, update 906 // PHI nodes in successors. 907 if (SDB->SwitchCases.empty() && 908 SDB->JTCases.empty() && 909 SDB->BitTestCases.empty()) { 910 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 911 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 912 assert(PHI->isPHI() && 913 "This is not a machine PHI node that we are updating!"); 914 if (!BB->isSuccessor(PHI->getParent())) 915 continue; 916 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 917 false)); 918 PHI->addOperand(MachineOperand::CreateMBB(BB)); 919 } 920 SDB->PHINodesToUpdate.clear(); 921 return; 922 } 923 924 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 925 // Lower header first, if it wasn't already lowered 926 if (!SDB->BitTestCases[i].Emitted) { 927 // Set the current basic block to the mbb we wish to insert the code into 928 BB = SDB->BitTestCases[i].Parent; 929 SDB->setCurrentBasicBlock(BB); 930 // Emit the code 931 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 932 CurDAG->setRoot(SDB->getRoot()); 933 CodeGenAndEmitDAG(); 934 SDB->clear(); 935 } 936 937 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 938 // Set the current basic block to the mbb we wish to insert the code into 939 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 940 SDB->setCurrentBasicBlock(BB); 941 // Emit the code 942 if (j+1 != ej) 943 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 944 SDB->BitTestCases[i].Reg, 945 SDB->BitTestCases[i].Cases[j]); 946 else 947 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 948 SDB->BitTestCases[i].Reg, 949 SDB->BitTestCases[i].Cases[j]); 950 951 952 CurDAG->setRoot(SDB->getRoot()); 953 CodeGenAndEmitDAG(); 954 SDB->clear(); 955 } 956 957 // Update PHI Nodes 958 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 959 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 960 MachineBasicBlock *PHIBB = PHI->getParent(); 961 assert(PHI->isPHI() && 962 "This is not a machine PHI node that we are updating!"); 963 // This is "default" BB. We have two jumps to it. From "header" BB and 964 // from last "case" BB. 965 if (PHIBB == SDB->BitTestCases[i].Default) { 966 PHI->addOperand(MachineOperand:: 967 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 968 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 969 PHI->addOperand(MachineOperand:: 970 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 971 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 972 back().ThisBB)); 973 } 974 // One of "cases" BB. 975 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 976 j != ej; ++j) { 977 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 978 if (cBB->isSuccessor(PHIBB)) { 979 PHI->addOperand(MachineOperand:: 980 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 981 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 982 } 983 } 984 } 985 } 986 SDB->BitTestCases.clear(); 987 988 // If the JumpTable record is filled in, then we need to emit a jump table. 989 // Updating the PHI nodes is tricky in this case, since we need to determine 990 // whether the PHI is a successor of the range check MBB or the jump table MBB 991 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 992 // Lower header first, if it wasn't already lowered 993 if (!SDB->JTCases[i].first.Emitted) { 994 // Set the current basic block to the mbb we wish to insert the code into 995 BB = SDB->JTCases[i].first.HeaderBB; 996 SDB->setCurrentBasicBlock(BB); 997 // Emit the code 998 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 999 CurDAG->setRoot(SDB->getRoot()); 1000 CodeGenAndEmitDAG(); 1001 SDB->clear(); 1002 } 1003 1004 // Set the current basic block to the mbb we wish to insert the code into 1005 BB = SDB->JTCases[i].second.MBB; 1006 SDB->setCurrentBasicBlock(BB); 1007 // Emit the code 1008 SDB->visitJumpTable(SDB->JTCases[i].second); 1009 CurDAG->setRoot(SDB->getRoot()); 1010 CodeGenAndEmitDAG(); 1011 SDB->clear(); 1012 1013 // Update PHI Nodes 1014 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1015 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1016 MachineBasicBlock *PHIBB = PHI->getParent(); 1017 assert(PHI->isPHI() && 1018 "This is not a machine PHI node that we are updating!"); 1019 // "default" BB. We can go there only from header BB. 1020 if (PHIBB == SDB->JTCases[i].second.Default) { 1021 PHI->addOperand 1022 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1023 PHI->addOperand 1024 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1025 } 1026 // JT BB. Just iterate over successors here 1027 if (BB->isSuccessor(PHIBB)) { 1028 PHI->addOperand 1029 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1030 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1031 } 1032 } 1033 } 1034 SDB->JTCases.clear(); 1035 1036 // If the switch block involved a branch to one of the actual successors, we 1037 // need to update PHI nodes in that block. 1038 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1039 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1040 assert(PHI->isPHI() && 1041 "This is not a machine PHI node that we are updating!"); 1042 if (BB->isSuccessor(PHI->getParent())) { 1043 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1044 false)); 1045 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1046 } 1047 } 1048 1049 // If we generated any switch lowering information, build and codegen any 1050 // additional DAGs necessary. 1051 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1052 // Set the current basic block to the mbb we wish to insert the code into 1053 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1054 SDB->setCurrentBasicBlock(BB); 1055 1056 // Emit the code 1057 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1058 CurDAG->setRoot(SDB->getRoot()); 1059 CodeGenAndEmitDAG(); 1060 1061 // Handle any PHI nodes in successors of this chunk, as if we were coming 1062 // from the original BB before switch expansion. Note that PHI nodes can 1063 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1064 // handle them the right number of times. 1065 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1066 // If new BB's are created during scheduling, the edges may have been 1067 // updated. That is, the edge from ThisBB to BB may have been split and 1068 // BB's predecessor is now another block. 1069 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1070 SDB->EdgeMapping.find(BB); 1071 if (EI != SDB->EdgeMapping.end()) 1072 ThisBB = EI->second; 1073 1074 // BB may have been removed from the CFG if a branch was constant folded. 1075 if (ThisBB->isSuccessor(BB)) { 1076 for (MachineBasicBlock::iterator Phi = BB->begin(); 1077 Phi != BB->end() && Phi->isPHI(); 1078 ++Phi) { 1079 // This value for this PHI node is recorded in PHINodesToUpdate. 1080 for (unsigned pn = 0; ; ++pn) { 1081 assert(pn != SDB->PHINodesToUpdate.size() && 1082 "Didn't find PHI entry!"); 1083 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1084 Phi->addOperand(MachineOperand:: 1085 CreateReg(SDB->PHINodesToUpdate[pn].second, 1086 false)); 1087 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1088 break; 1089 } 1090 } 1091 } 1092 } 1093 1094 // Don't process RHS if same block as LHS. 1095 if (BB == SDB->SwitchCases[i].FalseBB) 1096 SDB->SwitchCases[i].FalseBB = 0; 1097 1098 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1099 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1100 SDB->SwitchCases[i].FalseBB = 0; 1101 } 1102 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1103 SDB->clear(); 1104 } 1105 SDB->SwitchCases.clear(); 1106 1107 SDB->PHINodesToUpdate.clear(); 1108} 1109 1110 1111/// Create the scheduler. If a specific scheduler was specified 1112/// via the SchedulerRegistry, use it, otherwise select the 1113/// one preferred by the target. 1114/// 1115ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1116 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1117 1118 if (!Ctor) { 1119 Ctor = ISHeuristic; 1120 RegisterScheduler::setDefault(Ctor); 1121 } 1122 1123 return Ctor(this, OptLevel); 1124} 1125 1126ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1127 return new ScheduleHazardRecognizer(); 1128} 1129 1130//===----------------------------------------------------------------------===// 1131// Helper functions used by the generated instruction selector. 1132//===----------------------------------------------------------------------===// 1133// Calls to these methods are generated by tblgen. 1134 1135/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1136/// the dag combiner simplified the 255, we still want to match. RHS is the 1137/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1138/// specified in the .td file (e.g. 255). 1139bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1140 int64_t DesiredMaskS) const { 1141 const APInt &ActualMask = RHS->getAPIntValue(); 1142 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1143 1144 // If the actual mask exactly matches, success! 1145 if (ActualMask == DesiredMask) 1146 return true; 1147 1148 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1149 if (ActualMask.intersects(~DesiredMask)) 1150 return false; 1151 1152 // Otherwise, the DAG Combiner may have proven that the value coming in is 1153 // either already zero or is not demanded. Check for known zero input bits. 1154 APInt NeededMask = DesiredMask & ~ActualMask; 1155 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1156 return true; 1157 1158 // TODO: check to see if missing bits are just not demanded. 1159 1160 // Otherwise, this pattern doesn't match. 1161 return false; 1162} 1163 1164/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1165/// the dag combiner simplified the 255, we still want to match. RHS is the 1166/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1167/// specified in the .td file (e.g. 255). 1168bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1169 int64_t DesiredMaskS) const { 1170 const APInt &ActualMask = RHS->getAPIntValue(); 1171 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1172 1173 // If the actual mask exactly matches, success! 1174 if (ActualMask == DesiredMask) 1175 return true; 1176 1177 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1178 if (ActualMask.intersects(~DesiredMask)) 1179 return false; 1180 1181 // Otherwise, the DAG Combiner may have proven that the value coming in is 1182 // either already zero or is not demanded. Check for known zero input bits. 1183 APInt NeededMask = DesiredMask & ~ActualMask; 1184 1185 APInt KnownZero, KnownOne; 1186 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1187 1188 // If all the missing bits in the or are already known to be set, match! 1189 if ((NeededMask & KnownOne) == NeededMask) 1190 return true; 1191 1192 // TODO: check to see if missing bits are just not demanded. 1193 1194 // Otherwise, this pattern doesn't match. 1195 return false; 1196} 1197 1198 1199/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1200/// by tblgen. Others should not call it. 1201void SelectionDAGISel:: 1202SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1203 std::vector<SDValue> InOps; 1204 std::swap(InOps, Ops); 1205 1206 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1207 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1208 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1209 1210 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1211 if (InOps[e-1].getValueType() == MVT::Flag) 1212 --e; // Don't process a flag operand if it is here. 1213 1214 while (i != e) { 1215 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1216 if (!InlineAsm::isMemKind(Flags)) { 1217 // Just skip over this operand, copying the operands verbatim. 1218 Ops.insert(Ops.end(), InOps.begin()+i, 1219 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1220 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1221 } else { 1222 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1223 "Memory operand with multiple values?"); 1224 // Otherwise, this is a memory operand. Ask the target to select it. 1225 std::vector<SDValue> SelOps; 1226 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1227 report_fatal_error("Could not match memory address. Inline asm" 1228 " failure!"); 1229 1230 // Add this to the output node. 1231 unsigned NewFlags = 1232 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1233 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1234 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1235 i += 2; 1236 } 1237 } 1238 1239 // Add the flag input back if present. 1240 if (e != InOps.size()) 1241 Ops.push_back(InOps.back()); 1242} 1243 1244/// findFlagUse - Return use of EVT::Flag value produced by the specified 1245/// SDNode. 1246/// 1247static SDNode *findFlagUse(SDNode *N) { 1248 unsigned FlagResNo = N->getNumValues()-1; 1249 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1250 SDUse &Use = I.getUse(); 1251 if (Use.getResNo() == FlagResNo) 1252 return Use.getUser(); 1253 } 1254 return NULL; 1255} 1256 1257/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1258/// This function recursively traverses up the operand chain, ignoring 1259/// certain nodes. 1260static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1261 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1262 bool IgnoreChains) { 1263 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1264 // greater than all of its (recursive) operands. If we scan to a point where 1265 // 'use' is smaller than the node we're scanning for, then we know we will 1266 // never find it. 1267 // 1268 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1269 // happen because we scan down to newly selected nodes in the case of flag 1270 // uses. 1271 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1272 return false; 1273 1274 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1275 // won't fail if we scan it again. 1276 if (!Visited.insert(Use)) 1277 return false; 1278 1279 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1280 // Ignore chain uses, they are validated by HandleMergeInputChains. 1281 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1282 continue; 1283 1284 SDNode *N = Use->getOperand(i).getNode(); 1285 if (N == Def) { 1286 if (Use == ImmedUse || Use == Root) 1287 continue; // We are not looking for immediate use. 1288 assert(N != Root); 1289 return true; 1290 } 1291 1292 // Traverse up the operand chain. 1293 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1294 return true; 1295 } 1296 return false; 1297} 1298 1299/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1300/// operand node N of U during instruction selection that starts at Root. 1301bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1302 SDNode *Root) const { 1303 if (OptLevel == CodeGenOpt::None) return false; 1304 return N.hasOneUse(); 1305} 1306 1307/// IsLegalToFold - Returns true if the specific operand node N of 1308/// U can be folded during instruction selection that starts at Root. 1309bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1310 bool IgnoreChains) const { 1311 if (OptLevel == CodeGenOpt::None) return false; 1312 1313 // If Root use can somehow reach N through a path that that doesn't contain 1314 // U then folding N would create a cycle. e.g. In the following 1315 // diagram, Root can reach N through X. If N is folded into into Root, then 1316 // X is both a predecessor and a successor of U. 1317 // 1318 // [N*] // 1319 // ^ ^ // 1320 // / \ // 1321 // [U*] [X]? // 1322 // ^ ^ // 1323 // \ / // 1324 // \ / // 1325 // [Root*] // 1326 // 1327 // * indicates nodes to be folded together. 1328 // 1329 // If Root produces a flag, then it gets (even more) interesting. Since it 1330 // will be "glued" together with its flag use in the scheduler, we need to 1331 // check if it might reach N. 1332 // 1333 // [N*] // 1334 // ^ ^ // 1335 // / \ // 1336 // [U*] [X]? // 1337 // ^ ^ // 1338 // \ \ // 1339 // \ | // 1340 // [Root*] | // 1341 // ^ | // 1342 // f | // 1343 // | / // 1344 // [Y] / // 1345 // ^ / // 1346 // f / // 1347 // | / // 1348 // [FU] // 1349 // 1350 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1351 // (call it Fold), then X is a predecessor of FU and a successor of 1352 // Fold. But since Fold and FU are flagged together, this will create 1353 // a cycle in the scheduling graph. 1354 1355 // If the node has flags, walk down the graph to the "lowest" node in the 1356 // flagged set. 1357 EVT VT = Root->getValueType(Root->getNumValues()-1); 1358 while (VT == MVT::Flag) { 1359 SDNode *FU = findFlagUse(Root); 1360 if (FU == NULL) 1361 break; 1362 Root = FU; 1363 VT = Root->getValueType(Root->getNumValues()-1); 1364 1365 // If our query node has a flag result with a use, we've walked up it. If 1366 // the user (which has already been selected) has a chain or indirectly uses 1367 // the chain, our WalkChainUsers predicate will not consider it. Because of 1368 // this, we cannot ignore chains in this predicate. 1369 IgnoreChains = false; 1370 } 1371 1372 1373 SmallPtrSet<SDNode*, 16> Visited; 1374 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1375} 1376 1377SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1378 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1379 SelectInlineAsmMemoryOperands(Ops); 1380 1381 std::vector<EVT> VTs; 1382 VTs.push_back(MVT::Other); 1383 VTs.push_back(MVT::Flag); 1384 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1385 VTs, &Ops[0], Ops.size()); 1386 New->setNodeId(-1); 1387 return New.getNode(); 1388} 1389 1390SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1391 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1392} 1393 1394/// GetVBR - decode a vbr encoding whose top bit is set. 1395ALWAYS_INLINE static uint64_t 1396GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1397 assert(Val >= 128 && "Not a VBR"); 1398 Val &= 127; // Remove first vbr bit. 1399 1400 unsigned Shift = 7; 1401 uint64_t NextBits; 1402 do { 1403 NextBits = MatcherTable[Idx++]; 1404 Val |= (NextBits&127) << Shift; 1405 Shift += 7; 1406 } while (NextBits & 128); 1407 1408 return Val; 1409} 1410 1411 1412/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1413/// interior flag and chain results to use the new flag and chain results. 1414void SelectionDAGISel:: 1415UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1416 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1417 SDValue InputFlag, 1418 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1419 bool isMorphNodeTo) { 1420 SmallVector<SDNode*, 4> NowDeadNodes; 1421 1422 ISelUpdater ISU(ISelPosition); 1423 1424 // Now that all the normal results are replaced, we replace the chain and 1425 // flag results if present. 1426 if (!ChainNodesMatched.empty()) { 1427 assert(InputChain.getNode() != 0 && 1428 "Matched input chains but didn't produce a chain"); 1429 // Loop over all of the nodes we matched that produced a chain result. 1430 // Replace all the chain results with the final chain we ended up with. 1431 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1432 SDNode *ChainNode = ChainNodesMatched[i]; 1433 1434 // If this node was already deleted, don't look at it. 1435 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1436 continue; 1437 1438 // Don't replace the results of the root node if we're doing a 1439 // MorphNodeTo. 1440 if (ChainNode == NodeToMatch && isMorphNodeTo) 1441 continue; 1442 1443 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1444 if (ChainVal.getValueType() == MVT::Flag) 1445 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1446 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1447 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1448 1449 // If the node became dead and we haven't already seen it, delete it. 1450 if (ChainNode->use_empty() && 1451 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1452 NowDeadNodes.push_back(ChainNode); 1453 } 1454 } 1455 1456 // If the result produces a flag, update any flag results in the matched 1457 // pattern with the flag result. 1458 if (InputFlag.getNode() != 0) { 1459 // Handle any interior nodes explicitly marked. 1460 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1461 SDNode *FRN = FlagResultNodesMatched[i]; 1462 1463 // If this node was already deleted, don't look at it. 1464 if (FRN->getOpcode() == ISD::DELETED_NODE) 1465 continue; 1466 1467 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1468 "Doesn't have a flag result"); 1469 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1470 InputFlag, &ISU); 1471 1472 // If the node became dead and we haven't already seen it, delete it. 1473 if (FRN->use_empty() && 1474 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1475 NowDeadNodes.push_back(FRN); 1476 } 1477 } 1478 1479 if (!NowDeadNodes.empty()) 1480 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1481 1482 DEBUG(errs() << "ISEL: Match complete!\n"); 1483} 1484 1485enum ChainResult { 1486 CR_Simple, 1487 CR_InducesCycle, 1488 CR_LeadsToInteriorNode 1489}; 1490 1491/// WalkChainUsers - Walk down the users of the specified chained node that is 1492/// part of the pattern we're matching, looking at all of the users we find. 1493/// This determines whether something is an interior node, whether we have a 1494/// non-pattern node in between two pattern nodes (which prevent folding because 1495/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1496/// between pattern nodes (in which case the TF becomes part of the pattern). 1497/// 1498/// The walk we do here is guaranteed to be small because we quickly get down to 1499/// already selected nodes "below" us. 1500static ChainResult 1501WalkChainUsers(SDNode *ChainedNode, 1502 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1503 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1504 ChainResult Result = CR_Simple; 1505 1506 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1507 E = ChainedNode->use_end(); UI != E; ++UI) { 1508 // Make sure the use is of the chain, not some other value we produce. 1509 if (UI.getUse().getValueType() != MVT::Other) continue; 1510 1511 SDNode *User = *UI; 1512 1513 // If we see an already-selected machine node, then we've gone beyond the 1514 // pattern that we're selecting down into the already selected chunk of the 1515 // DAG. 1516 if (User->isMachineOpcode() || 1517 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1518 continue; 1519 1520 if (User->getOpcode() == ISD::CopyToReg || 1521 User->getOpcode() == ISD::CopyFromReg || 1522 User->getOpcode() == ISD::INLINEASM || 1523 User->getOpcode() == ISD::EH_LABEL) { 1524 // If their node ID got reset to -1 then they've already been selected. 1525 // Treat them like a MachineOpcode. 1526 if (User->getNodeId() == -1) 1527 continue; 1528 } 1529 1530 // If we have a TokenFactor, we handle it specially. 1531 if (User->getOpcode() != ISD::TokenFactor) { 1532 // If the node isn't a token factor and isn't part of our pattern, then it 1533 // must be a random chained node in between two nodes we're selecting. 1534 // This happens when we have something like: 1535 // x = load ptr 1536 // call 1537 // y = x+4 1538 // store y -> ptr 1539 // Because we structurally match the load/store as a read/modify/write, 1540 // but the call is chained between them. We cannot fold in this case 1541 // because it would induce a cycle in the graph. 1542 if (!std::count(ChainedNodesInPattern.begin(), 1543 ChainedNodesInPattern.end(), User)) 1544 return CR_InducesCycle; 1545 1546 // Otherwise we found a node that is part of our pattern. For example in: 1547 // x = load ptr 1548 // y = x+4 1549 // store y -> ptr 1550 // This would happen when we're scanning down from the load and see the 1551 // store as a user. Record that there is a use of ChainedNode that is 1552 // part of the pattern and keep scanning uses. 1553 Result = CR_LeadsToInteriorNode; 1554 InteriorChainedNodes.push_back(User); 1555 continue; 1556 } 1557 1558 // If we found a TokenFactor, there are two cases to consider: first if the 1559 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1560 // uses of the TF are in our pattern) we just want to ignore it. Second, 1561 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1562 // [Load chain] 1563 // ^ 1564 // | 1565 // [Load] 1566 // ^ ^ 1567 // | \ DAG's like cheese 1568 // / \ do you? 1569 // / | 1570 // [TokenFactor] [Op] 1571 // ^ ^ 1572 // | | 1573 // \ / 1574 // \ / 1575 // [Store] 1576 // 1577 // In this case, the TokenFactor becomes part of our match and we rewrite it 1578 // as a new TokenFactor. 1579 // 1580 // To distinguish these two cases, do a recursive walk down the uses. 1581 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1582 case CR_Simple: 1583 // If the uses of the TokenFactor are just already-selected nodes, ignore 1584 // it, it is "below" our pattern. 1585 continue; 1586 case CR_InducesCycle: 1587 // If the uses of the TokenFactor lead to nodes that are not part of our 1588 // pattern that are not selected, folding would turn this into a cycle, 1589 // bail out now. 1590 return CR_InducesCycle; 1591 case CR_LeadsToInteriorNode: 1592 break; // Otherwise, keep processing. 1593 } 1594 1595 // Okay, we know we're in the interesting interior case. The TokenFactor 1596 // is now going to be considered part of the pattern so that we rewrite its 1597 // uses (it may have uses that are not part of the pattern) with the 1598 // ultimate chain result of the generated code. We will also add its chain 1599 // inputs as inputs to the ultimate TokenFactor we create. 1600 Result = CR_LeadsToInteriorNode; 1601 ChainedNodesInPattern.push_back(User); 1602 InteriorChainedNodes.push_back(User); 1603 continue; 1604 } 1605 1606 return Result; 1607} 1608 1609/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1610/// operation for when the pattern matched at least one node with a chains. The 1611/// input vector contains a list of all of the chained nodes that we match. We 1612/// must determine if this is a valid thing to cover (i.e. matching it won't 1613/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1614/// be used as the input node chain for the generated nodes. 1615static SDValue 1616HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1617 SelectionDAG *CurDAG) { 1618 // Walk all of the chained nodes we've matched, recursively scanning down the 1619 // users of the chain result. This adds any TokenFactor nodes that are caught 1620 // in between chained nodes to the chained and interior nodes list. 1621 SmallVector<SDNode*, 3> InteriorChainedNodes; 1622 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1623 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1624 InteriorChainedNodes) == CR_InducesCycle) 1625 return SDValue(); // Would induce a cycle. 1626 } 1627 1628 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1629 // that we are interested in. Form our input TokenFactor node. 1630 SmallVector<SDValue, 3> InputChains; 1631 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1632 // Add the input chain of this node to the InputChains list (which will be 1633 // the operands of the generated TokenFactor) if it's not an interior node. 1634 SDNode *N = ChainNodesMatched[i]; 1635 if (N->getOpcode() != ISD::TokenFactor) { 1636 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1637 continue; 1638 1639 // Otherwise, add the input chain. 1640 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1641 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1642 InputChains.push_back(InChain); 1643 continue; 1644 } 1645 1646 // If we have a token factor, we want to add all inputs of the token factor 1647 // that are not part of the pattern we're matching. 1648 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1649 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1650 N->getOperand(op).getNode())) 1651 InputChains.push_back(N->getOperand(op)); 1652 } 1653 } 1654 1655 SDValue Res; 1656 if (InputChains.size() == 1) 1657 return InputChains[0]; 1658 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1659 MVT::Other, &InputChains[0], InputChains.size()); 1660} 1661 1662/// MorphNode - Handle morphing a node in place for the selector. 1663SDNode *SelectionDAGISel:: 1664MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1665 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1666 // It is possible we're using MorphNodeTo to replace a node with no 1667 // normal results with one that has a normal result (or we could be 1668 // adding a chain) and the input could have flags and chains as well. 1669 // In this case we need to shift the operands down. 1670 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1671 // than the old isel though. 1672 int OldFlagResultNo = -1, OldChainResultNo = -1; 1673 1674 unsigned NTMNumResults = Node->getNumValues(); 1675 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1676 OldFlagResultNo = NTMNumResults-1; 1677 if (NTMNumResults != 1 && 1678 Node->getValueType(NTMNumResults-2) == MVT::Other) 1679 OldChainResultNo = NTMNumResults-2; 1680 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1681 OldChainResultNo = NTMNumResults-1; 1682 1683 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1684 // that this deletes operands of the old node that become dead. 1685 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1686 1687 // MorphNodeTo can operate in two ways: if an existing node with the 1688 // specified operands exists, it can just return it. Otherwise, it 1689 // updates the node in place to have the requested operands. 1690 if (Res == Node) { 1691 // If we updated the node in place, reset the node ID. To the isel, 1692 // this should be just like a newly allocated machine node. 1693 Res->setNodeId(-1); 1694 } 1695 1696 unsigned ResNumResults = Res->getNumValues(); 1697 // Move the flag if needed. 1698 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1699 (unsigned)OldFlagResultNo != ResNumResults-1) 1700 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1701 SDValue(Res, ResNumResults-1)); 1702 1703 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1704 --ResNumResults; 1705 1706 // Move the chain reference if needed. 1707 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1708 (unsigned)OldChainResultNo != ResNumResults-1) 1709 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1710 SDValue(Res, ResNumResults-1)); 1711 1712 // Otherwise, no replacement happened because the node already exists. Replace 1713 // Uses of the old node with the new one. 1714 if (Res != Node) 1715 CurDAG->ReplaceAllUsesWith(Node, Res); 1716 1717 return Res; 1718} 1719 1720/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1721ALWAYS_INLINE static bool 1722CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1723 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1724 // Accept if it is exactly the same as a previously recorded node. 1725 unsigned RecNo = MatcherTable[MatcherIndex++]; 1726 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1727 return N == RecordedNodes[RecNo]; 1728} 1729 1730/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1731ALWAYS_INLINE static bool 1732CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1733 SelectionDAGISel &SDISel) { 1734 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1735} 1736 1737/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1738ALWAYS_INLINE static bool 1739CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1740 SelectionDAGISel &SDISel, SDNode *N) { 1741 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1742} 1743 1744ALWAYS_INLINE static bool 1745CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1746 SDNode *N) { 1747 uint16_t Opc = MatcherTable[MatcherIndex++]; 1748 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1749 return N->getOpcode() == Opc; 1750} 1751 1752ALWAYS_INLINE static bool 1753CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1754 SDValue N, const TargetLowering &TLI) { 1755 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1756 if (N.getValueType() == VT) return true; 1757 1758 // Handle the case when VT is iPTR. 1759 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1760} 1761 1762ALWAYS_INLINE static bool 1763CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1764 SDValue N, const TargetLowering &TLI, 1765 unsigned ChildNo) { 1766 if (ChildNo >= N.getNumOperands()) 1767 return false; // Match fails if out of range child #. 1768 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1769} 1770 1771 1772ALWAYS_INLINE static bool 1773CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1774 SDValue N) { 1775 return cast<CondCodeSDNode>(N)->get() == 1776 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1777} 1778 1779ALWAYS_INLINE static bool 1780CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1781 SDValue N, const TargetLowering &TLI) { 1782 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1783 if (cast<VTSDNode>(N)->getVT() == VT) 1784 return true; 1785 1786 // Handle the case when VT is iPTR. 1787 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1788} 1789 1790ALWAYS_INLINE static bool 1791CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1792 SDValue N) { 1793 int64_t Val = MatcherTable[MatcherIndex++]; 1794 if (Val & 128) 1795 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1796 1797 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1798 return C != 0 && C->getSExtValue() == Val; 1799} 1800 1801ALWAYS_INLINE static bool 1802CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1803 SDValue N, SelectionDAGISel &SDISel) { 1804 int64_t Val = MatcherTable[MatcherIndex++]; 1805 if (Val & 128) 1806 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1807 1808 if (N->getOpcode() != ISD::AND) return false; 1809 1810 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1811 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1812} 1813 1814ALWAYS_INLINE static bool 1815CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1816 SDValue N, SelectionDAGISel &SDISel) { 1817 int64_t Val = MatcherTable[MatcherIndex++]; 1818 if (Val & 128) 1819 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1820 1821 if (N->getOpcode() != ISD::OR) return false; 1822 1823 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1824 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1825} 1826 1827/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1828/// scope, evaluate the current node. If the current predicate is known to 1829/// fail, set Result=true and return anything. If the current predicate is 1830/// known to pass, set Result=false and return the MatcherIndex to continue 1831/// with. If the current predicate is unknown, set Result=false and return the 1832/// MatcherIndex to continue with. 1833static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1834 unsigned Index, SDValue N, 1835 bool &Result, SelectionDAGISel &SDISel, 1836 SmallVectorImpl<SDValue> &RecordedNodes){ 1837 switch (Table[Index++]) { 1838 default: 1839 Result = false; 1840 return Index-1; // Could not evaluate this predicate. 1841 case SelectionDAGISel::OPC_CheckSame: 1842 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1843 return Index; 1844 case SelectionDAGISel::OPC_CheckPatternPredicate: 1845 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1846 return Index; 1847 case SelectionDAGISel::OPC_CheckPredicate: 1848 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1849 return Index; 1850 case SelectionDAGISel::OPC_CheckOpcode: 1851 Result = !::CheckOpcode(Table, Index, N.getNode()); 1852 return Index; 1853 case SelectionDAGISel::OPC_CheckType: 1854 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1855 return Index; 1856 case SelectionDAGISel::OPC_CheckChild0Type: 1857 case SelectionDAGISel::OPC_CheckChild1Type: 1858 case SelectionDAGISel::OPC_CheckChild2Type: 1859 case SelectionDAGISel::OPC_CheckChild3Type: 1860 case SelectionDAGISel::OPC_CheckChild4Type: 1861 case SelectionDAGISel::OPC_CheckChild5Type: 1862 case SelectionDAGISel::OPC_CheckChild6Type: 1863 case SelectionDAGISel::OPC_CheckChild7Type: 1864 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1865 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1866 return Index; 1867 case SelectionDAGISel::OPC_CheckCondCode: 1868 Result = !::CheckCondCode(Table, Index, N); 1869 return Index; 1870 case SelectionDAGISel::OPC_CheckValueType: 1871 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1872 return Index; 1873 case SelectionDAGISel::OPC_CheckInteger: 1874 Result = !::CheckInteger(Table, Index, N); 1875 return Index; 1876 case SelectionDAGISel::OPC_CheckAndImm: 1877 Result = !::CheckAndImm(Table, Index, N, SDISel); 1878 return Index; 1879 case SelectionDAGISel::OPC_CheckOrImm: 1880 Result = !::CheckOrImm(Table, Index, N, SDISel); 1881 return Index; 1882 } 1883} 1884 1885 1886struct MatchScope { 1887 /// FailIndex - If this match fails, this is the index to continue with. 1888 unsigned FailIndex; 1889 1890 /// NodeStack - The node stack when the scope was formed. 1891 SmallVector<SDValue, 4> NodeStack; 1892 1893 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1894 unsigned NumRecordedNodes; 1895 1896 /// NumMatchedMemRefs - The number of matched memref entries. 1897 unsigned NumMatchedMemRefs; 1898 1899 /// InputChain/InputFlag - The current chain/flag 1900 SDValue InputChain, InputFlag; 1901 1902 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1903 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1904}; 1905 1906SDNode *SelectionDAGISel:: 1907SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1908 unsigned TableSize) { 1909 // FIXME: Should these even be selected? Handle these cases in the caller? 1910 switch (NodeToMatch->getOpcode()) { 1911 default: 1912 break; 1913 case ISD::EntryToken: // These nodes remain the same. 1914 case ISD::BasicBlock: 1915 case ISD::Register: 1916 //case ISD::VALUETYPE: 1917 //case ISD::CONDCODE: 1918 case ISD::HANDLENODE: 1919 case ISD::MDNODE_SDNODE: 1920 case ISD::TargetConstant: 1921 case ISD::TargetConstantFP: 1922 case ISD::TargetConstantPool: 1923 case ISD::TargetFrameIndex: 1924 case ISD::TargetExternalSymbol: 1925 case ISD::TargetBlockAddress: 1926 case ISD::TargetJumpTable: 1927 case ISD::TargetGlobalTLSAddress: 1928 case ISD::TargetGlobalAddress: 1929 case ISD::TokenFactor: 1930 case ISD::CopyFromReg: 1931 case ISD::CopyToReg: 1932 case ISD::EH_LABEL: 1933 NodeToMatch->setNodeId(-1); // Mark selected. 1934 return 0; 1935 case ISD::AssertSext: 1936 case ISD::AssertZext: 1937 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1938 NodeToMatch->getOperand(0)); 1939 return 0; 1940 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1941 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1942 } 1943 1944 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1945 1946 // Set up the node stack with NodeToMatch as the only node on the stack. 1947 SmallVector<SDValue, 8> NodeStack; 1948 SDValue N = SDValue(NodeToMatch, 0); 1949 NodeStack.push_back(N); 1950 1951 // MatchScopes - Scopes used when matching, if a match failure happens, this 1952 // indicates where to continue checking. 1953 SmallVector<MatchScope, 8> MatchScopes; 1954 1955 // RecordedNodes - This is the set of nodes that have been recorded by the 1956 // state machine. 1957 SmallVector<SDValue, 8> RecordedNodes; 1958 1959 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1960 // pattern. 1961 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1962 1963 // These are the current input chain and flag for use when generating nodes. 1964 // Various Emit operations change these. For example, emitting a copytoreg 1965 // uses and updates these. 1966 SDValue InputChain, InputFlag; 1967 1968 // ChainNodesMatched - If a pattern matches nodes that have input/output 1969 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1970 // which ones they are. The result is captured into this list so that we can 1971 // update the chain results when the pattern is complete. 1972 SmallVector<SDNode*, 3> ChainNodesMatched; 1973 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1974 1975 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1976 NodeToMatch->dump(CurDAG); 1977 errs() << '\n'); 1978 1979 // Determine where to start the interpreter. Normally we start at opcode #0, 1980 // but if the state machine starts with an OPC_SwitchOpcode, then we 1981 // accelerate the first lookup (which is guaranteed to be hot) with the 1982 // OpcodeOffset table. 1983 unsigned MatcherIndex = 0; 1984 1985 if (!OpcodeOffset.empty()) { 1986 // Already computed the OpcodeOffset table, just index into it. 1987 if (N.getOpcode() < OpcodeOffset.size()) 1988 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1989 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1990 1991 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1992 // Otherwise, the table isn't computed, but the state machine does start 1993 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1994 // is the first time we're selecting an instruction. 1995 unsigned Idx = 1; 1996 while (1) { 1997 // Get the size of this case. 1998 unsigned CaseSize = MatcherTable[Idx++]; 1999 if (CaseSize & 128) 2000 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2001 if (CaseSize == 0) break; 2002 2003 // Get the opcode, add the index to the table. 2004 uint16_t Opc = MatcherTable[Idx++]; 2005 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2006 if (Opc >= OpcodeOffset.size()) 2007 OpcodeOffset.resize((Opc+1)*2); 2008 OpcodeOffset[Opc] = Idx; 2009 Idx += CaseSize; 2010 } 2011 2012 // Okay, do the lookup for the first opcode. 2013 if (N.getOpcode() < OpcodeOffset.size()) 2014 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2015 } 2016 2017 while (1) { 2018 assert(MatcherIndex < TableSize && "Invalid index"); 2019#ifndef NDEBUG 2020 unsigned CurrentOpcodeIndex = MatcherIndex; 2021#endif 2022 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2023 switch (Opcode) { 2024 case OPC_Scope: { 2025 // Okay, the semantics of this operation are that we should push a scope 2026 // then evaluate the first child. However, pushing a scope only to have 2027 // the first check fail (which then pops it) is inefficient. If we can 2028 // determine immediately that the first check (or first several) will 2029 // immediately fail, don't even bother pushing a scope for them. 2030 unsigned FailIndex; 2031 2032 while (1) { 2033 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2034 if (NumToSkip & 128) 2035 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2036 // Found the end of the scope with no match. 2037 if (NumToSkip == 0) { 2038 FailIndex = 0; 2039 break; 2040 } 2041 2042 FailIndex = MatcherIndex+NumToSkip; 2043 2044 unsigned MatcherIndexOfPredicate = MatcherIndex; 2045 (void)MatcherIndexOfPredicate; // silence warning. 2046 2047 // If we can't evaluate this predicate without pushing a scope (e.g. if 2048 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2049 // push the scope and evaluate the full predicate chain. 2050 bool Result; 2051 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2052 Result, *this, RecordedNodes); 2053 if (!Result) 2054 break; 2055 2056 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2057 << "index " << MatcherIndexOfPredicate 2058 << ", continuing at " << FailIndex << "\n"); 2059 ++NumDAGIselRetries; 2060 2061 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2062 // move to the next case. 2063 MatcherIndex = FailIndex; 2064 } 2065 2066 // If the whole scope failed to match, bail. 2067 if (FailIndex == 0) break; 2068 2069 // Push a MatchScope which indicates where to go if the first child fails 2070 // to match. 2071 MatchScope NewEntry; 2072 NewEntry.FailIndex = FailIndex; 2073 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2074 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2075 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2076 NewEntry.InputChain = InputChain; 2077 NewEntry.InputFlag = InputFlag; 2078 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2079 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2080 MatchScopes.push_back(NewEntry); 2081 continue; 2082 } 2083 case OPC_RecordNode: 2084 // Remember this node, it may end up being an operand in the pattern. 2085 RecordedNodes.push_back(N); 2086 continue; 2087 2088 case OPC_RecordChild0: case OPC_RecordChild1: 2089 case OPC_RecordChild2: case OPC_RecordChild3: 2090 case OPC_RecordChild4: case OPC_RecordChild5: 2091 case OPC_RecordChild6: case OPC_RecordChild7: { 2092 unsigned ChildNo = Opcode-OPC_RecordChild0; 2093 if (ChildNo >= N.getNumOperands()) 2094 break; // Match fails if out of range child #. 2095 2096 RecordedNodes.push_back(N->getOperand(ChildNo)); 2097 continue; 2098 } 2099 case OPC_RecordMemRef: 2100 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2101 continue; 2102 2103 case OPC_CaptureFlagInput: 2104 // If the current node has an input flag, capture it in InputFlag. 2105 if (N->getNumOperands() != 0 && 2106 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2107 InputFlag = N->getOperand(N->getNumOperands()-1); 2108 continue; 2109 2110 case OPC_MoveChild: { 2111 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2112 if (ChildNo >= N.getNumOperands()) 2113 break; // Match fails if out of range child #. 2114 N = N.getOperand(ChildNo); 2115 NodeStack.push_back(N); 2116 continue; 2117 } 2118 2119 case OPC_MoveParent: 2120 // Pop the current node off the NodeStack. 2121 NodeStack.pop_back(); 2122 assert(!NodeStack.empty() && "Node stack imbalance!"); 2123 N = NodeStack.back(); 2124 continue; 2125 2126 case OPC_CheckSame: 2127 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2128 continue; 2129 case OPC_CheckPatternPredicate: 2130 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2131 continue; 2132 case OPC_CheckPredicate: 2133 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2134 N.getNode())) 2135 break; 2136 continue; 2137 case OPC_CheckComplexPat: { 2138 unsigned CPNum = MatcherTable[MatcherIndex++]; 2139 unsigned RecNo = MatcherTable[MatcherIndex++]; 2140 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2141 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2142 RecordedNodes)) 2143 break; 2144 continue; 2145 } 2146 case OPC_CheckOpcode: 2147 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2148 continue; 2149 2150 case OPC_CheckType: 2151 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2152 continue; 2153 2154 case OPC_SwitchOpcode: { 2155 unsigned CurNodeOpcode = N.getOpcode(); 2156 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2157 unsigned CaseSize; 2158 while (1) { 2159 // Get the size of this case. 2160 CaseSize = MatcherTable[MatcherIndex++]; 2161 if (CaseSize & 128) 2162 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2163 if (CaseSize == 0) break; 2164 2165 uint16_t Opc = MatcherTable[MatcherIndex++]; 2166 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2167 2168 // If the opcode matches, then we will execute this case. 2169 if (CurNodeOpcode == Opc) 2170 break; 2171 2172 // Otherwise, skip over this case. 2173 MatcherIndex += CaseSize; 2174 } 2175 2176 // If no cases matched, bail out. 2177 if (CaseSize == 0) break; 2178 2179 // Otherwise, execute the case we found. 2180 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2181 << " to " << MatcherIndex << "\n"); 2182 continue; 2183 } 2184 2185 case OPC_SwitchType: { 2186 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2187 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2188 unsigned CaseSize; 2189 while (1) { 2190 // Get the size of this case. 2191 CaseSize = MatcherTable[MatcherIndex++]; 2192 if (CaseSize & 128) 2193 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2194 if (CaseSize == 0) break; 2195 2196 MVT::SimpleValueType CaseVT = 2197 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2198 if (CaseVT == MVT::iPTR) 2199 CaseVT = TLI.getPointerTy().SimpleTy; 2200 2201 // If the VT matches, then we will execute this case. 2202 if (CurNodeVT == CaseVT) 2203 break; 2204 2205 // Otherwise, skip over this case. 2206 MatcherIndex += CaseSize; 2207 } 2208 2209 // If no cases matched, bail out. 2210 if (CaseSize == 0) break; 2211 2212 // Otherwise, execute the case we found. 2213 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2214 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2215 continue; 2216 } 2217 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2218 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2219 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2220 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2221 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2222 Opcode-OPC_CheckChild0Type)) 2223 break; 2224 continue; 2225 case OPC_CheckCondCode: 2226 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2227 continue; 2228 case OPC_CheckValueType: 2229 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2230 continue; 2231 case OPC_CheckInteger: 2232 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2233 continue; 2234 case OPC_CheckAndImm: 2235 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2236 continue; 2237 case OPC_CheckOrImm: 2238 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2239 continue; 2240 2241 case OPC_CheckFoldableChainNode: { 2242 assert(NodeStack.size() != 1 && "No parent node"); 2243 // Verify that all intermediate nodes between the root and this one have 2244 // a single use. 2245 bool HasMultipleUses = false; 2246 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2247 if (!NodeStack[i].hasOneUse()) { 2248 HasMultipleUses = true; 2249 break; 2250 } 2251 if (HasMultipleUses) break; 2252 2253 // Check to see that the target thinks this is profitable to fold and that 2254 // we can fold it without inducing cycles in the graph. 2255 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2256 NodeToMatch) || 2257 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2258 NodeToMatch, true/*We validate our own chains*/)) 2259 break; 2260 2261 continue; 2262 } 2263 case OPC_EmitInteger: { 2264 MVT::SimpleValueType VT = 2265 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2266 int64_t Val = MatcherTable[MatcherIndex++]; 2267 if (Val & 128) 2268 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2269 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2270 continue; 2271 } 2272 case OPC_EmitRegister: { 2273 MVT::SimpleValueType VT = 2274 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2275 unsigned RegNo = MatcherTable[MatcherIndex++]; 2276 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2277 continue; 2278 } 2279 2280 case OPC_EmitConvertToTarget: { 2281 // Convert from IMM/FPIMM to target version. 2282 unsigned RecNo = MatcherTable[MatcherIndex++]; 2283 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2284 SDValue Imm = RecordedNodes[RecNo]; 2285 2286 if (Imm->getOpcode() == ISD::Constant) { 2287 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2288 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2289 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2290 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2291 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2292 } 2293 2294 RecordedNodes.push_back(Imm); 2295 continue; 2296 } 2297 2298 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2299 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2300 // These are space-optimized forms of OPC_EmitMergeInputChains. 2301 assert(InputChain.getNode() == 0 && 2302 "EmitMergeInputChains should be the first chain producing node"); 2303 assert(ChainNodesMatched.empty() && 2304 "Should only have one EmitMergeInputChains per match"); 2305 2306 // Read all of the chained nodes. 2307 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2308 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2309 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2310 2311 // FIXME: What if other value results of the node have uses not matched 2312 // by this pattern? 2313 if (ChainNodesMatched.back() != NodeToMatch && 2314 !RecordedNodes[RecNo].hasOneUse()) { 2315 ChainNodesMatched.clear(); 2316 break; 2317 } 2318 2319 // Merge the input chains if they are not intra-pattern references. 2320 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2321 2322 if (InputChain.getNode() == 0) 2323 break; // Failed to merge. 2324 continue; 2325 } 2326 2327 case OPC_EmitMergeInputChains: { 2328 assert(InputChain.getNode() == 0 && 2329 "EmitMergeInputChains should be the first chain producing node"); 2330 // This node gets a list of nodes we matched in the input that have 2331 // chains. We want to token factor all of the input chains to these nodes 2332 // together. However, if any of the input chains is actually one of the 2333 // nodes matched in this pattern, then we have an intra-match reference. 2334 // Ignore these because the newly token factored chain should not refer to 2335 // the old nodes. 2336 unsigned NumChains = MatcherTable[MatcherIndex++]; 2337 assert(NumChains != 0 && "Can't TF zero chains"); 2338 2339 assert(ChainNodesMatched.empty() && 2340 "Should only have one EmitMergeInputChains per match"); 2341 2342 // Read all of the chained nodes. 2343 for (unsigned i = 0; i != NumChains; ++i) { 2344 unsigned RecNo = MatcherTable[MatcherIndex++]; 2345 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2346 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2347 2348 // FIXME: What if other value results of the node have uses not matched 2349 // by this pattern? 2350 if (ChainNodesMatched.back() != NodeToMatch && 2351 !RecordedNodes[RecNo].hasOneUse()) { 2352 ChainNodesMatched.clear(); 2353 break; 2354 } 2355 } 2356 2357 // If the inner loop broke out, the match fails. 2358 if (ChainNodesMatched.empty()) 2359 break; 2360 2361 // Merge the input chains if they are not intra-pattern references. 2362 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2363 2364 if (InputChain.getNode() == 0) 2365 break; // Failed to merge. 2366 2367 continue; 2368 } 2369 2370 case OPC_EmitCopyToReg: { 2371 unsigned RecNo = MatcherTable[MatcherIndex++]; 2372 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2373 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2374 2375 if (InputChain.getNode() == 0) 2376 InputChain = CurDAG->getEntryNode(); 2377 2378 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2379 DestPhysReg, RecordedNodes[RecNo], 2380 InputFlag); 2381 2382 InputFlag = InputChain.getValue(1); 2383 continue; 2384 } 2385 2386 case OPC_EmitNodeXForm: { 2387 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2388 unsigned RecNo = MatcherTable[MatcherIndex++]; 2389 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2390 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2391 continue; 2392 } 2393 2394 case OPC_EmitNode: 2395 case OPC_MorphNodeTo: { 2396 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2397 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2398 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2399 // Get the result VT list. 2400 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2401 SmallVector<EVT, 4> VTs; 2402 for (unsigned i = 0; i != NumVTs; ++i) { 2403 MVT::SimpleValueType VT = 2404 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2405 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2406 VTs.push_back(VT); 2407 } 2408 2409 if (EmitNodeInfo & OPFL_Chain) 2410 VTs.push_back(MVT::Other); 2411 if (EmitNodeInfo & OPFL_FlagOutput) 2412 VTs.push_back(MVT::Flag); 2413 2414 // This is hot code, so optimize the two most common cases of 1 and 2 2415 // results. 2416 SDVTList VTList; 2417 if (VTs.size() == 1) 2418 VTList = CurDAG->getVTList(VTs[0]); 2419 else if (VTs.size() == 2) 2420 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2421 else 2422 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2423 2424 // Get the operand list. 2425 unsigned NumOps = MatcherTable[MatcherIndex++]; 2426 SmallVector<SDValue, 8> Ops; 2427 for (unsigned i = 0; i != NumOps; ++i) { 2428 unsigned RecNo = MatcherTable[MatcherIndex++]; 2429 if (RecNo & 128) 2430 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2431 2432 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2433 Ops.push_back(RecordedNodes[RecNo]); 2434 } 2435 2436 // If there are variadic operands to add, handle them now. 2437 if (EmitNodeInfo & OPFL_VariadicInfo) { 2438 // Determine the start index to copy from. 2439 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2440 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2441 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2442 "Invalid variadic node"); 2443 // Copy all of the variadic operands, not including a potential flag 2444 // input. 2445 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2446 i != e; ++i) { 2447 SDValue V = NodeToMatch->getOperand(i); 2448 if (V.getValueType() == MVT::Flag) break; 2449 Ops.push_back(V); 2450 } 2451 } 2452 2453 // If this has chain/flag inputs, add them. 2454 if (EmitNodeInfo & OPFL_Chain) 2455 Ops.push_back(InputChain); 2456 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2457 Ops.push_back(InputFlag); 2458 2459 // Create the node. 2460 SDNode *Res = 0; 2461 if (Opcode != OPC_MorphNodeTo) { 2462 // If this is a normal EmitNode command, just create the new node and 2463 // add the results to the RecordedNodes list. 2464 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2465 VTList, Ops.data(), Ops.size()); 2466 2467 // Add all the non-flag/non-chain results to the RecordedNodes list. 2468 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2469 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2470 RecordedNodes.push_back(SDValue(Res, i)); 2471 } 2472 2473 } else { 2474 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2475 EmitNodeInfo); 2476 } 2477 2478 // If the node had chain/flag results, update our notion of the current 2479 // chain and flag. 2480 if (EmitNodeInfo & OPFL_FlagOutput) { 2481 InputFlag = SDValue(Res, VTs.size()-1); 2482 if (EmitNodeInfo & OPFL_Chain) 2483 InputChain = SDValue(Res, VTs.size()-2); 2484 } else if (EmitNodeInfo & OPFL_Chain) 2485 InputChain = SDValue(Res, VTs.size()-1); 2486 2487 // If the OPFL_MemRefs flag is set on this node, slap all of the 2488 // accumulated memrefs onto it. 2489 // 2490 // FIXME: This is vastly incorrect for patterns with multiple outputs 2491 // instructions that access memory and for ComplexPatterns that match 2492 // loads. 2493 if (EmitNodeInfo & OPFL_MemRefs) { 2494 MachineSDNode::mmo_iterator MemRefs = 2495 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2496 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2497 cast<MachineSDNode>(Res) 2498 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2499 } 2500 2501 DEBUG(errs() << " " 2502 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2503 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2504 2505 // If this was a MorphNodeTo then we're completely done! 2506 if (Opcode == OPC_MorphNodeTo) { 2507 // Update chain and flag uses. 2508 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2509 InputFlag, FlagResultNodesMatched, true); 2510 return Res; 2511 } 2512 2513 continue; 2514 } 2515 2516 case OPC_MarkFlagResults: { 2517 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2518 2519 // Read and remember all the flag-result nodes. 2520 for (unsigned i = 0; i != NumNodes; ++i) { 2521 unsigned RecNo = MatcherTable[MatcherIndex++]; 2522 if (RecNo & 128) 2523 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2524 2525 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2526 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2527 } 2528 continue; 2529 } 2530 2531 case OPC_CompleteMatch: { 2532 // The match has been completed, and any new nodes (if any) have been 2533 // created. Patch up references to the matched dag to use the newly 2534 // created nodes. 2535 unsigned NumResults = MatcherTable[MatcherIndex++]; 2536 2537 for (unsigned i = 0; i != NumResults; ++i) { 2538 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2539 if (ResSlot & 128) 2540 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2541 2542 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2543 SDValue Res = RecordedNodes[ResSlot]; 2544 2545 assert(i < NodeToMatch->getNumValues() && 2546 NodeToMatch->getValueType(i) != MVT::Other && 2547 NodeToMatch->getValueType(i) != MVT::Flag && 2548 "Invalid number of results to complete!"); 2549 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2550 NodeToMatch->getValueType(i) == MVT::iPTR || 2551 Res.getValueType() == MVT::iPTR || 2552 NodeToMatch->getValueType(i).getSizeInBits() == 2553 Res.getValueType().getSizeInBits()) && 2554 "invalid replacement"); 2555 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2556 } 2557 2558 // If the root node defines a flag, add it to the flag nodes to update 2559 // list. 2560 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2561 FlagResultNodesMatched.push_back(NodeToMatch); 2562 2563 // Update chain and flag uses. 2564 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2565 InputFlag, FlagResultNodesMatched, false); 2566 2567 assert(NodeToMatch->use_empty() && 2568 "Didn't replace all uses of the node?"); 2569 2570 // FIXME: We just return here, which interacts correctly with SelectRoot 2571 // above. We should fix this to not return an SDNode* anymore. 2572 return 0; 2573 } 2574 } 2575 2576 // If the code reached this point, then the match failed. See if there is 2577 // another child to try in the current 'Scope', otherwise pop it until we 2578 // find a case to check. 2579 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2580 ++NumDAGIselRetries; 2581 while (1) { 2582 if (MatchScopes.empty()) { 2583 CannotYetSelect(NodeToMatch); 2584 return 0; 2585 } 2586 2587 // Restore the interpreter state back to the point where the scope was 2588 // formed. 2589 MatchScope &LastScope = MatchScopes.back(); 2590 RecordedNodes.resize(LastScope.NumRecordedNodes); 2591 NodeStack.clear(); 2592 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2593 N = NodeStack.back(); 2594 2595 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2596 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2597 MatcherIndex = LastScope.FailIndex; 2598 2599 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2600 2601 InputChain = LastScope.InputChain; 2602 InputFlag = LastScope.InputFlag; 2603 if (!LastScope.HasChainNodesMatched) 2604 ChainNodesMatched.clear(); 2605 if (!LastScope.HasFlagResultNodesMatched) 2606 FlagResultNodesMatched.clear(); 2607 2608 // Check to see what the offset is at the new MatcherIndex. If it is zero 2609 // we have reached the end of this scope, otherwise we have another child 2610 // in the current scope to try. 2611 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2612 if (NumToSkip & 128) 2613 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2614 2615 // If we have another child in this scope to match, update FailIndex and 2616 // try it. 2617 if (NumToSkip != 0) { 2618 LastScope.FailIndex = MatcherIndex+NumToSkip; 2619 break; 2620 } 2621 2622 // End of this scope, pop it and try the next child in the containing 2623 // scope. 2624 MatchScopes.pop_back(); 2625 } 2626 } 2627} 2628 2629 2630 2631void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2632 std::string msg; 2633 raw_string_ostream Msg(msg); 2634 Msg << "Cannot yet select: "; 2635 2636 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2637 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2638 N->getOpcode() != ISD::INTRINSIC_VOID) { 2639 N->printrFull(Msg, CurDAG); 2640 } else { 2641 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2642 unsigned iid = 2643 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2644 if (iid < Intrinsic::num_intrinsics) 2645 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2646 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2647 Msg << "target intrinsic %" << TII->getName(iid); 2648 else 2649 Msg << "unknown intrinsic #" << iid; 2650 } 2651 report_fatal_error(Msg.str()); 2652} 2653 2654char SelectionDAGISel::ID = 0; 2655