SelectionDAGISel.cpp revision 2d76c84514216f51526f2be123315f585995d860
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/CodeGen/FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/Module.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetIntrinsicInfo.h" 42#include "llvm/Target/TargetInstrInfo.h" 43#include "llvm/Target/TargetLowering.h" 44#include "llvm/Target/TargetMachine.h" 45#include "llvm/Target/TargetOptions.h" 46#include "llvm/Transforms/Utils/BasicBlockUtils.h" 47#include "llvm/Support/Compiler.h" 48#include "llvm/Support/Debug.h" 49#include "llvm/Support/ErrorHandling.h" 50#include "llvm/Support/Timer.h" 51#include "llvm/Support/raw_ostream.h" 52#include "llvm/ADT/PostOrderIterator.h" 53#include "llvm/ADT/Statistic.h" 54#include <algorithm> 55using namespace llvm; 56 57STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 58STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 59STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 60STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 61 62#ifndef NDEBUG 63STATISTIC(NumBBWithOutOfOrderLineInfo, 64 "Number of blocks with out of order line number info"); 65STATISTIC(NumMBBWithOutOfOrderLineInfo, 66 "Number of machine blocks with out of order line number info"); 67#endif 68 69static cl::opt<bool> 70EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 71 cl::desc("Enable verbose messages in the \"fast\" " 72 "instruction selector")); 73static cl::opt<bool> 74EnableFastISelAbort("fast-isel-abort", cl::Hidden, 75 cl::desc("Enable abort calls when \"fast\" instruction fails")); 76 77#ifndef NDEBUG 78static cl::opt<bool> 79ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 80 cl::desc("Pop up a window to show dags before the first " 81 "dag combine pass")); 82static cl::opt<bool> 83ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize types")); 85static cl::opt<bool> 86ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before legalize")); 88static cl::opt<bool> 89ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 90 cl::desc("Pop up a window to show dags before the second " 91 "dag combine pass")); 92static cl::opt<bool> 93ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 94 cl::desc("Pop up a window to show dags before the post legalize types" 95 " dag combine pass")); 96static cl::opt<bool> 97ViewISelDAGs("view-isel-dags", cl::Hidden, 98 cl::desc("Pop up a window to show isel dags as they are selected")); 99static cl::opt<bool> 100ViewSchedDAGs("view-sched-dags", cl::Hidden, 101 cl::desc("Pop up a window to show sched dags as they are processed")); 102static cl::opt<bool> 103ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 104 cl::desc("Pop up a window to show SUnit dags after they are processed")); 105#else 106static const bool ViewDAGCombine1 = false, 107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 108 ViewDAGCombine2 = false, 109 ViewDAGCombineLT = false, 110 ViewISelDAGs = false, ViewSchedDAGs = false, 111 ViewSUnitDAGs = false; 112#endif 113 114//===---------------------------------------------------------------------===// 115/// 116/// RegisterScheduler class - Track the registration of instruction schedulers. 117/// 118//===---------------------------------------------------------------------===// 119MachinePassRegistry RegisterScheduler::Registry; 120 121//===---------------------------------------------------------------------===// 122/// 123/// ISHeuristic command line option for instruction schedulers. 124/// 125//===---------------------------------------------------------------------===// 126static cl::opt<RegisterScheduler::FunctionPassCtor, false, 127 RegisterPassParser<RegisterScheduler> > 128ISHeuristic("pre-RA-sched", 129 cl::init(&createDefaultScheduler), 130 cl::desc("Instruction schedulers available (before register" 131 " allocation):")); 132 133static RegisterScheduler 134defaultListDAGScheduler("default", "Best scheduler for the target", 135 createDefaultScheduler); 136 137namespace llvm { 138 //===--------------------------------------------------------------------===// 139 /// createDefaultScheduler - This creates an instruction scheduler appropriate 140 /// for the target. 141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 142 CodeGenOpt::Level OptLevel) { 143 const TargetLowering &TLI = IS->getTargetLowering(); 144 145 if (OptLevel == CodeGenOpt::None) 146 return createSourceListDAGScheduler(IS, OptLevel); 147 if (TLI.getSchedulingPreference() == Sched::Latency) 148 return createTDListDAGScheduler(IS, OptLevel); 149 if (TLI.getSchedulingPreference() == Sched::RegPressure) 150 return createBURRListDAGScheduler(IS, OptLevel); 151 if (TLI.getSchedulingPreference() == Sched::Hybrid) 152 return createHybridListDAGScheduler(IS, OptLevel); 153 assert(TLI.getSchedulingPreference() == Sched::ILP && 154 "Unknown sched type!"); 155 return createILPListDAGScheduler(IS, OptLevel); 156 } 157} 158 159// EmitInstrWithCustomInserter - This method should be implemented by targets 160// that mark instructions with the 'usesCustomInserter' flag. These 161// instructions are special in various ways, which require special support to 162// insert. The specified MachineInstr is created but not inserted into any 163// basic blocks, and this method is called to expand it into a sequence of 164// instructions, potentially also creating new basic blocks and control flow. 165// When new basic blocks are inserted and the edges from MBB to its successors 166// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 167// DenseMap. 168MachineBasicBlock * 169TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 170 MachineBasicBlock *MBB) const { 171#ifndef NDEBUG 172 dbgs() << "If a target marks an instruction with " 173 "'usesCustomInserter', it must implement " 174 "TargetLowering::EmitInstrWithCustomInserter!"; 175#endif 176 llvm_unreachable(0); 177 return 0; 178} 179 180//===----------------------------------------------------------------------===// 181// SelectionDAGISel code 182//===----------------------------------------------------------------------===// 183 184SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, 185 CodeGenOpt::Level OL) : 186 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 187 FuncInfo(new FunctionLoweringInfo(TLI)), 188 CurDAG(new SelectionDAG(tm)), 189 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 190 GFI(), 191 OptLevel(OL), 192 DAGSize(0) { 193 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 194 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 195 } 196 197SelectionDAGISel::~SelectionDAGISel() { 198 delete SDB; 199 delete CurDAG; 200 delete FuncInfo; 201} 202 203void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 204 AU.addRequired<AliasAnalysis>(); 205 AU.addPreserved<AliasAnalysis>(); 206 AU.addRequired<GCModuleInfo>(); 207 AU.addPreserved<GCModuleInfo>(); 208 MachineFunctionPass::getAnalysisUsage(AU); 209} 210 211/// FunctionCallsSetJmp - Return true if the function has a call to setjmp or 212/// other function that gcc recognizes as "returning twice". This is used to 213/// limit code-gen optimizations on the machine function. 214/// 215/// FIXME: Remove after <rdar://problem/8031714> is fixed. 216static bool FunctionCallsSetJmp(const Function *F) { 217 const Module *M = F->getParent(); 218 static const char *ReturnsTwiceFns[] = { 219 "_setjmp", 220 "setjmp", 221 "sigsetjmp", 222 "setjmp_syscall", 223 "savectx", 224 "qsetjmp", 225 "vfork", 226 "getcontext" 227 }; 228#define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *) 229 230 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I) 231 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) { 232 if (!Callee->use_empty()) 233 for (Value::const_use_iterator 234 I = Callee->use_begin(), E = Callee->use_end(); 235 I != E; ++I) 236 if (const CallInst *CI = dyn_cast<CallInst>(*I)) 237 if (CI->getParent()->getParent() == F) 238 return true; 239 } 240 241 return false; 242#undef NUM_RETURNS_TWICE_FNS 243} 244 245/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 246/// may trap on it. In this case we have to split the edge so that the path 247/// through the predecessor block that doesn't go to the phi block doesn't 248/// execute the possibly trapping instruction. 249/// 250/// This is required for correctness, so it must be done at -O0. 251/// 252static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 253 // Loop for blocks with phi nodes. 254 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 255 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 256 if (PN == 0) continue; 257 258 ReprocessBlock: 259 // For each block with a PHI node, check to see if any of the input values 260 // are potentially trapping constant expressions. Constant expressions are 261 // the only potentially trapping value that can occur as the argument to a 262 // PHI. 263 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 264 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 265 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 266 if (CE == 0 || !CE->canTrap()) continue; 267 268 // The only case we have to worry about is when the edge is critical. 269 // Since this block has a PHI Node, we assume it has multiple input 270 // edges: check to see if the pred has multiple successors. 271 BasicBlock *Pred = PN->getIncomingBlock(i); 272 if (Pred->getTerminator()->getNumSuccessors() == 1) 273 continue; 274 275 // Okay, we have to split this edge. 276 SplitCriticalEdge(Pred->getTerminator(), 277 GetSuccessorNumber(Pred, BB), SDISel, true); 278 goto ReprocessBlock; 279 } 280 } 281} 282 283bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 284 // Do some sanity-checking on the command-line options. 285 assert((!EnableFastISelVerbose || EnableFastISel) && 286 "-fast-isel-verbose requires -fast-isel"); 287 assert((!EnableFastISelAbort || EnableFastISel) && 288 "-fast-isel-abort requires -fast-isel"); 289 290 const Function &Fn = *mf.getFunction(); 291 const TargetInstrInfo &TII = *TM.getInstrInfo(); 292 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 293 294 MF = &mf; 295 RegInfo = &MF->getRegInfo(); 296 AA = &getAnalysis<AliasAnalysis>(); 297 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 298 299 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 300 301 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 302 303 CurDAG->init(*MF); 304 FuncInfo->set(Fn, *MF); 305 SDB->init(GFI, *AA); 306 307 SelectAllBasicBlocks(Fn); 308 309 // If the first basic block in the function has live ins that need to be 310 // copied into vregs, emit the copies into the top of the block before 311 // emitting the code for the block. 312 MachineBasicBlock *EntryMBB = MF->begin(); 313 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 314 315 DenseMap<unsigned, unsigned> LiveInMap; 316 if (!FuncInfo->ArgDbgValues.empty()) 317 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 318 E = RegInfo->livein_end(); LI != E; ++LI) 319 if (LI->second) 320 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 321 322 // Insert DBG_VALUE instructions for function arguments to the entry block. 323 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 324 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 325 unsigned Reg = MI->getOperand(0).getReg(); 326 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 327 EntryMBB->insert(EntryMBB->begin(), MI); 328 else { 329 MachineInstr *Def = RegInfo->getVRegDef(Reg); 330 MachineBasicBlock::iterator InsertPos = Def; 331 // FIXME: VR def may not be in entry block. 332 Def->getParent()->insert(llvm::next(InsertPos), MI); 333 } 334 335 // If Reg is live-in then update debug info to track its copy in a vreg. 336 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 337 if (LDI != LiveInMap.end()) { 338 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 339 MachineBasicBlock::iterator InsertPos = Def; 340 const MDNode *Variable = 341 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 342 unsigned Offset = MI->getOperand(1).getImm(); 343 // Def is never a terminator here, so it is ok to increment InsertPos. 344 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 345 TII.get(TargetOpcode::DBG_VALUE)) 346 .addReg(LDI->second, RegState::Debug) 347 .addImm(Offset).addMetadata(Variable); 348 349 // If this vreg is directly copied into an exported register then 350 // that COPY instructions also need DBG_VALUE, if it is the only 351 // user of LDI->second. 352 MachineInstr *CopyUseMI = NULL; 353 for (MachineRegisterInfo::use_iterator 354 UI = RegInfo->use_begin(LDI->second); 355 MachineInstr *UseMI = UI.skipInstruction();) { 356 if (UseMI->isDebugValue()) continue; 357 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 358 CopyUseMI = UseMI; continue; 359 } 360 // Otherwise this is another use or second copy use. 361 CopyUseMI = NULL; break; 362 } 363 if (CopyUseMI) { 364 MachineInstr *NewMI = 365 BuildMI(*MF, CopyUseMI->getDebugLoc(), 366 TII.get(TargetOpcode::DBG_VALUE)) 367 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 368 .addImm(Offset).addMetadata(Variable); 369 EntryMBB->insertAfter(CopyUseMI, NewMI); 370 } 371 } 372 } 373 374 // Determine if there are any calls in this machine function. 375 MachineFrameInfo *MFI = MF->getFrameInfo(); 376 if (!MFI->hasCalls()) { 377 for (MachineFunction::const_iterator 378 I = MF->begin(), E = MF->end(); I != E; ++I) { 379 const MachineBasicBlock *MBB = I; 380 for (MachineBasicBlock::const_iterator 381 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 382 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode()); 383 384 if ((TID.isCall() && !TID.isReturn()) || 385 II->isStackAligningInlineAsm()) { 386 MFI->setHasCalls(true); 387 goto done; 388 } 389 } 390 } 391 done:; 392 } 393 394 // Determine if there is a call to setjmp in the machine function. 395 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn)); 396 397 // Replace forward-declared registers with the registers containing 398 // the desired value. 399 MachineRegisterInfo &MRI = MF->getRegInfo(); 400 for (DenseMap<unsigned, unsigned>::iterator 401 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 402 I != E; ++I) { 403 unsigned From = I->first; 404 unsigned To = I->second; 405 // If To is also scheduled to be replaced, find what its ultimate 406 // replacement is. 407 for (;;) { 408 DenseMap<unsigned, unsigned>::iterator J = 409 FuncInfo->RegFixups.find(To); 410 if (J == E) break; 411 To = J->second; 412 } 413 // Replace it. 414 MRI.replaceRegWith(From, To); 415 } 416 417 // Release function-specific state. SDB and CurDAG are already cleared 418 // at this point. 419 FuncInfo->clear(); 420 421 return true; 422} 423 424void 425SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 426 BasicBlock::const_iterator End, 427 bool &HadTailCall) { 428 // Lower all of the non-terminator instructions. If a call is emitted 429 // as a tail call, cease emitting nodes for this block. Terminators 430 // are handled below. 431 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 432 SDB->visit(*I); 433 434 // Make sure the root of the DAG is up-to-date. 435 CurDAG->setRoot(SDB->getControlRoot()); 436 HadTailCall = SDB->HasTailCall; 437 SDB->clear(); 438 439 // Final step, emit the lowered DAG as machine code. 440 CodeGenAndEmitDAG(); 441 return; 442} 443 444void SelectionDAGISel::ComputeLiveOutVRegInfo() { 445 SmallPtrSet<SDNode*, 128> VisitedNodes; 446 SmallVector<SDNode*, 128> Worklist; 447 448 Worklist.push_back(CurDAG->getRoot().getNode()); 449 450 APInt Mask; 451 APInt KnownZero; 452 APInt KnownOne; 453 454 do { 455 SDNode *N = Worklist.pop_back_val(); 456 457 // If we've already seen this node, ignore it. 458 if (!VisitedNodes.insert(N)) 459 continue; 460 461 // Otherwise, add all chain operands to the worklist. 462 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 463 if (N->getOperand(i).getValueType() == MVT::Other) 464 Worklist.push_back(N->getOperand(i).getNode()); 465 466 // If this is a CopyToReg with a vreg dest, process it. 467 if (N->getOpcode() != ISD::CopyToReg) 468 continue; 469 470 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 471 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 472 continue; 473 474 // Ignore non-scalar or non-integer values. 475 SDValue Src = N->getOperand(2); 476 EVT SrcVT = Src.getValueType(); 477 if (!SrcVT.isInteger() || SrcVT.isVector()) 478 continue; 479 480 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 481 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 482 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 483 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 484 } while (!Worklist.empty()); 485} 486 487void SelectionDAGISel::CodeGenAndEmitDAG() { 488 std::string GroupName; 489 if (TimePassesIsEnabled) 490 GroupName = "Instruction Selection and Scheduling"; 491 std::string BlockName; 492 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 493 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 494 ViewSUnitDAGs) 495 BlockName = MF->getFunction()->getNameStr() + ":" + 496 FuncInfo->MBB->getBasicBlock()->getNameStr(); 497 498 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump()); 499 500 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 501 502 // Run the DAG combiner in pre-legalize mode. 503 { 504 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 505 CurDAG->Combine(Unrestricted, *AA, OptLevel); 506 } 507 508 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump()); 509 510 // Second step, hack on the DAG until it only uses operations and types that 511 // the target supports. 512 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 513 BlockName); 514 515 bool Changed; 516 { 517 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 518 Changed = CurDAG->LegalizeTypes(); 519 } 520 521 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump()); 522 523 if (Changed) { 524 if (ViewDAGCombineLT) 525 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 526 527 // Run the DAG combiner in post-type-legalize mode. 528 { 529 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 530 TimePassesIsEnabled); 531 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 532 } 533 534 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"; 535 CurDAG->dump()); 536 } 537 538 { 539 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 540 Changed = CurDAG->LegalizeVectors(); 541 } 542 543 if (Changed) { 544 { 545 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 546 CurDAG->LegalizeTypes(); 547 } 548 549 if (ViewDAGCombineLT) 550 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 551 552 // Run the DAG combiner in post-type-legalize mode. 553 { 554 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 555 TimePassesIsEnabled); 556 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 557 } 558 559 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"; 560 CurDAG->dump()); 561 } 562 563 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 564 565 { 566 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 567 CurDAG->Legalize(OptLevel); 568 } 569 570 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump()); 571 572 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 573 574 // Run the DAG combiner in post-legalize mode. 575 { 576 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 577 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 578 } 579 580 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump()); 581 582 if (OptLevel != CodeGenOpt::None) 583 ComputeLiveOutVRegInfo(); 584 585 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 586 587 // Third, instruction select all of the operations to machine code, adding the 588 // code to the MachineBasicBlock. 589 { 590 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 591 DoInstructionSelection(); 592 } 593 594 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump()); 595 596 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 597 598 // Schedule machine code. 599 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 600 { 601 NamedRegionTimer T("Instruction Scheduling", GroupName, 602 TimePassesIsEnabled); 603 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt); 604 } 605 606 if (ViewSUnitDAGs) Scheduler->viewGraph(); 607 608 // Emit machine code to BB. This can change 'BB' to the last block being 609 // inserted into. 610 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 611 { 612 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 613 614 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(); 615 FuncInfo->InsertPt = Scheduler->InsertPos; 616 } 617 618 // If the block was split, make sure we update any references that are used to 619 // update PHI nodes later on. 620 if (FirstMBB != LastMBB) 621 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 622 623 // Free the scheduler state. 624 { 625 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 626 TimePassesIsEnabled); 627 delete Scheduler; 628 } 629 630 // Free the SelectionDAG state, now that we're finished with it. 631 CurDAG->clear(); 632} 633 634void SelectionDAGISel::DoInstructionSelection() { 635 DEBUG(errs() << "===== Instruction selection begins:\n"); 636 637 PreprocessISelDAG(); 638 639 // Select target instructions for the DAG. 640 { 641 // Number all nodes with a topological order and set DAGSize. 642 DAGSize = CurDAG->AssignTopologicalOrder(); 643 644 // Create a dummy node (which is not added to allnodes), that adds 645 // a reference to the root node, preventing it from being deleted, 646 // and tracking any changes of the root. 647 HandleSDNode Dummy(CurDAG->getRoot()); 648 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 649 ++ISelPosition; 650 651 // The AllNodes list is now topological-sorted. Visit the 652 // nodes by starting at the end of the list (the root of the 653 // graph) and preceding back toward the beginning (the entry 654 // node). 655 while (ISelPosition != CurDAG->allnodes_begin()) { 656 SDNode *Node = --ISelPosition; 657 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 658 // but there are currently some corner cases that it misses. Also, this 659 // makes it theoretically possible to disable the DAGCombiner. 660 if (Node->use_empty()) 661 continue; 662 663 SDNode *ResNode = Select(Node); 664 665 // FIXME: This is pretty gross. 'Select' should be changed to not return 666 // anything at all and this code should be nuked with a tactical strike. 667 668 // If node should not be replaced, continue with the next one. 669 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 670 continue; 671 // Replace node. 672 if (ResNode) 673 ReplaceUses(Node, ResNode); 674 675 // If after the replacement this node is not used any more, 676 // remove this dead node. 677 if (Node->use_empty()) { // Don't delete EntryToken, etc. 678 ISelUpdater ISU(ISelPosition); 679 CurDAG->RemoveDeadNode(Node, &ISU); 680 } 681 } 682 683 CurDAG->setRoot(Dummy.getValue()); 684 } 685 686 DEBUG(errs() << "===== Instruction selection ends:\n"); 687 688 PostprocessISelDAG(); 689} 690 691/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 692/// do other setup for EH landing-pad blocks. 693void SelectionDAGISel::PrepareEHLandingPad() { 694 // Add a label to mark the beginning of the landing pad. Deletion of the 695 // landing pad can thus be detected via the MachineModuleInfo. 696 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB); 697 698 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 699 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 700 .addSym(Label); 701 702 // Mark exception register as live in. 703 unsigned Reg = TLI.getExceptionAddressRegister(); 704 if (Reg) FuncInfo->MBB->addLiveIn(Reg); 705 706 // Mark exception selector register as live in. 707 Reg = TLI.getExceptionSelectorRegister(); 708 if (Reg) FuncInfo->MBB->addLiveIn(Reg); 709 710 // FIXME: Hack around an exception handling flaw (PR1508): the personality 711 // function and list of typeids logically belong to the invoke (or, if you 712 // like, the basic block containing the invoke), and need to be associated 713 // with it in the dwarf exception handling tables. Currently however the 714 // information is provided by an intrinsic (eh.selector) that can be moved 715 // to unexpected places by the optimizers: if the unwind edge is critical, 716 // then breaking it can result in the intrinsics being in the successor of 717 // the landing pad, not the landing pad itself. This results 718 // in exceptions not being caught because no typeids are associated with 719 // the invoke. This may not be the only way things can go wrong, but it 720 // is the only way we try to work around for the moment. 721 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock(); 722 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 723 724 if (Br && Br->isUnconditional()) { // Critical edge? 725 BasicBlock::const_iterator I, E; 726 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 727 if (isa<EHSelectorInst>(I)) 728 break; 729 730 if (I == E) 731 // No catch info found - try to extract some from the successor. 732 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 733 } 734} 735 736 737 738 739bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI, 740 FastISel *FastIS) { 741 // Don't try to fold volatile loads. Target has to deal with alignment 742 // constraints. 743 if (LI->isVolatile()) return false; 744 745 // Figure out which vreg this is going into. 746 unsigned LoadReg = FastIS->getRegForValue(LI); 747 assert(LoadReg && "Load isn't already assigned a vreg? "); 748 749 // Check to see what the uses of this vreg are. If it has no uses, or more 750 // than one use (at the machine instr level) then we can't fold it. 751 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg); 752 if (RI == RegInfo->reg_end()) 753 return false; 754 755 // See if there is exactly one use of the vreg. If there are multiple uses, 756 // then the instruction got lowered to multiple machine instructions or the 757 // use of the loaded value ended up being multiple operands of the result, in 758 // either case, we can't fold this. 759 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI; 760 if (PostRI != RegInfo->reg_end()) 761 return false; 762 763 assert(RI.getOperand().isUse() && 764 "The only use of the vreg must be a use, we haven't emitted the def!"); 765 766 MachineInstr *User = &*RI; 767 768 // Set the insertion point properly. Folding the load can cause generation of 769 // other random instructions (like sign extends) for addressing modes, make 770 // sure they get inserted in a logical place before the new instruction. 771 FuncInfo->InsertPt = User; 772 FuncInfo->MBB = User->getParent(); 773 774 // Ask the target to try folding the load. 775 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI); 776} 777 778#ifndef NDEBUG 779/// CheckLineNumbers - Check if basic block instructions follow source order 780/// or not. 781static void CheckLineNumbers(const BasicBlock *BB) { 782 unsigned Line = 0; 783 unsigned Col = 0; 784 for (BasicBlock::const_iterator BI = BB->begin(), 785 BE = BB->end(); BI != BE; ++BI) { 786 const DebugLoc DL = BI->getDebugLoc(); 787 if (DL.isUnknown()) continue; 788 unsigned L = DL.getLine(); 789 unsigned C = DL.getCol(); 790 if (L < Line || (L == Line && C < Col)) { 791 ++NumBBWithOutOfOrderLineInfo; 792 return; 793 } 794 Line = L; 795 Col = C; 796 } 797} 798 799/// CheckLineNumbers - Check if machine basic block instructions follow source 800/// order or not. 801static void CheckLineNumbers(const MachineBasicBlock *MBB) { 802 unsigned Line = 0; 803 unsigned Col = 0; 804 for (MachineBasicBlock::const_iterator MBI = MBB->begin(), 805 MBE = MBB->end(); MBI != MBE; ++MBI) { 806 const DebugLoc DL = MBI->getDebugLoc(); 807 if (DL.isUnknown()) continue; 808 unsigned L = DL.getLine(); 809 unsigned C = DL.getCol(); 810 if (L < Line || (L == Line && C < Col)) { 811 ++NumMBBWithOutOfOrderLineInfo; 812 return; 813 } 814 Line = L; 815 Col = C; 816 } 817} 818#endif 819 820void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 821 // Initialize the Fast-ISel state, if needed. 822 FastISel *FastIS = 0; 823 if (EnableFastISel) 824 FastIS = TLI.createFastISel(*FuncInfo); 825 826 // Iterate over all basic blocks in the function. 827 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 828 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 829 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 830 const BasicBlock *LLVMBB = *I; 831#ifndef NDEBUG 832 CheckLineNumbers(LLVMBB); 833#endif 834 835 if (OptLevel != CodeGenOpt::None) { 836 bool AllPredsVisited = true; 837 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 838 PI != PE; ++PI) { 839 if (!FuncInfo->VisitedBBs.count(*PI)) { 840 AllPredsVisited = false; 841 break; 842 } 843 } 844 845 if (AllPredsVisited) { 846 for (BasicBlock::const_iterator I = LLVMBB->begin(), E = LLVMBB->end(); 847 I != E && isa<PHINode>(I); ++I) { 848 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I)); 849 } 850 } else { 851 for (BasicBlock::const_iterator I = LLVMBB->begin(), E = LLVMBB->end(); 852 I != E && isa<PHINode>(I); ++I) { 853 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I)); 854 } 855 } 856 857 FuncInfo->VisitedBBs.insert(LLVMBB); 858 } 859 860 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 861 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 862 863 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 864 BasicBlock::const_iterator const End = LLVMBB->end(); 865 BasicBlock::const_iterator BI = End; 866 867 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 868 869 // Setup an EH landing-pad block. 870 if (FuncInfo->MBB->isLandingPad()) 871 PrepareEHLandingPad(); 872 873 // Lower any arguments needed in this block if this is the entry block. 874 if (LLVMBB == &Fn.getEntryBlock()) 875 LowerArguments(LLVMBB); 876 877 // Before doing SelectionDAG ISel, see if FastISel has been requested. 878 if (FastIS) { 879 FastIS->startNewBlock(); 880 881 // Emit code for any incoming arguments. This must happen before 882 // beginning FastISel on the entry block. 883 if (LLVMBB == &Fn.getEntryBlock()) { 884 CurDAG->setRoot(SDB->getControlRoot()); 885 SDB->clear(); 886 CodeGenAndEmitDAG(); 887 888 // If we inserted any instructions at the beginning, make a note of 889 // where they are, so we can be sure to emit subsequent instructions 890 // after them. 891 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 892 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 893 else 894 FastIS->setLastLocalValue(0); 895 } 896 897 // Do FastISel on as many instructions as possible. 898 for (; BI != Begin; --BI) { 899 const Instruction *Inst = llvm::prior(BI); 900 901 // If we no longer require this instruction, skip it. 902 if (!Inst->mayWriteToMemory() && 903 !isa<TerminatorInst>(Inst) && 904 !isa<DbgInfoIntrinsic>(Inst) && 905 !FuncInfo->isExportedInst(Inst)) 906 continue; 907 908 // Bottom-up: reset the insert pos at the top, after any local-value 909 // instructions. 910 FastIS->recomputeInsertPt(); 911 912 // Try to select the instruction with FastISel. 913 if (FastIS->SelectInstruction(Inst)) { 914 // If fast isel succeeded, check to see if there is a single-use 915 // non-volatile load right before the selected instruction, and see if 916 // the load is used by the instruction. If so, try to fold it. 917 const Instruction *BeforeInst = 0; 918 if (Inst != Begin) 919 BeforeInst = llvm::prior(llvm::prior(BI)); 920 if (BeforeInst && isa<LoadInst>(BeforeInst) && 921 BeforeInst->hasOneUse() && *BeforeInst->use_begin() == Inst && 922 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), FastIS)) 923 --BI; // If we succeeded, don't re-select the load. 924 continue; 925 } 926 927 // Then handle certain instructions as single-LLVM-Instruction blocks. 928 if (isa<CallInst>(Inst)) { 929 ++NumFastIselFailures; 930 if (EnableFastISelVerbose || EnableFastISelAbort) { 931 dbgs() << "FastISel missed call: "; 932 Inst->dump(); 933 } 934 935 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 936 unsigned &R = FuncInfo->ValueMap[Inst]; 937 if (!R) 938 R = FuncInfo->CreateRegs(Inst->getType()); 939 } 940 941 bool HadTailCall = false; 942 SelectBasicBlock(Inst, BI, HadTailCall); 943 944 // If the call was emitted as a tail call, we're done with the block. 945 if (HadTailCall) { 946 --BI; 947 break; 948 } 949 950 continue; 951 } 952 953 // Otherwise, give up on FastISel for the rest of the block. 954 // For now, be a little lenient about non-branch terminators. 955 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) { 956 ++NumFastIselFailures; 957 if (EnableFastISelVerbose || EnableFastISelAbort) { 958 dbgs() << "FastISel miss: "; 959 Inst->dump(); 960 } 961 if (EnableFastISelAbort) 962 // The "fast" selector couldn't handle something and bailed. 963 // For the purpose of debugging, just abort. 964 llvm_unreachable("FastISel didn't select the entire block"); 965 } 966 break; 967 } 968 969 FastIS->recomputeInsertPt(); 970 } 971 972 if (Begin != BI) 973 ++NumDAGBlocks; 974 else 975 ++NumFastIselBlocks; 976 977 // Run SelectionDAG instruction selection on the remainder of the block 978 // not handled by FastISel. If FastISel is not run, this is the entire 979 // block. 980 bool HadTailCall; 981 SelectBasicBlock(Begin, BI, HadTailCall); 982 983 FinishBasicBlock(); 984 FuncInfo->PHINodesToUpdate.clear(); 985 } 986 987 delete FastIS; 988#ifndef NDEBUG 989 for (MachineFunction::const_iterator MBI = MF->begin(), MBE = MF->end(); 990 MBI != MBE; ++MBI) 991 CheckLineNumbers(MBI); 992#endif 993} 994 995void 996SelectionDAGISel::FinishBasicBlock() { 997 998 DEBUG(dbgs() << "Total amount of phi nodes to update: " 999 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1000 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1001 dbgs() << "Node " << i << " : (" 1002 << FuncInfo->PHINodesToUpdate[i].first 1003 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1004 1005 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1006 // PHI nodes in successors. 1007 if (SDB->SwitchCases.empty() && 1008 SDB->JTCases.empty() && 1009 SDB->BitTestCases.empty()) { 1010 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1011 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1012 assert(PHI->isPHI() && 1013 "This is not a machine PHI node that we are updating!"); 1014 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1015 continue; 1016 PHI->addOperand( 1017 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1018 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1019 } 1020 return; 1021 } 1022 1023 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1024 // Lower header first, if it wasn't already lowered 1025 if (!SDB->BitTestCases[i].Emitted) { 1026 // Set the current basic block to the mbb we wish to insert the code into 1027 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1028 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1029 // Emit the code 1030 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1031 CurDAG->setRoot(SDB->getRoot()); 1032 SDB->clear(); 1033 CodeGenAndEmitDAG(); 1034 } 1035 1036 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1037 // Set the current basic block to the mbb we wish to insert the code into 1038 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1039 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1040 // Emit the code 1041 if (j+1 != ej) 1042 SDB->visitBitTestCase(SDB->BitTestCases[i], 1043 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1044 SDB->BitTestCases[i].Reg, 1045 SDB->BitTestCases[i].Cases[j], 1046 FuncInfo->MBB); 1047 else 1048 SDB->visitBitTestCase(SDB->BitTestCases[i], 1049 SDB->BitTestCases[i].Default, 1050 SDB->BitTestCases[i].Reg, 1051 SDB->BitTestCases[i].Cases[j], 1052 FuncInfo->MBB); 1053 1054 1055 CurDAG->setRoot(SDB->getRoot()); 1056 SDB->clear(); 1057 CodeGenAndEmitDAG(); 1058 } 1059 1060 // Update PHI Nodes 1061 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1062 pi != pe; ++pi) { 1063 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1064 MachineBasicBlock *PHIBB = PHI->getParent(); 1065 assert(PHI->isPHI() && 1066 "This is not a machine PHI node that we are updating!"); 1067 // This is "default" BB. We have two jumps to it. From "header" BB and 1068 // from last "case" BB. 1069 if (PHIBB == SDB->BitTestCases[i].Default) { 1070 PHI->addOperand(MachineOperand:: 1071 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1072 false)); 1073 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1074 PHI->addOperand(MachineOperand:: 1075 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1076 false)); 1077 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1078 back().ThisBB)); 1079 } 1080 // One of "cases" BB. 1081 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1082 j != ej; ++j) { 1083 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1084 if (cBB->isSuccessor(PHIBB)) { 1085 PHI->addOperand(MachineOperand:: 1086 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1087 false)); 1088 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1089 } 1090 } 1091 } 1092 } 1093 SDB->BitTestCases.clear(); 1094 1095 // If the JumpTable record is filled in, then we need to emit a jump table. 1096 // Updating the PHI nodes is tricky in this case, since we need to determine 1097 // whether the PHI is a successor of the range check MBB or the jump table MBB 1098 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1099 // Lower header first, if it wasn't already lowered 1100 if (!SDB->JTCases[i].first.Emitted) { 1101 // Set the current basic block to the mbb we wish to insert the code into 1102 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1103 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1104 // Emit the code 1105 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1106 FuncInfo->MBB); 1107 CurDAG->setRoot(SDB->getRoot()); 1108 SDB->clear(); 1109 CodeGenAndEmitDAG(); 1110 } 1111 1112 // Set the current basic block to the mbb we wish to insert the code into 1113 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1114 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1115 // Emit the code 1116 SDB->visitJumpTable(SDB->JTCases[i].second); 1117 CurDAG->setRoot(SDB->getRoot()); 1118 SDB->clear(); 1119 CodeGenAndEmitDAG(); 1120 1121 // Update PHI Nodes 1122 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1123 pi != pe; ++pi) { 1124 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1125 MachineBasicBlock *PHIBB = PHI->getParent(); 1126 assert(PHI->isPHI() && 1127 "This is not a machine PHI node that we are updating!"); 1128 // "default" BB. We can go there only from header BB. 1129 if (PHIBB == SDB->JTCases[i].second.Default) { 1130 PHI->addOperand 1131 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1132 false)); 1133 PHI->addOperand 1134 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1135 } 1136 // JT BB. Just iterate over successors here 1137 if (FuncInfo->MBB->isSuccessor(PHIBB)) { 1138 PHI->addOperand 1139 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1140 false)); 1141 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1142 } 1143 } 1144 } 1145 SDB->JTCases.clear(); 1146 1147 // If the switch block involved a branch to one of the actual successors, we 1148 // need to update PHI nodes in that block. 1149 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1150 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1151 assert(PHI->isPHI() && 1152 "This is not a machine PHI node that we are updating!"); 1153 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) { 1154 PHI->addOperand( 1155 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1156 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1157 } 1158 } 1159 1160 // If we generated any switch lowering information, build and codegen any 1161 // additional DAGs necessary. 1162 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1163 // Set the current basic block to the mbb we wish to insert the code into 1164 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1165 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1166 1167 // Determine the unique successors. 1168 SmallVector<MachineBasicBlock *, 2> Succs; 1169 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1170 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1171 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1172 1173 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1174 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1175 CurDAG->setRoot(SDB->getRoot()); 1176 SDB->clear(); 1177 CodeGenAndEmitDAG(); 1178 1179 // Remember the last block, now that any splitting is done, for use in 1180 // populating PHI nodes in successors. 1181 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1182 1183 // Handle any PHI nodes in successors of this chunk, as if we were coming 1184 // from the original BB before switch expansion. Note that PHI nodes can 1185 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1186 // handle them the right number of times. 1187 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1188 FuncInfo->MBB = Succs[i]; 1189 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1190 // FuncInfo->MBB may have been removed from the CFG if a branch was 1191 // constant folded. 1192 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1193 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin(); 1194 Phi != FuncInfo->MBB->end() && Phi->isPHI(); 1195 ++Phi) { 1196 // This value for this PHI node is recorded in PHINodesToUpdate. 1197 for (unsigned pn = 0; ; ++pn) { 1198 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1199 "Didn't find PHI entry!"); 1200 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 1201 Phi->addOperand(MachineOperand:: 1202 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 1203 false)); 1204 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1205 break; 1206 } 1207 } 1208 } 1209 } 1210 } 1211 } 1212 SDB->SwitchCases.clear(); 1213} 1214 1215 1216/// Create the scheduler. If a specific scheduler was specified 1217/// via the SchedulerRegistry, use it, otherwise select the 1218/// one preferred by the target. 1219/// 1220ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1221 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1222 1223 if (!Ctor) { 1224 Ctor = ISHeuristic; 1225 RegisterScheduler::setDefault(Ctor); 1226 } 1227 1228 return Ctor(this, OptLevel); 1229} 1230 1231//===----------------------------------------------------------------------===// 1232// Helper functions used by the generated instruction selector. 1233//===----------------------------------------------------------------------===// 1234// Calls to these methods are generated by tblgen. 1235 1236/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1237/// the dag combiner simplified the 255, we still want to match. RHS is the 1238/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1239/// specified in the .td file (e.g. 255). 1240bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1241 int64_t DesiredMaskS) const { 1242 const APInt &ActualMask = RHS->getAPIntValue(); 1243 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1244 1245 // If the actual mask exactly matches, success! 1246 if (ActualMask == DesiredMask) 1247 return true; 1248 1249 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1250 if (ActualMask.intersects(~DesiredMask)) 1251 return false; 1252 1253 // Otherwise, the DAG Combiner may have proven that the value coming in is 1254 // either already zero or is not demanded. Check for known zero input bits. 1255 APInt NeededMask = DesiredMask & ~ActualMask; 1256 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1257 return true; 1258 1259 // TODO: check to see if missing bits are just not demanded. 1260 1261 // Otherwise, this pattern doesn't match. 1262 return false; 1263} 1264 1265/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1266/// the dag combiner simplified the 255, we still want to match. RHS is the 1267/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1268/// specified in the .td file (e.g. 255). 1269bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1270 int64_t DesiredMaskS) const { 1271 const APInt &ActualMask = RHS->getAPIntValue(); 1272 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1273 1274 // If the actual mask exactly matches, success! 1275 if (ActualMask == DesiredMask) 1276 return true; 1277 1278 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1279 if (ActualMask.intersects(~DesiredMask)) 1280 return false; 1281 1282 // Otherwise, the DAG Combiner may have proven that the value coming in is 1283 // either already zero or is not demanded. Check for known zero input bits. 1284 APInt NeededMask = DesiredMask & ~ActualMask; 1285 1286 APInt KnownZero, KnownOne; 1287 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1288 1289 // If all the missing bits in the or are already known to be set, match! 1290 if ((NeededMask & KnownOne) == NeededMask) 1291 return true; 1292 1293 // TODO: check to see if missing bits are just not demanded. 1294 1295 // Otherwise, this pattern doesn't match. 1296 return false; 1297} 1298 1299 1300/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1301/// by tblgen. Others should not call it. 1302void SelectionDAGISel:: 1303SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1304 std::vector<SDValue> InOps; 1305 std::swap(InOps, Ops); 1306 1307 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1308 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1309 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1310 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1311 1312 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1313 if (InOps[e-1].getValueType() == MVT::Glue) 1314 --e; // Don't process a glue operand if it is here. 1315 1316 while (i != e) { 1317 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1318 if (!InlineAsm::isMemKind(Flags)) { 1319 // Just skip over this operand, copying the operands verbatim. 1320 Ops.insert(Ops.end(), InOps.begin()+i, 1321 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1322 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1323 } else { 1324 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1325 "Memory operand with multiple values?"); 1326 // Otherwise, this is a memory operand. Ask the target to select it. 1327 std::vector<SDValue> SelOps; 1328 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1329 report_fatal_error("Could not match memory address. Inline asm" 1330 " failure!"); 1331 1332 // Add this to the output node. 1333 unsigned NewFlags = 1334 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1335 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1336 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1337 i += 2; 1338 } 1339 } 1340 1341 // Add the glue input back if present. 1342 if (e != InOps.size()) 1343 Ops.push_back(InOps.back()); 1344} 1345 1346/// findGlueUse - Return use of MVT::Glue value produced by the specified 1347/// SDNode. 1348/// 1349static SDNode *findGlueUse(SDNode *N) { 1350 unsigned FlagResNo = N->getNumValues()-1; 1351 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1352 SDUse &Use = I.getUse(); 1353 if (Use.getResNo() == FlagResNo) 1354 return Use.getUser(); 1355 } 1356 return NULL; 1357} 1358 1359/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1360/// This function recursively traverses up the operand chain, ignoring 1361/// certain nodes. 1362static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1363 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1364 bool IgnoreChains) { 1365 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1366 // greater than all of its (recursive) operands. If we scan to a point where 1367 // 'use' is smaller than the node we're scanning for, then we know we will 1368 // never find it. 1369 // 1370 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1371 // happen because we scan down to newly selected nodes in the case of glue 1372 // uses. 1373 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1374 return false; 1375 1376 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1377 // won't fail if we scan it again. 1378 if (!Visited.insert(Use)) 1379 return false; 1380 1381 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1382 // Ignore chain uses, they are validated by HandleMergeInputChains. 1383 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1384 continue; 1385 1386 SDNode *N = Use->getOperand(i).getNode(); 1387 if (N == Def) { 1388 if (Use == ImmedUse || Use == Root) 1389 continue; // We are not looking for immediate use. 1390 assert(N != Root); 1391 return true; 1392 } 1393 1394 // Traverse up the operand chain. 1395 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1396 return true; 1397 } 1398 return false; 1399} 1400 1401/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1402/// operand node N of U during instruction selection that starts at Root. 1403bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1404 SDNode *Root) const { 1405 if (OptLevel == CodeGenOpt::None) return false; 1406 return N.hasOneUse(); 1407} 1408 1409/// IsLegalToFold - Returns true if the specific operand node N of 1410/// U can be folded during instruction selection that starts at Root. 1411bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1412 CodeGenOpt::Level OptLevel, 1413 bool IgnoreChains) { 1414 if (OptLevel == CodeGenOpt::None) return false; 1415 1416 // If Root use can somehow reach N through a path that that doesn't contain 1417 // U then folding N would create a cycle. e.g. In the following 1418 // diagram, Root can reach N through X. If N is folded into into Root, then 1419 // X is both a predecessor and a successor of U. 1420 // 1421 // [N*] // 1422 // ^ ^ // 1423 // / \ // 1424 // [U*] [X]? // 1425 // ^ ^ // 1426 // \ / // 1427 // \ / // 1428 // [Root*] // 1429 // 1430 // * indicates nodes to be folded together. 1431 // 1432 // If Root produces glue, then it gets (even more) interesting. Since it 1433 // will be "glued" together with its glue use in the scheduler, we need to 1434 // check if it might reach N. 1435 // 1436 // [N*] // 1437 // ^ ^ // 1438 // / \ // 1439 // [U*] [X]? // 1440 // ^ ^ // 1441 // \ \ // 1442 // \ | // 1443 // [Root*] | // 1444 // ^ | // 1445 // f | // 1446 // | / // 1447 // [Y] / // 1448 // ^ / // 1449 // f / // 1450 // | / // 1451 // [GU] // 1452 // 1453 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1454 // (call it Fold), then X is a predecessor of GU and a successor of 1455 // Fold. But since Fold and GU are glued together, this will create 1456 // a cycle in the scheduling graph. 1457 1458 // If the node has glue, walk down the graph to the "lowest" node in the 1459 // glueged set. 1460 EVT VT = Root->getValueType(Root->getNumValues()-1); 1461 while (VT == MVT::Glue) { 1462 SDNode *GU = findGlueUse(Root); 1463 if (GU == NULL) 1464 break; 1465 Root = GU; 1466 VT = Root->getValueType(Root->getNumValues()-1); 1467 1468 // If our query node has a glue result with a use, we've walked up it. If 1469 // the user (which has already been selected) has a chain or indirectly uses 1470 // the chain, our WalkChainUsers predicate will not consider it. Because of 1471 // this, we cannot ignore chains in this predicate. 1472 IgnoreChains = false; 1473 } 1474 1475 1476 SmallPtrSet<SDNode*, 16> Visited; 1477 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1478} 1479 1480SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1481 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1482 SelectInlineAsmMemoryOperands(Ops); 1483 1484 std::vector<EVT> VTs; 1485 VTs.push_back(MVT::Other); 1486 VTs.push_back(MVT::Glue); 1487 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1488 VTs, &Ops[0], Ops.size()); 1489 New->setNodeId(-1); 1490 return New.getNode(); 1491} 1492 1493SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1494 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1495} 1496 1497/// GetVBR - decode a vbr encoding whose top bit is set. 1498LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1499GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1500 assert(Val >= 128 && "Not a VBR"); 1501 Val &= 127; // Remove first vbr bit. 1502 1503 unsigned Shift = 7; 1504 uint64_t NextBits; 1505 do { 1506 NextBits = MatcherTable[Idx++]; 1507 Val |= (NextBits&127) << Shift; 1508 Shift += 7; 1509 } while (NextBits & 128); 1510 1511 return Val; 1512} 1513 1514 1515/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1516/// interior glue and chain results to use the new glue and chain results. 1517void SelectionDAGISel:: 1518UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1519 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1520 SDValue InputGlue, 1521 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1522 bool isMorphNodeTo) { 1523 SmallVector<SDNode*, 4> NowDeadNodes; 1524 1525 ISelUpdater ISU(ISelPosition); 1526 1527 // Now that all the normal results are replaced, we replace the chain and 1528 // glue results if present. 1529 if (!ChainNodesMatched.empty()) { 1530 assert(InputChain.getNode() != 0 && 1531 "Matched input chains but didn't produce a chain"); 1532 // Loop over all of the nodes we matched that produced a chain result. 1533 // Replace all the chain results with the final chain we ended up with. 1534 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1535 SDNode *ChainNode = ChainNodesMatched[i]; 1536 1537 // If this node was already deleted, don't look at it. 1538 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1539 continue; 1540 1541 // Don't replace the results of the root node if we're doing a 1542 // MorphNodeTo. 1543 if (ChainNode == NodeToMatch && isMorphNodeTo) 1544 continue; 1545 1546 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1547 if (ChainVal.getValueType() == MVT::Glue) 1548 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1549 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1550 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1551 1552 // If the node became dead and we haven't already seen it, delete it. 1553 if (ChainNode->use_empty() && 1554 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1555 NowDeadNodes.push_back(ChainNode); 1556 } 1557 } 1558 1559 // If the result produces glue, update any glue results in the matched 1560 // pattern with the glue result. 1561 if (InputGlue.getNode() != 0) { 1562 // Handle any interior nodes explicitly marked. 1563 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1564 SDNode *FRN = GlueResultNodesMatched[i]; 1565 1566 // If this node was already deleted, don't look at it. 1567 if (FRN->getOpcode() == ISD::DELETED_NODE) 1568 continue; 1569 1570 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1571 "Doesn't have a glue result"); 1572 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1573 InputGlue, &ISU); 1574 1575 // If the node became dead and we haven't already seen it, delete it. 1576 if (FRN->use_empty() && 1577 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1578 NowDeadNodes.push_back(FRN); 1579 } 1580 } 1581 1582 if (!NowDeadNodes.empty()) 1583 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1584 1585 DEBUG(errs() << "ISEL: Match complete!\n"); 1586} 1587 1588enum ChainResult { 1589 CR_Simple, 1590 CR_InducesCycle, 1591 CR_LeadsToInteriorNode 1592}; 1593 1594/// WalkChainUsers - Walk down the users of the specified chained node that is 1595/// part of the pattern we're matching, looking at all of the users we find. 1596/// This determines whether something is an interior node, whether we have a 1597/// non-pattern node in between two pattern nodes (which prevent folding because 1598/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1599/// between pattern nodes (in which case the TF becomes part of the pattern). 1600/// 1601/// The walk we do here is guaranteed to be small because we quickly get down to 1602/// already selected nodes "below" us. 1603static ChainResult 1604WalkChainUsers(SDNode *ChainedNode, 1605 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1606 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1607 ChainResult Result = CR_Simple; 1608 1609 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1610 E = ChainedNode->use_end(); UI != E; ++UI) { 1611 // Make sure the use is of the chain, not some other value we produce. 1612 if (UI.getUse().getValueType() != MVT::Other) continue; 1613 1614 SDNode *User = *UI; 1615 1616 // If we see an already-selected machine node, then we've gone beyond the 1617 // pattern that we're selecting down into the already selected chunk of the 1618 // DAG. 1619 if (User->isMachineOpcode() || 1620 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1621 continue; 1622 1623 if (User->getOpcode() == ISD::CopyToReg || 1624 User->getOpcode() == ISD::CopyFromReg || 1625 User->getOpcode() == ISD::INLINEASM || 1626 User->getOpcode() == ISD::EH_LABEL) { 1627 // If their node ID got reset to -1 then they've already been selected. 1628 // Treat them like a MachineOpcode. 1629 if (User->getNodeId() == -1) 1630 continue; 1631 } 1632 1633 // If we have a TokenFactor, we handle it specially. 1634 if (User->getOpcode() != ISD::TokenFactor) { 1635 // If the node isn't a token factor and isn't part of our pattern, then it 1636 // must be a random chained node in between two nodes we're selecting. 1637 // This happens when we have something like: 1638 // x = load ptr 1639 // call 1640 // y = x+4 1641 // store y -> ptr 1642 // Because we structurally match the load/store as a read/modify/write, 1643 // but the call is chained between them. We cannot fold in this case 1644 // because it would induce a cycle in the graph. 1645 if (!std::count(ChainedNodesInPattern.begin(), 1646 ChainedNodesInPattern.end(), User)) 1647 return CR_InducesCycle; 1648 1649 // Otherwise we found a node that is part of our pattern. For example in: 1650 // x = load ptr 1651 // y = x+4 1652 // store y -> ptr 1653 // This would happen when we're scanning down from the load and see the 1654 // store as a user. Record that there is a use of ChainedNode that is 1655 // part of the pattern and keep scanning uses. 1656 Result = CR_LeadsToInteriorNode; 1657 InteriorChainedNodes.push_back(User); 1658 continue; 1659 } 1660 1661 // If we found a TokenFactor, there are two cases to consider: first if the 1662 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1663 // uses of the TF are in our pattern) we just want to ignore it. Second, 1664 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1665 // [Load chain] 1666 // ^ 1667 // | 1668 // [Load] 1669 // ^ ^ 1670 // | \ DAG's like cheese 1671 // / \ do you? 1672 // / | 1673 // [TokenFactor] [Op] 1674 // ^ ^ 1675 // | | 1676 // \ / 1677 // \ / 1678 // [Store] 1679 // 1680 // In this case, the TokenFactor becomes part of our match and we rewrite it 1681 // as a new TokenFactor. 1682 // 1683 // To distinguish these two cases, do a recursive walk down the uses. 1684 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1685 case CR_Simple: 1686 // If the uses of the TokenFactor are just already-selected nodes, ignore 1687 // it, it is "below" our pattern. 1688 continue; 1689 case CR_InducesCycle: 1690 // If the uses of the TokenFactor lead to nodes that are not part of our 1691 // pattern that are not selected, folding would turn this into a cycle, 1692 // bail out now. 1693 return CR_InducesCycle; 1694 case CR_LeadsToInteriorNode: 1695 break; // Otherwise, keep processing. 1696 } 1697 1698 // Okay, we know we're in the interesting interior case. The TokenFactor 1699 // is now going to be considered part of the pattern so that we rewrite its 1700 // uses (it may have uses that are not part of the pattern) with the 1701 // ultimate chain result of the generated code. We will also add its chain 1702 // inputs as inputs to the ultimate TokenFactor we create. 1703 Result = CR_LeadsToInteriorNode; 1704 ChainedNodesInPattern.push_back(User); 1705 InteriorChainedNodes.push_back(User); 1706 continue; 1707 } 1708 1709 return Result; 1710} 1711 1712/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1713/// operation for when the pattern matched at least one node with a chains. The 1714/// input vector contains a list of all of the chained nodes that we match. We 1715/// must determine if this is a valid thing to cover (i.e. matching it won't 1716/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1717/// be used as the input node chain for the generated nodes. 1718static SDValue 1719HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1720 SelectionDAG *CurDAG) { 1721 // Walk all of the chained nodes we've matched, recursively scanning down the 1722 // users of the chain result. This adds any TokenFactor nodes that are caught 1723 // in between chained nodes to the chained and interior nodes list. 1724 SmallVector<SDNode*, 3> InteriorChainedNodes; 1725 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1726 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1727 InteriorChainedNodes) == CR_InducesCycle) 1728 return SDValue(); // Would induce a cycle. 1729 } 1730 1731 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1732 // that we are interested in. Form our input TokenFactor node. 1733 SmallVector<SDValue, 3> InputChains; 1734 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1735 // Add the input chain of this node to the InputChains list (which will be 1736 // the operands of the generated TokenFactor) if it's not an interior node. 1737 SDNode *N = ChainNodesMatched[i]; 1738 if (N->getOpcode() != ISD::TokenFactor) { 1739 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1740 continue; 1741 1742 // Otherwise, add the input chain. 1743 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1744 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1745 InputChains.push_back(InChain); 1746 continue; 1747 } 1748 1749 // If we have a token factor, we want to add all inputs of the token factor 1750 // that are not part of the pattern we're matching. 1751 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1752 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1753 N->getOperand(op).getNode())) 1754 InputChains.push_back(N->getOperand(op)); 1755 } 1756 } 1757 1758 SDValue Res; 1759 if (InputChains.size() == 1) 1760 return InputChains[0]; 1761 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1762 MVT::Other, &InputChains[0], InputChains.size()); 1763} 1764 1765/// MorphNode - Handle morphing a node in place for the selector. 1766SDNode *SelectionDAGISel:: 1767MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1768 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1769 // It is possible we're using MorphNodeTo to replace a node with no 1770 // normal results with one that has a normal result (or we could be 1771 // adding a chain) and the input could have glue and chains as well. 1772 // In this case we need to shift the operands down. 1773 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1774 // than the old isel though. 1775 int OldGlueResultNo = -1, OldChainResultNo = -1; 1776 1777 unsigned NTMNumResults = Node->getNumValues(); 1778 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 1779 OldGlueResultNo = NTMNumResults-1; 1780 if (NTMNumResults != 1 && 1781 Node->getValueType(NTMNumResults-2) == MVT::Other) 1782 OldChainResultNo = NTMNumResults-2; 1783 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1784 OldChainResultNo = NTMNumResults-1; 1785 1786 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1787 // that this deletes operands of the old node that become dead. 1788 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1789 1790 // MorphNodeTo can operate in two ways: if an existing node with the 1791 // specified operands exists, it can just return it. Otherwise, it 1792 // updates the node in place to have the requested operands. 1793 if (Res == Node) { 1794 // If we updated the node in place, reset the node ID. To the isel, 1795 // this should be just like a newly allocated machine node. 1796 Res->setNodeId(-1); 1797 } 1798 1799 unsigned ResNumResults = Res->getNumValues(); 1800 // Move the glue if needed. 1801 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 1802 (unsigned)OldGlueResultNo != ResNumResults-1) 1803 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 1804 SDValue(Res, ResNumResults-1)); 1805 1806 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 1807 --ResNumResults; 1808 1809 // Move the chain reference if needed. 1810 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1811 (unsigned)OldChainResultNo != ResNumResults-1) 1812 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1813 SDValue(Res, ResNumResults-1)); 1814 1815 // Otherwise, no replacement happened because the node already exists. Replace 1816 // Uses of the old node with the new one. 1817 if (Res != Node) 1818 CurDAG->ReplaceAllUsesWith(Node, Res); 1819 1820 return Res; 1821} 1822 1823/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1824LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1825CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1826 SDValue N, 1827 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1828 // Accept if it is exactly the same as a previously recorded node. 1829 unsigned RecNo = MatcherTable[MatcherIndex++]; 1830 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1831 return N == RecordedNodes[RecNo].first; 1832} 1833 1834/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1835LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1836CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1837 SelectionDAGISel &SDISel) { 1838 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1839} 1840 1841/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1842LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1843CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1844 SelectionDAGISel &SDISel, SDNode *N) { 1845 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1846} 1847 1848LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1849CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1850 SDNode *N) { 1851 uint16_t Opc = MatcherTable[MatcherIndex++]; 1852 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1853 return N->getOpcode() == Opc; 1854} 1855 1856LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1857CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1858 SDValue N, const TargetLowering &TLI) { 1859 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1860 if (N.getValueType() == VT) return true; 1861 1862 // Handle the case when VT is iPTR. 1863 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1864} 1865 1866LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1867CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1868 SDValue N, const TargetLowering &TLI, 1869 unsigned ChildNo) { 1870 if (ChildNo >= N.getNumOperands()) 1871 return false; // Match fails if out of range child #. 1872 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1873} 1874 1875 1876LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1877CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1878 SDValue N) { 1879 return cast<CondCodeSDNode>(N)->get() == 1880 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1881} 1882 1883LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1884CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1885 SDValue N, const TargetLowering &TLI) { 1886 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1887 if (cast<VTSDNode>(N)->getVT() == VT) 1888 return true; 1889 1890 // Handle the case when VT is iPTR. 1891 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1892} 1893 1894LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1895CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1896 SDValue N) { 1897 int64_t Val = MatcherTable[MatcherIndex++]; 1898 if (Val & 128) 1899 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1900 1901 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1902 return C != 0 && C->getSExtValue() == Val; 1903} 1904 1905LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1906CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1907 SDValue N, SelectionDAGISel &SDISel) { 1908 int64_t Val = MatcherTable[MatcherIndex++]; 1909 if (Val & 128) 1910 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1911 1912 if (N->getOpcode() != ISD::AND) return false; 1913 1914 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1915 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1916} 1917 1918LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1919CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1920 SDValue N, SelectionDAGISel &SDISel) { 1921 int64_t Val = MatcherTable[MatcherIndex++]; 1922 if (Val & 128) 1923 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1924 1925 if (N->getOpcode() != ISD::OR) return false; 1926 1927 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1928 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1929} 1930 1931/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1932/// scope, evaluate the current node. If the current predicate is known to 1933/// fail, set Result=true and return anything. If the current predicate is 1934/// known to pass, set Result=false and return the MatcherIndex to continue 1935/// with. If the current predicate is unknown, set Result=false and return the 1936/// MatcherIndex to continue with. 1937static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1938 unsigned Index, SDValue N, 1939 bool &Result, SelectionDAGISel &SDISel, 1940 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1941 switch (Table[Index++]) { 1942 default: 1943 Result = false; 1944 return Index-1; // Could not evaluate this predicate. 1945 case SelectionDAGISel::OPC_CheckSame: 1946 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1947 return Index; 1948 case SelectionDAGISel::OPC_CheckPatternPredicate: 1949 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1950 return Index; 1951 case SelectionDAGISel::OPC_CheckPredicate: 1952 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1953 return Index; 1954 case SelectionDAGISel::OPC_CheckOpcode: 1955 Result = !::CheckOpcode(Table, Index, N.getNode()); 1956 return Index; 1957 case SelectionDAGISel::OPC_CheckType: 1958 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1959 return Index; 1960 case SelectionDAGISel::OPC_CheckChild0Type: 1961 case SelectionDAGISel::OPC_CheckChild1Type: 1962 case SelectionDAGISel::OPC_CheckChild2Type: 1963 case SelectionDAGISel::OPC_CheckChild3Type: 1964 case SelectionDAGISel::OPC_CheckChild4Type: 1965 case SelectionDAGISel::OPC_CheckChild5Type: 1966 case SelectionDAGISel::OPC_CheckChild6Type: 1967 case SelectionDAGISel::OPC_CheckChild7Type: 1968 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1969 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1970 return Index; 1971 case SelectionDAGISel::OPC_CheckCondCode: 1972 Result = !::CheckCondCode(Table, Index, N); 1973 return Index; 1974 case SelectionDAGISel::OPC_CheckValueType: 1975 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1976 return Index; 1977 case SelectionDAGISel::OPC_CheckInteger: 1978 Result = !::CheckInteger(Table, Index, N); 1979 return Index; 1980 case SelectionDAGISel::OPC_CheckAndImm: 1981 Result = !::CheckAndImm(Table, Index, N, SDISel); 1982 return Index; 1983 case SelectionDAGISel::OPC_CheckOrImm: 1984 Result = !::CheckOrImm(Table, Index, N, SDISel); 1985 return Index; 1986 } 1987} 1988 1989namespace { 1990 1991struct MatchScope { 1992 /// FailIndex - If this match fails, this is the index to continue with. 1993 unsigned FailIndex; 1994 1995 /// NodeStack - The node stack when the scope was formed. 1996 SmallVector<SDValue, 4> NodeStack; 1997 1998 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1999 unsigned NumRecordedNodes; 2000 2001 /// NumMatchedMemRefs - The number of matched memref entries. 2002 unsigned NumMatchedMemRefs; 2003 2004 /// InputChain/InputGlue - The current chain/glue 2005 SDValue InputChain, InputGlue; 2006 2007 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2008 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2009}; 2010 2011} 2012 2013SDNode *SelectionDAGISel:: 2014SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2015 unsigned TableSize) { 2016 // FIXME: Should these even be selected? Handle these cases in the caller? 2017 switch (NodeToMatch->getOpcode()) { 2018 default: 2019 break; 2020 case ISD::EntryToken: // These nodes remain the same. 2021 case ISD::BasicBlock: 2022 case ISD::Register: 2023 //case ISD::VALUETYPE: 2024 //case ISD::CONDCODE: 2025 case ISD::HANDLENODE: 2026 case ISD::MDNODE_SDNODE: 2027 case ISD::TargetConstant: 2028 case ISD::TargetConstantFP: 2029 case ISD::TargetConstantPool: 2030 case ISD::TargetFrameIndex: 2031 case ISD::TargetExternalSymbol: 2032 case ISD::TargetBlockAddress: 2033 case ISD::TargetJumpTable: 2034 case ISD::TargetGlobalTLSAddress: 2035 case ISD::TargetGlobalAddress: 2036 case ISD::TokenFactor: 2037 case ISD::CopyFromReg: 2038 case ISD::CopyToReg: 2039 case ISD::EH_LABEL: 2040 NodeToMatch->setNodeId(-1); // Mark selected. 2041 return 0; 2042 case ISD::AssertSext: 2043 case ISD::AssertZext: 2044 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2045 NodeToMatch->getOperand(0)); 2046 return 0; 2047 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2048 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2049 } 2050 2051 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2052 2053 // Set up the node stack with NodeToMatch as the only node on the stack. 2054 SmallVector<SDValue, 8> NodeStack; 2055 SDValue N = SDValue(NodeToMatch, 0); 2056 NodeStack.push_back(N); 2057 2058 // MatchScopes - Scopes used when matching, if a match failure happens, this 2059 // indicates where to continue checking. 2060 SmallVector<MatchScope, 8> MatchScopes; 2061 2062 // RecordedNodes - This is the set of nodes that have been recorded by the 2063 // state machine. The second value is the parent of the node, or null if the 2064 // root is recorded. 2065 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2066 2067 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2068 // pattern. 2069 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2070 2071 // These are the current input chain and glue for use when generating nodes. 2072 // Various Emit operations change these. For example, emitting a copytoreg 2073 // uses and updates these. 2074 SDValue InputChain, InputGlue; 2075 2076 // ChainNodesMatched - If a pattern matches nodes that have input/output 2077 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2078 // which ones they are. The result is captured into this list so that we can 2079 // update the chain results when the pattern is complete. 2080 SmallVector<SDNode*, 3> ChainNodesMatched; 2081 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2082 2083 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2084 NodeToMatch->dump(CurDAG); 2085 errs() << '\n'); 2086 2087 // Determine where to start the interpreter. Normally we start at opcode #0, 2088 // but if the state machine starts with an OPC_SwitchOpcode, then we 2089 // accelerate the first lookup (which is guaranteed to be hot) with the 2090 // OpcodeOffset table. 2091 unsigned MatcherIndex = 0; 2092 2093 if (!OpcodeOffset.empty()) { 2094 // Already computed the OpcodeOffset table, just index into it. 2095 if (N.getOpcode() < OpcodeOffset.size()) 2096 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2097 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2098 2099 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2100 // Otherwise, the table isn't computed, but the state machine does start 2101 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2102 // is the first time we're selecting an instruction. 2103 unsigned Idx = 1; 2104 while (1) { 2105 // Get the size of this case. 2106 unsigned CaseSize = MatcherTable[Idx++]; 2107 if (CaseSize & 128) 2108 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2109 if (CaseSize == 0) break; 2110 2111 // Get the opcode, add the index to the table. 2112 uint16_t Opc = MatcherTable[Idx++]; 2113 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2114 if (Opc >= OpcodeOffset.size()) 2115 OpcodeOffset.resize((Opc+1)*2); 2116 OpcodeOffset[Opc] = Idx; 2117 Idx += CaseSize; 2118 } 2119 2120 // Okay, do the lookup for the first opcode. 2121 if (N.getOpcode() < OpcodeOffset.size()) 2122 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2123 } 2124 2125 while (1) { 2126 assert(MatcherIndex < TableSize && "Invalid index"); 2127#ifndef NDEBUG 2128 unsigned CurrentOpcodeIndex = MatcherIndex; 2129#endif 2130 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2131 switch (Opcode) { 2132 case OPC_Scope: { 2133 // Okay, the semantics of this operation are that we should push a scope 2134 // then evaluate the first child. However, pushing a scope only to have 2135 // the first check fail (which then pops it) is inefficient. If we can 2136 // determine immediately that the first check (or first several) will 2137 // immediately fail, don't even bother pushing a scope for them. 2138 unsigned FailIndex; 2139 2140 while (1) { 2141 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2142 if (NumToSkip & 128) 2143 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2144 // Found the end of the scope with no match. 2145 if (NumToSkip == 0) { 2146 FailIndex = 0; 2147 break; 2148 } 2149 2150 FailIndex = MatcherIndex+NumToSkip; 2151 2152 unsigned MatcherIndexOfPredicate = MatcherIndex; 2153 (void)MatcherIndexOfPredicate; // silence warning. 2154 2155 // If we can't evaluate this predicate without pushing a scope (e.g. if 2156 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2157 // push the scope and evaluate the full predicate chain. 2158 bool Result; 2159 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2160 Result, *this, RecordedNodes); 2161 if (!Result) 2162 break; 2163 2164 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2165 << "index " << MatcherIndexOfPredicate 2166 << ", continuing at " << FailIndex << "\n"); 2167 ++NumDAGIselRetries; 2168 2169 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2170 // move to the next case. 2171 MatcherIndex = FailIndex; 2172 } 2173 2174 // If the whole scope failed to match, bail. 2175 if (FailIndex == 0) break; 2176 2177 // Push a MatchScope which indicates where to go if the first child fails 2178 // to match. 2179 MatchScope NewEntry; 2180 NewEntry.FailIndex = FailIndex; 2181 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2182 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2183 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2184 NewEntry.InputChain = InputChain; 2185 NewEntry.InputGlue = InputGlue; 2186 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2187 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2188 MatchScopes.push_back(NewEntry); 2189 continue; 2190 } 2191 case OPC_RecordNode: { 2192 // Remember this node, it may end up being an operand in the pattern. 2193 SDNode *Parent = 0; 2194 if (NodeStack.size() > 1) 2195 Parent = NodeStack[NodeStack.size()-2].getNode(); 2196 RecordedNodes.push_back(std::make_pair(N, Parent)); 2197 continue; 2198 } 2199 2200 case OPC_RecordChild0: case OPC_RecordChild1: 2201 case OPC_RecordChild2: case OPC_RecordChild3: 2202 case OPC_RecordChild4: case OPC_RecordChild5: 2203 case OPC_RecordChild6: case OPC_RecordChild7: { 2204 unsigned ChildNo = Opcode-OPC_RecordChild0; 2205 if (ChildNo >= N.getNumOperands()) 2206 break; // Match fails if out of range child #. 2207 2208 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2209 N.getNode())); 2210 continue; 2211 } 2212 case OPC_RecordMemRef: 2213 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2214 continue; 2215 2216 case OPC_CaptureGlueInput: 2217 // If the current node has an input glue, capture it in InputGlue. 2218 if (N->getNumOperands() != 0 && 2219 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2220 InputGlue = N->getOperand(N->getNumOperands()-1); 2221 continue; 2222 2223 case OPC_MoveChild: { 2224 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2225 if (ChildNo >= N.getNumOperands()) 2226 break; // Match fails if out of range child #. 2227 N = N.getOperand(ChildNo); 2228 NodeStack.push_back(N); 2229 continue; 2230 } 2231 2232 case OPC_MoveParent: 2233 // Pop the current node off the NodeStack. 2234 NodeStack.pop_back(); 2235 assert(!NodeStack.empty() && "Node stack imbalance!"); 2236 N = NodeStack.back(); 2237 continue; 2238 2239 case OPC_CheckSame: 2240 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2241 continue; 2242 case OPC_CheckPatternPredicate: 2243 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2244 continue; 2245 case OPC_CheckPredicate: 2246 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2247 N.getNode())) 2248 break; 2249 continue; 2250 case OPC_CheckComplexPat: { 2251 unsigned CPNum = MatcherTable[MatcherIndex++]; 2252 unsigned RecNo = MatcherTable[MatcherIndex++]; 2253 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2254 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2255 RecordedNodes[RecNo].first, CPNum, 2256 RecordedNodes)) 2257 break; 2258 continue; 2259 } 2260 case OPC_CheckOpcode: 2261 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2262 continue; 2263 2264 case OPC_CheckType: 2265 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2266 continue; 2267 2268 case OPC_SwitchOpcode: { 2269 unsigned CurNodeOpcode = N.getOpcode(); 2270 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2271 unsigned CaseSize; 2272 while (1) { 2273 // Get the size of this case. 2274 CaseSize = MatcherTable[MatcherIndex++]; 2275 if (CaseSize & 128) 2276 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2277 if (CaseSize == 0) break; 2278 2279 uint16_t Opc = MatcherTable[MatcherIndex++]; 2280 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2281 2282 // If the opcode matches, then we will execute this case. 2283 if (CurNodeOpcode == Opc) 2284 break; 2285 2286 // Otherwise, skip over this case. 2287 MatcherIndex += CaseSize; 2288 } 2289 2290 // If no cases matched, bail out. 2291 if (CaseSize == 0) break; 2292 2293 // Otherwise, execute the case we found. 2294 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2295 << " to " << MatcherIndex << "\n"); 2296 continue; 2297 } 2298 2299 case OPC_SwitchType: { 2300 MVT CurNodeVT = N.getValueType().getSimpleVT(); 2301 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2302 unsigned CaseSize; 2303 while (1) { 2304 // Get the size of this case. 2305 CaseSize = MatcherTable[MatcherIndex++]; 2306 if (CaseSize & 128) 2307 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2308 if (CaseSize == 0) break; 2309 2310 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2311 if (CaseVT == MVT::iPTR) 2312 CaseVT = TLI.getPointerTy(); 2313 2314 // If the VT matches, then we will execute this case. 2315 if (CurNodeVT == CaseVT) 2316 break; 2317 2318 // Otherwise, skip over this case. 2319 MatcherIndex += CaseSize; 2320 } 2321 2322 // If no cases matched, bail out. 2323 if (CaseSize == 0) break; 2324 2325 // Otherwise, execute the case we found. 2326 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2327 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2328 continue; 2329 } 2330 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2331 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2332 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2333 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2334 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2335 Opcode-OPC_CheckChild0Type)) 2336 break; 2337 continue; 2338 case OPC_CheckCondCode: 2339 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2340 continue; 2341 case OPC_CheckValueType: 2342 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2343 continue; 2344 case OPC_CheckInteger: 2345 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2346 continue; 2347 case OPC_CheckAndImm: 2348 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2349 continue; 2350 case OPC_CheckOrImm: 2351 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2352 continue; 2353 2354 case OPC_CheckFoldableChainNode: { 2355 assert(NodeStack.size() != 1 && "No parent node"); 2356 // Verify that all intermediate nodes between the root and this one have 2357 // a single use. 2358 bool HasMultipleUses = false; 2359 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2360 if (!NodeStack[i].hasOneUse()) { 2361 HasMultipleUses = true; 2362 break; 2363 } 2364 if (HasMultipleUses) break; 2365 2366 // Check to see that the target thinks this is profitable to fold and that 2367 // we can fold it without inducing cycles in the graph. 2368 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2369 NodeToMatch) || 2370 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2371 NodeToMatch, OptLevel, 2372 true/*We validate our own chains*/)) 2373 break; 2374 2375 continue; 2376 } 2377 case OPC_EmitInteger: { 2378 MVT::SimpleValueType VT = 2379 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2380 int64_t Val = MatcherTable[MatcherIndex++]; 2381 if (Val & 128) 2382 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2383 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2384 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2385 continue; 2386 } 2387 case OPC_EmitRegister: { 2388 MVT::SimpleValueType VT = 2389 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2390 unsigned RegNo = MatcherTable[MatcherIndex++]; 2391 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2392 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2393 continue; 2394 } 2395 case OPC_EmitRegister2: { 2396 // For targets w/ more than 256 register names, the register enum 2397 // values are stored in two bytes in the matcher table (just like 2398 // opcodes). 2399 MVT::SimpleValueType VT = 2400 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2401 unsigned RegNo = MatcherTable[MatcherIndex++]; 2402 RegNo |= MatcherTable[MatcherIndex++] << 8; 2403 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2404 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2405 continue; 2406 } 2407 2408 case OPC_EmitConvertToTarget: { 2409 // Convert from IMM/FPIMM to target version. 2410 unsigned RecNo = MatcherTable[MatcherIndex++]; 2411 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2412 SDValue Imm = RecordedNodes[RecNo].first; 2413 2414 if (Imm->getOpcode() == ISD::Constant) { 2415 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2416 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2417 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2418 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2419 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2420 } 2421 2422 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2423 continue; 2424 } 2425 2426 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2427 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2428 // These are space-optimized forms of OPC_EmitMergeInputChains. 2429 assert(InputChain.getNode() == 0 && 2430 "EmitMergeInputChains should be the first chain producing node"); 2431 assert(ChainNodesMatched.empty() && 2432 "Should only have one EmitMergeInputChains per match"); 2433 2434 // Read all of the chained nodes. 2435 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2436 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2437 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2438 2439 // FIXME: What if other value results of the node have uses not matched 2440 // by this pattern? 2441 if (ChainNodesMatched.back() != NodeToMatch && 2442 !RecordedNodes[RecNo].first.hasOneUse()) { 2443 ChainNodesMatched.clear(); 2444 break; 2445 } 2446 2447 // Merge the input chains if they are not intra-pattern references. 2448 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2449 2450 if (InputChain.getNode() == 0) 2451 break; // Failed to merge. 2452 continue; 2453 } 2454 2455 case OPC_EmitMergeInputChains: { 2456 assert(InputChain.getNode() == 0 && 2457 "EmitMergeInputChains should be the first chain producing node"); 2458 // This node gets a list of nodes we matched in the input that have 2459 // chains. We want to token factor all of the input chains to these nodes 2460 // together. However, if any of the input chains is actually one of the 2461 // nodes matched in this pattern, then we have an intra-match reference. 2462 // Ignore these because the newly token factored chain should not refer to 2463 // the old nodes. 2464 unsigned NumChains = MatcherTable[MatcherIndex++]; 2465 assert(NumChains != 0 && "Can't TF zero chains"); 2466 2467 assert(ChainNodesMatched.empty() && 2468 "Should only have one EmitMergeInputChains per match"); 2469 2470 // Read all of the chained nodes. 2471 for (unsigned i = 0; i != NumChains; ++i) { 2472 unsigned RecNo = MatcherTable[MatcherIndex++]; 2473 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2474 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2475 2476 // FIXME: What if other value results of the node have uses not matched 2477 // by this pattern? 2478 if (ChainNodesMatched.back() != NodeToMatch && 2479 !RecordedNodes[RecNo].first.hasOneUse()) { 2480 ChainNodesMatched.clear(); 2481 break; 2482 } 2483 } 2484 2485 // If the inner loop broke out, the match fails. 2486 if (ChainNodesMatched.empty()) 2487 break; 2488 2489 // Merge the input chains if they are not intra-pattern references. 2490 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2491 2492 if (InputChain.getNode() == 0) 2493 break; // Failed to merge. 2494 2495 continue; 2496 } 2497 2498 case OPC_EmitCopyToReg: { 2499 unsigned RecNo = MatcherTable[MatcherIndex++]; 2500 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2501 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2502 2503 if (InputChain.getNode() == 0) 2504 InputChain = CurDAG->getEntryNode(); 2505 2506 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2507 DestPhysReg, RecordedNodes[RecNo].first, 2508 InputGlue); 2509 2510 InputGlue = InputChain.getValue(1); 2511 continue; 2512 } 2513 2514 case OPC_EmitNodeXForm: { 2515 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2516 unsigned RecNo = MatcherTable[MatcherIndex++]; 2517 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2518 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2519 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2520 continue; 2521 } 2522 2523 case OPC_EmitNode: 2524 case OPC_MorphNodeTo: { 2525 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2526 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2527 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2528 // Get the result VT list. 2529 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2530 SmallVector<EVT, 4> VTs; 2531 for (unsigned i = 0; i != NumVTs; ++i) { 2532 MVT::SimpleValueType VT = 2533 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2534 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2535 VTs.push_back(VT); 2536 } 2537 2538 if (EmitNodeInfo & OPFL_Chain) 2539 VTs.push_back(MVT::Other); 2540 if (EmitNodeInfo & OPFL_GlueOutput) 2541 VTs.push_back(MVT::Glue); 2542 2543 // This is hot code, so optimize the two most common cases of 1 and 2 2544 // results. 2545 SDVTList VTList; 2546 if (VTs.size() == 1) 2547 VTList = CurDAG->getVTList(VTs[0]); 2548 else if (VTs.size() == 2) 2549 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2550 else 2551 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2552 2553 // Get the operand list. 2554 unsigned NumOps = MatcherTable[MatcherIndex++]; 2555 SmallVector<SDValue, 8> Ops; 2556 for (unsigned i = 0; i != NumOps; ++i) { 2557 unsigned RecNo = MatcherTable[MatcherIndex++]; 2558 if (RecNo & 128) 2559 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2560 2561 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2562 Ops.push_back(RecordedNodes[RecNo].first); 2563 } 2564 2565 // If there are variadic operands to add, handle them now. 2566 if (EmitNodeInfo & OPFL_VariadicInfo) { 2567 // Determine the start index to copy from. 2568 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2569 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2570 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2571 "Invalid variadic node"); 2572 // Copy all of the variadic operands, not including a potential glue 2573 // input. 2574 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2575 i != e; ++i) { 2576 SDValue V = NodeToMatch->getOperand(i); 2577 if (V.getValueType() == MVT::Glue) break; 2578 Ops.push_back(V); 2579 } 2580 } 2581 2582 // If this has chain/glue inputs, add them. 2583 if (EmitNodeInfo & OPFL_Chain) 2584 Ops.push_back(InputChain); 2585 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2586 Ops.push_back(InputGlue); 2587 2588 // Create the node. 2589 SDNode *Res = 0; 2590 if (Opcode != OPC_MorphNodeTo) { 2591 // If this is a normal EmitNode command, just create the new node and 2592 // add the results to the RecordedNodes list. 2593 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2594 VTList, Ops.data(), Ops.size()); 2595 2596 // Add all the non-glue/non-chain results to the RecordedNodes list. 2597 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2598 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2599 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2600 (SDNode*) 0)); 2601 } 2602 2603 } else { 2604 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2605 EmitNodeInfo); 2606 } 2607 2608 // If the node had chain/glue results, update our notion of the current 2609 // chain and glue. 2610 if (EmitNodeInfo & OPFL_GlueOutput) { 2611 InputGlue = SDValue(Res, VTs.size()-1); 2612 if (EmitNodeInfo & OPFL_Chain) 2613 InputChain = SDValue(Res, VTs.size()-2); 2614 } else if (EmitNodeInfo & OPFL_Chain) 2615 InputChain = SDValue(Res, VTs.size()-1); 2616 2617 // If the OPFL_MemRefs glue is set on this node, slap all of the 2618 // accumulated memrefs onto it. 2619 // 2620 // FIXME: This is vastly incorrect for patterns with multiple outputs 2621 // instructions that access memory and for ComplexPatterns that match 2622 // loads. 2623 if (EmitNodeInfo & OPFL_MemRefs) { 2624 MachineSDNode::mmo_iterator MemRefs = 2625 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2626 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2627 cast<MachineSDNode>(Res) 2628 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2629 } 2630 2631 DEBUG(errs() << " " 2632 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2633 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2634 2635 // If this was a MorphNodeTo then we're completely done! 2636 if (Opcode == OPC_MorphNodeTo) { 2637 // Update chain and glue uses. 2638 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2639 InputGlue, GlueResultNodesMatched, true); 2640 return Res; 2641 } 2642 2643 continue; 2644 } 2645 2646 case OPC_MarkGlueResults: { 2647 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2648 2649 // Read and remember all the glue-result nodes. 2650 for (unsigned i = 0; i != NumNodes; ++i) { 2651 unsigned RecNo = MatcherTable[MatcherIndex++]; 2652 if (RecNo & 128) 2653 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2654 2655 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2656 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2657 } 2658 continue; 2659 } 2660 2661 case OPC_CompleteMatch: { 2662 // The match has been completed, and any new nodes (if any) have been 2663 // created. Patch up references to the matched dag to use the newly 2664 // created nodes. 2665 unsigned NumResults = MatcherTable[MatcherIndex++]; 2666 2667 for (unsigned i = 0; i != NumResults; ++i) { 2668 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2669 if (ResSlot & 128) 2670 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2671 2672 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2673 SDValue Res = RecordedNodes[ResSlot].first; 2674 2675 assert(i < NodeToMatch->getNumValues() && 2676 NodeToMatch->getValueType(i) != MVT::Other && 2677 NodeToMatch->getValueType(i) != MVT::Glue && 2678 "Invalid number of results to complete!"); 2679 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2680 NodeToMatch->getValueType(i) == MVT::iPTR || 2681 Res.getValueType() == MVT::iPTR || 2682 NodeToMatch->getValueType(i).getSizeInBits() == 2683 Res.getValueType().getSizeInBits()) && 2684 "invalid replacement"); 2685 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2686 } 2687 2688 // If the root node defines glue, add it to the glue nodes to update list. 2689 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2690 GlueResultNodesMatched.push_back(NodeToMatch); 2691 2692 // Update chain and glue uses. 2693 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2694 InputGlue, GlueResultNodesMatched, false); 2695 2696 assert(NodeToMatch->use_empty() && 2697 "Didn't replace all uses of the node?"); 2698 2699 // FIXME: We just return here, which interacts correctly with SelectRoot 2700 // above. We should fix this to not return an SDNode* anymore. 2701 return 0; 2702 } 2703 } 2704 2705 // If the code reached this point, then the match failed. See if there is 2706 // another child to try in the current 'Scope', otherwise pop it until we 2707 // find a case to check. 2708 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2709 ++NumDAGIselRetries; 2710 while (1) { 2711 if (MatchScopes.empty()) { 2712 CannotYetSelect(NodeToMatch); 2713 return 0; 2714 } 2715 2716 // Restore the interpreter state back to the point where the scope was 2717 // formed. 2718 MatchScope &LastScope = MatchScopes.back(); 2719 RecordedNodes.resize(LastScope.NumRecordedNodes); 2720 NodeStack.clear(); 2721 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2722 N = NodeStack.back(); 2723 2724 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2725 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2726 MatcherIndex = LastScope.FailIndex; 2727 2728 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2729 2730 InputChain = LastScope.InputChain; 2731 InputGlue = LastScope.InputGlue; 2732 if (!LastScope.HasChainNodesMatched) 2733 ChainNodesMatched.clear(); 2734 if (!LastScope.HasGlueResultNodesMatched) 2735 GlueResultNodesMatched.clear(); 2736 2737 // Check to see what the offset is at the new MatcherIndex. If it is zero 2738 // we have reached the end of this scope, otherwise we have another child 2739 // in the current scope to try. 2740 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2741 if (NumToSkip & 128) 2742 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2743 2744 // If we have another child in this scope to match, update FailIndex and 2745 // try it. 2746 if (NumToSkip != 0) { 2747 LastScope.FailIndex = MatcherIndex+NumToSkip; 2748 break; 2749 } 2750 2751 // End of this scope, pop it and try the next child in the containing 2752 // scope. 2753 MatchScopes.pop_back(); 2754 } 2755 } 2756} 2757 2758 2759 2760void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2761 std::string msg; 2762 raw_string_ostream Msg(msg); 2763 Msg << "Cannot select: "; 2764 2765 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2766 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2767 N->getOpcode() != ISD::INTRINSIC_VOID) { 2768 N->printrFull(Msg, CurDAG); 2769 } else { 2770 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2771 unsigned iid = 2772 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2773 if (iid < Intrinsic::num_intrinsics) 2774 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2775 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2776 Msg << "target intrinsic %" << TII->getName(iid); 2777 else 2778 Msg << "unknown intrinsic #" << iid; 2779 } 2780 report_fatal_error(Msg.str()); 2781} 2782 2783char SelectionDAGISel::ID = 0; 2784