SelectionDAGISel.cpp revision 2f42901dff5d0b4a9bb571a2f57157c296584557
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/MachineModuleInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/CodeGen/SSARegMap.h" 37#include "llvm/Target/MRegisterInfo.h" 38#include "llvm/Target/TargetData.h" 39#include "llvm/Target/TargetFrameInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Compiler.h" 47#include <algorithm> 48using namespace llvm; 49 50#ifndef NDEBUG 51static cl::opt<bool> 52ViewISelDAGs("view-isel-dags", cl::Hidden, 53 cl::desc("Pop up a window to show isel dags as they are selected")); 54static cl::opt<bool> 55ViewSchedDAGs("view-sched-dags", cl::Hidden, 56 cl::desc("Pop up a window to show sched dags as they are processed")); 57static cl::opt<bool> 58ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 59 cl::desc("Pop up a window to show SUnit dags after they are processed")); 60#else 61static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0; 62#endif 63 64//===---------------------------------------------------------------------===// 65/// 66/// RegisterScheduler class - Track the registration of instruction schedulers. 67/// 68//===---------------------------------------------------------------------===// 69MachinePassRegistry RegisterScheduler::Registry; 70 71//===---------------------------------------------------------------------===// 72/// 73/// ISHeuristic command line option for instruction schedulers. 74/// 75//===---------------------------------------------------------------------===// 76namespace { 77 cl::opt<RegisterScheduler::FunctionPassCtor, false, 78 RegisterPassParser<RegisterScheduler> > 79 ISHeuristic("pre-RA-sched", 80 cl::init(&createDefaultScheduler), 81 cl::desc("Instruction schedulers available (before register allocation):")); 82 83 static RegisterScheduler 84 defaultListDAGScheduler("default", " Best scheduler for the target", 85 createDefaultScheduler); 86} // namespace 87 88namespace { struct AsmOperandInfo; } 89 90namespace { 91 /// RegsForValue - This struct represents the physical registers that a 92 /// particular value is assigned and the type information about the value. 93 /// This is needed because values can be promoted into larger registers and 94 /// expanded into multiple smaller registers than the value. 95 struct VISIBILITY_HIDDEN RegsForValue { 96 /// Regs - This list holds the register (for legal and promoted values) 97 /// or register set (for expanded values) that the value should be assigned 98 /// to. 99 std::vector<unsigned> Regs; 100 101 /// RegVT - The value type of each register. 102 /// 103 MVT::ValueType RegVT; 104 105 /// ValueVT - The value type of the LLVM value, which may be promoted from 106 /// RegVT or made from merging the two expanded parts. 107 MVT::ValueType ValueVT; 108 109 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 110 111 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 112 : RegVT(regvt), ValueVT(valuevt) { 113 Regs.push_back(Reg); 114 } 115 RegsForValue(const std::vector<unsigned> ®s, 116 MVT::ValueType regvt, MVT::ValueType valuevt) 117 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 118 } 119 120 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 121 /// this value and returns the result as a ValueVT value. This uses 122 /// Chain/Flag as the input and updates them for the output Chain/Flag. 123 /// If the Flag pointer is NULL, no flag is used. 124 SDOperand getCopyFromRegs(SelectionDAG &DAG, 125 SDOperand &Chain, SDOperand *Flag) const; 126 127 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 128 /// specified value into the registers specified by this object. This uses 129 /// Chain/Flag as the input and updates them for the output Chain/Flag. 130 /// If the Flag pointer is NULL, no flag is used. 131 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 132 SDOperand &Chain, SDOperand *Flag) const; 133 134 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 135 /// operand list. This adds the code marker and includes the number of 136 /// values added into it. 137 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 138 std::vector<SDOperand> &Ops) const; 139 }; 140} 141 142namespace llvm { 143 //===--------------------------------------------------------------------===// 144 /// createDefaultScheduler - This creates an instruction scheduler appropriate 145 /// for the target. 146 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 147 SelectionDAG *DAG, 148 MachineBasicBlock *BB) { 149 TargetLowering &TLI = IS->getTargetLowering(); 150 151 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 152 return createTDListDAGScheduler(IS, DAG, BB); 153 } else { 154 assert(TLI.getSchedulingPreference() == 155 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 156 return createBURRListDAGScheduler(IS, DAG, BB); 157 } 158 } 159 160 161 //===--------------------------------------------------------------------===// 162 /// FunctionLoweringInfo - This contains information that is global to a 163 /// function that is used when lowering a region of the function. 164 class FunctionLoweringInfo { 165 public: 166 TargetLowering &TLI; 167 Function &Fn; 168 MachineFunction &MF; 169 SSARegMap *RegMap; 170 171 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 172 173 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 174 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 175 176 /// ValueMap - Since we emit code for the function a basic block at a time, 177 /// we must remember which virtual registers hold the values for 178 /// cross-basic-block values. 179 DenseMap<const Value*, unsigned> ValueMap; 180 181 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 182 /// the entry block. This allows the allocas to be efficiently referenced 183 /// anywhere in the function. 184 std::map<const AllocaInst*, int> StaticAllocaMap; 185 186#ifndef NDEBUG 187 SmallSet<Instruction*, 8> CatchInfoLost; 188 SmallSet<Instruction*, 8> CatchInfoFound; 189#endif 190 191 unsigned MakeReg(MVT::ValueType VT) { 192 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 193 } 194 195 /// isExportedInst - Return true if the specified value is an instruction 196 /// exported from its block. 197 bool isExportedInst(const Value *V) { 198 return ValueMap.count(V); 199 } 200 201 unsigned CreateRegForValue(const Value *V); 202 203 unsigned InitializeRegForValue(const Value *V) { 204 unsigned &R = ValueMap[V]; 205 assert(R == 0 && "Already initialized this value register!"); 206 return R = CreateRegForValue(V); 207 } 208 }; 209} 210 211/// isSelector - Return true if this instruction is a call to the 212/// eh.selector intrinsic. 213static bool isSelector(Instruction *I) { 214 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 215 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 || 216 II->getIntrinsicID() == Intrinsic::eh_selector_i64); 217 return false; 218} 219 220/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 221/// PHI nodes or outside of the basic block that defines it, or used by a 222/// switch instruction, which may expand to multiple basic blocks. 223static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 224 if (isa<PHINode>(I)) return true; 225 BasicBlock *BB = I->getParent(); 226 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 227 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 228 // FIXME: Remove switchinst special case. 229 isa<SwitchInst>(*UI)) 230 return true; 231 return false; 232} 233 234/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 235/// entry block, return true. This includes arguments used by switches, since 236/// the switch may expand into multiple basic blocks. 237static bool isOnlyUsedInEntryBlock(Argument *A) { 238 BasicBlock *Entry = A->getParent()->begin(); 239 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 240 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 241 return false; // Use not in entry block. 242 return true; 243} 244 245FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 246 Function &fn, MachineFunction &mf) 247 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 248 249 // Create a vreg for each argument register that is not dead and is used 250 // outside of the entry block for the function. 251 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 252 AI != E; ++AI) 253 if (!isOnlyUsedInEntryBlock(AI)) 254 InitializeRegForValue(AI); 255 256 // Initialize the mapping of values to registers. This is only set up for 257 // instruction values that are used outside of the block that defines 258 // them. 259 Function::iterator BB = Fn.begin(), EB = Fn.end(); 260 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 261 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 262 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 263 const Type *Ty = AI->getAllocatedType(); 264 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 265 unsigned Align = 266 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 267 AI->getAlignment()); 268 269 TySize *= CUI->getZExtValue(); // Get total allocated size. 270 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 271 StaticAllocaMap[AI] = 272 MF.getFrameInfo()->CreateStackObject(TySize, Align); 273 } 274 275 for (; BB != EB; ++BB) 276 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 277 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 278 if (!isa<AllocaInst>(I) || 279 !StaticAllocaMap.count(cast<AllocaInst>(I))) 280 InitializeRegForValue(I); 281 282 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 283 // also creates the initial PHI MachineInstrs, though none of the input 284 // operands are populated. 285 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 286 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 287 MBBMap[BB] = MBB; 288 MF.getBasicBlockList().push_back(MBB); 289 290 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 291 // appropriate. 292 PHINode *PN; 293 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 294 if (PN->use_empty()) continue; 295 296 MVT::ValueType VT = TLI.getValueType(PN->getType()); 297 unsigned NumRegisters = TLI.getNumRegisters(VT); 298 unsigned PHIReg = ValueMap[PN]; 299 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 300 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 301 for (unsigned i = 0; i != NumRegisters; ++i) 302 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 303 } 304 } 305} 306 307/// CreateRegForValue - Allocate the appropriate number of virtual registers of 308/// the correctly promoted or expanded types. Assign these registers 309/// consecutive vreg numbers and return the first assigned number. 310unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 311 MVT::ValueType VT = TLI.getValueType(V->getType()); 312 313 unsigned NumRegisters = TLI.getNumRegisters(VT); 314 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 315 316 unsigned R = MakeReg(RegisterVT); 317 for (unsigned i = 1; i != NumRegisters; ++i) 318 MakeReg(RegisterVT); 319 320 return R; 321} 322 323//===----------------------------------------------------------------------===// 324/// SelectionDAGLowering - This is the common target-independent lowering 325/// implementation that is parameterized by a TargetLowering object. 326/// Also, targets can overload any lowering method. 327/// 328namespace llvm { 329class SelectionDAGLowering { 330 MachineBasicBlock *CurMBB; 331 332 DenseMap<const Value*, SDOperand> NodeMap; 333 334 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 335 /// them up and then emit token factor nodes when possible. This allows us to 336 /// get simple disambiguation between loads without worrying about alias 337 /// analysis. 338 std::vector<SDOperand> PendingLoads; 339 340 /// Case - A struct to record the Value for a switch case, and the 341 /// case's target basic block. 342 struct Case { 343 Constant* Low; 344 Constant* High; 345 MachineBasicBlock* BB; 346 347 Case() : Low(0), High(0), BB(0) { } 348 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 349 Low(low), High(high), BB(bb) { } 350 uint64_t size() const { 351 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 352 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 353 return (rHigh - rLow + 1ULL); 354 } 355 }; 356 357 struct CaseBits { 358 uint64_t Mask; 359 MachineBasicBlock* BB; 360 unsigned Bits; 361 362 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 363 Mask(mask), BB(bb), Bits(bits) { } 364 }; 365 366 typedef std::vector<Case> CaseVector; 367 typedef std::vector<CaseBits> CaseBitsVector; 368 typedef CaseVector::iterator CaseItr; 369 typedef std::pair<CaseItr, CaseItr> CaseRange; 370 371 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 372 /// of conditional branches. 373 struct CaseRec { 374 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 375 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 376 377 /// CaseBB - The MBB in which to emit the compare and branch 378 MachineBasicBlock *CaseBB; 379 /// LT, GE - If nonzero, we know the current case value must be less-than or 380 /// greater-than-or-equal-to these Constants. 381 Constant *LT; 382 Constant *GE; 383 /// Range - A pair of iterators representing the range of case values to be 384 /// processed at this point in the binary search tree. 385 CaseRange Range; 386 }; 387 388 typedef std::vector<CaseRec> CaseRecVector; 389 390 /// The comparison function for sorting the switch case values in the vector. 391 /// WARNING: Case ranges should be disjoint! 392 struct CaseCmp { 393 bool operator () (const Case& C1, const Case& C2) { 394 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 395 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 396 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 397 return CI1->getValue().slt(CI2->getValue()); 398 } 399 }; 400 401 struct CaseBitsCmp { 402 bool operator () (const CaseBits& C1, const CaseBits& C2) { 403 return C1.Bits > C2.Bits; 404 } 405 }; 406 407 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 408 409public: 410 // TLI - This is information that describes the available target features we 411 // need for lowering. This indicates when operations are unavailable, 412 // implemented with a libcall, etc. 413 TargetLowering &TLI; 414 SelectionDAG &DAG; 415 const TargetData *TD; 416 AliasAnalysis &AA; 417 418 /// SwitchCases - Vector of CaseBlock structures used to communicate 419 /// SwitchInst code generation information. 420 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 421 /// JTCases - Vector of JumpTable structures used to communicate 422 /// SwitchInst code generation information. 423 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 424 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 425 426 /// FuncInfo - Information about the function as a whole. 427 /// 428 FunctionLoweringInfo &FuncInfo; 429 430 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 431 AliasAnalysis &aa, 432 FunctionLoweringInfo &funcinfo) 433 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa), 434 FuncInfo(funcinfo) { 435 } 436 437 /// getRoot - Return the current virtual root of the Selection DAG. 438 /// 439 SDOperand getRoot() { 440 if (PendingLoads.empty()) 441 return DAG.getRoot(); 442 443 if (PendingLoads.size() == 1) { 444 SDOperand Root = PendingLoads[0]; 445 DAG.setRoot(Root); 446 PendingLoads.clear(); 447 return Root; 448 } 449 450 // Otherwise, we have to make a token factor node. 451 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 452 &PendingLoads[0], PendingLoads.size()); 453 PendingLoads.clear(); 454 DAG.setRoot(Root); 455 return Root; 456 } 457 458 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 459 460 void visit(Instruction &I) { visit(I.getOpcode(), I); } 461 462 void visit(unsigned Opcode, User &I) { 463 // Note: this doesn't use InstVisitor, because it has to work with 464 // ConstantExpr's in addition to instructions. 465 switch (Opcode) { 466 default: assert(0 && "Unknown instruction type encountered!"); 467 abort(); 468 // Build the switch statement using the Instruction.def file. 469#define HANDLE_INST(NUM, OPCODE, CLASS) \ 470 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 471#include "llvm/Instruction.def" 472 } 473 } 474 475 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 476 477 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 478 const Value *SV, SDOperand Root, 479 bool isVolatile, unsigned Alignment); 480 481 SDOperand getIntPtrConstant(uint64_t Val) { 482 return DAG.getConstant(Val, TLI.getPointerTy()); 483 } 484 485 SDOperand getValue(const Value *V); 486 487 void setValue(const Value *V, SDOperand NewN) { 488 SDOperand &N = NodeMap[V]; 489 assert(N.Val == 0 && "Already set a value for this node!"); 490 N = NewN; 491 } 492 493 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 494 std::set<unsigned> &OutputRegs, 495 std::set<unsigned> &InputRegs); 496 497 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 498 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 499 unsigned Opc); 500 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 501 void ExportFromCurrentBlock(Value *V); 502 void LowerCallTo(Instruction &I, 503 const Type *CalledValueTy, unsigned CallingConv, 504 bool IsTailCall, SDOperand Callee, unsigned OpIdx, 505 MachineBasicBlock *LandingPad = NULL); 506 507 // Terminator instructions. 508 void visitRet(ReturnInst &I); 509 void visitBr(BranchInst &I); 510 void visitSwitch(SwitchInst &I); 511 void visitUnreachable(UnreachableInst &I) { /* noop */ } 512 513 // Helpers for visitSwitch 514 bool handleSmallSwitchRange(CaseRec& CR, 515 CaseRecVector& WorkList, 516 Value* SV, 517 MachineBasicBlock* Default); 518 bool handleJTSwitchCase(CaseRec& CR, 519 CaseRecVector& WorkList, 520 Value* SV, 521 MachineBasicBlock* Default); 522 bool handleBTSplitSwitchCase(CaseRec& CR, 523 CaseRecVector& WorkList, 524 Value* SV, 525 MachineBasicBlock* Default); 526 bool handleBitTestsSwitchCase(CaseRec& CR, 527 CaseRecVector& WorkList, 528 Value* SV, 529 MachineBasicBlock* Default); 530 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 531 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 532 void visitBitTestCase(MachineBasicBlock* NextMBB, 533 unsigned Reg, 534 SelectionDAGISel::BitTestCase &B); 535 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 536 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 537 SelectionDAGISel::JumpTableHeader &JTH); 538 539 // These all get lowered before this pass. 540 void visitInvoke(InvokeInst &I); 541 void visitUnwind(UnwindInst &I); 542 543 void visitBinary(User &I, unsigned OpCode); 544 void visitShift(User &I, unsigned Opcode); 545 void visitAdd(User &I) { 546 if (I.getType()->isFPOrFPVector()) 547 visitBinary(I, ISD::FADD); 548 else 549 visitBinary(I, ISD::ADD); 550 } 551 void visitSub(User &I); 552 void visitMul(User &I) { 553 if (I.getType()->isFPOrFPVector()) 554 visitBinary(I, ISD::FMUL); 555 else 556 visitBinary(I, ISD::MUL); 557 } 558 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 559 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 560 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 561 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 562 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 563 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 564 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 565 void visitOr (User &I) { visitBinary(I, ISD::OR); } 566 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 567 void visitShl (User &I) { visitShift(I, ISD::SHL); } 568 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 569 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 570 void visitICmp(User &I); 571 void visitFCmp(User &I); 572 // Visit the conversion instructions 573 void visitTrunc(User &I); 574 void visitZExt(User &I); 575 void visitSExt(User &I); 576 void visitFPTrunc(User &I); 577 void visitFPExt(User &I); 578 void visitFPToUI(User &I); 579 void visitFPToSI(User &I); 580 void visitUIToFP(User &I); 581 void visitSIToFP(User &I); 582 void visitPtrToInt(User &I); 583 void visitIntToPtr(User &I); 584 void visitBitCast(User &I); 585 586 void visitExtractElement(User &I); 587 void visitInsertElement(User &I); 588 void visitShuffleVector(User &I); 589 590 void visitGetElementPtr(User &I); 591 void visitSelect(User &I); 592 593 void visitMalloc(MallocInst &I); 594 void visitFree(FreeInst &I); 595 void visitAlloca(AllocaInst &I); 596 void visitLoad(LoadInst &I); 597 void visitStore(StoreInst &I); 598 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 599 void visitCall(CallInst &I); 600 void visitInlineAsm(CallInst &I); 601 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 602 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 603 604 void visitVAStart(CallInst &I); 605 void visitVAArg(VAArgInst &I); 606 void visitVAEnd(CallInst &I); 607 void visitVACopy(CallInst &I); 608 609 void visitMemIntrinsic(CallInst &I, unsigned Op); 610 611 void visitUserOp1(Instruction &I) { 612 assert(0 && "UserOp1 should not exist at instruction selection time!"); 613 abort(); 614 } 615 void visitUserOp2(Instruction &I) { 616 assert(0 && "UserOp2 should not exist at instruction selection time!"); 617 abort(); 618 } 619}; 620} // end namespace llvm 621 622 623/// getCopyFromParts - Create a value that contains the 624/// specified legal parts combined into the value they represent. 625static SDOperand getCopyFromParts(SelectionDAG &DAG, 626 const SDOperand *Parts, 627 unsigned NumParts, 628 MVT::ValueType PartVT, 629 MVT::ValueType ValueVT, 630 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 631 if (!MVT::isVector(ValueVT) || NumParts == 1) { 632 SDOperand Val = Parts[0]; 633 634 // If the value was expanded, copy from the top part. 635 if (NumParts > 1) { 636 assert(NumParts == 2 && 637 "Cannot expand to more than 2 elts yet!"); 638 SDOperand Hi = Parts[1]; 639 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 640 std::swap(Val, Hi); 641 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 642 } 643 644 // Otherwise, if the value was promoted or extended, truncate it to the 645 // appropriate type. 646 if (PartVT == ValueVT) 647 return Val; 648 649 if (MVT::isVector(PartVT)) { 650 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!"); 651 return DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 652 } 653 654 if (MVT::isInteger(PartVT) && 655 MVT::isInteger(ValueVT)) { 656 if (ValueVT < PartVT) { 657 // For a truncate, see if we have any information to 658 // indicate whether the truncated bits will always be 659 // zero or sign-extension. 660 if (AssertOp != ISD::DELETED_NODE) 661 Val = DAG.getNode(AssertOp, PartVT, Val, 662 DAG.getValueType(ValueVT)); 663 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 664 } else { 665 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 666 } 667 } 668 669 if (MVT::isFloatingPoint(PartVT) && 670 MVT::isFloatingPoint(ValueVT)) 671 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 672 673 if (MVT::getSizeInBits(PartVT) == 674 MVT::getSizeInBits(ValueVT)) 675 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 676 677 assert(0 && "Unknown mismatch!"); 678 } 679 680 // Handle a multi-element vector. 681 MVT::ValueType IntermediateVT, RegisterVT; 682 unsigned NumIntermediates; 683 unsigned NumRegs = 684 DAG.getTargetLoweringInfo() 685 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 686 RegisterVT); 687 688 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 689 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 690 assert(RegisterVT == Parts[0].getValueType() && 691 "Part type doesn't match part!"); 692 693 // Assemble the parts into intermediate operands. 694 SmallVector<SDOperand, 8> Ops(NumIntermediates); 695 if (NumIntermediates == NumParts) { 696 // If the register was not expanded, truncate or copy the value, 697 // as appropriate. 698 for (unsigned i = 0; i != NumParts; ++i) 699 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 700 PartVT, IntermediateVT); 701 } else if (NumParts > 0) { 702 // If the intermediate type was expanded, build the intermediate operands 703 // from the parts. 704 assert(NumParts % NumIntermediates == 0 && 705 "Must expand into a divisible number of parts!"); 706 unsigned Factor = NumParts / NumIntermediates; 707 for (unsigned i = 0; i != NumIntermediates; ++i) 708 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 709 PartVT, IntermediateVT); 710 } 711 712 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 713 // operands. 714 return DAG.getNode(MVT::isVector(IntermediateVT) ? 715 ISD::CONCAT_VECTORS : 716 ISD::BUILD_VECTOR, 717 ValueVT, &Ops[0], NumIntermediates); 718} 719 720/// getCopyToParts - Create a series of nodes that contain the 721/// specified value split into legal parts. 722static void getCopyToParts(SelectionDAG &DAG, 723 SDOperand Val, 724 SDOperand *Parts, 725 unsigned NumParts, 726 MVT::ValueType PartVT) { 727 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 728 MVT::ValueType PtrVT = TLI.getPointerTy(); 729 MVT::ValueType ValueVT = Val.getValueType(); 730 731 if (!MVT::isVector(ValueVT) || NumParts == 1) { 732 // If the value was expanded, copy from the parts. 733 if (NumParts > 1) { 734 for (unsigned i = 0; i != NumParts; ++i) 735 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val, 736 DAG.getConstant(i, PtrVT)); 737 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 738 std::reverse(Parts, Parts + NumParts); 739 return; 740 } 741 742 // If there is a single part and the types differ, this must be 743 // a promotion. 744 if (PartVT != ValueVT) { 745 if (MVT::isVector(PartVT)) { 746 assert(MVT::isVector(ValueVT) && 747 "Not a vector-vector cast?"); 748 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 749 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 750 if (PartVT < ValueVT) 751 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val); 752 else 753 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val); 754 } else if (MVT::isFloatingPoint(PartVT) && 755 MVT::isFloatingPoint(ValueVT)) { 756 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 757 } else if (MVT::getSizeInBits(PartVT) == 758 MVT::getSizeInBits(ValueVT)) { 759 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 760 } else { 761 assert(0 && "Unknown mismatch!"); 762 } 763 } 764 Parts[0] = Val; 765 return; 766 } 767 768 // Handle a multi-element vector. 769 MVT::ValueType IntermediateVT, RegisterVT; 770 unsigned NumIntermediates; 771 unsigned NumRegs = 772 DAG.getTargetLoweringInfo() 773 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 774 RegisterVT); 775 unsigned NumElements = MVT::getVectorNumElements(ValueVT); 776 777 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 778 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 779 780 // Split the vector into intermediate operands. 781 SmallVector<SDOperand, 8> Ops(NumIntermediates); 782 for (unsigned i = 0; i != NumIntermediates; ++i) 783 if (MVT::isVector(IntermediateVT)) 784 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 785 IntermediateVT, Val, 786 DAG.getConstant(i * (NumElements / NumIntermediates), 787 PtrVT)); 788 else 789 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 790 IntermediateVT, Val, 791 DAG.getConstant(i, PtrVT)); 792 793 // Split the intermediate operands into legal parts. 794 if (NumParts == NumIntermediates) { 795 // If the register was not expanded, promote or copy the value, 796 // as appropriate. 797 for (unsigned i = 0; i != NumParts; ++i) 798 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 799 } else if (NumParts > 0) { 800 // If the intermediate type was expanded, split each the value into 801 // legal parts. 802 assert(NumParts % NumIntermediates == 0 && 803 "Must expand into a divisible number of parts!"); 804 unsigned Factor = NumParts / NumIntermediates; 805 for (unsigned i = 0; i != NumIntermediates; ++i) 806 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 807 } 808} 809 810 811SDOperand SelectionDAGLowering::getValue(const Value *V) { 812 SDOperand &N = NodeMap[V]; 813 if (N.Val) return N; 814 815 const Type *VTy = V->getType(); 816 MVT::ValueType VT = TLI.getValueType(VTy); 817 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 818 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 819 visit(CE->getOpcode(), *CE); 820 SDOperand N1 = NodeMap[V]; 821 assert(N1.Val && "visit didn't populate the ValueMap!"); 822 return N1; 823 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 824 return N = DAG.getGlobalAddress(GV, VT); 825 } else if (isa<ConstantPointerNull>(C)) { 826 return N = DAG.getConstant(0, TLI.getPointerTy()); 827 } else if (isa<UndefValue>(C)) { 828 if (!isa<VectorType>(VTy)) 829 return N = DAG.getNode(ISD::UNDEF, VT); 830 831 // Create a BUILD_VECTOR of undef nodes. 832 const VectorType *PTy = cast<VectorType>(VTy); 833 unsigned NumElements = PTy->getNumElements(); 834 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 835 836 SmallVector<SDOperand, 8> Ops; 837 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 838 839 // Create a VConstant node with generic Vector type. 840 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 841 return N = DAG.getNode(ISD::BUILD_VECTOR, VT, 842 &Ops[0], Ops.size()); 843 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 844 return N = DAG.getConstantFP(CFP->getValueAPF(), VT); 845 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 846 unsigned NumElements = PTy->getNumElements(); 847 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 848 849 // Now that we know the number and type of the elements, push a 850 // Constant or ConstantFP node onto the ops list for each element of 851 // the vector constant. 852 SmallVector<SDOperand, 8> Ops; 853 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 854 for (unsigned i = 0; i != NumElements; ++i) 855 Ops.push_back(getValue(CP->getOperand(i))); 856 } else { 857 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 858 SDOperand Op; 859 if (MVT::isFloatingPoint(PVT)) 860 Op = DAG.getConstantFP(0, PVT); 861 else 862 Op = DAG.getConstant(0, PVT); 863 Ops.assign(NumElements, Op); 864 } 865 866 // Create a BUILD_VECTOR node. 867 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 868 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], 869 Ops.size()); 870 } else { 871 // Canonicalize all constant ints to be unsigned. 872 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT); 873 } 874 } 875 876 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 877 std::map<const AllocaInst*, int>::iterator SI = 878 FuncInfo.StaticAllocaMap.find(AI); 879 if (SI != FuncInfo.StaticAllocaMap.end()) 880 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 881 } 882 883 unsigned InReg = FuncInfo.ValueMap[V]; 884 assert(InReg && "Value not in map!"); 885 886 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 887 unsigned NumRegs = TLI.getNumRegisters(VT); 888 889 std::vector<unsigned> Regs(NumRegs); 890 for (unsigned i = 0; i != NumRegs; ++i) 891 Regs[i] = InReg + i; 892 893 RegsForValue RFV(Regs, RegisterVT, VT); 894 SDOperand Chain = DAG.getEntryNode(); 895 896 return RFV.getCopyFromRegs(DAG, Chain, NULL); 897} 898 899 900void SelectionDAGLowering::visitRet(ReturnInst &I) { 901 if (I.getNumOperands() == 0) { 902 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 903 return; 904 } 905 SmallVector<SDOperand, 8> NewValues; 906 NewValues.push_back(getRoot()); 907 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 908 SDOperand RetOp = getValue(I.getOperand(i)); 909 910 // If this is an integer return value, we need to promote it ourselves to 911 // the full width of a register, since getCopyToParts and Legalize will use 912 // ANY_EXTEND rather than sign/zero. 913 // FIXME: C calling convention requires the return type to be promoted to 914 // at least 32-bit. But this is not necessary for non-C calling conventions. 915 if (MVT::isInteger(RetOp.getValueType()) && 916 RetOp.getValueType() < MVT::i64) { 917 MVT::ValueType TmpVT; 918 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 919 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 920 else 921 TmpVT = MVT::i32; 922 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType(); 923 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 924 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 925 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt)) 926 ExtendKind = ISD::SIGN_EXTEND; 927 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt)) 928 ExtendKind = ISD::ZERO_EXTEND; 929 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp); 930 NewValues.push_back(RetOp); 931 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 932 } else { 933 MVT::ValueType VT = RetOp.getValueType(); 934 unsigned NumParts = TLI.getNumRegisters(VT); 935 MVT::ValueType PartVT = TLI.getRegisterType(VT); 936 SmallVector<SDOperand, 4> Parts(NumParts); 937 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT); 938 for (unsigned i = 0; i < NumParts; ++i) { 939 NewValues.push_back(Parts[i]); 940 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 941 } 942 } 943 } 944 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 945 &NewValues[0], NewValues.size())); 946} 947 948/// ExportFromCurrentBlock - If this condition isn't known to be exported from 949/// the current basic block, add it to ValueMap now so that we'll get a 950/// CopyTo/FromReg. 951void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 952 // No need to export constants. 953 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 954 955 // Already exported? 956 if (FuncInfo.isExportedInst(V)) return; 957 958 unsigned Reg = FuncInfo.InitializeRegForValue(V); 959 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 960} 961 962bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 963 const BasicBlock *FromBB) { 964 // The operands of the setcc have to be in this block. We don't know 965 // how to export them from some other block. 966 if (Instruction *VI = dyn_cast<Instruction>(V)) { 967 // Can export from current BB. 968 if (VI->getParent() == FromBB) 969 return true; 970 971 // Is already exported, noop. 972 return FuncInfo.isExportedInst(V); 973 } 974 975 // If this is an argument, we can export it if the BB is the entry block or 976 // if it is already exported. 977 if (isa<Argument>(V)) { 978 if (FromBB == &FromBB->getParent()->getEntryBlock()) 979 return true; 980 981 // Otherwise, can only export this if it is already exported. 982 return FuncInfo.isExportedInst(V); 983 } 984 985 // Otherwise, constants can always be exported. 986 return true; 987} 988 989static bool InBlock(const Value *V, const BasicBlock *BB) { 990 if (const Instruction *I = dyn_cast<Instruction>(V)) 991 return I->getParent() == BB; 992 return true; 993} 994 995/// FindMergedConditions - If Cond is an expression like 996void SelectionDAGLowering::FindMergedConditions(Value *Cond, 997 MachineBasicBlock *TBB, 998 MachineBasicBlock *FBB, 999 MachineBasicBlock *CurBB, 1000 unsigned Opc) { 1001 // If this node is not part of the or/and tree, emit it as a branch. 1002 Instruction *BOp = dyn_cast<Instruction>(Cond); 1003 1004 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1005 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1006 BOp->getParent() != CurBB->getBasicBlock() || 1007 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1008 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1009 const BasicBlock *BB = CurBB->getBasicBlock(); 1010 1011 // If the leaf of the tree is a comparison, merge the condition into 1012 // the caseblock. 1013 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1014 // The operands of the cmp have to be in this block. We don't know 1015 // how to export them from some other block. If this is the first block 1016 // of the sequence, no exporting is needed. 1017 (CurBB == CurMBB || 1018 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1019 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1020 BOp = cast<Instruction>(Cond); 1021 ISD::CondCode Condition; 1022 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1023 switch (IC->getPredicate()) { 1024 default: assert(0 && "Unknown icmp predicate opcode!"); 1025 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1026 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1027 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1028 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1029 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1030 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1031 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1032 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1033 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1034 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1035 } 1036 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1037 ISD::CondCode FPC, FOC; 1038 switch (FC->getPredicate()) { 1039 default: assert(0 && "Unknown fcmp predicate opcode!"); 1040 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1041 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1042 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1043 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1044 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1045 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1046 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1047 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 1048 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 1049 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1050 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1051 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1052 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1053 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1054 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1055 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1056 } 1057 if (FiniteOnlyFPMath()) 1058 Condition = FOC; 1059 else 1060 Condition = FPC; 1061 } else { 1062 Condition = ISD::SETEQ; // silence warning. 1063 assert(0 && "Unknown compare instruction"); 1064 } 1065 1066 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1067 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1068 SwitchCases.push_back(CB); 1069 return; 1070 } 1071 1072 // Create a CaseBlock record representing this branch. 1073 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1074 NULL, TBB, FBB, CurBB); 1075 SwitchCases.push_back(CB); 1076 return; 1077 } 1078 1079 1080 // Create TmpBB after CurBB. 1081 MachineFunction::iterator BBI = CurBB; 1082 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 1083 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 1084 1085 if (Opc == Instruction::Or) { 1086 // Codegen X | Y as: 1087 // jmp_if_X TBB 1088 // jmp TmpBB 1089 // TmpBB: 1090 // jmp_if_Y TBB 1091 // jmp FBB 1092 // 1093 1094 // Emit the LHS condition. 1095 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1096 1097 // Emit the RHS condition into TmpBB. 1098 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1099 } else { 1100 assert(Opc == Instruction::And && "Unknown merge op!"); 1101 // Codegen X & Y as: 1102 // jmp_if_X TmpBB 1103 // jmp FBB 1104 // TmpBB: 1105 // jmp_if_Y TBB 1106 // jmp FBB 1107 // 1108 // This requires creation of TmpBB after CurBB. 1109 1110 // Emit the LHS condition. 1111 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1112 1113 // Emit the RHS condition into TmpBB. 1114 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1115 } 1116} 1117 1118/// If the set of cases should be emitted as a series of branches, return true. 1119/// If we should emit this as a bunch of and/or'd together conditions, return 1120/// false. 1121static bool 1122ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1123 if (Cases.size() != 2) return true; 1124 1125 // If this is two comparisons of the same values or'd or and'd together, they 1126 // will get folded into a single comparison, so don't emit two blocks. 1127 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1128 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1129 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1130 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1131 return false; 1132 } 1133 1134 return true; 1135} 1136 1137void SelectionDAGLowering::visitBr(BranchInst &I) { 1138 // Update machine-CFG edges. 1139 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1140 1141 // Figure out which block is immediately after the current one. 1142 MachineBasicBlock *NextBlock = 0; 1143 MachineFunction::iterator BBI = CurMBB; 1144 if (++BBI != CurMBB->getParent()->end()) 1145 NextBlock = BBI; 1146 1147 if (I.isUnconditional()) { 1148 // If this is not a fall-through branch, emit the branch. 1149 if (Succ0MBB != NextBlock) 1150 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1151 DAG.getBasicBlock(Succ0MBB))); 1152 1153 // Update machine-CFG edges. 1154 CurMBB->addSuccessor(Succ0MBB); 1155 1156 return; 1157 } 1158 1159 // If this condition is one of the special cases we handle, do special stuff 1160 // now. 1161 Value *CondVal = I.getCondition(); 1162 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1163 1164 // If this is a series of conditions that are or'd or and'd together, emit 1165 // this as a sequence of branches instead of setcc's with and/or operations. 1166 // For example, instead of something like: 1167 // cmp A, B 1168 // C = seteq 1169 // cmp D, E 1170 // F = setle 1171 // or C, F 1172 // jnz foo 1173 // Emit: 1174 // cmp A, B 1175 // je foo 1176 // cmp D, E 1177 // jle foo 1178 // 1179 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1180 if (BOp->hasOneUse() && 1181 (BOp->getOpcode() == Instruction::And || 1182 BOp->getOpcode() == Instruction::Or)) { 1183 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1184 // If the compares in later blocks need to use values not currently 1185 // exported from this block, export them now. This block should always 1186 // be the first entry. 1187 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1188 1189 // Allow some cases to be rejected. 1190 if (ShouldEmitAsBranches(SwitchCases)) { 1191 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1192 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1193 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1194 } 1195 1196 // Emit the branch for this block. 1197 visitSwitchCase(SwitchCases[0]); 1198 SwitchCases.erase(SwitchCases.begin()); 1199 return; 1200 } 1201 1202 // Okay, we decided not to do this, remove any inserted MBB's and clear 1203 // SwitchCases. 1204 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1205 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1206 1207 SwitchCases.clear(); 1208 } 1209 } 1210 1211 // Create a CaseBlock record representing this branch. 1212 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1213 NULL, Succ0MBB, Succ1MBB, CurMBB); 1214 // Use visitSwitchCase to actually insert the fast branch sequence for this 1215 // cond branch. 1216 visitSwitchCase(CB); 1217} 1218 1219/// visitSwitchCase - Emits the necessary code to represent a single node in 1220/// the binary search tree resulting from lowering a switch instruction. 1221void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1222 SDOperand Cond; 1223 SDOperand CondLHS = getValue(CB.CmpLHS); 1224 1225 // Build the setcc now. 1226 if (CB.CmpMHS == NULL) { 1227 // Fold "(X == true)" to X and "(X == false)" to !X to 1228 // handle common cases produced by branch lowering. 1229 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1230 Cond = CondLHS; 1231 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1232 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1233 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1234 } else 1235 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1236 } else { 1237 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1238 1239 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1240 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1241 1242 SDOperand CmpOp = getValue(CB.CmpMHS); 1243 MVT::ValueType VT = CmpOp.getValueType(); 1244 1245 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1246 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1247 } else { 1248 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1249 Cond = DAG.getSetCC(MVT::i1, SUB, 1250 DAG.getConstant(High-Low, VT), ISD::SETULE); 1251 } 1252 1253 } 1254 1255 // Set NextBlock to be the MBB immediately after the current one, if any. 1256 // This is used to avoid emitting unnecessary branches to the next block. 1257 MachineBasicBlock *NextBlock = 0; 1258 MachineFunction::iterator BBI = CurMBB; 1259 if (++BBI != CurMBB->getParent()->end()) 1260 NextBlock = BBI; 1261 1262 // If the lhs block is the next block, invert the condition so that we can 1263 // fall through to the lhs instead of the rhs block. 1264 if (CB.TrueBB == NextBlock) { 1265 std::swap(CB.TrueBB, CB.FalseBB); 1266 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1267 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1268 } 1269 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1270 DAG.getBasicBlock(CB.TrueBB)); 1271 if (CB.FalseBB == NextBlock) 1272 DAG.setRoot(BrCond); 1273 else 1274 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1275 DAG.getBasicBlock(CB.FalseBB))); 1276 // Update successor info 1277 CurMBB->addSuccessor(CB.TrueBB); 1278 CurMBB->addSuccessor(CB.FalseBB); 1279} 1280 1281/// visitJumpTable - Emit JumpTable node in the current MBB 1282void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1283 // Emit the code for the jump table 1284 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1285 MVT::ValueType PTy = TLI.getPointerTy(); 1286 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1287 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1288 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1289 Table, Index)); 1290 return; 1291} 1292 1293/// visitJumpTableHeader - This function emits necessary code to produce index 1294/// in the JumpTable from switch case. 1295void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1296 SelectionDAGISel::JumpTableHeader &JTH) { 1297 // Subtract the lowest switch case value from the value being switched on 1298 // and conditional branch to default mbb if the result is greater than the 1299 // difference between smallest and largest cases. 1300 SDOperand SwitchOp = getValue(JTH.SValue); 1301 MVT::ValueType VT = SwitchOp.getValueType(); 1302 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1303 DAG.getConstant(JTH.First, VT)); 1304 1305 // The SDNode we just created, which holds the value being switched on 1306 // minus the the smallest case value, needs to be copied to a virtual 1307 // register so it can be used as an index into the jump table in a 1308 // subsequent basic block. This value may be smaller or larger than the 1309 // target's pointer type, and therefore require extension or truncating. 1310 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 1311 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1312 else 1313 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1314 1315 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1316 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1317 JT.Reg = JumpTableReg; 1318 1319 // Emit the range check for the jump table, and branch to the default 1320 // block for the switch statement if the value being switched on exceeds 1321 // the largest case in the switch. 1322 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1323 DAG.getConstant(JTH.Last-JTH.First,VT), 1324 ISD::SETUGT); 1325 1326 // Set NextBlock to be the MBB immediately after the current one, if any. 1327 // This is used to avoid emitting unnecessary branches to the next block. 1328 MachineBasicBlock *NextBlock = 0; 1329 MachineFunction::iterator BBI = CurMBB; 1330 if (++BBI != CurMBB->getParent()->end()) 1331 NextBlock = BBI; 1332 1333 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1334 DAG.getBasicBlock(JT.Default)); 1335 1336 if (JT.MBB == NextBlock) 1337 DAG.setRoot(BrCond); 1338 else 1339 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1340 DAG.getBasicBlock(JT.MBB))); 1341 1342 return; 1343} 1344 1345/// visitBitTestHeader - This function emits necessary code to produce value 1346/// suitable for "bit tests" 1347void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1348 // Subtract the minimum value 1349 SDOperand SwitchOp = getValue(B.SValue); 1350 MVT::ValueType VT = SwitchOp.getValueType(); 1351 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1352 DAG.getConstant(B.First, VT)); 1353 1354 // Check range 1355 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1356 DAG.getConstant(B.Range, VT), 1357 ISD::SETUGT); 1358 1359 SDOperand ShiftOp; 1360 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy())) 1361 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1362 else 1363 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1364 1365 // Make desired shift 1366 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1367 DAG.getConstant(1, TLI.getPointerTy()), 1368 ShiftOp); 1369 1370 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1371 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1372 B.Reg = SwitchReg; 1373 1374 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1375 DAG.getBasicBlock(B.Default)); 1376 1377 // Set NextBlock to be the MBB immediately after the current one, if any. 1378 // This is used to avoid emitting unnecessary branches to the next block. 1379 MachineBasicBlock *NextBlock = 0; 1380 MachineFunction::iterator BBI = CurMBB; 1381 if (++BBI != CurMBB->getParent()->end()) 1382 NextBlock = BBI; 1383 1384 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1385 if (MBB == NextBlock) 1386 DAG.setRoot(BrRange); 1387 else 1388 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1389 DAG.getBasicBlock(MBB))); 1390 1391 CurMBB->addSuccessor(B.Default); 1392 CurMBB->addSuccessor(MBB); 1393 1394 return; 1395} 1396 1397/// visitBitTestCase - this function produces one "bit test" 1398void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1399 unsigned Reg, 1400 SelectionDAGISel::BitTestCase &B) { 1401 // Emit bit tests and jumps 1402 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1403 1404 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1405 SwitchVal, 1406 DAG.getConstant(B.Mask, 1407 TLI.getPointerTy())); 1408 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, 1409 DAG.getConstant(0, TLI.getPointerTy()), 1410 ISD::SETNE); 1411 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1412 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1413 1414 // Set NextBlock to be the MBB immediately after the current one, if any. 1415 // This is used to avoid emitting unnecessary branches to the next block. 1416 MachineBasicBlock *NextBlock = 0; 1417 MachineFunction::iterator BBI = CurMBB; 1418 if (++BBI != CurMBB->getParent()->end()) 1419 NextBlock = BBI; 1420 1421 if (NextMBB == NextBlock) 1422 DAG.setRoot(BrAnd); 1423 else 1424 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1425 DAG.getBasicBlock(NextMBB))); 1426 1427 CurMBB->addSuccessor(B.TargetBB); 1428 CurMBB->addSuccessor(NextMBB); 1429 1430 return; 1431} 1432 1433void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1434 // Retrieve successors. 1435 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1436 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1437 1438 LowerCallTo(I, I.getCalledValue()->getType(), 1439 I.getCallingConv(), 1440 false, 1441 getValue(I.getOperand(0)), 1442 3, LandingPad); 1443 1444 // If the value of the invoke is used outside of its defining block, make it 1445 // available as a virtual register. 1446 if (!I.use_empty()) { 1447 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1448 if (VMI != FuncInfo.ValueMap.end()) 1449 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second)); 1450 } 1451 1452 // Drop into normal successor. 1453 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1454 DAG.getBasicBlock(Return))); 1455 1456 // Update successor info 1457 CurMBB->addSuccessor(Return); 1458 CurMBB->addSuccessor(LandingPad); 1459} 1460 1461void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1462} 1463 1464/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1465/// small case ranges). 1466bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1467 CaseRecVector& WorkList, 1468 Value* SV, 1469 MachineBasicBlock* Default) { 1470 Case& BackCase = *(CR.Range.second-1); 1471 1472 // Size is the number of Cases represented by this range. 1473 unsigned Size = CR.Range.second - CR.Range.first; 1474 if (Size > 3) 1475 return false; 1476 1477 // Get the MachineFunction which holds the current MBB. This is used when 1478 // inserting any additional MBBs necessary to represent the switch. 1479 MachineFunction *CurMF = CurMBB->getParent(); 1480 1481 // Figure out which block is immediately after the current one. 1482 MachineBasicBlock *NextBlock = 0; 1483 MachineFunction::iterator BBI = CR.CaseBB; 1484 1485 if (++BBI != CurMBB->getParent()->end()) 1486 NextBlock = BBI; 1487 1488 // TODO: If any two of the cases has the same destination, and if one value 1489 // is the same as the other, but has one bit unset that the other has set, 1490 // use bit manipulation to do two compares at once. For example: 1491 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1492 1493 // Rearrange the case blocks so that the last one falls through if possible. 1494 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1495 // The last case block won't fall through into 'NextBlock' if we emit the 1496 // branches in this order. See if rearranging a case value would help. 1497 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1498 if (I->BB == NextBlock) { 1499 std::swap(*I, BackCase); 1500 break; 1501 } 1502 } 1503 } 1504 1505 // Create a CaseBlock record representing a conditional branch to 1506 // the Case's target mbb if the value being switched on SV is equal 1507 // to C. 1508 MachineBasicBlock *CurBlock = CR.CaseBB; 1509 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1510 MachineBasicBlock *FallThrough; 1511 if (I != E-1) { 1512 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1513 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1514 } else { 1515 // If the last case doesn't match, go to the default block. 1516 FallThrough = Default; 1517 } 1518 1519 Value *RHS, *LHS, *MHS; 1520 ISD::CondCode CC; 1521 if (I->High == I->Low) { 1522 // This is just small small case range :) containing exactly 1 case 1523 CC = ISD::SETEQ; 1524 LHS = SV; RHS = I->High; MHS = NULL; 1525 } else { 1526 CC = ISD::SETLE; 1527 LHS = I->Low; MHS = SV; RHS = I->High; 1528 } 1529 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1530 I->BB, FallThrough, CurBlock); 1531 1532 // If emitting the first comparison, just call visitSwitchCase to emit the 1533 // code into the current block. Otherwise, push the CaseBlock onto the 1534 // vector to be later processed by SDISel, and insert the node's MBB 1535 // before the next MBB. 1536 if (CurBlock == CurMBB) 1537 visitSwitchCase(CB); 1538 else 1539 SwitchCases.push_back(CB); 1540 1541 CurBlock = FallThrough; 1542 } 1543 1544 return true; 1545} 1546 1547static inline bool areJTsAllowed(const TargetLowering &TLI) { 1548 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1549 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1550} 1551 1552/// handleJTSwitchCase - Emit jumptable for current switch case range 1553bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1554 CaseRecVector& WorkList, 1555 Value* SV, 1556 MachineBasicBlock* Default) { 1557 Case& FrontCase = *CR.Range.first; 1558 Case& BackCase = *(CR.Range.second-1); 1559 1560 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1561 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1562 1563 uint64_t TSize = 0; 1564 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1565 I!=E; ++I) 1566 TSize += I->size(); 1567 1568 if (!areJTsAllowed(TLI) || TSize <= 3) 1569 return false; 1570 1571 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1572 if (Density < 0.4) 1573 return false; 1574 1575 DOUT << "Lowering jump table\n" 1576 << "First entry: " << First << ". Last entry: " << Last << "\n" 1577 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1578 1579 // Get the MachineFunction which holds the current MBB. This is used when 1580 // inserting any additional MBBs necessary to represent the switch. 1581 MachineFunction *CurMF = CurMBB->getParent(); 1582 1583 // Figure out which block is immediately after the current one. 1584 MachineBasicBlock *NextBlock = 0; 1585 MachineFunction::iterator BBI = CR.CaseBB; 1586 1587 if (++BBI != CurMBB->getParent()->end()) 1588 NextBlock = BBI; 1589 1590 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1591 1592 // Create a new basic block to hold the code for loading the address 1593 // of the jump table, and jumping to it. Update successor information; 1594 // we will either branch to the default case for the switch, or the jump 1595 // table. 1596 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1597 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1598 CR.CaseBB->addSuccessor(Default); 1599 CR.CaseBB->addSuccessor(JumpTableBB); 1600 1601 // Build a vector of destination BBs, corresponding to each target 1602 // of the jump table. If the value of the jump table slot corresponds to 1603 // a case statement, push the case's BB onto the vector, otherwise, push 1604 // the default BB. 1605 std::vector<MachineBasicBlock*> DestBBs; 1606 int64_t TEI = First; 1607 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1608 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1609 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1610 1611 if ((Low <= TEI) && (TEI <= High)) { 1612 DestBBs.push_back(I->BB); 1613 if (TEI==High) 1614 ++I; 1615 } else { 1616 DestBBs.push_back(Default); 1617 } 1618 } 1619 1620 // Update successor info. Add one edge to each unique successor. 1621 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1622 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1623 E = DestBBs.end(); I != E; ++I) { 1624 if (!SuccsHandled[(*I)->getNumber()]) { 1625 SuccsHandled[(*I)->getNumber()] = true; 1626 JumpTableBB->addSuccessor(*I); 1627 } 1628 } 1629 1630 // Create a jump table index for this jump table, or return an existing 1631 // one. 1632 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1633 1634 // Set the jump table information so that we can codegen it as a second 1635 // MachineBasicBlock 1636 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1637 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1638 (CR.CaseBB == CurMBB)); 1639 if (CR.CaseBB == CurMBB) 1640 visitJumpTableHeader(JT, JTH); 1641 1642 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1643 1644 return true; 1645} 1646 1647/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1648/// 2 subtrees. 1649bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1650 CaseRecVector& WorkList, 1651 Value* SV, 1652 MachineBasicBlock* Default) { 1653 // Get the MachineFunction which holds the current MBB. This is used when 1654 // inserting any additional MBBs necessary to represent the switch. 1655 MachineFunction *CurMF = CurMBB->getParent(); 1656 1657 // Figure out which block is immediately after the current one. 1658 MachineBasicBlock *NextBlock = 0; 1659 MachineFunction::iterator BBI = CR.CaseBB; 1660 1661 if (++BBI != CurMBB->getParent()->end()) 1662 NextBlock = BBI; 1663 1664 Case& FrontCase = *CR.Range.first; 1665 Case& BackCase = *(CR.Range.second-1); 1666 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1667 1668 // Size is the number of Cases represented by this range. 1669 unsigned Size = CR.Range.second - CR.Range.first; 1670 1671 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1672 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1673 double FMetric = 0; 1674 CaseItr Pivot = CR.Range.first + Size/2; 1675 1676 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1677 // (heuristically) allow us to emit JumpTable's later. 1678 uint64_t TSize = 0; 1679 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1680 I!=E; ++I) 1681 TSize += I->size(); 1682 1683 uint64_t LSize = FrontCase.size(); 1684 uint64_t RSize = TSize-LSize; 1685 DOUT << "Selecting best pivot: \n" 1686 << "First: " << First << ", Last: " << Last <<"\n" 1687 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1688 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1689 J!=E; ++I, ++J) { 1690 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1691 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1692 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1693 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1694 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1695 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1696 // Should always split in some non-trivial place 1697 DOUT <<"=>Step\n" 1698 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1699 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1700 << "Metric: " << Metric << "\n"; 1701 if (FMetric < Metric) { 1702 Pivot = J; 1703 FMetric = Metric; 1704 DOUT << "Current metric set to: " << FMetric << "\n"; 1705 } 1706 1707 LSize += J->size(); 1708 RSize -= J->size(); 1709 } 1710 if (areJTsAllowed(TLI)) { 1711 // If our case is dense we *really* should handle it earlier! 1712 assert((FMetric > 0) && "Should handle dense range earlier!"); 1713 } else { 1714 Pivot = CR.Range.first + Size/2; 1715 } 1716 1717 CaseRange LHSR(CR.Range.first, Pivot); 1718 CaseRange RHSR(Pivot, CR.Range.second); 1719 Constant *C = Pivot->Low; 1720 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1721 1722 // We know that we branch to the LHS if the Value being switched on is 1723 // less than the Pivot value, C. We use this to optimize our binary 1724 // tree a bit, by recognizing that if SV is greater than or equal to the 1725 // LHS's Case Value, and that Case Value is exactly one less than the 1726 // Pivot's Value, then we can branch directly to the LHS's Target, 1727 // rather than creating a leaf node for it. 1728 if ((LHSR.second - LHSR.first) == 1 && 1729 LHSR.first->High == CR.GE && 1730 cast<ConstantInt>(C)->getSExtValue() == 1731 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1732 TrueBB = LHSR.first->BB; 1733 } else { 1734 TrueBB = new MachineBasicBlock(LLVMBB); 1735 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1736 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1737 } 1738 1739 // Similar to the optimization above, if the Value being switched on is 1740 // known to be less than the Constant CR.LT, and the current Case Value 1741 // is CR.LT - 1, then we can branch directly to the target block for 1742 // the current Case Value, rather than emitting a RHS leaf node for it. 1743 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1744 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1745 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1746 FalseBB = RHSR.first->BB; 1747 } else { 1748 FalseBB = new MachineBasicBlock(LLVMBB); 1749 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1750 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1751 } 1752 1753 // Create a CaseBlock record representing a conditional branch to 1754 // the LHS node if the value being switched on SV is less than C. 1755 // Otherwise, branch to LHS. 1756 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1757 TrueBB, FalseBB, CR.CaseBB); 1758 1759 if (CR.CaseBB == CurMBB) 1760 visitSwitchCase(CB); 1761 else 1762 SwitchCases.push_back(CB); 1763 1764 return true; 1765} 1766 1767/// handleBitTestsSwitchCase - if current case range has few destination and 1768/// range span less, than machine word bitwidth, encode case range into series 1769/// of masks and emit bit tests with these masks. 1770bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1771 CaseRecVector& WorkList, 1772 Value* SV, 1773 MachineBasicBlock* Default){ 1774 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); 1775 1776 Case& FrontCase = *CR.Range.first; 1777 Case& BackCase = *(CR.Range.second-1); 1778 1779 // Get the MachineFunction which holds the current MBB. This is used when 1780 // inserting any additional MBBs necessary to represent the switch. 1781 MachineFunction *CurMF = CurMBB->getParent(); 1782 1783 unsigned numCmps = 0; 1784 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1785 I!=E; ++I) { 1786 // Single case counts one, case range - two. 1787 if (I->Low == I->High) 1788 numCmps +=1; 1789 else 1790 numCmps +=2; 1791 } 1792 1793 // Count unique destinations 1794 SmallSet<MachineBasicBlock*, 4> Dests; 1795 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1796 Dests.insert(I->BB); 1797 if (Dests.size() > 3) 1798 // Don't bother the code below, if there are too much unique destinations 1799 return false; 1800 } 1801 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1802 << "Total number of comparisons: " << numCmps << "\n"; 1803 1804 // Compute span of values. 1805 Constant* minValue = FrontCase.Low; 1806 Constant* maxValue = BackCase.High; 1807 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1808 cast<ConstantInt>(minValue)->getSExtValue(); 1809 DOUT << "Compare range: " << range << "\n" 1810 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1811 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1812 1813 if (range>=IntPtrBits || 1814 (!(Dests.size() == 1 && numCmps >= 3) && 1815 !(Dests.size() == 2 && numCmps >= 5) && 1816 !(Dests.size() >= 3 && numCmps >= 6))) 1817 return false; 1818 1819 DOUT << "Emitting bit tests\n"; 1820 int64_t lowBound = 0; 1821 1822 // Optimize the case where all the case values fit in a 1823 // word without having to subtract minValue. In this case, 1824 // we can optimize away the subtraction. 1825 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1826 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1827 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1828 } else { 1829 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1830 } 1831 1832 CaseBitsVector CasesBits; 1833 unsigned i, count = 0; 1834 1835 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1836 MachineBasicBlock* Dest = I->BB; 1837 for (i = 0; i < count; ++i) 1838 if (Dest == CasesBits[i].BB) 1839 break; 1840 1841 if (i == count) { 1842 assert((count < 3) && "Too much destinations to test!"); 1843 CasesBits.push_back(CaseBits(0, Dest, 0)); 1844 count++; 1845 } 1846 1847 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1848 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1849 1850 for (uint64_t j = lo; j <= hi; j++) { 1851 CasesBits[i].Mask |= 1ULL << j; 1852 CasesBits[i].Bits++; 1853 } 1854 1855 } 1856 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1857 1858 SelectionDAGISel::BitTestInfo BTC; 1859 1860 // Figure out which block is immediately after the current one. 1861 MachineFunction::iterator BBI = CR.CaseBB; 1862 ++BBI; 1863 1864 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1865 1866 DOUT << "Cases:\n"; 1867 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1868 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1869 << ", BB: " << CasesBits[i].BB << "\n"; 1870 1871 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1872 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1873 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1874 CaseBB, 1875 CasesBits[i].BB)); 1876 } 1877 1878 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 1879 -1U, (CR.CaseBB == CurMBB), 1880 CR.CaseBB, Default, BTC); 1881 1882 if (CR.CaseBB == CurMBB) 1883 visitBitTestHeader(BTB); 1884 1885 BitTestCases.push_back(BTB); 1886 1887 return true; 1888} 1889 1890 1891// Clusterify - Transform simple list of Cases into list of CaseRange's 1892unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 1893 const SwitchInst& SI) { 1894 unsigned numCmps = 0; 1895 1896 // Start with "simple" cases 1897 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 1898 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1899 Cases.push_back(Case(SI.getSuccessorValue(i), 1900 SI.getSuccessorValue(i), 1901 SMBB)); 1902 } 1903 sort(Cases.begin(), Cases.end(), CaseCmp()); 1904 1905 // Merge case into clusters 1906 if (Cases.size()>=2) 1907 // Must recompute end() each iteration because it may be 1908 // invalidated by erase if we hold on to it 1909 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 1910 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 1911 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 1912 MachineBasicBlock* nextBB = J->BB; 1913 MachineBasicBlock* currentBB = I->BB; 1914 1915 // If the two neighboring cases go to the same destination, merge them 1916 // into a single case. 1917 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 1918 I->High = J->High; 1919 J = Cases.erase(J); 1920 } else { 1921 I = J++; 1922 } 1923 } 1924 1925 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1926 if (I->Low != I->High) 1927 // A range counts double, since it requires two compares. 1928 ++numCmps; 1929 } 1930 1931 return numCmps; 1932} 1933 1934void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 1935 // Figure out which block is immediately after the current one. 1936 MachineBasicBlock *NextBlock = 0; 1937 MachineFunction::iterator BBI = CurMBB; 1938 1939 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 1940 1941 // If there is only the default destination, branch to it if it is not the 1942 // next basic block. Otherwise, just fall through. 1943 if (SI.getNumOperands() == 2) { 1944 // Update machine-CFG edges. 1945 1946 // If this is not a fall-through branch, emit the branch. 1947 if (Default != NextBlock) 1948 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1949 DAG.getBasicBlock(Default))); 1950 1951 CurMBB->addSuccessor(Default); 1952 return; 1953 } 1954 1955 // If there are any non-default case statements, create a vector of Cases 1956 // representing each one, and sort the vector so that we can efficiently 1957 // create a binary search tree from them. 1958 CaseVector Cases; 1959 unsigned numCmps = Clusterify(Cases, SI); 1960 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 1961 << ". Total compares: " << numCmps << "\n"; 1962 1963 // Get the Value to be switched on and default basic blocks, which will be 1964 // inserted into CaseBlock records, representing basic blocks in the binary 1965 // search tree. 1966 Value *SV = SI.getOperand(0); 1967 1968 // Push the initial CaseRec onto the worklist 1969 CaseRecVector WorkList; 1970 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1971 1972 while (!WorkList.empty()) { 1973 // Grab a record representing a case range to process off the worklist 1974 CaseRec CR = WorkList.back(); 1975 WorkList.pop_back(); 1976 1977 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 1978 continue; 1979 1980 // If the range has few cases (two or less) emit a series of specific 1981 // tests. 1982 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 1983 continue; 1984 1985 // If the switch has more than 5 blocks, and at least 40% dense, and the 1986 // target supports indirect branches, then emit a jump table rather than 1987 // lowering the switch to a binary tree of conditional branches. 1988 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 1989 continue; 1990 1991 // Emit binary tree. We need to pick a pivot, and push left and right ranges 1992 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 1993 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 1994 } 1995} 1996 1997 1998void SelectionDAGLowering::visitSub(User &I) { 1999 // -0.0 - X --> fneg 2000 const Type *Ty = I.getType(); 2001 if (isa<VectorType>(Ty)) { 2002 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2003 const VectorType *DestTy = cast<VectorType>(I.getType()); 2004 const Type *ElTy = DestTy->getElementType(); 2005 if (ElTy->isFloatingPoint()) { 2006 unsigned VL = DestTy->getNumElements(); 2007 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2008 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2009 if (CV == CNZ) { 2010 SDOperand Op2 = getValue(I.getOperand(1)); 2011 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2012 return; 2013 } 2014 } 2015 } 2016 } 2017 if (Ty->isFloatingPoint()) { 2018 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2019 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2020 SDOperand Op2 = getValue(I.getOperand(1)); 2021 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2022 return; 2023 } 2024 } 2025 2026 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2027} 2028 2029void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2030 SDOperand Op1 = getValue(I.getOperand(0)); 2031 SDOperand Op2 = getValue(I.getOperand(1)); 2032 2033 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2034} 2035 2036void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2037 SDOperand Op1 = getValue(I.getOperand(0)); 2038 SDOperand Op2 = getValue(I.getOperand(1)); 2039 2040 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) < 2041 MVT::getSizeInBits(Op2.getValueType())) 2042 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2043 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 2044 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2045 2046 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2047} 2048 2049void SelectionDAGLowering::visitICmp(User &I) { 2050 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2051 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2052 predicate = IC->getPredicate(); 2053 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2054 predicate = ICmpInst::Predicate(IC->getPredicate()); 2055 SDOperand Op1 = getValue(I.getOperand(0)); 2056 SDOperand Op2 = getValue(I.getOperand(1)); 2057 ISD::CondCode Opcode; 2058 switch (predicate) { 2059 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2060 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2061 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2062 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2063 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2064 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2065 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2066 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2067 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2068 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2069 default: 2070 assert(!"Invalid ICmp predicate value"); 2071 Opcode = ISD::SETEQ; 2072 break; 2073 } 2074 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2075} 2076 2077void SelectionDAGLowering::visitFCmp(User &I) { 2078 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2079 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2080 predicate = FC->getPredicate(); 2081 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2082 predicate = FCmpInst::Predicate(FC->getPredicate()); 2083 SDOperand Op1 = getValue(I.getOperand(0)); 2084 SDOperand Op2 = getValue(I.getOperand(1)); 2085 ISD::CondCode Condition, FOC, FPC; 2086 switch (predicate) { 2087 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2088 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2089 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2090 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2091 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2092 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2093 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2094 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 2095 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 2096 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2097 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2098 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2099 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2100 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2101 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2102 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2103 default: 2104 assert(!"Invalid FCmp predicate value"); 2105 FOC = FPC = ISD::SETFALSE; 2106 break; 2107 } 2108 if (FiniteOnlyFPMath()) 2109 Condition = FOC; 2110 else 2111 Condition = FPC; 2112 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2113} 2114 2115void SelectionDAGLowering::visitSelect(User &I) { 2116 SDOperand Cond = getValue(I.getOperand(0)); 2117 SDOperand TrueVal = getValue(I.getOperand(1)); 2118 SDOperand FalseVal = getValue(I.getOperand(2)); 2119 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2120 TrueVal, FalseVal)); 2121} 2122 2123 2124void SelectionDAGLowering::visitTrunc(User &I) { 2125 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2126 SDOperand N = getValue(I.getOperand(0)); 2127 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2128 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2129} 2130 2131void SelectionDAGLowering::visitZExt(User &I) { 2132 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2133 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2134 SDOperand N = getValue(I.getOperand(0)); 2135 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2136 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2137} 2138 2139void SelectionDAGLowering::visitSExt(User &I) { 2140 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2141 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2142 SDOperand N = getValue(I.getOperand(0)); 2143 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2144 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2145} 2146 2147void SelectionDAGLowering::visitFPTrunc(User &I) { 2148 // FPTrunc is never a no-op cast, no need to check 2149 SDOperand N = getValue(I.getOperand(0)); 2150 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2151 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 2152} 2153 2154void SelectionDAGLowering::visitFPExt(User &I){ 2155 // FPTrunc is never a no-op cast, no need to check 2156 SDOperand N = getValue(I.getOperand(0)); 2157 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2158 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2159} 2160 2161void SelectionDAGLowering::visitFPToUI(User &I) { 2162 // FPToUI is never a no-op cast, no need to check 2163 SDOperand N = getValue(I.getOperand(0)); 2164 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2165 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2166} 2167 2168void SelectionDAGLowering::visitFPToSI(User &I) { 2169 // FPToSI is never a no-op cast, no need to check 2170 SDOperand N = getValue(I.getOperand(0)); 2171 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2172 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2173} 2174 2175void SelectionDAGLowering::visitUIToFP(User &I) { 2176 // UIToFP is never a no-op cast, no need to check 2177 SDOperand N = getValue(I.getOperand(0)); 2178 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2179 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2180} 2181 2182void SelectionDAGLowering::visitSIToFP(User &I){ 2183 // UIToFP is never a no-op cast, no need to check 2184 SDOperand N = getValue(I.getOperand(0)); 2185 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2186 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2187} 2188 2189void SelectionDAGLowering::visitPtrToInt(User &I) { 2190 // What to do depends on the size of the integer and the size of the pointer. 2191 // We can either truncate, zero extend, or no-op, accordingly. 2192 SDOperand N = getValue(I.getOperand(0)); 2193 MVT::ValueType SrcVT = N.getValueType(); 2194 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2195 SDOperand Result; 2196 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2197 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2198 else 2199 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2200 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2201 setValue(&I, Result); 2202} 2203 2204void SelectionDAGLowering::visitIntToPtr(User &I) { 2205 // What to do depends on the size of the integer and the size of the pointer. 2206 // We can either truncate, zero extend, or no-op, accordingly. 2207 SDOperand N = getValue(I.getOperand(0)); 2208 MVT::ValueType SrcVT = N.getValueType(); 2209 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2210 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2211 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2212 else 2213 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2214 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2215} 2216 2217void SelectionDAGLowering::visitBitCast(User &I) { 2218 SDOperand N = getValue(I.getOperand(0)); 2219 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2220 2221 // BitCast assures us that source and destination are the same size so this 2222 // is either a BIT_CONVERT or a no-op. 2223 if (DestVT != N.getValueType()) 2224 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2225 else 2226 setValue(&I, N); // noop cast. 2227} 2228 2229void SelectionDAGLowering::visitInsertElement(User &I) { 2230 SDOperand InVec = getValue(I.getOperand(0)); 2231 SDOperand InVal = getValue(I.getOperand(1)); 2232 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2233 getValue(I.getOperand(2))); 2234 2235 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2236 TLI.getValueType(I.getType()), 2237 InVec, InVal, InIdx)); 2238} 2239 2240void SelectionDAGLowering::visitExtractElement(User &I) { 2241 SDOperand InVec = getValue(I.getOperand(0)); 2242 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2243 getValue(I.getOperand(1))); 2244 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2245 TLI.getValueType(I.getType()), InVec, InIdx)); 2246} 2247 2248void SelectionDAGLowering::visitShuffleVector(User &I) { 2249 SDOperand V1 = getValue(I.getOperand(0)); 2250 SDOperand V2 = getValue(I.getOperand(1)); 2251 SDOperand Mask = getValue(I.getOperand(2)); 2252 2253 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2254 TLI.getValueType(I.getType()), 2255 V1, V2, Mask)); 2256} 2257 2258 2259void SelectionDAGLowering::visitGetElementPtr(User &I) { 2260 SDOperand N = getValue(I.getOperand(0)); 2261 const Type *Ty = I.getOperand(0)->getType(); 2262 2263 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2264 OI != E; ++OI) { 2265 Value *Idx = *OI; 2266 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2267 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2268 if (Field) { 2269 // N = N + Offset 2270 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2271 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2272 getIntPtrConstant(Offset)); 2273 } 2274 Ty = StTy->getElementType(Field); 2275 } else { 2276 Ty = cast<SequentialType>(Ty)->getElementType(); 2277 2278 // If this is a constant subscript, handle it quickly. 2279 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2280 if (CI->getZExtValue() == 0) continue; 2281 uint64_t Offs = 2282 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2283 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 2284 continue; 2285 } 2286 2287 // N = N + Idx * ElementSize; 2288 uint64_t ElementSize = TD->getTypeSize(Ty); 2289 SDOperand IdxN = getValue(Idx); 2290 2291 // If the index is smaller or larger than intptr_t, truncate or extend 2292 // it. 2293 if (IdxN.getValueType() < N.getValueType()) { 2294 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2295 } else if (IdxN.getValueType() > N.getValueType()) 2296 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2297 2298 // If this is a multiply by a power of two, turn it into a shl 2299 // immediately. This is a very common case. 2300 if (isPowerOf2_64(ElementSize)) { 2301 unsigned Amt = Log2_64(ElementSize); 2302 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2303 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2304 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2305 continue; 2306 } 2307 2308 SDOperand Scale = getIntPtrConstant(ElementSize); 2309 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2310 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2311 } 2312 } 2313 setValue(&I, N); 2314} 2315 2316void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2317 // If this is a fixed sized alloca in the entry block of the function, 2318 // allocate it statically on the stack. 2319 if (FuncInfo.StaticAllocaMap.count(&I)) 2320 return; // getValue will auto-populate this. 2321 2322 const Type *Ty = I.getAllocatedType(); 2323 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 2324 unsigned Align = 2325 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2326 I.getAlignment()); 2327 2328 SDOperand AllocSize = getValue(I.getArraySize()); 2329 MVT::ValueType IntPtr = TLI.getPointerTy(); 2330 if (IntPtr < AllocSize.getValueType()) 2331 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2332 else if (IntPtr > AllocSize.getValueType()) 2333 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2334 2335 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2336 getIntPtrConstant(TySize)); 2337 2338 // Handle alignment. If the requested alignment is less than or equal to 2339 // the stack alignment, ignore it. If the size is greater than or equal to 2340 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2341 unsigned StackAlign = 2342 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2343 if (Align <= StackAlign) 2344 Align = 0; 2345 2346 // Round the size of the allocation up to the stack alignment size 2347 // by add SA-1 to the size. 2348 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2349 getIntPtrConstant(StackAlign-1)); 2350 // Mask out the low bits for alignment purposes. 2351 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2352 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2353 2354 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 2355 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2356 MVT::Other); 2357 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2358 setValue(&I, DSA); 2359 DAG.setRoot(DSA.getValue(1)); 2360 2361 // Inform the Frame Information that we have just allocated a variable-sized 2362 // object. 2363 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2364} 2365 2366void SelectionDAGLowering::visitLoad(LoadInst &I) { 2367 SDOperand Ptr = getValue(I.getOperand(0)); 2368 2369 SDOperand Root; 2370 if (I.isVolatile()) 2371 Root = getRoot(); 2372 else { 2373 // Do not serialize non-volatile loads against each other. 2374 Root = DAG.getRoot(); 2375 } 2376 2377 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2378 Root, I.isVolatile(), I.getAlignment())); 2379} 2380 2381SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2382 const Value *SV, SDOperand Root, 2383 bool isVolatile, 2384 unsigned Alignment) { 2385 SDOperand L = 2386 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2387 isVolatile, Alignment); 2388 2389 if (isVolatile) 2390 DAG.setRoot(L.getValue(1)); 2391 else 2392 PendingLoads.push_back(L.getValue(1)); 2393 2394 return L; 2395} 2396 2397 2398void SelectionDAGLowering::visitStore(StoreInst &I) { 2399 Value *SrcV = I.getOperand(0); 2400 SDOperand Src = getValue(SrcV); 2401 SDOperand Ptr = getValue(I.getOperand(1)); 2402 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2403 I.isVolatile(), I.getAlignment())); 2404} 2405 2406/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot 2407/// access memory and has no other side effects at all. 2408static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) { 2409#define GET_NO_MEMORY_INTRINSICS 2410#include "llvm/Intrinsics.gen" 2411#undef GET_NO_MEMORY_INTRINSICS 2412 return false; 2413} 2414 2415// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't 2416// have any side-effects or if it only reads memory. 2417static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) { 2418#define GET_SIDE_EFFECT_INFO 2419#include "llvm/Intrinsics.gen" 2420#undef GET_SIDE_EFFECT_INFO 2421 return false; 2422} 2423 2424/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2425/// node. 2426void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2427 unsigned Intrinsic) { 2428 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic); 2429 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic); 2430 2431 // Build the operand list. 2432 SmallVector<SDOperand, 8> Ops; 2433 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2434 if (OnlyLoad) { 2435 // We don't need to serialize loads against other loads. 2436 Ops.push_back(DAG.getRoot()); 2437 } else { 2438 Ops.push_back(getRoot()); 2439 } 2440 } 2441 2442 // Add the intrinsic ID as an integer operand. 2443 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2444 2445 // Add all operands of the call to the operand list. 2446 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2447 SDOperand Op = getValue(I.getOperand(i)); 2448 assert(TLI.isTypeLegal(Op.getValueType()) && 2449 "Intrinsic uses a non-legal type?"); 2450 Ops.push_back(Op); 2451 } 2452 2453 std::vector<MVT::ValueType> VTs; 2454 if (I.getType() != Type::VoidTy) { 2455 MVT::ValueType VT = TLI.getValueType(I.getType()); 2456 if (MVT::isVector(VT)) { 2457 const VectorType *DestTy = cast<VectorType>(I.getType()); 2458 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2459 2460 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2461 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2462 } 2463 2464 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2465 VTs.push_back(VT); 2466 } 2467 if (HasChain) 2468 VTs.push_back(MVT::Other); 2469 2470 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2471 2472 // Create the node. 2473 SDOperand Result; 2474 if (!HasChain) 2475 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2476 &Ops[0], Ops.size()); 2477 else if (I.getType() != Type::VoidTy) 2478 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2479 &Ops[0], Ops.size()); 2480 else 2481 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2482 &Ops[0], Ops.size()); 2483 2484 if (HasChain) { 2485 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2486 if (OnlyLoad) 2487 PendingLoads.push_back(Chain); 2488 else 2489 DAG.setRoot(Chain); 2490 } 2491 if (I.getType() != Type::VoidTy) { 2492 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2493 MVT::ValueType VT = TLI.getValueType(PTy); 2494 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 2495 } 2496 setValue(&I, Result); 2497 } 2498} 2499 2500/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 2501static GlobalVariable *ExtractTypeInfo (Value *V) { 2502 V = IntrinsicInst::StripPointerCasts(V); 2503 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 2504 assert (GV || isa<ConstantPointerNull>(V) && 2505 "TypeInfo must be a global variable or NULL"); 2506 return GV; 2507} 2508 2509/// addCatchInfo - Extract the personality and type infos from an eh.selector 2510/// call, and add them to the specified machine basic block. 2511static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 2512 MachineBasicBlock *MBB) { 2513 // Inform the MachineModuleInfo of the personality for this landing pad. 2514 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 2515 assert(CE->getOpcode() == Instruction::BitCast && 2516 isa<Function>(CE->getOperand(0)) && 2517 "Personality should be a function"); 2518 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 2519 2520 // Gather all the type infos for this landing pad and pass them along to 2521 // MachineModuleInfo. 2522 std::vector<GlobalVariable *> TyInfo; 2523 unsigned N = I.getNumOperands(); 2524 2525 for (unsigned i = N - 1; i > 2; --i) { 2526 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 2527 unsigned FilterLength = CI->getZExtValue(); 2528 unsigned FirstCatch = i + FilterLength + !FilterLength; 2529 assert (FirstCatch <= N && "Invalid filter length"); 2530 2531 if (FirstCatch < N) { 2532 TyInfo.reserve(N - FirstCatch); 2533 for (unsigned j = FirstCatch; j < N; ++j) 2534 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2535 MMI->addCatchTypeInfo(MBB, TyInfo); 2536 TyInfo.clear(); 2537 } 2538 2539 if (!FilterLength) { 2540 // Cleanup. 2541 MMI->addCleanup(MBB); 2542 } else { 2543 // Filter. 2544 TyInfo.reserve(FilterLength - 1); 2545 for (unsigned j = i + 1; j < FirstCatch; ++j) 2546 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2547 MMI->addFilterTypeInfo(MBB, TyInfo); 2548 TyInfo.clear(); 2549 } 2550 2551 N = i; 2552 } 2553 } 2554 2555 if (N > 3) { 2556 TyInfo.reserve(N - 3); 2557 for (unsigned j = 3; j < N; ++j) 2558 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2559 MMI->addCatchTypeInfo(MBB, TyInfo); 2560 } 2561} 2562 2563/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2564/// we want to emit this as a call to a named external function, return the name 2565/// otherwise lower it and return null. 2566const char * 2567SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2568 switch (Intrinsic) { 2569 default: 2570 // By default, turn this into a target intrinsic node. 2571 visitTargetIntrinsic(I, Intrinsic); 2572 return 0; 2573 case Intrinsic::vastart: visitVAStart(I); return 0; 2574 case Intrinsic::vaend: visitVAEnd(I); return 0; 2575 case Intrinsic::vacopy: visitVACopy(I); return 0; 2576 case Intrinsic::returnaddress: 2577 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2578 getValue(I.getOperand(1)))); 2579 return 0; 2580 case Intrinsic::frameaddress: 2581 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2582 getValue(I.getOperand(1)))); 2583 return 0; 2584 case Intrinsic::setjmp: 2585 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2586 break; 2587 case Intrinsic::longjmp: 2588 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2589 break; 2590 case Intrinsic::memcpy_i32: 2591 case Intrinsic::memcpy_i64: 2592 visitMemIntrinsic(I, ISD::MEMCPY); 2593 return 0; 2594 case Intrinsic::memset_i32: 2595 case Intrinsic::memset_i64: 2596 visitMemIntrinsic(I, ISD::MEMSET); 2597 return 0; 2598 case Intrinsic::memmove_i32: 2599 case Intrinsic::memmove_i64: 2600 visitMemIntrinsic(I, ISD::MEMMOVE); 2601 return 0; 2602 2603 case Intrinsic::dbg_stoppoint: { 2604 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2605 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2606 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2607 SDOperand Ops[5]; 2608 2609 Ops[0] = getRoot(); 2610 Ops[1] = getValue(SPI.getLineValue()); 2611 Ops[2] = getValue(SPI.getColumnValue()); 2612 2613 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2614 assert(DD && "Not a debug information descriptor"); 2615 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2616 2617 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2618 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2619 2620 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2621 } 2622 2623 return 0; 2624 } 2625 case Intrinsic::dbg_region_start: { 2626 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2627 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2628 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2629 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2630 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2631 DAG.getConstant(LabelID, MVT::i32))); 2632 } 2633 2634 return 0; 2635 } 2636 case Intrinsic::dbg_region_end: { 2637 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2638 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2639 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2640 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2641 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2642 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2643 } 2644 2645 return 0; 2646 } 2647 case Intrinsic::dbg_func_start: { 2648 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2649 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2650 if (MMI && FSI.getSubprogram() && 2651 MMI->Verify(FSI.getSubprogram())) { 2652 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram()); 2653 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2654 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2655 } 2656 2657 return 0; 2658 } 2659 case Intrinsic::dbg_declare: { 2660 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2661 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2662 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) { 2663 SDOperand AddressOp = getValue(DI.getAddress()); 2664 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 2665 MMI->RecordVariable(DI.getVariable(), FI->getIndex()); 2666 } 2667 2668 return 0; 2669 } 2670 2671 case Intrinsic::eh_exception: { 2672 if (ExceptionHandling) { 2673 if (!CurMBB->isLandingPad()) { 2674 // FIXME: Mark exception register as live in. Hack for PR1508. 2675 unsigned Reg = TLI.getExceptionAddressRegister(); 2676 if (Reg) CurMBB->addLiveIn(Reg); 2677 } 2678 // Insert the EXCEPTIONADDR instruction. 2679 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2680 SDOperand Ops[1]; 2681 Ops[0] = DAG.getRoot(); 2682 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2683 setValue(&I, Op); 2684 DAG.setRoot(Op.getValue(1)); 2685 } else { 2686 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2687 } 2688 return 0; 2689 } 2690 2691 case Intrinsic::eh_selector_i32: 2692 case Intrinsic::eh_selector_i64: { 2693 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2694 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ? 2695 MVT::i32 : MVT::i64); 2696 2697 if (ExceptionHandling && MMI) { 2698 if (CurMBB->isLandingPad()) 2699 addCatchInfo(I, MMI, CurMBB); 2700 else { 2701#ifndef NDEBUG 2702 FuncInfo.CatchInfoLost.insert(&I); 2703#endif 2704 // FIXME: Mark exception selector register as live in. Hack for PR1508. 2705 unsigned Reg = TLI.getExceptionSelectorRegister(); 2706 if (Reg) CurMBB->addLiveIn(Reg); 2707 } 2708 2709 // Insert the EHSELECTION instruction. 2710 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 2711 SDOperand Ops[2]; 2712 Ops[0] = getValue(I.getOperand(1)); 2713 Ops[1] = getRoot(); 2714 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2715 setValue(&I, Op); 2716 DAG.setRoot(Op.getValue(1)); 2717 } else { 2718 setValue(&I, DAG.getConstant(0, VT)); 2719 } 2720 2721 return 0; 2722 } 2723 2724 case Intrinsic::eh_typeid_for_i32: 2725 case Intrinsic::eh_typeid_for_i64: { 2726 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2727 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? 2728 MVT::i32 : MVT::i64); 2729 2730 if (MMI) { 2731 // Find the type id for the given typeinfo. 2732 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 2733 2734 unsigned TypeID = MMI->getTypeIDFor(GV); 2735 setValue(&I, DAG.getConstant(TypeID, VT)); 2736 } else { 2737 // Return something different to eh_selector. 2738 setValue(&I, DAG.getConstant(1, VT)); 2739 } 2740 2741 return 0; 2742 } 2743 2744 case Intrinsic::eh_return: { 2745 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2746 2747 if (MMI && ExceptionHandling) { 2748 MMI->setCallsEHReturn(true); 2749 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, 2750 MVT::Other, 2751 getRoot(), 2752 getValue(I.getOperand(1)), 2753 getValue(I.getOperand(2)))); 2754 } else { 2755 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2756 } 2757 2758 return 0; 2759 } 2760 2761 case Intrinsic::eh_unwind_init: { 2762 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 2763 MMI->setCallsUnwindInit(true); 2764 } 2765 2766 return 0; 2767 } 2768 2769 case Intrinsic::eh_dwarf_cfa: { 2770 if (ExceptionHandling) { 2771 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType(); 2772 SDOperand CfaArg; 2773 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 2774 CfaArg = DAG.getNode(ISD::TRUNCATE, 2775 TLI.getPointerTy(), getValue(I.getOperand(1))); 2776 else 2777 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, 2778 TLI.getPointerTy(), getValue(I.getOperand(1))); 2779 2780 SDOperand Offset = DAG.getNode(ISD::ADD, 2781 TLI.getPointerTy(), 2782 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, 2783 TLI.getPointerTy()), 2784 CfaArg); 2785 setValue(&I, DAG.getNode(ISD::ADD, 2786 TLI.getPointerTy(), 2787 DAG.getNode(ISD::FRAMEADDR, 2788 TLI.getPointerTy(), 2789 DAG.getConstant(0, 2790 TLI.getPointerTy())), 2791 Offset)); 2792 } else { 2793 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2794 } 2795 2796 return 0; 2797 } 2798 2799 case Intrinsic::sqrt_f32: 2800 case Intrinsic::sqrt_f64: 2801 setValue(&I, DAG.getNode(ISD::FSQRT, 2802 getValue(I.getOperand(1)).getValueType(), 2803 getValue(I.getOperand(1)))); 2804 return 0; 2805 case Intrinsic::powi_f32: 2806 case Intrinsic::powi_f64: 2807 setValue(&I, DAG.getNode(ISD::FPOWI, 2808 getValue(I.getOperand(1)).getValueType(), 2809 getValue(I.getOperand(1)), 2810 getValue(I.getOperand(2)))); 2811 return 0; 2812 case Intrinsic::pcmarker: { 2813 SDOperand Tmp = getValue(I.getOperand(1)); 2814 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2815 return 0; 2816 } 2817 case Intrinsic::readcyclecounter: { 2818 SDOperand Op = getRoot(); 2819 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2820 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2821 &Op, 1); 2822 setValue(&I, Tmp); 2823 DAG.setRoot(Tmp.getValue(1)); 2824 return 0; 2825 } 2826 case Intrinsic::part_select: { 2827 // Currently not implemented: just abort 2828 assert(0 && "part_select intrinsic not implemented"); 2829 abort(); 2830 } 2831 case Intrinsic::part_set: { 2832 // Currently not implemented: just abort 2833 assert(0 && "part_set intrinsic not implemented"); 2834 abort(); 2835 } 2836 case Intrinsic::bswap: 2837 setValue(&I, DAG.getNode(ISD::BSWAP, 2838 getValue(I.getOperand(1)).getValueType(), 2839 getValue(I.getOperand(1)))); 2840 return 0; 2841 case Intrinsic::cttz: { 2842 SDOperand Arg = getValue(I.getOperand(1)); 2843 MVT::ValueType Ty = Arg.getValueType(); 2844 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2845 setValue(&I, result); 2846 return 0; 2847 } 2848 case Intrinsic::ctlz: { 2849 SDOperand Arg = getValue(I.getOperand(1)); 2850 MVT::ValueType Ty = Arg.getValueType(); 2851 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2852 setValue(&I, result); 2853 return 0; 2854 } 2855 case Intrinsic::ctpop: { 2856 SDOperand Arg = getValue(I.getOperand(1)); 2857 MVT::ValueType Ty = Arg.getValueType(); 2858 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2859 setValue(&I, result); 2860 return 0; 2861 } 2862 case Intrinsic::stacksave: { 2863 SDOperand Op = getRoot(); 2864 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2865 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2866 setValue(&I, Tmp); 2867 DAG.setRoot(Tmp.getValue(1)); 2868 return 0; 2869 } 2870 case Intrinsic::stackrestore: { 2871 SDOperand Tmp = getValue(I.getOperand(1)); 2872 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2873 return 0; 2874 } 2875 case Intrinsic::prefetch: 2876 // FIXME: Currently discarding prefetches. 2877 return 0; 2878 2879 case Intrinsic::var_annotation: 2880 // Discard annotate attributes 2881 return 0; 2882 2883 case Intrinsic::init_trampoline: { 2884 const Function *F = 2885 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2))); 2886 2887 SDOperand Ops[6]; 2888 Ops[0] = getRoot(); 2889 Ops[1] = getValue(I.getOperand(1)); 2890 Ops[2] = getValue(I.getOperand(2)); 2891 Ops[3] = getValue(I.getOperand(3)); 2892 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 2893 Ops[5] = DAG.getSrcValue(F); 2894 2895 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE, 2896 DAG.getNodeValueTypes(TLI.getPointerTy(), 2897 MVT::Other), 2, 2898 Ops, 6); 2899 2900 setValue(&I, Tmp); 2901 DAG.setRoot(Tmp.getValue(1)); 2902 return 0; 2903 } 2904 } 2905} 2906 2907 2908void SelectionDAGLowering::LowerCallTo(Instruction &I, 2909 const Type *CalledValueTy, 2910 unsigned CallingConv, 2911 bool IsTailCall, 2912 SDOperand Callee, unsigned OpIdx, 2913 MachineBasicBlock *LandingPad) { 2914 const PointerType *PT = cast<PointerType>(CalledValueTy); 2915 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 2916 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 2917 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2918 unsigned BeginLabel = 0, EndLabel = 0; 2919 2920 TargetLowering::ArgListTy Args; 2921 TargetLowering::ArgListEntry Entry; 2922 Args.reserve(I.getNumOperands()); 2923 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) { 2924 Value *Arg = I.getOperand(i); 2925 SDOperand ArgNode = getValue(Arg); 2926 Entry.Node = ArgNode; Entry.Ty = Arg->getType(); 2927 2928 unsigned attrInd = i - OpIdx + 1; 2929 Entry.isSExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::SExt); 2930 Entry.isZExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ZExt); 2931 Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg); 2932 Entry.isSRet = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet); 2933 Entry.isNest = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::Nest); 2934 Entry.isByVal = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ByVal); 2935 Args.push_back(Entry); 2936 } 2937 2938 if (ExceptionHandling && MMI && LandingPad) { 2939 // Insert a label before the invoke call to mark the try range. This can be 2940 // used to detect deletion of the invoke via the MachineModuleInfo. 2941 BeginLabel = MMI->NextLabelID(); 2942 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2943 DAG.getConstant(BeginLabel, MVT::i32))); 2944 } 2945 2946 std::pair<SDOperand,SDOperand> Result = 2947 TLI.LowerCallTo(getRoot(), I.getType(), 2948 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt), 2949 FTy->isVarArg(), CallingConv, IsTailCall, 2950 Callee, Args, DAG); 2951 if (I.getType() != Type::VoidTy) 2952 setValue(&I, Result.first); 2953 DAG.setRoot(Result.second); 2954 2955 if (ExceptionHandling && MMI && LandingPad) { 2956 // Insert a label at the end of the invoke call to mark the try range. This 2957 // can be used to detect deletion of the invoke via the MachineModuleInfo. 2958 EndLabel = MMI->NextLabelID(); 2959 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2960 DAG.getConstant(EndLabel, MVT::i32))); 2961 2962 // Inform MachineModuleInfo of range. 2963 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 2964 } 2965} 2966 2967 2968void SelectionDAGLowering::visitCall(CallInst &I) { 2969 const char *RenameFn = 0; 2970 if (Function *F = I.getCalledFunction()) { 2971 if (F->isDeclaration()) { 2972 if (unsigned IID = F->getIntrinsicID()) { 2973 RenameFn = visitIntrinsicCall(I, IID); 2974 if (!RenameFn) 2975 return; 2976 } 2977 } 2978 2979 // Check for well-known libc/libm calls. If the function is internal, it 2980 // can't be a library call. 2981 unsigned NameLen = F->getNameLen(); 2982 if (!F->hasInternalLinkage() && NameLen) { 2983 const char *NameStr = F->getNameStart(); 2984 if (NameStr[0] == 'c' && 2985 ((NameLen == 8 && !strcmp(NameStr, "copysign")) || 2986 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) { 2987 if (I.getNumOperands() == 3 && // Basic sanity checks. 2988 I.getOperand(1)->getType()->isFloatingPoint() && 2989 I.getType() == I.getOperand(1)->getType() && 2990 I.getType() == I.getOperand(2)->getType()) { 2991 SDOperand LHS = getValue(I.getOperand(1)); 2992 SDOperand RHS = getValue(I.getOperand(2)); 2993 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 2994 LHS, RHS)); 2995 return; 2996 } 2997 } else if (NameStr[0] == 'f' && 2998 ((NameLen == 4 && !strcmp(NameStr, "fabs")) || 2999 (NameLen == 5 && !strcmp(NameStr, "fabsf")) || 3000 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) { 3001 if (I.getNumOperands() == 2 && // Basic sanity checks. 3002 I.getOperand(1)->getType()->isFloatingPoint() && 3003 I.getType() == I.getOperand(1)->getType()) { 3004 SDOperand Tmp = getValue(I.getOperand(1)); 3005 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 3006 return; 3007 } 3008 } else if (NameStr[0] == 's' && 3009 ((NameLen == 3 && !strcmp(NameStr, "sin")) || 3010 (NameLen == 4 && !strcmp(NameStr, "sinf")) || 3011 (NameLen == 4 && !strcmp(NameStr, "sinl")))) { 3012 if (I.getNumOperands() == 2 && // Basic sanity checks. 3013 I.getOperand(1)->getType()->isFloatingPoint() && 3014 I.getType() == I.getOperand(1)->getType()) { 3015 SDOperand Tmp = getValue(I.getOperand(1)); 3016 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 3017 return; 3018 } 3019 } else if (NameStr[0] == 'c' && 3020 ((NameLen == 3 && !strcmp(NameStr, "cos")) || 3021 (NameLen == 4 && !strcmp(NameStr, "cosf")) || 3022 (NameLen == 4 && !strcmp(NameStr, "cosl")))) { 3023 if (I.getNumOperands() == 2 && // Basic sanity checks. 3024 I.getOperand(1)->getType()->isFloatingPoint() && 3025 I.getType() == I.getOperand(1)->getType()) { 3026 SDOperand Tmp = getValue(I.getOperand(1)); 3027 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 3028 return; 3029 } 3030 } 3031 } 3032 } else if (isa<InlineAsm>(I.getOperand(0))) { 3033 visitInlineAsm(I); 3034 return; 3035 } 3036 3037 SDOperand Callee; 3038 if (!RenameFn) 3039 Callee = getValue(I.getOperand(0)); 3040 else 3041 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 3042 3043 LowerCallTo(I, I.getCalledValue()->getType(), 3044 I.getCallingConv(), 3045 I.isTailCall(), 3046 Callee, 3047 1); 3048} 3049 3050 3051/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 3052/// this value and returns the result as a ValueVT value. This uses 3053/// Chain/Flag as the input and updates them for the output Chain/Flag. 3054/// If the Flag pointer is NULL, no flag is used. 3055SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 3056 SDOperand &Chain, SDOperand *Flag)const{ 3057 // Copy the legal parts from the registers. 3058 unsigned NumParts = Regs.size(); 3059 SmallVector<SDOperand, 8> Parts(NumParts); 3060 for (unsigned i = 0; i != NumParts; ++i) { 3061 SDOperand Part = Flag ? 3062 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) : 3063 DAG.getCopyFromReg(Chain, Regs[i], RegVT); 3064 Chain = Part.getValue(1); 3065 if (Flag) 3066 *Flag = Part.getValue(2); 3067 Parts[i] = Part; 3068 } 3069 3070 // Assemble the legal parts into the final value. 3071 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT); 3072} 3073 3074/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 3075/// specified value into the registers specified by this object. This uses 3076/// Chain/Flag as the input and updates them for the output Chain/Flag. 3077/// If the Flag pointer is NULL, no flag is used. 3078void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 3079 SDOperand &Chain, SDOperand *Flag) const { 3080 // Get the list of the values's legal parts. 3081 unsigned NumParts = Regs.size(); 3082 SmallVector<SDOperand, 8> Parts(NumParts); 3083 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT); 3084 3085 // Copy the parts into the registers. 3086 for (unsigned i = 0; i != NumParts; ++i) { 3087 SDOperand Part = Flag ? 3088 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) : 3089 DAG.getCopyToReg(Chain, Regs[i], Parts[i]); 3090 Chain = Part.getValue(0); 3091 if (Flag) 3092 *Flag = Part.getValue(1); 3093 } 3094} 3095 3096/// AddInlineAsmOperands - Add this value to the specified inlineasm node 3097/// operand list. This adds the code marker and includes the number of 3098/// values added into it. 3099void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 3100 std::vector<SDOperand> &Ops) const { 3101 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3102 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3103 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 3104 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 3105} 3106 3107/// isAllocatableRegister - If the specified register is safe to allocate, 3108/// i.e. it isn't a stack pointer or some other special register, return the 3109/// register class for the register. Otherwise, return null. 3110static const TargetRegisterClass * 3111isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3112 const TargetLowering &TLI, const MRegisterInfo *MRI) { 3113 MVT::ValueType FoundVT = MVT::Other; 3114 const TargetRegisterClass *FoundRC = 0; 3115 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 3116 E = MRI->regclass_end(); RCI != E; ++RCI) { 3117 MVT::ValueType ThisVT = MVT::Other; 3118 3119 const TargetRegisterClass *RC = *RCI; 3120 // If none of the the value types for this register class are valid, we 3121 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3122 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3123 I != E; ++I) { 3124 if (TLI.isTypeLegal(*I)) { 3125 // If we have already found this register in a different register class, 3126 // choose the one with the largest VT specified. For example, on 3127 // PowerPC, we favor f64 register classes over f32. 3128 if (FoundVT == MVT::Other || 3129 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 3130 ThisVT = *I; 3131 break; 3132 } 3133 } 3134 } 3135 3136 if (ThisVT == MVT::Other) continue; 3137 3138 // NOTE: This isn't ideal. In particular, this might allocate the 3139 // frame pointer in functions that need it (due to them not being taken 3140 // out of allocation, because a variable sized allocation hasn't been seen 3141 // yet). This is a slight code pessimization, but should still work. 3142 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3143 E = RC->allocation_order_end(MF); I != E; ++I) 3144 if (*I == Reg) { 3145 // We found a matching register class. Keep looking at others in case 3146 // we find one with larger registers that this physreg is also in. 3147 FoundRC = RC; 3148 FoundVT = ThisVT; 3149 break; 3150 } 3151 } 3152 return FoundRC; 3153} 3154 3155 3156namespace { 3157/// AsmOperandInfo - This contains information for each constraint that we are 3158/// lowering. 3159struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 3160 /// ConstraintCode - This contains the actual string for the code, like "m". 3161 std::string ConstraintCode; 3162 3163 /// ConstraintType - Information about the constraint code, e.g. Register, 3164 /// RegisterClass, Memory, Other, Unknown. 3165 TargetLowering::ConstraintType ConstraintType; 3166 3167 /// CallOperand/CallOperandval - If this is the result output operand or a 3168 /// clobber, this is null, otherwise it is the incoming operand to the 3169 /// CallInst. This gets modified as the asm is processed. 3170 SDOperand CallOperand; 3171 Value *CallOperandVal; 3172 3173 /// ConstraintVT - The ValueType for the operand value. 3174 MVT::ValueType ConstraintVT; 3175 3176 /// AssignedRegs - If this is a register or register class operand, this 3177 /// contains the set of register corresponding to the operand. 3178 RegsForValue AssignedRegs; 3179 3180 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3181 : InlineAsm::ConstraintInfo(info), 3182 ConstraintType(TargetLowering::C_Unknown), 3183 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) { 3184 } 3185 3186 void ComputeConstraintToUse(const TargetLowering &TLI); 3187 3188 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3189 /// busy in OutputRegs/InputRegs. 3190 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3191 std::set<unsigned> &OutputRegs, 3192 std::set<unsigned> &InputRegs) const { 3193 if (isOutReg) 3194 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3195 if (isInReg) 3196 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3197 } 3198}; 3199} // end anon namespace. 3200 3201/// getConstraintGenerality - Return an integer indicating how general CT is. 3202static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3203 switch (CT) { 3204 default: assert(0 && "Unknown constraint type!"); 3205 case TargetLowering::C_Other: 3206 case TargetLowering::C_Unknown: 3207 return 0; 3208 case TargetLowering::C_Register: 3209 return 1; 3210 case TargetLowering::C_RegisterClass: 3211 return 2; 3212 case TargetLowering::C_Memory: 3213 return 3; 3214 } 3215} 3216 3217void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) { 3218 assert(!Codes.empty() && "Must have at least one constraint"); 3219 3220 std::string *Current = &Codes[0]; 3221 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current); 3222 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common. 3223 ConstraintCode = *Current; 3224 ConstraintType = CurType; 3225 return; 3226 } 3227 3228 unsigned CurGenerality = getConstraintGenerality(CurType); 3229 3230 // If we have multiple constraints, try to pick the most general one ahead 3231 // of time. This isn't a wonderful solution, but handles common cases. 3232 for (unsigned j = 1, e = Codes.size(); j != e; ++j) { 3233 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]); 3234 unsigned ThisGenerality = getConstraintGenerality(ThisType); 3235 if (ThisGenerality > CurGenerality) { 3236 // This constraint letter is more general than the previous one, 3237 // use it. 3238 CurType = ThisType; 3239 Current = &Codes[j]; 3240 CurGenerality = ThisGenerality; 3241 } 3242 } 3243 3244 ConstraintCode = *Current; 3245 ConstraintType = CurType; 3246} 3247 3248 3249void SelectionDAGLowering:: 3250GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 3251 std::set<unsigned> &OutputRegs, 3252 std::set<unsigned> &InputRegs) { 3253 // Compute whether this value requires an input register, an output register, 3254 // or both. 3255 bool isOutReg = false; 3256 bool isInReg = false; 3257 switch (OpInfo.Type) { 3258 case InlineAsm::isOutput: 3259 isOutReg = true; 3260 3261 // If this is an early-clobber output, or if there is an input 3262 // constraint that matches this, we need to reserve the input register 3263 // so no other inputs allocate to it. 3264 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3265 break; 3266 case InlineAsm::isInput: 3267 isInReg = true; 3268 isOutReg = false; 3269 break; 3270 case InlineAsm::isClobber: 3271 isOutReg = true; 3272 isInReg = true; 3273 break; 3274 } 3275 3276 3277 MachineFunction &MF = DAG.getMachineFunction(); 3278 std::vector<unsigned> Regs; 3279 3280 // If this is a constraint for a single physreg, or a constraint for a 3281 // register class, find it. 3282 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3283 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3284 OpInfo.ConstraintVT); 3285 3286 unsigned NumRegs = 1; 3287 if (OpInfo.ConstraintVT != MVT::Other) 3288 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3289 MVT::ValueType RegVT; 3290 MVT::ValueType ValueVT = OpInfo.ConstraintVT; 3291 3292 3293 // If this is a constraint for a specific physical register, like {r17}, 3294 // assign it now. 3295 if (PhysReg.first) { 3296 if (OpInfo.ConstraintVT == MVT::Other) 3297 ValueVT = *PhysReg.second->vt_begin(); 3298 3299 // Get the actual register value type. This is important, because the user 3300 // may have asked for (e.g.) the AX register in i32 type. We need to 3301 // remember that AX is actually i16 to get the right extension. 3302 RegVT = *PhysReg.second->vt_begin(); 3303 3304 // This is a explicit reference to a physical register. 3305 Regs.push_back(PhysReg.first); 3306 3307 // If this is an expanded reference, add the rest of the regs to Regs. 3308 if (NumRegs != 1) { 3309 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3310 TargetRegisterClass::iterator E = PhysReg.second->end(); 3311 for (; *I != PhysReg.first; ++I) 3312 assert(I != E && "Didn't find reg!"); 3313 3314 // Already added the first reg. 3315 --NumRegs; ++I; 3316 for (; NumRegs; --NumRegs, ++I) { 3317 assert(I != E && "Ran out of registers to allocate!"); 3318 Regs.push_back(*I); 3319 } 3320 } 3321 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3322 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3323 return; 3324 } 3325 3326 // Otherwise, if this was a reference to an LLVM register class, create vregs 3327 // for this reference. 3328 std::vector<unsigned> RegClassRegs; 3329 const TargetRegisterClass *RC = PhysReg.second; 3330 if (RC) { 3331 // If this is an early clobber or tied register, our regalloc doesn't know 3332 // how to maintain the constraint. If it isn't, go ahead and create vreg 3333 // and let the regalloc do the right thing. 3334 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 3335 // If there is some other early clobber and this is an input register, 3336 // then we are forced to pre-allocate the input reg so it doesn't 3337 // conflict with the earlyclobber. 3338 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 3339 RegVT = *PhysReg.second->vt_begin(); 3340 3341 if (OpInfo.ConstraintVT == MVT::Other) 3342 ValueVT = RegVT; 3343 3344 // Create the appropriate number of virtual registers. 3345 SSARegMap *RegMap = MF.getSSARegMap(); 3346 for (; NumRegs; --NumRegs) 3347 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second)); 3348 3349 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3350 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3351 return; 3352 } 3353 3354 // Otherwise, we can't allocate it. Let the code below figure out how to 3355 // maintain these constraints. 3356 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3357 3358 } else { 3359 // This is a reference to a register class that doesn't directly correspond 3360 // to an LLVM register class. Allocate NumRegs consecutive, available, 3361 // registers from the class. 3362 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3363 OpInfo.ConstraintVT); 3364 } 3365 3366 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 3367 unsigned NumAllocated = 0; 3368 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3369 unsigned Reg = RegClassRegs[i]; 3370 // See if this register is available. 3371 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3372 (isInReg && InputRegs.count(Reg))) { // Already used. 3373 // Make sure we find consecutive registers. 3374 NumAllocated = 0; 3375 continue; 3376 } 3377 3378 // Check to see if this register is allocatable (i.e. don't give out the 3379 // stack pointer). 3380 if (RC == 0) { 3381 RC = isAllocatableRegister(Reg, MF, TLI, MRI); 3382 if (!RC) { // Couldn't allocate this register. 3383 // Reset NumAllocated to make sure we return consecutive registers. 3384 NumAllocated = 0; 3385 continue; 3386 } 3387 } 3388 3389 // Okay, this register is good, we can use it. 3390 ++NumAllocated; 3391 3392 // If we allocated enough consecutive registers, succeed. 3393 if (NumAllocated == NumRegs) { 3394 unsigned RegStart = (i-NumAllocated)+1; 3395 unsigned RegEnd = i+1; 3396 // Mark all of the allocated registers used. 3397 for (unsigned i = RegStart; i != RegEnd; ++i) 3398 Regs.push_back(RegClassRegs[i]); 3399 3400 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 3401 OpInfo.ConstraintVT); 3402 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3403 return; 3404 } 3405 } 3406 3407 // Otherwise, we couldn't allocate enough registers for this. 3408 return; 3409} 3410 3411 3412/// visitInlineAsm - Handle a call to an InlineAsm object. 3413/// 3414void SelectionDAGLowering::visitInlineAsm(CallInst &I) { 3415 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0)); 3416 3417 /// ConstraintOperands - Information about all of the constraints. 3418 std::vector<AsmOperandInfo> ConstraintOperands; 3419 3420 SDOperand Chain = getRoot(); 3421 SDOperand Flag; 3422 3423 std::set<unsigned> OutputRegs, InputRegs; 3424 3425 // Do a prepass over the constraints, canonicalizing them, and building up the 3426 // ConstraintOperands list. 3427 std::vector<InlineAsm::ConstraintInfo> 3428 ConstraintInfos = IA->ParseConstraints(); 3429 3430 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 3431 // constraint. If so, we can't let the register allocator allocate any input 3432 // registers, because it will not know to avoid the earlyclobbered output reg. 3433 bool SawEarlyClobber = false; 3434 3435 unsigned OpNo = 1; // OpNo - The operand of the CallInst. 3436 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3437 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 3438 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 3439 3440 MVT::ValueType OpVT = MVT::Other; 3441 3442 // Compute the value type for each operand. 3443 switch (OpInfo.Type) { 3444 case InlineAsm::isOutput: 3445 if (!OpInfo.isIndirect) { 3446 // The return value of the call is this value. As such, there is no 3447 // corresponding argument. 3448 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3449 OpVT = TLI.getValueType(I.getType()); 3450 } else { 3451 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3452 } 3453 break; 3454 case InlineAsm::isInput: 3455 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3456 break; 3457 case InlineAsm::isClobber: 3458 // Nothing to do. 3459 break; 3460 } 3461 3462 // If this is an input or an indirect output, process the call argument. 3463 if (OpInfo.CallOperandVal) { 3464 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 3465 const Type *OpTy = OpInfo.CallOperandVal->getType(); 3466 // If this is an indirect operand, the operand is a pointer to the 3467 // accessed type. 3468 if (OpInfo.isIndirect) 3469 OpTy = cast<PointerType>(OpTy)->getElementType(); 3470 3471 // If OpTy is not a first-class value, it may be a struct/union that we 3472 // can tile with integers. 3473 if (!OpTy->isFirstClassType() && OpTy->isSized()) { 3474 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3475 switch (BitSize) { 3476 default: break; 3477 case 1: 3478 case 8: 3479 case 16: 3480 case 32: 3481 case 64: 3482 OpTy = IntegerType::get(BitSize); 3483 break; 3484 } 3485 } 3486 3487 OpVT = TLI.getValueType(OpTy, true); 3488 } 3489 3490 OpInfo.ConstraintVT = OpVT; 3491 3492 // Compute the constraint code and ConstraintType to use. 3493 OpInfo.ComputeConstraintToUse(TLI); 3494 3495 // Keep track of whether we see an earlyclobber. 3496 SawEarlyClobber |= OpInfo.isEarlyClobber; 3497 3498 // If this is a memory input, and if the operand is not indirect, do what we 3499 // need to to provide an address for the memory input. 3500 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 3501 !OpInfo.isIndirect) { 3502 assert(OpInfo.Type == InlineAsm::isInput && 3503 "Can only indirectify direct input operands!"); 3504 3505 // Memory operands really want the address of the value. If we don't have 3506 // an indirect input, put it in the constpool if we can, otherwise spill 3507 // it to a stack slot. 3508 3509 // If the operand is a float, integer, or vector constant, spill to a 3510 // constant pool entry to get its address. 3511 Value *OpVal = OpInfo.CallOperandVal; 3512 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 3513 isa<ConstantVector>(OpVal)) { 3514 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 3515 TLI.getPointerTy()); 3516 } else { 3517 // Otherwise, create a stack slot and emit a store to it before the 3518 // asm. 3519 const Type *Ty = OpVal->getType(); 3520 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3521 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3522 MachineFunction &MF = DAG.getMachineFunction(); 3523 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3524 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3525 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 3526 OpInfo.CallOperand = StackSlot; 3527 } 3528 3529 // There is no longer a Value* corresponding to this operand. 3530 OpInfo.CallOperandVal = 0; 3531 // It is now an indirect operand. 3532 OpInfo.isIndirect = true; 3533 } 3534 3535 // If this constraint is for a specific register, allocate it before 3536 // anything else. 3537 if (OpInfo.ConstraintType == TargetLowering::C_Register) 3538 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3539 } 3540 ConstraintInfos.clear(); 3541 3542 3543 // Second pass - Loop over all of the operands, assigning virtual or physregs 3544 // to registerclass operands. 3545 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3546 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3547 3548 // C_Register operands have already been allocated, Other/Memory don't need 3549 // to be. 3550 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 3551 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3552 } 3553 3554 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 3555 std::vector<SDOperand> AsmNodeOperands; 3556 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3557 AsmNodeOperands.push_back( 3558 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 3559 3560 3561 // Loop over all of the inputs, copying the operand values into the 3562 // appropriate registers and processing the output regs. 3563 RegsForValue RetValRegs; 3564 3565 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 3566 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3567 3568 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3569 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3570 3571 switch (OpInfo.Type) { 3572 case InlineAsm::isOutput: { 3573 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 3574 OpInfo.ConstraintType != TargetLowering::C_Register) { 3575 // Memory output, or 'other' output (e.g. 'X' constraint). 3576 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 3577 3578 // Add information to the INLINEASM node to know about this output. 3579 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3580 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3581 TLI.getPointerTy())); 3582 AsmNodeOperands.push_back(OpInfo.CallOperand); 3583 break; 3584 } 3585 3586 // Otherwise, this is a register or register class output. 3587 3588 // Copy the output from the appropriate register. Find a register that 3589 // we can use. 3590 if (OpInfo.AssignedRegs.Regs.empty()) { 3591 cerr << "Couldn't allocate output reg for contraint '" 3592 << OpInfo.ConstraintCode << "'!\n"; 3593 exit(1); 3594 } 3595 3596 if (!OpInfo.isIndirect) { 3597 // This is the result value of the call. 3598 assert(RetValRegs.Regs.empty() && 3599 "Cannot have multiple output constraints yet!"); 3600 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3601 RetValRegs = OpInfo.AssignedRegs; 3602 } else { 3603 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 3604 OpInfo.CallOperandVal)); 3605 } 3606 3607 // Add information to the INLINEASM node to know that this register is 3608 // set. 3609 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 3610 AsmNodeOperands); 3611 break; 3612 } 3613 case InlineAsm::isInput: { 3614 SDOperand InOperandVal = OpInfo.CallOperand; 3615 3616 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 3617 // If this is required to match an output register we have already set, 3618 // just use its register. 3619 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 3620 3621 // Scan until we find the definition we already emitted of this operand. 3622 // When we find it, create a RegsForValue operand. 3623 unsigned CurOp = 2; // The first operand. 3624 for (; OperandNo; --OperandNo) { 3625 // Advance to the next operand. 3626 unsigned NumOps = 3627 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3628 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3629 (NumOps & 7) == 4 /*MEM*/) && 3630 "Skipped past definitions?"); 3631 CurOp += (NumOps>>3)+1; 3632 } 3633 3634 unsigned NumOps = 3635 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3636 if ((NumOps & 7) == 2 /*REGDEF*/) { 3637 // Add NumOps>>3 registers to MatchedRegs. 3638 RegsForValue MatchedRegs; 3639 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3640 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3641 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3642 unsigned Reg = 3643 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3644 MatchedRegs.Regs.push_back(Reg); 3645 } 3646 3647 // Use the produced MatchedRegs object to 3648 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3649 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3650 break; 3651 } else { 3652 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3653 assert(0 && "matching constraints for memory operands unimp"); 3654 } 3655 } 3656 3657 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 3658 assert(!OpInfo.isIndirect && 3659 "Don't know how to handle indirect other inputs yet!"); 3660 3661 std::vector<SDOperand> Ops; 3662 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 3663 Ops, DAG); 3664 if (Ops.empty()) { 3665 cerr << "Invalid operand for inline asm constraint '" 3666 << OpInfo.ConstraintCode << "'!\n"; 3667 exit(1); 3668 } 3669 3670 // Add information to the INLINEASM node to know about this input. 3671 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 3672 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3673 TLI.getPointerTy())); 3674 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 3675 break; 3676 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 3677 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 3678 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 3679 "Memory operands expect pointer values"); 3680 3681 // Add information to the INLINEASM node to know about this input. 3682 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3683 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3684 TLI.getPointerTy())); 3685 AsmNodeOperands.push_back(InOperandVal); 3686 break; 3687 } 3688 3689 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 3690 OpInfo.ConstraintType == TargetLowering::C_Register) && 3691 "Unknown constraint type!"); 3692 assert(!OpInfo.isIndirect && 3693 "Don't know how to handle indirect register inputs yet!"); 3694 3695 // Copy the input into the appropriate registers. 3696 assert(!OpInfo.AssignedRegs.Regs.empty() && 3697 "Couldn't allocate input reg!"); 3698 3699 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3700 3701 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 3702 AsmNodeOperands); 3703 break; 3704 } 3705 case InlineAsm::isClobber: { 3706 // Add the clobbered value to the operand list, so that the register 3707 // allocator is aware that the physreg got clobbered. 3708 if (!OpInfo.AssignedRegs.Regs.empty()) 3709 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 3710 AsmNodeOperands); 3711 break; 3712 } 3713 } 3714 } 3715 3716 // Finish up input operands. 3717 AsmNodeOperands[0] = Chain; 3718 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3719 3720 Chain = DAG.getNode(ISD::INLINEASM, 3721 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3722 &AsmNodeOperands[0], AsmNodeOperands.size()); 3723 Flag = Chain.getValue(1); 3724 3725 // If this asm returns a register value, copy the result from that register 3726 // and set it as the value of the call. 3727 if (!RetValRegs.Regs.empty()) { 3728 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 3729 3730 // If the result of the inline asm is a vector, it may have the wrong 3731 // width/num elts. Make sure to convert it to the right type with 3732 // bit_convert. 3733 if (MVT::isVector(Val.getValueType())) { 3734 const VectorType *VTy = cast<VectorType>(I.getType()); 3735 MVT::ValueType DesiredVT = TLI.getValueType(VTy); 3736 3737 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val); 3738 } 3739 3740 setValue(&I, Val); 3741 } 3742 3743 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 3744 3745 // Process indirect outputs, first output all of the flagged copies out of 3746 // physregs. 3747 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 3748 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 3749 Value *Ptr = IndirectStoresToEmit[i].second; 3750 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 3751 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 3752 } 3753 3754 // Emit the non-flagged stores from the physregs. 3755 SmallVector<SDOperand, 8> OutChains; 3756 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 3757 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 3758 getValue(StoresToEmit[i].second), 3759 StoresToEmit[i].second, 0)); 3760 if (!OutChains.empty()) 3761 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3762 &OutChains[0], OutChains.size()); 3763 DAG.setRoot(Chain); 3764} 3765 3766 3767void SelectionDAGLowering::visitMalloc(MallocInst &I) { 3768 SDOperand Src = getValue(I.getOperand(0)); 3769 3770 MVT::ValueType IntPtr = TLI.getPointerTy(); 3771 3772 if (IntPtr < Src.getValueType()) 3773 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 3774 else if (IntPtr > Src.getValueType()) 3775 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 3776 3777 // Scale the source by the type size. 3778 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType()); 3779 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 3780 Src, getIntPtrConstant(ElementSize)); 3781 3782 TargetLowering::ArgListTy Args; 3783 TargetLowering::ArgListEntry Entry; 3784 Entry.Node = Src; 3785 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3786 Args.push_back(Entry); 3787 3788 std::pair<SDOperand,SDOperand> Result = 3789 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true, 3790 DAG.getExternalSymbol("malloc", IntPtr), 3791 Args, DAG); 3792 setValue(&I, Result.first); // Pointers always fit in registers 3793 DAG.setRoot(Result.second); 3794} 3795 3796void SelectionDAGLowering::visitFree(FreeInst &I) { 3797 TargetLowering::ArgListTy Args; 3798 TargetLowering::ArgListEntry Entry; 3799 Entry.Node = getValue(I.getOperand(0)); 3800 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3801 Args.push_back(Entry); 3802 MVT::ValueType IntPtr = TLI.getPointerTy(); 3803 std::pair<SDOperand,SDOperand> Result = 3804 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true, 3805 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 3806 DAG.setRoot(Result.second); 3807} 3808 3809// InsertAtEndOfBasicBlock - This method should be implemented by targets that 3810// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 3811// instructions are special in various ways, which require special support to 3812// insert. The specified MachineInstr is created but not inserted into any 3813// basic blocks, and the scheduler passes ownership of it to this method. 3814MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3815 MachineBasicBlock *MBB) { 3816 cerr << "If a target marks an instruction with " 3817 << "'usesCustomDAGSchedInserter', it must implement " 3818 << "TargetLowering::InsertAtEndOfBasicBlock!\n"; 3819 abort(); 3820 return 0; 3821} 3822 3823void SelectionDAGLowering::visitVAStart(CallInst &I) { 3824 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 3825 getValue(I.getOperand(1)), 3826 DAG.getSrcValue(I.getOperand(1)))); 3827} 3828 3829void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 3830 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 3831 getValue(I.getOperand(0)), 3832 DAG.getSrcValue(I.getOperand(0))); 3833 setValue(&I, V); 3834 DAG.setRoot(V.getValue(1)); 3835} 3836 3837void SelectionDAGLowering::visitVAEnd(CallInst &I) { 3838 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 3839 getValue(I.getOperand(1)), 3840 DAG.getSrcValue(I.getOperand(1)))); 3841} 3842 3843void SelectionDAGLowering::visitVACopy(CallInst &I) { 3844 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 3845 getValue(I.getOperand(1)), 3846 getValue(I.getOperand(2)), 3847 DAG.getSrcValue(I.getOperand(1)), 3848 DAG.getSrcValue(I.getOperand(2)))); 3849} 3850 3851/// TargetLowering::LowerArguments - This is the default LowerArguments 3852/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 3853/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 3854/// integrated into SDISel. 3855std::vector<SDOperand> 3856TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 3857 const FunctionType *FTy = F.getFunctionType(); 3858 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 3859 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 3860 std::vector<SDOperand> Ops; 3861 Ops.push_back(DAG.getRoot()); 3862 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 3863 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 3864 3865 // Add one result value for each formal argument. 3866 std::vector<MVT::ValueType> RetVals; 3867 unsigned j = 1; 3868 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 3869 I != E; ++I, ++j) { 3870 MVT::ValueType VT = getValueType(I->getType()); 3871 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3872 unsigned OriginalAlignment = 3873 getTargetData()->getABITypeAlignment(I->getType()); 3874 3875 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 3876 // that is zero extended! 3877 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt)) 3878 Flags &= ~(ISD::ParamFlags::SExt); 3879 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt)) 3880 Flags |= ISD::ParamFlags::SExt; 3881 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg)) 3882 Flags |= ISD::ParamFlags::InReg; 3883 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet)) 3884 Flags |= ISD::ParamFlags::StructReturn; 3885 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ByVal)) { 3886 Flags |= ISD::ParamFlags::ByVal; 3887 const PointerType *Ty = cast<PointerType>(I->getType()); 3888 const StructType *STy = cast<StructType>(Ty->getElementType()); 3889 unsigned StructAlign = 3890 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy)); 3891 unsigned StructSize = getTargetData()->getTypeSize(STy); 3892 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs); 3893 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs); 3894 } 3895 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::Nest)) 3896 Flags |= ISD::ParamFlags::Nest; 3897 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs); 3898 3899 switch (getTypeAction(VT)) { 3900 default: assert(0 && "Unknown type action!"); 3901 case Legal: 3902 RetVals.push_back(VT); 3903 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3904 break; 3905 case Promote: 3906 RetVals.push_back(getTypeToTransformTo(VT)); 3907 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3908 break; 3909 case Expand: { 3910 // If this is an illegal type, it needs to be broken up to fit into 3911 // registers. 3912 MVT::ValueType RegisterVT = getRegisterType(VT); 3913 unsigned NumRegs = getNumRegisters(VT); 3914 for (unsigned i = 0; i != NumRegs; ++i) { 3915 RetVals.push_back(RegisterVT); 3916 // if it isn't first piece, alignment must be 1 3917 if (i > 0) 3918 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3919 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3920 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3921 } 3922 break; 3923 } 3924 } 3925 } 3926 3927 RetVals.push_back(MVT::Other); 3928 3929 // Create the node. 3930 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 3931 DAG.getNodeValueTypes(RetVals), RetVals.size(), 3932 &Ops[0], Ops.size()).Val; 3933 unsigned NumArgRegs = Result->getNumValues() - 1; 3934 DAG.setRoot(SDOperand(Result, NumArgRegs)); 3935 3936 // Set up the return result vector. 3937 Ops.clear(); 3938 unsigned i = 0; 3939 unsigned Idx = 1; 3940 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 3941 ++I, ++Idx) { 3942 MVT::ValueType VT = getValueType(I->getType()); 3943 3944 switch (getTypeAction(VT)) { 3945 default: assert(0 && "Unknown type action!"); 3946 case Legal: 3947 Ops.push_back(SDOperand(Result, i++)); 3948 break; 3949 case Promote: { 3950 SDOperand Op(Result, i++); 3951 if (MVT::isInteger(VT)) { 3952 if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt)) 3953 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, 3954 DAG.getValueType(VT)); 3955 else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt)) 3956 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, 3957 DAG.getValueType(VT)); 3958 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3959 } else { 3960 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3961 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 3962 } 3963 Ops.push_back(Op); 3964 break; 3965 } 3966 case Expand: { 3967 MVT::ValueType PartVT = getRegisterType(VT); 3968 unsigned NumParts = getNumRegisters(VT); 3969 SmallVector<SDOperand, 4> Parts(NumParts); 3970 for (unsigned j = 0; j != NumParts; ++j) 3971 Parts[j] = SDOperand(Result, i++); 3972 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT)); 3973 break; 3974 } 3975 } 3976 } 3977 assert(i == NumArgRegs && "Argument register count mismatch!"); 3978 return Ops; 3979} 3980 3981 3982/// TargetLowering::LowerCallTo - This is the default LowerCallTo 3983/// implementation, which just inserts an ISD::CALL node, which is later custom 3984/// lowered by the target to something concrete. FIXME: When all targets are 3985/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 3986std::pair<SDOperand, SDOperand> 3987TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 3988 bool RetTyIsSigned, bool isVarArg, 3989 unsigned CallingConv, bool isTailCall, 3990 SDOperand Callee, 3991 ArgListTy &Args, SelectionDAG &DAG) { 3992 SmallVector<SDOperand, 32> Ops; 3993 Ops.push_back(Chain); // Op#0 - Chain 3994 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 3995 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 3996 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 3997 Ops.push_back(Callee); 3998 3999 // Handle all of the outgoing arguments. 4000 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 4001 MVT::ValueType VT = getValueType(Args[i].Ty); 4002 SDOperand Op = Args[i].Node; 4003 unsigned Flags = ISD::ParamFlags::NoFlagSet; 4004 unsigned OriginalAlignment = 4005 getTargetData()->getABITypeAlignment(Args[i].Ty); 4006 4007 if (Args[i].isSExt) 4008 Flags |= ISD::ParamFlags::SExt; 4009 if (Args[i].isZExt) 4010 Flags |= ISD::ParamFlags::ZExt; 4011 if (Args[i].isInReg) 4012 Flags |= ISD::ParamFlags::InReg; 4013 if (Args[i].isSRet) 4014 Flags |= ISD::ParamFlags::StructReturn; 4015 if (Args[i].isByVal) { 4016 Flags |= ISD::ParamFlags::ByVal; 4017 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 4018 const StructType *STy = cast<StructType>(Ty->getElementType()); 4019 unsigned StructAlign = 4020 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy)); 4021 unsigned StructSize = getTargetData()->getTypeSize(STy); 4022 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs); 4023 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs); 4024 } 4025 if (Args[i].isNest) 4026 Flags |= ISD::ParamFlags::Nest; 4027 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs; 4028 4029 switch (getTypeAction(VT)) { 4030 default: assert(0 && "Unknown type action!"); 4031 case Legal: 4032 Ops.push_back(Op); 4033 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4034 break; 4035 case Promote: 4036 if (MVT::isInteger(VT)) { 4037 unsigned ExtOp; 4038 if (Args[i].isSExt) 4039 ExtOp = ISD::SIGN_EXTEND; 4040 else if (Args[i].isZExt) 4041 ExtOp = ISD::ZERO_EXTEND; 4042 else 4043 ExtOp = ISD::ANY_EXTEND; 4044 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 4045 } else { 4046 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 4047 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 4048 } 4049 Ops.push_back(Op); 4050 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4051 break; 4052 case Expand: { 4053 MVT::ValueType PartVT = getRegisterType(VT); 4054 unsigned NumParts = getNumRegisters(VT); 4055 SmallVector<SDOperand, 4> Parts(NumParts); 4056 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT); 4057 for (unsigned i = 0; i != NumParts; ++i) { 4058 // if it isn't first piece, alignment must be 1 4059 unsigned MyFlags = Flags; 4060 if (i != 0) 4061 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) | 4062 (1 << ISD::ParamFlags::OrigAlignmentOffs); 4063 4064 Ops.push_back(Parts[i]); 4065 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32)); 4066 } 4067 break; 4068 } 4069 } 4070 } 4071 4072 // Figure out the result value types. 4073 MVT::ValueType VT = getValueType(RetTy); 4074 MVT::ValueType RegisterVT = getRegisterType(VT); 4075 unsigned NumRegs = getNumRegisters(VT); 4076 SmallVector<MVT::ValueType, 4> RetTys(NumRegs); 4077 for (unsigned i = 0; i != NumRegs; ++i) 4078 RetTys[i] = RegisterVT; 4079 4080 RetTys.push_back(MVT::Other); // Always has a chain. 4081 4082 // Create the CALL node. 4083 SDOperand Res = DAG.getNode(ISD::CALL, 4084 DAG.getVTList(&RetTys[0], NumRegs + 1), 4085 &Ops[0], Ops.size()); 4086 Chain = Res.getValue(NumRegs); 4087 4088 // Gather up the call result into a single value. 4089 if (RetTy != Type::VoidTy) { 4090 ISD::NodeType AssertOp = ISD::AssertSext; 4091 if (!RetTyIsSigned) 4092 AssertOp = ISD::AssertZext; 4093 SmallVector<SDOperand, 4> Results(NumRegs); 4094 for (unsigned i = 0; i != NumRegs; ++i) 4095 Results[i] = Res.getValue(i); 4096 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp); 4097 } 4098 4099 return std::make_pair(Res, Chain); 4100} 4101 4102SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4103 assert(0 && "LowerOperation not implemented for this target!"); 4104 abort(); 4105 return SDOperand(); 4106} 4107 4108SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 4109 SelectionDAG &DAG) { 4110 assert(0 && "CustomPromoteOperation not implemented for this target!"); 4111 abort(); 4112 return SDOperand(); 4113} 4114 4115/// getMemsetValue - Vectorized representation of the memset value 4116/// operand. 4117static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 4118 SelectionDAG &DAG) { 4119 MVT::ValueType CurVT = VT; 4120 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 4121 uint64_t Val = C->getValue() & 255; 4122 unsigned Shift = 8; 4123 while (CurVT != MVT::i8) { 4124 Val = (Val << Shift) | Val; 4125 Shift <<= 1; 4126 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4127 } 4128 return DAG.getConstant(Val, VT); 4129 } else { 4130 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4131 unsigned Shift = 8; 4132 while (CurVT != MVT::i8) { 4133 Value = 4134 DAG.getNode(ISD::OR, VT, 4135 DAG.getNode(ISD::SHL, VT, Value, 4136 DAG.getConstant(Shift, MVT::i8)), Value); 4137 Shift <<= 1; 4138 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4139 } 4140 4141 return Value; 4142 } 4143} 4144 4145/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4146/// used when a memcpy is turned into a memset when the source is a constant 4147/// string ptr. 4148static SDOperand getMemsetStringVal(MVT::ValueType VT, 4149 SelectionDAG &DAG, TargetLowering &TLI, 4150 std::string &Str, unsigned Offset) { 4151 uint64_t Val = 0; 4152 unsigned MSB = MVT::getSizeInBits(VT) / 8; 4153 if (TLI.isLittleEndian()) 4154 Offset = Offset + MSB - 1; 4155 for (unsigned i = 0; i != MSB; ++i) { 4156 Val = (Val << 8) | (unsigned char)Str[Offset]; 4157 Offset += TLI.isLittleEndian() ? -1 : 1; 4158 } 4159 return DAG.getConstant(Val, VT); 4160} 4161 4162/// getMemBasePlusOffset - Returns base and offset node for the 4163static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4164 SelectionDAG &DAG, TargetLowering &TLI) { 4165 MVT::ValueType VT = Base.getValueType(); 4166 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4167} 4168 4169/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4170/// to replace the memset / memcpy is below the threshold. It also returns the 4171/// types of the sequence of memory ops to perform memset / memcpy. 4172static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4173 unsigned Limit, uint64_t Size, 4174 unsigned Align, TargetLowering &TLI) { 4175 MVT::ValueType VT; 4176 4177 if (TLI.allowsUnalignedMemoryAccesses()) { 4178 VT = MVT::i64; 4179 } else { 4180 switch (Align & 7) { 4181 case 0: 4182 VT = MVT::i64; 4183 break; 4184 case 4: 4185 VT = MVT::i32; 4186 break; 4187 case 2: 4188 VT = MVT::i16; 4189 break; 4190 default: 4191 VT = MVT::i8; 4192 break; 4193 } 4194 } 4195 4196 MVT::ValueType LVT = MVT::i64; 4197 while (!TLI.isTypeLegal(LVT)) 4198 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4199 assert(MVT::isInteger(LVT)); 4200 4201 if (VT > LVT) 4202 VT = LVT; 4203 4204 unsigned NumMemOps = 0; 4205 while (Size != 0) { 4206 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4207 while (VTSize > Size) { 4208 VT = (MVT::ValueType)((unsigned)VT - 1); 4209 VTSize >>= 1; 4210 } 4211 assert(MVT::isInteger(VT)); 4212 4213 if (++NumMemOps > Limit) 4214 return false; 4215 MemOps.push_back(VT); 4216 Size -= VTSize; 4217 } 4218 4219 return true; 4220} 4221 4222void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4223 SDOperand Op1 = getValue(I.getOperand(1)); 4224 SDOperand Op2 = getValue(I.getOperand(2)); 4225 SDOperand Op3 = getValue(I.getOperand(3)); 4226 SDOperand Op4 = getValue(I.getOperand(4)); 4227 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4228 if (Align == 0) Align = 1; 4229 4230 // If the source and destination are known to not be aliases, we can 4231 // lower memmove as memcpy. 4232 if (Op == ISD::MEMMOVE) { 4233 uint64_t Size = -1ULL; 4234 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 4235 Size = C->getValue(); 4236 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) == 4237 AliasAnalysis::NoAlias) 4238 Op = ISD::MEMCPY; 4239 } 4240 4241 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4242 std::vector<MVT::ValueType> MemOps; 4243 4244 // Expand memset / memcpy to a series of load / store ops 4245 // if the size operand falls below a certain threshold. 4246 SmallVector<SDOperand, 8> OutChains; 4247 switch (Op) { 4248 default: break; // Do nothing for now. 4249 case ISD::MEMSET: { 4250 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4251 Size->getValue(), Align, TLI)) { 4252 unsigned NumMemOps = MemOps.size(); 4253 unsigned Offset = 0; 4254 for (unsigned i = 0; i < NumMemOps; i++) { 4255 MVT::ValueType VT = MemOps[i]; 4256 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4257 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4258 SDOperand Store = DAG.getStore(getRoot(), Value, 4259 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4260 I.getOperand(1), Offset); 4261 OutChains.push_back(Store); 4262 Offset += VTSize; 4263 } 4264 } 4265 break; 4266 } 4267 case ISD::MEMCPY: { 4268 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4269 Size->getValue(), Align, TLI)) { 4270 unsigned NumMemOps = MemOps.size(); 4271 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4272 GlobalAddressSDNode *G = NULL; 4273 std::string Str; 4274 bool CopyFromStr = false; 4275 4276 if (Op2.getOpcode() == ISD::GlobalAddress) 4277 G = cast<GlobalAddressSDNode>(Op2); 4278 else if (Op2.getOpcode() == ISD::ADD && 4279 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4280 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4281 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4282 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4283 } 4284 if (G) { 4285 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4286 if (GV && GV->isConstant()) { 4287 Str = GV->getStringValue(false); 4288 if (!Str.empty()) { 4289 CopyFromStr = true; 4290 SrcOff += SrcDelta; 4291 } 4292 } 4293 } 4294 4295 for (unsigned i = 0; i < NumMemOps; i++) { 4296 MVT::ValueType VT = MemOps[i]; 4297 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4298 SDOperand Value, Chain, Store; 4299 4300 if (CopyFromStr) { 4301 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4302 Chain = getRoot(); 4303 Store = 4304 DAG.getStore(Chain, Value, 4305 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4306 I.getOperand(1), DstOff); 4307 } else { 4308 Value = DAG.getLoad(VT, getRoot(), 4309 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4310 I.getOperand(2), SrcOff); 4311 Chain = Value.getValue(1); 4312 Store = 4313 DAG.getStore(Chain, Value, 4314 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4315 I.getOperand(1), DstOff); 4316 } 4317 OutChains.push_back(Store); 4318 SrcOff += VTSize; 4319 DstOff += VTSize; 4320 } 4321 } 4322 break; 4323 } 4324 } 4325 4326 if (!OutChains.empty()) { 4327 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4328 &OutChains[0], OutChains.size())); 4329 return; 4330 } 4331 } 4332 4333 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4)); 4334} 4335 4336//===----------------------------------------------------------------------===// 4337// SelectionDAGISel code 4338//===----------------------------------------------------------------------===// 4339 4340unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4341 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 4342} 4343 4344void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4345 AU.addRequired<AliasAnalysis>(); 4346 AU.setPreservesAll(); 4347} 4348 4349 4350 4351bool SelectionDAGISel::runOnFunction(Function &Fn) { 4352 // Get alias analysis for load/store combining. 4353 AA = &getAnalysis<AliasAnalysis>(); 4354 4355 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4356 RegMap = MF.getSSARegMap(); 4357 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4358 4359 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4360 4361 if (ExceptionHandling) 4362 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4363 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4364 // Mark landing pad. 4365 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4366 4367 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4368 SelectBasicBlock(I, MF, FuncInfo); 4369 4370 // Add function live-ins to entry block live-in set. 4371 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4372 BB = FuncInfo.MBBMap[EntryBB]; 4373 if (!MF.livein_empty()) 4374 for (MachineFunction::livein_iterator I = MF.livein_begin(), 4375 E = MF.livein_end(); I != E; ++I) 4376 BB->addLiveIn(I->first); 4377 4378#ifndef NDEBUG 4379 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4380 "Not all catch info was assigned to a landing pad!"); 4381#endif 4382 4383 return true; 4384} 4385 4386SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4387 unsigned Reg) { 4388 SDOperand Op = getValue(V); 4389 assert((Op.getOpcode() != ISD::CopyFromReg || 4390 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4391 "Copy from a reg to the same reg!"); 4392 4393 MVT::ValueType SrcVT = Op.getValueType(); 4394 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT); 4395 unsigned NumRegs = TLI.getNumRegisters(SrcVT); 4396 SmallVector<SDOperand, 8> Regs(NumRegs); 4397 SmallVector<SDOperand, 8> Chains(NumRegs); 4398 4399 // Copy the value by legal parts into sequential virtual registers. 4400 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT); 4401 for (unsigned i = 0; i != NumRegs; ++i) 4402 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); 4403 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 4404} 4405 4406void SelectionDAGISel:: 4407LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4408 std::vector<SDOperand> &UnorderedChains) { 4409 // If this is the entry block, emit arguments. 4410 Function &F = *LLVMBB->getParent(); 4411 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4412 SDOperand OldRoot = SDL.DAG.getRoot(); 4413 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4414 4415 unsigned a = 0; 4416 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4417 AI != E; ++AI, ++a) 4418 if (!AI->use_empty()) { 4419 SDL.setValue(AI, Args[a]); 4420 4421 // If this argument is live outside of the entry block, insert a copy from 4422 // whereever we got it to the vreg that other BB's will reference it as. 4423 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4424 if (VMI != FuncInfo.ValueMap.end()) { 4425 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4426 UnorderedChains.push_back(Copy); 4427 } 4428 } 4429 4430 // Finally, if the target has anything special to do, allow it to do so. 4431 // FIXME: this should insert code into the DAG! 4432 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4433} 4434 4435static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4436 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4437 assert(!FLI.MBBMap[SrcBB]->isLandingPad() && 4438 "Copying catch info out of a landing pad!"); 4439 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4440 if (isSelector(I)) { 4441 // Apply the catch info to DestBB. 4442 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4443#ifndef NDEBUG 4444 FLI.CatchInfoFound.insert(I); 4445#endif 4446 } 4447} 4448 4449void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4450 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4451 FunctionLoweringInfo &FuncInfo) { 4452 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo); 4453 4454 std::vector<SDOperand> UnorderedChains; 4455 4456 // Lower any arguments needed in this block if this is the entry block. 4457 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4458 LowerArguments(LLVMBB, SDL, UnorderedChains); 4459 4460 BB = FuncInfo.MBBMap[LLVMBB]; 4461 SDL.setCurrentBasicBlock(BB); 4462 4463 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4464 4465 if (ExceptionHandling && MMI && BB->isLandingPad()) { 4466 // Add a label to mark the beginning of the landing pad. Deletion of the 4467 // landing pad can thus be detected via the MachineModuleInfo. 4468 unsigned LabelID = MMI->addLandingPad(BB); 4469 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 4470 DAG.getConstant(LabelID, MVT::i32))); 4471 4472 // Mark exception register as live in. 4473 unsigned Reg = TLI.getExceptionAddressRegister(); 4474 if (Reg) BB->addLiveIn(Reg); 4475 4476 // Mark exception selector register as live in. 4477 Reg = TLI.getExceptionSelectorRegister(); 4478 if (Reg) BB->addLiveIn(Reg); 4479 4480 // FIXME: Hack around an exception handling flaw (PR1508): the personality 4481 // function and list of typeids logically belong to the invoke (or, if you 4482 // like, the basic block containing the invoke), and need to be associated 4483 // with it in the dwarf exception handling tables. Currently however the 4484 // information is provided by an intrinsic (eh.selector) that can be moved 4485 // to unexpected places by the optimizers: if the unwind edge is critical, 4486 // then breaking it can result in the intrinsics being in the successor of 4487 // the landing pad, not the landing pad itself. This results in exceptions 4488 // not being caught because no typeids are associated with the invoke. 4489 // This may not be the only way things can go wrong, but it is the only way 4490 // we try to work around for the moment. 4491 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 4492 4493 if (Br && Br->isUnconditional()) { // Critical edge? 4494 BasicBlock::iterator I, E; 4495 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 4496 if (isSelector(I)) 4497 break; 4498 4499 if (I == E) 4500 // No catch info found - try to extract some from the successor. 4501 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 4502 } 4503 } 4504 4505 // Lower all of the non-terminator instructions. 4506 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4507 I != E; ++I) 4508 SDL.visit(*I); 4509 4510 // Ensure that all instructions which are used outside of their defining 4511 // blocks are available as virtual registers. Invoke is handled elsewhere. 4512 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4513 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 4514 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4515 if (VMI != FuncInfo.ValueMap.end()) 4516 UnorderedChains.push_back( 4517 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4518 } 4519 4520 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4521 // ensure constants are generated when needed. Remember the virtual registers 4522 // that need to be added to the Machine PHI nodes as input. We cannot just 4523 // directly add them, because expansion might result in multiple MBB's for one 4524 // BB. As such, the start of the BB might correspond to a different MBB than 4525 // the end. 4526 // 4527 TerminatorInst *TI = LLVMBB->getTerminator(); 4528 4529 // Emit constants only once even if used by multiple PHI nodes. 4530 std::map<Constant*, unsigned> ConstantsOut; 4531 4532 // Vector bool would be better, but vector<bool> is really slow. 4533 std::vector<unsigned char> SuccsHandled; 4534 if (TI->getNumSuccessors()) 4535 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4536 4537 // Check successor nodes' PHI nodes that expect a constant to be available 4538 // from this block. 4539 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4540 BasicBlock *SuccBB = TI->getSuccessor(succ); 4541 if (!isa<PHINode>(SuccBB->begin())) continue; 4542 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4543 4544 // If this terminator has multiple identical successors (common for 4545 // switches), only handle each succ once. 4546 unsigned SuccMBBNo = SuccMBB->getNumber(); 4547 if (SuccsHandled[SuccMBBNo]) continue; 4548 SuccsHandled[SuccMBBNo] = true; 4549 4550 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4551 PHINode *PN; 4552 4553 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4554 // nodes and Machine PHI nodes, but the incoming operands have not been 4555 // emitted yet. 4556 for (BasicBlock::iterator I = SuccBB->begin(); 4557 (PN = dyn_cast<PHINode>(I)); ++I) { 4558 // Ignore dead phi's. 4559 if (PN->use_empty()) continue; 4560 4561 unsigned Reg; 4562 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4563 4564 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4565 unsigned &RegOut = ConstantsOut[C]; 4566 if (RegOut == 0) { 4567 RegOut = FuncInfo.CreateRegForValue(C); 4568 UnorderedChains.push_back( 4569 SDL.CopyValueToVirtualRegister(C, RegOut)); 4570 } 4571 Reg = RegOut; 4572 } else { 4573 Reg = FuncInfo.ValueMap[PHIOp]; 4574 if (Reg == 0) { 4575 assert(isa<AllocaInst>(PHIOp) && 4576 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4577 "Didn't codegen value into a register!??"); 4578 Reg = FuncInfo.CreateRegForValue(PHIOp); 4579 UnorderedChains.push_back( 4580 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4581 } 4582 } 4583 4584 // Remember that this register needs to added to the machine PHI node as 4585 // the input for this MBB. 4586 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4587 unsigned NumRegisters = TLI.getNumRegisters(VT); 4588 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 4589 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4590 } 4591 } 4592 ConstantsOut.clear(); 4593 4594 // Turn all of the unordered chains into one factored node. 4595 if (!UnorderedChains.empty()) { 4596 SDOperand Root = SDL.getRoot(); 4597 if (Root.getOpcode() != ISD::EntryToken) { 4598 unsigned i = 0, e = UnorderedChains.size(); 4599 for (; i != e; ++i) { 4600 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4601 if (UnorderedChains[i].Val->getOperand(0) == Root) 4602 break; // Don't add the root if we already indirectly depend on it. 4603 } 4604 4605 if (i == e) 4606 UnorderedChains.push_back(Root); 4607 } 4608 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4609 &UnorderedChains[0], UnorderedChains.size())); 4610 } 4611 4612 // Lower the terminator after the copies are emitted. 4613 SDL.visit(*LLVMBB->getTerminator()); 4614 4615 // Copy over any CaseBlock records that may now exist due to SwitchInst 4616 // lowering, as well as any jump table information. 4617 SwitchCases.clear(); 4618 SwitchCases = SDL.SwitchCases; 4619 JTCases.clear(); 4620 JTCases = SDL.JTCases; 4621 BitTestCases.clear(); 4622 BitTestCases = SDL.BitTestCases; 4623 4624 // Make sure the root of the DAG is up-to-date. 4625 DAG.setRoot(SDL.getRoot()); 4626} 4627 4628void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4629 // Run the DAG combiner in pre-legalize mode. 4630 DAG.Combine(false, *AA); 4631 4632 DOUT << "Lowered selection DAG:\n"; 4633 DEBUG(DAG.dump()); 4634 4635 // Second step, hack on the DAG until it only uses operations and types that 4636 // the target supports. 4637 DAG.Legalize(); 4638 4639 DOUT << "Legalized selection DAG:\n"; 4640 DEBUG(DAG.dump()); 4641 4642 // Run the DAG combiner in post-legalize mode. 4643 DAG.Combine(true, *AA); 4644 4645 if (ViewISelDAGs) DAG.viewGraph(); 4646 4647 // Third, instruction select all of the operations to machine code, adding the 4648 // code to the MachineBasicBlock. 4649 InstructionSelectBasicBlock(DAG); 4650 4651 DOUT << "Selected machine code:\n"; 4652 DEBUG(BB->dump()); 4653} 4654 4655void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4656 FunctionLoweringInfo &FuncInfo) { 4657 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4658 { 4659 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4660 CurDAG = &DAG; 4661 4662 // First step, lower LLVM code to some DAG. This DAG may use operations and 4663 // types that are not supported by the target. 4664 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4665 4666 // Second step, emit the lowered DAG as machine code. 4667 CodeGenAndEmitDAG(DAG); 4668 } 4669 4670 DOUT << "Total amount of phi nodes to update: " 4671 << PHINodesToUpdate.size() << "\n"; 4672 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4673 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4674 << ", " << PHINodesToUpdate[i].second << ")\n";); 4675 4676 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4677 // PHI nodes in successors. 4678 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4679 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4680 MachineInstr *PHI = PHINodesToUpdate[i].first; 4681 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4682 "This is not a machine PHI node that we are updating!"); 4683 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4684 PHI->addMachineBasicBlockOperand(BB); 4685 } 4686 return; 4687 } 4688 4689 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4690 // Lower header first, if it wasn't already lowered 4691 if (!BitTestCases[i].Emitted) { 4692 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4693 CurDAG = &HSDAG; 4694 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo); 4695 // Set the current basic block to the mbb we wish to insert the code into 4696 BB = BitTestCases[i].Parent; 4697 HSDL.setCurrentBasicBlock(BB); 4698 // Emit the code 4699 HSDL.visitBitTestHeader(BitTestCases[i]); 4700 HSDAG.setRoot(HSDL.getRoot()); 4701 CodeGenAndEmitDAG(HSDAG); 4702 } 4703 4704 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4705 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4706 CurDAG = &BSDAG; 4707 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo); 4708 // Set the current basic block to the mbb we wish to insert the code into 4709 BB = BitTestCases[i].Cases[j].ThisBB; 4710 BSDL.setCurrentBasicBlock(BB); 4711 // Emit the code 4712 if (j+1 != ej) 4713 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 4714 BitTestCases[i].Reg, 4715 BitTestCases[i].Cases[j]); 4716 else 4717 BSDL.visitBitTestCase(BitTestCases[i].Default, 4718 BitTestCases[i].Reg, 4719 BitTestCases[i].Cases[j]); 4720 4721 4722 BSDAG.setRoot(BSDL.getRoot()); 4723 CodeGenAndEmitDAG(BSDAG); 4724 } 4725 4726 // Update PHI Nodes 4727 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4728 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4729 MachineBasicBlock *PHIBB = PHI->getParent(); 4730 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4731 "This is not a machine PHI node that we are updating!"); 4732 // This is "default" BB. We have two jumps to it. From "header" BB and 4733 // from last "case" BB. 4734 if (PHIBB == BitTestCases[i].Default) { 4735 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4736 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent); 4737 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4738 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB); 4739 } 4740 // One of "cases" BB. 4741 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4742 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 4743 if (cBB->succ_end() != 4744 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 4745 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4746 PHI->addMachineBasicBlockOperand(cBB); 4747 } 4748 } 4749 } 4750 } 4751 4752 // If the JumpTable record is filled in, then we need to emit a jump table. 4753 // Updating the PHI nodes is tricky in this case, since we need to determine 4754 // whether the PHI is a successor of the range check MBB or the jump table MBB 4755 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 4756 // Lower header first, if it wasn't already lowered 4757 if (!JTCases[i].first.Emitted) { 4758 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4759 CurDAG = &HSDAG; 4760 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo); 4761 // Set the current basic block to the mbb we wish to insert the code into 4762 BB = JTCases[i].first.HeaderBB; 4763 HSDL.setCurrentBasicBlock(BB); 4764 // Emit the code 4765 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 4766 HSDAG.setRoot(HSDL.getRoot()); 4767 CodeGenAndEmitDAG(HSDAG); 4768 } 4769 4770 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4771 CurDAG = &JSDAG; 4772 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo); 4773 // Set the current basic block to the mbb we wish to insert the code into 4774 BB = JTCases[i].second.MBB; 4775 JSDL.setCurrentBasicBlock(BB); 4776 // Emit the code 4777 JSDL.visitJumpTable(JTCases[i].second); 4778 JSDAG.setRoot(JSDL.getRoot()); 4779 CodeGenAndEmitDAG(JSDAG); 4780 4781 // Update PHI Nodes 4782 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4783 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4784 MachineBasicBlock *PHIBB = PHI->getParent(); 4785 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4786 "This is not a machine PHI node that we are updating!"); 4787 // "default" BB. We can go there only from header BB. 4788 if (PHIBB == JTCases[i].second.Default) { 4789 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4790 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB); 4791 } 4792 // JT BB. Just iterate over successors here 4793 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 4794 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4795 PHI->addMachineBasicBlockOperand(BB); 4796 } 4797 } 4798 } 4799 4800 // If the switch block involved a branch to one of the actual successors, we 4801 // need to update PHI nodes in that block. 4802 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4803 MachineInstr *PHI = PHINodesToUpdate[i].first; 4804 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4805 "This is not a machine PHI node that we are updating!"); 4806 if (BB->isSuccessor(PHI->getParent())) { 4807 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4808 PHI->addMachineBasicBlockOperand(BB); 4809 } 4810 } 4811 4812 // If we generated any switch lowering information, build and codegen any 4813 // additional DAGs necessary. 4814 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 4815 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4816 CurDAG = &SDAG; 4817 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo); 4818 4819 // Set the current basic block to the mbb we wish to insert the code into 4820 BB = SwitchCases[i].ThisBB; 4821 SDL.setCurrentBasicBlock(BB); 4822 4823 // Emit the code 4824 SDL.visitSwitchCase(SwitchCases[i]); 4825 SDAG.setRoot(SDL.getRoot()); 4826 CodeGenAndEmitDAG(SDAG); 4827 4828 // Handle any PHI nodes in successors of this chunk, as if we were coming 4829 // from the original BB before switch expansion. Note that PHI nodes can 4830 // occur multiple times in PHINodesToUpdate. We have to be very careful to 4831 // handle them the right number of times. 4832 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 4833 for (MachineBasicBlock::iterator Phi = BB->begin(); 4834 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 4835 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 4836 for (unsigned pn = 0; ; ++pn) { 4837 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 4838 if (PHINodesToUpdate[pn].first == Phi) { 4839 Phi->addRegOperand(PHINodesToUpdate[pn].second, false); 4840 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB); 4841 break; 4842 } 4843 } 4844 } 4845 4846 // Don't process RHS if same block as LHS. 4847 if (BB == SwitchCases[i].FalseBB) 4848 SwitchCases[i].FalseBB = 0; 4849 4850 // If we haven't handled the RHS, do so now. Otherwise, we're done. 4851 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 4852 SwitchCases[i].FalseBB = 0; 4853 } 4854 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 4855 } 4856} 4857 4858 4859//===----------------------------------------------------------------------===// 4860/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 4861/// target node in the graph. 4862void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 4863 if (ViewSchedDAGs) DAG.viewGraph(); 4864 4865 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 4866 4867 if (!Ctor) { 4868 Ctor = ISHeuristic; 4869 RegisterScheduler::setDefault(Ctor); 4870 } 4871 4872 ScheduleDAG *SL = Ctor(this, &DAG, BB); 4873 BB = SL->Run(); 4874 4875 if (ViewSUnitDAGs) SL->viewGraph(); 4876 4877 delete SL; 4878} 4879 4880 4881HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 4882 return new HazardRecognizer(); 4883} 4884 4885//===----------------------------------------------------------------------===// 4886// Helper functions used by the generated instruction selector. 4887//===----------------------------------------------------------------------===// 4888// Calls to these methods are generated by tblgen. 4889 4890/// CheckAndMask - The isel is trying to match something like (and X, 255). If 4891/// the dag combiner simplified the 255, we still want to match. RHS is the 4892/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 4893/// specified in the .td file (e.g. 255). 4894bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 4895 int64_t DesiredMaskS) const { 4896 uint64_t ActualMask = RHS->getValue(); 4897 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4898 4899 // If the actual mask exactly matches, success! 4900 if (ActualMask == DesiredMask) 4901 return true; 4902 4903 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4904 if (ActualMask & ~DesiredMask) 4905 return false; 4906 4907 // Otherwise, the DAG Combiner may have proven that the value coming in is 4908 // either already zero or is not demanded. Check for known zero input bits. 4909 uint64_t NeededMask = DesiredMask & ~ActualMask; 4910 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 4911 return true; 4912 4913 // TODO: check to see if missing bits are just not demanded. 4914 4915 // Otherwise, this pattern doesn't match. 4916 return false; 4917} 4918 4919/// CheckOrMask - The isel is trying to match something like (or X, 255). If 4920/// the dag combiner simplified the 255, we still want to match. RHS is the 4921/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 4922/// specified in the .td file (e.g. 255). 4923bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 4924 int64_t DesiredMaskS) const { 4925 uint64_t ActualMask = RHS->getValue(); 4926 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4927 4928 // If the actual mask exactly matches, success! 4929 if (ActualMask == DesiredMask) 4930 return true; 4931 4932 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4933 if (ActualMask & ~DesiredMask) 4934 return false; 4935 4936 // Otherwise, the DAG Combiner may have proven that the value coming in is 4937 // either already zero or is not demanded. Check for known zero input bits. 4938 uint64_t NeededMask = DesiredMask & ~ActualMask; 4939 4940 uint64_t KnownZero, KnownOne; 4941 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 4942 4943 // If all the missing bits in the or are already known to be set, match! 4944 if ((NeededMask & KnownOne) == NeededMask) 4945 return true; 4946 4947 // TODO: check to see if missing bits are just not demanded. 4948 4949 // Otherwise, this pattern doesn't match. 4950 return false; 4951} 4952 4953 4954/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 4955/// by tblgen. Others should not call it. 4956void SelectionDAGISel:: 4957SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 4958 std::vector<SDOperand> InOps; 4959 std::swap(InOps, Ops); 4960 4961 Ops.push_back(InOps[0]); // input chain. 4962 Ops.push_back(InOps[1]); // input asm string. 4963 4964 unsigned i = 2, e = InOps.size(); 4965 if (InOps[e-1].getValueType() == MVT::Flag) 4966 --e; // Don't process a flag operand if it is here. 4967 4968 while (i != e) { 4969 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 4970 if ((Flags & 7) != 4 /*MEM*/) { 4971 // Just skip over this operand, copying the operands verbatim. 4972 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 4973 i += (Flags >> 3) + 1; 4974 } else { 4975 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 4976 // Otherwise, this is a memory operand. Ask the target to select it. 4977 std::vector<SDOperand> SelOps; 4978 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 4979 cerr << "Could not match memory address. Inline asm failure!\n"; 4980 exit(1); 4981 } 4982 4983 // Add this to the output node. 4984 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 4985 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 4986 IntPtrTy)); 4987 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 4988 i += 2; 4989 } 4990 } 4991 4992 // Add the flag input back if present. 4993 if (e != InOps.size()) 4994 Ops.push_back(InOps.back()); 4995} 4996 4997char SelectionDAGISel::ID = 0; 4998