SelectionDAGISel.cpp revision 32ac9e77eb4519d019bf8a7c9c3be71dd21530c0
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/FastISel.h" 32#include "llvm/CodeGen/GCStrategy.h" 33#include "llvm/CodeGen/GCMetadata.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineFunctionAnalysis.h" 36#include "llvm/CodeGen/MachineFrameInfo.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineJumpTableInfo.h" 39#include "llvm/CodeGen/MachineModuleInfo.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 42#include "llvm/CodeGen/SchedulerRegistry.h" 43#include "llvm/CodeGen/SelectionDAG.h" 44#include "llvm/CodeGen/DwarfWriter.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameInfo.h" 48#include "llvm/Target/TargetIntrinsicInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetLowering.h" 51#include "llvm/Target/TargetMachine.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/Timer.h" 58#include "llvm/Support/raw_ostream.h" 59#include "llvm/ADT/Statistic.h" 60#include <algorithm> 61using namespace llvm; 62 63STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 64 65static cl::opt<bool> 66EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 67 cl::desc("Enable verbose messages in the \"fast\" " 68 "instruction selector")); 69static cl::opt<bool> 70EnableFastISelAbort("fast-isel-abort", cl::Hidden, 71 cl::desc("Enable abort calls when \"fast\" instruction fails")); 72static cl::opt<bool> 73SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 74 cl::desc("Schedule copies of livein registers"), 75 cl::init(false)); 76 77#ifndef NDEBUG 78static cl::opt<bool> 79ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 80 cl::desc("Pop up a window to show dags before the first " 81 "dag combine pass")); 82static cl::opt<bool> 83ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize types")); 85static cl::opt<bool> 86ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before legalize")); 88static cl::opt<bool> 89ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 90 cl::desc("Pop up a window to show dags before the second " 91 "dag combine pass")); 92static cl::opt<bool> 93ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 94 cl::desc("Pop up a window to show dags before the post legalize types" 95 " dag combine pass")); 96static cl::opt<bool> 97ViewISelDAGs("view-isel-dags", cl::Hidden, 98 cl::desc("Pop up a window to show isel dags as they are selected")); 99static cl::opt<bool> 100ViewSchedDAGs("view-sched-dags", cl::Hidden, 101 cl::desc("Pop up a window to show sched dags as they are processed")); 102static cl::opt<bool> 103ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 104 cl::desc("Pop up a window to show SUnit dags after they are processed")); 105#else 106static const bool ViewDAGCombine1 = false, 107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 108 ViewDAGCombine2 = false, 109 ViewDAGCombineLT = false, 110 ViewISelDAGs = false, ViewSchedDAGs = false, 111 ViewSUnitDAGs = false; 112#endif 113 114//===---------------------------------------------------------------------===// 115/// 116/// RegisterScheduler class - Track the registration of instruction schedulers. 117/// 118//===---------------------------------------------------------------------===// 119MachinePassRegistry RegisterScheduler::Registry; 120 121//===---------------------------------------------------------------------===// 122/// 123/// ISHeuristic command line option for instruction schedulers. 124/// 125//===---------------------------------------------------------------------===// 126static cl::opt<RegisterScheduler::FunctionPassCtor, false, 127 RegisterPassParser<RegisterScheduler> > 128ISHeuristic("pre-RA-sched", 129 cl::init(&createDefaultScheduler), 130 cl::desc("Instruction schedulers available (before register" 131 " allocation):")); 132 133static RegisterScheduler 134defaultListDAGScheduler("default", "Best scheduler for the target", 135 createDefaultScheduler); 136 137namespace llvm { 138 //===--------------------------------------------------------------------===// 139 /// createDefaultScheduler - This creates an instruction scheduler appropriate 140 /// for the target. 141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 142 CodeGenOpt::Level OptLevel) { 143 const TargetLowering &TLI = IS->getTargetLowering(); 144 145 if (OptLevel == CodeGenOpt::None) 146 return createFastDAGScheduler(IS, OptLevel); 147 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 148 return createTDListDAGScheduler(IS, OptLevel); 149 assert(TLI.getSchedulingPreference() == 150 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 151 return createBURRListDAGScheduler(IS, OptLevel); 152 } 153} 154 155// EmitInstrWithCustomInserter - This method should be implemented by targets 156// that mark instructions with the 'usesCustomInserter' flag. These 157// instructions are special in various ways, which require special support to 158// insert. The specified MachineInstr is created but not inserted into any 159// basic blocks, and this method is called to expand it into a sequence of 160// instructions, potentially also creating new basic blocks and control flow. 161// When new basic blocks are inserted and the edges from MBB to its successors 162// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 163// DenseMap. 164MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 165 MachineBasicBlock *MBB, 166 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 167#ifndef NDEBUG 168 dbgs() << "If a target marks an instruction with " 169 "'usesCustomInserter', it must implement " 170 "TargetLowering::EmitInstrWithCustomInserter!"; 171#endif 172 llvm_unreachable(0); 173 return 0; 174} 175 176/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 177/// physical register has only a single copy use, then coalesced the copy 178/// if possible. 179static void EmitLiveInCopy(MachineBasicBlock *MBB, 180 MachineBasicBlock::iterator &InsertPos, 181 unsigned VirtReg, unsigned PhysReg, 182 const TargetRegisterClass *RC, 183 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 184 const MachineRegisterInfo &MRI, 185 const TargetRegisterInfo &TRI, 186 const TargetInstrInfo &TII) { 187 unsigned NumUses = 0; 188 MachineInstr *UseMI = NULL; 189 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 190 UE = MRI.use_end(); UI != UE; ++UI) { 191 UseMI = &*UI; 192 if (++NumUses > 1) 193 break; 194 } 195 196 // If the number of uses is not one, or the use is not a move instruction, 197 // don't coalesce. Also, only coalesce away a virtual register to virtual 198 // register copy. 199 bool Coalesced = false; 200 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 201 if (NumUses == 1 && 202 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 203 TargetRegisterInfo::isVirtualRegister(DstReg)) { 204 VirtReg = DstReg; 205 Coalesced = true; 206 } 207 208 // Now find an ideal location to insert the copy. 209 MachineBasicBlock::iterator Pos = InsertPos; 210 while (Pos != MBB->begin()) { 211 MachineInstr *PrevMI = prior(Pos); 212 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 213 // copyRegToReg might emit multiple instructions to do a copy. 214 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 215 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 216 // This is what the BB looks like right now: 217 // r1024 = mov r0 218 // ... 219 // r1 = mov r1024 220 // 221 // We want to insert "r1025 = mov r1". Inserting this copy below the 222 // move to r1024 makes it impossible for that move to be coalesced. 223 // 224 // r1025 = mov r1 225 // r1024 = mov r0 226 // ... 227 // r1 = mov 1024 228 // r2 = mov 1025 229 break; // Woot! Found a good location. 230 --Pos; 231 } 232 233 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 234 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 235 (void) Emitted; 236 237 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 238 if (Coalesced) { 239 if (&*InsertPos == UseMI) ++InsertPos; 240 MBB->erase(UseMI); 241 } 242} 243 244/// EmitLiveInCopies - If this is the first basic block in the function, 245/// and if it has live ins that need to be copied into vregs, emit the 246/// copies into the block. 247static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 248 const MachineRegisterInfo &MRI, 249 const TargetRegisterInfo &TRI, 250 const TargetInstrInfo &TII) { 251 if (SchedLiveInCopies) { 252 // Emit the copies at a heuristically-determined location in the block. 253 DenseMap<MachineInstr*, unsigned> CopyRegMap; 254 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 255 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 256 E = MRI.livein_end(); LI != E; ++LI) 257 if (LI->second) { 258 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 259 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 260 RC, CopyRegMap, MRI, TRI, TII); 261 } 262 } else { 263 // Emit the copies into the top of the block. 264 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 265 E = MRI.livein_end(); LI != E; ++LI) 266 if (LI->second) { 267 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 268 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 269 LI->second, LI->first, RC, RC); 270 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 271 (void) Emitted; 272 } 273 } 274} 275 276//===----------------------------------------------------------------------===// 277// SelectionDAGISel code 278//===----------------------------------------------------------------------===// 279 280SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 281 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 282 FuncInfo(new FunctionLoweringInfo(TLI)), 283 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 284 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 285 GFI(), 286 OptLevel(OL), 287 DAGSize(0) 288{} 289 290SelectionDAGISel::~SelectionDAGISel() { 291 delete SDB; 292 delete CurDAG; 293 delete FuncInfo; 294} 295 296unsigned SelectionDAGISel::MakeReg(EVT VT) { 297 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 298} 299 300void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 301 AU.addRequired<AliasAnalysis>(); 302 AU.addPreserved<AliasAnalysis>(); 303 AU.addRequired<GCModuleInfo>(); 304 AU.addPreserved<GCModuleInfo>(); 305 AU.addRequired<DwarfWriter>(); 306 AU.addPreserved<DwarfWriter>(); 307 MachineFunctionPass::getAnalysisUsage(AU); 308} 309 310bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 311 Function &Fn = *mf.getFunction(); 312 313 // Do some sanity-checking on the command-line options. 314 assert((!EnableFastISelVerbose || EnableFastISel) && 315 "-fast-isel-verbose requires -fast-isel"); 316 assert((!EnableFastISelAbort || EnableFastISel) && 317 "-fast-isel-abort requires -fast-isel"); 318 319 // Get alias analysis for load/store combining. 320 AA = &getAnalysis<AliasAnalysis>(); 321 322 MF = &mf; 323 const TargetInstrInfo &TII = *TM.getInstrInfo(); 324 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 325 326 if (Fn.hasGC()) 327 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 328 else 329 GFI = 0; 330 RegInfo = &MF->getRegInfo(); 331 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 332 333 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 334 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 335 CurDAG->init(*MF, MMI, DW); 336 FuncInfo->set(Fn, *MF, EnableFastISel); 337 SDB->init(GFI, *AA); 338 339 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 340 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 341 // Mark landing pad. 342 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 343 344 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 345 346 // If the first basic block in the function has live ins that need to be 347 // copied into vregs, emit the copies into the top of the block before 348 // emitting the code for the block. 349 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 350 351 // Add function live-ins to entry block live-in set. 352 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 353 E = RegInfo->livein_end(); I != E; ++I) 354 MF->begin()->addLiveIn(I->first); 355 356#ifndef NDEBUG 357 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 358 "Not all catch info was assigned to a landing pad!"); 359#endif 360 361 FuncInfo->clear(); 362 363 return true; 364} 365 366/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 367/// attached with this instruction. 368static void SetDebugLoc(unsigned MDDbgKind, Instruction *I, 369 SelectionDAGBuilder *SDB, 370 FastISel *FastIS, MachineFunction *MF) { 371 if (MDNode *Dbg = I->getMetadata(MDDbgKind)) { 372 DILocation DILoc(Dbg); 373 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo()); 374 375 SDB->setCurDebugLoc(Loc); 376 377 if (FastIS) 378 FastIS->setCurDebugLoc(Loc); 379 380 // If the function doesn't have a default debug location yet, set 381 // it. This is kind of a hack. 382 if (MF->getDefaultDebugLoc().isUnknown()) 383 MF->setDefaultDebugLoc(Loc); 384 } 385} 386 387/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 388static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 389 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc()); 390 if (FastIS) 391 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc()); 392} 393 394void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 395 BasicBlock::iterator Begin, 396 BasicBlock::iterator End, 397 bool &HadTailCall) { 398 SDB->setCurrentBasicBlock(BB); 399 unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg"); 400 401 // Lower all of the non-terminator instructions. If a call is emitted 402 // as a tail call, cease emitting nodes for this block. 403 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 404 SetDebugLoc(MDDbgKind, I, SDB, 0, MF); 405 406 if (!isa<TerminatorInst>(I)) { 407 SDB->visit(*I); 408 409 // Set the current debug location back to "unknown" so that it doesn't 410 // spuriously apply to subsequent instructions. 411 ResetDebugLoc(SDB, 0); 412 } 413 } 414 415 if (!SDB->HasTailCall) { 416 // Ensure that all instructions which are used outside of their defining 417 // blocks are available as virtual registers. Invoke is handled elsewhere. 418 for (BasicBlock::iterator I = Begin; I != End; ++I) 419 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 420 SDB->CopyToExportRegsIfNeeded(I); 421 422 // Handle PHI nodes in successor blocks. 423 if (End == LLVMBB->end()) { 424 HandlePHINodesInSuccessorBlocks(LLVMBB); 425 426 // Lower the terminator after the copies are emitted. 427 SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF); 428 SDB->visit(*LLVMBB->getTerminator()); 429 ResetDebugLoc(SDB, 0); 430 } 431 } 432 433 // Make sure the root of the DAG is up-to-date. 434 CurDAG->setRoot(SDB->getControlRoot()); 435 436 // Final step, emit the lowered DAG as machine code. 437 CodeGenAndEmitDAG(); 438 HadTailCall = SDB->HasTailCall; 439 SDB->clear(); 440} 441 442namespace { 443/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 444/// nodes from the worklist. 445class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 446 SmallVector<SDNode*, 128> &Worklist; 447 SmallPtrSet<SDNode*, 128> &InWorklist; 448public: 449 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 450 SmallPtrSet<SDNode*, 128> &inwl) 451 : Worklist(wl), InWorklist(inwl) {} 452 453 void RemoveFromWorklist(SDNode *N) { 454 if (!InWorklist.erase(N)) return; 455 456 SmallVector<SDNode*, 128>::iterator I = 457 std::find(Worklist.begin(), Worklist.end(), N); 458 assert(I != Worklist.end() && "Not in worklist"); 459 460 *I = Worklist.back(); 461 Worklist.pop_back(); 462 } 463 464 virtual void NodeDeleted(SDNode *N, SDNode *E) { 465 RemoveFromWorklist(N); 466 } 467 468 virtual void NodeUpdated(SDNode *N) { 469 // Ignore updates. 470 } 471}; 472} 473 474/// TrivialTruncElim - Eliminate some trivial nops that can result from 475/// ShrinkDemandedOps: (trunc (ext n)) -> n. 476static bool TrivialTruncElim(SDValue Op, 477 TargetLowering::TargetLoweringOpt &TLO) { 478 SDValue N0 = Op.getOperand(0); 479 EVT VT = Op.getValueType(); 480 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 481 N0.getOpcode() == ISD::SIGN_EXTEND || 482 N0.getOpcode() == ISD::ANY_EXTEND) && 483 N0.getOperand(0).getValueType() == VT) { 484 return TLO.CombineTo(Op, N0.getOperand(0)); 485 } 486 return false; 487} 488 489/// ShrinkDemandedOps - A late transformation pass that shrink expressions 490/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 491/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 492void SelectionDAGISel::ShrinkDemandedOps() { 493 SmallVector<SDNode*, 128> Worklist; 494 SmallPtrSet<SDNode*, 128> InWorklist; 495 496 // Add all the dag nodes to the worklist. 497 Worklist.reserve(CurDAG->allnodes_size()); 498 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 499 E = CurDAG->allnodes_end(); I != E; ++I) { 500 Worklist.push_back(I); 501 InWorklist.insert(I); 502 } 503 504 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true); 505 while (!Worklist.empty()) { 506 SDNode *N = Worklist.pop_back_val(); 507 InWorklist.erase(N); 508 509 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 510 // Deleting this node may make its operands dead, add them to the worklist 511 // if they aren't already there. 512 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 513 if (InWorklist.insert(N->getOperand(i).getNode())) 514 Worklist.push_back(N->getOperand(i).getNode()); 515 516 CurDAG->DeleteNode(N); 517 continue; 518 } 519 520 // Run ShrinkDemandedOp on scalar binary operations. 521 if (N->getNumValues() != 1 || 522 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 523 continue; 524 525 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 526 APInt Demanded = APInt::getAllOnesValue(BitWidth); 527 APInt KnownZero, KnownOne; 528 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 529 KnownZero, KnownOne, TLO) && 530 (N->getOpcode() != ISD::TRUNCATE || 531 !TrivialTruncElim(SDValue(N, 0), TLO))) 532 continue; 533 534 // Revisit the node. 535 assert(!InWorklist.count(N) && "Already in worklist"); 536 Worklist.push_back(N); 537 InWorklist.insert(N); 538 539 // Replace the old value with the new one. 540 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 541 TLO.Old.getNode()->dump(CurDAG); 542 errs() << "\nWith: "; 543 TLO.New.getNode()->dump(CurDAG); 544 errs() << '\n'); 545 546 if (InWorklist.insert(TLO.New.getNode())) 547 Worklist.push_back(TLO.New.getNode()); 548 549 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 550 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 551 552 if (!TLO.Old.getNode()->use_empty()) continue; 553 554 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 555 i != e; ++i) { 556 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 557 if (OpNode->hasOneUse()) { 558 // Add OpNode to the end of the list to revisit. 559 DeadNodes.RemoveFromWorklist(OpNode); 560 Worklist.push_back(OpNode); 561 InWorklist.insert(OpNode); 562 } 563 } 564 565 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 566 CurDAG->DeleteNode(TLO.Old.getNode()); 567 } 568} 569 570void SelectionDAGISel::ComputeLiveOutVRegInfo() { 571 SmallPtrSet<SDNode*, 128> VisitedNodes; 572 SmallVector<SDNode*, 128> Worklist; 573 574 Worklist.push_back(CurDAG->getRoot().getNode()); 575 576 APInt Mask; 577 APInt KnownZero; 578 APInt KnownOne; 579 580 do { 581 SDNode *N = Worklist.pop_back_val(); 582 583 // If we've already seen this node, ignore it. 584 if (!VisitedNodes.insert(N)) 585 continue; 586 587 // Otherwise, add all chain operands to the worklist. 588 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 589 if (N->getOperand(i).getValueType() == MVT::Other) 590 Worklist.push_back(N->getOperand(i).getNode()); 591 592 // If this is a CopyToReg with a vreg dest, process it. 593 if (N->getOpcode() != ISD::CopyToReg) 594 continue; 595 596 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 597 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 598 continue; 599 600 // Ignore non-scalar or non-integer values. 601 SDValue Src = N->getOperand(2); 602 EVT SrcVT = Src.getValueType(); 603 if (!SrcVT.isInteger() || SrcVT.isVector()) 604 continue; 605 606 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 607 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 608 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 609 610 // Only install this information if it tells us something. 611 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 612 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 613 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 614 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 615 FunctionLoweringInfo::LiveOutInfo &LOI = 616 FuncInfo->LiveOutRegInfo[DestReg]; 617 LOI.NumSignBits = NumSignBits; 618 LOI.KnownOne = KnownOne; 619 LOI.KnownZero = KnownZero; 620 } 621 } while (!Worklist.empty()); 622} 623 624void SelectionDAGISel::CodeGenAndEmitDAG() { 625 std::string GroupName; 626 if (TimePassesIsEnabled) 627 GroupName = "Instruction Selection and Scheduling"; 628 std::string BlockName; 629 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 630 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 631 ViewSUnitDAGs) 632 BlockName = MF->getFunction()->getNameStr() + ":" + 633 BB->getBasicBlock()->getNameStr(); 634 635 DEBUG(dbgs() << "Initial selection DAG:\n"); 636 DEBUG(CurDAG->dump()); 637 638 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 639 640 // Run the DAG combiner in pre-legalize mode. 641 if (TimePassesIsEnabled) { 642 NamedRegionTimer T("DAG Combining 1", GroupName); 643 CurDAG->Combine(Unrestricted, *AA, OptLevel); 644 } else { 645 CurDAG->Combine(Unrestricted, *AA, OptLevel); 646 } 647 648 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 649 DEBUG(CurDAG->dump()); 650 651 // Second step, hack on the DAG until it only uses operations and types that 652 // the target supports. 653 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 654 BlockName); 655 656 bool Changed; 657 if (TimePassesIsEnabled) { 658 NamedRegionTimer T("Type Legalization", GroupName); 659 Changed = CurDAG->LegalizeTypes(); 660 } else { 661 Changed = CurDAG->LegalizeTypes(); 662 } 663 664 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 665 DEBUG(CurDAG->dump()); 666 667 if (Changed) { 668 if (ViewDAGCombineLT) 669 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 670 671 // Run the DAG combiner in post-type-legalize mode. 672 if (TimePassesIsEnabled) { 673 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 674 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 675 } else { 676 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 677 } 678 679 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 680 DEBUG(CurDAG->dump()); 681 } 682 683 if (TimePassesIsEnabled) { 684 NamedRegionTimer T("Vector Legalization", GroupName); 685 Changed = CurDAG->LegalizeVectors(); 686 } else { 687 Changed = CurDAG->LegalizeVectors(); 688 } 689 690 if (Changed) { 691 if (TimePassesIsEnabled) { 692 NamedRegionTimer T("Type Legalization 2", GroupName); 693 CurDAG->LegalizeTypes(); 694 } else { 695 CurDAG->LegalizeTypes(); 696 } 697 698 if (ViewDAGCombineLT) 699 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 700 701 // Run the DAG combiner in post-type-legalize mode. 702 if (TimePassesIsEnabled) { 703 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 704 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 705 } else { 706 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 707 } 708 709 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 710 DEBUG(CurDAG->dump()); 711 } 712 713 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 714 715 if (TimePassesIsEnabled) { 716 NamedRegionTimer T("DAG Legalization", GroupName); 717 CurDAG->Legalize(OptLevel); 718 } else { 719 CurDAG->Legalize(OptLevel); 720 } 721 722 DEBUG(dbgs() << "Legalized selection DAG:\n"); 723 DEBUG(CurDAG->dump()); 724 725 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 726 727 // Run the DAG combiner in post-legalize mode. 728 if (TimePassesIsEnabled) { 729 NamedRegionTimer T("DAG Combining 2", GroupName); 730 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 731 } else { 732 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 733 } 734 735 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 736 DEBUG(CurDAG->dump()); 737 738 if (OptLevel != CodeGenOpt::None) { 739 ShrinkDemandedOps(); 740 ComputeLiveOutVRegInfo(); 741 } 742 743 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 744 745 // Third, instruction select all of the operations to machine code, adding the 746 // code to the MachineBasicBlock. 747 if (TimePassesIsEnabled) { 748 NamedRegionTimer T("Instruction Selection", GroupName); 749 DoInstructionSelection(); 750 } else { 751 DoInstructionSelection(); 752 } 753 754 DEBUG(dbgs() << "Selected selection DAG:\n"); 755 DEBUG(CurDAG->dump()); 756 757 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 758 759 // Schedule machine code. 760 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 761 if (TimePassesIsEnabled) { 762 NamedRegionTimer T("Instruction Scheduling", GroupName); 763 Scheduler->Run(CurDAG, BB, BB->end()); 764 } else { 765 Scheduler->Run(CurDAG, BB, BB->end()); 766 } 767 768 if (ViewSUnitDAGs) Scheduler->viewGraph(); 769 770 // Emit machine code to BB. This can change 'BB' to the last block being 771 // inserted into. 772 if (TimePassesIsEnabled) { 773 NamedRegionTimer T("Instruction Creation", GroupName); 774 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 775 } else { 776 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 777 } 778 779 // Free the scheduler state. 780 if (TimePassesIsEnabled) { 781 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 782 delete Scheduler; 783 } else { 784 delete Scheduler; 785 } 786 787 DEBUG(dbgs() << "Selected machine code:\n"); 788 DEBUG(BB->dump()); 789} 790 791void SelectionDAGISel::DoInstructionSelection() { 792 DEBUG(errs() << "===== Instruction selection begins:\n"); 793 794 PreprocessISelDAG(); 795 796 // Select target instructions for the DAG. 797 { 798 // Number all nodes with a topological order and set DAGSize. 799 DAGSize = CurDAG->AssignTopologicalOrder(); 800 801 // Create a dummy node (which is not added to allnodes), that adds 802 // a reference to the root node, preventing it from being deleted, 803 // and tracking any changes of the root. 804 HandleSDNode Dummy(CurDAG->getRoot()); 805 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 806 ++ISelPosition; 807 808 // The AllNodes list is now topological-sorted. Visit the 809 // nodes by starting at the end of the list (the root of the 810 // graph) and preceding back toward the beginning (the entry 811 // node). 812 while (ISelPosition != CurDAG->allnodes_begin()) { 813 SDNode *Node = --ISelPosition; 814 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 815 // but there are currently some corner cases that it misses. Also, this 816 // makes it theoretically possible to disable the DAGCombiner. 817 if (Node->use_empty()) 818 continue; 819 820 SDNode *ResNode = Select(Node); 821 822 // FIXME: This is pretty gross. 'Select' should be changed to not return 823 // anything at all and this code should be nuked with a tactical strike. 824 825 // If node should not be replaced, continue with the next one. 826 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 827 continue; 828 // Replace node. 829 if (ResNode) 830 ReplaceUses(Node, ResNode); 831 832 // If after the replacement this node is not used any more, 833 // remove this dead node. 834 if (Node->use_empty()) { // Don't delete EntryToken, etc. 835 ISelUpdater ISU(ISelPosition); 836 CurDAG->RemoveDeadNode(Node, &ISU); 837 } 838 } 839 840 CurDAG->setRoot(Dummy.getValue()); 841 } 842 DEBUG(errs() << "===== Instruction selection ends:\n"); 843 844 PostprocessISelDAG(); 845 846 // FIXME: This shouldn't be needed, remove it. 847 CurDAG->RemoveDeadNodes(); 848} 849 850 851void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 852 MachineFunction &MF, 853 MachineModuleInfo *MMI, 854 DwarfWriter *DW, 855 const TargetInstrInfo &TII) { 856 // Initialize the Fast-ISel state, if needed. 857 FastISel *FastIS = 0; 858 if (EnableFastISel) 859 FastIS = TLI.createFastISel(MF, MMI, DW, 860 FuncInfo->ValueMap, 861 FuncInfo->MBBMap, 862 FuncInfo->StaticAllocaMap 863#ifndef NDEBUG 864 , FuncInfo->CatchInfoLost 865#endif 866 ); 867 868 unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg"); 869 870 // Iterate over all basic blocks in the function. 871 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 872 BasicBlock *LLVMBB = &*I; 873 BB = FuncInfo->MBBMap[LLVMBB]; 874 875 BasicBlock::iterator const Begin = LLVMBB->begin(); 876 BasicBlock::iterator const End = LLVMBB->end(); 877 BasicBlock::iterator BI = Begin; 878 879 // Lower any arguments needed in this block if this is the entry block. 880 bool SuppressFastISel = false; 881 if (LLVMBB == &Fn.getEntryBlock()) { 882 LowerArguments(LLVMBB); 883 884 // If any of the arguments has the byval attribute, forgo 885 // fast-isel in the entry block. 886 if (FastIS) { 887 unsigned j = 1; 888 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 889 I != E; ++I, ++j) 890 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 891 if (EnableFastISelVerbose || EnableFastISelAbort) 892 dbgs() << "FastISel skips entry block due to byval argument\n"; 893 SuppressFastISel = true; 894 break; 895 } 896 } 897 } 898 899 if (MMI && BB->isLandingPad()) { 900 // Add a label to mark the beginning of the landing pad. Deletion of the 901 // landing pad can thus be detected via the MachineModuleInfo. 902 MCSymbol *Label = MMI->addLandingPad(BB); 903 904 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL); 905 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 906 907 // Mark exception register as live in. 908 unsigned Reg = TLI.getExceptionAddressRegister(); 909 if (Reg) BB->addLiveIn(Reg); 910 911 // Mark exception selector register as live in. 912 Reg = TLI.getExceptionSelectorRegister(); 913 if (Reg) BB->addLiveIn(Reg); 914 915 // FIXME: Hack around an exception handling flaw (PR1508): the personality 916 // function and list of typeids logically belong to the invoke (or, if you 917 // like, the basic block containing the invoke), and need to be associated 918 // with it in the dwarf exception handling tables. Currently however the 919 // information is provided by an intrinsic (eh.selector) that can be moved 920 // to unexpected places by the optimizers: if the unwind edge is critical, 921 // then breaking it can result in the intrinsics being in the successor of 922 // the landing pad, not the landing pad itself. This results 923 // in exceptions not being caught because no typeids are associated with 924 // the invoke. This may not be the only way things can go wrong, but it 925 // is the only way we try to work around for the moment. 926 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 927 928 if (Br && Br->isUnconditional()) { // Critical edge? 929 BasicBlock::iterator I, E; 930 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 931 if (isa<EHSelectorInst>(I)) 932 break; 933 934 if (I == E) 935 // No catch info found - try to extract some from the successor. 936 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 937 } 938 } 939 940 // Before doing SelectionDAG ISel, see if FastISel has been requested. 941 if (FastIS && !SuppressFastISel) { 942 // Emit code for any incoming arguments. This must happen before 943 // beginning FastISel on the entry block. 944 if (LLVMBB == &Fn.getEntryBlock()) { 945 CurDAG->setRoot(SDB->getControlRoot()); 946 CodeGenAndEmitDAG(); 947 SDB->clear(); 948 } 949 FastIS->startNewBlock(BB); 950 // Do FastISel on as many instructions as possible. 951 for (; BI != End; ++BI) { 952 // Just before the terminator instruction, insert instructions to 953 // feed PHI nodes in successor blocks. 954 if (isa<TerminatorInst>(BI)) 955 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 956 ++NumFastIselFailures; 957 ResetDebugLoc(SDB, FastIS); 958 if (EnableFastISelVerbose || EnableFastISelAbort) { 959 dbgs() << "FastISel miss: "; 960 BI->dump(); 961 } 962 assert(!EnableFastISelAbort && 963 "FastISel didn't handle a PHI in a successor"); 964 break; 965 } 966 967 SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF); 968 969 // Try to select the instruction with FastISel. 970 if (FastIS->SelectInstruction(BI)) { 971 ResetDebugLoc(SDB, FastIS); 972 continue; 973 } 974 975 // Clear out the debug location so that it doesn't carry over to 976 // unrelated instructions. 977 ResetDebugLoc(SDB, FastIS); 978 979 // Then handle certain instructions as single-LLVM-Instruction blocks. 980 if (isa<CallInst>(BI)) { 981 ++NumFastIselFailures; 982 if (EnableFastISelVerbose || EnableFastISelAbort) { 983 dbgs() << "FastISel missed call: "; 984 BI->dump(); 985 } 986 987 if (!BI->getType()->isVoidTy()) { 988 unsigned &R = FuncInfo->ValueMap[BI]; 989 if (!R) 990 R = FuncInfo->CreateRegForValue(BI); 991 } 992 993 bool HadTailCall = false; 994 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 995 996 // If the call was emitted as a tail call, we're done with the block. 997 if (HadTailCall) { 998 BI = End; 999 break; 1000 } 1001 1002 // If the instruction was codegen'd with multiple blocks, 1003 // inform the FastISel object where to resume inserting. 1004 FastIS->setCurrentBlock(BB); 1005 continue; 1006 } 1007 1008 // Otherwise, give up on FastISel for the rest of the block. 1009 // For now, be a little lenient about non-branch terminators. 1010 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 1011 ++NumFastIselFailures; 1012 if (EnableFastISelVerbose || EnableFastISelAbort) { 1013 dbgs() << "FastISel miss: "; 1014 BI->dump(); 1015 } 1016 if (EnableFastISelAbort) 1017 // The "fast" selector couldn't handle something and bailed. 1018 // For the purpose of debugging, just abort. 1019 llvm_unreachable("FastISel didn't select the entire block"); 1020 } 1021 break; 1022 } 1023 } 1024 1025 // Run SelectionDAG instruction selection on the remainder of the block 1026 // not handled by FastISel. If FastISel is not run, this is the entire 1027 // block. 1028 if (BI != End) { 1029 bool HadTailCall; 1030 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 1031 } 1032 1033 FinishBasicBlock(); 1034 } 1035 1036 delete FastIS; 1037} 1038 1039void 1040SelectionDAGISel::FinishBasicBlock() { 1041 1042 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 1043 DEBUG(BB->dump()); 1044 1045 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1046 << SDB->PHINodesToUpdate.size() << "\n"); 1047 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 1048 dbgs() << "Node " << i << " : (" 1049 << SDB->PHINodesToUpdate[i].first 1050 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 1051 1052 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1053 // PHI nodes in successors. 1054 if (SDB->SwitchCases.empty() && 1055 SDB->JTCases.empty() && 1056 SDB->BitTestCases.empty()) { 1057 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1058 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1059 assert(PHI->isPHI() && 1060 "This is not a machine PHI node that we are updating!"); 1061 if (!BB->isSuccessor(PHI->getParent())) 1062 continue; 1063 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1064 false)); 1065 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1066 } 1067 SDB->PHINodesToUpdate.clear(); 1068 return; 1069 } 1070 1071 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1072 // Lower header first, if it wasn't already lowered 1073 if (!SDB->BitTestCases[i].Emitted) { 1074 // Set the current basic block to the mbb we wish to insert the code into 1075 BB = SDB->BitTestCases[i].Parent; 1076 SDB->setCurrentBasicBlock(BB); 1077 // Emit the code 1078 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 1079 CurDAG->setRoot(SDB->getRoot()); 1080 CodeGenAndEmitDAG(); 1081 SDB->clear(); 1082 } 1083 1084 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1085 // Set the current basic block to the mbb we wish to insert the code into 1086 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 1087 SDB->setCurrentBasicBlock(BB); 1088 // Emit the code 1089 if (j+1 != ej) 1090 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 1091 SDB->BitTestCases[i].Reg, 1092 SDB->BitTestCases[i].Cases[j]); 1093 else 1094 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 1095 SDB->BitTestCases[i].Reg, 1096 SDB->BitTestCases[i].Cases[j]); 1097 1098 1099 CurDAG->setRoot(SDB->getRoot()); 1100 CodeGenAndEmitDAG(); 1101 SDB->clear(); 1102 } 1103 1104 // Update PHI Nodes 1105 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1106 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1107 MachineBasicBlock *PHIBB = PHI->getParent(); 1108 assert(PHI->isPHI() && 1109 "This is not a machine PHI node that we are updating!"); 1110 // This is "default" BB. We have two jumps to it. From "header" BB and 1111 // from last "case" BB. 1112 if (PHIBB == SDB->BitTestCases[i].Default) { 1113 PHI->addOperand(MachineOperand:: 1114 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1115 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1116 PHI->addOperand(MachineOperand:: 1117 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1118 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1119 back().ThisBB)); 1120 } 1121 // One of "cases" BB. 1122 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1123 j != ej; ++j) { 1124 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1125 if (cBB->isSuccessor(PHIBB)) { 1126 PHI->addOperand(MachineOperand:: 1127 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1128 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1129 } 1130 } 1131 } 1132 } 1133 SDB->BitTestCases.clear(); 1134 1135 // If the JumpTable record is filled in, then we need to emit a jump table. 1136 // Updating the PHI nodes is tricky in this case, since we need to determine 1137 // whether the PHI is a successor of the range check MBB or the jump table MBB 1138 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1139 // Lower header first, if it wasn't already lowered 1140 if (!SDB->JTCases[i].first.Emitted) { 1141 // Set the current basic block to the mbb we wish to insert the code into 1142 BB = SDB->JTCases[i].first.HeaderBB; 1143 SDB->setCurrentBasicBlock(BB); 1144 // Emit the code 1145 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 1146 CurDAG->setRoot(SDB->getRoot()); 1147 CodeGenAndEmitDAG(); 1148 SDB->clear(); 1149 } 1150 1151 // Set the current basic block to the mbb we wish to insert the code into 1152 BB = SDB->JTCases[i].second.MBB; 1153 SDB->setCurrentBasicBlock(BB); 1154 // Emit the code 1155 SDB->visitJumpTable(SDB->JTCases[i].second); 1156 CurDAG->setRoot(SDB->getRoot()); 1157 CodeGenAndEmitDAG(); 1158 SDB->clear(); 1159 1160 // Update PHI Nodes 1161 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1162 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1163 MachineBasicBlock *PHIBB = PHI->getParent(); 1164 assert(PHI->isPHI() && 1165 "This is not a machine PHI node that we are updating!"); 1166 // "default" BB. We can go there only from header BB. 1167 if (PHIBB == SDB->JTCases[i].second.Default) { 1168 PHI->addOperand 1169 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1170 PHI->addOperand 1171 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1172 } 1173 // JT BB. Just iterate over successors here 1174 if (BB->isSuccessor(PHIBB)) { 1175 PHI->addOperand 1176 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1177 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1178 } 1179 } 1180 } 1181 SDB->JTCases.clear(); 1182 1183 // If the switch block involved a branch to one of the actual successors, we 1184 // need to update PHI nodes in that block. 1185 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1186 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1187 assert(PHI->isPHI() && 1188 "This is not a machine PHI node that we are updating!"); 1189 if (BB->isSuccessor(PHI->getParent())) { 1190 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1191 false)); 1192 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1193 } 1194 } 1195 1196 // If we generated any switch lowering information, build and codegen any 1197 // additional DAGs necessary. 1198 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1199 // Set the current basic block to the mbb we wish to insert the code into 1200 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1201 SDB->setCurrentBasicBlock(BB); 1202 1203 // Emit the code 1204 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1205 CurDAG->setRoot(SDB->getRoot()); 1206 CodeGenAndEmitDAG(); 1207 1208 // Handle any PHI nodes in successors of this chunk, as if we were coming 1209 // from the original BB before switch expansion. Note that PHI nodes can 1210 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1211 // handle them the right number of times. 1212 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1213 // If new BB's are created during scheduling, the edges may have been 1214 // updated. That is, the edge from ThisBB to BB may have been split and 1215 // BB's predecessor is now another block. 1216 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1217 SDB->EdgeMapping.find(BB); 1218 if (EI != SDB->EdgeMapping.end()) 1219 ThisBB = EI->second; 1220 1221 // BB may have been removed from the CFG if a branch was constant folded. 1222 if (ThisBB->isSuccessor(BB)) { 1223 for (MachineBasicBlock::iterator Phi = BB->begin(); 1224 Phi != BB->end() && Phi->isPHI(); 1225 ++Phi) { 1226 // This value for this PHI node is recorded in PHINodesToUpdate. 1227 for (unsigned pn = 0; ; ++pn) { 1228 assert(pn != SDB->PHINodesToUpdate.size() && 1229 "Didn't find PHI entry!"); 1230 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1231 Phi->addOperand(MachineOperand:: 1232 CreateReg(SDB->PHINodesToUpdate[pn].second, 1233 false)); 1234 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1235 break; 1236 } 1237 } 1238 } 1239 } 1240 1241 // Don't process RHS if same block as LHS. 1242 if (BB == SDB->SwitchCases[i].FalseBB) 1243 SDB->SwitchCases[i].FalseBB = 0; 1244 1245 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1246 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1247 SDB->SwitchCases[i].FalseBB = 0; 1248 } 1249 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1250 SDB->clear(); 1251 } 1252 SDB->SwitchCases.clear(); 1253 1254 SDB->PHINodesToUpdate.clear(); 1255} 1256 1257 1258/// Create the scheduler. If a specific scheduler was specified 1259/// via the SchedulerRegistry, use it, otherwise select the 1260/// one preferred by the target. 1261/// 1262ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1263 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1264 1265 if (!Ctor) { 1266 Ctor = ISHeuristic; 1267 RegisterScheduler::setDefault(Ctor); 1268 } 1269 1270 return Ctor(this, OptLevel); 1271} 1272 1273ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1274 return new ScheduleHazardRecognizer(); 1275} 1276 1277//===----------------------------------------------------------------------===// 1278// Helper functions used by the generated instruction selector. 1279//===----------------------------------------------------------------------===// 1280// Calls to these methods are generated by tblgen. 1281 1282/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1283/// the dag combiner simplified the 255, we still want to match. RHS is the 1284/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1285/// specified in the .td file (e.g. 255). 1286bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1287 int64_t DesiredMaskS) const { 1288 const APInt &ActualMask = RHS->getAPIntValue(); 1289 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1290 1291 // If the actual mask exactly matches, success! 1292 if (ActualMask == DesiredMask) 1293 return true; 1294 1295 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1296 if (ActualMask.intersects(~DesiredMask)) 1297 return false; 1298 1299 // Otherwise, the DAG Combiner may have proven that the value coming in is 1300 // either already zero or is not demanded. Check for known zero input bits. 1301 APInt NeededMask = DesiredMask & ~ActualMask; 1302 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1303 return true; 1304 1305 // TODO: check to see if missing bits are just not demanded. 1306 1307 // Otherwise, this pattern doesn't match. 1308 return false; 1309} 1310 1311/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1312/// the dag combiner simplified the 255, we still want to match. RHS is the 1313/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1314/// specified in the .td file (e.g. 255). 1315bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1316 int64_t DesiredMaskS) const { 1317 const APInt &ActualMask = RHS->getAPIntValue(); 1318 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1319 1320 // If the actual mask exactly matches, success! 1321 if (ActualMask == DesiredMask) 1322 return true; 1323 1324 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1325 if (ActualMask.intersects(~DesiredMask)) 1326 return false; 1327 1328 // Otherwise, the DAG Combiner may have proven that the value coming in is 1329 // either already zero or is not demanded. Check for known zero input bits. 1330 APInt NeededMask = DesiredMask & ~ActualMask; 1331 1332 APInt KnownZero, KnownOne; 1333 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1334 1335 // If all the missing bits in the or are already known to be set, match! 1336 if ((NeededMask & KnownOne) == NeededMask) 1337 return true; 1338 1339 // TODO: check to see if missing bits are just not demanded. 1340 1341 // Otherwise, this pattern doesn't match. 1342 return false; 1343} 1344 1345 1346/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1347/// by tblgen. Others should not call it. 1348void SelectionDAGISel:: 1349SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1350 std::vector<SDValue> InOps; 1351 std::swap(InOps, Ops); 1352 1353 Ops.push_back(InOps[0]); // input chain. 1354 Ops.push_back(InOps[1]); // input asm string. 1355 1356 unsigned i = 2, e = InOps.size(); 1357 if (InOps[e-1].getValueType() == MVT::Flag) 1358 --e; // Don't process a flag operand if it is here. 1359 1360 while (i != e) { 1361 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1362 if ((Flags & 7) != 4 /*MEM*/) { 1363 // Just skip over this operand, copying the operands verbatim. 1364 Ops.insert(Ops.end(), InOps.begin()+i, 1365 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1366 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1367 } else { 1368 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1369 "Memory operand with multiple values?"); 1370 // Otherwise, this is a memory operand. Ask the target to select it. 1371 std::vector<SDValue> SelOps; 1372 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1373 llvm_report_error("Could not match memory address. Inline asm" 1374 " failure!"); 1375 } 1376 1377 // Add this to the output node. 1378 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1379 MVT::i32)); 1380 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1381 i += 2; 1382 } 1383 } 1384 1385 // Add the flag input back if present. 1386 if (e != InOps.size()) 1387 Ops.push_back(InOps.back()); 1388} 1389 1390/// findFlagUse - Return use of EVT::Flag value produced by the specified 1391/// SDNode. 1392/// 1393static SDNode *findFlagUse(SDNode *N) { 1394 unsigned FlagResNo = N->getNumValues()-1; 1395 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1396 SDUse &Use = I.getUse(); 1397 if (Use.getResNo() == FlagResNo) 1398 return Use.getUser(); 1399 } 1400 return NULL; 1401} 1402 1403/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1404/// This function recursively traverses up the operand chain, ignoring 1405/// certain nodes. 1406static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1407 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1408 bool IgnoreChains) { 1409 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1410 // greater than all of its (recursive) operands. If we scan to a point where 1411 // 'use' is smaller than the node we're scanning for, then we know we will 1412 // never find it. 1413 // 1414 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1415 // happen because we scan down to newly selected nodes in the case of flag 1416 // uses. 1417 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1418 return false; 1419 1420 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1421 // won't fail if we scan it again. 1422 if (!Visited.insert(Use)) 1423 return false; 1424 1425 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1426 // Ignore chain uses, they are validated by HandleMergeInputChains. 1427 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1428 continue; 1429 1430 SDNode *N = Use->getOperand(i).getNode(); 1431 if (N == Def) { 1432 if (Use == ImmedUse || Use == Root) 1433 continue; // We are not looking for immediate use. 1434 assert(N != Root); 1435 return true; 1436 } 1437 1438 // Traverse up the operand chain. 1439 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1440 return true; 1441 } 1442 return false; 1443} 1444 1445/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1446/// operand node N of U during instruction selection that starts at Root. 1447bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1448 SDNode *Root) const { 1449 if (OptLevel == CodeGenOpt::None) return false; 1450 return N.hasOneUse(); 1451} 1452 1453/// IsLegalToFold - Returns true if the specific operand node N of 1454/// U can be folded during instruction selection that starts at Root. 1455bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1456 bool IgnoreChains) const { 1457 if (OptLevel == CodeGenOpt::None) return false; 1458 1459 // If Root use can somehow reach N through a path that that doesn't contain 1460 // U then folding N would create a cycle. e.g. In the following 1461 // diagram, Root can reach N through X. If N is folded into into Root, then 1462 // X is both a predecessor and a successor of U. 1463 // 1464 // [N*] // 1465 // ^ ^ // 1466 // / \ // 1467 // [U*] [X]? // 1468 // ^ ^ // 1469 // \ / // 1470 // \ / // 1471 // [Root*] // 1472 // 1473 // * indicates nodes to be folded together. 1474 // 1475 // If Root produces a flag, then it gets (even more) interesting. Since it 1476 // will be "glued" together with its flag use in the scheduler, we need to 1477 // check if it might reach N. 1478 // 1479 // [N*] // 1480 // ^ ^ // 1481 // / \ // 1482 // [U*] [X]? // 1483 // ^ ^ // 1484 // \ \ // 1485 // \ | // 1486 // [Root*] | // 1487 // ^ | // 1488 // f | // 1489 // | / // 1490 // [Y] / // 1491 // ^ / // 1492 // f / // 1493 // | / // 1494 // [FU] // 1495 // 1496 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1497 // (call it Fold), then X is a predecessor of FU and a successor of 1498 // Fold. But since Fold and FU are flagged together, this will create 1499 // a cycle in the scheduling graph. 1500 1501 // If the node has flags, walk down the graph to the "lowest" node in the 1502 // flagged set. 1503 EVT VT = Root->getValueType(Root->getNumValues()-1); 1504 while (VT == MVT::Flag) { 1505 SDNode *FU = findFlagUse(Root); 1506 if (FU == NULL) 1507 break; 1508 Root = FU; 1509 VT = Root->getValueType(Root->getNumValues()-1); 1510 1511 // If our query node has a flag result with a use, we've walked up it. If 1512 // the user (which has already been selected) has a chain or indirectly uses 1513 // the chain, our WalkChainUsers predicate will not consider it. Because of 1514 // this, we cannot ignore chains in this predicate. 1515 IgnoreChains = false; 1516 } 1517 1518 1519 SmallPtrSet<SDNode*, 16> Visited; 1520 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1521} 1522 1523SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1524 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1525 SelectInlineAsmMemoryOperands(Ops); 1526 1527 std::vector<EVT> VTs; 1528 VTs.push_back(MVT::Other); 1529 VTs.push_back(MVT::Flag); 1530 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1531 VTs, &Ops[0], Ops.size()); 1532 New->setNodeId(-1); 1533 return New.getNode(); 1534} 1535 1536SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1537 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1538} 1539 1540/// GetVBR - decode a vbr encoding whose top bit is set. 1541ALWAYS_INLINE static uint64_t 1542GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1543 assert(Val >= 128 && "Not a VBR"); 1544 Val &= 127; // Remove first vbr bit. 1545 1546 unsigned Shift = 7; 1547 uint64_t NextBits; 1548 do { 1549 NextBits = MatcherTable[Idx++]; 1550 Val |= (NextBits&127) << Shift; 1551 Shift += 7; 1552 } while (NextBits & 128); 1553 1554 return Val; 1555} 1556 1557 1558/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1559/// interior flag and chain results to use the new flag and chain results. 1560void SelectionDAGISel:: 1561UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1562 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1563 SDValue InputFlag, 1564 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1565 bool isMorphNodeTo) { 1566 SmallVector<SDNode*, 4> NowDeadNodes; 1567 1568 ISelUpdater ISU(ISelPosition); 1569 1570 // Now that all the normal results are replaced, we replace the chain and 1571 // flag results if present. 1572 if (!ChainNodesMatched.empty()) { 1573 assert(InputChain.getNode() != 0 && 1574 "Matched input chains but didn't produce a chain"); 1575 // Loop over all of the nodes we matched that produced a chain result. 1576 // Replace all the chain results with the final chain we ended up with. 1577 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1578 SDNode *ChainNode = ChainNodesMatched[i]; 1579 1580 // If this node was already deleted, don't look at it. 1581 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1582 continue; 1583 1584 // Don't replace the results of the root node if we're doing a 1585 // MorphNodeTo. 1586 if (ChainNode == NodeToMatch && isMorphNodeTo) 1587 continue; 1588 1589 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1590 if (ChainVal.getValueType() == MVT::Flag) 1591 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1592 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1593 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1594 1595 // If the node became dead and we haven't already seen it, delete it. 1596 if (ChainNode->use_empty() && 1597 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1598 NowDeadNodes.push_back(ChainNode); 1599 } 1600 } 1601 1602 // If the result produces a flag, update any flag results in the matched 1603 // pattern with the flag result. 1604 if (InputFlag.getNode() != 0) { 1605 // Handle any interior nodes explicitly marked. 1606 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1607 SDNode *FRN = FlagResultNodesMatched[i]; 1608 1609 // If this node was already deleted, don't look at it. 1610 if (FRN->getOpcode() == ISD::DELETED_NODE) 1611 continue; 1612 1613 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1614 "Doesn't have a flag result"); 1615 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1616 InputFlag, &ISU); 1617 1618 // If the node became dead and we haven't already seen it, delete it. 1619 if (FRN->use_empty() && 1620 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1621 NowDeadNodes.push_back(FRN); 1622 } 1623 } 1624 1625 if (!NowDeadNodes.empty()) 1626 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1627 1628 DEBUG(errs() << "ISEL: Match complete!\n"); 1629} 1630 1631enum ChainResult { 1632 CR_Simple, 1633 CR_InducesCycle, 1634 CR_LeadsToInteriorNode 1635}; 1636 1637/// WalkChainUsers - Walk down the users of the specified chained node that is 1638/// part of the pattern we're matching, looking at all of the users we find. 1639/// This determines whether something is an interior node, whether we have a 1640/// non-pattern node in between two pattern nodes (which prevent folding because 1641/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1642/// between pattern nodes (in which case the TF becomes part of the pattern). 1643/// 1644/// The walk we do here is guaranteed to be small because we quickly get down to 1645/// already selected nodes "below" us. 1646static ChainResult 1647WalkChainUsers(SDNode *ChainedNode, 1648 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1649 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1650 ChainResult Result = CR_Simple; 1651 1652 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1653 E = ChainedNode->use_end(); UI != E; ++UI) { 1654 // Make sure the use is of the chain, not some other value we produce. 1655 if (UI.getUse().getValueType() != MVT::Other) continue; 1656 1657 SDNode *User = *UI; 1658 1659 // If we see an already-selected machine node, then we've gone beyond the 1660 // pattern that we're selecting down into the already selected chunk of the 1661 // DAG. 1662 if (User->isMachineOpcode() || 1663 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1664 continue; 1665 1666 if (User->getOpcode() == ISD::CopyToReg || 1667 User->getOpcode() == ISD::CopyFromReg || 1668 User->getOpcode() == ISD::INLINEASM || 1669 User->getOpcode() == ISD::EH_LABEL) { 1670 // If their node ID got reset to -1 then they've already been selected. 1671 // Treat them like a MachineOpcode. 1672 if (User->getNodeId() == -1) 1673 continue; 1674 } 1675 1676 // If we have a TokenFactor, we handle it specially. 1677 if (User->getOpcode() != ISD::TokenFactor) { 1678 // If the node isn't a token factor and isn't part of our pattern, then it 1679 // must be a random chained node in between two nodes we're selecting. 1680 // This happens when we have something like: 1681 // x = load ptr 1682 // call 1683 // y = x+4 1684 // store y -> ptr 1685 // Because we structurally match the load/store as a read/modify/write, 1686 // but the call is chained between them. We cannot fold in this case 1687 // because it would induce a cycle in the graph. 1688 if (!std::count(ChainedNodesInPattern.begin(), 1689 ChainedNodesInPattern.end(), User)) 1690 return CR_InducesCycle; 1691 1692 // Otherwise we found a node that is part of our pattern. For example in: 1693 // x = load ptr 1694 // y = x+4 1695 // store y -> ptr 1696 // This would happen when we're scanning down from the load and see the 1697 // store as a user. Record that there is a use of ChainedNode that is 1698 // part of the pattern and keep scanning uses. 1699 Result = CR_LeadsToInteriorNode; 1700 InteriorChainedNodes.push_back(User); 1701 continue; 1702 } 1703 1704 // If we found a TokenFactor, there are two cases to consider: first if the 1705 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1706 // uses of the TF are in our pattern) we just want to ignore it. Second, 1707 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1708 // [Load chain] 1709 // ^ 1710 // | 1711 // [Load] 1712 // ^ ^ 1713 // | \ DAG's like cheese 1714 // / \ do you? 1715 // / | 1716 // [TokenFactor] [Op] 1717 // ^ ^ 1718 // | | 1719 // \ / 1720 // \ / 1721 // [Store] 1722 // 1723 // In this case, the TokenFactor becomes part of our match and we rewrite it 1724 // as a new TokenFactor. 1725 // 1726 // To distinguish these two cases, do a recursive walk down the uses. 1727 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1728 case CR_Simple: 1729 // If the uses of the TokenFactor are just already-selected nodes, ignore 1730 // it, it is "below" our pattern. 1731 continue; 1732 case CR_InducesCycle: 1733 // If the uses of the TokenFactor lead to nodes that are not part of our 1734 // pattern that are not selected, folding would turn this into a cycle, 1735 // bail out now. 1736 return CR_InducesCycle; 1737 case CR_LeadsToInteriorNode: 1738 break; // Otherwise, keep processing. 1739 } 1740 1741 // Okay, we know we're in the interesting interior case. The TokenFactor 1742 // is now going to be considered part of the pattern so that we rewrite its 1743 // uses (it may have uses that are not part of the pattern) with the 1744 // ultimate chain result of the generated code. We will also add its chain 1745 // inputs as inputs to the ultimate TokenFactor we create. 1746 Result = CR_LeadsToInteriorNode; 1747 ChainedNodesInPattern.push_back(User); 1748 InteriorChainedNodes.push_back(User); 1749 continue; 1750 } 1751 1752 return Result; 1753} 1754 1755/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1756/// operation for when the pattern matched at least one node with a chains. The 1757/// input vector contains a list of all of the chained nodes that we match. We 1758/// must determine if this is a valid thing to cover (i.e. matching it won't 1759/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1760/// be used as the input node chain for the generated nodes. 1761static SDValue 1762HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1763 SelectionDAG *CurDAG) { 1764 // Walk all of the chained nodes we've matched, recursively scanning down the 1765 // users of the chain result. This adds any TokenFactor nodes that are caught 1766 // in between chained nodes to the chained and interior nodes list. 1767 SmallVector<SDNode*, 3> InteriorChainedNodes; 1768 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1769 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1770 InteriorChainedNodes) == CR_InducesCycle) 1771 return SDValue(); // Would induce a cycle. 1772 } 1773 1774 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1775 // that we are interested in. Form our input TokenFactor node. 1776 SmallVector<SDValue, 3> InputChains; 1777 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1778 // Add the input chain of this node to the InputChains list (which will be 1779 // the operands of the generated TokenFactor) if it's not an interior node. 1780 SDNode *N = ChainNodesMatched[i]; 1781 if (N->getOpcode() != ISD::TokenFactor) { 1782 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1783 continue; 1784 1785 // Otherwise, add the input chain. 1786 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1787 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1788 InputChains.push_back(InChain); 1789 continue; 1790 } 1791 1792 // If we have a token factor, we want to add all inputs of the token factor 1793 // that are not part of the pattern we're matching. 1794 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1795 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1796 N->getOperand(op).getNode())) 1797 InputChains.push_back(N->getOperand(op)); 1798 } 1799 } 1800 1801 SDValue Res; 1802 if (InputChains.size() == 1) 1803 return InputChains[0]; 1804 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1805 MVT::Other, &InputChains[0], InputChains.size()); 1806} 1807 1808/// MorphNode - Handle morphing a node in place for the selector. 1809SDNode *SelectionDAGISel:: 1810MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1811 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1812 // It is possible we're using MorphNodeTo to replace a node with no 1813 // normal results with one that has a normal result (or we could be 1814 // adding a chain) and the input could have flags and chains as well. 1815 // In this case we need to shifting the operands down. 1816 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1817 // than the old isel though. 1818 int OldFlagResultNo = -1, OldChainResultNo = -1; 1819 1820 unsigned NTMNumResults = Node->getNumValues(); 1821 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1822 OldFlagResultNo = NTMNumResults-1; 1823 if (NTMNumResults != 1 && 1824 Node->getValueType(NTMNumResults-2) == MVT::Other) 1825 OldChainResultNo = NTMNumResults-2; 1826 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1827 OldChainResultNo = NTMNumResults-1; 1828 1829 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1830 // that this deletes operands of the old node that become dead. 1831 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1832 1833 // MorphNodeTo can operate in two ways: if an existing node with the 1834 // specified operands exists, it can just return it. Otherwise, it 1835 // updates the node in place to have the requested operands. 1836 if (Res == Node) { 1837 // If we updated the node in place, reset the node ID. To the isel, 1838 // this should be just like a newly allocated machine node. 1839 Res->setNodeId(-1); 1840 } 1841 1842 unsigned ResNumResults = Res->getNumValues(); 1843 // Move the flag if needed. 1844 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1845 (unsigned)OldFlagResultNo != ResNumResults-1) 1846 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1847 SDValue(Res, ResNumResults-1)); 1848 1849 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1850 --ResNumResults; 1851 1852 // Move the chain reference if needed. 1853 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1854 (unsigned)OldChainResultNo != ResNumResults-1) 1855 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1856 SDValue(Res, ResNumResults-1)); 1857 1858 // Otherwise, no replacement happened because the node already exists. Replace 1859 // Uses of the old node with the new one. 1860 if (Res != Node) 1861 CurDAG->ReplaceAllUsesWith(Node, Res); 1862 1863 return Res; 1864} 1865 1866/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1867ALWAYS_INLINE static bool 1868CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1869 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1870 // Accept if it is exactly the same as a previously recorded node. 1871 unsigned RecNo = MatcherTable[MatcherIndex++]; 1872 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1873 return N == RecordedNodes[RecNo]; 1874} 1875 1876/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1877ALWAYS_INLINE static bool 1878CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1879 SelectionDAGISel &SDISel) { 1880 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1881} 1882 1883/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1884ALWAYS_INLINE static bool 1885CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1886 SelectionDAGISel &SDISel, SDNode *N) { 1887 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1888} 1889 1890ALWAYS_INLINE static bool 1891CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1892 SDNode *N) { 1893 uint16_t Opc = MatcherTable[MatcherIndex++]; 1894 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1895 return N->getOpcode() == Opc; 1896} 1897 1898ALWAYS_INLINE static bool 1899CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1900 SDValue N, const TargetLowering &TLI) { 1901 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1902 if (N.getValueType() == VT) return true; 1903 1904 // Handle the case when VT is iPTR. 1905 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1906} 1907 1908ALWAYS_INLINE static bool 1909CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1910 SDValue N, const TargetLowering &TLI, 1911 unsigned ChildNo) { 1912 if (ChildNo >= N.getNumOperands()) 1913 return false; // Match fails if out of range child #. 1914 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1915} 1916 1917 1918ALWAYS_INLINE static bool 1919CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1920 SDValue N) { 1921 return cast<CondCodeSDNode>(N)->get() == 1922 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1923} 1924 1925ALWAYS_INLINE static bool 1926CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1927 SDValue N, const TargetLowering &TLI) { 1928 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1929 if (cast<VTSDNode>(N)->getVT() == VT) 1930 return true; 1931 1932 // Handle the case when VT is iPTR. 1933 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1934} 1935 1936ALWAYS_INLINE static bool 1937CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1938 SDValue N) { 1939 int64_t Val = MatcherTable[MatcherIndex++]; 1940 if (Val & 128) 1941 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1942 1943 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1944 return C != 0 && C->getSExtValue() == Val; 1945} 1946 1947ALWAYS_INLINE static bool 1948CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1949 SDValue N, SelectionDAGISel &SDISel) { 1950 int64_t Val = MatcherTable[MatcherIndex++]; 1951 if (Val & 128) 1952 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1953 1954 if (N->getOpcode() != ISD::AND) return false; 1955 1956 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1957 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1958} 1959 1960ALWAYS_INLINE static bool 1961CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1962 SDValue N, SelectionDAGISel &SDISel) { 1963 int64_t Val = MatcherTable[MatcherIndex++]; 1964 if (Val & 128) 1965 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1966 1967 if (N->getOpcode() != ISD::OR) return false; 1968 1969 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1970 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1971} 1972 1973/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1974/// scope, evaluate the current node. If the current predicate is known to 1975/// fail, set Result=true and return anything. If the current predicate is 1976/// known to pass, set Result=false and return the MatcherIndex to continue 1977/// with. If the current predicate is unknown, set Result=false and return the 1978/// MatcherIndex to continue with. 1979static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1980 unsigned Index, SDValue N, 1981 bool &Result, SelectionDAGISel &SDISel, 1982 SmallVectorImpl<SDValue> &RecordedNodes){ 1983 switch (Table[Index++]) { 1984 default: 1985 Result = false; 1986 return Index-1; // Could not evaluate this predicate. 1987 case SelectionDAGISel::OPC_CheckSame: 1988 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1989 return Index; 1990 case SelectionDAGISel::OPC_CheckPatternPredicate: 1991 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1992 return Index; 1993 case SelectionDAGISel::OPC_CheckPredicate: 1994 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1995 return Index; 1996 case SelectionDAGISel::OPC_CheckOpcode: 1997 Result = !::CheckOpcode(Table, Index, N.getNode()); 1998 return Index; 1999 case SelectionDAGISel::OPC_CheckType: 2000 Result = !::CheckType(Table, Index, N, SDISel.TLI); 2001 return Index; 2002 case SelectionDAGISel::OPC_CheckChild0Type: 2003 case SelectionDAGISel::OPC_CheckChild1Type: 2004 case SelectionDAGISel::OPC_CheckChild2Type: 2005 case SelectionDAGISel::OPC_CheckChild3Type: 2006 case SelectionDAGISel::OPC_CheckChild4Type: 2007 case SelectionDAGISel::OPC_CheckChild5Type: 2008 case SelectionDAGISel::OPC_CheckChild6Type: 2009 case SelectionDAGISel::OPC_CheckChild7Type: 2010 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 2011 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2012 return Index; 2013 case SelectionDAGISel::OPC_CheckCondCode: 2014 Result = !::CheckCondCode(Table, Index, N); 2015 return Index; 2016 case SelectionDAGISel::OPC_CheckValueType: 2017 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2018 return Index; 2019 case SelectionDAGISel::OPC_CheckInteger: 2020 Result = !::CheckInteger(Table, Index, N); 2021 return Index; 2022 case SelectionDAGISel::OPC_CheckAndImm: 2023 Result = !::CheckAndImm(Table, Index, N, SDISel); 2024 return Index; 2025 case SelectionDAGISel::OPC_CheckOrImm: 2026 Result = !::CheckOrImm(Table, Index, N, SDISel); 2027 return Index; 2028 } 2029} 2030 2031 2032struct MatchScope { 2033 /// FailIndex - If this match fails, this is the index to continue with. 2034 unsigned FailIndex; 2035 2036 /// NodeStack - The node stack when the scope was formed. 2037 SmallVector<SDValue, 4> NodeStack; 2038 2039 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2040 unsigned NumRecordedNodes; 2041 2042 /// NumMatchedMemRefs - The number of matched memref entries. 2043 unsigned NumMatchedMemRefs; 2044 2045 /// InputChain/InputFlag - The current chain/flag 2046 SDValue InputChain, InputFlag; 2047 2048 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2049 bool HasChainNodesMatched, HasFlagResultNodesMatched; 2050}; 2051 2052SDNode *SelectionDAGISel:: 2053SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2054 unsigned TableSize) { 2055 // FIXME: Should these even be selected? Handle these cases in the caller? 2056 switch (NodeToMatch->getOpcode()) { 2057 default: 2058 break; 2059 case ISD::EntryToken: // These nodes remain the same. 2060 case ISD::BasicBlock: 2061 case ISD::Register: 2062 //case ISD::VALUETYPE: 2063 //case ISD::CONDCODE: 2064 case ISD::HANDLENODE: 2065 case ISD::TargetConstant: 2066 case ISD::TargetConstantFP: 2067 case ISD::TargetConstantPool: 2068 case ISD::TargetFrameIndex: 2069 case ISD::TargetExternalSymbol: 2070 case ISD::TargetBlockAddress: 2071 case ISD::TargetJumpTable: 2072 case ISD::TargetGlobalTLSAddress: 2073 case ISD::TargetGlobalAddress: 2074 case ISD::TokenFactor: 2075 case ISD::CopyFromReg: 2076 case ISD::CopyToReg: 2077 case ISD::EH_LABEL: 2078 NodeToMatch->setNodeId(-1); // Mark selected. 2079 return 0; 2080 case ISD::AssertSext: 2081 case ISD::AssertZext: 2082 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2083 NodeToMatch->getOperand(0)); 2084 return 0; 2085 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2086 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2087 } 2088 2089 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2090 2091 // Set up the node stack with NodeToMatch as the only node on the stack. 2092 SmallVector<SDValue, 8> NodeStack; 2093 SDValue N = SDValue(NodeToMatch, 0); 2094 NodeStack.push_back(N); 2095 2096 // MatchScopes - Scopes used when matching, if a match failure happens, this 2097 // indicates where to continue checking. 2098 SmallVector<MatchScope, 8> MatchScopes; 2099 2100 // RecordedNodes - This is the set of nodes that have been recorded by the 2101 // state machine. 2102 SmallVector<SDValue, 8> RecordedNodes; 2103 2104 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2105 // pattern. 2106 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2107 2108 // These are the current input chain and flag for use when generating nodes. 2109 // Various Emit operations change these. For example, emitting a copytoreg 2110 // uses and updates these. 2111 SDValue InputChain, InputFlag; 2112 2113 // ChainNodesMatched - If a pattern matches nodes that have input/output 2114 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2115 // which ones they are. The result is captured into this list so that we can 2116 // update the chain results when the pattern is complete. 2117 SmallVector<SDNode*, 3> ChainNodesMatched; 2118 SmallVector<SDNode*, 3> FlagResultNodesMatched; 2119 2120 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2121 NodeToMatch->dump(CurDAG); 2122 errs() << '\n'); 2123 2124 // Determine where to start the interpreter. Normally we start at opcode #0, 2125 // but if the state machine starts with an OPC_SwitchOpcode, then we 2126 // accelerate the first lookup (which is guaranteed to be hot) with the 2127 // OpcodeOffset table. 2128 unsigned MatcherIndex = 0; 2129 2130 if (!OpcodeOffset.empty()) { 2131 // Already computed the OpcodeOffset table, just index into it. 2132 if (N.getOpcode() < OpcodeOffset.size()) 2133 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2134 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2135 2136 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2137 // Otherwise, the table isn't computed, but the state machine does start 2138 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2139 // is the first time we're selecting an instruction. 2140 unsigned Idx = 1; 2141 while (1) { 2142 // Get the size of this case. 2143 unsigned CaseSize = MatcherTable[Idx++]; 2144 if (CaseSize & 128) 2145 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2146 if (CaseSize == 0) break; 2147 2148 // Get the opcode, add the index to the table. 2149 uint16_t Opc = MatcherTable[Idx++]; 2150 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2151 if (Opc >= OpcodeOffset.size()) 2152 OpcodeOffset.resize((Opc+1)*2); 2153 OpcodeOffset[Opc] = Idx; 2154 Idx += CaseSize; 2155 } 2156 2157 // Okay, do the lookup for the first opcode. 2158 if (N.getOpcode() < OpcodeOffset.size()) 2159 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2160 } 2161 2162 while (1) { 2163 assert(MatcherIndex < TableSize && "Invalid index"); 2164#ifndef NDEBUG 2165 unsigned CurrentOpcodeIndex = MatcherIndex; 2166#endif 2167 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2168 switch (Opcode) { 2169 case OPC_Scope: { 2170 // Okay, the semantics of this operation are that we should push a scope 2171 // then evaluate the first child. However, pushing a scope only to have 2172 // the first check fail (which then pops it) is inefficient. If we can 2173 // determine immediately that the first check (or first several) will 2174 // immediately fail, don't even bother pushing a scope for them. 2175 unsigned FailIndex; 2176 2177 while (1) { 2178 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2179 if (NumToSkip & 128) 2180 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2181 // Found the end of the scope with no match. 2182 if (NumToSkip == 0) { 2183 FailIndex = 0; 2184 break; 2185 } 2186 2187 FailIndex = MatcherIndex+NumToSkip; 2188 2189 unsigned MatcherIndexOfPredicate = MatcherIndex; 2190 (void)MatcherIndexOfPredicate; // silence warning. 2191 2192 // If we can't evaluate this predicate without pushing a scope (e.g. if 2193 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2194 // push the scope and evaluate the full predicate chain. 2195 bool Result; 2196 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2197 Result, *this, RecordedNodes); 2198 if (!Result) 2199 break; 2200 2201 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2202 << "index " << MatcherIndexOfPredicate 2203 << ", continuing at " << FailIndex << "\n"); 2204 2205 2206 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2207 // move to the next case. 2208 MatcherIndex = FailIndex; 2209 } 2210 2211 // If the whole scope failed to match, bail. 2212 if (FailIndex == 0) break; 2213 2214 // Push a MatchScope which indicates where to go if the first child fails 2215 // to match. 2216 MatchScope NewEntry; 2217 NewEntry.FailIndex = FailIndex; 2218 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2219 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2220 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2221 NewEntry.InputChain = InputChain; 2222 NewEntry.InputFlag = InputFlag; 2223 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2224 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2225 MatchScopes.push_back(NewEntry); 2226 continue; 2227 } 2228 case OPC_RecordNode: 2229 // Remember this node, it may end up being an operand in the pattern. 2230 RecordedNodes.push_back(N); 2231 continue; 2232 2233 case OPC_RecordChild0: case OPC_RecordChild1: 2234 case OPC_RecordChild2: case OPC_RecordChild3: 2235 case OPC_RecordChild4: case OPC_RecordChild5: 2236 case OPC_RecordChild6: case OPC_RecordChild7: { 2237 unsigned ChildNo = Opcode-OPC_RecordChild0; 2238 if (ChildNo >= N.getNumOperands()) 2239 break; // Match fails if out of range child #. 2240 2241 RecordedNodes.push_back(N->getOperand(ChildNo)); 2242 continue; 2243 } 2244 case OPC_RecordMemRef: 2245 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2246 continue; 2247 2248 case OPC_CaptureFlagInput: 2249 // If the current node has an input flag, capture it in InputFlag. 2250 if (N->getNumOperands() != 0 && 2251 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2252 InputFlag = N->getOperand(N->getNumOperands()-1); 2253 continue; 2254 2255 case OPC_MoveChild: { 2256 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2257 if (ChildNo >= N.getNumOperands()) 2258 break; // Match fails if out of range child #. 2259 N = N.getOperand(ChildNo); 2260 NodeStack.push_back(N); 2261 continue; 2262 } 2263 2264 case OPC_MoveParent: 2265 // Pop the current node off the NodeStack. 2266 NodeStack.pop_back(); 2267 assert(!NodeStack.empty() && "Node stack imbalance!"); 2268 N = NodeStack.back(); 2269 continue; 2270 2271 case OPC_CheckSame: 2272 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2273 continue; 2274 case OPC_CheckPatternPredicate: 2275 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2276 continue; 2277 case OPC_CheckPredicate: 2278 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2279 N.getNode())) 2280 break; 2281 continue; 2282 case OPC_CheckComplexPat: { 2283 unsigned CPNum = MatcherTable[MatcherIndex++]; 2284 unsigned RecNo = MatcherTable[MatcherIndex++]; 2285 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2286 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2287 RecordedNodes)) 2288 break; 2289 continue; 2290 } 2291 case OPC_CheckOpcode: 2292 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2293 continue; 2294 2295 case OPC_CheckType: 2296 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2297 continue; 2298 2299 case OPC_SwitchOpcode: { 2300 unsigned CurNodeOpcode = N.getOpcode(); 2301 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2302 unsigned CaseSize; 2303 while (1) { 2304 // Get the size of this case. 2305 CaseSize = MatcherTable[MatcherIndex++]; 2306 if (CaseSize & 128) 2307 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2308 if (CaseSize == 0) break; 2309 2310 uint16_t Opc = MatcherTable[MatcherIndex++]; 2311 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2312 2313 // If the opcode matches, then we will execute this case. 2314 if (CurNodeOpcode == Opc) 2315 break; 2316 2317 // Otherwise, skip over this case. 2318 MatcherIndex += CaseSize; 2319 } 2320 2321 // If no cases matched, bail out. 2322 if (CaseSize == 0) break; 2323 2324 // Otherwise, execute the case we found. 2325 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2326 << " to " << MatcherIndex << "\n"); 2327 continue; 2328 } 2329 2330 case OPC_SwitchType: { 2331 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2332 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2333 unsigned CaseSize; 2334 while (1) { 2335 // Get the size of this case. 2336 CaseSize = MatcherTable[MatcherIndex++]; 2337 if (CaseSize & 128) 2338 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2339 if (CaseSize == 0) break; 2340 2341 MVT::SimpleValueType CaseVT = 2342 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2343 if (CaseVT == MVT::iPTR) 2344 CaseVT = TLI.getPointerTy().SimpleTy; 2345 2346 // If the VT matches, then we will execute this case. 2347 if (CurNodeVT == CaseVT) 2348 break; 2349 2350 // Otherwise, skip over this case. 2351 MatcherIndex += CaseSize; 2352 } 2353 2354 // If no cases matched, bail out. 2355 if (CaseSize == 0) break; 2356 2357 // Otherwise, execute the case we found. 2358 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2359 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2360 continue; 2361 } 2362 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2363 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2364 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2365 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2366 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2367 Opcode-OPC_CheckChild0Type)) 2368 break; 2369 continue; 2370 case OPC_CheckCondCode: 2371 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2372 continue; 2373 case OPC_CheckValueType: 2374 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2375 continue; 2376 case OPC_CheckInteger: 2377 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2378 continue; 2379 case OPC_CheckAndImm: 2380 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2381 continue; 2382 case OPC_CheckOrImm: 2383 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2384 continue; 2385 2386 case OPC_CheckFoldableChainNode: { 2387 assert(NodeStack.size() != 1 && "No parent node"); 2388 // Verify that all intermediate nodes between the root and this one have 2389 // a single use. 2390 bool HasMultipleUses = false; 2391 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2392 if (!NodeStack[i].hasOneUse()) { 2393 HasMultipleUses = true; 2394 break; 2395 } 2396 if (HasMultipleUses) break; 2397 2398 // Check to see that the target thinks this is profitable to fold and that 2399 // we can fold it without inducing cycles in the graph. 2400 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2401 NodeToMatch) || 2402 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2403 NodeToMatch, true/*We validate our own chains*/)) 2404 break; 2405 2406 continue; 2407 } 2408 case OPC_EmitInteger: { 2409 MVT::SimpleValueType VT = 2410 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2411 int64_t Val = MatcherTable[MatcherIndex++]; 2412 if (Val & 128) 2413 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2414 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2415 continue; 2416 } 2417 case OPC_EmitRegister: { 2418 MVT::SimpleValueType VT = 2419 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2420 unsigned RegNo = MatcherTable[MatcherIndex++]; 2421 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2422 continue; 2423 } 2424 2425 case OPC_EmitConvertToTarget: { 2426 // Convert from IMM/FPIMM to target version. 2427 unsigned RecNo = MatcherTable[MatcherIndex++]; 2428 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2429 SDValue Imm = RecordedNodes[RecNo]; 2430 2431 if (Imm->getOpcode() == ISD::Constant) { 2432 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2433 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2434 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2435 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2436 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2437 } 2438 2439 RecordedNodes.push_back(Imm); 2440 continue; 2441 } 2442 2443 case OPC_EmitMergeInputChains: { 2444 assert(InputChain.getNode() == 0 && 2445 "EmitMergeInputChains should be the first chain producing node"); 2446 // This node gets a list of nodes we matched in the input that have 2447 // chains. We want to token factor all of the input chains to these nodes 2448 // together. However, if any of the input chains is actually one of the 2449 // nodes matched in this pattern, then we have an intra-match reference. 2450 // Ignore these because the newly token factored chain should not refer to 2451 // the old nodes. 2452 unsigned NumChains = MatcherTable[MatcherIndex++]; 2453 assert(NumChains != 0 && "Can't TF zero chains"); 2454 2455 assert(ChainNodesMatched.empty() && 2456 "Should only have one EmitMergeInputChains per match"); 2457 2458 // Read all of the chained nodes. 2459 for (unsigned i = 0; i != NumChains; ++i) { 2460 unsigned RecNo = MatcherTable[MatcherIndex++]; 2461 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2462 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2463 2464 // FIXME: What if other value results of the node have uses not matched 2465 // by this pattern? 2466 if (ChainNodesMatched.back() != NodeToMatch && 2467 !RecordedNodes[RecNo].hasOneUse()) { 2468 ChainNodesMatched.clear(); 2469 break; 2470 } 2471 } 2472 2473 // If the inner loop broke out, the match fails. 2474 if (ChainNodesMatched.empty()) 2475 break; 2476 2477 // Merge the input chains if they are not intra-pattern references. 2478 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2479 2480 if (InputChain.getNode() == 0) 2481 break; // Failed to merge. 2482 2483 continue; 2484 } 2485 2486 case OPC_EmitCopyToReg: { 2487 unsigned RecNo = MatcherTable[MatcherIndex++]; 2488 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2489 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2490 2491 if (InputChain.getNode() == 0) 2492 InputChain = CurDAG->getEntryNode(); 2493 2494 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2495 DestPhysReg, RecordedNodes[RecNo], 2496 InputFlag); 2497 2498 InputFlag = InputChain.getValue(1); 2499 continue; 2500 } 2501 2502 case OPC_EmitNodeXForm: { 2503 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2504 unsigned RecNo = MatcherTable[MatcherIndex++]; 2505 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2506 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2507 continue; 2508 } 2509 2510 case OPC_EmitNode: 2511 case OPC_MorphNodeTo: { 2512 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2513 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2514 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2515 // Get the result VT list. 2516 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2517 SmallVector<EVT, 4> VTs; 2518 for (unsigned i = 0; i != NumVTs; ++i) { 2519 MVT::SimpleValueType VT = 2520 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2521 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2522 VTs.push_back(VT); 2523 } 2524 2525 if (EmitNodeInfo & OPFL_Chain) 2526 VTs.push_back(MVT::Other); 2527 if (EmitNodeInfo & OPFL_FlagOutput) 2528 VTs.push_back(MVT::Flag); 2529 2530 // This is hot code, so optimize the two most common cases of 1 and 2 2531 // results. 2532 SDVTList VTList; 2533 if (VTs.size() == 1) 2534 VTList = CurDAG->getVTList(VTs[0]); 2535 else if (VTs.size() == 2) 2536 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2537 else 2538 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2539 2540 // Get the operand list. 2541 unsigned NumOps = MatcherTable[MatcherIndex++]; 2542 SmallVector<SDValue, 8> Ops; 2543 for (unsigned i = 0; i != NumOps; ++i) { 2544 unsigned RecNo = MatcherTable[MatcherIndex++]; 2545 if (RecNo & 128) 2546 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2547 2548 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2549 Ops.push_back(RecordedNodes[RecNo]); 2550 } 2551 2552 // If there are variadic operands to add, handle them now. 2553 if (EmitNodeInfo & OPFL_VariadicInfo) { 2554 // Determine the start index to copy from. 2555 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2556 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2557 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2558 "Invalid variadic node"); 2559 // Copy all of the variadic operands, not including a potential flag 2560 // input. 2561 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2562 i != e; ++i) { 2563 SDValue V = NodeToMatch->getOperand(i); 2564 if (V.getValueType() == MVT::Flag) break; 2565 Ops.push_back(V); 2566 } 2567 } 2568 2569 // If this has chain/flag inputs, add them. 2570 if (EmitNodeInfo & OPFL_Chain) 2571 Ops.push_back(InputChain); 2572 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2573 Ops.push_back(InputFlag); 2574 2575 // Create the node. 2576 SDNode *Res = 0; 2577 if (Opcode != OPC_MorphNodeTo) { 2578 // If this is a normal EmitNode command, just create the new node and 2579 // add the results to the RecordedNodes list. 2580 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2581 VTList, Ops.data(), Ops.size()); 2582 2583 // Add all the non-flag/non-chain results to the RecordedNodes list. 2584 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2585 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2586 RecordedNodes.push_back(SDValue(Res, i)); 2587 } 2588 2589 } else { 2590 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2591 EmitNodeInfo); 2592 } 2593 2594 // If the node had chain/flag results, update our notion of the current 2595 // chain and flag. 2596 if (EmitNodeInfo & OPFL_FlagOutput) { 2597 InputFlag = SDValue(Res, VTs.size()-1); 2598 if (EmitNodeInfo & OPFL_Chain) 2599 InputChain = SDValue(Res, VTs.size()-2); 2600 } else if (EmitNodeInfo & OPFL_Chain) 2601 InputChain = SDValue(Res, VTs.size()-1); 2602 2603 // If the OPFL_MemRefs flag is set on this node, slap all of the 2604 // accumulated memrefs onto it. 2605 // 2606 // FIXME: This is vastly incorrect for patterns with multiple outputs 2607 // instructions that access memory and for ComplexPatterns that match 2608 // loads. 2609 if (EmitNodeInfo & OPFL_MemRefs) { 2610 MachineSDNode::mmo_iterator MemRefs = 2611 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2612 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2613 cast<MachineSDNode>(Res) 2614 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2615 } 2616 2617 DEBUG(errs() << " " 2618 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2619 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2620 2621 // If this was a MorphNodeTo then we're completely done! 2622 if (Opcode == OPC_MorphNodeTo) { 2623 // Update chain and flag uses. 2624 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2625 InputFlag, FlagResultNodesMatched, true); 2626 return Res; 2627 } 2628 2629 continue; 2630 } 2631 2632 case OPC_MarkFlagResults: { 2633 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2634 2635 // Read and remember all the flag-result nodes. 2636 for (unsigned i = 0; i != NumNodes; ++i) { 2637 unsigned RecNo = MatcherTable[MatcherIndex++]; 2638 if (RecNo & 128) 2639 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2640 2641 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2642 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2643 } 2644 continue; 2645 } 2646 2647 case OPC_CompleteMatch: { 2648 // The match has been completed, and any new nodes (if any) have been 2649 // created. Patch up references to the matched dag to use the newly 2650 // created nodes. 2651 unsigned NumResults = MatcherTable[MatcherIndex++]; 2652 2653 for (unsigned i = 0; i != NumResults; ++i) { 2654 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2655 if (ResSlot & 128) 2656 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2657 2658 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2659 SDValue Res = RecordedNodes[ResSlot]; 2660 2661 // FIXME2: Eliminate this horrible hack by fixing the 'Gen' program 2662 // after (parallel) on input patterns are removed. This would also 2663 // allow us to stop encoding #results in OPC_CompleteMatch's table 2664 // entry. 2665 if (i >= NodeToMatch->getNumValues() || 2666 NodeToMatch->getValueType(i) == MVT::Other || 2667 NodeToMatch->getValueType(i) == MVT::Flag) 2668 break; 2669 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2670 NodeToMatch->getValueType(i) == MVT::iPTR || 2671 Res.getValueType() == MVT::iPTR || 2672 NodeToMatch->getValueType(i).getSizeInBits() == 2673 Res.getValueType().getSizeInBits()) && 2674 "invalid replacement"); 2675 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2676 } 2677 2678 // If the root node defines a flag, add it to the flag nodes to update 2679 // list. 2680 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2681 FlagResultNodesMatched.push_back(NodeToMatch); 2682 2683 // Update chain and flag uses. 2684 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2685 InputFlag, FlagResultNodesMatched, false); 2686 2687 assert(NodeToMatch->use_empty() && 2688 "Didn't replace all uses of the node?"); 2689 2690 // FIXME: We just return here, which interacts correctly with SelectRoot 2691 // above. We should fix this to not return an SDNode* anymore. 2692 return 0; 2693 } 2694 } 2695 2696 // If the code reached this point, then the match failed. See if there is 2697 // another child to try in the current 'Scope', otherwise pop it until we 2698 // find a case to check. 2699 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2700 while (1) { 2701 if (MatchScopes.empty()) { 2702 CannotYetSelect(NodeToMatch); 2703 return 0; 2704 } 2705 2706 // Restore the interpreter state back to the point where the scope was 2707 // formed. 2708 MatchScope &LastScope = MatchScopes.back(); 2709 RecordedNodes.resize(LastScope.NumRecordedNodes); 2710 NodeStack.clear(); 2711 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2712 N = NodeStack.back(); 2713 2714 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2715 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2716 MatcherIndex = LastScope.FailIndex; 2717 2718 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2719 2720 InputChain = LastScope.InputChain; 2721 InputFlag = LastScope.InputFlag; 2722 if (!LastScope.HasChainNodesMatched) 2723 ChainNodesMatched.clear(); 2724 if (!LastScope.HasFlagResultNodesMatched) 2725 FlagResultNodesMatched.clear(); 2726 2727 // Check to see what the offset is at the new MatcherIndex. If it is zero 2728 // we have reached the end of this scope, otherwise we have another child 2729 // in the current scope to try. 2730 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2731 if (NumToSkip & 128) 2732 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2733 2734 // If we have another child in this scope to match, update FailIndex and 2735 // try it. 2736 if (NumToSkip != 0) { 2737 LastScope.FailIndex = MatcherIndex+NumToSkip; 2738 break; 2739 } 2740 2741 // End of this scope, pop it and try the next child in the containing 2742 // scope. 2743 MatchScopes.pop_back(); 2744 } 2745 } 2746} 2747 2748 2749 2750void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2751 std::string msg; 2752 raw_string_ostream Msg(msg); 2753 Msg << "Cannot yet select: "; 2754 2755 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2756 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2757 N->getOpcode() != ISD::INTRINSIC_VOID) { 2758 N->printrFull(Msg, CurDAG); 2759 } else { 2760 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2761 unsigned iid = 2762 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2763 if (iid < Intrinsic::num_intrinsics) 2764 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2765 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2766 Msg << "target intrinsic %" << TII->getName(iid); 2767 else 2768 Msg << "unknown intrinsic #" << iid; 2769 } 2770 llvm_report_error(Msg.str()); 2771} 2772 2773char SelectionDAGISel::ID = 0; 2774