SelectionDAGISel.cpp revision 32e3150faba95187c76b211e27d6496a21bee360
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "ScheduleDAGSDNodes.h" 17#include "SelectionDAGBuilder.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/Statistic.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/BranchProbabilityInfo.h" 22#include "llvm/Analysis/CFG.h" 23#include "llvm/Analysis/TargetTransformInfo.h" 24#include "llvm/CodeGen/FastISel.h" 25#include "llvm/CodeGen/FunctionLoweringInfo.h" 26#include "llvm/CodeGen/GCMetadata.h" 27#include "llvm/CodeGen/GCStrategy.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineModuleInfo.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/DebugInfo.h" 37#include "llvm/IR/Constants.h" 38#include "llvm/IR/Function.h" 39#include "llvm/IR/InlineAsm.h" 40#include "llvm/IR/Instructions.h" 41#include "llvm/IR/IntrinsicInst.h" 42#include "llvm/IR/Intrinsics.h" 43#include "llvm/IR/LLVMContext.h" 44#include "llvm/IR/Module.h" 45#include "llvm/Support/Compiler.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/ErrorHandling.h" 48#include "llvm/Support/Timer.h" 49#include "llvm/Support/raw_ostream.h" 50#include "llvm/Target/TargetInstrInfo.h" 51#include "llvm/Target/TargetIntrinsicInfo.h" 52#include "llvm/Target/TargetLibraryInfo.h" 53#include "llvm/Target/TargetLowering.h" 54#include "llvm/Target/TargetMachine.h" 55#include "llvm/Target/TargetOptions.h" 56#include "llvm/Target/TargetRegisterInfo.h" 57#include "llvm/Target/TargetSubtargetInfo.h" 58#include "llvm/Transforms/Utils/BasicBlockUtils.h" 59#include <algorithm> 60using namespace llvm; 61 62STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 63STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 64STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 65STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 66STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 67STATISTIC(NumEntryBlocks, "Number of entry blocks encountered"); 68STATISTIC(NumFastIselFailLowerArguments, 69 "Number of entry blocks where fast isel failed to lower arguments"); 70 71#ifndef NDEBUG 72static cl::opt<bool> 73EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 74 cl::desc("Enable extra verbose messages in the \"fast\" " 75 "instruction selector")); 76 77 // Terminators 78STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 79STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 80STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 81STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 82STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 83STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 84STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 85 86 // Standard binary operators... 87STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 88STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 89STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 90STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 91STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 92STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 93STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 94STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 95STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 96STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 97STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 98STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 99 100 // Logical operators... 101STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 102STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 103STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 104 105 // Memory instructions... 106STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 107STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 108STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 109STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 110STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 111STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 112STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 113 114 // Convert instructions... 115STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 116STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 117STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 118STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 119STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 120STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 121STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 122STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 123STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 124STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 125STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 126STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 127 128 // Other instructions... 129STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 130STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 131STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 132STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 133STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 134STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 135STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 136STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 137STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 138STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 139STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 140STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 141STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 142STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 143STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 144#endif 145 146static cl::opt<bool> 147EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 148 cl::desc("Enable verbose messages in the \"fast\" " 149 "instruction selector")); 150static cl::opt<bool> 151EnableFastISelAbort("fast-isel-abort", cl::Hidden, 152 cl::desc("Enable abort calls when \"fast\" instruction selection " 153 "fails to lower an instruction")); 154static cl::opt<bool> 155EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden, 156 cl::desc("Enable abort calls when \"fast\" instruction selection " 157 "fails to lower a formal argument")); 158 159static cl::opt<bool> 160UseMBPI("use-mbpi", 161 cl::desc("use Machine Branch Probability Info"), 162 cl::init(true), cl::Hidden); 163 164#ifndef NDEBUG 165static cl::opt<bool> 166ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 167 cl::desc("Pop up a window to show dags before the first " 168 "dag combine pass")); 169static cl::opt<bool> 170ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 171 cl::desc("Pop up a window to show dags before legalize types")); 172static cl::opt<bool> 173ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 174 cl::desc("Pop up a window to show dags before legalize")); 175static cl::opt<bool> 176ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 177 cl::desc("Pop up a window to show dags before the second " 178 "dag combine pass")); 179static cl::opt<bool> 180ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 181 cl::desc("Pop up a window to show dags before the post legalize types" 182 " dag combine pass")); 183static cl::opt<bool> 184ViewISelDAGs("view-isel-dags", cl::Hidden, 185 cl::desc("Pop up a window to show isel dags as they are selected")); 186static cl::opt<bool> 187ViewSchedDAGs("view-sched-dags", cl::Hidden, 188 cl::desc("Pop up a window to show sched dags as they are processed")); 189static cl::opt<bool> 190ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 191 cl::desc("Pop up a window to show SUnit dags after they are processed")); 192#else 193static const bool ViewDAGCombine1 = false, 194 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 195 ViewDAGCombine2 = false, 196 ViewDAGCombineLT = false, 197 ViewISelDAGs = false, ViewSchedDAGs = false, 198 ViewSUnitDAGs = false; 199#endif 200 201//===---------------------------------------------------------------------===// 202/// 203/// RegisterScheduler class - Track the registration of instruction schedulers. 204/// 205//===---------------------------------------------------------------------===// 206MachinePassRegistry RegisterScheduler::Registry; 207 208//===---------------------------------------------------------------------===// 209/// 210/// ISHeuristic command line option for instruction schedulers. 211/// 212//===---------------------------------------------------------------------===// 213static cl::opt<RegisterScheduler::FunctionPassCtor, false, 214 RegisterPassParser<RegisterScheduler> > 215ISHeuristic("pre-RA-sched", 216 cl::init(&createDefaultScheduler), 217 cl::desc("Instruction schedulers available (before register" 218 " allocation):")); 219 220static RegisterScheduler 221defaultListDAGScheduler("default", "Best scheduler for the target", 222 createDefaultScheduler); 223 224namespace llvm { 225 //===--------------------------------------------------------------------===// 226 /// createDefaultScheduler - This creates an instruction scheduler appropriate 227 /// for the target. 228 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 229 CodeGenOpt::Level OptLevel) { 230 const TargetLowering *TLI = IS->getTargetLowering(); 231 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 232 233 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() || 234 TLI->getSchedulingPreference() == Sched::Source) 235 return createSourceListDAGScheduler(IS, OptLevel); 236 if (TLI->getSchedulingPreference() == Sched::RegPressure) 237 return createBURRListDAGScheduler(IS, OptLevel); 238 if (TLI->getSchedulingPreference() == Sched::Hybrid) 239 return createHybridListDAGScheduler(IS, OptLevel); 240 if (TLI->getSchedulingPreference() == Sched::VLIW) 241 return createVLIWDAGScheduler(IS, OptLevel); 242 assert(TLI->getSchedulingPreference() == Sched::ILP && 243 "Unknown sched type!"); 244 return createILPListDAGScheduler(IS, OptLevel); 245 } 246} 247 248// EmitInstrWithCustomInserter - This method should be implemented by targets 249// that mark instructions with the 'usesCustomInserter' flag. These 250// instructions are special in various ways, which require special support to 251// insert. The specified MachineInstr is created but not inserted into any 252// basic blocks, and this method is called to expand it into a sequence of 253// instructions, potentially also creating new basic blocks and control flow. 254// When new basic blocks are inserted and the edges from MBB to its successors 255// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 256// DenseMap. 257MachineBasicBlock * 258TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 259 MachineBasicBlock *MBB) const { 260#ifndef NDEBUG 261 dbgs() << "If a target marks an instruction with " 262 "'usesCustomInserter', it must implement " 263 "TargetLowering::EmitInstrWithCustomInserter!"; 264#endif 265 llvm_unreachable(0); 266} 267 268void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 269 SDNode *Node) const { 270 assert(!MI->hasPostISelHook() && 271 "If a target marks an instruction with 'hasPostISelHook', " 272 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 273} 274 275//===----------------------------------------------------------------------===// 276// SelectionDAGISel code 277//===----------------------------------------------------------------------===// 278 279SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, 280 CodeGenOpt::Level OL) : 281 MachineFunctionPass(ID), TM(tm), 282 FuncInfo(new FunctionLoweringInfo(TM)), 283 CurDAG(new SelectionDAG(tm, OL)), 284 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 285 GFI(), 286 OptLevel(OL), 287 DAGSize(0) { 288 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 289 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 290 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 291 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 292 } 293 294SelectionDAGISel::~SelectionDAGISel() { 295 delete SDB; 296 delete CurDAG; 297 delete FuncInfo; 298} 299 300void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 301 AU.addRequired<AliasAnalysis>(); 302 AU.addPreserved<AliasAnalysis>(); 303 AU.addRequired<GCModuleInfo>(); 304 AU.addPreserved<GCModuleInfo>(); 305 AU.addRequired<TargetLibraryInfo>(); 306 if (UseMBPI && OptLevel != CodeGenOpt::None) 307 AU.addRequired<BranchProbabilityInfo>(); 308 MachineFunctionPass::getAnalysisUsage(AU); 309} 310 311/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 312/// may trap on it. In this case we have to split the edge so that the path 313/// through the predecessor block that doesn't go to the phi block doesn't 314/// execute the possibly trapping instruction. 315/// 316/// This is required for correctness, so it must be done at -O0. 317/// 318static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 319 // Loop for blocks with phi nodes. 320 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 321 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 322 if (PN == 0) continue; 323 324 ReprocessBlock: 325 // For each block with a PHI node, check to see if any of the input values 326 // are potentially trapping constant expressions. Constant expressions are 327 // the only potentially trapping value that can occur as the argument to a 328 // PHI. 329 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 330 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 331 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 332 if (CE == 0 || !CE->canTrap()) continue; 333 334 // The only case we have to worry about is when the edge is critical. 335 // Since this block has a PHI Node, we assume it has multiple input 336 // edges: check to see if the pred has multiple successors. 337 BasicBlock *Pred = PN->getIncomingBlock(i); 338 if (Pred->getTerminator()->getNumSuccessors() == 1) 339 continue; 340 341 // Okay, we have to split this edge. 342 SplitCriticalEdge(Pred->getTerminator(), 343 GetSuccessorNumber(Pred, BB), SDISel, true); 344 goto ReprocessBlock; 345 } 346 } 347} 348 349bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 350 // Do some sanity-checking on the command-line options. 351 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 352 "-fast-isel-verbose requires -fast-isel"); 353 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 354 "-fast-isel-abort requires -fast-isel"); 355 356 const Function &Fn = *mf.getFunction(); 357 const TargetInstrInfo &TII = *TM.getInstrInfo(); 358 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 359 360 MF = &mf; 361 RegInfo = &MF->getRegInfo(); 362 AA = &getAnalysis<AliasAnalysis>(); 363 LibInfo = &getAnalysis<TargetLibraryInfo>(); 364 TTI = getAnalysisIfAvailable<TargetTransformInfo>(); 365 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 366 367 TargetSubtargetInfo &ST = 368 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 369 ST.resetSubtargetFeatures(MF); 370 TM.resetTargetOptions(MF); 371 372 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 373 374 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 375 376 CurDAG->init(*MF, TTI); 377 FuncInfo->set(Fn, *MF); 378 379 if (UseMBPI && OptLevel != CodeGenOpt::None) 380 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 381 else 382 FuncInfo->BPI = 0; 383 384 SDB->init(GFI, *AA, LibInfo); 385 386 MF->setHasMSInlineAsm(false); 387 SelectAllBasicBlocks(Fn); 388 389 // If the first basic block in the function has live ins that need to be 390 // copied into vregs, emit the copies into the top of the block before 391 // emitting the code for the block. 392 MachineBasicBlock *EntryMBB = MF->begin(); 393 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 394 395 DenseMap<unsigned, unsigned> LiveInMap; 396 if (!FuncInfo->ArgDbgValues.empty()) 397 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 398 E = RegInfo->livein_end(); LI != E; ++LI) 399 if (LI->second) 400 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 401 402 // Insert DBG_VALUE instructions for function arguments to the entry block. 403 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 404 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 405 bool hasFI = MI->getOperand(0).isFI(); 406 unsigned Reg = hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg(); 407 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 408 EntryMBB->insert(EntryMBB->begin(), MI); 409 else { 410 MachineInstr *Def = RegInfo->getVRegDef(Reg); 411 if (Def) { 412 MachineBasicBlock::iterator InsertPos = Def; 413 // FIXME: VR def may not be in entry block. 414 Def->getParent()->insert(llvm::next(InsertPos), MI); 415 } else 416 DEBUG(dbgs() << "Dropping debug info for dead vreg" 417 << TargetRegisterInfo::virtReg2Index(Reg) << "\n"); 418 } 419 420 // If Reg is live-in then update debug info to track its copy in a vreg. 421 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 422 if (LDI != LiveInMap.end()) { 423 assert(!hasFI && "There's no handling of frame pointer updating here yet " 424 "- add if needed"); 425 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 426 MachineBasicBlock::iterator InsertPos = Def; 427 const MDNode *Variable = 428 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 429 bool IsIndirect = MI->isIndirectDebugValue(); 430 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; 431 // Def is never a terminator here, so it is ok to increment InsertPos. 432 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 433 TII.get(TargetOpcode::DBG_VALUE), 434 IsIndirect, 435 LDI->second, Offset, Variable); 436 437 // If this vreg is directly copied into an exported register then 438 // that COPY instructions also need DBG_VALUE, if it is the only 439 // user of LDI->second. 440 MachineInstr *CopyUseMI = NULL; 441 for (MachineRegisterInfo::use_iterator 442 UI = RegInfo->use_begin(LDI->second); 443 MachineInstr *UseMI = UI.skipInstruction();) { 444 if (UseMI->isDebugValue()) continue; 445 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 446 CopyUseMI = UseMI; continue; 447 } 448 // Otherwise this is another use or second copy use. 449 CopyUseMI = NULL; break; 450 } 451 if (CopyUseMI) { 452 MachineInstr *NewMI = 453 BuildMI(*MF, CopyUseMI->getDebugLoc(), 454 TII.get(TargetOpcode::DBG_VALUE), 455 IsIndirect, 456 CopyUseMI->getOperand(0).getReg(), 457 Offset, Variable); 458 MachineBasicBlock::iterator Pos = CopyUseMI; 459 EntryMBB->insertAfter(Pos, NewMI); 460 } 461 } 462 } 463 464 // Determine if there are any calls in this machine function. 465 MachineFrameInfo *MFI = MF->getFrameInfo(); 466 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E; 467 ++I) { 468 469 if (MFI->hasCalls() && MF->hasMSInlineAsm()) 470 break; 471 472 const MachineBasicBlock *MBB = I; 473 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end(); 474 II != IE; ++II) { 475 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 476 if ((MCID.isCall() && !MCID.isReturn()) || 477 II->isStackAligningInlineAsm()) { 478 MFI->setHasCalls(true); 479 } 480 if (II->isMSInlineAsm()) { 481 MF->setHasMSInlineAsm(true); 482 } 483 } 484 } 485 486 // Determine if there is a call to setjmp in the machine function. 487 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 488 489 // Replace forward-declared registers with the registers containing 490 // the desired value. 491 MachineRegisterInfo &MRI = MF->getRegInfo(); 492 for (DenseMap<unsigned, unsigned>::iterator 493 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 494 I != E; ++I) { 495 unsigned From = I->first; 496 unsigned To = I->second; 497 // If To is also scheduled to be replaced, find what its ultimate 498 // replacement is. 499 for (;;) { 500 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 501 if (J == E) break; 502 To = J->second; 503 } 504 // Make sure the new register has a sufficiently constrained register class. 505 if (TargetRegisterInfo::isVirtualRegister(From) && 506 TargetRegisterInfo::isVirtualRegister(To)) 507 MRI.constrainRegClass(To, MRI.getRegClass(From)); 508 // Replace it. 509 MRI.replaceRegWith(From, To); 510 } 511 512 // Freeze the set of reserved registers now that MachineFrameInfo has been 513 // set up. All the information required by getReservedRegs() should be 514 // available now. 515 MRI.freezeReservedRegs(*MF); 516 517 // Release function-specific state. SDB and CurDAG are already cleared 518 // at this point. 519 FuncInfo->clear(); 520 521 return true; 522} 523 524void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 525 BasicBlock::const_iterator End, 526 bool &HadTailCall) { 527 // Lower all of the non-terminator instructions. If a call is emitted 528 // as a tail call, cease emitting nodes for this block. Terminators 529 // are handled below. 530 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 531 SDB->visit(*I); 532 533 // Make sure the root of the DAG is up-to-date. 534 CurDAG->setRoot(SDB->getControlRoot()); 535 HadTailCall = SDB->HasTailCall; 536 SDB->clear(); 537 538 // Final step, emit the lowered DAG as machine code. 539 CodeGenAndEmitDAG(); 540} 541 542void SelectionDAGISel::ComputeLiveOutVRegInfo() { 543 SmallPtrSet<SDNode*, 128> VisitedNodes; 544 SmallVector<SDNode*, 128> Worklist; 545 546 Worklist.push_back(CurDAG->getRoot().getNode()); 547 548 APInt KnownZero; 549 APInt KnownOne; 550 551 do { 552 SDNode *N = Worklist.pop_back_val(); 553 554 // If we've already seen this node, ignore it. 555 if (!VisitedNodes.insert(N)) 556 continue; 557 558 // Otherwise, add all chain operands to the worklist. 559 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 560 if (N->getOperand(i).getValueType() == MVT::Other) 561 Worklist.push_back(N->getOperand(i).getNode()); 562 563 // If this is a CopyToReg with a vreg dest, process it. 564 if (N->getOpcode() != ISD::CopyToReg) 565 continue; 566 567 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 568 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 569 continue; 570 571 // Ignore non-scalar or non-integer values. 572 SDValue Src = N->getOperand(2); 573 EVT SrcVT = Src.getValueType(); 574 if (!SrcVT.isInteger() || SrcVT.isVector()) 575 continue; 576 577 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 578 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 579 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 580 } while (!Worklist.empty()); 581} 582 583void SelectionDAGISel::CodeGenAndEmitDAG() { 584 std::string GroupName; 585 if (TimePassesIsEnabled) 586 GroupName = "Instruction Selection and Scheduling"; 587 std::string BlockName; 588 int BlockNumber = -1; 589 (void)BlockNumber; 590#ifdef NDEBUG 591 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 592 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 593 ViewSUnitDAGs) 594#endif 595 { 596 BlockNumber = FuncInfo->MBB->getNumber(); 597 BlockName = MF->getName().str() + ":" + 598 FuncInfo->MBB->getBasicBlock()->getName().str(); 599 } 600 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 601 << " '" << BlockName << "'\n"; CurDAG->dump()); 602 603 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 604 605 // Run the DAG combiner in pre-legalize mode. 606 { 607 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 608 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 609 } 610 611 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 612 << " '" << BlockName << "'\n"; CurDAG->dump()); 613 614 // Second step, hack on the DAG until it only uses operations and types that 615 // the target supports. 616 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 617 BlockName); 618 619 bool Changed; 620 { 621 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 622 Changed = CurDAG->LegalizeTypes(); 623 } 624 625 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 626 << " '" << BlockName << "'\n"; CurDAG->dump()); 627 628 if (Changed) { 629 if (ViewDAGCombineLT) 630 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 631 632 // Run the DAG combiner in post-type-legalize mode. 633 { 634 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 635 TimePassesIsEnabled); 636 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 637 } 638 639 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 640 << " '" << BlockName << "'\n"; CurDAG->dump()); 641 642 } 643 644 { 645 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 646 Changed = CurDAG->LegalizeVectors(); 647 } 648 649 if (Changed) { 650 { 651 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 652 CurDAG->LegalizeTypes(); 653 } 654 655 if (ViewDAGCombineLT) 656 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 657 658 // Run the DAG combiner in post-type-legalize mode. 659 { 660 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 661 TimePassesIsEnabled); 662 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 663 } 664 665 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 666 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 667 } 668 669 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 670 671 { 672 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 673 CurDAG->Legalize(); 674 } 675 676 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 677 << " '" << BlockName << "'\n"; CurDAG->dump()); 678 679 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 680 681 // Run the DAG combiner in post-legalize mode. 682 { 683 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 684 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 685 } 686 687 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 688 << " '" << BlockName << "'\n"; CurDAG->dump()); 689 690 if (OptLevel != CodeGenOpt::None) 691 ComputeLiveOutVRegInfo(); 692 693 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 694 695 // Third, instruction select all of the operations to machine code, adding the 696 // code to the MachineBasicBlock. 697 { 698 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 699 DoInstructionSelection(); 700 } 701 702 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 703 << " '" << BlockName << "'\n"; CurDAG->dump()); 704 705 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 706 707 // Schedule machine code. 708 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 709 { 710 NamedRegionTimer T("Instruction Scheduling", GroupName, 711 TimePassesIsEnabled); 712 Scheduler->Run(CurDAG, FuncInfo->MBB); 713 } 714 715 if (ViewSUnitDAGs) Scheduler->viewGraph(); 716 717 // Emit machine code to BB. This can change 'BB' to the last block being 718 // inserted into. 719 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 720 { 721 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 722 723 // FuncInfo->InsertPt is passed by reference and set to the end of the 724 // scheduled instructions. 725 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 726 } 727 728 // If the block was split, make sure we update any references that are used to 729 // update PHI nodes later on. 730 if (FirstMBB != LastMBB) 731 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 732 733 // Free the scheduler state. 734 { 735 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 736 TimePassesIsEnabled); 737 delete Scheduler; 738 } 739 740 // Free the SelectionDAG state, now that we're finished with it. 741 CurDAG->clear(); 742} 743 744namespace { 745/// ISelUpdater - helper class to handle updates of the instruction selection 746/// graph. 747class ISelUpdater : public SelectionDAG::DAGUpdateListener { 748 SelectionDAG::allnodes_iterator &ISelPosition; 749public: 750 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 751 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 752 753 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 754 /// deleted is the current ISelPosition node, update ISelPosition. 755 /// 756 virtual void NodeDeleted(SDNode *N, SDNode *E) { 757 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 758 ++ISelPosition; 759 } 760}; 761} // end anonymous namespace 762 763void SelectionDAGISel::DoInstructionSelection() { 764 DEBUG(dbgs() << "===== Instruction selection begins: BB#" 765 << FuncInfo->MBB->getNumber() 766 << " '" << FuncInfo->MBB->getName() << "'\n"); 767 768 PreprocessISelDAG(); 769 770 // Select target instructions for the DAG. 771 { 772 // Number all nodes with a topological order and set DAGSize. 773 DAGSize = CurDAG->AssignTopologicalOrder(); 774 775 // Create a dummy node (which is not added to allnodes), that adds 776 // a reference to the root node, preventing it from being deleted, 777 // and tracking any changes of the root. 778 HandleSDNode Dummy(CurDAG->getRoot()); 779 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 780 ++ISelPosition; 781 782 // Make sure that ISelPosition gets properly updated when nodes are deleted 783 // in calls made from this function. 784 ISelUpdater ISU(*CurDAG, ISelPosition); 785 786 // The AllNodes list is now topological-sorted. Visit the 787 // nodes by starting at the end of the list (the root of the 788 // graph) and preceding back toward the beginning (the entry 789 // node). 790 while (ISelPosition != CurDAG->allnodes_begin()) { 791 SDNode *Node = --ISelPosition; 792 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 793 // but there are currently some corner cases that it misses. Also, this 794 // makes it theoretically possible to disable the DAGCombiner. 795 if (Node->use_empty()) 796 continue; 797 798 SDNode *ResNode = Select(Node); 799 800 // FIXME: This is pretty gross. 'Select' should be changed to not return 801 // anything at all and this code should be nuked with a tactical strike. 802 803 // If node should not be replaced, continue with the next one. 804 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 805 continue; 806 // Replace node. 807 if (ResNode) { 808 ReplaceUses(Node, ResNode); 809 } 810 811 // If after the replacement this node is not used any more, 812 // remove this dead node. 813 if (Node->use_empty()) // Don't delete EntryToken, etc. 814 CurDAG->RemoveDeadNode(Node); 815 } 816 817 CurDAG->setRoot(Dummy.getValue()); 818 } 819 820 DEBUG(dbgs() << "===== Instruction selection ends:\n"); 821 822 PostprocessISelDAG(); 823} 824 825/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 826/// do other setup for EH landing-pad blocks. 827void SelectionDAGISel::PrepareEHLandingPad() { 828 MachineBasicBlock *MBB = FuncInfo->MBB; 829 830 // Add a label to mark the beginning of the landing pad. Deletion of the 831 // landing pad can thus be detected via the MachineModuleInfo. 832 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 833 834 // Assign the call site to the landing pad's begin label. 835 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 836 837 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 838 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 839 .addSym(Label); 840 841 // Mark exception register as live in. 842 const TargetLowering *TLI = getTargetLowering(); 843 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy()); 844 if (unsigned Reg = TLI->getExceptionPointerRegister()) 845 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC); 846 847 // Mark exception selector register as live in. 848 if (unsigned Reg = TLI->getExceptionSelectorRegister()) 849 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC); 850} 851 852/// isFoldedOrDeadInstruction - Return true if the specified instruction is 853/// side-effect free and is either dead or folded into a generated instruction. 854/// Return false if it needs to be emitted. 855static bool isFoldedOrDeadInstruction(const Instruction *I, 856 FunctionLoweringInfo *FuncInfo) { 857 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 858 !isa<TerminatorInst>(I) && // Terminators aren't folded. 859 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 860 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 861 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 862} 863 864#ifndef NDEBUG 865// Collect per Instruction statistics for fast-isel misses. Only those 866// instructions that cause the bail are accounted for. It does not account for 867// instructions higher in the block. Thus, summing the per instructions stats 868// will not add up to what is reported by NumFastIselFailures. 869static void collectFailStats(const Instruction *I) { 870 switch (I->getOpcode()) { 871 default: assert (0 && "<Invalid operator> "); 872 873 // Terminators 874 case Instruction::Ret: NumFastIselFailRet++; return; 875 case Instruction::Br: NumFastIselFailBr++; return; 876 case Instruction::Switch: NumFastIselFailSwitch++; return; 877 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 878 case Instruction::Invoke: NumFastIselFailInvoke++; return; 879 case Instruction::Resume: NumFastIselFailResume++; return; 880 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 881 882 // Standard binary operators... 883 case Instruction::Add: NumFastIselFailAdd++; return; 884 case Instruction::FAdd: NumFastIselFailFAdd++; return; 885 case Instruction::Sub: NumFastIselFailSub++; return; 886 case Instruction::FSub: NumFastIselFailFSub++; return; 887 case Instruction::Mul: NumFastIselFailMul++; return; 888 case Instruction::FMul: NumFastIselFailFMul++; return; 889 case Instruction::UDiv: NumFastIselFailUDiv++; return; 890 case Instruction::SDiv: NumFastIselFailSDiv++; return; 891 case Instruction::FDiv: NumFastIselFailFDiv++; return; 892 case Instruction::URem: NumFastIselFailURem++; return; 893 case Instruction::SRem: NumFastIselFailSRem++; return; 894 case Instruction::FRem: NumFastIselFailFRem++; return; 895 896 // Logical operators... 897 case Instruction::And: NumFastIselFailAnd++; return; 898 case Instruction::Or: NumFastIselFailOr++; return; 899 case Instruction::Xor: NumFastIselFailXor++; return; 900 901 // Memory instructions... 902 case Instruction::Alloca: NumFastIselFailAlloca++; return; 903 case Instruction::Load: NumFastIselFailLoad++; return; 904 case Instruction::Store: NumFastIselFailStore++; return; 905 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 906 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 907 case Instruction::Fence: NumFastIselFailFence++; return; 908 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 909 910 // Convert instructions... 911 case Instruction::Trunc: NumFastIselFailTrunc++; return; 912 case Instruction::ZExt: NumFastIselFailZExt++; return; 913 case Instruction::SExt: NumFastIselFailSExt++; return; 914 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 915 case Instruction::FPExt: NumFastIselFailFPExt++; return; 916 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 917 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 918 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 919 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 920 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 921 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 922 case Instruction::BitCast: NumFastIselFailBitCast++; return; 923 924 // Other instructions... 925 case Instruction::ICmp: NumFastIselFailICmp++; return; 926 case Instruction::FCmp: NumFastIselFailFCmp++; return; 927 case Instruction::PHI: NumFastIselFailPHI++; return; 928 case Instruction::Select: NumFastIselFailSelect++; return; 929 case Instruction::Call: NumFastIselFailCall++; return; 930 case Instruction::Shl: NumFastIselFailShl++; return; 931 case Instruction::LShr: NumFastIselFailLShr++; return; 932 case Instruction::AShr: NumFastIselFailAShr++; return; 933 case Instruction::VAArg: NumFastIselFailVAArg++; return; 934 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 935 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 936 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 937 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 938 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 939 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 940 } 941} 942#endif 943 944void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 945 // Initialize the Fast-ISel state, if needed. 946 FastISel *FastIS = 0; 947 if (TM.Options.EnableFastISel) 948 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo); 949 950 // Iterate over all basic blocks in the function. 951 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 952 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 953 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 954 const BasicBlock *LLVMBB = *I; 955 956 if (OptLevel != CodeGenOpt::None) { 957 bool AllPredsVisited = true; 958 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 959 PI != PE; ++PI) { 960 if (!FuncInfo->VisitedBBs.count(*PI)) { 961 AllPredsVisited = false; 962 break; 963 } 964 } 965 966 if (AllPredsVisited) { 967 for (BasicBlock::const_iterator I = LLVMBB->begin(); 968 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 969 FuncInfo->ComputePHILiveOutRegInfo(PN); 970 } else { 971 for (BasicBlock::const_iterator I = LLVMBB->begin(); 972 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 973 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 974 } 975 976 FuncInfo->VisitedBBs.insert(LLVMBB); 977 } 978 979 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 980 BasicBlock::const_iterator const End = LLVMBB->end(); 981 BasicBlock::const_iterator BI = End; 982 983 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 984 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 985 986 // Setup an EH landing-pad block. 987 FuncInfo->ExceptionPointerVirtReg = 0; 988 FuncInfo->ExceptionSelectorVirtReg = 0; 989 if (FuncInfo->MBB->isLandingPad()) 990 PrepareEHLandingPad(); 991 992 // Before doing SelectionDAG ISel, see if FastISel has been requested. 993 if (FastIS) { 994 FastIS->startNewBlock(); 995 996 // Emit code for any incoming arguments. This must happen before 997 // beginning FastISel on the entry block. 998 if (LLVMBB == &Fn.getEntryBlock()) { 999 ++NumEntryBlocks; 1000 1001 // Lower any arguments needed in this block if this is the entry block. 1002 if (!FastIS->LowerArguments()) { 1003 // Fast isel failed to lower these arguments 1004 ++NumFastIselFailLowerArguments; 1005 if (EnableFastISelAbortArgs) 1006 llvm_unreachable("FastISel didn't lower all arguments"); 1007 1008 // Use SelectionDAG argument lowering 1009 LowerArguments(Fn); 1010 CurDAG->setRoot(SDB->getControlRoot()); 1011 SDB->clear(); 1012 CodeGenAndEmitDAG(); 1013 } 1014 1015 // If we inserted any instructions at the beginning, make a note of 1016 // where they are, so we can be sure to emit subsequent instructions 1017 // after them. 1018 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1019 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 1020 else 1021 FastIS->setLastLocalValue(0); 1022 } 1023 1024 unsigned NumFastIselRemaining = std::distance(Begin, End); 1025 // Do FastISel on as many instructions as possible. 1026 for (; BI != Begin; --BI) { 1027 const Instruction *Inst = llvm::prior(BI); 1028 1029 // If we no longer require this instruction, skip it. 1030 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1031 --NumFastIselRemaining; 1032 continue; 1033 } 1034 1035 // Bottom-up: reset the insert pos at the top, after any local-value 1036 // instructions. 1037 FastIS->recomputeInsertPt(); 1038 1039 // Try to select the instruction with FastISel. 1040 if (FastIS->SelectInstruction(Inst)) { 1041 --NumFastIselRemaining; 1042 ++NumFastIselSuccess; 1043 // If fast isel succeeded, skip over all the folded instructions, and 1044 // then see if there is a load right before the selected instructions. 1045 // Try to fold the load if so. 1046 const Instruction *BeforeInst = Inst; 1047 while (BeforeInst != Begin) { 1048 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 1049 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1050 break; 1051 } 1052 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1053 BeforeInst->hasOneUse() && 1054 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) { 1055 // If we succeeded, don't re-select the load. 1056 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 1057 --NumFastIselRemaining; 1058 ++NumFastIselSuccess; 1059 } 1060 continue; 1061 } 1062 1063#ifndef NDEBUG 1064 if (EnableFastISelVerbose2) 1065 collectFailStats(Inst); 1066#endif 1067 1068 // Then handle certain instructions as single-LLVM-Instruction blocks. 1069 if (isa<CallInst>(Inst)) { 1070 1071 if (EnableFastISelVerbose || EnableFastISelAbort) { 1072 dbgs() << "FastISel missed call: "; 1073 Inst->dump(); 1074 } 1075 1076 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1077 unsigned &R = FuncInfo->ValueMap[Inst]; 1078 if (!R) 1079 R = FuncInfo->CreateRegs(Inst->getType()); 1080 } 1081 1082 bool HadTailCall = false; 1083 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1084 SelectBasicBlock(Inst, BI, HadTailCall); 1085 1086 // If the call was emitted as a tail call, we're done with the block. 1087 // We also need to delete any previously emitted instructions. 1088 if (HadTailCall) { 1089 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1090 --BI; 1091 break; 1092 } 1093 1094 // Recompute NumFastIselRemaining as Selection DAG instruction 1095 // selection may have handled the call, input args, etc. 1096 unsigned RemainingNow = std::distance(Begin, BI); 1097 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1098 NumFastIselRemaining = RemainingNow; 1099 continue; 1100 } 1101 1102 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1103 // Don't abort, and use a different message for terminator misses. 1104 NumFastIselFailures += NumFastIselRemaining; 1105 if (EnableFastISelVerbose || EnableFastISelAbort) { 1106 dbgs() << "FastISel missed terminator: "; 1107 Inst->dump(); 1108 } 1109 } else { 1110 NumFastIselFailures += NumFastIselRemaining; 1111 if (EnableFastISelVerbose || EnableFastISelAbort) { 1112 dbgs() << "FastISel miss: "; 1113 Inst->dump(); 1114 } 1115 if (EnableFastISelAbort) 1116 // The "fast" selector couldn't handle something and bailed. 1117 // For the purpose of debugging, just abort. 1118 llvm_unreachable("FastISel didn't select the entire block"); 1119 } 1120 break; 1121 } 1122 1123 FastIS->recomputeInsertPt(); 1124 } else { 1125 // Lower any arguments needed in this block if this is the entry block. 1126 if (LLVMBB == &Fn.getEntryBlock()) { 1127 ++NumEntryBlocks; 1128 LowerArguments(Fn); 1129 } 1130 } 1131 1132 if (Begin != BI) 1133 ++NumDAGBlocks; 1134 else 1135 ++NumFastIselBlocks; 1136 1137 if (Begin != BI) { 1138 // Run SelectionDAG instruction selection on the remainder of the block 1139 // not handled by FastISel. If FastISel is not run, this is the entire 1140 // block. 1141 bool HadTailCall; 1142 SelectBasicBlock(Begin, BI, HadTailCall); 1143 } 1144 1145 FinishBasicBlock(); 1146 FuncInfo->PHINodesToUpdate.clear(); 1147 } 1148 1149 delete FastIS; 1150 SDB->clearDanglingDebugInfo(); 1151 SDB->SPDescriptor.resetPerFunctionState(); 1152} 1153 1154/// Given that the input MI is before a partial terminator sequence TSeq, return 1155/// true if M + TSeq also a partial terminator sequence. 1156/// 1157/// A Terminator sequence is a sequence of MachineInstrs which at this point in 1158/// lowering copy vregs into physical registers, which are then passed into 1159/// terminator instructors so we can satisfy ABI constraints. A partial 1160/// terminator sequence is an improper subset of a terminator sequence (i.e. it 1161/// may be the whole terminator sequence). 1162static bool MIIsInTerminatorSequence(const MachineInstr *MI) { 1163 // If we do not have a copy or an implicit def, we return true if and only if 1164 // MI is a debug value. 1165 if (!MI->isCopy() && !MI->isImplicitDef()) 1166 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the 1167 // physical registers if there is debug info associated with the terminator 1168 // of our mbb. We want to include said debug info in our terminator 1169 // sequence, so we return true in that case. 1170 return MI->isDebugValue(); 1171 1172 // We have left the terminator sequence if we are not doing one of the 1173 // following: 1174 // 1175 // 1. Copying a vreg into a physical register. 1176 // 2. Copying a vreg into a vreg. 1177 // 3. Defining a register via an implicit def. 1178 1179 // OPI should always be a register definition... 1180 MachineInstr::const_mop_iterator OPI = MI->operands_begin(); 1181 if (!OPI->isReg() || !OPI->isDef()) 1182 return false; 1183 1184 // Defining any register via an implicit def is always ok. 1185 if (MI->isImplicitDef()) 1186 return true; 1187 1188 // Grab the copy source... 1189 MachineInstr::const_mop_iterator OPI2 = OPI; 1190 ++OPI2; 1191 assert(OPI2 != MI->operands_end() 1192 && "Should have a copy implying we should have 2 arguments."); 1193 1194 // Make sure that the copy dest is not a vreg when the copy source is a 1195 // physical register. 1196 if (!OPI2->isReg() || 1197 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) && 1198 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg()))) 1199 return false; 1200 1201 return true; 1202} 1203 1204/// Find the split point at which to splice the end of BB into its success stack 1205/// protector check machine basic block. 1206/// 1207/// On many platforms, due to ABI constraints, terminators, even before register 1208/// allocation, use physical registers. This creates an issue for us since 1209/// physical registers at this point can not travel across basic 1210/// blocks. Luckily, selectiondag always moves physical registers into vregs 1211/// when they enter functions and moves them through a sequence of copies back 1212/// into the physical registers right before the terminator creating a 1213/// ``Terminator Sequence''. This function is searching for the beginning of the 1214/// terminator sequence so that we can ensure that we splice off not just the 1215/// terminator, but additionally the copies that move the vregs into the 1216/// physical registers. 1217static MachineBasicBlock::iterator 1218FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) { 1219 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator(); 1220 // 1221 if (SplitPoint == BB->begin()) 1222 return SplitPoint; 1223 1224 MachineBasicBlock::iterator Start = BB->begin(); 1225 MachineBasicBlock::iterator Previous = SplitPoint; 1226 --Previous; 1227 1228 while (MIIsInTerminatorSequence(Previous)) { 1229 SplitPoint = Previous; 1230 if (Previous == Start) 1231 break; 1232 --Previous; 1233 } 1234 1235 return SplitPoint; 1236} 1237 1238void 1239SelectionDAGISel::FinishBasicBlock() { 1240 1241 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1242 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1243 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1244 dbgs() << "Node " << i << " : (" 1245 << FuncInfo->PHINodesToUpdate[i].first 1246 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1247 1248 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() && 1249 SDB->JTCases.empty() && 1250 SDB->BitTestCases.empty(); 1251 1252 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1253 // PHI nodes in successors. 1254 if (MustUpdatePHINodes) { 1255 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1256 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1257 assert(PHI->isPHI() && 1258 "This is not a machine PHI node that we are updating!"); 1259 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1260 continue; 1261 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1262 } 1263 } 1264 1265 // Handle stack protector. 1266 if (SDB->SPDescriptor.shouldEmitStackProtector()) { 1267 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB(); 1268 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB(); 1269 1270 // Find the split point to split the parent mbb. At the same time copy all 1271 // physical registers used in the tail of parent mbb into virtual registers 1272 // before the split point and back into physical registers after the split 1273 // point. This prevents us needing to deal with Live-ins and many other 1274 // register allocation issues caused by us splitting the parent mbb. The 1275 // register allocator will clean up said virtual copies later on. 1276 MachineBasicBlock::iterator SplitPoint = 1277 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc()); 1278 1279 // Splice the terminator of ParentMBB into SuccessMBB. 1280 SuccessMBB->splice(SuccessMBB->end(), ParentMBB, 1281 SplitPoint, 1282 ParentMBB->end()); 1283 1284 // Add compare/jump on neq/jump to the parent BB. 1285 FuncInfo->MBB = ParentMBB; 1286 FuncInfo->InsertPt = ParentMBB->end(); 1287 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB); 1288 CurDAG->setRoot(SDB->getRoot()); 1289 SDB->clear(); 1290 CodeGenAndEmitDAG(); 1291 1292 // CodeGen Failure MBB if we have not codegened it yet. 1293 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB(); 1294 if (!FailureMBB->size()) { 1295 FuncInfo->MBB = FailureMBB; 1296 FuncInfo->InsertPt = FailureMBB->end(); 1297 SDB->visitSPDescriptorFailure(SDB->SPDescriptor); 1298 CurDAG->setRoot(SDB->getRoot()); 1299 SDB->clear(); 1300 CodeGenAndEmitDAG(); 1301 } 1302 1303 // Clear the Per-BB State. 1304 SDB->SPDescriptor.resetPerBBState(); 1305 } 1306 1307 // If we updated PHI Nodes, return early. 1308 if (MustUpdatePHINodes) 1309 return; 1310 1311 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1312 // Lower header first, if it wasn't already lowered 1313 if (!SDB->BitTestCases[i].Emitted) { 1314 // Set the current basic block to the mbb we wish to insert the code into 1315 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1316 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1317 // Emit the code 1318 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1319 CurDAG->setRoot(SDB->getRoot()); 1320 SDB->clear(); 1321 CodeGenAndEmitDAG(); 1322 } 1323 1324 uint32_t UnhandledWeight = 0; 1325 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1326 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1327 1328 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1329 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1330 // Set the current basic block to the mbb we wish to insert the code into 1331 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1332 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1333 // Emit the code 1334 if (j+1 != ej) 1335 SDB->visitBitTestCase(SDB->BitTestCases[i], 1336 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1337 UnhandledWeight, 1338 SDB->BitTestCases[i].Reg, 1339 SDB->BitTestCases[i].Cases[j], 1340 FuncInfo->MBB); 1341 else 1342 SDB->visitBitTestCase(SDB->BitTestCases[i], 1343 SDB->BitTestCases[i].Default, 1344 UnhandledWeight, 1345 SDB->BitTestCases[i].Reg, 1346 SDB->BitTestCases[i].Cases[j], 1347 FuncInfo->MBB); 1348 1349 1350 CurDAG->setRoot(SDB->getRoot()); 1351 SDB->clear(); 1352 CodeGenAndEmitDAG(); 1353 } 1354 1355 // Update PHI Nodes 1356 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1357 pi != pe; ++pi) { 1358 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1359 MachineBasicBlock *PHIBB = PHI->getParent(); 1360 assert(PHI->isPHI() && 1361 "This is not a machine PHI node that we are updating!"); 1362 // This is "default" BB. We have two jumps to it. From "header" BB and 1363 // from last "case" BB. 1364 if (PHIBB == SDB->BitTestCases[i].Default) 1365 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1366 .addMBB(SDB->BitTestCases[i].Parent) 1367 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1368 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1369 // One of "cases" BB. 1370 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1371 j != ej; ++j) { 1372 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1373 if (cBB->isSuccessor(PHIBB)) 1374 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1375 } 1376 } 1377 } 1378 SDB->BitTestCases.clear(); 1379 1380 // If the JumpTable record is filled in, then we need to emit a jump table. 1381 // Updating the PHI nodes is tricky in this case, since we need to determine 1382 // whether the PHI is a successor of the range check MBB or the jump table MBB 1383 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1384 // Lower header first, if it wasn't already lowered 1385 if (!SDB->JTCases[i].first.Emitted) { 1386 // Set the current basic block to the mbb we wish to insert the code into 1387 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1388 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1389 // Emit the code 1390 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1391 FuncInfo->MBB); 1392 CurDAG->setRoot(SDB->getRoot()); 1393 SDB->clear(); 1394 CodeGenAndEmitDAG(); 1395 } 1396 1397 // Set the current basic block to the mbb we wish to insert the code into 1398 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1399 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1400 // Emit the code 1401 SDB->visitJumpTable(SDB->JTCases[i].second); 1402 CurDAG->setRoot(SDB->getRoot()); 1403 SDB->clear(); 1404 CodeGenAndEmitDAG(); 1405 1406 // Update PHI Nodes 1407 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1408 pi != pe; ++pi) { 1409 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1410 MachineBasicBlock *PHIBB = PHI->getParent(); 1411 assert(PHI->isPHI() && 1412 "This is not a machine PHI node that we are updating!"); 1413 // "default" BB. We can go there only from header BB. 1414 if (PHIBB == SDB->JTCases[i].second.Default) 1415 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1416 .addMBB(SDB->JTCases[i].first.HeaderBB); 1417 // JT BB. Just iterate over successors here 1418 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1419 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1420 } 1421 } 1422 SDB->JTCases.clear(); 1423 1424 // If the switch block involved a branch to one of the actual successors, we 1425 // need to update PHI nodes in that block. 1426 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1427 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1428 assert(PHI->isPHI() && 1429 "This is not a machine PHI node that we are updating!"); 1430 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 1431 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1432 } 1433 1434 // If we generated any switch lowering information, build and codegen any 1435 // additional DAGs necessary. 1436 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1437 // Set the current basic block to the mbb we wish to insert the code into 1438 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1439 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1440 1441 // Determine the unique successors. 1442 SmallVector<MachineBasicBlock *, 2> Succs; 1443 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1444 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1445 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1446 1447 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1448 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1449 CurDAG->setRoot(SDB->getRoot()); 1450 SDB->clear(); 1451 CodeGenAndEmitDAG(); 1452 1453 // Remember the last block, now that any splitting is done, for use in 1454 // populating PHI nodes in successors. 1455 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1456 1457 // Handle any PHI nodes in successors of this chunk, as if we were coming 1458 // from the original BB before switch expansion. Note that PHI nodes can 1459 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1460 // handle them the right number of times. 1461 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1462 FuncInfo->MBB = Succs[i]; 1463 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1464 // FuncInfo->MBB may have been removed from the CFG if a branch was 1465 // constant folded. 1466 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1467 for (MachineBasicBlock::iterator 1468 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1469 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1470 MachineInstrBuilder PHI(*MF, MBBI); 1471 // This value for this PHI node is recorded in PHINodesToUpdate. 1472 for (unsigned pn = 0; ; ++pn) { 1473 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1474 "Didn't find PHI entry!"); 1475 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1476 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1477 break; 1478 } 1479 } 1480 } 1481 } 1482 } 1483 } 1484 SDB->SwitchCases.clear(); 1485} 1486 1487 1488/// Create the scheduler. If a specific scheduler was specified 1489/// via the SchedulerRegistry, use it, otherwise select the 1490/// one preferred by the target. 1491/// 1492ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1493 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1494 1495 if (!Ctor) { 1496 Ctor = ISHeuristic; 1497 RegisterScheduler::setDefault(Ctor); 1498 } 1499 1500 return Ctor(this, OptLevel); 1501} 1502 1503//===----------------------------------------------------------------------===// 1504// Helper functions used by the generated instruction selector. 1505//===----------------------------------------------------------------------===// 1506// Calls to these methods are generated by tblgen. 1507 1508/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1509/// the dag combiner simplified the 255, we still want to match. RHS is the 1510/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1511/// specified in the .td file (e.g. 255). 1512bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1513 int64_t DesiredMaskS) const { 1514 const APInt &ActualMask = RHS->getAPIntValue(); 1515 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1516 1517 // If the actual mask exactly matches, success! 1518 if (ActualMask == DesiredMask) 1519 return true; 1520 1521 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1522 if (ActualMask.intersects(~DesiredMask)) 1523 return false; 1524 1525 // Otherwise, the DAG Combiner may have proven that the value coming in is 1526 // either already zero or is not demanded. Check for known zero input bits. 1527 APInt NeededMask = DesiredMask & ~ActualMask; 1528 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1529 return true; 1530 1531 // TODO: check to see if missing bits are just not demanded. 1532 1533 // Otherwise, this pattern doesn't match. 1534 return false; 1535} 1536 1537/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1538/// the dag combiner simplified the 255, we still want to match. RHS is the 1539/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1540/// specified in the .td file (e.g. 255). 1541bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1542 int64_t DesiredMaskS) const { 1543 const APInt &ActualMask = RHS->getAPIntValue(); 1544 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1545 1546 // If the actual mask exactly matches, success! 1547 if (ActualMask == DesiredMask) 1548 return true; 1549 1550 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1551 if (ActualMask.intersects(~DesiredMask)) 1552 return false; 1553 1554 // Otherwise, the DAG Combiner may have proven that the value coming in is 1555 // either already zero or is not demanded. Check for known zero input bits. 1556 APInt NeededMask = DesiredMask & ~ActualMask; 1557 1558 APInt KnownZero, KnownOne; 1559 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 1560 1561 // If all the missing bits in the or are already known to be set, match! 1562 if ((NeededMask & KnownOne) == NeededMask) 1563 return true; 1564 1565 // TODO: check to see if missing bits are just not demanded. 1566 1567 // Otherwise, this pattern doesn't match. 1568 return false; 1569} 1570 1571 1572/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1573/// by tblgen. Others should not call it. 1574void SelectionDAGISel:: 1575SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1576 std::vector<SDValue> InOps; 1577 std::swap(InOps, Ops); 1578 1579 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1580 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1581 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1582 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1583 1584 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1585 if (InOps[e-1].getValueType() == MVT::Glue) 1586 --e; // Don't process a glue operand if it is here. 1587 1588 while (i != e) { 1589 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1590 if (!InlineAsm::isMemKind(Flags)) { 1591 // Just skip over this operand, copying the operands verbatim. 1592 Ops.insert(Ops.end(), InOps.begin()+i, 1593 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1594 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1595 } else { 1596 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1597 "Memory operand with multiple values?"); 1598 // Otherwise, this is a memory operand. Ask the target to select it. 1599 std::vector<SDValue> SelOps; 1600 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1601 report_fatal_error("Could not match memory address. Inline asm" 1602 " failure!"); 1603 1604 // Add this to the output node. 1605 unsigned NewFlags = 1606 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1607 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1608 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1609 i += 2; 1610 } 1611 } 1612 1613 // Add the glue input back if present. 1614 if (e != InOps.size()) 1615 Ops.push_back(InOps.back()); 1616} 1617 1618/// findGlueUse - Return use of MVT::Glue value produced by the specified 1619/// SDNode. 1620/// 1621static SDNode *findGlueUse(SDNode *N) { 1622 unsigned FlagResNo = N->getNumValues()-1; 1623 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1624 SDUse &Use = I.getUse(); 1625 if (Use.getResNo() == FlagResNo) 1626 return Use.getUser(); 1627 } 1628 return NULL; 1629} 1630 1631/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1632/// This function recursively traverses up the operand chain, ignoring 1633/// certain nodes. 1634static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1635 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1636 bool IgnoreChains) { 1637 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1638 // greater than all of its (recursive) operands. If we scan to a point where 1639 // 'use' is smaller than the node we're scanning for, then we know we will 1640 // never find it. 1641 // 1642 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1643 // happen because we scan down to newly selected nodes in the case of glue 1644 // uses. 1645 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1646 return false; 1647 1648 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1649 // won't fail if we scan it again. 1650 if (!Visited.insert(Use)) 1651 return false; 1652 1653 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1654 // Ignore chain uses, they are validated by HandleMergeInputChains. 1655 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1656 continue; 1657 1658 SDNode *N = Use->getOperand(i).getNode(); 1659 if (N == Def) { 1660 if (Use == ImmedUse || Use == Root) 1661 continue; // We are not looking for immediate use. 1662 assert(N != Root); 1663 return true; 1664 } 1665 1666 // Traverse up the operand chain. 1667 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1668 return true; 1669 } 1670 return false; 1671} 1672 1673/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1674/// operand node N of U during instruction selection that starts at Root. 1675bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1676 SDNode *Root) const { 1677 if (OptLevel == CodeGenOpt::None) return false; 1678 return N.hasOneUse(); 1679} 1680 1681/// IsLegalToFold - Returns true if the specific operand node N of 1682/// U can be folded during instruction selection that starts at Root. 1683bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1684 CodeGenOpt::Level OptLevel, 1685 bool IgnoreChains) { 1686 if (OptLevel == CodeGenOpt::None) return false; 1687 1688 // If Root use can somehow reach N through a path that that doesn't contain 1689 // U then folding N would create a cycle. e.g. In the following 1690 // diagram, Root can reach N through X. If N is folded into into Root, then 1691 // X is both a predecessor and a successor of U. 1692 // 1693 // [N*] // 1694 // ^ ^ // 1695 // / \ // 1696 // [U*] [X]? // 1697 // ^ ^ // 1698 // \ / // 1699 // \ / // 1700 // [Root*] // 1701 // 1702 // * indicates nodes to be folded together. 1703 // 1704 // If Root produces glue, then it gets (even more) interesting. Since it 1705 // will be "glued" together with its glue use in the scheduler, we need to 1706 // check if it might reach N. 1707 // 1708 // [N*] // 1709 // ^ ^ // 1710 // / \ // 1711 // [U*] [X]? // 1712 // ^ ^ // 1713 // \ \ // 1714 // \ | // 1715 // [Root*] | // 1716 // ^ | // 1717 // f | // 1718 // | / // 1719 // [Y] / // 1720 // ^ / // 1721 // f / // 1722 // | / // 1723 // [GU] // 1724 // 1725 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1726 // (call it Fold), then X is a predecessor of GU and a successor of 1727 // Fold. But since Fold and GU are glued together, this will create 1728 // a cycle in the scheduling graph. 1729 1730 // If the node has glue, walk down the graph to the "lowest" node in the 1731 // glueged set. 1732 EVT VT = Root->getValueType(Root->getNumValues()-1); 1733 while (VT == MVT::Glue) { 1734 SDNode *GU = findGlueUse(Root); 1735 if (GU == NULL) 1736 break; 1737 Root = GU; 1738 VT = Root->getValueType(Root->getNumValues()-1); 1739 1740 // If our query node has a glue result with a use, we've walked up it. If 1741 // the user (which has already been selected) has a chain or indirectly uses 1742 // the chain, our WalkChainUsers predicate will not consider it. Because of 1743 // this, we cannot ignore chains in this predicate. 1744 IgnoreChains = false; 1745 } 1746 1747 1748 SmallPtrSet<SDNode*, 16> Visited; 1749 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1750} 1751 1752SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1753 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1754 SelectInlineAsmMemoryOperands(Ops); 1755 1756 EVT VTs[] = { MVT::Other, MVT::Glue }; 1757 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), 1758 VTs, &Ops[0], Ops.size()); 1759 New->setNodeId(-1); 1760 return New.getNode(); 1761} 1762 1763SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1764 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1765} 1766 1767/// GetVBR - decode a vbr encoding whose top bit is set. 1768LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1769GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1770 assert(Val >= 128 && "Not a VBR"); 1771 Val &= 127; // Remove first vbr bit. 1772 1773 unsigned Shift = 7; 1774 uint64_t NextBits; 1775 do { 1776 NextBits = MatcherTable[Idx++]; 1777 Val |= (NextBits&127) << Shift; 1778 Shift += 7; 1779 } while (NextBits & 128); 1780 1781 return Val; 1782} 1783 1784 1785/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1786/// interior glue and chain results to use the new glue and chain results. 1787void SelectionDAGISel:: 1788UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1789 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1790 SDValue InputGlue, 1791 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1792 bool isMorphNodeTo) { 1793 SmallVector<SDNode*, 4> NowDeadNodes; 1794 1795 // Now that all the normal results are replaced, we replace the chain and 1796 // glue results if present. 1797 if (!ChainNodesMatched.empty()) { 1798 assert(InputChain.getNode() != 0 && 1799 "Matched input chains but didn't produce a chain"); 1800 // Loop over all of the nodes we matched that produced a chain result. 1801 // Replace all the chain results with the final chain we ended up with. 1802 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1803 SDNode *ChainNode = ChainNodesMatched[i]; 1804 1805 // If this node was already deleted, don't look at it. 1806 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1807 continue; 1808 1809 // Don't replace the results of the root node if we're doing a 1810 // MorphNodeTo. 1811 if (ChainNode == NodeToMatch && isMorphNodeTo) 1812 continue; 1813 1814 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1815 if (ChainVal.getValueType() == MVT::Glue) 1816 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1817 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1818 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1819 1820 // If the node became dead and we haven't already seen it, delete it. 1821 if (ChainNode->use_empty() && 1822 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1823 NowDeadNodes.push_back(ChainNode); 1824 } 1825 } 1826 1827 // If the result produces glue, update any glue results in the matched 1828 // pattern with the glue result. 1829 if (InputGlue.getNode() != 0) { 1830 // Handle any interior nodes explicitly marked. 1831 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1832 SDNode *FRN = GlueResultNodesMatched[i]; 1833 1834 // If this node was already deleted, don't look at it. 1835 if (FRN->getOpcode() == ISD::DELETED_NODE) 1836 continue; 1837 1838 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1839 "Doesn't have a glue result"); 1840 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1841 InputGlue); 1842 1843 // If the node became dead and we haven't already seen it, delete it. 1844 if (FRN->use_empty() && 1845 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1846 NowDeadNodes.push_back(FRN); 1847 } 1848 } 1849 1850 if (!NowDeadNodes.empty()) 1851 CurDAG->RemoveDeadNodes(NowDeadNodes); 1852 1853 DEBUG(dbgs() << "ISEL: Match complete!\n"); 1854} 1855 1856enum ChainResult { 1857 CR_Simple, 1858 CR_InducesCycle, 1859 CR_LeadsToInteriorNode 1860}; 1861 1862/// WalkChainUsers - Walk down the users of the specified chained node that is 1863/// part of the pattern we're matching, looking at all of the users we find. 1864/// This determines whether something is an interior node, whether we have a 1865/// non-pattern node in between two pattern nodes (which prevent folding because 1866/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1867/// between pattern nodes (in which case the TF becomes part of the pattern). 1868/// 1869/// The walk we do here is guaranteed to be small because we quickly get down to 1870/// already selected nodes "below" us. 1871static ChainResult 1872WalkChainUsers(const SDNode *ChainedNode, 1873 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1874 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1875 ChainResult Result = CR_Simple; 1876 1877 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1878 E = ChainedNode->use_end(); UI != E; ++UI) { 1879 // Make sure the use is of the chain, not some other value we produce. 1880 if (UI.getUse().getValueType() != MVT::Other) continue; 1881 1882 SDNode *User = *UI; 1883 1884 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1885 continue; 1886 1887 // If we see an already-selected machine node, then we've gone beyond the 1888 // pattern that we're selecting down into the already selected chunk of the 1889 // DAG. 1890 unsigned UserOpcode = User->getOpcode(); 1891 if (User->isMachineOpcode() || 1892 UserOpcode == ISD::CopyToReg || 1893 UserOpcode == ISD::CopyFromReg || 1894 UserOpcode == ISD::INLINEASM || 1895 UserOpcode == ISD::EH_LABEL || 1896 UserOpcode == ISD::LIFETIME_START || 1897 UserOpcode == ISD::LIFETIME_END) { 1898 // If their node ID got reset to -1 then they've already been selected. 1899 // Treat them like a MachineOpcode. 1900 if (User->getNodeId() == -1) 1901 continue; 1902 } 1903 1904 // If we have a TokenFactor, we handle it specially. 1905 if (User->getOpcode() != ISD::TokenFactor) { 1906 // If the node isn't a token factor and isn't part of our pattern, then it 1907 // must be a random chained node in between two nodes we're selecting. 1908 // This happens when we have something like: 1909 // x = load ptr 1910 // call 1911 // y = x+4 1912 // store y -> ptr 1913 // Because we structurally match the load/store as a read/modify/write, 1914 // but the call is chained between them. We cannot fold in this case 1915 // because it would induce a cycle in the graph. 1916 if (!std::count(ChainedNodesInPattern.begin(), 1917 ChainedNodesInPattern.end(), User)) 1918 return CR_InducesCycle; 1919 1920 // Otherwise we found a node that is part of our pattern. For example in: 1921 // x = load ptr 1922 // y = x+4 1923 // store y -> ptr 1924 // This would happen when we're scanning down from the load and see the 1925 // store as a user. Record that there is a use of ChainedNode that is 1926 // part of the pattern and keep scanning uses. 1927 Result = CR_LeadsToInteriorNode; 1928 InteriorChainedNodes.push_back(User); 1929 continue; 1930 } 1931 1932 // If we found a TokenFactor, there are two cases to consider: first if the 1933 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1934 // uses of the TF are in our pattern) we just want to ignore it. Second, 1935 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1936 // [Load chain] 1937 // ^ 1938 // | 1939 // [Load] 1940 // ^ ^ 1941 // | \ DAG's like cheese 1942 // / \ do you? 1943 // / | 1944 // [TokenFactor] [Op] 1945 // ^ ^ 1946 // | | 1947 // \ / 1948 // \ / 1949 // [Store] 1950 // 1951 // In this case, the TokenFactor becomes part of our match and we rewrite it 1952 // as a new TokenFactor. 1953 // 1954 // To distinguish these two cases, do a recursive walk down the uses. 1955 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1956 case CR_Simple: 1957 // If the uses of the TokenFactor are just already-selected nodes, ignore 1958 // it, it is "below" our pattern. 1959 continue; 1960 case CR_InducesCycle: 1961 // If the uses of the TokenFactor lead to nodes that are not part of our 1962 // pattern that are not selected, folding would turn this into a cycle, 1963 // bail out now. 1964 return CR_InducesCycle; 1965 case CR_LeadsToInteriorNode: 1966 break; // Otherwise, keep processing. 1967 } 1968 1969 // Okay, we know we're in the interesting interior case. The TokenFactor 1970 // is now going to be considered part of the pattern so that we rewrite its 1971 // uses (it may have uses that are not part of the pattern) with the 1972 // ultimate chain result of the generated code. We will also add its chain 1973 // inputs as inputs to the ultimate TokenFactor we create. 1974 Result = CR_LeadsToInteriorNode; 1975 ChainedNodesInPattern.push_back(User); 1976 InteriorChainedNodes.push_back(User); 1977 continue; 1978 } 1979 1980 return Result; 1981} 1982 1983/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1984/// operation for when the pattern matched at least one node with a chains. The 1985/// input vector contains a list of all of the chained nodes that we match. We 1986/// must determine if this is a valid thing to cover (i.e. matching it won't 1987/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1988/// be used as the input node chain for the generated nodes. 1989static SDValue 1990HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1991 SelectionDAG *CurDAG) { 1992 // Walk all of the chained nodes we've matched, recursively scanning down the 1993 // users of the chain result. This adds any TokenFactor nodes that are caught 1994 // in between chained nodes to the chained and interior nodes list. 1995 SmallVector<SDNode*, 3> InteriorChainedNodes; 1996 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1997 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1998 InteriorChainedNodes) == CR_InducesCycle) 1999 return SDValue(); // Would induce a cycle. 2000 } 2001 2002 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 2003 // that we are interested in. Form our input TokenFactor node. 2004 SmallVector<SDValue, 3> InputChains; 2005 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2006 // Add the input chain of this node to the InputChains list (which will be 2007 // the operands of the generated TokenFactor) if it's not an interior node. 2008 SDNode *N = ChainNodesMatched[i]; 2009 if (N->getOpcode() != ISD::TokenFactor) { 2010 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 2011 continue; 2012 2013 // Otherwise, add the input chain. 2014 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 2015 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 2016 InputChains.push_back(InChain); 2017 continue; 2018 } 2019 2020 // If we have a token factor, we want to add all inputs of the token factor 2021 // that are not part of the pattern we're matching. 2022 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 2023 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 2024 N->getOperand(op).getNode())) 2025 InputChains.push_back(N->getOperand(op)); 2026 } 2027 } 2028 2029 if (InputChains.size() == 1) 2030 return InputChains[0]; 2031 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]), 2032 MVT::Other, &InputChains[0], InputChains.size()); 2033} 2034 2035/// MorphNode - Handle morphing a node in place for the selector. 2036SDNode *SelectionDAGISel:: 2037MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 2038 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 2039 // It is possible we're using MorphNodeTo to replace a node with no 2040 // normal results with one that has a normal result (or we could be 2041 // adding a chain) and the input could have glue and chains as well. 2042 // In this case we need to shift the operands down. 2043 // FIXME: This is a horrible hack and broken in obscure cases, no worse 2044 // than the old isel though. 2045 int OldGlueResultNo = -1, OldChainResultNo = -1; 2046 2047 unsigned NTMNumResults = Node->getNumValues(); 2048 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 2049 OldGlueResultNo = NTMNumResults-1; 2050 if (NTMNumResults != 1 && 2051 Node->getValueType(NTMNumResults-2) == MVT::Other) 2052 OldChainResultNo = NTMNumResults-2; 2053 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 2054 OldChainResultNo = NTMNumResults-1; 2055 2056 // Call the underlying SelectionDAG routine to do the transmogrification. Note 2057 // that this deletes operands of the old node that become dead. 2058 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 2059 2060 // MorphNodeTo can operate in two ways: if an existing node with the 2061 // specified operands exists, it can just return it. Otherwise, it 2062 // updates the node in place to have the requested operands. 2063 if (Res == Node) { 2064 // If we updated the node in place, reset the node ID. To the isel, 2065 // this should be just like a newly allocated machine node. 2066 Res->setNodeId(-1); 2067 } 2068 2069 unsigned ResNumResults = Res->getNumValues(); 2070 // Move the glue if needed. 2071 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 2072 (unsigned)OldGlueResultNo != ResNumResults-1) 2073 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 2074 SDValue(Res, ResNumResults-1)); 2075 2076 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 2077 --ResNumResults; 2078 2079 // Move the chain reference if needed. 2080 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 2081 (unsigned)OldChainResultNo != ResNumResults-1) 2082 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 2083 SDValue(Res, ResNumResults-1)); 2084 2085 // Otherwise, no replacement happened because the node already exists. Replace 2086 // Uses of the old node with the new one. 2087 if (Res != Node) 2088 CurDAG->ReplaceAllUsesWith(Node, Res); 2089 2090 return Res; 2091} 2092 2093/// CheckSame - Implements OP_CheckSame. 2094LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2095CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2096 SDValue N, 2097 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2098 // Accept if it is exactly the same as a previously recorded node. 2099 unsigned RecNo = MatcherTable[MatcherIndex++]; 2100 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2101 return N == RecordedNodes[RecNo].first; 2102} 2103 2104/// CheckChildSame - Implements OP_CheckChildXSame. 2105LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2106CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2107 SDValue N, 2108 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes, 2109 unsigned ChildNo) { 2110 if (ChildNo >= N.getNumOperands()) 2111 return false; // Match fails if out of range child #. 2112 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo), 2113 RecordedNodes); 2114} 2115 2116/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2117LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2118CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2119 const SelectionDAGISel &SDISel) { 2120 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 2121} 2122 2123/// CheckNodePredicate - Implements OP_CheckNodePredicate. 2124LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2125CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2126 const SelectionDAGISel &SDISel, SDNode *N) { 2127 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2128} 2129 2130LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2131CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2132 SDNode *N) { 2133 uint16_t Opc = MatcherTable[MatcherIndex++]; 2134 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2135 return N->getOpcode() == Opc; 2136} 2137 2138LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2139CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2140 SDValue N, const TargetLowering *TLI) { 2141 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2142 if (N.getValueType() == VT) return true; 2143 2144 // Handle the case when VT is iPTR. 2145 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(); 2146} 2147 2148LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2149CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2150 SDValue N, const TargetLowering *TLI, 2151 unsigned ChildNo) { 2152 if (ChildNo >= N.getNumOperands()) 2153 return false; // Match fails if out of range child #. 2154 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2155} 2156 2157LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2158CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2159 SDValue N) { 2160 return cast<CondCodeSDNode>(N)->get() == 2161 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2162} 2163 2164LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2165CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2166 SDValue N, const TargetLowering *TLI) { 2167 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2168 if (cast<VTSDNode>(N)->getVT() == VT) 2169 return true; 2170 2171 // Handle the case when VT is iPTR. 2172 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(); 2173} 2174 2175LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2176CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2177 SDValue N) { 2178 int64_t Val = MatcherTable[MatcherIndex++]; 2179 if (Val & 128) 2180 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2181 2182 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2183 return C != 0 && C->getSExtValue() == Val; 2184} 2185 2186LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2187CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2188 SDValue N, const SelectionDAGISel &SDISel) { 2189 int64_t Val = MatcherTable[MatcherIndex++]; 2190 if (Val & 128) 2191 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2192 2193 if (N->getOpcode() != ISD::AND) return false; 2194 2195 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2196 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2197} 2198 2199LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2200CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2201 SDValue N, const SelectionDAGISel &SDISel) { 2202 int64_t Val = MatcherTable[MatcherIndex++]; 2203 if (Val & 128) 2204 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2205 2206 if (N->getOpcode() != ISD::OR) return false; 2207 2208 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2209 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2210} 2211 2212/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2213/// scope, evaluate the current node. If the current predicate is known to 2214/// fail, set Result=true and return anything. If the current predicate is 2215/// known to pass, set Result=false and return the MatcherIndex to continue 2216/// with. If the current predicate is unknown, set Result=false and return the 2217/// MatcherIndex to continue with. 2218static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2219 unsigned Index, SDValue N, 2220 bool &Result, 2221 const SelectionDAGISel &SDISel, 2222 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2223 switch (Table[Index++]) { 2224 default: 2225 Result = false; 2226 return Index-1; // Could not evaluate this predicate. 2227 case SelectionDAGISel::OPC_CheckSame: 2228 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2229 return Index; 2230 case SelectionDAGISel::OPC_CheckChild0Same: 2231 case SelectionDAGISel::OPC_CheckChild1Same: 2232 case SelectionDAGISel::OPC_CheckChild2Same: 2233 case SelectionDAGISel::OPC_CheckChild3Same: 2234 Result = !::CheckChildSame(Table, Index, N, RecordedNodes, 2235 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same); 2236 return Index; 2237 case SelectionDAGISel::OPC_CheckPatternPredicate: 2238 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2239 return Index; 2240 case SelectionDAGISel::OPC_CheckPredicate: 2241 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2242 return Index; 2243 case SelectionDAGISel::OPC_CheckOpcode: 2244 Result = !::CheckOpcode(Table, Index, N.getNode()); 2245 return Index; 2246 case SelectionDAGISel::OPC_CheckType: 2247 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering()); 2248 return Index; 2249 case SelectionDAGISel::OPC_CheckChild0Type: 2250 case SelectionDAGISel::OPC_CheckChild1Type: 2251 case SelectionDAGISel::OPC_CheckChild2Type: 2252 case SelectionDAGISel::OPC_CheckChild3Type: 2253 case SelectionDAGISel::OPC_CheckChild4Type: 2254 case SelectionDAGISel::OPC_CheckChild5Type: 2255 case SelectionDAGISel::OPC_CheckChild6Type: 2256 case SelectionDAGISel::OPC_CheckChild7Type: 2257 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(), 2258 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2259 return Index; 2260 case SelectionDAGISel::OPC_CheckCondCode: 2261 Result = !::CheckCondCode(Table, Index, N); 2262 return Index; 2263 case SelectionDAGISel::OPC_CheckValueType: 2264 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering()); 2265 return Index; 2266 case SelectionDAGISel::OPC_CheckInteger: 2267 Result = !::CheckInteger(Table, Index, N); 2268 return Index; 2269 case SelectionDAGISel::OPC_CheckAndImm: 2270 Result = !::CheckAndImm(Table, Index, N, SDISel); 2271 return Index; 2272 case SelectionDAGISel::OPC_CheckOrImm: 2273 Result = !::CheckOrImm(Table, Index, N, SDISel); 2274 return Index; 2275 } 2276} 2277 2278namespace { 2279 2280struct MatchScope { 2281 /// FailIndex - If this match fails, this is the index to continue with. 2282 unsigned FailIndex; 2283 2284 /// NodeStack - The node stack when the scope was formed. 2285 SmallVector<SDValue, 4> NodeStack; 2286 2287 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2288 unsigned NumRecordedNodes; 2289 2290 /// NumMatchedMemRefs - The number of matched memref entries. 2291 unsigned NumMatchedMemRefs; 2292 2293 /// InputChain/InputGlue - The current chain/glue 2294 SDValue InputChain, InputGlue; 2295 2296 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2297 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2298}; 2299 2300} 2301 2302SDNode *SelectionDAGISel:: 2303SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2304 unsigned TableSize) { 2305 // FIXME: Should these even be selected? Handle these cases in the caller? 2306 switch (NodeToMatch->getOpcode()) { 2307 default: 2308 break; 2309 case ISD::EntryToken: // These nodes remain the same. 2310 case ISD::BasicBlock: 2311 case ISD::Register: 2312 case ISD::RegisterMask: 2313 //case ISD::VALUETYPE: 2314 //case ISD::CONDCODE: 2315 case ISD::HANDLENODE: 2316 case ISD::MDNODE_SDNODE: 2317 case ISD::TargetConstant: 2318 case ISD::TargetConstantFP: 2319 case ISD::TargetConstantPool: 2320 case ISD::TargetFrameIndex: 2321 case ISD::TargetExternalSymbol: 2322 case ISD::TargetBlockAddress: 2323 case ISD::TargetJumpTable: 2324 case ISD::TargetGlobalTLSAddress: 2325 case ISD::TargetGlobalAddress: 2326 case ISD::TokenFactor: 2327 case ISD::CopyFromReg: 2328 case ISD::CopyToReg: 2329 case ISD::EH_LABEL: 2330 case ISD::LIFETIME_START: 2331 case ISD::LIFETIME_END: 2332 NodeToMatch->setNodeId(-1); // Mark selected. 2333 return 0; 2334 case ISD::AssertSext: 2335 case ISD::AssertZext: 2336 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2337 NodeToMatch->getOperand(0)); 2338 return 0; 2339 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2340 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2341 } 2342 2343 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2344 2345 // Set up the node stack with NodeToMatch as the only node on the stack. 2346 SmallVector<SDValue, 8> NodeStack; 2347 SDValue N = SDValue(NodeToMatch, 0); 2348 NodeStack.push_back(N); 2349 2350 // MatchScopes - Scopes used when matching, if a match failure happens, this 2351 // indicates where to continue checking. 2352 SmallVector<MatchScope, 8> MatchScopes; 2353 2354 // RecordedNodes - This is the set of nodes that have been recorded by the 2355 // state machine. The second value is the parent of the node, or null if the 2356 // root is recorded. 2357 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2358 2359 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2360 // pattern. 2361 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2362 2363 // These are the current input chain and glue for use when generating nodes. 2364 // Various Emit operations change these. For example, emitting a copytoreg 2365 // uses and updates these. 2366 SDValue InputChain, InputGlue; 2367 2368 // ChainNodesMatched - If a pattern matches nodes that have input/output 2369 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2370 // which ones they are. The result is captured into this list so that we can 2371 // update the chain results when the pattern is complete. 2372 SmallVector<SDNode*, 3> ChainNodesMatched; 2373 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2374 2375 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: "; 2376 NodeToMatch->dump(CurDAG); 2377 dbgs() << '\n'); 2378 2379 // Determine where to start the interpreter. Normally we start at opcode #0, 2380 // but if the state machine starts with an OPC_SwitchOpcode, then we 2381 // accelerate the first lookup (which is guaranteed to be hot) with the 2382 // OpcodeOffset table. 2383 unsigned MatcherIndex = 0; 2384 2385 if (!OpcodeOffset.empty()) { 2386 // Already computed the OpcodeOffset table, just index into it. 2387 if (N.getOpcode() < OpcodeOffset.size()) 2388 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2389 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2390 2391 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2392 // Otherwise, the table isn't computed, but the state machine does start 2393 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2394 // is the first time we're selecting an instruction. 2395 unsigned Idx = 1; 2396 while (1) { 2397 // Get the size of this case. 2398 unsigned CaseSize = MatcherTable[Idx++]; 2399 if (CaseSize & 128) 2400 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2401 if (CaseSize == 0) break; 2402 2403 // Get the opcode, add the index to the table. 2404 uint16_t Opc = MatcherTable[Idx++]; 2405 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2406 if (Opc >= OpcodeOffset.size()) 2407 OpcodeOffset.resize((Opc+1)*2); 2408 OpcodeOffset[Opc] = Idx; 2409 Idx += CaseSize; 2410 } 2411 2412 // Okay, do the lookup for the first opcode. 2413 if (N.getOpcode() < OpcodeOffset.size()) 2414 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2415 } 2416 2417 while (1) { 2418 assert(MatcherIndex < TableSize && "Invalid index"); 2419#ifndef NDEBUG 2420 unsigned CurrentOpcodeIndex = MatcherIndex; 2421#endif 2422 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2423 switch (Opcode) { 2424 case OPC_Scope: { 2425 // Okay, the semantics of this operation are that we should push a scope 2426 // then evaluate the first child. However, pushing a scope only to have 2427 // the first check fail (which then pops it) is inefficient. If we can 2428 // determine immediately that the first check (or first several) will 2429 // immediately fail, don't even bother pushing a scope for them. 2430 unsigned FailIndex; 2431 2432 while (1) { 2433 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2434 if (NumToSkip & 128) 2435 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2436 // Found the end of the scope with no match. 2437 if (NumToSkip == 0) { 2438 FailIndex = 0; 2439 break; 2440 } 2441 2442 FailIndex = MatcherIndex+NumToSkip; 2443 2444 unsigned MatcherIndexOfPredicate = MatcherIndex; 2445 (void)MatcherIndexOfPredicate; // silence warning. 2446 2447 // If we can't evaluate this predicate without pushing a scope (e.g. if 2448 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2449 // push the scope and evaluate the full predicate chain. 2450 bool Result; 2451 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2452 Result, *this, RecordedNodes); 2453 if (!Result) 2454 break; 2455 2456 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at " 2457 << "index " << MatcherIndexOfPredicate 2458 << ", continuing at " << FailIndex << "\n"); 2459 ++NumDAGIselRetries; 2460 2461 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2462 // move to the next case. 2463 MatcherIndex = FailIndex; 2464 } 2465 2466 // If the whole scope failed to match, bail. 2467 if (FailIndex == 0) break; 2468 2469 // Push a MatchScope which indicates where to go if the first child fails 2470 // to match. 2471 MatchScope NewEntry; 2472 NewEntry.FailIndex = FailIndex; 2473 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2474 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2475 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2476 NewEntry.InputChain = InputChain; 2477 NewEntry.InputGlue = InputGlue; 2478 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2479 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2480 MatchScopes.push_back(NewEntry); 2481 continue; 2482 } 2483 case OPC_RecordNode: { 2484 // Remember this node, it may end up being an operand in the pattern. 2485 SDNode *Parent = 0; 2486 if (NodeStack.size() > 1) 2487 Parent = NodeStack[NodeStack.size()-2].getNode(); 2488 RecordedNodes.push_back(std::make_pair(N, Parent)); 2489 continue; 2490 } 2491 2492 case OPC_RecordChild0: case OPC_RecordChild1: 2493 case OPC_RecordChild2: case OPC_RecordChild3: 2494 case OPC_RecordChild4: case OPC_RecordChild5: 2495 case OPC_RecordChild6: case OPC_RecordChild7: { 2496 unsigned ChildNo = Opcode-OPC_RecordChild0; 2497 if (ChildNo >= N.getNumOperands()) 2498 break; // Match fails if out of range child #. 2499 2500 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2501 N.getNode())); 2502 continue; 2503 } 2504 case OPC_RecordMemRef: 2505 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2506 continue; 2507 2508 case OPC_CaptureGlueInput: 2509 // If the current node has an input glue, capture it in InputGlue. 2510 if (N->getNumOperands() != 0 && 2511 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2512 InputGlue = N->getOperand(N->getNumOperands()-1); 2513 continue; 2514 2515 case OPC_MoveChild: { 2516 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2517 if (ChildNo >= N.getNumOperands()) 2518 break; // Match fails if out of range child #. 2519 N = N.getOperand(ChildNo); 2520 NodeStack.push_back(N); 2521 continue; 2522 } 2523 2524 case OPC_MoveParent: 2525 // Pop the current node off the NodeStack. 2526 NodeStack.pop_back(); 2527 assert(!NodeStack.empty() && "Node stack imbalance!"); 2528 N = NodeStack.back(); 2529 continue; 2530 2531 case OPC_CheckSame: 2532 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2533 continue; 2534 2535 case OPC_CheckChild0Same: case OPC_CheckChild1Same: 2536 case OPC_CheckChild2Same: case OPC_CheckChild3Same: 2537 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes, 2538 Opcode-OPC_CheckChild0Same)) 2539 break; 2540 continue; 2541 2542 case OPC_CheckPatternPredicate: 2543 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2544 continue; 2545 case OPC_CheckPredicate: 2546 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2547 N.getNode())) 2548 break; 2549 continue; 2550 case OPC_CheckComplexPat: { 2551 unsigned CPNum = MatcherTable[MatcherIndex++]; 2552 unsigned RecNo = MatcherTable[MatcherIndex++]; 2553 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2554 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2555 RecordedNodes[RecNo].first, CPNum, 2556 RecordedNodes)) 2557 break; 2558 continue; 2559 } 2560 case OPC_CheckOpcode: 2561 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2562 continue; 2563 2564 case OPC_CheckType: 2565 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2566 break; 2567 continue; 2568 2569 case OPC_SwitchOpcode: { 2570 unsigned CurNodeOpcode = N.getOpcode(); 2571 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2572 unsigned CaseSize; 2573 while (1) { 2574 // Get the size of this case. 2575 CaseSize = MatcherTable[MatcherIndex++]; 2576 if (CaseSize & 128) 2577 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2578 if (CaseSize == 0) break; 2579 2580 uint16_t Opc = MatcherTable[MatcherIndex++]; 2581 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2582 2583 // If the opcode matches, then we will execute this case. 2584 if (CurNodeOpcode == Opc) 2585 break; 2586 2587 // Otherwise, skip over this case. 2588 MatcherIndex += CaseSize; 2589 } 2590 2591 // If no cases matched, bail out. 2592 if (CaseSize == 0) break; 2593 2594 // Otherwise, execute the case we found. 2595 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart 2596 << " to " << MatcherIndex << "\n"); 2597 continue; 2598 } 2599 2600 case OPC_SwitchType: { 2601 MVT CurNodeVT = N.getSimpleValueType(); 2602 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2603 unsigned CaseSize; 2604 while (1) { 2605 // Get the size of this case. 2606 CaseSize = MatcherTable[MatcherIndex++]; 2607 if (CaseSize & 128) 2608 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2609 if (CaseSize == 0) break; 2610 2611 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2612 if (CaseVT == MVT::iPTR) 2613 CaseVT = getTargetLowering()->getPointerTy(); 2614 2615 // If the VT matches, then we will execute this case. 2616 if (CurNodeVT == CaseVT) 2617 break; 2618 2619 // Otherwise, skip over this case. 2620 MatcherIndex += CaseSize; 2621 } 2622 2623 // If no cases matched, bail out. 2624 if (CaseSize == 0) break; 2625 2626 // Otherwise, execute the case we found. 2627 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2628 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2629 continue; 2630 } 2631 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2632 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2633 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2634 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2635 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(), 2636 Opcode-OPC_CheckChild0Type)) 2637 break; 2638 continue; 2639 case OPC_CheckCondCode: 2640 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2641 continue; 2642 case OPC_CheckValueType: 2643 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2644 break; 2645 continue; 2646 case OPC_CheckInteger: 2647 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2648 continue; 2649 case OPC_CheckAndImm: 2650 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2651 continue; 2652 case OPC_CheckOrImm: 2653 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2654 continue; 2655 2656 case OPC_CheckFoldableChainNode: { 2657 assert(NodeStack.size() != 1 && "No parent node"); 2658 // Verify that all intermediate nodes between the root and this one have 2659 // a single use. 2660 bool HasMultipleUses = false; 2661 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2662 if (!NodeStack[i].hasOneUse()) { 2663 HasMultipleUses = true; 2664 break; 2665 } 2666 if (HasMultipleUses) break; 2667 2668 // Check to see that the target thinks this is profitable to fold and that 2669 // we can fold it without inducing cycles in the graph. 2670 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2671 NodeToMatch) || 2672 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2673 NodeToMatch, OptLevel, 2674 true/*We validate our own chains*/)) 2675 break; 2676 2677 continue; 2678 } 2679 case OPC_EmitInteger: { 2680 MVT::SimpleValueType VT = 2681 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2682 int64_t Val = MatcherTable[MatcherIndex++]; 2683 if (Val & 128) 2684 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2685 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2686 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2687 continue; 2688 } 2689 case OPC_EmitRegister: { 2690 MVT::SimpleValueType VT = 2691 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2692 unsigned RegNo = MatcherTable[MatcherIndex++]; 2693 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2694 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2695 continue; 2696 } 2697 case OPC_EmitRegister2: { 2698 // For targets w/ more than 256 register names, the register enum 2699 // values are stored in two bytes in the matcher table (just like 2700 // opcodes). 2701 MVT::SimpleValueType VT = 2702 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2703 unsigned RegNo = MatcherTable[MatcherIndex++]; 2704 RegNo |= MatcherTable[MatcherIndex++] << 8; 2705 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2706 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2707 continue; 2708 } 2709 2710 case OPC_EmitConvertToTarget: { 2711 // Convert from IMM/FPIMM to target version. 2712 unsigned RecNo = MatcherTable[MatcherIndex++]; 2713 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget"); 2714 SDValue Imm = RecordedNodes[RecNo].first; 2715 2716 if (Imm->getOpcode() == ISD::Constant) { 2717 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 2718 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true); 2719 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2720 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2721 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true); 2722 } 2723 2724 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2725 continue; 2726 } 2727 2728 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2729 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2730 // These are space-optimized forms of OPC_EmitMergeInputChains. 2731 assert(InputChain.getNode() == 0 && 2732 "EmitMergeInputChains should be the first chain producing node"); 2733 assert(ChainNodesMatched.empty() && 2734 "Should only have one EmitMergeInputChains per match"); 2735 2736 // Read all of the chained nodes. 2737 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2738 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains"); 2739 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2740 2741 // FIXME: What if other value results of the node have uses not matched 2742 // by this pattern? 2743 if (ChainNodesMatched.back() != NodeToMatch && 2744 !RecordedNodes[RecNo].first.hasOneUse()) { 2745 ChainNodesMatched.clear(); 2746 break; 2747 } 2748 2749 // Merge the input chains if they are not intra-pattern references. 2750 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2751 2752 if (InputChain.getNode() == 0) 2753 break; // Failed to merge. 2754 continue; 2755 } 2756 2757 case OPC_EmitMergeInputChains: { 2758 assert(InputChain.getNode() == 0 && 2759 "EmitMergeInputChains should be the first chain producing node"); 2760 // This node gets a list of nodes we matched in the input that have 2761 // chains. We want to token factor all of the input chains to these nodes 2762 // together. However, if any of the input chains is actually one of the 2763 // nodes matched in this pattern, then we have an intra-match reference. 2764 // Ignore these because the newly token factored chain should not refer to 2765 // the old nodes. 2766 unsigned NumChains = MatcherTable[MatcherIndex++]; 2767 assert(NumChains != 0 && "Can't TF zero chains"); 2768 2769 assert(ChainNodesMatched.empty() && 2770 "Should only have one EmitMergeInputChains per match"); 2771 2772 // Read all of the chained nodes. 2773 for (unsigned i = 0; i != NumChains; ++i) { 2774 unsigned RecNo = MatcherTable[MatcherIndex++]; 2775 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains"); 2776 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2777 2778 // FIXME: What if other value results of the node have uses not matched 2779 // by this pattern? 2780 if (ChainNodesMatched.back() != NodeToMatch && 2781 !RecordedNodes[RecNo].first.hasOneUse()) { 2782 ChainNodesMatched.clear(); 2783 break; 2784 } 2785 } 2786 2787 // If the inner loop broke out, the match fails. 2788 if (ChainNodesMatched.empty()) 2789 break; 2790 2791 // Merge the input chains if they are not intra-pattern references. 2792 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2793 2794 if (InputChain.getNode() == 0) 2795 break; // Failed to merge. 2796 2797 continue; 2798 } 2799 2800 case OPC_EmitCopyToReg: { 2801 unsigned RecNo = MatcherTable[MatcherIndex++]; 2802 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg"); 2803 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2804 2805 if (InputChain.getNode() == 0) 2806 InputChain = CurDAG->getEntryNode(); 2807 2808 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch), 2809 DestPhysReg, RecordedNodes[RecNo].first, 2810 InputGlue); 2811 2812 InputGlue = InputChain.getValue(1); 2813 continue; 2814 } 2815 2816 case OPC_EmitNodeXForm: { 2817 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2818 unsigned RecNo = MatcherTable[MatcherIndex++]; 2819 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm"); 2820 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2821 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2822 continue; 2823 } 2824 2825 case OPC_EmitNode: 2826 case OPC_MorphNodeTo: { 2827 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2828 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2829 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2830 // Get the result VT list. 2831 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2832 SmallVector<EVT, 4> VTs; 2833 for (unsigned i = 0; i != NumVTs; ++i) { 2834 MVT::SimpleValueType VT = 2835 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2836 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy; 2837 VTs.push_back(VT); 2838 } 2839 2840 if (EmitNodeInfo & OPFL_Chain) 2841 VTs.push_back(MVT::Other); 2842 if (EmitNodeInfo & OPFL_GlueOutput) 2843 VTs.push_back(MVT::Glue); 2844 2845 // This is hot code, so optimize the two most common cases of 1 and 2 2846 // results. 2847 SDVTList VTList; 2848 if (VTs.size() == 1) 2849 VTList = CurDAG->getVTList(VTs[0]); 2850 else if (VTs.size() == 2) 2851 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2852 else 2853 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2854 2855 // Get the operand list. 2856 unsigned NumOps = MatcherTable[MatcherIndex++]; 2857 SmallVector<SDValue, 8> Ops; 2858 for (unsigned i = 0; i != NumOps; ++i) { 2859 unsigned RecNo = MatcherTable[MatcherIndex++]; 2860 if (RecNo & 128) 2861 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2862 2863 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2864 Ops.push_back(RecordedNodes[RecNo].first); 2865 } 2866 2867 // If there are variadic operands to add, handle them now. 2868 if (EmitNodeInfo & OPFL_VariadicInfo) { 2869 // Determine the start index to copy from. 2870 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2871 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2872 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2873 "Invalid variadic node"); 2874 // Copy all of the variadic operands, not including a potential glue 2875 // input. 2876 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2877 i != e; ++i) { 2878 SDValue V = NodeToMatch->getOperand(i); 2879 if (V.getValueType() == MVT::Glue) break; 2880 Ops.push_back(V); 2881 } 2882 } 2883 2884 // If this has chain/glue inputs, add them. 2885 if (EmitNodeInfo & OPFL_Chain) 2886 Ops.push_back(InputChain); 2887 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2888 Ops.push_back(InputGlue); 2889 2890 // Create the node. 2891 SDNode *Res = 0; 2892 if (Opcode != OPC_MorphNodeTo) { 2893 // If this is a normal EmitNode command, just create the new node and 2894 // add the results to the RecordedNodes list. 2895 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch), 2896 VTList, Ops); 2897 2898 // Add all the non-glue/non-chain results to the RecordedNodes list. 2899 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2900 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2901 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2902 (SDNode*) 0)); 2903 } 2904 2905 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 2906 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2907 EmitNodeInfo); 2908 } else { 2909 // NodeToMatch was eliminated by CSE when the target changed the DAG. 2910 // We will visit the equivalent node later. 2911 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 2912 return 0; 2913 } 2914 2915 // If the node had chain/glue results, update our notion of the current 2916 // chain and glue. 2917 if (EmitNodeInfo & OPFL_GlueOutput) { 2918 InputGlue = SDValue(Res, VTs.size()-1); 2919 if (EmitNodeInfo & OPFL_Chain) 2920 InputChain = SDValue(Res, VTs.size()-2); 2921 } else if (EmitNodeInfo & OPFL_Chain) 2922 InputChain = SDValue(Res, VTs.size()-1); 2923 2924 // If the OPFL_MemRefs glue is set on this node, slap all of the 2925 // accumulated memrefs onto it. 2926 // 2927 // FIXME: This is vastly incorrect for patterns with multiple outputs 2928 // instructions that access memory and for ComplexPatterns that match 2929 // loads. 2930 if (EmitNodeInfo & OPFL_MemRefs) { 2931 // Only attach load or store memory operands if the generated 2932 // instruction may load or store. 2933 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2934 bool mayLoad = MCID.mayLoad(); 2935 bool mayStore = MCID.mayStore(); 2936 2937 unsigned NumMemRefs = 0; 2938 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 2939 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2940 if ((*I)->isLoad()) { 2941 if (mayLoad) 2942 ++NumMemRefs; 2943 } else if ((*I)->isStore()) { 2944 if (mayStore) 2945 ++NumMemRefs; 2946 } else { 2947 ++NumMemRefs; 2948 } 2949 } 2950 2951 MachineSDNode::mmo_iterator MemRefs = 2952 MF->allocateMemRefsArray(NumMemRefs); 2953 2954 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 2955 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 2956 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2957 if ((*I)->isLoad()) { 2958 if (mayLoad) 2959 *MemRefsPos++ = *I; 2960 } else if ((*I)->isStore()) { 2961 if (mayStore) 2962 *MemRefsPos++ = *I; 2963 } else { 2964 *MemRefsPos++ = *I; 2965 } 2966 } 2967 2968 cast<MachineSDNode>(Res) 2969 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 2970 } 2971 2972 DEBUG(dbgs() << " " 2973 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2974 << " node: "; Res->dump(CurDAG); dbgs() << "\n"); 2975 2976 // If this was a MorphNodeTo then we're completely done! 2977 if (Opcode == OPC_MorphNodeTo) { 2978 // Update chain and glue uses. 2979 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2980 InputGlue, GlueResultNodesMatched, true); 2981 return Res; 2982 } 2983 2984 continue; 2985 } 2986 2987 case OPC_MarkGlueResults: { 2988 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2989 2990 // Read and remember all the glue-result nodes. 2991 for (unsigned i = 0; i != NumNodes; ++i) { 2992 unsigned RecNo = MatcherTable[MatcherIndex++]; 2993 if (RecNo & 128) 2994 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2995 2996 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults"); 2997 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2998 } 2999 continue; 3000 } 3001 3002 case OPC_CompleteMatch: { 3003 // The match has been completed, and any new nodes (if any) have been 3004 // created. Patch up references to the matched dag to use the newly 3005 // created nodes. 3006 unsigned NumResults = MatcherTable[MatcherIndex++]; 3007 3008 for (unsigned i = 0; i != NumResults; ++i) { 3009 unsigned ResSlot = MatcherTable[MatcherIndex++]; 3010 if (ResSlot & 128) 3011 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 3012 3013 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch"); 3014 SDValue Res = RecordedNodes[ResSlot].first; 3015 3016 assert(i < NodeToMatch->getNumValues() && 3017 NodeToMatch->getValueType(i) != MVT::Other && 3018 NodeToMatch->getValueType(i) != MVT::Glue && 3019 "Invalid number of results to complete!"); 3020 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 3021 NodeToMatch->getValueType(i) == MVT::iPTR || 3022 Res.getValueType() == MVT::iPTR || 3023 NodeToMatch->getValueType(i).getSizeInBits() == 3024 Res.getValueType().getSizeInBits()) && 3025 "invalid replacement"); 3026 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 3027 } 3028 3029 // If the root node defines glue, add it to the glue nodes to update list. 3030 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 3031 GlueResultNodesMatched.push_back(NodeToMatch); 3032 3033 // Update chain and glue uses. 3034 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 3035 InputGlue, GlueResultNodesMatched, false); 3036 3037 assert(NodeToMatch->use_empty() && 3038 "Didn't replace all uses of the node?"); 3039 3040 // FIXME: We just return here, which interacts correctly with SelectRoot 3041 // above. We should fix this to not return an SDNode* anymore. 3042 return 0; 3043 } 3044 } 3045 3046 // If the code reached this point, then the match failed. See if there is 3047 // another child to try in the current 'Scope', otherwise pop it until we 3048 // find a case to check. 3049 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 3050 ++NumDAGIselRetries; 3051 while (1) { 3052 if (MatchScopes.empty()) { 3053 CannotYetSelect(NodeToMatch); 3054 return 0; 3055 } 3056 3057 // Restore the interpreter state back to the point where the scope was 3058 // formed. 3059 MatchScope &LastScope = MatchScopes.back(); 3060 RecordedNodes.resize(LastScope.NumRecordedNodes); 3061 NodeStack.clear(); 3062 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 3063 N = NodeStack.back(); 3064 3065 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 3066 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 3067 MatcherIndex = LastScope.FailIndex; 3068 3069 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); 3070 3071 InputChain = LastScope.InputChain; 3072 InputGlue = LastScope.InputGlue; 3073 if (!LastScope.HasChainNodesMatched) 3074 ChainNodesMatched.clear(); 3075 if (!LastScope.HasGlueResultNodesMatched) 3076 GlueResultNodesMatched.clear(); 3077 3078 // Check to see what the offset is at the new MatcherIndex. If it is zero 3079 // we have reached the end of this scope, otherwise we have another child 3080 // in the current scope to try. 3081 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 3082 if (NumToSkip & 128) 3083 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 3084 3085 // If we have another child in this scope to match, update FailIndex and 3086 // try it. 3087 if (NumToSkip != 0) { 3088 LastScope.FailIndex = MatcherIndex+NumToSkip; 3089 break; 3090 } 3091 3092 // End of this scope, pop it and try the next child in the containing 3093 // scope. 3094 MatchScopes.pop_back(); 3095 } 3096 } 3097} 3098 3099 3100 3101void SelectionDAGISel::CannotYetSelect(SDNode *N) { 3102 std::string msg; 3103 raw_string_ostream Msg(msg); 3104 Msg << "Cannot select: "; 3105 3106 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 3107 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 3108 N->getOpcode() != ISD::INTRINSIC_VOID) { 3109 N->printrFull(Msg, CurDAG); 3110 Msg << "\nIn function: " << MF->getName(); 3111 } else { 3112 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 3113 unsigned iid = 3114 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 3115 if (iid < Intrinsic::num_intrinsics) 3116 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 3117 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 3118 Msg << "target intrinsic %" << TII->getName(iid); 3119 else 3120 Msg << "unknown intrinsic #" << iid; 3121 } 3122 report_fatal_error(Msg.str()); 3123} 3124 3125char SelectionDAGISel::ID = 0; 3126