SelectionDAGISel.cpp revision 3687e34c2cc7ce435bc29e9cacdb4d7320890b91
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/MachineModuleInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/CodeGen/SSARegMap.h" 37#include "llvm/Target/MRegisterInfo.h" 38#include "llvm/Target/TargetData.h" 39#include "llvm/Target/TargetFrameInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Compiler.h" 47#include <algorithm> 48using namespace llvm; 49 50#ifndef NDEBUG 51static cl::opt<bool> 52ViewISelDAGs("view-isel-dags", cl::Hidden, 53 cl::desc("Pop up a window to show isel dags as they are selected")); 54static cl::opt<bool> 55ViewSchedDAGs("view-sched-dags", cl::Hidden, 56 cl::desc("Pop up a window to show sched dags as they are processed")); 57static cl::opt<bool> 58ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 59 cl::desc("Pop up a window to show SUnit dags after they are processed")); 60#else 61static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0; 62#endif 63 64//===---------------------------------------------------------------------===// 65/// 66/// RegisterScheduler class - Track the registration of instruction schedulers. 67/// 68//===---------------------------------------------------------------------===// 69MachinePassRegistry RegisterScheduler::Registry; 70 71//===---------------------------------------------------------------------===// 72/// 73/// ISHeuristic command line option for instruction schedulers. 74/// 75//===---------------------------------------------------------------------===// 76namespace { 77 cl::opt<RegisterScheduler::FunctionPassCtor, false, 78 RegisterPassParser<RegisterScheduler> > 79 ISHeuristic("pre-RA-sched", 80 cl::init(&createDefaultScheduler), 81 cl::desc("Instruction schedulers available (before register allocation):")); 82 83 static RegisterScheduler 84 defaultListDAGScheduler("default", " Best scheduler for the target", 85 createDefaultScheduler); 86} // namespace 87 88namespace { struct AsmOperandInfo; } 89 90namespace { 91 /// RegsForValue - This struct represents the physical registers that a 92 /// particular value is assigned and the type information about the value. 93 /// This is needed because values can be promoted into larger registers and 94 /// expanded into multiple smaller registers than the value. 95 struct VISIBILITY_HIDDEN RegsForValue { 96 /// Regs - This list holds the register (for legal and promoted values) 97 /// or register set (for expanded values) that the value should be assigned 98 /// to. 99 std::vector<unsigned> Regs; 100 101 /// RegVT - The value type of each register. 102 /// 103 MVT::ValueType RegVT; 104 105 /// ValueVT - The value type of the LLVM value, which may be promoted from 106 /// RegVT or made from merging the two expanded parts. 107 MVT::ValueType ValueVT; 108 109 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 110 111 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 112 : RegVT(regvt), ValueVT(valuevt) { 113 Regs.push_back(Reg); 114 } 115 RegsForValue(const std::vector<unsigned> ®s, 116 MVT::ValueType regvt, MVT::ValueType valuevt) 117 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 118 } 119 120 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 121 /// this value and returns the result as a ValueVT value. This uses 122 /// Chain/Flag as the input and updates them for the output Chain/Flag. 123 /// If the Flag pointer is NULL, no flag is used. 124 SDOperand getCopyFromRegs(SelectionDAG &DAG, 125 SDOperand &Chain, SDOperand *Flag) const; 126 127 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 128 /// specified value into the registers specified by this object. This uses 129 /// Chain/Flag as the input and updates them for the output Chain/Flag. 130 /// If the Flag pointer is NULL, no flag is used. 131 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 132 SDOperand &Chain, SDOperand *Flag) const; 133 134 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 135 /// operand list. This adds the code marker and includes the number of 136 /// values added into it. 137 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 138 std::vector<SDOperand> &Ops) const; 139 }; 140} 141 142namespace llvm { 143 //===--------------------------------------------------------------------===// 144 /// createDefaultScheduler - This creates an instruction scheduler appropriate 145 /// for the target. 146 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 147 SelectionDAG *DAG, 148 MachineBasicBlock *BB) { 149 TargetLowering &TLI = IS->getTargetLowering(); 150 151 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 152 return createTDListDAGScheduler(IS, DAG, BB); 153 } else { 154 assert(TLI.getSchedulingPreference() == 155 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 156 return createBURRListDAGScheduler(IS, DAG, BB); 157 } 158 } 159 160 161 //===--------------------------------------------------------------------===// 162 /// FunctionLoweringInfo - This contains information that is global to a 163 /// function that is used when lowering a region of the function. 164 class FunctionLoweringInfo { 165 public: 166 TargetLowering &TLI; 167 Function &Fn; 168 MachineFunction &MF; 169 SSARegMap *RegMap; 170 171 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 172 173 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 174 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 175 176 /// ValueMap - Since we emit code for the function a basic block at a time, 177 /// we must remember which virtual registers hold the values for 178 /// cross-basic-block values. 179 DenseMap<const Value*, unsigned> ValueMap; 180 181 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 182 /// the entry block. This allows the allocas to be efficiently referenced 183 /// anywhere in the function. 184 std::map<const AllocaInst*, int> StaticAllocaMap; 185 186#ifndef NDEBUG 187 SmallSet<Instruction*, 8> CatchInfoLost; 188 SmallSet<Instruction*, 8> CatchInfoFound; 189#endif 190 191 unsigned MakeReg(MVT::ValueType VT) { 192 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 193 } 194 195 /// isExportedInst - Return true if the specified value is an instruction 196 /// exported from its block. 197 bool isExportedInst(const Value *V) { 198 return ValueMap.count(V); 199 } 200 201 unsigned CreateRegForValue(const Value *V); 202 203 unsigned InitializeRegForValue(const Value *V) { 204 unsigned &R = ValueMap[V]; 205 assert(R == 0 && "Already initialized this value register!"); 206 return R = CreateRegForValue(V); 207 } 208 }; 209} 210 211/// isSelector - Return true if this instruction is a call to the 212/// eh.selector intrinsic. 213static bool isSelector(Instruction *I) { 214 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 215 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 || 216 II->getIntrinsicID() == Intrinsic::eh_selector_i64); 217 return false; 218} 219 220/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 221/// PHI nodes or outside of the basic block that defines it, or used by a 222/// switch instruction, which may expand to multiple basic blocks. 223static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 224 if (isa<PHINode>(I)) return true; 225 BasicBlock *BB = I->getParent(); 226 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 227 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 228 // FIXME: Remove switchinst special case. 229 isa<SwitchInst>(*UI)) 230 return true; 231 return false; 232} 233 234/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 235/// entry block, return true. This includes arguments used by switches, since 236/// the switch may expand into multiple basic blocks. 237static bool isOnlyUsedInEntryBlock(Argument *A) { 238 BasicBlock *Entry = A->getParent()->begin(); 239 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 240 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 241 return false; // Use not in entry block. 242 return true; 243} 244 245FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 246 Function &fn, MachineFunction &mf) 247 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 248 249 // Create a vreg for each argument register that is not dead and is used 250 // outside of the entry block for the function. 251 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 252 AI != E; ++AI) 253 if (!isOnlyUsedInEntryBlock(AI)) 254 InitializeRegForValue(AI); 255 256 // Initialize the mapping of values to registers. This is only set up for 257 // instruction values that are used outside of the block that defines 258 // them. 259 Function::iterator BB = Fn.begin(), EB = Fn.end(); 260 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 261 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 262 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 263 const Type *Ty = AI->getAllocatedType(); 264 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 265 unsigned Align = 266 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 267 AI->getAlignment()); 268 269 TySize *= CUI->getZExtValue(); // Get total allocated size. 270 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 271 StaticAllocaMap[AI] = 272 MF.getFrameInfo()->CreateStackObject(TySize, Align); 273 } 274 275 for (; BB != EB; ++BB) 276 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 277 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 278 if (!isa<AllocaInst>(I) || 279 !StaticAllocaMap.count(cast<AllocaInst>(I))) 280 InitializeRegForValue(I); 281 282 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 283 // also creates the initial PHI MachineInstrs, though none of the input 284 // operands are populated. 285 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 286 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 287 MBBMap[BB] = MBB; 288 MF.getBasicBlockList().push_back(MBB); 289 290 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 291 // appropriate. 292 PHINode *PN; 293 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 294 if (PN->use_empty()) continue; 295 296 MVT::ValueType VT = TLI.getValueType(PN->getType()); 297 unsigned NumRegisters = TLI.getNumRegisters(VT); 298 unsigned PHIReg = ValueMap[PN]; 299 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 300 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 301 for (unsigned i = 0; i != NumRegisters; ++i) 302 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 303 } 304 } 305} 306 307/// CreateRegForValue - Allocate the appropriate number of virtual registers of 308/// the correctly promoted or expanded types. Assign these registers 309/// consecutive vreg numbers and return the first assigned number. 310unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 311 MVT::ValueType VT = TLI.getValueType(V->getType()); 312 313 unsigned NumRegisters = TLI.getNumRegisters(VT); 314 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 315 316 unsigned R = MakeReg(RegisterVT); 317 for (unsigned i = 1; i != NumRegisters; ++i) 318 MakeReg(RegisterVT); 319 320 return R; 321} 322 323//===----------------------------------------------------------------------===// 324/// SelectionDAGLowering - This is the common target-independent lowering 325/// implementation that is parameterized by a TargetLowering object. 326/// Also, targets can overload any lowering method. 327/// 328namespace llvm { 329class SelectionDAGLowering { 330 MachineBasicBlock *CurMBB; 331 332 DenseMap<const Value*, SDOperand> NodeMap; 333 334 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 335 /// them up and then emit token factor nodes when possible. This allows us to 336 /// get simple disambiguation between loads without worrying about alias 337 /// analysis. 338 std::vector<SDOperand> PendingLoads; 339 340 /// Case - A struct to record the Value for a switch case, and the 341 /// case's target basic block. 342 struct Case { 343 Constant* Low; 344 Constant* High; 345 MachineBasicBlock* BB; 346 347 Case() : Low(0), High(0), BB(0) { } 348 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 349 Low(low), High(high), BB(bb) { } 350 uint64_t size() const { 351 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 352 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 353 return (rHigh - rLow + 1ULL); 354 } 355 }; 356 357 struct CaseBits { 358 uint64_t Mask; 359 MachineBasicBlock* BB; 360 unsigned Bits; 361 362 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 363 Mask(mask), BB(bb), Bits(bits) { } 364 }; 365 366 typedef std::vector<Case> CaseVector; 367 typedef std::vector<CaseBits> CaseBitsVector; 368 typedef CaseVector::iterator CaseItr; 369 typedef std::pair<CaseItr, CaseItr> CaseRange; 370 371 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 372 /// of conditional branches. 373 struct CaseRec { 374 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 375 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 376 377 /// CaseBB - The MBB in which to emit the compare and branch 378 MachineBasicBlock *CaseBB; 379 /// LT, GE - If nonzero, we know the current case value must be less-than or 380 /// greater-than-or-equal-to these Constants. 381 Constant *LT; 382 Constant *GE; 383 /// Range - A pair of iterators representing the range of case values to be 384 /// processed at this point in the binary search tree. 385 CaseRange Range; 386 }; 387 388 typedef std::vector<CaseRec> CaseRecVector; 389 390 /// The comparison function for sorting the switch case values in the vector. 391 /// WARNING: Case ranges should be disjoint! 392 struct CaseCmp { 393 bool operator () (const Case& C1, const Case& C2) { 394 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 395 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 396 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 397 return CI1->getValue().slt(CI2->getValue()); 398 } 399 }; 400 401 struct CaseBitsCmp { 402 bool operator () (const CaseBits& C1, const CaseBits& C2) { 403 return C1.Bits > C2.Bits; 404 } 405 }; 406 407 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 408 409public: 410 // TLI - This is information that describes the available target features we 411 // need for lowering. This indicates when operations are unavailable, 412 // implemented with a libcall, etc. 413 TargetLowering &TLI; 414 SelectionDAG &DAG; 415 const TargetData *TD; 416 AliasAnalysis &AA; 417 418 /// SwitchCases - Vector of CaseBlock structures used to communicate 419 /// SwitchInst code generation information. 420 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 421 /// JTCases - Vector of JumpTable structures used to communicate 422 /// SwitchInst code generation information. 423 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 424 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 425 426 /// FuncInfo - Information about the function as a whole. 427 /// 428 FunctionLoweringInfo &FuncInfo; 429 430 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 431 AliasAnalysis &aa, 432 FunctionLoweringInfo &funcinfo) 433 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa), 434 FuncInfo(funcinfo) { 435 } 436 437 /// getRoot - Return the current virtual root of the Selection DAG. 438 /// 439 SDOperand getRoot() { 440 if (PendingLoads.empty()) 441 return DAG.getRoot(); 442 443 if (PendingLoads.size() == 1) { 444 SDOperand Root = PendingLoads[0]; 445 DAG.setRoot(Root); 446 PendingLoads.clear(); 447 return Root; 448 } 449 450 // Otherwise, we have to make a token factor node. 451 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 452 &PendingLoads[0], PendingLoads.size()); 453 PendingLoads.clear(); 454 DAG.setRoot(Root); 455 return Root; 456 } 457 458 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 459 460 void visit(Instruction &I) { visit(I.getOpcode(), I); } 461 462 void visit(unsigned Opcode, User &I) { 463 // Note: this doesn't use InstVisitor, because it has to work with 464 // ConstantExpr's in addition to instructions. 465 switch (Opcode) { 466 default: assert(0 && "Unknown instruction type encountered!"); 467 abort(); 468 // Build the switch statement using the Instruction.def file. 469#define HANDLE_INST(NUM, OPCODE, CLASS) \ 470 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 471#include "llvm/Instruction.def" 472 } 473 } 474 475 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 476 477 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 478 const Value *SV, SDOperand Root, 479 bool isVolatile, unsigned Alignment); 480 481 SDOperand getIntPtrConstant(uint64_t Val) { 482 return DAG.getConstant(Val, TLI.getPointerTy()); 483 } 484 485 SDOperand getValue(const Value *V); 486 487 void setValue(const Value *V, SDOperand NewN) { 488 SDOperand &N = NodeMap[V]; 489 assert(N.Val == 0 && "Already set a value for this node!"); 490 N = NewN; 491 } 492 493 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 494 std::set<unsigned> &OutputRegs, 495 std::set<unsigned> &InputRegs); 496 497 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 498 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 499 unsigned Opc); 500 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 501 void ExportFromCurrentBlock(Value *V); 502 void LowerCallTo(Instruction &I, 503 const Type *CalledValueTy, unsigned CallingConv, 504 bool IsTailCall, SDOperand Callee, unsigned OpIdx, 505 MachineBasicBlock *LandingPad = NULL); 506 507 // Terminator instructions. 508 void visitRet(ReturnInst &I); 509 void visitBr(BranchInst &I); 510 void visitSwitch(SwitchInst &I); 511 void visitUnreachable(UnreachableInst &I) { /* noop */ } 512 513 // Helpers for visitSwitch 514 bool handleSmallSwitchRange(CaseRec& CR, 515 CaseRecVector& WorkList, 516 Value* SV, 517 MachineBasicBlock* Default); 518 bool handleJTSwitchCase(CaseRec& CR, 519 CaseRecVector& WorkList, 520 Value* SV, 521 MachineBasicBlock* Default); 522 bool handleBTSplitSwitchCase(CaseRec& CR, 523 CaseRecVector& WorkList, 524 Value* SV, 525 MachineBasicBlock* Default); 526 bool handleBitTestsSwitchCase(CaseRec& CR, 527 CaseRecVector& WorkList, 528 Value* SV, 529 MachineBasicBlock* Default); 530 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 531 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 532 void visitBitTestCase(MachineBasicBlock* NextMBB, 533 unsigned Reg, 534 SelectionDAGISel::BitTestCase &B); 535 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 536 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 537 SelectionDAGISel::JumpTableHeader &JTH); 538 539 // These all get lowered before this pass. 540 void visitInvoke(InvokeInst &I); 541 void visitUnwind(UnwindInst &I); 542 543 void visitBinary(User &I, unsigned OpCode); 544 void visitShift(User &I, unsigned Opcode); 545 void visitAdd(User &I) { 546 if (I.getType()->isFPOrFPVector()) 547 visitBinary(I, ISD::FADD); 548 else 549 visitBinary(I, ISD::ADD); 550 } 551 void visitSub(User &I); 552 void visitMul(User &I) { 553 if (I.getType()->isFPOrFPVector()) 554 visitBinary(I, ISD::FMUL); 555 else 556 visitBinary(I, ISD::MUL); 557 } 558 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 559 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 560 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 561 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 562 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 563 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 564 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 565 void visitOr (User &I) { visitBinary(I, ISD::OR); } 566 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 567 void visitShl (User &I) { visitShift(I, ISD::SHL); } 568 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 569 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 570 void visitICmp(User &I); 571 void visitFCmp(User &I); 572 // Visit the conversion instructions 573 void visitTrunc(User &I); 574 void visitZExt(User &I); 575 void visitSExt(User &I); 576 void visitFPTrunc(User &I); 577 void visitFPExt(User &I); 578 void visitFPToUI(User &I); 579 void visitFPToSI(User &I); 580 void visitUIToFP(User &I); 581 void visitSIToFP(User &I); 582 void visitPtrToInt(User &I); 583 void visitIntToPtr(User &I); 584 void visitBitCast(User &I); 585 586 void visitExtractElement(User &I); 587 void visitInsertElement(User &I); 588 void visitShuffleVector(User &I); 589 590 void visitGetElementPtr(User &I); 591 void visitSelect(User &I); 592 593 void visitMalloc(MallocInst &I); 594 void visitFree(FreeInst &I); 595 void visitAlloca(AllocaInst &I); 596 void visitLoad(LoadInst &I); 597 void visitStore(StoreInst &I); 598 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 599 void visitCall(CallInst &I); 600 void visitInlineAsm(CallInst &I); 601 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 602 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 603 604 void visitVAStart(CallInst &I); 605 void visitVAArg(VAArgInst &I); 606 void visitVAEnd(CallInst &I); 607 void visitVACopy(CallInst &I); 608 609 void visitMemIntrinsic(CallInst &I, unsigned Op); 610 611 void visitUserOp1(Instruction &I) { 612 assert(0 && "UserOp1 should not exist at instruction selection time!"); 613 abort(); 614 } 615 void visitUserOp2(Instruction &I) { 616 assert(0 && "UserOp2 should not exist at instruction selection time!"); 617 abort(); 618 } 619}; 620} // end namespace llvm 621 622 623/// getCopyFromParts - Create a value that contains the 624/// specified legal parts combined into the value they represent. 625static SDOperand getCopyFromParts(SelectionDAG &DAG, 626 const SDOperand *Parts, 627 unsigned NumParts, 628 MVT::ValueType PartVT, 629 MVT::ValueType ValueVT, 630 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 631 if (!MVT::isVector(ValueVT) || NumParts == 1) { 632 SDOperand Val = Parts[0]; 633 634 // If the value was expanded, copy from the top part. 635 if (NumParts > 1) { 636 assert(NumParts == 2 && 637 "Cannot expand to more than 2 elts yet!"); 638 SDOperand Hi = Parts[1]; 639 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 640 std::swap(Val, Hi); 641 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 642 } 643 644 // Otherwise, if the value was promoted or extended, truncate it to the 645 // appropriate type. 646 if (PartVT == ValueVT) 647 return Val; 648 649 if (MVT::isVector(PartVT)) { 650 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!"); 651 return DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 652 } 653 654 if (MVT::isInteger(PartVT) && 655 MVT::isInteger(ValueVT)) { 656 if (ValueVT < PartVT) { 657 // For a truncate, see if we have any information to 658 // indicate whether the truncated bits will always be 659 // zero or sign-extension. 660 if (AssertOp != ISD::DELETED_NODE) 661 Val = DAG.getNode(AssertOp, PartVT, Val, 662 DAG.getValueType(ValueVT)); 663 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 664 } else { 665 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 666 } 667 } 668 669 if (MVT::isFloatingPoint(PartVT) && 670 MVT::isFloatingPoint(ValueVT)) 671 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 672 673 if (MVT::getSizeInBits(PartVT) == 674 MVT::getSizeInBits(ValueVT)) 675 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 676 677 assert(0 && "Unknown mismatch!"); 678 } 679 680 // Handle a multi-element vector. 681 MVT::ValueType IntermediateVT, RegisterVT; 682 unsigned NumIntermediates; 683 unsigned NumRegs = 684 DAG.getTargetLoweringInfo() 685 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 686 RegisterVT); 687 688 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 689 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 690 assert(RegisterVT == Parts[0].getValueType() && 691 "Part type doesn't match part!"); 692 693 // Assemble the parts into intermediate operands. 694 SmallVector<SDOperand, 8> Ops(NumIntermediates); 695 if (NumIntermediates == NumParts) { 696 // If the register was not expanded, truncate or copy the value, 697 // as appropriate. 698 for (unsigned i = 0; i != NumParts; ++i) 699 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 700 PartVT, IntermediateVT); 701 } else if (NumParts > 0) { 702 // If the intermediate type was expanded, build the intermediate operands 703 // from the parts. 704 assert(NumParts % NumIntermediates == 0 && 705 "Must expand into a divisible number of parts!"); 706 unsigned Factor = NumParts / NumIntermediates; 707 for (unsigned i = 0; i != NumIntermediates; ++i) 708 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 709 PartVT, IntermediateVT); 710 } 711 712 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 713 // operands. 714 return DAG.getNode(MVT::isVector(IntermediateVT) ? 715 ISD::CONCAT_VECTORS : 716 ISD::BUILD_VECTOR, 717 ValueVT, &Ops[0], NumIntermediates); 718} 719 720/// getCopyToParts - Create a series of nodes that contain the 721/// specified value split into legal parts. 722static void getCopyToParts(SelectionDAG &DAG, 723 SDOperand Val, 724 SDOperand *Parts, 725 unsigned NumParts, 726 MVT::ValueType PartVT) { 727 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 728 MVT::ValueType PtrVT = TLI.getPointerTy(); 729 MVT::ValueType ValueVT = Val.getValueType(); 730 731 if (!MVT::isVector(ValueVT) || NumParts == 1) { 732 // If the value was expanded, copy from the parts. 733 if (NumParts > 1) { 734 for (unsigned i = 0; i != NumParts; ++i) 735 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val, 736 DAG.getConstant(i, PtrVT)); 737 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 738 std::reverse(Parts, Parts + NumParts); 739 return; 740 } 741 742 // If there is a single part and the types differ, this must be 743 // a promotion. 744 if (PartVT != ValueVT) { 745 if (MVT::isVector(PartVT)) { 746 assert(MVT::isVector(ValueVT) && 747 "Not a vector-vector cast?"); 748 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 749 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 750 if (PartVT < ValueVT) 751 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val); 752 else 753 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val); 754 } else if (MVT::isFloatingPoint(PartVT) && 755 MVT::isFloatingPoint(ValueVT)) { 756 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 757 } else if (MVT::getSizeInBits(PartVT) == 758 MVT::getSizeInBits(ValueVT)) { 759 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 760 } else { 761 assert(0 && "Unknown mismatch!"); 762 } 763 } 764 Parts[0] = Val; 765 return; 766 } 767 768 // Handle a multi-element vector. 769 MVT::ValueType IntermediateVT, RegisterVT; 770 unsigned NumIntermediates; 771 unsigned NumRegs = 772 DAG.getTargetLoweringInfo() 773 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 774 RegisterVT); 775 unsigned NumElements = MVT::getVectorNumElements(ValueVT); 776 777 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 778 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 779 780 // Split the vector into intermediate operands. 781 SmallVector<SDOperand, 8> Ops(NumIntermediates); 782 for (unsigned i = 0; i != NumIntermediates; ++i) 783 if (MVT::isVector(IntermediateVT)) 784 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 785 IntermediateVT, Val, 786 DAG.getConstant(i * (NumElements / NumIntermediates), 787 PtrVT)); 788 else 789 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 790 IntermediateVT, Val, 791 DAG.getConstant(i, PtrVT)); 792 793 // Split the intermediate operands into legal parts. 794 if (NumParts == NumIntermediates) { 795 // If the register was not expanded, promote or copy the value, 796 // as appropriate. 797 for (unsigned i = 0; i != NumParts; ++i) 798 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 799 } else if (NumParts > 0) { 800 // If the intermediate type was expanded, split each the value into 801 // legal parts. 802 assert(NumParts % NumIntermediates == 0 && 803 "Must expand into a divisible number of parts!"); 804 unsigned Factor = NumParts / NumIntermediates; 805 for (unsigned i = 0; i != NumIntermediates; ++i) 806 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 807 } 808} 809 810 811SDOperand SelectionDAGLowering::getValue(const Value *V) { 812 SDOperand &N = NodeMap[V]; 813 if (N.Val) return N; 814 815 const Type *VTy = V->getType(); 816 MVT::ValueType VT = TLI.getValueType(VTy); 817 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 818 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 819 visit(CE->getOpcode(), *CE); 820 SDOperand N1 = NodeMap[V]; 821 assert(N1.Val && "visit didn't populate the ValueMap!"); 822 return N1; 823 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 824 return N = DAG.getGlobalAddress(GV, VT); 825 } else if (isa<ConstantPointerNull>(C)) { 826 return N = DAG.getConstant(0, TLI.getPointerTy()); 827 } else if (isa<UndefValue>(C)) { 828 if (!isa<VectorType>(VTy)) 829 return N = DAG.getNode(ISD::UNDEF, VT); 830 831 // Create a BUILD_VECTOR of undef nodes. 832 const VectorType *PTy = cast<VectorType>(VTy); 833 unsigned NumElements = PTy->getNumElements(); 834 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 835 836 SmallVector<SDOperand, 8> Ops; 837 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 838 839 // Create a VConstant node with generic Vector type. 840 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 841 return N = DAG.getNode(ISD::BUILD_VECTOR, VT, 842 &Ops[0], Ops.size()); 843 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 844 return N = DAG.getConstantFP(CFP->getValueAPF(), VT); 845 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 846 unsigned NumElements = PTy->getNumElements(); 847 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 848 849 // Now that we know the number and type of the elements, push a 850 // Constant or ConstantFP node onto the ops list for each element of 851 // the vector constant. 852 SmallVector<SDOperand, 8> Ops; 853 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 854 for (unsigned i = 0; i != NumElements; ++i) 855 Ops.push_back(getValue(CP->getOperand(i))); 856 } else { 857 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 858 SDOperand Op; 859 if (MVT::isFloatingPoint(PVT)) 860 Op = DAG.getConstantFP(0, PVT); 861 else 862 Op = DAG.getConstant(0, PVT); 863 Ops.assign(NumElements, Op); 864 } 865 866 // Create a BUILD_VECTOR node. 867 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 868 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], 869 Ops.size()); 870 } else { 871 // Canonicalize all constant ints to be unsigned. 872 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT); 873 } 874 } 875 876 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 877 std::map<const AllocaInst*, int>::iterator SI = 878 FuncInfo.StaticAllocaMap.find(AI); 879 if (SI != FuncInfo.StaticAllocaMap.end()) 880 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 881 } 882 883 unsigned InReg = FuncInfo.ValueMap[V]; 884 assert(InReg && "Value not in map!"); 885 886 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 887 unsigned NumRegs = TLI.getNumRegisters(VT); 888 889 std::vector<unsigned> Regs(NumRegs); 890 for (unsigned i = 0; i != NumRegs; ++i) 891 Regs[i] = InReg + i; 892 893 RegsForValue RFV(Regs, RegisterVT, VT); 894 SDOperand Chain = DAG.getEntryNode(); 895 896 return RFV.getCopyFromRegs(DAG, Chain, NULL); 897} 898 899 900void SelectionDAGLowering::visitRet(ReturnInst &I) { 901 if (I.getNumOperands() == 0) { 902 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 903 return; 904 } 905 SmallVector<SDOperand, 8> NewValues; 906 NewValues.push_back(getRoot()); 907 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 908 SDOperand RetOp = getValue(I.getOperand(i)); 909 910 // If this is an integer return value, we need to promote it ourselves to 911 // the full width of a register, since getCopyToParts and Legalize will use 912 // ANY_EXTEND rather than sign/zero. 913 // FIXME: C calling convention requires the return type to be promoted to 914 // at least 32-bit. But this is not necessary for non-C calling conventions. 915 if (MVT::isInteger(RetOp.getValueType()) && 916 RetOp.getValueType() < MVT::i64) { 917 MVT::ValueType TmpVT; 918 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 919 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 920 else 921 TmpVT = MVT::i32; 922 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType(); 923 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 924 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 925 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt)) 926 ExtendKind = ISD::SIGN_EXTEND; 927 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt)) 928 ExtendKind = ISD::ZERO_EXTEND; 929 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp); 930 NewValues.push_back(RetOp); 931 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 932 } else { 933 MVT::ValueType VT = RetOp.getValueType(); 934 unsigned NumParts = TLI.getNumRegisters(VT); 935 MVT::ValueType PartVT = TLI.getRegisterType(VT); 936 SmallVector<SDOperand, 4> Parts(NumParts); 937 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT); 938 for (unsigned i = 0; i < NumParts; ++i) { 939 NewValues.push_back(Parts[i]); 940 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 941 } 942 } 943 } 944 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 945 &NewValues[0], NewValues.size())); 946} 947 948/// ExportFromCurrentBlock - If this condition isn't known to be exported from 949/// the current basic block, add it to ValueMap now so that we'll get a 950/// CopyTo/FromReg. 951void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 952 // No need to export constants. 953 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 954 955 // Already exported? 956 if (FuncInfo.isExportedInst(V)) return; 957 958 unsigned Reg = FuncInfo.InitializeRegForValue(V); 959 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 960} 961 962bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 963 const BasicBlock *FromBB) { 964 // The operands of the setcc have to be in this block. We don't know 965 // how to export them from some other block. 966 if (Instruction *VI = dyn_cast<Instruction>(V)) { 967 // Can export from current BB. 968 if (VI->getParent() == FromBB) 969 return true; 970 971 // Is already exported, noop. 972 return FuncInfo.isExportedInst(V); 973 } 974 975 // If this is an argument, we can export it if the BB is the entry block or 976 // if it is already exported. 977 if (isa<Argument>(V)) { 978 if (FromBB == &FromBB->getParent()->getEntryBlock()) 979 return true; 980 981 // Otherwise, can only export this if it is already exported. 982 return FuncInfo.isExportedInst(V); 983 } 984 985 // Otherwise, constants can always be exported. 986 return true; 987} 988 989static bool InBlock(const Value *V, const BasicBlock *BB) { 990 if (const Instruction *I = dyn_cast<Instruction>(V)) 991 return I->getParent() == BB; 992 return true; 993} 994 995/// FindMergedConditions - If Cond is an expression like 996void SelectionDAGLowering::FindMergedConditions(Value *Cond, 997 MachineBasicBlock *TBB, 998 MachineBasicBlock *FBB, 999 MachineBasicBlock *CurBB, 1000 unsigned Opc) { 1001 // If this node is not part of the or/and tree, emit it as a branch. 1002 Instruction *BOp = dyn_cast<Instruction>(Cond); 1003 1004 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1005 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1006 BOp->getParent() != CurBB->getBasicBlock() || 1007 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1008 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1009 const BasicBlock *BB = CurBB->getBasicBlock(); 1010 1011 // If the leaf of the tree is a comparison, merge the condition into 1012 // the caseblock. 1013 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1014 // The operands of the cmp have to be in this block. We don't know 1015 // how to export them from some other block. If this is the first block 1016 // of the sequence, no exporting is needed. 1017 (CurBB == CurMBB || 1018 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1019 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1020 BOp = cast<Instruction>(Cond); 1021 ISD::CondCode Condition; 1022 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1023 switch (IC->getPredicate()) { 1024 default: assert(0 && "Unknown icmp predicate opcode!"); 1025 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1026 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1027 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1028 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1029 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1030 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1031 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1032 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1033 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1034 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1035 } 1036 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1037 ISD::CondCode FPC, FOC; 1038 switch (FC->getPredicate()) { 1039 default: assert(0 && "Unknown fcmp predicate opcode!"); 1040 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1041 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1042 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1043 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1044 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1045 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1046 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1047 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 1048 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 1049 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1050 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1051 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1052 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1053 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1054 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1055 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1056 } 1057 if (FiniteOnlyFPMath()) 1058 Condition = FOC; 1059 else 1060 Condition = FPC; 1061 } else { 1062 Condition = ISD::SETEQ; // silence warning. 1063 assert(0 && "Unknown compare instruction"); 1064 } 1065 1066 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1067 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1068 SwitchCases.push_back(CB); 1069 return; 1070 } 1071 1072 // Create a CaseBlock record representing this branch. 1073 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1074 NULL, TBB, FBB, CurBB); 1075 SwitchCases.push_back(CB); 1076 return; 1077 } 1078 1079 1080 // Create TmpBB after CurBB. 1081 MachineFunction::iterator BBI = CurBB; 1082 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 1083 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 1084 1085 if (Opc == Instruction::Or) { 1086 // Codegen X | Y as: 1087 // jmp_if_X TBB 1088 // jmp TmpBB 1089 // TmpBB: 1090 // jmp_if_Y TBB 1091 // jmp FBB 1092 // 1093 1094 // Emit the LHS condition. 1095 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1096 1097 // Emit the RHS condition into TmpBB. 1098 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1099 } else { 1100 assert(Opc == Instruction::And && "Unknown merge op!"); 1101 // Codegen X & Y as: 1102 // jmp_if_X TmpBB 1103 // jmp FBB 1104 // TmpBB: 1105 // jmp_if_Y TBB 1106 // jmp FBB 1107 // 1108 // This requires creation of TmpBB after CurBB. 1109 1110 // Emit the LHS condition. 1111 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1112 1113 // Emit the RHS condition into TmpBB. 1114 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1115 } 1116} 1117 1118/// If the set of cases should be emitted as a series of branches, return true. 1119/// If we should emit this as a bunch of and/or'd together conditions, return 1120/// false. 1121static bool 1122ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1123 if (Cases.size() != 2) return true; 1124 1125 // If this is two comparisons of the same values or'd or and'd together, they 1126 // will get folded into a single comparison, so don't emit two blocks. 1127 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1128 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1129 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1130 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1131 return false; 1132 } 1133 1134 return true; 1135} 1136 1137void SelectionDAGLowering::visitBr(BranchInst &I) { 1138 // Update machine-CFG edges. 1139 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1140 1141 // Figure out which block is immediately after the current one. 1142 MachineBasicBlock *NextBlock = 0; 1143 MachineFunction::iterator BBI = CurMBB; 1144 if (++BBI != CurMBB->getParent()->end()) 1145 NextBlock = BBI; 1146 1147 if (I.isUnconditional()) { 1148 // If this is not a fall-through branch, emit the branch. 1149 if (Succ0MBB != NextBlock) 1150 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1151 DAG.getBasicBlock(Succ0MBB))); 1152 1153 // Update machine-CFG edges. 1154 CurMBB->addSuccessor(Succ0MBB); 1155 1156 return; 1157 } 1158 1159 // If this condition is one of the special cases we handle, do special stuff 1160 // now. 1161 Value *CondVal = I.getCondition(); 1162 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1163 1164 // If this is a series of conditions that are or'd or and'd together, emit 1165 // this as a sequence of branches instead of setcc's with and/or operations. 1166 // For example, instead of something like: 1167 // cmp A, B 1168 // C = seteq 1169 // cmp D, E 1170 // F = setle 1171 // or C, F 1172 // jnz foo 1173 // Emit: 1174 // cmp A, B 1175 // je foo 1176 // cmp D, E 1177 // jle foo 1178 // 1179 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1180 if (BOp->hasOneUse() && 1181 (BOp->getOpcode() == Instruction::And || 1182 BOp->getOpcode() == Instruction::Or)) { 1183 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1184 // If the compares in later blocks need to use values not currently 1185 // exported from this block, export them now. This block should always 1186 // be the first entry. 1187 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1188 1189 // Allow some cases to be rejected. 1190 if (ShouldEmitAsBranches(SwitchCases)) { 1191 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1192 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1193 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1194 } 1195 1196 // Emit the branch for this block. 1197 visitSwitchCase(SwitchCases[0]); 1198 SwitchCases.erase(SwitchCases.begin()); 1199 return; 1200 } 1201 1202 // Okay, we decided not to do this, remove any inserted MBB's and clear 1203 // SwitchCases. 1204 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1205 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1206 1207 SwitchCases.clear(); 1208 } 1209 } 1210 1211 // Create a CaseBlock record representing this branch. 1212 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1213 NULL, Succ0MBB, Succ1MBB, CurMBB); 1214 // Use visitSwitchCase to actually insert the fast branch sequence for this 1215 // cond branch. 1216 visitSwitchCase(CB); 1217} 1218 1219/// visitSwitchCase - Emits the necessary code to represent a single node in 1220/// the binary search tree resulting from lowering a switch instruction. 1221void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1222 SDOperand Cond; 1223 SDOperand CondLHS = getValue(CB.CmpLHS); 1224 1225 // Build the setcc now. 1226 if (CB.CmpMHS == NULL) { 1227 // Fold "(X == true)" to X and "(X == false)" to !X to 1228 // handle common cases produced by branch lowering. 1229 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1230 Cond = CondLHS; 1231 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1232 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1233 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1234 } else 1235 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1236 } else { 1237 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1238 1239 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1240 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1241 1242 SDOperand CmpOp = getValue(CB.CmpMHS); 1243 MVT::ValueType VT = CmpOp.getValueType(); 1244 1245 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1246 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1247 } else { 1248 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1249 Cond = DAG.getSetCC(MVT::i1, SUB, 1250 DAG.getConstant(High-Low, VT), ISD::SETULE); 1251 } 1252 1253 } 1254 1255 // Set NextBlock to be the MBB immediately after the current one, if any. 1256 // This is used to avoid emitting unnecessary branches to the next block. 1257 MachineBasicBlock *NextBlock = 0; 1258 MachineFunction::iterator BBI = CurMBB; 1259 if (++BBI != CurMBB->getParent()->end()) 1260 NextBlock = BBI; 1261 1262 // If the lhs block is the next block, invert the condition so that we can 1263 // fall through to the lhs instead of the rhs block. 1264 if (CB.TrueBB == NextBlock) { 1265 std::swap(CB.TrueBB, CB.FalseBB); 1266 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1267 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1268 } 1269 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1270 DAG.getBasicBlock(CB.TrueBB)); 1271 if (CB.FalseBB == NextBlock) 1272 DAG.setRoot(BrCond); 1273 else 1274 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1275 DAG.getBasicBlock(CB.FalseBB))); 1276 // Update successor info 1277 CurMBB->addSuccessor(CB.TrueBB); 1278 CurMBB->addSuccessor(CB.FalseBB); 1279} 1280 1281/// visitJumpTable - Emit JumpTable node in the current MBB 1282void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1283 // Emit the code for the jump table 1284 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1285 MVT::ValueType PTy = TLI.getPointerTy(); 1286 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1287 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1288 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1289 Table, Index)); 1290 return; 1291} 1292 1293/// visitJumpTableHeader - This function emits necessary code to produce index 1294/// in the JumpTable from switch case. 1295void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1296 SelectionDAGISel::JumpTableHeader &JTH) { 1297 // Subtract the lowest switch case value from the value being switched on 1298 // and conditional branch to default mbb if the result is greater than the 1299 // difference between smallest and largest cases. 1300 SDOperand SwitchOp = getValue(JTH.SValue); 1301 MVT::ValueType VT = SwitchOp.getValueType(); 1302 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1303 DAG.getConstant(JTH.First, VT)); 1304 1305 // The SDNode we just created, which holds the value being switched on 1306 // minus the the smallest case value, needs to be copied to a virtual 1307 // register so it can be used as an index into the jump table in a 1308 // subsequent basic block. This value may be smaller or larger than the 1309 // target's pointer type, and therefore require extension or truncating. 1310 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 1311 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1312 else 1313 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1314 1315 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1316 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1317 JT.Reg = JumpTableReg; 1318 1319 // Emit the range check for the jump table, and branch to the default 1320 // block for the switch statement if the value being switched on exceeds 1321 // the largest case in the switch. 1322 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1323 DAG.getConstant(JTH.Last-JTH.First,VT), 1324 ISD::SETUGT); 1325 1326 // Set NextBlock to be the MBB immediately after the current one, if any. 1327 // This is used to avoid emitting unnecessary branches to the next block. 1328 MachineBasicBlock *NextBlock = 0; 1329 MachineFunction::iterator BBI = CurMBB; 1330 if (++BBI != CurMBB->getParent()->end()) 1331 NextBlock = BBI; 1332 1333 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1334 DAG.getBasicBlock(JT.Default)); 1335 1336 if (JT.MBB == NextBlock) 1337 DAG.setRoot(BrCond); 1338 else 1339 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1340 DAG.getBasicBlock(JT.MBB))); 1341 1342 return; 1343} 1344 1345/// visitBitTestHeader - This function emits necessary code to produce value 1346/// suitable for "bit tests" 1347void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1348 // Subtract the minimum value 1349 SDOperand SwitchOp = getValue(B.SValue); 1350 MVT::ValueType VT = SwitchOp.getValueType(); 1351 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1352 DAG.getConstant(B.First, VT)); 1353 1354 // Check range 1355 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1356 DAG.getConstant(B.Range, VT), 1357 ISD::SETUGT); 1358 1359 SDOperand ShiftOp; 1360 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy())) 1361 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1362 else 1363 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1364 1365 // Make desired shift 1366 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1367 DAG.getConstant(1, TLI.getPointerTy()), 1368 ShiftOp); 1369 1370 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1371 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1372 B.Reg = SwitchReg; 1373 1374 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1375 DAG.getBasicBlock(B.Default)); 1376 1377 // Set NextBlock to be the MBB immediately after the current one, if any. 1378 // This is used to avoid emitting unnecessary branches to the next block. 1379 MachineBasicBlock *NextBlock = 0; 1380 MachineFunction::iterator BBI = CurMBB; 1381 if (++BBI != CurMBB->getParent()->end()) 1382 NextBlock = BBI; 1383 1384 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1385 if (MBB == NextBlock) 1386 DAG.setRoot(BrRange); 1387 else 1388 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1389 DAG.getBasicBlock(MBB))); 1390 1391 CurMBB->addSuccessor(B.Default); 1392 CurMBB->addSuccessor(MBB); 1393 1394 return; 1395} 1396 1397/// visitBitTestCase - this function produces one "bit test" 1398void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1399 unsigned Reg, 1400 SelectionDAGISel::BitTestCase &B) { 1401 // Emit bit tests and jumps 1402 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1403 1404 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1405 SwitchVal, 1406 DAG.getConstant(B.Mask, 1407 TLI.getPointerTy())); 1408 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, 1409 DAG.getConstant(0, TLI.getPointerTy()), 1410 ISD::SETNE); 1411 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1412 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1413 1414 // Set NextBlock to be the MBB immediately after the current one, if any. 1415 // This is used to avoid emitting unnecessary branches to the next block. 1416 MachineBasicBlock *NextBlock = 0; 1417 MachineFunction::iterator BBI = CurMBB; 1418 if (++BBI != CurMBB->getParent()->end()) 1419 NextBlock = BBI; 1420 1421 if (NextMBB == NextBlock) 1422 DAG.setRoot(BrAnd); 1423 else 1424 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1425 DAG.getBasicBlock(NextMBB))); 1426 1427 CurMBB->addSuccessor(B.TargetBB); 1428 CurMBB->addSuccessor(NextMBB); 1429 1430 return; 1431} 1432 1433void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1434 // Retrieve successors. 1435 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1436 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1437 1438 LowerCallTo(I, I.getCalledValue()->getType(), 1439 I.getCallingConv(), 1440 false, 1441 getValue(I.getOperand(0)), 1442 3, LandingPad); 1443 1444 // If the value of the invoke is used outside of its defining block, make it 1445 // available as a virtual register. 1446 if (!I.use_empty()) { 1447 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1448 if (VMI != FuncInfo.ValueMap.end()) 1449 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second)); 1450 } 1451 1452 // Drop into normal successor. 1453 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1454 DAG.getBasicBlock(Return))); 1455 1456 // Update successor info 1457 CurMBB->addSuccessor(Return); 1458 CurMBB->addSuccessor(LandingPad); 1459} 1460 1461void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1462} 1463 1464/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1465/// small case ranges). 1466bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1467 CaseRecVector& WorkList, 1468 Value* SV, 1469 MachineBasicBlock* Default) { 1470 Case& BackCase = *(CR.Range.second-1); 1471 1472 // Size is the number of Cases represented by this range. 1473 unsigned Size = CR.Range.second - CR.Range.first; 1474 if (Size > 3) 1475 return false; 1476 1477 // Get the MachineFunction which holds the current MBB. This is used when 1478 // inserting any additional MBBs necessary to represent the switch. 1479 MachineFunction *CurMF = CurMBB->getParent(); 1480 1481 // Figure out which block is immediately after the current one. 1482 MachineBasicBlock *NextBlock = 0; 1483 MachineFunction::iterator BBI = CR.CaseBB; 1484 1485 if (++BBI != CurMBB->getParent()->end()) 1486 NextBlock = BBI; 1487 1488 // TODO: If any two of the cases has the same destination, and if one value 1489 // is the same as the other, but has one bit unset that the other has set, 1490 // use bit manipulation to do two compares at once. For example: 1491 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1492 1493 // Rearrange the case blocks so that the last one falls through if possible. 1494 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1495 // The last case block won't fall through into 'NextBlock' if we emit the 1496 // branches in this order. See if rearranging a case value would help. 1497 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1498 if (I->BB == NextBlock) { 1499 std::swap(*I, BackCase); 1500 break; 1501 } 1502 } 1503 } 1504 1505 // Create a CaseBlock record representing a conditional branch to 1506 // the Case's target mbb if the value being switched on SV is equal 1507 // to C. 1508 MachineBasicBlock *CurBlock = CR.CaseBB; 1509 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1510 MachineBasicBlock *FallThrough; 1511 if (I != E-1) { 1512 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1513 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1514 } else { 1515 // If the last case doesn't match, go to the default block. 1516 FallThrough = Default; 1517 } 1518 1519 Value *RHS, *LHS, *MHS; 1520 ISD::CondCode CC; 1521 if (I->High == I->Low) { 1522 // This is just small small case range :) containing exactly 1 case 1523 CC = ISD::SETEQ; 1524 LHS = SV; RHS = I->High; MHS = NULL; 1525 } else { 1526 CC = ISD::SETLE; 1527 LHS = I->Low; MHS = SV; RHS = I->High; 1528 } 1529 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1530 I->BB, FallThrough, CurBlock); 1531 1532 // If emitting the first comparison, just call visitSwitchCase to emit the 1533 // code into the current block. Otherwise, push the CaseBlock onto the 1534 // vector to be later processed by SDISel, and insert the node's MBB 1535 // before the next MBB. 1536 if (CurBlock == CurMBB) 1537 visitSwitchCase(CB); 1538 else 1539 SwitchCases.push_back(CB); 1540 1541 CurBlock = FallThrough; 1542 } 1543 1544 return true; 1545} 1546 1547static inline bool areJTsAllowed(const TargetLowering &TLI) { 1548 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1549 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1550} 1551 1552/// handleJTSwitchCase - Emit jumptable for current switch case range 1553bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1554 CaseRecVector& WorkList, 1555 Value* SV, 1556 MachineBasicBlock* Default) { 1557 Case& FrontCase = *CR.Range.first; 1558 Case& BackCase = *(CR.Range.second-1); 1559 1560 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1561 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1562 1563 uint64_t TSize = 0; 1564 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1565 I!=E; ++I) 1566 TSize += I->size(); 1567 1568 if (!areJTsAllowed(TLI) || TSize <= 3) 1569 return false; 1570 1571 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1572 if (Density < 0.4) 1573 return false; 1574 1575 DOUT << "Lowering jump table\n" 1576 << "First entry: " << First << ". Last entry: " << Last << "\n" 1577 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1578 1579 // Get the MachineFunction which holds the current MBB. This is used when 1580 // inserting any additional MBBs necessary to represent the switch. 1581 MachineFunction *CurMF = CurMBB->getParent(); 1582 1583 // Figure out which block is immediately after the current one. 1584 MachineBasicBlock *NextBlock = 0; 1585 MachineFunction::iterator BBI = CR.CaseBB; 1586 1587 if (++BBI != CurMBB->getParent()->end()) 1588 NextBlock = BBI; 1589 1590 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1591 1592 // Create a new basic block to hold the code for loading the address 1593 // of the jump table, and jumping to it. Update successor information; 1594 // we will either branch to the default case for the switch, or the jump 1595 // table. 1596 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1597 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1598 CR.CaseBB->addSuccessor(Default); 1599 CR.CaseBB->addSuccessor(JumpTableBB); 1600 1601 // Build a vector of destination BBs, corresponding to each target 1602 // of the jump table. If the value of the jump table slot corresponds to 1603 // a case statement, push the case's BB onto the vector, otherwise, push 1604 // the default BB. 1605 std::vector<MachineBasicBlock*> DestBBs; 1606 int64_t TEI = First; 1607 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1608 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1609 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1610 1611 if ((Low <= TEI) && (TEI <= High)) { 1612 DestBBs.push_back(I->BB); 1613 if (TEI==High) 1614 ++I; 1615 } else { 1616 DestBBs.push_back(Default); 1617 } 1618 } 1619 1620 // Update successor info. Add one edge to each unique successor. 1621 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1622 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1623 E = DestBBs.end(); I != E; ++I) { 1624 if (!SuccsHandled[(*I)->getNumber()]) { 1625 SuccsHandled[(*I)->getNumber()] = true; 1626 JumpTableBB->addSuccessor(*I); 1627 } 1628 } 1629 1630 // Create a jump table index for this jump table, or return an existing 1631 // one. 1632 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1633 1634 // Set the jump table information so that we can codegen it as a second 1635 // MachineBasicBlock 1636 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1637 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1638 (CR.CaseBB == CurMBB)); 1639 if (CR.CaseBB == CurMBB) 1640 visitJumpTableHeader(JT, JTH); 1641 1642 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1643 1644 return true; 1645} 1646 1647/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1648/// 2 subtrees. 1649bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1650 CaseRecVector& WorkList, 1651 Value* SV, 1652 MachineBasicBlock* Default) { 1653 // Get the MachineFunction which holds the current MBB. This is used when 1654 // inserting any additional MBBs necessary to represent the switch. 1655 MachineFunction *CurMF = CurMBB->getParent(); 1656 1657 // Figure out which block is immediately after the current one. 1658 MachineBasicBlock *NextBlock = 0; 1659 MachineFunction::iterator BBI = CR.CaseBB; 1660 1661 if (++BBI != CurMBB->getParent()->end()) 1662 NextBlock = BBI; 1663 1664 Case& FrontCase = *CR.Range.first; 1665 Case& BackCase = *(CR.Range.second-1); 1666 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1667 1668 // Size is the number of Cases represented by this range. 1669 unsigned Size = CR.Range.second - CR.Range.first; 1670 1671 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1672 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1673 double FMetric = 0; 1674 CaseItr Pivot = CR.Range.first + Size/2; 1675 1676 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1677 // (heuristically) allow us to emit JumpTable's later. 1678 uint64_t TSize = 0; 1679 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1680 I!=E; ++I) 1681 TSize += I->size(); 1682 1683 uint64_t LSize = FrontCase.size(); 1684 uint64_t RSize = TSize-LSize; 1685 DOUT << "Selecting best pivot: \n" 1686 << "First: " << First << ", Last: " << Last <<"\n" 1687 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1688 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1689 J!=E; ++I, ++J) { 1690 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1691 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1692 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1693 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1694 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1695 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1696 // Should always split in some non-trivial place 1697 DOUT <<"=>Step\n" 1698 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1699 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1700 << "Metric: " << Metric << "\n"; 1701 if (FMetric < Metric) { 1702 Pivot = J; 1703 FMetric = Metric; 1704 DOUT << "Current metric set to: " << FMetric << "\n"; 1705 } 1706 1707 LSize += J->size(); 1708 RSize -= J->size(); 1709 } 1710 if (areJTsAllowed(TLI)) { 1711 // If our case is dense we *really* should handle it earlier! 1712 assert((FMetric > 0) && "Should handle dense range earlier!"); 1713 } else { 1714 Pivot = CR.Range.first + Size/2; 1715 } 1716 1717 CaseRange LHSR(CR.Range.first, Pivot); 1718 CaseRange RHSR(Pivot, CR.Range.second); 1719 Constant *C = Pivot->Low; 1720 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1721 1722 // We know that we branch to the LHS if the Value being switched on is 1723 // less than the Pivot value, C. We use this to optimize our binary 1724 // tree a bit, by recognizing that if SV is greater than or equal to the 1725 // LHS's Case Value, and that Case Value is exactly one less than the 1726 // Pivot's Value, then we can branch directly to the LHS's Target, 1727 // rather than creating a leaf node for it. 1728 if ((LHSR.second - LHSR.first) == 1 && 1729 LHSR.first->High == CR.GE && 1730 cast<ConstantInt>(C)->getSExtValue() == 1731 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1732 TrueBB = LHSR.first->BB; 1733 } else { 1734 TrueBB = new MachineBasicBlock(LLVMBB); 1735 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1736 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1737 } 1738 1739 // Similar to the optimization above, if the Value being switched on is 1740 // known to be less than the Constant CR.LT, and the current Case Value 1741 // is CR.LT - 1, then we can branch directly to the target block for 1742 // the current Case Value, rather than emitting a RHS leaf node for it. 1743 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1744 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1745 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1746 FalseBB = RHSR.first->BB; 1747 } else { 1748 FalseBB = new MachineBasicBlock(LLVMBB); 1749 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1750 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1751 } 1752 1753 // Create a CaseBlock record representing a conditional branch to 1754 // the LHS node if the value being switched on SV is less than C. 1755 // Otherwise, branch to LHS. 1756 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1757 TrueBB, FalseBB, CR.CaseBB); 1758 1759 if (CR.CaseBB == CurMBB) 1760 visitSwitchCase(CB); 1761 else 1762 SwitchCases.push_back(CB); 1763 1764 return true; 1765} 1766 1767/// handleBitTestsSwitchCase - if current case range has few destination and 1768/// range span less, than machine word bitwidth, encode case range into series 1769/// of masks and emit bit tests with these masks. 1770bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1771 CaseRecVector& WorkList, 1772 Value* SV, 1773 MachineBasicBlock* Default){ 1774 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); 1775 1776 Case& FrontCase = *CR.Range.first; 1777 Case& BackCase = *(CR.Range.second-1); 1778 1779 // Get the MachineFunction which holds the current MBB. This is used when 1780 // inserting any additional MBBs necessary to represent the switch. 1781 MachineFunction *CurMF = CurMBB->getParent(); 1782 1783 unsigned numCmps = 0; 1784 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1785 I!=E; ++I) { 1786 // Single case counts one, case range - two. 1787 if (I->Low == I->High) 1788 numCmps +=1; 1789 else 1790 numCmps +=2; 1791 } 1792 1793 // Count unique destinations 1794 SmallSet<MachineBasicBlock*, 4> Dests; 1795 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1796 Dests.insert(I->BB); 1797 if (Dests.size() > 3) 1798 // Don't bother the code below, if there are too much unique destinations 1799 return false; 1800 } 1801 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1802 << "Total number of comparisons: " << numCmps << "\n"; 1803 1804 // Compute span of values. 1805 Constant* minValue = FrontCase.Low; 1806 Constant* maxValue = BackCase.High; 1807 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1808 cast<ConstantInt>(minValue)->getSExtValue(); 1809 DOUT << "Compare range: " << range << "\n" 1810 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1811 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1812 1813 if (range>=IntPtrBits || 1814 (!(Dests.size() == 1 && numCmps >= 3) && 1815 !(Dests.size() == 2 && numCmps >= 5) && 1816 !(Dests.size() >= 3 && numCmps >= 6))) 1817 return false; 1818 1819 DOUT << "Emitting bit tests\n"; 1820 int64_t lowBound = 0; 1821 1822 // Optimize the case where all the case values fit in a 1823 // word without having to subtract minValue. In this case, 1824 // we can optimize away the subtraction. 1825 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1826 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1827 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1828 } else { 1829 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1830 } 1831 1832 CaseBitsVector CasesBits; 1833 unsigned i, count = 0; 1834 1835 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1836 MachineBasicBlock* Dest = I->BB; 1837 for (i = 0; i < count; ++i) 1838 if (Dest == CasesBits[i].BB) 1839 break; 1840 1841 if (i == count) { 1842 assert((count < 3) && "Too much destinations to test!"); 1843 CasesBits.push_back(CaseBits(0, Dest, 0)); 1844 count++; 1845 } 1846 1847 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1848 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1849 1850 for (uint64_t j = lo; j <= hi; j++) { 1851 CasesBits[i].Mask |= 1ULL << j; 1852 CasesBits[i].Bits++; 1853 } 1854 1855 } 1856 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1857 1858 SelectionDAGISel::BitTestInfo BTC; 1859 1860 // Figure out which block is immediately after the current one. 1861 MachineFunction::iterator BBI = CR.CaseBB; 1862 ++BBI; 1863 1864 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1865 1866 DOUT << "Cases:\n"; 1867 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1868 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1869 << ", BB: " << CasesBits[i].BB << "\n"; 1870 1871 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1872 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1873 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1874 CaseBB, 1875 CasesBits[i].BB)); 1876 } 1877 1878 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 1879 -1U, (CR.CaseBB == CurMBB), 1880 CR.CaseBB, Default, BTC); 1881 1882 if (CR.CaseBB == CurMBB) 1883 visitBitTestHeader(BTB); 1884 1885 BitTestCases.push_back(BTB); 1886 1887 return true; 1888} 1889 1890 1891// Clusterify - Transform simple list of Cases into list of CaseRange's 1892unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 1893 const SwitchInst& SI) { 1894 unsigned numCmps = 0; 1895 1896 // Start with "simple" cases 1897 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 1898 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1899 Cases.push_back(Case(SI.getSuccessorValue(i), 1900 SI.getSuccessorValue(i), 1901 SMBB)); 1902 } 1903 sort(Cases.begin(), Cases.end(), CaseCmp()); 1904 1905 // Merge case into clusters 1906 if (Cases.size()>=2) 1907 // Must recompute end() each iteration because it may be 1908 // invalidated by erase if we hold on to it 1909 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 1910 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 1911 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 1912 MachineBasicBlock* nextBB = J->BB; 1913 MachineBasicBlock* currentBB = I->BB; 1914 1915 // If the two neighboring cases go to the same destination, merge them 1916 // into a single case. 1917 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 1918 I->High = J->High; 1919 J = Cases.erase(J); 1920 } else { 1921 I = J++; 1922 } 1923 } 1924 1925 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1926 if (I->Low != I->High) 1927 // A range counts double, since it requires two compares. 1928 ++numCmps; 1929 } 1930 1931 return numCmps; 1932} 1933 1934void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 1935 // Figure out which block is immediately after the current one. 1936 MachineBasicBlock *NextBlock = 0; 1937 MachineFunction::iterator BBI = CurMBB; 1938 1939 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 1940 1941 // If there is only the default destination, branch to it if it is not the 1942 // next basic block. Otherwise, just fall through. 1943 if (SI.getNumOperands() == 2) { 1944 // Update machine-CFG edges. 1945 1946 // If this is not a fall-through branch, emit the branch. 1947 if (Default != NextBlock) 1948 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1949 DAG.getBasicBlock(Default))); 1950 1951 CurMBB->addSuccessor(Default); 1952 return; 1953 } 1954 1955 // If there are any non-default case statements, create a vector of Cases 1956 // representing each one, and sort the vector so that we can efficiently 1957 // create a binary search tree from them. 1958 CaseVector Cases; 1959 unsigned numCmps = Clusterify(Cases, SI); 1960 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 1961 << ". Total compares: " << numCmps << "\n"; 1962 1963 // Get the Value to be switched on and default basic blocks, which will be 1964 // inserted into CaseBlock records, representing basic blocks in the binary 1965 // search tree. 1966 Value *SV = SI.getOperand(0); 1967 1968 // Push the initial CaseRec onto the worklist 1969 CaseRecVector WorkList; 1970 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1971 1972 while (!WorkList.empty()) { 1973 // Grab a record representing a case range to process off the worklist 1974 CaseRec CR = WorkList.back(); 1975 WorkList.pop_back(); 1976 1977 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 1978 continue; 1979 1980 // If the range has few cases (two or less) emit a series of specific 1981 // tests. 1982 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 1983 continue; 1984 1985 // If the switch has more than 5 blocks, and at least 40% dense, and the 1986 // target supports indirect branches, then emit a jump table rather than 1987 // lowering the switch to a binary tree of conditional branches. 1988 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 1989 continue; 1990 1991 // Emit binary tree. We need to pick a pivot, and push left and right ranges 1992 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 1993 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 1994 } 1995} 1996 1997 1998void SelectionDAGLowering::visitSub(User &I) { 1999 // -0.0 - X --> fneg 2000 const Type *Ty = I.getType(); 2001 if (isa<VectorType>(Ty)) { 2002 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2003 const VectorType *DestTy = cast<VectorType>(I.getType()); 2004 const Type *ElTy = DestTy->getElementType(); 2005 if (ElTy->isFloatingPoint()) { 2006 unsigned VL = DestTy->getNumElements(); 2007 std::vector<Constant*> NZ(VL, ConstantFP::get(ElTy, 2008 ElTy==Type::FloatTy ? APFloat(-0.0f) : APFloat(-0.0))); 2009 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2010 if (CV == CNZ) { 2011 SDOperand Op2 = getValue(I.getOperand(1)); 2012 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2013 return; 2014 } 2015 } 2016 } 2017 } 2018 if (Ty->isFloatingPoint()) { 2019 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2020 if (CFP->isExactlyValue(-0.0)) { 2021 SDOperand Op2 = getValue(I.getOperand(1)); 2022 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2023 return; 2024 } 2025 } 2026 2027 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2028} 2029 2030void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2031 SDOperand Op1 = getValue(I.getOperand(0)); 2032 SDOperand Op2 = getValue(I.getOperand(1)); 2033 2034 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2035} 2036 2037void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2038 SDOperand Op1 = getValue(I.getOperand(0)); 2039 SDOperand Op2 = getValue(I.getOperand(1)); 2040 2041 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) < 2042 MVT::getSizeInBits(Op2.getValueType())) 2043 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2044 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 2045 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2046 2047 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2048} 2049 2050void SelectionDAGLowering::visitICmp(User &I) { 2051 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2052 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2053 predicate = IC->getPredicate(); 2054 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2055 predicate = ICmpInst::Predicate(IC->getPredicate()); 2056 SDOperand Op1 = getValue(I.getOperand(0)); 2057 SDOperand Op2 = getValue(I.getOperand(1)); 2058 ISD::CondCode Opcode; 2059 switch (predicate) { 2060 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2061 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2062 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2063 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2064 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2065 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2066 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2067 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2068 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2069 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2070 default: 2071 assert(!"Invalid ICmp predicate value"); 2072 Opcode = ISD::SETEQ; 2073 break; 2074 } 2075 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2076} 2077 2078void SelectionDAGLowering::visitFCmp(User &I) { 2079 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2080 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2081 predicate = FC->getPredicate(); 2082 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2083 predicate = FCmpInst::Predicate(FC->getPredicate()); 2084 SDOperand Op1 = getValue(I.getOperand(0)); 2085 SDOperand Op2 = getValue(I.getOperand(1)); 2086 ISD::CondCode Condition, FOC, FPC; 2087 switch (predicate) { 2088 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2089 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2090 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2091 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2092 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2093 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2094 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2095 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 2096 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 2097 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2098 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2099 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2100 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2101 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2102 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2103 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2104 default: 2105 assert(!"Invalid FCmp predicate value"); 2106 FOC = FPC = ISD::SETFALSE; 2107 break; 2108 } 2109 if (FiniteOnlyFPMath()) 2110 Condition = FOC; 2111 else 2112 Condition = FPC; 2113 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2114} 2115 2116void SelectionDAGLowering::visitSelect(User &I) { 2117 SDOperand Cond = getValue(I.getOperand(0)); 2118 SDOperand TrueVal = getValue(I.getOperand(1)); 2119 SDOperand FalseVal = getValue(I.getOperand(2)); 2120 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2121 TrueVal, FalseVal)); 2122} 2123 2124 2125void SelectionDAGLowering::visitTrunc(User &I) { 2126 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2127 SDOperand N = getValue(I.getOperand(0)); 2128 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2129 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2130} 2131 2132void SelectionDAGLowering::visitZExt(User &I) { 2133 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2134 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2135 SDOperand N = getValue(I.getOperand(0)); 2136 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2137 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2138} 2139 2140void SelectionDAGLowering::visitSExt(User &I) { 2141 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2142 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2143 SDOperand N = getValue(I.getOperand(0)); 2144 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2145 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2146} 2147 2148void SelectionDAGLowering::visitFPTrunc(User &I) { 2149 // FPTrunc is never a no-op cast, no need to check 2150 SDOperand N = getValue(I.getOperand(0)); 2151 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2152 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 2153} 2154 2155void SelectionDAGLowering::visitFPExt(User &I){ 2156 // FPTrunc is never a no-op cast, no need to check 2157 SDOperand N = getValue(I.getOperand(0)); 2158 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2159 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2160} 2161 2162void SelectionDAGLowering::visitFPToUI(User &I) { 2163 // FPToUI is never a no-op cast, no need to check 2164 SDOperand N = getValue(I.getOperand(0)); 2165 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2166 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2167} 2168 2169void SelectionDAGLowering::visitFPToSI(User &I) { 2170 // FPToSI is never a no-op cast, no need to check 2171 SDOperand N = getValue(I.getOperand(0)); 2172 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2173 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2174} 2175 2176void SelectionDAGLowering::visitUIToFP(User &I) { 2177 // UIToFP is never a no-op cast, no need to check 2178 SDOperand N = getValue(I.getOperand(0)); 2179 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2180 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2181} 2182 2183void SelectionDAGLowering::visitSIToFP(User &I){ 2184 // UIToFP is never a no-op cast, no need to check 2185 SDOperand N = getValue(I.getOperand(0)); 2186 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2187 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2188} 2189 2190void SelectionDAGLowering::visitPtrToInt(User &I) { 2191 // What to do depends on the size of the integer and the size of the pointer. 2192 // We can either truncate, zero extend, or no-op, accordingly. 2193 SDOperand N = getValue(I.getOperand(0)); 2194 MVT::ValueType SrcVT = N.getValueType(); 2195 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2196 SDOperand Result; 2197 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2198 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2199 else 2200 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2201 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2202 setValue(&I, Result); 2203} 2204 2205void SelectionDAGLowering::visitIntToPtr(User &I) { 2206 // What to do depends on the size of the integer and the size of the pointer. 2207 // We can either truncate, zero extend, or no-op, accordingly. 2208 SDOperand N = getValue(I.getOperand(0)); 2209 MVT::ValueType SrcVT = N.getValueType(); 2210 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2211 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2212 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2213 else 2214 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2215 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2216} 2217 2218void SelectionDAGLowering::visitBitCast(User &I) { 2219 SDOperand N = getValue(I.getOperand(0)); 2220 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2221 2222 // BitCast assures us that source and destination are the same size so this 2223 // is either a BIT_CONVERT or a no-op. 2224 if (DestVT != N.getValueType()) 2225 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2226 else 2227 setValue(&I, N); // noop cast. 2228} 2229 2230void SelectionDAGLowering::visitInsertElement(User &I) { 2231 SDOperand InVec = getValue(I.getOperand(0)); 2232 SDOperand InVal = getValue(I.getOperand(1)); 2233 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2234 getValue(I.getOperand(2))); 2235 2236 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2237 TLI.getValueType(I.getType()), 2238 InVec, InVal, InIdx)); 2239} 2240 2241void SelectionDAGLowering::visitExtractElement(User &I) { 2242 SDOperand InVec = getValue(I.getOperand(0)); 2243 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2244 getValue(I.getOperand(1))); 2245 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2246 TLI.getValueType(I.getType()), InVec, InIdx)); 2247} 2248 2249void SelectionDAGLowering::visitShuffleVector(User &I) { 2250 SDOperand V1 = getValue(I.getOperand(0)); 2251 SDOperand V2 = getValue(I.getOperand(1)); 2252 SDOperand Mask = getValue(I.getOperand(2)); 2253 2254 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2255 TLI.getValueType(I.getType()), 2256 V1, V2, Mask)); 2257} 2258 2259 2260void SelectionDAGLowering::visitGetElementPtr(User &I) { 2261 SDOperand N = getValue(I.getOperand(0)); 2262 const Type *Ty = I.getOperand(0)->getType(); 2263 2264 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2265 OI != E; ++OI) { 2266 Value *Idx = *OI; 2267 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2268 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2269 if (Field) { 2270 // N = N + Offset 2271 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2272 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2273 getIntPtrConstant(Offset)); 2274 } 2275 Ty = StTy->getElementType(Field); 2276 } else { 2277 Ty = cast<SequentialType>(Ty)->getElementType(); 2278 2279 // If this is a constant subscript, handle it quickly. 2280 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2281 if (CI->getZExtValue() == 0) continue; 2282 uint64_t Offs = 2283 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2284 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 2285 continue; 2286 } 2287 2288 // N = N + Idx * ElementSize; 2289 uint64_t ElementSize = TD->getTypeSize(Ty); 2290 SDOperand IdxN = getValue(Idx); 2291 2292 // If the index is smaller or larger than intptr_t, truncate or extend 2293 // it. 2294 if (IdxN.getValueType() < N.getValueType()) { 2295 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2296 } else if (IdxN.getValueType() > N.getValueType()) 2297 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2298 2299 // If this is a multiply by a power of two, turn it into a shl 2300 // immediately. This is a very common case. 2301 if (isPowerOf2_64(ElementSize)) { 2302 unsigned Amt = Log2_64(ElementSize); 2303 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2304 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2305 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2306 continue; 2307 } 2308 2309 SDOperand Scale = getIntPtrConstant(ElementSize); 2310 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2311 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2312 } 2313 } 2314 setValue(&I, N); 2315} 2316 2317void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2318 // If this is a fixed sized alloca in the entry block of the function, 2319 // allocate it statically on the stack. 2320 if (FuncInfo.StaticAllocaMap.count(&I)) 2321 return; // getValue will auto-populate this. 2322 2323 const Type *Ty = I.getAllocatedType(); 2324 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 2325 unsigned Align = 2326 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2327 I.getAlignment()); 2328 2329 SDOperand AllocSize = getValue(I.getArraySize()); 2330 MVT::ValueType IntPtr = TLI.getPointerTy(); 2331 if (IntPtr < AllocSize.getValueType()) 2332 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2333 else if (IntPtr > AllocSize.getValueType()) 2334 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2335 2336 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2337 getIntPtrConstant(TySize)); 2338 2339 // Handle alignment. If the requested alignment is less than or equal to 2340 // the stack alignment, ignore it. If the size is greater than or equal to 2341 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2342 unsigned StackAlign = 2343 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2344 if (Align <= StackAlign) 2345 Align = 0; 2346 2347 // Round the size of the allocation up to the stack alignment size 2348 // by add SA-1 to the size. 2349 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2350 getIntPtrConstant(StackAlign-1)); 2351 // Mask out the low bits for alignment purposes. 2352 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2353 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2354 2355 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 2356 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2357 MVT::Other); 2358 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2359 setValue(&I, DSA); 2360 DAG.setRoot(DSA.getValue(1)); 2361 2362 // Inform the Frame Information that we have just allocated a variable-sized 2363 // object. 2364 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2365} 2366 2367void SelectionDAGLowering::visitLoad(LoadInst &I) { 2368 SDOperand Ptr = getValue(I.getOperand(0)); 2369 2370 SDOperand Root; 2371 if (I.isVolatile()) 2372 Root = getRoot(); 2373 else { 2374 // Do not serialize non-volatile loads against each other. 2375 Root = DAG.getRoot(); 2376 } 2377 2378 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2379 Root, I.isVolatile(), I.getAlignment())); 2380} 2381 2382SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2383 const Value *SV, SDOperand Root, 2384 bool isVolatile, 2385 unsigned Alignment) { 2386 SDOperand L = 2387 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2388 isVolatile, Alignment); 2389 2390 if (isVolatile) 2391 DAG.setRoot(L.getValue(1)); 2392 else 2393 PendingLoads.push_back(L.getValue(1)); 2394 2395 return L; 2396} 2397 2398 2399void SelectionDAGLowering::visitStore(StoreInst &I) { 2400 Value *SrcV = I.getOperand(0); 2401 SDOperand Src = getValue(SrcV); 2402 SDOperand Ptr = getValue(I.getOperand(1)); 2403 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2404 I.isVolatile(), I.getAlignment())); 2405} 2406 2407/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot 2408/// access memory and has no other side effects at all. 2409static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) { 2410#define GET_NO_MEMORY_INTRINSICS 2411#include "llvm/Intrinsics.gen" 2412#undef GET_NO_MEMORY_INTRINSICS 2413 return false; 2414} 2415 2416// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't 2417// have any side-effects or if it only reads memory. 2418static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) { 2419#define GET_SIDE_EFFECT_INFO 2420#include "llvm/Intrinsics.gen" 2421#undef GET_SIDE_EFFECT_INFO 2422 return false; 2423} 2424 2425/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2426/// node. 2427void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2428 unsigned Intrinsic) { 2429 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic); 2430 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic); 2431 2432 // Build the operand list. 2433 SmallVector<SDOperand, 8> Ops; 2434 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2435 if (OnlyLoad) { 2436 // We don't need to serialize loads against other loads. 2437 Ops.push_back(DAG.getRoot()); 2438 } else { 2439 Ops.push_back(getRoot()); 2440 } 2441 } 2442 2443 // Add the intrinsic ID as an integer operand. 2444 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2445 2446 // Add all operands of the call to the operand list. 2447 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2448 SDOperand Op = getValue(I.getOperand(i)); 2449 assert(TLI.isTypeLegal(Op.getValueType()) && 2450 "Intrinsic uses a non-legal type?"); 2451 Ops.push_back(Op); 2452 } 2453 2454 std::vector<MVT::ValueType> VTs; 2455 if (I.getType() != Type::VoidTy) { 2456 MVT::ValueType VT = TLI.getValueType(I.getType()); 2457 if (MVT::isVector(VT)) { 2458 const VectorType *DestTy = cast<VectorType>(I.getType()); 2459 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2460 2461 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2462 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2463 } 2464 2465 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2466 VTs.push_back(VT); 2467 } 2468 if (HasChain) 2469 VTs.push_back(MVT::Other); 2470 2471 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2472 2473 // Create the node. 2474 SDOperand Result; 2475 if (!HasChain) 2476 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2477 &Ops[0], Ops.size()); 2478 else if (I.getType() != Type::VoidTy) 2479 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2480 &Ops[0], Ops.size()); 2481 else 2482 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2483 &Ops[0], Ops.size()); 2484 2485 if (HasChain) { 2486 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2487 if (OnlyLoad) 2488 PendingLoads.push_back(Chain); 2489 else 2490 DAG.setRoot(Chain); 2491 } 2492 if (I.getType() != Type::VoidTy) { 2493 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2494 MVT::ValueType VT = TLI.getValueType(PTy); 2495 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 2496 } 2497 setValue(&I, Result); 2498 } 2499} 2500 2501/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 2502static GlobalVariable *ExtractTypeInfo (Value *V) { 2503 V = IntrinsicInst::StripPointerCasts(V); 2504 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 2505 assert (GV || isa<ConstantPointerNull>(V) && 2506 "TypeInfo must be a global variable or NULL"); 2507 return GV; 2508} 2509 2510/// addCatchInfo - Extract the personality and type infos from an eh.selector 2511/// call, and add them to the specified machine basic block. 2512static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 2513 MachineBasicBlock *MBB) { 2514 // Inform the MachineModuleInfo of the personality for this landing pad. 2515 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 2516 assert(CE->getOpcode() == Instruction::BitCast && 2517 isa<Function>(CE->getOperand(0)) && 2518 "Personality should be a function"); 2519 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 2520 2521 // Gather all the type infos for this landing pad and pass them along to 2522 // MachineModuleInfo. 2523 std::vector<GlobalVariable *> TyInfo; 2524 unsigned N = I.getNumOperands(); 2525 2526 for (unsigned i = N - 1; i > 2; --i) { 2527 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 2528 unsigned FilterLength = CI->getZExtValue(); 2529 unsigned FirstCatch = i + FilterLength + !FilterLength; 2530 assert (FirstCatch <= N && "Invalid filter length"); 2531 2532 if (FirstCatch < N) { 2533 TyInfo.reserve(N - FirstCatch); 2534 for (unsigned j = FirstCatch; j < N; ++j) 2535 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2536 MMI->addCatchTypeInfo(MBB, TyInfo); 2537 TyInfo.clear(); 2538 } 2539 2540 if (!FilterLength) { 2541 // Cleanup. 2542 MMI->addCleanup(MBB); 2543 } else { 2544 // Filter. 2545 TyInfo.reserve(FilterLength - 1); 2546 for (unsigned j = i + 1; j < FirstCatch; ++j) 2547 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2548 MMI->addFilterTypeInfo(MBB, TyInfo); 2549 TyInfo.clear(); 2550 } 2551 2552 N = i; 2553 } 2554 } 2555 2556 if (N > 3) { 2557 TyInfo.reserve(N - 3); 2558 for (unsigned j = 3; j < N; ++j) 2559 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2560 MMI->addCatchTypeInfo(MBB, TyInfo); 2561 } 2562} 2563 2564/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2565/// we want to emit this as a call to a named external function, return the name 2566/// otherwise lower it and return null. 2567const char * 2568SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2569 switch (Intrinsic) { 2570 default: 2571 // By default, turn this into a target intrinsic node. 2572 visitTargetIntrinsic(I, Intrinsic); 2573 return 0; 2574 case Intrinsic::vastart: visitVAStart(I); return 0; 2575 case Intrinsic::vaend: visitVAEnd(I); return 0; 2576 case Intrinsic::vacopy: visitVACopy(I); return 0; 2577 case Intrinsic::returnaddress: 2578 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2579 getValue(I.getOperand(1)))); 2580 return 0; 2581 case Intrinsic::frameaddress: 2582 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2583 getValue(I.getOperand(1)))); 2584 return 0; 2585 case Intrinsic::setjmp: 2586 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2587 break; 2588 case Intrinsic::longjmp: 2589 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2590 break; 2591 case Intrinsic::memcpy_i32: 2592 case Intrinsic::memcpy_i64: 2593 visitMemIntrinsic(I, ISD::MEMCPY); 2594 return 0; 2595 case Intrinsic::memset_i32: 2596 case Intrinsic::memset_i64: 2597 visitMemIntrinsic(I, ISD::MEMSET); 2598 return 0; 2599 case Intrinsic::memmove_i32: 2600 case Intrinsic::memmove_i64: 2601 visitMemIntrinsic(I, ISD::MEMMOVE); 2602 return 0; 2603 2604 case Intrinsic::dbg_stoppoint: { 2605 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2606 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2607 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2608 SDOperand Ops[5]; 2609 2610 Ops[0] = getRoot(); 2611 Ops[1] = getValue(SPI.getLineValue()); 2612 Ops[2] = getValue(SPI.getColumnValue()); 2613 2614 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2615 assert(DD && "Not a debug information descriptor"); 2616 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2617 2618 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2619 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2620 2621 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2622 } 2623 2624 return 0; 2625 } 2626 case Intrinsic::dbg_region_start: { 2627 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2628 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2629 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2630 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2631 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2632 DAG.getConstant(LabelID, MVT::i32))); 2633 } 2634 2635 return 0; 2636 } 2637 case Intrinsic::dbg_region_end: { 2638 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2639 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2640 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2641 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2642 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2643 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2644 } 2645 2646 return 0; 2647 } 2648 case Intrinsic::dbg_func_start: { 2649 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2650 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2651 if (MMI && FSI.getSubprogram() && 2652 MMI->Verify(FSI.getSubprogram())) { 2653 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram()); 2654 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2655 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2656 } 2657 2658 return 0; 2659 } 2660 case Intrinsic::dbg_declare: { 2661 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2662 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2663 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) { 2664 SDOperand AddressOp = getValue(DI.getAddress()); 2665 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 2666 MMI->RecordVariable(DI.getVariable(), FI->getIndex()); 2667 } 2668 2669 return 0; 2670 } 2671 2672 case Intrinsic::eh_exception: { 2673 if (ExceptionHandling) { 2674 if (!CurMBB->isLandingPad()) { 2675 // FIXME: Mark exception register as live in. Hack for PR1508. 2676 unsigned Reg = TLI.getExceptionAddressRegister(); 2677 if (Reg) CurMBB->addLiveIn(Reg); 2678 } 2679 // Insert the EXCEPTIONADDR instruction. 2680 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2681 SDOperand Ops[1]; 2682 Ops[0] = DAG.getRoot(); 2683 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2684 setValue(&I, Op); 2685 DAG.setRoot(Op.getValue(1)); 2686 } else { 2687 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2688 } 2689 return 0; 2690 } 2691 2692 case Intrinsic::eh_selector_i32: 2693 case Intrinsic::eh_selector_i64: { 2694 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2695 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ? 2696 MVT::i32 : MVT::i64); 2697 2698 if (ExceptionHandling && MMI) { 2699 if (CurMBB->isLandingPad()) 2700 addCatchInfo(I, MMI, CurMBB); 2701 else { 2702#ifndef NDEBUG 2703 FuncInfo.CatchInfoLost.insert(&I); 2704#endif 2705 // FIXME: Mark exception selector register as live in. Hack for PR1508. 2706 unsigned Reg = TLI.getExceptionSelectorRegister(); 2707 if (Reg) CurMBB->addLiveIn(Reg); 2708 } 2709 2710 // Insert the EHSELECTION instruction. 2711 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 2712 SDOperand Ops[2]; 2713 Ops[0] = getValue(I.getOperand(1)); 2714 Ops[1] = getRoot(); 2715 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2716 setValue(&I, Op); 2717 DAG.setRoot(Op.getValue(1)); 2718 } else { 2719 setValue(&I, DAG.getConstant(0, VT)); 2720 } 2721 2722 return 0; 2723 } 2724 2725 case Intrinsic::eh_typeid_for_i32: 2726 case Intrinsic::eh_typeid_for_i64: { 2727 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2728 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? 2729 MVT::i32 : MVT::i64); 2730 2731 if (MMI) { 2732 // Find the type id for the given typeinfo. 2733 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 2734 2735 unsigned TypeID = MMI->getTypeIDFor(GV); 2736 setValue(&I, DAG.getConstant(TypeID, VT)); 2737 } else { 2738 // Return something different to eh_selector. 2739 setValue(&I, DAG.getConstant(1, VT)); 2740 } 2741 2742 return 0; 2743 } 2744 2745 case Intrinsic::eh_return: { 2746 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2747 2748 if (MMI && ExceptionHandling) { 2749 MMI->setCallsEHReturn(true); 2750 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, 2751 MVT::Other, 2752 getRoot(), 2753 getValue(I.getOperand(1)), 2754 getValue(I.getOperand(2)))); 2755 } else { 2756 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2757 } 2758 2759 return 0; 2760 } 2761 2762 case Intrinsic::eh_unwind_init: { 2763 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 2764 MMI->setCallsUnwindInit(true); 2765 } 2766 2767 return 0; 2768 } 2769 2770 case Intrinsic::eh_dwarf_cfa: { 2771 if (ExceptionHandling) { 2772 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType(); 2773 SDOperand CfaArg; 2774 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 2775 CfaArg = DAG.getNode(ISD::TRUNCATE, 2776 TLI.getPointerTy(), getValue(I.getOperand(1))); 2777 else 2778 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, 2779 TLI.getPointerTy(), getValue(I.getOperand(1))); 2780 2781 SDOperand Offset = DAG.getNode(ISD::ADD, 2782 TLI.getPointerTy(), 2783 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, 2784 TLI.getPointerTy()), 2785 CfaArg); 2786 setValue(&I, DAG.getNode(ISD::ADD, 2787 TLI.getPointerTy(), 2788 DAG.getNode(ISD::FRAMEADDR, 2789 TLI.getPointerTy(), 2790 DAG.getConstant(0, 2791 TLI.getPointerTy())), 2792 Offset)); 2793 } else { 2794 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2795 } 2796 2797 return 0; 2798 } 2799 2800 case Intrinsic::sqrt_f32: 2801 case Intrinsic::sqrt_f64: 2802 setValue(&I, DAG.getNode(ISD::FSQRT, 2803 getValue(I.getOperand(1)).getValueType(), 2804 getValue(I.getOperand(1)))); 2805 return 0; 2806 case Intrinsic::powi_f32: 2807 case Intrinsic::powi_f64: 2808 setValue(&I, DAG.getNode(ISD::FPOWI, 2809 getValue(I.getOperand(1)).getValueType(), 2810 getValue(I.getOperand(1)), 2811 getValue(I.getOperand(2)))); 2812 return 0; 2813 case Intrinsic::pcmarker: { 2814 SDOperand Tmp = getValue(I.getOperand(1)); 2815 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2816 return 0; 2817 } 2818 case Intrinsic::readcyclecounter: { 2819 SDOperand Op = getRoot(); 2820 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2821 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2822 &Op, 1); 2823 setValue(&I, Tmp); 2824 DAG.setRoot(Tmp.getValue(1)); 2825 return 0; 2826 } 2827 case Intrinsic::part_select: { 2828 // Currently not implemented: just abort 2829 assert(0 && "part_select intrinsic not implemented"); 2830 abort(); 2831 } 2832 case Intrinsic::part_set: { 2833 // Currently not implemented: just abort 2834 assert(0 && "part_set intrinsic not implemented"); 2835 abort(); 2836 } 2837 case Intrinsic::bswap: 2838 setValue(&I, DAG.getNode(ISD::BSWAP, 2839 getValue(I.getOperand(1)).getValueType(), 2840 getValue(I.getOperand(1)))); 2841 return 0; 2842 case Intrinsic::cttz: { 2843 SDOperand Arg = getValue(I.getOperand(1)); 2844 MVT::ValueType Ty = Arg.getValueType(); 2845 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2846 setValue(&I, result); 2847 return 0; 2848 } 2849 case Intrinsic::ctlz: { 2850 SDOperand Arg = getValue(I.getOperand(1)); 2851 MVT::ValueType Ty = Arg.getValueType(); 2852 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2853 setValue(&I, result); 2854 return 0; 2855 } 2856 case Intrinsic::ctpop: { 2857 SDOperand Arg = getValue(I.getOperand(1)); 2858 MVT::ValueType Ty = Arg.getValueType(); 2859 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2860 setValue(&I, result); 2861 return 0; 2862 } 2863 case Intrinsic::stacksave: { 2864 SDOperand Op = getRoot(); 2865 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2866 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2867 setValue(&I, Tmp); 2868 DAG.setRoot(Tmp.getValue(1)); 2869 return 0; 2870 } 2871 case Intrinsic::stackrestore: { 2872 SDOperand Tmp = getValue(I.getOperand(1)); 2873 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2874 return 0; 2875 } 2876 case Intrinsic::prefetch: 2877 // FIXME: Currently discarding prefetches. 2878 return 0; 2879 2880 case Intrinsic::var_annotation: 2881 // Discard annotate attributes 2882 return 0; 2883 2884 case Intrinsic::adjust_trampoline: { 2885 SDOperand Arg = getValue(I.getOperand(1)); 2886 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMP, TLI.getPointerTy(), Arg)); 2887 return 0; 2888 } 2889 2890 case Intrinsic::init_trampoline: { 2891 const Function *F = 2892 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2))); 2893 2894 SDOperand Ops[6]; 2895 Ops[0] = getRoot(); 2896 Ops[1] = getValue(I.getOperand(1)); 2897 Ops[2] = getValue(I.getOperand(2)); 2898 Ops[3] = getValue(I.getOperand(3)); 2899 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 2900 Ops[5] = DAG.getSrcValue(F); 2901 2902 DAG.setRoot(DAG.getNode(ISD::TRAMPOLINE, MVT::Other, Ops, 6)); 2903 return 0; 2904 } 2905 } 2906} 2907 2908 2909void SelectionDAGLowering::LowerCallTo(Instruction &I, 2910 const Type *CalledValueTy, 2911 unsigned CallingConv, 2912 bool IsTailCall, 2913 SDOperand Callee, unsigned OpIdx, 2914 MachineBasicBlock *LandingPad) { 2915 const PointerType *PT = cast<PointerType>(CalledValueTy); 2916 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 2917 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 2918 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2919 unsigned BeginLabel = 0, EndLabel = 0; 2920 2921 TargetLowering::ArgListTy Args; 2922 TargetLowering::ArgListEntry Entry; 2923 Args.reserve(I.getNumOperands()); 2924 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) { 2925 Value *Arg = I.getOperand(i); 2926 SDOperand ArgNode = getValue(Arg); 2927 Entry.Node = ArgNode; Entry.Ty = Arg->getType(); 2928 2929 unsigned attrInd = i - OpIdx + 1; 2930 Entry.isSExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::SExt); 2931 Entry.isZExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ZExt); 2932 Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg); 2933 Entry.isSRet = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet); 2934 Entry.isNest = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::Nest); 2935 Entry.isByVal = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ByVal); 2936 Args.push_back(Entry); 2937 } 2938 2939 if (ExceptionHandling && MMI && LandingPad) { 2940 // Insert a label before the invoke call to mark the try range. This can be 2941 // used to detect deletion of the invoke via the MachineModuleInfo. 2942 BeginLabel = MMI->NextLabelID(); 2943 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2944 DAG.getConstant(BeginLabel, MVT::i32))); 2945 } 2946 2947 std::pair<SDOperand,SDOperand> Result = 2948 TLI.LowerCallTo(getRoot(), I.getType(), 2949 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt), 2950 FTy->isVarArg(), CallingConv, IsTailCall, 2951 Callee, Args, DAG); 2952 if (I.getType() != Type::VoidTy) 2953 setValue(&I, Result.first); 2954 DAG.setRoot(Result.second); 2955 2956 if (ExceptionHandling && MMI && LandingPad) { 2957 // Insert a label at the end of the invoke call to mark the try range. This 2958 // can be used to detect deletion of the invoke via the MachineModuleInfo. 2959 EndLabel = MMI->NextLabelID(); 2960 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2961 DAG.getConstant(EndLabel, MVT::i32))); 2962 2963 // Inform MachineModuleInfo of range. 2964 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 2965 } 2966} 2967 2968 2969void SelectionDAGLowering::visitCall(CallInst &I) { 2970 const char *RenameFn = 0; 2971 if (Function *F = I.getCalledFunction()) { 2972 if (F->isDeclaration()) { 2973 if (unsigned IID = F->getIntrinsicID()) { 2974 RenameFn = visitIntrinsicCall(I, IID); 2975 if (!RenameFn) 2976 return; 2977 } 2978 } 2979 2980 // Check for well-known libc/libm calls. If the function is internal, it 2981 // can't be a library call. 2982 unsigned NameLen = F->getNameLen(); 2983 if (!F->hasInternalLinkage() && NameLen) { 2984 const char *NameStr = F->getNameStart(); 2985 if (NameStr[0] == 'c' && 2986 ((NameLen == 8 && !strcmp(NameStr, "copysign")) || 2987 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) { 2988 if (I.getNumOperands() == 3 && // Basic sanity checks. 2989 I.getOperand(1)->getType()->isFloatingPoint() && 2990 I.getType() == I.getOperand(1)->getType() && 2991 I.getType() == I.getOperand(2)->getType()) { 2992 SDOperand LHS = getValue(I.getOperand(1)); 2993 SDOperand RHS = getValue(I.getOperand(2)); 2994 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 2995 LHS, RHS)); 2996 return; 2997 } 2998 } else if (NameStr[0] == 'f' && 2999 ((NameLen == 4 && !strcmp(NameStr, "fabs")) || 3000 (NameLen == 5 && !strcmp(NameStr, "fabsf")))) { 3001 if (I.getNumOperands() == 2 && // Basic sanity checks. 3002 I.getOperand(1)->getType()->isFloatingPoint() && 3003 I.getType() == I.getOperand(1)->getType()) { 3004 SDOperand Tmp = getValue(I.getOperand(1)); 3005 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 3006 return; 3007 } 3008 } else if (NameStr[0] == 's' && 3009 ((NameLen == 3 && !strcmp(NameStr, "sin")) || 3010 (NameLen == 4 && !strcmp(NameStr, "sinf")))) { 3011 if (I.getNumOperands() == 2 && // Basic sanity checks. 3012 I.getOperand(1)->getType()->isFloatingPoint() && 3013 I.getType() == I.getOperand(1)->getType()) { 3014 SDOperand Tmp = getValue(I.getOperand(1)); 3015 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 3016 return; 3017 } 3018 } else if (NameStr[0] == 'c' && 3019 ((NameLen == 3 && !strcmp(NameStr, "cos")) || 3020 (NameLen == 4 && !strcmp(NameStr, "cosf")))) { 3021 if (I.getNumOperands() == 2 && // Basic sanity checks. 3022 I.getOperand(1)->getType()->isFloatingPoint() && 3023 I.getType() == I.getOperand(1)->getType()) { 3024 SDOperand Tmp = getValue(I.getOperand(1)); 3025 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 3026 return; 3027 } 3028 } 3029 } 3030 } else if (isa<InlineAsm>(I.getOperand(0))) { 3031 visitInlineAsm(I); 3032 return; 3033 } 3034 3035 SDOperand Callee; 3036 if (!RenameFn) 3037 Callee = getValue(I.getOperand(0)); 3038 else 3039 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 3040 3041 LowerCallTo(I, I.getCalledValue()->getType(), 3042 I.getCallingConv(), 3043 I.isTailCall(), 3044 Callee, 3045 1); 3046} 3047 3048 3049/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 3050/// this value and returns the result as a ValueVT value. This uses 3051/// Chain/Flag as the input and updates them for the output Chain/Flag. 3052/// If the Flag pointer is NULL, no flag is used. 3053SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 3054 SDOperand &Chain, SDOperand *Flag)const{ 3055 // Copy the legal parts from the registers. 3056 unsigned NumParts = Regs.size(); 3057 SmallVector<SDOperand, 8> Parts(NumParts); 3058 for (unsigned i = 0; i != NumParts; ++i) { 3059 SDOperand Part = Flag ? 3060 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) : 3061 DAG.getCopyFromReg(Chain, Regs[i], RegVT); 3062 Chain = Part.getValue(1); 3063 if (Flag) 3064 *Flag = Part.getValue(2); 3065 Parts[i] = Part; 3066 } 3067 3068 // Assemble the legal parts into the final value. 3069 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT); 3070} 3071 3072/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 3073/// specified value into the registers specified by this object. This uses 3074/// Chain/Flag as the input and updates them for the output Chain/Flag. 3075/// If the Flag pointer is NULL, no flag is used. 3076void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 3077 SDOperand &Chain, SDOperand *Flag) const { 3078 // Get the list of the values's legal parts. 3079 unsigned NumParts = Regs.size(); 3080 SmallVector<SDOperand, 8> Parts(NumParts); 3081 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT); 3082 3083 // Copy the parts into the registers. 3084 for (unsigned i = 0; i != NumParts; ++i) { 3085 SDOperand Part = Flag ? 3086 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) : 3087 DAG.getCopyToReg(Chain, Regs[i], Parts[i]); 3088 Chain = Part.getValue(0); 3089 if (Flag) 3090 *Flag = Part.getValue(1); 3091 } 3092} 3093 3094/// AddInlineAsmOperands - Add this value to the specified inlineasm node 3095/// operand list. This adds the code marker and includes the number of 3096/// values added into it. 3097void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 3098 std::vector<SDOperand> &Ops) const { 3099 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3100 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3101 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 3102 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 3103} 3104 3105/// isAllocatableRegister - If the specified register is safe to allocate, 3106/// i.e. it isn't a stack pointer or some other special register, return the 3107/// register class for the register. Otherwise, return null. 3108static const TargetRegisterClass * 3109isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3110 const TargetLowering &TLI, const MRegisterInfo *MRI) { 3111 MVT::ValueType FoundVT = MVT::Other; 3112 const TargetRegisterClass *FoundRC = 0; 3113 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 3114 E = MRI->regclass_end(); RCI != E; ++RCI) { 3115 MVT::ValueType ThisVT = MVT::Other; 3116 3117 const TargetRegisterClass *RC = *RCI; 3118 // If none of the the value types for this register class are valid, we 3119 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3120 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3121 I != E; ++I) { 3122 if (TLI.isTypeLegal(*I)) { 3123 // If we have already found this register in a different register class, 3124 // choose the one with the largest VT specified. For example, on 3125 // PowerPC, we favor f64 register classes over f32. 3126 if (FoundVT == MVT::Other || 3127 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 3128 ThisVT = *I; 3129 break; 3130 } 3131 } 3132 } 3133 3134 if (ThisVT == MVT::Other) continue; 3135 3136 // NOTE: This isn't ideal. In particular, this might allocate the 3137 // frame pointer in functions that need it (due to them not being taken 3138 // out of allocation, because a variable sized allocation hasn't been seen 3139 // yet). This is a slight code pessimization, but should still work. 3140 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3141 E = RC->allocation_order_end(MF); I != E; ++I) 3142 if (*I == Reg) { 3143 // We found a matching register class. Keep looking at others in case 3144 // we find one with larger registers that this physreg is also in. 3145 FoundRC = RC; 3146 FoundVT = ThisVT; 3147 break; 3148 } 3149 } 3150 return FoundRC; 3151} 3152 3153 3154namespace { 3155/// AsmOperandInfo - This contains information for each constraint that we are 3156/// lowering. 3157struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 3158 /// ConstraintCode - This contains the actual string for the code, like "m". 3159 std::string ConstraintCode; 3160 3161 /// ConstraintType - Information about the constraint code, e.g. Register, 3162 /// RegisterClass, Memory, Other, Unknown. 3163 TargetLowering::ConstraintType ConstraintType; 3164 3165 /// CallOperand/CallOperandval - If this is the result output operand or a 3166 /// clobber, this is null, otherwise it is the incoming operand to the 3167 /// CallInst. This gets modified as the asm is processed. 3168 SDOperand CallOperand; 3169 Value *CallOperandVal; 3170 3171 /// ConstraintVT - The ValueType for the operand value. 3172 MVT::ValueType ConstraintVT; 3173 3174 /// AssignedRegs - If this is a register or register class operand, this 3175 /// contains the set of register corresponding to the operand. 3176 RegsForValue AssignedRegs; 3177 3178 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3179 : InlineAsm::ConstraintInfo(info), 3180 ConstraintType(TargetLowering::C_Unknown), 3181 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) { 3182 } 3183 3184 void ComputeConstraintToUse(const TargetLowering &TLI); 3185 3186 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3187 /// busy in OutputRegs/InputRegs. 3188 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3189 std::set<unsigned> &OutputRegs, 3190 std::set<unsigned> &InputRegs) const { 3191 if (isOutReg) 3192 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3193 if (isInReg) 3194 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3195 } 3196}; 3197} // end anon namespace. 3198 3199/// getConstraintGenerality - Return an integer indicating how general CT is. 3200static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3201 switch (CT) { 3202 default: assert(0 && "Unknown constraint type!"); 3203 case TargetLowering::C_Other: 3204 case TargetLowering::C_Unknown: 3205 return 0; 3206 case TargetLowering::C_Register: 3207 return 1; 3208 case TargetLowering::C_RegisterClass: 3209 return 2; 3210 case TargetLowering::C_Memory: 3211 return 3; 3212 } 3213} 3214 3215void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) { 3216 assert(!Codes.empty() && "Must have at least one constraint"); 3217 3218 std::string *Current = &Codes[0]; 3219 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current); 3220 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common. 3221 ConstraintCode = *Current; 3222 ConstraintType = CurType; 3223 return; 3224 } 3225 3226 unsigned CurGenerality = getConstraintGenerality(CurType); 3227 3228 // If we have multiple constraints, try to pick the most general one ahead 3229 // of time. This isn't a wonderful solution, but handles common cases. 3230 for (unsigned j = 1, e = Codes.size(); j != e; ++j) { 3231 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]); 3232 unsigned ThisGenerality = getConstraintGenerality(ThisType); 3233 if (ThisGenerality > CurGenerality) { 3234 // This constraint letter is more general than the previous one, 3235 // use it. 3236 CurType = ThisType; 3237 Current = &Codes[j]; 3238 CurGenerality = ThisGenerality; 3239 } 3240 } 3241 3242 ConstraintCode = *Current; 3243 ConstraintType = CurType; 3244} 3245 3246 3247void SelectionDAGLowering:: 3248GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 3249 std::set<unsigned> &OutputRegs, 3250 std::set<unsigned> &InputRegs) { 3251 // Compute whether this value requires an input register, an output register, 3252 // or both. 3253 bool isOutReg = false; 3254 bool isInReg = false; 3255 switch (OpInfo.Type) { 3256 case InlineAsm::isOutput: 3257 isOutReg = true; 3258 3259 // If this is an early-clobber output, or if there is an input 3260 // constraint that matches this, we need to reserve the input register 3261 // so no other inputs allocate to it. 3262 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3263 break; 3264 case InlineAsm::isInput: 3265 isInReg = true; 3266 isOutReg = false; 3267 break; 3268 case InlineAsm::isClobber: 3269 isOutReg = true; 3270 isInReg = true; 3271 break; 3272 } 3273 3274 3275 MachineFunction &MF = DAG.getMachineFunction(); 3276 std::vector<unsigned> Regs; 3277 3278 // If this is a constraint for a single physreg, or a constraint for a 3279 // register class, find it. 3280 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3281 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3282 OpInfo.ConstraintVT); 3283 3284 unsigned NumRegs = 1; 3285 if (OpInfo.ConstraintVT != MVT::Other) 3286 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3287 MVT::ValueType RegVT; 3288 MVT::ValueType ValueVT = OpInfo.ConstraintVT; 3289 3290 3291 // If this is a constraint for a specific physical register, like {r17}, 3292 // assign it now. 3293 if (PhysReg.first) { 3294 if (OpInfo.ConstraintVT == MVT::Other) 3295 ValueVT = *PhysReg.second->vt_begin(); 3296 3297 // Get the actual register value type. This is important, because the user 3298 // may have asked for (e.g.) the AX register in i32 type. We need to 3299 // remember that AX is actually i16 to get the right extension. 3300 RegVT = *PhysReg.second->vt_begin(); 3301 3302 // This is a explicit reference to a physical register. 3303 Regs.push_back(PhysReg.first); 3304 3305 // If this is an expanded reference, add the rest of the regs to Regs. 3306 if (NumRegs != 1) { 3307 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3308 TargetRegisterClass::iterator E = PhysReg.second->end(); 3309 for (; *I != PhysReg.first; ++I) 3310 assert(I != E && "Didn't find reg!"); 3311 3312 // Already added the first reg. 3313 --NumRegs; ++I; 3314 for (; NumRegs; --NumRegs, ++I) { 3315 assert(I != E && "Ran out of registers to allocate!"); 3316 Regs.push_back(*I); 3317 } 3318 } 3319 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3320 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3321 return; 3322 } 3323 3324 // Otherwise, if this was a reference to an LLVM register class, create vregs 3325 // for this reference. 3326 std::vector<unsigned> RegClassRegs; 3327 const TargetRegisterClass *RC = PhysReg.second; 3328 if (RC) { 3329 // If this is an early clobber or tied register, our regalloc doesn't know 3330 // how to maintain the constraint. If it isn't, go ahead and create vreg 3331 // and let the regalloc do the right thing. 3332 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 3333 // If there is some other early clobber and this is an input register, 3334 // then we are forced to pre-allocate the input reg so it doesn't 3335 // conflict with the earlyclobber. 3336 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 3337 RegVT = *PhysReg.second->vt_begin(); 3338 3339 if (OpInfo.ConstraintVT == MVT::Other) 3340 ValueVT = RegVT; 3341 3342 // Create the appropriate number of virtual registers. 3343 SSARegMap *RegMap = MF.getSSARegMap(); 3344 for (; NumRegs; --NumRegs) 3345 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second)); 3346 3347 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3348 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3349 return; 3350 } 3351 3352 // Otherwise, we can't allocate it. Let the code below figure out how to 3353 // maintain these constraints. 3354 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3355 3356 } else { 3357 // This is a reference to a register class that doesn't directly correspond 3358 // to an LLVM register class. Allocate NumRegs consecutive, available, 3359 // registers from the class. 3360 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3361 OpInfo.ConstraintVT); 3362 } 3363 3364 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 3365 unsigned NumAllocated = 0; 3366 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3367 unsigned Reg = RegClassRegs[i]; 3368 // See if this register is available. 3369 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3370 (isInReg && InputRegs.count(Reg))) { // Already used. 3371 // Make sure we find consecutive registers. 3372 NumAllocated = 0; 3373 continue; 3374 } 3375 3376 // Check to see if this register is allocatable (i.e. don't give out the 3377 // stack pointer). 3378 if (RC == 0) { 3379 RC = isAllocatableRegister(Reg, MF, TLI, MRI); 3380 if (!RC) { // Couldn't allocate this register. 3381 // Reset NumAllocated to make sure we return consecutive registers. 3382 NumAllocated = 0; 3383 continue; 3384 } 3385 } 3386 3387 // Okay, this register is good, we can use it. 3388 ++NumAllocated; 3389 3390 // If we allocated enough consecutive registers, succeed. 3391 if (NumAllocated == NumRegs) { 3392 unsigned RegStart = (i-NumAllocated)+1; 3393 unsigned RegEnd = i+1; 3394 // Mark all of the allocated registers used. 3395 for (unsigned i = RegStart; i != RegEnd; ++i) 3396 Regs.push_back(RegClassRegs[i]); 3397 3398 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 3399 OpInfo.ConstraintVT); 3400 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3401 return; 3402 } 3403 } 3404 3405 // Otherwise, we couldn't allocate enough registers for this. 3406 return; 3407} 3408 3409 3410/// visitInlineAsm - Handle a call to an InlineAsm object. 3411/// 3412void SelectionDAGLowering::visitInlineAsm(CallInst &I) { 3413 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0)); 3414 3415 /// ConstraintOperands - Information about all of the constraints. 3416 std::vector<AsmOperandInfo> ConstraintOperands; 3417 3418 SDOperand Chain = getRoot(); 3419 SDOperand Flag; 3420 3421 std::set<unsigned> OutputRegs, InputRegs; 3422 3423 // Do a prepass over the constraints, canonicalizing them, and building up the 3424 // ConstraintOperands list. 3425 std::vector<InlineAsm::ConstraintInfo> 3426 ConstraintInfos = IA->ParseConstraints(); 3427 3428 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 3429 // constraint. If so, we can't let the register allocator allocate any input 3430 // registers, because it will not know to avoid the earlyclobbered output reg. 3431 bool SawEarlyClobber = false; 3432 3433 unsigned OpNo = 1; // OpNo - The operand of the CallInst. 3434 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3435 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 3436 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 3437 3438 MVT::ValueType OpVT = MVT::Other; 3439 3440 // Compute the value type for each operand. 3441 switch (OpInfo.Type) { 3442 case InlineAsm::isOutput: 3443 if (!OpInfo.isIndirect) { 3444 // The return value of the call is this value. As such, there is no 3445 // corresponding argument. 3446 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3447 OpVT = TLI.getValueType(I.getType()); 3448 } else { 3449 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3450 } 3451 break; 3452 case InlineAsm::isInput: 3453 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3454 break; 3455 case InlineAsm::isClobber: 3456 // Nothing to do. 3457 break; 3458 } 3459 3460 // If this is an input or an indirect output, process the call argument. 3461 if (OpInfo.CallOperandVal) { 3462 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 3463 const Type *OpTy = OpInfo.CallOperandVal->getType(); 3464 // If this is an indirect operand, the operand is a pointer to the 3465 // accessed type. 3466 if (OpInfo.isIndirect) 3467 OpTy = cast<PointerType>(OpTy)->getElementType(); 3468 3469 // If OpTy is not a first-class value, it may be a struct/union that we 3470 // can tile with integers. 3471 if (!OpTy->isFirstClassType() && OpTy->isSized()) { 3472 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3473 switch (BitSize) { 3474 default: break; 3475 case 1: 3476 case 8: 3477 case 16: 3478 case 32: 3479 case 64: 3480 OpTy = IntegerType::get(BitSize); 3481 break; 3482 } 3483 } 3484 3485 OpVT = TLI.getValueType(OpTy, true); 3486 } 3487 3488 OpInfo.ConstraintVT = OpVT; 3489 3490 // Compute the constraint code and ConstraintType to use. 3491 OpInfo.ComputeConstraintToUse(TLI); 3492 3493 // Keep track of whether we see an earlyclobber. 3494 SawEarlyClobber |= OpInfo.isEarlyClobber; 3495 3496 // If this is a memory input, and if the operand is not indirect, do what we 3497 // need to to provide an address for the memory input. 3498 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 3499 !OpInfo.isIndirect) { 3500 assert(OpInfo.Type == InlineAsm::isInput && 3501 "Can only indirectify direct input operands!"); 3502 3503 // Memory operands really want the address of the value. If we don't have 3504 // an indirect input, put it in the constpool if we can, otherwise spill 3505 // it to a stack slot. 3506 3507 // If the operand is a float, integer, or vector constant, spill to a 3508 // constant pool entry to get its address. 3509 Value *OpVal = OpInfo.CallOperandVal; 3510 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 3511 isa<ConstantVector>(OpVal)) { 3512 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 3513 TLI.getPointerTy()); 3514 } else { 3515 // Otherwise, create a stack slot and emit a store to it before the 3516 // asm. 3517 const Type *Ty = OpVal->getType(); 3518 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3519 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3520 MachineFunction &MF = DAG.getMachineFunction(); 3521 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3522 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3523 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 3524 OpInfo.CallOperand = StackSlot; 3525 } 3526 3527 // There is no longer a Value* corresponding to this operand. 3528 OpInfo.CallOperandVal = 0; 3529 // It is now an indirect operand. 3530 OpInfo.isIndirect = true; 3531 } 3532 3533 // If this constraint is for a specific register, allocate it before 3534 // anything else. 3535 if (OpInfo.ConstraintType == TargetLowering::C_Register) 3536 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3537 } 3538 ConstraintInfos.clear(); 3539 3540 3541 // Second pass - Loop over all of the operands, assigning virtual or physregs 3542 // to registerclass operands. 3543 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3544 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3545 3546 // C_Register operands have already been allocated, Other/Memory don't need 3547 // to be. 3548 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 3549 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3550 } 3551 3552 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 3553 std::vector<SDOperand> AsmNodeOperands; 3554 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3555 AsmNodeOperands.push_back( 3556 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 3557 3558 3559 // Loop over all of the inputs, copying the operand values into the 3560 // appropriate registers and processing the output regs. 3561 RegsForValue RetValRegs; 3562 3563 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 3564 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3565 3566 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3567 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3568 3569 switch (OpInfo.Type) { 3570 case InlineAsm::isOutput: { 3571 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 3572 OpInfo.ConstraintType != TargetLowering::C_Register) { 3573 // Memory output, or 'other' output (e.g. 'X' constraint). 3574 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 3575 3576 // Add information to the INLINEASM node to know about this output. 3577 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3578 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3579 TLI.getPointerTy())); 3580 AsmNodeOperands.push_back(OpInfo.CallOperand); 3581 break; 3582 } 3583 3584 // Otherwise, this is a register or register class output. 3585 3586 // Copy the output from the appropriate register. Find a register that 3587 // we can use. 3588 if (OpInfo.AssignedRegs.Regs.empty()) { 3589 cerr << "Couldn't allocate output reg for contraint '" 3590 << OpInfo.ConstraintCode << "'!\n"; 3591 exit(1); 3592 } 3593 3594 if (!OpInfo.isIndirect) { 3595 // This is the result value of the call. 3596 assert(RetValRegs.Regs.empty() && 3597 "Cannot have multiple output constraints yet!"); 3598 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3599 RetValRegs = OpInfo.AssignedRegs; 3600 } else { 3601 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 3602 OpInfo.CallOperandVal)); 3603 } 3604 3605 // Add information to the INLINEASM node to know that this register is 3606 // set. 3607 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 3608 AsmNodeOperands); 3609 break; 3610 } 3611 case InlineAsm::isInput: { 3612 SDOperand InOperandVal = OpInfo.CallOperand; 3613 3614 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 3615 // If this is required to match an output register we have already set, 3616 // just use its register. 3617 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 3618 3619 // Scan until we find the definition we already emitted of this operand. 3620 // When we find it, create a RegsForValue operand. 3621 unsigned CurOp = 2; // The first operand. 3622 for (; OperandNo; --OperandNo) { 3623 // Advance to the next operand. 3624 unsigned NumOps = 3625 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3626 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3627 (NumOps & 7) == 4 /*MEM*/) && 3628 "Skipped past definitions?"); 3629 CurOp += (NumOps>>3)+1; 3630 } 3631 3632 unsigned NumOps = 3633 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3634 if ((NumOps & 7) == 2 /*REGDEF*/) { 3635 // Add NumOps>>3 registers to MatchedRegs. 3636 RegsForValue MatchedRegs; 3637 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3638 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3639 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3640 unsigned Reg = 3641 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3642 MatchedRegs.Regs.push_back(Reg); 3643 } 3644 3645 // Use the produced MatchedRegs object to 3646 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3647 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3648 break; 3649 } else { 3650 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3651 assert(0 && "matching constraints for memory operands unimp"); 3652 } 3653 } 3654 3655 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 3656 assert(!OpInfo.isIndirect && 3657 "Don't know how to handle indirect other inputs yet!"); 3658 3659 std::vector<SDOperand> Ops; 3660 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 3661 Ops, DAG); 3662 if (Ops.empty()) { 3663 cerr << "Invalid operand for inline asm constraint '" 3664 << OpInfo.ConstraintCode << "'!\n"; 3665 exit(1); 3666 } 3667 3668 // Add information to the INLINEASM node to know about this input. 3669 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 3670 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3671 TLI.getPointerTy())); 3672 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 3673 break; 3674 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 3675 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 3676 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 3677 "Memory operands expect pointer values"); 3678 3679 // Add information to the INLINEASM node to know about this input. 3680 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3681 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3682 TLI.getPointerTy())); 3683 AsmNodeOperands.push_back(InOperandVal); 3684 break; 3685 } 3686 3687 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 3688 OpInfo.ConstraintType == TargetLowering::C_Register) && 3689 "Unknown constraint type!"); 3690 assert(!OpInfo.isIndirect && 3691 "Don't know how to handle indirect register inputs yet!"); 3692 3693 // Copy the input into the appropriate registers. 3694 assert(!OpInfo.AssignedRegs.Regs.empty() && 3695 "Couldn't allocate input reg!"); 3696 3697 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3698 3699 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 3700 AsmNodeOperands); 3701 break; 3702 } 3703 case InlineAsm::isClobber: { 3704 // Add the clobbered value to the operand list, so that the register 3705 // allocator is aware that the physreg got clobbered. 3706 if (!OpInfo.AssignedRegs.Regs.empty()) 3707 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 3708 AsmNodeOperands); 3709 break; 3710 } 3711 } 3712 } 3713 3714 // Finish up input operands. 3715 AsmNodeOperands[0] = Chain; 3716 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3717 3718 Chain = DAG.getNode(ISD::INLINEASM, 3719 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3720 &AsmNodeOperands[0], AsmNodeOperands.size()); 3721 Flag = Chain.getValue(1); 3722 3723 // If this asm returns a register value, copy the result from that register 3724 // and set it as the value of the call. 3725 if (!RetValRegs.Regs.empty()) { 3726 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 3727 3728 // If the result of the inline asm is a vector, it may have the wrong 3729 // width/num elts. Make sure to convert it to the right type with 3730 // bit_convert. 3731 if (MVT::isVector(Val.getValueType())) { 3732 const VectorType *VTy = cast<VectorType>(I.getType()); 3733 MVT::ValueType DesiredVT = TLI.getValueType(VTy); 3734 3735 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val); 3736 } 3737 3738 setValue(&I, Val); 3739 } 3740 3741 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 3742 3743 // Process indirect outputs, first output all of the flagged copies out of 3744 // physregs. 3745 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 3746 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 3747 Value *Ptr = IndirectStoresToEmit[i].second; 3748 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 3749 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 3750 } 3751 3752 // Emit the non-flagged stores from the physregs. 3753 SmallVector<SDOperand, 8> OutChains; 3754 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 3755 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 3756 getValue(StoresToEmit[i].second), 3757 StoresToEmit[i].second, 0)); 3758 if (!OutChains.empty()) 3759 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3760 &OutChains[0], OutChains.size()); 3761 DAG.setRoot(Chain); 3762} 3763 3764 3765void SelectionDAGLowering::visitMalloc(MallocInst &I) { 3766 SDOperand Src = getValue(I.getOperand(0)); 3767 3768 MVT::ValueType IntPtr = TLI.getPointerTy(); 3769 3770 if (IntPtr < Src.getValueType()) 3771 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 3772 else if (IntPtr > Src.getValueType()) 3773 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 3774 3775 // Scale the source by the type size. 3776 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType()); 3777 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 3778 Src, getIntPtrConstant(ElementSize)); 3779 3780 TargetLowering::ArgListTy Args; 3781 TargetLowering::ArgListEntry Entry; 3782 Entry.Node = Src; 3783 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3784 Args.push_back(Entry); 3785 3786 std::pair<SDOperand,SDOperand> Result = 3787 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true, 3788 DAG.getExternalSymbol("malloc", IntPtr), 3789 Args, DAG); 3790 setValue(&I, Result.first); // Pointers always fit in registers 3791 DAG.setRoot(Result.second); 3792} 3793 3794void SelectionDAGLowering::visitFree(FreeInst &I) { 3795 TargetLowering::ArgListTy Args; 3796 TargetLowering::ArgListEntry Entry; 3797 Entry.Node = getValue(I.getOperand(0)); 3798 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3799 Args.push_back(Entry); 3800 MVT::ValueType IntPtr = TLI.getPointerTy(); 3801 std::pair<SDOperand,SDOperand> Result = 3802 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true, 3803 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 3804 DAG.setRoot(Result.second); 3805} 3806 3807// InsertAtEndOfBasicBlock - This method should be implemented by targets that 3808// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 3809// instructions are special in various ways, which require special support to 3810// insert. The specified MachineInstr is created but not inserted into any 3811// basic blocks, and the scheduler passes ownership of it to this method. 3812MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3813 MachineBasicBlock *MBB) { 3814 cerr << "If a target marks an instruction with " 3815 << "'usesCustomDAGSchedInserter', it must implement " 3816 << "TargetLowering::InsertAtEndOfBasicBlock!\n"; 3817 abort(); 3818 return 0; 3819} 3820 3821void SelectionDAGLowering::visitVAStart(CallInst &I) { 3822 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 3823 getValue(I.getOperand(1)), 3824 DAG.getSrcValue(I.getOperand(1)))); 3825} 3826 3827void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 3828 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 3829 getValue(I.getOperand(0)), 3830 DAG.getSrcValue(I.getOperand(0))); 3831 setValue(&I, V); 3832 DAG.setRoot(V.getValue(1)); 3833} 3834 3835void SelectionDAGLowering::visitVAEnd(CallInst &I) { 3836 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 3837 getValue(I.getOperand(1)), 3838 DAG.getSrcValue(I.getOperand(1)))); 3839} 3840 3841void SelectionDAGLowering::visitVACopy(CallInst &I) { 3842 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 3843 getValue(I.getOperand(1)), 3844 getValue(I.getOperand(2)), 3845 DAG.getSrcValue(I.getOperand(1)), 3846 DAG.getSrcValue(I.getOperand(2)))); 3847} 3848 3849/// TargetLowering::LowerArguments - This is the default LowerArguments 3850/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 3851/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 3852/// integrated into SDISel. 3853std::vector<SDOperand> 3854TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 3855 const FunctionType *FTy = F.getFunctionType(); 3856 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 3857 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 3858 std::vector<SDOperand> Ops; 3859 Ops.push_back(DAG.getRoot()); 3860 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 3861 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 3862 3863 // Add one result value for each formal argument. 3864 std::vector<MVT::ValueType> RetVals; 3865 unsigned j = 1; 3866 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 3867 I != E; ++I, ++j) { 3868 MVT::ValueType VT = getValueType(I->getType()); 3869 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3870 unsigned OriginalAlignment = 3871 getTargetData()->getABITypeAlignment(I->getType()); 3872 3873 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 3874 // that is zero extended! 3875 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt)) 3876 Flags &= ~(ISD::ParamFlags::SExt); 3877 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt)) 3878 Flags |= ISD::ParamFlags::SExt; 3879 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg)) 3880 Flags |= ISD::ParamFlags::InReg; 3881 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet)) 3882 Flags |= ISD::ParamFlags::StructReturn; 3883 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ByVal)) { 3884 Flags |= ISD::ParamFlags::ByVal; 3885 const PointerType *Ty = cast<PointerType>(I->getType()); 3886 const StructType *STy = cast<StructType>(Ty->getElementType()); 3887 unsigned StructAlign = 3888 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy)); 3889 unsigned StructSize = getTargetData()->getTypeSize(STy); 3890 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs); 3891 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs); 3892 } 3893 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::Nest)) 3894 Flags |= ISD::ParamFlags::Nest; 3895 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs); 3896 3897 switch (getTypeAction(VT)) { 3898 default: assert(0 && "Unknown type action!"); 3899 case Legal: 3900 RetVals.push_back(VT); 3901 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3902 break; 3903 case Promote: 3904 RetVals.push_back(getTypeToTransformTo(VT)); 3905 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3906 break; 3907 case Expand: { 3908 // If this is an illegal type, it needs to be broken up to fit into 3909 // registers. 3910 MVT::ValueType RegisterVT = getRegisterType(VT); 3911 unsigned NumRegs = getNumRegisters(VT); 3912 for (unsigned i = 0; i != NumRegs; ++i) { 3913 RetVals.push_back(RegisterVT); 3914 // if it isn't first piece, alignment must be 1 3915 if (i > 0) 3916 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3917 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3918 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3919 } 3920 break; 3921 } 3922 } 3923 } 3924 3925 RetVals.push_back(MVT::Other); 3926 3927 // Create the node. 3928 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 3929 DAG.getNodeValueTypes(RetVals), RetVals.size(), 3930 &Ops[0], Ops.size()).Val; 3931 unsigned NumArgRegs = Result->getNumValues() - 1; 3932 DAG.setRoot(SDOperand(Result, NumArgRegs)); 3933 3934 // Set up the return result vector. 3935 Ops.clear(); 3936 unsigned i = 0; 3937 unsigned Idx = 1; 3938 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 3939 ++I, ++Idx) { 3940 MVT::ValueType VT = getValueType(I->getType()); 3941 3942 switch (getTypeAction(VT)) { 3943 default: assert(0 && "Unknown type action!"); 3944 case Legal: 3945 Ops.push_back(SDOperand(Result, i++)); 3946 break; 3947 case Promote: { 3948 SDOperand Op(Result, i++); 3949 if (MVT::isInteger(VT)) { 3950 if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt)) 3951 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, 3952 DAG.getValueType(VT)); 3953 else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt)) 3954 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, 3955 DAG.getValueType(VT)); 3956 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3957 } else { 3958 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3959 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 3960 } 3961 Ops.push_back(Op); 3962 break; 3963 } 3964 case Expand: { 3965 MVT::ValueType PartVT = getRegisterType(VT); 3966 unsigned NumParts = getNumRegisters(VT); 3967 SmallVector<SDOperand, 4> Parts(NumParts); 3968 for (unsigned j = 0; j != NumParts; ++j) 3969 Parts[j] = SDOperand(Result, i++); 3970 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT)); 3971 break; 3972 } 3973 } 3974 } 3975 assert(i == NumArgRegs && "Argument register count mismatch!"); 3976 return Ops; 3977} 3978 3979 3980/// TargetLowering::LowerCallTo - This is the default LowerCallTo 3981/// implementation, which just inserts an ISD::CALL node, which is later custom 3982/// lowered by the target to something concrete. FIXME: When all targets are 3983/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 3984std::pair<SDOperand, SDOperand> 3985TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 3986 bool RetTyIsSigned, bool isVarArg, 3987 unsigned CallingConv, bool isTailCall, 3988 SDOperand Callee, 3989 ArgListTy &Args, SelectionDAG &DAG) { 3990 SmallVector<SDOperand, 32> Ops; 3991 Ops.push_back(Chain); // Op#0 - Chain 3992 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 3993 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 3994 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 3995 Ops.push_back(Callee); 3996 3997 // Handle all of the outgoing arguments. 3998 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 3999 MVT::ValueType VT = getValueType(Args[i].Ty); 4000 SDOperand Op = Args[i].Node; 4001 unsigned Flags = ISD::ParamFlags::NoFlagSet; 4002 unsigned OriginalAlignment = 4003 getTargetData()->getABITypeAlignment(Args[i].Ty); 4004 4005 if (Args[i].isSExt) 4006 Flags |= ISD::ParamFlags::SExt; 4007 if (Args[i].isZExt) 4008 Flags |= ISD::ParamFlags::ZExt; 4009 if (Args[i].isInReg) 4010 Flags |= ISD::ParamFlags::InReg; 4011 if (Args[i].isSRet) 4012 Flags |= ISD::ParamFlags::StructReturn; 4013 if (Args[i].isByVal) { 4014 Flags |= ISD::ParamFlags::ByVal; 4015 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 4016 const StructType *STy = cast<StructType>(Ty->getElementType()); 4017 unsigned StructAlign = 4018 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy)); 4019 unsigned StructSize = getTargetData()->getTypeSize(STy); 4020 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs); 4021 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs); 4022 } 4023 if (Args[i].isNest) 4024 Flags |= ISD::ParamFlags::Nest; 4025 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs; 4026 4027 switch (getTypeAction(VT)) { 4028 default: assert(0 && "Unknown type action!"); 4029 case Legal: 4030 Ops.push_back(Op); 4031 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4032 break; 4033 case Promote: 4034 if (MVT::isInteger(VT)) { 4035 unsigned ExtOp; 4036 if (Args[i].isSExt) 4037 ExtOp = ISD::SIGN_EXTEND; 4038 else if (Args[i].isZExt) 4039 ExtOp = ISD::ZERO_EXTEND; 4040 else 4041 ExtOp = ISD::ANY_EXTEND; 4042 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 4043 } else { 4044 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 4045 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 4046 } 4047 Ops.push_back(Op); 4048 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4049 break; 4050 case Expand: { 4051 MVT::ValueType PartVT = getRegisterType(VT); 4052 unsigned NumParts = getNumRegisters(VT); 4053 SmallVector<SDOperand, 4> Parts(NumParts); 4054 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT); 4055 for (unsigned i = 0; i != NumParts; ++i) { 4056 // if it isn't first piece, alignment must be 1 4057 unsigned MyFlags = Flags; 4058 if (i != 0) 4059 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) | 4060 (1 << ISD::ParamFlags::OrigAlignmentOffs); 4061 4062 Ops.push_back(Parts[i]); 4063 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32)); 4064 } 4065 break; 4066 } 4067 } 4068 } 4069 4070 // Figure out the result value types. 4071 MVT::ValueType VT = getValueType(RetTy); 4072 MVT::ValueType RegisterVT = getRegisterType(VT); 4073 unsigned NumRegs = getNumRegisters(VT); 4074 SmallVector<MVT::ValueType, 4> RetTys(NumRegs); 4075 for (unsigned i = 0; i != NumRegs; ++i) 4076 RetTys[i] = RegisterVT; 4077 4078 RetTys.push_back(MVT::Other); // Always has a chain. 4079 4080 // Create the CALL node. 4081 SDOperand Res = DAG.getNode(ISD::CALL, 4082 DAG.getVTList(&RetTys[0], NumRegs + 1), 4083 &Ops[0], Ops.size()); 4084 Chain = Res.getValue(NumRegs); 4085 4086 // Gather up the call result into a single value. 4087 if (RetTy != Type::VoidTy) { 4088 ISD::NodeType AssertOp = ISD::AssertSext; 4089 if (!RetTyIsSigned) 4090 AssertOp = ISD::AssertZext; 4091 SmallVector<SDOperand, 4> Results(NumRegs); 4092 for (unsigned i = 0; i != NumRegs; ++i) 4093 Results[i] = Res.getValue(i); 4094 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp); 4095 } 4096 4097 return std::make_pair(Res, Chain); 4098} 4099 4100SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4101 assert(0 && "LowerOperation not implemented for this target!"); 4102 abort(); 4103 return SDOperand(); 4104} 4105 4106SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 4107 SelectionDAG &DAG) { 4108 assert(0 && "CustomPromoteOperation not implemented for this target!"); 4109 abort(); 4110 return SDOperand(); 4111} 4112 4113/// getMemsetValue - Vectorized representation of the memset value 4114/// operand. 4115static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 4116 SelectionDAG &DAG) { 4117 MVT::ValueType CurVT = VT; 4118 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 4119 uint64_t Val = C->getValue() & 255; 4120 unsigned Shift = 8; 4121 while (CurVT != MVT::i8) { 4122 Val = (Val << Shift) | Val; 4123 Shift <<= 1; 4124 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4125 } 4126 return DAG.getConstant(Val, VT); 4127 } else { 4128 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4129 unsigned Shift = 8; 4130 while (CurVT != MVT::i8) { 4131 Value = 4132 DAG.getNode(ISD::OR, VT, 4133 DAG.getNode(ISD::SHL, VT, Value, 4134 DAG.getConstant(Shift, MVT::i8)), Value); 4135 Shift <<= 1; 4136 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4137 } 4138 4139 return Value; 4140 } 4141} 4142 4143/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4144/// used when a memcpy is turned into a memset when the source is a constant 4145/// string ptr. 4146static SDOperand getMemsetStringVal(MVT::ValueType VT, 4147 SelectionDAG &DAG, TargetLowering &TLI, 4148 std::string &Str, unsigned Offset) { 4149 uint64_t Val = 0; 4150 unsigned MSB = MVT::getSizeInBits(VT) / 8; 4151 if (TLI.isLittleEndian()) 4152 Offset = Offset + MSB - 1; 4153 for (unsigned i = 0; i != MSB; ++i) { 4154 Val = (Val << 8) | (unsigned char)Str[Offset]; 4155 Offset += TLI.isLittleEndian() ? -1 : 1; 4156 } 4157 return DAG.getConstant(Val, VT); 4158} 4159 4160/// getMemBasePlusOffset - Returns base and offset node for the 4161static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4162 SelectionDAG &DAG, TargetLowering &TLI) { 4163 MVT::ValueType VT = Base.getValueType(); 4164 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4165} 4166 4167/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4168/// to replace the memset / memcpy is below the threshold. It also returns the 4169/// types of the sequence of memory ops to perform memset / memcpy. 4170static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4171 unsigned Limit, uint64_t Size, 4172 unsigned Align, TargetLowering &TLI) { 4173 MVT::ValueType VT; 4174 4175 if (TLI.allowsUnalignedMemoryAccesses()) { 4176 VT = MVT::i64; 4177 } else { 4178 switch (Align & 7) { 4179 case 0: 4180 VT = MVT::i64; 4181 break; 4182 case 4: 4183 VT = MVT::i32; 4184 break; 4185 case 2: 4186 VT = MVT::i16; 4187 break; 4188 default: 4189 VT = MVT::i8; 4190 break; 4191 } 4192 } 4193 4194 MVT::ValueType LVT = MVT::i64; 4195 while (!TLI.isTypeLegal(LVT)) 4196 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4197 assert(MVT::isInteger(LVT)); 4198 4199 if (VT > LVT) 4200 VT = LVT; 4201 4202 unsigned NumMemOps = 0; 4203 while (Size != 0) { 4204 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4205 while (VTSize > Size) { 4206 VT = (MVT::ValueType)((unsigned)VT - 1); 4207 VTSize >>= 1; 4208 } 4209 assert(MVT::isInteger(VT)); 4210 4211 if (++NumMemOps > Limit) 4212 return false; 4213 MemOps.push_back(VT); 4214 Size -= VTSize; 4215 } 4216 4217 return true; 4218} 4219 4220void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4221 SDOperand Op1 = getValue(I.getOperand(1)); 4222 SDOperand Op2 = getValue(I.getOperand(2)); 4223 SDOperand Op3 = getValue(I.getOperand(3)); 4224 SDOperand Op4 = getValue(I.getOperand(4)); 4225 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4226 if (Align == 0) Align = 1; 4227 4228 // If the source and destination are known to not be aliases, we can 4229 // lower memmove as memcpy. 4230 if (Op == ISD::MEMMOVE) { 4231 uint64_t Size = -1ULL; 4232 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 4233 Size = C->getValue(); 4234 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) == 4235 AliasAnalysis::NoAlias) 4236 Op = ISD::MEMCPY; 4237 } 4238 4239 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4240 std::vector<MVT::ValueType> MemOps; 4241 4242 // Expand memset / memcpy to a series of load / store ops 4243 // if the size operand falls below a certain threshold. 4244 SmallVector<SDOperand, 8> OutChains; 4245 switch (Op) { 4246 default: break; // Do nothing for now. 4247 case ISD::MEMSET: { 4248 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4249 Size->getValue(), Align, TLI)) { 4250 unsigned NumMemOps = MemOps.size(); 4251 unsigned Offset = 0; 4252 for (unsigned i = 0; i < NumMemOps; i++) { 4253 MVT::ValueType VT = MemOps[i]; 4254 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4255 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4256 SDOperand Store = DAG.getStore(getRoot(), Value, 4257 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4258 I.getOperand(1), Offset); 4259 OutChains.push_back(Store); 4260 Offset += VTSize; 4261 } 4262 } 4263 break; 4264 } 4265 case ISD::MEMCPY: { 4266 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4267 Size->getValue(), Align, TLI)) { 4268 unsigned NumMemOps = MemOps.size(); 4269 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4270 GlobalAddressSDNode *G = NULL; 4271 std::string Str; 4272 bool CopyFromStr = false; 4273 4274 if (Op2.getOpcode() == ISD::GlobalAddress) 4275 G = cast<GlobalAddressSDNode>(Op2); 4276 else if (Op2.getOpcode() == ISD::ADD && 4277 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4278 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4279 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4280 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4281 } 4282 if (G) { 4283 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4284 if (GV && GV->isConstant()) { 4285 Str = GV->getStringValue(false); 4286 if (!Str.empty()) { 4287 CopyFromStr = true; 4288 SrcOff += SrcDelta; 4289 } 4290 } 4291 } 4292 4293 for (unsigned i = 0; i < NumMemOps; i++) { 4294 MVT::ValueType VT = MemOps[i]; 4295 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4296 SDOperand Value, Chain, Store; 4297 4298 if (CopyFromStr) { 4299 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4300 Chain = getRoot(); 4301 Store = 4302 DAG.getStore(Chain, Value, 4303 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4304 I.getOperand(1), DstOff); 4305 } else { 4306 Value = DAG.getLoad(VT, getRoot(), 4307 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4308 I.getOperand(2), SrcOff); 4309 Chain = Value.getValue(1); 4310 Store = 4311 DAG.getStore(Chain, Value, 4312 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4313 I.getOperand(1), DstOff); 4314 } 4315 OutChains.push_back(Store); 4316 SrcOff += VTSize; 4317 DstOff += VTSize; 4318 } 4319 } 4320 break; 4321 } 4322 } 4323 4324 if (!OutChains.empty()) { 4325 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4326 &OutChains[0], OutChains.size())); 4327 return; 4328 } 4329 } 4330 4331 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4)); 4332} 4333 4334//===----------------------------------------------------------------------===// 4335// SelectionDAGISel code 4336//===----------------------------------------------------------------------===// 4337 4338unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4339 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 4340} 4341 4342void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4343 AU.addRequired<AliasAnalysis>(); 4344 AU.setPreservesAll(); 4345} 4346 4347 4348 4349bool SelectionDAGISel::runOnFunction(Function &Fn) { 4350 // Get alias analysis for load/store combining. 4351 AA = &getAnalysis<AliasAnalysis>(); 4352 4353 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4354 RegMap = MF.getSSARegMap(); 4355 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4356 4357 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4358 4359 if (ExceptionHandling) 4360 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4361 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4362 // Mark landing pad. 4363 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4364 4365 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4366 SelectBasicBlock(I, MF, FuncInfo); 4367 4368 // Add function live-ins to entry block live-in set. 4369 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4370 BB = FuncInfo.MBBMap[EntryBB]; 4371 if (!MF.livein_empty()) 4372 for (MachineFunction::livein_iterator I = MF.livein_begin(), 4373 E = MF.livein_end(); I != E; ++I) 4374 BB->addLiveIn(I->first); 4375 4376#ifndef NDEBUG 4377 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4378 "Not all catch info was assigned to a landing pad!"); 4379#endif 4380 4381 return true; 4382} 4383 4384SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4385 unsigned Reg) { 4386 SDOperand Op = getValue(V); 4387 assert((Op.getOpcode() != ISD::CopyFromReg || 4388 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4389 "Copy from a reg to the same reg!"); 4390 4391 MVT::ValueType SrcVT = Op.getValueType(); 4392 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT); 4393 unsigned NumRegs = TLI.getNumRegisters(SrcVT); 4394 SmallVector<SDOperand, 8> Regs(NumRegs); 4395 SmallVector<SDOperand, 8> Chains(NumRegs); 4396 4397 // Copy the value by legal parts into sequential virtual registers. 4398 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT); 4399 for (unsigned i = 0; i != NumRegs; ++i) 4400 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); 4401 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 4402} 4403 4404void SelectionDAGISel:: 4405LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4406 std::vector<SDOperand> &UnorderedChains) { 4407 // If this is the entry block, emit arguments. 4408 Function &F = *LLVMBB->getParent(); 4409 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4410 SDOperand OldRoot = SDL.DAG.getRoot(); 4411 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4412 4413 unsigned a = 0; 4414 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4415 AI != E; ++AI, ++a) 4416 if (!AI->use_empty()) { 4417 SDL.setValue(AI, Args[a]); 4418 4419 // If this argument is live outside of the entry block, insert a copy from 4420 // whereever we got it to the vreg that other BB's will reference it as. 4421 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4422 if (VMI != FuncInfo.ValueMap.end()) { 4423 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4424 UnorderedChains.push_back(Copy); 4425 } 4426 } 4427 4428 // Finally, if the target has anything special to do, allow it to do so. 4429 // FIXME: this should insert code into the DAG! 4430 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4431} 4432 4433static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4434 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4435 assert(!FLI.MBBMap[SrcBB]->isLandingPad() && 4436 "Copying catch info out of a landing pad!"); 4437 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4438 if (isSelector(I)) { 4439 // Apply the catch info to DestBB. 4440 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4441#ifndef NDEBUG 4442 FLI.CatchInfoFound.insert(I); 4443#endif 4444 } 4445} 4446 4447void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4448 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4449 FunctionLoweringInfo &FuncInfo) { 4450 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo); 4451 4452 std::vector<SDOperand> UnorderedChains; 4453 4454 // Lower any arguments needed in this block if this is the entry block. 4455 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4456 LowerArguments(LLVMBB, SDL, UnorderedChains); 4457 4458 BB = FuncInfo.MBBMap[LLVMBB]; 4459 SDL.setCurrentBasicBlock(BB); 4460 4461 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4462 4463 if (ExceptionHandling && MMI && BB->isLandingPad()) { 4464 // Add a label to mark the beginning of the landing pad. Deletion of the 4465 // landing pad can thus be detected via the MachineModuleInfo. 4466 unsigned LabelID = MMI->addLandingPad(BB); 4467 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 4468 DAG.getConstant(LabelID, MVT::i32))); 4469 4470 // Mark exception register as live in. 4471 unsigned Reg = TLI.getExceptionAddressRegister(); 4472 if (Reg) BB->addLiveIn(Reg); 4473 4474 // Mark exception selector register as live in. 4475 Reg = TLI.getExceptionSelectorRegister(); 4476 if (Reg) BB->addLiveIn(Reg); 4477 4478 // FIXME: Hack around an exception handling flaw (PR1508): the personality 4479 // function and list of typeids logically belong to the invoke (or, if you 4480 // like, the basic block containing the invoke), and need to be associated 4481 // with it in the dwarf exception handling tables. Currently however the 4482 // information is provided by an intrinsic (eh.selector) that can be moved 4483 // to unexpected places by the optimizers: if the unwind edge is critical, 4484 // then breaking it can result in the intrinsics being in the successor of 4485 // the landing pad, not the landing pad itself. This results in exceptions 4486 // not being caught because no typeids are associated with the invoke. 4487 // This may not be the only way things can go wrong, but it is the only way 4488 // we try to work around for the moment. 4489 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 4490 4491 if (Br && Br->isUnconditional()) { // Critical edge? 4492 BasicBlock::iterator I, E; 4493 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 4494 if (isSelector(I)) 4495 break; 4496 4497 if (I == E) 4498 // No catch info found - try to extract some from the successor. 4499 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 4500 } 4501 } 4502 4503 // Lower all of the non-terminator instructions. 4504 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4505 I != E; ++I) 4506 SDL.visit(*I); 4507 4508 // Ensure that all instructions which are used outside of their defining 4509 // blocks are available as virtual registers. Invoke is handled elsewhere. 4510 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4511 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 4512 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4513 if (VMI != FuncInfo.ValueMap.end()) 4514 UnorderedChains.push_back( 4515 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4516 } 4517 4518 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4519 // ensure constants are generated when needed. Remember the virtual registers 4520 // that need to be added to the Machine PHI nodes as input. We cannot just 4521 // directly add them, because expansion might result in multiple MBB's for one 4522 // BB. As such, the start of the BB might correspond to a different MBB than 4523 // the end. 4524 // 4525 TerminatorInst *TI = LLVMBB->getTerminator(); 4526 4527 // Emit constants only once even if used by multiple PHI nodes. 4528 std::map<Constant*, unsigned> ConstantsOut; 4529 4530 // Vector bool would be better, but vector<bool> is really slow. 4531 std::vector<unsigned char> SuccsHandled; 4532 if (TI->getNumSuccessors()) 4533 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4534 4535 // Check successor nodes' PHI nodes that expect a constant to be available 4536 // from this block. 4537 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4538 BasicBlock *SuccBB = TI->getSuccessor(succ); 4539 if (!isa<PHINode>(SuccBB->begin())) continue; 4540 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4541 4542 // If this terminator has multiple identical successors (common for 4543 // switches), only handle each succ once. 4544 unsigned SuccMBBNo = SuccMBB->getNumber(); 4545 if (SuccsHandled[SuccMBBNo]) continue; 4546 SuccsHandled[SuccMBBNo] = true; 4547 4548 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4549 PHINode *PN; 4550 4551 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4552 // nodes and Machine PHI nodes, but the incoming operands have not been 4553 // emitted yet. 4554 for (BasicBlock::iterator I = SuccBB->begin(); 4555 (PN = dyn_cast<PHINode>(I)); ++I) { 4556 // Ignore dead phi's. 4557 if (PN->use_empty()) continue; 4558 4559 unsigned Reg; 4560 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4561 4562 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4563 unsigned &RegOut = ConstantsOut[C]; 4564 if (RegOut == 0) { 4565 RegOut = FuncInfo.CreateRegForValue(C); 4566 UnorderedChains.push_back( 4567 SDL.CopyValueToVirtualRegister(C, RegOut)); 4568 } 4569 Reg = RegOut; 4570 } else { 4571 Reg = FuncInfo.ValueMap[PHIOp]; 4572 if (Reg == 0) { 4573 assert(isa<AllocaInst>(PHIOp) && 4574 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4575 "Didn't codegen value into a register!??"); 4576 Reg = FuncInfo.CreateRegForValue(PHIOp); 4577 UnorderedChains.push_back( 4578 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4579 } 4580 } 4581 4582 // Remember that this register needs to added to the machine PHI node as 4583 // the input for this MBB. 4584 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4585 unsigned NumRegisters = TLI.getNumRegisters(VT); 4586 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 4587 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4588 } 4589 } 4590 ConstantsOut.clear(); 4591 4592 // Turn all of the unordered chains into one factored node. 4593 if (!UnorderedChains.empty()) { 4594 SDOperand Root = SDL.getRoot(); 4595 if (Root.getOpcode() != ISD::EntryToken) { 4596 unsigned i = 0, e = UnorderedChains.size(); 4597 for (; i != e; ++i) { 4598 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4599 if (UnorderedChains[i].Val->getOperand(0) == Root) 4600 break; // Don't add the root if we already indirectly depend on it. 4601 } 4602 4603 if (i == e) 4604 UnorderedChains.push_back(Root); 4605 } 4606 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4607 &UnorderedChains[0], UnorderedChains.size())); 4608 } 4609 4610 // Lower the terminator after the copies are emitted. 4611 SDL.visit(*LLVMBB->getTerminator()); 4612 4613 // Copy over any CaseBlock records that may now exist due to SwitchInst 4614 // lowering, as well as any jump table information. 4615 SwitchCases.clear(); 4616 SwitchCases = SDL.SwitchCases; 4617 JTCases.clear(); 4618 JTCases = SDL.JTCases; 4619 BitTestCases.clear(); 4620 BitTestCases = SDL.BitTestCases; 4621 4622 // Make sure the root of the DAG is up-to-date. 4623 DAG.setRoot(SDL.getRoot()); 4624} 4625 4626void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4627 // Run the DAG combiner in pre-legalize mode. 4628 DAG.Combine(false, *AA); 4629 4630 DOUT << "Lowered selection DAG:\n"; 4631 DEBUG(DAG.dump()); 4632 4633 // Second step, hack on the DAG until it only uses operations and types that 4634 // the target supports. 4635 DAG.Legalize(); 4636 4637 DOUT << "Legalized selection DAG:\n"; 4638 DEBUG(DAG.dump()); 4639 4640 // Run the DAG combiner in post-legalize mode. 4641 DAG.Combine(true, *AA); 4642 4643 if (ViewISelDAGs) DAG.viewGraph(); 4644 4645 // Third, instruction select all of the operations to machine code, adding the 4646 // code to the MachineBasicBlock. 4647 InstructionSelectBasicBlock(DAG); 4648 4649 DOUT << "Selected machine code:\n"; 4650 DEBUG(BB->dump()); 4651} 4652 4653void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4654 FunctionLoweringInfo &FuncInfo) { 4655 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4656 { 4657 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4658 CurDAG = &DAG; 4659 4660 // First step, lower LLVM code to some DAG. This DAG may use operations and 4661 // types that are not supported by the target. 4662 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4663 4664 // Second step, emit the lowered DAG as machine code. 4665 CodeGenAndEmitDAG(DAG); 4666 } 4667 4668 DOUT << "Total amount of phi nodes to update: " 4669 << PHINodesToUpdate.size() << "\n"; 4670 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4671 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4672 << ", " << PHINodesToUpdate[i].second << ")\n";); 4673 4674 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4675 // PHI nodes in successors. 4676 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4677 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4678 MachineInstr *PHI = PHINodesToUpdate[i].first; 4679 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4680 "This is not a machine PHI node that we are updating!"); 4681 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4682 PHI->addMachineBasicBlockOperand(BB); 4683 } 4684 return; 4685 } 4686 4687 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4688 // Lower header first, if it wasn't already lowered 4689 if (!BitTestCases[i].Emitted) { 4690 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4691 CurDAG = &HSDAG; 4692 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo); 4693 // Set the current basic block to the mbb we wish to insert the code into 4694 BB = BitTestCases[i].Parent; 4695 HSDL.setCurrentBasicBlock(BB); 4696 // Emit the code 4697 HSDL.visitBitTestHeader(BitTestCases[i]); 4698 HSDAG.setRoot(HSDL.getRoot()); 4699 CodeGenAndEmitDAG(HSDAG); 4700 } 4701 4702 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4703 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4704 CurDAG = &BSDAG; 4705 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo); 4706 // Set the current basic block to the mbb we wish to insert the code into 4707 BB = BitTestCases[i].Cases[j].ThisBB; 4708 BSDL.setCurrentBasicBlock(BB); 4709 // Emit the code 4710 if (j+1 != ej) 4711 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 4712 BitTestCases[i].Reg, 4713 BitTestCases[i].Cases[j]); 4714 else 4715 BSDL.visitBitTestCase(BitTestCases[i].Default, 4716 BitTestCases[i].Reg, 4717 BitTestCases[i].Cases[j]); 4718 4719 4720 BSDAG.setRoot(BSDL.getRoot()); 4721 CodeGenAndEmitDAG(BSDAG); 4722 } 4723 4724 // Update PHI Nodes 4725 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4726 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4727 MachineBasicBlock *PHIBB = PHI->getParent(); 4728 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4729 "This is not a machine PHI node that we are updating!"); 4730 // This is "default" BB. We have two jumps to it. From "header" BB and 4731 // from last "case" BB. 4732 if (PHIBB == BitTestCases[i].Default) { 4733 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4734 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent); 4735 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4736 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB); 4737 } 4738 // One of "cases" BB. 4739 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4740 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 4741 if (cBB->succ_end() != 4742 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 4743 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4744 PHI->addMachineBasicBlockOperand(cBB); 4745 } 4746 } 4747 } 4748 } 4749 4750 // If the JumpTable record is filled in, then we need to emit a jump table. 4751 // Updating the PHI nodes is tricky in this case, since we need to determine 4752 // whether the PHI is a successor of the range check MBB or the jump table MBB 4753 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 4754 // Lower header first, if it wasn't already lowered 4755 if (!JTCases[i].first.Emitted) { 4756 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4757 CurDAG = &HSDAG; 4758 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo); 4759 // Set the current basic block to the mbb we wish to insert the code into 4760 BB = JTCases[i].first.HeaderBB; 4761 HSDL.setCurrentBasicBlock(BB); 4762 // Emit the code 4763 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 4764 HSDAG.setRoot(HSDL.getRoot()); 4765 CodeGenAndEmitDAG(HSDAG); 4766 } 4767 4768 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4769 CurDAG = &JSDAG; 4770 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo); 4771 // Set the current basic block to the mbb we wish to insert the code into 4772 BB = JTCases[i].second.MBB; 4773 JSDL.setCurrentBasicBlock(BB); 4774 // Emit the code 4775 JSDL.visitJumpTable(JTCases[i].second); 4776 JSDAG.setRoot(JSDL.getRoot()); 4777 CodeGenAndEmitDAG(JSDAG); 4778 4779 // Update PHI Nodes 4780 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4781 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4782 MachineBasicBlock *PHIBB = PHI->getParent(); 4783 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4784 "This is not a machine PHI node that we are updating!"); 4785 // "default" BB. We can go there only from header BB. 4786 if (PHIBB == JTCases[i].second.Default) { 4787 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4788 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB); 4789 } 4790 // JT BB. Just iterate over successors here 4791 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 4792 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4793 PHI->addMachineBasicBlockOperand(BB); 4794 } 4795 } 4796 } 4797 4798 // If the switch block involved a branch to one of the actual successors, we 4799 // need to update PHI nodes in that block. 4800 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4801 MachineInstr *PHI = PHINodesToUpdate[i].first; 4802 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4803 "This is not a machine PHI node that we are updating!"); 4804 if (BB->isSuccessor(PHI->getParent())) { 4805 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4806 PHI->addMachineBasicBlockOperand(BB); 4807 } 4808 } 4809 4810 // If we generated any switch lowering information, build and codegen any 4811 // additional DAGs necessary. 4812 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 4813 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4814 CurDAG = &SDAG; 4815 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo); 4816 4817 // Set the current basic block to the mbb we wish to insert the code into 4818 BB = SwitchCases[i].ThisBB; 4819 SDL.setCurrentBasicBlock(BB); 4820 4821 // Emit the code 4822 SDL.visitSwitchCase(SwitchCases[i]); 4823 SDAG.setRoot(SDL.getRoot()); 4824 CodeGenAndEmitDAG(SDAG); 4825 4826 // Handle any PHI nodes in successors of this chunk, as if we were coming 4827 // from the original BB before switch expansion. Note that PHI nodes can 4828 // occur multiple times in PHINodesToUpdate. We have to be very careful to 4829 // handle them the right number of times. 4830 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 4831 for (MachineBasicBlock::iterator Phi = BB->begin(); 4832 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 4833 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 4834 for (unsigned pn = 0; ; ++pn) { 4835 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 4836 if (PHINodesToUpdate[pn].first == Phi) { 4837 Phi->addRegOperand(PHINodesToUpdate[pn].second, false); 4838 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB); 4839 break; 4840 } 4841 } 4842 } 4843 4844 // Don't process RHS if same block as LHS. 4845 if (BB == SwitchCases[i].FalseBB) 4846 SwitchCases[i].FalseBB = 0; 4847 4848 // If we haven't handled the RHS, do so now. Otherwise, we're done. 4849 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 4850 SwitchCases[i].FalseBB = 0; 4851 } 4852 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 4853 } 4854} 4855 4856 4857//===----------------------------------------------------------------------===// 4858/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 4859/// target node in the graph. 4860void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 4861 if (ViewSchedDAGs) DAG.viewGraph(); 4862 4863 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 4864 4865 if (!Ctor) { 4866 Ctor = ISHeuristic; 4867 RegisterScheduler::setDefault(Ctor); 4868 } 4869 4870 ScheduleDAG *SL = Ctor(this, &DAG, BB); 4871 BB = SL->Run(); 4872 4873 if (ViewSUnitDAGs) SL->viewGraph(); 4874 4875 delete SL; 4876} 4877 4878 4879HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 4880 return new HazardRecognizer(); 4881} 4882 4883//===----------------------------------------------------------------------===// 4884// Helper functions used by the generated instruction selector. 4885//===----------------------------------------------------------------------===// 4886// Calls to these methods are generated by tblgen. 4887 4888/// CheckAndMask - The isel is trying to match something like (and X, 255). If 4889/// the dag combiner simplified the 255, we still want to match. RHS is the 4890/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 4891/// specified in the .td file (e.g. 255). 4892bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 4893 int64_t DesiredMaskS) const { 4894 uint64_t ActualMask = RHS->getValue(); 4895 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4896 4897 // If the actual mask exactly matches, success! 4898 if (ActualMask == DesiredMask) 4899 return true; 4900 4901 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4902 if (ActualMask & ~DesiredMask) 4903 return false; 4904 4905 // Otherwise, the DAG Combiner may have proven that the value coming in is 4906 // either already zero or is not demanded. Check for known zero input bits. 4907 uint64_t NeededMask = DesiredMask & ~ActualMask; 4908 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 4909 return true; 4910 4911 // TODO: check to see if missing bits are just not demanded. 4912 4913 // Otherwise, this pattern doesn't match. 4914 return false; 4915} 4916 4917/// CheckOrMask - The isel is trying to match something like (or X, 255). If 4918/// the dag combiner simplified the 255, we still want to match. RHS is the 4919/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 4920/// specified in the .td file (e.g. 255). 4921bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 4922 int64_t DesiredMaskS) const { 4923 uint64_t ActualMask = RHS->getValue(); 4924 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4925 4926 // If the actual mask exactly matches, success! 4927 if (ActualMask == DesiredMask) 4928 return true; 4929 4930 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4931 if (ActualMask & ~DesiredMask) 4932 return false; 4933 4934 // Otherwise, the DAG Combiner may have proven that the value coming in is 4935 // either already zero or is not demanded. Check for known zero input bits. 4936 uint64_t NeededMask = DesiredMask & ~ActualMask; 4937 4938 uint64_t KnownZero, KnownOne; 4939 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 4940 4941 // If all the missing bits in the or are already known to be set, match! 4942 if ((NeededMask & KnownOne) == NeededMask) 4943 return true; 4944 4945 // TODO: check to see if missing bits are just not demanded. 4946 4947 // Otherwise, this pattern doesn't match. 4948 return false; 4949} 4950 4951 4952/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 4953/// by tblgen. Others should not call it. 4954void SelectionDAGISel:: 4955SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 4956 std::vector<SDOperand> InOps; 4957 std::swap(InOps, Ops); 4958 4959 Ops.push_back(InOps[0]); // input chain. 4960 Ops.push_back(InOps[1]); // input asm string. 4961 4962 unsigned i = 2, e = InOps.size(); 4963 if (InOps[e-1].getValueType() == MVT::Flag) 4964 --e; // Don't process a flag operand if it is here. 4965 4966 while (i != e) { 4967 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 4968 if ((Flags & 7) != 4 /*MEM*/) { 4969 // Just skip over this operand, copying the operands verbatim. 4970 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 4971 i += (Flags >> 3) + 1; 4972 } else { 4973 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 4974 // Otherwise, this is a memory operand. Ask the target to select it. 4975 std::vector<SDOperand> SelOps; 4976 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 4977 cerr << "Could not match memory address. Inline asm failure!\n"; 4978 exit(1); 4979 } 4980 4981 // Add this to the output node. 4982 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 4983 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 4984 IntPtrTy)); 4985 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 4986 i += 2; 4987 } 4988 } 4989 4990 // Add the flag input back if present. 4991 if (e != InOps.size()) 4992 Ops.push_back(InOps.back()); 4993} 4994 4995char SelectionDAGISel::ID = 0; 4996