SelectionDAGISel.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "ScheduleDAGSDNodes.h" 17#include "SelectionDAGBuilder.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/Statistic.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/BranchProbabilityInfo.h" 22#include "llvm/Analysis/CFG.h" 23#include "llvm/CodeGen/FastISel.h" 24#include "llvm/CodeGen/FunctionLoweringInfo.h" 25#include "llvm/CodeGen/GCMetadata.h" 26#include "llvm/CodeGen/GCStrategy.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/MachineModuleInfo.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 33#include "llvm/CodeGen/SchedulerRegistry.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/IR/Constants.h" 36#include "llvm/IR/DebugInfo.h" 37#include "llvm/IR/Function.h" 38#include "llvm/IR/InlineAsm.h" 39#include "llvm/IR/Instructions.h" 40#include "llvm/IR/IntrinsicInst.h" 41#include "llvm/IR/Intrinsics.h" 42#include "llvm/IR/LLVMContext.h" 43#include "llvm/IR/Module.h" 44#include "llvm/Support/Compiler.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/Timer.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLibraryInfo.h" 52#include "llvm/Target/TargetLowering.h" 53#include "llvm/Target/TargetMachine.h" 54#include "llvm/Target/TargetOptions.h" 55#include "llvm/Target/TargetRegisterInfo.h" 56#include "llvm/Target/TargetSubtargetInfo.h" 57#include "llvm/Transforms/Utils/BasicBlockUtils.h" 58#include <algorithm> 59using namespace llvm; 60 61STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 62STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 63STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 64STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 65STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 66STATISTIC(NumEntryBlocks, "Number of entry blocks encountered"); 67STATISTIC(NumFastIselFailLowerArguments, 68 "Number of entry blocks where fast isel failed to lower arguments"); 69 70#ifndef NDEBUG 71static cl::opt<bool> 72EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 73 cl::desc("Enable extra verbose messages in the \"fast\" " 74 "instruction selector")); 75 76 // Terminators 77STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 78STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 79STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 80STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 81STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 82STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 83STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 84 85 // Standard binary operators... 86STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 87STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 88STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 89STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 90STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 91STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 92STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 93STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 94STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 95STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 96STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 97STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 98 99 // Logical operators... 100STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 101STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 102STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 103 104 // Memory instructions... 105STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 106STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 107STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 108STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 109STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 110STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 111STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 112 113 // Convert instructions... 114STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 115STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 116STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 117STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 118STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 119STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 120STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 121STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 122STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 123STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 124STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 125STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 126 127 // Other instructions... 128STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 129STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 130STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 131STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 132STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 133STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 134STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 135STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 136STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 137STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 138STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 139STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 140STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 141STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 142STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 143#endif 144 145static cl::opt<bool> 146EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 147 cl::desc("Enable verbose messages in the \"fast\" " 148 "instruction selector")); 149static cl::opt<bool> 150EnableFastISelAbort("fast-isel-abort", cl::Hidden, 151 cl::desc("Enable abort calls when \"fast\" instruction selection " 152 "fails to lower an instruction")); 153static cl::opt<bool> 154EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden, 155 cl::desc("Enable abort calls when \"fast\" instruction selection " 156 "fails to lower a formal argument")); 157 158static cl::opt<bool> 159UseMBPI("use-mbpi", 160 cl::desc("use Machine Branch Probability Info"), 161 cl::init(true), cl::Hidden); 162 163#ifndef NDEBUG 164static cl::opt<bool> 165ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 166 cl::desc("Pop up a window to show dags before the first " 167 "dag combine pass")); 168static cl::opt<bool> 169ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 170 cl::desc("Pop up a window to show dags before legalize types")); 171static cl::opt<bool> 172ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 173 cl::desc("Pop up a window to show dags before legalize")); 174static cl::opt<bool> 175ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 176 cl::desc("Pop up a window to show dags before the second " 177 "dag combine pass")); 178static cl::opt<bool> 179ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 180 cl::desc("Pop up a window to show dags before the post legalize types" 181 " dag combine pass")); 182static cl::opt<bool> 183ViewISelDAGs("view-isel-dags", cl::Hidden, 184 cl::desc("Pop up a window to show isel dags as they are selected")); 185static cl::opt<bool> 186ViewSchedDAGs("view-sched-dags", cl::Hidden, 187 cl::desc("Pop up a window to show sched dags as they are processed")); 188static cl::opt<bool> 189ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 190 cl::desc("Pop up a window to show SUnit dags after they are processed")); 191#else 192static const bool ViewDAGCombine1 = false, 193 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 194 ViewDAGCombine2 = false, 195 ViewDAGCombineLT = false, 196 ViewISelDAGs = false, ViewSchedDAGs = false, 197 ViewSUnitDAGs = false; 198#endif 199 200//===---------------------------------------------------------------------===// 201/// 202/// RegisterScheduler class - Track the registration of instruction schedulers. 203/// 204//===---------------------------------------------------------------------===// 205MachinePassRegistry RegisterScheduler::Registry; 206 207//===---------------------------------------------------------------------===// 208/// 209/// ISHeuristic command line option for instruction schedulers. 210/// 211//===---------------------------------------------------------------------===// 212static cl::opt<RegisterScheduler::FunctionPassCtor, false, 213 RegisterPassParser<RegisterScheduler> > 214ISHeuristic("pre-RA-sched", 215 cl::init(&createDefaultScheduler), cl::Hidden, 216 cl::desc("Instruction schedulers available (before register" 217 " allocation):")); 218 219static RegisterScheduler 220defaultListDAGScheduler("default", "Best scheduler for the target", 221 createDefaultScheduler); 222 223namespace llvm { 224 //===--------------------------------------------------------------------===// 225 /// \brief This class is used by SelectionDAGISel to temporarily override 226 /// the optimization level on a per-function basis. 227 class OptLevelChanger { 228 SelectionDAGISel &IS; 229 CodeGenOpt::Level SavedOptLevel; 230 bool SavedFastISel; 231 232 public: 233 OptLevelChanger(SelectionDAGISel &ISel, 234 CodeGenOpt::Level NewOptLevel) : IS(ISel) { 235 SavedOptLevel = IS.OptLevel; 236 if (NewOptLevel == SavedOptLevel) 237 return; 238 IS.OptLevel = NewOptLevel; 239 IS.TM.setOptLevel(NewOptLevel); 240 SavedFastISel = IS.TM.Options.EnableFastISel; 241 if (NewOptLevel == CodeGenOpt::None) 242 IS.TM.setFastISel(true); 243 DEBUG(dbgs() << "\nChanging optimization level for Function " 244 << IS.MF->getFunction()->getName() << "\n"); 245 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel 246 << " ; After: -O" << NewOptLevel << "\n"); 247 } 248 249 ~OptLevelChanger() { 250 if (IS.OptLevel == SavedOptLevel) 251 return; 252 DEBUG(dbgs() << "\nRestoring optimization level for Function " 253 << IS.MF->getFunction()->getName() << "\n"); 254 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel 255 << " ; After: -O" << SavedOptLevel << "\n"); 256 IS.OptLevel = SavedOptLevel; 257 IS.TM.setOptLevel(SavedOptLevel); 258 IS.TM.setFastISel(SavedFastISel); 259 } 260 }; 261 262 //===--------------------------------------------------------------------===// 263 /// createDefaultScheduler - This creates an instruction scheduler appropriate 264 /// for the target. 265 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 266 CodeGenOpt::Level OptLevel) { 267 const TargetLowering *TLI = IS->getTargetLowering(); 268 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 269 270 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() || 271 TLI->getSchedulingPreference() == Sched::Source) 272 return createSourceListDAGScheduler(IS, OptLevel); 273 if (TLI->getSchedulingPreference() == Sched::RegPressure) 274 return createBURRListDAGScheduler(IS, OptLevel); 275 if (TLI->getSchedulingPreference() == Sched::Hybrid) 276 return createHybridListDAGScheduler(IS, OptLevel); 277 if (TLI->getSchedulingPreference() == Sched::VLIW) 278 return createVLIWDAGScheduler(IS, OptLevel); 279 assert(TLI->getSchedulingPreference() == Sched::ILP && 280 "Unknown sched type!"); 281 return createILPListDAGScheduler(IS, OptLevel); 282 } 283} 284 285// EmitInstrWithCustomInserter - This method should be implemented by targets 286// that mark instructions with the 'usesCustomInserter' flag. These 287// instructions are special in various ways, which require special support to 288// insert. The specified MachineInstr is created but not inserted into any 289// basic blocks, and this method is called to expand it into a sequence of 290// instructions, potentially also creating new basic blocks and control flow. 291// When new basic blocks are inserted and the edges from MBB to its successors 292// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 293// DenseMap. 294MachineBasicBlock * 295TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 296 MachineBasicBlock *MBB) const { 297#ifndef NDEBUG 298 dbgs() << "If a target marks an instruction with " 299 "'usesCustomInserter', it must implement " 300 "TargetLowering::EmitInstrWithCustomInserter!"; 301#endif 302 llvm_unreachable(0); 303} 304 305void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 306 SDNode *Node) const { 307 assert(!MI->hasPostISelHook() && 308 "If a target marks an instruction with 'hasPostISelHook', " 309 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 310} 311 312//===----------------------------------------------------------------------===// 313// SelectionDAGISel code 314//===----------------------------------------------------------------------===// 315 316SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, 317 CodeGenOpt::Level OL) : 318 MachineFunctionPass(ID), TM(tm), 319 FuncInfo(new FunctionLoweringInfo(TM)), 320 CurDAG(new SelectionDAG(tm, OL)), 321 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 322 GFI(), 323 OptLevel(OL), 324 DAGSize(0) { 325 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 326 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 327 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 328 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 329 } 330 331SelectionDAGISel::~SelectionDAGISel() { 332 delete SDB; 333 delete CurDAG; 334 delete FuncInfo; 335} 336 337void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 338 AU.addRequired<AliasAnalysis>(); 339 AU.addPreserved<AliasAnalysis>(); 340 AU.addRequired<GCModuleInfo>(); 341 AU.addPreserved<GCModuleInfo>(); 342 AU.addRequired<TargetLibraryInfo>(); 343 if (UseMBPI && OptLevel != CodeGenOpt::None) 344 AU.addRequired<BranchProbabilityInfo>(); 345 MachineFunctionPass::getAnalysisUsage(AU); 346} 347 348/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 349/// may trap on it. In this case we have to split the edge so that the path 350/// through the predecessor block that doesn't go to the phi block doesn't 351/// execute the possibly trapping instruction. 352/// 353/// This is required for correctness, so it must be done at -O0. 354/// 355static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 356 // Loop for blocks with phi nodes. 357 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 358 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 359 if (PN == 0) continue; 360 361 ReprocessBlock: 362 // For each block with a PHI node, check to see if any of the input values 363 // are potentially trapping constant expressions. Constant expressions are 364 // the only potentially trapping value that can occur as the argument to a 365 // PHI. 366 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 367 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 368 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 369 if (CE == 0 || !CE->canTrap()) continue; 370 371 // The only case we have to worry about is when the edge is critical. 372 // Since this block has a PHI Node, we assume it has multiple input 373 // edges: check to see if the pred has multiple successors. 374 BasicBlock *Pred = PN->getIncomingBlock(i); 375 if (Pred->getTerminator()->getNumSuccessors() == 1) 376 continue; 377 378 // Okay, we have to split this edge. 379 SplitCriticalEdge(Pred->getTerminator(), 380 GetSuccessorNumber(Pred, BB), SDISel, true); 381 goto ReprocessBlock; 382 } 383 } 384} 385 386bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 387 // Do some sanity-checking on the command-line options. 388 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 389 "-fast-isel-verbose requires -fast-isel"); 390 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 391 "-fast-isel-abort requires -fast-isel"); 392 393 const Function &Fn = *mf.getFunction(); 394 const TargetInstrInfo &TII = *TM.getInstrInfo(); 395 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 396 const TargetLowering *TLI = TM.getTargetLowering(); 397 398 MF = &mf; 399 RegInfo = &MF->getRegInfo(); 400 AA = &getAnalysis<AliasAnalysis>(); 401 LibInfo = &getAnalysis<TargetLibraryInfo>(); 402 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 403 404 TargetSubtargetInfo &ST = 405 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 406 ST.resetSubtargetFeatures(MF); 407 TM.resetTargetOptions(MF); 408 409 // Reset OptLevel to None for optnone functions. 410 CodeGenOpt::Level NewOptLevel = OptLevel; 411 if (Fn.hasFnAttribute(Attribute::OptimizeNone)) 412 NewOptLevel = CodeGenOpt::None; 413 OptLevelChanger OLC(*this, NewOptLevel); 414 415 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 416 417 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 418 419 CurDAG->init(*MF, TLI); 420 FuncInfo->set(Fn, *MF, CurDAG); 421 422 if (UseMBPI && OptLevel != CodeGenOpt::None) 423 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 424 else 425 FuncInfo->BPI = 0; 426 427 SDB->init(GFI, *AA, LibInfo); 428 429 MF->setHasInlineAsm(false); 430 431 SelectAllBasicBlocks(Fn); 432 433 // If the first basic block in the function has live ins that need to be 434 // copied into vregs, emit the copies into the top of the block before 435 // emitting the code for the block. 436 MachineBasicBlock *EntryMBB = MF->begin(); 437 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 438 439 DenseMap<unsigned, unsigned> LiveInMap; 440 if (!FuncInfo->ArgDbgValues.empty()) 441 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 442 E = RegInfo->livein_end(); LI != E; ++LI) 443 if (LI->second) 444 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 445 446 // Insert DBG_VALUE instructions for function arguments to the entry block. 447 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 448 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 449 bool hasFI = MI->getOperand(0).isFI(); 450 unsigned Reg = 451 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg(); 452 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 453 EntryMBB->insert(EntryMBB->begin(), MI); 454 else { 455 MachineInstr *Def = RegInfo->getVRegDef(Reg); 456 if (Def) { 457 MachineBasicBlock::iterator InsertPos = Def; 458 // FIXME: VR def may not be in entry block. 459 Def->getParent()->insert(std::next(InsertPos), MI); 460 } else 461 DEBUG(dbgs() << "Dropping debug info for dead vreg" 462 << TargetRegisterInfo::virtReg2Index(Reg) << "\n"); 463 } 464 465 // If Reg is live-in then update debug info to track its copy in a vreg. 466 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 467 if (LDI != LiveInMap.end()) { 468 assert(!hasFI && "There's no handling of frame pointer updating here yet " 469 "- add if needed"); 470 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 471 MachineBasicBlock::iterator InsertPos = Def; 472 const MDNode *Variable = 473 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 474 bool IsIndirect = MI->isIndirectDebugValue(); 475 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; 476 // Def is never a terminator here, so it is ok to increment InsertPos. 477 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 478 TII.get(TargetOpcode::DBG_VALUE), 479 IsIndirect, 480 LDI->second, Offset, Variable); 481 482 // If this vreg is directly copied into an exported register then 483 // that COPY instructions also need DBG_VALUE, if it is the only 484 // user of LDI->second. 485 MachineInstr *CopyUseMI = NULL; 486 for (MachineRegisterInfo::use_instr_iterator 487 UI = RegInfo->use_instr_begin(LDI->second), 488 E = RegInfo->use_instr_end(); UI != E; ) { 489 MachineInstr *UseMI = &*(UI++); 490 if (UseMI->isDebugValue()) continue; 491 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 492 CopyUseMI = UseMI; continue; 493 } 494 // Otherwise this is another use or second copy use. 495 CopyUseMI = NULL; break; 496 } 497 if (CopyUseMI) { 498 MachineInstr *NewMI = 499 BuildMI(*MF, CopyUseMI->getDebugLoc(), 500 TII.get(TargetOpcode::DBG_VALUE), 501 IsIndirect, 502 CopyUseMI->getOperand(0).getReg(), 503 Offset, Variable); 504 MachineBasicBlock::iterator Pos = CopyUseMI; 505 EntryMBB->insertAfter(Pos, NewMI); 506 } 507 } 508 } 509 510 // Determine if there are any calls in this machine function. 511 MachineFrameInfo *MFI = MF->getFrameInfo(); 512 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E; 513 ++I) { 514 515 if (MFI->hasCalls() && MF->hasInlineAsm()) 516 break; 517 518 const MachineBasicBlock *MBB = I; 519 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end(); 520 II != IE; ++II) { 521 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 522 if ((MCID.isCall() && !MCID.isReturn()) || 523 II->isStackAligningInlineAsm()) { 524 MFI->setHasCalls(true); 525 } 526 if (II->isInlineAsm()) { 527 MF->setHasInlineAsm(true); 528 } 529 } 530 } 531 532 // Determine if there is a call to setjmp in the machine function. 533 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 534 535 // Replace forward-declared registers with the registers containing 536 // the desired value. 537 MachineRegisterInfo &MRI = MF->getRegInfo(); 538 for (DenseMap<unsigned, unsigned>::iterator 539 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 540 I != E; ++I) { 541 unsigned From = I->first; 542 unsigned To = I->second; 543 // If To is also scheduled to be replaced, find what its ultimate 544 // replacement is. 545 for (;;) { 546 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 547 if (J == E) break; 548 To = J->second; 549 } 550 // Make sure the new register has a sufficiently constrained register class. 551 if (TargetRegisterInfo::isVirtualRegister(From) && 552 TargetRegisterInfo::isVirtualRegister(To)) 553 MRI.constrainRegClass(To, MRI.getRegClass(From)); 554 // Replace it. 555 MRI.replaceRegWith(From, To); 556 } 557 558 // Freeze the set of reserved registers now that MachineFrameInfo has been 559 // set up. All the information required by getReservedRegs() should be 560 // available now. 561 MRI.freezeReservedRegs(*MF); 562 563 // Release function-specific state. SDB and CurDAG are already cleared 564 // at this point. 565 FuncInfo->clear(); 566 567 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n"); 568 DEBUG(MF->print(dbgs())); 569 570 return true; 571} 572 573void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 574 BasicBlock::const_iterator End, 575 bool &HadTailCall) { 576 // Lower all of the non-terminator instructions. If a call is emitted 577 // as a tail call, cease emitting nodes for this block. Terminators 578 // are handled below. 579 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 580 SDB->visit(*I); 581 582 // Make sure the root of the DAG is up-to-date. 583 CurDAG->setRoot(SDB->getControlRoot()); 584 HadTailCall = SDB->HasTailCall; 585 SDB->clear(); 586 587 // Final step, emit the lowered DAG as machine code. 588 CodeGenAndEmitDAG(); 589} 590 591void SelectionDAGISel::ComputeLiveOutVRegInfo() { 592 SmallPtrSet<SDNode*, 128> VisitedNodes; 593 SmallVector<SDNode*, 128> Worklist; 594 595 Worklist.push_back(CurDAG->getRoot().getNode()); 596 597 APInt KnownZero; 598 APInt KnownOne; 599 600 do { 601 SDNode *N = Worklist.pop_back_val(); 602 603 // If we've already seen this node, ignore it. 604 if (!VisitedNodes.insert(N)) 605 continue; 606 607 // Otherwise, add all chain operands to the worklist. 608 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 609 if (N->getOperand(i).getValueType() == MVT::Other) 610 Worklist.push_back(N->getOperand(i).getNode()); 611 612 // If this is a CopyToReg with a vreg dest, process it. 613 if (N->getOpcode() != ISD::CopyToReg) 614 continue; 615 616 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 617 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 618 continue; 619 620 // Ignore non-scalar or non-integer values. 621 SDValue Src = N->getOperand(2); 622 EVT SrcVT = Src.getValueType(); 623 if (!SrcVT.isInteger() || SrcVT.isVector()) 624 continue; 625 626 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 627 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 628 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 629 } while (!Worklist.empty()); 630} 631 632void SelectionDAGISel::CodeGenAndEmitDAG() { 633 std::string GroupName; 634 if (TimePassesIsEnabled) 635 GroupName = "Instruction Selection and Scheduling"; 636 std::string BlockName; 637 int BlockNumber = -1; 638 (void)BlockNumber; 639#ifdef NDEBUG 640 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 641 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 642 ViewSUnitDAGs) 643#endif 644 { 645 BlockNumber = FuncInfo->MBB->getNumber(); 646 BlockName = MF->getName().str() + ":" + 647 FuncInfo->MBB->getBasicBlock()->getName().str(); 648 } 649 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 650 << " '" << BlockName << "'\n"; CurDAG->dump()); 651 652 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 653 654 // Run the DAG combiner in pre-legalize mode. 655 { 656 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 657 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 658 } 659 660 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 661 << " '" << BlockName << "'\n"; CurDAG->dump()); 662 663 // Second step, hack on the DAG until it only uses operations and types that 664 // the target supports. 665 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 666 BlockName); 667 668 bool Changed; 669 { 670 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 671 Changed = CurDAG->LegalizeTypes(); 672 } 673 674 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 675 << " '" << BlockName << "'\n"; CurDAG->dump()); 676 677 CurDAG->NewNodesMustHaveLegalTypes = true; 678 679 if (Changed) { 680 if (ViewDAGCombineLT) 681 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 682 683 // Run the DAG combiner in post-type-legalize mode. 684 { 685 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 686 TimePassesIsEnabled); 687 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 688 } 689 690 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 691 << " '" << BlockName << "'\n"; CurDAG->dump()); 692 693 } 694 695 { 696 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 697 Changed = CurDAG->LegalizeVectors(); 698 } 699 700 if (Changed) { 701 { 702 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 703 CurDAG->LegalizeTypes(); 704 } 705 706 if (ViewDAGCombineLT) 707 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 708 709 // Run the DAG combiner in post-type-legalize mode. 710 { 711 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 712 TimePassesIsEnabled); 713 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 714 } 715 716 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 717 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 718 } 719 720 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 721 722 { 723 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 724 CurDAG->Legalize(); 725 } 726 727 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 728 << " '" << BlockName << "'\n"; CurDAG->dump()); 729 730 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 731 732 // Run the DAG combiner in post-legalize mode. 733 { 734 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 735 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 736 } 737 738 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 739 << " '" << BlockName << "'\n"; CurDAG->dump()); 740 741 if (OptLevel != CodeGenOpt::None) 742 ComputeLiveOutVRegInfo(); 743 744 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 745 746 // Third, instruction select all of the operations to machine code, adding the 747 // code to the MachineBasicBlock. 748 { 749 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 750 DoInstructionSelection(); 751 } 752 753 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 754 << " '" << BlockName << "'\n"; CurDAG->dump()); 755 756 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 757 758 // Schedule machine code. 759 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 760 { 761 NamedRegionTimer T("Instruction Scheduling", GroupName, 762 TimePassesIsEnabled); 763 Scheduler->Run(CurDAG, FuncInfo->MBB); 764 } 765 766 if (ViewSUnitDAGs) Scheduler->viewGraph(); 767 768 // Emit machine code to BB. This can change 'BB' to the last block being 769 // inserted into. 770 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 771 { 772 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 773 774 // FuncInfo->InsertPt is passed by reference and set to the end of the 775 // scheduled instructions. 776 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 777 } 778 779 // If the block was split, make sure we update any references that are used to 780 // update PHI nodes later on. 781 if (FirstMBB != LastMBB) 782 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 783 784 // Free the scheduler state. 785 { 786 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 787 TimePassesIsEnabled); 788 delete Scheduler; 789 } 790 791 // Free the SelectionDAG state, now that we're finished with it. 792 CurDAG->clear(); 793} 794 795namespace { 796/// ISelUpdater - helper class to handle updates of the instruction selection 797/// graph. 798class ISelUpdater : public SelectionDAG::DAGUpdateListener { 799 SelectionDAG::allnodes_iterator &ISelPosition; 800public: 801 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 802 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 803 804 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 805 /// deleted is the current ISelPosition node, update ISelPosition. 806 /// 807 void NodeDeleted(SDNode *N, SDNode *E) override { 808 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 809 ++ISelPosition; 810 } 811}; 812} // end anonymous namespace 813 814void SelectionDAGISel::DoInstructionSelection() { 815 DEBUG(dbgs() << "===== Instruction selection begins: BB#" 816 << FuncInfo->MBB->getNumber() 817 << " '" << FuncInfo->MBB->getName() << "'\n"); 818 819 PreprocessISelDAG(); 820 821 // Select target instructions for the DAG. 822 { 823 // Number all nodes with a topological order and set DAGSize. 824 DAGSize = CurDAG->AssignTopologicalOrder(); 825 826 // Create a dummy node (which is not added to allnodes), that adds 827 // a reference to the root node, preventing it from being deleted, 828 // and tracking any changes of the root. 829 HandleSDNode Dummy(CurDAG->getRoot()); 830 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 831 ++ISelPosition; 832 833 // Make sure that ISelPosition gets properly updated when nodes are deleted 834 // in calls made from this function. 835 ISelUpdater ISU(*CurDAG, ISelPosition); 836 837 // The AllNodes list is now topological-sorted. Visit the 838 // nodes by starting at the end of the list (the root of the 839 // graph) and preceding back toward the beginning (the entry 840 // node). 841 while (ISelPosition != CurDAG->allnodes_begin()) { 842 SDNode *Node = --ISelPosition; 843 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 844 // but there are currently some corner cases that it misses. Also, this 845 // makes it theoretically possible to disable the DAGCombiner. 846 if (Node->use_empty()) 847 continue; 848 849 SDNode *ResNode = Select(Node); 850 851 // FIXME: This is pretty gross. 'Select' should be changed to not return 852 // anything at all and this code should be nuked with a tactical strike. 853 854 // If node should not be replaced, continue with the next one. 855 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 856 continue; 857 // Replace node. 858 if (ResNode) { 859 ReplaceUses(Node, ResNode); 860 } 861 862 // If after the replacement this node is not used any more, 863 // remove this dead node. 864 if (Node->use_empty()) // Don't delete EntryToken, etc. 865 CurDAG->RemoveDeadNode(Node); 866 } 867 868 CurDAG->setRoot(Dummy.getValue()); 869 } 870 871 DEBUG(dbgs() << "===== Instruction selection ends:\n"); 872 873 PostprocessISelDAG(); 874} 875 876/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 877/// do other setup for EH landing-pad blocks. 878void SelectionDAGISel::PrepareEHLandingPad() { 879 MachineBasicBlock *MBB = FuncInfo->MBB; 880 881 // Add a label to mark the beginning of the landing pad. Deletion of the 882 // landing pad can thus be detected via the MachineModuleInfo. 883 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 884 885 // Assign the call site to the landing pad's begin label. 886 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 887 888 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 889 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 890 .addSym(Label); 891 892 // Mark exception register as live in. 893 const TargetLowering *TLI = getTargetLowering(); 894 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy()); 895 if (unsigned Reg = TLI->getExceptionPointerRegister()) 896 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC); 897 898 // Mark exception selector register as live in. 899 if (unsigned Reg = TLI->getExceptionSelectorRegister()) 900 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC); 901} 902 903/// isFoldedOrDeadInstruction - Return true if the specified instruction is 904/// side-effect free and is either dead or folded into a generated instruction. 905/// Return false if it needs to be emitted. 906static bool isFoldedOrDeadInstruction(const Instruction *I, 907 FunctionLoweringInfo *FuncInfo) { 908 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 909 !isa<TerminatorInst>(I) && // Terminators aren't folded. 910 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 911 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 912 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 913} 914 915#ifndef NDEBUG 916// Collect per Instruction statistics for fast-isel misses. Only those 917// instructions that cause the bail are accounted for. It does not account for 918// instructions higher in the block. Thus, summing the per instructions stats 919// will not add up to what is reported by NumFastIselFailures. 920static void collectFailStats(const Instruction *I) { 921 switch (I->getOpcode()) { 922 default: assert (0 && "<Invalid operator> "); 923 924 // Terminators 925 case Instruction::Ret: NumFastIselFailRet++; return; 926 case Instruction::Br: NumFastIselFailBr++; return; 927 case Instruction::Switch: NumFastIselFailSwitch++; return; 928 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 929 case Instruction::Invoke: NumFastIselFailInvoke++; return; 930 case Instruction::Resume: NumFastIselFailResume++; return; 931 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 932 933 // Standard binary operators... 934 case Instruction::Add: NumFastIselFailAdd++; return; 935 case Instruction::FAdd: NumFastIselFailFAdd++; return; 936 case Instruction::Sub: NumFastIselFailSub++; return; 937 case Instruction::FSub: NumFastIselFailFSub++; return; 938 case Instruction::Mul: NumFastIselFailMul++; return; 939 case Instruction::FMul: NumFastIselFailFMul++; return; 940 case Instruction::UDiv: NumFastIselFailUDiv++; return; 941 case Instruction::SDiv: NumFastIselFailSDiv++; return; 942 case Instruction::FDiv: NumFastIselFailFDiv++; return; 943 case Instruction::URem: NumFastIselFailURem++; return; 944 case Instruction::SRem: NumFastIselFailSRem++; return; 945 case Instruction::FRem: NumFastIselFailFRem++; return; 946 947 // Logical operators... 948 case Instruction::And: NumFastIselFailAnd++; return; 949 case Instruction::Or: NumFastIselFailOr++; return; 950 case Instruction::Xor: NumFastIselFailXor++; return; 951 952 // Memory instructions... 953 case Instruction::Alloca: NumFastIselFailAlloca++; return; 954 case Instruction::Load: NumFastIselFailLoad++; return; 955 case Instruction::Store: NumFastIselFailStore++; return; 956 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 957 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 958 case Instruction::Fence: NumFastIselFailFence++; return; 959 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 960 961 // Convert instructions... 962 case Instruction::Trunc: NumFastIselFailTrunc++; return; 963 case Instruction::ZExt: NumFastIselFailZExt++; return; 964 case Instruction::SExt: NumFastIselFailSExt++; return; 965 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 966 case Instruction::FPExt: NumFastIselFailFPExt++; return; 967 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 968 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 969 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 970 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 971 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 972 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 973 case Instruction::BitCast: NumFastIselFailBitCast++; return; 974 975 // Other instructions... 976 case Instruction::ICmp: NumFastIselFailICmp++; return; 977 case Instruction::FCmp: NumFastIselFailFCmp++; return; 978 case Instruction::PHI: NumFastIselFailPHI++; return; 979 case Instruction::Select: NumFastIselFailSelect++; return; 980 case Instruction::Call: NumFastIselFailCall++; return; 981 case Instruction::Shl: NumFastIselFailShl++; return; 982 case Instruction::LShr: NumFastIselFailLShr++; return; 983 case Instruction::AShr: NumFastIselFailAShr++; return; 984 case Instruction::VAArg: NumFastIselFailVAArg++; return; 985 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 986 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 987 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 988 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 989 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 990 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 991 } 992} 993#endif 994 995void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 996 // Initialize the Fast-ISel state, if needed. 997 FastISel *FastIS = 0; 998 if (TM.Options.EnableFastISel) 999 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo); 1000 1001 // Iterate over all basic blocks in the function. 1002 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 1003 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 1004 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 1005 const BasicBlock *LLVMBB = *I; 1006 1007 if (OptLevel != CodeGenOpt::None) { 1008 bool AllPredsVisited = true; 1009 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 1010 PI != PE; ++PI) { 1011 if (!FuncInfo->VisitedBBs.count(*PI)) { 1012 AllPredsVisited = false; 1013 break; 1014 } 1015 } 1016 1017 if (AllPredsVisited) { 1018 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1019 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1020 FuncInfo->ComputePHILiveOutRegInfo(PN); 1021 } else { 1022 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1023 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1024 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 1025 } 1026 1027 FuncInfo->VisitedBBs.insert(LLVMBB); 1028 } 1029 1030 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 1031 BasicBlock::const_iterator const End = LLVMBB->end(); 1032 BasicBlock::const_iterator BI = End; 1033 1034 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 1035 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1036 1037 // Setup an EH landing-pad block. 1038 FuncInfo->ExceptionPointerVirtReg = 0; 1039 FuncInfo->ExceptionSelectorVirtReg = 0; 1040 if (FuncInfo->MBB->isLandingPad()) 1041 PrepareEHLandingPad(); 1042 1043 // Before doing SelectionDAG ISel, see if FastISel has been requested. 1044 if (FastIS) { 1045 FastIS->startNewBlock(); 1046 1047 // Emit code for any incoming arguments. This must happen before 1048 // beginning FastISel on the entry block. 1049 if (LLVMBB == &Fn.getEntryBlock()) { 1050 ++NumEntryBlocks; 1051 1052 // Lower any arguments needed in this block if this is the entry block. 1053 if (!FastIS->LowerArguments()) { 1054 // Fast isel failed to lower these arguments 1055 ++NumFastIselFailLowerArguments; 1056 if (EnableFastISelAbortArgs) 1057 llvm_unreachable("FastISel didn't lower all arguments"); 1058 1059 // Use SelectionDAG argument lowering 1060 LowerArguments(Fn); 1061 CurDAG->setRoot(SDB->getControlRoot()); 1062 SDB->clear(); 1063 CodeGenAndEmitDAG(); 1064 } 1065 1066 // If we inserted any instructions at the beginning, make a note of 1067 // where they are, so we can be sure to emit subsequent instructions 1068 // after them. 1069 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1070 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt)); 1071 else 1072 FastIS->setLastLocalValue(0); 1073 } 1074 1075 unsigned NumFastIselRemaining = std::distance(Begin, End); 1076 // Do FastISel on as many instructions as possible. 1077 for (; BI != Begin; --BI) { 1078 const Instruction *Inst = std::prev(BI); 1079 1080 // If we no longer require this instruction, skip it. 1081 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1082 --NumFastIselRemaining; 1083 continue; 1084 } 1085 1086 // Bottom-up: reset the insert pos at the top, after any local-value 1087 // instructions. 1088 FastIS->recomputeInsertPt(); 1089 1090 // Try to select the instruction with FastISel. 1091 if (FastIS->SelectInstruction(Inst)) { 1092 --NumFastIselRemaining; 1093 ++NumFastIselSuccess; 1094 // If fast isel succeeded, skip over all the folded instructions, and 1095 // then see if there is a load right before the selected instructions. 1096 // Try to fold the load if so. 1097 const Instruction *BeforeInst = Inst; 1098 while (BeforeInst != Begin) { 1099 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst)); 1100 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1101 break; 1102 } 1103 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1104 BeforeInst->hasOneUse() && 1105 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) { 1106 // If we succeeded, don't re-select the load. 1107 BI = std::next(BasicBlock::const_iterator(BeforeInst)); 1108 --NumFastIselRemaining; 1109 ++NumFastIselSuccess; 1110 } 1111 continue; 1112 } 1113 1114#ifndef NDEBUG 1115 if (EnableFastISelVerbose2) 1116 collectFailStats(Inst); 1117#endif 1118 1119 // Then handle certain instructions as single-LLVM-Instruction blocks. 1120 if (isa<CallInst>(Inst)) { 1121 1122 if (EnableFastISelVerbose || EnableFastISelAbort) { 1123 dbgs() << "FastISel missed call: "; 1124 Inst->dump(); 1125 } 1126 1127 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1128 unsigned &R = FuncInfo->ValueMap[Inst]; 1129 if (!R) 1130 R = FuncInfo->CreateRegs(Inst->getType()); 1131 } 1132 1133 bool HadTailCall = false; 1134 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1135 SelectBasicBlock(Inst, BI, HadTailCall); 1136 1137 // If the call was emitted as a tail call, we're done with the block. 1138 // We also need to delete any previously emitted instructions. 1139 if (HadTailCall) { 1140 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1141 --BI; 1142 break; 1143 } 1144 1145 // Recompute NumFastIselRemaining as Selection DAG instruction 1146 // selection may have handled the call, input args, etc. 1147 unsigned RemainingNow = std::distance(Begin, BI); 1148 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1149 NumFastIselRemaining = RemainingNow; 1150 continue; 1151 } 1152 1153 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1154 // Don't abort, and use a different message for terminator misses. 1155 NumFastIselFailures += NumFastIselRemaining; 1156 if (EnableFastISelVerbose || EnableFastISelAbort) { 1157 dbgs() << "FastISel missed terminator: "; 1158 Inst->dump(); 1159 } 1160 } else { 1161 NumFastIselFailures += NumFastIselRemaining; 1162 if (EnableFastISelVerbose || EnableFastISelAbort) { 1163 dbgs() << "FastISel miss: "; 1164 Inst->dump(); 1165 } 1166 if (EnableFastISelAbort) 1167 // The "fast" selector couldn't handle something and bailed. 1168 // For the purpose of debugging, just abort. 1169 llvm_unreachable("FastISel didn't select the entire block"); 1170 } 1171 break; 1172 } 1173 1174 FastIS->recomputeInsertPt(); 1175 } else { 1176 // Lower any arguments needed in this block if this is the entry block. 1177 if (LLVMBB == &Fn.getEntryBlock()) { 1178 ++NumEntryBlocks; 1179 LowerArguments(Fn); 1180 } 1181 } 1182 1183 if (Begin != BI) 1184 ++NumDAGBlocks; 1185 else 1186 ++NumFastIselBlocks; 1187 1188 if (Begin != BI) { 1189 // Run SelectionDAG instruction selection on the remainder of the block 1190 // not handled by FastISel. If FastISel is not run, this is the entire 1191 // block. 1192 bool HadTailCall; 1193 SelectBasicBlock(Begin, BI, HadTailCall); 1194 } 1195 1196 FinishBasicBlock(); 1197 FuncInfo->PHINodesToUpdate.clear(); 1198 } 1199 1200 delete FastIS; 1201 SDB->clearDanglingDebugInfo(); 1202 SDB->SPDescriptor.resetPerFunctionState(); 1203} 1204 1205/// Given that the input MI is before a partial terminator sequence TSeq, return 1206/// true if M + TSeq also a partial terminator sequence. 1207/// 1208/// A Terminator sequence is a sequence of MachineInstrs which at this point in 1209/// lowering copy vregs into physical registers, which are then passed into 1210/// terminator instructors so we can satisfy ABI constraints. A partial 1211/// terminator sequence is an improper subset of a terminator sequence (i.e. it 1212/// may be the whole terminator sequence). 1213static bool MIIsInTerminatorSequence(const MachineInstr *MI) { 1214 // If we do not have a copy or an implicit def, we return true if and only if 1215 // MI is a debug value. 1216 if (!MI->isCopy() && !MI->isImplicitDef()) 1217 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the 1218 // physical registers if there is debug info associated with the terminator 1219 // of our mbb. We want to include said debug info in our terminator 1220 // sequence, so we return true in that case. 1221 return MI->isDebugValue(); 1222 1223 // We have left the terminator sequence if we are not doing one of the 1224 // following: 1225 // 1226 // 1. Copying a vreg into a physical register. 1227 // 2. Copying a vreg into a vreg. 1228 // 3. Defining a register via an implicit def. 1229 1230 // OPI should always be a register definition... 1231 MachineInstr::const_mop_iterator OPI = MI->operands_begin(); 1232 if (!OPI->isReg() || !OPI->isDef()) 1233 return false; 1234 1235 // Defining any register via an implicit def is always ok. 1236 if (MI->isImplicitDef()) 1237 return true; 1238 1239 // Grab the copy source... 1240 MachineInstr::const_mop_iterator OPI2 = OPI; 1241 ++OPI2; 1242 assert(OPI2 != MI->operands_end() 1243 && "Should have a copy implying we should have 2 arguments."); 1244 1245 // Make sure that the copy dest is not a vreg when the copy source is a 1246 // physical register. 1247 if (!OPI2->isReg() || 1248 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) && 1249 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg()))) 1250 return false; 1251 1252 return true; 1253} 1254 1255/// Find the split point at which to splice the end of BB into its success stack 1256/// protector check machine basic block. 1257/// 1258/// On many platforms, due to ABI constraints, terminators, even before register 1259/// allocation, use physical registers. This creates an issue for us since 1260/// physical registers at this point can not travel across basic 1261/// blocks. Luckily, selectiondag always moves physical registers into vregs 1262/// when they enter functions and moves them through a sequence of copies back 1263/// into the physical registers right before the terminator creating a 1264/// ``Terminator Sequence''. This function is searching for the beginning of the 1265/// terminator sequence so that we can ensure that we splice off not just the 1266/// terminator, but additionally the copies that move the vregs into the 1267/// physical registers. 1268static MachineBasicBlock::iterator 1269FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) { 1270 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator(); 1271 // 1272 if (SplitPoint == BB->begin()) 1273 return SplitPoint; 1274 1275 MachineBasicBlock::iterator Start = BB->begin(); 1276 MachineBasicBlock::iterator Previous = SplitPoint; 1277 --Previous; 1278 1279 while (MIIsInTerminatorSequence(Previous)) { 1280 SplitPoint = Previous; 1281 if (Previous == Start) 1282 break; 1283 --Previous; 1284 } 1285 1286 return SplitPoint; 1287} 1288 1289void 1290SelectionDAGISel::FinishBasicBlock() { 1291 1292 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1293 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1294 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1295 dbgs() << "Node " << i << " : (" 1296 << FuncInfo->PHINodesToUpdate[i].first 1297 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1298 1299 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() && 1300 SDB->JTCases.empty() && 1301 SDB->BitTestCases.empty(); 1302 1303 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1304 // PHI nodes in successors. 1305 if (MustUpdatePHINodes) { 1306 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1307 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1308 assert(PHI->isPHI() && 1309 "This is not a machine PHI node that we are updating!"); 1310 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1311 continue; 1312 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1313 } 1314 } 1315 1316 // Handle stack protector. 1317 if (SDB->SPDescriptor.shouldEmitStackProtector()) { 1318 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB(); 1319 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB(); 1320 1321 // Find the split point to split the parent mbb. At the same time copy all 1322 // physical registers used in the tail of parent mbb into virtual registers 1323 // before the split point and back into physical registers after the split 1324 // point. This prevents us needing to deal with Live-ins and many other 1325 // register allocation issues caused by us splitting the parent mbb. The 1326 // register allocator will clean up said virtual copies later on. 1327 MachineBasicBlock::iterator SplitPoint = 1328 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc()); 1329 1330 // Splice the terminator of ParentMBB into SuccessMBB. 1331 SuccessMBB->splice(SuccessMBB->end(), ParentMBB, 1332 SplitPoint, 1333 ParentMBB->end()); 1334 1335 // Add compare/jump on neq/jump to the parent BB. 1336 FuncInfo->MBB = ParentMBB; 1337 FuncInfo->InsertPt = ParentMBB->end(); 1338 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB); 1339 CurDAG->setRoot(SDB->getRoot()); 1340 SDB->clear(); 1341 CodeGenAndEmitDAG(); 1342 1343 // CodeGen Failure MBB if we have not codegened it yet. 1344 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB(); 1345 if (!FailureMBB->size()) { 1346 FuncInfo->MBB = FailureMBB; 1347 FuncInfo->InsertPt = FailureMBB->end(); 1348 SDB->visitSPDescriptorFailure(SDB->SPDescriptor); 1349 CurDAG->setRoot(SDB->getRoot()); 1350 SDB->clear(); 1351 CodeGenAndEmitDAG(); 1352 } 1353 1354 // Clear the Per-BB State. 1355 SDB->SPDescriptor.resetPerBBState(); 1356 } 1357 1358 // If we updated PHI Nodes, return early. 1359 if (MustUpdatePHINodes) 1360 return; 1361 1362 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1363 // Lower header first, if it wasn't already lowered 1364 if (!SDB->BitTestCases[i].Emitted) { 1365 // Set the current basic block to the mbb we wish to insert the code into 1366 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1367 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1368 // Emit the code 1369 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1370 CurDAG->setRoot(SDB->getRoot()); 1371 SDB->clear(); 1372 CodeGenAndEmitDAG(); 1373 } 1374 1375 uint32_t UnhandledWeight = 0; 1376 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1377 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1378 1379 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1380 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1381 // Set the current basic block to the mbb we wish to insert the code into 1382 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1383 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1384 // Emit the code 1385 if (j+1 != ej) 1386 SDB->visitBitTestCase(SDB->BitTestCases[i], 1387 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1388 UnhandledWeight, 1389 SDB->BitTestCases[i].Reg, 1390 SDB->BitTestCases[i].Cases[j], 1391 FuncInfo->MBB); 1392 else 1393 SDB->visitBitTestCase(SDB->BitTestCases[i], 1394 SDB->BitTestCases[i].Default, 1395 UnhandledWeight, 1396 SDB->BitTestCases[i].Reg, 1397 SDB->BitTestCases[i].Cases[j], 1398 FuncInfo->MBB); 1399 1400 1401 CurDAG->setRoot(SDB->getRoot()); 1402 SDB->clear(); 1403 CodeGenAndEmitDAG(); 1404 } 1405 1406 // Update PHI Nodes 1407 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1408 pi != pe; ++pi) { 1409 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1410 MachineBasicBlock *PHIBB = PHI->getParent(); 1411 assert(PHI->isPHI() && 1412 "This is not a machine PHI node that we are updating!"); 1413 // This is "default" BB. We have two jumps to it. From "header" BB and 1414 // from last "case" BB. 1415 if (PHIBB == SDB->BitTestCases[i].Default) 1416 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1417 .addMBB(SDB->BitTestCases[i].Parent) 1418 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1419 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1420 // One of "cases" BB. 1421 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1422 j != ej; ++j) { 1423 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1424 if (cBB->isSuccessor(PHIBB)) 1425 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1426 } 1427 } 1428 } 1429 SDB->BitTestCases.clear(); 1430 1431 // If the JumpTable record is filled in, then we need to emit a jump table. 1432 // Updating the PHI nodes is tricky in this case, since we need to determine 1433 // whether the PHI is a successor of the range check MBB or the jump table MBB 1434 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1435 // Lower header first, if it wasn't already lowered 1436 if (!SDB->JTCases[i].first.Emitted) { 1437 // Set the current basic block to the mbb we wish to insert the code into 1438 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1439 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1440 // Emit the code 1441 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1442 FuncInfo->MBB); 1443 CurDAG->setRoot(SDB->getRoot()); 1444 SDB->clear(); 1445 CodeGenAndEmitDAG(); 1446 } 1447 1448 // Set the current basic block to the mbb we wish to insert the code into 1449 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1450 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1451 // Emit the code 1452 SDB->visitJumpTable(SDB->JTCases[i].second); 1453 CurDAG->setRoot(SDB->getRoot()); 1454 SDB->clear(); 1455 CodeGenAndEmitDAG(); 1456 1457 // Update PHI Nodes 1458 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1459 pi != pe; ++pi) { 1460 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1461 MachineBasicBlock *PHIBB = PHI->getParent(); 1462 assert(PHI->isPHI() && 1463 "This is not a machine PHI node that we are updating!"); 1464 // "default" BB. We can go there only from header BB. 1465 if (PHIBB == SDB->JTCases[i].second.Default) 1466 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1467 .addMBB(SDB->JTCases[i].first.HeaderBB); 1468 // JT BB. Just iterate over successors here 1469 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1470 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1471 } 1472 } 1473 SDB->JTCases.clear(); 1474 1475 // If the switch block involved a branch to one of the actual successors, we 1476 // need to update PHI nodes in that block. 1477 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1478 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1479 assert(PHI->isPHI() && 1480 "This is not a machine PHI node that we are updating!"); 1481 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 1482 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1483 } 1484 1485 // If we generated any switch lowering information, build and codegen any 1486 // additional DAGs necessary. 1487 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1488 // Set the current basic block to the mbb we wish to insert the code into 1489 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1490 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1491 1492 // Determine the unique successors. 1493 SmallVector<MachineBasicBlock *, 2> Succs; 1494 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1495 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1496 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1497 1498 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1499 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1500 CurDAG->setRoot(SDB->getRoot()); 1501 SDB->clear(); 1502 CodeGenAndEmitDAG(); 1503 1504 // Remember the last block, now that any splitting is done, for use in 1505 // populating PHI nodes in successors. 1506 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1507 1508 // Handle any PHI nodes in successors of this chunk, as if we were coming 1509 // from the original BB before switch expansion. Note that PHI nodes can 1510 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1511 // handle them the right number of times. 1512 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1513 FuncInfo->MBB = Succs[i]; 1514 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1515 // FuncInfo->MBB may have been removed from the CFG if a branch was 1516 // constant folded. 1517 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1518 for (MachineBasicBlock::iterator 1519 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1520 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1521 MachineInstrBuilder PHI(*MF, MBBI); 1522 // This value for this PHI node is recorded in PHINodesToUpdate. 1523 for (unsigned pn = 0; ; ++pn) { 1524 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1525 "Didn't find PHI entry!"); 1526 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1527 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1528 break; 1529 } 1530 } 1531 } 1532 } 1533 } 1534 } 1535 SDB->SwitchCases.clear(); 1536} 1537 1538 1539/// Create the scheduler. If a specific scheduler was specified 1540/// via the SchedulerRegistry, use it, otherwise select the 1541/// one preferred by the target. 1542/// 1543ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1544 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1545 1546 if (!Ctor) { 1547 Ctor = ISHeuristic; 1548 RegisterScheduler::setDefault(Ctor); 1549 } 1550 1551 return Ctor(this, OptLevel); 1552} 1553 1554//===----------------------------------------------------------------------===// 1555// Helper functions used by the generated instruction selector. 1556//===----------------------------------------------------------------------===// 1557// Calls to these methods are generated by tblgen. 1558 1559/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1560/// the dag combiner simplified the 255, we still want to match. RHS is the 1561/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1562/// specified in the .td file (e.g. 255). 1563bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1564 int64_t DesiredMaskS) const { 1565 const APInt &ActualMask = RHS->getAPIntValue(); 1566 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1567 1568 // If the actual mask exactly matches, success! 1569 if (ActualMask == DesiredMask) 1570 return true; 1571 1572 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1573 if (ActualMask.intersects(~DesiredMask)) 1574 return false; 1575 1576 // Otherwise, the DAG Combiner may have proven that the value coming in is 1577 // either already zero or is not demanded. Check for known zero input bits. 1578 APInt NeededMask = DesiredMask & ~ActualMask; 1579 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1580 return true; 1581 1582 // TODO: check to see if missing bits are just not demanded. 1583 1584 // Otherwise, this pattern doesn't match. 1585 return false; 1586} 1587 1588/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1589/// the dag combiner simplified the 255, we still want to match. RHS is the 1590/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1591/// specified in the .td file (e.g. 255). 1592bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1593 int64_t DesiredMaskS) const { 1594 const APInt &ActualMask = RHS->getAPIntValue(); 1595 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1596 1597 // If the actual mask exactly matches, success! 1598 if (ActualMask == DesiredMask) 1599 return true; 1600 1601 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1602 if (ActualMask.intersects(~DesiredMask)) 1603 return false; 1604 1605 // Otherwise, the DAG Combiner may have proven that the value coming in is 1606 // either already zero or is not demanded. Check for known zero input bits. 1607 APInt NeededMask = DesiredMask & ~ActualMask; 1608 1609 APInt KnownZero, KnownOne; 1610 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 1611 1612 // If all the missing bits in the or are already known to be set, match! 1613 if ((NeededMask & KnownOne) == NeededMask) 1614 return true; 1615 1616 // TODO: check to see if missing bits are just not demanded. 1617 1618 // Otherwise, this pattern doesn't match. 1619 return false; 1620} 1621 1622 1623/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1624/// by tblgen. Others should not call it. 1625void SelectionDAGISel:: 1626SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1627 std::vector<SDValue> InOps; 1628 std::swap(InOps, Ops); 1629 1630 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1631 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1632 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1633 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1634 1635 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1636 if (InOps[e-1].getValueType() == MVT::Glue) 1637 --e; // Don't process a glue operand if it is here. 1638 1639 while (i != e) { 1640 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1641 if (!InlineAsm::isMemKind(Flags)) { 1642 // Just skip over this operand, copying the operands verbatim. 1643 Ops.insert(Ops.end(), InOps.begin()+i, 1644 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1645 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1646 } else { 1647 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1648 "Memory operand with multiple values?"); 1649 // Otherwise, this is a memory operand. Ask the target to select it. 1650 std::vector<SDValue> SelOps; 1651 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1652 report_fatal_error("Could not match memory address. Inline asm" 1653 " failure!"); 1654 1655 // Add this to the output node. 1656 unsigned NewFlags = 1657 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1658 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1659 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1660 i += 2; 1661 } 1662 } 1663 1664 // Add the glue input back if present. 1665 if (e != InOps.size()) 1666 Ops.push_back(InOps.back()); 1667} 1668 1669/// findGlueUse - Return use of MVT::Glue value produced by the specified 1670/// SDNode. 1671/// 1672static SDNode *findGlueUse(SDNode *N) { 1673 unsigned FlagResNo = N->getNumValues()-1; 1674 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1675 SDUse &Use = I.getUse(); 1676 if (Use.getResNo() == FlagResNo) 1677 return Use.getUser(); 1678 } 1679 return NULL; 1680} 1681 1682/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1683/// This function recursively traverses up the operand chain, ignoring 1684/// certain nodes. 1685static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1686 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1687 bool IgnoreChains) { 1688 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1689 // greater than all of its (recursive) operands. If we scan to a point where 1690 // 'use' is smaller than the node we're scanning for, then we know we will 1691 // never find it. 1692 // 1693 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1694 // happen because we scan down to newly selected nodes in the case of glue 1695 // uses. 1696 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1697 return false; 1698 1699 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1700 // won't fail if we scan it again. 1701 if (!Visited.insert(Use)) 1702 return false; 1703 1704 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1705 // Ignore chain uses, they are validated by HandleMergeInputChains. 1706 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1707 continue; 1708 1709 SDNode *N = Use->getOperand(i).getNode(); 1710 if (N == Def) { 1711 if (Use == ImmedUse || Use == Root) 1712 continue; // We are not looking for immediate use. 1713 assert(N != Root); 1714 return true; 1715 } 1716 1717 // Traverse up the operand chain. 1718 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1719 return true; 1720 } 1721 return false; 1722} 1723 1724/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1725/// operand node N of U during instruction selection that starts at Root. 1726bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1727 SDNode *Root) const { 1728 if (OptLevel == CodeGenOpt::None) return false; 1729 return N.hasOneUse(); 1730} 1731 1732/// IsLegalToFold - Returns true if the specific operand node N of 1733/// U can be folded during instruction selection that starts at Root. 1734bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1735 CodeGenOpt::Level OptLevel, 1736 bool IgnoreChains) { 1737 if (OptLevel == CodeGenOpt::None) return false; 1738 1739 // If Root use can somehow reach N through a path that that doesn't contain 1740 // U then folding N would create a cycle. e.g. In the following 1741 // diagram, Root can reach N through X. If N is folded into into Root, then 1742 // X is both a predecessor and a successor of U. 1743 // 1744 // [N*] // 1745 // ^ ^ // 1746 // / \ // 1747 // [U*] [X]? // 1748 // ^ ^ // 1749 // \ / // 1750 // \ / // 1751 // [Root*] // 1752 // 1753 // * indicates nodes to be folded together. 1754 // 1755 // If Root produces glue, then it gets (even more) interesting. Since it 1756 // will be "glued" together with its glue use in the scheduler, we need to 1757 // check if it might reach N. 1758 // 1759 // [N*] // 1760 // ^ ^ // 1761 // / \ // 1762 // [U*] [X]? // 1763 // ^ ^ // 1764 // \ \ // 1765 // \ | // 1766 // [Root*] | // 1767 // ^ | // 1768 // f | // 1769 // | / // 1770 // [Y] / // 1771 // ^ / // 1772 // f / // 1773 // | / // 1774 // [GU] // 1775 // 1776 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1777 // (call it Fold), then X is a predecessor of GU and a successor of 1778 // Fold. But since Fold and GU are glued together, this will create 1779 // a cycle in the scheduling graph. 1780 1781 // If the node has glue, walk down the graph to the "lowest" node in the 1782 // glueged set. 1783 EVT VT = Root->getValueType(Root->getNumValues()-1); 1784 while (VT == MVT::Glue) { 1785 SDNode *GU = findGlueUse(Root); 1786 if (GU == NULL) 1787 break; 1788 Root = GU; 1789 VT = Root->getValueType(Root->getNumValues()-1); 1790 1791 // If our query node has a glue result with a use, we've walked up it. If 1792 // the user (which has already been selected) has a chain or indirectly uses 1793 // the chain, our WalkChainUsers predicate will not consider it. Because of 1794 // this, we cannot ignore chains in this predicate. 1795 IgnoreChains = false; 1796 } 1797 1798 1799 SmallPtrSet<SDNode*, 16> Visited; 1800 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1801} 1802 1803SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1804 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1805 SelectInlineAsmMemoryOperands(Ops); 1806 1807 EVT VTs[] = { MVT::Other, MVT::Glue }; 1808 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), 1809 VTs, &Ops[0], Ops.size()); 1810 New->setNodeId(-1); 1811 return New.getNode(); 1812} 1813 1814SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1815 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1816} 1817 1818/// GetVBR - decode a vbr encoding whose top bit is set. 1819LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1820GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1821 assert(Val >= 128 && "Not a VBR"); 1822 Val &= 127; // Remove first vbr bit. 1823 1824 unsigned Shift = 7; 1825 uint64_t NextBits; 1826 do { 1827 NextBits = MatcherTable[Idx++]; 1828 Val |= (NextBits&127) << Shift; 1829 Shift += 7; 1830 } while (NextBits & 128); 1831 1832 return Val; 1833} 1834 1835 1836/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1837/// interior glue and chain results to use the new glue and chain results. 1838void SelectionDAGISel:: 1839UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1840 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1841 SDValue InputGlue, 1842 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1843 bool isMorphNodeTo) { 1844 SmallVector<SDNode*, 4> NowDeadNodes; 1845 1846 // Now that all the normal results are replaced, we replace the chain and 1847 // glue results if present. 1848 if (!ChainNodesMatched.empty()) { 1849 assert(InputChain.getNode() != 0 && 1850 "Matched input chains but didn't produce a chain"); 1851 // Loop over all of the nodes we matched that produced a chain result. 1852 // Replace all the chain results with the final chain we ended up with. 1853 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1854 SDNode *ChainNode = ChainNodesMatched[i]; 1855 1856 // If this node was already deleted, don't look at it. 1857 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1858 continue; 1859 1860 // Don't replace the results of the root node if we're doing a 1861 // MorphNodeTo. 1862 if (ChainNode == NodeToMatch && isMorphNodeTo) 1863 continue; 1864 1865 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1866 if (ChainVal.getValueType() == MVT::Glue) 1867 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1868 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1869 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1870 1871 // If the node became dead and we haven't already seen it, delete it. 1872 if (ChainNode->use_empty() && 1873 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1874 NowDeadNodes.push_back(ChainNode); 1875 } 1876 } 1877 1878 // If the result produces glue, update any glue results in the matched 1879 // pattern with the glue result. 1880 if (InputGlue.getNode() != 0) { 1881 // Handle any interior nodes explicitly marked. 1882 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1883 SDNode *FRN = GlueResultNodesMatched[i]; 1884 1885 // If this node was already deleted, don't look at it. 1886 if (FRN->getOpcode() == ISD::DELETED_NODE) 1887 continue; 1888 1889 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1890 "Doesn't have a glue result"); 1891 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1892 InputGlue); 1893 1894 // If the node became dead and we haven't already seen it, delete it. 1895 if (FRN->use_empty() && 1896 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1897 NowDeadNodes.push_back(FRN); 1898 } 1899 } 1900 1901 if (!NowDeadNodes.empty()) 1902 CurDAG->RemoveDeadNodes(NowDeadNodes); 1903 1904 DEBUG(dbgs() << "ISEL: Match complete!\n"); 1905} 1906 1907enum ChainResult { 1908 CR_Simple, 1909 CR_InducesCycle, 1910 CR_LeadsToInteriorNode 1911}; 1912 1913/// WalkChainUsers - Walk down the users of the specified chained node that is 1914/// part of the pattern we're matching, looking at all of the users we find. 1915/// This determines whether something is an interior node, whether we have a 1916/// non-pattern node in between two pattern nodes (which prevent folding because 1917/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1918/// between pattern nodes (in which case the TF becomes part of the pattern). 1919/// 1920/// The walk we do here is guaranteed to be small because we quickly get down to 1921/// already selected nodes "below" us. 1922static ChainResult 1923WalkChainUsers(const SDNode *ChainedNode, 1924 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1925 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1926 ChainResult Result = CR_Simple; 1927 1928 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1929 E = ChainedNode->use_end(); UI != E; ++UI) { 1930 // Make sure the use is of the chain, not some other value we produce. 1931 if (UI.getUse().getValueType() != MVT::Other) continue; 1932 1933 SDNode *User = *UI; 1934 1935 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1936 continue; 1937 1938 // If we see an already-selected machine node, then we've gone beyond the 1939 // pattern that we're selecting down into the already selected chunk of the 1940 // DAG. 1941 unsigned UserOpcode = User->getOpcode(); 1942 if (User->isMachineOpcode() || 1943 UserOpcode == ISD::CopyToReg || 1944 UserOpcode == ISD::CopyFromReg || 1945 UserOpcode == ISD::INLINEASM || 1946 UserOpcode == ISD::EH_LABEL || 1947 UserOpcode == ISD::LIFETIME_START || 1948 UserOpcode == ISD::LIFETIME_END) { 1949 // If their node ID got reset to -1 then they've already been selected. 1950 // Treat them like a MachineOpcode. 1951 if (User->getNodeId() == -1) 1952 continue; 1953 } 1954 1955 // If we have a TokenFactor, we handle it specially. 1956 if (User->getOpcode() != ISD::TokenFactor) { 1957 // If the node isn't a token factor and isn't part of our pattern, then it 1958 // must be a random chained node in between two nodes we're selecting. 1959 // This happens when we have something like: 1960 // x = load ptr 1961 // call 1962 // y = x+4 1963 // store y -> ptr 1964 // Because we structurally match the load/store as a read/modify/write, 1965 // but the call is chained between them. We cannot fold in this case 1966 // because it would induce a cycle in the graph. 1967 if (!std::count(ChainedNodesInPattern.begin(), 1968 ChainedNodesInPattern.end(), User)) 1969 return CR_InducesCycle; 1970 1971 // Otherwise we found a node that is part of our pattern. For example in: 1972 // x = load ptr 1973 // y = x+4 1974 // store y -> ptr 1975 // This would happen when we're scanning down from the load and see the 1976 // store as a user. Record that there is a use of ChainedNode that is 1977 // part of the pattern and keep scanning uses. 1978 Result = CR_LeadsToInteriorNode; 1979 InteriorChainedNodes.push_back(User); 1980 continue; 1981 } 1982 1983 // If we found a TokenFactor, there are two cases to consider: first if the 1984 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1985 // uses of the TF are in our pattern) we just want to ignore it. Second, 1986 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1987 // [Load chain] 1988 // ^ 1989 // | 1990 // [Load] 1991 // ^ ^ 1992 // | \ DAG's like cheese 1993 // / \ do you? 1994 // / | 1995 // [TokenFactor] [Op] 1996 // ^ ^ 1997 // | | 1998 // \ / 1999 // \ / 2000 // [Store] 2001 // 2002 // In this case, the TokenFactor becomes part of our match and we rewrite it 2003 // as a new TokenFactor. 2004 // 2005 // To distinguish these two cases, do a recursive walk down the uses. 2006 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 2007 case CR_Simple: 2008 // If the uses of the TokenFactor are just already-selected nodes, ignore 2009 // it, it is "below" our pattern. 2010 continue; 2011 case CR_InducesCycle: 2012 // If the uses of the TokenFactor lead to nodes that are not part of our 2013 // pattern that are not selected, folding would turn this into a cycle, 2014 // bail out now. 2015 return CR_InducesCycle; 2016 case CR_LeadsToInteriorNode: 2017 break; // Otherwise, keep processing. 2018 } 2019 2020 // Okay, we know we're in the interesting interior case. The TokenFactor 2021 // is now going to be considered part of the pattern so that we rewrite its 2022 // uses (it may have uses that are not part of the pattern) with the 2023 // ultimate chain result of the generated code. We will also add its chain 2024 // inputs as inputs to the ultimate TokenFactor we create. 2025 Result = CR_LeadsToInteriorNode; 2026 ChainedNodesInPattern.push_back(User); 2027 InteriorChainedNodes.push_back(User); 2028 continue; 2029 } 2030 2031 return Result; 2032} 2033 2034/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 2035/// operation for when the pattern matched at least one node with a chains. The 2036/// input vector contains a list of all of the chained nodes that we match. We 2037/// must determine if this is a valid thing to cover (i.e. matching it won't 2038/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 2039/// be used as the input node chain for the generated nodes. 2040static SDValue 2041HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 2042 SelectionDAG *CurDAG) { 2043 // Walk all of the chained nodes we've matched, recursively scanning down the 2044 // users of the chain result. This adds any TokenFactor nodes that are caught 2045 // in between chained nodes to the chained and interior nodes list. 2046 SmallVector<SDNode*, 3> InteriorChainedNodes; 2047 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2048 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 2049 InteriorChainedNodes) == CR_InducesCycle) 2050 return SDValue(); // Would induce a cycle. 2051 } 2052 2053 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 2054 // that we are interested in. Form our input TokenFactor node. 2055 SmallVector<SDValue, 3> InputChains; 2056 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2057 // Add the input chain of this node to the InputChains list (which will be 2058 // the operands of the generated TokenFactor) if it's not an interior node. 2059 SDNode *N = ChainNodesMatched[i]; 2060 if (N->getOpcode() != ISD::TokenFactor) { 2061 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 2062 continue; 2063 2064 // Otherwise, add the input chain. 2065 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 2066 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 2067 InputChains.push_back(InChain); 2068 continue; 2069 } 2070 2071 // If we have a token factor, we want to add all inputs of the token factor 2072 // that are not part of the pattern we're matching. 2073 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 2074 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 2075 N->getOperand(op).getNode())) 2076 InputChains.push_back(N->getOperand(op)); 2077 } 2078 } 2079 2080 if (InputChains.size() == 1) 2081 return InputChains[0]; 2082 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]), 2083 MVT::Other, &InputChains[0], InputChains.size()); 2084} 2085 2086/// MorphNode - Handle morphing a node in place for the selector. 2087SDNode *SelectionDAGISel:: 2088MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 2089 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 2090 // It is possible we're using MorphNodeTo to replace a node with no 2091 // normal results with one that has a normal result (or we could be 2092 // adding a chain) and the input could have glue and chains as well. 2093 // In this case we need to shift the operands down. 2094 // FIXME: This is a horrible hack and broken in obscure cases, no worse 2095 // than the old isel though. 2096 int OldGlueResultNo = -1, OldChainResultNo = -1; 2097 2098 unsigned NTMNumResults = Node->getNumValues(); 2099 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 2100 OldGlueResultNo = NTMNumResults-1; 2101 if (NTMNumResults != 1 && 2102 Node->getValueType(NTMNumResults-2) == MVT::Other) 2103 OldChainResultNo = NTMNumResults-2; 2104 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 2105 OldChainResultNo = NTMNumResults-1; 2106 2107 // Call the underlying SelectionDAG routine to do the transmogrification. Note 2108 // that this deletes operands of the old node that become dead. 2109 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 2110 2111 // MorphNodeTo can operate in two ways: if an existing node with the 2112 // specified operands exists, it can just return it. Otherwise, it 2113 // updates the node in place to have the requested operands. 2114 if (Res == Node) { 2115 // If we updated the node in place, reset the node ID. To the isel, 2116 // this should be just like a newly allocated machine node. 2117 Res->setNodeId(-1); 2118 } 2119 2120 unsigned ResNumResults = Res->getNumValues(); 2121 // Move the glue if needed. 2122 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 2123 (unsigned)OldGlueResultNo != ResNumResults-1) 2124 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 2125 SDValue(Res, ResNumResults-1)); 2126 2127 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 2128 --ResNumResults; 2129 2130 // Move the chain reference if needed. 2131 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 2132 (unsigned)OldChainResultNo != ResNumResults-1) 2133 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 2134 SDValue(Res, ResNumResults-1)); 2135 2136 // Otherwise, no replacement happened because the node already exists. Replace 2137 // Uses of the old node with the new one. 2138 if (Res != Node) 2139 CurDAG->ReplaceAllUsesWith(Node, Res); 2140 2141 return Res; 2142} 2143 2144/// CheckSame - Implements OP_CheckSame. 2145LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2146CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2147 SDValue N, 2148 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2149 // Accept if it is exactly the same as a previously recorded node. 2150 unsigned RecNo = MatcherTable[MatcherIndex++]; 2151 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2152 return N == RecordedNodes[RecNo].first; 2153} 2154 2155/// CheckChildSame - Implements OP_CheckChildXSame. 2156LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2157CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2158 SDValue N, 2159 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes, 2160 unsigned ChildNo) { 2161 if (ChildNo >= N.getNumOperands()) 2162 return false; // Match fails if out of range child #. 2163 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo), 2164 RecordedNodes); 2165} 2166 2167/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2168LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2169CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2170 const SelectionDAGISel &SDISel) { 2171 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 2172} 2173 2174/// CheckNodePredicate - Implements OP_CheckNodePredicate. 2175LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2176CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2177 const SelectionDAGISel &SDISel, SDNode *N) { 2178 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2179} 2180 2181LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2182CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2183 SDNode *N) { 2184 uint16_t Opc = MatcherTable[MatcherIndex++]; 2185 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2186 return N->getOpcode() == Opc; 2187} 2188 2189LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2190CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2191 SDValue N, const TargetLowering *TLI) { 2192 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2193 if (N.getValueType() == VT) return true; 2194 2195 // Handle the case when VT is iPTR. 2196 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(); 2197} 2198 2199LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2200CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2201 SDValue N, const TargetLowering *TLI, unsigned ChildNo) { 2202 if (ChildNo >= N.getNumOperands()) 2203 return false; // Match fails if out of range child #. 2204 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2205} 2206 2207LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2208CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2209 SDValue N) { 2210 return cast<CondCodeSDNode>(N)->get() == 2211 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2212} 2213 2214LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2215CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2216 SDValue N, const TargetLowering *TLI) { 2217 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2218 if (cast<VTSDNode>(N)->getVT() == VT) 2219 return true; 2220 2221 // Handle the case when VT is iPTR. 2222 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(); 2223} 2224 2225LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2226CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2227 SDValue N) { 2228 int64_t Val = MatcherTable[MatcherIndex++]; 2229 if (Val & 128) 2230 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2231 2232 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2233 return C != 0 && C->getSExtValue() == Val; 2234} 2235 2236LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2237CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2238 SDValue N, unsigned ChildNo) { 2239 if (ChildNo >= N.getNumOperands()) 2240 return false; // Match fails if out of range child #. 2241 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo)); 2242} 2243 2244LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2245CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2246 SDValue N, const SelectionDAGISel &SDISel) { 2247 int64_t Val = MatcherTable[MatcherIndex++]; 2248 if (Val & 128) 2249 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2250 2251 if (N->getOpcode() != ISD::AND) return false; 2252 2253 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2254 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2255} 2256 2257LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2258CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2259 SDValue N, const SelectionDAGISel &SDISel) { 2260 int64_t Val = MatcherTable[MatcherIndex++]; 2261 if (Val & 128) 2262 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2263 2264 if (N->getOpcode() != ISD::OR) return false; 2265 2266 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2267 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2268} 2269 2270/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2271/// scope, evaluate the current node. If the current predicate is known to 2272/// fail, set Result=true and return anything. If the current predicate is 2273/// known to pass, set Result=false and return the MatcherIndex to continue 2274/// with. If the current predicate is unknown, set Result=false and return the 2275/// MatcherIndex to continue with. 2276static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2277 unsigned Index, SDValue N, 2278 bool &Result, 2279 const SelectionDAGISel &SDISel, 2280 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2281 switch (Table[Index++]) { 2282 default: 2283 Result = false; 2284 return Index-1; // Could not evaluate this predicate. 2285 case SelectionDAGISel::OPC_CheckSame: 2286 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2287 return Index; 2288 case SelectionDAGISel::OPC_CheckChild0Same: 2289 case SelectionDAGISel::OPC_CheckChild1Same: 2290 case SelectionDAGISel::OPC_CheckChild2Same: 2291 case SelectionDAGISel::OPC_CheckChild3Same: 2292 Result = !::CheckChildSame(Table, Index, N, RecordedNodes, 2293 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same); 2294 return Index; 2295 case SelectionDAGISel::OPC_CheckPatternPredicate: 2296 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2297 return Index; 2298 case SelectionDAGISel::OPC_CheckPredicate: 2299 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2300 return Index; 2301 case SelectionDAGISel::OPC_CheckOpcode: 2302 Result = !::CheckOpcode(Table, Index, N.getNode()); 2303 return Index; 2304 case SelectionDAGISel::OPC_CheckType: 2305 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering()); 2306 return Index; 2307 case SelectionDAGISel::OPC_CheckChild0Type: 2308 case SelectionDAGISel::OPC_CheckChild1Type: 2309 case SelectionDAGISel::OPC_CheckChild2Type: 2310 case SelectionDAGISel::OPC_CheckChild3Type: 2311 case SelectionDAGISel::OPC_CheckChild4Type: 2312 case SelectionDAGISel::OPC_CheckChild5Type: 2313 case SelectionDAGISel::OPC_CheckChild6Type: 2314 case SelectionDAGISel::OPC_CheckChild7Type: 2315 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(), 2316 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2317 return Index; 2318 case SelectionDAGISel::OPC_CheckCondCode: 2319 Result = !::CheckCondCode(Table, Index, N); 2320 return Index; 2321 case SelectionDAGISel::OPC_CheckValueType: 2322 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering()); 2323 return Index; 2324 case SelectionDAGISel::OPC_CheckInteger: 2325 Result = !::CheckInteger(Table, Index, N); 2326 return Index; 2327 case SelectionDAGISel::OPC_CheckChild0Integer: 2328 case SelectionDAGISel::OPC_CheckChild1Integer: 2329 case SelectionDAGISel::OPC_CheckChild2Integer: 2330 case SelectionDAGISel::OPC_CheckChild3Integer: 2331 case SelectionDAGISel::OPC_CheckChild4Integer: 2332 Result = !::CheckChildInteger(Table, Index, N, 2333 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer); 2334 return Index; 2335 case SelectionDAGISel::OPC_CheckAndImm: 2336 Result = !::CheckAndImm(Table, Index, N, SDISel); 2337 return Index; 2338 case SelectionDAGISel::OPC_CheckOrImm: 2339 Result = !::CheckOrImm(Table, Index, N, SDISel); 2340 return Index; 2341 } 2342} 2343 2344namespace { 2345 2346struct MatchScope { 2347 /// FailIndex - If this match fails, this is the index to continue with. 2348 unsigned FailIndex; 2349 2350 /// NodeStack - The node stack when the scope was formed. 2351 SmallVector<SDValue, 4> NodeStack; 2352 2353 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2354 unsigned NumRecordedNodes; 2355 2356 /// NumMatchedMemRefs - The number of matched memref entries. 2357 unsigned NumMatchedMemRefs; 2358 2359 /// InputChain/InputGlue - The current chain/glue 2360 SDValue InputChain, InputGlue; 2361 2362 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2363 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2364}; 2365 2366} 2367 2368SDNode *SelectionDAGISel:: 2369SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2370 unsigned TableSize) { 2371 // FIXME: Should these even be selected? Handle these cases in the caller? 2372 switch (NodeToMatch->getOpcode()) { 2373 default: 2374 break; 2375 case ISD::EntryToken: // These nodes remain the same. 2376 case ISD::BasicBlock: 2377 case ISD::Register: 2378 case ISD::RegisterMask: 2379 //case ISD::VALUETYPE: 2380 //case ISD::CONDCODE: 2381 case ISD::HANDLENODE: 2382 case ISD::MDNODE_SDNODE: 2383 case ISD::TargetConstant: 2384 case ISD::TargetConstantFP: 2385 case ISD::TargetConstantPool: 2386 case ISD::TargetFrameIndex: 2387 case ISD::TargetExternalSymbol: 2388 case ISD::TargetBlockAddress: 2389 case ISD::TargetJumpTable: 2390 case ISD::TargetGlobalTLSAddress: 2391 case ISD::TargetGlobalAddress: 2392 case ISD::TokenFactor: 2393 case ISD::CopyFromReg: 2394 case ISD::CopyToReg: 2395 case ISD::EH_LABEL: 2396 case ISD::LIFETIME_START: 2397 case ISD::LIFETIME_END: 2398 NodeToMatch->setNodeId(-1); // Mark selected. 2399 return 0; 2400 case ISD::AssertSext: 2401 case ISD::AssertZext: 2402 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2403 NodeToMatch->getOperand(0)); 2404 return 0; 2405 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2406 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2407 } 2408 2409 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2410 2411 // Set up the node stack with NodeToMatch as the only node on the stack. 2412 SmallVector<SDValue, 8> NodeStack; 2413 SDValue N = SDValue(NodeToMatch, 0); 2414 NodeStack.push_back(N); 2415 2416 // MatchScopes - Scopes used when matching, if a match failure happens, this 2417 // indicates where to continue checking. 2418 SmallVector<MatchScope, 8> MatchScopes; 2419 2420 // RecordedNodes - This is the set of nodes that have been recorded by the 2421 // state machine. The second value is the parent of the node, or null if the 2422 // root is recorded. 2423 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2424 2425 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2426 // pattern. 2427 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2428 2429 // These are the current input chain and glue for use when generating nodes. 2430 // Various Emit operations change these. For example, emitting a copytoreg 2431 // uses and updates these. 2432 SDValue InputChain, InputGlue; 2433 2434 // ChainNodesMatched - If a pattern matches nodes that have input/output 2435 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2436 // which ones they are. The result is captured into this list so that we can 2437 // update the chain results when the pattern is complete. 2438 SmallVector<SDNode*, 3> ChainNodesMatched; 2439 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2440 2441 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: "; 2442 NodeToMatch->dump(CurDAG); 2443 dbgs() << '\n'); 2444 2445 // Determine where to start the interpreter. Normally we start at opcode #0, 2446 // but if the state machine starts with an OPC_SwitchOpcode, then we 2447 // accelerate the first lookup (which is guaranteed to be hot) with the 2448 // OpcodeOffset table. 2449 unsigned MatcherIndex = 0; 2450 2451 if (!OpcodeOffset.empty()) { 2452 // Already computed the OpcodeOffset table, just index into it. 2453 if (N.getOpcode() < OpcodeOffset.size()) 2454 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2455 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2456 2457 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2458 // Otherwise, the table isn't computed, but the state machine does start 2459 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2460 // is the first time we're selecting an instruction. 2461 unsigned Idx = 1; 2462 while (1) { 2463 // Get the size of this case. 2464 unsigned CaseSize = MatcherTable[Idx++]; 2465 if (CaseSize & 128) 2466 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2467 if (CaseSize == 0) break; 2468 2469 // Get the opcode, add the index to the table. 2470 uint16_t Opc = MatcherTable[Idx++]; 2471 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2472 if (Opc >= OpcodeOffset.size()) 2473 OpcodeOffset.resize((Opc+1)*2); 2474 OpcodeOffset[Opc] = Idx; 2475 Idx += CaseSize; 2476 } 2477 2478 // Okay, do the lookup for the first opcode. 2479 if (N.getOpcode() < OpcodeOffset.size()) 2480 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2481 } 2482 2483 while (1) { 2484 assert(MatcherIndex < TableSize && "Invalid index"); 2485#ifndef NDEBUG 2486 unsigned CurrentOpcodeIndex = MatcherIndex; 2487#endif 2488 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2489 switch (Opcode) { 2490 case OPC_Scope: { 2491 // Okay, the semantics of this operation are that we should push a scope 2492 // then evaluate the first child. However, pushing a scope only to have 2493 // the first check fail (which then pops it) is inefficient. If we can 2494 // determine immediately that the first check (or first several) will 2495 // immediately fail, don't even bother pushing a scope for them. 2496 unsigned FailIndex; 2497 2498 while (1) { 2499 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2500 if (NumToSkip & 128) 2501 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2502 // Found the end of the scope with no match. 2503 if (NumToSkip == 0) { 2504 FailIndex = 0; 2505 break; 2506 } 2507 2508 FailIndex = MatcherIndex+NumToSkip; 2509 2510 unsigned MatcherIndexOfPredicate = MatcherIndex; 2511 (void)MatcherIndexOfPredicate; // silence warning. 2512 2513 // If we can't evaluate this predicate without pushing a scope (e.g. if 2514 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2515 // push the scope and evaluate the full predicate chain. 2516 bool Result; 2517 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2518 Result, *this, RecordedNodes); 2519 if (!Result) 2520 break; 2521 2522 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at " 2523 << "index " << MatcherIndexOfPredicate 2524 << ", continuing at " << FailIndex << "\n"); 2525 ++NumDAGIselRetries; 2526 2527 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2528 // move to the next case. 2529 MatcherIndex = FailIndex; 2530 } 2531 2532 // If the whole scope failed to match, bail. 2533 if (FailIndex == 0) break; 2534 2535 // Push a MatchScope which indicates where to go if the first child fails 2536 // to match. 2537 MatchScope NewEntry; 2538 NewEntry.FailIndex = FailIndex; 2539 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2540 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2541 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2542 NewEntry.InputChain = InputChain; 2543 NewEntry.InputGlue = InputGlue; 2544 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2545 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2546 MatchScopes.push_back(NewEntry); 2547 continue; 2548 } 2549 case OPC_RecordNode: { 2550 // Remember this node, it may end up being an operand in the pattern. 2551 SDNode *Parent = 0; 2552 if (NodeStack.size() > 1) 2553 Parent = NodeStack[NodeStack.size()-2].getNode(); 2554 RecordedNodes.push_back(std::make_pair(N, Parent)); 2555 continue; 2556 } 2557 2558 case OPC_RecordChild0: case OPC_RecordChild1: 2559 case OPC_RecordChild2: case OPC_RecordChild3: 2560 case OPC_RecordChild4: case OPC_RecordChild5: 2561 case OPC_RecordChild6: case OPC_RecordChild7: { 2562 unsigned ChildNo = Opcode-OPC_RecordChild0; 2563 if (ChildNo >= N.getNumOperands()) 2564 break; // Match fails if out of range child #. 2565 2566 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2567 N.getNode())); 2568 continue; 2569 } 2570 case OPC_RecordMemRef: 2571 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2572 continue; 2573 2574 case OPC_CaptureGlueInput: 2575 // If the current node has an input glue, capture it in InputGlue. 2576 if (N->getNumOperands() != 0 && 2577 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2578 InputGlue = N->getOperand(N->getNumOperands()-1); 2579 continue; 2580 2581 case OPC_MoveChild: { 2582 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2583 if (ChildNo >= N.getNumOperands()) 2584 break; // Match fails if out of range child #. 2585 N = N.getOperand(ChildNo); 2586 NodeStack.push_back(N); 2587 continue; 2588 } 2589 2590 case OPC_MoveParent: 2591 // Pop the current node off the NodeStack. 2592 NodeStack.pop_back(); 2593 assert(!NodeStack.empty() && "Node stack imbalance!"); 2594 N = NodeStack.back(); 2595 continue; 2596 2597 case OPC_CheckSame: 2598 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2599 continue; 2600 2601 case OPC_CheckChild0Same: case OPC_CheckChild1Same: 2602 case OPC_CheckChild2Same: case OPC_CheckChild3Same: 2603 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes, 2604 Opcode-OPC_CheckChild0Same)) 2605 break; 2606 continue; 2607 2608 case OPC_CheckPatternPredicate: 2609 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2610 continue; 2611 case OPC_CheckPredicate: 2612 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2613 N.getNode())) 2614 break; 2615 continue; 2616 case OPC_CheckComplexPat: { 2617 unsigned CPNum = MatcherTable[MatcherIndex++]; 2618 unsigned RecNo = MatcherTable[MatcherIndex++]; 2619 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2620 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2621 RecordedNodes[RecNo].first, CPNum, 2622 RecordedNodes)) 2623 break; 2624 continue; 2625 } 2626 case OPC_CheckOpcode: 2627 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2628 continue; 2629 2630 case OPC_CheckType: 2631 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2632 break; 2633 continue; 2634 2635 case OPC_SwitchOpcode: { 2636 unsigned CurNodeOpcode = N.getOpcode(); 2637 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2638 unsigned CaseSize; 2639 while (1) { 2640 // Get the size of this case. 2641 CaseSize = MatcherTable[MatcherIndex++]; 2642 if (CaseSize & 128) 2643 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2644 if (CaseSize == 0) break; 2645 2646 uint16_t Opc = MatcherTable[MatcherIndex++]; 2647 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2648 2649 // If the opcode matches, then we will execute this case. 2650 if (CurNodeOpcode == Opc) 2651 break; 2652 2653 // Otherwise, skip over this case. 2654 MatcherIndex += CaseSize; 2655 } 2656 2657 // If no cases matched, bail out. 2658 if (CaseSize == 0) break; 2659 2660 // Otherwise, execute the case we found. 2661 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart 2662 << " to " << MatcherIndex << "\n"); 2663 continue; 2664 } 2665 2666 case OPC_SwitchType: { 2667 MVT CurNodeVT = N.getSimpleValueType(); 2668 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2669 unsigned CaseSize; 2670 while (1) { 2671 // Get the size of this case. 2672 CaseSize = MatcherTable[MatcherIndex++]; 2673 if (CaseSize & 128) 2674 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2675 if (CaseSize == 0) break; 2676 2677 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2678 if (CaseVT == MVT::iPTR) 2679 CaseVT = getTargetLowering()->getPointerTy(); 2680 2681 // If the VT matches, then we will execute this case. 2682 if (CurNodeVT == CaseVT) 2683 break; 2684 2685 // Otherwise, skip over this case. 2686 MatcherIndex += CaseSize; 2687 } 2688 2689 // If no cases matched, bail out. 2690 if (CaseSize == 0) break; 2691 2692 // Otherwise, execute the case we found. 2693 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2694 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2695 continue; 2696 } 2697 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2698 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2699 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2700 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2701 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(), 2702 Opcode-OPC_CheckChild0Type)) 2703 break; 2704 continue; 2705 case OPC_CheckCondCode: 2706 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2707 continue; 2708 case OPC_CheckValueType: 2709 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2710 break; 2711 continue; 2712 case OPC_CheckInteger: 2713 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2714 continue; 2715 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer: 2716 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer: 2717 case OPC_CheckChild4Integer: 2718 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N, 2719 Opcode-OPC_CheckChild0Integer)) break; 2720 continue; 2721 case OPC_CheckAndImm: 2722 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2723 continue; 2724 case OPC_CheckOrImm: 2725 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2726 continue; 2727 2728 case OPC_CheckFoldableChainNode: { 2729 assert(NodeStack.size() != 1 && "No parent node"); 2730 // Verify that all intermediate nodes between the root and this one have 2731 // a single use. 2732 bool HasMultipleUses = false; 2733 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2734 if (!NodeStack[i].hasOneUse()) { 2735 HasMultipleUses = true; 2736 break; 2737 } 2738 if (HasMultipleUses) break; 2739 2740 // Check to see that the target thinks this is profitable to fold and that 2741 // we can fold it without inducing cycles in the graph. 2742 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2743 NodeToMatch) || 2744 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2745 NodeToMatch, OptLevel, 2746 true/*We validate our own chains*/)) 2747 break; 2748 2749 continue; 2750 } 2751 case OPC_EmitInteger: { 2752 MVT::SimpleValueType VT = 2753 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2754 int64_t Val = MatcherTable[MatcherIndex++]; 2755 if (Val & 128) 2756 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2757 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2758 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2759 continue; 2760 } 2761 case OPC_EmitRegister: { 2762 MVT::SimpleValueType VT = 2763 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2764 unsigned RegNo = MatcherTable[MatcherIndex++]; 2765 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2766 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2767 continue; 2768 } 2769 case OPC_EmitRegister2: { 2770 // For targets w/ more than 256 register names, the register enum 2771 // values are stored in two bytes in the matcher table (just like 2772 // opcodes). 2773 MVT::SimpleValueType VT = 2774 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2775 unsigned RegNo = MatcherTable[MatcherIndex++]; 2776 RegNo |= MatcherTable[MatcherIndex++] << 8; 2777 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2778 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2779 continue; 2780 } 2781 2782 case OPC_EmitConvertToTarget: { 2783 // Convert from IMM/FPIMM to target version. 2784 unsigned RecNo = MatcherTable[MatcherIndex++]; 2785 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget"); 2786 SDValue Imm = RecordedNodes[RecNo].first; 2787 2788 if (Imm->getOpcode() == ISD::Constant) { 2789 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 2790 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true); 2791 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2792 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2793 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true); 2794 } 2795 2796 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2797 continue; 2798 } 2799 2800 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2801 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2802 // These are space-optimized forms of OPC_EmitMergeInputChains. 2803 assert(InputChain.getNode() == 0 && 2804 "EmitMergeInputChains should be the first chain producing node"); 2805 assert(ChainNodesMatched.empty() && 2806 "Should only have one EmitMergeInputChains per match"); 2807 2808 // Read all of the chained nodes. 2809 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2810 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains"); 2811 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2812 2813 // FIXME: What if other value results of the node have uses not matched 2814 // by this pattern? 2815 if (ChainNodesMatched.back() != NodeToMatch && 2816 !RecordedNodes[RecNo].first.hasOneUse()) { 2817 ChainNodesMatched.clear(); 2818 break; 2819 } 2820 2821 // Merge the input chains if they are not intra-pattern references. 2822 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2823 2824 if (InputChain.getNode() == 0) 2825 break; // Failed to merge. 2826 continue; 2827 } 2828 2829 case OPC_EmitMergeInputChains: { 2830 assert(InputChain.getNode() == 0 && 2831 "EmitMergeInputChains should be the first chain producing node"); 2832 // This node gets a list of nodes we matched in the input that have 2833 // chains. We want to token factor all of the input chains to these nodes 2834 // together. However, if any of the input chains is actually one of the 2835 // nodes matched in this pattern, then we have an intra-match reference. 2836 // Ignore these because the newly token factored chain should not refer to 2837 // the old nodes. 2838 unsigned NumChains = MatcherTable[MatcherIndex++]; 2839 assert(NumChains != 0 && "Can't TF zero chains"); 2840 2841 assert(ChainNodesMatched.empty() && 2842 "Should only have one EmitMergeInputChains per match"); 2843 2844 // Read all of the chained nodes. 2845 for (unsigned i = 0; i != NumChains; ++i) { 2846 unsigned RecNo = MatcherTable[MatcherIndex++]; 2847 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains"); 2848 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2849 2850 // FIXME: What if other value results of the node have uses not matched 2851 // by this pattern? 2852 if (ChainNodesMatched.back() != NodeToMatch && 2853 !RecordedNodes[RecNo].first.hasOneUse()) { 2854 ChainNodesMatched.clear(); 2855 break; 2856 } 2857 } 2858 2859 // If the inner loop broke out, the match fails. 2860 if (ChainNodesMatched.empty()) 2861 break; 2862 2863 // Merge the input chains if they are not intra-pattern references. 2864 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2865 2866 if (InputChain.getNode() == 0) 2867 break; // Failed to merge. 2868 2869 continue; 2870 } 2871 2872 case OPC_EmitCopyToReg: { 2873 unsigned RecNo = MatcherTable[MatcherIndex++]; 2874 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg"); 2875 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2876 2877 if (InputChain.getNode() == 0) 2878 InputChain = CurDAG->getEntryNode(); 2879 2880 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch), 2881 DestPhysReg, RecordedNodes[RecNo].first, 2882 InputGlue); 2883 2884 InputGlue = InputChain.getValue(1); 2885 continue; 2886 } 2887 2888 case OPC_EmitNodeXForm: { 2889 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2890 unsigned RecNo = MatcherTable[MatcherIndex++]; 2891 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm"); 2892 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2893 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2894 continue; 2895 } 2896 2897 case OPC_EmitNode: 2898 case OPC_MorphNodeTo: { 2899 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2900 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2901 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2902 // Get the result VT list. 2903 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2904 SmallVector<EVT, 4> VTs; 2905 for (unsigned i = 0; i != NumVTs; ++i) { 2906 MVT::SimpleValueType VT = 2907 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2908 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy; 2909 VTs.push_back(VT); 2910 } 2911 2912 if (EmitNodeInfo & OPFL_Chain) 2913 VTs.push_back(MVT::Other); 2914 if (EmitNodeInfo & OPFL_GlueOutput) 2915 VTs.push_back(MVT::Glue); 2916 2917 // This is hot code, so optimize the two most common cases of 1 and 2 2918 // results. 2919 SDVTList VTList; 2920 if (VTs.size() == 1) 2921 VTList = CurDAG->getVTList(VTs[0]); 2922 else if (VTs.size() == 2) 2923 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2924 else 2925 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2926 2927 // Get the operand list. 2928 unsigned NumOps = MatcherTable[MatcherIndex++]; 2929 SmallVector<SDValue, 8> Ops; 2930 for (unsigned i = 0; i != NumOps; ++i) { 2931 unsigned RecNo = MatcherTable[MatcherIndex++]; 2932 if (RecNo & 128) 2933 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2934 2935 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2936 Ops.push_back(RecordedNodes[RecNo].first); 2937 } 2938 2939 // If there are variadic operands to add, handle them now. 2940 if (EmitNodeInfo & OPFL_VariadicInfo) { 2941 // Determine the start index to copy from. 2942 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2943 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2944 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2945 "Invalid variadic node"); 2946 // Copy all of the variadic operands, not including a potential glue 2947 // input. 2948 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2949 i != e; ++i) { 2950 SDValue V = NodeToMatch->getOperand(i); 2951 if (V.getValueType() == MVT::Glue) break; 2952 Ops.push_back(V); 2953 } 2954 } 2955 2956 // If this has chain/glue inputs, add them. 2957 if (EmitNodeInfo & OPFL_Chain) 2958 Ops.push_back(InputChain); 2959 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2960 Ops.push_back(InputGlue); 2961 2962 // Create the node. 2963 SDNode *Res = 0; 2964 if (Opcode != OPC_MorphNodeTo) { 2965 // If this is a normal EmitNode command, just create the new node and 2966 // add the results to the RecordedNodes list. 2967 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch), 2968 VTList, Ops); 2969 2970 // Add all the non-glue/non-chain results to the RecordedNodes list. 2971 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2972 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2973 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2974 (SDNode*) 0)); 2975 } 2976 2977 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 2978 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2979 EmitNodeInfo); 2980 } else { 2981 // NodeToMatch was eliminated by CSE when the target changed the DAG. 2982 // We will visit the equivalent node later. 2983 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 2984 return 0; 2985 } 2986 2987 // If the node had chain/glue results, update our notion of the current 2988 // chain and glue. 2989 if (EmitNodeInfo & OPFL_GlueOutput) { 2990 InputGlue = SDValue(Res, VTs.size()-1); 2991 if (EmitNodeInfo & OPFL_Chain) 2992 InputChain = SDValue(Res, VTs.size()-2); 2993 } else if (EmitNodeInfo & OPFL_Chain) 2994 InputChain = SDValue(Res, VTs.size()-1); 2995 2996 // If the OPFL_MemRefs glue is set on this node, slap all of the 2997 // accumulated memrefs onto it. 2998 // 2999 // FIXME: This is vastly incorrect for patterns with multiple outputs 3000 // instructions that access memory and for ComplexPatterns that match 3001 // loads. 3002 if (EmitNodeInfo & OPFL_MemRefs) { 3003 // Only attach load or store memory operands if the generated 3004 // instruction may load or store. 3005 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 3006 bool mayLoad = MCID.mayLoad(); 3007 bool mayStore = MCID.mayStore(); 3008 3009 unsigned NumMemRefs = 0; 3010 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 3011 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 3012 if ((*I)->isLoad()) { 3013 if (mayLoad) 3014 ++NumMemRefs; 3015 } else if ((*I)->isStore()) { 3016 if (mayStore) 3017 ++NumMemRefs; 3018 } else { 3019 ++NumMemRefs; 3020 } 3021 } 3022 3023 MachineSDNode::mmo_iterator MemRefs = 3024 MF->allocateMemRefsArray(NumMemRefs); 3025 3026 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 3027 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 3028 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 3029 if ((*I)->isLoad()) { 3030 if (mayLoad) 3031 *MemRefsPos++ = *I; 3032 } else if ((*I)->isStore()) { 3033 if (mayStore) 3034 *MemRefsPos++ = *I; 3035 } else { 3036 *MemRefsPos++ = *I; 3037 } 3038 } 3039 3040 cast<MachineSDNode>(Res) 3041 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 3042 } 3043 3044 DEBUG(dbgs() << " " 3045 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 3046 << " node: "; Res->dump(CurDAG); dbgs() << "\n"); 3047 3048 // If this was a MorphNodeTo then we're completely done! 3049 if (Opcode == OPC_MorphNodeTo) { 3050 // Update chain and glue uses. 3051 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 3052 InputGlue, GlueResultNodesMatched, true); 3053 return Res; 3054 } 3055 3056 continue; 3057 } 3058 3059 case OPC_MarkGlueResults: { 3060 unsigned NumNodes = MatcherTable[MatcherIndex++]; 3061 3062 // Read and remember all the glue-result nodes. 3063 for (unsigned i = 0; i != NumNodes; ++i) { 3064 unsigned RecNo = MatcherTable[MatcherIndex++]; 3065 if (RecNo & 128) 3066 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 3067 3068 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults"); 3069 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 3070 } 3071 continue; 3072 } 3073 3074 case OPC_CompleteMatch: { 3075 // The match has been completed, and any new nodes (if any) have been 3076 // created. Patch up references to the matched dag to use the newly 3077 // created nodes. 3078 unsigned NumResults = MatcherTable[MatcherIndex++]; 3079 3080 for (unsigned i = 0; i != NumResults; ++i) { 3081 unsigned ResSlot = MatcherTable[MatcherIndex++]; 3082 if (ResSlot & 128) 3083 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 3084 3085 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch"); 3086 SDValue Res = RecordedNodes[ResSlot].first; 3087 3088 assert(i < NodeToMatch->getNumValues() && 3089 NodeToMatch->getValueType(i) != MVT::Other && 3090 NodeToMatch->getValueType(i) != MVT::Glue && 3091 "Invalid number of results to complete!"); 3092 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 3093 NodeToMatch->getValueType(i) == MVT::iPTR || 3094 Res.getValueType() == MVT::iPTR || 3095 NodeToMatch->getValueType(i).getSizeInBits() == 3096 Res.getValueType().getSizeInBits()) && 3097 "invalid replacement"); 3098 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 3099 } 3100 3101 // If the root node defines glue, add it to the glue nodes to update list. 3102 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 3103 GlueResultNodesMatched.push_back(NodeToMatch); 3104 3105 // Update chain and glue uses. 3106 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 3107 InputGlue, GlueResultNodesMatched, false); 3108 3109 assert(NodeToMatch->use_empty() && 3110 "Didn't replace all uses of the node?"); 3111 3112 // FIXME: We just return here, which interacts correctly with SelectRoot 3113 // above. We should fix this to not return an SDNode* anymore. 3114 return 0; 3115 } 3116 } 3117 3118 // If the code reached this point, then the match failed. See if there is 3119 // another child to try in the current 'Scope', otherwise pop it until we 3120 // find a case to check. 3121 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 3122 ++NumDAGIselRetries; 3123 while (1) { 3124 if (MatchScopes.empty()) { 3125 CannotYetSelect(NodeToMatch); 3126 return 0; 3127 } 3128 3129 // Restore the interpreter state back to the point where the scope was 3130 // formed. 3131 MatchScope &LastScope = MatchScopes.back(); 3132 RecordedNodes.resize(LastScope.NumRecordedNodes); 3133 NodeStack.clear(); 3134 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 3135 N = NodeStack.back(); 3136 3137 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 3138 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 3139 MatcherIndex = LastScope.FailIndex; 3140 3141 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); 3142 3143 InputChain = LastScope.InputChain; 3144 InputGlue = LastScope.InputGlue; 3145 if (!LastScope.HasChainNodesMatched) 3146 ChainNodesMatched.clear(); 3147 if (!LastScope.HasGlueResultNodesMatched) 3148 GlueResultNodesMatched.clear(); 3149 3150 // Check to see what the offset is at the new MatcherIndex. If it is zero 3151 // we have reached the end of this scope, otherwise we have another child 3152 // in the current scope to try. 3153 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 3154 if (NumToSkip & 128) 3155 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 3156 3157 // If we have another child in this scope to match, update FailIndex and 3158 // try it. 3159 if (NumToSkip != 0) { 3160 LastScope.FailIndex = MatcherIndex+NumToSkip; 3161 break; 3162 } 3163 3164 // End of this scope, pop it and try the next child in the containing 3165 // scope. 3166 MatchScopes.pop_back(); 3167 } 3168 } 3169} 3170 3171 3172 3173void SelectionDAGISel::CannotYetSelect(SDNode *N) { 3174 std::string msg; 3175 raw_string_ostream Msg(msg); 3176 Msg << "Cannot select: "; 3177 3178 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 3179 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 3180 N->getOpcode() != ISD::INTRINSIC_VOID) { 3181 N->printrFull(Msg, CurDAG); 3182 Msg << "\nIn function: " << MF->getName(); 3183 } else { 3184 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 3185 unsigned iid = 3186 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 3187 if (iid < Intrinsic::num_intrinsics) 3188 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 3189 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 3190 Msg << "target intrinsic %" << TII->getName(iid); 3191 else 3192 Msg << "unknown intrinsic #" << iid; 3193 } 3194 report_fatal_error(Msg.str()); 3195} 3196 3197char SelectionDAGISel::ID = 0; 3198