SelectionDAGISel.cpp revision 4477d691ed9fa63f051986dcb98e358054c8281f
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/CodeGen/FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/BranchProbabilityInfo.h" 21#include "llvm/Analysis/DebugInfo.h" 22#include "llvm/Constants.h" 23#include "llvm/Function.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/LLVMContext.h" 29#include "llvm/Module.h" 30#include "llvm/CodeGen/FastISel.h" 31#include "llvm/CodeGen/GCStrategy.h" 32#include "llvm/CodeGen/GCMetadata.h" 33#include "llvm/CodeGen/MachineFrameInfo.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineInstrBuilder.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 39#include "llvm/CodeGen/SchedulerRegistry.h" 40#include "llvm/CodeGen/SelectionDAG.h" 41#include "llvm/Target/TargetRegisterInfo.h" 42#include "llvm/Target/TargetIntrinsicInfo.h" 43#include "llvm/Target/TargetInstrInfo.h" 44#include "llvm/Target/TargetLowering.h" 45#include "llvm/Target/TargetMachine.h" 46#include "llvm/Target/TargetOptions.h" 47#include "llvm/Transforms/Utils/BasicBlockUtils.h" 48#include "llvm/Support/Compiler.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/ErrorHandling.h" 51#include "llvm/Support/Timer.h" 52#include "llvm/Support/raw_ostream.h" 53#include "llvm/ADT/PostOrderIterator.h" 54#include "llvm/ADT/Statistic.h" 55#include <algorithm> 56using namespace llvm; 57 58STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 59STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 60STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 61STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 62STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 63 64static cl::opt<bool> 65EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 66 cl::desc("Enable verbose messages in the \"fast\" " 67 "instruction selector")); 68static cl::opt<bool> 69EnableFastISelAbort("fast-isel-abort", cl::Hidden, 70 cl::desc("Enable abort calls when \"fast\" instruction fails")); 71 72static cl::opt<bool> 73UseMBPI("use-mbpi", 74 cl::desc("use Machine Branch Probability Info"), 75 cl::init(true), cl::Hidden); 76 77#ifndef NDEBUG 78static cl::opt<bool> 79ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 80 cl::desc("Pop up a window to show dags before the first " 81 "dag combine pass")); 82static cl::opt<bool> 83ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize types")); 85static cl::opt<bool> 86ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before legalize")); 88static cl::opt<bool> 89ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 90 cl::desc("Pop up a window to show dags before the second " 91 "dag combine pass")); 92static cl::opt<bool> 93ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 94 cl::desc("Pop up a window to show dags before the post legalize types" 95 " dag combine pass")); 96static cl::opt<bool> 97ViewISelDAGs("view-isel-dags", cl::Hidden, 98 cl::desc("Pop up a window to show isel dags as they are selected")); 99static cl::opt<bool> 100ViewSchedDAGs("view-sched-dags", cl::Hidden, 101 cl::desc("Pop up a window to show sched dags as they are processed")); 102static cl::opt<bool> 103ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 104 cl::desc("Pop up a window to show SUnit dags after they are processed")); 105#else 106static const bool ViewDAGCombine1 = false, 107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 108 ViewDAGCombine2 = false, 109 ViewDAGCombineLT = false, 110 ViewISelDAGs = false, ViewSchedDAGs = false, 111 ViewSUnitDAGs = false; 112#endif 113 114//===---------------------------------------------------------------------===// 115/// 116/// RegisterScheduler class - Track the registration of instruction schedulers. 117/// 118//===---------------------------------------------------------------------===// 119MachinePassRegistry RegisterScheduler::Registry; 120 121//===---------------------------------------------------------------------===// 122/// 123/// ISHeuristic command line option for instruction schedulers. 124/// 125//===---------------------------------------------------------------------===// 126static cl::opt<RegisterScheduler::FunctionPassCtor, false, 127 RegisterPassParser<RegisterScheduler> > 128ISHeuristic("pre-RA-sched", 129 cl::init(&createDefaultScheduler), 130 cl::desc("Instruction schedulers available (before register" 131 " allocation):")); 132 133static RegisterScheduler 134defaultListDAGScheduler("default", "Best scheduler for the target", 135 createDefaultScheduler); 136 137namespace llvm { 138 //===--------------------------------------------------------------------===// 139 /// createDefaultScheduler - This creates an instruction scheduler appropriate 140 /// for the target. 141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 142 CodeGenOpt::Level OptLevel) { 143 const TargetLowering &TLI = IS->getTargetLowering(); 144 145 if (OptLevel == CodeGenOpt::None) 146 return createSourceListDAGScheduler(IS, OptLevel); 147 if (TLI.getSchedulingPreference() == Sched::Latency) 148 return createTDListDAGScheduler(IS, OptLevel); 149 if (TLI.getSchedulingPreference() == Sched::RegPressure) 150 return createBURRListDAGScheduler(IS, OptLevel); 151 if (TLI.getSchedulingPreference() == Sched::Hybrid) 152 return createHybridListDAGScheduler(IS, OptLevel); 153 assert(TLI.getSchedulingPreference() == Sched::ILP && 154 "Unknown sched type!"); 155 return createILPListDAGScheduler(IS, OptLevel); 156 } 157} 158 159// EmitInstrWithCustomInserter - This method should be implemented by targets 160// that mark instructions with the 'usesCustomInserter' flag. These 161// instructions are special in various ways, which require special support to 162// insert. The specified MachineInstr is created but not inserted into any 163// basic blocks, and this method is called to expand it into a sequence of 164// instructions, potentially also creating new basic blocks and control flow. 165// When new basic blocks are inserted and the edges from MBB to its successors 166// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 167// DenseMap. 168MachineBasicBlock * 169TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 170 MachineBasicBlock *MBB) const { 171#ifndef NDEBUG 172 dbgs() << "If a target marks an instruction with " 173 "'usesCustomInserter', it must implement " 174 "TargetLowering::EmitInstrWithCustomInserter!"; 175#endif 176 llvm_unreachable(0); 177 return 0; 178} 179 180//===----------------------------------------------------------------------===// 181// SelectionDAGISel code 182//===----------------------------------------------------------------------===// 183 184SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, 185 CodeGenOpt::Level OL) : 186 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 187 FuncInfo(new FunctionLoweringInfo(TLI)), 188 CurDAG(new SelectionDAG(tm)), 189 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 190 GFI(), 191 OptLevel(OL), 192 DAGSize(0) { 193 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 194 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 195 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 196 } 197 198SelectionDAGISel::~SelectionDAGISel() { 199 delete SDB; 200 delete CurDAG; 201 delete FuncInfo; 202} 203 204void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 205 AU.addRequired<AliasAnalysis>(); 206 AU.addPreserved<AliasAnalysis>(); 207 AU.addRequired<GCModuleInfo>(); 208 AU.addPreserved<GCModuleInfo>(); 209 if (UseMBPI && OptLevel != CodeGenOpt::None) 210 AU.addRequired<BranchProbabilityInfo>(); 211 MachineFunctionPass::getAnalysisUsage(AU); 212} 213 214/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 215/// may trap on it. In this case we have to split the edge so that the path 216/// through the predecessor block that doesn't go to the phi block doesn't 217/// execute the possibly trapping instruction. 218/// 219/// This is required for correctness, so it must be done at -O0. 220/// 221static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 222 // Loop for blocks with phi nodes. 223 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 224 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 225 if (PN == 0) continue; 226 227 ReprocessBlock: 228 // For each block with a PHI node, check to see if any of the input values 229 // are potentially trapping constant expressions. Constant expressions are 230 // the only potentially trapping value that can occur as the argument to a 231 // PHI. 232 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 233 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 234 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 235 if (CE == 0 || !CE->canTrap()) continue; 236 237 // The only case we have to worry about is when the edge is critical. 238 // Since this block has a PHI Node, we assume it has multiple input 239 // edges: check to see if the pred has multiple successors. 240 BasicBlock *Pred = PN->getIncomingBlock(i); 241 if (Pred->getTerminator()->getNumSuccessors() == 1) 242 continue; 243 244 // Okay, we have to split this edge. 245 SplitCriticalEdge(Pred->getTerminator(), 246 GetSuccessorNumber(Pred, BB), SDISel, true); 247 goto ReprocessBlock; 248 } 249 } 250} 251 252bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 253 // Do some sanity-checking on the command-line options. 254 assert((!EnableFastISelVerbose || EnableFastISel) && 255 "-fast-isel-verbose requires -fast-isel"); 256 assert((!EnableFastISelAbort || EnableFastISel) && 257 "-fast-isel-abort requires -fast-isel"); 258 259 const Function &Fn = *mf.getFunction(); 260 const TargetInstrInfo &TII = *TM.getInstrInfo(); 261 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 262 263 MF = &mf; 264 RegInfo = &MF->getRegInfo(); 265 AA = &getAnalysis<AliasAnalysis>(); 266 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 267 268 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 269 270 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 271 272 CurDAG->init(*MF); 273 FuncInfo->set(Fn, *MF); 274 275 if (UseMBPI && OptLevel != CodeGenOpt::None) 276 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 277 else 278 FuncInfo->BPI = 0; 279 280 SDB->init(GFI, *AA); 281 282 SelectAllBasicBlocks(Fn); 283 284 // If the first basic block in the function has live ins that need to be 285 // copied into vregs, emit the copies into the top of the block before 286 // emitting the code for the block. 287 MachineBasicBlock *EntryMBB = MF->begin(); 288 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 289 290 DenseMap<unsigned, unsigned> LiveInMap; 291 if (!FuncInfo->ArgDbgValues.empty()) 292 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 293 E = RegInfo->livein_end(); LI != E; ++LI) 294 if (LI->second) 295 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 296 297 // Insert DBG_VALUE instructions for function arguments to the entry block. 298 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 299 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 300 unsigned Reg = MI->getOperand(0).getReg(); 301 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 302 EntryMBB->insert(EntryMBB->begin(), MI); 303 else { 304 MachineInstr *Def = RegInfo->getVRegDef(Reg); 305 MachineBasicBlock::iterator InsertPos = Def; 306 // FIXME: VR def may not be in entry block. 307 Def->getParent()->insert(llvm::next(InsertPos), MI); 308 } 309 310 // If Reg is live-in then update debug info to track its copy in a vreg. 311 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 312 if (LDI != LiveInMap.end()) { 313 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 314 MachineBasicBlock::iterator InsertPos = Def; 315 const MDNode *Variable = 316 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 317 unsigned Offset = MI->getOperand(1).getImm(); 318 // Def is never a terminator here, so it is ok to increment InsertPos. 319 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 320 TII.get(TargetOpcode::DBG_VALUE)) 321 .addReg(LDI->second, RegState::Debug) 322 .addImm(Offset).addMetadata(Variable); 323 324 // If this vreg is directly copied into an exported register then 325 // that COPY instructions also need DBG_VALUE, if it is the only 326 // user of LDI->second. 327 MachineInstr *CopyUseMI = NULL; 328 for (MachineRegisterInfo::use_iterator 329 UI = RegInfo->use_begin(LDI->second); 330 MachineInstr *UseMI = UI.skipInstruction();) { 331 if (UseMI->isDebugValue()) continue; 332 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 333 CopyUseMI = UseMI; continue; 334 } 335 // Otherwise this is another use or second copy use. 336 CopyUseMI = NULL; break; 337 } 338 if (CopyUseMI) { 339 MachineInstr *NewMI = 340 BuildMI(*MF, CopyUseMI->getDebugLoc(), 341 TII.get(TargetOpcode::DBG_VALUE)) 342 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 343 .addImm(Offset).addMetadata(Variable); 344 EntryMBB->insertAfter(CopyUseMI, NewMI); 345 } 346 } 347 } 348 349 // Determine if there are any calls in this machine function. 350 MachineFrameInfo *MFI = MF->getFrameInfo(); 351 if (!MFI->hasCalls()) { 352 for (MachineFunction::const_iterator 353 I = MF->begin(), E = MF->end(); I != E; ++I) { 354 const MachineBasicBlock *MBB = I; 355 for (MachineBasicBlock::const_iterator 356 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 357 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 358 359 if ((MCID.isCall() && !MCID.isReturn()) || 360 II->isStackAligningInlineAsm()) { 361 MFI->setHasCalls(true); 362 goto done; 363 } 364 } 365 } 366 done:; 367 } 368 369 // Determine if there is a call to setjmp in the machine function. 370 MF->setCallsSetJmp(Fn.callsFunctionThatReturnsTwice()); 371 372 // Replace forward-declared registers with the registers containing 373 // the desired value. 374 MachineRegisterInfo &MRI = MF->getRegInfo(); 375 for (DenseMap<unsigned, unsigned>::iterator 376 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 377 I != E; ++I) { 378 unsigned From = I->first; 379 unsigned To = I->second; 380 // If To is also scheduled to be replaced, find what its ultimate 381 // replacement is. 382 for (;;) { 383 DenseMap<unsigned, unsigned>::iterator J = 384 FuncInfo->RegFixups.find(To); 385 if (J == E) break; 386 To = J->second; 387 } 388 // Replace it. 389 MRI.replaceRegWith(From, To); 390 } 391 392 // Release function-specific state. SDB and CurDAG are already cleared 393 // at this point. 394 FuncInfo->clear(); 395 396 return true; 397} 398 399void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 400 BasicBlock::const_iterator End, 401 bool &HadTailCall) { 402 // Lower all of the non-terminator instructions. If a call is emitted 403 // as a tail call, cease emitting nodes for this block. Terminators 404 // are handled below. 405 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 406 SDB->visit(*I); 407 408 // Make sure the root of the DAG is up-to-date. 409 CurDAG->setRoot(SDB->getControlRoot()); 410 HadTailCall = SDB->HasTailCall; 411 SDB->clear(); 412 413 // Final step, emit the lowered DAG as machine code. 414 CodeGenAndEmitDAG(); 415} 416 417void SelectionDAGISel::ComputeLiveOutVRegInfo() { 418 SmallPtrSet<SDNode*, 128> VisitedNodes; 419 SmallVector<SDNode*, 128> Worklist; 420 421 Worklist.push_back(CurDAG->getRoot().getNode()); 422 423 APInt Mask; 424 APInt KnownZero; 425 APInt KnownOne; 426 427 do { 428 SDNode *N = Worklist.pop_back_val(); 429 430 // If we've already seen this node, ignore it. 431 if (!VisitedNodes.insert(N)) 432 continue; 433 434 // Otherwise, add all chain operands to the worklist. 435 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 436 if (N->getOperand(i).getValueType() == MVT::Other) 437 Worklist.push_back(N->getOperand(i).getNode()); 438 439 // If this is a CopyToReg with a vreg dest, process it. 440 if (N->getOpcode() != ISD::CopyToReg) 441 continue; 442 443 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 444 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 445 continue; 446 447 // Ignore non-scalar or non-integer values. 448 SDValue Src = N->getOperand(2); 449 EVT SrcVT = Src.getValueType(); 450 if (!SrcVT.isInteger() || SrcVT.isVector()) 451 continue; 452 453 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 454 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 455 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 456 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 457 } while (!Worklist.empty()); 458} 459 460void SelectionDAGISel::CodeGenAndEmitDAG() { 461 std::string GroupName; 462 if (TimePassesIsEnabled) 463 GroupName = "Instruction Selection and Scheduling"; 464 std::string BlockName; 465 int BlockNumber = -1; 466 (void)BlockNumber; 467#ifdef NDEBUG 468 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 469 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 470 ViewSUnitDAGs) 471#endif 472 { 473 BlockNumber = FuncInfo->MBB->getNumber(); 474 BlockName = MF->getFunction()->getNameStr() + ":" + 475 FuncInfo->MBB->getBasicBlock()->getNameStr(); 476 } 477 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 478 << " '" << BlockName << "'\n"; CurDAG->dump()); 479 480 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 481 482 // Run the DAG combiner in pre-legalize mode. 483 { 484 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 485 CurDAG->Combine(Unrestricted, *AA, OptLevel); 486 } 487 488 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 489 << " '" << BlockName << "'\n"; CurDAG->dump()); 490 491 // Second step, hack on the DAG until it only uses operations and types that 492 // the target supports. 493 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 494 BlockName); 495 496 bool Changed; 497 { 498 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 499 Changed = CurDAG->LegalizeTypes(); 500 } 501 502 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 503 << " '" << BlockName << "'\n"; CurDAG->dump()); 504 505 if (Changed) { 506 if (ViewDAGCombineLT) 507 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 508 509 // Run the DAG combiner in post-type-legalize mode. 510 { 511 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 512 TimePassesIsEnabled); 513 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 514 } 515 516 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 517 << " '" << BlockName << "'\n"; CurDAG->dump()); 518 } 519 520 { 521 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 522 Changed = CurDAG->LegalizeVectors(); 523 } 524 525 if (Changed) { 526 { 527 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 528 CurDAG->LegalizeTypes(); 529 } 530 531 if (ViewDAGCombineLT) 532 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 533 534 // Run the DAG combiner in post-type-legalize mode. 535 { 536 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 537 TimePassesIsEnabled); 538 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 539 } 540 541 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 542 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 543 } 544 545 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 546 547 { 548 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 549 CurDAG->Legalize(); 550 } 551 552 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 553 << " '" << BlockName << "'\n"; CurDAG->dump()); 554 555 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 556 557 // Run the DAG combiner in post-legalize mode. 558 { 559 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 560 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 561 } 562 563 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 564 << " '" << BlockName << "'\n"; CurDAG->dump()); 565 566 if (OptLevel != CodeGenOpt::None) 567 ComputeLiveOutVRegInfo(); 568 569 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 570 571 // Third, instruction select all of the operations to machine code, adding the 572 // code to the MachineBasicBlock. 573 { 574 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 575 DoInstructionSelection(); 576 } 577 578 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 579 << " '" << BlockName << "'\n"; CurDAG->dump()); 580 581 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 582 583 // Schedule machine code. 584 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 585 { 586 NamedRegionTimer T("Instruction Scheduling", GroupName, 587 TimePassesIsEnabled); 588 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt); 589 } 590 591 if (ViewSUnitDAGs) Scheduler->viewGraph(); 592 593 // Emit machine code to BB. This can change 'BB' to the last block being 594 // inserted into. 595 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 596 { 597 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 598 599 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(); 600 FuncInfo->InsertPt = Scheduler->InsertPos; 601 } 602 603 // If the block was split, make sure we update any references that are used to 604 // update PHI nodes later on. 605 if (FirstMBB != LastMBB) 606 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 607 608 // Free the scheduler state. 609 { 610 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 611 TimePassesIsEnabled); 612 delete Scheduler; 613 } 614 615 // Free the SelectionDAG state, now that we're finished with it. 616 CurDAG->clear(); 617} 618 619void SelectionDAGISel::DoInstructionSelection() { 620 DEBUG(errs() << "===== Instruction selection begins: BB#" 621 << FuncInfo->MBB->getNumber() 622 << " '" << FuncInfo->MBB->getName() << "'\n"); 623 624 PreprocessISelDAG(); 625 626 // Select target instructions for the DAG. 627 { 628 // Number all nodes with a topological order and set DAGSize. 629 DAGSize = CurDAG->AssignTopologicalOrder(); 630 631 // Create a dummy node (which is not added to allnodes), that adds 632 // a reference to the root node, preventing it from being deleted, 633 // and tracking any changes of the root. 634 HandleSDNode Dummy(CurDAG->getRoot()); 635 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 636 ++ISelPosition; 637 638 // The AllNodes list is now topological-sorted. Visit the 639 // nodes by starting at the end of the list (the root of the 640 // graph) and preceding back toward the beginning (the entry 641 // node). 642 while (ISelPosition != CurDAG->allnodes_begin()) { 643 SDNode *Node = --ISelPosition; 644 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 645 // but there are currently some corner cases that it misses. Also, this 646 // makes it theoretically possible to disable the DAGCombiner. 647 if (Node->use_empty()) 648 continue; 649 650 SDNode *ResNode = Select(Node); 651 652 // FIXME: This is pretty gross. 'Select' should be changed to not return 653 // anything at all and this code should be nuked with a tactical strike. 654 655 // If node should not be replaced, continue with the next one. 656 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 657 continue; 658 // Replace node. 659 if (ResNode) 660 ReplaceUses(Node, ResNode); 661 662 // If after the replacement this node is not used any more, 663 // remove this dead node. 664 if (Node->use_empty()) { // Don't delete EntryToken, etc. 665 ISelUpdater ISU(ISelPosition); 666 CurDAG->RemoveDeadNode(Node, &ISU); 667 } 668 } 669 670 CurDAG->setRoot(Dummy.getValue()); 671 } 672 673 DEBUG(errs() << "===== Instruction selection ends:\n"); 674 675 PostprocessISelDAG(); 676} 677 678/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 679/// do other setup for EH landing-pad blocks. 680void SelectionDAGISel::PrepareEHLandingPad() { 681 // Add a label to mark the beginning of the landing pad. Deletion of the 682 // landing pad can thus be detected via the MachineModuleInfo. 683 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB); 684 685 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 686 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 687 .addSym(Label); 688 689 // Mark exception register as live in. 690 unsigned Reg = TLI.getExceptionAddressRegister(); 691 if (Reg) FuncInfo->MBB->addLiveIn(Reg); 692 693 // Mark exception selector register as live in. 694 Reg = TLI.getExceptionSelectorRegister(); 695 if (Reg) FuncInfo->MBB->addLiveIn(Reg); 696 697 // FIXME: Hack around an exception handling flaw (PR1508): the personality 698 // function and list of typeids logically belong to the invoke (or, if you 699 // like, the basic block containing the invoke), and need to be associated 700 // with it in the dwarf exception handling tables. Currently however the 701 // information is provided by an intrinsic (eh.selector) that can be moved 702 // to unexpected places by the optimizers: if the unwind edge is critical, 703 // then breaking it can result in the intrinsics being in the successor of 704 // the landing pad, not the landing pad itself. This results 705 // in exceptions not being caught because no typeids are associated with 706 // the invoke. This may not be the only way things can go wrong, but it 707 // is the only way we try to work around for the moment. 708 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock(); 709 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 710 711 if (Br && Br->isUnconditional()) { // Critical edge? 712 BasicBlock::const_iterator I, E; 713 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 714 if (isa<EHSelectorInst>(I)) 715 break; 716 717 if (I == E) 718 // No catch info found - try to extract some from the successor. 719 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 720 } 721} 722 723 724 725/// TryToFoldFastISelLoad - We're checking to see if we can fold the specified 726/// load into the specified FoldInst. Note that we could have a sequence where 727/// multiple LLVM IR instructions are folded into the same machineinstr. For 728/// example we could have: 729/// A: x = load i32 *P 730/// B: y = icmp A, 42 731/// C: br y, ... 732/// 733/// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and 734/// any other folded instructions) because it is between A and C. 735/// 736/// If we succeed in folding the load into the operation, return true. 737/// 738bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI, 739 const Instruction *FoldInst, 740 FastISel *FastIS) { 741 // We know that the load has a single use, but don't know what it is. If it 742 // isn't one of the folded instructions, then we can't succeed here. Handle 743 // this by scanning the single-use users of the load until we get to FoldInst. 744 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs. 745 746 const Instruction *TheUser = LI->use_back(); 747 while (TheUser != FoldInst && // Scan up until we find FoldInst. 748 // Stay in the right block. 749 TheUser->getParent() == FoldInst->getParent() && 750 --MaxUsers) { // Don't scan too far. 751 // If there are multiple or no uses of this instruction, then bail out. 752 if (!TheUser->hasOneUse()) 753 return false; 754 755 TheUser = TheUser->use_back(); 756 } 757 758 // If we didn't find the fold instruction, then we failed to collapse the 759 // sequence. 760 if (TheUser != FoldInst) 761 return false; 762 763 // Don't try to fold volatile loads. Target has to deal with alignment 764 // constraints. 765 if (LI->isVolatile()) return false; 766 767 // Figure out which vreg this is going into. If there is no assigned vreg yet 768 // then there actually was no reference to it. Perhaps the load is referenced 769 // by a dead instruction. 770 unsigned LoadReg = FastIS->getRegForValue(LI); 771 if (LoadReg == 0) 772 return false; 773 774 // Check to see what the uses of this vreg are. If it has no uses, or more 775 // than one use (at the machine instr level) then we can't fold it. 776 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg); 777 if (RI == RegInfo->reg_end()) 778 return false; 779 780 // See if there is exactly one use of the vreg. If there are multiple uses, 781 // then the instruction got lowered to multiple machine instructions or the 782 // use of the loaded value ended up being multiple operands of the result, in 783 // either case, we can't fold this. 784 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI; 785 if (PostRI != RegInfo->reg_end()) 786 return false; 787 788 assert(RI.getOperand().isUse() && 789 "The only use of the vreg must be a use, we haven't emitted the def!"); 790 791 MachineInstr *User = &*RI; 792 793 // Set the insertion point properly. Folding the load can cause generation of 794 // other random instructions (like sign extends) for addressing modes, make 795 // sure they get inserted in a logical place before the new instruction. 796 FuncInfo->InsertPt = User; 797 FuncInfo->MBB = User->getParent(); 798 799 // Ask the target to try folding the load. 800 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI); 801} 802 803/// isFoldedOrDeadInstruction - Return true if the specified instruction is 804/// side-effect free and is either dead or folded into a generated instruction. 805/// Return false if it needs to be emitted. 806static bool isFoldedOrDeadInstruction(const Instruction *I, 807 FunctionLoweringInfo *FuncInfo) { 808 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 809 !isa<TerminatorInst>(I) && // Terminators aren't folded. 810 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 811 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 812 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 813} 814 815void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 816 // Initialize the Fast-ISel state, if needed. 817 FastISel *FastIS = 0; 818 if (EnableFastISel) 819 FastIS = TLI.createFastISel(*FuncInfo); 820 821 // Iterate over all basic blocks in the function. 822 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 823 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 824 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 825 const BasicBlock *LLVMBB = *I; 826 827 if (OptLevel != CodeGenOpt::None) { 828 bool AllPredsVisited = true; 829 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 830 PI != PE; ++PI) { 831 if (!FuncInfo->VisitedBBs.count(*PI)) { 832 AllPredsVisited = false; 833 break; 834 } 835 } 836 837 if (AllPredsVisited) { 838 for (BasicBlock::const_iterator I = LLVMBB->begin(); 839 isa<PHINode>(I); ++I) 840 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I)); 841 } else { 842 for (BasicBlock::const_iterator I = LLVMBB->begin(); 843 isa<PHINode>(I); ++I) 844 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I)); 845 } 846 847 FuncInfo->VisitedBBs.insert(LLVMBB); 848 } 849 850 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 851 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 852 853 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 854 BasicBlock::const_iterator const End = LLVMBB->end(); 855 BasicBlock::const_iterator BI = End; 856 857 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 858 859 // Setup an EH landing-pad block. 860 if (FuncInfo->MBB->isLandingPad()) 861 PrepareEHLandingPad(); 862 863 // Lower any arguments needed in this block if this is the entry block. 864 if (LLVMBB == &Fn.getEntryBlock()) 865 LowerArguments(LLVMBB); 866 867 // Before doing SelectionDAG ISel, see if FastISel has been requested. 868 if (FastIS) { 869 FastIS->startNewBlock(); 870 871 // Emit code for any incoming arguments. This must happen before 872 // beginning FastISel on the entry block. 873 if (LLVMBB == &Fn.getEntryBlock()) { 874 CurDAG->setRoot(SDB->getControlRoot()); 875 SDB->clear(); 876 CodeGenAndEmitDAG(); 877 878 // If we inserted any instructions at the beginning, make a note of 879 // where they are, so we can be sure to emit subsequent instructions 880 // after them. 881 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 882 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 883 else 884 FastIS->setLastLocalValue(0); 885 } 886 887 // Do FastISel on as many instructions as possible. 888 for (; BI != Begin; --BI) { 889 const Instruction *Inst = llvm::prior(BI); 890 891 // If we no longer require this instruction, skip it. 892 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) 893 continue; 894 895 // Bottom-up: reset the insert pos at the top, after any local-value 896 // instructions. 897 FastIS->recomputeInsertPt(); 898 899 // Try to select the instruction with FastISel. 900 if (FastIS->SelectInstruction(Inst)) { 901 ++NumFastIselSuccess; 902 // If fast isel succeeded, skip over all the folded instructions, and 903 // then see if there is a load right before the selected instructions. 904 // Try to fold the load if so. 905 const Instruction *BeforeInst = Inst; 906 while (BeforeInst != Begin) { 907 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 908 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 909 break; 910 } 911 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 912 BeforeInst->hasOneUse() && 913 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) 914 // If we succeeded, don't re-select the load. 915 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 916 continue; 917 } 918 919 // Then handle certain instructions as single-LLVM-Instruction blocks. 920 if (isa<CallInst>(Inst)) { 921 ++NumFastIselFailures; 922 if (EnableFastISelVerbose || EnableFastISelAbort) { 923 dbgs() << "FastISel missed call: "; 924 Inst->dump(); 925 } 926 927 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 928 unsigned &R = FuncInfo->ValueMap[Inst]; 929 if (!R) 930 R = FuncInfo->CreateRegs(Inst->getType()); 931 } 932 933 bool HadTailCall = false; 934 SelectBasicBlock(Inst, BI, HadTailCall); 935 936 // If the call was emitted as a tail call, we're done with the block. 937 if (HadTailCall) { 938 --BI; 939 break; 940 } 941 942 continue; 943 } 944 945 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 946 // Don't abort, and use a different message for terminator misses. 947 ++NumFastIselFailures; 948 if (EnableFastISelVerbose || EnableFastISelAbort) { 949 dbgs() << "FastISel missed terminator: "; 950 Inst->dump(); 951 } 952 } else { 953 ++NumFastIselFailures; 954 if (EnableFastISelVerbose || EnableFastISelAbort) { 955 dbgs() << "FastISel miss: "; 956 Inst->dump(); 957 } 958 if (EnableFastISelAbort) 959 // The "fast" selector couldn't handle something and bailed. 960 // For the purpose of debugging, just abort. 961 llvm_unreachable("FastISel didn't select the entire block"); 962 } 963 break; 964 } 965 966 FastIS->recomputeInsertPt(); 967 } 968 969 if (Begin != BI) 970 ++NumDAGBlocks; 971 else 972 ++NumFastIselBlocks; 973 974 if (Begin != BI) { 975 // Run SelectionDAG instruction selection on the remainder of the block 976 // not handled by FastISel. If FastISel is not run, this is the entire 977 // block. 978 bool HadTailCall; 979 SelectBasicBlock(Begin, BI, HadTailCall); 980 } 981 982 FinishBasicBlock(); 983 FuncInfo->PHINodesToUpdate.clear(); 984 } 985 986 delete FastIS; 987 SDB->clearDanglingDebugInfo(); 988} 989 990void 991SelectionDAGISel::FinishBasicBlock() { 992 993 DEBUG(dbgs() << "Total amount of phi nodes to update: " 994 << FuncInfo->PHINodesToUpdate.size() << "\n"; 995 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 996 dbgs() << "Node " << i << " : (" 997 << FuncInfo->PHINodesToUpdate[i].first 998 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 999 1000 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1001 // PHI nodes in successors. 1002 if (SDB->SwitchCases.empty() && 1003 SDB->JTCases.empty() && 1004 SDB->BitTestCases.empty()) { 1005 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1006 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1007 assert(PHI->isPHI() && 1008 "This is not a machine PHI node that we are updating!"); 1009 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1010 continue; 1011 PHI->addOperand( 1012 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1013 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1014 } 1015 return; 1016 } 1017 1018 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1019 // Lower header first, if it wasn't already lowered 1020 if (!SDB->BitTestCases[i].Emitted) { 1021 // Set the current basic block to the mbb we wish to insert the code into 1022 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1023 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1024 // Emit the code 1025 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1026 CurDAG->setRoot(SDB->getRoot()); 1027 SDB->clear(); 1028 CodeGenAndEmitDAG(); 1029 } 1030 1031 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1032 // Set the current basic block to the mbb we wish to insert the code into 1033 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1034 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1035 // Emit the code 1036 if (j+1 != ej) 1037 SDB->visitBitTestCase(SDB->BitTestCases[i], 1038 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1039 SDB->BitTestCases[i].Reg, 1040 SDB->BitTestCases[i].Cases[j], 1041 FuncInfo->MBB); 1042 else 1043 SDB->visitBitTestCase(SDB->BitTestCases[i], 1044 SDB->BitTestCases[i].Default, 1045 SDB->BitTestCases[i].Reg, 1046 SDB->BitTestCases[i].Cases[j], 1047 FuncInfo->MBB); 1048 1049 1050 CurDAG->setRoot(SDB->getRoot()); 1051 SDB->clear(); 1052 CodeGenAndEmitDAG(); 1053 } 1054 1055 // Update PHI Nodes 1056 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1057 pi != pe; ++pi) { 1058 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1059 MachineBasicBlock *PHIBB = PHI->getParent(); 1060 assert(PHI->isPHI() && 1061 "This is not a machine PHI node that we are updating!"); 1062 // This is "default" BB. We have two jumps to it. From "header" BB and 1063 // from last "case" BB. 1064 if (PHIBB == SDB->BitTestCases[i].Default) { 1065 PHI->addOperand(MachineOperand:: 1066 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1067 false)); 1068 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1069 PHI->addOperand(MachineOperand:: 1070 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1071 false)); 1072 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1073 back().ThisBB)); 1074 } 1075 // One of "cases" BB. 1076 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1077 j != ej; ++j) { 1078 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1079 if (cBB->isSuccessor(PHIBB)) { 1080 PHI->addOperand(MachineOperand:: 1081 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1082 false)); 1083 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1084 } 1085 } 1086 } 1087 } 1088 SDB->BitTestCases.clear(); 1089 1090 // If the JumpTable record is filled in, then we need to emit a jump table. 1091 // Updating the PHI nodes is tricky in this case, since we need to determine 1092 // whether the PHI is a successor of the range check MBB or the jump table MBB 1093 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1094 // Lower header first, if it wasn't already lowered 1095 if (!SDB->JTCases[i].first.Emitted) { 1096 // Set the current basic block to the mbb we wish to insert the code into 1097 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1098 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1099 // Emit the code 1100 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1101 FuncInfo->MBB); 1102 CurDAG->setRoot(SDB->getRoot()); 1103 SDB->clear(); 1104 CodeGenAndEmitDAG(); 1105 } 1106 1107 // Set the current basic block to the mbb we wish to insert the code into 1108 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1109 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1110 // Emit the code 1111 SDB->visitJumpTable(SDB->JTCases[i].second); 1112 CurDAG->setRoot(SDB->getRoot()); 1113 SDB->clear(); 1114 CodeGenAndEmitDAG(); 1115 1116 // Update PHI Nodes 1117 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1118 pi != pe; ++pi) { 1119 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1120 MachineBasicBlock *PHIBB = PHI->getParent(); 1121 assert(PHI->isPHI() && 1122 "This is not a machine PHI node that we are updating!"); 1123 // "default" BB. We can go there only from header BB. 1124 if (PHIBB == SDB->JTCases[i].second.Default) { 1125 PHI->addOperand 1126 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1127 false)); 1128 PHI->addOperand 1129 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1130 } 1131 // JT BB. Just iterate over successors here 1132 if (FuncInfo->MBB->isSuccessor(PHIBB)) { 1133 PHI->addOperand 1134 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1135 false)); 1136 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1137 } 1138 } 1139 } 1140 SDB->JTCases.clear(); 1141 1142 // If the switch block involved a branch to one of the actual successors, we 1143 // need to update PHI nodes in that block. 1144 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1145 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1146 assert(PHI->isPHI() && 1147 "This is not a machine PHI node that we are updating!"); 1148 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) { 1149 PHI->addOperand( 1150 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1151 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1152 } 1153 } 1154 1155 // If we generated any switch lowering information, build and codegen any 1156 // additional DAGs necessary. 1157 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1158 // Set the current basic block to the mbb we wish to insert the code into 1159 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1160 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1161 1162 // Determine the unique successors. 1163 SmallVector<MachineBasicBlock *, 2> Succs; 1164 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1165 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1166 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1167 1168 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1169 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1170 CurDAG->setRoot(SDB->getRoot()); 1171 SDB->clear(); 1172 CodeGenAndEmitDAG(); 1173 1174 // Remember the last block, now that any splitting is done, for use in 1175 // populating PHI nodes in successors. 1176 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1177 1178 // Handle any PHI nodes in successors of this chunk, as if we were coming 1179 // from the original BB before switch expansion. Note that PHI nodes can 1180 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1181 // handle them the right number of times. 1182 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1183 FuncInfo->MBB = Succs[i]; 1184 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1185 // FuncInfo->MBB may have been removed from the CFG if a branch was 1186 // constant folded. 1187 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1188 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin(); 1189 Phi != FuncInfo->MBB->end() && Phi->isPHI(); 1190 ++Phi) { 1191 // This value for this PHI node is recorded in PHINodesToUpdate. 1192 for (unsigned pn = 0; ; ++pn) { 1193 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1194 "Didn't find PHI entry!"); 1195 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 1196 Phi->addOperand(MachineOperand:: 1197 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 1198 false)); 1199 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1200 break; 1201 } 1202 } 1203 } 1204 } 1205 } 1206 } 1207 SDB->SwitchCases.clear(); 1208} 1209 1210 1211/// Create the scheduler. If a specific scheduler was specified 1212/// via the SchedulerRegistry, use it, otherwise select the 1213/// one preferred by the target. 1214/// 1215ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1216 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1217 1218 if (!Ctor) { 1219 Ctor = ISHeuristic; 1220 RegisterScheduler::setDefault(Ctor); 1221 } 1222 1223 return Ctor(this, OptLevel); 1224} 1225 1226//===----------------------------------------------------------------------===// 1227// Helper functions used by the generated instruction selector. 1228//===----------------------------------------------------------------------===// 1229// Calls to these methods are generated by tblgen. 1230 1231/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1232/// the dag combiner simplified the 255, we still want to match. RHS is the 1233/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1234/// specified in the .td file (e.g. 255). 1235bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1236 int64_t DesiredMaskS) const { 1237 const APInt &ActualMask = RHS->getAPIntValue(); 1238 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1239 1240 // If the actual mask exactly matches, success! 1241 if (ActualMask == DesiredMask) 1242 return true; 1243 1244 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1245 if (ActualMask.intersects(~DesiredMask)) 1246 return false; 1247 1248 // Otherwise, the DAG Combiner may have proven that the value coming in is 1249 // either already zero or is not demanded. Check for known zero input bits. 1250 APInt NeededMask = DesiredMask & ~ActualMask; 1251 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1252 return true; 1253 1254 // TODO: check to see if missing bits are just not demanded. 1255 1256 // Otherwise, this pattern doesn't match. 1257 return false; 1258} 1259 1260/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1261/// the dag combiner simplified the 255, we still want to match. RHS is the 1262/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1263/// specified in the .td file (e.g. 255). 1264bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1265 int64_t DesiredMaskS) const { 1266 const APInt &ActualMask = RHS->getAPIntValue(); 1267 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1268 1269 // If the actual mask exactly matches, success! 1270 if (ActualMask == DesiredMask) 1271 return true; 1272 1273 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1274 if (ActualMask.intersects(~DesiredMask)) 1275 return false; 1276 1277 // Otherwise, the DAG Combiner may have proven that the value coming in is 1278 // either already zero or is not demanded. Check for known zero input bits. 1279 APInt NeededMask = DesiredMask & ~ActualMask; 1280 1281 APInt KnownZero, KnownOne; 1282 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1283 1284 // If all the missing bits in the or are already known to be set, match! 1285 if ((NeededMask & KnownOne) == NeededMask) 1286 return true; 1287 1288 // TODO: check to see if missing bits are just not demanded. 1289 1290 // Otherwise, this pattern doesn't match. 1291 return false; 1292} 1293 1294 1295/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1296/// by tblgen. Others should not call it. 1297void SelectionDAGISel:: 1298SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1299 std::vector<SDValue> InOps; 1300 std::swap(InOps, Ops); 1301 1302 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1303 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1304 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1305 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1306 1307 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1308 if (InOps[e-1].getValueType() == MVT::Glue) 1309 --e; // Don't process a glue operand if it is here. 1310 1311 while (i != e) { 1312 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1313 if (!InlineAsm::isMemKind(Flags)) { 1314 // Just skip over this operand, copying the operands verbatim. 1315 Ops.insert(Ops.end(), InOps.begin()+i, 1316 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1317 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1318 } else { 1319 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1320 "Memory operand with multiple values?"); 1321 // Otherwise, this is a memory operand. Ask the target to select it. 1322 std::vector<SDValue> SelOps; 1323 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1324 report_fatal_error("Could not match memory address. Inline asm" 1325 " failure!"); 1326 1327 // Add this to the output node. 1328 unsigned NewFlags = 1329 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1330 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1331 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1332 i += 2; 1333 } 1334 } 1335 1336 // Add the glue input back if present. 1337 if (e != InOps.size()) 1338 Ops.push_back(InOps.back()); 1339} 1340 1341/// findGlueUse - Return use of MVT::Glue value produced by the specified 1342/// SDNode. 1343/// 1344static SDNode *findGlueUse(SDNode *N) { 1345 unsigned FlagResNo = N->getNumValues()-1; 1346 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1347 SDUse &Use = I.getUse(); 1348 if (Use.getResNo() == FlagResNo) 1349 return Use.getUser(); 1350 } 1351 return NULL; 1352} 1353 1354/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1355/// This function recursively traverses up the operand chain, ignoring 1356/// certain nodes. 1357static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1358 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1359 bool IgnoreChains) { 1360 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1361 // greater than all of its (recursive) operands. If we scan to a point where 1362 // 'use' is smaller than the node we're scanning for, then we know we will 1363 // never find it. 1364 // 1365 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1366 // happen because we scan down to newly selected nodes in the case of glue 1367 // uses. 1368 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1369 return false; 1370 1371 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1372 // won't fail if we scan it again. 1373 if (!Visited.insert(Use)) 1374 return false; 1375 1376 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1377 // Ignore chain uses, they are validated by HandleMergeInputChains. 1378 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1379 continue; 1380 1381 SDNode *N = Use->getOperand(i).getNode(); 1382 if (N == Def) { 1383 if (Use == ImmedUse || Use == Root) 1384 continue; // We are not looking for immediate use. 1385 assert(N != Root); 1386 return true; 1387 } 1388 1389 // Traverse up the operand chain. 1390 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1391 return true; 1392 } 1393 return false; 1394} 1395 1396/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1397/// operand node N of U during instruction selection that starts at Root. 1398bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1399 SDNode *Root) const { 1400 if (OptLevel == CodeGenOpt::None) return false; 1401 return N.hasOneUse(); 1402} 1403 1404/// IsLegalToFold - Returns true if the specific operand node N of 1405/// U can be folded during instruction selection that starts at Root. 1406bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1407 CodeGenOpt::Level OptLevel, 1408 bool IgnoreChains) { 1409 if (OptLevel == CodeGenOpt::None) return false; 1410 1411 // If Root use can somehow reach N through a path that that doesn't contain 1412 // U then folding N would create a cycle. e.g. In the following 1413 // diagram, Root can reach N through X. If N is folded into into Root, then 1414 // X is both a predecessor and a successor of U. 1415 // 1416 // [N*] // 1417 // ^ ^ // 1418 // / \ // 1419 // [U*] [X]? // 1420 // ^ ^ // 1421 // \ / // 1422 // \ / // 1423 // [Root*] // 1424 // 1425 // * indicates nodes to be folded together. 1426 // 1427 // If Root produces glue, then it gets (even more) interesting. Since it 1428 // will be "glued" together with its glue use in the scheduler, we need to 1429 // check if it might reach N. 1430 // 1431 // [N*] // 1432 // ^ ^ // 1433 // / \ // 1434 // [U*] [X]? // 1435 // ^ ^ // 1436 // \ \ // 1437 // \ | // 1438 // [Root*] | // 1439 // ^ | // 1440 // f | // 1441 // | / // 1442 // [Y] / // 1443 // ^ / // 1444 // f / // 1445 // | / // 1446 // [GU] // 1447 // 1448 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1449 // (call it Fold), then X is a predecessor of GU and a successor of 1450 // Fold. But since Fold and GU are glued together, this will create 1451 // a cycle in the scheduling graph. 1452 1453 // If the node has glue, walk down the graph to the "lowest" node in the 1454 // glueged set. 1455 EVT VT = Root->getValueType(Root->getNumValues()-1); 1456 while (VT == MVT::Glue) { 1457 SDNode *GU = findGlueUse(Root); 1458 if (GU == NULL) 1459 break; 1460 Root = GU; 1461 VT = Root->getValueType(Root->getNumValues()-1); 1462 1463 // If our query node has a glue result with a use, we've walked up it. If 1464 // the user (which has already been selected) has a chain or indirectly uses 1465 // the chain, our WalkChainUsers predicate will not consider it. Because of 1466 // this, we cannot ignore chains in this predicate. 1467 IgnoreChains = false; 1468 } 1469 1470 1471 SmallPtrSet<SDNode*, 16> Visited; 1472 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1473} 1474 1475SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1476 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1477 SelectInlineAsmMemoryOperands(Ops); 1478 1479 std::vector<EVT> VTs; 1480 VTs.push_back(MVT::Other); 1481 VTs.push_back(MVT::Glue); 1482 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1483 VTs, &Ops[0], Ops.size()); 1484 New->setNodeId(-1); 1485 return New.getNode(); 1486} 1487 1488SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1489 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1490} 1491 1492/// GetVBR - decode a vbr encoding whose top bit is set. 1493LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1494GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1495 assert(Val >= 128 && "Not a VBR"); 1496 Val &= 127; // Remove first vbr bit. 1497 1498 unsigned Shift = 7; 1499 uint64_t NextBits; 1500 do { 1501 NextBits = MatcherTable[Idx++]; 1502 Val |= (NextBits&127) << Shift; 1503 Shift += 7; 1504 } while (NextBits & 128); 1505 1506 return Val; 1507} 1508 1509 1510/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1511/// interior glue and chain results to use the new glue and chain results. 1512void SelectionDAGISel:: 1513UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1514 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1515 SDValue InputGlue, 1516 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1517 bool isMorphNodeTo) { 1518 SmallVector<SDNode*, 4> NowDeadNodes; 1519 1520 ISelUpdater ISU(ISelPosition); 1521 1522 // Now that all the normal results are replaced, we replace the chain and 1523 // glue results if present. 1524 if (!ChainNodesMatched.empty()) { 1525 assert(InputChain.getNode() != 0 && 1526 "Matched input chains but didn't produce a chain"); 1527 // Loop over all of the nodes we matched that produced a chain result. 1528 // Replace all the chain results with the final chain we ended up with. 1529 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1530 SDNode *ChainNode = ChainNodesMatched[i]; 1531 1532 // If this node was already deleted, don't look at it. 1533 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1534 continue; 1535 1536 // Don't replace the results of the root node if we're doing a 1537 // MorphNodeTo. 1538 if (ChainNode == NodeToMatch && isMorphNodeTo) 1539 continue; 1540 1541 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1542 if (ChainVal.getValueType() == MVT::Glue) 1543 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1544 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1545 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1546 1547 // If the node became dead and we haven't already seen it, delete it. 1548 if (ChainNode->use_empty() && 1549 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1550 NowDeadNodes.push_back(ChainNode); 1551 } 1552 } 1553 1554 // If the result produces glue, update any glue results in the matched 1555 // pattern with the glue result. 1556 if (InputGlue.getNode() != 0) { 1557 // Handle any interior nodes explicitly marked. 1558 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1559 SDNode *FRN = GlueResultNodesMatched[i]; 1560 1561 // If this node was already deleted, don't look at it. 1562 if (FRN->getOpcode() == ISD::DELETED_NODE) 1563 continue; 1564 1565 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1566 "Doesn't have a glue result"); 1567 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1568 InputGlue, &ISU); 1569 1570 // If the node became dead and we haven't already seen it, delete it. 1571 if (FRN->use_empty() && 1572 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1573 NowDeadNodes.push_back(FRN); 1574 } 1575 } 1576 1577 if (!NowDeadNodes.empty()) 1578 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1579 1580 DEBUG(errs() << "ISEL: Match complete!\n"); 1581} 1582 1583enum ChainResult { 1584 CR_Simple, 1585 CR_InducesCycle, 1586 CR_LeadsToInteriorNode 1587}; 1588 1589/// WalkChainUsers - Walk down the users of the specified chained node that is 1590/// part of the pattern we're matching, looking at all of the users we find. 1591/// This determines whether something is an interior node, whether we have a 1592/// non-pattern node in between two pattern nodes (which prevent folding because 1593/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1594/// between pattern nodes (in which case the TF becomes part of the pattern). 1595/// 1596/// The walk we do here is guaranteed to be small because we quickly get down to 1597/// already selected nodes "below" us. 1598static ChainResult 1599WalkChainUsers(SDNode *ChainedNode, 1600 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1601 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1602 ChainResult Result = CR_Simple; 1603 1604 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1605 E = ChainedNode->use_end(); UI != E; ++UI) { 1606 // Make sure the use is of the chain, not some other value we produce. 1607 if (UI.getUse().getValueType() != MVT::Other) continue; 1608 1609 SDNode *User = *UI; 1610 1611 // If we see an already-selected machine node, then we've gone beyond the 1612 // pattern that we're selecting down into the already selected chunk of the 1613 // DAG. 1614 if (User->isMachineOpcode() || 1615 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1616 continue; 1617 1618 if (User->getOpcode() == ISD::CopyToReg || 1619 User->getOpcode() == ISD::CopyFromReg || 1620 User->getOpcode() == ISD::INLINEASM || 1621 User->getOpcode() == ISD::EH_LABEL) { 1622 // If their node ID got reset to -1 then they've already been selected. 1623 // Treat them like a MachineOpcode. 1624 if (User->getNodeId() == -1) 1625 continue; 1626 } 1627 1628 // If we have a TokenFactor, we handle it specially. 1629 if (User->getOpcode() != ISD::TokenFactor) { 1630 // If the node isn't a token factor and isn't part of our pattern, then it 1631 // must be a random chained node in between two nodes we're selecting. 1632 // This happens when we have something like: 1633 // x = load ptr 1634 // call 1635 // y = x+4 1636 // store y -> ptr 1637 // Because we structurally match the load/store as a read/modify/write, 1638 // but the call is chained between them. We cannot fold in this case 1639 // because it would induce a cycle in the graph. 1640 if (!std::count(ChainedNodesInPattern.begin(), 1641 ChainedNodesInPattern.end(), User)) 1642 return CR_InducesCycle; 1643 1644 // Otherwise we found a node that is part of our pattern. For example in: 1645 // x = load ptr 1646 // y = x+4 1647 // store y -> ptr 1648 // This would happen when we're scanning down from the load and see the 1649 // store as a user. Record that there is a use of ChainedNode that is 1650 // part of the pattern and keep scanning uses. 1651 Result = CR_LeadsToInteriorNode; 1652 InteriorChainedNodes.push_back(User); 1653 continue; 1654 } 1655 1656 // If we found a TokenFactor, there are two cases to consider: first if the 1657 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1658 // uses of the TF are in our pattern) we just want to ignore it. Second, 1659 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1660 // [Load chain] 1661 // ^ 1662 // | 1663 // [Load] 1664 // ^ ^ 1665 // | \ DAG's like cheese 1666 // / \ do you? 1667 // / | 1668 // [TokenFactor] [Op] 1669 // ^ ^ 1670 // | | 1671 // \ / 1672 // \ / 1673 // [Store] 1674 // 1675 // In this case, the TokenFactor becomes part of our match and we rewrite it 1676 // as a new TokenFactor. 1677 // 1678 // To distinguish these two cases, do a recursive walk down the uses. 1679 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1680 case CR_Simple: 1681 // If the uses of the TokenFactor are just already-selected nodes, ignore 1682 // it, it is "below" our pattern. 1683 continue; 1684 case CR_InducesCycle: 1685 // If the uses of the TokenFactor lead to nodes that are not part of our 1686 // pattern that are not selected, folding would turn this into a cycle, 1687 // bail out now. 1688 return CR_InducesCycle; 1689 case CR_LeadsToInteriorNode: 1690 break; // Otherwise, keep processing. 1691 } 1692 1693 // Okay, we know we're in the interesting interior case. The TokenFactor 1694 // is now going to be considered part of the pattern so that we rewrite its 1695 // uses (it may have uses that are not part of the pattern) with the 1696 // ultimate chain result of the generated code. We will also add its chain 1697 // inputs as inputs to the ultimate TokenFactor we create. 1698 Result = CR_LeadsToInteriorNode; 1699 ChainedNodesInPattern.push_back(User); 1700 InteriorChainedNodes.push_back(User); 1701 continue; 1702 } 1703 1704 return Result; 1705} 1706 1707/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1708/// operation for when the pattern matched at least one node with a chains. The 1709/// input vector contains a list of all of the chained nodes that we match. We 1710/// must determine if this is a valid thing to cover (i.e. matching it won't 1711/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1712/// be used as the input node chain for the generated nodes. 1713static SDValue 1714HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1715 SelectionDAG *CurDAG) { 1716 // Walk all of the chained nodes we've matched, recursively scanning down the 1717 // users of the chain result. This adds any TokenFactor nodes that are caught 1718 // in between chained nodes to the chained and interior nodes list. 1719 SmallVector<SDNode*, 3> InteriorChainedNodes; 1720 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1721 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1722 InteriorChainedNodes) == CR_InducesCycle) 1723 return SDValue(); // Would induce a cycle. 1724 } 1725 1726 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1727 // that we are interested in. Form our input TokenFactor node. 1728 SmallVector<SDValue, 3> InputChains; 1729 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1730 // Add the input chain of this node to the InputChains list (which will be 1731 // the operands of the generated TokenFactor) if it's not an interior node. 1732 SDNode *N = ChainNodesMatched[i]; 1733 if (N->getOpcode() != ISD::TokenFactor) { 1734 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1735 continue; 1736 1737 // Otherwise, add the input chain. 1738 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1739 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1740 InputChains.push_back(InChain); 1741 continue; 1742 } 1743 1744 // If we have a token factor, we want to add all inputs of the token factor 1745 // that are not part of the pattern we're matching. 1746 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1747 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1748 N->getOperand(op).getNode())) 1749 InputChains.push_back(N->getOperand(op)); 1750 } 1751 } 1752 1753 SDValue Res; 1754 if (InputChains.size() == 1) 1755 return InputChains[0]; 1756 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1757 MVT::Other, &InputChains[0], InputChains.size()); 1758} 1759 1760/// MorphNode - Handle morphing a node in place for the selector. 1761SDNode *SelectionDAGISel:: 1762MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1763 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1764 // It is possible we're using MorphNodeTo to replace a node with no 1765 // normal results with one that has a normal result (or we could be 1766 // adding a chain) and the input could have glue and chains as well. 1767 // In this case we need to shift the operands down. 1768 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1769 // than the old isel though. 1770 int OldGlueResultNo = -1, OldChainResultNo = -1; 1771 1772 unsigned NTMNumResults = Node->getNumValues(); 1773 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 1774 OldGlueResultNo = NTMNumResults-1; 1775 if (NTMNumResults != 1 && 1776 Node->getValueType(NTMNumResults-2) == MVT::Other) 1777 OldChainResultNo = NTMNumResults-2; 1778 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1779 OldChainResultNo = NTMNumResults-1; 1780 1781 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1782 // that this deletes operands of the old node that become dead. 1783 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1784 1785 // MorphNodeTo can operate in two ways: if an existing node with the 1786 // specified operands exists, it can just return it. Otherwise, it 1787 // updates the node in place to have the requested operands. 1788 if (Res == Node) { 1789 // If we updated the node in place, reset the node ID. To the isel, 1790 // this should be just like a newly allocated machine node. 1791 Res->setNodeId(-1); 1792 } 1793 1794 unsigned ResNumResults = Res->getNumValues(); 1795 // Move the glue if needed. 1796 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 1797 (unsigned)OldGlueResultNo != ResNumResults-1) 1798 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 1799 SDValue(Res, ResNumResults-1)); 1800 1801 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 1802 --ResNumResults; 1803 1804 // Move the chain reference if needed. 1805 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1806 (unsigned)OldChainResultNo != ResNumResults-1) 1807 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1808 SDValue(Res, ResNumResults-1)); 1809 1810 // Otherwise, no replacement happened because the node already exists. Replace 1811 // Uses of the old node with the new one. 1812 if (Res != Node) 1813 CurDAG->ReplaceAllUsesWith(Node, Res); 1814 1815 return Res; 1816} 1817 1818/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1819LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1820CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1821 SDValue N, 1822 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1823 // Accept if it is exactly the same as a previously recorded node. 1824 unsigned RecNo = MatcherTable[MatcherIndex++]; 1825 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1826 return N == RecordedNodes[RecNo].first; 1827} 1828 1829/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1830LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1831CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1832 SelectionDAGISel &SDISel) { 1833 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1834} 1835 1836/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1837LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1838CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1839 SelectionDAGISel &SDISel, SDNode *N) { 1840 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1841} 1842 1843LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1844CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1845 SDNode *N) { 1846 uint16_t Opc = MatcherTable[MatcherIndex++]; 1847 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1848 return N->getOpcode() == Opc; 1849} 1850 1851LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1852CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1853 SDValue N, const TargetLowering &TLI) { 1854 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1855 if (N.getValueType() == VT) return true; 1856 1857 // Handle the case when VT is iPTR. 1858 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1859} 1860 1861LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1862CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1863 SDValue N, const TargetLowering &TLI, 1864 unsigned ChildNo) { 1865 if (ChildNo >= N.getNumOperands()) 1866 return false; // Match fails if out of range child #. 1867 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1868} 1869 1870 1871LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1872CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1873 SDValue N) { 1874 return cast<CondCodeSDNode>(N)->get() == 1875 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1876} 1877 1878LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1879CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1880 SDValue N, const TargetLowering &TLI) { 1881 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1882 if (cast<VTSDNode>(N)->getVT() == VT) 1883 return true; 1884 1885 // Handle the case when VT is iPTR. 1886 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1887} 1888 1889LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1890CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1891 SDValue N) { 1892 int64_t Val = MatcherTable[MatcherIndex++]; 1893 if (Val & 128) 1894 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1895 1896 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1897 return C != 0 && C->getSExtValue() == Val; 1898} 1899 1900LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1901CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1902 SDValue N, SelectionDAGISel &SDISel) { 1903 int64_t Val = MatcherTable[MatcherIndex++]; 1904 if (Val & 128) 1905 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1906 1907 if (N->getOpcode() != ISD::AND) return false; 1908 1909 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1910 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1911} 1912 1913LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1914CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1915 SDValue N, SelectionDAGISel &SDISel) { 1916 int64_t Val = MatcherTable[MatcherIndex++]; 1917 if (Val & 128) 1918 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1919 1920 if (N->getOpcode() != ISD::OR) return false; 1921 1922 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1923 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1924} 1925 1926/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1927/// scope, evaluate the current node. If the current predicate is known to 1928/// fail, set Result=true and return anything. If the current predicate is 1929/// known to pass, set Result=false and return the MatcherIndex to continue 1930/// with. If the current predicate is unknown, set Result=false and return the 1931/// MatcherIndex to continue with. 1932static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1933 unsigned Index, SDValue N, 1934 bool &Result, SelectionDAGISel &SDISel, 1935 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1936 switch (Table[Index++]) { 1937 default: 1938 Result = false; 1939 return Index-1; // Could not evaluate this predicate. 1940 case SelectionDAGISel::OPC_CheckSame: 1941 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1942 return Index; 1943 case SelectionDAGISel::OPC_CheckPatternPredicate: 1944 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1945 return Index; 1946 case SelectionDAGISel::OPC_CheckPredicate: 1947 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1948 return Index; 1949 case SelectionDAGISel::OPC_CheckOpcode: 1950 Result = !::CheckOpcode(Table, Index, N.getNode()); 1951 return Index; 1952 case SelectionDAGISel::OPC_CheckType: 1953 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1954 return Index; 1955 case SelectionDAGISel::OPC_CheckChild0Type: 1956 case SelectionDAGISel::OPC_CheckChild1Type: 1957 case SelectionDAGISel::OPC_CheckChild2Type: 1958 case SelectionDAGISel::OPC_CheckChild3Type: 1959 case SelectionDAGISel::OPC_CheckChild4Type: 1960 case SelectionDAGISel::OPC_CheckChild5Type: 1961 case SelectionDAGISel::OPC_CheckChild6Type: 1962 case SelectionDAGISel::OPC_CheckChild7Type: 1963 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1964 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1965 return Index; 1966 case SelectionDAGISel::OPC_CheckCondCode: 1967 Result = !::CheckCondCode(Table, Index, N); 1968 return Index; 1969 case SelectionDAGISel::OPC_CheckValueType: 1970 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1971 return Index; 1972 case SelectionDAGISel::OPC_CheckInteger: 1973 Result = !::CheckInteger(Table, Index, N); 1974 return Index; 1975 case SelectionDAGISel::OPC_CheckAndImm: 1976 Result = !::CheckAndImm(Table, Index, N, SDISel); 1977 return Index; 1978 case SelectionDAGISel::OPC_CheckOrImm: 1979 Result = !::CheckOrImm(Table, Index, N, SDISel); 1980 return Index; 1981 } 1982} 1983 1984namespace { 1985 1986struct MatchScope { 1987 /// FailIndex - If this match fails, this is the index to continue with. 1988 unsigned FailIndex; 1989 1990 /// NodeStack - The node stack when the scope was formed. 1991 SmallVector<SDValue, 4> NodeStack; 1992 1993 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1994 unsigned NumRecordedNodes; 1995 1996 /// NumMatchedMemRefs - The number of matched memref entries. 1997 unsigned NumMatchedMemRefs; 1998 1999 /// InputChain/InputGlue - The current chain/glue 2000 SDValue InputChain, InputGlue; 2001 2002 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2003 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2004}; 2005 2006} 2007 2008SDNode *SelectionDAGISel:: 2009SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2010 unsigned TableSize) { 2011 // FIXME: Should these even be selected? Handle these cases in the caller? 2012 switch (NodeToMatch->getOpcode()) { 2013 default: 2014 break; 2015 case ISD::EntryToken: // These nodes remain the same. 2016 case ISD::BasicBlock: 2017 case ISD::Register: 2018 //case ISD::VALUETYPE: 2019 //case ISD::CONDCODE: 2020 case ISD::HANDLENODE: 2021 case ISD::MDNODE_SDNODE: 2022 case ISD::TargetConstant: 2023 case ISD::TargetConstantFP: 2024 case ISD::TargetConstantPool: 2025 case ISD::TargetFrameIndex: 2026 case ISD::TargetExternalSymbol: 2027 case ISD::TargetBlockAddress: 2028 case ISD::TargetJumpTable: 2029 case ISD::TargetGlobalTLSAddress: 2030 case ISD::TargetGlobalAddress: 2031 case ISD::TokenFactor: 2032 case ISD::CopyFromReg: 2033 case ISD::CopyToReg: 2034 case ISD::EH_LABEL: 2035 NodeToMatch->setNodeId(-1); // Mark selected. 2036 return 0; 2037 case ISD::AssertSext: 2038 case ISD::AssertZext: 2039 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2040 NodeToMatch->getOperand(0)); 2041 return 0; 2042 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2043 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2044 } 2045 2046 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2047 2048 // Set up the node stack with NodeToMatch as the only node on the stack. 2049 SmallVector<SDValue, 8> NodeStack; 2050 SDValue N = SDValue(NodeToMatch, 0); 2051 NodeStack.push_back(N); 2052 2053 // MatchScopes - Scopes used when matching, if a match failure happens, this 2054 // indicates where to continue checking. 2055 SmallVector<MatchScope, 8> MatchScopes; 2056 2057 // RecordedNodes - This is the set of nodes that have been recorded by the 2058 // state machine. The second value is the parent of the node, or null if the 2059 // root is recorded. 2060 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2061 2062 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2063 // pattern. 2064 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2065 2066 // These are the current input chain and glue for use when generating nodes. 2067 // Various Emit operations change these. For example, emitting a copytoreg 2068 // uses and updates these. 2069 SDValue InputChain, InputGlue; 2070 2071 // ChainNodesMatched - If a pattern matches nodes that have input/output 2072 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2073 // which ones they are. The result is captured into this list so that we can 2074 // update the chain results when the pattern is complete. 2075 SmallVector<SDNode*, 3> ChainNodesMatched; 2076 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2077 2078 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2079 NodeToMatch->dump(CurDAG); 2080 errs() << '\n'); 2081 2082 // Determine where to start the interpreter. Normally we start at opcode #0, 2083 // but if the state machine starts with an OPC_SwitchOpcode, then we 2084 // accelerate the first lookup (which is guaranteed to be hot) with the 2085 // OpcodeOffset table. 2086 unsigned MatcherIndex = 0; 2087 2088 if (!OpcodeOffset.empty()) { 2089 // Already computed the OpcodeOffset table, just index into it. 2090 if (N.getOpcode() < OpcodeOffset.size()) 2091 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2092 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2093 2094 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2095 // Otherwise, the table isn't computed, but the state machine does start 2096 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2097 // is the first time we're selecting an instruction. 2098 unsigned Idx = 1; 2099 while (1) { 2100 // Get the size of this case. 2101 unsigned CaseSize = MatcherTable[Idx++]; 2102 if (CaseSize & 128) 2103 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2104 if (CaseSize == 0) break; 2105 2106 // Get the opcode, add the index to the table. 2107 uint16_t Opc = MatcherTable[Idx++]; 2108 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2109 if (Opc >= OpcodeOffset.size()) 2110 OpcodeOffset.resize((Opc+1)*2); 2111 OpcodeOffset[Opc] = Idx; 2112 Idx += CaseSize; 2113 } 2114 2115 // Okay, do the lookup for the first opcode. 2116 if (N.getOpcode() < OpcodeOffset.size()) 2117 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2118 } 2119 2120 while (1) { 2121 assert(MatcherIndex < TableSize && "Invalid index"); 2122#ifndef NDEBUG 2123 unsigned CurrentOpcodeIndex = MatcherIndex; 2124#endif 2125 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2126 switch (Opcode) { 2127 case OPC_Scope: { 2128 // Okay, the semantics of this operation are that we should push a scope 2129 // then evaluate the first child. However, pushing a scope only to have 2130 // the first check fail (which then pops it) is inefficient. If we can 2131 // determine immediately that the first check (or first several) will 2132 // immediately fail, don't even bother pushing a scope for them. 2133 unsigned FailIndex; 2134 2135 while (1) { 2136 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2137 if (NumToSkip & 128) 2138 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2139 // Found the end of the scope with no match. 2140 if (NumToSkip == 0) { 2141 FailIndex = 0; 2142 break; 2143 } 2144 2145 FailIndex = MatcherIndex+NumToSkip; 2146 2147 unsigned MatcherIndexOfPredicate = MatcherIndex; 2148 (void)MatcherIndexOfPredicate; // silence warning. 2149 2150 // If we can't evaluate this predicate without pushing a scope (e.g. if 2151 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2152 // push the scope and evaluate the full predicate chain. 2153 bool Result; 2154 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2155 Result, *this, RecordedNodes); 2156 if (!Result) 2157 break; 2158 2159 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2160 << "index " << MatcherIndexOfPredicate 2161 << ", continuing at " << FailIndex << "\n"); 2162 ++NumDAGIselRetries; 2163 2164 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2165 // move to the next case. 2166 MatcherIndex = FailIndex; 2167 } 2168 2169 // If the whole scope failed to match, bail. 2170 if (FailIndex == 0) break; 2171 2172 // Push a MatchScope which indicates where to go if the first child fails 2173 // to match. 2174 MatchScope NewEntry; 2175 NewEntry.FailIndex = FailIndex; 2176 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2177 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2178 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2179 NewEntry.InputChain = InputChain; 2180 NewEntry.InputGlue = InputGlue; 2181 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2182 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2183 MatchScopes.push_back(NewEntry); 2184 continue; 2185 } 2186 case OPC_RecordNode: { 2187 // Remember this node, it may end up being an operand in the pattern. 2188 SDNode *Parent = 0; 2189 if (NodeStack.size() > 1) 2190 Parent = NodeStack[NodeStack.size()-2].getNode(); 2191 RecordedNodes.push_back(std::make_pair(N, Parent)); 2192 continue; 2193 } 2194 2195 case OPC_RecordChild0: case OPC_RecordChild1: 2196 case OPC_RecordChild2: case OPC_RecordChild3: 2197 case OPC_RecordChild4: case OPC_RecordChild5: 2198 case OPC_RecordChild6: case OPC_RecordChild7: { 2199 unsigned ChildNo = Opcode-OPC_RecordChild0; 2200 if (ChildNo >= N.getNumOperands()) 2201 break; // Match fails if out of range child #. 2202 2203 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2204 N.getNode())); 2205 continue; 2206 } 2207 case OPC_RecordMemRef: 2208 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2209 continue; 2210 2211 case OPC_CaptureGlueInput: 2212 // If the current node has an input glue, capture it in InputGlue. 2213 if (N->getNumOperands() != 0 && 2214 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2215 InputGlue = N->getOperand(N->getNumOperands()-1); 2216 continue; 2217 2218 case OPC_MoveChild: { 2219 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2220 if (ChildNo >= N.getNumOperands()) 2221 break; // Match fails if out of range child #. 2222 N = N.getOperand(ChildNo); 2223 NodeStack.push_back(N); 2224 continue; 2225 } 2226 2227 case OPC_MoveParent: 2228 // Pop the current node off the NodeStack. 2229 NodeStack.pop_back(); 2230 assert(!NodeStack.empty() && "Node stack imbalance!"); 2231 N = NodeStack.back(); 2232 continue; 2233 2234 case OPC_CheckSame: 2235 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2236 continue; 2237 case OPC_CheckPatternPredicate: 2238 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2239 continue; 2240 case OPC_CheckPredicate: 2241 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2242 N.getNode())) 2243 break; 2244 continue; 2245 case OPC_CheckComplexPat: { 2246 unsigned CPNum = MatcherTable[MatcherIndex++]; 2247 unsigned RecNo = MatcherTable[MatcherIndex++]; 2248 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2249 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2250 RecordedNodes[RecNo].first, CPNum, 2251 RecordedNodes)) 2252 break; 2253 continue; 2254 } 2255 case OPC_CheckOpcode: 2256 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2257 continue; 2258 2259 case OPC_CheckType: 2260 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2261 continue; 2262 2263 case OPC_SwitchOpcode: { 2264 unsigned CurNodeOpcode = N.getOpcode(); 2265 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2266 unsigned CaseSize; 2267 while (1) { 2268 // Get the size of this case. 2269 CaseSize = MatcherTable[MatcherIndex++]; 2270 if (CaseSize & 128) 2271 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2272 if (CaseSize == 0) break; 2273 2274 uint16_t Opc = MatcherTable[MatcherIndex++]; 2275 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2276 2277 // If the opcode matches, then we will execute this case. 2278 if (CurNodeOpcode == Opc) 2279 break; 2280 2281 // Otherwise, skip over this case. 2282 MatcherIndex += CaseSize; 2283 } 2284 2285 // If no cases matched, bail out. 2286 if (CaseSize == 0) break; 2287 2288 // Otherwise, execute the case we found. 2289 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2290 << " to " << MatcherIndex << "\n"); 2291 continue; 2292 } 2293 2294 case OPC_SwitchType: { 2295 MVT CurNodeVT = N.getValueType().getSimpleVT(); 2296 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2297 unsigned CaseSize; 2298 while (1) { 2299 // Get the size of this case. 2300 CaseSize = MatcherTable[MatcherIndex++]; 2301 if (CaseSize & 128) 2302 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2303 if (CaseSize == 0) break; 2304 2305 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2306 if (CaseVT == MVT::iPTR) 2307 CaseVT = TLI.getPointerTy(); 2308 2309 // If the VT matches, then we will execute this case. 2310 if (CurNodeVT == CaseVT) 2311 break; 2312 2313 // Otherwise, skip over this case. 2314 MatcherIndex += CaseSize; 2315 } 2316 2317 // If no cases matched, bail out. 2318 if (CaseSize == 0) break; 2319 2320 // Otherwise, execute the case we found. 2321 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2322 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2323 continue; 2324 } 2325 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2326 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2327 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2328 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2329 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2330 Opcode-OPC_CheckChild0Type)) 2331 break; 2332 continue; 2333 case OPC_CheckCondCode: 2334 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2335 continue; 2336 case OPC_CheckValueType: 2337 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2338 continue; 2339 case OPC_CheckInteger: 2340 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2341 continue; 2342 case OPC_CheckAndImm: 2343 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2344 continue; 2345 case OPC_CheckOrImm: 2346 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2347 continue; 2348 2349 case OPC_CheckFoldableChainNode: { 2350 assert(NodeStack.size() != 1 && "No parent node"); 2351 // Verify that all intermediate nodes between the root and this one have 2352 // a single use. 2353 bool HasMultipleUses = false; 2354 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2355 if (!NodeStack[i].hasOneUse()) { 2356 HasMultipleUses = true; 2357 break; 2358 } 2359 if (HasMultipleUses) break; 2360 2361 // Check to see that the target thinks this is profitable to fold and that 2362 // we can fold it without inducing cycles in the graph. 2363 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2364 NodeToMatch) || 2365 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2366 NodeToMatch, OptLevel, 2367 true/*We validate our own chains*/)) 2368 break; 2369 2370 continue; 2371 } 2372 case OPC_EmitInteger: { 2373 MVT::SimpleValueType VT = 2374 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2375 int64_t Val = MatcherTable[MatcherIndex++]; 2376 if (Val & 128) 2377 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2378 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2379 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2380 continue; 2381 } 2382 case OPC_EmitRegister: { 2383 MVT::SimpleValueType VT = 2384 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2385 unsigned RegNo = MatcherTable[MatcherIndex++]; 2386 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2387 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2388 continue; 2389 } 2390 case OPC_EmitRegister2: { 2391 // For targets w/ more than 256 register names, the register enum 2392 // values are stored in two bytes in the matcher table (just like 2393 // opcodes). 2394 MVT::SimpleValueType VT = 2395 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2396 unsigned RegNo = MatcherTable[MatcherIndex++]; 2397 RegNo |= MatcherTable[MatcherIndex++] << 8; 2398 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2399 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2400 continue; 2401 } 2402 2403 case OPC_EmitConvertToTarget: { 2404 // Convert from IMM/FPIMM to target version. 2405 unsigned RecNo = MatcherTable[MatcherIndex++]; 2406 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2407 SDValue Imm = RecordedNodes[RecNo].first; 2408 2409 if (Imm->getOpcode() == ISD::Constant) { 2410 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2411 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2412 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2413 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2414 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2415 } 2416 2417 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2418 continue; 2419 } 2420 2421 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2422 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2423 // These are space-optimized forms of OPC_EmitMergeInputChains. 2424 assert(InputChain.getNode() == 0 && 2425 "EmitMergeInputChains should be the first chain producing node"); 2426 assert(ChainNodesMatched.empty() && 2427 "Should only have one EmitMergeInputChains per match"); 2428 2429 // Read all of the chained nodes. 2430 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2431 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2432 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2433 2434 // FIXME: What if other value results of the node have uses not matched 2435 // by this pattern? 2436 if (ChainNodesMatched.back() != NodeToMatch && 2437 !RecordedNodes[RecNo].first.hasOneUse()) { 2438 ChainNodesMatched.clear(); 2439 break; 2440 } 2441 2442 // Merge the input chains if they are not intra-pattern references. 2443 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2444 2445 if (InputChain.getNode() == 0) 2446 break; // Failed to merge. 2447 continue; 2448 } 2449 2450 case OPC_EmitMergeInputChains: { 2451 assert(InputChain.getNode() == 0 && 2452 "EmitMergeInputChains should be the first chain producing node"); 2453 // This node gets a list of nodes we matched in the input that have 2454 // chains. We want to token factor all of the input chains to these nodes 2455 // together. However, if any of the input chains is actually one of the 2456 // nodes matched in this pattern, then we have an intra-match reference. 2457 // Ignore these because the newly token factored chain should not refer to 2458 // the old nodes. 2459 unsigned NumChains = MatcherTable[MatcherIndex++]; 2460 assert(NumChains != 0 && "Can't TF zero chains"); 2461 2462 assert(ChainNodesMatched.empty() && 2463 "Should only have one EmitMergeInputChains per match"); 2464 2465 // Read all of the chained nodes. 2466 for (unsigned i = 0; i != NumChains; ++i) { 2467 unsigned RecNo = MatcherTable[MatcherIndex++]; 2468 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2469 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2470 2471 // FIXME: What if other value results of the node have uses not matched 2472 // by this pattern? 2473 if (ChainNodesMatched.back() != NodeToMatch && 2474 !RecordedNodes[RecNo].first.hasOneUse()) { 2475 ChainNodesMatched.clear(); 2476 break; 2477 } 2478 } 2479 2480 // If the inner loop broke out, the match fails. 2481 if (ChainNodesMatched.empty()) 2482 break; 2483 2484 // Merge the input chains if they are not intra-pattern references. 2485 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2486 2487 if (InputChain.getNode() == 0) 2488 break; // Failed to merge. 2489 2490 continue; 2491 } 2492 2493 case OPC_EmitCopyToReg: { 2494 unsigned RecNo = MatcherTable[MatcherIndex++]; 2495 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2496 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2497 2498 if (InputChain.getNode() == 0) 2499 InputChain = CurDAG->getEntryNode(); 2500 2501 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2502 DestPhysReg, RecordedNodes[RecNo].first, 2503 InputGlue); 2504 2505 InputGlue = InputChain.getValue(1); 2506 continue; 2507 } 2508 2509 case OPC_EmitNodeXForm: { 2510 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2511 unsigned RecNo = MatcherTable[MatcherIndex++]; 2512 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2513 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2514 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2515 continue; 2516 } 2517 2518 case OPC_EmitNode: 2519 case OPC_MorphNodeTo: { 2520 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2521 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2522 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2523 // Get the result VT list. 2524 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2525 SmallVector<EVT, 4> VTs; 2526 for (unsigned i = 0; i != NumVTs; ++i) { 2527 MVT::SimpleValueType VT = 2528 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2529 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2530 VTs.push_back(VT); 2531 } 2532 2533 if (EmitNodeInfo & OPFL_Chain) 2534 VTs.push_back(MVT::Other); 2535 if (EmitNodeInfo & OPFL_GlueOutput) 2536 VTs.push_back(MVT::Glue); 2537 2538 // This is hot code, so optimize the two most common cases of 1 and 2 2539 // results. 2540 SDVTList VTList; 2541 if (VTs.size() == 1) 2542 VTList = CurDAG->getVTList(VTs[0]); 2543 else if (VTs.size() == 2) 2544 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2545 else 2546 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2547 2548 // Get the operand list. 2549 unsigned NumOps = MatcherTable[MatcherIndex++]; 2550 SmallVector<SDValue, 8> Ops; 2551 for (unsigned i = 0; i != NumOps; ++i) { 2552 unsigned RecNo = MatcherTable[MatcherIndex++]; 2553 if (RecNo & 128) 2554 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2555 2556 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2557 Ops.push_back(RecordedNodes[RecNo].first); 2558 } 2559 2560 // If there are variadic operands to add, handle them now. 2561 if (EmitNodeInfo & OPFL_VariadicInfo) { 2562 // Determine the start index to copy from. 2563 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2564 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2565 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2566 "Invalid variadic node"); 2567 // Copy all of the variadic operands, not including a potential glue 2568 // input. 2569 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2570 i != e; ++i) { 2571 SDValue V = NodeToMatch->getOperand(i); 2572 if (V.getValueType() == MVT::Glue) break; 2573 Ops.push_back(V); 2574 } 2575 } 2576 2577 // If this has chain/glue inputs, add them. 2578 if (EmitNodeInfo & OPFL_Chain) 2579 Ops.push_back(InputChain); 2580 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2581 Ops.push_back(InputGlue); 2582 2583 // Create the node. 2584 SDNode *Res = 0; 2585 if (Opcode != OPC_MorphNodeTo) { 2586 // If this is a normal EmitNode command, just create the new node and 2587 // add the results to the RecordedNodes list. 2588 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2589 VTList, Ops.data(), Ops.size()); 2590 2591 // Add all the non-glue/non-chain results to the RecordedNodes list. 2592 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2593 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2594 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2595 (SDNode*) 0)); 2596 } 2597 2598 } else { 2599 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2600 EmitNodeInfo); 2601 } 2602 2603 // If the node had chain/glue results, update our notion of the current 2604 // chain and glue. 2605 if (EmitNodeInfo & OPFL_GlueOutput) { 2606 InputGlue = SDValue(Res, VTs.size()-1); 2607 if (EmitNodeInfo & OPFL_Chain) 2608 InputChain = SDValue(Res, VTs.size()-2); 2609 } else if (EmitNodeInfo & OPFL_Chain) 2610 InputChain = SDValue(Res, VTs.size()-1); 2611 2612 // If the OPFL_MemRefs glue is set on this node, slap all of the 2613 // accumulated memrefs onto it. 2614 // 2615 // FIXME: This is vastly incorrect for patterns with multiple outputs 2616 // instructions that access memory and for ComplexPatterns that match 2617 // loads. 2618 if (EmitNodeInfo & OPFL_MemRefs) { 2619 // Only attach load or store memory operands if the generated 2620 // instruction may load or store. 2621 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2622 bool mayLoad = MCID.mayLoad(); 2623 bool mayStore = MCID.mayStore(); 2624 2625 unsigned NumMemRefs = 0; 2626 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2627 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2628 if ((*I)->isLoad()) { 2629 if (mayLoad) 2630 ++NumMemRefs; 2631 } else if ((*I)->isStore()) { 2632 if (mayStore) 2633 ++NumMemRefs; 2634 } else { 2635 ++NumMemRefs; 2636 } 2637 } 2638 2639 MachineSDNode::mmo_iterator MemRefs = 2640 MF->allocateMemRefsArray(NumMemRefs); 2641 2642 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 2643 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2644 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2645 if ((*I)->isLoad()) { 2646 if (mayLoad) 2647 *MemRefsPos++ = *I; 2648 } else if ((*I)->isStore()) { 2649 if (mayStore) 2650 *MemRefsPos++ = *I; 2651 } else { 2652 *MemRefsPos++ = *I; 2653 } 2654 } 2655 2656 cast<MachineSDNode>(Res) 2657 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 2658 } 2659 2660 DEBUG(errs() << " " 2661 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2662 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2663 2664 // If this was a MorphNodeTo then we're completely done! 2665 if (Opcode == OPC_MorphNodeTo) { 2666 // Update chain and glue uses. 2667 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2668 InputGlue, GlueResultNodesMatched, true); 2669 return Res; 2670 } 2671 2672 continue; 2673 } 2674 2675 case OPC_MarkGlueResults: { 2676 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2677 2678 // Read and remember all the glue-result nodes. 2679 for (unsigned i = 0; i != NumNodes; ++i) { 2680 unsigned RecNo = MatcherTable[MatcherIndex++]; 2681 if (RecNo & 128) 2682 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2683 2684 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2685 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2686 } 2687 continue; 2688 } 2689 2690 case OPC_CompleteMatch: { 2691 // The match has been completed, and any new nodes (if any) have been 2692 // created. Patch up references to the matched dag to use the newly 2693 // created nodes. 2694 unsigned NumResults = MatcherTable[MatcherIndex++]; 2695 2696 for (unsigned i = 0; i != NumResults; ++i) { 2697 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2698 if (ResSlot & 128) 2699 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2700 2701 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2702 SDValue Res = RecordedNodes[ResSlot].first; 2703 2704 assert(i < NodeToMatch->getNumValues() && 2705 NodeToMatch->getValueType(i) != MVT::Other && 2706 NodeToMatch->getValueType(i) != MVT::Glue && 2707 "Invalid number of results to complete!"); 2708 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2709 NodeToMatch->getValueType(i) == MVT::iPTR || 2710 Res.getValueType() == MVT::iPTR || 2711 NodeToMatch->getValueType(i).getSizeInBits() == 2712 Res.getValueType().getSizeInBits()) && 2713 "invalid replacement"); 2714 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2715 } 2716 2717 // If the root node defines glue, add it to the glue nodes to update list. 2718 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2719 GlueResultNodesMatched.push_back(NodeToMatch); 2720 2721 // Update chain and glue uses. 2722 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2723 InputGlue, GlueResultNodesMatched, false); 2724 2725 assert(NodeToMatch->use_empty() && 2726 "Didn't replace all uses of the node?"); 2727 2728 // FIXME: We just return here, which interacts correctly with SelectRoot 2729 // above. We should fix this to not return an SDNode* anymore. 2730 return 0; 2731 } 2732 } 2733 2734 // If the code reached this point, then the match failed. See if there is 2735 // another child to try in the current 'Scope', otherwise pop it until we 2736 // find a case to check. 2737 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2738 ++NumDAGIselRetries; 2739 while (1) { 2740 if (MatchScopes.empty()) { 2741 CannotYetSelect(NodeToMatch); 2742 return 0; 2743 } 2744 2745 // Restore the interpreter state back to the point where the scope was 2746 // formed. 2747 MatchScope &LastScope = MatchScopes.back(); 2748 RecordedNodes.resize(LastScope.NumRecordedNodes); 2749 NodeStack.clear(); 2750 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2751 N = NodeStack.back(); 2752 2753 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2754 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2755 MatcherIndex = LastScope.FailIndex; 2756 2757 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2758 2759 InputChain = LastScope.InputChain; 2760 InputGlue = LastScope.InputGlue; 2761 if (!LastScope.HasChainNodesMatched) 2762 ChainNodesMatched.clear(); 2763 if (!LastScope.HasGlueResultNodesMatched) 2764 GlueResultNodesMatched.clear(); 2765 2766 // Check to see what the offset is at the new MatcherIndex. If it is zero 2767 // we have reached the end of this scope, otherwise we have another child 2768 // in the current scope to try. 2769 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2770 if (NumToSkip & 128) 2771 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2772 2773 // If we have another child in this scope to match, update FailIndex and 2774 // try it. 2775 if (NumToSkip != 0) { 2776 LastScope.FailIndex = MatcherIndex+NumToSkip; 2777 break; 2778 } 2779 2780 // End of this scope, pop it and try the next child in the containing 2781 // scope. 2782 MatchScopes.pop_back(); 2783 } 2784 } 2785} 2786 2787 2788 2789void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2790 std::string msg; 2791 raw_string_ostream Msg(msg); 2792 Msg << "Cannot select: "; 2793 2794 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2795 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2796 N->getOpcode() != ISD::INTRINSIC_VOID) { 2797 N->printrFull(Msg, CurDAG); 2798 } else { 2799 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2800 unsigned iid = 2801 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2802 if (iid < Intrinsic::num_intrinsics) 2803 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2804 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2805 Msg << "target intrinsic %" << TII->getName(iid); 2806 else 2807 Msg << "unknown intrinsic #" << iid; 2808 } 2809 report_fatal_error(Msg.str()); 2810} 2811 2812char SelectionDAGISel::ID = 0; 2813