SelectionDAGISel.cpp revision 47c144505b9be28ed22c626b3a407c11dba2fec5
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/CodeGen/FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/BranchProbabilityInfo.h" 21#include "llvm/Analysis/DebugInfo.h" 22#include "llvm/Constants.h" 23#include "llvm/Function.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/LLVMContext.h" 29#include "llvm/Module.h" 30#include "llvm/CodeGen/FastISel.h" 31#include "llvm/CodeGen/GCStrategy.h" 32#include "llvm/CodeGen/GCMetadata.h" 33#include "llvm/CodeGen/MachineFrameInfo.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineInstrBuilder.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 39#include "llvm/CodeGen/SchedulerRegistry.h" 40#include "llvm/CodeGen/SelectionDAG.h" 41#include "llvm/Target/TargetRegisterInfo.h" 42#include "llvm/Target/TargetIntrinsicInfo.h" 43#include "llvm/Target/TargetInstrInfo.h" 44#include "llvm/Target/TargetLibraryInfo.h" 45#include "llvm/Target/TargetLowering.h" 46#include "llvm/Target/TargetMachine.h" 47#include "llvm/Target/TargetOptions.h" 48#include "llvm/Transforms/Utils/BasicBlockUtils.h" 49#include "llvm/Support/Compiler.h" 50#include "llvm/Support/Debug.h" 51#include "llvm/Support/ErrorHandling.h" 52#include "llvm/Support/Timer.h" 53#include "llvm/Support/raw_ostream.h" 54#include "llvm/ADT/PostOrderIterator.h" 55#include "llvm/ADT/Statistic.h" 56#include <algorithm> 57using namespace llvm; 58 59STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 60STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 61STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 62STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 63STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 64 65#ifndef NDEBUG 66static cl::opt<bool> 67EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 68 cl::desc("Enable extra verbose messages in the \"fast\" " 69 "instruction selector")); 70 // Terminators 71STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 72STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 73STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 74STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 75STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 76STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 77STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 78 79 // Standard binary operators... 80STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 81STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 82STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 83STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 84STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 85STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 86STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 87STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 88STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 89STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 90STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 91STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 92 93 // Logical operators... 94STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 95STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 96STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 97 98 // Memory instructions... 99STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 100STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 101STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 102STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 103STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 104STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 105STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 106 107 // Convert instructions... 108STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 109STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 110STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 111STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 112STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 113STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 114STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 115STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 116STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 117STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 118STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 119STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 120 121 // Other instructions... 122STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 123STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 124STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 125STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 126STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 127STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 128STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 129STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 130STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 131STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 132STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 133STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 134STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 135STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 136STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 137#endif 138 139static cl::opt<bool> 140EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 141 cl::desc("Enable verbose messages in the \"fast\" " 142 "instruction selector")); 143static cl::opt<bool> 144EnableFastISelAbort("fast-isel-abort", cl::Hidden, 145 cl::desc("Enable abort calls when \"fast\" instruction fails")); 146 147static cl::opt<bool> 148UseMBPI("use-mbpi", 149 cl::desc("use Machine Branch Probability Info"), 150 cl::init(true), cl::Hidden); 151 152#ifndef NDEBUG 153static cl::opt<bool> 154ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 155 cl::desc("Pop up a window to show dags before the first " 156 "dag combine pass")); 157static cl::opt<bool> 158ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 159 cl::desc("Pop up a window to show dags before legalize types")); 160static cl::opt<bool> 161ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 162 cl::desc("Pop up a window to show dags before legalize")); 163static cl::opt<bool> 164ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 165 cl::desc("Pop up a window to show dags before the second " 166 "dag combine pass")); 167static cl::opt<bool> 168ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 169 cl::desc("Pop up a window to show dags before the post legalize types" 170 " dag combine pass")); 171static cl::opt<bool> 172ViewISelDAGs("view-isel-dags", cl::Hidden, 173 cl::desc("Pop up a window to show isel dags as they are selected")); 174static cl::opt<bool> 175ViewSchedDAGs("view-sched-dags", cl::Hidden, 176 cl::desc("Pop up a window to show sched dags as they are processed")); 177static cl::opt<bool> 178ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 179 cl::desc("Pop up a window to show SUnit dags after they are processed")); 180#else 181static const bool ViewDAGCombine1 = false, 182 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 183 ViewDAGCombine2 = false, 184 ViewDAGCombineLT = false, 185 ViewISelDAGs = false, ViewSchedDAGs = false, 186 ViewSUnitDAGs = false; 187#endif 188 189//===---------------------------------------------------------------------===// 190/// 191/// RegisterScheduler class - Track the registration of instruction schedulers. 192/// 193//===---------------------------------------------------------------------===// 194MachinePassRegistry RegisterScheduler::Registry; 195 196//===---------------------------------------------------------------------===// 197/// 198/// ISHeuristic command line option for instruction schedulers. 199/// 200//===---------------------------------------------------------------------===// 201static cl::opt<RegisterScheduler::FunctionPassCtor, false, 202 RegisterPassParser<RegisterScheduler> > 203ISHeuristic("pre-RA-sched", 204 cl::init(&createDefaultScheduler), 205 cl::desc("Instruction schedulers available (before register" 206 " allocation):")); 207 208static RegisterScheduler 209defaultListDAGScheduler("default", "Best scheduler for the target", 210 createDefaultScheduler); 211 212namespace llvm { 213 //===--------------------------------------------------------------------===// 214 /// createDefaultScheduler - This creates an instruction scheduler appropriate 215 /// for the target. 216 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 217 CodeGenOpt::Level OptLevel) { 218 const TargetLowering &TLI = IS->getTargetLowering(); 219 220 if (OptLevel == CodeGenOpt::None || 221 TLI.getSchedulingPreference() == Sched::Source) 222 return createSourceListDAGScheduler(IS, OptLevel); 223 if (TLI.getSchedulingPreference() == Sched::RegPressure) 224 return createBURRListDAGScheduler(IS, OptLevel); 225 if (TLI.getSchedulingPreference() == Sched::Hybrid) 226 return createHybridListDAGScheduler(IS, OptLevel); 227 if (TLI.getSchedulingPreference() == Sched::VLIW) 228 return createVLIWDAGScheduler(IS, OptLevel); 229 assert(TLI.getSchedulingPreference() == Sched::ILP && 230 "Unknown sched type!"); 231 return createILPListDAGScheduler(IS, OptLevel); 232 } 233} 234 235// EmitInstrWithCustomInserter - This method should be implemented by targets 236// that mark instructions with the 'usesCustomInserter' flag. These 237// instructions are special in various ways, which require special support to 238// insert. The specified MachineInstr is created but not inserted into any 239// basic blocks, and this method is called to expand it into a sequence of 240// instructions, potentially also creating new basic blocks and control flow. 241// When new basic blocks are inserted and the edges from MBB to its successors 242// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 243// DenseMap. 244MachineBasicBlock * 245TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 246 MachineBasicBlock *MBB) const { 247#ifndef NDEBUG 248 dbgs() << "If a target marks an instruction with " 249 "'usesCustomInserter', it must implement " 250 "TargetLowering::EmitInstrWithCustomInserter!"; 251#endif 252 llvm_unreachable(0); 253} 254 255void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 256 SDNode *Node) const { 257 assert(!MI->hasPostISelHook() && 258 "If a target marks an instruction with 'hasPostISelHook', " 259 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 260} 261 262//===----------------------------------------------------------------------===// 263// SelectionDAGISel code 264//===----------------------------------------------------------------------===// 265 266void SelectionDAGISel::ISelUpdater::anchor() { } 267 268SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, 269 CodeGenOpt::Level OL) : 270 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 271 FuncInfo(new FunctionLoweringInfo(TLI)), 272 CurDAG(new SelectionDAG(tm, OL)), 273 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 274 GFI(), 275 OptLevel(OL), 276 DAGSize(0) { 277 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 278 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 279 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 280 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 281 } 282 283SelectionDAGISel::~SelectionDAGISel() { 284 delete SDB; 285 delete CurDAG; 286 delete FuncInfo; 287} 288 289void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 290 AU.addRequired<AliasAnalysis>(); 291 AU.addPreserved<AliasAnalysis>(); 292 AU.addRequired<GCModuleInfo>(); 293 AU.addPreserved<GCModuleInfo>(); 294 AU.addRequired<TargetLibraryInfo>(); 295 if (UseMBPI && OptLevel != CodeGenOpt::None) 296 AU.addRequired<BranchProbabilityInfo>(); 297 MachineFunctionPass::getAnalysisUsage(AU); 298} 299 300/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 301/// may trap on it. In this case we have to split the edge so that the path 302/// through the predecessor block that doesn't go to the phi block doesn't 303/// execute the possibly trapping instruction. 304/// 305/// This is required for correctness, so it must be done at -O0. 306/// 307static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 308 // Loop for blocks with phi nodes. 309 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 310 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 311 if (PN == 0) continue; 312 313 ReprocessBlock: 314 // For each block with a PHI node, check to see if any of the input values 315 // are potentially trapping constant expressions. Constant expressions are 316 // the only potentially trapping value that can occur as the argument to a 317 // PHI. 318 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 319 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 320 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 321 if (CE == 0 || !CE->canTrap()) continue; 322 323 // The only case we have to worry about is when the edge is critical. 324 // Since this block has a PHI Node, we assume it has multiple input 325 // edges: check to see if the pred has multiple successors. 326 BasicBlock *Pred = PN->getIncomingBlock(i); 327 if (Pred->getTerminator()->getNumSuccessors() == 1) 328 continue; 329 330 // Okay, we have to split this edge. 331 SplitCriticalEdge(Pred->getTerminator(), 332 GetSuccessorNumber(Pred, BB), SDISel, true); 333 goto ReprocessBlock; 334 } 335 } 336} 337 338bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 339 // Do some sanity-checking on the command-line options. 340 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 341 "-fast-isel-verbose requires -fast-isel"); 342 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 343 "-fast-isel-abort requires -fast-isel"); 344 345 const Function &Fn = *mf.getFunction(); 346 const TargetInstrInfo &TII = *TM.getInstrInfo(); 347 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 348 349 MF = &mf; 350 RegInfo = &MF->getRegInfo(); 351 AA = &getAnalysis<AliasAnalysis>(); 352 LibInfo = &getAnalysis<TargetLibraryInfo>(); 353 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 354 355 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 356 357 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 358 359 CurDAG->init(*MF); 360 FuncInfo->set(Fn, *MF); 361 362 if (UseMBPI && OptLevel != CodeGenOpt::None) 363 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 364 else 365 FuncInfo->BPI = 0; 366 367 SDB->init(GFI, *AA, LibInfo); 368 369 SelectAllBasicBlocks(Fn); 370 371 // If the first basic block in the function has live ins that need to be 372 // copied into vregs, emit the copies into the top of the block before 373 // emitting the code for the block. 374 MachineBasicBlock *EntryMBB = MF->begin(); 375 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 376 377 DenseMap<unsigned, unsigned> LiveInMap; 378 if (!FuncInfo->ArgDbgValues.empty()) 379 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 380 E = RegInfo->livein_end(); LI != E; ++LI) 381 if (LI->second) 382 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 383 384 // Insert DBG_VALUE instructions for function arguments to the entry block. 385 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 386 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 387 unsigned Reg = MI->getOperand(0).getReg(); 388 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 389 EntryMBB->insert(EntryMBB->begin(), MI); 390 else { 391 MachineInstr *Def = RegInfo->getVRegDef(Reg); 392 MachineBasicBlock::iterator InsertPos = Def; 393 // FIXME: VR def may not be in entry block. 394 Def->getParent()->insert(llvm::next(InsertPos), MI); 395 } 396 397 // If Reg is live-in then update debug info to track its copy in a vreg. 398 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 399 if (LDI != LiveInMap.end()) { 400 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 401 MachineBasicBlock::iterator InsertPos = Def; 402 const MDNode *Variable = 403 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 404 unsigned Offset = MI->getOperand(1).getImm(); 405 // Def is never a terminator here, so it is ok to increment InsertPos. 406 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 407 TII.get(TargetOpcode::DBG_VALUE)) 408 .addReg(LDI->second, RegState::Debug) 409 .addImm(Offset).addMetadata(Variable); 410 411 // If this vreg is directly copied into an exported register then 412 // that COPY instructions also need DBG_VALUE, if it is the only 413 // user of LDI->second. 414 MachineInstr *CopyUseMI = NULL; 415 for (MachineRegisterInfo::use_iterator 416 UI = RegInfo->use_begin(LDI->second); 417 MachineInstr *UseMI = UI.skipInstruction();) { 418 if (UseMI->isDebugValue()) continue; 419 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 420 CopyUseMI = UseMI; continue; 421 } 422 // Otherwise this is another use or second copy use. 423 CopyUseMI = NULL; break; 424 } 425 if (CopyUseMI) { 426 MachineInstr *NewMI = 427 BuildMI(*MF, CopyUseMI->getDebugLoc(), 428 TII.get(TargetOpcode::DBG_VALUE)) 429 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 430 .addImm(Offset).addMetadata(Variable); 431 MachineBasicBlock::iterator Pos = CopyUseMI; 432 EntryMBB->insertAfter(Pos, NewMI); 433 } 434 } 435 } 436 437 // Determine if there are any calls in this machine function. 438 MachineFrameInfo *MFI = MF->getFrameInfo(); 439 if (!MFI->hasCalls()) { 440 for (MachineFunction::const_iterator 441 I = MF->begin(), E = MF->end(); I != E; ++I) { 442 const MachineBasicBlock *MBB = I; 443 for (MachineBasicBlock::const_iterator 444 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 445 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 446 447 if ((MCID.isCall() && !MCID.isReturn()) || 448 II->isStackAligningInlineAsm()) { 449 MFI->setHasCalls(true); 450 goto done; 451 } 452 } 453 } 454 done:; 455 } 456 457 // Determine if there is a call to setjmp in the machine function. 458 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 459 460 // Replace forward-declared registers with the registers containing 461 // the desired value. 462 MachineRegisterInfo &MRI = MF->getRegInfo(); 463 for (DenseMap<unsigned, unsigned>::iterator 464 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 465 I != E; ++I) { 466 unsigned From = I->first; 467 unsigned To = I->second; 468 // If To is also scheduled to be replaced, find what its ultimate 469 // replacement is. 470 for (;;) { 471 DenseMap<unsigned, unsigned>::iterator J = 472 FuncInfo->RegFixups.find(To); 473 if (J == E) break; 474 To = J->second; 475 } 476 // Replace it. 477 MRI.replaceRegWith(From, To); 478 } 479 480 // Release function-specific state. SDB and CurDAG are already cleared 481 // at this point. 482 FuncInfo->clear(); 483 484 return true; 485} 486 487void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 488 BasicBlock::const_iterator End, 489 bool &HadTailCall) { 490 // Lower all of the non-terminator instructions. If a call is emitted 491 // as a tail call, cease emitting nodes for this block. Terminators 492 // are handled below. 493 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 494 SDB->visit(*I); 495 496 // Make sure the root of the DAG is up-to-date. 497 CurDAG->setRoot(SDB->getControlRoot()); 498 HadTailCall = SDB->HasTailCall; 499 SDB->clear(); 500 501 // Final step, emit the lowered DAG as machine code. 502 CodeGenAndEmitDAG(); 503} 504 505void SelectionDAGISel::ComputeLiveOutVRegInfo() { 506 SmallPtrSet<SDNode*, 128> VisitedNodes; 507 SmallVector<SDNode*, 128> Worklist; 508 509 Worklist.push_back(CurDAG->getRoot().getNode()); 510 511 APInt Mask; 512 APInt KnownZero; 513 APInt KnownOne; 514 515 do { 516 SDNode *N = Worklist.pop_back_val(); 517 518 // If we've already seen this node, ignore it. 519 if (!VisitedNodes.insert(N)) 520 continue; 521 522 // Otherwise, add all chain operands to the worklist. 523 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 524 if (N->getOperand(i).getValueType() == MVT::Other) 525 Worklist.push_back(N->getOperand(i).getNode()); 526 527 // If this is a CopyToReg with a vreg dest, process it. 528 if (N->getOpcode() != ISD::CopyToReg) 529 continue; 530 531 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 532 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 533 continue; 534 535 // Ignore non-scalar or non-integer values. 536 SDValue Src = N->getOperand(2); 537 EVT SrcVT = Src.getValueType(); 538 if (!SrcVT.isInteger() || SrcVT.isVector()) 539 continue; 540 541 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 542 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 543 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 544 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 545 } while (!Worklist.empty()); 546} 547 548void SelectionDAGISel::CodeGenAndEmitDAG() { 549 std::string GroupName; 550 if (TimePassesIsEnabled) 551 GroupName = "Instruction Selection and Scheduling"; 552 std::string BlockName; 553 int BlockNumber = -1; 554 (void)BlockNumber; 555#ifdef NDEBUG 556 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 557 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 558 ViewSUnitDAGs) 559#endif 560 { 561 BlockNumber = FuncInfo->MBB->getNumber(); 562 BlockName = MF->getFunction()->getName().str() + ":" + 563 FuncInfo->MBB->getBasicBlock()->getName().str(); 564 } 565 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 566 << " '" << BlockName << "'\n"; CurDAG->dump()); 567 568 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 569 570 // Run the DAG combiner in pre-legalize mode. 571 { 572 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 573 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 574 } 575 576 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 577 << " '" << BlockName << "'\n"; CurDAG->dump()); 578 579 // Second step, hack on the DAG until it only uses operations and types that 580 // the target supports. 581 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 582 BlockName); 583 584 bool Changed; 585 { 586 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 587 Changed = CurDAG->LegalizeTypes(); 588 } 589 590 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 591 << " '" << BlockName << "'\n"; CurDAG->dump()); 592 593 if (Changed) { 594 if (ViewDAGCombineLT) 595 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 596 597 // Run the DAG combiner in post-type-legalize mode. 598 { 599 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 600 TimePassesIsEnabled); 601 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 602 } 603 604 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 605 << " '" << BlockName << "'\n"; CurDAG->dump()); 606 } 607 608 { 609 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 610 Changed = CurDAG->LegalizeVectors(); 611 } 612 613 if (Changed) { 614 { 615 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 616 CurDAG->LegalizeTypes(); 617 } 618 619 if (ViewDAGCombineLT) 620 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 621 622 // Run the DAG combiner in post-type-legalize mode. 623 { 624 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 625 TimePassesIsEnabled); 626 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 627 } 628 629 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 630 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 631 } 632 633 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 634 635 { 636 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 637 CurDAG->Legalize(); 638 } 639 640 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 641 << " '" << BlockName << "'\n"; CurDAG->dump()); 642 643 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 644 645 // Run the DAG combiner in post-legalize mode. 646 { 647 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 648 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 649 } 650 651 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 652 << " '" << BlockName << "'\n"; CurDAG->dump()); 653 654 if (OptLevel != CodeGenOpt::None) 655 ComputeLiveOutVRegInfo(); 656 657 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 658 659 // Third, instruction select all of the operations to machine code, adding the 660 // code to the MachineBasicBlock. 661 { 662 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 663 DoInstructionSelection(); 664 } 665 666 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 667 << " '" << BlockName << "'\n"; CurDAG->dump()); 668 669 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 670 671 // Schedule machine code. 672 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 673 { 674 NamedRegionTimer T("Instruction Scheduling", GroupName, 675 TimePassesIsEnabled); 676 Scheduler->Run(CurDAG, FuncInfo->MBB); 677 } 678 679 if (ViewSUnitDAGs) Scheduler->viewGraph(); 680 681 // Emit machine code to BB. This can change 'BB' to the last block being 682 // inserted into. 683 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 684 { 685 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 686 687 // FuncInfo->InsertPt is passed by reference and set to the end of the 688 // scheduled instructions. 689 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 690 } 691 692 // If the block was split, make sure we update any references that are used to 693 // update PHI nodes later on. 694 if (FirstMBB != LastMBB) 695 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 696 697 // Free the scheduler state. 698 { 699 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 700 TimePassesIsEnabled); 701 delete Scheduler; 702 } 703 704 // Free the SelectionDAG state, now that we're finished with it. 705 CurDAG->clear(); 706} 707 708void SelectionDAGISel::DoInstructionSelection() { 709 DEBUG(errs() << "===== Instruction selection begins: BB#" 710 << FuncInfo->MBB->getNumber() 711 << " '" << FuncInfo->MBB->getName() << "'\n"); 712 713 PreprocessISelDAG(); 714 715 // Select target instructions for the DAG. 716 { 717 // Number all nodes with a topological order and set DAGSize. 718 DAGSize = CurDAG->AssignTopologicalOrder(); 719 720 // Create a dummy node (which is not added to allnodes), that adds 721 // a reference to the root node, preventing it from being deleted, 722 // and tracking any changes of the root. 723 HandleSDNode Dummy(CurDAG->getRoot()); 724 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 725 ++ISelPosition; 726 727 // The AllNodes list is now topological-sorted. Visit the 728 // nodes by starting at the end of the list (the root of the 729 // graph) and preceding back toward the beginning (the entry 730 // node). 731 while (ISelPosition != CurDAG->allnodes_begin()) { 732 SDNode *Node = --ISelPosition; 733 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 734 // but there are currently some corner cases that it misses. Also, this 735 // makes it theoretically possible to disable the DAGCombiner. 736 if (Node->use_empty()) 737 continue; 738 739 SDNode *ResNode = Select(Node); 740 741 // FIXME: This is pretty gross. 'Select' should be changed to not return 742 // anything at all and this code should be nuked with a tactical strike. 743 744 // If node should not be replaced, continue with the next one. 745 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 746 continue; 747 // Replace node. 748 if (ResNode) 749 ReplaceUses(Node, ResNode); 750 751 // If after the replacement this node is not used any more, 752 // remove this dead node. 753 if (Node->use_empty()) { // Don't delete EntryToken, etc. 754 ISelUpdater ISU(ISelPosition); 755 CurDAG->RemoveDeadNode(Node, &ISU); 756 } 757 } 758 759 CurDAG->setRoot(Dummy.getValue()); 760 } 761 762 DEBUG(errs() << "===== Instruction selection ends:\n"); 763 764 PostprocessISelDAG(); 765} 766 767/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 768/// do other setup for EH landing-pad blocks. 769void SelectionDAGISel::PrepareEHLandingPad() { 770 MachineBasicBlock *MBB = FuncInfo->MBB; 771 772 // Add a label to mark the beginning of the landing pad. Deletion of the 773 // landing pad can thus be detected via the MachineModuleInfo. 774 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 775 776 // Assign the call site to the landing pad's begin label. 777 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 778 779 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 780 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 781 .addSym(Label); 782 783 // Mark exception register as live in. 784 unsigned Reg = TLI.getExceptionPointerRegister(); 785 if (Reg) MBB->addLiveIn(Reg); 786 787 // Mark exception selector register as live in. 788 Reg = TLI.getExceptionSelectorRegister(); 789 if (Reg) MBB->addLiveIn(Reg); 790} 791 792/// TryToFoldFastISelLoad - We're checking to see if we can fold the specified 793/// load into the specified FoldInst. Note that we could have a sequence where 794/// multiple LLVM IR instructions are folded into the same machineinstr. For 795/// example we could have: 796/// A: x = load i32 *P 797/// B: y = icmp A, 42 798/// C: br y, ... 799/// 800/// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and 801/// any other folded instructions) because it is between A and C. 802/// 803/// If we succeed in folding the load into the operation, return true. 804/// 805bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI, 806 const Instruction *FoldInst, 807 FastISel *FastIS) { 808 // We know that the load has a single use, but don't know what it is. If it 809 // isn't one of the folded instructions, then we can't succeed here. Handle 810 // this by scanning the single-use users of the load until we get to FoldInst. 811 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs. 812 813 const Instruction *TheUser = LI->use_back(); 814 while (TheUser != FoldInst && // Scan up until we find FoldInst. 815 // Stay in the right block. 816 TheUser->getParent() == FoldInst->getParent() && 817 --MaxUsers) { // Don't scan too far. 818 // If there are multiple or no uses of this instruction, then bail out. 819 if (!TheUser->hasOneUse()) 820 return false; 821 822 TheUser = TheUser->use_back(); 823 } 824 825 // If we didn't find the fold instruction, then we failed to collapse the 826 // sequence. 827 if (TheUser != FoldInst) 828 return false; 829 830 // Don't try to fold volatile loads. Target has to deal with alignment 831 // constraints. 832 if (LI->isVolatile()) return false; 833 834 // Figure out which vreg this is going into. If there is no assigned vreg yet 835 // then there actually was no reference to it. Perhaps the load is referenced 836 // by a dead instruction. 837 unsigned LoadReg = FastIS->getRegForValue(LI); 838 if (LoadReg == 0) 839 return false; 840 841 // Check to see what the uses of this vreg are. If it has no uses, or more 842 // than one use (at the machine instr level) then we can't fold it. 843 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg); 844 if (RI == RegInfo->reg_end()) 845 return false; 846 847 // See if there is exactly one use of the vreg. If there are multiple uses, 848 // then the instruction got lowered to multiple machine instructions or the 849 // use of the loaded value ended up being multiple operands of the result, in 850 // either case, we can't fold this. 851 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI; 852 if (PostRI != RegInfo->reg_end()) 853 return false; 854 855 assert(RI.getOperand().isUse() && 856 "The only use of the vreg must be a use, we haven't emitted the def!"); 857 858 MachineInstr *User = &*RI; 859 860 // Set the insertion point properly. Folding the load can cause generation of 861 // other random instructions (like sign extends) for addressing modes, make 862 // sure they get inserted in a logical place before the new instruction. 863 FuncInfo->InsertPt = User; 864 FuncInfo->MBB = User->getParent(); 865 866 // Ask the target to try folding the load. 867 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI); 868} 869 870/// isFoldedOrDeadInstruction - Return true if the specified instruction is 871/// side-effect free and is either dead or folded into a generated instruction. 872/// Return false if it needs to be emitted. 873static bool isFoldedOrDeadInstruction(const Instruction *I, 874 FunctionLoweringInfo *FuncInfo) { 875 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 876 !isa<TerminatorInst>(I) && // Terminators aren't folded. 877 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 878 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 879 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 880} 881 882#ifndef NDEBUG 883// Collect per Instruction statistics for fast-isel misses. Only those 884// instructions that cause the bail are accounted for. It does not account for 885// instructions higher in the block. Thus, summing the per instructions stats 886// will not add up to what is reported by NumFastIselFailures. 887static void collectFailStats(const Instruction *I) { 888 switch (I->getOpcode()) { 889 default: assert (0 && "<Invalid operator> "); 890 891 // Terminators 892 case Instruction::Ret: NumFastIselFailRet++; return; 893 case Instruction::Br: NumFastIselFailBr++; return; 894 case Instruction::Switch: NumFastIselFailSwitch++; return; 895 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 896 case Instruction::Invoke: NumFastIselFailInvoke++; return; 897 case Instruction::Resume: NumFastIselFailResume++; return; 898 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 899 900 // Standard binary operators... 901 case Instruction::Add: NumFastIselFailAdd++; return; 902 case Instruction::FAdd: NumFastIselFailFAdd++; return; 903 case Instruction::Sub: NumFastIselFailSub++; return; 904 case Instruction::FSub: NumFastIselFailFSub++; return; 905 case Instruction::Mul: NumFastIselFailMul++; return; 906 case Instruction::FMul: NumFastIselFailFMul++; return; 907 case Instruction::UDiv: NumFastIselFailUDiv++; return; 908 case Instruction::SDiv: NumFastIselFailSDiv++; return; 909 case Instruction::FDiv: NumFastIselFailFDiv++; return; 910 case Instruction::URem: NumFastIselFailURem++; return; 911 case Instruction::SRem: NumFastIselFailSRem++; return; 912 case Instruction::FRem: NumFastIselFailFRem++; return; 913 914 // Logical operators... 915 case Instruction::And: NumFastIselFailAnd++; return; 916 case Instruction::Or: NumFastIselFailOr++; return; 917 case Instruction::Xor: NumFastIselFailXor++; return; 918 919 // Memory instructions... 920 case Instruction::Alloca: NumFastIselFailAlloca++; return; 921 case Instruction::Load: NumFastIselFailLoad++; return; 922 case Instruction::Store: NumFastIselFailStore++; return; 923 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 924 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 925 case Instruction::Fence: NumFastIselFailFence++; return; 926 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 927 928 // Convert instructions... 929 case Instruction::Trunc: NumFastIselFailTrunc++; return; 930 case Instruction::ZExt: NumFastIselFailZExt++; return; 931 case Instruction::SExt: NumFastIselFailSExt++; return; 932 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 933 case Instruction::FPExt: NumFastIselFailFPExt++; return; 934 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 935 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 936 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 937 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 938 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 939 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 940 case Instruction::BitCast: NumFastIselFailBitCast++; return; 941 942 // Other instructions... 943 case Instruction::ICmp: NumFastIselFailICmp++; return; 944 case Instruction::FCmp: NumFastIselFailFCmp++; return; 945 case Instruction::PHI: NumFastIselFailPHI++; return; 946 case Instruction::Select: NumFastIselFailSelect++; return; 947 case Instruction::Call: NumFastIselFailCall++; return; 948 case Instruction::Shl: NumFastIselFailShl++; return; 949 case Instruction::LShr: NumFastIselFailLShr++; return; 950 case Instruction::AShr: NumFastIselFailAShr++; return; 951 case Instruction::VAArg: NumFastIselFailVAArg++; return; 952 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 953 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 954 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 955 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 956 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 957 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 958 } 959} 960#endif 961 962void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 963 // Initialize the Fast-ISel state, if needed. 964 FastISel *FastIS = 0; 965 if (TM.Options.EnableFastISel) 966 FastIS = TLI.createFastISel(*FuncInfo); 967 968 // Iterate over all basic blocks in the function. 969 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 970 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 971 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 972 const BasicBlock *LLVMBB = *I; 973 974 if (OptLevel != CodeGenOpt::None) { 975 bool AllPredsVisited = true; 976 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 977 PI != PE; ++PI) { 978 if (!FuncInfo->VisitedBBs.count(*PI)) { 979 AllPredsVisited = false; 980 break; 981 } 982 } 983 984 if (AllPredsVisited) { 985 for (BasicBlock::const_iterator I = LLVMBB->begin(); 986 isa<PHINode>(I); ++I) 987 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I)); 988 } else { 989 for (BasicBlock::const_iterator I = LLVMBB->begin(); 990 isa<PHINode>(I); ++I) 991 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I)); 992 } 993 994 FuncInfo->VisitedBBs.insert(LLVMBB); 995 } 996 997 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 998 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 999 1000 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 1001 BasicBlock::const_iterator const End = LLVMBB->end(); 1002 BasicBlock::const_iterator BI = End; 1003 1004 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1005 1006 // Setup an EH landing-pad block. 1007 if (FuncInfo->MBB->isLandingPad()) 1008 PrepareEHLandingPad(); 1009 1010 // Lower any arguments needed in this block if this is the entry block. 1011 if (LLVMBB == &Fn.getEntryBlock()) 1012 LowerArguments(LLVMBB); 1013 1014 // Before doing SelectionDAG ISel, see if FastISel has been requested. 1015 if (FastIS) { 1016 FastIS->startNewBlock(); 1017 1018 // Emit code for any incoming arguments. This must happen before 1019 // beginning FastISel on the entry block. 1020 if (LLVMBB == &Fn.getEntryBlock()) { 1021 CurDAG->setRoot(SDB->getControlRoot()); 1022 SDB->clear(); 1023 CodeGenAndEmitDAG(); 1024 1025 // If we inserted any instructions at the beginning, make a note of 1026 // where they are, so we can be sure to emit subsequent instructions 1027 // after them. 1028 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1029 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 1030 else 1031 FastIS->setLastLocalValue(0); 1032 } 1033 1034 unsigned NumFastIselRemaining = std::distance(Begin, End); 1035 // Do FastISel on as many instructions as possible. 1036 for (; BI != Begin; --BI) { 1037 const Instruction *Inst = llvm::prior(BI); 1038 1039 // If we no longer require this instruction, skip it. 1040 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1041 --NumFastIselRemaining; 1042 continue; 1043 } 1044 1045 // Bottom-up: reset the insert pos at the top, after any local-value 1046 // instructions. 1047 FastIS->recomputeInsertPt(); 1048 1049 // Try to select the instruction with FastISel. 1050 if (FastIS->SelectInstruction(Inst)) { 1051 --NumFastIselRemaining; 1052 ++NumFastIselSuccess; 1053 // If fast isel succeeded, skip over all the folded instructions, and 1054 // then see if there is a load right before the selected instructions. 1055 // Try to fold the load if so. 1056 const Instruction *BeforeInst = Inst; 1057 while (BeforeInst != Begin) { 1058 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 1059 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1060 break; 1061 } 1062 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1063 BeforeInst->hasOneUse() && 1064 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) { 1065 // If we succeeded, don't re-select the load. 1066 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 1067 --NumFastIselRemaining; 1068 ++NumFastIselSuccess; 1069 } 1070 continue; 1071 } 1072 1073#ifndef NDEBUG 1074 if (EnableFastISelVerbose2) 1075 collectFailStats(Inst); 1076#endif 1077 1078 // Then handle certain instructions as single-LLVM-Instruction blocks. 1079 if (isa<CallInst>(Inst)) { 1080 1081 if (EnableFastISelVerbose || EnableFastISelAbort) { 1082 dbgs() << "FastISel missed call: "; 1083 Inst->dump(); 1084 } 1085 1086 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1087 unsigned &R = FuncInfo->ValueMap[Inst]; 1088 if (!R) 1089 R = FuncInfo->CreateRegs(Inst->getType()); 1090 } 1091 1092 bool HadTailCall = false; 1093 SelectBasicBlock(Inst, BI, HadTailCall); 1094 1095 // Recompute NumFastIselRemaining as Selection DAG instruction 1096 // selection may have handled the call, input args, etc. 1097 unsigned RemainingNow = std::distance(Begin, BI); 1098 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1099 1100 // If the call was emitted as a tail call, we're done with the block. 1101 if (HadTailCall) { 1102 --BI; 1103 break; 1104 } 1105 1106 NumFastIselRemaining = RemainingNow; 1107 continue; 1108 } 1109 1110 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1111 // Don't abort, and use a different message for terminator misses. 1112 NumFastIselFailures += NumFastIselRemaining; 1113 if (EnableFastISelVerbose || EnableFastISelAbort) { 1114 dbgs() << "FastISel missed terminator: "; 1115 Inst->dump(); 1116 } 1117 } else { 1118 NumFastIselFailures += NumFastIselRemaining; 1119 if (EnableFastISelVerbose || EnableFastISelAbort) { 1120 dbgs() << "FastISel miss: "; 1121 Inst->dump(); 1122 } 1123 if (EnableFastISelAbort) 1124 // The "fast" selector couldn't handle something and bailed. 1125 // For the purpose of debugging, just abort. 1126 llvm_unreachable("FastISel didn't select the entire block"); 1127 } 1128 break; 1129 } 1130 1131 FastIS->recomputeInsertPt(); 1132 } 1133 1134 if (Begin != BI) 1135 ++NumDAGBlocks; 1136 else 1137 ++NumFastIselBlocks; 1138 1139 if (Begin != BI) { 1140 // Run SelectionDAG instruction selection on the remainder of the block 1141 // not handled by FastISel. If FastISel is not run, this is the entire 1142 // block. 1143 bool HadTailCall; 1144 SelectBasicBlock(Begin, BI, HadTailCall); 1145 } 1146 1147 FinishBasicBlock(); 1148 FuncInfo->PHINodesToUpdate.clear(); 1149 } 1150 1151 delete FastIS; 1152 SDB->clearDanglingDebugInfo(); 1153} 1154 1155void 1156SelectionDAGISel::FinishBasicBlock() { 1157 1158 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1159 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1160 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1161 dbgs() << "Node " << i << " : (" 1162 << FuncInfo->PHINodesToUpdate[i].first 1163 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1164 1165 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1166 // PHI nodes in successors. 1167 if (SDB->SwitchCases.empty() && 1168 SDB->JTCases.empty() && 1169 SDB->BitTestCases.empty()) { 1170 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1171 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1172 assert(PHI->isPHI() && 1173 "This is not a machine PHI node that we are updating!"); 1174 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1175 continue; 1176 PHI->addOperand( 1177 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1178 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1179 } 1180 return; 1181 } 1182 1183 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1184 // Lower header first, if it wasn't already lowered 1185 if (!SDB->BitTestCases[i].Emitted) { 1186 // Set the current basic block to the mbb we wish to insert the code into 1187 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1188 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1189 // Emit the code 1190 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1191 CurDAG->setRoot(SDB->getRoot()); 1192 SDB->clear(); 1193 CodeGenAndEmitDAG(); 1194 } 1195 1196 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1197 // Set the current basic block to the mbb we wish to insert the code into 1198 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1199 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1200 // Emit the code 1201 if (j+1 != ej) 1202 SDB->visitBitTestCase(SDB->BitTestCases[i], 1203 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1204 SDB->BitTestCases[i].Reg, 1205 SDB->BitTestCases[i].Cases[j], 1206 FuncInfo->MBB); 1207 else 1208 SDB->visitBitTestCase(SDB->BitTestCases[i], 1209 SDB->BitTestCases[i].Default, 1210 SDB->BitTestCases[i].Reg, 1211 SDB->BitTestCases[i].Cases[j], 1212 FuncInfo->MBB); 1213 1214 1215 CurDAG->setRoot(SDB->getRoot()); 1216 SDB->clear(); 1217 CodeGenAndEmitDAG(); 1218 } 1219 1220 // Update PHI Nodes 1221 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1222 pi != pe; ++pi) { 1223 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1224 MachineBasicBlock *PHIBB = PHI->getParent(); 1225 assert(PHI->isPHI() && 1226 "This is not a machine PHI node that we are updating!"); 1227 // This is "default" BB. We have two jumps to it. From "header" BB and 1228 // from last "case" BB. 1229 if (PHIBB == SDB->BitTestCases[i].Default) { 1230 PHI->addOperand(MachineOperand:: 1231 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1232 false)); 1233 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1234 PHI->addOperand(MachineOperand:: 1235 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1236 false)); 1237 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1238 back().ThisBB)); 1239 } 1240 // One of "cases" BB. 1241 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1242 j != ej; ++j) { 1243 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1244 if (cBB->isSuccessor(PHIBB)) { 1245 PHI->addOperand(MachineOperand:: 1246 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1247 false)); 1248 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1249 } 1250 } 1251 } 1252 } 1253 SDB->BitTestCases.clear(); 1254 1255 // If the JumpTable record is filled in, then we need to emit a jump table. 1256 // Updating the PHI nodes is tricky in this case, since we need to determine 1257 // whether the PHI is a successor of the range check MBB or the jump table MBB 1258 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1259 // Lower header first, if it wasn't already lowered 1260 if (!SDB->JTCases[i].first.Emitted) { 1261 // Set the current basic block to the mbb we wish to insert the code into 1262 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1263 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1264 // Emit the code 1265 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1266 FuncInfo->MBB); 1267 CurDAG->setRoot(SDB->getRoot()); 1268 SDB->clear(); 1269 CodeGenAndEmitDAG(); 1270 } 1271 1272 // Set the current basic block to the mbb we wish to insert the code into 1273 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1274 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1275 // Emit the code 1276 SDB->visitJumpTable(SDB->JTCases[i].second); 1277 CurDAG->setRoot(SDB->getRoot()); 1278 SDB->clear(); 1279 CodeGenAndEmitDAG(); 1280 1281 // Update PHI Nodes 1282 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1283 pi != pe; ++pi) { 1284 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1285 MachineBasicBlock *PHIBB = PHI->getParent(); 1286 assert(PHI->isPHI() && 1287 "This is not a machine PHI node that we are updating!"); 1288 // "default" BB. We can go there only from header BB. 1289 if (PHIBB == SDB->JTCases[i].second.Default) { 1290 PHI->addOperand 1291 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1292 false)); 1293 PHI->addOperand 1294 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1295 } 1296 // JT BB. Just iterate over successors here 1297 if (FuncInfo->MBB->isSuccessor(PHIBB)) { 1298 PHI->addOperand 1299 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1300 false)); 1301 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1302 } 1303 } 1304 } 1305 SDB->JTCases.clear(); 1306 1307 // If the switch block involved a branch to one of the actual successors, we 1308 // need to update PHI nodes in that block. 1309 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1310 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1311 assert(PHI->isPHI() && 1312 "This is not a machine PHI node that we are updating!"); 1313 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) { 1314 PHI->addOperand( 1315 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1316 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1317 } 1318 } 1319 1320 // If we generated any switch lowering information, build and codegen any 1321 // additional DAGs necessary. 1322 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1323 // Set the current basic block to the mbb we wish to insert the code into 1324 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1325 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1326 1327 // Determine the unique successors. 1328 SmallVector<MachineBasicBlock *, 2> Succs; 1329 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1330 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1331 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1332 1333 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1334 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1335 CurDAG->setRoot(SDB->getRoot()); 1336 SDB->clear(); 1337 CodeGenAndEmitDAG(); 1338 1339 // Remember the last block, now that any splitting is done, for use in 1340 // populating PHI nodes in successors. 1341 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1342 1343 // Handle any PHI nodes in successors of this chunk, as if we were coming 1344 // from the original BB before switch expansion. Note that PHI nodes can 1345 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1346 // handle them the right number of times. 1347 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1348 FuncInfo->MBB = Succs[i]; 1349 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1350 // FuncInfo->MBB may have been removed from the CFG if a branch was 1351 // constant folded. 1352 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1353 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin(); 1354 Phi != FuncInfo->MBB->end() && Phi->isPHI(); 1355 ++Phi) { 1356 // This value for this PHI node is recorded in PHINodesToUpdate. 1357 for (unsigned pn = 0; ; ++pn) { 1358 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1359 "Didn't find PHI entry!"); 1360 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 1361 Phi->addOperand(MachineOperand:: 1362 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 1363 false)); 1364 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1365 break; 1366 } 1367 } 1368 } 1369 } 1370 } 1371 } 1372 SDB->SwitchCases.clear(); 1373} 1374 1375 1376/// Create the scheduler. If a specific scheduler was specified 1377/// via the SchedulerRegistry, use it, otherwise select the 1378/// one preferred by the target. 1379/// 1380ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1381 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1382 1383 if (!Ctor) { 1384 Ctor = ISHeuristic; 1385 RegisterScheduler::setDefault(Ctor); 1386 } 1387 1388 return Ctor(this, OptLevel); 1389} 1390 1391//===----------------------------------------------------------------------===// 1392// Helper functions used by the generated instruction selector. 1393//===----------------------------------------------------------------------===// 1394// Calls to these methods are generated by tblgen. 1395 1396/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1397/// the dag combiner simplified the 255, we still want to match. RHS is the 1398/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1399/// specified in the .td file (e.g. 255). 1400bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1401 int64_t DesiredMaskS) const { 1402 const APInt &ActualMask = RHS->getAPIntValue(); 1403 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1404 1405 // If the actual mask exactly matches, success! 1406 if (ActualMask == DesiredMask) 1407 return true; 1408 1409 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1410 if (ActualMask.intersects(~DesiredMask)) 1411 return false; 1412 1413 // Otherwise, the DAG Combiner may have proven that the value coming in is 1414 // either already zero or is not demanded. Check for known zero input bits. 1415 APInt NeededMask = DesiredMask & ~ActualMask; 1416 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1417 return true; 1418 1419 // TODO: check to see if missing bits are just not demanded. 1420 1421 // Otherwise, this pattern doesn't match. 1422 return false; 1423} 1424 1425/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1426/// the dag combiner simplified the 255, we still want to match. RHS is the 1427/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1428/// specified in the .td file (e.g. 255). 1429bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1430 int64_t DesiredMaskS) const { 1431 const APInt &ActualMask = RHS->getAPIntValue(); 1432 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1433 1434 // If the actual mask exactly matches, success! 1435 if (ActualMask == DesiredMask) 1436 return true; 1437 1438 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1439 if (ActualMask.intersects(~DesiredMask)) 1440 return false; 1441 1442 // Otherwise, the DAG Combiner may have proven that the value coming in is 1443 // either already zero or is not demanded. Check for known zero input bits. 1444 APInt NeededMask = DesiredMask & ~ActualMask; 1445 1446 APInt KnownZero, KnownOne; 1447 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1448 1449 // If all the missing bits in the or are already known to be set, match! 1450 if ((NeededMask & KnownOne) == NeededMask) 1451 return true; 1452 1453 // TODO: check to see if missing bits are just not demanded. 1454 1455 // Otherwise, this pattern doesn't match. 1456 return false; 1457} 1458 1459 1460/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1461/// by tblgen. Others should not call it. 1462void SelectionDAGISel:: 1463SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1464 std::vector<SDValue> InOps; 1465 std::swap(InOps, Ops); 1466 1467 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1468 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1469 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1470 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1471 1472 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1473 if (InOps[e-1].getValueType() == MVT::Glue) 1474 --e; // Don't process a glue operand if it is here. 1475 1476 while (i != e) { 1477 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1478 if (!InlineAsm::isMemKind(Flags)) { 1479 // Just skip over this operand, copying the operands verbatim. 1480 Ops.insert(Ops.end(), InOps.begin()+i, 1481 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1482 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1483 } else { 1484 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1485 "Memory operand with multiple values?"); 1486 // Otherwise, this is a memory operand. Ask the target to select it. 1487 std::vector<SDValue> SelOps; 1488 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1489 report_fatal_error("Could not match memory address. Inline asm" 1490 " failure!"); 1491 1492 // Add this to the output node. 1493 unsigned NewFlags = 1494 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1495 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1496 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1497 i += 2; 1498 } 1499 } 1500 1501 // Add the glue input back if present. 1502 if (e != InOps.size()) 1503 Ops.push_back(InOps.back()); 1504} 1505 1506/// findGlueUse - Return use of MVT::Glue value produced by the specified 1507/// SDNode. 1508/// 1509static SDNode *findGlueUse(SDNode *N) { 1510 unsigned FlagResNo = N->getNumValues()-1; 1511 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1512 SDUse &Use = I.getUse(); 1513 if (Use.getResNo() == FlagResNo) 1514 return Use.getUser(); 1515 } 1516 return NULL; 1517} 1518 1519/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1520/// This function recursively traverses up the operand chain, ignoring 1521/// certain nodes. 1522static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1523 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1524 bool IgnoreChains) { 1525 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1526 // greater than all of its (recursive) operands. If we scan to a point where 1527 // 'use' is smaller than the node we're scanning for, then we know we will 1528 // never find it. 1529 // 1530 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1531 // happen because we scan down to newly selected nodes in the case of glue 1532 // uses. 1533 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1534 return false; 1535 1536 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1537 // won't fail if we scan it again. 1538 if (!Visited.insert(Use)) 1539 return false; 1540 1541 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1542 // Ignore chain uses, they are validated by HandleMergeInputChains. 1543 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1544 continue; 1545 1546 SDNode *N = Use->getOperand(i).getNode(); 1547 if (N == Def) { 1548 if (Use == ImmedUse || Use == Root) 1549 continue; // We are not looking for immediate use. 1550 assert(N != Root); 1551 return true; 1552 } 1553 1554 // Traverse up the operand chain. 1555 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1556 return true; 1557 } 1558 return false; 1559} 1560 1561/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1562/// operand node N of U during instruction selection that starts at Root. 1563bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1564 SDNode *Root) const { 1565 if (OptLevel == CodeGenOpt::None) return false; 1566 return N.hasOneUse(); 1567} 1568 1569/// IsLegalToFold - Returns true if the specific operand node N of 1570/// U can be folded during instruction selection that starts at Root. 1571bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1572 CodeGenOpt::Level OptLevel, 1573 bool IgnoreChains) { 1574 if (OptLevel == CodeGenOpt::None) return false; 1575 1576 // If Root use can somehow reach N through a path that that doesn't contain 1577 // U then folding N would create a cycle. e.g. In the following 1578 // diagram, Root can reach N through X. If N is folded into into Root, then 1579 // X is both a predecessor and a successor of U. 1580 // 1581 // [N*] // 1582 // ^ ^ // 1583 // / \ // 1584 // [U*] [X]? // 1585 // ^ ^ // 1586 // \ / // 1587 // \ / // 1588 // [Root*] // 1589 // 1590 // * indicates nodes to be folded together. 1591 // 1592 // If Root produces glue, then it gets (even more) interesting. Since it 1593 // will be "glued" together with its glue use in the scheduler, we need to 1594 // check if it might reach N. 1595 // 1596 // [N*] // 1597 // ^ ^ // 1598 // / \ // 1599 // [U*] [X]? // 1600 // ^ ^ // 1601 // \ \ // 1602 // \ | // 1603 // [Root*] | // 1604 // ^ | // 1605 // f | // 1606 // | / // 1607 // [Y] / // 1608 // ^ / // 1609 // f / // 1610 // | / // 1611 // [GU] // 1612 // 1613 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1614 // (call it Fold), then X is a predecessor of GU and a successor of 1615 // Fold. But since Fold and GU are glued together, this will create 1616 // a cycle in the scheduling graph. 1617 1618 // If the node has glue, walk down the graph to the "lowest" node in the 1619 // glueged set. 1620 EVT VT = Root->getValueType(Root->getNumValues()-1); 1621 while (VT == MVT::Glue) { 1622 SDNode *GU = findGlueUse(Root); 1623 if (GU == NULL) 1624 break; 1625 Root = GU; 1626 VT = Root->getValueType(Root->getNumValues()-1); 1627 1628 // If our query node has a glue result with a use, we've walked up it. If 1629 // the user (which has already been selected) has a chain or indirectly uses 1630 // the chain, our WalkChainUsers predicate will not consider it. Because of 1631 // this, we cannot ignore chains in this predicate. 1632 IgnoreChains = false; 1633 } 1634 1635 1636 SmallPtrSet<SDNode*, 16> Visited; 1637 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1638} 1639 1640SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1641 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1642 SelectInlineAsmMemoryOperands(Ops); 1643 1644 std::vector<EVT> VTs; 1645 VTs.push_back(MVT::Other); 1646 VTs.push_back(MVT::Glue); 1647 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1648 VTs, &Ops[0], Ops.size()); 1649 New->setNodeId(-1); 1650 return New.getNode(); 1651} 1652 1653SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1654 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1655} 1656 1657/// GetVBR - decode a vbr encoding whose top bit is set. 1658LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1659GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1660 assert(Val >= 128 && "Not a VBR"); 1661 Val &= 127; // Remove first vbr bit. 1662 1663 unsigned Shift = 7; 1664 uint64_t NextBits; 1665 do { 1666 NextBits = MatcherTable[Idx++]; 1667 Val |= (NextBits&127) << Shift; 1668 Shift += 7; 1669 } while (NextBits & 128); 1670 1671 return Val; 1672} 1673 1674 1675/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1676/// interior glue and chain results to use the new glue and chain results. 1677void SelectionDAGISel:: 1678UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1679 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1680 SDValue InputGlue, 1681 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1682 bool isMorphNodeTo) { 1683 SmallVector<SDNode*, 4> NowDeadNodes; 1684 1685 ISelUpdater ISU(ISelPosition); 1686 1687 // Now that all the normal results are replaced, we replace the chain and 1688 // glue results if present. 1689 if (!ChainNodesMatched.empty()) { 1690 assert(InputChain.getNode() != 0 && 1691 "Matched input chains but didn't produce a chain"); 1692 // Loop over all of the nodes we matched that produced a chain result. 1693 // Replace all the chain results with the final chain we ended up with. 1694 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1695 SDNode *ChainNode = ChainNodesMatched[i]; 1696 1697 // If this node was already deleted, don't look at it. 1698 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1699 continue; 1700 1701 // Don't replace the results of the root node if we're doing a 1702 // MorphNodeTo. 1703 if (ChainNode == NodeToMatch && isMorphNodeTo) 1704 continue; 1705 1706 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1707 if (ChainVal.getValueType() == MVT::Glue) 1708 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1709 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1710 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1711 1712 // If the node became dead and we haven't already seen it, delete it. 1713 if (ChainNode->use_empty() && 1714 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1715 NowDeadNodes.push_back(ChainNode); 1716 } 1717 } 1718 1719 // If the result produces glue, update any glue results in the matched 1720 // pattern with the glue result. 1721 if (InputGlue.getNode() != 0) { 1722 // Handle any interior nodes explicitly marked. 1723 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1724 SDNode *FRN = GlueResultNodesMatched[i]; 1725 1726 // If this node was already deleted, don't look at it. 1727 if (FRN->getOpcode() == ISD::DELETED_NODE) 1728 continue; 1729 1730 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1731 "Doesn't have a glue result"); 1732 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1733 InputGlue, &ISU); 1734 1735 // If the node became dead and we haven't already seen it, delete it. 1736 if (FRN->use_empty() && 1737 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1738 NowDeadNodes.push_back(FRN); 1739 } 1740 } 1741 1742 if (!NowDeadNodes.empty()) 1743 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1744 1745 DEBUG(errs() << "ISEL: Match complete!\n"); 1746} 1747 1748enum ChainResult { 1749 CR_Simple, 1750 CR_InducesCycle, 1751 CR_LeadsToInteriorNode 1752}; 1753 1754/// WalkChainUsers - Walk down the users of the specified chained node that is 1755/// part of the pattern we're matching, looking at all of the users we find. 1756/// This determines whether something is an interior node, whether we have a 1757/// non-pattern node in between two pattern nodes (which prevent folding because 1758/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1759/// between pattern nodes (in which case the TF becomes part of the pattern). 1760/// 1761/// The walk we do here is guaranteed to be small because we quickly get down to 1762/// already selected nodes "below" us. 1763static ChainResult 1764WalkChainUsers(SDNode *ChainedNode, 1765 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1766 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1767 ChainResult Result = CR_Simple; 1768 1769 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1770 E = ChainedNode->use_end(); UI != E; ++UI) { 1771 // Make sure the use is of the chain, not some other value we produce. 1772 if (UI.getUse().getValueType() != MVT::Other) continue; 1773 1774 SDNode *User = *UI; 1775 1776 // If we see an already-selected machine node, then we've gone beyond the 1777 // pattern that we're selecting down into the already selected chunk of the 1778 // DAG. 1779 if (User->isMachineOpcode() || 1780 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1781 continue; 1782 1783 if (User->getOpcode() == ISD::CopyToReg || 1784 User->getOpcode() == ISD::CopyFromReg || 1785 User->getOpcode() == ISD::INLINEASM || 1786 User->getOpcode() == ISD::EH_LABEL) { 1787 // If their node ID got reset to -1 then they've already been selected. 1788 // Treat them like a MachineOpcode. 1789 if (User->getNodeId() == -1) 1790 continue; 1791 } 1792 1793 // If we have a TokenFactor, we handle it specially. 1794 if (User->getOpcode() != ISD::TokenFactor) { 1795 // If the node isn't a token factor and isn't part of our pattern, then it 1796 // must be a random chained node in between two nodes we're selecting. 1797 // This happens when we have something like: 1798 // x = load ptr 1799 // call 1800 // y = x+4 1801 // store y -> ptr 1802 // Because we structurally match the load/store as a read/modify/write, 1803 // but the call is chained between them. We cannot fold in this case 1804 // because it would induce a cycle in the graph. 1805 if (!std::count(ChainedNodesInPattern.begin(), 1806 ChainedNodesInPattern.end(), User)) 1807 return CR_InducesCycle; 1808 1809 // Otherwise we found a node that is part of our pattern. For example in: 1810 // x = load ptr 1811 // y = x+4 1812 // store y -> ptr 1813 // This would happen when we're scanning down from the load and see the 1814 // store as a user. Record that there is a use of ChainedNode that is 1815 // part of the pattern and keep scanning uses. 1816 Result = CR_LeadsToInteriorNode; 1817 InteriorChainedNodes.push_back(User); 1818 continue; 1819 } 1820 1821 // If we found a TokenFactor, there are two cases to consider: first if the 1822 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1823 // uses of the TF are in our pattern) we just want to ignore it. Second, 1824 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1825 // [Load chain] 1826 // ^ 1827 // | 1828 // [Load] 1829 // ^ ^ 1830 // | \ DAG's like cheese 1831 // / \ do you? 1832 // / | 1833 // [TokenFactor] [Op] 1834 // ^ ^ 1835 // | | 1836 // \ / 1837 // \ / 1838 // [Store] 1839 // 1840 // In this case, the TokenFactor becomes part of our match and we rewrite it 1841 // as a new TokenFactor. 1842 // 1843 // To distinguish these two cases, do a recursive walk down the uses. 1844 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1845 case CR_Simple: 1846 // If the uses of the TokenFactor are just already-selected nodes, ignore 1847 // it, it is "below" our pattern. 1848 continue; 1849 case CR_InducesCycle: 1850 // If the uses of the TokenFactor lead to nodes that are not part of our 1851 // pattern that are not selected, folding would turn this into a cycle, 1852 // bail out now. 1853 return CR_InducesCycle; 1854 case CR_LeadsToInteriorNode: 1855 break; // Otherwise, keep processing. 1856 } 1857 1858 // Okay, we know we're in the interesting interior case. The TokenFactor 1859 // is now going to be considered part of the pattern so that we rewrite its 1860 // uses (it may have uses that are not part of the pattern) with the 1861 // ultimate chain result of the generated code. We will also add its chain 1862 // inputs as inputs to the ultimate TokenFactor we create. 1863 Result = CR_LeadsToInteriorNode; 1864 ChainedNodesInPattern.push_back(User); 1865 InteriorChainedNodes.push_back(User); 1866 continue; 1867 } 1868 1869 return Result; 1870} 1871 1872/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1873/// operation for when the pattern matched at least one node with a chains. The 1874/// input vector contains a list of all of the chained nodes that we match. We 1875/// must determine if this is a valid thing to cover (i.e. matching it won't 1876/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1877/// be used as the input node chain for the generated nodes. 1878static SDValue 1879HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1880 SelectionDAG *CurDAG) { 1881 // Walk all of the chained nodes we've matched, recursively scanning down the 1882 // users of the chain result. This adds any TokenFactor nodes that are caught 1883 // in between chained nodes to the chained and interior nodes list. 1884 SmallVector<SDNode*, 3> InteriorChainedNodes; 1885 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1886 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1887 InteriorChainedNodes) == CR_InducesCycle) 1888 return SDValue(); // Would induce a cycle. 1889 } 1890 1891 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1892 // that we are interested in. Form our input TokenFactor node. 1893 SmallVector<SDValue, 3> InputChains; 1894 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1895 // Add the input chain of this node to the InputChains list (which will be 1896 // the operands of the generated TokenFactor) if it's not an interior node. 1897 SDNode *N = ChainNodesMatched[i]; 1898 if (N->getOpcode() != ISD::TokenFactor) { 1899 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1900 continue; 1901 1902 // Otherwise, add the input chain. 1903 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1904 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1905 InputChains.push_back(InChain); 1906 continue; 1907 } 1908 1909 // If we have a token factor, we want to add all inputs of the token factor 1910 // that are not part of the pattern we're matching. 1911 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1912 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1913 N->getOperand(op).getNode())) 1914 InputChains.push_back(N->getOperand(op)); 1915 } 1916 } 1917 1918 SDValue Res; 1919 if (InputChains.size() == 1) 1920 return InputChains[0]; 1921 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1922 MVT::Other, &InputChains[0], InputChains.size()); 1923} 1924 1925/// MorphNode - Handle morphing a node in place for the selector. 1926SDNode *SelectionDAGISel:: 1927MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1928 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1929 // It is possible we're using MorphNodeTo to replace a node with no 1930 // normal results with one that has a normal result (or we could be 1931 // adding a chain) and the input could have glue and chains as well. 1932 // In this case we need to shift the operands down. 1933 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1934 // than the old isel though. 1935 int OldGlueResultNo = -1, OldChainResultNo = -1; 1936 1937 unsigned NTMNumResults = Node->getNumValues(); 1938 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 1939 OldGlueResultNo = NTMNumResults-1; 1940 if (NTMNumResults != 1 && 1941 Node->getValueType(NTMNumResults-2) == MVT::Other) 1942 OldChainResultNo = NTMNumResults-2; 1943 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1944 OldChainResultNo = NTMNumResults-1; 1945 1946 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1947 // that this deletes operands of the old node that become dead. 1948 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1949 1950 // MorphNodeTo can operate in two ways: if an existing node with the 1951 // specified operands exists, it can just return it. Otherwise, it 1952 // updates the node in place to have the requested operands. 1953 if (Res == Node) { 1954 // If we updated the node in place, reset the node ID. To the isel, 1955 // this should be just like a newly allocated machine node. 1956 Res->setNodeId(-1); 1957 } 1958 1959 unsigned ResNumResults = Res->getNumValues(); 1960 // Move the glue if needed. 1961 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 1962 (unsigned)OldGlueResultNo != ResNumResults-1) 1963 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 1964 SDValue(Res, ResNumResults-1)); 1965 1966 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 1967 --ResNumResults; 1968 1969 // Move the chain reference if needed. 1970 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1971 (unsigned)OldChainResultNo != ResNumResults-1) 1972 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1973 SDValue(Res, ResNumResults-1)); 1974 1975 // Otherwise, no replacement happened because the node already exists. Replace 1976 // Uses of the old node with the new one. 1977 if (Res != Node) 1978 CurDAG->ReplaceAllUsesWith(Node, Res); 1979 1980 return Res; 1981} 1982 1983/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1984LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1985CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1986 SDValue N, 1987 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1988 // Accept if it is exactly the same as a previously recorded node. 1989 unsigned RecNo = MatcherTable[MatcherIndex++]; 1990 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1991 return N == RecordedNodes[RecNo].first; 1992} 1993 1994/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1995LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1996CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1997 SelectionDAGISel &SDISel) { 1998 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1999} 2000 2001/// CheckNodePredicate - Implements OP_CheckNodePredicate. 2002LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2003CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2004 SelectionDAGISel &SDISel, SDNode *N) { 2005 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2006} 2007 2008LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2009CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2010 SDNode *N) { 2011 uint16_t Opc = MatcherTable[MatcherIndex++]; 2012 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2013 return N->getOpcode() == Opc; 2014} 2015 2016LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2017CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2018 SDValue N, const TargetLowering &TLI) { 2019 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2020 if (N.getValueType() == VT) return true; 2021 2022 // Handle the case when VT is iPTR. 2023 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 2024} 2025 2026LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2027CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2028 SDValue N, const TargetLowering &TLI, 2029 unsigned ChildNo) { 2030 if (ChildNo >= N.getNumOperands()) 2031 return false; // Match fails if out of range child #. 2032 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2033} 2034 2035 2036LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2037CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2038 SDValue N) { 2039 return cast<CondCodeSDNode>(N)->get() == 2040 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2041} 2042 2043LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2044CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2045 SDValue N, const TargetLowering &TLI) { 2046 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2047 if (cast<VTSDNode>(N)->getVT() == VT) 2048 return true; 2049 2050 // Handle the case when VT is iPTR. 2051 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 2052} 2053 2054LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2055CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2056 SDValue N) { 2057 int64_t Val = MatcherTable[MatcherIndex++]; 2058 if (Val & 128) 2059 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2060 2061 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2062 return C != 0 && C->getSExtValue() == Val; 2063} 2064 2065LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2066CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2067 SDValue N, SelectionDAGISel &SDISel) { 2068 int64_t Val = MatcherTable[MatcherIndex++]; 2069 if (Val & 128) 2070 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2071 2072 if (N->getOpcode() != ISD::AND) return false; 2073 2074 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2075 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2076} 2077 2078LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2079CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2080 SDValue N, SelectionDAGISel &SDISel) { 2081 int64_t Val = MatcherTable[MatcherIndex++]; 2082 if (Val & 128) 2083 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2084 2085 if (N->getOpcode() != ISD::OR) return false; 2086 2087 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2088 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2089} 2090 2091/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2092/// scope, evaluate the current node. If the current predicate is known to 2093/// fail, set Result=true and return anything. If the current predicate is 2094/// known to pass, set Result=false and return the MatcherIndex to continue 2095/// with. If the current predicate is unknown, set Result=false and return the 2096/// MatcherIndex to continue with. 2097static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2098 unsigned Index, SDValue N, 2099 bool &Result, SelectionDAGISel &SDISel, 2100 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2101 switch (Table[Index++]) { 2102 default: 2103 Result = false; 2104 return Index-1; // Could not evaluate this predicate. 2105 case SelectionDAGISel::OPC_CheckSame: 2106 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2107 return Index; 2108 case SelectionDAGISel::OPC_CheckPatternPredicate: 2109 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2110 return Index; 2111 case SelectionDAGISel::OPC_CheckPredicate: 2112 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2113 return Index; 2114 case SelectionDAGISel::OPC_CheckOpcode: 2115 Result = !::CheckOpcode(Table, Index, N.getNode()); 2116 return Index; 2117 case SelectionDAGISel::OPC_CheckType: 2118 Result = !::CheckType(Table, Index, N, SDISel.TLI); 2119 return Index; 2120 case SelectionDAGISel::OPC_CheckChild0Type: 2121 case SelectionDAGISel::OPC_CheckChild1Type: 2122 case SelectionDAGISel::OPC_CheckChild2Type: 2123 case SelectionDAGISel::OPC_CheckChild3Type: 2124 case SelectionDAGISel::OPC_CheckChild4Type: 2125 case SelectionDAGISel::OPC_CheckChild5Type: 2126 case SelectionDAGISel::OPC_CheckChild6Type: 2127 case SelectionDAGISel::OPC_CheckChild7Type: 2128 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 2129 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2130 return Index; 2131 case SelectionDAGISel::OPC_CheckCondCode: 2132 Result = !::CheckCondCode(Table, Index, N); 2133 return Index; 2134 case SelectionDAGISel::OPC_CheckValueType: 2135 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2136 return Index; 2137 case SelectionDAGISel::OPC_CheckInteger: 2138 Result = !::CheckInteger(Table, Index, N); 2139 return Index; 2140 case SelectionDAGISel::OPC_CheckAndImm: 2141 Result = !::CheckAndImm(Table, Index, N, SDISel); 2142 return Index; 2143 case SelectionDAGISel::OPC_CheckOrImm: 2144 Result = !::CheckOrImm(Table, Index, N, SDISel); 2145 return Index; 2146 } 2147} 2148 2149namespace { 2150 2151struct MatchScope { 2152 /// FailIndex - If this match fails, this is the index to continue with. 2153 unsigned FailIndex; 2154 2155 /// NodeStack - The node stack when the scope was formed. 2156 SmallVector<SDValue, 4> NodeStack; 2157 2158 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2159 unsigned NumRecordedNodes; 2160 2161 /// NumMatchedMemRefs - The number of matched memref entries. 2162 unsigned NumMatchedMemRefs; 2163 2164 /// InputChain/InputGlue - The current chain/glue 2165 SDValue InputChain, InputGlue; 2166 2167 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2168 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2169}; 2170 2171} 2172 2173SDNode *SelectionDAGISel:: 2174SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2175 unsigned TableSize) { 2176 // FIXME: Should these even be selected? Handle these cases in the caller? 2177 switch (NodeToMatch->getOpcode()) { 2178 default: 2179 break; 2180 case ISD::EntryToken: // These nodes remain the same. 2181 case ISD::BasicBlock: 2182 case ISD::Register: 2183 case ISD::RegisterMask: 2184 //case ISD::VALUETYPE: 2185 //case ISD::CONDCODE: 2186 case ISD::HANDLENODE: 2187 case ISD::MDNODE_SDNODE: 2188 case ISD::TargetConstant: 2189 case ISD::TargetConstantFP: 2190 case ISD::TargetConstantPool: 2191 case ISD::TargetFrameIndex: 2192 case ISD::TargetExternalSymbol: 2193 case ISD::TargetBlockAddress: 2194 case ISD::TargetJumpTable: 2195 case ISD::TargetGlobalTLSAddress: 2196 case ISD::TargetGlobalAddress: 2197 case ISD::TokenFactor: 2198 case ISD::CopyFromReg: 2199 case ISD::CopyToReg: 2200 case ISD::EH_LABEL: 2201 NodeToMatch->setNodeId(-1); // Mark selected. 2202 return 0; 2203 case ISD::AssertSext: 2204 case ISD::AssertZext: 2205 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2206 NodeToMatch->getOperand(0)); 2207 return 0; 2208 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2209 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2210 } 2211 2212 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2213 2214 // Set up the node stack with NodeToMatch as the only node on the stack. 2215 SmallVector<SDValue, 8> NodeStack; 2216 SDValue N = SDValue(NodeToMatch, 0); 2217 NodeStack.push_back(N); 2218 2219 // MatchScopes - Scopes used when matching, if a match failure happens, this 2220 // indicates where to continue checking. 2221 SmallVector<MatchScope, 8> MatchScopes; 2222 2223 // RecordedNodes - This is the set of nodes that have been recorded by the 2224 // state machine. The second value is the parent of the node, or null if the 2225 // root is recorded. 2226 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2227 2228 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2229 // pattern. 2230 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2231 2232 // These are the current input chain and glue for use when generating nodes. 2233 // Various Emit operations change these. For example, emitting a copytoreg 2234 // uses and updates these. 2235 SDValue InputChain, InputGlue; 2236 2237 // ChainNodesMatched - If a pattern matches nodes that have input/output 2238 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2239 // which ones they are. The result is captured into this list so that we can 2240 // update the chain results when the pattern is complete. 2241 SmallVector<SDNode*, 3> ChainNodesMatched; 2242 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2243 2244 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2245 NodeToMatch->dump(CurDAG); 2246 errs() << '\n'); 2247 2248 // Determine where to start the interpreter. Normally we start at opcode #0, 2249 // but if the state machine starts with an OPC_SwitchOpcode, then we 2250 // accelerate the first lookup (which is guaranteed to be hot) with the 2251 // OpcodeOffset table. 2252 unsigned MatcherIndex = 0; 2253 2254 if (!OpcodeOffset.empty()) { 2255 // Already computed the OpcodeOffset table, just index into it. 2256 if (N.getOpcode() < OpcodeOffset.size()) 2257 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2258 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2259 2260 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2261 // Otherwise, the table isn't computed, but the state machine does start 2262 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2263 // is the first time we're selecting an instruction. 2264 unsigned Idx = 1; 2265 while (1) { 2266 // Get the size of this case. 2267 unsigned CaseSize = MatcherTable[Idx++]; 2268 if (CaseSize & 128) 2269 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2270 if (CaseSize == 0) break; 2271 2272 // Get the opcode, add the index to the table. 2273 uint16_t Opc = MatcherTable[Idx++]; 2274 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2275 if (Opc >= OpcodeOffset.size()) 2276 OpcodeOffset.resize((Opc+1)*2); 2277 OpcodeOffset[Opc] = Idx; 2278 Idx += CaseSize; 2279 } 2280 2281 // Okay, do the lookup for the first opcode. 2282 if (N.getOpcode() < OpcodeOffset.size()) 2283 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2284 } 2285 2286 while (1) { 2287 assert(MatcherIndex < TableSize && "Invalid index"); 2288#ifndef NDEBUG 2289 unsigned CurrentOpcodeIndex = MatcherIndex; 2290#endif 2291 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2292 switch (Opcode) { 2293 case OPC_Scope: { 2294 // Okay, the semantics of this operation are that we should push a scope 2295 // then evaluate the first child. However, pushing a scope only to have 2296 // the first check fail (which then pops it) is inefficient. If we can 2297 // determine immediately that the first check (or first several) will 2298 // immediately fail, don't even bother pushing a scope for them. 2299 unsigned FailIndex; 2300 2301 while (1) { 2302 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2303 if (NumToSkip & 128) 2304 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2305 // Found the end of the scope with no match. 2306 if (NumToSkip == 0) { 2307 FailIndex = 0; 2308 break; 2309 } 2310 2311 FailIndex = MatcherIndex+NumToSkip; 2312 2313 unsigned MatcherIndexOfPredicate = MatcherIndex; 2314 (void)MatcherIndexOfPredicate; // silence warning. 2315 2316 // If we can't evaluate this predicate without pushing a scope (e.g. if 2317 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2318 // push the scope and evaluate the full predicate chain. 2319 bool Result; 2320 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2321 Result, *this, RecordedNodes); 2322 if (!Result) 2323 break; 2324 2325 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2326 << "index " << MatcherIndexOfPredicate 2327 << ", continuing at " << FailIndex << "\n"); 2328 ++NumDAGIselRetries; 2329 2330 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2331 // move to the next case. 2332 MatcherIndex = FailIndex; 2333 } 2334 2335 // If the whole scope failed to match, bail. 2336 if (FailIndex == 0) break; 2337 2338 // Push a MatchScope which indicates where to go if the first child fails 2339 // to match. 2340 MatchScope NewEntry; 2341 NewEntry.FailIndex = FailIndex; 2342 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2343 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2344 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2345 NewEntry.InputChain = InputChain; 2346 NewEntry.InputGlue = InputGlue; 2347 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2348 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2349 MatchScopes.push_back(NewEntry); 2350 continue; 2351 } 2352 case OPC_RecordNode: { 2353 // Remember this node, it may end up being an operand in the pattern. 2354 SDNode *Parent = 0; 2355 if (NodeStack.size() > 1) 2356 Parent = NodeStack[NodeStack.size()-2].getNode(); 2357 RecordedNodes.push_back(std::make_pair(N, Parent)); 2358 continue; 2359 } 2360 2361 case OPC_RecordChild0: case OPC_RecordChild1: 2362 case OPC_RecordChild2: case OPC_RecordChild3: 2363 case OPC_RecordChild4: case OPC_RecordChild5: 2364 case OPC_RecordChild6: case OPC_RecordChild7: { 2365 unsigned ChildNo = Opcode-OPC_RecordChild0; 2366 if (ChildNo >= N.getNumOperands()) 2367 break; // Match fails if out of range child #. 2368 2369 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2370 N.getNode())); 2371 continue; 2372 } 2373 case OPC_RecordMemRef: 2374 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2375 continue; 2376 2377 case OPC_CaptureGlueInput: 2378 // If the current node has an input glue, capture it in InputGlue. 2379 if (N->getNumOperands() != 0 && 2380 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2381 InputGlue = N->getOperand(N->getNumOperands()-1); 2382 continue; 2383 2384 case OPC_MoveChild: { 2385 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2386 if (ChildNo >= N.getNumOperands()) 2387 break; // Match fails if out of range child #. 2388 N = N.getOperand(ChildNo); 2389 NodeStack.push_back(N); 2390 continue; 2391 } 2392 2393 case OPC_MoveParent: 2394 // Pop the current node off the NodeStack. 2395 NodeStack.pop_back(); 2396 assert(!NodeStack.empty() && "Node stack imbalance!"); 2397 N = NodeStack.back(); 2398 continue; 2399 2400 case OPC_CheckSame: 2401 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2402 continue; 2403 case OPC_CheckPatternPredicate: 2404 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2405 continue; 2406 case OPC_CheckPredicate: 2407 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2408 N.getNode())) 2409 break; 2410 continue; 2411 case OPC_CheckComplexPat: { 2412 unsigned CPNum = MatcherTable[MatcherIndex++]; 2413 unsigned RecNo = MatcherTable[MatcherIndex++]; 2414 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2415 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2416 RecordedNodes[RecNo].first, CPNum, 2417 RecordedNodes)) 2418 break; 2419 continue; 2420 } 2421 case OPC_CheckOpcode: 2422 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2423 continue; 2424 2425 case OPC_CheckType: 2426 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2427 continue; 2428 2429 case OPC_SwitchOpcode: { 2430 unsigned CurNodeOpcode = N.getOpcode(); 2431 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2432 unsigned CaseSize; 2433 while (1) { 2434 // Get the size of this case. 2435 CaseSize = MatcherTable[MatcherIndex++]; 2436 if (CaseSize & 128) 2437 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2438 if (CaseSize == 0) break; 2439 2440 uint16_t Opc = MatcherTable[MatcherIndex++]; 2441 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2442 2443 // If the opcode matches, then we will execute this case. 2444 if (CurNodeOpcode == Opc) 2445 break; 2446 2447 // Otherwise, skip over this case. 2448 MatcherIndex += CaseSize; 2449 } 2450 2451 // If no cases matched, bail out. 2452 if (CaseSize == 0) break; 2453 2454 // Otherwise, execute the case we found. 2455 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2456 << " to " << MatcherIndex << "\n"); 2457 continue; 2458 } 2459 2460 case OPC_SwitchType: { 2461 MVT CurNodeVT = N.getValueType().getSimpleVT(); 2462 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2463 unsigned CaseSize; 2464 while (1) { 2465 // Get the size of this case. 2466 CaseSize = MatcherTable[MatcherIndex++]; 2467 if (CaseSize & 128) 2468 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2469 if (CaseSize == 0) break; 2470 2471 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2472 if (CaseVT == MVT::iPTR) 2473 CaseVT = TLI.getPointerTy(); 2474 2475 // If the VT matches, then we will execute this case. 2476 if (CurNodeVT == CaseVT) 2477 break; 2478 2479 // Otherwise, skip over this case. 2480 MatcherIndex += CaseSize; 2481 } 2482 2483 // If no cases matched, bail out. 2484 if (CaseSize == 0) break; 2485 2486 // Otherwise, execute the case we found. 2487 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2488 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2489 continue; 2490 } 2491 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2492 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2493 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2494 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2495 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2496 Opcode-OPC_CheckChild0Type)) 2497 break; 2498 continue; 2499 case OPC_CheckCondCode: 2500 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2501 continue; 2502 case OPC_CheckValueType: 2503 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2504 continue; 2505 case OPC_CheckInteger: 2506 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2507 continue; 2508 case OPC_CheckAndImm: 2509 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2510 continue; 2511 case OPC_CheckOrImm: 2512 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2513 continue; 2514 2515 case OPC_CheckFoldableChainNode: { 2516 assert(NodeStack.size() != 1 && "No parent node"); 2517 // Verify that all intermediate nodes between the root and this one have 2518 // a single use. 2519 bool HasMultipleUses = false; 2520 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2521 if (!NodeStack[i].hasOneUse()) { 2522 HasMultipleUses = true; 2523 break; 2524 } 2525 if (HasMultipleUses) break; 2526 2527 // Check to see that the target thinks this is profitable to fold and that 2528 // we can fold it without inducing cycles in the graph. 2529 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2530 NodeToMatch) || 2531 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2532 NodeToMatch, OptLevel, 2533 true/*We validate our own chains*/)) 2534 break; 2535 2536 continue; 2537 } 2538 case OPC_EmitInteger: { 2539 MVT::SimpleValueType VT = 2540 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2541 int64_t Val = MatcherTable[MatcherIndex++]; 2542 if (Val & 128) 2543 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2544 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2545 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2546 continue; 2547 } 2548 case OPC_EmitRegister: { 2549 MVT::SimpleValueType VT = 2550 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2551 unsigned RegNo = MatcherTable[MatcherIndex++]; 2552 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2553 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2554 continue; 2555 } 2556 case OPC_EmitRegister2: { 2557 // For targets w/ more than 256 register names, the register enum 2558 // values are stored in two bytes in the matcher table (just like 2559 // opcodes). 2560 MVT::SimpleValueType VT = 2561 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2562 unsigned RegNo = MatcherTable[MatcherIndex++]; 2563 RegNo |= MatcherTable[MatcherIndex++] << 8; 2564 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2565 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2566 continue; 2567 } 2568 2569 case OPC_EmitConvertToTarget: { 2570 // Convert from IMM/FPIMM to target version. 2571 unsigned RecNo = MatcherTable[MatcherIndex++]; 2572 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2573 SDValue Imm = RecordedNodes[RecNo].first; 2574 2575 if (Imm->getOpcode() == ISD::Constant) { 2576 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2577 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2578 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2579 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2580 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2581 } 2582 2583 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2584 continue; 2585 } 2586 2587 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2588 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2589 // These are space-optimized forms of OPC_EmitMergeInputChains. 2590 assert(InputChain.getNode() == 0 && 2591 "EmitMergeInputChains should be the first chain producing node"); 2592 assert(ChainNodesMatched.empty() && 2593 "Should only have one EmitMergeInputChains per match"); 2594 2595 // Read all of the chained nodes. 2596 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2597 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2598 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2599 2600 // FIXME: What if other value results of the node have uses not matched 2601 // by this pattern? 2602 if (ChainNodesMatched.back() != NodeToMatch && 2603 !RecordedNodes[RecNo].first.hasOneUse()) { 2604 ChainNodesMatched.clear(); 2605 break; 2606 } 2607 2608 // Merge the input chains if they are not intra-pattern references. 2609 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2610 2611 if (InputChain.getNode() == 0) 2612 break; // Failed to merge. 2613 continue; 2614 } 2615 2616 case OPC_EmitMergeInputChains: { 2617 assert(InputChain.getNode() == 0 && 2618 "EmitMergeInputChains should be the first chain producing node"); 2619 // This node gets a list of nodes we matched in the input that have 2620 // chains. We want to token factor all of the input chains to these nodes 2621 // together. However, if any of the input chains is actually one of the 2622 // nodes matched in this pattern, then we have an intra-match reference. 2623 // Ignore these because the newly token factored chain should not refer to 2624 // the old nodes. 2625 unsigned NumChains = MatcherTable[MatcherIndex++]; 2626 assert(NumChains != 0 && "Can't TF zero chains"); 2627 2628 assert(ChainNodesMatched.empty() && 2629 "Should only have one EmitMergeInputChains per match"); 2630 2631 // Read all of the chained nodes. 2632 for (unsigned i = 0; i != NumChains; ++i) { 2633 unsigned RecNo = MatcherTable[MatcherIndex++]; 2634 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2635 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2636 2637 // FIXME: What if other value results of the node have uses not matched 2638 // by this pattern? 2639 if (ChainNodesMatched.back() != NodeToMatch && 2640 !RecordedNodes[RecNo].first.hasOneUse()) { 2641 ChainNodesMatched.clear(); 2642 break; 2643 } 2644 } 2645 2646 // If the inner loop broke out, the match fails. 2647 if (ChainNodesMatched.empty()) 2648 break; 2649 2650 // Merge the input chains if they are not intra-pattern references. 2651 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2652 2653 if (InputChain.getNode() == 0) 2654 break; // Failed to merge. 2655 2656 continue; 2657 } 2658 2659 case OPC_EmitCopyToReg: { 2660 unsigned RecNo = MatcherTable[MatcherIndex++]; 2661 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2662 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2663 2664 if (InputChain.getNode() == 0) 2665 InputChain = CurDAG->getEntryNode(); 2666 2667 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2668 DestPhysReg, RecordedNodes[RecNo].first, 2669 InputGlue); 2670 2671 InputGlue = InputChain.getValue(1); 2672 continue; 2673 } 2674 2675 case OPC_EmitNodeXForm: { 2676 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2677 unsigned RecNo = MatcherTable[MatcherIndex++]; 2678 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2679 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2680 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2681 continue; 2682 } 2683 2684 case OPC_EmitNode: 2685 case OPC_MorphNodeTo: { 2686 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2687 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2688 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2689 // Get the result VT list. 2690 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2691 SmallVector<EVT, 4> VTs; 2692 for (unsigned i = 0; i != NumVTs; ++i) { 2693 MVT::SimpleValueType VT = 2694 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2695 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2696 VTs.push_back(VT); 2697 } 2698 2699 if (EmitNodeInfo & OPFL_Chain) 2700 VTs.push_back(MVT::Other); 2701 if (EmitNodeInfo & OPFL_GlueOutput) 2702 VTs.push_back(MVT::Glue); 2703 2704 // This is hot code, so optimize the two most common cases of 1 and 2 2705 // results. 2706 SDVTList VTList; 2707 if (VTs.size() == 1) 2708 VTList = CurDAG->getVTList(VTs[0]); 2709 else if (VTs.size() == 2) 2710 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2711 else 2712 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2713 2714 // Get the operand list. 2715 unsigned NumOps = MatcherTable[MatcherIndex++]; 2716 SmallVector<SDValue, 8> Ops; 2717 for (unsigned i = 0; i != NumOps; ++i) { 2718 unsigned RecNo = MatcherTable[MatcherIndex++]; 2719 if (RecNo & 128) 2720 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2721 2722 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2723 Ops.push_back(RecordedNodes[RecNo].first); 2724 } 2725 2726 // If there are variadic operands to add, handle them now. 2727 if (EmitNodeInfo & OPFL_VariadicInfo) { 2728 // Determine the start index to copy from. 2729 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2730 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2731 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2732 "Invalid variadic node"); 2733 // Copy all of the variadic operands, not including a potential glue 2734 // input. 2735 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2736 i != e; ++i) { 2737 SDValue V = NodeToMatch->getOperand(i); 2738 if (V.getValueType() == MVT::Glue) break; 2739 Ops.push_back(V); 2740 } 2741 } 2742 2743 // If this has chain/glue inputs, add them. 2744 if (EmitNodeInfo & OPFL_Chain) 2745 Ops.push_back(InputChain); 2746 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2747 Ops.push_back(InputGlue); 2748 2749 // Create the node. 2750 SDNode *Res = 0; 2751 if (Opcode != OPC_MorphNodeTo) { 2752 // If this is a normal EmitNode command, just create the new node and 2753 // add the results to the RecordedNodes list. 2754 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2755 VTList, Ops.data(), Ops.size()); 2756 2757 // Add all the non-glue/non-chain results to the RecordedNodes list. 2758 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2759 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2760 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2761 (SDNode*) 0)); 2762 } 2763 2764 } else { 2765 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2766 EmitNodeInfo); 2767 } 2768 2769 // If the node had chain/glue results, update our notion of the current 2770 // chain and glue. 2771 if (EmitNodeInfo & OPFL_GlueOutput) { 2772 InputGlue = SDValue(Res, VTs.size()-1); 2773 if (EmitNodeInfo & OPFL_Chain) 2774 InputChain = SDValue(Res, VTs.size()-2); 2775 } else if (EmitNodeInfo & OPFL_Chain) 2776 InputChain = SDValue(Res, VTs.size()-1); 2777 2778 // If the OPFL_MemRefs glue is set on this node, slap all of the 2779 // accumulated memrefs onto it. 2780 // 2781 // FIXME: This is vastly incorrect for patterns with multiple outputs 2782 // instructions that access memory and for ComplexPatterns that match 2783 // loads. 2784 if (EmitNodeInfo & OPFL_MemRefs) { 2785 // Only attach load or store memory operands if the generated 2786 // instruction may load or store. 2787 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2788 bool mayLoad = MCID.mayLoad(); 2789 bool mayStore = MCID.mayStore(); 2790 2791 unsigned NumMemRefs = 0; 2792 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2793 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2794 if ((*I)->isLoad()) { 2795 if (mayLoad) 2796 ++NumMemRefs; 2797 } else if ((*I)->isStore()) { 2798 if (mayStore) 2799 ++NumMemRefs; 2800 } else { 2801 ++NumMemRefs; 2802 } 2803 } 2804 2805 MachineSDNode::mmo_iterator MemRefs = 2806 MF->allocateMemRefsArray(NumMemRefs); 2807 2808 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 2809 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2810 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2811 if ((*I)->isLoad()) { 2812 if (mayLoad) 2813 *MemRefsPos++ = *I; 2814 } else if ((*I)->isStore()) { 2815 if (mayStore) 2816 *MemRefsPos++ = *I; 2817 } else { 2818 *MemRefsPos++ = *I; 2819 } 2820 } 2821 2822 cast<MachineSDNode>(Res) 2823 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 2824 } 2825 2826 DEBUG(errs() << " " 2827 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2828 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2829 2830 // If this was a MorphNodeTo then we're completely done! 2831 if (Opcode == OPC_MorphNodeTo) { 2832 // Update chain and glue uses. 2833 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2834 InputGlue, GlueResultNodesMatched, true); 2835 return Res; 2836 } 2837 2838 continue; 2839 } 2840 2841 case OPC_MarkGlueResults: { 2842 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2843 2844 // Read and remember all the glue-result nodes. 2845 for (unsigned i = 0; i != NumNodes; ++i) { 2846 unsigned RecNo = MatcherTable[MatcherIndex++]; 2847 if (RecNo & 128) 2848 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2849 2850 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2851 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2852 } 2853 continue; 2854 } 2855 2856 case OPC_CompleteMatch: { 2857 // The match has been completed, and any new nodes (if any) have been 2858 // created. Patch up references to the matched dag to use the newly 2859 // created nodes. 2860 unsigned NumResults = MatcherTable[MatcherIndex++]; 2861 2862 for (unsigned i = 0; i != NumResults; ++i) { 2863 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2864 if (ResSlot & 128) 2865 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2866 2867 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2868 SDValue Res = RecordedNodes[ResSlot].first; 2869 2870 assert(i < NodeToMatch->getNumValues() && 2871 NodeToMatch->getValueType(i) != MVT::Other && 2872 NodeToMatch->getValueType(i) != MVT::Glue && 2873 "Invalid number of results to complete!"); 2874 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2875 NodeToMatch->getValueType(i) == MVT::iPTR || 2876 Res.getValueType() == MVT::iPTR || 2877 NodeToMatch->getValueType(i).getSizeInBits() == 2878 Res.getValueType().getSizeInBits()) && 2879 "invalid replacement"); 2880 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2881 } 2882 2883 // If the root node defines glue, add it to the glue nodes to update list. 2884 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2885 GlueResultNodesMatched.push_back(NodeToMatch); 2886 2887 // Update chain and glue uses. 2888 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2889 InputGlue, GlueResultNodesMatched, false); 2890 2891 assert(NodeToMatch->use_empty() && 2892 "Didn't replace all uses of the node?"); 2893 2894 // FIXME: We just return here, which interacts correctly with SelectRoot 2895 // above. We should fix this to not return an SDNode* anymore. 2896 return 0; 2897 } 2898 } 2899 2900 // If the code reached this point, then the match failed. See if there is 2901 // another child to try in the current 'Scope', otherwise pop it until we 2902 // find a case to check. 2903 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2904 ++NumDAGIselRetries; 2905 while (1) { 2906 if (MatchScopes.empty()) { 2907 CannotYetSelect(NodeToMatch); 2908 return 0; 2909 } 2910 2911 // Restore the interpreter state back to the point where the scope was 2912 // formed. 2913 MatchScope &LastScope = MatchScopes.back(); 2914 RecordedNodes.resize(LastScope.NumRecordedNodes); 2915 NodeStack.clear(); 2916 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2917 N = NodeStack.back(); 2918 2919 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2920 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2921 MatcherIndex = LastScope.FailIndex; 2922 2923 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2924 2925 InputChain = LastScope.InputChain; 2926 InputGlue = LastScope.InputGlue; 2927 if (!LastScope.HasChainNodesMatched) 2928 ChainNodesMatched.clear(); 2929 if (!LastScope.HasGlueResultNodesMatched) 2930 GlueResultNodesMatched.clear(); 2931 2932 // Check to see what the offset is at the new MatcherIndex. If it is zero 2933 // we have reached the end of this scope, otherwise we have another child 2934 // in the current scope to try. 2935 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2936 if (NumToSkip & 128) 2937 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2938 2939 // If we have another child in this scope to match, update FailIndex and 2940 // try it. 2941 if (NumToSkip != 0) { 2942 LastScope.FailIndex = MatcherIndex+NumToSkip; 2943 break; 2944 } 2945 2946 // End of this scope, pop it and try the next child in the containing 2947 // scope. 2948 MatchScopes.pop_back(); 2949 } 2950 } 2951} 2952 2953 2954 2955void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2956 std::string msg; 2957 raw_string_ostream Msg(msg); 2958 Msg << "Cannot select: "; 2959 2960 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2961 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2962 N->getOpcode() != ISD::INTRINSIC_VOID) { 2963 N->printrFull(Msg, CurDAG); 2964 } else { 2965 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2966 unsigned iid = 2967 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2968 if (iid < Intrinsic::num_intrinsics) 2969 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2970 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2971 Msg << "target intrinsic %" << TII->getName(iid); 2972 else 2973 Msg << "unknown intrinsic #" << iid; 2974 } 2975 report_fatal_error(Msg.str()); 2976} 2977 2978char SelectionDAGISel::ID = 0; 2979