SelectionDAGISel.cpp revision 48884cd80b52be1528618f2e9b3425ac24e7b5ca
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/MachineModuleInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/CodeGen/SSARegMap.h" 37#include "llvm/Target/MRegisterInfo.h" 38#include "llvm/Target/TargetData.h" 39#include "llvm/Target/TargetFrameInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Compiler.h" 47#include <algorithm> 48using namespace llvm; 49 50#ifndef NDEBUG 51static cl::opt<bool> 52ViewISelDAGs("view-isel-dags", cl::Hidden, 53 cl::desc("Pop up a window to show isel dags as they are selected")); 54static cl::opt<bool> 55ViewSchedDAGs("view-sched-dags", cl::Hidden, 56 cl::desc("Pop up a window to show sched dags as they are processed")); 57#else 58static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0; 59#endif 60 61//===---------------------------------------------------------------------===// 62/// 63/// RegisterScheduler class - Track the registration of instruction schedulers. 64/// 65//===---------------------------------------------------------------------===// 66MachinePassRegistry RegisterScheduler::Registry; 67 68//===---------------------------------------------------------------------===// 69/// 70/// ISHeuristic command line option for instruction schedulers. 71/// 72//===---------------------------------------------------------------------===// 73namespace { 74 cl::opt<RegisterScheduler::FunctionPassCtor, false, 75 RegisterPassParser<RegisterScheduler> > 76 ISHeuristic("pre-RA-sched", 77 cl::init(&createDefaultScheduler), 78 cl::desc("Instruction schedulers available (before register allocation):")); 79 80 static RegisterScheduler 81 defaultListDAGScheduler("default", " Best scheduler for the target", 82 createDefaultScheduler); 83} // namespace 84 85namespace { struct AsmOperandInfo; } 86 87namespace { 88 /// RegsForValue - This struct represents the physical registers that a 89 /// particular value is assigned and the type information about the value. 90 /// This is needed because values can be promoted into larger registers and 91 /// expanded into multiple smaller registers than the value. 92 struct VISIBILITY_HIDDEN RegsForValue { 93 /// Regs - This list holds the register (for legal and promoted values) 94 /// or register set (for expanded values) that the value should be assigned 95 /// to. 96 std::vector<unsigned> Regs; 97 98 /// RegVT - The value type of each register. 99 /// 100 MVT::ValueType RegVT; 101 102 /// ValueVT - The value type of the LLVM value, which may be promoted from 103 /// RegVT or made from merging the two expanded parts. 104 MVT::ValueType ValueVT; 105 106 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 107 108 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 109 : RegVT(regvt), ValueVT(valuevt) { 110 Regs.push_back(Reg); 111 } 112 RegsForValue(const std::vector<unsigned> ®s, 113 MVT::ValueType regvt, MVT::ValueType valuevt) 114 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 115 } 116 117 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 118 /// this value and returns the result as a ValueVT value. This uses 119 /// Chain/Flag as the input and updates them for the output Chain/Flag. 120 /// If the Flag pointer is NULL, no flag is used. 121 SDOperand getCopyFromRegs(SelectionDAG &DAG, 122 SDOperand &Chain, SDOperand *Flag) const; 123 124 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 125 /// specified value into the registers specified by this object. This uses 126 /// Chain/Flag as the input and updates them for the output Chain/Flag. 127 /// If the Flag pointer is NULL, no flag is used. 128 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 129 SDOperand &Chain, SDOperand *Flag) const; 130 131 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 132 /// operand list. This adds the code marker and includes the number of 133 /// values added into it. 134 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 135 std::vector<SDOperand> &Ops) const; 136 }; 137} 138 139namespace llvm { 140 //===--------------------------------------------------------------------===// 141 /// createDefaultScheduler - This creates an instruction scheduler appropriate 142 /// for the target. 143 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 144 SelectionDAG *DAG, 145 MachineBasicBlock *BB) { 146 TargetLowering &TLI = IS->getTargetLowering(); 147 148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 149 return createTDListDAGScheduler(IS, DAG, BB); 150 } else { 151 assert(TLI.getSchedulingPreference() == 152 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 153 return createBURRListDAGScheduler(IS, DAG, BB); 154 } 155 } 156 157 158 //===--------------------------------------------------------------------===// 159 /// FunctionLoweringInfo - This contains information that is global to a 160 /// function that is used when lowering a region of the function. 161 class FunctionLoweringInfo { 162 public: 163 TargetLowering &TLI; 164 Function &Fn; 165 MachineFunction &MF; 166 SSARegMap *RegMap; 167 168 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 169 170 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 171 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 172 173 /// ValueMap - Since we emit code for the function a basic block at a time, 174 /// we must remember which virtual registers hold the values for 175 /// cross-basic-block values. 176 DenseMap<const Value*, unsigned> ValueMap; 177 178 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 179 /// the entry block. This allows the allocas to be efficiently referenced 180 /// anywhere in the function. 181 std::map<const AllocaInst*, int> StaticAllocaMap; 182 183#ifndef NDEBUG 184 SmallSet<Instruction*, 8> CatchInfoLost; 185 SmallSet<Instruction*, 8> CatchInfoFound; 186#endif 187 188 unsigned MakeReg(MVT::ValueType VT) { 189 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 190 } 191 192 /// isExportedInst - Return true if the specified value is an instruction 193 /// exported from its block. 194 bool isExportedInst(const Value *V) { 195 return ValueMap.count(V); 196 } 197 198 unsigned CreateRegForValue(const Value *V); 199 200 unsigned InitializeRegForValue(const Value *V) { 201 unsigned &R = ValueMap[V]; 202 assert(R == 0 && "Already initialized this value register!"); 203 return R = CreateRegForValue(V); 204 } 205 }; 206} 207 208/// isSelector - Return true if this instruction is a call to the 209/// eh.selector intrinsic. 210static bool isSelector(Instruction *I) { 211 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 212 return II->getIntrinsicID() == Intrinsic::eh_selector; 213 return false; 214} 215 216/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 217/// PHI nodes or outside of the basic block that defines it, or used by a 218/// switch instruction, which may expand to multiple basic blocks. 219static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 220 if (isa<PHINode>(I)) return true; 221 BasicBlock *BB = I->getParent(); 222 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 223 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 224 // FIXME: Remove switchinst special case. 225 isa<SwitchInst>(*UI)) 226 return true; 227 return false; 228} 229 230/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 231/// entry block, return true. This includes arguments used by switches, since 232/// the switch may expand into multiple basic blocks. 233static bool isOnlyUsedInEntryBlock(Argument *A) { 234 BasicBlock *Entry = A->getParent()->begin(); 235 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 236 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 237 return false; // Use not in entry block. 238 return true; 239} 240 241FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 242 Function &fn, MachineFunction &mf) 243 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 244 245 // Create a vreg for each argument register that is not dead and is used 246 // outside of the entry block for the function. 247 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 248 AI != E; ++AI) 249 if (!isOnlyUsedInEntryBlock(AI)) 250 InitializeRegForValue(AI); 251 252 // Initialize the mapping of values to registers. This is only set up for 253 // instruction values that are used outside of the block that defines 254 // them. 255 Function::iterator BB = Fn.begin(), EB = Fn.end(); 256 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 257 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 258 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 259 const Type *Ty = AI->getAllocatedType(); 260 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 261 unsigned Align = 262 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 263 AI->getAlignment()); 264 265 TySize *= CUI->getZExtValue(); // Get total allocated size. 266 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 267 StaticAllocaMap[AI] = 268 MF.getFrameInfo()->CreateStackObject(TySize, Align); 269 } 270 271 for (; BB != EB; ++BB) 272 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 273 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 274 if (!isa<AllocaInst>(I) || 275 !StaticAllocaMap.count(cast<AllocaInst>(I))) 276 InitializeRegForValue(I); 277 278 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 279 // also creates the initial PHI MachineInstrs, though none of the input 280 // operands are populated. 281 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 282 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 283 MBBMap[BB] = MBB; 284 MF.getBasicBlockList().push_back(MBB); 285 286 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 287 // appropriate. 288 PHINode *PN; 289 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 290 if (PN->use_empty()) continue; 291 292 MVT::ValueType VT = TLI.getValueType(PN->getType()); 293 unsigned NumRegisters = TLI.getNumRegisters(VT); 294 unsigned PHIReg = ValueMap[PN]; 295 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 296 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 297 for (unsigned i = 0; i != NumRegisters; ++i) 298 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 299 } 300 } 301} 302 303/// CreateRegForValue - Allocate the appropriate number of virtual registers of 304/// the correctly promoted or expanded types. Assign these registers 305/// consecutive vreg numbers and return the first assigned number. 306unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 307 MVT::ValueType VT = TLI.getValueType(V->getType()); 308 309 unsigned NumRegisters = TLI.getNumRegisters(VT); 310 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 311 312 unsigned R = MakeReg(RegisterVT); 313 for (unsigned i = 1; i != NumRegisters; ++i) 314 MakeReg(RegisterVT); 315 316 return R; 317} 318 319//===----------------------------------------------------------------------===// 320/// SelectionDAGLowering - This is the common target-independent lowering 321/// implementation that is parameterized by a TargetLowering object. 322/// Also, targets can overload any lowering method. 323/// 324namespace llvm { 325class SelectionDAGLowering { 326 MachineBasicBlock *CurMBB; 327 328 DenseMap<const Value*, SDOperand> NodeMap; 329 330 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 331 /// them up and then emit token factor nodes when possible. This allows us to 332 /// get simple disambiguation between loads without worrying about alias 333 /// analysis. 334 std::vector<SDOperand> PendingLoads; 335 336 /// Case - A struct to record the Value for a switch case, and the 337 /// case's target basic block. 338 struct Case { 339 Constant* Low; 340 Constant* High; 341 MachineBasicBlock* BB; 342 343 Case() : Low(0), High(0), BB(0) { } 344 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 345 Low(low), High(high), BB(bb) { } 346 uint64_t size() const { 347 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 348 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 349 return (rHigh - rLow + 1ULL); 350 } 351 }; 352 353 struct CaseBits { 354 uint64_t Mask; 355 MachineBasicBlock* BB; 356 unsigned Bits; 357 358 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 359 Mask(mask), BB(bb), Bits(bits) { } 360 }; 361 362 typedef std::vector<Case> CaseVector; 363 typedef std::vector<CaseBits> CaseBitsVector; 364 typedef CaseVector::iterator CaseItr; 365 typedef std::pair<CaseItr, CaseItr> CaseRange; 366 367 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 368 /// of conditional branches. 369 struct CaseRec { 370 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 371 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 372 373 /// CaseBB - The MBB in which to emit the compare and branch 374 MachineBasicBlock *CaseBB; 375 /// LT, GE - If nonzero, we know the current case value must be less-than or 376 /// greater-than-or-equal-to these Constants. 377 Constant *LT; 378 Constant *GE; 379 /// Range - A pair of iterators representing the range of case values to be 380 /// processed at this point in the binary search tree. 381 CaseRange Range; 382 }; 383 384 typedef std::vector<CaseRec> CaseRecVector; 385 386 /// The comparison function for sorting the switch case values in the vector. 387 /// WARNING: Case ranges should be disjoint! 388 struct CaseCmp { 389 bool operator () (const Case& C1, const Case& C2) { 390 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 391 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 392 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 393 return CI1->getValue().slt(CI2->getValue()); 394 } 395 }; 396 397 struct CaseBitsCmp { 398 bool operator () (const CaseBits& C1, const CaseBits& C2) { 399 return C1.Bits > C2.Bits; 400 } 401 }; 402 403 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 404 405public: 406 // TLI - This is information that describes the available target features we 407 // need for lowering. This indicates when operations are unavailable, 408 // implemented with a libcall, etc. 409 TargetLowering &TLI; 410 SelectionDAG &DAG; 411 const TargetData *TD; 412 413 /// SwitchCases - Vector of CaseBlock structures used to communicate 414 /// SwitchInst code generation information. 415 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 416 /// JTCases - Vector of JumpTable structures used to communicate 417 /// SwitchInst code generation information. 418 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 419 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 420 421 /// FuncInfo - Information about the function as a whole. 422 /// 423 FunctionLoweringInfo &FuncInfo; 424 425 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 426 FunctionLoweringInfo &funcinfo) 427 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), 428 FuncInfo(funcinfo) { 429 } 430 431 /// getRoot - Return the current virtual root of the Selection DAG. 432 /// 433 SDOperand getRoot() { 434 if (PendingLoads.empty()) 435 return DAG.getRoot(); 436 437 if (PendingLoads.size() == 1) { 438 SDOperand Root = PendingLoads[0]; 439 DAG.setRoot(Root); 440 PendingLoads.clear(); 441 return Root; 442 } 443 444 // Otherwise, we have to make a token factor node. 445 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 446 &PendingLoads[0], PendingLoads.size()); 447 PendingLoads.clear(); 448 DAG.setRoot(Root); 449 return Root; 450 } 451 452 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 453 454 void visit(Instruction &I) { visit(I.getOpcode(), I); } 455 456 void visit(unsigned Opcode, User &I) { 457 // Note: this doesn't use InstVisitor, because it has to work with 458 // ConstantExpr's in addition to instructions. 459 switch (Opcode) { 460 default: assert(0 && "Unknown instruction type encountered!"); 461 abort(); 462 // Build the switch statement using the Instruction.def file. 463#define HANDLE_INST(NUM, OPCODE, CLASS) \ 464 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 465#include "llvm/Instruction.def" 466 } 467 } 468 469 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 470 471 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 472 const Value *SV, SDOperand Root, 473 bool isVolatile, unsigned Alignment); 474 475 SDOperand getIntPtrConstant(uint64_t Val) { 476 return DAG.getConstant(Val, TLI.getPointerTy()); 477 } 478 479 SDOperand getValue(const Value *V); 480 481 void setValue(const Value *V, SDOperand NewN) { 482 SDOperand &N = NodeMap[V]; 483 assert(N.Val == 0 && "Already set a value for this node!"); 484 N = NewN; 485 } 486 487 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 488 std::set<unsigned> &OutputRegs, 489 std::set<unsigned> &InputRegs); 490 491 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 492 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 493 unsigned Opc); 494 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 495 void ExportFromCurrentBlock(Value *V); 496 void LowerCallTo(Instruction &I, 497 const Type *CalledValueTy, unsigned CallingConv, 498 bool IsTailCall, SDOperand Callee, unsigned OpIdx, 499 MachineBasicBlock *LandingPad = NULL); 500 501 // Terminator instructions. 502 void visitRet(ReturnInst &I); 503 void visitBr(BranchInst &I); 504 void visitSwitch(SwitchInst &I); 505 void visitUnreachable(UnreachableInst &I) { /* noop */ } 506 507 // Helpers for visitSwitch 508 bool handleSmallSwitchRange(CaseRec& CR, 509 CaseRecVector& WorkList, 510 Value* SV, 511 MachineBasicBlock* Default); 512 bool handleJTSwitchCase(CaseRec& CR, 513 CaseRecVector& WorkList, 514 Value* SV, 515 MachineBasicBlock* Default); 516 bool handleBTSplitSwitchCase(CaseRec& CR, 517 CaseRecVector& WorkList, 518 Value* SV, 519 MachineBasicBlock* Default); 520 bool handleBitTestsSwitchCase(CaseRec& CR, 521 CaseRecVector& WorkList, 522 Value* SV, 523 MachineBasicBlock* Default); 524 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 525 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 526 void visitBitTestCase(MachineBasicBlock* NextMBB, 527 unsigned Reg, 528 SelectionDAGISel::BitTestCase &B); 529 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 530 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 531 SelectionDAGISel::JumpTableHeader &JTH); 532 533 // These all get lowered before this pass. 534 void visitInvoke(InvokeInst &I); 535 void visitUnwind(UnwindInst &I); 536 537 void visitBinary(User &I, unsigned OpCode); 538 void visitShift(User &I, unsigned Opcode); 539 void visitAdd(User &I) { 540 if (I.getType()->isFPOrFPVector()) 541 visitBinary(I, ISD::FADD); 542 else 543 visitBinary(I, ISD::ADD); 544 } 545 void visitSub(User &I); 546 void visitMul(User &I) { 547 if (I.getType()->isFPOrFPVector()) 548 visitBinary(I, ISD::FMUL); 549 else 550 visitBinary(I, ISD::MUL); 551 } 552 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 553 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 554 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 555 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 556 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 557 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 558 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 559 void visitOr (User &I) { visitBinary(I, ISD::OR); } 560 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 561 void visitShl (User &I) { visitShift(I, ISD::SHL); } 562 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 563 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 564 void visitICmp(User &I); 565 void visitFCmp(User &I); 566 // Visit the conversion instructions 567 void visitTrunc(User &I); 568 void visitZExt(User &I); 569 void visitSExt(User &I); 570 void visitFPTrunc(User &I); 571 void visitFPExt(User &I); 572 void visitFPToUI(User &I); 573 void visitFPToSI(User &I); 574 void visitUIToFP(User &I); 575 void visitSIToFP(User &I); 576 void visitPtrToInt(User &I); 577 void visitIntToPtr(User &I); 578 void visitBitCast(User &I); 579 580 void visitExtractElement(User &I); 581 void visitInsertElement(User &I); 582 void visitShuffleVector(User &I); 583 584 void visitGetElementPtr(User &I); 585 void visitSelect(User &I); 586 587 void visitMalloc(MallocInst &I); 588 void visitFree(FreeInst &I); 589 void visitAlloca(AllocaInst &I); 590 void visitLoad(LoadInst &I); 591 void visitStore(StoreInst &I); 592 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 593 void visitCall(CallInst &I); 594 void visitInlineAsm(CallInst &I); 595 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 596 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 597 598 void visitVAStart(CallInst &I); 599 void visitVAArg(VAArgInst &I); 600 void visitVAEnd(CallInst &I); 601 void visitVACopy(CallInst &I); 602 603 void visitMemIntrinsic(CallInst &I, unsigned Op); 604 605 void visitUserOp1(Instruction &I) { 606 assert(0 && "UserOp1 should not exist at instruction selection time!"); 607 abort(); 608 } 609 void visitUserOp2(Instruction &I) { 610 assert(0 && "UserOp2 should not exist at instruction selection time!"); 611 abort(); 612 } 613}; 614} // end namespace llvm 615 616 617/// getCopyFromParts - Create a value that contains the 618/// specified legal parts combined into the value they represent. 619static SDOperand getCopyFromParts(SelectionDAG &DAG, 620 const SDOperand *Parts, 621 unsigned NumParts, 622 MVT::ValueType PartVT, 623 MVT::ValueType ValueVT, 624 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 625 if (!MVT::isVector(ValueVT) || NumParts == 1) { 626 SDOperand Val = Parts[0]; 627 628 // If the value was expanded, copy from the top part. 629 if (NumParts > 1) { 630 assert(NumParts == 2 && 631 "Cannot expand to more than 2 elts yet!"); 632 SDOperand Hi = Parts[1]; 633 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 634 std::swap(Val, Hi); 635 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 636 } 637 638 // Otherwise, if the value was promoted or extended, truncate it to the 639 // appropriate type. 640 if (PartVT == ValueVT) 641 return Val; 642 643 if (MVT::isVector(PartVT)) { 644 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!"); 645 return DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 646 } 647 648 if (MVT::isInteger(PartVT) && 649 MVT::isInteger(ValueVT)) { 650 if (ValueVT < PartVT) { 651 // For a truncate, see if we have any information to 652 // indicate whether the truncated bits will always be 653 // zero or sign-extension. 654 if (AssertOp != ISD::DELETED_NODE) 655 Val = DAG.getNode(AssertOp, PartVT, Val, 656 DAG.getValueType(ValueVT)); 657 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 658 } else { 659 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 660 } 661 } 662 663 if (MVT::isFloatingPoint(PartVT) && 664 MVT::isFloatingPoint(ValueVT)) 665 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 666 667 if (MVT::getSizeInBits(PartVT) == 668 MVT::getSizeInBits(ValueVT)) 669 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 670 671 assert(0 && "Unknown mismatch!"); 672 } 673 674 // Handle a multi-element vector. 675 MVT::ValueType IntermediateVT, RegisterVT; 676 unsigned NumIntermediates; 677 unsigned NumRegs = 678 DAG.getTargetLoweringInfo() 679 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 680 RegisterVT); 681 682 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 683 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 684 assert(RegisterVT == Parts[0].getValueType() && 685 "Part type doesn't match part!"); 686 687 // Assemble the parts into intermediate operands. 688 SmallVector<SDOperand, 8> Ops(NumIntermediates); 689 if (NumIntermediates == NumParts) { 690 // If the register was not expanded, truncate or copy the value, 691 // as appropriate. 692 for (unsigned i = 0; i != NumParts; ++i) 693 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 694 PartVT, IntermediateVT); 695 } else if (NumParts > 0) { 696 // If the intermediate type was expanded, build the intermediate operands 697 // from the parts. 698 assert(NumParts % NumIntermediates == 0 && 699 "Must expand into a divisible number of parts!"); 700 unsigned Factor = NumParts / NumIntermediates; 701 for (unsigned i = 0; i != NumIntermediates; ++i) 702 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 703 PartVT, IntermediateVT); 704 } 705 706 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 707 // operands. 708 return DAG.getNode(MVT::isVector(IntermediateVT) ? 709 ISD::CONCAT_VECTORS : 710 ISD::BUILD_VECTOR, 711 ValueVT, &Ops[0], NumIntermediates); 712} 713 714/// getCopyToParts - Create a series of nodes that contain the 715/// specified value split into legal parts. 716static void getCopyToParts(SelectionDAG &DAG, 717 SDOperand Val, 718 SDOperand *Parts, 719 unsigned NumParts, 720 MVT::ValueType PartVT) { 721 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 722 MVT::ValueType PtrVT = TLI.getPointerTy(); 723 MVT::ValueType ValueVT = Val.getValueType(); 724 725 if (!MVT::isVector(ValueVT) || NumParts == 1) { 726 // If the value was expanded, copy from the parts. 727 if (NumParts > 1) { 728 for (unsigned i = 0; i != NumParts; ++i) 729 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val, 730 DAG.getConstant(i, PtrVT)); 731 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 732 std::reverse(Parts, Parts + NumParts); 733 return; 734 } 735 736 // If there is a single part and the types differ, this must be 737 // a promotion. 738 if (PartVT != ValueVT) { 739 if (MVT::isVector(PartVT)) { 740 assert(MVT::isVector(ValueVT) && 741 "Not a vector-vector cast?"); 742 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 743 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 744 if (PartVT < ValueVT) 745 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val); 746 else 747 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val); 748 } else if (MVT::isFloatingPoint(PartVT) && 749 MVT::isFloatingPoint(ValueVT)) { 750 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 751 } else if (MVT::getSizeInBits(PartVT) == 752 MVT::getSizeInBits(ValueVT)) { 753 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 754 } else { 755 assert(0 && "Unknown mismatch!"); 756 } 757 } 758 Parts[0] = Val; 759 return; 760 } 761 762 // Handle a multi-element vector. 763 MVT::ValueType IntermediateVT, RegisterVT; 764 unsigned NumIntermediates; 765 unsigned NumRegs = 766 DAG.getTargetLoweringInfo() 767 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 768 RegisterVT); 769 unsigned NumElements = MVT::getVectorNumElements(ValueVT); 770 771 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 772 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 773 774 // Split the vector into intermediate operands. 775 SmallVector<SDOperand, 8> Ops(NumIntermediates); 776 for (unsigned i = 0; i != NumIntermediates; ++i) 777 if (MVT::isVector(IntermediateVT)) 778 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 779 IntermediateVT, Val, 780 DAG.getConstant(i * (NumElements / NumIntermediates), 781 PtrVT)); 782 else 783 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 784 IntermediateVT, Val, 785 DAG.getConstant(i, PtrVT)); 786 787 // Split the intermediate operands into legal parts. 788 if (NumParts == NumIntermediates) { 789 // If the register was not expanded, promote or copy the value, 790 // as appropriate. 791 for (unsigned i = 0; i != NumParts; ++i) 792 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 793 } else if (NumParts > 0) { 794 // If the intermediate type was expanded, split each the value into 795 // legal parts. 796 assert(NumParts % NumIntermediates == 0 && 797 "Must expand into a divisible number of parts!"); 798 unsigned Factor = NumParts / NumIntermediates; 799 for (unsigned i = 0; i != NumIntermediates; ++i) 800 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 801 } 802} 803 804 805SDOperand SelectionDAGLowering::getValue(const Value *V) { 806 SDOperand &N = NodeMap[V]; 807 if (N.Val) return N; 808 809 const Type *VTy = V->getType(); 810 MVT::ValueType VT = TLI.getValueType(VTy); 811 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 812 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 813 visit(CE->getOpcode(), *CE); 814 SDOperand N1 = NodeMap[V]; 815 assert(N1.Val && "visit didn't populate the ValueMap!"); 816 return N1; 817 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 818 return N = DAG.getGlobalAddress(GV, VT); 819 } else if (isa<ConstantPointerNull>(C)) { 820 return N = DAG.getConstant(0, TLI.getPointerTy()); 821 } else if (isa<UndefValue>(C)) { 822 if (!isa<VectorType>(VTy)) 823 return N = DAG.getNode(ISD::UNDEF, VT); 824 825 // Create a BUILD_VECTOR of undef nodes. 826 const VectorType *PTy = cast<VectorType>(VTy); 827 unsigned NumElements = PTy->getNumElements(); 828 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 829 830 SmallVector<SDOperand, 8> Ops; 831 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 832 833 // Create a VConstant node with generic Vector type. 834 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 835 return N = DAG.getNode(ISD::BUILD_VECTOR, VT, 836 &Ops[0], Ops.size()); 837 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 838 return N = DAG.getConstantFP(CFP->getValue(), VT); 839 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 840 unsigned NumElements = PTy->getNumElements(); 841 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 842 843 // Now that we know the number and type of the elements, push a 844 // Constant or ConstantFP node onto the ops list for each element of 845 // the vector constant. 846 SmallVector<SDOperand, 8> Ops; 847 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 848 for (unsigned i = 0; i != NumElements; ++i) 849 Ops.push_back(getValue(CP->getOperand(i))); 850 } else { 851 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 852 SDOperand Op; 853 if (MVT::isFloatingPoint(PVT)) 854 Op = DAG.getConstantFP(0, PVT); 855 else 856 Op = DAG.getConstant(0, PVT); 857 Ops.assign(NumElements, Op); 858 } 859 860 // Create a BUILD_VECTOR node. 861 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 862 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], 863 Ops.size()); 864 } else { 865 // Canonicalize all constant ints to be unsigned. 866 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT); 867 } 868 } 869 870 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 871 std::map<const AllocaInst*, int>::iterator SI = 872 FuncInfo.StaticAllocaMap.find(AI); 873 if (SI != FuncInfo.StaticAllocaMap.end()) 874 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 875 } 876 877 unsigned InReg = FuncInfo.ValueMap[V]; 878 assert(InReg && "Value not in map!"); 879 880 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 881 unsigned NumRegs = TLI.getNumRegisters(VT); 882 883 std::vector<unsigned> Regs(NumRegs); 884 for (unsigned i = 0; i != NumRegs; ++i) 885 Regs[i] = InReg + i; 886 887 RegsForValue RFV(Regs, RegisterVT, VT); 888 SDOperand Chain = DAG.getEntryNode(); 889 890 return RFV.getCopyFromRegs(DAG, Chain, NULL); 891} 892 893 894void SelectionDAGLowering::visitRet(ReturnInst &I) { 895 if (I.getNumOperands() == 0) { 896 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 897 return; 898 } 899 SmallVector<SDOperand, 8> NewValues; 900 NewValues.push_back(getRoot()); 901 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 902 SDOperand RetOp = getValue(I.getOperand(i)); 903 904 // If this is an integer return value, we need to promote it ourselves to 905 // the full width of a register, since getCopyToParts and Legalize will use 906 // ANY_EXTEND rather than sign/zero. 907 // FIXME: C calling convention requires the return type to be promoted to 908 // at least 32-bit. But this is not necessary for non-C calling conventions. 909 if (MVT::isInteger(RetOp.getValueType()) && 910 RetOp.getValueType() < MVT::i64) { 911 MVT::ValueType TmpVT; 912 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 913 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 914 else 915 TmpVT = MVT::i32; 916 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType(); 917 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 918 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 919 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt)) 920 ExtendKind = ISD::SIGN_EXTEND; 921 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt)) 922 ExtendKind = ISD::ZERO_EXTEND; 923 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp); 924 NewValues.push_back(RetOp); 925 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 926 } else { 927 MVT::ValueType VT = RetOp.getValueType(); 928 unsigned NumParts = TLI.getNumRegisters(VT); 929 MVT::ValueType PartVT = TLI.getRegisterType(VT); 930 SmallVector<SDOperand, 4> Parts(NumParts); 931 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT); 932 for (unsigned i = 0; i < NumParts; ++i) { 933 NewValues.push_back(Parts[i]); 934 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 935 } 936 } 937 } 938 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 939 &NewValues[0], NewValues.size())); 940} 941 942/// ExportFromCurrentBlock - If this condition isn't known to be exported from 943/// the current basic block, add it to ValueMap now so that we'll get a 944/// CopyTo/FromReg. 945void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 946 // No need to export constants. 947 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 948 949 // Already exported? 950 if (FuncInfo.isExportedInst(V)) return; 951 952 unsigned Reg = FuncInfo.InitializeRegForValue(V); 953 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 954} 955 956bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 957 const BasicBlock *FromBB) { 958 // The operands of the setcc have to be in this block. We don't know 959 // how to export them from some other block. 960 if (Instruction *VI = dyn_cast<Instruction>(V)) { 961 // Can export from current BB. 962 if (VI->getParent() == FromBB) 963 return true; 964 965 // Is already exported, noop. 966 return FuncInfo.isExportedInst(V); 967 } 968 969 // If this is an argument, we can export it if the BB is the entry block or 970 // if it is already exported. 971 if (isa<Argument>(V)) { 972 if (FromBB == &FromBB->getParent()->getEntryBlock()) 973 return true; 974 975 // Otherwise, can only export this if it is already exported. 976 return FuncInfo.isExportedInst(V); 977 } 978 979 // Otherwise, constants can always be exported. 980 return true; 981} 982 983static bool InBlock(const Value *V, const BasicBlock *BB) { 984 if (const Instruction *I = dyn_cast<Instruction>(V)) 985 return I->getParent() == BB; 986 return true; 987} 988 989/// FindMergedConditions - If Cond is an expression like 990void SelectionDAGLowering::FindMergedConditions(Value *Cond, 991 MachineBasicBlock *TBB, 992 MachineBasicBlock *FBB, 993 MachineBasicBlock *CurBB, 994 unsigned Opc) { 995 // If this node is not part of the or/and tree, emit it as a branch. 996 Instruction *BOp = dyn_cast<Instruction>(Cond); 997 998 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 999 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1000 BOp->getParent() != CurBB->getBasicBlock() || 1001 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1002 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1003 const BasicBlock *BB = CurBB->getBasicBlock(); 1004 1005 // If the leaf of the tree is a comparison, merge the condition into 1006 // the caseblock. 1007 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1008 // The operands of the cmp have to be in this block. We don't know 1009 // how to export them from some other block. If this is the first block 1010 // of the sequence, no exporting is needed. 1011 (CurBB == CurMBB || 1012 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1013 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1014 BOp = cast<Instruction>(Cond); 1015 ISD::CondCode Condition; 1016 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1017 switch (IC->getPredicate()) { 1018 default: assert(0 && "Unknown icmp predicate opcode!"); 1019 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1020 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1021 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1022 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1023 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1024 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1025 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1026 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1027 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1028 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1029 } 1030 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1031 ISD::CondCode FPC, FOC; 1032 switch (FC->getPredicate()) { 1033 default: assert(0 && "Unknown fcmp predicate opcode!"); 1034 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1035 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1036 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1037 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1038 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1039 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1040 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1041 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 1042 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 1043 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1044 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1045 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1046 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1047 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1048 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1049 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1050 } 1051 if (FiniteOnlyFPMath()) 1052 Condition = FOC; 1053 else 1054 Condition = FPC; 1055 } else { 1056 Condition = ISD::SETEQ; // silence warning. 1057 assert(0 && "Unknown compare instruction"); 1058 } 1059 1060 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1061 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1062 SwitchCases.push_back(CB); 1063 return; 1064 } 1065 1066 // Create a CaseBlock record representing this branch. 1067 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1068 NULL, TBB, FBB, CurBB); 1069 SwitchCases.push_back(CB); 1070 return; 1071 } 1072 1073 1074 // Create TmpBB after CurBB. 1075 MachineFunction::iterator BBI = CurBB; 1076 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 1077 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 1078 1079 if (Opc == Instruction::Or) { 1080 // Codegen X | Y as: 1081 // jmp_if_X TBB 1082 // jmp TmpBB 1083 // TmpBB: 1084 // jmp_if_Y TBB 1085 // jmp FBB 1086 // 1087 1088 // Emit the LHS condition. 1089 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1090 1091 // Emit the RHS condition into TmpBB. 1092 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1093 } else { 1094 assert(Opc == Instruction::And && "Unknown merge op!"); 1095 // Codegen X & Y as: 1096 // jmp_if_X TmpBB 1097 // jmp FBB 1098 // TmpBB: 1099 // jmp_if_Y TBB 1100 // jmp FBB 1101 // 1102 // This requires creation of TmpBB after CurBB. 1103 1104 // Emit the LHS condition. 1105 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1106 1107 // Emit the RHS condition into TmpBB. 1108 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1109 } 1110} 1111 1112/// If the set of cases should be emitted as a series of branches, return true. 1113/// If we should emit this as a bunch of and/or'd together conditions, return 1114/// false. 1115static bool 1116ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1117 if (Cases.size() != 2) return true; 1118 1119 // If this is two comparisons of the same values or'd or and'd together, they 1120 // will get folded into a single comparison, so don't emit two blocks. 1121 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1122 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1123 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1124 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1125 return false; 1126 } 1127 1128 return true; 1129} 1130 1131void SelectionDAGLowering::visitBr(BranchInst &I) { 1132 // Update machine-CFG edges. 1133 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1134 1135 // Figure out which block is immediately after the current one. 1136 MachineBasicBlock *NextBlock = 0; 1137 MachineFunction::iterator BBI = CurMBB; 1138 if (++BBI != CurMBB->getParent()->end()) 1139 NextBlock = BBI; 1140 1141 if (I.isUnconditional()) { 1142 // If this is not a fall-through branch, emit the branch. 1143 if (Succ0MBB != NextBlock) 1144 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1145 DAG.getBasicBlock(Succ0MBB))); 1146 1147 // Update machine-CFG edges. 1148 CurMBB->addSuccessor(Succ0MBB); 1149 1150 return; 1151 } 1152 1153 // If this condition is one of the special cases we handle, do special stuff 1154 // now. 1155 Value *CondVal = I.getCondition(); 1156 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1157 1158 // If this is a series of conditions that are or'd or and'd together, emit 1159 // this as a sequence of branches instead of setcc's with and/or operations. 1160 // For example, instead of something like: 1161 // cmp A, B 1162 // C = seteq 1163 // cmp D, E 1164 // F = setle 1165 // or C, F 1166 // jnz foo 1167 // Emit: 1168 // cmp A, B 1169 // je foo 1170 // cmp D, E 1171 // jle foo 1172 // 1173 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1174 if (BOp->hasOneUse() && 1175 (BOp->getOpcode() == Instruction::And || 1176 BOp->getOpcode() == Instruction::Or)) { 1177 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1178 // If the compares in later blocks need to use values not currently 1179 // exported from this block, export them now. This block should always 1180 // be the first entry. 1181 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1182 1183 // Allow some cases to be rejected. 1184 if (ShouldEmitAsBranches(SwitchCases)) { 1185 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1186 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1187 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1188 } 1189 1190 // Emit the branch for this block. 1191 visitSwitchCase(SwitchCases[0]); 1192 SwitchCases.erase(SwitchCases.begin()); 1193 return; 1194 } 1195 1196 // Okay, we decided not to do this, remove any inserted MBB's and clear 1197 // SwitchCases. 1198 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1199 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1200 1201 SwitchCases.clear(); 1202 } 1203 } 1204 1205 // Create a CaseBlock record representing this branch. 1206 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1207 NULL, Succ0MBB, Succ1MBB, CurMBB); 1208 // Use visitSwitchCase to actually insert the fast branch sequence for this 1209 // cond branch. 1210 visitSwitchCase(CB); 1211} 1212 1213/// visitSwitchCase - Emits the necessary code to represent a single node in 1214/// the binary search tree resulting from lowering a switch instruction. 1215void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1216 SDOperand Cond; 1217 SDOperand CondLHS = getValue(CB.CmpLHS); 1218 1219 // Build the setcc now. 1220 if (CB.CmpMHS == NULL) { 1221 // Fold "(X == true)" to X and "(X == false)" to !X to 1222 // handle common cases produced by branch lowering. 1223 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1224 Cond = CondLHS; 1225 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1226 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1227 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1228 } else 1229 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1230 } else { 1231 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1232 1233 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1234 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1235 1236 SDOperand CmpOp = getValue(CB.CmpMHS); 1237 MVT::ValueType VT = CmpOp.getValueType(); 1238 1239 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1240 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1241 } else { 1242 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1243 Cond = DAG.getSetCC(MVT::i1, SUB, 1244 DAG.getConstant(High-Low, VT), ISD::SETULE); 1245 } 1246 1247 } 1248 1249 // Set NextBlock to be the MBB immediately after the current one, if any. 1250 // This is used to avoid emitting unnecessary branches to the next block. 1251 MachineBasicBlock *NextBlock = 0; 1252 MachineFunction::iterator BBI = CurMBB; 1253 if (++BBI != CurMBB->getParent()->end()) 1254 NextBlock = BBI; 1255 1256 // If the lhs block is the next block, invert the condition so that we can 1257 // fall through to the lhs instead of the rhs block. 1258 if (CB.TrueBB == NextBlock) { 1259 std::swap(CB.TrueBB, CB.FalseBB); 1260 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1261 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1262 } 1263 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1264 DAG.getBasicBlock(CB.TrueBB)); 1265 if (CB.FalseBB == NextBlock) 1266 DAG.setRoot(BrCond); 1267 else 1268 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1269 DAG.getBasicBlock(CB.FalseBB))); 1270 // Update successor info 1271 CurMBB->addSuccessor(CB.TrueBB); 1272 CurMBB->addSuccessor(CB.FalseBB); 1273} 1274 1275/// visitJumpTable - Emit JumpTable node in the current MBB 1276void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1277 // Emit the code for the jump table 1278 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1279 MVT::ValueType PTy = TLI.getPointerTy(); 1280 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1281 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1282 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1283 Table, Index)); 1284 return; 1285} 1286 1287/// visitJumpTableHeader - This function emits necessary code to produce index 1288/// in the JumpTable from switch case. 1289void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1290 SelectionDAGISel::JumpTableHeader &JTH) { 1291 // Subtract the lowest switch case value from the value being switched on 1292 // and conditional branch to default mbb if the result is greater than the 1293 // difference between smallest and largest cases. 1294 SDOperand SwitchOp = getValue(JTH.SValue); 1295 MVT::ValueType VT = SwitchOp.getValueType(); 1296 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1297 DAG.getConstant(JTH.First, VT)); 1298 1299 // The SDNode we just created, which holds the value being switched on 1300 // minus the the smallest case value, needs to be copied to a virtual 1301 // register so it can be used as an index into the jump table in a 1302 // subsequent basic block. This value may be smaller or larger than the 1303 // target's pointer type, and therefore require extension or truncating. 1304 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 1305 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1306 else 1307 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1308 1309 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1310 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1311 JT.Reg = JumpTableReg; 1312 1313 // Emit the range check for the jump table, and branch to the default 1314 // block for the switch statement if the value being switched on exceeds 1315 // the largest case in the switch. 1316 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1317 DAG.getConstant(JTH.Last-JTH.First,VT), 1318 ISD::SETUGT); 1319 1320 // Set NextBlock to be the MBB immediately after the current one, if any. 1321 // This is used to avoid emitting unnecessary branches to the next block. 1322 MachineBasicBlock *NextBlock = 0; 1323 MachineFunction::iterator BBI = CurMBB; 1324 if (++BBI != CurMBB->getParent()->end()) 1325 NextBlock = BBI; 1326 1327 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1328 DAG.getBasicBlock(JT.Default)); 1329 1330 if (JT.MBB == NextBlock) 1331 DAG.setRoot(BrCond); 1332 else 1333 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1334 DAG.getBasicBlock(JT.MBB))); 1335 1336 return; 1337} 1338 1339/// visitBitTestHeader - This function emits necessary code to produce value 1340/// suitable for "bit tests" 1341void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1342 // Subtract the minimum value 1343 SDOperand SwitchOp = getValue(B.SValue); 1344 MVT::ValueType VT = SwitchOp.getValueType(); 1345 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1346 DAG.getConstant(B.First, VT)); 1347 1348 // Check range 1349 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1350 DAG.getConstant(B.Range, VT), 1351 ISD::SETUGT); 1352 1353 SDOperand ShiftOp; 1354 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy())) 1355 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1356 else 1357 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1358 1359 // Make desired shift 1360 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1361 DAG.getConstant(1, TLI.getPointerTy()), 1362 ShiftOp); 1363 1364 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1365 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1366 B.Reg = SwitchReg; 1367 1368 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1369 DAG.getBasicBlock(B.Default)); 1370 1371 // Set NextBlock to be the MBB immediately after the current one, if any. 1372 // This is used to avoid emitting unnecessary branches to the next block. 1373 MachineBasicBlock *NextBlock = 0; 1374 MachineFunction::iterator BBI = CurMBB; 1375 if (++BBI != CurMBB->getParent()->end()) 1376 NextBlock = BBI; 1377 1378 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1379 if (MBB == NextBlock) 1380 DAG.setRoot(BrRange); 1381 else 1382 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1383 DAG.getBasicBlock(MBB))); 1384 1385 CurMBB->addSuccessor(B.Default); 1386 CurMBB->addSuccessor(MBB); 1387 1388 return; 1389} 1390 1391/// visitBitTestCase - this function produces one "bit test" 1392void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1393 unsigned Reg, 1394 SelectionDAGISel::BitTestCase &B) { 1395 // Emit bit tests and jumps 1396 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1397 1398 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1399 SwitchVal, 1400 DAG.getConstant(B.Mask, 1401 TLI.getPointerTy())); 1402 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, 1403 DAG.getConstant(0, TLI.getPointerTy()), 1404 ISD::SETNE); 1405 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1406 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1407 1408 // Set NextBlock to be the MBB immediately after the current one, if any. 1409 // This is used to avoid emitting unnecessary branches to the next block. 1410 MachineBasicBlock *NextBlock = 0; 1411 MachineFunction::iterator BBI = CurMBB; 1412 if (++BBI != CurMBB->getParent()->end()) 1413 NextBlock = BBI; 1414 1415 if (NextMBB == NextBlock) 1416 DAG.setRoot(BrAnd); 1417 else 1418 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1419 DAG.getBasicBlock(NextMBB))); 1420 1421 CurMBB->addSuccessor(B.TargetBB); 1422 CurMBB->addSuccessor(NextMBB); 1423 1424 return; 1425} 1426 1427void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1428 // Retrieve successors. 1429 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1430 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1431 1432 LowerCallTo(I, I.getCalledValue()->getType(), 1433 I.getCallingConv(), 1434 false, 1435 getValue(I.getOperand(0)), 1436 3, LandingPad); 1437 1438 // If the value of the invoke is used outside of its defining block, make it 1439 // available as a virtual register. 1440 if (!I.use_empty()) { 1441 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1442 if (VMI != FuncInfo.ValueMap.end()) 1443 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second)); 1444 } 1445 1446 // Drop into normal successor. 1447 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1448 DAG.getBasicBlock(Return))); 1449 1450 // Update successor info 1451 CurMBB->addSuccessor(Return); 1452 CurMBB->addSuccessor(LandingPad); 1453} 1454 1455void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1456} 1457 1458/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1459/// small case ranges). 1460bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1461 CaseRecVector& WorkList, 1462 Value* SV, 1463 MachineBasicBlock* Default) { 1464 Case& BackCase = *(CR.Range.second-1); 1465 1466 // Size is the number of Cases represented by this range. 1467 unsigned Size = CR.Range.second - CR.Range.first; 1468 if (Size > 3) 1469 return false; 1470 1471 // Get the MachineFunction which holds the current MBB. This is used when 1472 // inserting any additional MBBs necessary to represent the switch. 1473 MachineFunction *CurMF = CurMBB->getParent(); 1474 1475 // Figure out which block is immediately after the current one. 1476 MachineBasicBlock *NextBlock = 0; 1477 MachineFunction::iterator BBI = CR.CaseBB; 1478 1479 if (++BBI != CurMBB->getParent()->end()) 1480 NextBlock = BBI; 1481 1482 // TODO: If any two of the cases has the same destination, and if one value 1483 // is the same as the other, but has one bit unset that the other has set, 1484 // use bit manipulation to do two compares at once. For example: 1485 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1486 1487 // Rearrange the case blocks so that the last one falls through if possible. 1488 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1489 // The last case block won't fall through into 'NextBlock' if we emit the 1490 // branches in this order. See if rearranging a case value would help. 1491 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1492 if (I->BB == NextBlock) { 1493 std::swap(*I, BackCase); 1494 break; 1495 } 1496 } 1497 } 1498 1499 // Create a CaseBlock record representing a conditional branch to 1500 // the Case's target mbb if the value being switched on SV is equal 1501 // to C. 1502 MachineBasicBlock *CurBlock = CR.CaseBB; 1503 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1504 MachineBasicBlock *FallThrough; 1505 if (I != E-1) { 1506 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1507 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1508 } else { 1509 // If the last case doesn't match, go to the default block. 1510 FallThrough = Default; 1511 } 1512 1513 Value *RHS, *LHS, *MHS; 1514 ISD::CondCode CC; 1515 if (I->High == I->Low) { 1516 // This is just small small case range :) containing exactly 1 case 1517 CC = ISD::SETEQ; 1518 LHS = SV; RHS = I->High; MHS = NULL; 1519 } else { 1520 CC = ISD::SETLE; 1521 LHS = I->Low; MHS = SV; RHS = I->High; 1522 } 1523 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1524 I->BB, FallThrough, CurBlock); 1525 1526 // If emitting the first comparison, just call visitSwitchCase to emit the 1527 // code into the current block. Otherwise, push the CaseBlock onto the 1528 // vector to be later processed by SDISel, and insert the node's MBB 1529 // before the next MBB. 1530 if (CurBlock == CurMBB) 1531 visitSwitchCase(CB); 1532 else 1533 SwitchCases.push_back(CB); 1534 1535 CurBlock = FallThrough; 1536 } 1537 1538 return true; 1539} 1540 1541static inline bool areJTsAllowed(const TargetLowering &TLI) { 1542 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1543 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1544} 1545 1546/// handleJTSwitchCase - Emit jumptable for current switch case range 1547bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1548 CaseRecVector& WorkList, 1549 Value* SV, 1550 MachineBasicBlock* Default) { 1551 Case& FrontCase = *CR.Range.first; 1552 Case& BackCase = *(CR.Range.second-1); 1553 1554 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1555 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1556 1557 uint64_t TSize = 0; 1558 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1559 I!=E; ++I) 1560 TSize += I->size(); 1561 1562 if (!areJTsAllowed(TLI) || TSize <= 3) 1563 return false; 1564 1565 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1566 if (Density < 0.4) 1567 return false; 1568 1569 DOUT << "Lowering jump table\n" 1570 << "First entry: " << First << ". Last entry: " << Last << "\n" 1571 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1572 1573 // Get the MachineFunction which holds the current MBB. This is used when 1574 // inserting any additional MBBs necessary to represent the switch. 1575 MachineFunction *CurMF = CurMBB->getParent(); 1576 1577 // Figure out which block is immediately after the current one. 1578 MachineBasicBlock *NextBlock = 0; 1579 MachineFunction::iterator BBI = CR.CaseBB; 1580 1581 if (++BBI != CurMBB->getParent()->end()) 1582 NextBlock = BBI; 1583 1584 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1585 1586 // Create a new basic block to hold the code for loading the address 1587 // of the jump table, and jumping to it. Update successor information; 1588 // we will either branch to the default case for the switch, or the jump 1589 // table. 1590 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1591 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1592 CR.CaseBB->addSuccessor(Default); 1593 CR.CaseBB->addSuccessor(JumpTableBB); 1594 1595 // Build a vector of destination BBs, corresponding to each target 1596 // of the jump table. If the value of the jump table slot corresponds to 1597 // a case statement, push the case's BB onto the vector, otherwise, push 1598 // the default BB. 1599 std::vector<MachineBasicBlock*> DestBBs; 1600 int64_t TEI = First; 1601 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1602 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1603 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1604 1605 if ((Low <= TEI) && (TEI <= High)) { 1606 DestBBs.push_back(I->BB); 1607 if (TEI==High) 1608 ++I; 1609 } else { 1610 DestBBs.push_back(Default); 1611 } 1612 } 1613 1614 // Update successor info. Add one edge to each unique successor. 1615 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1616 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1617 E = DestBBs.end(); I != E; ++I) { 1618 if (!SuccsHandled[(*I)->getNumber()]) { 1619 SuccsHandled[(*I)->getNumber()] = true; 1620 JumpTableBB->addSuccessor(*I); 1621 } 1622 } 1623 1624 // Create a jump table index for this jump table, or return an existing 1625 // one. 1626 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1627 1628 // Set the jump table information so that we can codegen it as a second 1629 // MachineBasicBlock 1630 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1631 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1632 (CR.CaseBB == CurMBB)); 1633 if (CR.CaseBB == CurMBB) 1634 visitJumpTableHeader(JT, JTH); 1635 1636 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1637 1638 return true; 1639} 1640 1641/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1642/// 2 subtrees. 1643bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1644 CaseRecVector& WorkList, 1645 Value* SV, 1646 MachineBasicBlock* Default) { 1647 // Get the MachineFunction which holds the current MBB. This is used when 1648 // inserting any additional MBBs necessary to represent the switch. 1649 MachineFunction *CurMF = CurMBB->getParent(); 1650 1651 // Figure out which block is immediately after the current one. 1652 MachineBasicBlock *NextBlock = 0; 1653 MachineFunction::iterator BBI = CR.CaseBB; 1654 1655 if (++BBI != CurMBB->getParent()->end()) 1656 NextBlock = BBI; 1657 1658 Case& FrontCase = *CR.Range.first; 1659 Case& BackCase = *(CR.Range.second-1); 1660 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1661 1662 // Size is the number of Cases represented by this range. 1663 unsigned Size = CR.Range.second - CR.Range.first; 1664 1665 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1666 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1667 double FMetric = 0; 1668 CaseItr Pivot = CR.Range.first + Size/2; 1669 1670 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1671 // (heuristically) allow us to emit JumpTable's later. 1672 uint64_t TSize = 0; 1673 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1674 I!=E; ++I) 1675 TSize += I->size(); 1676 1677 uint64_t LSize = FrontCase.size(); 1678 uint64_t RSize = TSize-LSize; 1679 DOUT << "Selecting best pivot: \n" 1680 << "First: " << First << ", Last: " << Last <<"\n" 1681 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1682 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1683 J!=E; ++I, ++J) { 1684 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1685 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1686 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1687 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1688 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1689 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1690 // Should always split in some non-trivial place 1691 DOUT <<"=>Step\n" 1692 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1693 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1694 << "Metric: " << Metric << "\n"; 1695 if (FMetric < Metric) { 1696 Pivot = J; 1697 FMetric = Metric; 1698 DOUT << "Current metric set to: " << FMetric << "\n"; 1699 } 1700 1701 LSize += J->size(); 1702 RSize -= J->size(); 1703 } 1704 if (areJTsAllowed(TLI)) { 1705 // If our case is dense we *really* should handle it earlier! 1706 assert((FMetric > 0) && "Should handle dense range earlier!"); 1707 } else { 1708 Pivot = CR.Range.first + Size/2; 1709 } 1710 1711 CaseRange LHSR(CR.Range.first, Pivot); 1712 CaseRange RHSR(Pivot, CR.Range.second); 1713 Constant *C = Pivot->Low; 1714 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1715 1716 // We know that we branch to the LHS if the Value being switched on is 1717 // less than the Pivot value, C. We use this to optimize our binary 1718 // tree a bit, by recognizing that if SV is greater than or equal to the 1719 // LHS's Case Value, and that Case Value is exactly one less than the 1720 // Pivot's Value, then we can branch directly to the LHS's Target, 1721 // rather than creating a leaf node for it. 1722 if ((LHSR.second - LHSR.first) == 1 && 1723 LHSR.first->High == CR.GE && 1724 cast<ConstantInt>(C)->getSExtValue() == 1725 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1726 TrueBB = LHSR.first->BB; 1727 } else { 1728 TrueBB = new MachineBasicBlock(LLVMBB); 1729 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1730 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1731 } 1732 1733 // Similar to the optimization above, if the Value being switched on is 1734 // known to be less than the Constant CR.LT, and the current Case Value 1735 // is CR.LT - 1, then we can branch directly to the target block for 1736 // the current Case Value, rather than emitting a RHS leaf node for it. 1737 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1738 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1739 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1740 FalseBB = RHSR.first->BB; 1741 } else { 1742 FalseBB = new MachineBasicBlock(LLVMBB); 1743 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1744 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1745 } 1746 1747 // Create a CaseBlock record representing a conditional branch to 1748 // the LHS node if the value being switched on SV is less than C. 1749 // Otherwise, branch to LHS. 1750 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1751 TrueBB, FalseBB, CR.CaseBB); 1752 1753 if (CR.CaseBB == CurMBB) 1754 visitSwitchCase(CB); 1755 else 1756 SwitchCases.push_back(CB); 1757 1758 return true; 1759} 1760 1761/// handleBitTestsSwitchCase - if current case range has few destination and 1762/// range span less, than machine word bitwidth, encode case range into series 1763/// of masks and emit bit tests with these masks. 1764bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1765 CaseRecVector& WorkList, 1766 Value* SV, 1767 MachineBasicBlock* Default){ 1768 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); 1769 1770 Case& FrontCase = *CR.Range.first; 1771 Case& BackCase = *(CR.Range.second-1); 1772 1773 // Get the MachineFunction which holds the current MBB. This is used when 1774 // inserting any additional MBBs necessary to represent the switch. 1775 MachineFunction *CurMF = CurMBB->getParent(); 1776 1777 unsigned numCmps = 0; 1778 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1779 I!=E; ++I) { 1780 // Single case counts one, case range - two. 1781 if (I->Low == I->High) 1782 numCmps +=1; 1783 else 1784 numCmps +=2; 1785 } 1786 1787 // Count unique destinations 1788 SmallSet<MachineBasicBlock*, 4> Dests; 1789 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1790 Dests.insert(I->BB); 1791 if (Dests.size() > 3) 1792 // Don't bother the code below, if there are too much unique destinations 1793 return false; 1794 } 1795 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1796 << "Total number of comparisons: " << numCmps << "\n"; 1797 1798 // Compute span of values. 1799 Constant* minValue = FrontCase.Low; 1800 Constant* maxValue = BackCase.High; 1801 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1802 cast<ConstantInt>(minValue)->getSExtValue(); 1803 DOUT << "Compare range: " << range << "\n" 1804 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1805 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1806 1807 if (range>=IntPtrBits || 1808 (!(Dests.size() == 1 && numCmps >= 3) && 1809 !(Dests.size() == 2 && numCmps >= 5) && 1810 !(Dests.size() >= 3 && numCmps >= 6))) 1811 return false; 1812 1813 DOUT << "Emitting bit tests\n"; 1814 int64_t lowBound = 0; 1815 1816 // Optimize the case where all the case values fit in a 1817 // word without having to subtract minValue. In this case, 1818 // we can optimize away the subtraction. 1819 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1820 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1821 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1822 } else { 1823 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1824 } 1825 1826 CaseBitsVector CasesBits; 1827 unsigned i, count = 0; 1828 1829 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1830 MachineBasicBlock* Dest = I->BB; 1831 for (i = 0; i < count; ++i) 1832 if (Dest == CasesBits[i].BB) 1833 break; 1834 1835 if (i == count) { 1836 assert((count < 3) && "Too much destinations to test!"); 1837 CasesBits.push_back(CaseBits(0, Dest, 0)); 1838 count++; 1839 } 1840 1841 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1842 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1843 1844 for (uint64_t j = lo; j <= hi; j++) { 1845 CasesBits[i].Mask |= 1ULL << j; 1846 CasesBits[i].Bits++; 1847 } 1848 1849 } 1850 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1851 1852 SelectionDAGISel::BitTestInfo BTC; 1853 1854 // Figure out which block is immediately after the current one. 1855 MachineFunction::iterator BBI = CR.CaseBB; 1856 ++BBI; 1857 1858 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1859 1860 DOUT << "Cases:\n"; 1861 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1862 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1863 << ", BB: " << CasesBits[i].BB << "\n"; 1864 1865 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1866 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1867 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1868 CaseBB, 1869 CasesBits[i].BB)); 1870 } 1871 1872 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 1873 -1U, (CR.CaseBB == CurMBB), 1874 CR.CaseBB, Default, BTC); 1875 1876 if (CR.CaseBB == CurMBB) 1877 visitBitTestHeader(BTB); 1878 1879 BitTestCases.push_back(BTB); 1880 1881 return true; 1882} 1883 1884 1885// Clusterify - Transform simple list of Cases into list of CaseRange's 1886unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 1887 const SwitchInst& SI) { 1888 unsigned numCmps = 0; 1889 1890 // Start with "simple" cases 1891 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 1892 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1893 Cases.push_back(Case(SI.getSuccessorValue(i), 1894 SI.getSuccessorValue(i), 1895 SMBB)); 1896 } 1897 sort(Cases.begin(), Cases.end(), CaseCmp()); 1898 1899 // Merge case into clusters 1900 if (Cases.size()>=2) 1901 // Must recompute end() each iteration because it may be 1902 // invalidated by erase if we hold on to it 1903 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 1904 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 1905 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 1906 MachineBasicBlock* nextBB = J->BB; 1907 MachineBasicBlock* currentBB = I->BB; 1908 1909 // If the two neighboring cases go to the same destination, merge them 1910 // into a single case. 1911 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 1912 I->High = J->High; 1913 J = Cases.erase(J); 1914 } else { 1915 I = J++; 1916 } 1917 } 1918 1919 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1920 if (I->Low != I->High) 1921 // A range counts double, since it requires two compares. 1922 ++numCmps; 1923 } 1924 1925 return numCmps; 1926} 1927 1928void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 1929 // Figure out which block is immediately after the current one. 1930 MachineBasicBlock *NextBlock = 0; 1931 MachineFunction::iterator BBI = CurMBB; 1932 1933 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 1934 1935 // If there is only the default destination, branch to it if it is not the 1936 // next basic block. Otherwise, just fall through. 1937 if (SI.getNumOperands() == 2) { 1938 // Update machine-CFG edges. 1939 1940 // If this is not a fall-through branch, emit the branch. 1941 if (Default != NextBlock) 1942 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1943 DAG.getBasicBlock(Default))); 1944 1945 CurMBB->addSuccessor(Default); 1946 return; 1947 } 1948 1949 // If there are any non-default case statements, create a vector of Cases 1950 // representing each one, and sort the vector so that we can efficiently 1951 // create a binary search tree from them. 1952 CaseVector Cases; 1953 unsigned numCmps = Clusterify(Cases, SI); 1954 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 1955 << ". Total compares: " << numCmps << "\n"; 1956 1957 // Get the Value to be switched on and default basic blocks, which will be 1958 // inserted into CaseBlock records, representing basic blocks in the binary 1959 // search tree. 1960 Value *SV = SI.getOperand(0); 1961 1962 // Push the initial CaseRec onto the worklist 1963 CaseRecVector WorkList; 1964 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1965 1966 while (!WorkList.empty()) { 1967 // Grab a record representing a case range to process off the worklist 1968 CaseRec CR = WorkList.back(); 1969 WorkList.pop_back(); 1970 1971 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 1972 continue; 1973 1974 // If the range has few cases (two or less) emit a series of specific 1975 // tests. 1976 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 1977 continue; 1978 1979 // If the switch has more than 5 blocks, and at least 40% dense, and the 1980 // target supports indirect branches, then emit a jump table rather than 1981 // lowering the switch to a binary tree of conditional branches. 1982 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 1983 continue; 1984 1985 // Emit binary tree. We need to pick a pivot, and push left and right ranges 1986 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 1987 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 1988 } 1989} 1990 1991 1992void SelectionDAGLowering::visitSub(User &I) { 1993 // -0.0 - X --> fneg 1994 const Type *Ty = I.getType(); 1995 if (isa<VectorType>(Ty)) { 1996 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 1997 const VectorType *DestTy = cast<VectorType>(I.getType()); 1998 const Type *ElTy = DestTy->getElementType(); 1999 if (ElTy->isFloatingPoint()) { 2000 unsigned VL = DestTy->getNumElements(); 2001 std::vector<Constant*> NZ(VL, ConstantFP::get(ElTy, -0.0)); 2002 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2003 if (CV == CNZ) { 2004 SDOperand Op2 = getValue(I.getOperand(1)); 2005 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2006 return; 2007 } 2008 } 2009 } 2010 } 2011 if (Ty->isFloatingPoint()) { 2012 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2013 if (CFP->isExactlyValue(-0.0)) { 2014 SDOperand Op2 = getValue(I.getOperand(1)); 2015 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2016 return; 2017 } 2018 } 2019 2020 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2021} 2022 2023void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2024 SDOperand Op1 = getValue(I.getOperand(0)); 2025 SDOperand Op2 = getValue(I.getOperand(1)); 2026 2027 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2028} 2029 2030void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2031 SDOperand Op1 = getValue(I.getOperand(0)); 2032 SDOperand Op2 = getValue(I.getOperand(1)); 2033 2034 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) < 2035 MVT::getSizeInBits(Op2.getValueType())) 2036 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2037 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 2038 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2039 2040 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2041} 2042 2043void SelectionDAGLowering::visitICmp(User &I) { 2044 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2045 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2046 predicate = IC->getPredicate(); 2047 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2048 predicate = ICmpInst::Predicate(IC->getPredicate()); 2049 SDOperand Op1 = getValue(I.getOperand(0)); 2050 SDOperand Op2 = getValue(I.getOperand(1)); 2051 ISD::CondCode Opcode; 2052 switch (predicate) { 2053 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2054 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2055 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2056 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2057 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2058 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2059 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2060 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2061 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2062 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2063 default: 2064 assert(!"Invalid ICmp predicate value"); 2065 Opcode = ISD::SETEQ; 2066 break; 2067 } 2068 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2069} 2070 2071void SelectionDAGLowering::visitFCmp(User &I) { 2072 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2073 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2074 predicate = FC->getPredicate(); 2075 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2076 predicate = FCmpInst::Predicate(FC->getPredicate()); 2077 SDOperand Op1 = getValue(I.getOperand(0)); 2078 SDOperand Op2 = getValue(I.getOperand(1)); 2079 ISD::CondCode Condition, FOC, FPC; 2080 switch (predicate) { 2081 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2082 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2083 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2084 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2085 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2086 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2087 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2088 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 2089 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 2090 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2091 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2092 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2093 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2094 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2095 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2096 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2097 default: 2098 assert(!"Invalid FCmp predicate value"); 2099 FOC = FPC = ISD::SETFALSE; 2100 break; 2101 } 2102 if (FiniteOnlyFPMath()) 2103 Condition = FOC; 2104 else 2105 Condition = FPC; 2106 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2107} 2108 2109void SelectionDAGLowering::visitSelect(User &I) { 2110 SDOperand Cond = getValue(I.getOperand(0)); 2111 SDOperand TrueVal = getValue(I.getOperand(1)); 2112 SDOperand FalseVal = getValue(I.getOperand(2)); 2113 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2114 TrueVal, FalseVal)); 2115} 2116 2117 2118void SelectionDAGLowering::visitTrunc(User &I) { 2119 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2120 SDOperand N = getValue(I.getOperand(0)); 2121 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2122 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2123} 2124 2125void SelectionDAGLowering::visitZExt(User &I) { 2126 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2127 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2128 SDOperand N = getValue(I.getOperand(0)); 2129 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2130 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2131} 2132 2133void SelectionDAGLowering::visitSExt(User &I) { 2134 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2135 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2136 SDOperand N = getValue(I.getOperand(0)); 2137 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2138 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2139} 2140 2141void SelectionDAGLowering::visitFPTrunc(User &I) { 2142 // FPTrunc is never a no-op cast, no need to check 2143 SDOperand N = getValue(I.getOperand(0)); 2144 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2145 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 2146} 2147 2148void SelectionDAGLowering::visitFPExt(User &I){ 2149 // FPTrunc is never a no-op cast, no need to check 2150 SDOperand N = getValue(I.getOperand(0)); 2151 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2152 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2153} 2154 2155void SelectionDAGLowering::visitFPToUI(User &I) { 2156 // FPToUI is never a no-op cast, no need to check 2157 SDOperand N = getValue(I.getOperand(0)); 2158 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2159 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2160} 2161 2162void SelectionDAGLowering::visitFPToSI(User &I) { 2163 // FPToSI is never a no-op cast, no need to check 2164 SDOperand N = getValue(I.getOperand(0)); 2165 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2166 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2167} 2168 2169void SelectionDAGLowering::visitUIToFP(User &I) { 2170 // UIToFP is never a no-op cast, no need to check 2171 SDOperand N = getValue(I.getOperand(0)); 2172 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2173 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2174} 2175 2176void SelectionDAGLowering::visitSIToFP(User &I){ 2177 // UIToFP is never a no-op cast, no need to check 2178 SDOperand N = getValue(I.getOperand(0)); 2179 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2180 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2181} 2182 2183void SelectionDAGLowering::visitPtrToInt(User &I) { 2184 // What to do depends on the size of the integer and the size of the pointer. 2185 // We can either truncate, zero extend, or no-op, accordingly. 2186 SDOperand N = getValue(I.getOperand(0)); 2187 MVT::ValueType SrcVT = N.getValueType(); 2188 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2189 SDOperand Result; 2190 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2191 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2192 else 2193 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2194 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2195 setValue(&I, Result); 2196} 2197 2198void SelectionDAGLowering::visitIntToPtr(User &I) { 2199 // What to do depends on the size of the integer and the size of the pointer. 2200 // We can either truncate, zero extend, or no-op, accordingly. 2201 SDOperand N = getValue(I.getOperand(0)); 2202 MVT::ValueType SrcVT = N.getValueType(); 2203 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2204 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2205 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2206 else 2207 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2208 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2209} 2210 2211void SelectionDAGLowering::visitBitCast(User &I) { 2212 SDOperand N = getValue(I.getOperand(0)); 2213 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2214 2215 // BitCast assures us that source and destination are the same size so this 2216 // is either a BIT_CONVERT or a no-op. 2217 if (DestVT != N.getValueType()) 2218 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2219 else 2220 setValue(&I, N); // noop cast. 2221} 2222 2223void SelectionDAGLowering::visitInsertElement(User &I) { 2224 SDOperand InVec = getValue(I.getOperand(0)); 2225 SDOperand InVal = getValue(I.getOperand(1)); 2226 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2227 getValue(I.getOperand(2))); 2228 2229 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2230 TLI.getValueType(I.getType()), 2231 InVec, InVal, InIdx)); 2232} 2233 2234void SelectionDAGLowering::visitExtractElement(User &I) { 2235 SDOperand InVec = getValue(I.getOperand(0)); 2236 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2237 getValue(I.getOperand(1))); 2238 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2239 TLI.getValueType(I.getType()), InVec, InIdx)); 2240} 2241 2242void SelectionDAGLowering::visitShuffleVector(User &I) { 2243 SDOperand V1 = getValue(I.getOperand(0)); 2244 SDOperand V2 = getValue(I.getOperand(1)); 2245 SDOperand Mask = getValue(I.getOperand(2)); 2246 2247 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2248 TLI.getValueType(I.getType()), 2249 V1, V2, Mask)); 2250} 2251 2252 2253void SelectionDAGLowering::visitGetElementPtr(User &I) { 2254 SDOperand N = getValue(I.getOperand(0)); 2255 const Type *Ty = I.getOperand(0)->getType(); 2256 2257 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2258 OI != E; ++OI) { 2259 Value *Idx = *OI; 2260 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2261 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2262 if (Field) { 2263 // N = N + Offset 2264 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2265 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2266 getIntPtrConstant(Offset)); 2267 } 2268 Ty = StTy->getElementType(Field); 2269 } else { 2270 Ty = cast<SequentialType>(Ty)->getElementType(); 2271 2272 // If this is a constant subscript, handle it quickly. 2273 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2274 if (CI->getZExtValue() == 0) continue; 2275 uint64_t Offs = 2276 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2277 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 2278 continue; 2279 } 2280 2281 // N = N + Idx * ElementSize; 2282 uint64_t ElementSize = TD->getTypeSize(Ty); 2283 SDOperand IdxN = getValue(Idx); 2284 2285 // If the index is smaller or larger than intptr_t, truncate or extend 2286 // it. 2287 if (IdxN.getValueType() < N.getValueType()) { 2288 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2289 } else if (IdxN.getValueType() > N.getValueType()) 2290 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2291 2292 // If this is a multiply by a power of two, turn it into a shl 2293 // immediately. This is a very common case. 2294 if (isPowerOf2_64(ElementSize)) { 2295 unsigned Amt = Log2_64(ElementSize); 2296 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2297 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2298 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2299 continue; 2300 } 2301 2302 SDOperand Scale = getIntPtrConstant(ElementSize); 2303 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2304 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2305 } 2306 } 2307 setValue(&I, N); 2308} 2309 2310void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2311 // If this is a fixed sized alloca in the entry block of the function, 2312 // allocate it statically on the stack. 2313 if (FuncInfo.StaticAllocaMap.count(&I)) 2314 return; // getValue will auto-populate this. 2315 2316 const Type *Ty = I.getAllocatedType(); 2317 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 2318 unsigned Align = 2319 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2320 I.getAlignment()); 2321 2322 SDOperand AllocSize = getValue(I.getArraySize()); 2323 MVT::ValueType IntPtr = TLI.getPointerTy(); 2324 if (IntPtr < AllocSize.getValueType()) 2325 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2326 else if (IntPtr > AllocSize.getValueType()) 2327 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2328 2329 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2330 getIntPtrConstant(TySize)); 2331 2332 // Handle alignment. If the requested alignment is less than or equal to 2333 // the stack alignment, ignore it. If the size is greater than or equal to 2334 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2335 unsigned StackAlign = 2336 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2337 if (Align <= StackAlign) 2338 Align = 0; 2339 2340 // Round the size of the allocation up to the stack alignment size 2341 // by add SA-1 to the size. 2342 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2343 getIntPtrConstant(StackAlign-1)); 2344 // Mask out the low bits for alignment purposes. 2345 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2346 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2347 2348 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 2349 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2350 MVT::Other); 2351 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2352 setValue(&I, DSA); 2353 DAG.setRoot(DSA.getValue(1)); 2354 2355 // Inform the Frame Information that we have just allocated a variable-sized 2356 // object. 2357 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2358} 2359 2360void SelectionDAGLowering::visitLoad(LoadInst &I) { 2361 SDOperand Ptr = getValue(I.getOperand(0)); 2362 2363 SDOperand Root; 2364 if (I.isVolatile()) 2365 Root = getRoot(); 2366 else { 2367 // Do not serialize non-volatile loads against each other. 2368 Root = DAG.getRoot(); 2369 } 2370 2371 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2372 Root, I.isVolatile(), I.getAlignment())); 2373} 2374 2375SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2376 const Value *SV, SDOperand Root, 2377 bool isVolatile, 2378 unsigned Alignment) { 2379 SDOperand L = 2380 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2381 isVolatile, Alignment); 2382 2383 if (isVolatile) 2384 DAG.setRoot(L.getValue(1)); 2385 else 2386 PendingLoads.push_back(L.getValue(1)); 2387 2388 return L; 2389} 2390 2391 2392void SelectionDAGLowering::visitStore(StoreInst &I) { 2393 Value *SrcV = I.getOperand(0); 2394 SDOperand Src = getValue(SrcV); 2395 SDOperand Ptr = getValue(I.getOperand(1)); 2396 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2397 I.isVolatile(), I.getAlignment())); 2398} 2399 2400/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot 2401/// access memory and has no other side effects at all. 2402static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) { 2403#define GET_NO_MEMORY_INTRINSICS 2404#include "llvm/Intrinsics.gen" 2405#undef GET_NO_MEMORY_INTRINSICS 2406 return false; 2407} 2408 2409// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't 2410// have any side-effects or if it only reads memory. 2411static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) { 2412#define GET_SIDE_EFFECT_INFO 2413#include "llvm/Intrinsics.gen" 2414#undef GET_SIDE_EFFECT_INFO 2415 return false; 2416} 2417 2418/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2419/// node. 2420void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2421 unsigned Intrinsic) { 2422 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic); 2423 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic); 2424 2425 // Build the operand list. 2426 SmallVector<SDOperand, 8> Ops; 2427 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2428 if (OnlyLoad) { 2429 // We don't need to serialize loads against other loads. 2430 Ops.push_back(DAG.getRoot()); 2431 } else { 2432 Ops.push_back(getRoot()); 2433 } 2434 } 2435 2436 // Add the intrinsic ID as an integer operand. 2437 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2438 2439 // Add all operands of the call to the operand list. 2440 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2441 SDOperand Op = getValue(I.getOperand(i)); 2442 assert(TLI.isTypeLegal(Op.getValueType()) && 2443 "Intrinsic uses a non-legal type?"); 2444 Ops.push_back(Op); 2445 } 2446 2447 std::vector<MVT::ValueType> VTs; 2448 if (I.getType() != Type::VoidTy) { 2449 MVT::ValueType VT = TLI.getValueType(I.getType()); 2450 if (MVT::isVector(VT)) { 2451 const VectorType *DestTy = cast<VectorType>(I.getType()); 2452 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2453 2454 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2455 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2456 } 2457 2458 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2459 VTs.push_back(VT); 2460 } 2461 if (HasChain) 2462 VTs.push_back(MVT::Other); 2463 2464 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2465 2466 // Create the node. 2467 SDOperand Result; 2468 if (!HasChain) 2469 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2470 &Ops[0], Ops.size()); 2471 else if (I.getType() != Type::VoidTy) 2472 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2473 &Ops[0], Ops.size()); 2474 else 2475 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2476 &Ops[0], Ops.size()); 2477 2478 if (HasChain) { 2479 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2480 if (OnlyLoad) 2481 PendingLoads.push_back(Chain); 2482 else 2483 DAG.setRoot(Chain); 2484 } 2485 if (I.getType() != Type::VoidTy) { 2486 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2487 MVT::ValueType VT = TLI.getValueType(PTy); 2488 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 2489 } 2490 setValue(&I, Result); 2491 } 2492} 2493 2494/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 2495static GlobalVariable *ExtractTypeInfo (Value *V) { 2496 V = IntrinsicInst::StripPointerCasts(V); 2497 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 2498 assert (GV || isa<ConstantPointerNull>(V) && 2499 "TypeInfo must be a global variable or NULL"); 2500 return GV; 2501} 2502 2503/// addCatchInfo - Extract the personality and type infos from an eh.selector 2504/// call, and add them to the specified machine basic block. 2505static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 2506 MachineBasicBlock *MBB) { 2507 // Inform the MachineModuleInfo of the personality for this landing pad. 2508 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 2509 assert(CE->getOpcode() == Instruction::BitCast && 2510 isa<Function>(CE->getOperand(0)) && 2511 "Personality should be a function"); 2512 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 2513 2514 // Gather all the type infos for this landing pad and pass them along to 2515 // MachineModuleInfo. 2516 std::vector<GlobalVariable *> TyInfo; 2517 unsigned N = I.getNumOperands(); 2518 2519 for (unsigned i = N - 1; i > 2; --i) { 2520 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 2521 unsigned FilterLength = CI->getZExtValue(); 2522 unsigned FirstCatch = i + FilterLength + 1; 2523 assert (FirstCatch <= N && "Invalid filter length"); 2524 2525 if (FirstCatch < N) { 2526 TyInfo.reserve(N - FirstCatch); 2527 for (unsigned j = FirstCatch; j < N; ++j) 2528 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2529 MMI->addCatchTypeInfo(MBB, TyInfo); 2530 TyInfo.clear(); 2531 } 2532 2533 TyInfo.reserve(FilterLength); 2534 for (unsigned j = i + 1; j < FirstCatch; ++j) 2535 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2536 MMI->addFilterTypeInfo(MBB, TyInfo); 2537 TyInfo.clear(); 2538 2539 N = i; 2540 } 2541 } 2542 2543 if (N > 3) { 2544 TyInfo.reserve(N - 3); 2545 for (unsigned j = 3; j < N; ++j) 2546 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2547 MMI->addCatchTypeInfo(MBB, TyInfo); 2548 } 2549} 2550 2551/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2552/// we want to emit this as a call to a named external function, return the name 2553/// otherwise lower it and return null. 2554const char * 2555SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2556 switch (Intrinsic) { 2557 default: 2558 // By default, turn this into a target intrinsic node. 2559 visitTargetIntrinsic(I, Intrinsic); 2560 return 0; 2561 case Intrinsic::vastart: visitVAStart(I); return 0; 2562 case Intrinsic::vaend: visitVAEnd(I); return 0; 2563 case Intrinsic::vacopy: visitVACopy(I); return 0; 2564 case Intrinsic::returnaddress: 2565 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2566 getValue(I.getOperand(1)))); 2567 return 0; 2568 case Intrinsic::frameaddress: 2569 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2570 getValue(I.getOperand(1)))); 2571 return 0; 2572 case Intrinsic::setjmp: 2573 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2574 break; 2575 case Intrinsic::longjmp: 2576 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2577 break; 2578 case Intrinsic::memcpy_i32: 2579 case Intrinsic::memcpy_i64: 2580 visitMemIntrinsic(I, ISD::MEMCPY); 2581 return 0; 2582 case Intrinsic::memset_i32: 2583 case Intrinsic::memset_i64: 2584 visitMemIntrinsic(I, ISD::MEMSET); 2585 return 0; 2586 case Intrinsic::memmove_i32: 2587 case Intrinsic::memmove_i64: 2588 visitMemIntrinsic(I, ISD::MEMMOVE); 2589 return 0; 2590 2591 case Intrinsic::dbg_stoppoint: { 2592 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2593 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2594 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2595 SDOperand Ops[5]; 2596 2597 Ops[0] = getRoot(); 2598 Ops[1] = getValue(SPI.getLineValue()); 2599 Ops[2] = getValue(SPI.getColumnValue()); 2600 2601 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2602 assert(DD && "Not a debug information descriptor"); 2603 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2604 2605 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2606 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2607 2608 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2609 } 2610 2611 return 0; 2612 } 2613 case Intrinsic::dbg_region_start: { 2614 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2615 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2616 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2617 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2618 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2619 DAG.getConstant(LabelID, MVT::i32))); 2620 } 2621 2622 return 0; 2623 } 2624 case Intrinsic::dbg_region_end: { 2625 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2626 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2627 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2628 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2629 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2630 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2631 } 2632 2633 return 0; 2634 } 2635 case Intrinsic::dbg_func_start: { 2636 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2637 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2638 if (MMI && FSI.getSubprogram() && 2639 MMI->Verify(FSI.getSubprogram())) { 2640 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram()); 2641 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2642 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2643 } 2644 2645 return 0; 2646 } 2647 case Intrinsic::dbg_declare: { 2648 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2649 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2650 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) { 2651 SDOperand AddressOp = getValue(DI.getAddress()); 2652 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 2653 MMI->RecordVariable(DI.getVariable(), FI->getIndex()); 2654 } 2655 2656 return 0; 2657 } 2658 2659 case Intrinsic::eh_exception: { 2660 if (ExceptionHandling) { 2661 if (!CurMBB->isLandingPad()) { 2662 // FIXME: Mark exception register as live in. Hack for PR1508. 2663 unsigned Reg = TLI.getExceptionAddressRegister(); 2664 if (Reg) CurMBB->addLiveIn(Reg); 2665 } 2666 // Insert the EXCEPTIONADDR instruction. 2667 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2668 SDOperand Ops[1]; 2669 Ops[0] = DAG.getRoot(); 2670 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2671 setValue(&I, Op); 2672 DAG.setRoot(Op.getValue(1)); 2673 } else { 2674 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2675 } 2676 return 0; 2677 } 2678 2679 case Intrinsic::eh_selector:{ 2680 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2681 2682 if (ExceptionHandling && MMI) { 2683 if (CurMBB->isLandingPad()) 2684 addCatchInfo(I, MMI, CurMBB); 2685 else { 2686#ifndef NDEBUG 2687 FuncInfo.CatchInfoLost.insert(&I); 2688#endif 2689 // FIXME: Mark exception selector register as live in. Hack for PR1508. 2690 unsigned Reg = TLI.getExceptionSelectorRegister(); 2691 if (Reg) CurMBB->addLiveIn(Reg); 2692 } 2693 2694 // Insert the EHSELECTION instruction. 2695 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2696 SDOperand Ops[2]; 2697 Ops[0] = getValue(I.getOperand(1)); 2698 Ops[1] = getRoot(); 2699 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2700 setValue(&I, Op); 2701 DAG.setRoot(Op.getValue(1)); 2702 } else { 2703 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2704 } 2705 2706 return 0; 2707 } 2708 2709 case Intrinsic::eh_typeid_for: { 2710 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2711 2712 if (MMI) { 2713 // Find the type id for the given typeinfo. 2714 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 2715 2716 unsigned TypeID = MMI->getTypeIDFor(GV); 2717 setValue(&I, DAG.getConstant(TypeID, MVT::i32)); 2718 } else { 2719 // Return something different to eh_selector. 2720 setValue(&I, DAG.getConstant(1, MVT::i32)); 2721 } 2722 2723 return 0; 2724 } 2725 2726 case Intrinsic::eh_return: { 2727 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2728 2729 if (MMI && ExceptionHandling) { 2730 MMI->setCallsEHReturn(true); 2731 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, 2732 MVT::Other, 2733 getRoot(), 2734 getValue(I.getOperand(1)), 2735 getValue(I.getOperand(2)))); 2736 } else { 2737 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2738 } 2739 2740 return 0; 2741 } 2742 2743 case Intrinsic::eh_unwind_init: { 2744 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 2745 MMI->setCallsUnwindInit(true); 2746 } 2747 2748 return 0; 2749 } 2750 2751 case Intrinsic::eh_dwarf_cfa: { 2752 if (ExceptionHandling) { 2753 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType(); 2754 SDOperand CfaArg; 2755 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 2756 CfaArg = DAG.getNode(ISD::TRUNCATE, 2757 TLI.getPointerTy(), getValue(I.getOperand(1))); 2758 else 2759 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, 2760 TLI.getPointerTy(), getValue(I.getOperand(1))); 2761 2762 SDOperand Offset = DAG.getNode(ISD::ADD, 2763 TLI.getPointerTy(), 2764 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, 2765 TLI.getPointerTy()), 2766 CfaArg); 2767 setValue(&I, DAG.getNode(ISD::ADD, 2768 TLI.getPointerTy(), 2769 DAG.getNode(ISD::FRAMEADDR, 2770 TLI.getPointerTy(), 2771 DAG.getConstant(0, 2772 TLI.getPointerTy())), 2773 Offset)); 2774 } else { 2775 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2776 } 2777 2778 return 0; 2779 } 2780 2781 case Intrinsic::sqrt_f32: 2782 case Intrinsic::sqrt_f64: 2783 setValue(&I, DAG.getNode(ISD::FSQRT, 2784 getValue(I.getOperand(1)).getValueType(), 2785 getValue(I.getOperand(1)))); 2786 return 0; 2787 case Intrinsic::powi_f32: 2788 case Intrinsic::powi_f64: 2789 setValue(&I, DAG.getNode(ISD::FPOWI, 2790 getValue(I.getOperand(1)).getValueType(), 2791 getValue(I.getOperand(1)), 2792 getValue(I.getOperand(2)))); 2793 return 0; 2794 case Intrinsic::pcmarker: { 2795 SDOperand Tmp = getValue(I.getOperand(1)); 2796 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2797 return 0; 2798 } 2799 case Intrinsic::readcyclecounter: { 2800 SDOperand Op = getRoot(); 2801 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2802 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2803 &Op, 1); 2804 setValue(&I, Tmp); 2805 DAG.setRoot(Tmp.getValue(1)); 2806 return 0; 2807 } 2808 case Intrinsic::part_select: { 2809 // Currently not implemented: just abort 2810 assert(0 && "part_select intrinsic not implemented"); 2811 abort(); 2812 } 2813 case Intrinsic::part_set: { 2814 // Currently not implemented: just abort 2815 assert(0 && "part_set intrinsic not implemented"); 2816 abort(); 2817 } 2818 case Intrinsic::bswap: 2819 setValue(&I, DAG.getNode(ISD::BSWAP, 2820 getValue(I.getOperand(1)).getValueType(), 2821 getValue(I.getOperand(1)))); 2822 return 0; 2823 case Intrinsic::cttz: { 2824 SDOperand Arg = getValue(I.getOperand(1)); 2825 MVT::ValueType Ty = Arg.getValueType(); 2826 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2827 setValue(&I, result); 2828 return 0; 2829 } 2830 case Intrinsic::ctlz: { 2831 SDOperand Arg = getValue(I.getOperand(1)); 2832 MVT::ValueType Ty = Arg.getValueType(); 2833 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2834 setValue(&I, result); 2835 return 0; 2836 } 2837 case Intrinsic::ctpop: { 2838 SDOperand Arg = getValue(I.getOperand(1)); 2839 MVT::ValueType Ty = Arg.getValueType(); 2840 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2841 setValue(&I, result); 2842 return 0; 2843 } 2844 case Intrinsic::stacksave: { 2845 SDOperand Op = getRoot(); 2846 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2847 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2848 setValue(&I, Tmp); 2849 DAG.setRoot(Tmp.getValue(1)); 2850 return 0; 2851 } 2852 case Intrinsic::stackrestore: { 2853 SDOperand Tmp = getValue(I.getOperand(1)); 2854 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2855 return 0; 2856 } 2857 case Intrinsic::prefetch: 2858 // FIXME: Currently discarding prefetches. 2859 return 0; 2860 2861 case Intrinsic::var_annotation: 2862 // Discard annotate attributes 2863 return 0; 2864 2865 case Intrinsic::adjust_trampoline: { 2866 SDOperand Arg = getValue(I.getOperand(1)); 2867 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMP, TLI.getPointerTy(), Arg)); 2868 return 0; 2869 } 2870 2871 case Intrinsic::init_trampoline: { 2872 const Function *F = 2873 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2))); 2874 2875 SDOperand Ops[6]; 2876 Ops[0] = getRoot(); 2877 Ops[1] = getValue(I.getOperand(1)); 2878 Ops[2] = getValue(I.getOperand(2)); 2879 Ops[3] = getValue(I.getOperand(3)); 2880 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 2881 Ops[5] = DAG.getSrcValue(F); 2882 2883 DAG.setRoot(DAG.getNode(ISD::TRAMPOLINE, MVT::Other, Ops, 6)); 2884 return 0; 2885 } 2886 } 2887} 2888 2889 2890void SelectionDAGLowering::LowerCallTo(Instruction &I, 2891 const Type *CalledValueTy, 2892 unsigned CallingConv, 2893 bool IsTailCall, 2894 SDOperand Callee, unsigned OpIdx, 2895 MachineBasicBlock *LandingPad) { 2896 const PointerType *PT = cast<PointerType>(CalledValueTy); 2897 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 2898 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 2899 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2900 unsigned BeginLabel = 0, EndLabel = 0; 2901 2902 TargetLowering::ArgListTy Args; 2903 TargetLowering::ArgListEntry Entry; 2904 Args.reserve(I.getNumOperands()); 2905 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) { 2906 Value *Arg = I.getOperand(i); 2907 SDOperand ArgNode = getValue(Arg); 2908 Entry.Node = ArgNode; Entry.Ty = Arg->getType(); 2909 2910 unsigned attrInd = i - OpIdx + 1; 2911 Entry.isSExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::SExt); 2912 Entry.isZExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ZExt); 2913 Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg); 2914 Entry.isSRet = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet); 2915 Entry.isNest = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::Nest); 2916 Entry.isByVal = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ByVal); 2917 Args.push_back(Entry); 2918 } 2919 2920 if (ExceptionHandling && MMI) { 2921 // Insert a label before the invoke call to mark the try range. This can be 2922 // used to detect deletion of the invoke via the MachineModuleInfo. 2923 BeginLabel = MMI->NextLabelID(); 2924 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2925 DAG.getConstant(BeginLabel, MVT::i32))); 2926 } 2927 2928 std::pair<SDOperand,SDOperand> Result = 2929 TLI.LowerCallTo(getRoot(), I.getType(), 2930 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt), 2931 FTy->isVarArg(), CallingConv, IsTailCall, 2932 Callee, Args, DAG); 2933 if (I.getType() != Type::VoidTy) 2934 setValue(&I, Result.first); 2935 DAG.setRoot(Result.second); 2936 2937 if (ExceptionHandling && MMI) { 2938 // Insert a label at the end of the invoke call to mark the try range. This 2939 // can be used to detect deletion of the invoke via the MachineModuleInfo. 2940 EndLabel = MMI->NextLabelID(); 2941 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2942 DAG.getConstant(EndLabel, MVT::i32))); 2943 2944 // Inform MachineModuleInfo of range. 2945 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 2946 } 2947} 2948 2949 2950void SelectionDAGLowering::visitCall(CallInst &I) { 2951 const char *RenameFn = 0; 2952 if (Function *F = I.getCalledFunction()) { 2953 if (F->isDeclaration()) 2954 if (unsigned IID = F->getIntrinsicID()) { 2955 RenameFn = visitIntrinsicCall(I, IID); 2956 if (!RenameFn) 2957 return; 2958 } else { // Not an LLVM intrinsic. 2959 const std::string &Name = F->getName(); 2960 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) { 2961 if (I.getNumOperands() == 3 && // Basic sanity checks. 2962 I.getOperand(1)->getType()->isFloatingPoint() && 2963 I.getType() == I.getOperand(1)->getType() && 2964 I.getType() == I.getOperand(2)->getType()) { 2965 SDOperand LHS = getValue(I.getOperand(1)); 2966 SDOperand RHS = getValue(I.getOperand(2)); 2967 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 2968 LHS, RHS)); 2969 return; 2970 } 2971 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) { 2972 if (I.getNumOperands() == 2 && // Basic sanity checks. 2973 I.getOperand(1)->getType()->isFloatingPoint() && 2974 I.getType() == I.getOperand(1)->getType()) { 2975 SDOperand Tmp = getValue(I.getOperand(1)); 2976 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 2977 return; 2978 } 2979 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) { 2980 if (I.getNumOperands() == 2 && // Basic sanity checks. 2981 I.getOperand(1)->getType()->isFloatingPoint() && 2982 I.getType() == I.getOperand(1)->getType()) { 2983 SDOperand Tmp = getValue(I.getOperand(1)); 2984 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 2985 return; 2986 } 2987 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) { 2988 if (I.getNumOperands() == 2 && // Basic sanity checks. 2989 I.getOperand(1)->getType()->isFloatingPoint() && 2990 I.getType() == I.getOperand(1)->getType()) { 2991 SDOperand Tmp = getValue(I.getOperand(1)); 2992 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 2993 return; 2994 } 2995 } 2996 } 2997 } else if (isa<InlineAsm>(I.getOperand(0))) { 2998 visitInlineAsm(I); 2999 return; 3000 } 3001 3002 SDOperand Callee; 3003 if (!RenameFn) 3004 Callee = getValue(I.getOperand(0)); 3005 else 3006 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 3007 3008 LowerCallTo(I, I.getCalledValue()->getType(), 3009 I.getCallingConv(), 3010 I.isTailCall(), 3011 Callee, 3012 1); 3013} 3014 3015 3016/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 3017/// this value and returns the result as a ValueVT value. This uses 3018/// Chain/Flag as the input and updates them for the output Chain/Flag. 3019/// If the Flag pointer is NULL, no flag is used. 3020SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 3021 SDOperand &Chain, SDOperand *Flag)const{ 3022 // Copy the legal parts from the registers. 3023 unsigned NumParts = Regs.size(); 3024 SmallVector<SDOperand, 8> Parts(NumParts); 3025 for (unsigned i = 0; i != NumParts; ++i) { 3026 SDOperand Part = Flag ? 3027 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) : 3028 DAG.getCopyFromReg(Chain, Regs[i], RegVT); 3029 Chain = Part.getValue(1); 3030 if (Flag) 3031 *Flag = Part.getValue(2); 3032 Parts[i] = Part; 3033 } 3034 3035 // Assemble the legal parts into the final value. 3036 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT); 3037} 3038 3039/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 3040/// specified value into the registers specified by this object. This uses 3041/// Chain/Flag as the input and updates them for the output Chain/Flag. 3042/// If the Flag pointer is NULL, no flag is used. 3043void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 3044 SDOperand &Chain, SDOperand *Flag) const { 3045 // Get the list of the values's legal parts. 3046 unsigned NumParts = Regs.size(); 3047 SmallVector<SDOperand, 8> Parts(NumParts); 3048 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT); 3049 3050 // Copy the parts into the registers. 3051 for (unsigned i = 0; i != NumParts; ++i) { 3052 SDOperand Part = Flag ? 3053 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) : 3054 DAG.getCopyToReg(Chain, Regs[i], Parts[i]); 3055 Chain = Part.getValue(0); 3056 if (Flag) 3057 *Flag = Part.getValue(1); 3058 } 3059} 3060 3061/// AddInlineAsmOperands - Add this value to the specified inlineasm node 3062/// operand list. This adds the code marker and includes the number of 3063/// values added into it. 3064void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 3065 std::vector<SDOperand> &Ops) const { 3066 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3067 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3068 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 3069 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 3070} 3071 3072/// isAllocatableRegister - If the specified register is safe to allocate, 3073/// i.e. it isn't a stack pointer or some other special register, return the 3074/// register class for the register. Otherwise, return null. 3075static const TargetRegisterClass * 3076isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3077 const TargetLowering &TLI, const MRegisterInfo *MRI) { 3078 MVT::ValueType FoundVT = MVT::Other; 3079 const TargetRegisterClass *FoundRC = 0; 3080 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 3081 E = MRI->regclass_end(); RCI != E; ++RCI) { 3082 MVT::ValueType ThisVT = MVT::Other; 3083 3084 const TargetRegisterClass *RC = *RCI; 3085 // If none of the the value types for this register class are valid, we 3086 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3087 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3088 I != E; ++I) { 3089 if (TLI.isTypeLegal(*I)) { 3090 // If we have already found this register in a different register class, 3091 // choose the one with the largest VT specified. For example, on 3092 // PowerPC, we favor f64 register classes over f32. 3093 if (FoundVT == MVT::Other || 3094 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 3095 ThisVT = *I; 3096 break; 3097 } 3098 } 3099 } 3100 3101 if (ThisVT == MVT::Other) continue; 3102 3103 // NOTE: This isn't ideal. In particular, this might allocate the 3104 // frame pointer in functions that need it (due to them not being taken 3105 // out of allocation, because a variable sized allocation hasn't been seen 3106 // yet). This is a slight code pessimization, but should still work. 3107 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3108 E = RC->allocation_order_end(MF); I != E; ++I) 3109 if (*I == Reg) { 3110 // We found a matching register class. Keep looking at others in case 3111 // we find one with larger registers that this physreg is also in. 3112 FoundRC = RC; 3113 FoundVT = ThisVT; 3114 break; 3115 } 3116 } 3117 return FoundRC; 3118} 3119 3120 3121namespace { 3122/// AsmOperandInfo - This contains information for each constraint that we are 3123/// lowering. 3124struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 3125 /// ConstraintCode - This contains the actual string for the code, like "m". 3126 std::string ConstraintCode; 3127 3128 /// ConstraintType - Information about the constraint code, e.g. Register, 3129 /// RegisterClass, Memory, Other, Unknown. 3130 TargetLowering::ConstraintType ConstraintType; 3131 3132 /// CallOperand/CallOperandval - If this is the result output operand or a 3133 /// clobber, this is null, otherwise it is the incoming operand to the 3134 /// CallInst. This gets modified as the asm is processed. 3135 SDOperand CallOperand; 3136 Value *CallOperandVal; 3137 3138 /// ConstraintVT - The ValueType for the operand value. 3139 MVT::ValueType ConstraintVT; 3140 3141 /// AssignedRegs - If this is a register or register class operand, this 3142 /// contains the set of register corresponding to the operand. 3143 RegsForValue AssignedRegs; 3144 3145 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3146 : InlineAsm::ConstraintInfo(info), 3147 ConstraintType(TargetLowering::C_Unknown), 3148 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) { 3149 } 3150 3151 void ComputeConstraintToUse(const TargetLowering &TLI); 3152 3153 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3154 /// busy in OutputRegs/InputRegs. 3155 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3156 std::set<unsigned> &OutputRegs, 3157 std::set<unsigned> &InputRegs) const { 3158 if (isOutReg) 3159 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3160 if (isInReg) 3161 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3162 } 3163}; 3164} // end anon namespace. 3165 3166/// getConstraintGenerality - Return an integer indicating how general CT is. 3167static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3168 switch (CT) { 3169 default: assert(0 && "Unknown constraint type!"); 3170 case TargetLowering::C_Other: 3171 case TargetLowering::C_Unknown: 3172 return 0; 3173 case TargetLowering::C_Register: 3174 return 1; 3175 case TargetLowering::C_RegisterClass: 3176 return 2; 3177 case TargetLowering::C_Memory: 3178 return 3; 3179 } 3180} 3181 3182void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) { 3183 assert(!Codes.empty() && "Must have at least one constraint"); 3184 3185 std::string *Current = &Codes[0]; 3186 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current); 3187 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common. 3188 ConstraintCode = *Current; 3189 ConstraintType = CurType; 3190 return; 3191 } 3192 3193 unsigned CurGenerality = getConstraintGenerality(CurType); 3194 3195 // If we have multiple constraints, try to pick the most general one ahead 3196 // of time. This isn't a wonderful solution, but handles common cases. 3197 for (unsigned j = 1, e = Codes.size(); j != e; ++j) { 3198 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]); 3199 unsigned ThisGenerality = getConstraintGenerality(ThisType); 3200 if (ThisGenerality > CurGenerality) { 3201 // This constraint letter is more general than the previous one, 3202 // use it. 3203 CurType = ThisType; 3204 Current = &Codes[j]; 3205 CurGenerality = ThisGenerality; 3206 } 3207 } 3208 3209 ConstraintCode = *Current; 3210 ConstraintType = CurType; 3211} 3212 3213 3214void SelectionDAGLowering:: 3215GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 3216 std::set<unsigned> &OutputRegs, 3217 std::set<unsigned> &InputRegs) { 3218 // Compute whether this value requires an input register, an output register, 3219 // or both. 3220 bool isOutReg = false; 3221 bool isInReg = false; 3222 switch (OpInfo.Type) { 3223 case InlineAsm::isOutput: 3224 isOutReg = true; 3225 3226 // If this is an early-clobber output, or if there is an input 3227 // constraint that matches this, we need to reserve the input register 3228 // so no other inputs allocate to it. 3229 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3230 break; 3231 case InlineAsm::isInput: 3232 isInReg = true; 3233 isOutReg = false; 3234 break; 3235 case InlineAsm::isClobber: 3236 isOutReg = true; 3237 isInReg = true; 3238 break; 3239 } 3240 3241 3242 MachineFunction &MF = DAG.getMachineFunction(); 3243 std::vector<unsigned> Regs; 3244 3245 // If this is a constraint for a single physreg, or a constraint for a 3246 // register class, find it. 3247 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3248 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3249 OpInfo.ConstraintVT); 3250 3251 unsigned NumRegs = 1; 3252 if (OpInfo.ConstraintVT != MVT::Other) 3253 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3254 MVT::ValueType RegVT; 3255 MVT::ValueType ValueVT = OpInfo.ConstraintVT; 3256 3257 3258 // If this is a constraint for a specific physical register, like {r17}, 3259 // assign it now. 3260 if (PhysReg.first) { 3261 if (OpInfo.ConstraintVT == MVT::Other) 3262 ValueVT = *PhysReg.second->vt_begin(); 3263 3264 // Get the actual register value type. This is important, because the user 3265 // may have asked for (e.g.) the AX register in i32 type. We need to 3266 // remember that AX is actually i16 to get the right extension. 3267 RegVT = *PhysReg.second->vt_begin(); 3268 3269 // This is a explicit reference to a physical register. 3270 Regs.push_back(PhysReg.first); 3271 3272 // If this is an expanded reference, add the rest of the regs to Regs. 3273 if (NumRegs != 1) { 3274 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3275 TargetRegisterClass::iterator E = PhysReg.second->end(); 3276 for (; *I != PhysReg.first; ++I) 3277 assert(I != E && "Didn't find reg!"); 3278 3279 // Already added the first reg. 3280 --NumRegs; ++I; 3281 for (; NumRegs; --NumRegs, ++I) { 3282 assert(I != E && "Ran out of registers to allocate!"); 3283 Regs.push_back(*I); 3284 } 3285 } 3286 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3287 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3288 return; 3289 } 3290 3291 // Otherwise, if this was a reference to an LLVM register class, create vregs 3292 // for this reference. 3293 std::vector<unsigned> RegClassRegs; 3294 const TargetRegisterClass *RC = PhysReg.second; 3295 if (RC) { 3296 // If this is an early clobber or tied register, our regalloc doesn't know 3297 // how to maintain the constraint. If it isn't, go ahead and create vreg 3298 // and let the regalloc do the right thing. 3299 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 3300 // If there is some other early clobber and this is an input register, 3301 // then we are forced to pre-allocate the input reg so it doesn't 3302 // conflict with the earlyclobber. 3303 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 3304 RegVT = *PhysReg.second->vt_begin(); 3305 3306 if (OpInfo.ConstraintVT == MVT::Other) 3307 ValueVT = RegVT; 3308 3309 // Create the appropriate number of virtual registers. 3310 SSARegMap *RegMap = MF.getSSARegMap(); 3311 for (; NumRegs; --NumRegs) 3312 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second)); 3313 3314 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3315 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3316 return; 3317 } 3318 3319 // Otherwise, we can't allocate it. Let the code below figure out how to 3320 // maintain these constraints. 3321 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3322 3323 } else { 3324 // This is a reference to a register class that doesn't directly correspond 3325 // to an LLVM register class. Allocate NumRegs consecutive, available, 3326 // registers from the class. 3327 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3328 OpInfo.ConstraintVT); 3329 } 3330 3331 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 3332 unsigned NumAllocated = 0; 3333 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3334 unsigned Reg = RegClassRegs[i]; 3335 // See if this register is available. 3336 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3337 (isInReg && InputRegs.count(Reg))) { // Already used. 3338 // Make sure we find consecutive registers. 3339 NumAllocated = 0; 3340 continue; 3341 } 3342 3343 // Check to see if this register is allocatable (i.e. don't give out the 3344 // stack pointer). 3345 if (RC == 0) { 3346 RC = isAllocatableRegister(Reg, MF, TLI, MRI); 3347 if (!RC) { // Couldn't allocate this register. 3348 // Reset NumAllocated to make sure we return consecutive registers. 3349 NumAllocated = 0; 3350 continue; 3351 } 3352 } 3353 3354 // Okay, this register is good, we can use it. 3355 ++NumAllocated; 3356 3357 // If we allocated enough consecutive registers, succeed. 3358 if (NumAllocated == NumRegs) { 3359 unsigned RegStart = (i-NumAllocated)+1; 3360 unsigned RegEnd = i+1; 3361 // Mark all of the allocated registers used. 3362 for (unsigned i = RegStart; i != RegEnd; ++i) 3363 Regs.push_back(RegClassRegs[i]); 3364 3365 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 3366 OpInfo.ConstraintVT); 3367 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3368 return; 3369 } 3370 } 3371 3372 // Otherwise, we couldn't allocate enough registers for this. 3373 return; 3374} 3375 3376 3377/// visitInlineAsm - Handle a call to an InlineAsm object. 3378/// 3379void SelectionDAGLowering::visitInlineAsm(CallInst &I) { 3380 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0)); 3381 3382 /// ConstraintOperands - Information about all of the constraints. 3383 std::vector<AsmOperandInfo> ConstraintOperands; 3384 3385 SDOperand Chain = getRoot(); 3386 SDOperand Flag; 3387 3388 std::set<unsigned> OutputRegs, InputRegs; 3389 3390 // Do a prepass over the constraints, canonicalizing them, and building up the 3391 // ConstraintOperands list. 3392 std::vector<InlineAsm::ConstraintInfo> 3393 ConstraintInfos = IA->ParseConstraints(); 3394 3395 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 3396 // constraint. If so, we can't let the register allocator allocate any input 3397 // registers, because it will not know to avoid the earlyclobbered output reg. 3398 bool SawEarlyClobber = false; 3399 3400 unsigned OpNo = 1; // OpNo - The operand of the CallInst. 3401 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3402 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 3403 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 3404 3405 MVT::ValueType OpVT = MVT::Other; 3406 3407 // Compute the value type for each operand. 3408 switch (OpInfo.Type) { 3409 case InlineAsm::isOutput: 3410 if (!OpInfo.isIndirect) { 3411 // The return value of the call is this value. As such, there is no 3412 // corresponding argument. 3413 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3414 OpVT = TLI.getValueType(I.getType()); 3415 } else { 3416 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3417 } 3418 break; 3419 case InlineAsm::isInput: 3420 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3421 break; 3422 case InlineAsm::isClobber: 3423 // Nothing to do. 3424 break; 3425 } 3426 3427 // If this is an input or an indirect output, process the call argument. 3428 if (OpInfo.CallOperandVal) { 3429 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 3430 const Type *OpTy = OpInfo.CallOperandVal->getType(); 3431 // If this is an indirect operand, the operand is a pointer to the 3432 // accessed type. 3433 if (OpInfo.isIndirect) 3434 OpTy = cast<PointerType>(OpTy)->getElementType(); 3435 3436 // If OpTy is not a first-class value, it may be a struct/union that we 3437 // can tile with integers. 3438 if (!OpTy->isFirstClassType() && OpTy->isSized()) { 3439 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3440 switch (BitSize) { 3441 default: break; 3442 case 1: 3443 case 8: 3444 case 16: 3445 case 32: 3446 case 64: 3447 OpTy = IntegerType::get(BitSize); 3448 break; 3449 } 3450 } 3451 3452 OpVT = TLI.getValueType(OpTy, true); 3453 } 3454 3455 OpInfo.ConstraintVT = OpVT; 3456 3457 // Compute the constraint code and ConstraintType to use. 3458 OpInfo.ComputeConstraintToUse(TLI); 3459 3460 // Keep track of whether we see an earlyclobber. 3461 SawEarlyClobber |= OpInfo.isEarlyClobber; 3462 3463 // If this is a memory input, and if the operand is not indirect, do what we 3464 // need to to provide an address for the memory input. 3465 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 3466 !OpInfo.isIndirect) { 3467 assert(OpInfo.Type == InlineAsm::isInput && 3468 "Can only indirectify direct input operands!"); 3469 3470 // Memory operands really want the address of the value. If we don't have 3471 // an indirect input, put it in the constpool if we can, otherwise spill 3472 // it to a stack slot. 3473 3474 // If the operand is a float, integer, or vector constant, spill to a 3475 // constant pool entry to get its address. 3476 Value *OpVal = OpInfo.CallOperandVal; 3477 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 3478 isa<ConstantVector>(OpVal)) { 3479 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 3480 TLI.getPointerTy()); 3481 } else { 3482 // Otherwise, create a stack slot and emit a store to it before the 3483 // asm. 3484 const Type *Ty = OpVal->getType(); 3485 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3486 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3487 MachineFunction &MF = DAG.getMachineFunction(); 3488 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3489 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3490 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 3491 OpInfo.CallOperand = StackSlot; 3492 } 3493 3494 // There is no longer a Value* corresponding to this operand. 3495 OpInfo.CallOperandVal = 0; 3496 // It is now an indirect operand. 3497 OpInfo.isIndirect = true; 3498 } 3499 3500 // If this constraint is for a specific register, allocate it before 3501 // anything else. 3502 if (OpInfo.ConstraintType == TargetLowering::C_Register) 3503 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3504 } 3505 ConstraintInfos.clear(); 3506 3507 3508 // Second pass - Loop over all of the operands, assigning virtual or physregs 3509 // to registerclass operands. 3510 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3511 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3512 3513 // C_Register operands have already been allocated, Other/Memory don't need 3514 // to be. 3515 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 3516 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3517 } 3518 3519 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 3520 std::vector<SDOperand> AsmNodeOperands; 3521 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3522 AsmNodeOperands.push_back( 3523 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 3524 3525 3526 // Loop over all of the inputs, copying the operand values into the 3527 // appropriate registers and processing the output regs. 3528 RegsForValue RetValRegs; 3529 3530 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 3531 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3532 3533 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3534 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3535 3536 switch (OpInfo.Type) { 3537 case InlineAsm::isOutput: { 3538 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 3539 OpInfo.ConstraintType != TargetLowering::C_Register) { 3540 // Memory output, or 'other' output (e.g. 'X' constraint). 3541 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 3542 3543 // Add information to the INLINEASM node to know about this output. 3544 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3545 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3546 TLI.getPointerTy())); 3547 AsmNodeOperands.push_back(OpInfo.CallOperand); 3548 break; 3549 } 3550 3551 // Otherwise, this is a register or register class output. 3552 3553 // Copy the output from the appropriate register. Find a register that 3554 // we can use. 3555 if (OpInfo.AssignedRegs.Regs.empty()) { 3556 cerr << "Couldn't allocate output reg for contraint '" 3557 << OpInfo.ConstraintCode << "'!\n"; 3558 exit(1); 3559 } 3560 3561 if (!OpInfo.isIndirect) { 3562 // This is the result value of the call. 3563 assert(RetValRegs.Regs.empty() && 3564 "Cannot have multiple output constraints yet!"); 3565 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3566 RetValRegs = OpInfo.AssignedRegs; 3567 } else { 3568 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 3569 OpInfo.CallOperandVal)); 3570 } 3571 3572 // Add information to the INLINEASM node to know that this register is 3573 // set. 3574 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 3575 AsmNodeOperands); 3576 break; 3577 } 3578 case InlineAsm::isInput: { 3579 SDOperand InOperandVal = OpInfo.CallOperand; 3580 3581 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 3582 // If this is required to match an output register we have already set, 3583 // just use its register. 3584 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 3585 3586 // Scan until we find the definition we already emitted of this operand. 3587 // When we find it, create a RegsForValue operand. 3588 unsigned CurOp = 2; // The first operand. 3589 for (; OperandNo; --OperandNo) { 3590 // Advance to the next operand. 3591 unsigned NumOps = 3592 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3593 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3594 (NumOps & 7) == 4 /*MEM*/) && 3595 "Skipped past definitions?"); 3596 CurOp += (NumOps>>3)+1; 3597 } 3598 3599 unsigned NumOps = 3600 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3601 if ((NumOps & 7) == 2 /*REGDEF*/) { 3602 // Add NumOps>>3 registers to MatchedRegs. 3603 RegsForValue MatchedRegs; 3604 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3605 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3606 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3607 unsigned Reg = 3608 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3609 MatchedRegs.Regs.push_back(Reg); 3610 } 3611 3612 // Use the produced MatchedRegs object to 3613 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3614 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3615 break; 3616 } else { 3617 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3618 assert(0 && "matching constraints for memory operands unimp"); 3619 } 3620 } 3621 3622 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 3623 assert(!OpInfo.isIndirect && 3624 "Don't know how to handle indirect other inputs yet!"); 3625 3626 std::vector<SDOperand> Ops; 3627 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 3628 Ops, DAG); 3629 if (Ops.empty()) { 3630 cerr << "Invalid operand for inline asm constraint '" 3631 << OpInfo.ConstraintCode << "'!\n"; 3632 exit(1); 3633 } 3634 3635 // Add information to the INLINEASM node to know about this input. 3636 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 3637 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3638 TLI.getPointerTy())); 3639 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 3640 break; 3641 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 3642 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 3643 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 3644 "Memory operands expect pointer values"); 3645 3646 // Add information to the INLINEASM node to know about this input. 3647 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3648 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3649 TLI.getPointerTy())); 3650 AsmNodeOperands.push_back(InOperandVal); 3651 break; 3652 } 3653 3654 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 3655 OpInfo.ConstraintType == TargetLowering::C_Register) && 3656 "Unknown constraint type!"); 3657 assert(!OpInfo.isIndirect && 3658 "Don't know how to handle indirect register inputs yet!"); 3659 3660 // Copy the input into the appropriate registers. 3661 assert(!OpInfo.AssignedRegs.Regs.empty() && 3662 "Couldn't allocate input reg!"); 3663 3664 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3665 3666 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 3667 AsmNodeOperands); 3668 break; 3669 } 3670 case InlineAsm::isClobber: { 3671 // Add the clobbered value to the operand list, so that the register 3672 // allocator is aware that the physreg got clobbered. 3673 if (!OpInfo.AssignedRegs.Regs.empty()) 3674 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 3675 AsmNodeOperands); 3676 break; 3677 } 3678 } 3679 } 3680 3681 // Finish up input operands. 3682 AsmNodeOperands[0] = Chain; 3683 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3684 3685 Chain = DAG.getNode(ISD::INLINEASM, 3686 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3687 &AsmNodeOperands[0], AsmNodeOperands.size()); 3688 Flag = Chain.getValue(1); 3689 3690 // If this asm returns a register value, copy the result from that register 3691 // and set it as the value of the call. 3692 if (!RetValRegs.Regs.empty()) { 3693 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 3694 3695 // If the result of the inline asm is a vector, it may have the wrong 3696 // width/num elts. Make sure to convert it to the right type with 3697 // bit_convert. 3698 if (MVT::isVector(Val.getValueType())) { 3699 const VectorType *VTy = cast<VectorType>(I.getType()); 3700 MVT::ValueType DesiredVT = TLI.getValueType(VTy); 3701 3702 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val); 3703 } 3704 3705 setValue(&I, Val); 3706 } 3707 3708 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 3709 3710 // Process indirect outputs, first output all of the flagged copies out of 3711 // physregs. 3712 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 3713 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 3714 Value *Ptr = IndirectStoresToEmit[i].second; 3715 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 3716 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 3717 } 3718 3719 // Emit the non-flagged stores from the physregs. 3720 SmallVector<SDOperand, 8> OutChains; 3721 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 3722 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 3723 getValue(StoresToEmit[i].second), 3724 StoresToEmit[i].second, 0)); 3725 if (!OutChains.empty()) 3726 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3727 &OutChains[0], OutChains.size()); 3728 DAG.setRoot(Chain); 3729} 3730 3731 3732void SelectionDAGLowering::visitMalloc(MallocInst &I) { 3733 SDOperand Src = getValue(I.getOperand(0)); 3734 3735 MVT::ValueType IntPtr = TLI.getPointerTy(); 3736 3737 if (IntPtr < Src.getValueType()) 3738 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 3739 else if (IntPtr > Src.getValueType()) 3740 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 3741 3742 // Scale the source by the type size. 3743 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType()); 3744 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 3745 Src, getIntPtrConstant(ElementSize)); 3746 3747 TargetLowering::ArgListTy Args; 3748 TargetLowering::ArgListEntry Entry; 3749 Entry.Node = Src; 3750 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3751 Args.push_back(Entry); 3752 3753 std::pair<SDOperand,SDOperand> Result = 3754 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true, 3755 DAG.getExternalSymbol("malloc", IntPtr), 3756 Args, DAG); 3757 setValue(&I, Result.first); // Pointers always fit in registers 3758 DAG.setRoot(Result.second); 3759} 3760 3761void SelectionDAGLowering::visitFree(FreeInst &I) { 3762 TargetLowering::ArgListTy Args; 3763 TargetLowering::ArgListEntry Entry; 3764 Entry.Node = getValue(I.getOperand(0)); 3765 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3766 Args.push_back(Entry); 3767 MVT::ValueType IntPtr = TLI.getPointerTy(); 3768 std::pair<SDOperand,SDOperand> Result = 3769 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true, 3770 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 3771 DAG.setRoot(Result.second); 3772} 3773 3774// InsertAtEndOfBasicBlock - This method should be implemented by targets that 3775// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 3776// instructions are special in various ways, which require special support to 3777// insert. The specified MachineInstr is created but not inserted into any 3778// basic blocks, and the scheduler passes ownership of it to this method. 3779MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3780 MachineBasicBlock *MBB) { 3781 cerr << "If a target marks an instruction with " 3782 << "'usesCustomDAGSchedInserter', it must implement " 3783 << "TargetLowering::InsertAtEndOfBasicBlock!\n"; 3784 abort(); 3785 return 0; 3786} 3787 3788void SelectionDAGLowering::visitVAStart(CallInst &I) { 3789 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 3790 getValue(I.getOperand(1)), 3791 DAG.getSrcValue(I.getOperand(1)))); 3792} 3793 3794void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 3795 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 3796 getValue(I.getOperand(0)), 3797 DAG.getSrcValue(I.getOperand(0))); 3798 setValue(&I, V); 3799 DAG.setRoot(V.getValue(1)); 3800} 3801 3802void SelectionDAGLowering::visitVAEnd(CallInst &I) { 3803 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 3804 getValue(I.getOperand(1)), 3805 DAG.getSrcValue(I.getOperand(1)))); 3806} 3807 3808void SelectionDAGLowering::visitVACopy(CallInst &I) { 3809 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 3810 getValue(I.getOperand(1)), 3811 getValue(I.getOperand(2)), 3812 DAG.getSrcValue(I.getOperand(1)), 3813 DAG.getSrcValue(I.getOperand(2)))); 3814} 3815 3816/// TargetLowering::LowerArguments - This is the default LowerArguments 3817/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 3818/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 3819/// integrated into SDISel. 3820std::vector<SDOperand> 3821TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 3822 const FunctionType *FTy = F.getFunctionType(); 3823 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 3824 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 3825 std::vector<SDOperand> Ops; 3826 Ops.push_back(DAG.getRoot()); 3827 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 3828 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 3829 3830 // Add one result value for each formal argument. 3831 std::vector<MVT::ValueType> RetVals; 3832 unsigned j = 1; 3833 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 3834 I != E; ++I, ++j) { 3835 MVT::ValueType VT = getValueType(I->getType()); 3836 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3837 unsigned OriginalAlignment = 3838 getTargetData()->getABITypeAlignment(I->getType()); 3839 3840 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 3841 // that is zero extended! 3842 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt)) 3843 Flags &= ~(ISD::ParamFlags::SExt); 3844 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt)) 3845 Flags |= ISD::ParamFlags::SExt; 3846 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg)) 3847 Flags |= ISD::ParamFlags::InReg; 3848 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet)) 3849 Flags |= ISD::ParamFlags::StructReturn; 3850 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ByVal)) { 3851 Flags |= ISD::ParamFlags::ByVal; 3852 const PointerType *Ty = cast<PointerType>(I->getType()); 3853 const StructType *STy = cast<StructType>(Ty->getElementType()); 3854 unsigned StructAlign = Log2_32(getTargetData()->getABITypeAlignment(STy)); 3855 unsigned StructSize = getTargetData()->getTypeSize(STy); 3856 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs); 3857 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs); 3858 } 3859 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::Nest)) 3860 Flags |= ISD::ParamFlags::Nest; 3861 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs); 3862 3863 switch (getTypeAction(VT)) { 3864 default: assert(0 && "Unknown type action!"); 3865 case Legal: 3866 RetVals.push_back(VT); 3867 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3868 break; 3869 case Promote: 3870 RetVals.push_back(getTypeToTransformTo(VT)); 3871 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3872 break; 3873 case Expand: { 3874 // If this is an illegal type, it needs to be broken up to fit into 3875 // registers. 3876 MVT::ValueType RegisterVT = getRegisterType(VT); 3877 unsigned NumRegs = getNumRegisters(VT); 3878 for (unsigned i = 0; i != NumRegs; ++i) { 3879 RetVals.push_back(RegisterVT); 3880 // if it isn't first piece, alignment must be 1 3881 if (i > 0) 3882 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3883 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3884 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3885 } 3886 break; 3887 } 3888 } 3889 } 3890 3891 RetVals.push_back(MVT::Other); 3892 3893 // Create the node. 3894 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 3895 DAG.getNodeValueTypes(RetVals), RetVals.size(), 3896 &Ops[0], Ops.size()).Val; 3897 unsigned NumArgRegs = Result->getNumValues() - 1; 3898 DAG.setRoot(SDOperand(Result, NumArgRegs)); 3899 3900 // Set up the return result vector. 3901 Ops.clear(); 3902 unsigned i = 0; 3903 unsigned Idx = 1; 3904 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 3905 ++I, ++Idx) { 3906 MVT::ValueType VT = getValueType(I->getType()); 3907 3908 switch (getTypeAction(VT)) { 3909 default: assert(0 && "Unknown type action!"); 3910 case Legal: 3911 Ops.push_back(SDOperand(Result, i++)); 3912 break; 3913 case Promote: { 3914 SDOperand Op(Result, i++); 3915 if (MVT::isInteger(VT)) { 3916 if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt)) 3917 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, 3918 DAG.getValueType(VT)); 3919 else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt)) 3920 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, 3921 DAG.getValueType(VT)); 3922 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3923 } else { 3924 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3925 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 3926 } 3927 Ops.push_back(Op); 3928 break; 3929 } 3930 case Expand: { 3931 MVT::ValueType PartVT = getRegisterType(VT); 3932 unsigned NumParts = getNumRegisters(VT); 3933 SmallVector<SDOperand, 4> Parts(NumParts); 3934 for (unsigned j = 0; j != NumParts; ++j) 3935 Parts[j] = SDOperand(Result, i++); 3936 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT)); 3937 break; 3938 } 3939 } 3940 } 3941 assert(i == NumArgRegs && "Argument register count mismatch!"); 3942 return Ops; 3943} 3944 3945 3946/// TargetLowering::LowerCallTo - This is the default LowerCallTo 3947/// implementation, which just inserts an ISD::CALL node, which is later custom 3948/// lowered by the target to something concrete. FIXME: When all targets are 3949/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 3950std::pair<SDOperand, SDOperand> 3951TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 3952 bool RetTyIsSigned, bool isVarArg, 3953 unsigned CallingConv, bool isTailCall, 3954 SDOperand Callee, 3955 ArgListTy &Args, SelectionDAG &DAG) { 3956 SmallVector<SDOperand, 32> Ops; 3957 Ops.push_back(Chain); // Op#0 - Chain 3958 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 3959 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 3960 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 3961 Ops.push_back(Callee); 3962 3963 // Handle all of the outgoing arguments. 3964 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 3965 MVT::ValueType VT = getValueType(Args[i].Ty); 3966 SDOperand Op = Args[i].Node; 3967 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3968 unsigned OriginalAlignment = 3969 getTargetData()->getABITypeAlignment(Args[i].Ty); 3970 3971 if (Args[i].isSExt) 3972 Flags |= ISD::ParamFlags::SExt; 3973 if (Args[i].isZExt) 3974 Flags |= ISD::ParamFlags::ZExt; 3975 if (Args[i].isInReg) 3976 Flags |= ISD::ParamFlags::InReg; 3977 if (Args[i].isSRet) 3978 Flags |= ISD::ParamFlags::StructReturn; 3979 if (Args[i].isByVal) { 3980 Flags |= ISD::ParamFlags::ByVal; 3981 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 3982 const StructType *STy = cast<StructType>(Ty->getElementType()); 3983 unsigned StructAlign = Log2_32(getTargetData()->getABITypeAlignment(STy)); 3984 unsigned StructSize = getTargetData()->getTypeSize(STy); 3985 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs); 3986 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs); 3987 } 3988 if (Args[i].isNest) 3989 Flags |= ISD::ParamFlags::Nest; 3990 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs; 3991 3992 switch (getTypeAction(VT)) { 3993 default: assert(0 && "Unknown type action!"); 3994 case Legal: 3995 Ops.push_back(Op); 3996 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3997 break; 3998 case Promote: 3999 if (MVT::isInteger(VT)) { 4000 unsigned ExtOp; 4001 if (Args[i].isSExt) 4002 ExtOp = ISD::SIGN_EXTEND; 4003 else if (Args[i].isZExt) 4004 ExtOp = ISD::ZERO_EXTEND; 4005 else 4006 ExtOp = ISD::ANY_EXTEND; 4007 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 4008 } else { 4009 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 4010 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 4011 } 4012 Ops.push_back(Op); 4013 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4014 break; 4015 case Expand: { 4016 MVT::ValueType PartVT = getRegisterType(VT); 4017 unsigned NumParts = getNumRegisters(VT); 4018 SmallVector<SDOperand, 4> Parts(NumParts); 4019 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT); 4020 for (unsigned i = 0; i != NumParts; ++i) { 4021 // if it isn't first piece, alignment must be 1 4022 unsigned MyFlags = Flags; 4023 if (i != 0) 4024 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) | 4025 (1 << ISD::ParamFlags::OrigAlignmentOffs); 4026 4027 Ops.push_back(Parts[i]); 4028 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32)); 4029 } 4030 break; 4031 } 4032 } 4033 } 4034 4035 // Figure out the result value types. 4036 MVT::ValueType VT = getValueType(RetTy); 4037 MVT::ValueType RegisterVT = getRegisterType(VT); 4038 unsigned NumRegs = getNumRegisters(VT); 4039 SmallVector<MVT::ValueType, 4> RetTys(NumRegs); 4040 for (unsigned i = 0; i != NumRegs; ++i) 4041 RetTys[i] = RegisterVT; 4042 4043 RetTys.push_back(MVT::Other); // Always has a chain. 4044 4045 // Create the CALL node. 4046 SDOperand Res = DAG.getNode(ISD::CALL, 4047 DAG.getVTList(&RetTys[0], NumRegs + 1), 4048 &Ops[0], Ops.size()); 4049 Chain = Res.getValue(NumRegs); 4050 4051 // Gather up the call result into a single value. 4052 if (RetTy != Type::VoidTy) { 4053 ISD::NodeType AssertOp = ISD::AssertSext; 4054 if (!RetTyIsSigned) 4055 AssertOp = ISD::AssertZext; 4056 SmallVector<SDOperand, 4> Results(NumRegs); 4057 for (unsigned i = 0; i != NumRegs; ++i) 4058 Results[i] = Res.getValue(i); 4059 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp); 4060 } 4061 4062 return std::make_pair(Res, Chain); 4063} 4064 4065SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4066 assert(0 && "LowerOperation not implemented for this target!"); 4067 abort(); 4068 return SDOperand(); 4069} 4070 4071SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 4072 SelectionDAG &DAG) { 4073 assert(0 && "CustomPromoteOperation not implemented for this target!"); 4074 abort(); 4075 return SDOperand(); 4076} 4077 4078/// getMemsetValue - Vectorized representation of the memset value 4079/// operand. 4080static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 4081 SelectionDAG &DAG) { 4082 MVT::ValueType CurVT = VT; 4083 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 4084 uint64_t Val = C->getValue() & 255; 4085 unsigned Shift = 8; 4086 while (CurVT != MVT::i8) { 4087 Val = (Val << Shift) | Val; 4088 Shift <<= 1; 4089 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4090 } 4091 return DAG.getConstant(Val, VT); 4092 } else { 4093 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4094 unsigned Shift = 8; 4095 while (CurVT != MVT::i8) { 4096 Value = 4097 DAG.getNode(ISD::OR, VT, 4098 DAG.getNode(ISD::SHL, VT, Value, 4099 DAG.getConstant(Shift, MVT::i8)), Value); 4100 Shift <<= 1; 4101 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4102 } 4103 4104 return Value; 4105 } 4106} 4107 4108/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4109/// used when a memcpy is turned into a memset when the source is a constant 4110/// string ptr. 4111static SDOperand getMemsetStringVal(MVT::ValueType VT, 4112 SelectionDAG &DAG, TargetLowering &TLI, 4113 std::string &Str, unsigned Offset) { 4114 uint64_t Val = 0; 4115 unsigned MSB = MVT::getSizeInBits(VT) / 8; 4116 if (TLI.isLittleEndian()) 4117 Offset = Offset + MSB - 1; 4118 for (unsigned i = 0; i != MSB; ++i) { 4119 Val = (Val << 8) | (unsigned char)Str[Offset]; 4120 Offset += TLI.isLittleEndian() ? -1 : 1; 4121 } 4122 return DAG.getConstant(Val, VT); 4123} 4124 4125/// getMemBasePlusOffset - Returns base and offset node for the 4126static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4127 SelectionDAG &DAG, TargetLowering &TLI) { 4128 MVT::ValueType VT = Base.getValueType(); 4129 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4130} 4131 4132/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4133/// to replace the memset / memcpy is below the threshold. It also returns the 4134/// types of the sequence of memory ops to perform memset / memcpy. 4135static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4136 unsigned Limit, uint64_t Size, 4137 unsigned Align, TargetLowering &TLI) { 4138 MVT::ValueType VT; 4139 4140 if (TLI.allowsUnalignedMemoryAccesses()) { 4141 VT = MVT::i64; 4142 } else { 4143 switch (Align & 7) { 4144 case 0: 4145 VT = MVT::i64; 4146 break; 4147 case 4: 4148 VT = MVT::i32; 4149 break; 4150 case 2: 4151 VT = MVT::i16; 4152 break; 4153 default: 4154 VT = MVT::i8; 4155 break; 4156 } 4157 } 4158 4159 MVT::ValueType LVT = MVT::i64; 4160 while (!TLI.isTypeLegal(LVT)) 4161 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4162 assert(MVT::isInteger(LVT)); 4163 4164 if (VT > LVT) 4165 VT = LVT; 4166 4167 unsigned NumMemOps = 0; 4168 while (Size != 0) { 4169 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4170 while (VTSize > Size) { 4171 VT = (MVT::ValueType)((unsigned)VT - 1); 4172 VTSize >>= 1; 4173 } 4174 assert(MVT::isInteger(VT)); 4175 4176 if (++NumMemOps > Limit) 4177 return false; 4178 MemOps.push_back(VT); 4179 Size -= VTSize; 4180 } 4181 4182 return true; 4183} 4184 4185void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4186 SDOperand Op1 = getValue(I.getOperand(1)); 4187 SDOperand Op2 = getValue(I.getOperand(2)); 4188 SDOperand Op3 = getValue(I.getOperand(3)); 4189 SDOperand Op4 = getValue(I.getOperand(4)); 4190 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4191 if (Align == 0) Align = 1; 4192 4193 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4194 std::vector<MVT::ValueType> MemOps; 4195 4196 // Expand memset / memcpy to a series of load / store ops 4197 // if the size operand falls below a certain threshold. 4198 SmallVector<SDOperand, 8> OutChains; 4199 switch (Op) { 4200 default: break; // Do nothing for now. 4201 case ISD::MEMSET: { 4202 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4203 Size->getValue(), Align, TLI)) { 4204 unsigned NumMemOps = MemOps.size(); 4205 unsigned Offset = 0; 4206 for (unsigned i = 0; i < NumMemOps; i++) { 4207 MVT::ValueType VT = MemOps[i]; 4208 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4209 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4210 SDOperand Store = DAG.getStore(getRoot(), Value, 4211 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4212 I.getOperand(1), Offset); 4213 OutChains.push_back(Store); 4214 Offset += VTSize; 4215 } 4216 } 4217 break; 4218 } 4219 case ISD::MEMCPY: { 4220 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4221 Size->getValue(), Align, TLI)) { 4222 unsigned NumMemOps = MemOps.size(); 4223 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4224 GlobalAddressSDNode *G = NULL; 4225 std::string Str; 4226 bool CopyFromStr = false; 4227 4228 if (Op2.getOpcode() == ISD::GlobalAddress) 4229 G = cast<GlobalAddressSDNode>(Op2); 4230 else if (Op2.getOpcode() == ISD::ADD && 4231 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4232 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4233 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4234 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4235 } 4236 if (G) { 4237 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4238 if (GV && GV->isConstant()) { 4239 Str = GV->getStringValue(false); 4240 if (!Str.empty()) { 4241 CopyFromStr = true; 4242 SrcOff += SrcDelta; 4243 } 4244 } 4245 } 4246 4247 for (unsigned i = 0; i < NumMemOps; i++) { 4248 MVT::ValueType VT = MemOps[i]; 4249 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4250 SDOperand Value, Chain, Store; 4251 4252 if (CopyFromStr) { 4253 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4254 Chain = getRoot(); 4255 Store = 4256 DAG.getStore(Chain, Value, 4257 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4258 I.getOperand(1), DstOff); 4259 } else { 4260 Value = DAG.getLoad(VT, getRoot(), 4261 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4262 I.getOperand(2), SrcOff); 4263 Chain = Value.getValue(1); 4264 Store = 4265 DAG.getStore(Chain, Value, 4266 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4267 I.getOperand(1), DstOff); 4268 } 4269 OutChains.push_back(Store); 4270 SrcOff += VTSize; 4271 DstOff += VTSize; 4272 } 4273 } 4274 break; 4275 } 4276 } 4277 4278 if (!OutChains.empty()) { 4279 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4280 &OutChains[0], OutChains.size())); 4281 return; 4282 } 4283 } 4284 4285 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4)); 4286} 4287 4288//===----------------------------------------------------------------------===// 4289// SelectionDAGISel code 4290//===----------------------------------------------------------------------===// 4291 4292unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4293 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 4294} 4295 4296void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4297 AU.addRequired<AliasAnalysis>(); 4298 AU.setPreservesAll(); 4299} 4300 4301 4302 4303bool SelectionDAGISel::runOnFunction(Function &Fn) { 4304 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4305 RegMap = MF.getSSARegMap(); 4306 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4307 4308 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4309 4310 if (ExceptionHandling) 4311 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4312 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4313 // Mark landing pad. 4314 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4315 4316 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4317 SelectBasicBlock(I, MF, FuncInfo); 4318 4319 // Add function live-ins to entry block live-in set. 4320 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4321 BB = FuncInfo.MBBMap[EntryBB]; 4322 if (!MF.livein_empty()) 4323 for (MachineFunction::livein_iterator I = MF.livein_begin(), 4324 E = MF.livein_end(); I != E; ++I) 4325 BB->addLiveIn(I->first); 4326 4327#ifndef NDEBUG 4328 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4329 "Not all catch info was assigned to a landing pad!"); 4330#endif 4331 4332 return true; 4333} 4334 4335SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4336 unsigned Reg) { 4337 SDOperand Op = getValue(V); 4338 assert((Op.getOpcode() != ISD::CopyFromReg || 4339 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4340 "Copy from a reg to the same reg!"); 4341 4342 MVT::ValueType SrcVT = Op.getValueType(); 4343 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT); 4344 unsigned NumRegs = TLI.getNumRegisters(SrcVT); 4345 SmallVector<SDOperand, 8> Regs(NumRegs); 4346 SmallVector<SDOperand, 8> Chains(NumRegs); 4347 4348 // Copy the value by legal parts into sequential virtual registers. 4349 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT); 4350 for (unsigned i = 0; i != NumRegs; ++i) 4351 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); 4352 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 4353} 4354 4355void SelectionDAGISel:: 4356LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4357 std::vector<SDOperand> &UnorderedChains) { 4358 // If this is the entry block, emit arguments. 4359 Function &F = *LLVMBB->getParent(); 4360 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4361 SDOperand OldRoot = SDL.DAG.getRoot(); 4362 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4363 4364 unsigned a = 0; 4365 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4366 AI != E; ++AI, ++a) 4367 if (!AI->use_empty()) { 4368 SDL.setValue(AI, Args[a]); 4369 4370 // If this argument is live outside of the entry block, insert a copy from 4371 // whereever we got it to the vreg that other BB's will reference it as. 4372 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4373 if (VMI != FuncInfo.ValueMap.end()) { 4374 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4375 UnorderedChains.push_back(Copy); 4376 } 4377 } 4378 4379 // Finally, if the target has anything special to do, allow it to do so. 4380 // FIXME: this should insert code into the DAG! 4381 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4382} 4383 4384static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4385 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4386 assert(!FLI.MBBMap[SrcBB]->isLandingPad() && 4387 "Copying catch info out of a landing pad!"); 4388 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4389 if (isSelector(I)) { 4390 // Apply the catch info to DestBB. 4391 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4392#ifndef NDEBUG 4393 FLI.CatchInfoFound.insert(I); 4394#endif 4395 } 4396} 4397 4398void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4399 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4400 FunctionLoweringInfo &FuncInfo) { 4401 SelectionDAGLowering SDL(DAG, TLI, FuncInfo); 4402 4403 std::vector<SDOperand> UnorderedChains; 4404 4405 // Lower any arguments needed in this block if this is the entry block. 4406 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4407 LowerArguments(LLVMBB, SDL, UnorderedChains); 4408 4409 BB = FuncInfo.MBBMap[LLVMBB]; 4410 SDL.setCurrentBasicBlock(BB); 4411 4412 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4413 4414 if (ExceptionHandling && MMI && BB->isLandingPad()) { 4415 // Add a label to mark the beginning of the landing pad. Deletion of the 4416 // landing pad can thus be detected via the MachineModuleInfo. 4417 unsigned LabelID = MMI->addLandingPad(BB); 4418 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 4419 DAG.getConstant(LabelID, MVT::i32))); 4420 4421 // Mark exception register as live in. 4422 unsigned Reg = TLI.getExceptionAddressRegister(); 4423 if (Reg) BB->addLiveIn(Reg); 4424 4425 // Mark exception selector register as live in. 4426 Reg = TLI.getExceptionSelectorRegister(); 4427 if (Reg) BB->addLiveIn(Reg); 4428 4429 // FIXME: Hack around an exception handling flaw (PR1508): the personality 4430 // function and list of typeids logically belong to the invoke (or, if you 4431 // like, the basic block containing the invoke), and need to be associated 4432 // with it in the dwarf exception handling tables. Currently however the 4433 // information is provided by an intrinsic (eh.selector) that can be moved 4434 // to unexpected places by the optimizers: if the unwind edge is critical, 4435 // then breaking it can result in the intrinsics being in the successor of 4436 // the landing pad, not the landing pad itself. This results in exceptions 4437 // not being caught because no typeids are associated with the invoke. 4438 // This may not be the only way things can go wrong, but it is the only way 4439 // we try to work around for the moment. 4440 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 4441 4442 if (Br && Br->isUnconditional()) { // Critical edge? 4443 BasicBlock::iterator I, E; 4444 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 4445 if (isSelector(I)) 4446 break; 4447 4448 if (I == E) 4449 // No catch info found - try to extract some from the successor. 4450 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 4451 } 4452 } 4453 4454 // Lower all of the non-terminator instructions. 4455 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4456 I != E; ++I) 4457 SDL.visit(*I); 4458 4459 // Ensure that all instructions which are used outside of their defining 4460 // blocks are available as virtual registers. Invoke is handled elsewhere. 4461 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4462 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 4463 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4464 if (VMI != FuncInfo.ValueMap.end()) 4465 UnorderedChains.push_back( 4466 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4467 } 4468 4469 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4470 // ensure constants are generated when needed. Remember the virtual registers 4471 // that need to be added to the Machine PHI nodes as input. We cannot just 4472 // directly add them, because expansion might result in multiple MBB's for one 4473 // BB. As such, the start of the BB might correspond to a different MBB than 4474 // the end. 4475 // 4476 TerminatorInst *TI = LLVMBB->getTerminator(); 4477 4478 // Emit constants only once even if used by multiple PHI nodes. 4479 std::map<Constant*, unsigned> ConstantsOut; 4480 4481 // Vector bool would be better, but vector<bool> is really slow. 4482 std::vector<unsigned char> SuccsHandled; 4483 if (TI->getNumSuccessors()) 4484 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4485 4486 // Check successor nodes' PHI nodes that expect a constant to be available 4487 // from this block. 4488 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4489 BasicBlock *SuccBB = TI->getSuccessor(succ); 4490 if (!isa<PHINode>(SuccBB->begin())) continue; 4491 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4492 4493 // If this terminator has multiple identical successors (common for 4494 // switches), only handle each succ once. 4495 unsigned SuccMBBNo = SuccMBB->getNumber(); 4496 if (SuccsHandled[SuccMBBNo]) continue; 4497 SuccsHandled[SuccMBBNo] = true; 4498 4499 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4500 PHINode *PN; 4501 4502 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4503 // nodes and Machine PHI nodes, but the incoming operands have not been 4504 // emitted yet. 4505 for (BasicBlock::iterator I = SuccBB->begin(); 4506 (PN = dyn_cast<PHINode>(I)); ++I) { 4507 // Ignore dead phi's. 4508 if (PN->use_empty()) continue; 4509 4510 unsigned Reg; 4511 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4512 4513 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4514 unsigned &RegOut = ConstantsOut[C]; 4515 if (RegOut == 0) { 4516 RegOut = FuncInfo.CreateRegForValue(C); 4517 UnorderedChains.push_back( 4518 SDL.CopyValueToVirtualRegister(C, RegOut)); 4519 } 4520 Reg = RegOut; 4521 } else { 4522 Reg = FuncInfo.ValueMap[PHIOp]; 4523 if (Reg == 0) { 4524 assert(isa<AllocaInst>(PHIOp) && 4525 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4526 "Didn't codegen value into a register!??"); 4527 Reg = FuncInfo.CreateRegForValue(PHIOp); 4528 UnorderedChains.push_back( 4529 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4530 } 4531 } 4532 4533 // Remember that this register needs to added to the machine PHI node as 4534 // the input for this MBB. 4535 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4536 unsigned NumRegisters = TLI.getNumRegisters(VT); 4537 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 4538 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4539 } 4540 } 4541 ConstantsOut.clear(); 4542 4543 // Turn all of the unordered chains into one factored node. 4544 if (!UnorderedChains.empty()) { 4545 SDOperand Root = SDL.getRoot(); 4546 if (Root.getOpcode() != ISD::EntryToken) { 4547 unsigned i = 0, e = UnorderedChains.size(); 4548 for (; i != e; ++i) { 4549 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4550 if (UnorderedChains[i].Val->getOperand(0) == Root) 4551 break; // Don't add the root if we already indirectly depend on it. 4552 } 4553 4554 if (i == e) 4555 UnorderedChains.push_back(Root); 4556 } 4557 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4558 &UnorderedChains[0], UnorderedChains.size())); 4559 } 4560 4561 // Lower the terminator after the copies are emitted. 4562 SDL.visit(*LLVMBB->getTerminator()); 4563 4564 // Copy over any CaseBlock records that may now exist due to SwitchInst 4565 // lowering, as well as any jump table information. 4566 SwitchCases.clear(); 4567 SwitchCases = SDL.SwitchCases; 4568 JTCases.clear(); 4569 JTCases = SDL.JTCases; 4570 BitTestCases.clear(); 4571 BitTestCases = SDL.BitTestCases; 4572 4573 // Make sure the root of the DAG is up-to-date. 4574 DAG.setRoot(SDL.getRoot()); 4575} 4576 4577void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4578 // Get alias analysis for load/store combining. 4579 AliasAnalysis &AA = getAnalysis<AliasAnalysis>(); 4580 4581 // Run the DAG combiner in pre-legalize mode. 4582 DAG.Combine(false, AA); 4583 4584 DOUT << "Lowered selection DAG:\n"; 4585 DEBUG(DAG.dump()); 4586 4587 // Second step, hack on the DAG until it only uses operations and types that 4588 // the target supports. 4589 DAG.Legalize(); 4590 4591 DOUT << "Legalized selection DAG:\n"; 4592 DEBUG(DAG.dump()); 4593 4594 // Run the DAG combiner in post-legalize mode. 4595 DAG.Combine(true, AA); 4596 4597 if (ViewISelDAGs) DAG.viewGraph(); 4598 4599 // Third, instruction select all of the operations to machine code, adding the 4600 // code to the MachineBasicBlock. 4601 InstructionSelectBasicBlock(DAG); 4602 4603 DOUT << "Selected machine code:\n"; 4604 DEBUG(BB->dump()); 4605} 4606 4607void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4608 FunctionLoweringInfo &FuncInfo) { 4609 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4610 { 4611 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4612 CurDAG = &DAG; 4613 4614 // First step, lower LLVM code to some DAG. This DAG may use operations and 4615 // types that are not supported by the target. 4616 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4617 4618 // Second step, emit the lowered DAG as machine code. 4619 CodeGenAndEmitDAG(DAG); 4620 } 4621 4622 DOUT << "Total amount of phi nodes to update: " 4623 << PHINodesToUpdate.size() << "\n"; 4624 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4625 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4626 << ", " << PHINodesToUpdate[i].second << ")\n";); 4627 4628 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4629 // PHI nodes in successors. 4630 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4631 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4632 MachineInstr *PHI = PHINodesToUpdate[i].first; 4633 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4634 "This is not a machine PHI node that we are updating!"); 4635 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4636 PHI->addMachineBasicBlockOperand(BB); 4637 } 4638 return; 4639 } 4640 4641 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4642 // Lower header first, if it wasn't already lowered 4643 if (!BitTestCases[i].Emitted) { 4644 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4645 CurDAG = &HSDAG; 4646 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo); 4647 // Set the current basic block to the mbb we wish to insert the code into 4648 BB = BitTestCases[i].Parent; 4649 HSDL.setCurrentBasicBlock(BB); 4650 // Emit the code 4651 HSDL.visitBitTestHeader(BitTestCases[i]); 4652 HSDAG.setRoot(HSDL.getRoot()); 4653 CodeGenAndEmitDAG(HSDAG); 4654 } 4655 4656 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4657 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4658 CurDAG = &BSDAG; 4659 SelectionDAGLowering BSDL(BSDAG, TLI, FuncInfo); 4660 // Set the current basic block to the mbb we wish to insert the code into 4661 BB = BitTestCases[i].Cases[j].ThisBB; 4662 BSDL.setCurrentBasicBlock(BB); 4663 // Emit the code 4664 if (j+1 != ej) 4665 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 4666 BitTestCases[i].Reg, 4667 BitTestCases[i].Cases[j]); 4668 else 4669 BSDL.visitBitTestCase(BitTestCases[i].Default, 4670 BitTestCases[i].Reg, 4671 BitTestCases[i].Cases[j]); 4672 4673 4674 BSDAG.setRoot(BSDL.getRoot()); 4675 CodeGenAndEmitDAG(BSDAG); 4676 } 4677 4678 // Update PHI Nodes 4679 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4680 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4681 MachineBasicBlock *PHIBB = PHI->getParent(); 4682 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4683 "This is not a machine PHI node that we are updating!"); 4684 // This is "default" BB. We have two jumps to it. From "header" BB and 4685 // from last "case" BB. 4686 if (PHIBB == BitTestCases[i].Default) { 4687 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4688 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent); 4689 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4690 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB); 4691 } 4692 // One of "cases" BB. 4693 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4694 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 4695 if (cBB->succ_end() != 4696 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 4697 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4698 PHI->addMachineBasicBlockOperand(cBB); 4699 } 4700 } 4701 } 4702 } 4703 4704 // If the JumpTable record is filled in, then we need to emit a jump table. 4705 // Updating the PHI nodes is tricky in this case, since we need to determine 4706 // whether the PHI is a successor of the range check MBB or the jump table MBB 4707 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 4708 // Lower header first, if it wasn't already lowered 4709 if (!JTCases[i].first.Emitted) { 4710 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4711 CurDAG = &HSDAG; 4712 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo); 4713 // Set the current basic block to the mbb we wish to insert the code into 4714 BB = JTCases[i].first.HeaderBB; 4715 HSDL.setCurrentBasicBlock(BB); 4716 // Emit the code 4717 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 4718 HSDAG.setRoot(HSDL.getRoot()); 4719 CodeGenAndEmitDAG(HSDAG); 4720 } 4721 4722 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4723 CurDAG = &JSDAG; 4724 SelectionDAGLowering JSDL(JSDAG, TLI, FuncInfo); 4725 // Set the current basic block to the mbb we wish to insert the code into 4726 BB = JTCases[i].second.MBB; 4727 JSDL.setCurrentBasicBlock(BB); 4728 // Emit the code 4729 JSDL.visitJumpTable(JTCases[i].second); 4730 JSDAG.setRoot(JSDL.getRoot()); 4731 CodeGenAndEmitDAG(JSDAG); 4732 4733 // Update PHI Nodes 4734 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4735 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4736 MachineBasicBlock *PHIBB = PHI->getParent(); 4737 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4738 "This is not a machine PHI node that we are updating!"); 4739 // "default" BB. We can go there only from header BB. 4740 if (PHIBB == JTCases[i].second.Default) { 4741 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4742 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB); 4743 } 4744 // JT BB. Just iterate over successors here 4745 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 4746 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4747 PHI->addMachineBasicBlockOperand(BB); 4748 } 4749 } 4750 } 4751 4752 // If the switch block involved a branch to one of the actual successors, we 4753 // need to update PHI nodes in that block. 4754 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4755 MachineInstr *PHI = PHINodesToUpdate[i].first; 4756 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4757 "This is not a machine PHI node that we are updating!"); 4758 if (BB->isSuccessor(PHI->getParent())) { 4759 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4760 PHI->addMachineBasicBlockOperand(BB); 4761 } 4762 } 4763 4764 // If we generated any switch lowering information, build and codegen any 4765 // additional DAGs necessary. 4766 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 4767 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4768 CurDAG = &SDAG; 4769 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 4770 4771 // Set the current basic block to the mbb we wish to insert the code into 4772 BB = SwitchCases[i].ThisBB; 4773 SDL.setCurrentBasicBlock(BB); 4774 4775 // Emit the code 4776 SDL.visitSwitchCase(SwitchCases[i]); 4777 SDAG.setRoot(SDL.getRoot()); 4778 CodeGenAndEmitDAG(SDAG); 4779 4780 // Handle any PHI nodes in successors of this chunk, as if we were coming 4781 // from the original BB before switch expansion. Note that PHI nodes can 4782 // occur multiple times in PHINodesToUpdate. We have to be very careful to 4783 // handle them the right number of times. 4784 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 4785 for (MachineBasicBlock::iterator Phi = BB->begin(); 4786 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 4787 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 4788 for (unsigned pn = 0; ; ++pn) { 4789 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 4790 if (PHINodesToUpdate[pn].first == Phi) { 4791 Phi->addRegOperand(PHINodesToUpdate[pn].second, false); 4792 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB); 4793 break; 4794 } 4795 } 4796 } 4797 4798 // Don't process RHS if same block as LHS. 4799 if (BB == SwitchCases[i].FalseBB) 4800 SwitchCases[i].FalseBB = 0; 4801 4802 // If we haven't handled the RHS, do so now. Otherwise, we're done. 4803 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 4804 SwitchCases[i].FalseBB = 0; 4805 } 4806 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 4807 } 4808} 4809 4810 4811//===----------------------------------------------------------------------===// 4812/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 4813/// target node in the graph. 4814void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 4815 if (ViewSchedDAGs) DAG.viewGraph(); 4816 4817 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 4818 4819 if (!Ctor) { 4820 Ctor = ISHeuristic; 4821 RegisterScheduler::setDefault(Ctor); 4822 } 4823 4824 ScheduleDAG *SL = Ctor(this, &DAG, BB); 4825 BB = SL->Run(); 4826 delete SL; 4827} 4828 4829 4830HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 4831 return new HazardRecognizer(); 4832} 4833 4834//===----------------------------------------------------------------------===// 4835// Helper functions used by the generated instruction selector. 4836//===----------------------------------------------------------------------===// 4837// Calls to these methods are generated by tblgen. 4838 4839/// CheckAndMask - The isel is trying to match something like (and X, 255). If 4840/// the dag combiner simplified the 255, we still want to match. RHS is the 4841/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 4842/// specified in the .td file (e.g. 255). 4843bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 4844 int64_t DesiredMaskS) const { 4845 uint64_t ActualMask = RHS->getValue(); 4846 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4847 4848 // If the actual mask exactly matches, success! 4849 if (ActualMask == DesiredMask) 4850 return true; 4851 4852 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4853 if (ActualMask & ~DesiredMask) 4854 return false; 4855 4856 // Otherwise, the DAG Combiner may have proven that the value coming in is 4857 // either already zero or is not demanded. Check for known zero input bits. 4858 uint64_t NeededMask = DesiredMask & ~ActualMask; 4859 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 4860 return true; 4861 4862 // TODO: check to see if missing bits are just not demanded. 4863 4864 // Otherwise, this pattern doesn't match. 4865 return false; 4866} 4867 4868/// CheckOrMask - The isel is trying to match something like (or X, 255). If 4869/// the dag combiner simplified the 255, we still want to match. RHS is the 4870/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 4871/// specified in the .td file (e.g. 255). 4872bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 4873 int64_t DesiredMaskS) const { 4874 uint64_t ActualMask = RHS->getValue(); 4875 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4876 4877 // If the actual mask exactly matches, success! 4878 if (ActualMask == DesiredMask) 4879 return true; 4880 4881 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4882 if (ActualMask & ~DesiredMask) 4883 return false; 4884 4885 // Otherwise, the DAG Combiner may have proven that the value coming in is 4886 // either already zero or is not demanded. Check for known zero input bits. 4887 uint64_t NeededMask = DesiredMask & ~ActualMask; 4888 4889 uint64_t KnownZero, KnownOne; 4890 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 4891 4892 // If all the missing bits in the or are already known to be set, match! 4893 if ((NeededMask & KnownOne) == NeededMask) 4894 return true; 4895 4896 // TODO: check to see if missing bits are just not demanded. 4897 4898 // Otherwise, this pattern doesn't match. 4899 return false; 4900} 4901 4902 4903/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 4904/// by tblgen. Others should not call it. 4905void SelectionDAGISel:: 4906SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 4907 std::vector<SDOperand> InOps; 4908 std::swap(InOps, Ops); 4909 4910 Ops.push_back(InOps[0]); // input chain. 4911 Ops.push_back(InOps[1]); // input asm string. 4912 4913 unsigned i = 2, e = InOps.size(); 4914 if (InOps[e-1].getValueType() == MVT::Flag) 4915 --e; // Don't process a flag operand if it is here. 4916 4917 while (i != e) { 4918 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 4919 if ((Flags & 7) != 4 /*MEM*/) { 4920 // Just skip over this operand, copying the operands verbatim. 4921 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 4922 i += (Flags >> 3) + 1; 4923 } else { 4924 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 4925 // Otherwise, this is a memory operand. Ask the target to select it. 4926 std::vector<SDOperand> SelOps; 4927 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 4928 cerr << "Could not match memory address. Inline asm failure!\n"; 4929 exit(1); 4930 } 4931 4932 // Add this to the output node. 4933 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 4934 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 4935 IntPtrTy)); 4936 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 4937 i += 2; 4938 } 4939 } 4940 4941 // Add the flag input back if present. 4942 if (e != InOps.size()) 4943 Ops.push_back(InOps.back()); 4944} 4945 4946char SelectionDAGISel::ID = 0; 4947