SelectionDAGISel.cpp revision 49e2c678a41530c1a2af5d78b9c3bf2d8e436b8f
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/CodeGen/FastISel.h" 29#include "llvm/CodeGen/GCStrategy.h" 30#include "llvm/CodeGen/GCMetadata.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetIntrinsicInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/Compiler.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/Timer.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/ADT/Statistic.h" 50#include <algorithm> 51using namespace llvm; 52 53STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 54STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 55 56static cl::opt<bool> 57EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 58 cl::desc("Enable verbose messages in the \"fast\" " 59 "instruction selector")); 60static cl::opt<bool> 61EnableFastISelAbort("fast-isel-abort", cl::Hidden, 62 cl::desc("Enable abort calls when \"fast\" instruction fails")); 63 64#ifndef NDEBUG 65static cl::opt<bool> 66ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 67 cl::desc("Pop up a window to show dags before the first " 68 "dag combine pass")); 69static cl::opt<bool> 70ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 71 cl::desc("Pop up a window to show dags before legalize types")); 72static cl::opt<bool> 73ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 74 cl::desc("Pop up a window to show dags before legalize")); 75static cl::opt<bool> 76ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the second " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before the post legalize types" 82 " dag combine pass")); 83static cl::opt<bool> 84ViewISelDAGs("view-isel-dags", cl::Hidden, 85 cl::desc("Pop up a window to show isel dags as they are selected")); 86static cl::opt<bool> 87ViewSchedDAGs("view-sched-dags", cl::Hidden, 88 cl::desc("Pop up a window to show sched dags as they are processed")); 89static cl::opt<bool> 90ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 91 cl::desc("Pop up a window to show SUnit dags after they are processed")); 92#else 93static const bool ViewDAGCombine1 = false, 94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 95 ViewDAGCombine2 = false, 96 ViewDAGCombineLT = false, 97 ViewISelDAGs = false, ViewSchedDAGs = false, 98 ViewSUnitDAGs = false; 99#endif 100 101//===---------------------------------------------------------------------===// 102/// 103/// RegisterScheduler class - Track the registration of instruction schedulers. 104/// 105//===---------------------------------------------------------------------===// 106MachinePassRegistry RegisterScheduler::Registry; 107 108//===---------------------------------------------------------------------===// 109/// 110/// ISHeuristic command line option for instruction schedulers. 111/// 112//===---------------------------------------------------------------------===// 113static cl::opt<RegisterScheduler::FunctionPassCtor, false, 114 RegisterPassParser<RegisterScheduler> > 115ISHeuristic("pre-RA-sched", 116 cl::init(&createDefaultScheduler), 117 cl::desc("Instruction schedulers available (before register" 118 " allocation):")); 119 120static RegisterScheduler 121defaultListDAGScheduler("default", "Best scheduler for the target", 122 createDefaultScheduler); 123 124namespace llvm { 125 //===--------------------------------------------------------------------===// 126 /// createDefaultScheduler - This creates an instruction scheduler appropriate 127 /// for the target. 128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 129 CodeGenOpt::Level OptLevel) { 130 const TargetLowering &TLI = IS->getTargetLowering(); 131 132 if (OptLevel == CodeGenOpt::None) 133 return createFastDAGScheduler(IS, OptLevel); 134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 135 return createTDListDAGScheduler(IS, OptLevel); 136 assert(TLI.getSchedulingPreference() == 137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 138 return createBURRListDAGScheduler(IS, OptLevel); 139 } 140} 141 142// EmitInstrWithCustomInserter - This method should be implemented by targets 143// that mark instructions with the 'usesCustomInserter' flag. These 144// instructions are special in various ways, which require special support to 145// insert. The specified MachineInstr is created but not inserted into any 146// basic blocks, and this method is called to expand it into a sequence of 147// instructions, potentially also creating new basic blocks and control flow. 148// When new basic blocks are inserted and the edges from MBB to its successors 149// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 150// DenseMap. 151MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 152 MachineBasicBlock *MBB, 153 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 154#ifndef NDEBUG 155 dbgs() << "If a target marks an instruction with " 156 "'usesCustomInserter', it must implement " 157 "TargetLowering::EmitInstrWithCustomInserter!"; 158#endif 159 llvm_unreachable(0); 160 return 0; 161} 162 163//===----------------------------------------------------------------------===// 164// SelectionDAGISel code 165//===----------------------------------------------------------------------===// 166 167SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 169 FuncInfo(new FunctionLoweringInfo(TLI)), 170 CurDAG(new SelectionDAG(tm, *FuncInfo)), 171 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 172 GFI(), 173 OptLevel(OL), 174 DAGSize(0) 175{} 176 177SelectionDAGISel::~SelectionDAGISel() { 178 delete SDB; 179 delete CurDAG; 180 delete FuncInfo; 181} 182 183void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 184 AU.addRequired<AliasAnalysis>(); 185 AU.addPreserved<AliasAnalysis>(); 186 AU.addRequired<GCModuleInfo>(); 187 AU.addPreserved<GCModuleInfo>(); 188 MachineFunctionPass::getAnalysisUsage(AU); 189} 190 191bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 192 // Do some sanity-checking on the command-line options. 193 assert((!EnableFastISelVerbose || EnableFastISel) && 194 "-fast-isel-verbose requires -fast-isel"); 195 assert((!EnableFastISelAbort || EnableFastISel) && 196 "-fast-isel-abort requires -fast-isel"); 197 198 const Function &Fn = *mf.getFunction(); 199 const TargetInstrInfo &TII = *TM.getInstrInfo(); 200 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 201 202 MF = &mf; 203 RegInfo = &MF->getRegInfo(); 204 AA = &getAnalysis<AliasAnalysis>(); 205 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 206 207 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 208 209 CurDAG->init(*MF); 210 FuncInfo->set(Fn, *MF, EnableFastISel); 211 SDB->init(GFI, *AA); 212 213 SelectAllBasicBlocks(Fn); 214 215 // Release function-specific state. SDB and CurDAG are already cleared 216 // at this point. 217 FuncInfo->clear(); 218 219 // If the first basic block in the function has live ins that need to be 220 // copied into vregs, emit the copies into the top of the block before 221 // emitting the code for the block. 222 RegInfo->EmitLiveInCopies(MF->begin(), TRI, TII); 223 224 return true; 225} 226 227/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 228/// attached with this instruction. 229static void SetDebugLoc(const Instruction *I, SelectionDAGBuilder *SDB, 230 FastISel *FastIS, MachineFunction *MF) { 231 DebugLoc DL = I->getDebugLoc(); 232 if (DL.isUnknown()) return; 233 234 SDB->setCurDebugLoc(DL); 235 236 if (FastIS) 237 FastIS->setCurDebugLoc(DL); 238 239 // If the function doesn't have a default debug location yet, set 240 // it. This is a total hack. 241 if (MF->getDefaultDebugLoc().isUnknown()) 242 MF->setDefaultDebugLoc(DL); 243} 244 245/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 246static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 247 SDB->setCurDebugLoc(DebugLoc()); 248 if (FastIS) 249 FastIS->setCurDebugLoc(DebugLoc()); 250} 251 252void SelectionDAGISel::SelectBasicBlock(const BasicBlock *LLVMBB, 253 BasicBlock::const_iterator Begin, 254 BasicBlock::const_iterator End, 255 bool &HadTailCall) { 256 // Lower all of the non-terminator instructions. If a call is emitted 257 // as a tail call, cease emitting nodes for this block. Terminators 258 // are handled below. 259 for (BasicBlock::const_iterator I = Begin; 260 I != End && !SDB->HasTailCall && !isa<TerminatorInst>(I); 261 ++I) { 262 SetDebugLoc(I, SDB, 0, MF); 263 SDB->visit(*I); 264 ResetDebugLoc(SDB, 0); 265 } 266 267 if (!SDB->HasTailCall) { 268 // Ensure that all instructions which are used outside of their defining 269 // blocks are available as virtual registers. Invoke is handled elsewhere. 270 for (BasicBlock::const_iterator I = Begin; I != End; ++I) 271 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 272 SDB->CopyToExportRegsIfNeeded(I); 273 274 // Handle PHI nodes in successor blocks. 275 if (End == LLVMBB->end()) { 276 HandlePHINodesInSuccessorBlocks(LLVMBB); 277 278 // Lower the terminator after the copies are emitted. 279 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF); 280 SDB->visit(*LLVMBB->getTerminator()); 281 ResetDebugLoc(SDB, 0); 282 } 283 } 284 285 // Make sure the root of the DAG is up-to-date. 286 CurDAG->setRoot(SDB->getControlRoot()); 287 288 // Final step, emit the lowered DAG as machine code. 289 CodeGenAndEmitDAG(); 290 HadTailCall = SDB->HasTailCall; 291 SDB->clear(); 292} 293 294namespace { 295/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 296/// nodes from the worklist. 297class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 298 SmallVector<SDNode*, 128> &Worklist; 299 SmallPtrSet<SDNode*, 128> &InWorklist; 300public: 301 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 302 SmallPtrSet<SDNode*, 128> &inwl) 303 : Worklist(wl), InWorklist(inwl) {} 304 305 void RemoveFromWorklist(SDNode *N) { 306 if (!InWorklist.erase(N)) return; 307 308 SmallVector<SDNode*, 128>::iterator I = 309 std::find(Worklist.begin(), Worklist.end(), N); 310 assert(I != Worklist.end() && "Not in worklist"); 311 312 *I = Worklist.back(); 313 Worklist.pop_back(); 314 } 315 316 virtual void NodeDeleted(SDNode *N, SDNode *E) { 317 RemoveFromWorklist(N); 318 } 319 320 virtual void NodeUpdated(SDNode *N) { 321 // Ignore updates. 322 } 323}; 324} 325 326/// TrivialTruncElim - Eliminate some trivial nops that can result from 327/// ShrinkDemandedOps: (trunc (ext n)) -> n. 328static bool TrivialTruncElim(SDValue Op, 329 TargetLowering::TargetLoweringOpt &TLO) { 330 SDValue N0 = Op.getOperand(0); 331 EVT VT = Op.getValueType(); 332 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 333 N0.getOpcode() == ISD::SIGN_EXTEND || 334 N0.getOpcode() == ISD::ANY_EXTEND) && 335 N0.getOperand(0).getValueType() == VT) { 336 return TLO.CombineTo(Op, N0.getOperand(0)); 337 } 338 return false; 339} 340 341/// ShrinkDemandedOps - A late transformation pass that shrink expressions 342/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 343/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 344void SelectionDAGISel::ShrinkDemandedOps() { 345 SmallVector<SDNode*, 128> Worklist; 346 SmallPtrSet<SDNode*, 128> InWorklist; 347 348 // Add all the dag nodes to the worklist. 349 Worklist.reserve(CurDAG->allnodes_size()); 350 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 351 E = CurDAG->allnodes_end(); I != E; ++I) { 352 Worklist.push_back(I); 353 InWorklist.insert(I); 354 } 355 356 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true); 357 while (!Worklist.empty()) { 358 SDNode *N = Worklist.pop_back_val(); 359 InWorklist.erase(N); 360 361 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 362 // Deleting this node may make its operands dead, add them to the worklist 363 // if they aren't already there. 364 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 365 if (InWorklist.insert(N->getOperand(i).getNode())) 366 Worklist.push_back(N->getOperand(i).getNode()); 367 368 CurDAG->DeleteNode(N); 369 continue; 370 } 371 372 // Run ShrinkDemandedOp on scalar binary operations. 373 if (N->getNumValues() != 1 || 374 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 375 continue; 376 377 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 378 APInt Demanded = APInt::getAllOnesValue(BitWidth); 379 APInt KnownZero, KnownOne; 380 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 381 KnownZero, KnownOne, TLO) && 382 (N->getOpcode() != ISD::TRUNCATE || 383 !TrivialTruncElim(SDValue(N, 0), TLO))) 384 continue; 385 386 // Revisit the node. 387 assert(!InWorklist.count(N) && "Already in worklist"); 388 Worklist.push_back(N); 389 InWorklist.insert(N); 390 391 // Replace the old value with the new one. 392 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 393 TLO.Old.getNode()->dump(CurDAG); 394 errs() << "\nWith: "; 395 TLO.New.getNode()->dump(CurDAG); 396 errs() << '\n'); 397 398 if (InWorklist.insert(TLO.New.getNode())) 399 Worklist.push_back(TLO.New.getNode()); 400 401 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 402 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 403 404 if (!TLO.Old.getNode()->use_empty()) continue; 405 406 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 407 i != e; ++i) { 408 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 409 if (OpNode->hasOneUse()) { 410 // Add OpNode to the end of the list to revisit. 411 DeadNodes.RemoveFromWorklist(OpNode); 412 Worklist.push_back(OpNode); 413 InWorklist.insert(OpNode); 414 } 415 } 416 417 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 418 CurDAG->DeleteNode(TLO.Old.getNode()); 419 } 420} 421 422void SelectionDAGISel::ComputeLiveOutVRegInfo() { 423 SmallPtrSet<SDNode*, 128> VisitedNodes; 424 SmallVector<SDNode*, 128> Worklist; 425 426 Worklist.push_back(CurDAG->getRoot().getNode()); 427 428 APInt Mask; 429 APInt KnownZero; 430 APInt KnownOne; 431 432 do { 433 SDNode *N = Worklist.pop_back_val(); 434 435 // If we've already seen this node, ignore it. 436 if (!VisitedNodes.insert(N)) 437 continue; 438 439 // Otherwise, add all chain operands to the worklist. 440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 441 if (N->getOperand(i).getValueType() == MVT::Other) 442 Worklist.push_back(N->getOperand(i).getNode()); 443 444 // If this is a CopyToReg with a vreg dest, process it. 445 if (N->getOpcode() != ISD::CopyToReg) 446 continue; 447 448 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 449 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 450 continue; 451 452 // Ignore non-scalar or non-integer values. 453 SDValue Src = N->getOperand(2); 454 EVT SrcVT = Src.getValueType(); 455 if (!SrcVT.isInteger() || SrcVT.isVector()) 456 continue; 457 458 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 459 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 460 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 461 462 // Only install this information if it tells us something. 463 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 464 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 465 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 466 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 467 FunctionLoweringInfo::LiveOutInfo &LOI = 468 FuncInfo->LiveOutRegInfo[DestReg]; 469 LOI.NumSignBits = NumSignBits; 470 LOI.KnownOne = KnownOne; 471 LOI.KnownZero = KnownZero; 472 } 473 } while (!Worklist.empty()); 474} 475 476void SelectionDAGISel::CodeGenAndEmitDAG() { 477 std::string GroupName; 478 if (TimePassesIsEnabled) 479 GroupName = "Instruction Selection and Scheduling"; 480 std::string BlockName; 481 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 482 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 483 ViewSUnitDAGs) 484 BlockName = MF->getFunction()->getNameStr() + ":" + 485 BB->getBasicBlock()->getNameStr(); 486 487 DEBUG(dbgs() << "Initial selection DAG:\n"); 488 DEBUG(CurDAG->dump()); 489 490 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 491 492 // Run the DAG combiner in pre-legalize mode. 493 if (TimePassesIsEnabled) { 494 NamedRegionTimer T("DAG Combining 1", GroupName); 495 CurDAG->Combine(Unrestricted, *AA, OptLevel); 496 } else { 497 CurDAG->Combine(Unrestricted, *AA, OptLevel); 498 } 499 500 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 501 DEBUG(CurDAG->dump()); 502 503 // Second step, hack on the DAG until it only uses operations and types that 504 // the target supports. 505 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 506 BlockName); 507 508 bool Changed; 509 if (TimePassesIsEnabled) { 510 NamedRegionTimer T("Type Legalization", GroupName); 511 Changed = CurDAG->LegalizeTypes(); 512 } else { 513 Changed = CurDAG->LegalizeTypes(); 514 } 515 516 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 517 DEBUG(CurDAG->dump()); 518 519 if (Changed) { 520 if (ViewDAGCombineLT) 521 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 522 523 // Run the DAG combiner in post-type-legalize mode. 524 if (TimePassesIsEnabled) { 525 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 526 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 527 } else { 528 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 529 } 530 531 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 532 DEBUG(CurDAG->dump()); 533 } 534 535 if (TimePassesIsEnabled) { 536 NamedRegionTimer T("Vector Legalization", GroupName); 537 Changed = CurDAG->LegalizeVectors(); 538 } else { 539 Changed = CurDAG->LegalizeVectors(); 540 } 541 542 if (Changed) { 543 if (TimePassesIsEnabled) { 544 NamedRegionTimer T("Type Legalization 2", GroupName); 545 CurDAG->LegalizeTypes(); 546 } else { 547 CurDAG->LegalizeTypes(); 548 } 549 550 if (ViewDAGCombineLT) 551 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 552 553 // Run the DAG combiner in post-type-legalize mode. 554 if (TimePassesIsEnabled) { 555 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 556 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 557 } else { 558 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 559 } 560 561 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 562 DEBUG(CurDAG->dump()); 563 } 564 565 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 566 567 if (TimePassesIsEnabled) { 568 NamedRegionTimer T("DAG Legalization", GroupName); 569 CurDAG->Legalize(OptLevel); 570 } else { 571 CurDAG->Legalize(OptLevel); 572 } 573 574 DEBUG(dbgs() << "Legalized selection DAG:\n"); 575 DEBUG(CurDAG->dump()); 576 577 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 578 579 // Run the DAG combiner in post-legalize mode. 580 if (TimePassesIsEnabled) { 581 NamedRegionTimer T("DAG Combining 2", GroupName); 582 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 583 } else { 584 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 585 } 586 587 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 588 DEBUG(CurDAG->dump()); 589 590 if (OptLevel != CodeGenOpt::None) { 591 ShrinkDemandedOps(); 592 ComputeLiveOutVRegInfo(); 593 } 594 595 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 596 597 // Third, instruction select all of the operations to machine code, adding the 598 // code to the MachineBasicBlock. 599 if (TimePassesIsEnabled) { 600 NamedRegionTimer T("Instruction Selection", GroupName); 601 DoInstructionSelection(); 602 } else { 603 DoInstructionSelection(); 604 } 605 606 DEBUG(dbgs() << "Selected selection DAG:\n"); 607 DEBUG(CurDAG->dump()); 608 609 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 610 611 // Schedule machine code. 612 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 613 if (TimePassesIsEnabled) { 614 NamedRegionTimer T("Instruction Scheduling", GroupName); 615 Scheduler->Run(CurDAG, BB, BB->end()); 616 } else { 617 Scheduler->Run(CurDAG, BB, BB->end()); 618 } 619 620 if (ViewSUnitDAGs) Scheduler->viewGraph(); 621 622 // Emit machine code to BB. This can change 'BB' to the last block being 623 // inserted into. 624 if (TimePassesIsEnabled) { 625 NamedRegionTimer T("Instruction Creation", GroupName); 626 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 627 } else { 628 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 629 } 630 631 // Free the scheduler state. 632 if (TimePassesIsEnabled) { 633 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 634 delete Scheduler; 635 } else { 636 delete Scheduler; 637 } 638 639 DEBUG(dbgs() << "Selected machine code:\n"); 640 DEBUG(BB->dump()); 641} 642 643void SelectionDAGISel::DoInstructionSelection() { 644 DEBUG(errs() << "===== Instruction selection begins:\n"); 645 646 PreprocessISelDAG(); 647 648 // Select target instructions for the DAG. 649 { 650 // Number all nodes with a topological order and set DAGSize. 651 DAGSize = CurDAG->AssignTopologicalOrder(); 652 653 // Create a dummy node (which is not added to allnodes), that adds 654 // a reference to the root node, preventing it from being deleted, 655 // and tracking any changes of the root. 656 HandleSDNode Dummy(CurDAG->getRoot()); 657 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 658 ++ISelPosition; 659 660 // The AllNodes list is now topological-sorted. Visit the 661 // nodes by starting at the end of the list (the root of the 662 // graph) and preceding back toward the beginning (the entry 663 // node). 664 while (ISelPosition != CurDAG->allnodes_begin()) { 665 SDNode *Node = --ISelPosition; 666 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 667 // but there are currently some corner cases that it misses. Also, this 668 // makes it theoretically possible to disable the DAGCombiner. 669 if (Node->use_empty()) 670 continue; 671 672 SDNode *ResNode = Select(Node); 673 674 // FIXME: This is pretty gross. 'Select' should be changed to not return 675 // anything at all and this code should be nuked with a tactical strike. 676 677 // If node should not be replaced, continue with the next one. 678 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 679 continue; 680 // Replace node. 681 if (ResNode) 682 ReplaceUses(Node, ResNode); 683 684 // If after the replacement this node is not used any more, 685 // remove this dead node. 686 if (Node->use_empty()) { // Don't delete EntryToken, etc. 687 ISelUpdater ISU(ISelPosition); 688 CurDAG->RemoveDeadNode(Node, &ISU); 689 } 690 } 691 692 CurDAG->setRoot(Dummy.getValue()); 693 } 694 DEBUG(errs() << "===== Instruction selection ends:\n"); 695 696 PostprocessISelDAG(); 697} 698 699/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 700/// do other setup for EH landing-pad blocks. 701void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) { 702 // Add a label to mark the beginning of the landing pad. Deletion of the 703 // landing pad can thus be detected via the MachineModuleInfo. 704 MCSymbol *Label = MF->getMMI().addLandingPad(BB); 705 706 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 707 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 708 709 // Mark exception register as live in. 710 unsigned Reg = TLI.getExceptionAddressRegister(); 711 if (Reg) BB->addLiveIn(Reg); 712 713 // Mark exception selector register as live in. 714 Reg = TLI.getExceptionSelectorRegister(); 715 if (Reg) BB->addLiveIn(Reg); 716 717 // FIXME: Hack around an exception handling flaw (PR1508): the personality 718 // function and list of typeids logically belong to the invoke (or, if you 719 // like, the basic block containing the invoke), and need to be associated 720 // with it in the dwarf exception handling tables. Currently however the 721 // information is provided by an intrinsic (eh.selector) that can be moved 722 // to unexpected places by the optimizers: if the unwind edge is critical, 723 // then breaking it can result in the intrinsics being in the successor of 724 // the landing pad, not the landing pad itself. This results 725 // in exceptions not being caught because no typeids are associated with 726 // the invoke. This may not be the only way things can go wrong, but it 727 // is the only way we try to work around for the moment. 728 const BasicBlock *LLVMBB = BB->getBasicBlock(); 729 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 730 731 if (Br && Br->isUnconditional()) { // Critical edge? 732 BasicBlock::const_iterator I, E; 733 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 734 if (isa<EHSelectorInst>(I)) 735 break; 736 737 if (I == E) 738 // No catch info found - try to extract some from the successor. 739 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 740 } 741} 742 743void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 744 // Initialize the Fast-ISel state, if needed. 745 FastISel *FastIS = 0; 746 if (EnableFastISel) 747 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 748 FuncInfo->StaticAllocaMap 749#ifndef NDEBUG 750 , FuncInfo->CatchInfoLost 751#endif 752 ); 753 754 // Iterate over all basic blocks in the function. 755 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 756 const BasicBlock *LLVMBB = &*I; 757 BB = FuncInfo->MBBMap[LLVMBB]; 758 759 BasicBlock::const_iterator const Begin = LLVMBB->begin(); 760 BasicBlock::const_iterator const End = LLVMBB->end(); 761 BasicBlock::const_iterator BI = Begin; 762 763 // Lower any arguments needed in this block if this is the entry block. 764 bool SuppressFastISel = false; 765 if (LLVMBB == &Fn.getEntryBlock()) { 766 LowerArguments(LLVMBB); 767 768 // If any of the arguments has the byval attribute, forgo 769 // fast-isel in the entry block. 770 if (FastIS) { 771 unsigned j = 1; 772 for (Function::const_arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 773 I != E; ++I, ++j) 774 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 775 if (EnableFastISelVerbose || EnableFastISelAbort) 776 dbgs() << "FastISel skips entry block due to byval argument\n"; 777 SuppressFastISel = true; 778 break; 779 } 780 } 781 } 782 783 // Setup an EH landing-pad block. 784 if (BB->isLandingPad()) 785 PrepareEHLandingPad(BB); 786 787 // Before doing SelectionDAG ISel, see if FastISel has been requested. 788 if (FastIS && !SuppressFastISel) { 789 // Emit code for any incoming arguments. This must happen before 790 // beginning FastISel on the entry block. 791 if (LLVMBB == &Fn.getEntryBlock()) { 792 CurDAG->setRoot(SDB->getControlRoot()); 793 CodeGenAndEmitDAG(); 794 SDB->clear(); 795 } 796 FastIS->startNewBlock(BB); 797 // Do FastISel on as many instructions as possible. 798 for (; BI != End; ++BI) { 799 // Just before the terminator instruction, insert instructions to 800 // feed PHI nodes in successor blocks. 801 if (isa<TerminatorInst>(BI)) 802 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 803 ++NumFastIselFailures; 804 ResetDebugLoc(SDB, FastIS); 805 if (EnableFastISelVerbose || EnableFastISelAbort) { 806 dbgs() << "FastISel miss: "; 807 BI->dump(); 808 } 809 assert(!EnableFastISelAbort && 810 "FastISel didn't handle a PHI in a successor"); 811 break; 812 } 813 814 SetDebugLoc(BI, SDB, FastIS, MF); 815 816 // Try to select the instruction with FastISel. 817 if (FastIS->SelectInstruction(BI)) { 818 ResetDebugLoc(SDB, FastIS); 819 continue; 820 } 821 822 // Clear out the debug location so that it doesn't carry over to 823 // unrelated instructions. 824 ResetDebugLoc(SDB, FastIS); 825 826 // Then handle certain instructions as single-LLVM-Instruction blocks. 827 if (isa<CallInst>(BI)) { 828 ++NumFastIselFailures; 829 if (EnableFastISelVerbose || EnableFastISelAbort) { 830 dbgs() << "FastISel missed call: "; 831 BI->dump(); 832 } 833 834 if (!BI->getType()->isVoidTy() && !BI->use_empty()) { 835 unsigned &R = FuncInfo->ValueMap[BI]; 836 if (!R) 837 R = FuncInfo->CreateRegForValue(BI); 838 } 839 840 bool HadTailCall = false; 841 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 842 843 // If the call was emitted as a tail call, we're done with the block. 844 if (HadTailCall) { 845 BI = End; 846 break; 847 } 848 849 // If the instruction was codegen'd with multiple blocks, 850 // inform the FastISel object where to resume inserting. 851 FastIS->setCurrentBlock(BB); 852 continue; 853 } 854 855 // Otherwise, give up on FastISel for the rest of the block. 856 // For now, be a little lenient about non-branch terminators. 857 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 858 ++NumFastIselFailures; 859 if (EnableFastISelVerbose || EnableFastISelAbort) { 860 dbgs() << "FastISel miss: "; 861 BI->dump(); 862 } 863 if (EnableFastISelAbort) 864 // The "fast" selector couldn't handle something and bailed. 865 // For the purpose of debugging, just abort. 866 llvm_unreachable("FastISel didn't select the entire block"); 867 } 868 break; 869 } 870 } 871 872 // Run SelectionDAG instruction selection on the remainder of the block 873 // not handled by FastISel. If FastISel is not run, this is the entire 874 // block. 875 if (BI != End) { 876 bool HadTailCall; 877 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 878 } 879 880 FinishBasicBlock(); 881 } 882 883 delete FastIS; 884} 885 886void 887SelectionDAGISel::FinishBasicBlock() { 888 889 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 890 DEBUG(BB->dump()); 891 892 DEBUG(dbgs() << "Total amount of phi nodes to update: " 893 << SDB->PHINodesToUpdate.size() << "\n"); 894 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 895 dbgs() << "Node " << i << " : (" 896 << SDB->PHINodesToUpdate[i].first 897 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 898 899 // Next, now that we know what the last MBB the LLVM BB expanded is, update 900 // PHI nodes in successors. 901 if (SDB->SwitchCases.empty() && 902 SDB->JTCases.empty() && 903 SDB->BitTestCases.empty()) { 904 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 905 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 906 assert(PHI->isPHI() && 907 "This is not a machine PHI node that we are updating!"); 908 if (!BB->isSuccessor(PHI->getParent())) 909 continue; 910 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 911 false)); 912 PHI->addOperand(MachineOperand::CreateMBB(BB)); 913 } 914 SDB->PHINodesToUpdate.clear(); 915 return; 916 } 917 918 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 919 // Lower header first, if it wasn't already lowered 920 if (!SDB->BitTestCases[i].Emitted) { 921 // Set the current basic block to the mbb we wish to insert the code into 922 BB = SDB->BitTestCases[i].Parent; 923 // Emit the code 924 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB); 925 CurDAG->setRoot(SDB->getRoot()); 926 CodeGenAndEmitDAG(); 927 SDB->clear(); 928 } 929 930 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 931 // Set the current basic block to the mbb we wish to insert the code into 932 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 933 // Emit the code 934 if (j+1 != ej) 935 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 936 SDB->BitTestCases[i].Reg, 937 SDB->BitTestCases[i].Cases[j], 938 BB); 939 else 940 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 941 SDB->BitTestCases[i].Reg, 942 SDB->BitTestCases[i].Cases[j], 943 BB); 944 945 946 CurDAG->setRoot(SDB->getRoot()); 947 CodeGenAndEmitDAG(); 948 SDB->clear(); 949 } 950 951 // Update PHI Nodes 952 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 953 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 954 MachineBasicBlock *PHIBB = PHI->getParent(); 955 assert(PHI->isPHI() && 956 "This is not a machine PHI node that we are updating!"); 957 // This is "default" BB. We have two jumps to it. From "header" BB and 958 // from last "case" BB. 959 if (PHIBB == SDB->BitTestCases[i].Default) { 960 PHI->addOperand(MachineOperand:: 961 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 962 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 963 PHI->addOperand(MachineOperand:: 964 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 965 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 966 back().ThisBB)); 967 } 968 // One of "cases" BB. 969 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 970 j != ej; ++j) { 971 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 972 if (cBB->isSuccessor(PHIBB)) { 973 PHI->addOperand(MachineOperand:: 974 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 975 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 976 } 977 } 978 } 979 } 980 SDB->BitTestCases.clear(); 981 982 // If the JumpTable record is filled in, then we need to emit a jump table. 983 // Updating the PHI nodes is tricky in this case, since we need to determine 984 // whether the PHI is a successor of the range check MBB or the jump table MBB 985 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 986 // Lower header first, if it wasn't already lowered 987 if (!SDB->JTCases[i].first.Emitted) { 988 // Set the current basic block to the mbb we wish to insert the code into 989 BB = SDB->JTCases[i].first.HeaderBB; 990 // Emit the code 991 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 992 BB); 993 CurDAG->setRoot(SDB->getRoot()); 994 CodeGenAndEmitDAG(); 995 SDB->clear(); 996 } 997 998 // Set the current basic block to the mbb we wish to insert the code into 999 BB = SDB->JTCases[i].second.MBB; 1000 // Emit the code 1001 SDB->visitJumpTable(SDB->JTCases[i].second); 1002 CurDAG->setRoot(SDB->getRoot()); 1003 CodeGenAndEmitDAG(); 1004 SDB->clear(); 1005 1006 // Update PHI Nodes 1007 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1008 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1009 MachineBasicBlock *PHIBB = PHI->getParent(); 1010 assert(PHI->isPHI() && 1011 "This is not a machine PHI node that we are updating!"); 1012 // "default" BB. We can go there only from header BB. 1013 if (PHIBB == SDB->JTCases[i].second.Default) { 1014 PHI->addOperand 1015 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1016 PHI->addOperand 1017 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1018 } 1019 // JT BB. Just iterate over successors here 1020 if (BB->isSuccessor(PHIBB)) { 1021 PHI->addOperand 1022 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1023 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1024 } 1025 } 1026 } 1027 SDB->JTCases.clear(); 1028 1029 // If the switch block involved a branch to one of the actual successors, we 1030 // need to update PHI nodes in that block. 1031 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1032 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1033 assert(PHI->isPHI() && 1034 "This is not a machine PHI node that we are updating!"); 1035 if (BB->isSuccessor(PHI->getParent())) { 1036 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1037 false)); 1038 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1039 } 1040 } 1041 1042 // If we generated any switch lowering information, build and codegen any 1043 // additional DAGs necessary. 1044 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1045 // Set the current basic block to the mbb we wish to insert the code into 1046 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1047 1048 // Emit the code 1049 SDB->visitSwitchCase(SDB->SwitchCases[i], BB); 1050 CurDAG->setRoot(SDB->getRoot()); 1051 CodeGenAndEmitDAG(); 1052 1053 // Handle any PHI nodes in successors of this chunk, as if we were coming 1054 // from the original BB before switch expansion. Note that PHI nodes can 1055 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1056 // handle them the right number of times. 1057 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1058 // If new BB's are created during scheduling, the edges may have been 1059 // updated. That is, the edge from ThisBB to BB may have been split and 1060 // BB's predecessor is now another block. 1061 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1062 SDB->EdgeMapping.find(BB); 1063 if (EI != SDB->EdgeMapping.end()) 1064 ThisBB = EI->second; 1065 1066 // BB may have been removed from the CFG if a branch was constant folded. 1067 if (ThisBB->isSuccessor(BB)) { 1068 for (MachineBasicBlock::iterator Phi = BB->begin(); 1069 Phi != BB->end() && Phi->isPHI(); 1070 ++Phi) { 1071 // This value for this PHI node is recorded in PHINodesToUpdate. 1072 for (unsigned pn = 0; ; ++pn) { 1073 assert(pn != SDB->PHINodesToUpdate.size() && 1074 "Didn't find PHI entry!"); 1075 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1076 Phi->addOperand(MachineOperand:: 1077 CreateReg(SDB->PHINodesToUpdate[pn].second, 1078 false)); 1079 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1080 break; 1081 } 1082 } 1083 } 1084 } 1085 1086 // Don't process RHS if same block as LHS. 1087 if (BB == SDB->SwitchCases[i].FalseBB) 1088 SDB->SwitchCases[i].FalseBB = 0; 1089 1090 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1091 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1092 SDB->SwitchCases[i].FalseBB = 0; 1093 } 1094 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1095 SDB->clear(); 1096 } 1097 SDB->SwitchCases.clear(); 1098 1099 SDB->PHINodesToUpdate.clear(); 1100} 1101 1102 1103/// Create the scheduler. If a specific scheduler was specified 1104/// via the SchedulerRegistry, use it, otherwise select the 1105/// one preferred by the target. 1106/// 1107ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1108 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1109 1110 if (!Ctor) { 1111 Ctor = ISHeuristic; 1112 RegisterScheduler::setDefault(Ctor); 1113 } 1114 1115 return Ctor(this, OptLevel); 1116} 1117 1118ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1119 return new ScheduleHazardRecognizer(); 1120} 1121 1122//===----------------------------------------------------------------------===// 1123// Helper functions used by the generated instruction selector. 1124//===----------------------------------------------------------------------===// 1125// Calls to these methods are generated by tblgen. 1126 1127/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1128/// the dag combiner simplified the 255, we still want to match. RHS is the 1129/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1130/// specified in the .td file (e.g. 255). 1131bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1132 int64_t DesiredMaskS) const { 1133 const APInt &ActualMask = RHS->getAPIntValue(); 1134 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1135 1136 // If the actual mask exactly matches, success! 1137 if (ActualMask == DesiredMask) 1138 return true; 1139 1140 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1141 if (ActualMask.intersects(~DesiredMask)) 1142 return false; 1143 1144 // Otherwise, the DAG Combiner may have proven that the value coming in is 1145 // either already zero or is not demanded. Check for known zero input bits. 1146 APInt NeededMask = DesiredMask & ~ActualMask; 1147 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1148 return true; 1149 1150 // TODO: check to see if missing bits are just not demanded. 1151 1152 // Otherwise, this pattern doesn't match. 1153 return false; 1154} 1155 1156/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1157/// the dag combiner simplified the 255, we still want to match. RHS is the 1158/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1159/// specified in the .td file (e.g. 255). 1160bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1161 int64_t DesiredMaskS) const { 1162 const APInt &ActualMask = RHS->getAPIntValue(); 1163 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1164 1165 // If the actual mask exactly matches, success! 1166 if (ActualMask == DesiredMask) 1167 return true; 1168 1169 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1170 if (ActualMask.intersects(~DesiredMask)) 1171 return false; 1172 1173 // Otherwise, the DAG Combiner may have proven that the value coming in is 1174 // either already zero or is not demanded. Check for known zero input bits. 1175 APInt NeededMask = DesiredMask & ~ActualMask; 1176 1177 APInt KnownZero, KnownOne; 1178 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1179 1180 // If all the missing bits in the or are already known to be set, match! 1181 if ((NeededMask & KnownOne) == NeededMask) 1182 return true; 1183 1184 // TODO: check to see if missing bits are just not demanded. 1185 1186 // Otherwise, this pattern doesn't match. 1187 return false; 1188} 1189 1190 1191/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1192/// by tblgen. Others should not call it. 1193void SelectionDAGISel:: 1194SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1195 std::vector<SDValue> InOps; 1196 std::swap(InOps, Ops); 1197 1198 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1199 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1200 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1201 1202 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1203 if (InOps[e-1].getValueType() == MVT::Flag) 1204 --e; // Don't process a flag operand if it is here. 1205 1206 while (i != e) { 1207 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1208 if (!InlineAsm::isMemKind(Flags)) { 1209 // Just skip over this operand, copying the operands verbatim. 1210 Ops.insert(Ops.end(), InOps.begin()+i, 1211 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1212 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1213 } else { 1214 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1215 "Memory operand with multiple values?"); 1216 // Otherwise, this is a memory operand. Ask the target to select it. 1217 std::vector<SDValue> SelOps; 1218 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1219 report_fatal_error("Could not match memory address. Inline asm" 1220 " failure!"); 1221 1222 // Add this to the output node. 1223 unsigned NewFlags = 1224 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1225 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1226 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1227 i += 2; 1228 } 1229 } 1230 1231 // Add the flag input back if present. 1232 if (e != InOps.size()) 1233 Ops.push_back(InOps.back()); 1234} 1235 1236/// findFlagUse - Return use of EVT::Flag value produced by the specified 1237/// SDNode. 1238/// 1239static SDNode *findFlagUse(SDNode *N) { 1240 unsigned FlagResNo = N->getNumValues()-1; 1241 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1242 SDUse &Use = I.getUse(); 1243 if (Use.getResNo() == FlagResNo) 1244 return Use.getUser(); 1245 } 1246 return NULL; 1247} 1248 1249/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1250/// This function recursively traverses up the operand chain, ignoring 1251/// certain nodes. 1252static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1253 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1254 bool IgnoreChains) { 1255 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1256 // greater than all of its (recursive) operands. If we scan to a point where 1257 // 'use' is smaller than the node we're scanning for, then we know we will 1258 // never find it. 1259 // 1260 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1261 // happen because we scan down to newly selected nodes in the case of flag 1262 // uses. 1263 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1264 return false; 1265 1266 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1267 // won't fail if we scan it again. 1268 if (!Visited.insert(Use)) 1269 return false; 1270 1271 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1272 // Ignore chain uses, they are validated by HandleMergeInputChains. 1273 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1274 continue; 1275 1276 SDNode *N = Use->getOperand(i).getNode(); 1277 if (N == Def) { 1278 if (Use == ImmedUse || Use == Root) 1279 continue; // We are not looking for immediate use. 1280 assert(N != Root); 1281 return true; 1282 } 1283 1284 // Traverse up the operand chain. 1285 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1286 return true; 1287 } 1288 return false; 1289} 1290 1291/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1292/// operand node N of U during instruction selection that starts at Root. 1293bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1294 SDNode *Root) const { 1295 if (OptLevel == CodeGenOpt::None) return false; 1296 return N.hasOneUse(); 1297} 1298 1299/// IsLegalToFold - Returns true if the specific operand node N of 1300/// U can be folded during instruction selection that starts at Root. 1301bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1302 CodeGenOpt::Level OptLevel, 1303 bool IgnoreChains) { 1304 if (OptLevel == CodeGenOpt::None) return false; 1305 1306 // If Root use can somehow reach N through a path that that doesn't contain 1307 // U then folding N would create a cycle. e.g. In the following 1308 // diagram, Root can reach N through X. If N is folded into into Root, then 1309 // X is both a predecessor and a successor of U. 1310 // 1311 // [N*] // 1312 // ^ ^ // 1313 // / \ // 1314 // [U*] [X]? // 1315 // ^ ^ // 1316 // \ / // 1317 // \ / // 1318 // [Root*] // 1319 // 1320 // * indicates nodes to be folded together. 1321 // 1322 // If Root produces a flag, then it gets (even more) interesting. Since it 1323 // will be "glued" together with its flag use in the scheduler, we need to 1324 // check if it might reach N. 1325 // 1326 // [N*] // 1327 // ^ ^ // 1328 // / \ // 1329 // [U*] [X]? // 1330 // ^ ^ // 1331 // \ \ // 1332 // \ | // 1333 // [Root*] | // 1334 // ^ | // 1335 // f | // 1336 // | / // 1337 // [Y] / // 1338 // ^ / // 1339 // f / // 1340 // | / // 1341 // [FU] // 1342 // 1343 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1344 // (call it Fold), then X is a predecessor of FU and a successor of 1345 // Fold. But since Fold and FU are flagged together, this will create 1346 // a cycle in the scheduling graph. 1347 1348 // If the node has flags, walk down the graph to the "lowest" node in the 1349 // flagged set. 1350 EVT VT = Root->getValueType(Root->getNumValues()-1); 1351 while (VT == MVT::Flag) { 1352 SDNode *FU = findFlagUse(Root); 1353 if (FU == NULL) 1354 break; 1355 Root = FU; 1356 VT = Root->getValueType(Root->getNumValues()-1); 1357 1358 // If our query node has a flag result with a use, we've walked up it. If 1359 // the user (which has already been selected) has a chain or indirectly uses 1360 // the chain, our WalkChainUsers predicate will not consider it. Because of 1361 // this, we cannot ignore chains in this predicate. 1362 IgnoreChains = false; 1363 } 1364 1365 1366 SmallPtrSet<SDNode*, 16> Visited; 1367 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1368} 1369 1370SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1371 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1372 SelectInlineAsmMemoryOperands(Ops); 1373 1374 std::vector<EVT> VTs; 1375 VTs.push_back(MVT::Other); 1376 VTs.push_back(MVT::Flag); 1377 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1378 VTs, &Ops[0], Ops.size()); 1379 New->setNodeId(-1); 1380 return New.getNode(); 1381} 1382 1383SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1384 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1385} 1386 1387/// GetVBR - decode a vbr encoding whose top bit is set. 1388ALWAYS_INLINE static uint64_t 1389GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1390 assert(Val >= 128 && "Not a VBR"); 1391 Val &= 127; // Remove first vbr bit. 1392 1393 unsigned Shift = 7; 1394 uint64_t NextBits; 1395 do { 1396 NextBits = MatcherTable[Idx++]; 1397 Val |= (NextBits&127) << Shift; 1398 Shift += 7; 1399 } while (NextBits & 128); 1400 1401 return Val; 1402} 1403 1404 1405/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1406/// interior flag and chain results to use the new flag and chain results. 1407void SelectionDAGISel:: 1408UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1409 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1410 SDValue InputFlag, 1411 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1412 bool isMorphNodeTo) { 1413 SmallVector<SDNode*, 4> NowDeadNodes; 1414 1415 ISelUpdater ISU(ISelPosition); 1416 1417 // Now that all the normal results are replaced, we replace the chain and 1418 // flag results if present. 1419 if (!ChainNodesMatched.empty()) { 1420 assert(InputChain.getNode() != 0 && 1421 "Matched input chains but didn't produce a chain"); 1422 // Loop over all of the nodes we matched that produced a chain result. 1423 // Replace all the chain results with the final chain we ended up with. 1424 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1425 SDNode *ChainNode = ChainNodesMatched[i]; 1426 1427 // If this node was already deleted, don't look at it. 1428 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1429 continue; 1430 1431 // Don't replace the results of the root node if we're doing a 1432 // MorphNodeTo. 1433 if (ChainNode == NodeToMatch && isMorphNodeTo) 1434 continue; 1435 1436 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1437 if (ChainVal.getValueType() == MVT::Flag) 1438 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1439 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1440 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1441 1442 // If the node became dead and we haven't already seen it, delete it. 1443 if (ChainNode->use_empty() && 1444 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1445 NowDeadNodes.push_back(ChainNode); 1446 } 1447 } 1448 1449 // If the result produces a flag, update any flag results in the matched 1450 // pattern with the flag result. 1451 if (InputFlag.getNode() != 0) { 1452 // Handle any interior nodes explicitly marked. 1453 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1454 SDNode *FRN = FlagResultNodesMatched[i]; 1455 1456 // If this node was already deleted, don't look at it. 1457 if (FRN->getOpcode() == ISD::DELETED_NODE) 1458 continue; 1459 1460 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1461 "Doesn't have a flag result"); 1462 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1463 InputFlag, &ISU); 1464 1465 // If the node became dead and we haven't already seen it, delete it. 1466 if (FRN->use_empty() && 1467 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1468 NowDeadNodes.push_back(FRN); 1469 } 1470 } 1471 1472 if (!NowDeadNodes.empty()) 1473 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1474 1475 DEBUG(errs() << "ISEL: Match complete!\n"); 1476} 1477 1478enum ChainResult { 1479 CR_Simple, 1480 CR_InducesCycle, 1481 CR_LeadsToInteriorNode 1482}; 1483 1484/// WalkChainUsers - Walk down the users of the specified chained node that is 1485/// part of the pattern we're matching, looking at all of the users we find. 1486/// This determines whether something is an interior node, whether we have a 1487/// non-pattern node in between two pattern nodes (which prevent folding because 1488/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1489/// between pattern nodes (in which case the TF becomes part of the pattern). 1490/// 1491/// The walk we do here is guaranteed to be small because we quickly get down to 1492/// already selected nodes "below" us. 1493static ChainResult 1494WalkChainUsers(SDNode *ChainedNode, 1495 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1496 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1497 ChainResult Result = CR_Simple; 1498 1499 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1500 E = ChainedNode->use_end(); UI != E; ++UI) { 1501 // Make sure the use is of the chain, not some other value we produce. 1502 if (UI.getUse().getValueType() != MVT::Other) continue; 1503 1504 SDNode *User = *UI; 1505 1506 // If we see an already-selected machine node, then we've gone beyond the 1507 // pattern that we're selecting down into the already selected chunk of the 1508 // DAG. 1509 if (User->isMachineOpcode() || 1510 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1511 continue; 1512 1513 if (User->getOpcode() == ISD::CopyToReg || 1514 User->getOpcode() == ISD::CopyFromReg || 1515 User->getOpcode() == ISD::INLINEASM || 1516 User->getOpcode() == ISD::EH_LABEL) { 1517 // If their node ID got reset to -1 then they've already been selected. 1518 // Treat them like a MachineOpcode. 1519 if (User->getNodeId() == -1) 1520 continue; 1521 } 1522 1523 // If we have a TokenFactor, we handle it specially. 1524 if (User->getOpcode() != ISD::TokenFactor) { 1525 // If the node isn't a token factor and isn't part of our pattern, then it 1526 // must be a random chained node in between two nodes we're selecting. 1527 // This happens when we have something like: 1528 // x = load ptr 1529 // call 1530 // y = x+4 1531 // store y -> ptr 1532 // Because we structurally match the load/store as a read/modify/write, 1533 // but the call is chained between them. We cannot fold in this case 1534 // because it would induce a cycle in the graph. 1535 if (!std::count(ChainedNodesInPattern.begin(), 1536 ChainedNodesInPattern.end(), User)) 1537 return CR_InducesCycle; 1538 1539 // Otherwise we found a node that is part of our pattern. For example in: 1540 // x = load ptr 1541 // y = x+4 1542 // store y -> ptr 1543 // This would happen when we're scanning down from the load and see the 1544 // store as a user. Record that there is a use of ChainedNode that is 1545 // part of the pattern and keep scanning uses. 1546 Result = CR_LeadsToInteriorNode; 1547 InteriorChainedNodes.push_back(User); 1548 continue; 1549 } 1550 1551 // If we found a TokenFactor, there are two cases to consider: first if the 1552 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1553 // uses of the TF are in our pattern) we just want to ignore it. Second, 1554 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1555 // [Load chain] 1556 // ^ 1557 // | 1558 // [Load] 1559 // ^ ^ 1560 // | \ DAG's like cheese 1561 // / \ do you? 1562 // / | 1563 // [TokenFactor] [Op] 1564 // ^ ^ 1565 // | | 1566 // \ / 1567 // \ / 1568 // [Store] 1569 // 1570 // In this case, the TokenFactor becomes part of our match and we rewrite it 1571 // as a new TokenFactor. 1572 // 1573 // To distinguish these two cases, do a recursive walk down the uses. 1574 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1575 case CR_Simple: 1576 // If the uses of the TokenFactor are just already-selected nodes, ignore 1577 // it, it is "below" our pattern. 1578 continue; 1579 case CR_InducesCycle: 1580 // If the uses of the TokenFactor lead to nodes that are not part of our 1581 // pattern that are not selected, folding would turn this into a cycle, 1582 // bail out now. 1583 return CR_InducesCycle; 1584 case CR_LeadsToInteriorNode: 1585 break; // Otherwise, keep processing. 1586 } 1587 1588 // Okay, we know we're in the interesting interior case. The TokenFactor 1589 // is now going to be considered part of the pattern so that we rewrite its 1590 // uses (it may have uses that are not part of the pattern) with the 1591 // ultimate chain result of the generated code. We will also add its chain 1592 // inputs as inputs to the ultimate TokenFactor we create. 1593 Result = CR_LeadsToInteriorNode; 1594 ChainedNodesInPattern.push_back(User); 1595 InteriorChainedNodes.push_back(User); 1596 continue; 1597 } 1598 1599 return Result; 1600} 1601 1602/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1603/// operation for when the pattern matched at least one node with a chains. The 1604/// input vector contains a list of all of the chained nodes that we match. We 1605/// must determine if this is a valid thing to cover (i.e. matching it won't 1606/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1607/// be used as the input node chain for the generated nodes. 1608static SDValue 1609HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1610 SelectionDAG *CurDAG) { 1611 // Walk all of the chained nodes we've matched, recursively scanning down the 1612 // users of the chain result. This adds any TokenFactor nodes that are caught 1613 // in between chained nodes to the chained and interior nodes list. 1614 SmallVector<SDNode*, 3> InteriorChainedNodes; 1615 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1616 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1617 InteriorChainedNodes) == CR_InducesCycle) 1618 return SDValue(); // Would induce a cycle. 1619 } 1620 1621 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1622 // that we are interested in. Form our input TokenFactor node. 1623 SmallVector<SDValue, 3> InputChains; 1624 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1625 // Add the input chain of this node to the InputChains list (which will be 1626 // the operands of the generated TokenFactor) if it's not an interior node. 1627 SDNode *N = ChainNodesMatched[i]; 1628 if (N->getOpcode() != ISD::TokenFactor) { 1629 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1630 continue; 1631 1632 // Otherwise, add the input chain. 1633 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1634 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1635 InputChains.push_back(InChain); 1636 continue; 1637 } 1638 1639 // If we have a token factor, we want to add all inputs of the token factor 1640 // that are not part of the pattern we're matching. 1641 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1642 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1643 N->getOperand(op).getNode())) 1644 InputChains.push_back(N->getOperand(op)); 1645 } 1646 } 1647 1648 SDValue Res; 1649 if (InputChains.size() == 1) 1650 return InputChains[0]; 1651 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1652 MVT::Other, &InputChains[0], InputChains.size()); 1653} 1654 1655/// MorphNode - Handle morphing a node in place for the selector. 1656SDNode *SelectionDAGISel:: 1657MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1658 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1659 // It is possible we're using MorphNodeTo to replace a node with no 1660 // normal results with one that has a normal result (or we could be 1661 // adding a chain) and the input could have flags and chains as well. 1662 // In this case we need to shift the operands down. 1663 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1664 // than the old isel though. 1665 int OldFlagResultNo = -1, OldChainResultNo = -1; 1666 1667 unsigned NTMNumResults = Node->getNumValues(); 1668 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1669 OldFlagResultNo = NTMNumResults-1; 1670 if (NTMNumResults != 1 && 1671 Node->getValueType(NTMNumResults-2) == MVT::Other) 1672 OldChainResultNo = NTMNumResults-2; 1673 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1674 OldChainResultNo = NTMNumResults-1; 1675 1676 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1677 // that this deletes operands of the old node that become dead. 1678 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1679 1680 // MorphNodeTo can operate in two ways: if an existing node with the 1681 // specified operands exists, it can just return it. Otherwise, it 1682 // updates the node in place to have the requested operands. 1683 if (Res == Node) { 1684 // If we updated the node in place, reset the node ID. To the isel, 1685 // this should be just like a newly allocated machine node. 1686 Res->setNodeId(-1); 1687 } 1688 1689 unsigned ResNumResults = Res->getNumValues(); 1690 // Move the flag if needed. 1691 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1692 (unsigned)OldFlagResultNo != ResNumResults-1) 1693 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1694 SDValue(Res, ResNumResults-1)); 1695 1696 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1697 --ResNumResults; 1698 1699 // Move the chain reference if needed. 1700 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1701 (unsigned)OldChainResultNo != ResNumResults-1) 1702 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1703 SDValue(Res, ResNumResults-1)); 1704 1705 // Otherwise, no replacement happened because the node already exists. Replace 1706 // Uses of the old node with the new one. 1707 if (Res != Node) 1708 CurDAG->ReplaceAllUsesWith(Node, Res); 1709 1710 return Res; 1711} 1712 1713/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1714ALWAYS_INLINE static bool 1715CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1716 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1717 // Accept if it is exactly the same as a previously recorded node. 1718 unsigned RecNo = MatcherTable[MatcherIndex++]; 1719 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1720 return N == RecordedNodes[RecNo]; 1721} 1722 1723/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1724ALWAYS_INLINE static bool 1725CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1726 SelectionDAGISel &SDISel) { 1727 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1728} 1729 1730/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1731ALWAYS_INLINE static bool 1732CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1733 SelectionDAGISel &SDISel, SDNode *N) { 1734 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1735} 1736 1737ALWAYS_INLINE static bool 1738CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1739 SDNode *N) { 1740 uint16_t Opc = MatcherTable[MatcherIndex++]; 1741 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1742 return N->getOpcode() == Opc; 1743} 1744 1745ALWAYS_INLINE static bool 1746CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1747 SDValue N, const TargetLowering &TLI) { 1748 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1749 if (N.getValueType() == VT) return true; 1750 1751 // Handle the case when VT is iPTR. 1752 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1753} 1754 1755ALWAYS_INLINE static bool 1756CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1757 SDValue N, const TargetLowering &TLI, 1758 unsigned ChildNo) { 1759 if (ChildNo >= N.getNumOperands()) 1760 return false; // Match fails if out of range child #. 1761 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1762} 1763 1764 1765ALWAYS_INLINE static bool 1766CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1767 SDValue N) { 1768 return cast<CondCodeSDNode>(N)->get() == 1769 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1770} 1771 1772ALWAYS_INLINE static bool 1773CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1774 SDValue N, const TargetLowering &TLI) { 1775 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1776 if (cast<VTSDNode>(N)->getVT() == VT) 1777 return true; 1778 1779 // Handle the case when VT is iPTR. 1780 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1781} 1782 1783ALWAYS_INLINE static bool 1784CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1785 SDValue N) { 1786 int64_t Val = MatcherTable[MatcherIndex++]; 1787 if (Val & 128) 1788 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1789 1790 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1791 return C != 0 && C->getSExtValue() == Val; 1792} 1793 1794ALWAYS_INLINE static bool 1795CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1796 SDValue N, SelectionDAGISel &SDISel) { 1797 int64_t Val = MatcherTable[MatcherIndex++]; 1798 if (Val & 128) 1799 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1800 1801 if (N->getOpcode() != ISD::AND) return false; 1802 1803 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1804 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1805} 1806 1807ALWAYS_INLINE static bool 1808CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1809 SDValue N, SelectionDAGISel &SDISel) { 1810 int64_t Val = MatcherTable[MatcherIndex++]; 1811 if (Val & 128) 1812 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1813 1814 if (N->getOpcode() != ISD::OR) return false; 1815 1816 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1817 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1818} 1819 1820/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1821/// scope, evaluate the current node. If the current predicate is known to 1822/// fail, set Result=true and return anything. If the current predicate is 1823/// known to pass, set Result=false and return the MatcherIndex to continue 1824/// with. If the current predicate is unknown, set Result=false and return the 1825/// MatcherIndex to continue with. 1826static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1827 unsigned Index, SDValue N, 1828 bool &Result, SelectionDAGISel &SDISel, 1829 SmallVectorImpl<SDValue> &RecordedNodes){ 1830 switch (Table[Index++]) { 1831 default: 1832 Result = false; 1833 return Index-1; // Could not evaluate this predicate. 1834 case SelectionDAGISel::OPC_CheckSame: 1835 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1836 return Index; 1837 case SelectionDAGISel::OPC_CheckPatternPredicate: 1838 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1839 return Index; 1840 case SelectionDAGISel::OPC_CheckPredicate: 1841 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1842 return Index; 1843 case SelectionDAGISel::OPC_CheckOpcode: 1844 Result = !::CheckOpcode(Table, Index, N.getNode()); 1845 return Index; 1846 case SelectionDAGISel::OPC_CheckType: 1847 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1848 return Index; 1849 case SelectionDAGISel::OPC_CheckChild0Type: 1850 case SelectionDAGISel::OPC_CheckChild1Type: 1851 case SelectionDAGISel::OPC_CheckChild2Type: 1852 case SelectionDAGISel::OPC_CheckChild3Type: 1853 case SelectionDAGISel::OPC_CheckChild4Type: 1854 case SelectionDAGISel::OPC_CheckChild5Type: 1855 case SelectionDAGISel::OPC_CheckChild6Type: 1856 case SelectionDAGISel::OPC_CheckChild7Type: 1857 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1858 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1859 return Index; 1860 case SelectionDAGISel::OPC_CheckCondCode: 1861 Result = !::CheckCondCode(Table, Index, N); 1862 return Index; 1863 case SelectionDAGISel::OPC_CheckValueType: 1864 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1865 return Index; 1866 case SelectionDAGISel::OPC_CheckInteger: 1867 Result = !::CheckInteger(Table, Index, N); 1868 return Index; 1869 case SelectionDAGISel::OPC_CheckAndImm: 1870 Result = !::CheckAndImm(Table, Index, N, SDISel); 1871 return Index; 1872 case SelectionDAGISel::OPC_CheckOrImm: 1873 Result = !::CheckOrImm(Table, Index, N, SDISel); 1874 return Index; 1875 } 1876} 1877 1878namespace { 1879 1880struct MatchScope { 1881 /// FailIndex - If this match fails, this is the index to continue with. 1882 unsigned FailIndex; 1883 1884 /// NodeStack - The node stack when the scope was formed. 1885 SmallVector<SDValue, 4> NodeStack; 1886 1887 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1888 unsigned NumRecordedNodes; 1889 1890 /// NumMatchedMemRefs - The number of matched memref entries. 1891 unsigned NumMatchedMemRefs; 1892 1893 /// InputChain/InputFlag - The current chain/flag 1894 SDValue InputChain, InputFlag; 1895 1896 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1897 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1898}; 1899 1900} 1901 1902SDNode *SelectionDAGISel:: 1903SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1904 unsigned TableSize) { 1905 // FIXME: Should these even be selected? Handle these cases in the caller? 1906 switch (NodeToMatch->getOpcode()) { 1907 default: 1908 break; 1909 case ISD::EntryToken: // These nodes remain the same. 1910 case ISD::BasicBlock: 1911 case ISD::Register: 1912 //case ISD::VALUETYPE: 1913 //case ISD::CONDCODE: 1914 case ISD::HANDLENODE: 1915 case ISD::MDNODE_SDNODE: 1916 case ISD::TargetConstant: 1917 case ISD::TargetConstantFP: 1918 case ISD::TargetConstantPool: 1919 case ISD::TargetFrameIndex: 1920 case ISD::TargetExternalSymbol: 1921 case ISD::TargetBlockAddress: 1922 case ISD::TargetJumpTable: 1923 case ISD::TargetGlobalTLSAddress: 1924 case ISD::TargetGlobalAddress: 1925 case ISD::TokenFactor: 1926 case ISD::CopyFromReg: 1927 case ISD::CopyToReg: 1928 case ISD::EH_LABEL: 1929 NodeToMatch->setNodeId(-1); // Mark selected. 1930 return 0; 1931 case ISD::AssertSext: 1932 case ISD::AssertZext: 1933 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1934 NodeToMatch->getOperand(0)); 1935 return 0; 1936 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1937 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1938 } 1939 1940 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1941 1942 // Set up the node stack with NodeToMatch as the only node on the stack. 1943 SmallVector<SDValue, 8> NodeStack; 1944 SDValue N = SDValue(NodeToMatch, 0); 1945 NodeStack.push_back(N); 1946 1947 // MatchScopes - Scopes used when matching, if a match failure happens, this 1948 // indicates where to continue checking. 1949 SmallVector<MatchScope, 8> MatchScopes; 1950 1951 // RecordedNodes - This is the set of nodes that have been recorded by the 1952 // state machine. 1953 SmallVector<SDValue, 8> RecordedNodes; 1954 1955 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1956 // pattern. 1957 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1958 1959 // These are the current input chain and flag for use when generating nodes. 1960 // Various Emit operations change these. For example, emitting a copytoreg 1961 // uses and updates these. 1962 SDValue InputChain, InputFlag; 1963 1964 // ChainNodesMatched - If a pattern matches nodes that have input/output 1965 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1966 // which ones they are. The result is captured into this list so that we can 1967 // update the chain results when the pattern is complete. 1968 SmallVector<SDNode*, 3> ChainNodesMatched; 1969 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1970 1971 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1972 NodeToMatch->dump(CurDAG); 1973 errs() << '\n'); 1974 1975 // Determine where to start the interpreter. Normally we start at opcode #0, 1976 // but if the state machine starts with an OPC_SwitchOpcode, then we 1977 // accelerate the first lookup (which is guaranteed to be hot) with the 1978 // OpcodeOffset table. 1979 unsigned MatcherIndex = 0; 1980 1981 if (!OpcodeOffset.empty()) { 1982 // Already computed the OpcodeOffset table, just index into it. 1983 if (N.getOpcode() < OpcodeOffset.size()) 1984 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1985 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1986 1987 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1988 // Otherwise, the table isn't computed, but the state machine does start 1989 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1990 // is the first time we're selecting an instruction. 1991 unsigned Idx = 1; 1992 while (1) { 1993 // Get the size of this case. 1994 unsigned CaseSize = MatcherTable[Idx++]; 1995 if (CaseSize & 128) 1996 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1997 if (CaseSize == 0) break; 1998 1999 // Get the opcode, add the index to the table. 2000 uint16_t Opc = MatcherTable[Idx++]; 2001 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2002 if (Opc >= OpcodeOffset.size()) 2003 OpcodeOffset.resize((Opc+1)*2); 2004 OpcodeOffset[Opc] = Idx; 2005 Idx += CaseSize; 2006 } 2007 2008 // Okay, do the lookup for the first opcode. 2009 if (N.getOpcode() < OpcodeOffset.size()) 2010 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2011 } 2012 2013 while (1) { 2014 assert(MatcherIndex < TableSize && "Invalid index"); 2015#ifndef NDEBUG 2016 unsigned CurrentOpcodeIndex = MatcherIndex; 2017#endif 2018 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2019 switch (Opcode) { 2020 case OPC_Scope: { 2021 // Okay, the semantics of this operation are that we should push a scope 2022 // then evaluate the first child. However, pushing a scope only to have 2023 // the first check fail (which then pops it) is inefficient. If we can 2024 // determine immediately that the first check (or first several) will 2025 // immediately fail, don't even bother pushing a scope for them. 2026 unsigned FailIndex; 2027 2028 while (1) { 2029 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2030 if (NumToSkip & 128) 2031 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2032 // Found the end of the scope with no match. 2033 if (NumToSkip == 0) { 2034 FailIndex = 0; 2035 break; 2036 } 2037 2038 FailIndex = MatcherIndex+NumToSkip; 2039 2040 unsigned MatcherIndexOfPredicate = MatcherIndex; 2041 (void)MatcherIndexOfPredicate; // silence warning. 2042 2043 // If we can't evaluate this predicate without pushing a scope (e.g. if 2044 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2045 // push the scope and evaluate the full predicate chain. 2046 bool Result; 2047 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2048 Result, *this, RecordedNodes); 2049 if (!Result) 2050 break; 2051 2052 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2053 << "index " << MatcherIndexOfPredicate 2054 << ", continuing at " << FailIndex << "\n"); 2055 ++NumDAGIselRetries; 2056 2057 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2058 // move to the next case. 2059 MatcherIndex = FailIndex; 2060 } 2061 2062 // If the whole scope failed to match, bail. 2063 if (FailIndex == 0) break; 2064 2065 // Push a MatchScope which indicates where to go if the first child fails 2066 // to match. 2067 MatchScope NewEntry; 2068 NewEntry.FailIndex = FailIndex; 2069 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2070 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2071 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2072 NewEntry.InputChain = InputChain; 2073 NewEntry.InputFlag = InputFlag; 2074 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2075 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2076 MatchScopes.push_back(NewEntry); 2077 continue; 2078 } 2079 case OPC_RecordNode: 2080 // Remember this node, it may end up being an operand in the pattern. 2081 RecordedNodes.push_back(N); 2082 continue; 2083 2084 case OPC_RecordChild0: case OPC_RecordChild1: 2085 case OPC_RecordChild2: case OPC_RecordChild3: 2086 case OPC_RecordChild4: case OPC_RecordChild5: 2087 case OPC_RecordChild6: case OPC_RecordChild7: { 2088 unsigned ChildNo = Opcode-OPC_RecordChild0; 2089 if (ChildNo >= N.getNumOperands()) 2090 break; // Match fails if out of range child #. 2091 2092 RecordedNodes.push_back(N->getOperand(ChildNo)); 2093 continue; 2094 } 2095 case OPC_RecordMemRef: 2096 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2097 continue; 2098 2099 case OPC_CaptureFlagInput: 2100 // If the current node has an input flag, capture it in InputFlag. 2101 if (N->getNumOperands() != 0 && 2102 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2103 InputFlag = N->getOperand(N->getNumOperands()-1); 2104 continue; 2105 2106 case OPC_MoveChild: { 2107 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2108 if (ChildNo >= N.getNumOperands()) 2109 break; // Match fails if out of range child #. 2110 N = N.getOperand(ChildNo); 2111 NodeStack.push_back(N); 2112 continue; 2113 } 2114 2115 case OPC_MoveParent: 2116 // Pop the current node off the NodeStack. 2117 NodeStack.pop_back(); 2118 assert(!NodeStack.empty() && "Node stack imbalance!"); 2119 N = NodeStack.back(); 2120 continue; 2121 2122 case OPC_CheckSame: 2123 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2124 continue; 2125 case OPC_CheckPatternPredicate: 2126 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2127 continue; 2128 case OPC_CheckPredicate: 2129 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2130 N.getNode())) 2131 break; 2132 continue; 2133 case OPC_CheckComplexPat: { 2134 unsigned CPNum = MatcherTable[MatcherIndex++]; 2135 unsigned RecNo = MatcherTable[MatcherIndex++]; 2136 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2137 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2138 RecordedNodes)) 2139 break; 2140 continue; 2141 } 2142 case OPC_CheckOpcode: 2143 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2144 continue; 2145 2146 case OPC_CheckType: 2147 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2148 continue; 2149 2150 case OPC_SwitchOpcode: { 2151 unsigned CurNodeOpcode = N.getOpcode(); 2152 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2153 unsigned CaseSize; 2154 while (1) { 2155 // Get the size of this case. 2156 CaseSize = MatcherTable[MatcherIndex++]; 2157 if (CaseSize & 128) 2158 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2159 if (CaseSize == 0) break; 2160 2161 uint16_t Opc = MatcherTable[MatcherIndex++]; 2162 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2163 2164 // If the opcode matches, then we will execute this case. 2165 if (CurNodeOpcode == Opc) 2166 break; 2167 2168 // Otherwise, skip over this case. 2169 MatcherIndex += CaseSize; 2170 } 2171 2172 // If no cases matched, bail out. 2173 if (CaseSize == 0) break; 2174 2175 // Otherwise, execute the case we found. 2176 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2177 << " to " << MatcherIndex << "\n"); 2178 continue; 2179 } 2180 2181 case OPC_SwitchType: { 2182 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2183 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2184 unsigned CaseSize; 2185 while (1) { 2186 // Get the size of this case. 2187 CaseSize = MatcherTable[MatcherIndex++]; 2188 if (CaseSize & 128) 2189 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2190 if (CaseSize == 0) break; 2191 2192 MVT::SimpleValueType CaseVT = 2193 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2194 if (CaseVT == MVT::iPTR) 2195 CaseVT = TLI.getPointerTy().SimpleTy; 2196 2197 // If the VT matches, then we will execute this case. 2198 if (CurNodeVT == CaseVT) 2199 break; 2200 2201 // Otherwise, skip over this case. 2202 MatcherIndex += CaseSize; 2203 } 2204 2205 // If no cases matched, bail out. 2206 if (CaseSize == 0) break; 2207 2208 // Otherwise, execute the case we found. 2209 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2210 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2211 continue; 2212 } 2213 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2214 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2215 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2216 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2217 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2218 Opcode-OPC_CheckChild0Type)) 2219 break; 2220 continue; 2221 case OPC_CheckCondCode: 2222 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2223 continue; 2224 case OPC_CheckValueType: 2225 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2226 continue; 2227 case OPC_CheckInteger: 2228 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2229 continue; 2230 case OPC_CheckAndImm: 2231 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2232 continue; 2233 case OPC_CheckOrImm: 2234 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2235 continue; 2236 2237 case OPC_CheckFoldableChainNode: { 2238 assert(NodeStack.size() != 1 && "No parent node"); 2239 // Verify that all intermediate nodes between the root and this one have 2240 // a single use. 2241 bool HasMultipleUses = false; 2242 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2243 if (!NodeStack[i].hasOneUse()) { 2244 HasMultipleUses = true; 2245 break; 2246 } 2247 if (HasMultipleUses) break; 2248 2249 // Check to see that the target thinks this is profitable to fold and that 2250 // we can fold it without inducing cycles in the graph. 2251 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2252 NodeToMatch) || 2253 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2254 NodeToMatch, OptLevel, 2255 true/*We validate our own chains*/)) 2256 break; 2257 2258 continue; 2259 } 2260 case OPC_EmitInteger: { 2261 MVT::SimpleValueType VT = 2262 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2263 int64_t Val = MatcherTable[MatcherIndex++]; 2264 if (Val & 128) 2265 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2266 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2267 continue; 2268 } 2269 case OPC_EmitRegister: { 2270 MVT::SimpleValueType VT = 2271 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2272 unsigned RegNo = MatcherTable[MatcherIndex++]; 2273 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2274 continue; 2275 } 2276 2277 case OPC_EmitConvertToTarget: { 2278 // Convert from IMM/FPIMM to target version. 2279 unsigned RecNo = MatcherTable[MatcherIndex++]; 2280 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2281 SDValue Imm = RecordedNodes[RecNo]; 2282 2283 if (Imm->getOpcode() == ISD::Constant) { 2284 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2285 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2286 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2287 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2288 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2289 } 2290 2291 RecordedNodes.push_back(Imm); 2292 continue; 2293 } 2294 2295 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2296 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2297 // These are space-optimized forms of OPC_EmitMergeInputChains. 2298 assert(InputChain.getNode() == 0 && 2299 "EmitMergeInputChains should be the first chain producing node"); 2300 assert(ChainNodesMatched.empty() && 2301 "Should only have one EmitMergeInputChains per match"); 2302 2303 // Read all of the chained nodes. 2304 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2305 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2306 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2307 2308 // FIXME: What if other value results of the node have uses not matched 2309 // by this pattern? 2310 if (ChainNodesMatched.back() != NodeToMatch && 2311 !RecordedNodes[RecNo].hasOneUse()) { 2312 ChainNodesMatched.clear(); 2313 break; 2314 } 2315 2316 // Merge the input chains if they are not intra-pattern references. 2317 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2318 2319 if (InputChain.getNode() == 0) 2320 break; // Failed to merge. 2321 continue; 2322 } 2323 2324 case OPC_EmitMergeInputChains: { 2325 assert(InputChain.getNode() == 0 && 2326 "EmitMergeInputChains should be the first chain producing node"); 2327 // This node gets a list of nodes we matched in the input that have 2328 // chains. We want to token factor all of the input chains to these nodes 2329 // together. However, if any of the input chains is actually one of the 2330 // nodes matched in this pattern, then we have an intra-match reference. 2331 // Ignore these because the newly token factored chain should not refer to 2332 // the old nodes. 2333 unsigned NumChains = MatcherTable[MatcherIndex++]; 2334 assert(NumChains != 0 && "Can't TF zero chains"); 2335 2336 assert(ChainNodesMatched.empty() && 2337 "Should only have one EmitMergeInputChains per match"); 2338 2339 // Read all of the chained nodes. 2340 for (unsigned i = 0; i != NumChains; ++i) { 2341 unsigned RecNo = MatcherTable[MatcherIndex++]; 2342 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2343 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2344 2345 // FIXME: What if other value results of the node have uses not matched 2346 // by this pattern? 2347 if (ChainNodesMatched.back() != NodeToMatch && 2348 !RecordedNodes[RecNo].hasOneUse()) { 2349 ChainNodesMatched.clear(); 2350 break; 2351 } 2352 } 2353 2354 // If the inner loop broke out, the match fails. 2355 if (ChainNodesMatched.empty()) 2356 break; 2357 2358 // Merge the input chains if they are not intra-pattern references. 2359 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2360 2361 if (InputChain.getNode() == 0) 2362 break; // Failed to merge. 2363 2364 continue; 2365 } 2366 2367 case OPC_EmitCopyToReg: { 2368 unsigned RecNo = MatcherTable[MatcherIndex++]; 2369 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2370 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2371 2372 if (InputChain.getNode() == 0) 2373 InputChain = CurDAG->getEntryNode(); 2374 2375 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2376 DestPhysReg, RecordedNodes[RecNo], 2377 InputFlag); 2378 2379 InputFlag = InputChain.getValue(1); 2380 continue; 2381 } 2382 2383 case OPC_EmitNodeXForm: { 2384 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2385 unsigned RecNo = MatcherTable[MatcherIndex++]; 2386 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2387 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2388 continue; 2389 } 2390 2391 case OPC_EmitNode: 2392 case OPC_MorphNodeTo: { 2393 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2394 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2395 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2396 // Get the result VT list. 2397 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2398 SmallVector<EVT, 4> VTs; 2399 for (unsigned i = 0; i != NumVTs; ++i) { 2400 MVT::SimpleValueType VT = 2401 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2402 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2403 VTs.push_back(VT); 2404 } 2405 2406 if (EmitNodeInfo & OPFL_Chain) 2407 VTs.push_back(MVT::Other); 2408 if (EmitNodeInfo & OPFL_FlagOutput) 2409 VTs.push_back(MVT::Flag); 2410 2411 // This is hot code, so optimize the two most common cases of 1 and 2 2412 // results. 2413 SDVTList VTList; 2414 if (VTs.size() == 1) 2415 VTList = CurDAG->getVTList(VTs[0]); 2416 else if (VTs.size() == 2) 2417 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2418 else 2419 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2420 2421 // Get the operand list. 2422 unsigned NumOps = MatcherTable[MatcherIndex++]; 2423 SmallVector<SDValue, 8> Ops; 2424 for (unsigned i = 0; i != NumOps; ++i) { 2425 unsigned RecNo = MatcherTable[MatcherIndex++]; 2426 if (RecNo & 128) 2427 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2428 2429 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2430 Ops.push_back(RecordedNodes[RecNo]); 2431 } 2432 2433 // If there are variadic operands to add, handle them now. 2434 if (EmitNodeInfo & OPFL_VariadicInfo) { 2435 // Determine the start index to copy from. 2436 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2437 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2438 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2439 "Invalid variadic node"); 2440 // Copy all of the variadic operands, not including a potential flag 2441 // input. 2442 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2443 i != e; ++i) { 2444 SDValue V = NodeToMatch->getOperand(i); 2445 if (V.getValueType() == MVT::Flag) break; 2446 Ops.push_back(V); 2447 } 2448 } 2449 2450 // If this has chain/flag inputs, add them. 2451 if (EmitNodeInfo & OPFL_Chain) 2452 Ops.push_back(InputChain); 2453 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2454 Ops.push_back(InputFlag); 2455 2456 // Create the node. 2457 SDNode *Res = 0; 2458 if (Opcode != OPC_MorphNodeTo) { 2459 // If this is a normal EmitNode command, just create the new node and 2460 // add the results to the RecordedNodes list. 2461 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2462 VTList, Ops.data(), Ops.size()); 2463 2464 // Add all the non-flag/non-chain results to the RecordedNodes list. 2465 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2466 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2467 RecordedNodes.push_back(SDValue(Res, i)); 2468 } 2469 2470 } else { 2471 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2472 EmitNodeInfo); 2473 } 2474 2475 // If the node had chain/flag results, update our notion of the current 2476 // chain and flag. 2477 if (EmitNodeInfo & OPFL_FlagOutput) { 2478 InputFlag = SDValue(Res, VTs.size()-1); 2479 if (EmitNodeInfo & OPFL_Chain) 2480 InputChain = SDValue(Res, VTs.size()-2); 2481 } else if (EmitNodeInfo & OPFL_Chain) 2482 InputChain = SDValue(Res, VTs.size()-1); 2483 2484 // If the OPFL_MemRefs flag is set on this node, slap all of the 2485 // accumulated memrefs onto it. 2486 // 2487 // FIXME: This is vastly incorrect for patterns with multiple outputs 2488 // instructions that access memory and for ComplexPatterns that match 2489 // loads. 2490 if (EmitNodeInfo & OPFL_MemRefs) { 2491 MachineSDNode::mmo_iterator MemRefs = 2492 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2493 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2494 cast<MachineSDNode>(Res) 2495 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2496 } 2497 2498 DEBUG(errs() << " " 2499 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2500 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2501 2502 // If this was a MorphNodeTo then we're completely done! 2503 if (Opcode == OPC_MorphNodeTo) { 2504 // Update chain and flag uses. 2505 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2506 InputFlag, FlagResultNodesMatched, true); 2507 return Res; 2508 } 2509 2510 continue; 2511 } 2512 2513 case OPC_MarkFlagResults: { 2514 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2515 2516 // Read and remember all the flag-result nodes. 2517 for (unsigned i = 0; i != NumNodes; ++i) { 2518 unsigned RecNo = MatcherTable[MatcherIndex++]; 2519 if (RecNo & 128) 2520 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2521 2522 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2523 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2524 } 2525 continue; 2526 } 2527 2528 case OPC_CompleteMatch: { 2529 // The match has been completed, and any new nodes (if any) have been 2530 // created. Patch up references to the matched dag to use the newly 2531 // created nodes. 2532 unsigned NumResults = MatcherTable[MatcherIndex++]; 2533 2534 for (unsigned i = 0; i != NumResults; ++i) { 2535 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2536 if (ResSlot & 128) 2537 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2538 2539 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2540 SDValue Res = RecordedNodes[ResSlot]; 2541 2542 assert(i < NodeToMatch->getNumValues() && 2543 NodeToMatch->getValueType(i) != MVT::Other && 2544 NodeToMatch->getValueType(i) != MVT::Flag && 2545 "Invalid number of results to complete!"); 2546 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2547 NodeToMatch->getValueType(i) == MVT::iPTR || 2548 Res.getValueType() == MVT::iPTR || 2549 NodeToMatch->getValueType(i).getSizeInBits() == 2550 Res.getValueType().getSizeInBits()) && 2551 "invalid replacement"); 2552 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2553 } 2554 2555 // If the root node defines a flag, add it to the flag nodes to update 2556 // list. 2557 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2558 FlagResultNodesMatched.push_back(NodeToMatch); 2559 2560 // Update chain and flag uses. 2561 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2562 InputFlag, FlagResultNodesMatched, false); 2563 2564 assert(NodeToMatch->use_empty() && 2565 "Didn't replace all uses of the node?"); 2566 2567 // FIXME: We just return here, which interacts correctly with SelectRoot 2568 // above. We should fix this to not return an SDNode* anymore. 2569 return 0; 2570 } 2571 } 2572 2573 // If the code reached this point, then the match failed. See if there is 2574 // another child to try in the current 'Scope', otherwise pop it until we 2575 // find a case to check. 2576 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2577 ++NumDAGIselRetries; 2578 while (1) { 2579 if (MatchScopes.empty()) { 2580 CannotYetSelect(NodeToMatch); 2581 return 0; 2582 } 2583 2584 // Restore the interpreter state back to the point where the scope was 2585 // formed. 2586 MatchScope &LastScope = MatchScopes.back(); 2587 RecordedNodes.resize(LastScope.NumRecordedNodes); 2588 NodeStack.clear(); 2589 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2590 N = NodeStack.back(); 2591 2592 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2593 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2594 MatcherIndex = LastScope.FailIndex; 2595 2596 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2597 2598 InputChain = LastScope.InputChain; 2599 InputFlag = LastScope.InputFlag; 2600 if (!LastScope.HasChainNodesMatched) 2601 ChainNodesMatched.clear(); 2602 if (!LastScope.HasFlagResultNodesMatched) 2603 FlagResultNodesMatched.clear(); 2604 2605 // Check to see what the offset is at the new MatcherIndex. If it is zero 2606 // we have reached the end of this scope, otherwise we have another child 2607 // in the current scope to try. 2608 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2609 if (NumToSkip & 128) 2610 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2611 2612 // If we have another child in this scope to match, update FailIndex and 2613 // try it. 2614 if (NumToSkip != 0) { 2615 LastScope.FailIndex = MatcherIndex+NumToSkip; 2616 break; 2617 } 2618 2619 // End of this scope, pop it and try the next child in the containing 2620 // scope. 2621 MatchScopes.pop_back(); 2622 } 2623 } 2624} 2625 2626 2627 2628void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2629 std::string msg; 2630 raw_string_ostream Msg(msg); 2631 Msg << "Cannot yet select: "; 2632 2633 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2634 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2635 N->getOpcode() != ISD::INTRINSIC_VOID) { 2636 N->printrFull(Msg, CurDAG); 2637 } else { 2638 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2639 unsigned iid = 2640 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2641 if (iid < Intrinsic::num_intrinsics) 2642 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2643 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2644 Msg << "target intrinsic %" << TII->getName(iid); 2645 else 2646 Msg << "unknown intrinsic #" << iid; 2647 } 2648 report_fatal_error(Msg.str()); 2649} 2650 2651char SelectionDAGISel::ID = 0; 2652