SelectionDAGISel.cpp revision 50d2b1ac029d63500ea9b9347561b1454fa6ed6a
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/CodeGen/FastISel.h" 29#include "llvm/CodeGen/GCStrategy.h" 30#include "llvm/CodeGen/GCMetadata.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetIntrinsicInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/Compiler.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/Timer.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/ADT/Statistic.h" 50#include <algorithm> 51using namespace llvm; 52 53STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 54STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 55 56static cl::opt<bool> 57EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 58 cl::desc("Enable verbose messages in the \"fast\" " 59 "instruction selector")); 60static cl::opt<bool> 61EnableFastISelAbort("fast-isel-abort", cl::Hidden, 62 cl::desc("Enable abort calls when \"fast\" instruction fails")); 63 64#ifndef NDEBUG 65static cl::opt<bool> 66ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 67 cl::desc("Pop up a window to show dags before the first " 68 "dag combine pass")); 69static cl::opt<bool> 70ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 71 cl::desc("Pop up a window to show dags before legalize types")); 72static cl::opt<bool> 73ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 74 cl::desc("Pop up a window to show dags before legalize")); 75static cl::opt<bool> 76ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the second " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before the post legalize types" 82 " dag combine pass")); 83static cl::opt<bool> 84ViewISelDAGs("view-isel-dags", cl::Hidden, 85 cl::desc("Pop up a window to show isel dags as they are selected")); 86static cl::opt<bool> 87ViewSchedDAGs("view-sched-dags", cl::Hidden, 88 cl::desc("Pop up a window to show sched dags as they are processed")); 89static cl::opt<bool> 90ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 91 cl::desc("Pop up a window to show SUnit dags after they are processed")); 92#else 93static const bool ViewDAGCombine1 = false, 94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 95 ViewDAGCombine2 = false, 96 ViewDAGCombineLT = false, 97 ViewISelDAGs = false, ViewSchedDAGs = false, 98 ViewSUnitDAGs = false; 99#endif 100 101//===---------------------------------------------------------------------===// 102/// 103/// RegisterScheduler class - Track the registration of instruction schedulers. 104/// 105//===---------------------------------------------------------------------===// 106MachinePassRegistry RegisterScheduler::Registry; 107 108//===---------------------------------------------------------------------===// 109/// 110/// ISHeuristic command line option for instruction schedulers. 111/// 112//===---------------------------------------------------------------------===// 113static cl::opt<RegisterScheduler::FunctionPassCtor, false, 114 RegisterPassParser<RegisterScheduler> > 115ISHeuristic("pre-RA-sched", 116 cl::init(&createDefaultScheduler), 117 cl::desc("Instruction schedulers available (before register" 118 " allocation):")); 119 120static RegisterScheduler 121defaultListDAGScheduler("default", "Best scheduler for the target", 122 createDefaultScheduler); 123 124namespace llvm { 125 //===--------------------------------------------------------------------===// 126 /// createDefaultScheduler - This creates an instruction scheduler appropriate 127 /// for the target. 128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 129 CodeGenOpt::Level OptLevel) { 130 const TargetLowering &TLI = IS->getTargetLowering(); 131 132 if (OptLevel == CodeGenOpt::None) 133 return createFastDAGScheduler(IS, OptLevel); 134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 135 return createTDListDAGScheduler(IS, OptLevel); 136 assert(TLI.getSchedulingPreference() == 137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 138 return createBURRListDAGScheduler(IS, OptLevel); 139 } 140} 141 142// EmitInstrWithCustomInserter - This method should be implemented by targets 143// that mark instructions with the 'usesCustomInserter' flag. These 144// instructions are special in various ways, which require special support to 145// insert. The specified MachineInstr is created but not inserted into any 146// basic blocks, and this method is called to expand it into a sequence of 147// instructions, potentially also creating new basic blocks and control flow. 148// When new basic blocks are inserted and the edges from MBB to its successors 149// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 150// DenseMap. 151MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 152 MachineBasicBlock *MBB, 153 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 154#ifndef NDEBUG 155 dbgs() << "If a target marks an instruction with " 156 "'usesCustomInserter', it must implement " 157 "TargetLowering::EmitInstrWithCustomInserter!"; 158#endif 159 llvm_unreachable(0); 160 return 0; 161} 162 163//===----------------------------------------------------------------------===// 164// SelectionDAGISel code 165//===----------------------------------------------------------------------===// 166 167SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 169 FuncInfo(new FunctionLoweringInfo(TLI)), 170 CurDAG(new SelectionDAG(tm, *FuncInfo)), 171 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 172 GFI(), 173 OptLevel(OL), 174 DAGSize(0) 175{} 176 177SelectionDAGISel::~SelectionDAGISel() { 178 delete SDB; 179 delete CurDAG; 180 delete FuncInfo; 181} 182 183void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 184 AU.addRequired<AliasAnalysis>(); 185 AU.addPreserved<AliasAnalysis>(); 186 AU.addRequired<GCModuleInfo>(); 187 AU.addPreserved<GCModuleInfo>(); 188 MachineFunctionPass::getAnalysisUsage(AU); 189} 190 191bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 192 // Do some sanity-checking on the command-line options. 193 assert((!EnableFastISelVerbose || EnableFastISel) && 194 "-fast-isel-verbose requires -fast-isel"); 195 assert((!EnableFastISelAbort || EnableFastISel) && 196 "-fast-isel-abort requires -fast-isel"); 197 198 const Function &Fn = *mf.getFunction(); 199 const TargetInstrInfo &TII = *TM.getInstrInfo(); 200 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 201 202 MF = &mf; 203 RegInfo = &MF->getRegInfo(); 204 AA = &getAnalysis<AliasAnalysis>(); 205 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 206 207 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 208 209 CurDAG->init(*MF); 210 FuncInfo->set(Fn, *MF, EnableFastISel); 211 SDB->init(GFI, *AA); 212 213 SelectAllBasicBlocks(Fn); 214 215 // Release function-specific state. SDB and CurDAG are already cleared 216 // at this point. 217 FuncInfo->clear(); 218 219 // If the first basic block in the function has live ins that need to be 220 // copied into vregs, emit the copies into the top of the block before 221 // emitting the code for the block. 222 RegInfo->EmitLiveInCopies(MF->begin(), TRI, TII); 223 224 return true; 225} 226 227/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 228/// attached with this instruction. 229static void SetDebugLoc(const Instruction *I, SelectionDAGBuilder *SDB, 230 FastISel *FastIS, MachineFunction *MF) { 231 DebugLoc DL = I->getDebugLoc(); 232 if (DL.isUnknown()) return; 233 234 SDB->setCurDebugLoc(DL); 235 236 if (FastIS) 237 FastIS->setCurDebugLoc(DL); 238 239 // If the function doesn't have a default debug location yet, set 240 // it. This is a total hack. 241 if (MF->getDefaultDebugLoc().isUnknown()) 242 MF->setDefaultDebugLoc(DL); 243} 244 245/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 246static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 247 SDB->setCurDebugLoc(DebugLoc()); 248 if (FastIS) 249 FastIS->setCurDebugLoc(DebugLoc()); 250} 251 252void SelectionDAGISel::SelectBasicBlock(const BasicBlock *LLVMBB, 253 BasicBlock::const_iterator Begin, 254 BasicBlock::const_iterator End, 255 bool &HadTailCall) { 256 SDB->setCurrentBasicBlock(BB); 257 258 // Lower all of the non-terminator instructions. If a call is emitted 259 // as a tail call, cease emitting nodes for this block. Terminators 260 // are handled below. 261 for (BasicBlock::const_iterator I = Begin; 262 I != End && !SDB->HasTailCall && !isa<TerminatorInst>(I); 263 ++I) { 264 SetDebugLoc(I, SDB, 0, MF); 265 SDB->visit(*I); 266 ResetDebugLoc(SDB, 0); 267 } 268 269 if (!SDB->HasTailCall) { 270 // Ensure that all instructions which are used outside of their defining 271 // blocks are available as virtual registers. Invoke is handled elsewhere. 272 for (BasicBlock::const_iterator I = Begin; I != End; ++I) 273 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 274 SDB->CopyToExportRegsIfNeeded(I); 275 276 // Handle PHI nodes in successor blocks. 277 if (End == LLVMBB->end()) { 278 HandlePHINodesInSuccessorBlocks(LLVMBB); 279 280 // Lower the terminator after the copies are emitted. 281 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF); 282 SDB->visit(*LLVMBB->getTerminator()); 283 ResetDebugLoc(SDB, 0); 284 } 285 } 286 287 // Make sure the root of the DAG is up-to-date. 288 CurDAG->setRoot(SDB->getControlRoot()); 289 290 // Final step, emit the lowered DAG as machine code. 291 CodeGenAndEmitDAG(); 292 HadTailCall = SDB->HasTailCall; 293 SDB->clear(); 294} 295 296namespace { 297/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 298/// nodes from the worklist. 299class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 300 SmallVector<SDNode*, 128> &Worklist; 301 SmallPtrSet<SDNode*, 128> &InWorklist; 302public: 303 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 304 SmallPtrSet<SDNode*, 128> &inwl) 305 : Worklist(wl), InWorklist(inwl) {} 306 307 void RemoveFromWorklist(SDNode *N) { 308 if (!InWorklist.erase(N)) return; 309 310 SmallVector<SDNode*, 128>::iterator I = 311 std::find(Worklist.begin(), Worklist.end(), N); 312 assert(I != Worklist.end() && "Not in worklist"); 313 314 *I = Worklist.back(); 315 Worklist.pop_back(); 316 } 317 318 virtual void NodeDeleted(SDNode *N, SDNode *E) { 319 RemoveFromWorklist(N); 320 } 321 322 virtual void NodeUpdated(SDNode *N) { 323 // Ignore updates. 324 } 325}; 326} 327 328/// TrivialTruncElim - Eliminate some trivial nops that can result from 329/// ShrinkDemandedOps: (trunc (ext n)) -> n. 330static bool TrivialTruncElim(SDValue Op, 331 TargetLowering::TargetLoweringOpt &TLO) { 332 SDValue N0 = Op.getOperand(0); 333 EVT VT = Op.getValueType(); 334 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 335 N0.getOpcode() == ISD::SIGN_EXTEND || 336 N0.getOpcode() == ISD::ANY_EXTEND) && 337 N0.getOperand(0).getValueType() == VT) { 338 return TLO.CombineTo(Op, N0.getOperand(0)); 339 } 340 return false; 341} 342 343/// ShrinkDemandedOps - A late transformation pass that shrink expressions 344/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 345/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 346void SelectionDAGISel::ShrinkDemandedOps() { 347 SmallVector<SDNode*, 128> Worklist; 348 SmallPtrSet<SDNode*, 128> InWorklist; 349 350 // Add all the dag nodes to the worklist. 351 Worklist.reserve(CurDAG->allnodes_size()); 352 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 353 E = CurDAG->allnodes_end(); I != E; ++I) { 354 Worklist.push_back(I); 355 InWorklist.insert(I); 356 } 357 358 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true); 359 while (!Worklist.empty()) { 360 SDNode *N = Worklist.pop_back_val(); 361 InWorklist.erase(N); 362 363 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 364 // Deleting this node may make its operands dead, add them to the worklist 365 // if they aren't already there. 366 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 367 if (InWorklist.insert(N->getOperand(i).getNode())) 368 Worklist.push_back(N->getOperand(i).getNode()); 369 370 CurDAG->DeleteNode(N); 371 continue; 372 } 373 374 // Run ShrinkDemandedOp on scalar binary operations. 375 if (N->getNumValues() != 1 || 376 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 377 continue; 378 379 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 380 APInt Demanded = APInt::getAllOnesValue(BitWidth); 381 APInt KnownZero, KnownOne; 382 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 383 KnownZero, KnownOne, TLO) && 384 (N->getOpcode() != ISD::TRUNCATE || 385 !TrivialTruncElim(SDValue(N, 0), TLO))) 386 continue; 387 388 // Revisit the node. 389 assert(!InWorklist.count(N) && "Already in worklist"); 390 Worklist.push_back(N); 391 InWorklist.insert(N); 392 393 // Replace the old value with the new one. 394 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 395 TLO.Old.getNode()->dump(CurDAG); 396 errs() << "\nWith: "; 397 TLO.New.getNode()->dump(CurDAG); 398 errs() << '\n'); 399 400 if (InWorklist.insert(TLO.New.getNode())) 401 Worklist.push_back(TLO.New.getNode()); 402 403 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 404 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 405 406 if (!TLO.Old.getNode()->use_empty()) continue; 407 408 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 409 i != e; ++i) { 410 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 411 if (OpNode->hasOneUse()) { 412 // Add OpNode to the end of the list to revisit. 413 DeadNodes.RemoveFromWorklist(OpNode); 414 Worklist.push_back(OpNode); 415 InWorklist.insert(OpNode); 416 } 417 } 418 419 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 420 CurDAG->DeleteNode(TLO.Old.getNode()); 421 } 422} 423 424void SelectionDAGISel::ComputeLiveOutVRegInfo() { 425 SmallPtrSet<SDNode*, 128> VisitedNodes; 426 SmallVector<SDNode*, 128> Worklist; 427 428 Worklist.push_back(CurDAG->getRoot().getNode()); 429 430 APInt Mask; 431 APInt KnownZero; 432 APInt KnownOne; 433 434 do { 435 SDNode *N = Worklist.pop_back_val(); 436 437 // If we've already seen this node, ignore it. 438 if (!VisitedNodes.insert(N)) 439 continue; 440 441 // Otherwise, add all chain operands to the worklist. 442 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 443 if (N->getOperand(i).getValueType() == MVT::Other) 444 Worklist.push_back(N->getOperand(i).getNode()); 445 446 // If this is a CopyToReg with a vreg dest, process it. 447 if (N->getOpcode() != ISD::CopyToReg) 448 continue; 449 450 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 451 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 452 continue; 453 454 // Ignore non-scalar or non-integer values. 455 SDValue Src = N->getOperand(2); 456 EVT SrcVT = Src.getValueType(); 457 if (!SrcVT.isInteger() || SrcVT.isVector()) 458 continue; 459 460 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 461 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 462 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 463 464 // Only install this information if it tells us something. 465 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 466 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 467 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 468 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 469 FunctionLoweringInfo::LiveOutInfo &LOI = 470 FuncInfo->LiveOutRegInfo[DestReg]; 471 LOI.NumSignBits = NumSignBits; 472 LOI.KnownOne = KnownOne; 473 LOI.KnownZero = KnownZero; 474 } 475 } while (!Worklist.empty()); 476} 477 478void SelectionDAGISel::CodeGenAndEmitDAG() { 479 std::string GroupName; 480 if (TimePassesIsEnabled) 481 GroupName = "Instruction Selection and Scheduling"; 482 std::string BlockName; 483 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 484 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 485 ViewSUnitDAGs) 486 BlockName = MF->getFunction()->getNameStr() + ":" + 487 BB->getBasicBlock()->getNameStr(); 488 489 DEBUG(dbgs() << "Initial selection DAG:\n"); 490 DEBUG(CurDAG->dump()); 491 492 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 493 494 // Run the DAG combiner in pre-legalize mode. 495 if (TimePassesIsEnabled) { 496 NamedRegionTimer T("DAG Combining 1", GroupName); 497 CurDAG->Combine(Unrestricted, *AA, OptLevel); 498 } else { 499 CurDAG->Combine(Unrestricted, *AA, OptLevel); 500 } 501 502 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 503 DEBUG(CurDAG->dump()); 504 505 // Second step, hack on the DAG until it only uses operations and types that 506 // the target supports. 507 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 508 BlockName); 509 510 bool Changed; 511 if (TimePassesIsEnabled) { 512 NamedRegionTimer T("Type Legalization", GroupName); 513 Changed = CurDAG->LegalizeTypes(); 514 } else { 515 Changed = CurDAG->LegalizeTypes(); 516 } 517 518 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 519 DEBUG(CurDAG->dump()); 520 521 if (Changed) { 522 if (ViewDAGCombineLT) 523 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 524 525 // Run the DAG combiner in post-type-legalize mode. 526 if (TimePassesIsEnabled) { 527 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 528 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 529 } else { 530 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 531 } 532 533 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 534 DEBUG(CurDAG->dump()); 535 } 536 537 if (TimePassesIsEnabled) { 538 NamedRegionTimer T("Vector Legalization", GroupName); 539 Changed = CurDAG->LegalizeVectors(); 540 } else { 541 Changed = CurDAG->LegalizeVectors(); 542 } 543 544 if (Changed) { 545 if (TimePassesIsEnabled) { 546 NamedRegionTimer T("Type Legalization 2", GroupName); 547 CurDAG->LegalizeTypes(); 548 } else { 549 CurDAG->LegalizeTypes(); 550 } 551 552 if (ViewDAGCombineLT) 553 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 554 555 // Run the DAG combiner in post-type-legalize mode. 556 if (TimePassesIsEnabled) { 557 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 558 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 559 } else { 560 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 561 } 562 563 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 564 DEBUG(CurDAG->dump()); 565 } 566 567 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 568 569 if (TimePassesIsEnabled) { 570 NamedRegionTimer T("DAG Legalization", GroupName); 571 CurDAG->Legalize(OptLevel); 572 } else { 573 CurDAG->Legalize(OptLevel); 574 } 575 576 DEBUG(dbgs() << "Legalized selection DAG:\n"); 577 DEBUG(CurDAG->dump()); 578 579 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 580 581 // Run the DAG combiner in post-legalize mode. 582 if (TimePassesIsEnabled) { 583 NamedRegionTimer T("DAG Combining 2", GroupName); 584 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 585 } else { 586 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 587 } 588 589 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 590 DEBUG(CurDAG->dump()); 591 592 if (OptLevel != CodeGenOpt::None) { 593 ShrinkDemandedOps(); 594 ComputeLiveOutVRegInfo(); 595 } 596 597 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 598 599 // Third, instruction select all of the operations to machine code, adding the 600 // code to the MachineBasicBlock. 601 if (TimePassesIsEnabled) { 602 NamedRegionTimer T("Instruction Selection", GroupName); 603 DoInstructionSelection(); 604 } else { 605 DoInstructionSelection(); 606 } 607 608 DEBUG(dbgs() << "Selected selection DAG:\n"); 609 DEBUG(CurDAG->dump()); 610 611 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 612 613 // Schedule machine code. 614 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 615 if (TimePassesIsEnabled) { 616 NamedRegionTimer T("Instruction Scheduling", GroupName); 617 Scheduler->Run(CurDAG, BB, BB->end()); 618 } else { 619 Scheduler->Run(CurDAG, BB, BB->end()); 620 } 621 622 if (ViewSUnitDAGs) Scheduler->viewGraph(); 623 624 // Emit machine code to BB. This can change 'BB' to the last block being 625 // inserted into. 626 if (TimePassesIsEnabled) { 627 NamedRegionTimer T("Instruction Creation", GroupName); 628 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 629 } else { 630 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 631 } 632 633 // Free the scheduler state. 634 if (TimePassesIsEnabled) { 635 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 636 delete Scheduler; 637 } else { 638 delete Scheduler; 639 } 640 641 DEBUG(dbgs() << "Selected machine code:\n"); 642 DEBUG(BB->dump()); 643} 644 645void SelectionDAGISel::DoInstructionSelection() { 646 DEBUG(errs() << "===== Instruction selection begins:\n"); 647 648 PreprocessISelDAG(); 649 650 // Select target instructions for the DAG. 651 { 652 // Number all nodes with a topological order and set DAGSize. 653 DAGSize = CurDAG->AssignTopologicalOrder(); 654 655 // Create a dummy node (which is not added to allnodes), that adds 656 // a reference to the root node, preventing it from being deleted, 657 // and tracking any changes of the root. 658 HandleSDNode Dummy(CurDAG->getRoot()); 659 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 660 ++ISelPosition; 661 662 // The AllNodes list is now topological-sorted. Visit the 663 // nodes by starting at the end of the list (the root of the 664 // graph) and preceding back toward the beginning (the entry 665 // node). 666 while (ISelPosition != CurDAG->allnodes_begin()) { 667 SDNode *Node = --ISelPosition; 668 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 669 // but there are currently some corner cases that it misses. Also, this 670 // makes it theoretically possible to disable the DAGCombiner. 671 if (Node->use_empty()) 672 continue; 673 674 SDNode *ResNode = Select(Node); 675 676 // FIXME: This is pretty gross. 'Select' should be changed to not return 677 // anything at all and this code should be nuked with a tactical strike. 678 679 // If node should not be replaced, continue with the next one. 680 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 681 continue; 682 // Replace node. 683 if (ResNode) 684 ReplaceUses(Node, ResNode); 685 686 // If after the replacement this node is not used any more, 687 // remove this dead node. 688 if (Node->use_empty()) { // Don't delete EntryToken, etc. 689 ISelUpdater ISU(ISelPosition); 690 CurDAG->RemoveDeadNode(Node, &ISU); 691 } 692 } 693 694 CurDAG->setRoot(Dummy.getValue()); 695 } 696 DEBUG(errs() << "===== Instruction selection ends:\n"); 697 698 PostprocessISelDAG(); 699} 700 701/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 702/// do other setup for EH landing-pad blocks. 703void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) { 704 // Add a label to mark the beginning of the landing pad. Deletion of the 705 // landing pad can thus be detected via the MachineModuleInfo. 706 MCSymbol *Label = MF->getMMI().addLandingPad(BB); 707 708 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 709 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 710 711 // Mark exception register as live in. 712 unsigned Reg = TLI.getExceptionAddressRegister(); 713 if (Reg) BB->addLiveIn(Reg); 714 715 // Mark exception selector register as live in. 716 Reg = TLI.getExceptionSelectorRegister(); 717 if (Reg) BB->addLiveIn(Reg); 718 719 // FIXME: Hack around an exception handling flaw (PR1508): the personality 720 // function and list of typeids logically belong to the invoke (or, if you 721 // like, the basic block containing the invoke), and need to be associated 722 // with it in the dwarf exception handling tables. Currently however the 723 // information is provided by an intrinsic (eh.selector) that can be moved 724 // to unexpected places by the optimizers: if the unwind edge is critical, 725 // then breaking it can result in the intrinsics being in the successor of 726 // the landing pad, not the landing pad itself. This results 727 // in exceptions not being caught because no typeids are associated with 728 // the invoke. This may not be the only way things can go wrong, but it 729 // is the only way we try to work around for the moment. 730 const BasicBlock *LLVMBB = BB->getBasicBlock(); 731 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 732 733 if (Br && Br->isUnconditional()) { // Critical edge? 734 BasicBlock::const_iterator I, E; 735 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 736 if (isa<EHSelectorInst>(I)) 737 break; 738 739 if (I == E) 740 // No catch info found - try to extract some from the successor. 741 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 742 } 743} 744 745void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 746 // Initialize the Fast-ISel state, if needed. 747 FastISel *FastIS = 0; 748 if (EnableFastISel) 749 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 750 FuncInfo->StaticAllocaMap 751#ifndef NDEBUG 752 , FuncInfo->CatchInfoLost 753#endif 754 ); 755 756 // Iterate over all basic blocks in the function. 757 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 758 const BasicBlock *LLVMBB = &*I; 759 BB = FuncInfo->MBBMap[LLVMBB]; 760 761 BasicBlock::const_iterator const Begin = LLVMBB->begin(); 762 BasicBlock::const_iterator const End = LLVMBB->end(); 763 BasicBlock::const_iterator BI = Begin; 764 765 // Lower any arguments needed in this block if this is the entry block. 766 bool SuppressFastISel = false; 767 if (LLVMBB == &Fn.getEntryBlock()) { 768 LowerArguments(LLVMBB); 769 770 // If any of the arguments has the byval attribute, forgo 771 // fast-isel in the entry block. 772 if (FastIS) { 773 unsigned j = 1; 774 for (Function::const_arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 775 I != E; ++I, ++j) 776 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 777 if (EnableFastISelVerbose || EnableFastISelAbort) 778 dbgs() << "FastISel skips entry block due to byval argument\n"; 779 SuppressFastISel = true; 780 break; 781 } 782 } 783 } 784 785 // Setup an EH landing-pad block. 786 if (BB->isLandingPad()) 787 PrepareEHLandingPad(BB); 788 789 // Before doing SelectionDAG ISel, see if FastISel has been requested. 790 if (FastIS && !SuppressFastISel) { 791 // Emit code for any incoming arguments. This must happen before 792 // beginning FastISel on the entry block. 793 if (LLVMBB == &Fn.getEntryBlock()) { 794 CurDAG->setRoot(SDB->getControlRoot()); 795 CodeGenAndEmitDAG(); 796 SDB->clear(); 797 } 798 FastIS->startNewBlock(BB); 799 // Do FastISel on as many instructions as possible. 800 for (; BI != End; ++BI) { 801 // Just before the terminator instruction, insert instructions to 802 // feed PHI nodes in successor blocks. 803 if (isa<TerminatorInst>(BI)) 804 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 805 ++NumFastIselFailures; 806 ResetDebugLoc(SDB, FastIS); 807 if (EnableFastISelVerbose || EnableFastISelAbort) { 808 dbgs() << "FastISel miss: "; 809 BI->dump(); 810 } 811 assert(!EnableFastISelAbort && 812 "FastISel didn't handle a PHI in a successor"); 813 break; 814 } 815 816 SetDebugLoc(BI, SDB, FastIS, MF); 817 818 // Try to select the instruction with FastISel. 819 if (FastIS->SelectInstruction(BI)) { 820 ResetDebugLoc(SDB, FastIS); 821 continue; 822 } 823 824 // Clear out the debug location so that it doesn't carry over to 825 // unrelated instructions. 826 ResetDebugLoc(SDB, FastIS); 827 828 // Then handle certain instructions as single-LLVM-Instruction blocks. 829 if (isa<CallInst>(BI)) { 830 ++NumFastIselFailures; 831 if (EnableFastISelVerbose || EnableFastISelAbort) { 832 dbgs() << "FastISel missed call: "; 833 BI->dump(); 834 } 835 836 if (!BI->getType()->isVoidTy() && !BI->use_empty()) { 837 unsigned &R = FuncInfo->ValueMap[BI]; 838 if (!R) 839 R = FuncInfo->CreateRegForValue(BI); 840 } 841 842 bool HadTailCall = false; 843 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 844 845 // If the call was emitted as a tail call, we're done with the block. 846 if (HadTailCall) { 847 BI = End; 848 break; 849 } 850 851 // If the instruction was codegen'd with multiple blocks, 852 // inform the FastISel object where to resume inserting. 853 FastIS->setCurrentBlock(BB); 854 continue; 855 } 856 857 // Otherwise, give up on FastISel for the rest of the block. 858 // For now, be a little lenient about non-branch terminators. 859 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 860 ++NumFastIselFailures; 861 if (EnableFastISelVerbose || EnableFastISelAbort) { 862 dbgs() << "FastISel miss: "; 863 BI->dump(); 864 } 865 if (EnableFastISelAbort) 866 // The "fast" selector couldn't handle something and bailed. 867 // For the purpose of debugging, just abort. 868 llvm_unreachable("FastISel didn't select the entire block"); 869 } 870 break; 871 } 872 } 873 874 // Run SelectionDAG instruction selection on the remainder of the block 875 // not handled by FastISel. If FastISel is not run, this is the entire 876 // block. 877 if (BI != End) { 878 bool HadTailCall; 879 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 880 } 881 882 FinishBasicBlock(); 883 } 884 885 delete FastIS; 886} 887 888void 889SelectionDAGISel::FinishBasicBlock() { 890 891 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 892 DEBUG(BB->dump()); 893 894 DEBUG(dbgs() << "Total amount of phi nodes to update: " 895 << SDB->PHINodesToUpdate.size() << "\n"); 896 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 897 dbgs() << "Node " << i << " : (" 898 << SDB->PHINodesToUpdate[i].first 899 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 900 901 // Next, now that we know what the last MBB the LLVM BB expanded is, update 902 // PHI nodes in successors. 903 if (SDB->SwitchCases.empty() && 904 SDB->JTCases.empty() && 905 SDB->BitTestCases.empty()) { 906 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 907 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 908 assert(PHI->isPHI() && 909 "This is not a machine PHI node that we are updating!"); 910 if (!BB->isSuccessor(PHI->getParent())) 911 continue; 912 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 913 false)); 914 PHI->addOperand(MachineOperand::CreateMBB(BB)); 915 } 916 SDB->PHINodesToUpdate.clear(); 917 return; 918 } 919 920 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 921 // Lower header first, if it wasn't already lowered 922 if (!SDB->BitTestCases[i].Emitted) { 923 // Set the current basic block to the mbb we wish to insert the code into 924 BB = SDB->BitTestCases[i].Parent; 925 SDB->setCurrentBasicBlock(BB); 926 // Emit the code 927 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 928 CurDAG->setRoot(SDB->getRoot()); 929 CodeGenAndEmitDAG(); 930 SDB->clear(); 931 } 932 933 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 934 // Set the current basic block to the mbb we wish to insert the code into 935 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 936 SDB->setCurrentBasicBlock(BB); 937 // Emit the code 938 if (j+1 != ej) 939 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 940 SDB->BitTestCases[i].Reg, 941 SDB->BitTestCases[i].Cases[j]); 942 else 943 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 944 SDB->BitTestCases[i].Reg, 945 SDB->BitTestCases[i].Cases[j]); 946 947 948 CurDAG->setRoot(SDB->getRoot()); 949 CodeGenAndEmitDAG(); 950 SDB->clear(); 951 } 952 953 // Update PHI Nodes 954 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 955 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 956 MachineBasicBlock *PHIBB = PHI->getParent(); 957 assert(PHI->isPHI() && 958 "This is not a machine PHI node that we are updating!"); 959 // This is "default" BB. We have two jumps to it. From "header" BB and 960 // from last "case" BB. 961 if (PHIBB == SDB->BitTestCases[i].Default) { 962 PHI->addOperand(MachineOperand:: 963 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 964 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 965 PHI->addOperand(MachineOperand:: 966 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 967 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 968 back().ThisBB)); 969 } 970 // One of "cases" BB. 971 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 972 j != ej; ++j) { 973 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 974 if (cBB->isSuccessor(PHIBB)) { 975 PHI->addOperand(MachineOperand:: 976 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 977 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 978 } 979 } 980 } 981 } 982 SDB->BitTestCases.clear(); 983 984 // If the JumpTable record is filled in, then we need to emit a jump table. 985 // Updating the PHI nodes is tricky in this case, since we need to determine 986 // whether the PHI is a successor of the range check MBB or the jump table MBB 987 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 988 // Lower header first, if it wasn't already lowered 989 if (!SDB->JTCases[i].first.Emitted) { 990 // Set the current basic block to the mbb we wish to insert the code into 991 BB = SDB->JTCases[i].first.HeaderBB; 992 SDB->setCurrentBasicBlock(BB); 993 // Emit the code 994 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 995 CurDAG->setRoot(SDB->getRoot()); 996 CodeGenAndEmitDAG(); 997 SDB->clear(); 998 } 999 1000 // Set the current basic block to the mbb we wish to insert the code into 1001 BB = SDB->JTCases[i].second.MBB; 1002 SDB->setCurrentBasicBlock(BB); 1003 // Emit the code 1004 SDB->visitJumpTable(SDB->JTCases[i].second); 1005 CurDAG->setRoot(SDB->getRoot()); 1006 CodeGenAndEmitDAG(); 1007 SDB->clear(); 1008 1009 // Update PHI Nodes 1010 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1011 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1012 MachineBasicBlock *PHIBB = PHI->getParent(); 1013 assert(PHI->isPHI() && 1014 "This is not a machine PHI node that we are updating!"); 1015 // "default" BB. We can go there only from header BB. 1016 if (PHIBB == SDB->JTCases[i].second.Default) { 1017 PHI->addOperand 1018 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1019 PHI->addOperand 1020 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1021 } 1022 // JT BB. Just iterate over successors here 1023 if (BB->isSuccessor(PHIBB)) { 1024 PHI->addOperand 1025 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1026 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1027 } 1028 } 1029 } 1030 SDB->JTCases.clear(); 1031 1032 // If the switch block involved a branch to one of the actual successors, we 1033 // need to update PHI nodes in that block. 1034 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1035 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1036 assert(PHI->isPHI() && 1037 "This is not a machine PHI node that we are updating!"); 1038 if (BB->isSuccessor(PHI->getParent())) { 1039 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1040 false)); 1041 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1042 } 1043 } 1044 1045 // If we generated any switch lowering information, build and codegen any 1046 // additional DAGs necessary. 1047 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1048 // Set the current basic block to the mbb we wish to insert the code into 1049 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1050 SDB->setCurrentBasicBlock(BB); 1051 1052 // Emit the code 1053 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1054 CurDAG->setRoot(SDB->getRoot()); 1055 CodeGenAndEmitDAG(); 1056 1057 // Handle any PHI nodes in successors of this chunk, as if we were coming 1058 // from the original BB before switch expansion. Note that PHI nodes can 1059 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1060 // handle them the right number of times. 1061 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1062 // If new BB's are created during scheduling, the edges may have been 1063 // updated. That is, the edge from ThisBB to BB may have been split and 1064 // BB's predecessor is now another block. 1065 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1066 SDB->EdgeMapping.find(BB); 1067 if (EI != SDB->EdgeMapping.end()) 1068 ThisBB = EI->second; 1069 1070 // BB may have been removed from the CFG if a branch was constant folded. 1071 if (ThisBB->isSuccessor(BB)) { 1072 for (MachineBasicBlock::iterator Phi = BB->begin(); 1073 Phi != BB->end() && Phi->isPHI(); 1074 ++Phi) { 1075 // This value for this PHI node is recorded in PHINodesToUpdate. 1076 for (unsigned pn = 0; ; ++pn) { 1077 assert(pn != SDB->PHINodesToUpdate.size() && 1078 "Didn't find PHI entry!"); 1079 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1080 Phi->addOperand(MachineOperand:: 1081 CreateReg(SDB->PHINodesToUpdate[pn].second, 1082 false)); 1083 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1084 break; 1085 } 1086 } 1087 } 1088 } 1089 1090 // Don't process RHS if same block as LHS. 1091 if (BB == SDB->SwitchCases[i].FalseBB) 1092 SDB->SwitchCases[i].FalseBB = 0; 1093 1094 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1095 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1096 SDB->SwitchCases[i].FalseBB = 0; 1097 } 1098 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1099 SDB->clear(); 1100 } 1101 SDB->SwitchCases.clear(); 1102 1103 SDB->PHINodesToUpdate.clear(); 1104} 1105 1106 1107/// Create the scheduler. If a specific scheduler was specified 1108/// via the SchedulerRegistry, use it, otherwise select the 1109/// one preferred by the target. 1110/// 1111ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1112 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1113 1114 if (!Ctor) { 1115 Ctor = ISHeuristic; 1116 RegisterScheduler::setDefault(Ctor); 1117 } 1118 1119 return Ctor(this, OptLevel); 1120} 1121 1122ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1123 return new ScheduleHazardRecognizer(); 1124} 1125 1126//===----------------------------------------------------------------------===// 1127// Helper functions used by the generated instruction selector. 1128//===----------------------------------------------------------------------===// 1129// Calls to these methods are generated by tblgen. 1130 1131/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1132/// the dag combiner simplified the 255, we still want to match. RHS is the 1133/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1134/// specified in the .td file (e.g. 255). 1135bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1136 int64_t DesiredMaskS) const { 1137 const APInt &ActualMask = RHS->getAPIntValue(); 1138 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1139 1140 // If the actual mask exactly matches, success! 1141 if (ActualMask == DesiredMask) 1142 return true; 1143 1144 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1145 if (ActualMask.intersects(~DesiredMask)) 1146 return false; 1147 1148 // Otherwise, the DAG Combiner may have proven that the value coming in is 1149 // either already zero or is not demanded. Check for known zero input bits. 1150 APInt NeededMask = DesiredMask & ~ActualMask; 1151 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1152 return true; 1153 1154 // TODO: check to see if missing bits are just not demanded. 1155 1156 // Otherwise, this pattern doesn't match. 1157 return false; 1158} 1159 1160/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1161/// the dag combiner simplified the 255, we still want to match. RHS is the 1162/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1163/// specified in the .td file (e.g. 255). 1164bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1165 int64_t DesiredMaskS) const { 1166 const APInt &ActualMask = RHS->getAPIntValue(); 1167 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1168 1169 // If the actual mask exactly matches, success! 1170 if (ActualMask == DesiredMask) 1171 return true; 1172 1173 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1174 if (ActualMask.intersects(~DesiredMask)) 1175 return false; 1176 1177 // Otherwise, the DAG Combiner may have proven that the value coming in is 1178 // either already zero or is not demanded. Check for known zero input bits. 1179 APInt NeededMask = DesiredMask & ~ActualMask; 1180 1181 APInt KnownZero, KnownOne; 1182 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1183 1184 // If all the missing bits in the or are already known to be set, match! 1185 if ((NeededMask & KnownOne) == NeededMask) 1186 return true; 1187 1188 // TODO: check to see if missing bits are just not demanded. 1189 1190 // Otherwise, this pattern doesn't match. 1191 return false; 1192} 1193 1194 1195/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1196/// by tblgen. Others should not call it. 1197void SelectionDAGISel:: 1198SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1199 std::vector<SDValue> InOps; 1200 std::swap(InOps, Ops); 1201 1202 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1203 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1204 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1205 1206 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1207 if (InOps[e-1].getValueType() == MVT::Flag) 1208 --e; // Don't process a flag operand if it is here. 1209 1210 while (i != e) { 1211 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1212 if (!InlineAsm::isMemKind(Flags)) { 1213 // Just skip over this operand, copying the operands verbatim. 1214 Ops.insert(Ops.end(), InOps.begin()+i, 1215 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1216 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1217 } else { 1218 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1219 "Memory operand with multiple values?"); 1220 // Otherwise, this is a memory operand. Ask the target to select it. 1221 std::vector<SDValue> SelOps; 1222 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1223 report_fatal_error("Could not match memory address. Inline asm" 1224 " failure!"); 1225 1226 // Add this to the output node. 1227 unsigned NewFlags = 1228 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1229 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1230 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1231 i += 2; 1232 } 1233 } 1234 1235 // Add the flag input back if present. 1236 if (e != InOps.size()) 1237 Ops.push_back(InOps.back()); 1238} 1239 1240/// findFlagUse - Return use of EVT::Flag value produced by the specified 1241/// SDNode. 1242/// 1243static SDNode *findFlagUse(SDNode *N) { 1244 unsigned FlagResNo = N->getNumValues()-1; 1245 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1246 SDUse &Use = I.getUse(); 1247 if (Use.getResNo() == FlagResNo) 1248 return Use.getUser(); 1249 } 1250 return NULL; 1251} 1252 1253/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1254/// This function recursively traverses up the operand chain, ignoring 1255/// certain nodes. 1256static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1257 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1258 bool IgnoreChains) { 1259 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1260 // greater than all of its (recursive) operands. If we scan to a point where 1261 // 'use' is smaller than the node we're scanning for, then we know we will 1262 // never find it. 1263 // 1264 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1265 // happen because we scan down to newly selected nodes in the case of flag 1266 // uses. 1267 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1268 return false; 1269 1270 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1271 // won't fail if we scan it again. 1272 if (!Visited.insert(Use)) 1273 return false; 1274 1275 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1276 // Ignore chain uses, they are validated by HandleMergeInputChains. 1277 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1278 continue; 1279 1280 SDNode *N = Use->getOperand(i).getNode(); 1281 if (N == Def) { 1282 if (Use == ImmedUse || Use == Root) 1283 continue; // We are not looking for immediate use. 1284 assert(N != Root); 1285 return true; 1286 } 1287 1288 // Traverse up the operand chain. 1289 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1290 return true; 1291 } 1292 return false; 1293} 1294 1295/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1296/// operand node N of U during instruction selection that starts at Root. 1297bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1298 SDNode *Root) const { 1299 if (OptLevel == CodeGenOpt::None) return false; 1300 return N.hasOneUse(); 1301} 1302 1303/// IsLegalToFold - Returns true if the specific operand node N of 1304/// U can be folded during instruction selection that starts at Root. 1305bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1306 CodeGenOpt::Level OptLevel, 1307 bool IgnoreChains) { 1308 if (OptLevel == CodeGenOpt::None) return false; 1309 1310 // If Root use can somehow reach N through a path that that doesn't contain 1311 // U then folding N would create a cycle. e.g. In the following 1312 // diagram, Root can reach N through X. If N is folded into into Root, then 1313 // X is both a predecessor and a successor of U. 1314 // 1315 // [N*] // 1316 // ^ ^ // 1317 // / \ // 1318 // [U*] [X]? // 1319 // ^ ^ // 1320 // \ / // 1321 // \ / // 1322 // [Root*] // 1323 // 1324 // * indicates nodes to be folded together. 1325 // 1326 // If Root produces a flag, then it gets (even more) interesting. Since it 1327 // will be "glued" together with its flag use in the scheduler, we need to 1328 // check if it might reach N. 1329 // 1330 // [N*] // 1331 // ^ ^ // 1332 // / \ // 1333 // [U*] [X]? // 1334 // ^ ^ // 1335 // \ \ // 1336 // \ | // 1337 // [Root*] | // 1338 // ^ | // 1339 // f | // 1340 // | / // 1341 // [Y] / // 1342 // ^ / // 1343 // f / // 1344 // | / // 1345 // [FU] // 1346 // 1347 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1348 // (call it Fold), then X is a predecessor of FU and a successor of 1349 // Fold. But since Fold and FU are flagged together, this will create 1350 // a cycle in the scheduling graph. 1351 1352 // If the node has flags, walk down the graph to the "lowest" node in the 1353 // flagged set. 1354 EVT VT = Root->getValueType(Root->getNumValues()-1); 1355 while (VT == MVT::Flag) { 1356 SDNode *FU = findFlagUse(Root); 1357 if (FU == NULL) 1358 break; 1359 Root = FU; 1360 VT = Root->getValueType(Root->getNumValues()-1); 1361 1362 // If our query node has a flag result with a use, we've walked up it. If 1363 // the user (which has already been selected) has a chain or indirectly uses 1364 // the chain, our WalkChainUsers predicate will not consider it. Because of 1365 // this, we cannot ignore chains in this predicate. 1366 IgnoreChains = false; 1367 } 1368 1369 1370 SmallPtrSet<SDNode*, 16> Visited; 1371 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1372} 1373 1374SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1375 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1376 SelectInlineAsmMemoryOperands(Ops); 1377 1378 std::vector<EVT> VTs; 1379 VTs.push_back(MVT::Other); 1380 VTs.push_back(MVT::Flag); 1381 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1382 VTs, &Ops[0], Ops.size()); 1383 New->setNodeId(-1); 1384 return New.getNode(); 1385} 1386 1387SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1388 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1389} 1390 1391/// GetVBR - decode a vbr encoding whose top bit is set. 1392ALWAYS_INLINE static uint64_t 1393GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1394 assert(Val >= 128 && "Not a VBR"); 1395 Val &= 127; // Remove first vbr bit. 1396 1397 unsigned Shift = 7; 1398 uint64_t NextBits; 1399 do { 1400 NextBits = MatcherTable[Idx++]; 1401 Val |= (NextBits&127) << Shift; 1402 Shift += 7; 1403 } while (NextBits & 128); 1404 1405 return Val; 1406} 1407 1408 1409/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1410/// interior flag and chain results to use the new flag and chain results. 1411void SelectionDAGISel:: 1412UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1413 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1414 SDValue InputFlag, 1415 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1416 bool isMorphNodeTo) { 1417 SmallVector<SDNode*, 4> NowDeadNodes; 1418 1419 ISelUpdater ISU(ISelPosition); 1420 1421 // Now that all the normal results are replaced, we replace the chain and 1422 // flag results if present. 1423 if (!ChainNodesMatched.empty()) { 1424 assert(InputChain.getNode() != 0 && 1425 "Matched input chains but didn't produce a chain"); 1426 // Loop over all of the nodes we matched that produced a chain result. 1427 // Replace all the chain results with the final chain we ended up with. 1428 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1429 SDNode *ChainNode = ChainNodesMatched[i]; 1430 1431 // If this node was already deleted, don't look at it. 1432 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1433 continue; 1434 1435 // Don't replace the results of the root node if we're doing a 1436 // MorphNodeTo. 1437 if (ChainNode == NodeToMatch && isMorphNodeTo) 1438 continue; 1439 1440 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1441 if (ChainVal.getValueType() == MVT::Flag) 1442 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1443 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1444 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1445 1446 // If the node became dead and we haven't already seen it, delete it. 1447 if (ChainNode->use_empty() && 1448 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1449 NowDeadNodes.push_back(ChainNode); 1450 } 1451 } 1452 1453 // If the result produces a flag, update any flag results in the matched 1454 // pattern with the flag result. 1455 if (InputFlag.getNode() != 0) { 1456 // Handle any interior nodes explicitly marked. 1457 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1458 SDNode *FRN = FlagResultNodesMatched[i]; 1459 1460 // If this node was already deleted, don't look at it. 1461 if (FRN->getOpcode() == ISD::DELETED_NODE) 1462 continue; 1463 1464 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1465 "Doesn't have a flag result"); 1466 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1467 InputFlag, &ISU); 1468 1469 // If the node became dead and we haven't already seen it, delete it. 1470 if (FRN->use_empty() && 1471 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1472 NowDeadNodes.push_back(FRN); 1473 } 1474 } 1475 1476 if (!NowDeadNodes.empty()) 1477 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1478 1479 DEBUG(errs() << "ISEL: Match complete!\n"); 1480} 1481 1482enum ChainResult { 1483 CR_Simple, 1484 CR_InducesCycle, 1485 CR_LeadsToInteriorNode 1486}; 1487 1488/// WalkChainUsers - Walk down the users of the specified chained node that is 1489/// part of the pattern we're matching, looking at all of the users we find. 1490/// This determines whether something is an interior node, whether we have a 1491/// non-pattern node in between two pattern nodes (which prevent folding because 1492/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1493/// between pattern nodes (in which case the TF becomes part of the pattern). 1494/// 1495/// The walk we do here is guaranteed to be small because we quickly get down to 1496/// already selected nodes "below" us. 1497static ChainResult 1498WalkChainUsers(SDNode *ChainedNode, 1499 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1500 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1501 ChainResult Result = CR_Simple; 1502 1503 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1504 E = ChainedNode->use_end(); UI != E; ++UI) { 1505 // Make sure the use is of the chain, not some other value we produce. 1506 if (UI.getUse().getValueType() != MVT::Other) continue; 1507 1508 SDNode *User = *UI; 1509 1510 // If we see an already-selected machine node, then we've gone beyond the 1511 // pattern that we're selecting down into the already selected chunk of the 1512 // DAG. 1513 if (User->isMachineOpcode() || 1514 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1515 continue; 1516 1517 if (User->getOpcode() == ISD::CopyToReg || 1518 User->getOpcode() == ISD::CopyFromReg || 1519 User->getOpcode() == ISD::INLINEASM || 1520 User->getOpcode() == ISD::EH_LABEL) { 1521 // If their node ID got reset to -1 then they've already been selected. 1522 // Treat them like a MachineOpcode. 1523 if (User->getNodeId() == -1) 1524 continue; 1525 } 1526 1527 // If we have a TokenFactor, we handle it specially. 1528 if (User->getOpcode() != ISD::TokenFactor) { 1529 // If the node isn't a token factor and isn't part of our pattern, then it 1530 // must be a random chained node in between two nodes we're selecting. 1531 // This happens when we have something like: 1532 // x = load ptr 1533 // call 1534 // y = x+4 1535 // store y -> ptr 1536 // Because we structurally match the load/store as a read/modify/write, 1537 // but the call is chained between them. We cannot fold in this case 1538 // because it would induce a cycle in the graph. 1539 if (!std::count(ChainedNodesInPattern.begin(), 1540 ChainedNodesInPattern.end(), User)) 1541 return CR_InducesCycle; 1542 1543 // Otherwise we found a node that is part of our pattern. For example in: 1544 // x = load ptr 1545 // y = x+4 1546 // store y -> ptr 1547 // This would happen when we're scanning down from the load and see the 1548 // store as a user. Record that there is a use of ChainedNode that is 1549 // part of the pattern and keep scanning uses. 1550 Result = CR_LeadsToInteriorNode; 1551 InteriorChainedNodes.push_back(User); 1552 continue; 1553 } 1554 1555 // If we found a TokenFactor, there are two cases to consider: first if the 1556 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1557 // uses of the TF are in our pattern) we just want to ignore it. Second, 1558 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1559 // [Load chain] 1560 // ^ 1561 // | 1562 // [Load] 1563 // ^ ^ 1564 // | \ DAG's like cheese 1565 // / \ do you? 1566 // / | 1567 // [TokenFactor] [Op] 1568 // ^ ^ 1569 // | | 1570 // \ / 1571 // \ / 1572 // [Store] 1573 // 1574 // In this case, the TokenFactor becomes part of our match and we rewrite it 1575 // as a new TokenFactor. 1576 // 1577 // To distinguish these two cases, do a recursive walk down the uses. 1578 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1579 case CR_Simple: 1580 // If the uses of the TokenFactor are just already-selected nodes, ignore 1581 // it, it is "below" our pattern. 1582 continue; 1583 case CR_InducesCycle: 1584 // If the uses of the TokenFactor lead to nodes that are not part of our 1585 // pattern that are not selected, folding would turn this into a cycle, 1586 // bail out now. 1587 return CR_InducesCycle; 1588 case CR_LeadsToInteriorNode: 1589 break; // Otherwise, keep processing. 1590 } 1591 1592 // Okay, we know we're in the interesting interior case. The TokenFactor 1593 // is now going to be considered part of the pattern so that we rewrite its 1594 // uses (it may have uses that are not part of the pattern) with the 1595 // ultimate chain result of the generated code. We will also add its chain 1596 // inputs as inputs to the ultimate TokenFactor we create. 1597 Result = CR_LeadsToInteriorNode; 1598 ChainedNodesInPattern.push_back(User); 1599 InteriorChainedNodes.push_back(User); 1600 continue; 1601 } 1602 1603 return Result; 1604} 1605 1606/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1607/// operation for when the pattern matched at least one node with a chains. The 1608/// input vector contains a list of all of the chained nodes that we match. We 1609/// must determine if this is a valid thing to cover (i.e. matching it won't 1610/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1611/// be used as the input node chain for the generated nodes. 1612static SDValue 1613HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1614 SelectionDAG *CurDAG) { 1615 // Walk all of the chained nodes we've matched, recursively scanning down the 1616 // users of the chain result. This adds any TokenFactor nodes that are caught 1617 // in between chained nodes to the chained and interior nodes list. 1618 SmallVector<SDNode*, 3> InteriorChainedNodes; 1619 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1620 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1621 InteriorChainedNodes) == CR_InducesCycle) 1622 return SDValue(); // Would induce a cycle. 1623 } 1624 1625 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1626 // that we are interested in. Form our input TokenFactor node. 1627 SmallVector<SDValue, 3> InputChains; 1628 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1629 // Add the input chain of this node to the InputChains list (which will be 1630 // the operands of the generated TokenFactor) if it's not an interior node. 1631 SDNode *N = ChainNodesMatched[i]; 1632 if (N->getOpcode() != ISD::TokenFactor) { 1633 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1634 continue; 1635 1636 // Otherwise, add the input chain. 1637 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1638 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1639 InputChains.push_back(InChain); 1640 continue; 1641 } 1642 1643 // If we have a token factor, we want to add all inputs of the token factor 1644 // that are not part of the pattern we're matching. 1645 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1646 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1647 N->getOperand(op).getNode())) 1648 InputChains.push_back(N->getOperand(op)); 1649 } 1650 } 1651 1652 SDValue Res; 1653 if (InputChains.size() == 1) 1654 return InputChains[0]; 1655 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1656 MVT::Other, &InputChains[0], InputChains.size()); 1657} 1658 1659/// MorphNode - Handle morphing a node in place for the selector. 1660SDNode *SelectionDAGISel:: 1661MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1662 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1663 // It is possible we're using MorphNodeTo to replace a node with no 1664 // normal results with one that has a normal result (or we could be 1665 // adding a chain) and the input could have flags and chains as well. 1666 // In this case we need to shift the operands down. 1667 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1668 // than the old isel though. 1669 int OldFlagResultNo = -1, OldChainResultNo = -1; 1670 1671 unsigned NTMNumResults = Node->getNumValues(); 1672 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1673 OldFlagResultNo = NTMNumResults-1; 1674 if (NTMNumResults != 1 && 1675 Node->getValueType(NTMNumResults-2) == MVT::Other) 1676 OldChainResultNo = NTMNumResults-2; 1677 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1678 OldChainResultNo = NTMNumResults-1; 1679 1680 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1681 // that this deletes operands of the old node that become dead. 1682 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1683 1684 // MorphNodeTo can operate in two ways: if an existing node with the 1685 // specified operands exists, it can just return it. Otherwise, it 1686 // updates the node in place to have the requested operands. 1687 if (Res == Node) { 1688 // If we updated the node in place, reset the node ID. To the isel, 1689 // this should be just like a newly allocated machine node. 1690 Res->setNodeId(-1); 1691 } 1692 1693 unsigned ResNumResults = Res->getNumValues(); 1694 // Move the flag if needed. 1695 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1696 (unsigned)OldFlagResultNo != ResNumResults-1) 1697 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1698 SDValue(Res, ResNumResults-1)); 1699 1700 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1701 --ResNumResults; 1702 1703 // Move the chain reference if needed. 1704 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1705 (unsigned)OldChainResultNo != ResNumResults-1) 1706 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1707 SDValue(Res, ResNumResults-1)); 1708 1709 // Otherwise, no replacement happened because the node already exists. Replace 1710 // Uses of the old node with the new one. 1711 if (Res != Node) 1712 CurDAG->ReplaceAllUsesWith(Node, Res); 1713 1714 return Res; 1715} 1716 1717/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1718ALWAYS_INLINE static bool 1719CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1720 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1721 // Accept if it is exactly the same as a previously recorded node. 1722 unsigned RecNo = MatcherTable[MatcherIndex++]; 1723 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1724 return N == RecordedNodes[RecNo]; 1725} 1726 1727/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1728ALWAYS_INLINE static bool 1729CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1730 SelectionDAGISel &SDISel) { 1731 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1732} 1733 1734/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1735ALWAYS_INLINE static bool 1736CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1737 SelectionDAGISel &SDISel, SDNode *N) { 1738 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1739} 1740 1741ALWAYS_INLINE static bool 1742CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1743 SDNode *N) { 1744 uint16_t Opc = MatcherTable[MatcherIndex++]; 1745 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1746 return N->getOpcode() == Opc; 1747} 1748 1749ALWAYS_INLINE static bool 1750CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1751 SDValue N, const TargetLowering &TLI) { 1752 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1753 if (N.getValueType() == VT) return true; 1754 1755 // Handle the case when VT is iPTR. 1756 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1757} 1758 1759ALWAYS_INLINE static bool 1760CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1761 SDValue N, const TargetLowering &TLI, 1762 unsigned ChildNo) { 1763 if (ChildNo >= N.getNumOperands()) 1764 return false; // Match fails if out of range child #. 1765 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1766} 1767 1768 1769ALWAYS_INLINE static bool 1770CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1771 SDValue N) { 1772 return cast<CondCodeSDNode>(N)->get() == 1773 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1774} 1775 1776ALWAYS_INLINE static bool 1777CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1778 SDValue N, const TargetLowering &TLI) { 1779 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1780 if (cast<VTSDNode>(N)->getVT() == VT) 1781 return true; 1782 1783 // Handle the case when VT is iPTR. 1784 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1785} 1786 1787ALWAYS_INLINE static bool 1788CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1789 SDValue N) { 1790 int64_t Val = MatcherTable[MatcherIndex++]; 1791 if (Val & 128) 1792 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1793 1794 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1795 return C != 0 && C->getSExtValue() == Val; 1796} 1797 1798ALWAYS_INLINE static bool 1799CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1800 SDValue N, SelectionDAGISel &SDISel) { 1801 int64_t Val = MatcherTable[MatcherIndex++]; 1802 if (Val & 128) 1803 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1804 1805 if (N->getOpcode() != ISD::AND) return false; 1806 1807 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1808 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1809} 1810 1811ALWAYS_INLINE static bool 1812CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1813 SDValue N, SelectionDAGISel &SDISel) { 1814 int64_t Val = MatcherTable[MatcherIndex++]; 1815 if (Val & 128) 1816 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1817 1818 if (N->getOpcode() != ISD::OR) return false; 1819 1820 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1821 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1822} 1823 1824/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1825/// scope, evaluate the current node. If the current predicate is known to 1826/// fail, set Result=true and return anything. If the current predicate is 1827/// known to pass, set Result=false and return the MatcherIndex to continue 1828/// with. If the current predicate is unknown, set Result=false and return the 1829/// MatcherIndex to continue with. 1830static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1831 unsigned Index, SDValue N, 1832 bool &Result, SelectionDAGISel &SDISel, 1833 SmallVectorImpl<SDValue> &RecordedNodes){ 1834 switch (Table[Index++]) { 1835 default: 1836 Result = false; 1837 return Index-1; // Could not evaluate this predicate. 1838 case SelectionDAGISel::OPC_CheckSame: 1839 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1840 return Index; 1841 case SelectionDAGISel::OPC_CheckPatternPredicate: 1842 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1843 return Index; 1844 case SelectionDAGISel::OPC_CheckPredicate: 1845 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1846 return Index; 1847 case SelectionDAGISel::OPC_CheckOpcode: 1848 Result = !::CheckOpcode(Table, Index, N.getNode()); 1849 return Index; 1850 case SelectionDAGISel::OPC_CheckType: 1851 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1852 return Index; 1853 case SelectionDAGISel::OPC_CheckChild0Type: 1854 case SelectionDAGISel::OPC_CheckChild1Type: 1855 case SelectionDAGISel::OPC_CheckChild2Type: 1856 case SelectionDAGISel::OPC_CheckChild3Type: 1857 case SelectionDAGISel::OPC_CheckChild4Type: 1858 case SelectionDAGISel::OPC_CheckChild5Type: 1859 case SelectionDAGISel::OPC_CheckChild6Type: 1860 case SelectionDAGISel::OPC_CheckChild7Type: 1861 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1862 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1863 return Index; 1864 case SelectionDAGISel::OPC_CheckCondCode: 1865 Result = !::CheckCondCode(Table, Index, N); 1866 return Index; 1867 case SelectionDAGISel::OPC_CheckValueType: 1868 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1869 return Index; 1870 case SelectionDAGISel::OPC_CheckInteger: 1871 Result = !::CheckInteger(Table, Index, N); 1872 return Index; 1873 case SelectionDAGISel::OPC_CheckAndImm: 1874 Result = !::CheckAndImm(Table, Index, N, SDISel); 1875 return Index; 1876 case SelectionDAGISel::OPC_CheckOrImm: 1877 Result = !::CheckOrImm(Table, Index, N, SDISel); 1878 return Index; 1879 } 1880} 1881 1882namespace { 1883 1884struct MatchScope { 1885 /// FailIndex - If this match fails, this is the index to continue with. 1886 unsigned FailIndex; 1887 1888 /// NodeStack - The node stack when the scope was formed. 1889 SmallVector<SDValue, 4> NodeStack; 1890 1891 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1892 unsigned NumRecordedNodes; 1893 1894 /// NumMatchedMemRefs - The number of matched memref entries. 1895 unsigned NumMatchedMemRefs; 1896 1897 /// InputChain/InputFlag - The current chain/flag 1898 SDValue InputChain, InputFlag; 1899 1900 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1901 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1902}; 1903 1904} 1905 1906SDNode *SelectionDAGISel:: 1907SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1908 unsigned TableSize) { 1909 // FIXME: Should these even be selected? Handle these cases in the caller? 1910 switch (NodeToMatch->getOpcode()) { 1911 default: 1912 break; 1913 case ISD::EntryToken: // These nodes remain the same. 1914 case ISD::BasicBlock: 1915 case ISD::Register: 1916 //case ISD::VALUETYPE: 1917 //case ISD::CONDCODE: 1918 case ISD::HANDLENODE: 1919 case ISD::MDNODE_SDNODE: 1920 case ISD::TargetConstant: 1921 case ISD::TargetConstantFP: 1922 case ISD::TargetConstantPool: 1923 case ISD::TargetFrameIndex: 1924 case ISD::TargetExternalSymbol: 1925 case ISD::TargetBlockAddress: 1926 case ISD::TargetJumpTable: 1927 case ISD::TargetGlobalTLSAddress: 1928 case ISD::TargetGlobalAddress: 1929 case ISD::TokenFactor: 1930 case ISD::CopyFromReg: 1931 case ISD::CopyToReg: 1932 case ISD::EH_LABEL: 1933 NodeToMatch->setNodeId(-1); // Mark selected. 1934 return 0; 1935 case ISD::AssertSext: 1936 case ISD::AssertZext: 1937 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1938 NodeToMatch->getOperand(0)); 1939 return 0; 1940 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1941 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1942 } 1943 1944 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1945 1946 // Set up the node stack with NodeToMatch as the only node on the stack. 1947 SmallVector<SDValue, 8> NodeStack; 1948 SDValue N = SDValue(NodeToMatch, 0); 1949 NodeStack.push_back(N); 1950 1951 // MatchScopes - Scopes used when matching, if a match failure happens, this 1952 // indicates where to continue checking. 1953 SmallVector<MatchScope, 8> MatchScopes; 1954 1955 // RecordedNodes - This is the set of nodes that have been recorded by the 1956 // state machine. 1957 SmallVector<SDValue, 8> RecordedNodes; 1958 1959 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1960 // pattern. 1961 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1962 1963 // These are the current input chain and flag for use when generating nodes. 1964 // Various Emit operations change these. For example, emitting a copytoreg 1965 // uses and updates these. 1966 SDValue InputChain, InputFlag; 1967 1968 // ChainNodesMatched - If a pattern matches nodes that have input/output 1969 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1970 // which ones they are. The result is captured into this list so that we can 1971 // update the chain results when the pattern is complete. 1972 SmallVector<SDNode*, 3> ChainNodesMatched; 1973 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1974 1975 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1976 NodeToMatch->dump(CurDAG); 1977 errs() << '\n'); 1978 1979 // Determine where to start the interpreter. Normally we start at opcode #0, 1980 // but if the state machine starts with an OPC_SwitchOpcode, then we 1981 // accelerate the first lookup (which is guaranteed to be hot) with the 1982 // OpcodeOffset table. 1983 unsigned MatcherIndex = 0; 1984 1985 if (!OpcodeOffset.empty()) { 1986 // Already computed the OpcodeOffset table, just index into it. 1987 if (N.getOpcode() < OpcodeOffset.size()) 1988 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1989 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1990 1991 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1992 // Otherwise, the table isn't computed, but the state machine does start 1993 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1994 // is the first time we're selecting an instruction. 1995 unsigned Idx = 1; 1996 while (1) { 1997 // Get the size of this case. 1998 unsigned CaseSize = MatcherTable[Idx++]; 1999 if (CaseSize & 128) 2000 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2001 if (CaseSize == 0) break; 2002 2003 // Get the opcode, add the index to the table. 2004 uint16_t Opc = MatcherTable[Idx++]; 2005 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2006 if (Opc >= OpcodeOffset.size()) 2007 OpcodeOffset.resize((Opc+1)*2); 2008 OpcodeOffset[Opc] = Idx; 2009 Idx += CaseSize; 2010 } 2011 2012 // Okay, do the lookup for the first opcode. 2013 if (N.getOpcode() < OpcodeOffset.size()) 2014 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2015 } 2016 2017 while (1) { 2018 assert(MatcherIndex < TableSize && "Invalid index"); 2019#ifndef NDEBUG 2020 unsigned CurrentOpcodeIndex = MatcherIndex; 2021#endif 2022 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2023 switch (Opcode) { 2024 case OPC_Scope: { 2025 // Okay, the semantics of this operation are that we should push a scope 2026 // then evaluate the first child. However, pushing a scope only to have 2027 // the first check fail (which then pops it) is inefficient. If we can 2028 // determine immediately that the first check (or first several) will 2029 // immediately fail, don't even bother pushing a scope for them. 2030 unsigned FailIndex; 2031 2032 while (1) { 2033 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2034 if (NumToSkip & 128) 2035 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2036 // Found the end of the scope with no match. 2037 if (NumToSkip == 0) { 2038 FailIndex = 0; 2039 break; 2040 } 2041 2042 FailIndex = MatcherIndex+NumToSkip; 2043 2044 unsigned MatcherIndexOfPredicate = MatcherIndex; 2045 (void)MatcherIndexOfPredicate; // silence warning. 2046 2047 // If we can't evaluate this predicate without pushing a scope (e.g. if 2048 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2049 // push the scope and evaluate the full predicate chain. 2050 bool Result; 2051 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2052 Result, *this, RecordedNodes); 2053 if (!Result) 2054 break; 2055 2056 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2057 << "index " << MatcherIndexOfPredicate 2058 << ", continuing at " << FailIndex << "\n"); 2059 ++NumDAGIselRetries; 2060 2061 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2062 // move to the next case. 2063 MatcherIndex = FailIndex; 2064 } 2065 2066 // If the whole scope failed to match, bail. 2067 if (FailIndex == 0) break; 2068 2069 // Push a MatchScope which indicates where to go if the first child fails 2070 // to match. 2071 MatchScope NewEntry; 2072 NewEntry.FailIndex = FailIndex; 2073 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2074 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2075 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2076 NewEntry.InputChain = InputChain; 2077 NewEntry.InputFlag = InputFlag; 2078 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2079 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2080 MatchScopes.push_back(NewEntry); 2081 continue; 2082 } 2083 case OPC_RecordNode: 2084 // Remember this node, it may end up being an operand in the pattern. 2085 RecordedNodes.push_back(N); 2086 continue; 2087 2088 case OPC_RecordChild0: case OPC_RecordChild1: 2089 case OPC_RecordChild2: case OPC_RecordChild3: 2090 case OPC_RecordChild4: case OPC_RecordChild5: 2091 case OPC_RecordChild6: case OPC_RecordChild7: { 2092 unsigned ChildNo = Opcode-OPC_RecordChild0; 2093 if (ChildNo >= N.getNumOperands()) 2094 break; // Match fails if out of range child #. 2095 2096 RecordedNodes.push_back(N->getOperand(ChildNo)); 2097 continue; 2098 } 2099 case OPC_RecordMemRef: 2100 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2101 continue; 2102 2103 case OPC_CaptureFlagInput: 2104 // If the current node has an input flag, capture it in InputFlag. 2105 if (N->getNumOperands() != 0 && 2106 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2107 InputFlag = N->getOperand(N->getNumOperands()-1); 2108 continue; 2109 2110 case OPC_MoveChild: { 2111 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2112 if (ChildNo >= N.getNumOperands()) 2113 break; // Match fails if out of range child #. 2114 N = N.getOperand(ChildNo); 2115 NodeStack.push_back(N); 2116 continue; 2117 } 2118 2119 case OPC_MoveParent: 2120 // Pop the current node off the NodeStack. 2121 NodeStack.pop_back(); 2122 assert(!NodeStack.empty() && "Node stack imbalance!"); 2123 N = NodeStack.back(); 2124 continue; 2125 2126 case OPC_CheckSame: 2127 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2128 continue; 2129 case OPC_CheckPatternPredicate: 2130 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2131 continue; 2132 case OPC_CheckPredicate: 2133 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2134 N.getNode())) 2135 break; 2136 continue; 2137 case OPC_CheckComplexPat: { 2138 unsigned CPNum = MatcherTable[MatcherIndex++]; 2139 unsigned RecNo = MatcherTable[MatcherIndex++]; 2140 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2141 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2142 RecordedNodes)) 2143 break; 2144 continue; 2145 } 2146 case OPC_CheckOpcode: 2147 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2148 continue; 2149 2150 case OPC_CheckType: 2151 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2152 continue; 2153 2154 case OPC_SwitchOpcode: { 2155 unsigned CurNodeOpcode = N.getOpcode(); 2156 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2157 unsigned CaseSize; 2158 while (1) { 2159 // Get the size of this case. 2160 CaseSize = MatcherTable[MatcherIndex++]; 2161 if (CaseSize & 128) 2162 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2163 if (CaseSize == 0) break; 2164 2165 uint16_t Opc = MatcherTable[MatcherIndex++]; 2166 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2167 2168 // If the opcode matches, then we will execute this case. 2169 if (CurNodeOpcode == Opc) 2170 break; 2171 2172 // Otherwise, skip over this case. 2173 MatcherIndex += CaseSize; 2174 } 2175 2176 // If no cases matched, bail out. 2177 if (CaseSize == 0) break; 2178 2179 // Otherwise, execute the case we found. 2180 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2181 << " to " << MatcherIndex << "\n"); 2182 continue; 2183 } 2184 2185 case OPC_SwitchType: { 2186 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2187 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2188 unsigned CaseSize; 2189 while (1) { 2190 // Get the size of this case. 2191 CaseSize = MatcherTable[MatcherIndex++]; 2192 if (CaseSize & 128) 2193 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2194 if (CaseSize == 0) break; 2195 2196 MVT::SimpleValueType CaseVT = 2197 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2198 if (CaseVT == MVT::iPTR) 2199 CaseVT = TLI.getPointerTy().SimpleTy; 2200 2201 // If the VT matches, then we will execute this case. 2202 if (CurNodeVT == CaseVT) 2203 break; 2204 2205 // Otherwise, skip over this case. 2206 MatcherIndex += CaseSize; 2207 } 2208 2209 // If no cases matched, bail out. 2210 if (CaseSize == 0) break; 2211 2212 // Otherwise, execute the case we found. 2213 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2214 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2215 continue; 2216 } 2217 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2218 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2219 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2220 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2221 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2222 Opcode-OPC_CheckChild0Type)) 2223 break; 2224 continue; 2225 case OPC_CheckCondCode: 2226 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2227 continue; 2228 case OPC_CheckValueType: 2229 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2230 continue; 2231 case OPC_CheckInteger: 2232 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2233 continue; 2234 case OPC_CheckAndImm: 2235 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2236 continue; 2237 case OPC_CheckOrImm: 2238 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2239 continue; 2240 2241 case OPC_CheckFoldableChainNode: { 2242 assert(NodeStack.size() != 1 && "No parent node"); 2243 // Verify that all intermediate nodes between the root and this one have 2244 // a single use. 2245 bool HasMultipleUses = false; 2246 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2247 if (!NodeStack[i].hasOneUse()) { 2248 HasMultipleUses = true; 2249 break; 2250 } 2251 if (HasMultipleUses) break; 2252 2253 // Check to see that the target thinks this is profitable to fold and that 2254 // we can fold it without inducing cycles in the graph. 2255 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2256 NodeToMatch) || 2257 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2258 NodeToMatch, OptLevel, 2259 true/*We validate our own chains*/)) 2260 break; 2261 2262 continue; 2263 } 2264 case OPC_EmitInteger: { 2265 MVT::SimpleValueType VT = 2266 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2267 int64_t Val = MatcherTable[MatcherIndex++]; 2268 if (Val & 128) 2269 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2270 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2271 continue; 2272 } 2273 case OPC_EmitRegister: { 2274 MVT::SimpleValueType VT = 2275 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2276 unsigned RegNo = MatcherTable[MatcherIndex++]; 2277 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2278 continue; 2279 } 2280 2281 case OPC_EmitConvertToTarget: { 2282 // Convert from IMM/FPIMM to target version. 2283 unsigned RecNo = MatcherTable[MatcherIndex++]; 2284 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2285 SDValue Imm = RecordedNodes[RecNo]; 2286 2287 if (Imm->getOpcode() == ISD::Constant) { 2288 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2289 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2290 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2291 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2292 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2293 } 2294 2295 RecordedNodes.push_back(Imm); 2296 continue; 2297 } 2298 2299 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2300 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2301 // These are space-optimized forms of OPC_EmitMergeInputChains. 2302 assert(InputChain.getNode() == 0 && 2303 "EmitMergeInputChains should be the first chain producing node"); 2304 assert(ChainNodesMatched.empty() && 2305 "Should only have one EmitMergeInputChains per match"); 2306 2307 // Read all of the chained nodes. 2308 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2309 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2310 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2311 2312 // FIXME: What if other value results of the node have uses not matched 2313 // by this pattern? 2314 if (ChainNodesMatched.back() != NodeToMatch && 2315 !RecordedNodes[RecNo].hasOneUse()) { 2316 ChainNodesMatched.clear(); 2317 break; 2318 } 2319 2320 // Merge the input chains if they are not intra-pattern references. 2321 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2322 2323 if (InputChain.getNode() == 0) 2324 break; // Failed to merge. 2325 continue; 2326 } 2327 2328 case OPC_EmitMergeInputChains: { 2329 assert(InputChain.getNode() == 0 && 2330 "EmitMergeInputChains should be the first chain producing node"); 2331 // This node gets a list of nodes we matched in the input that have 2332 // chains. We want to token factor all of the input chains to these nodes 2333 // together. However, if any of the input chains is actually one of the 2334 // nodes matched in this pattern, then we have an intra-match reference. 2335 // Ignore these because the newly token factored chain should not refer to 2336 // the old nodes. 2337 unsigned NumChains = MatcherTable[MatcherIndex++]; 2338 assert(NumChains != 0 && "Can't TF zero chains"); 2339 2340 assert(ChainNodesMatched.empty() && 2341 "Should only have one EmitMergeInputChains per match"); 2342 2343 // Read all of the chained nodes. 2344 for (unsigned i = 0; i != NumChains; ++i) { 2345 unsigned RecNo = MatcherTable[MatcherIndex++]; 2346 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2347 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2348 2349 // FIXME: What if other value results of the node have uses not matched 2350 // by this pattern? 2351 if (ChainNodesMatched.back() != NodeToMatch && 2352 !RecordedNodes[RecNo].hasOneUse()) { 2353 ChainNodesMatched.clear(); 2354 break; 2355 } 2356 } 2357 2358 // If the inner loop broke out, the match fails. 2359 if (ChainNodesMatched.empty()) 2360 break; 2361 2362 // Merge the input chains if they are not intra-pattern references. 2363 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2364 2365 if (InputChain.getNode() == 0) 2366 break; // Failed to merge. 2367 2368 continue; 2369 } 2370 2371 case OPC_EmitCopyToReg: { 2372 unsigned RecNo = MatcherTable[MatcherIndex++]; 2373 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2374 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2375 2376 if (InputChain.getNode() == 0) 2377 InputChain = CurDAG->getEntryNode(); 2378 2379 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2380 DestPhysReg, RecordedNodes[RecNo], 2381 InputFlag); 2382 2383 InputFlag = InputChain.getValue(1); 2384 continue; 2385 } 2386 2387 case OPC_EmitNodeXForm: { 2388 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2389 unsigned RecNo = MatcherTable[MatcherIndex++]; 2390 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2391 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2392 continue; 2393 } 2394 2395 case OPC_EmitNode: 2396 case OPC_MorphNodeTo: { 2397 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2398 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2399 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2400 // Get the result VT list. 2401 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2402 SmallVector<EVT, 4> VTs; 2403 for (unsigned i = 0; i != NumVTs; ++i) { 2404 MVT::SimpleValueType VT = 2405 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2406 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2407 VTs.push_back(VT); 2408 } 2409 2410 if (EmitNodeInfo & OPFL_Chain) 2411 VTs.push_back(MVT::Other); 2412 if (EmitNodeInfo & OPFL_FlagOutput) 2413 VTs.push_back(MVT::Flag); 2414 2415 // This is hot code, so optimize the two most common cases of 1 and 2 2416 // results. 2417 SDVTList VTList; 2418 if (VTs.size() == 1) 2419 VTList = CurDAG->getVTList(VTs[0]); 2420 else if (VTs.size() == 2) 2421 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2422 else 2423 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2424 2425 // Get the operand list. 2426 unsigned NumOps = MatcherTable[MatcherIndex++]; 2427 SmallVector<SDValue, 8> Ops; 2428 for (unsigned i = 0; i != NumOps; ++i) { 2429 unsigned RecNo = MatcherTable[MatcherIndex++]; 2430 if (RecNo & 128) 2431 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2432 2433 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2434 Ops.push_back(RecordedNodes[RecNo]); 2435 } 2436 2437 // If there are variadic operands to add, handle them now. 2438 if (EmitNodeInfo & OPFL_VariadicInfo) { 2439 // Determine the start index to copy from. 2440 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2441 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2442 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2443 "Invalid variadic node"); 2444 // Copy all of the variadic operands, not including a potential flag 2445 // input. 2446 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2447 i != e; ++i) { 2448 SDValue V = NodeToMatch->getOperand(i); 2449 if (V.getValueType() == MVT::Flag) break; 2450 Ops.push_back(V); 2451 } 2452 } 2453 2454 // If this has chain/flag inputs, add them. 2455 if (EmitNodeInfo & OPFL_Chain) 2456 Ops.push_back(InputChain); 2457 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2458 Ops.push_back(InputFlag); 2459 2460 // Create the node. 2461 SDNode *Res = 0; 2462 if (Opcode != OPC_MorphNodeTo) { 2463 // If this is a normal EmitNode command, just create the new node and 2464 // add the results to the RecordedNodes list. 2465 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2466 VTList, Ops.data(), Ops.size()); 2467 2468 // Add all the non-flag/non-chain results to the RecordedNodes list. 2469 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2470 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2471 RecordedNodes.push_back(SDValue(Res, i)); 2472 } 2473 2474 } else { 2475 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2476 EmitNodeInfo); 2477 } 2478 2479 // If the node had chain/flag results, update our notion of the current 2480 // chain and flag. 2481 if (EmitNodeInfo & OPFL_FlagOutput) { 2482 InputFlag = SDValue(Res, VTs.size()-1); 2483 if (EmitNodeInfo & OPFL_Chain) 2484 InputChain = SDValue(Res, VTs.size()-2); 2485 } else if (EmitNodeInfo & OPFL_Chain) 2486 InputChain = SDValue(Res, VTs.size()-1); 2487 2488 // If the OPFL_MemRefs flag is set on this node, slap all of the 2489 // accumulated memrefs onto it. 2490 // 2491 // FIXME: This is vastly incorrect for patterns with multiple outputs 2492 // instructions that access memory and for ComplexPatterns that match 2493 // loads. 2494 if (EmitNodeInfo & OPFL_MemRefs) { 2495 MachineSDNode::mmo_iterator MemRefs = 2496 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2497 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2498 cast<MachineSDNode>(Res) 2499 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2500 } 2501 2502 DEBUG(errs() << " " 2503 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2504 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2505 2506 // If this was a MorphNodeTo then we're completely done! 2507 if (Opcode == OPC_MorphNodeTo) { 2508 // Update chain and flag uses. 2509 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2510 InputFlag, FlagResultNodesMatched, true); 2511 return Res; 2512 } 2513 2514 continue; 2515 } 2516 2517 case OPC_MarkFlagResults: { 2518 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2519 2520 // Read and remember all the flag-result nodes. 2521 for (unsigned i = 0; i != NumNodes; ++i) { 2522 unsigned RecNo = MatcherTable[MatcherIndex++]; 2523 if (RecNo & 128) 2524 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2525 2526 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2527 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2528 } 2529 continue; 2530 } 2531 2532 case OPC_CompleteMatch: { 2533 // The match has been completed, and any new nodes (if any) have been 2534 // created. Patch up references to the matched dag to use the newly 2535 // created nodes. 2536 unsigned NumResults = MatcherTable[MatcherIndex++]; 2537 2538 for (unsigned i = 0; i != NumResults; ++i) { 2539 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2540 if (ResSlot & 128) 2541 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2542 2543 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2544 SDValue Res = RecordedNodes[ResSlot]; 2545 2546 assert(i < NodeToMatch->getNumValues() && 2547 NodeToMatch->getValueType(i) != MVT::Other && 2548 NodeToMatch->getValueType(i) != MVT::Flag && 2549 "Invalid number of results to complete!"); 2550 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2551 NodeToMatch->getValueType(i) == MVT::iPTR || 2552 Res.getValueType() == MVT::iPTR || 2553 NodeToMatch->getValueType(i).getSizeInBits() == 2554 Res.getValueType().getSizeInBits()) && 2555 "invalid replacement"); 2556 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2557 } 2558 2559 // If the root node defines a flag, add it to the flag nodes to update 2560 // list. 2561 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2562 FlagResultNodesMatched.push_back(NodeToMatch); 2563 2564 // Update chain and flag uses. 2565 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2566 InputFlag, FlagResultNodesMatched, false); 2567 2568 assert(NodeToMatch->use_empty() && 2569 "Didn't replace all uses of the node?"); 2570 2571 // FIXME: We just return here, which interacts correctly with SelectRoot 2572 // above. We should fix this to not return an SDNode* anymore. 2573 return 0; 2574 } 2575 } 2576 2577 // If the code reached this point, then the match failed. See if there is 2578 // another child to try in the current 'Scope', otherwise pop it until we 2579 // find a case to check. 2580 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2581 ++NumDAGIselRetries; 2582 while (1) { 2583 if (MatchScopes.empty()) { 2584 CannotYetSelect(NodeToMatch); 2585 return 0; 2586 } 2587 2588 // Restore the interpreter state back to the point where the scope was 2589 // formed. 2590 MatchScope &LastScope = MatchScopes.back(); 2591 RecordedNodes.resize(LastScope.NumRecordedNodes); 2592 NodeStack.clear(); 2593 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2594 N = NodeStack.back(); 2595 2596 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2597 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2598 MatcherIndex = LastScope.FailIndex; 2599 2600 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2601 2602 InputChain = LastScope.InputChain; 2603 InputFlag = LastScope.InputFlag; 2604 if (!LastScope.HasChainNodesMatched) 2605 ChainNodesMatched.clear(); 2606 if (!LastScope.HasFlagResultNodesMatched) 2607 FlagResultNodesMatched.clear(); 2608 2609 // Check to see what the offset is at the new MatcherIndex. If it is zero 2610 // we have reached the end of this scope, otherwise we have another child 2611 // in the current scope to try. 2612 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2613 if (NumToSkip & 128) 2614 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2615 2616 // If we have another child in this scope to match, update FailIndex and 2617 // try it. 2618 if (NumToSkip != 0) { 2619 LastScope.FailIndex = MatcherIndex+NumToSkip; 2620 break; 2621 } 2622 2623 // End of this scope, pop it and try the next child in the containing 2624 // scope. 2625 MatchScopes.pop_back(); 2626 } 2627 } 2628} 2629 2630 2631 2632void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2633 std::string msg; 2634 raw_string_ostream Msg(msg); 2635 Msg << "Cannot yet select: "; 2636 2637 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2638 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2639 N->getOpcode() != ISD::INTRINSIC_VOID) { 2640 N->printrFull(Msg, CurDAG); 2641 } else { 2642 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2643 unsigned iid = 2644 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2645 if (iid < Intrinsic::num_intrinsics) 2646 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2647 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2648 Msg << "target intrinsic %" << TII->getName(iid); 2649 else 2650 Msg << "unknown intrinsic #" << iid; 2651 } 2652 report_fatal_error(Msg.str()); 2653} 2654 2655char SelectionDAGISel::ID = 0; 2656