SelectionDAGISel.cpp revision 532dc2e1f2473b16b48566c1cbc9eefe94a4e58e
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/MachineModuleInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/CodeGen/SSARegMap.h" 37#include "llvm/Target/MRegisterInfo.h" 38#include "llvm/Target/TargetData.h" 39#include "llvm/Target/TargetFrameInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Compiler.h" 47#include <algorithm> 48using namespace llvm; 49 50#ifndef NDEBUG 51static cl::opt<bool> 52ViewISelDAGs("view-isel-dags", cl::Hidden, 53 cl::desc("Pop up a window to show isel dags as they are selected")); 54static cl::opt<bool> 55ViewSchedDAGs("view-sched-dags", cl::Hidden, 56 cl::desc("Pop up a window to show sched dags as they are processed")); 57#else 58static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0; 59#endif 60 61//===---------------------------------------------------------------------===// 62/// 63/// RegisterScheduler class - Track the registration of instruction schedulers. 64/// 65//===---------------------------------------------------------------------===// 66MachinePassRegistry RegisterScheduler::Registry; 67 68//===---------------------------------------------------------------------===// 69/// 70/// ISHeuristic command line option for instruction schedulers. 71/// 72//===---------------------------------------------------------------------===// 73namespace { 74 cl::opt<RegisterScheduler::FunctionPassCtor, false, 75 RegisterPassParser<RegisterScheduler> > 76 ISHeuristic("sched", 77 cl::init(&createDefaultScheduler), 78 cl::desc("Instruction schedulers available:")); 79 80 static RegisterScheduler 81 defaultListDAGScheduler("default", " Best scheduler for the target", 82 createDefaultScheduler); 83} // namespace 84 85namespace { struct AsmOperandInfo; } 86 87namespace { 88 /// RegsForValue - This struct represents the physical registers that a 89 /// particular value is assigned and the type information about the value. 90 /// This is needed because values can be promoted into larger registers and 91 /// expanded into multiple smaller registers than the value. 92 struct VISIBILITY_HIDDEN RegsForValue { 93 /// Regs - This list holds the register (for legal and promoted values) 94 /// or register set (for expanded values) that the value should be assigned 95 /// to. 96 std::vector<unsigned> Regs; 97 98 /// RegVT - The value type of each register. 99 /// 100 MVT::ValueType RegVT; 101 102 /// ValueVT - The value type of the LLVM value, which may be promoted from 103 /// RegVT or made from merging the two expanded parts. 104 MVT::ValueType ValueVT; 105 106 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 107 108 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 109 : RegVT(regvt), ValueVT(valuevt) { 110 Regs.push_back(Reg); 111 } 112 RegsForValue(const std::vector<unsigned> ®s, 113 MVT::ValueType regvt, MVT::ValueType valuevt) 114 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 115 } 116 117 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 118 /// this value and returns the result as a ValueVT value. This uses 119 /// Chain/Flag as the input and updates them for the output Chain/Flag. 120 /// If the Flag pointer is NULL, no flag is used. 121 SDOperand getCopyFromRegs(SelectionDAG &DAG, 122 SDOperand &Chain, SDOperand *Flag) const; 123 124 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 125 /// specified value into the registers specified by this object. This uses 126 /// Chain/Flag as the input and updates them for the output Chain/Flag. 127 /// If the Flag pointer is NULL, no flag is used. 128 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 129 SDOperand &Chain, SDOperand *Flag) const; 130 131 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 132 /// operand list. This adds the code marker and includes the number of 133 /// values added into it. 134 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 135 std::vector<SDOperand> &Ops) const; 136 }; 137} 138 139namespace llvm { 140 //===--------------------------------------------------------------------===// 141 /// createDefaultScheduler - This creates an instruction scheduler appropriate 142 /// for the target. 143 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 144 SelectionDAG *DAG, 145 MachineBasicBlock *BB) { 146 TargetLowering &TLI = IS->getTargetLowering(); 147 148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 149 return createTDListDAGScheduler(IS, DAG, BB); 150 } else { 151 assert(TLI.getSchedulingPreference() == 152 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 153 return createBURRListDAGScheduler(IS, DAG, BB); 154 } 155 } 156 157 158 //===--------------------------------------------------------------------===// 159 /// FunctionLoweringInfo - This contains information that is global to a 160 /// function that is used when lowering a region of the function. 161 class FunctionLoweringInfo { 162 public: 163 TargetLowering &TLI; 164 Function &Fn; 165 MachineFunction &MF; 166 SSARegMap *RegMap; 167 168 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 169 170 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 171 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 172 173 /// ValueMap - Since we emit code for the function a basic block at a time, 174 /// we must remember which virtual registers hold the values for 175 /// cross-basic-block values. 176 DenseMap<const Value*, unsigned> ValueMap; 177 178 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 179 /// the entry block. This allows the allocas to be efficiently referenced 180 /// anywhere in the function. 181 std::map<const AllocaInst*, int> StaticAllocaMap; 182 183#ifndef NDEBUG 184 SmallSet<Instruction*, 8> CatchInfoLost; 185 SmallSet<Instruction*, 8> CatchInfoFound; 186#endif 187 188 unsigned MakeReg(MVT::ValueType VT) { 189 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 190 } 191 192 /// isExportedInst - Return true if the specified value is an instruction 193 /// exported from its block. 194 bool isExportedInst(const Value *V) { 195 return ValueMap.count(V); 196 } 197 198 unsigned CreateRegForValue(const Value *V); 199 200 unsigned InitializeRegForValue(const Value *V) { 201 unsigned &R = ValueMap[V]; 202 assert(R == 0 && "Already initialized this value register!"); 203 return R = CreateRegForValue(V); 204 } 205 }; 206} 207 208/// isSelector - Return true if this instruction is a call to the 209/// eh.selector intrinsic. 210static bool isSelector(Instruction *I) { 211 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 212 return II->getIntrinsicID() == Intrinsic::eh_selector; 213 return false; 214} 215 216/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 217/// PHI nodes or outside of the basic block that defines it, or used by a 218/// switch instruction, which may expand to multiple basic blocks. 219static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 220 if (isa<PHINode>(I)) return true; 221 BasicBlock *BB = I->getParent(); 222 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 223 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 224 // FIXME: Remove switchinst special case. 225 isa<SwitchInst>(*UI)) 226 return true; 227 return false; 228} 229 230/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 231/// entry block, return true. This includes arguments used by switches, since 232/// the switch may expand into multiple basic blocks. 233static bool isOnlyUsedInEntryBlock(Argument *A) { 234 BasicBlock *Entry = A->getParent()->begin(); 235 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 236 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 237 return false; // Use not in entry block. 238 return true; 239} 240 241FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 242 Function &fn, MachineFunction &mf) 243 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 244 245 // Create a vreg for each argument register that is not dead and is used 246 // outside of the entry block for the function. 247 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 248 AI != E; ++AI) 249 if (!isOnlyUsedInEntryBlock(AI)) 250 InitializeRegForValue(AI); 251 252 // Initialize the mapping of values to registers. This is only set up for 253 // instruction values that are used outside of the block that defines 254 // them. 255 Function::iterator BB = Fn.begin(), EB = Fn.end(); 256 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 257 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 258 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 259 const Type *Ty = AI->getAllocatedType(); 260 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 261 unsigned Align = 262 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 263 AI->getAlignment()); 264 265 TySize *= CUI->getZExtValue(); // Get total allocated size. 266 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 267 StaticAllocaMap[AI] = 268 MF.getFrameInfo()->CreateStackObject(TySize, Align); 269 } 270 271 for (; BB != EB; ++BB) 272 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 273 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 274 if (!isa<AllocaInst>(I) || 275 !StaticAllocaMap.count(cast<AllocaInst>(I))) 276 InitializeRegForValue(I); 277 278 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 279 // also creates the initial PHI MachineInstrs, though none of the input 280 // operands are populated. 281 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 282 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 283 MBBMap[BB] = MBB; 284 MF.getBasicBlockList().push_back(MBB); 285 286 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 287 // appropriate. 288 PHINode *PN; 289 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 290 if (PN->use_empty()) continue; 291 292 MVT::ValueType VT = TLI.getValueType(PN->getType()); 293 unsigned NumRegisters = TLI.getNumRegisters(VT); 294 unsigned PHIReg = ValueMap[PN]; 295 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 296 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 297 for (unsigned i = 0; i != NumRegisters; ++i) 298 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 299 } 300 } 301} 302 303/// CreateRegForValue - Allocate the appropriate number of virtual registers of 304/// the correctly promoted or expanded types. Assign these registers 305/// consecutive vreg numbers and return the first assigned number. 306unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 307 MVT::ValueType VT = TLI.getValueType(V->getType()); 308 309 unsigned NumRegisters = TLI.getNumRegisters(VT); 310 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 311 312 unsigned R = MakeReg(RegisterVT); 313 for (unsigned i = 1; i != NumRegisters; ++i) 314 MakeReg(RegisterVT); 315 316 return R; 317} 318 319//===----------------------------------------------------------------------===// 320/// SelectionDAGLowering - This is the common target-independent lowering 321/// implementation that is parameterized by a TargetLowering object. 322/// Also, targets can overload any lowering method. 323/// 324namespace llvm { 325class SelectionDAGLowering { 326 MachineBasicBlock *CurMBB; 327 328 DenseMap<const Value*, SDOperand> NodeMap; 329 330 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 331 /// them up and then emit token factor nodes when possible. This allows us to 332 /// get simple disambiguation between loads without worrying about alias 333 /// analysis. 334 std::vector<SDOperand> PendingLoads; 335 336 /// Case - A struct to record the Value for a switch case, and the 337 /// case's target basic block. 338 struct Case { 339 Constant* Low; 340 Constant* High; 341 MachineBasicBlock* BB; 342 343 Case() : Low(0), High(0), BB(0) { } 344 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 345 Low(low), High(high), BB(bb) { } 346 uint64_t size() const { 347 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 348 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 349 return (rHigh - rLow + 1ULL); 350 } 351 }; 352 353 struct CaseBits { 354 uint64_t Mask; 355 MachineBasicBlock* BB; 356 unsigned Bits; 357 358 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 359 Mask(mask), BB(bb), Bits(bits) { } 360 }; 361 362 typedef std::vector<Case> CaseVector; 363 typedef std::vector<CaseBits> CaseBitsVector; 364 typedef CaseVector::iterator CaseItr; 365 typedef std::pair<CaseItr, CaseItr> CaseRange; 366 367 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 368 /// of conditional branches. 369 struct CaseRec { 370 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 371 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 372 373 /// CaseBB - The MBB in which to emit the compare and branch 374 MachineBasicBlock *CaseBB; 375 /// LT, GE - If nonzero, we know the current case value must be less-than or 376 /// greater-than-or-equal-to these Constants. 377 Constant *LT; 378 Constant *GE; 379 /// Range - A pair of iterators representing the range of case values to be 380 /// processed at this point in the binary search tree. 381 CaseRange Range; 382 }; 383 384 typedef std::vector<CaseRec> CaseRecVector; 385 386 /// The comparison function for sorting the switch case values in the vector. 387 /// WARNING: Case ranges should be disjoint! 388 struct CaseCmp { 389 bool operator () (const Case& C1, const Case& C2) { 390 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 391 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 392 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 393 return CI1->getValue().slt(CI2->getValue()); 394 } 395 }; 396 397 struct CaseBitsCmp { 398 bool operator () (const CaseBits& C1, const CaseBits& C2) { 399 return C1.Bits > C2.Bits; 400 } 401 }; 402 403 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 404 405public: 406 // TLI - This is information that describes the available target features we 407 // need for lowering. This indicates when operations are unavailable, 408 // implemented with a libcall, etc. 409 TargetLowering &TLI; 410 SelectionDAG &DAG; 411 const TargetData *TD; 412 413 /// SwitchCases - Vector of CaseBlock structures used to communicate 414 /// SwitchInst code generation information. 415 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 416 /// JTCases - Vector of JumpTable structures used to communicate 417 /// SwitchInst code generation information. 418 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 419 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 420 421 /// FuncInfo - Information about the function as a whole. 422 /// 423 FunctionLoweringInfo &FuncInfo; 424 425 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 426 FunctionLoweringInfo &funcinfo) 427 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), 428 FuncInfo(funcinfo) { 429 } 430 431 /// getRoot - Return the current virtual root of the Selection DAG. 432 /// 433 SDOperand getRoot() { 434 if (PendingLoads.empty()) 435 return DAG.getRoot(); 436 437 if (PendingLoads.size() == 1) { 438 SDOperand Root = PendingLoads[0]; 439 DAG.setRoot(Root); 440 PendingLoads.clear(); 441 return Root; 442 } 443 444 // Otherwise, we have to make a token factor node. 445 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 446 &PendingLoads[0], PendingLoads.size()); 447 PendingLoads.clear(); 448 DAG.setRoot(Root); 449 return Root; 450 } 451 452 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 453 454 void visit(Instruction &I) { visit(I.getOpcode(), I); } 455 456 void visit(unsigned Opcode, User &I) { 457 // Note: this doesn't use InstVisitor, because it has to work with 458 // ConstantExpr's in addition to instructions. 459 switch (Opcode) { 460 default: assert(0 && "Unknown instruction type encountered!"); 461 abort(); 462 // Build the switch statement using the Instruction.def file. 463#define HANDLE_INST(NUM, OPCODE, CLASS) \ 464 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 465#include "llvm/Instruction.def" 466 } 467 } 468 469 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 470 471 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 472 const Value *SV, SDOperand Root, 473 bool isVolatile, unsigned Alignment); 474 475 SDOperand getIntPtrConstant(uint64_t Val) { 476 return DAG.getConstant(Val, TLI.getPointerTy()); 477 } 478 479 SDOperand getValue(const Value *V); 480 481 void setValue(const Value *V, SDOperand NewN) { 482 SDOperand &N = NodeMap[V]; 483 assert(N.Val == 0 && "Already set a value for this node!"); 484 N = NewN; 485 } 486 487 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 488 std::set<unsigned> &OutputRegs, 489 std::set<unsigned> &InputRegs); 490 491 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 492 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 493 unsigned Opc); 494 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 495 void ExportFromCurrentBlock(Value *V); 496 void LowerCallTo(Instruction &I, 497 const Type *CalledValueTy, unsigned CallingConv, 498 bool IsTailCall, SDOperand Callee, unsigned OpIdx, 499 MachineBasicBlock *LandingPad = NULL); 500 501 // Terminator instructions. 502 void visitRet(ReturnInst &I); 503 void visitBr(BranchInst &I); 504 void visitSwitch(SwitchInst &I); 505 void visitUnreachable(UnreachableInst &I) { /* noop */ } 506 507 // Helpers for visitSwitch 508 bool handleSmallSwitchRange(CaseRec& CR, 509 CaseRecVector& WorkList, 510 Value* SV, 511 MachineBasicBlock* Default); 512 bool handleJTSwitchCase(CaseRec& CR, 513 CaseRecVector& WorkList, 514 Value* SV, 515 MachineBasicBlock* Default); 516 bool handleBTSplitSwitchCase(CaseRec& CR, 517 CaseRecVector& WorkList, 518 Value* SV, 519 MachineBasicBlock* Default); 520 bool handleBitTestsSwitchCase(CaseRec& CR, 521 CaseRecVector& WorkList, 522 Value* SV, 523 MachineBasicBlock* Default); 524 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 525 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 526 void visitBitTestCase(MachineBasicBlock* NextMBB, 527 unsigned Reg, 528 SelectionDAGISel::BitTestCase &B); 529 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 530 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 531 SelectionDAGISel::JumpTableHeader &JTH); 532 533 // These all get lowered before this pass. 534 void visitInvoke(InvokeInst &I); 535 void visitUnwind(UnwindInst &I); 536 537 void visitBinary(User &I, unsigned OpCode); 538 void visitShift(User &I, unsigned Opcode); 539 void visitAdd(User &I) { 540 if (I.getType()->isFPOrFPVector()) 541 visitBinary(I, ISD::FADD); 542 else 543 visitBinary(I, ISD::ADD); 544 } 545 void visitSub(User &I); 546 void visitMul(User &I) { 547 if (I.getType()->isFPOrFPVector()) 548 visitBinary(I, ISD::FMUL); 549 else 550 visitBinary(I, ISD::MUL); 551 } 552 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 553 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 554 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 555 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 556 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 557 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 558 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 559 void visitOr (User &I) { visitBinary(I, ISD::OR); } 560 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 561 void visitShl (User &I) { visitShift(I, ISD::SHL); } 562 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 563 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 564 void visitICmp(User &I); 565 void visitFCmp(User &I); 566 // Visit the conversion instructions 567 void visitTrunc(User &I); 568 void visitZExt(User &I); 569 void visitSExt(User &I); 570 void visitFPTrunc(User &I); 571 void visitFPExt(User &I); 572 void visitFPToUI(User &I); 573 void visitFPToSI(User &I); 574 void visitUIToFP(User &I); 575 void visitSIToFP(User &I); 576 void visitPtrToInt(User &I); 577 void visitIntToPtr(User &I); 578 void visitBitCast(User &I); 579 580 void visitExtractElement(User &I); 581 void visitInsertElement(User &I); 582 void visitShuffleVector(User &I); 583 584 void visitGetElementPtr(User &I); 585 void visitSelect(User &I); 586 587 void visitMalloc(MallocInst &I); 588 void visitFree(FreeInst &I); 589 void visitAlloca(AllocaInst &I); 590 void visitLoad(LoadInst &I); 591 void visitStore(StoreInst &I); 592 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 593 void visitCall(CallInst &I); 594 void visitInlineAsm(CallInst &I); 595 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 596 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 597 598 void visitVAStart(CallInst &I); 599 void visitVAArg(VAArgInst &I); 600 void visitVAEnd(CallInst &I); 601 void visitVACopy(CallInst &I); 602 603 void visitMemIntrinsic(CallInst &I, unsigned Op); 604 605 void visitUserOp1(Instruction &I) { 606 assert(0 && "UserOp1 should not exist at instruction selection time!"); 607 abort(); 608 } 609 void visitUserOp2(Instruction &I) { 610 assert(0 && "UserOp2 should not exist at instruction selection time!"); 611 abort(); 612 } 613}; 614} // end namespace llvm 615 616 617/// getCopyFromParts - Create a value that contains the 618/// specified legal parts combined into the value they represent. 619static SDOperand getCopyFromParts(SelectionDAG &DAG, 620 const SDOperand *Parts, 621 unsigned NumParts, 622 MVT::ValueType PartVT, 623 MVT::ValueType ValueVT, 624 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 625 if (!MVT::isVector(ValueVT) || NumParts == 1) { 626 SDOperand Val = Parts[0]; 627 628 // If the value was expanded, copy from the top part. 629 if (NumParts > 1) { 630 assert(NumParts == 2 && 631 "Cannot expand to more than 2 elts yet!"); 632 SDOperand Hi = Parts[1]; 633 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 634 std::swap(Val, Hi); 635 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 636 } 637 638 // Otherwise, if the value was promoted or extended, truncate it to the 639 // appropriate type. 640 if (PartVT == ValueVT) 641 return Val; 642 643 if (MVT::isVector(PartVT)) { 644 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!"); 645 return DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 646 } 647 648 if (MVT::isInteger(PartVT) && 649 MVT::isInteger(ValueVT)) { 650 if (ValueVT < PartVT) { 651 // For a truncate, see if we have any information to 652 // indicate whether the truncated bits will always be 653 // zero or sign-extension. 654 if (AssertOp != ISD::DELETED_NODE) 655 Val = DAG.getNode(AssertOp, PartVT, Val, 656 DAG.getValueType(ValueVT)); 657 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 658 } else { 659 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 660 } 661 } 662 663 if (MVT::isFloatingPoint(PartVT) && 664 MVT::isFloatingPoint(ValueVT)) 665 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 666 667 if (MVT::getSizeInBits(PartVT) == 668 MVT::getSizeInBits(ValueVT)) 669 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 670 671 assert(0 && "Unknown mismatch!"); 672 } 673 674 // Handle a multi-element vector. 675 MVT::ValueType IntermediateVT, RegisterVT; 676 unsigned NumIntermediates; 677 unsigned NumRegs = 678 DAG.getTargetLoweringInfo() 679 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 680 RegisterVT); 681 682 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 683 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 684 assert(RegisterVT == Parts[0].getValueType() && 685 "Part type doesn't match part!"); 686 687 // Assemble the parts into intermediate operands. 688 SmallVector<SDOperand, 8> Ops(NumIntermediates); 689 if (NumIntermediates == NumParts) { 690 // If the register was not expanded, truncate or copy the value, 691 // as appropriate. 692 for (unsigned i = 0; i != NumParts; ++i) 693 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 694 PartVT, IntermediateVT); 695 } else if (NumParts > 0) { 696 // If the intermediate type was expanded, build the intermediate operands 697 // from the parts. 698 assert(NumIntermediates % NumParts == 0 && 699 "Must expand into a divisible number of parts!"); 700 unsigned Factor = NumIntermediates / NumParts; 701 for (unsigned i = 0; i != NumIntermediates; ++i) 702 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 703 PartVT, IntermediateVT); 704 } 705 706 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 707 // operands. 708 return DAG.getNode(MVT::isVector(IntermediateVT) ? 709 ISD::CONCAT_VECTORS : 710 ISD::BUILD_VECTOR, 711 ValueVT, &Ops[0], NumParts); 712} 713 714/// getCopyToParts - Create a series of nodes that contain the 715/// specified value split into legal parts. 716static void getCopyToParts(SelectionDAG &DAG, 717 SDOperand Val, 718 SDOperand *Parts, 719 unsigned NumParts, 720 MVT::ValueType PartVT) { 721 MVT::ValueType ValueVT = Val.getValueType(); 722 723 if (!MVT::isVector(ValueVT) || NumParts == 1) { 724 // If the value was expanded, copy from the parts. 725 if (NumParts > 1) { 726 for (unsigned i = 0; i != NumParts; ++i) 727 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val, 728 DAG.getConstant(i, MVT::i32)); 729 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 730 std::reverse(Parts, Parts + NumParts); 731 return; 732 } 733 734 // If there is a single part and the types differ, this must be 735 // a promotion. 736 if (PartVT != ValueVT) { 737 if (MVT::isVector(PartVT)) { 738 assert(MVT::isVector(ValueVT) && 739 "Not a vector-vector cast?"); 740 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 741 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 742 if (PartVT < ValueVT) 743 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val); 744 else 745 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val); 746 } else if (MVT::isFloatingPoint(PartVT) && 747 MVT::isFloatingPoint(ValueVT)) { 748 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 749 } else if (MVT::getSizeInBits(PartVT) == 750 MVT::getSizeInBits(ValueVT)) { 751 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 752 } else { 753 assert(0 && "Unknown mismatch!"); 754 } 755 } 756 Parts[0] = Val; 757 return; 758 } 759 760 // Handle a multi-element vector. 761 MVT::ValueType IntermediateVT, RegisterVT; 762 unsigned NumIntermediates; 763 unsigned NumRegs = 764 DAG.getTargetLoweringInfo() 765 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 766 RegisterVT); 767 unsigned NumElements = MVT::getVectorNumElements(ValueVT); 768 769 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 770 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 771 772 // Split the vector into intermediate operands. 773 SmallVector<SDOperand, 8> Ops(NumIntermediates); 774 for (unsigned i = 0; i != NumIntermediates; ++i) 775 if (MVT::isVector(IntermediateVT)) 776 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 777 IntermediateVT, Val, 778 DAG.getConstant(i * (NumElements / NumIntermediates), 779 MVT::i32)); 780 else 781 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 782 IntermediateVT, Val, 783 DAG.getConstant(i, MVT::i32)); 784 785 // Split the intermediate operands into legal parts. 786 if (NumParts == NumIntermediates) { 787 // If the register was not expanded, promote or copy the value, 788 // as appropriate. 789 for (unsigned i = 0; i != NumParts; ++i) 790 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 791 } else if (NumParts > 0) { 792 // If the intermediate type was expanded, split each the value into 793 // legal parts. 794 assert(NumParts % NumIntermediates == 0 && 795 "Must expand into a divisible number of parts!"); 796 unsigned Factor = NumParts / NumIntermediates; 797 for (unsigned i = 0; i != NumIntermediates; ++i) 798 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 799 } 800} 801 802 803SDOperand SelectionDAGLowering::getValue(const Value *V) { 804 SDOperand &N = NodeMap[V]; 805 if (N.Val) return N; 806 807 const Type *VTy = V->getType(); 808 MVT::ValueType VT = TLI.getValueType(VTy); 809 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 810 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 811 visit(CE->getOpcode(), *CE); 812 SDOperand N1 = NodeMap[V]; 813 assert(N1.Val && "visit didn't populate the ValueMap!"); 814 return N1; 815 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 816 return N = DAG.getGlobalAddress(GV, VT); 817 } else if (isa<ConstantPointerNull>(C)) { 818 return N = DAG.getConstant(0, TLI.getPointerTy()); 819 } else if (isa<UndefValue>(C)) { 820 if (!isa<VectorType>(VTy)) 821 return N = DAG.getNode(ISD::UNDEF, VT); 822 823 // Create a BUILD_VECTOR of undef nodes. 824 const VectorType *PTy = cast<VectorType>(VTy); 825 unsigned NumElements = PTy->getNumElements(); 826 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 827 828 SmallVector<SDOperand, 8> Ops; 829 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 830 831 // Create a VConstant node with generic Vector type. 832 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 833 return N = DAG.getNode(ISD::BUILD_VECTOR, VT, 834 &Ops[0], Ops.size()); 835 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 836 return N = DAG.getConstantFP(CFP->getValue(), VT); 837 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 838 unsigned NumElements = PTy->getNumElements(); 839 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 840 841 // Now that we know the number and type of the elements, push a 842 // Constant or ConstantFP node onto the ops list for each element of 843 // the packed constant. 844 SmallVector<SDOperand, 8> Ops; 845 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 846 for (unsigned i = 0; i != NumElements; ++i) 847 Ops.push_back(getValue(CP->getOperand(i))); 848 } else { 849 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!"); 850 SDOperand Op; 851 if (MVT::isFloatingPoint(PVT)) 852 Op = DAG.getConstantFP(0, PVT); 853 else 854 Op = DAG.getConstant(0, PVT); 855 Ops.assign(NumElements, Op); 856 } 857 858 // Create a BUILD_VECTOR node. 859 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 860 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], 861 Ops.size()); 862 } else { 863 // Canonicalize all constant ints to be unsigned. 864 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT); 865 } 866 } 867 868 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 869 std::map<const AllocaInst*, int>::iterator SI = 870 FuncInfo.StaticAllocaMap.find(AI); 871 if (SI != FuncInfo.StaticAllocaMap.end()) 872 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 873 } 874 875 unsigned InReg = FuncInfo.ValueMap[V]; 876 assert(InReg && "Value not in map!"); 877 878 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 879 unsigned NumRegs = TLI.getNumRegisters(VT); 880 881 std::vector<unsigned> Regs(NumRegs); 882 for (unsigned i = 0; i != NumRegs; ++i) 883 Regs[i] = InReg + i; 884 885 RegsForValue RFV(Regs, RegisterVT, VT); 886 SDOperand Chain = DAG.getEntryNode(); 887 888 return RFV.getCopyFromRegs(DAG, Chain, NULL); 889} 890 891 892void SelectionDAGLowering::visitRet(ReturnInst &I) { 893 if (I.getNumOperands() == 0) { 894 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 895 return; 896 } 897 SmallVector<SDOperand, 8> NewValues; 898 NewValues.push_back(getRoot()); 899 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 900 SDOperand RetOp = getValue(I.getOperand(i)); 901 902 // If this is an integer return value, we need to promote it ourselves to 903 // the full width of a register, since getCopyToParts and Legalize will use 904 // ANY_EXTEND rather than sign/zero. 905 // FIXME: C calling convention requires the return type to be promoted to 906 // at least 32-bit. But this is not necessary for non-C calling conventions. 907 if (MVT::isInteger(RetOp.getValueType()) && 908 RetOp.getValueType() < MVT::i64) { 909 MVT::ValueType TmpVT; 910 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 911 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 912 else 913 TmpVT = MVT::i32; 914 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType(); 915 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 916 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 917 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt)) 918 ExtendKind = ISD::SIGN_EXTEND; 919 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt)) 920 ExtendKind = ISD::ZERO_EXTEND; 921 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp); 922 NewValues.push_back(RetOp); 923 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 924 } else { 925 MVT::ValueType VT = RetOp.getValueType(); 926 unsigned NumParts = TLI.getNumRegisters(VT); 927 MVT::ValueType PartVT = TLI.getRegisterType(VT); 928 SmallVector<SDOperand, 4> Parts(NumParts); 929 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT); 930 for (unsigned i = 0; i < NumParts; ++i) { 931 NewValues.push_back(Parts[i]); 932 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 933 } 934 } 935 } 936 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 937 &NewValues[0], NewValues.size())); 938} 939 940/// ExportFromCurrentBlock - If this condition isn't known to be exported from 941/// the current basic block, add it to ValueMap now so that we'll get a 942/// CopyTo/FromReg. 943void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 944 // No need to export constants. 945 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 946 947 // Already exported? 948 if (FuncInfo.isExportedInst(V)) return; 949 950 unsigned Reg = FuncInfo.InitializeRegForValue(V); 951 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 952} 953 954bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 955 const BasicBlock *FromBB) { 956 // The operands of the setcc have to be in this block. We don't know 957 // how to export them from some other block. 958 if (Instruction *VI = dyn_cast<Instruction>(V)) { 959 // Can export from current BB. 960 if (VI->getParent() == FromBB) 961 return true; 962 963 // Is already exported, noop. 964 return FuncInfo.isExportedInst(V); 965 } 966 967 // If this is an argument, we can export it if the BB is the entry block or 968 // if it is already exported. 969 if (isa<Argument>(V)) { 970 if (FromBB == &FromBB->getParent()->getEntryBlock()) 971 return true; 972 973 // Otherwise, can only export this if it is already exported. 974 return FuncInfo.isExportedInst(V); 975 } 976 977 // Otherwise, constants can always be exported. 978 return true; 979} 980 981static bool InBlock(const Value *V, const BasicBlock *BB) { 982 if (const Instruction *I = dyn_cast<Instruction>(V)) 983 return I->getParent() == BB; 984 return true; 985} 986 987/// FindMergedConditions - If Cond is an expression like 988void SelectionDAGLowering::FindMergedConditions(Value *Cond, 989 MachineBasicBlock *TBB, 990 MachineBasicBlock *FBB, 991 MachineBasicBlock *CurBB, 992 unsigned Opc) { 993 // If this node is not part of the or/and tree, emit it as a branch. 994 Instruction *BOp = dyn_cast<Instruction>(Cond); 995 996 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 997 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 998 BOp->getParent() != CurBB->getBasicBlock() || 999 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1000 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1001 const BasicBlock *BB = CurBB->getBasicBlock(); 1002 1003 // If the leaf of the tree is a comparison, merge the condition into 1004 // the caseblock. 1005 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1006 // The operands of the cmp have to be in this block. We don't know 1007 // how to export them from some other block. If this is the first block 1008 // of the sequence, no exporting is needed. 1009 (CurBB == CurMBB || 1010 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1011 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1012 BOp = cast<Instruction>(Cond); 1013 ISD::CondCode Condition; 1014 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1015 switch (IC->getPredicate()) { 1016 default: assert(0 && "Unknown icmp predicate opcode!"); 1017 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1018 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1019 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1020 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1021 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1022 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1023 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1024 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1025 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1026 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1027 } 1028 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1029 ISD::CondCode FPC, FOC; 1030 switch (FC->getPredicate()) { 1031 default: assert(0 && "Unknown fcmp predicate opcode!"); 1032 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1033 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1034 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1035 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1036 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1037 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1038 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1039 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 1040 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 1041 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1042 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1043 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1044 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1045 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1046 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1047 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1048 } 1049 if (FiniteOnlyFPMath()) 1050 Condition = FOC; 1051 else 1052 Condition = FPC; 1053 } else { 1054 Condition = ISD::SETEQ; // silence warning. 1055 assert(0 && "Unknown compare instruction"); 1056 } 1057 1058 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1059 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1060 SwitchCases.push_back(CB); 1061 return; 1062 } 1063 1064 // Create a CaseBlock record representing this branch. 1065 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1066 NULL, TBB, FBB, CurBB); 1067 SwitchCases.push_back(CB); 1068 return; 1069 } 1070 1071 1072 // Create TmpBB after CurBB. 1073 MachineFunction::iterator BBI = CurBB; 1074 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 1075 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 1076 1077 if (Opc == Instruction::Or) { 1078 // Codegen X | Y as: 1079 // jmp_if_X TBB 1080 // jmp TmpBB 1081 // TmpBB: 1082 // jmp_if_Y TBB 1083 // jmp FBB 1084 // 1085 1086 // Emit the LHS condition. 1087 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1088 1089 // Emit the RHS condition into TmpBB. 1090 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1091 } else { 1092 assert(Opc == Instruction::And && "Unknown merge op!"); 1093 // Codegen X & Y as: 1094 // jmp_if_X TmpBB 1095 // jmp FBB 1096 // TmpBB: 1097 // jmp_if_Y TBB 1098 // jmp FBB 1099 // 1100 // This requires creation of TmpBB after CurBB. 1101 1102 // Emit the LHS condition. 1103 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1104 1105 // Emit the RHS condition into TmpBB. 1106 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1107 } 1108} 1109 1110/// If the set of cases should be emitted as a series of branches, return true. 1111/// If we should emit this as a bunch of and/or'd together conditions, return 1112/// false. 1113static bool 1114ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1115 if (Cases.size() != 2) return true; 1116 1117 // If this is two comparisons of the same values or'd or and'd together, they 1118 // will get folded into a single comparison, so don't emit two blocks. 1119 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1120 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1121 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1122 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1123 return false; 1124 } 1125 1126 return true; 1127} 1128 1129void SelectionDAGLowering::visitBr(BranchInst &I) { 1130 // Update machine-CFG edges. 1131 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1132 1133 // Figure out which block is immediately after the current one. 1134 MachineBasicBlock *NextBlock = 0; 1135 MachineFunction::iterator BBI = CurMBB; 1136 if (++BBI != CurMBB->getParent()->end()) 1137 NextBlock = BBI; 1138 1139 if (I.isUnconditional()) { 1140 // If this is not a fall-through branch, emit the branch. 1141 if (Succ0MBB != NextBlock) 1142 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1143 DAG.getBasicBlock(Succ0MBB))); 1144 1145 // Update machine-CFG edges. 1146 CurMBB->addSuccessor(Succ0MBB); 1147 1148 return; 1149 } 1150 1151 // If this condition is one of the special cases we handle, do special stuff 1152 // now. 1153 Value *CondVal = I.getCondition(); 1154 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1155 1156 // If this is a series of conditions that are or'd or and'd together, emit 1157 // this as a sequence of branches instead of setcc's with and/or operations. 1158 // For example, instead of something like: 1159 // cmp A, B 1160 // C = seteq 1161 // cmp D, E 1162 // F = setle 1163 // or C, F 1164 // jnz foo 1165 // Emit: 1166 // cmp A, B 1167 // je foo 1168 // cmp D, E 1169 // jle foo 1170 // 1171 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1172 if (BOp->hasOneUse() && 1173 (BOp->getOpcode() == Instruction::And || 1174 BOp->getOpcode() == Instruction::Or)) { 1175 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1176 // If the compares in later blocks need to use values not currently 1177 // exported from this block, export them now. This block should always 1178 // be the first entry. 1179 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1180 1181 // Allow some cases to be rejected. 1182 if (ShouldEmitAsBranches(SwitchCases)) { 1183 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1184 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1185 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1186 } 1187 1188 // Emit the branch for this block. 1189 visitSwitchCase(SwitchCases[0]); 1190 SwitchCases.erase(SwitchCases.begin()); 1191 return; 1192 } 1193 1194 // Okay, we decided not to do this, remove any inserted MBB's and clear 1195 // SwitchCases. 1196 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1197 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1198 1199 SwitchCases.clear(); 1200 } 1201 } 1202 1203 // Create a CaseBlock record representing this branch. 1204 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1205 NULL, Succ0MBB, Succ1MBB, CurMBB); 1206 // Use visitSwitchCase to actually insert the fast branch sequence for this 1207 // cond branch. 1208 visitSwitchCase(CB); 1209} 1210 1211/// visitSwitchCase - Emits the necessary code to represent a single node in 1212/// the binary search tree resulting from lowering a switch instruction. 1213void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1214 SDOperand Cond; 1215 SDOperand CondLHS = getValue(CB.CmpLHS); 1216 1217 // Build the setcc now. 1218 if (CB.CmpMHS == NULL) { 1219 // Fold "(X == true)" to X and "(X == false)" to !X to 1220 // handle common cases produced by branch lowering. 1221 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1222 Cond = CondLHS; 1223 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1224 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1225 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1226 } else 1227 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1228 } else { 1229 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1230 1231 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1232 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1233 1234 SDOperand CmpOp = getValue(CB.CmpMHS); 1235 MVT::ValueType VT = CmpOp.getValueType(); 1236 1237 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1238 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1239 } else { 1240 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1241 Cond = DAG.getSetCC(MVT::i1, SUB, 1242 DAG.getConstant(High-Low, VT), ISD::SETULE); 1243 } 1244 1245 } 1246 1247 // Set NextBlock to be the MBB immediately after the current one, if any. 1248 // This is used to avoid emitting unnecessary branches to the next block. 1249 MachineBasicBlock *NextBlock = 0; 1250 MachineFunction::iterator BBI = CurMBB; 1251 if (++BBI != CurMBB->getParent()->end()) 1252 NextBlock = BBI; 1253 1254 // If the lhs block is the next block, invert the condition so that we can 1255 // fall through to the lhs instead of the rhs block. 1256 if (CB.TrueBB == NextBlock) { 1257 std::swap(CB.TrueBB, CB.FalseBB); 1258 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1259 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1260 } 1261 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1262 DAG.getBasicBlock(CB.TrueBB)); 1263 if (CB.FalseBB == NextBlock) 1264 DAG.setRoot(BrCond); 1265 else 1266 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1267 DAG.getBasicBlock(CB.FalseBB))); 1268 // Update successor info 1269 CurMBB->addSuccessor(CB.TrueBB); 1270 CurMBB->addSuccessor(CB.FalseBB); 1271} 1272 1273/// visitJumpTable - Emit JumpTable node in the current MBB 1274void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1275 // Emit the code for the jump table 1276 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1277 MVT::ValueType PTy = TLI.getPointerTy(); 1278 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1279 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1280 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1281 Table, Index)); 1282 return; 1283} 1284 1285/// visitJumpTableHeader - This function emits necessary code to produce index 1286/// in the JumpTable from switch case. 1287void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1288 SelectionDAGISel::JumpTableHeader &JTH) { 1289 // Subtract the lowest switch case value from the value being switched on 1290 // and conditional branch to default mbb if the result is greater than the 1291 // difference between smallest and largest cases. 1292 SDOperand SwitchOp = getValue(JTH.SValue); 1293 MVT::ValueType VT = SwitchOp.getValueType(); 1294 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1295 DAG.getConstant(JTH.First, VT)); 1296 1297 // The SDNode we just created, which holds the value being switched on 1298 // minus the the smallest case value, needs to be copied to a virtual 1299 // register so it can be used as an index into the jump table in a 1300 // subsequent basic block. This value may be smaller or larger than the 1301 // target's pointer type, and therefore require extension or truncating. 1302 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 1303 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1304 else 1305 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1306 1307 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1308 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1309 JT.Reg = JumpTableReg; 1310 1311 // Emit the range check for the jump table, and branch to the default 1312 // block for the switch statement if the value being switched on exceeds 1313 // the largest case in the switch. 1314 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1315 DAG.getConstant(JTH.Last-JTH.First,VT), 1316 ISD::SETUGT); 1317 1318 // Set NextBlock to be the MBB immediately after the current one, if any. 1319 // This is used to avoid emitting unnecessary branches to the next block. 1320 MachineBasicBlock *NextBlock = 0; 1321 MachineFunction::iterator BBI = CurMBB; 1322 if (++BBI != CurMBB->getParent()->end()) 1323 NextBlock = BBI; 1324 1325 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1326 DAG.getBasicBlock(JT.Default)); 1327 1328 if (JT.MBB == NextBlock) 1329 DAG.setRoot(BrCond); 1330 else 1331 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1332 DAG.getBasicBlock(JT.MBB))); 1333 1334 return; 1335} 1336 1337/// visitBitTestHeader - This function emits necessary code to produce value 1338/// suitable for "bit tests" 1339void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1340 // Subtract the minimum value 1341 SDOperand SwitchOp = getValue(B.SValue); 1342 MVT::ValueType VT = SwitchOp.getValueType(); 1343 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1344 DAG.getConstant(B.First, VT)); 1345 1346 // Check range 1347 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1348 DAG.getConstant(B.Range, VT), 1349 ISD::SETUGT); 1350 1351 SDOperand ShiftOp; 1352 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy())) 1353 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1354 else 1355 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1356 1357 // Make desired shift 1358 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1359 DAG.getConstant(1, TLI.getPointerTy()), 1360 ShiftOp); 1361 1362 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1363 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1364 B.Reg = SwitchReg; 1365 1366 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1367 DAG.getBasicBlock(B.Default)); 1368 1369 // Set NextBlock to be the MBB immediately after the current one, if any. 1370 // This is used to avoid emitting unnecessary branches to the next block. 1371 MachineBasicBlock *NextBlock = 0; 1372 MachineFunction::iterator BBI = CurMBB; 1373 if (++BBI != CurMBB->getParent()->end()) 1374 NextBlock = BBI; 1375 1376 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1377 if (MBB == NextBlock) 1378 DAG.setRoot(BrRange); 1379 else 1380 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1381 DAG.getBasicBlock(MBB))); 1382 1383 CurMBB->addSuccessor(B.Default); 1384 CurMBB->addSuccessor(MBB); 1385 1386 return; 1387} 1388 1389/// visitBitTestCase - this function produces one "bit test" 1390void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1391 unsigned Reg, 1392 SelectionDAGISel::BitTestCase &B) { 1393 // Emit bit tests and jumps 1394 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1395 1396 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1397 SwitchVal, 1398 DAG.getConstant(B.Mask, 1399 TLI.getPointerTy())); 1400 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, 1401 DAG.getConstant(0, TLI.getPointerTy()), 1402 ISD::SETNE); 1403 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1404 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1405 1406 // Set NextBlock to be the MBB immediately after the current one, if any. 1407 // This is used to avoid emitting unnecessary branches to the next block. 1408 MachineBasicBlock *NextBlock = 0; 1409 MachineFunction::iterator BBI = CurMBB; 1410 if (++BBI != CurMBB->getParent()->end()) 1411 NextBlock = BBI; 1412 1413 if (NextMBB == NextBlock) 1414 DAG.setRoot(BrAnd); 1415 else 1416 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1417 DAG.getBasicBlock(NextMBB))); 1418 1419 CurMBB->addSuccessor(B.TargetBB); 1420 CurMBB->addSuccessor(NextMBB); 1421 1422 return; 1423} 1424 1425void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1426 // Retrieve successors. 1427 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1428 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1429 1430 LowerCallTo(I, I.getCalledValue()->getType(), 1431 I.getCallingConv(), 1432 false, 1433 getValue(I.getOperand(0)), 1434 3, LandingPad); 1435 1436 // If the value of the invoke is used outside of its defining block, make it 1437 // available as a virtual register. 1438 if (!I.use_empty()) { 1439 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1440 if (VMI != FuncInfo.ValueMap.end()) 1441 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second)); 1442 } 1443 1444 // Drop into normal successor. 1445 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1446 DAG.getBasicBlock(Return))); 1447 1448 // Update successor info 1449 CurMBB->addSuccessor(Return); 1450 CurMBB->addSuccessor(LandingPad); 1451} 1452 1453void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1454} 1455 1456/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1457/// small case ranges). 1458bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1459 CaseRecVector& WorkList, 1460 Value* SV, 1461 MachineBasicBlock* Default) { 1462 Case& BackCase = *(CR.Range.second-1); 1463 1464 // Size is the number of Cases represented by this range. 1465 unsigned Size = CR.Range.second - CR.Range.first; 1466 if (Size > 3) 1467 return false; 1468 1469 // Get the MachineFunction which holds the current MBB. This is used when 1470 // inserting any additional MBBs necessary to represent the switch. 1471 MachineFunction *CurMF = CurMBB->getParent(); 1472 1473 // Figure out which block is immediately after the current one. 1474 MachineBasicBlock *NextBlock = 0; 1475 MachineFunction::iterator BBI = CR.CaseBB; 1476 1477 if (++BBI != CurMBB->getParent()->end()) 1478 NextBlock = BBI; 1479 1480 // TODO: If any two of the cases has the same destination, and if one value 1481 // is the same as the other, but has one bit unset that the other has set, 1482 // use bit manipulation to do two compares at once. For example: 1483 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1484 1485 // Rearrange the case blocks so that the last one falls through if possible. 1486 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1487 // The last case block won't fall through into 'NextBlock' if we emit the 1488 // branches in this order. See if rearranging a case value would help. 1489 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1490 if (I->BB == NextBlock) { 1491 std::swap(*I, BackCase); 1492 break; 1493 } 1494 } 1495 } 1496 1497 // Create a CaseBlock record representing a conditional branch to 1498 // the Case's target mbb if the value being switched on SV is equal 1499 // to C. 1500 MachineBasicBlock *CurBlock = CR.CaseBB; 1501 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1502 MachineBasicBlock *FallThrough; 1503 if (I != E-1) { 1504 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1505 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1506 } else { 1507 // If the last case doesn't match, go to the default block. 1508 FallThrough = Default; 1509 } 1510 1511 Value *RHS, *LHS, *MHS; 1512 ISD::CondCode CC; 1513 if (I->High == I->Low) { 1514 // This is just small small case range :) containing exactly 1 case 1515 CC = ISD::SETEQ; 1516 LHS = SV; RHS = I->High; MHS = NULL; 1517 } else { 1518 CC = ISD::SETLE; 1519 LHS = I->Low; MHS = SV; RHS = I->High; 1520 } 1521 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1522 I->BB, FallThrough, CurBlock); 1523 1524 // If emitting the first comparison, just call visitSwitchCase to emit the 1525 // code into the current block. Otherwise, push the CaseBlock onto the 1526 // vector to be later processed by SDISel, and insert the node's MBB 1527 // before the next MBB. 1528 if (CurBlock == CurMBB) 1529 visitSwitchCase(CB); 1530 else 1531 SwitchCases.push_back(CB); 1532 1533 CurBlock = FallThrough; 1534 } 1535 1536 return true; 1537} 1538 1539static inline bool areJTsAllowed(const TargetLowering &TLI) { 1540 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1541 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1542} 1543 1544/// handleJTSwitchCase - Emit jumptable for current switch case range 1545bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1546 CaseRecVector& WorkList, 1547 Value* SV, 1548 MachineBasicBlock* Default) { 1549 Case& FrontCase = *CR.Range.first; 1550 Case& BackCase = *(CR.Range.second-1); 1551 1552 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1553 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1554 1555 uint64_t TSize = 0; 1556 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1557 I!=E; ++I) 1558 TSize += I->size(); 1559 1560 if (!areJTsAllowed(TLI) || TSize <= 3) 1561 return false; 1562 1563 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1564 if (Density < 0.4) 1565 return false; 1566 1567 DOUT << "Lowering jump table\n" 1568 << "First entry: " << First << ". Last entry: " << Last << "\n" 1569 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1570 1571 // Get the MachineFunction which holds the current MBB. This is used when 1572 // inserting any additional MBBs necessary to represent the switch. 1573 MachineFunction *CurMF = CurMBB->getParent(); 1574 1575 // Figure out which block is immediately after the current one. 1576 MachineBasicBlock *NextBlock = 0; 1577 MachineFunction::iterator BBI = CR.CaseBB; 1578 1579 if (++BBI != CurMBB->getParent()->end()) 1580 NextBlock = BBI; 1581 1582 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1583 1584 // Create a new basic block to hold the code for loading the address 1585 // of the jump table, and jumping to it. Update successor information; 1586 // we will either branch to the default case for the switch, or the jump 1587 // table. 1588 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1589 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1590 CR.CaseBB->addSuccessor(Default); 1591 CR.CaseBB->addSuccessor(JumpTableBB); 1592 1593 // Build a vector of destination BBs, corresponding to each target 1594 // of the jump table. If the value of the jump table slot corresponds to 1595 // a case statement, push the case's BB onto the vector, otherwise, push 1596 // the default BB. 1597 std::vector<MachineBasicBlock*> DestBBs; 1598 int64_t TEI = First; 1599 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1600 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1601 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1602 1603 if ((Low <= TEI) && (TEI <= High)) { 1604 DestBBs.push_back(I->BB); 1605 if (TEI==High) 1606 ++I; 1607 } else { 1608 DestBBs.push_back(Default); 1609 } 1610 } 1611 1612 // Update successor info. Add one edge to each unique successor. 1613 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1614 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1615 E = DestBBs.end(); I != E; ++I) { 1616 if (!SuccsHandled[(*I)->getNumber()]) { 1617 SuccsHandled[(*I)->getNumber()] = true; 1618 JumpTableBB->addSuccessor(*I); 1619 } 1620 } 1621 1622 // Create a jump table index for this jump table, or return an existing 1623 // one. 1624 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1625 1626 // Set the jump table information so that we can codegen it as a second 1627 // MachineBasicBlock 1628 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1629 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1630 (CR.CaseBB == CurMBB)); 1631 if (CR.CaseBB == CurMBB) 1632 visitJumpTableHeader(JT, JTH); 1633 1634 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1635 1636 return true; 1637} 1638 1639/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1640/// 2 subtrees. 1641bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1642 CaseRecVector& WorkList, 1643 Value* SV, 1644 MachineBasicBlock* Default) { 1645 // Get the MachineFunction which holds the current MBB. This is used when 1646 // inserting any additional MBBs necessary to represent the switch. 1647 MachineFunction *CurMF = CurMBB->getParent(); 1648 1649 // Figure out which block is immediately after the current one. 1650 MachineBasicBlock *NextBlock = 0; 1651 MachineFunction::iterator BBI = CR.CaseBB; 1652 1653 if (++BBI != CurMBB->getParent()->end()) 1654 NextBlock = BBI; 1655 1656 Case& FrontCase = *CR.Range.first; 1657 Case& BackCase = *(CR.Range.second-1); 1658 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1659 1660 // Size is the number of Cases represented by this range. 1661 unsigned Size = CR.Range.second - CR.Range.first; 1662 1663 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1664 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1665 double FMetric = 0; 1666 CaseItr Pivot = CR.Range.first + Size/2; 1667 1668 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1669 // (heuristically) allow us to emit JumpTable's later. 1670 uint64_t TSize = 0; 1671 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1672 I!=E; ++I) 1673 TSize += I->size(); 1674 1675 uint64_t LSize = FrontCase.size(); 1676 uint64_t RSize = TSize-LSize; 1677 DOUT << "Selecting best pivot: \n" 1678 << "First: " << First << ", Last: " << Last <<"\n" 1679 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1680 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1681 J!=E; ++I, ++J) { 1682 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1683 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1684 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1685 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1686 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1687 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1688 // Should always split in some non-trivial place 1689 DOUT <<"=>Step\n" 1690 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1691 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1692 << "Metric: " << Metric << "\n"; 1693 if (FMetric < Metric) { 1694 Pivot = J; 1695 FMetric = Metric; 1696 DOUT << "Current metric set to: " << FMetric << "\n"; 1697 } 1698 1699 LSize += J->size(); 1700 RSize -= J->size(); 1701 } 1702 if (areJTsAllowed(TLI)) { 1703 // If our case is dense we *really* should handle it earlier! 1704 assert((FMetric > 0) && "Should handle dense range earlier!"); 1705 } else { 1706 Pivot = CR.Range.first + Size/2; 1707 } 1708 1709 CaseRange LHSR(CR.Range.first, Pivot); 1710 CaseRange RHSR(Pivot, CR.Range.second); 1711 Constant *C = Pivot->Low; 1712 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1713 1714 // We know that we branch to the LHS if the Value being switched on is 1715 // less than the Pivot value, C. We use this to optimize our binary 1716 // tree a bit, by recognizing that if SV is greater than or equal to the 1717 // LHS's Case Value, and that Case Value is exactly one less than the 1718 // Pivot's Value, then we can branch directly to the LHS's Target, 1719 // rather than creating a leaf node for it. 1720 if ((LHSR.second - LHSR.first) == 1 && 1721 LHSR.first->High == CR.GE && 1722 cast<ConstantInt>(C)->getSExtValue() == 1723 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1724 TrueBB = LHSR.first->BB; 1725 } else { 1726 TrueBB = new MachineBasicBlock(LLVMBB); 1727 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1728 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1729 } 1730 1731 // Similar to the optimization above, if the Value being switched on is 1732 // known to be less than the Constant CR.LT, and the current Case Value 1733 // is CR.LT - 1, then we can branch directly to the target block for 1734 // the current Case Value, rather than emitting a RHS leaf node for it. 1735 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1736 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1737 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1738 FalseBB = RHSR.first->BB; 1739 } else { 1740 FalseBB = new MachineBasicBlock(LLVMBB); 1741 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1742 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1743 } 1744 1745 // Create a CaseBlock record representing a conditional branch to 1746 // the LHS node if the value being switched on SV is less than C. 1747 // Otherwise, branch to LHS. 1748 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1749 TrueBB, FalseBB, CR.CaseBB); 1750 1751 if (CR.CaseBB == CurMBB) 1752 visitSwitchCase(CB); 1753 else 1754 SwitchCases.push_back(CB); 1755 1756 return true; 1757} 1758 1759/// handleBitTestsSwitchCase - if current case range has few destination and 1760/// range span less, than machine word bitwidth, encode case range into series 1761/// of masks and emit bit tests with these masks. 1762bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1763 CaseRecVector& WorkList, 1764 Value* SV, 1765 MachineBasicBlock* Default){ 1766 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); 1767 1768 Case& FrontCase = *CR.Range.first; 1769 Case& BackCase = *(CR.Range.second-1); 1770 1771 // Get the MachineFunction which holds the current MBB. This is used when 1772 // inserting any additional MBBs necessary to represent the switch. 1773 MachineFunction *CurMF = CurMBB->getParent(); 1774 1775 unsigned numCmps = 0; 1776 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1777 I!=E; ++I) { 1778 // Single case counts one, case range - two. 1779 if (I->Low == I->High) 1780 numCmps +=1; 1781 else 1782 numCmps +=2; 1783 } 1784 1785 // Count unique destinations 1786 SmallSet<MachineBasicBlock*, 4> Dests; 1787 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1788 Dests.insert(I->BB); 1789 if (Dests.size() > 3) 1790 // Don't bother the code below, if there are too much unique destinations 1791 return false; 1792 } 1793 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1794 << "Total number of comparisons: " << numCmps << "\n"; 1795 1796 // Compute span of values. 1797 Constant* minValue = FrontCase.Low; 1798 Constant* maxValue = BackCase.High; 1799 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1800 cast<ConstantInt>(minValue)->getSExtValue(); 1801 DOUT << "Compare range: " << range << "\n" 1802 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1803 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1804 1805 if (range>=IntPtrBits || 1806 (!(Dests.size() == 1 && numCmps >= 3) && 1807 !(Dests.size() == 2 && numCmps >= 5) && 1808 !(Dests.size() >= 3 && numCmps >= 6))) 1809 return false; 1810 1811 DOUT << "Emitting bit tests\n"; 1812 int64_t lowBound = 0; 1813 1814 // Optimize the case where all the case values fit in a 1815 // word without having to subtract minValue. In this case, 1816 // we can optimize away the subtraction. 1817 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1818 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1819 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1820 } else { 1821 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1822 } 1823 1824 CaseBitsVector CasesBits; 1825 unsigned i, count = 0; 1826 1827 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1828 MachineBasicBlock* Dest = I->BB; 1829 for (i = 0; i < count; ++i) 1830 if (Dest == CasesBits[i].BB) 1831 break; 1832 1833 if (i == count) { 1834 assert((count < 3) && "Too much destinations to test!"); 1835 CasesBits.push_back(CaseBits(0, Dest, 0)); 1836 count++; 1837 } 1838 1839 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1840 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1841 1842 for (uint64_t j = lo; j <= hi; j++) { 1843 CasesBits[i].Mask |= 1ULL << j; 1844 CasesBits[i].Bits++; 1845 } 1846 1847 } 1848 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1849 1850 SelectionDAGISel::BitTestInfo BTC; 1851 1852 // Figure out which block is immediately after the current one. 1853 MachineFunction::iterator BBI = CR.CaseBB; 1854 ++BBI; 1855 1856 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1857 1858 DOUT << "Cases:\n"; 1859 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1860 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1861 << ", BB: " << CasesBits[i].BB << "\n"; 1862 1863 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1864 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1865 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1866 CaseBB, 1867 CasesBits[i].BB)); 1868 } 1869 1870 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 1871 -1U, (CR.CaseBB == CurMBB), 1872 CR.CaseBB, Default, BTC); 1873 1874 if (CR.CaseBB == CurMBB) 1875 visitBitTestHeader(BTB); 1876 1877 BitTestCases.push_back(BTB); 1878 1879 return true; 1880} 1881 1882 1883// Clusterify - Transform simple list of Cases into list of CaseRange's 1884unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 1885 const SwitchInst& SI) { 1886 unsigned numCmps = 0; 1887 1888 // Start with "simple" cases 1889 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 1890 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1891 Cases.push_back(Case(SI.getSuccessorValue(i), 1892 SI.getSuccessorValue(i), 1893 SMBB)); 1894 } 1895 sort(Cases.begin(), Cases.end(), CaseCmp()); 1896 1897 // Merge case into clusters 1898 if (Cases.size()>=2) 1899 // Must recompute end() each iteration because it may be 1900 // invalidated by erase if we hold on to it 1901 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 1902 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 1903 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 1904 MachineBasicBlock* nextBB = J->BB; 1905 MachineBasicBlock* currentBB = I->BB; 1906 1907 // If the two neighboring cases go to the same destination, merge them 1908 // into a single case. 1909 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 1910 I->High = J->High; 1911 J = Cases.erase(J); 1912 } else { 1913 I = J++; 1914 } 1915 } 1916 1917 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1918 if (I->Low != I->High) 1919 // A range counts double, since it requires two compares. 1920 ++numCmps; 1921 } 1922 1923 return numCmps; 1924} 1925 1926void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 1927 // Figure out which block is immediately after the current one. 1928 MachineBasicBlock *NextBlock = 0; 1929 MachineFunction::iterator BBI = CurMBB; 1930 1931 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 1932 1933 // If there is only the default destination, branch to it if it is not the 1934 // next basic block. Otherwise, just fall through. 1935 if (SI.getNumOperands() == 2) { 1936 // Update machine-CFG edges. 1937 1938 // If this is not a fall-through branch, emit the branch. 1939 if (Default != NextBlock) 1940 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1941 DAG.getBasicBlock(Default))); 1942 1943 CurMBB->addSuccessor(Default); 1944 return; 1945 } 1946 1947 // If there are any non-default case statements, create a vector of Cases 1948 // representing each one, and sort the vector so that we can efficiently 1949 // create a binary search tree from them. 1950 CaseVector Cases; 1951 unsigned numCmps = Clusterify(Cases, SI); 1952 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 1953 << ". Total compares: " << numCmps << "\n"; 1954 1955 // Get the Value to be switched on and default basic blocks, which will be 1956 // inserted into CaseBlock records, representing basic blocks in the binary 1957 // search tree. 1958 Value *SV = SI.getOperand(0); 1959 1960 // Push the initial CaseRec onto the worklist 1961 CaseRecVector WorkList; 1962 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1963 1964 while (!WorkList.empty()) { 1965 // Grab a record representing a case range to process off the worklist 1966 CaseRec CR = WorkList.back(); 1967 WorkList.pop_back(); 1968 1969 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 1970 continue; 1971 1972 // If the range has few cases (two or less) emit a series of specific 1973 // tests. 1974 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 1975 continue; 1976 1977 // If the switch has more than 5 blocks, and at least 40% dense, and the 1978 // target supports indirect branches, then emit a jump table rather than 1979 // lowering the switch to a binary tree of conditional branches. 1980 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 1981 continue; 1982 1983 // Emit binary tree. We need to pick a pivot, and push left and right ranges 1984 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 1985 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 1986 } 1987} 1988 1989 1990void SelectionDAGLowering::visitSub(User &I) { 1991 // -0.0 - X --> fneg 1992 const Type *Ty = I.getType(); 1993 if (isa<VectorType>(Ty)) { 1994 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 1995 const VectorType *DestTy = cast<VectorType>(I.getType()); 1996 const Type *ElTy = DestTy->getElementType(); 1997 if (ElTy->isFloatingPoint()) { 1998 unsigned VL = DestTy->getNumElements(); 1999 std::vector<Constant*> NZ(VL, ConstantFP::get(ElTy, -0.0)); 2000 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2001 if (CV == CNZ) { 2002 SDOperand Op2 = getValue(I.getOperand(1)); 2003 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2004 return; 2005 } 2006 } 2007 } 2008 } 2009 if (Ty->isFloatingPoint()) { 2010 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2011 if (CFP->isExactlyValue(-0.0)) { 2012 SDOperand Op2 = getValue(I.getOperand(1)); 2013 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2014 return; 2015 } 2016 } 2017 2018 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2019} 2020 2021void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2022 SDOperand Op1 = getValue(I.getOperand(0)); 2023 SDOperand Op2 = getValue(I.getOperand(1)); 2024 2025 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2026} 2027 2028void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2029 SDOperand Op1 = getValue(I.getOperand(0)); 2030 SDOperand Op2 = getValue(I.getOperand(1)); 2031 2032 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) < 2033 MVT::getSizeInBits(Op2.getValueType())) 2034 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2035 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 2036 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2037 2038 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2039} 2040 2041void SelectionDAGLowering::visitICmp(User &I) { 2042 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2043 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2044 predicate = IC->getPredicate(); 2045 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2046 predicate = ICmpInst::Predicate(IC->getPredicate()); 2047 SDOperand Op1 = getValue(I.getOperand(0)); 2048 SDOperand Op2 = getValue(I.getOperand(1)); 2049 ISD::CondCode Opcode; 2050 switch (predicate) { 2051 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2052 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2053 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2054 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2055 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2056 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2057 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2058 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2059 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2060 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2061 default: 2062 assert(!"Invalid ICmp predicate value"); 2063 Opcode = ISD::SETEQ; 2064 break; 2065 } 2066 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2067} 2068 2069void SelectionDAGLowering::visitFCmp(User &I) { 2070 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2071 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2072 predicate = FC->getPredicate(); 2073 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2074 predicate = FCmpInst::Predicate(FC->getPredicate()); 2075 SDOperand Op1 = getValue(I.getOperand(0)); 2076 SDOperand Op2 = getValue(I.getOperand(1)); 2077 ISD::CondCode Condition, FOC, FPC; 2078 switch (predicate) { 2079 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2080 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2081 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2082 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2083 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2084 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2085 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2086 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 2087 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 2088 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2089 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2090 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2091 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2092 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2093 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2094 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2095 default: 2096 assert(!"Invalid FCmp predicate value"); 2097 FOC = FPC = ISD::SETFALSE; 2098 break; 2099 } 2100 if (FiniteOnlyFPMath()) 2101 Condition = FOC; 2102 else 2103 Condition = FPC; 2104 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2105} 2106 2107void SelectionDAGLowering::visitSelect(User &I) { 2108 SDOperand Cond = getValue(I.getOperand(0)); 2109 SDOperand TrueVal = getValue(I.getOperand(1)); 2110 SDOperand FalseVal = getValue(I.getOperand(2)); 2111 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2112 TrueVal, FalseVal)); 2113} 2114 2115 2116void SelectionDAGLowering::visitTrunc(User &I) { 2117 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2118 SDOperand N = getValue(I.getOperand(0)); 2119 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2120 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2121} 2122 2123void SelectionDAGLowering::visitZExt(User &I) { 2124 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2125 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2126 SDOperand N = getValue(I.getOperand(0)); 2127 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2128 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2129} 2130 2131void SelectionDAGLowering::visitSExt(User &I) { 2132 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2133 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2134 SDOperand N = getValue(I.getOperand(0)); 2135 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2136 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2137} 2138 2139void SelectionDAGLowering::visitFPTrunc(User &I) { 2140 // FPTrunc is never a no-op cast, no need to check 2141 SDOperand N = getValue(I.getOperand(0)); 2142 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2143 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 2144} 2145 2146void SelectionDAGLowering::visitFPExt(User &I){ 2147 // FPTrunc is never a no-op cast, no need to check 2148 SDOperand N = getValue(I.getOperand(0)); 2149 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2150 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2151} 2152 2153void SelectionDAGLowering::visitFPToUI(User &I) { 2154 // FPToUI is never a no-op cast, no need to check 2155 SDOperand N = getValue(I.getOperand(0)); 2156 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2157 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2158} 2159 2160void SelectionDAGLowering::visitFPToSI(User &I) { 2161 // FPToSI is never a no-op cast, no need to check 2162 SDOperand N = getValue(I.getOperand(0)); 2163 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2164 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2165} 2166 2167void SelectionDAGLowering::visitUIToFP(User &I) { 2168 // UIToFP is never a no-op cast, no need to check 2169 SDOperand N = getValue(I.getOperand(0)); 2170 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2171 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2172} 2173 2174void SelectionDAGLowering::visitSIToFP(User &I){ 2175 // UIToFP is never a no-op cast, no need to check 2176 SDOperand N = getValue(I.getOperand(0)); 2177 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2178 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2179} 2180 2181void SelectionDAGLowering::visitPtrToInt(User &I) { 2182 // What to do depends on the size of the integer and the size of the pointer. 2183 // We can either truncate, zero extend, or no-op, accordingly. 2184 SDOperand N = getValue(I.getOperand(0)); 2185 MVT::ValueType SrcVT = N.getValueType(); 2186 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2187 SDOperand Result; 2188 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2189 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2190 else 2191 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2192 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2193 setValue(&I, Result); 2194} 2195 2196void SelectionDAGLowering::visitIntToPtr(User &I) { 2197 // What to do depends on the size of the integer and the size of the pointer. 2198 // We can either truncate, zero extend, or no-op, accordingly. 2199 SDOperand N = getValue(I.getOperand(0)); 2200 MVT::ValueType SrcVT = N.getValueType(); 2201 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2202 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2203 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2204 else 2205 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2206 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2207} 2208 2209void SelectionDAGLowering::visitBitCast(User &I) { 2210 SDOperand N = getValue(I.getOperand(0)); 2211 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2212 2213 // BitCast assures us that source and destination are the same size so this 2214 // is either a BIT_CONVERT or a no-op. 2215 if (DestVT != N.getValueType()) 2216 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2217 else 2218 setValue(&I, N); // noop cast. 2219} 2220 2221void SelectionDAGLowering::visitInsertElement(User &I) { 2222 SDOperand InVec = getValue(I.getOperand(0)); 2223 SDOperand InVal = getValue(I.getOperand(1)); 2224 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2225 getValue(I.getOperand(2))); 2226 2227 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2228 TLI.getValueType(I.getType()), 2229 InVec, InVal, InIdx)); 2230} 2231 2232void SelectionDAGLowering::visitExtractElement(User &I) { 2233 SDOperand InVec = getValue(I.getOperand(0)); 2234 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2235 getValue(I.getOperand(1))); 2236 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2237 TLI.getValueType(I.getType()), InVec, InIdx)); 2238} 2239 2240void SelectionDAGLowering::visitShuffleVector(User &I) { 2241 SDOperand V1 = getValue(I.getOperand(0)); 2242 SDOperand V2 = getValue(I.getOperand(1)); 2243 SDOperand Mask = getValue(I.getOperand(2)); 2244 2245 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2246 TLI.getValueType(I.getType()), 2247 V1, V2, Mask)); 2248} 2249 2250 2251void SelectionDAGLowering::visitGetElementPtr(User &I) { 2252 SDOperand N = getValue(I.getOperand(0)); 2253 const Type *Ty = I.getOperand(0)->getType(); 2254 2255 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2256 OI != E; ++OI) { 2257 Value *Idx = *OI; 2258 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2259 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2260 if (Field) { 2261 // N = N + Offset 2262 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2263 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2264 getIntPtrConstant(Offset)); 2265 } 2266 Ty = StTy->getElementType(Field); 2267 } else { 2268 Ty = cast<SequentialType>(Ty)->getElementType(); 2269 2270 // If this is a constant subscript, handle it quickly. 2271 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2272 if (CI->getZExtValue() == 0) continue; 2273 uint64_t Offs = 2274 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2275 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 2276 continue; 2277 } 2278 2279 // N = N + Idx * ElementSize; 2280 uint64_t ElementSize = TD->getTypeSize(Ty); 2281 SDOperand IdxN = getValue(Idx); 2282 2283 // If the index is smaller or larger than intptr_t, truncate or extend 2284 // it. 2285 if (IdxN.getValueType() < N.getValueType()) { 2286 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2287 } else if (IdxN.getValueType() > N.getValueType()) 2288 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2289 2290 // If this is a multiply by a power of two, turn it into a shl 2291 // immediately. This is a very common case. 2292 if (isPowerOf2_64(ElementSize)) { 2293 unsigned Amt = Log2_64(ElementSize); 2294 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2295 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2296 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2297 continue; 2298 } 2299 2300 SDOperand Scale = getIntPtrConstant(ElementSize); 2301 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2302 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2303 } 2304 } 2305 setValue(&I, N); 2306} 2307 2308void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2309 // If this is a fixed sized alloca in the entry block of the function, 2310 // allocate it statically on the stack. 2311 if (FuncInfo.StaticAllocaMap.count(&I)) 2312 return; // getValue will auto-populate this. 2313 2314 const Type *Ty = I.getAllocatedType(); 2315 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 2316 unsigned Align = 2317 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2318 I.getAlignment()); 2319 2320 SDOperand AllocSize = getValue(I.getArraySize()); 2321 MVT::ValueType IntPtr = TLI.getPointerTy(); 2322 if (IntPtr < AllocSize.getValueType()) 2323 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2324 else if (IntPtr > AllocSize.getValueType()) 2325 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2326 2327 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2328 getIntPtrConstant(TySize)); 2329 2330 // Handle alignment. If the requested alignment is less than or equal to the 2331 // stack alignment, ignore it and round the size of the allocation up to the 2332 // stack alignment size. If the size is greater than the stack alignment, we 2333 // note this in the DYNAMIC_STACKALLOC node. 2334 unsigned StackAlign = 2335 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2336 if (Align <= StackAlign) { 2337 Align = 0; 2338 // Add SA-1 to the size. 2339 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2340 getIntPtrConstant(StackAlign-1)); 2341 // Mask out the low bits for alignment purposes. 2342 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2343 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2344 } 2345 2346 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 2347 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2348 MVT::Other); 2349 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2350 setValue(&I, DSA); 2351 DAG.setRoot(DSA.getValue(1)); 2352 2353 // Inform the Frame Information that we have just allocated a variable-sized 2354 // object. 2355 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2356} 2357 2358void SelectionDAGLowering::visitLoad(LoadInst &I) { 2359 SDOperand Ptr = getValue(I.getOperand(0)); 2360 2361 SDOperand Root; 2362 if (I.isVolatile()) 2363 Root = getRoot(); 2364 else { 2365 // Do not serialize non-volatile loads against each other. 2366 Root = DAG.getRoot(); 2367 } 2368 2369 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2370 Root, I.isVolatile(), I.getAlignment())); 2371} 2372 2373SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2374 const Value *SV, SDOperand Root, 2375 bool isVolatile, 2376 unsigned Alignment) { 2377 SDOperand L = 2378 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2379 isVolatile, Alignment); 2380 2381 if (isVolatile) 2382 DAG.setRoot(L.getValue(1)); 2383 else 2384 PendingLoads.push_back(L.getValue(1)); 2385 2386 return L; 2387} 2388 2389 2390void SelectionDAGLowering::visitStore(StoreInst &I) { 2391 Value *SrcV = I.getOperand(0); 2392 SDOperand Src = getValue(SrcV); 2393 SDOperand Ptr = getValue(I.getOperand(1)); 2394 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2395 I.isVolatile(), I.getAlignment())); 2396} 2397 2398/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot 2399/// access memory and has no other side effects at all. 2400static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) { 2401#define GET_NO_MEMORY_INTRINSICS 2402#include "llvm/Intrinsics.gen" 2403#undef GET_NO_MEMORY_INTRINSICS 2404 return false; 2405} 2406 2407// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't 2408// have any side-effects or if it only reads memory. 2409static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) { 2410#define GET_SIDE_EFFECT_INFO 2411#include "llvm/Intrinsics.gen" 2412#undef GET_SIDE_EFFECT_INFO 2413 return false; 2414} 2415 2416/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2417/// node. 2418void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2419 unsigned Intrinsic) { 2420 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic); 2421 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic); 2422 2423 // Build the operand list. 2424 SmallVector<SDOperand, 8> Ops; 2425 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2426 if (OnlyLoad) { 2427 // We don't need to serialize loads against other loads. 2428 Ops.push_back(DAG.getRoot()); 2429 } else { 2430 Ops.push_back(getRoot()); 2431 } 2432 } 2433 2434 // Add the intrinsic ID as an integer operand. 2435 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2436 2437 // Add all operands of the call to the operand list. 2438 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2439 SDOperand Op = getValue(I.getOperand(i)); 2440 assert(TLI.isTypeLegal(Op.getValueType()) && 2441 "Intrinsic uses a non-legal type?"); 2442 Ops.push_back(Op); 2443 } 2444 2445 std::vector<MVT::ValueType> VTs; 2446 if (I.getType() != Type::VoidTy) { 2447 MVT::ValueType VT = TLI.getValueType(I.getType()); 2448 if (MVT::isVector(VT)) { 2449 const VectorType *DestTy = cast<VectorType>(I.getType()); 2450 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2451 2452 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2453 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2454 } 2455 2456 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2457 VTs.push_back(VT); 2458 } 2459 if (HasChain) 2460 VTs.push_back(MVT::Other); 2461 2462 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2463 2464 // Create the node. 2465 SDOperand Result; 2466 if (!HasChain) 2467 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2468 &Ops[0], Ops.size()); 2469 else if (I.getType() != Type::VoidTy) 2470 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2471 &Ops[0], Ops.size()); 2472 else 2473 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2474 &Ops[0], Ops.size()); 2475 2476 if (HasChain) { 2477 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2478 if (OnlyLoad) 2479 PendingLoads.push_back(Chain); 2480 else 2481 DAG.setRoot(Chain); 2482 } 2483 if (I.getType() != Type::VoidTy) { 2484 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2485 MVT::ValueType VT = TLI.getValueType(PTy); 2486 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 2487 } 2488 setValue(&I, Result); 2489 } 2490} 2491 2492/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 2493static GlobalVariable *ExtractTypeInfo (Value *V) { 2494 V = IntrinsicInst::StripPointerCasts(V); 2495 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 2496 assert (GV || isa<ConstantPointerNull>(V) && 2497 "TypeInfo must be a global variable or NULL"); 2498 return GV; 2499} 2500 2501/// addCatchInfo - Extract the personality and type infos from an eh.selector 2502/// call, and add them to the specified machine basic block. 2503static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 2504 MachineBasicBlock *MBB) { 2505 // Inform the MachineModuleInfo of the personality for this landing pad. 2506 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 2507 assert(CE->getOpcode() == Instruction::BitCast && 2508 isa<Function>(CE->getOperand(0)) && 2509 "Personality should be a function"); 2510 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 2511 2512 // Gather all the type infos for this landing pad and pass them along to 2513 // MachineModuleInfo. 2514 std::vector<GlobalVariable *> TyInfo; 2515 unsigned N = I.getNumOperands(); 2516 2517 for (unsigned i = N - 1; i > 2; --i) { 2518 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 2519 unsigned FilterLength = CI->getZExtValue(); 2520 unsigned FirstCatch = i + FilterLength + 1; 2521 assert (FirstCatch <= N && "Invalid filter length"); 2522 2523 if (FirstCatch < N) { 2524 TyInfo.reserve(N - FirstCatch); 2525 for (unsigned j = FirstCatch; j < N; ++j) 2526 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2527 MMI->addCatchTypeInfo(MBB, TyInfo); 2528 TyInfo.clear(); 2529 } 2530 2531 TyInfo.reserve(FilterLength); 2532 for (unsigned j = i + 1; j < FirstCatch; ++j) 2533 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2534 MMI->addFilterTypeInfo(MBB, TyInfo); 2535 TyInfo.clear(); 2536 2537 N = i; 2538 } 2539 } 2540 2541 if (N > 3) { 2542 TyInfo.reserve(N - 3); 2543 for (unsigned j = 3; j < N; ++j) 2544 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2545 MMI->addCatchTypeInfo(MBB, TyInfo); 2546 } 2547} 2548 2549/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2550/// we want to emit this as a call to a named external function, return the name 2551/// otherwise lower it and return null. 2552const char * 2553SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2554 switch (Intrinsic) { 2555 default: 2556 // By default, turn this into a target intrinsic node. 2557 visitTargetIntrinsic(I, Intrinsic); 2558 return 0; 2559 case Intrinsic::vastart: visitVAStart(I); return 0; 2560 case Intrinsic::vaend: visitVAEnd(I); return 0; 2561 case Intrinsic::vacopy: visitVACopy(I); return 0; 2562 case Intrinsic::returnaddress: 2563 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2564 getValue(I.getOperand(1)))); 2565 return 0; 2566 case Intrinsic::frameaddress: 2567 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2568 getValue(I.getOperand(1)))); 2569 return 0; 2570 case Intrinsic::setjmp: 2571 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2572 break; 2573 case Intrinsic::longjmp: 2574 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2575 break; 2576 case Intrinsic::memcpy_i32: 2577 case Intrinsic::memcpy_i64: 2578 visitMemIntrinsic(I, ISD::MEMCPY); 2579 return 0; 2580 case Intrinsic::memset_i32: 2581 case Intrinsic::memset_i64: 2582 visitMemIntrinsic(I, ISD::MEMSET); 2583 return 0; 2584 case Intrinsic::memmove_i32: 2585 case Intrinsic::memmove_i64: 2586 visitMemIntrinsic(I, ISD::MEMMOVE); 2587 return 0; 2588 2589 case Intrinsic::dbg_stoppoint: { 2590 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2591 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2592 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2593 SDOperand Ops[5]; 2594 2595 Ops[0] = getRoot(); 2596 Ops[1] = getValue(SPI.getLineValue()); 2597 Ops[2] = getValue(SPI.getColumnValue()); 2598 2599 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2600 assert(DD && "Not a debug information descriptor"); 2601 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2602 2603 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2604 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2605 2606 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2607 } 2608 2609 return 0; 2610 } 2611 case Intrinsic::dbg_region_start: { 2612 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2613 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2614 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2615 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2616 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2617 DAG.getConstant(LabelID, MVT::i32))); 2618 } 2619 2620 return 0; 2621 } 2622 case Intrinsic::dbg_region_end: { 2623 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2624 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2625 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2626 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2627 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2628 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2629 } 2630 2631 return 0; 2632 } 2633 case Intrinsic::dbg_func_start: { 2634 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2635 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2636 if (MMI && FSI.getSubprogram() && 2637 MMI->Verify(FSI.getSubprogram())) { 2638 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram()); 2639 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2640 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2641 } 2642 2643 return 0; 2644 } 2645 case Intrinsic::dbg_declare: { 2646 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2647 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2648 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) { 2649 SDOperand AddressOp = getValue(DI.getAddress()); 2650 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 2651 MMI->RecordVariable(DI.getVariable(), FI->getIndex()); 2652 } 2653 2654 return 0; 2655 } 2656 2657 case Intrinsic::eh_exception: { 2658 if (ExceptionHandling) { 2659 if (!CurMBB->isLandingPad()) { 2660 // FIXME: Mark exception register as live in. Hack for PR1508. 2661 unsigned Reg = TLI.getExceptionAddressRegister(); 2662 if (Reg) CurMBB->addLiveIn(Reg); 2663 } 2664 // Insert the EXCEPTIONADDR instruction. 2665 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2666 SDOperand Ops[1]; 2667 Ops[0] = DAG.getRoot(); 2668 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2669 setValue(&I, Op); 2670 DAG.setRoot(Op.getValue(1)); 2671 } else { 2672 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2673 } 2674 return 0; 2675 } 2676 2677 case Intrinsic::eh_selector:{ 2678 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2679 2680 if (ExceptionHandling && MMI) { 2681 if (CurMBB->isLandingPad()) 2682 addCatchInfo(I, MMI, CurMBB); 2683 else { 2684#ifndef NDEBUG 2685 FuncInfo.CatchInfoLost.insert(&I); 2686#endif 2687 // FIXME: Mark exception selector register as live in. Hack for PR1508. 2688 unsigned Reg = TLI.getExceptionSelectorRegister(); 2689 if (Reg) CurMBB->addLiveIn(Reg); 2690 } 2691 2692 // Insert the EHSELECTION instruction. 2693 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2694 SDOperand Ops[2]; 2695 Ops[0] = getValue(I.getOperand(1)); 2696 Ops[1] = getRoot(); 2697 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2698 setValue(&I, Op); 2699 DAG.setRoot(Op.getValue(1)); 2700 } else { 2701 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2702 } 2703 2704 return 0; 2705 } 2706 2707 case Intrinsic::eh_typeid_for: { 2708 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2709 2710 if (MMI) { 2711 // Find the type id for the given typeinfo. 2712 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 2713 2714 unsigned TypeID = MMI->getTypeIDFor(GV); 2715 setValue(&I, DAG.getConstant(TypeID, MVT::i32)); 2716 } else { 2717 // Return something different to eh_selector. 2718 setValue(&I, DAG.getConstant(1, MVT::i32)); 2719 } 2720 2721 return 0; 2722 } 2723 2724 case Intrinsic::sqrt_f32: 2725 case Intrinsic::sqrt_f64: 2726 setValue(&I, DAG.getNode(ISD::FSQRT, 2727 getValue(I.getOperand(1)).getValueType(), 2728 getValue(I.getOperand(1)))); 2729 return 0; 2730 case Intrinsic::powi_f32: 2731 case Intrinsic::powi_f64: 2732 setValue(&I, DAG.getNode(ISD::FPOWI, 2733 getValue(I.getOperand(1)).getValueType(), 2734 getValue(I.getOperand(1)), 2735 getValue(I.getOperand(2)))); 2736 return 0; 2737 case Intrinsic::pcmarker: { 2738 SDOperand Tmp = getValue(I.getOperand(1)); 2739 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2740 return 0; 2741 } 2742 case Intrinsic::readcyclecounter: { 2743 SDOperand Op = getRoot(); 2744 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2745 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2746 &Op, 1); 2747 setValue(&I, Tmp); 2748 DAG.setRoot(Tmp.getValue(1)); 2749 return 0; 2750 } 2751 case Intrinsic::part_select: { 2752 // Currently not implemented: just abort 2753 assert(0 && "part_select intrinsic not implemented"); 2754 abort(); 2755 } 2756 case Intrinsic::part_set: { 2757 // Currently not implemented: just abort 2758 assert(0 && "part_set intrinsic not implemented"); 2759 abort(); 2760 } 2761 case Intrinsic::bswap: 2762 setValue(&I, DAG.getNode(ISD::BSWAP, 2763 getValue(I.getOperand(1)).getValueType(), 2764 getValue(I.getOperand(1)))); 2765 return 0; 2766 case Intrinsic::cttz: { 2767 SDOperand Arg = getValue(I.getOperand(1)); 2768 MVT::ValueType Ty = Arg.getValueType(); 2769 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2770 if (Ty < MVT::i32) 2771 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2772 else if (Ty > MVT::i32) 2773 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2774 setValue(&I, result); 2775 return 0; 2776 } 2777 case Intrinsic::ctlz: { 2778 SDOperand Arg = getValue(I.getOperand(1)); 2779 MVT::ValueType Ty = Arg.getValueType(); 2780 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2781 if (Ty < MVT::i32) 2782 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2783 else if (Ty > MVT::i32) 2784 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2785 setValue(&I, result); 2786 return 0; 2787 } 2788 case Intrinsic::ctpop: { 2789 SDOperand Arg = getValue(I.getOperand(1)); 2790 MVT::ValueType Ty = Arg.getValueType(); 2791 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2792 if (Ty < MVT::i32) 2793 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2794 else if (Ty > MVT::i32) 2795 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2796 setValue(&I, result); 2797 return 0; 2798 } 2799 case Intrinsic::stacksave: { 2800 SDOperand Op = getRoot(); 2801 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2802 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2803 setValue(&I, Tmp); 2804 DAG.setRoot(Tmp.getValue(1)); 2805 return 0; 2806 } 2807 case Intrinsic::stackrestore: { 2808 SDOperand Tmp = getValue(I.getOperand(1)); 2809 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2810 return 0; 2811 } 2812 case Intrinsic::prefetch: 2813 // FIXME: Currently discarding prefetches. 2814 return 0; 2815 2816 case Intrinsic::var_annotation: 2817 // Discard annotate attributes 2818 return 0; 2819 } 2820} 2821 2822 2823void SelectionDAGLowering::LowerCallTo(Instruction &I, 2824 const Type *CalledValueTy, 2825 unsigned CallingConv, 2826 bool IsTailCall, 2827 SDOperand Callee, unsigned OpIdx, 2828 MachineBasicBlock *LandingPad) { 2829 const PointerType *PT = cast<PointerType>(CalledValueTy); 2830 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 2831 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 2832 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2833 unsigned BeginLabel = 0, EndLabel = 0; 2834 2835 TargetLowering::ArgListTy Args; 2836 TargetLowering::ArgListEntry Entry; 2837 Args.reserve(I.getNumOperands()); 2838 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) { 2839 Value *Arg = I.getOperand(i); 2840 SDOperand ArgNode = getValue(Arg); 2841 Entry.Node = ArgNode; Entry.Ty = Arg->getType(); 2842 2843 unsigned attrInd = i - OpIdx + 1; 2844 Entry.isSExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::SExt); 2845 Entry.isZExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ZExt); 2846 Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg); 2847 Entry.isSRet = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet); 2848 Args.push_back(Entry); 2849 } 2850 2851 if (ExceptionHandling && MMI) { 2852 // Insert a label before the invoke call to mark the try range. This can be 2853 // used to detect deletion of the invoke via the MachineModuleInfo. 2854 BeginLabel = MMI->NextLabelID(); 2855 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2856 DAG.getConstant(BeginLabel, MVT::i32))); 2857 } 2858 2859 std::pair<SDOperand,SDOperand> Result = 2860 TLI.LowerCallTo(getRoot(), I.getType(), 2861 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt), 2862 FTy->isVarArg(), CallingConv, IsTailCall, 2863 Callee, Args, DAG); 2864 if (I.getType() != Type::VoidTy) 2865 setValue(&I, Result.first); 2866 DAG.setRoot(Result.second); 2867 2868 if (ExceptionHandling && MMI) { 2869 // Insert a label at the end of the invoke call to mark the try range. This 2870 // can be used to detect deletion of the invoke via the MachineModuleInfo. 2871 EndLabel = MMI->NextLabelID(); 2872 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2873 DAG.getConstant(EndLabel, MVT::i32))); 2874 2875 // Inform MachineModuleInfo of range. 2876 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 2877 } 2878} 2879 2880 2881void SelectionDAGLowering::visitCall(CallInst &I) { 2882 const char *RenameFn = 0; 2883 if (Function *F = I.getCalledFunction()) { 2884 if (F->isDeclaration()) 2885 if (unsigned IID = F->getIntrinsicID()) { 2886 RenameFn = visitIntrinsicCall(I, IID); 2887 if (!RenameFn) 2888 return; 2889 } else { // Not an LLVM intrinsic. 2890 const std::string &Name = F->getName(); 2891 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) { 2892 if (I.getNumOperands() == 3 && // Basic sanity checks. 2893 I.getOperand(1)->getType()->isFloatingPoint() && 2894 I.getType() == I.getOperand(1)->getType() && 2895 I.getType() == I.getOperand(2)->getType()) { 2896 SDOperand LHS = getValue(I.getOperand(1)); 2897 SDOperand RHS = getValue(I.getOperand(2)); 2898 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 2899 LHS, RHS)); 2900 return; 2901 } 2902 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) { 2903 if (I.getNumOperands() == 2 && // Basic sanity checks. 2904 I.getOperand(1)->getType()->isFloatingPoint() && 2905 I.getType() == I.getOperand(1)->getType()) { 2906 SDOperand Tmp = getValue(I.getOperand(1)); 2907 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 2908 return; 2909 } 2910 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) { 2911 if (I.getNumOperands() == 2 && // Basic sanity checks. 2912 I.getOperand(1)->getType()->isFloatingPoint() && 2913 I.getType() == I.getOperand(1)->getType()) { 2914 SDOperand Tmp = getValue(I.getOperand(1)); 2915 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 2916 return; 2917 } 2918 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) { 2919 if (I.getNumOperands() == 2 && // Basic sanity checks. 2920 I.getOperand(1)->getType()->isFloatingPoint() && 2921 I.getType() == I.getOperand(1)->getType()) { 2922 SDOperand Tmp = getValue(I.getOperand(1)); 2923 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 2924 return; 2925 } 2926 } 2927 } 2928 } else if (isa<InlineAsm>(I.getOperand(0))) { 2929 visitInlineAsm(I); 2930 return; 2931 } 2932 2933 SDOperand Callee; 2934 if (!RenameFn) 2935 Callee = getValue(I.getOperand(0)); 2936 else 2937 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 2938 2939 LowerCallTo(I, I.getCalledValue()->getType(), 2940 I.getCallingConv(), 2941 I.isTailCall(), 2942 Callee, 2943 1); 2944} 2945 2946 2947/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 2948/// this value and returns the result as a ValueVT value. This uses 2949/// Chain/Flag as the input and updates them for the output Chain/Flag. 2950/// If the Flag pointer is NULL, no flag is used. 2951SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 2952 SDOperand &Chain, SDOperand *Flag)const{ 2953 // Copy the legal parts from the registers. 2954 unsigned NumParts = Regs.size(); 2955 SmallVector<SDOperand, 8> Parts(NumParts); 2956 for (unsigned i = 0; i != NumParts; ++i) { 2957 SDOperand Part = Flag ? 2958 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) : 2959 DAG.getCopyFromReg(Chain, Regs[i], RegVT); 2960 Chain = Part.getValue(1); 2961 if (Flag) 2962 *Flag = Part.getValue(2); 2963 Parts[i] = Part; 2964 } 2965 2966 // Assemble the legal parts into the final value. 2967 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT); 2968} 2969 2970/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 2971/// specified value into the registers specified by this object. This uses 2972/// Chain/Flag as the input and updates them for the output Chain/Flag. 2973/// If the Flag pointer is NULL, no flag is used. 2974void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 2975 SDOperand &Chain, SDOperand *Flag) const { 2976 // Get the list of the values's legal parts. 2977 unsigned NumParts = Regs.size(); 2978 SmallVector<SDOperand, 8> Parts(NumParts); 2979 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT); 2980 2981 // Copy the parts into the registers. 2982 for (unsigned i = 0; i != NumParts; ++i) { 2983 SDOperand Part = Flag ? 2984 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) : 2985 DAG.getCopyToReg(Chain, Regs[i], Parts[i]); 2986 Chain = Part.getValue(0); 2987 if (Flag) 2988 *Flag = Part.getValue(1); 2989 } 2990} 2991 2992/// AddInlineAsmOperands - Add this value to the specified inlineasm node 2993/// operand list. This adds the code marker and includes the number of 2994/// values added into it. 2995void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 2996 std::vector<SDOperand> &Ops) const { 2997 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 2998 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 2999 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 3000 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 3001} 3002 3003/// isAllocatableRegister - If the specified register is safe to allocate, 3004/// i.e. it isn't a stack pointer or some other special register, return the 3005/// register class for the register. Otherwise, return null. 3006static const TargetRegisterClass * 3007isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3008 const TargetLowering &TLI, const MRegisterInfo *MRI) { 3009 MVT::ValueType FoundVT = MVT::Other; 3010 const TargetRegisterClass *FoundRC = 0; 3011 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 3012 E = MRI->regclass_end(); RCI != E; ++RCI) { 3013 MVT::ValueType ThisVT = MVT::Other; 3014 3015 const TargetRegisterClass *RC = *RCI; 3016 // If none of the the value types for this register class are valid, we 3017 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3018 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3019 I != E; ++I) { 3020 if (TLI.isTypeLegal(*I)) { 3021 // If we have already found this register in a different register class, 3022 // choose the one with the largest VT specified. For example, on 3023 // PowerPC, we favor f64 register classes over f32. 3024 if (FoundVT == MVT::Other || 3025 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 3026 ThisVT = *I; 3027 break; 3028 } 3029 } 3030 } 3031 3032 if (ThisVT == MVT::Other) continue; 3033 3034 // NOTE: This isn't ideal. In particular, this might allocate the 3035 // frame pointer in functions that need it (due to them not being taken 3036 // out of allocation, because a variable sized allocation hasn't been seen 3037 // yet). This is a slight code pessimization, but should still work. 3038 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3039 E = RC->allocation_order_end(MF); I != E; ++I) 3040 if (*I == Reg) { 3041 // We found a matching register class. Keep looking at others in case 3042 // we find one with larger registers that this physreg is also in. 3043 FoundRC = RC; 3044 FoundVT = ThisVT; 3045 break; 3046 } 3047 } 3048 return FoundRC; 3049} 3050 3051 3052namespace { 3053/// AsmOperandInfo - This contains information for each constraint that we are 3054/// lowering. 3055struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 3056 /// ConstraintCode - This contains the actual string for the code, like "m". 3057 std::string ConstraintCode; 3058 3059 /// ConstraintType - Information about the constraint code, e.g. Register, 3060 /// RegisterClass, Memory, Other, Unknown. 3061 TargetLowering::ConstraintType ConstraintType; 3062 3063 /// CallOperand/CallOperandval - If this is the result output operand or a 3064 /// clobber, this is null, otherwise it is the incoming operand to the 3065 /// CallInst. This gets modified as the asm is processed. 3066 SDOperand CallOperand; 3067 Value *CallOperandVal; 3068 3069 /// ConstraintVT - The ValueType for the operand value. 3070 MVT::ValueType ConstraintVT; 3071 3072 /// AssignedRegs - If this is a register or register class operand, this 3073 /// contains the set of register corresponding to the operand. 3074 RegsForValue AssignedRegs; 3075 3076 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3077 : InlineAsm::ConstraintInfo(info), 3078 ConstraintType(TargetLowering::C_Unknown), 3079 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) { 3080 } 3081 3082 void ComputeConstraintToUse(const TargetLowering &TLI); 3083 3084 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3085 /// busy in OutputRegs/InputRegs. 3086 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3087 std::set<unsigned> &OutputRegs, 3088 std::set<unsigned> &InputRegs) const { 3089 if (isOutReg) 3090 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3091 if (isInReg) 3092 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3093 } 3094}; 3095} // end anon namespace. 3096 3097/// getConstraintGenerality - Return an integer indicating how general CT is. 3098static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3099 switch (CT) { 3100 default: assert(0 && "Unknown constraint type!"); 3101 case TargetLowering::C_Other: 3102 case TargetLowering::C_Unknown: 3103 return 0; 3104 case TargetLowering::C_Register: 3105 return 1; 3106 case TargetLowering::C_RegisterClass: 3107 return 2; 3108 case TargetLowering::C_Memory: 3109 return 3; 3110 } 3111} 3112 3113void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) { 3114 assert(!Codes.empty() && "Must have at least one constraint"); 3115 3116 std::string *Current = &Codes[0]; 3117 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current); 3118 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common. 3119 ConstraintCode = *Current; 3120 ConstraintType = CurType; 3121 return; 3122 } 3123 3124 unsigned CurGenerality = getConstraintGenerality(CurType); 3125 3126 // If we have multiple constraints, try to pick the most general one ahead 3127 // of time. This isn't a wonderful solution, but handles common cases. 3128 for (unsigned j = 1, e = Codes.size(); j != e; ++j) { 3129 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]); 3130 unsigned ThisGenerality = getConstraintGenerality(ThisType); 3131 if (ThisGenerality > CurGenerality) { 3132 // This constraint letter is more general than the previous one, 3133 // use it. 3134 CurType = ThisType; 3135 Current = &Codes[j]; 3136 CurGenerality = ThisGenerality; 3137 } 3138 } 3139 3140 ConstraintCode = *Current; 3141 ConstraintType = CurType; 3142} 3143 3144 3145void SelectionDAGLowering:: 3146GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 3147 std::set<unsigned> &OutputRegs, 3148 std::set<unsigned> &InputRegs) { 3149 // Compute whether this value requires an input register, an output register, 3150 // or both. 3151 bool isOutReg = false; 3152 bool isInReg = false; 3153 switch (OpInfo.Type) { 3154 case InlineAsm::isOutput: 3155 isOutReg = true; 3156 3157 // If this is an early-clobber output, or if there is an input 3158 // constraint that matches this, we need to reserve the input register 3159 // so no other inputs allocate to it. 3160 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3161 break; 3162 case InlineAsm::isInput: 3163 isInReg = true; 3164 isOutReg = false; 3165 break; 3166 case InlineAsm::isClobber: 3167 isOutReg = true; 3168 isInReg = true; 3169 break; 3170 } 3171 3172 3173 MachineFunction &MF = DAG.getMachineFunction(); 3174 std::vector<unsigned> Regs; 3175 3176 // If this is a constraint for a single physreg, or a constraint for a 3177 // register class, find it. 3178 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3179 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3180 OpInfo.ConstraintVT); 3181 3182 unsigned NumRegs = 1; 3183 if (OpInfo.ConstraintVT != MVT::Other) 3184 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3185 MVT::ValueType RegVT; 3186 MVT::ValueType ValueVT = OpInfo.ConstraintVT; 3187 3188 3189 // If this is a constraint for a specific physical register, like {r17}, 3190 // assign it now. 3191 if (PhysReg.first) { 3192 if (OpInfo.ConstraintVT == MVT::Other) 3193 ValueVT = *PhysReg.second->vt_begin(); 3194 3195 // Get the actual register value type. This is important, because the user 3196 // may have asked for (e.g.) the AX register in i32 type. We need to 3197 // remember that AX is actually i16 to get the right extension. 3198 RegVT = *PhysReg.second->vt_begin(); 3199 3200 // This is a explicit reference to a physical register. 3201 Regs.push_back(PhysReg.first); 3202 3203 // If this is an expanded reference, add the rest of the regs to Regs. 3204 if (NumRegs != 1) { 3205 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3206 TargetRegisterClass::iterator E = PhysReg.second->end(); 3207 for (; *I != PhysReg.first; ++I) 3208 assert(I != E && "Didn't find reg!"); 3209 3210 // Already added the first reg. 3211 --NumRegs; ++I; 3212 for (; NumRegs; --NumRegs, ++I) { 3213 assert(I != E && "Ran out of registers to allocate!"); 3214 Regs.push_back(*I); 3215 } 3216 } 3217 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3218 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3219 return; 3220 } 3221 3222 // Otherwise, if this was a reference to an LLVM register class, create vregs 3223 // for this reference. 3224 std::vector<unsigned> RegClassRegs; 3225 const TargetRegisterClass *RC = PhysReg.second; 3226 if (RC) { 3227 // If this is an early clobber or tied register, our regalloc doesn't know 3228 // how to maintain the constraint. If it isn't, go ahead and create vreg 3229 // and let the regalloc do the right thing. 3230 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 3231 // If there is some other early clobber and this is an input register, 3232 // then we are forced to pre-allocate the input reg so it doesn't 3233 // conflict with the earlyclobber. 3234 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 3235 RegVT = *PhysReg.second->vt_begin(); 3236 3237 if (OpInfo.ConstraintVT == MVT::Other) 3238 ValueVT = RegVT; 3239 3240 // Create the appropriate number of virtual registers. 3241 SSARegMap *RegMap = MF.getSSARegMap(); 3242 for (; NumRegs; --NumRegs) 3243 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second)); 3244 3245 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3246 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3247 return; 3248 } 3249 3250 // Otherwise, we can't allocate it. Let the code below figure out how to 3251 // maintain these constraints. 3252 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3253 3254 } else { 3255 // This is a reference to a register class that doesn't directly correspond 3256 // to an LLVM register class. Allocate NumRegs consecutive, available, 3257 // registers from the class. 3258 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3259 OpInfo.ConstraintVT); 3260 } 3261 3262 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 3263 unsigned NumAllocated = 0; 3264 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3265 unsigned Reg = RegClassRegs[i]; 3266 // See if this register is available. 3267 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3268 (isInReg && InputRegs.count(Reg))) { // Already used. 3269 // Make sure we find consecutive registers. 3270 NumAllocated = 0; 3271 continue; 3272 } 3273 3274 // Check to see if this register is allocatable (i.e. don't give out the 3275 // stack pointer). 3276 if (RC == 0) { 3277 RC = isAllocatableRegister(Reg, MF, TLI, MRI); 3278 if (!RC) { // Couldn't allocate this register. 3279 // Reset NumAllocated to make sure we return consecutive registers. 3280 NumAllocated = 0; 3281 continue; 3282 } 3283 } 3284 3285 // Okay, this register is good, we can use it. 3286 ++NumAllocated; 3287 3288 // If we allocated enough consecutive registers, succeed. 3289 if (NumAllocated == NumRegs) { 3290 unsigned RegStart = (i-NumAllocated)+1; 3291 unsigned RegEnd = i+1; 3292 // Mark all of the allocated registers used. 3293 for (unsigned i = RegStart; i != RegEnd; ++i) 3294 Regs.push_back(RegClassRegs[i]); 3295 3296 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 3297 OpInfo.ConstraintVT); 3298 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3299 return; 3300 } 3301 } 3302 3303 // Otherwise, we couldn't allocate enough registers for this. 3304 return; 3305} 3306 3307 3308/// visitInlineAsm - Handle a call to an InlineAsm object. 3309/// 3310void SelectionDAGLowering::visitInlineAsm(CallInst &I) { 3311 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0)); 3312 3313 /// ConstraintOperands - Information about all of the constraints. 3314 std::vector<AsmOperandInfo> ConstraintOperands; 3315 3316 SDOperand Chain = getRoot(); 3317 SDOperand Flag; 3318 3319 std::set<unsigned> OutputRegs, InputRegs; 3320 3321 // Do a prepass over the constraints, canonicalizing them, and building up the 3322 // ConstraintOperands list. 3323 std::vector<InlineAsm::ConstraintInfo> 3324 ConstraintInfos = IA->ParseConstraints(); 3325 3326 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 3327 // constraint. If so, we can't let the register allocator allocate any input 3328 // registers, because it will not know to avoid the earlyclobbered output reg. 3329 bool SawEarlyClobber = false; 3330 3331 unsigned OpNo = 1; // OpNo - The operand of the CallInst. 3332 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3333 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 3334 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 3335 3336 MVT::ValueType OpVT = MVT::Other; 3337 3338 // Compute the value type for each operand. 3339 switch (OpInfo.Type) { 3340 case InlineAsm::isOutput: 3341 if (!OpInfo.isIndirect) { 3342 // The return value of the call is this value. As such, there is no 3343 // corresponding argument. 3344 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3345 OpVT = TLI.getValueType(I.getType()); 3346 } else { 3347 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3348 } 3349 break; 3350 case InlineAsm::isInput: 3351 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3352 break; 3353 case InlineAsm::isClobber: 3354 // Nothing to do. 3355 break; 3356 } 3357 3358 // If this is an input or an indirect output, process the call argument. 3359 if (OpInfo.CallOperandVal) { 3360 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 3361 const Type *OpTy = OpInfo.CallOperandVal->getType(); 3362 // If this is an indirect operand, the operand is a pointer to the 3363 // accessed type. 3364 if (OpInfo.isIndirect) 3365 OpTy = cast<PointerType>(OpTy)->getElementType(); 3366 3367 // If OpTy is not a first-class value, it may be a struct/union that we 3368 // can tile with integers. 3369 if (!OpTy->isFirstClassType() && OpTy->isSized()) { 3370 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3371 switch (BitSize) { 3372 default: break; 3373 case 1: 3374 case 8: 3375 case 16: 3376 case 32: 3377 case 64: 3378 OpTy = IntegerType::get(BitSize); 3379 break; 3380 } 3381 } 3382 3383 OpVT = TLI.getValueType(OpTy, true); 3384 } 3385 3386 OpInfo.ConstraintVT = OpVT; 3387 3388 // Compute the constraint code and ConstraintType to use. 3389 OpInfo.ComputeConstraintToUse(TLI); 3390 3391 // Keep track of whether we see an earlyclobber. 3392 SawEarlyClobber |= OpInfo.isEarlyClobber; 3393 3394 // If this is a memory input, and if the operand is not indirect, do what we 3395 // need to to provide an address for the memory input. 3396 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 3397 !OpInfo.isIndirect) { 3398 assert(OpInfo.Type == InlineAsm::isInput && 3399 "Can only indirectify direct input operands!"); 3400 3401 // Memory operands really want the address of the value. If we don't have 3402 // an indirect input, put it in the constpool if we can, otherwise spill 3403 // it to a stack slot. 3404 3405 // If the operand is a float, integer, or vector constant, spill to a 3406 // constant pool entry to get its address. 3407 Value *OpVal = OpInfo.CallOperandVal; 3408 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 3409 isa<ConstantVector>(OpVal)) { 3410 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 3411 TLI.getPointerTy()); 3412 } else { 3413 // Otherwise, create a stack slot and emit a store to it before the 3414 // asm. 3415 const Type *Ty = OpVal->getType(); 3416 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3417 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3418 MachineFunction &MF = DAG.getMachineFunction(); 3419 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3420 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3421 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 3422 OpInfo.CallOperand = StackSlot; 3423 } 3424 3425 // There is no longer a Value* corresponding to this operand. 3426 OpInfo.CallOperandVal = 0; 3427 // It is now an indirect operand. 3428 OpInfo.isIndirect = true; 3429 } 3430 3431 // If this constraint is for a specific register, allocate it before 3432 // anything else. 3433 if (OpInfo.ConstraintType == TargetLowering::C_Register) 3434 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3435 } 3436 ConstraintInfos.clear(); 3437 3438 3439 // Second pass - Loop over all of the operands, assigning virtual or physregs 3440 // to registerclass operands. 3441 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3442 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3443 3444 // C_Register operands have already been allocated, Other/Memory don't need 3445 // to be. 3446 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 3447 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3448 } 3449 3450 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 3451 std::vector<SDOperand> AsmNodeOperands; 3452 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3453 AsmNodeOperands.push_back( 3454 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 3455 3456 3457 // Loop over all of the inputs, copying the operand values into the 3458 // appropriate registers and processing the output regs. 3459 RegsForValue RetValRegs; 3460 3461 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 3462 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3463 3464 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3465 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3466 3467 switch (OpInfo.Type) { 3468 case InlineAsm::isOutput: { 3469 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 3470 OpInfo.ConstraintType != TargetLowering::C_Register) { 3471 // Memory output, or 'other' output (e.g. 'X' constraint). 3472 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 3473 3474 // Add information to the INLINEASM node to know about this output. 3475 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3476 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3477 TLI.getPointerTy())); 3478 AsmNodeOperands.push_back(OpInfo.CallOperand); 3479 break; 3480 } 3481 3482 // Otherwise, this is a register or register class output. 3483 3484 // Copy the output from the appropriate register. Find a register that 3485 // we can use. 3486 if (OpInfo.AssignedRegs.Regs.empty()) { 3487 cerr << "Couldn't allocate output reg for contraint '" 3488 << OpInfo.ConstraintCode << "'!\n"; 3489 exit(1); 3490 } 3491 3492 if (!OpInfo.isIndirect) { 3493 // This is the result value of the call. 3494 assert(RetValRegs.Regs.empty() && 3495 "Cannot have multiple output constraints yet!"); 3496 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3497 RetValRegs = OpInfo.AssignedRegs; 3498 } else { 3499 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 3500 OpInfo.CallOperandVal)); 3501 } 3502 3503 // Add information to the INLINEASM node to know that this register is 3504 // set. 3505 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 3506 AsmNodeOperands); 3507 break; 3508 } 3509 case InlineAsm::isInput: { 3510 SDOperand InOperandVal = OpInfo.CallOperand; 3511 3512 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 3513 // If this is required to match an output register we have already set, 3514 // just use its register. 3515 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 3516 3517 // Scan until we find the definition we already emitted of this operand. 3518 // When we find it, create a RegsForValue operand. 3519 unsigned CurOp = 2; // The first operand. 3520 for (; OperandNo; --OperandNo) { 3521 // Advance to the next operand. 3522 unsigned NumOps = 3523 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3524 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3525 (NumOps & 7) == 4 /*MEM*/) && 3526 "Skipped past definitions?"); 3527 CurOp += (NumOps>>3)+1; 3528 } 3529 3530 unsigned NumOps = 3531 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3532 if ((NumOps & 7) == 2 /*REGDEF*/) { 3533 // Add NumOps>>3 registers to MatchedRegs. 3534 RegsForValue MatchedRegs; 3535 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3536 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3537 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3538 unsigned Reg = 3539 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3540 MatchedRegs.Regs.push_back(Reg); 3541 } 3542 3543 // Use the produced MatchedRegs object to 3544 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3545 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3546 break; 3547 } else { 3548 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3549 assert(0 && "matching constraints for memory operands unimp"); 3550 } 3551 } 3552 3553 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 3554 assert(!OpInfo.isIndirect && 3555 "Don't know how to handle indirect other inputs yet!"); 3556 3557 InOperandVal = TLI.isOperandValidForConstraint(InOperandVal, 3558 OpInfo.ConstraintCode[0], 3559 DAG); 3560 if (!InOperandVal.Val) { 3561 cerr << "Invalid operand for inline asm constraint '" 3562 << OpInfo.ConstraintCode << "'!\n"; 3563 exit(1); 3564 } 3565 3566 // Add information to the INLINEASM node to know about this input. 3567 unsigned ResOpType = 3 /*IMM*/ | (1 << 3); 3568 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3569 TLI.getPointerTy())); 3570 AsmNodeOperands.push_back(InOperandVal); 3571 break; 3572 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 3573 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 3574 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 3575 "Memory operands expect pointer values"); 3576 3577 // Add information to the INLINEASM node to know about this input. 3578 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3579 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3580 TLI.getPointerTy())); 3581 AsmNodeOperands.push_back(InOperandVal); 3582 break; 3583 } 3584 3585 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 3586 OpInfo.ConstraintType == TargetLowering::C_Register) && 3587 "Unknown constraint type!"); 3588 assert(!OpInfo.isIndirect && 3589 "Don't know how to handle indirect register inputs yet!"); 3590 3591 // Copy the input into the appropriate registers. 3592 assert(!OpInfo.AssignedRegs.Regs.empty() && 3593 "Couldn't allocate input reg!"); 3594 3595 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3596 3597 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 3598 AsmNodeOperands); 3599 break; 3600 } 3601 case InlineAsm::isClobber: { 3602 // Add the clobbered value to the operand list, so that the register 3603 // allocator is aware that the physreg got clobbered. 3604 if (!OpInfo.AssignedRegs.Regs.empty()) 3605 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 3606 AsmNodeOperands); 3607 break; 3608 } 3609 } 3610 } 3611 3612 // Finish up input operands. 3613 AsmNodeOperands[0] = Chain; 3614 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3615 3616 Chain = DAG.getNode(ISD::INLINEASM, 3617 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3618 &AsmNodeOperands[0], AsmNodeOperands.size()); 3619 Flag = Chain.getValue(1); 3620 3621 // If this asm returns a register value, copy the result from that register 3622 // and set it as the value of the call. 3623 if (!RetValRegs.Regs.empty()) { 3624 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 3625 3626 // If the result of the inline asm is a vector, it may have the wrong 3627 // width/num elts. Make sure to convert it to the right type with 3628 // bit_convert. 3629 if (MVT::isVector(Val.getValueType())) { 3630 const VectorType *VTy = cast<VectorType>(I.getType()); 3631 MVT::ValueType DesiredVT = TLI.getValueType(VTy); 3632 3633 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val); 3634 } 3635 3636 setValue(&I, Val); 3637 } 3638 3639 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 3640 3641 // Process indirect outputs, first output all of the flagged copies out of 3642 // physregs. 3643 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 3644 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 3645 Value *Ptr = IndirectStoresToEmit[i].second; 3646 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 3647 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 3648 } 3649 3650 // Emit the non-flagged stores from the physregs. 3651 SmallVector<SDOperand, 8> OutChains; 3652 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 3653 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 3654 getValue(StoresToEmit[i].second), 3655 StoresToEmit[i].second, 0)); 3656 if (!OutChains.empty()) 3657 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3658 &OutChains[0], OutChains.size()); 3659 DAG.setRoot(Chain); 3660} 3661 3662 3663void SelectionDAGLowering::visitMalloc(MallocInst &I) { 3664 SDOperand Src = getValue(I.getOperand(0)); 3665 3666 MVT::ValueType IntPtr = TLI.getPointerTy(); 3667 3668 if (IntPtr < Src.getValueType()) 3669 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 3670 else if (IntPtr > Src.getValueType()) 3671 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 3672 3673 // Scale the source by the type size. 3674 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType()); 3675 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 3676 Src, getIntPtrConstant(ElementSize)); 3677 3678 TargetLowering::ArgListTy Args; 3679 TargetLowering::ArgListEntry Entry; 3680 Entry.Node = Src; 3681 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3682 Args.push_back(Entry); 3683 3684 std::pair<SDOperand,SDOperand> Result = 3685 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true, 3686 DAG.getExternalSymbol("malloc", IntPtr), 3687 Args, DAG); 3688 setValue(&I, Result.first); // Pointers always fit in registers 3689 DAG.setRoot(Result.second); 3690} 3691 3692void SelectionDAGLowering::visitFree(FreeInst &I) { 3693 TargetLowering::ArgListTy Args; 3694 TargetLowering::ArgListEntry Entry; 3695 Entry.Node = getValue(I.getOperand(0)); 3696 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3697 Args.push_back(Entry); 3698 MVT::ValueType IntPtr = TLI.getPointerTy(); 3699 std::pair<SDOperand,SDOperand> Result = 3700 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true, 3701 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 3702 DAG.setRoot(Result.second); 3703} 3704 3705// InsertAtEndOfBasicBlock - This method should be implemented by targets that 3706// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 3707// instructions are special in various ways, which require special support to 3708// insert. The specified MachineInstr is created but not inserted into any 3709// basic blocks, and the scheduler passes ownership of it to this method. 3710MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3711 MachineBasicBlock *MBB) { 3712 cerr << "If a target marks an instruction with " 3713 << "'usesCustomDAGSchedInserter', it must implement " 3714 << "TargetLowering::InsertAtEndOfBasicBlock!\n"; 3715 abort(); 3716 return 0; 3717} 3718 3719void SelectionDAGLowering::visitVAStart(CallInst &I) { 3720 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 3721 getValue(I.getOperand(1)), 3722 DAG.getSrcValue(I.getOperand(1)))); 3723} 3724 3725void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 3726 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 3727 getValue(I.getOperand(0)), 3728 DAG.getSrcValue(I.getOperand(0))); 3729 setValue(&I, V); 3730 DAG.setRoot(V.getValue(1)); 3731} 3732 3733void SelectionDAGLowering::visitVAEnd(CallInst &I) { 3734 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 3735 getValue(I.getOperand(1)), 3736 DAG.getSrcValue(I.getOperand(1)))); 3737} 3738 3739void SelectionDAGLowering::visitVACopy(CallInst &I) { 3740 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 3741 getValue(I.getOperand(1)), 3742 getValue(I.getOperand(2)), 3743 DAG.getSrcValue(I.getOperand(1)), 3744 DAG.getSrcValue(I.getOperand(2)))); 3745} 3746 3747/// TargetLowering::LowerArguments - This is the default LowerArguments 3748/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 3749/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 3750/// integrated into SDISel. 3751std::vector<SDOperand> 3752TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 3753 const FunctionType *FTy = F.getFunctionType(); 3754 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 3755 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 3756 std::vector<SDOperand> Ops; 3757 Ops.push_back(DAG.getRoot()); 3758 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 3759 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 3760 3761 // Add one result value for each formal argument. 3762 std::vector<MVT::ValueType> RetVals; 3763 unsigned j = 1; 3764 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 3765 I != E; ++I, ++j) { 3766 MVT::ValueType VT = getValueType(I->getType()); 3767 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3768 unsigned OriginalAlignment = 3769 getTargetData()->getABITypeAlignment(I->getType()); 3770 3771 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 3772 // that is zero extended! 3773 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt)) 3774 Flags &= ~(ISD::ParamFlags::SExt); 3775 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt)) 3776 Flags |= ISD::ParamFlags::SExt; 3777 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg)) 3778 Flags |= ISD::ParamFlags::InReg; 3779 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet)) 3780 Flags |= ISD::ParamFlags::StructReturn; 3781 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ByVal)) 3782 Flags |= ISD::ParamFlags::ByVal; 3783 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs); 3784 3785 switch (getTypeAction(VT)) { 3786 default: assert(0 && "Unknown type action!"); 3787 case Legal: 3788 RetVals.push_back(VT); 3789 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3790 break; 3791 case Promote: 3792 RetVals.push_back(getTypeToTransformTo(VT)); 3793 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3794 break; 3795 case Expand: { 3796 // If this is an illegal type, it needs to be broken up to fit into 3797 // registers. 3798 MVT::ValueType RegisterVT = getRegisterType(VT); 3799 unsigned NumRegs = getNumRegisters(VT); 3800 for (unsigned i = 0; i != NumRegs; ++i) { 3801 RetVals.push_back(RegisterVT); 3802 // if it isn't first piece, alignment must be 1 3803 if (i > 0) 3804 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3805 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3806 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3807 } 3808 break; 3809 } 3810 } 3811 } 3812 3813 RetVals.push_back(MVT::Other); 3814 3815 // Create the node. 3816 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 3817 DAG.getNodeValueTypes(RetVals), RetVals.size(), 3818 &Ops[0], Ops.size()).Val; 3819 unsigned NumArgRegs = Result->getNumValues() - 1; 3820 DAG.setRoot(SDOperand(Result, NumArgRegs)); 3821 3822 // Set up the return result vector. 3823 Ops.clear(); 3824 unsigned i = 0; 3825 unsigned Idx = 1; 3826 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 3827 ++I, ++Idx) { 3828 MVT::ValueType VT = getValueType(I->getType()); 3829 3830 switch (getTypeAction(VT)) { 3831 default: assert(0 && "Unknown type action!"); 3832 case Legal: 3833 Ops.push_back(SDOperand(Result, i++)); 3834 break; 3835 case Promote: { 3836 SDOperand Op(Result, i++); 3837 if (MVT::isInteger(VT)) { 3838 if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt)) 3839 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, 3840 DAG.getValueType(VT)); 3841 else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt)) 3842 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, 3843 DAG.getValueType(VT)); 3844 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3845 } else { 3846 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3847 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 3848 } 3849 Ops.push_back(Op); 3850 break; 3851 } 3852 case Expand: { 3853 MVT::ValueType PartVT = getRegisterType(VT); 3854 unsigned NumParts = getNumRegisters(VT); 3855 SmallVector<SDOperand, 4> Parts(NumParts); 3856 for (unsigned j = 0; j != NumParts; ++j) 3857 Parts[j] = SDOperand(Result, i++); 3858 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT)); 3859 break; 3860 } 3861 } 3862 } 3863 assert(i == NumArgRegs && "Argument register count mismatch!"); 3864 return Ops; 3865} 3866 3867 3868/// TargetLowering::LowerCallTo - This is the default LowerCallTo 3869/// implementation, which just inserts an ISD::CALL node, which is later custom 3870/// lowered by the target to something concrete. FIXME: When all targets are 3871/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 3872std::pair<SDOperand, SDOperand> 3873TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 3874 bool RetTyIsSigned, bool isVarArg, 3875 unsigned CallingConv, bool isTailCall, 3876 SDOperand Callee, 3877 ArgListTy &Args, SelectionDAG &DAG) { 3878 SmallVector<SDOperand, 32> Ops; 3879 Ops.push_back(Chain); // Op#0 - Chain 3880 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 3881 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 3882 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 3883 Ops.push_back(Callee); 3884 3885 // Handle all of the outgoing arguments. 3886 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 3887 MVT::ValueType VT = getValueType(Args[i].Ty); 3888 SDOperand Op = Args[i].Node; 3889 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3890 unsigned OriginalAlignment = 3891 getTargetData()->getABITypeAlignment(Args[i].Ty); 3892 3893 if (Args[i].isSExt) 3894 Flags |= ISD::ParamFlags::SExt; 3895 if (Args[i].isZExt) 3896 Flags |= ISD::ParamFlags::ZExt; 3897 if (Args[i].isInReg) 3898 Flags |= ISD::ParamFlags::InReg; 3899 if (Args[i].isSRet) 3900 Flags |= ISD::ParamFlags::StructReturn; 3901 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs; 3902 3903 switch (getTypeAction(VT)) { 3904 default: assert(0 && "Unknown type action!"); 3905 case Legal: 3906 Ops.push_back(Op); 3907 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3908 break; 3909 case Promote: 3910 if (MVT::isInteger(VT)) { 3911 unsigned ExtOp; 3912 if (Args[i].isSExt) 3913 ExtOp = ISD::SIGN_EXTEND; 3914 else if (Args[i].isZExt) 3915 ExtOp = ISD::ZERO_EXTEND; 3916 else 3917 ExtOp = ISD::ANY_EXTEND; 3918 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 3919 } else { 3920 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3921 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 3922 } 3923 Ops.push_back(Op); 3924 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3925 break; 3926 case Expand: { 3927 MVT::ValueType PartVT = getRegisterType(VT); 3928 unsigned NumParts = getNumRegisters(VT); 3929 SmallVector<SDOperand, 4> Parts(NumParts); 3930 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT); 3931 for (unsigned i = 0; i != NumParts; ++i) { 3932 // if it isn't first piece, alignment must be 1 3933 unsigned MyFlags = Flags; 3934 if (i != 0) 3935 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) | 3936 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3937 3938 Ops.push_back(Parts[i]); 3939 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32)); 3940 } 3941 break; 3942 } 3943 } 3944 } 3945 3946 // Figure out the result value types. 3947 MVT::ValueType VT = getValueType(RetTy); 3948 MVT::ValueType RegisterVT = getRegisterType(VT); 3949 unsigned NumRegs = getNumRegisters(VT); 3950 SmallVector<MVT::ValueType, 4> RetTys(NumRegs); 3951 for (unsigned i = 0; i != NumRegs; ++i) 3952 RetTys[i] = RegisterVT; 3953 3954 RetTys.push_back(MVT::Other); // Always has a chain. 3955 3956 // Create the CALL node. 3957 SDOperand Res = DAG.getNode(ISD::CALL, 3958 DAG.getVTList(&RetTys[0], NumRegs + 1), 3959 &Ops[0], Ops.size()); 3960 SDOperand Chain = Res.getValue(NumRegs); 3961 3962 // Gather up the call result into a single value. 3963 if (RetTy != Type::VoidTy) { 3964 ISD::NodeType AssertOp = ISD::AssertSext; 3965 if (!RetTyIsSigned) 3966 AssertOp = ISD::AssertZext; 3967 SmallVector<SDOperand, 4> Results(NumRegs); 3968 for (unsigned i = 0; i != NumRegs; ++i) 3969 Results[i] = Res.getValue(i); 3970 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp); 3971 } 3972 3973 return std::make_pair(Res, Chain); 3974} 3975 3976SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 3977 assert(0 && "LowerOperation not implemented for this target!"); 3978 abort(); 3979 return SDOperand(); 3980} 3981 3982SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 3983 SelectionDAG &DAG) { 3984 assert(0 && "CustomPromoteOperation not implemented for this target!"); 3985 abort(); 3986 return SDOperand(); 3987} 3988 3989/// getMemsetValue - Vectorized representation of the memset value 3990/// operand. 3991static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 3992 SelectionDAG &DAG) { 3993 MVT::ValueType CurVT = VT; 3994 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 3995 uint64_t Val = C->getValue() & 255; 3996 unsigned Shift = 8; 3997 while (CurVT != MVT::i8) { 3998 Val = (Val << Shift) | Val; 3999 Shift <<= 1; 4000 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4001 } 4002 return DAG.getConstant(Val, VT); 4003 } else { 4004 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4005 unsigned Shift = 8; 4006 while (CurVT != MVT::i8) { 4007 Value = 4008 DAG.getNode(ISD::OR, VT, 4009 DAG.getNode(ISD::SHL, VT, Value, 4010 DAG.getConstant(Shift, MVT::i8)), Value); 4011 Shift <<= 1; 4012 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4013 } 4014 4015 return Value; 4016 } 4017} 4018 4019/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4020/// used when a memcpy is turned into a memset when the source is a constant 4021/// string ptr. 4022static SDOperand getMemsetStringVal(MVT::ValueType VT, 4023 SelectionDAG &DAG, TargetLowering &TLI, 4024 std::string &Str, unsigned Offset) { 4025 uint64_t Val = 0; 4026 unsigned MSB = MVT::getSizeInBits(VT) / 8; 4027 if (TLI.isLittleEndian()) 4028 Offset = Offset + MSB - 1; 4029 for (unsigned i = 0; i != MSB; ++i) { 4030 Val = (Val << 8) | (unsigned char)Str[Offset]; 4031 Offset += TLI.isLittleEndian() ? -1 : 1; 4032 } 4033 return DAG.getConstant(Val, VT); 4034} 4035 4036/// getMemBasePlusOffset - Returns base and offset node for the 4037static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4038 SelectionDAG &DAG, TargetLowering &TLI) { 4039 MVT::ValueType VT = Base.getValueType(); 4040 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4041} 4042 4043/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4044/// to replace the memset / memcpy is below the threshold. It also returns the 4045/// types of the sequence of memory ops to perform memset / memcpy. 4046static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4047 unsigned Limit, uint64_t Size, 4048 unsigned Align, TargetLowering &TLI) { 4049 MVT::ValueType VT; 4050 4051 if (TLI.allowsUnalignedMemoryAccesses()) { 4052 VT = MVT::i64; 4053 } else { 4054 switch (Align & 7) { 4055 case 0: 4056 VT = MVT::i64; 4057 break; 4058 case 4: 4059 VT = MVT::i32; 4060 break; 4061 case 2: 4062 VT = MVT::i16; 4063 break; 4064 default: 4065 VT = MVT::i8; 4066 break; 4067 } 4068 } 4069 4070 MVT::ValueType LVT = MVT::i64; 4071 while (!TLI.isTypeLegal(LVT)) 4072 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4073 assert(MVT::isInteger(LVT)); 4074 4075 if (VT > LVT) 4076 VT = LVT; 4077 4078 unsigned NumMemOps = 0; 4079 while (Size != 0) { 4080 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4081 while (VTSize > Size) { 4082 VT = (MVT::ValueType)((unsigned)VT - 1); 4083 VTSize >>= 1; 4084 } 4085 assert(MVT::isInteger(VT)); 4086 4087 if (++NumMemOps > Limit) 4088 return false; 4089 MemOps.push_back(VT); 4090 Size -= VTSize; 4091 } 4092 4093 return true; 4094} 4095 4096void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4097 SDOperand Op1 = getValue(I.getOperand(1)); 4098 SDOperand Op2 = getValue(I.getOperand(2)); 4099 SDOperand Op3 = getValue(I.getOperand(3)); 4100 SDOperand Op4 = getValue(I.getOperand(4)); 4101 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4102 if (Align == 0) Align = 1; 4103 4104 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4105 std::vector<MVT::ValueType> MemOps; 4106 4107 // Expand memset / memcpy to a series of load / store ops 4108 // if the size operand falls below a certain threshold. 4109 SmallVector<SDOperand, 8> OutChains; 4110 switch (Op) { 4111 default: break; // Do nothing for now. 4112 case ISD::MEMSET: { 4113 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4114 Size->getValue(), Align, TLI)) { 4115 unsigned NumMemOps = MemOps.size(); 4116 unsigned Offset = 0; 4117 for (unsigned i = 0; i < NumMemOps; i++) { 4118 MVT::ValueType VT = MemOps[i]; 4119 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4120 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4121 SDOperand Store = DAG.getStore(getRoot(), Value, 4122 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4123 I.getOperand(1), Offset); 4124 OutChains.push_back(Store); 4125 Offset += VTSize; 4126 } 4127 } 4128 break; 4129 } 4130 case ISD::MEMCPY: { 4131 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4132 Size->getValue(), Align, TLI)) { 4133 unsigned NumMemOps = MemOps.size(); 4134 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4135 GlobalAddressSDNode *G = NULL; 4136 std::string Str; 4137 bool CopyFromStr = false; 4138 4139 if (Op2.getOpcode() == ISD::GlobalAddress) 4140 G = cast<GlobalAddressSDNode>(Op2); 4141 else if (Op2.getOpcode() == ISD::ADD && 4142 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4143 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4144 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4145 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4146 } 4147 if (G) { 4148 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4149 if (GV && GV->isConstant()) { 4150 Str = GV->getStringValue(false); 4151 if (!Str.empty()) { 4152 CopyFromStr = true; 4153 SrcOff += SrcDelta; 4154 } 4155 } 4156 } 4157 4158 for (unsigned i = 0; i < NumMemOps; i++) { 4159 MVT::ValueType VT = MemOps[i]; 4160 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4161 SDOperand Value, Chain, Store; 4162 4163 if (CopyFromStr) { 4164 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4165 Chain = getRoot(); 4166 Store = 4167 DAG.getStore(Chain, Value, 4168 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4169 I.getOperand(1), DstOff); 4170 } else { 4171 Value = DAG.getLoad(VT, getRoot(), 4172 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4173 I.getOperand(2), SrcOff); 4174 Chain = Value.getValue(1); 4175 Store = 4176 DAG.getStore(Chain, Value, 4177 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4178 I.getOperand(1), DstOff); 4179 } 4180 OutChains.push_back(Store); 4181 SrcOff += VTSize; 4182 DstOff += VTSize; 4183 } 4184 } 4185 break; 4186 } 4187 } 4188 4189 if (!OutChains.empty()) { 4190 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4191 &OutChains[0], OutChains.size())); 4192 return; 4193 } 4194 } 4195 4196 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4)); 4197} 4198 4199//===----------------------------------------------------------------------===// 4200// SelectionDAGISel code 4201//===----------------------------------------------------------------------===// 4202 4203unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4204 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 4205} 4206 4207void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4208 AU.addRequired<AliasAnalysis>(); 4209 AU.setPreservesAll(); 4210} 4211 4212 4213 4214bool SelectionDAGISel::runOnFunction(Function &Fn) { 4215 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4216 RegMap = MF.getSSARegMap(); 4217 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4218 4219 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4220 4221 if (ExceptionHandling) 4222 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4223 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4224 // Mark landing pad. 4225 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4226 4227 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4228 SelectBasicBlock(I, MF, FuncInfo); 4229 4230 // Add function live-ins to entry block live-in set. 4231 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4232 BB = FuncInfo.MBBMap[EntryBB]; 4233 if (!MF.livein_empty()) 4234 for (MachineFunction::livein_iterator I = MF.livein_begin(), 4235 E = MF.livein_end(); I != E; ++I) 4236 BB->addLiveIn(I->first); 4237 4238#ifndef NDEBUG 4239 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4240 "Not all catch info was assigned to a landing pad!"); 4241#endif 4242 4243 return true; 4244} 4245 4246SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4247 unsigned Reg) { 4248 SDOperand Op = getValue(V); 4249 assert((Op.getOpcode() != ISD::CopyFromReg || 4250 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4251 "Copy from a reg to the same reg!"); 4252 4253 MVT::ValueType SrcVT = Op.getValueType(); 4254 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT); 4255 unsigned NumRegs = TLI.getNumRegisters(SrcVT); 4256 SmallVector<SDOperand, 8> Regs(NumRegs); 4257 SmallVector<SDOperand, 8> Chains(NumRegs); 4258 4259 // Copy the value by legal parts into sequential virtual registers. 4260 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT); 4261 for (unsigned i = 0; i != NumRegs; ++i) 4262 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); 4263 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 4264} 4265 4266void SelectionDAGISel:: 4267LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4268 std::vector<SDOperand> &UnorderedChains) { 4269 // If this is the entry block, emit arguments. 4270 Function &F = *LLVMBB->getParent(); 4271 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4272 SDOperand OldRoot = SDL.DAG.getRoot(); 4273 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4274 4275 unsigned a = 0; 4276 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4277 AI != E; ++AI, ++a) 4278 if (!AI->use_empty()) { 4279 SDL.setValue(AI, Args[a]); 4280 4281 // If this argument is live outside of the entry block, insert a copy from 4282 // whereever we got it to the vreg that other BB's will reference it as. 4283 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4284 if (VMI != FuncInfo.ValueMap.end()) { 4285 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4286 UnorderedChains.push_back(Copy); 4287 } 4288 } 4289 4290 // Finally, if the target has anything special to do, allow it to do so. 4291 // FIXME: this should insert code into the DAG! 4292 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4293} 4294 4295static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4296 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4297 assert(!FLI.MBBMap[SrcBB]->isLandingPad() && 4298 "Copying catch info out of a landing pad!"); 4299 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4300 if (isSelector(I)) { 4301 // Apply the catch info to DestBB. 4302 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4303#ifndef NDEBUG 4304 FLI.CatchInfoFound.insert(I); 4305#endif 4306 } 4307} 4308 4309void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4310 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4311 FunctionLoweringInfo &FuncInfo) { 4312 SelectionDAGLowering SDL(DAG, TLI, FuncInfo); 4313 4314 std::vector<SDOperand> UnorderedChains; 4315 4316 // Lower any arguments needed in this block if this is the entry block. 4317 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4318 LowerArguments(LLVMBB, SDL, UnorderedChains); 4319 4320 BB = FuncInfo.MBBMap[LLVMBB]; 4321 SDL.setCurrentBasicBlock(BB); 4322 4323 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4324 4325 if (ExceptionHandling && MMI && BB->isLandingPad()) { 4326 // Add a label to mark the beginning of the landing pad. Deletion of the 4327 // landing pad can thus be detected via the MachineModuleInfo. 4328 unsigned LabelID = MMI->addLandingPad(BB); 4329 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 4330 DAG.getConstant(LabelID, MVT::i32))); 4331 4332 // Mark exception register as live in. 4333 unsigned Reg = TLI.getExceptionAddressRegister(); 4334 if (Reg) BB->addLiveIn(Reg); 4335 4336 // Mark exception selector register as live in. 4337 Reg = TLI.getExceptionSelectorRegister(); 4338 if (Reg) BB->addLiveIn(Reg); 4339 4340 // FIXME: Hack around an exception handling flaw (PR1508): the personality 4341 // function and list of typeids logically belong to the invoke (or, if you 4342 // like, the basic block containing the invoke), and need to be associated 4343 // with it in the dwarf exception handling tables. Currently however the 4344 // information is provided by an intrinsic (eh.selector) that can be moved 4345 // to unexpected places by the optimizers: if the unwind edge is critical, 4346 // then breaking it can result in the intrinsics being in the successor of 4347 // the landing pad, not the landing pad itself. This results in exceptions 4348 // not being caught because no typeids are associated with the invoke. 4349 // This may not be the only way things can go wrong, but it is the only way 4350 // we try to work around for the moment. 4351 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 4352 4353 if (Br && Br->isUnconditional()) { // Critical edge? 4354 BasicBlock::iterator I, E; 4355 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 4356 if (isSelector(I)) 4357 break; 4358 4359 if (I == E) 4360 // No catch info found - try to extract some from the successor. 4361 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 4362 } 4363 } 4364 4365 // Lower all of the non-terminator instructions. 4366 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4367 I != E; ++I) 4368 SDL.visit(*I); 4369 4370 // Ensure that all instructions which are used outside of their defining 4371 // blocks are available as virtual registers. Invoke is handled elsewhere. 4372 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4373 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 4374 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4375 if (VMI != FuncInfo.ValueMap.end()) 4376 UnorderedChains.push_back( 4377 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4378 } 4379 4380 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4381 // ensure constants are generated when needed. Remember the virtual registers 4382 // that need to be added to the Machine PHI nodes as input. We cannot just 4383 // directly add them, because expansion might result in multiple MBB's for one 4384 // BB. As such, the start of the BB might correspond to a different MBB than 4385 // the end. 4386 // 4387 TerminatorInst *TI = LLVMBB->getTerminator(); 4388 4389 // Emit constants only once even if used by multiple PHI nodes. 4390 std::map<Constant*, unsigned> ConstantsOut; 4391 4392 // Vector bool would be better, but vector<bool> is really slow. 4393 std::vector<unsigned char> SuccsHandled; 4394 if (TI->getNumSuccessors()) 4395 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4396 4397 // Check successor nodes' PHI nodes that expect a constant to be available 4398 // from this block. 4399 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4400 BasicBlock *SuccBB = TI->getSuccessor(succ); 4401 if (!isa<PHINode>(SuccBB->begin())) continue; 4402 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4403 4404 // If this terminator has multiple identical successors (common for 4405 // switches), only handle each succ once. 4406 unsigned SuccMBBNo = SuccMBB->getNumber(); 4407 if (SuccsHandled[SuccMBBNo]) continue; 4408 SuccsHandled[SuccMBBNo] = true; 4409 4410 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4411 PHINode *PN; 4412 4413 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4414 // nodes and Machine PHI nodes, but the incoming operands have not been 4415 // emitted yet. 4416 for (BasicBlock::iterator I = SuccBB->begin(); 4417 (PN = dyn_cast<PHINode>(I)); ++I) { 4418 // Ignore dead phi's. 4419 if (PN->use_empty()) continue; 4420 4421 unsigned Reg; 4422 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4423 4424 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4425 unsigned &RegOut = ConstantsOut[C]; 4426 if (RegOut == 0) { 4427 RegOut = FuncInfo.CreateRegForValue(C); 4428 UnorderedChains.push_back( 4429 SDL.CopyValueToVirtualRegister(C, RegOut)); 4430 } 4431 Reg = RegOut; 4432 } else { 4433 Reg = FuncInfo.ValueMap[PHIOp]; 4434 if (Reg == 0) { 4435 assert(isa<AllocaInst>(PHIOp) && 4436 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4437 "Didn't codegen value into a register!??"); 4438 Reg = FuncInfo.CreateRegForValue(PHIOp); 4439 UnorderedChains.push_back( 4440 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4441 } 4442 } 4443 4444 // Remember that this register needs to added to the machine PHI node as 4445 // the input for this MBB. 4446 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4447 unsigned NumRegisters = TLI.getNumRegisters(VT); 4448 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 4449 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4450 } 4451 } 4452 ConstantsOut.clear(); 4453 4454 // Turn all of the unordered chains into one factored node. 4455 if (!UnorderedChains.empty()) { 4456 SDOperand Root = SDL.getRoot(); 4457 if (Root.getOpcode() != ISD::EntryToken) { 4458 unsigned i = 0, e = UnorderedChains.size(); 4459 for (; i != e; ++i) { 4460 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4461 if (UnorderedChains[i].Val->getOperand(0) == Root) 4462 break; // Don't add the root if we already indirectly depend on it. 4463 } 4464 4465 if (i == e) 4466 UnorderedChains.push_back(Root); 4467 } 4468 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4469 &UnorderedChains[0], UnorderedChains.size())); 4470 } 4471 4472 // Lower the terminator after the copies are emitted. 4473 SDL.visit(*LLVMBB->getTerminator()); 4474 4475 // Copy over any CaseBlock records that may now exist due to SwitchInst 4476 // lowering, as well as any jump table information. 4477 SwitchCases.clear(); 4478 SwitchCases = SDL.SwitchCases; 4479 JTCases.clear(); 4480 JTCases = SDL.JTCases; 4481 BitTestCases.clear(); 4482 BitTestCases = SDL.BitTestCases; 4483 4484 // Make sure the root of the DAG is up-to-date. 4485 DAG.setRoot(SDL.getRoot()); 4486} 4487 4488void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4489 // Get alias analysis for load/store combining. 4490 AliasAnalysis &AA = getAnalysis<AliasAnalysis>(); 4491 4492 // Run the DAG combiner in pre-legalize mode. 4493 DAG.Combine(false, AA); 4494 4495 DOUT << "Lowered selection DAG:\n"; 4496 DEBUG(DAG.dump()); 4497 4498 // Second step, hack on the DAG until it only uses operations and types that 4499 // the target supports. 4500 DAG.Legalize(); 4501 4502 DOUT << "Legalized selection DAG:\n"; 4503 DEBUG(DAG.dump()); 4504 4505 // Run the DAG combiner in post-legalize mode. 4506 DAG.Combine(true, AA); 4507 4508 if (ViewISelDAGs) DAG.viewGraph(); 4509 4510 // Third, instruction select all of the operations to machine code, adding the 4511 // code to the MachineBasicBlock. 4512 InstructionSelectBasicBlock(DAG); 4513 4514 DOUT << "Selected machine code:\n"; 4515 DEBUG(BB->dump()); 4516} 4517 4518void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4519 FunctionLoweringInfo &FuncInfo) { 4520 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4521 { 4522 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4523 CurDAG = &DAG; 4524 4525 // First step, lower LLVM code to some DAG. This DAG may use operations and 4526 // types that are not supported by the target. 4527 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4528 4529 // Second step, emit the lowered DAG as machine code. 4530 CodeGenAndEmitDAG(DAG); 4531 } 4532 4533 DOUT << "Total amount of phi nodes to update: " 4534 << PHINodesToUpdate.size() << "\n"; 4535 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4536 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4537 << ", " << PHINodesToUpdate[i].second << ")\n";); 4538 4539 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4540 // PHI nodes in successors. 4541 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4542 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4543 MachineInstr *PHI = PHINodesToUpdate[i].first; 4544 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4545 "This is not a machine PHI node that we are updating!"); 4546 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4547 PHI->addMachineBasicBlockOperand(BB); 4548 } 4549 return; 4550 } 4551 4552 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4553 // Lower header first, if it wasn't already lowered 4554 if (!BitTestCases[i].Emitted) { 4555 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4556 CurDAG = &HSDAG; 4557 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo); 4558 // Set the current basic block to the mbb we wish to insert the code into 4559 BB = BitTestCases[i].Parent; 4560 HSDL.setCurrentBasicBlock(BB); 4561 // Emit the code 4562 HSDL.visitBitTestHeader(BitTestCases[i]); 4563 HSDAG.setRoot(HSDL.getRoot()); 4564 CodeGenAndEmitDAG(HSDAG); 4565 } 4566 4567 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4568 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4569 CurDAG = &BSDAG; 4570 SelectionDAGLowering BSDL(BSDAG, TLI, FuncInfo); 4571 // Set the current basic block to the mbb we wish to insert the code into 4572 BB = BitTestCases[i].Cases[j].ThisBB; 4573 BSDL.setCurrentBasicBlock(BB); 4574 // Emit the code 4575 if (j+1 != ej) 4576 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 4577 BitTestCases[i].Reg, 4578 BitTestCases[i].Cases[j]); 4579 else 4580 BSDL.visitBitTestCase(BitTestCases[i].Default, 4581 BitTestCases[i].Reg, 4582 BitTestCases[i].Cases[j]); 4583 4584 4585 BSDAG.setRoot(BSDL.getRoot()); 4586 CodeGenAndEmitDAG(BSDAG); 4587 } 4588 4589 // Update PHI Nodes 4590 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4591 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4592 MachineBasicBlock *PHIBB = PHI->getParent(); 4593 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4594 "This is not a machine PHI node that we are updating!"); 4595 // This is "default" BB. We have two jumps to it. From "header" BB and 4596 // from last "case" BB. 4597 if (PHIBB == BitTestCases[i].Default) { 4598 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4599 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent); 4600 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4601 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB); 4602 } 4603 // One of "cases" BB. 4604 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4605 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 4606 if (cBB->succ_end() != 4607 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 4608 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4609 PHI->addMachineBasicBlockOperand(cBB); 4610 } 4611 } 4612 } 4613 } 4614 4615 // If the JumpTable record is filled in, then we need to emit a jump table. 4616 // Updating the PHI nodes is tricky in this case, since we need to determine 4617 // whether the PHI is a successor of the range check MBB or the jump table MBB 4618 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 4619 // Lower header first, if it wasn't already lowered 4620 if (!JTCases[i].first.Emitted) { 4621 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4622 CurDAG = &HSDAG; 4623 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo); 4624 // Set the current basic block to the mbb we wish to insert the code into 4625 BB = JTCases[i].first.HeaderBB; 4626 HSDL.setCurrentBasicBlock(BB); 4627 // Emit the code 4628 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 4629 HSDAG.setRoot(HSDL.getRoot()); 4630 CodeGenAndEmitDAG(HSDAG); 4631 } 4632 4633 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4634 CurDAG = &JSDAG; 4635 SelectionDAGLowering JSDL(JSDAG, TLI, FuncInfo); 4636 // Set the current basic block to the mbb we wish to insert the code into 4637 BB = JTCases[i].second.MBB; 4638 JSDL.setCurrentBasicBlock(BB); 4639 // Emit the code 4640 JSDL.visitJumpTable(JTCases[i].second); 4641 JSDAG.setRoot(JSDL.getRoot()); 4642 CodeGenAndEmitDAG(JSDAG); 4643 4644 // Update PHI Nodes 4645 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4646 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4647 MachineBasicBlock *PHIBB = PHI->getParent(); 4648 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4649 "This is not a machine PHI node that we are updating!"); 4650 // "default" BB. We can go there only from header BB. 4651 if (PHIBB == JTCases[i].second.Default) { 4652 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4653 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB); 4654 } 4655 // JT BB. Just iterate over successors here 4656 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 4657 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4658 PHI->addMachineBasicBlockOperand(BB); 4659 } 4660 } 4661 } 4662 4663 // If the switch block involved a branch to one of the actual successors, we 4664 // need to update PHI nodes in that block. 4665 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4666 MachineInstr *PHI = PHINodesToUpdate[i].first; 4667 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4668 "This is not a machine PHI node that we are updating!"); 4669 if (BB->isSuccessor(PHI->getParent())) { 4670 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4671 PHI->addMachineBasicBlockOperand(BB); 4672 } 4673 } 4674 4675 // If we generated any switch lowering information, build and codegen any 4676 // additional DAGs necessary. 4677 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 4678 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4679 CurDAG = &SDAG; 4680 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 4681 4682 // Set the current basic block to the mbb we wish to insert the code into 4683 BB = SwitchCases[i].ThisBB; 4684 SDL.setCurrentBasicBlock(BB); 4685 4686 // Emit the code 4687 SDL.visitSwitchCase(SwitchCases[i]); 4688 SDAG.setRoot(SDL.getRoot()); 4689 CodeGenAndEmitDAG(SDAG); 4690 4691 // Handle any PHI nodes in successors of this chunk, as if we were coming 4692 // from the original BB before switch expansion. Note that PHI nodes can 4693 // occur multiple times in PHINodesToUpdate. We have to be very careful to 4694 // handle them the right number of times. 4695 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 4696 for (MachineBasicBlock::iterator Phi = BB->begin(); 4697 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 4698 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 4699 for (unsigned pn = 0; ; ++pn) { 4700 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 4701 if (PHINodesToUpdate[pn].first == Phi) { 4702 Phi->addRegOperand(PHINodesToUpdate[pn].second, false); 4703 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB); 4704 break; 4705 } 4706 } 4707 } 4708 4709 // Don't process RHS if same block as LHS. 4710 if (BB == SwitchCases[i].FalseBB) 4711 SwitchCases[i].FalseBB = 0; 4712 4713 // If we haven't handled the RHS, do so now. Otherwise, we're done. 4714 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 4715 SwitchCases[i].FalseBB = 0; 4716 } 4717 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 4718 } 4719} 4720 4721 4722//===----------------------------------------------------------------------===// 4723/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 4724/// target node in the graph. 4725void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 4726 if (ViewSchedDAGs) DAG.viewGraph(); 4727 4728 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 4729 4730 if (!Ctor) { 4731 Ctor = ISHeuristic; 4732 RegisterScheduler::setDefault(Ctor); 4733 } 4734 4735 ScheduleDAG *SL = Ctor(this, &DAG, BB); 4736 BB = SL->Run(); 4737 delete SL; 4738} 4739 4740 4741HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 4742 return new HazardRecognizer(); 4743} 4744 4745//===----------------------------------------------------------------------===// 4746// Helper functions used by the generated instruction selector. 4747//===----------------------------------------------------------------------===// 4748// Calls to these methods are generated by tblgen. 4749 4750/// CheckAndMask - The isel is trying to match something like (and X, 255). If 4751/// the dag combiner simplified the 255, we still want to match. RHS is the 4752/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 4753/// specified in the .td file (e.g. 255). 4754bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 4755 int64_t DesiredMaskS) { 4756 uint64_t ActualMask = RHS->getValue(); 4757 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4758 4759 // If the actual mask exactly matches, success! 4760 if (ActualMask == DesiredMask) 4761 return true; 4762 4763 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4764 if (ActualMask & ~DesiredMask) 4765 return false; 4766 4767 // Otherwise, the DAG Combiner may have proven that the value coming in is 4768 // either already zero or is not demanded. Check for known zero input bits. 4769 uint64_t NeededMask = DesiredMask & ~ActualMask; 4770 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 4771 return true; 4772 4773 // TODO: check to see if missing bits are just not demanded. 4774 4775 // Otherwise, this pattern doesn't match. 4776 return false; 4777} 4778 4779/// CheckOrMask - The isel is trying to match something like (or X, 255). If 4780/// the dag combiner simplified the 255, we still want to match. RHS is the 4781/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 4782/// specified in the .td file (e.g. 255). 4783bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 4784 int64_t DesiredMaskS) { 4785 uint64_t ActualMask = RHS->getValue(); 4786 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4787 4788 // If the actual mask exactly matches, success! 4789 if (ActualMask == DesiredMask) 4790 return true; 4791 4792 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4793 if (ActualMask & ~DesiredMask) 4794 return false; 4795 4796 // Otherwise, the DAG Combiner may have proven that the value coming in is 4797 // either already zero or is not demanded. Check for known zero input bits. 4798 uint64_t NeededMask = DesiredMask & ~ActualMask; 4799 4800 uint64_t KnownZero, KnownOne; 4801 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 4802 4803 // If all the missing bits in the or are already known to be set, match! 4804 if ((NeededMask & KnownOne) == NeededMask) 4805 return true; 4806 4807 // TODO: check to see if missing bits are just not demanded. 4808 4809 // Otherwise, this pattern doesn't match. 4810 return false; 4811} 4812 4813 4814/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 4815/// by tblgen. Others should not call it. 4816void SelectionDAGISel:: 4817SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 4818 std::vector<SDOperand> InOps; 4819 std::swap(InOps, Ops); 4820 4821 Ops.push_back(InOps[0]); // input chain. 4822 Ops.push_back(InOps[1]); // input asm string. 4823 4824 unsigned i = 2, e = InOps.size(); 4825 if (InOps[e-1].getValueType() == MVT::Flag) 4826 --e; // Don't process a flag operand if it is here. 4827 4828 while (i != e) { 4829 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 4830 if ((Flags & 7) != 4 /*MEM*/) { 4831 // Just skip over this operand, copying the operands verbatim. 4832 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 4833 i += (Flags >> 3) + 1; 4834 } else { 4835 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 4836 // Otherwise, this is a memory operand. Ask the target to select it. 4837 std::vector<SDOperand> SelOps; 4838 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 4839 cerr << "Could not match memory address. Inline asm failure!\n"; 4840 exit(1); 4841 } 4842 4843 // Add this to the output node. 4844 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 4845 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 4846 IntPtrTy)); 4847 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 4848 i += 2; 4849 } 4850 } 4851 4852 // Add the flag input back if present. 4853 if (e != InOps.size()) 4854 Ops.push_back(InOps.back()); 4855} 4856 4857char SelectionDAGISel::ID = 0; 4858