SelectionDAGISel.cpp revision 58ed5d27258df9688ac2694cf5e3d31f7dbdeef6
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuild.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/Analysis/AliasAnalysis.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/CodeGen/FastISel.h" 29#include "llvm/CodeGen/GCStrategy.h" 30#include "llvm/CodeGen/GCMetadata.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/MachineJumpTableInfo.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/CodeGen/DwarfWriter.h" 41#include "llvm/Target/TargetRegisterInfo.h" 42#include "llvm/Target/TargetData.h" 43#include "llvm/Target/TargetFrameInfo.h" 44#include "llvm/Target/TargetInstrInfo.h" 45#include "llvm/Target/TargetLowering.h" 46#include "llvm/Target/TargetMachine.h" 47#include "llvm/Target/TargetOptions.h" 48#include "llvm/Support/Compiler.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/MathExtras.h" 51#include "llvm/Support/Timer.h" 52#include <algorithm> 53using namespace llvm; 54 55static cl::opt<bool> 56DisableLegalizeTypes("disable-legalize-types", cl::Hidden); 57#ifndef NDEBUG 58static cl::opt<bool> 59EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 60 cl::desc("Enable verbose messages in the \"fast\" " 61 "instruction selector")); 62static cl::opt<bool> 63EnableFastISelAbort("fast-isel-abort", cl::Hidden, 64 cl::desc("Enable abort calls when \"fast\" instruction fails")); 65#else 66static const bool EnableFastISelVerbose = false, 67 EnableFastISelAbort = false; 68#endif 69static cl::opt<bool> 70SchedLiveInCopies("schedule-livein-copies", 71 cl::desc("Schedule copies of livein registers"), 72 cl::init(false)); 73 74#ifndef NDEBUG 75static cl::opt<bool> 76ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the first " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before legalize types")); 82static cl::opt<bool> 83ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize")); 85static cl::opt<bool> 86ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before the second " 88 "dag combine pass")); 89static cl::opt<bool> 90ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 91 cl::desc("Pop up a window to show dags before the post legalize types" 92 " dag combine pass")); 93static cl::opt<bool> 94ViewISelDAGs("view-isel-dags", cl::Hidden, 95 cl::desc("Pop up a window to show isel dags as they are selected")); 96static cl::opt<bool> 97ViewSchedDAGs("view-sched-dags", cl::Hidden, 98 cl::desc("Pop up a window to show sched dags as they are processed")); 99static cl::opt<bool> 100ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 101 cl::desc("Pop up a window to show SUnit dags after they are processed")); 102#else 103static const bool ViewDAGCombine1 = false, 104 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 105 ViewDAGCombine2 = false, 106 ViewDAGCombineLT = false, 107 ViewISelDAGs = false, ViewSchedDAGs = false, 108 ViewSUnitDAGs = false; 109#endif 110 111//===---------------------------------------------------------------------===// 112/// 113/// RegisterScheduler class - Track the registration of instruction schedulers. 114/// 115//===---------------------------------------------------------------------===// 116MachinePassRegistry RegisterScheduler::Registry; 117 118//===---------------------------------------------------------------------===// 119/// 120/// ISHeuristic command line option for instruction schedulers. 121/// 122//===---------------------------------------------------------------------===// 123static cl::opt<RegisterScheduler::FunctionPassCtor, false, 124 RegisterPassParser<RegisterScheduler> > 125ISHeuristic("pre-RA-sched", 126 cl::init(&createDefaultScheduler), 127 cl::desc("Instruction schedulers available (before register" 128 " allocation):")); 129 130static RegisterScheduler 131defaultListDAGScheduler("default", "Best scheduler for the target", 132 createDefaultScheduler); 133 134namespace llvm { 135 //===--------------------------------------------------------------------===// 136 /// createDefaultScheduler - This creates an instruction scheduler appropriate 137 /// for the target. 138 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 139 unsigned OptLevel) { 140 const TargetLowering &TLI = IS->getTargetLowering(); 141 142 if (OptLevel == 0) 143 return createFastDAGScheduler(IS, OptLevel); 144 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 145 return createTDListDAGScheduler(IS, OptLevel); 146 assert(TLI.getSchedulingPreference() == 147 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 148 return createBURRListDAGScheduler(IS, OptLevel); 149 } 150} 151 152// EmitInstrWithCustomInserter - This method should be implemented by targets 153// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 154// instructions are special in various ways, which require special support to 155// insert. The specified MachineInstr is created but not inserted into any 156// basic blocks, and the scheduler passes ownership of it to this method. 157MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 158 MachineBasicBlock *MBB) const { 159 cerr << "If a target marks an instruction with " 160 << "'usesCustomDAGSchedInserter', it must implement " 161 << "TargetLowering::EmitInstrWithCustomInserter!\n"; 162 abort(); 163 return 0; 164} 165 166/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 167/// physical register has only a single copy use, then coalesced the copy 168/// if possible. 169static void EmitLiveInCopy(MachineBasicBlock *MBB, 170 MachineBasicBlock::iterator &InsertPos, 171 unsigned VirtReg, unsigned PhysReg, 172 const TargetRegisterClass *RC, 173 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 174 const MachineRegisterInfo &MRI, 175 const TargetRegisterInfo &TRI, 176 const TargetInstrInfo &TII) { 177 unsigned NumUses = 0; 178 MachineInstr *UseMI = NULL; 179 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 180 UE = MRI.use_end(); UI != UE; ++UI) { 181 UseMI = &*UI; 182 if (++NumUses > 1) 183 break; 184 } 185 186 // If the number of uses is not one, or the use is not a move instruction, 187 // don't coalesce. Also, only coalesce away a virtual register to virtual 188 // register copy. 189 bool Coalesced = false; 190 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 191 if (NumUses == 1 && 192 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 193 TargetRegisterInfo::isVirtualRegister(DstReg)) { 194 VirtReg = DstReg; 195 Coalesced = true; 196 } 197 198 // Now find an ideal location to insert the copy. 199 MachineBasicBlock::iterator Pos = InsertPos; 200 while (Pos != MBB->begin()) { 201 MachineInstr *PrevMI = prior(Pos); 202 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 203 // copyRegToReg might emit multiple instructions to do a copy. 204 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 205 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 206 // This is what the BB looks like right now: 207 // r1024 = mov r0 208 // ... 209 // r1 = mov r1024 210 // 211 // We want to insert "r1025 = mov r1". Inserting this copy below the 212 // move to r1024 makes it impossible for that move to be coalesced. 213 // 214 // r1025 = mov r1 215 // r1024 = mov r0 216 // ... 217 // r1 = mov 1024 218 // r2 = mov 1025 219 break; // Woot! Found a good location. 220 --Pos; 221 } 222 223 TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 224 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 225 if (Coalesced) { 226 if (&*InsertPos == UseMI) ++InsertPos; 227 MBB->erase(UseMI); 228 } 229} 230 231/// EmitLiveInCopies - If this is the first basic block in the function, 232/// and if it has live ins that need to be copied into vregs, emit the 233/// copies into the block. 234static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 235 const MachineRegisterInfo &MRI, 236 const TargetRegisterInfo &TRI, 237 const TargetInstrInfo &TII) { 238 if (SchedLiveInCopies) { 239 // Emit the copies at a heuristically-determined location in the block. 240 DenseMap<MachineInstr*, unsigned> CopyRegMap; 241 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 242 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 243 E = MRI.livein_end(); LI != E; ++LI) 244 if (LI->second) { 245 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 246 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 247 RC, CopyRegMap, MRI, TRI, TII); 248 } 249 } else { 250 // Emit the copies into the top of the block. 251 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 252 E = MRI.livein_end(); LI != E; ++LI) 253 if (LI->second) { 254 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 255 TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 256 LI->second, LI->first, RC, RC); 257 } 258 } 259} 260 261//===----------------------------------------------------------------------===// 262// SelectionDAGISel code 263//===----------------------------------------------------------------------===// 264 265SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) : 266 FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 267 FuncInfo(new FunctionLoweringInfo(TLI)), 268 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 269 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)), 270 GFI(), 271 OptLevel(OL), 272 DAGSize(0) 273{} 274 275SelectionDAGISel::~SelectionDAGISel() { 276 delete SDL; 277 delete CurDAG; 278 delete FuncInfo; 279} 280 281unsigned SelectionDAGISel::MakeReg(MVT VT) { 282 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 283} 284 285void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 286 AU.addRequired<AliasAnalysis>(); 287 AU.addRequired<GCModuleInfo>(); 288 AU.addRequired<DwarfWriter>(); 289 AU.setPreservesAll(); 290} 291 292bool SelectionDAGISel::runOnFunction(Function &Fn) { 293 // Do some sanity-checking on the command-line options. 294 assert((!EnableFastISelVerbose || EnableFastISel) && 295 "-fast-isel-verbose requires -fast-isel"); 296 assert((!EnableFastISelAbort || EnableFastISel) && 297 "-fast-isel-abort requires -fast-isel"); 298 299 // Do not codegen any 'available_externally' functions at all, they have 300 // definitions outside the translation unit. 301 if (Fn.hasAvailableExternallyLinkage()) 302 return false; 303 304 305 // Get alias analysis for load/store combining. 306 AA = &getAnalysis<AliasAnalysis>(); 307 308 TargetMachine &TM = TLI.getTargetMachine(); 309 MF = &MachineFunction::construct(&Fn, TM); 310 const TargetInstrInfo &TII = *TM.getInstrInfo(); 311 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 312 313 if (MF->getFunction()->hasGC()) 314 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF->getFunction()); 315 else 316 GFI = 0; 317 RegInfo = &MF->getRegInfo(); 318 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 319 320 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 321 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 322 CurDAG->init(*MF, MMI, DW); 323 FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel); 324 SDL->init(GFI, *AA); 325 326 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 327 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 328 // Mark landing pad. 329 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 330 331 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 332 333 // If the first basic block in the function has live ins that need to be 334 // copied into vregs, emit the copies into the top of the block before 335 // emitting the code for the block. 336 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 337 338 // Add function live-ins to entry block live-in set. 339 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 340 E = RegInfo->livein_end(); I != E; ++I) 341 MF->begin()->addLiveIn(I->first); 342 343#ifndef NDEBUG 344 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 345 "Not all catch info was assigned to a landing pad!"); 346#endif 347 348 FuncInfo->clear(); 349 350 return true; 351} 352 353static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 354 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 355 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 356 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) { 357 // Apply the catch info to DestBB. 358 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]); 359#ifndef NDEBUG 360 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 361 FLI.CatchInfoFound.insert(EHSel); 362#endif 363 } 364} 365 366/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and 367/// whether object offset >= 0. 368static bool 369IsFixedFrameObjectWithPosOffset(MachineFrameInfo *MFI, SDValue Op) { 370 if (!isa<FrameIndexSDNode>(Op)) return false; 371 372 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op); 373 int FrameIdx = FrameIdxNode->getIndex(); 374 return MFI->isFixedObjectIndex(FrameIdx) && 375 MFI->getObjectOffset(FrameIdx) >= 0; 376} 377 378/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could 379/// possibly be overwritten when lowering the outgoing arguments in a tail 380/// call. Currently the implementation of this call is very conservative and 381/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with 382/// virtual registers would be overwritten by direct lowering. 383static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op, 384 MachineFrameInfo *MFI) { 385 RegisterSDNode * OpReg = NULL; 386 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS || 387 (Op.getOpcode()== ISD::CopyFromReg && 388 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) && 389 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) || 390 (Op.getOpcode() == ISD::LOAD && 391 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) || 392 (Op.getOpcode() == ISD::MERGE_VALUES && 393 Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD && 394 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()). 395 getOperand(1)))) 396 return true; 397 return false; 398} 399 400/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 401/// DAG and fixes their tailcall attribute operand. 402static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 403 const TargetLowering& TLI) { 404 SDNode * Ret = NULL; 405 SDValue Terminator = DAG.getRoot(); 406 407 // Find RET node. 408 if (Terminator.getOpcode() == ISD::RET) { 409 Ret = Terminator.getNode(); 410 } 411 412 // Fix tail call attribute of CALL nodes. 413 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 414 BI = DAG.allnodes_end(); BI != BE; ) { 415 --BI; 416 if (CallSDNode *TheCall = dyn_cast<CallSDNode>(BI)) { 417 SDValue OpRet(Ret, 0); 418 SDValue OpCall(BI, 0); 419 bool isMarkedTailCall = TheCall->isTailCall(); 420 // If CALL node has tail call attribute set to true and the call is not 421 // eligible (no RET or the target rejects) the attribute is fixed to 422 // false. The TargetLowering::IsEligibleForTailCallOptimization function 423 // must correctly identify tail call optimizable calls. 424 if (!isMarkedTailCall) continue; 425 if (Ret==NULL || 426 !TLI.IsEligibleForTailCallOptimization(TheCall, OpRet, DAG)) { 427 // Not eligible. Mark CALL node as non tail call. Note that we 428 // can modify the call node in place since calls are not CSE'd. 429 TheCall->setNotTailCall(); 430 } else { 431 // Look for tail call clobbered arguments. Emit a series of 432 // copyto/copyfrom virtual register nodes to protect them. 433 SmallVector<SDValue, 32> Ops; 434 SDValue Chain = TheCall->getChain(), InFlag; 435 Ops.push_back(Chain); 436 Ops.push_back(TheCall->getCallee()); 437 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) { 438 SDValue Arg = TheCall->getArg(i); 439 bool isByVal = TheCall->getArgFlags(i).isByVal(); 440 MachineFunction &MF = DAG.getMachineFunction(); 441 MachineFrameInfo *MFI = MF.getFrameInfo(); 442 if (!isByVal && 443 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) { 444 MVT VT = Arg.getValueType(); 445 unsigned VReg = MF.getRegInfo(). 446 createVirtualRegister(TLI.getRegClassFor(VT)); 447 Chain = DAG.getCopyToReg(Chain, Arg.getDebugLoc(), 448 VReg, Arg, InFlag); 449 InFlag = Chain.getValue(1); 450 Arg = DAG.getCopyFromReg(Chain, Arg.getDebugLoc(), 451 VReg, VT, InFlag); 452 Chain = Arg.getValue(1); 453 InFlag = Arg.getValue(2); 454 } 455 Ops.push_back(Arg); 456 Ops.push_back(TheCall->getArgFlagsVal(i)); 457 } 458 // Link in chain of CopyTo/CopyFromReg. 459 Ops[0] = Chain; 460 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 461 } 462 } 463 } 464} 465 466void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 467 BasicBlock::iterator Begin, 468 BasicBlock::iterator End) { 469 SDL->setCurrentBasicBlock(BB); 470 471 // Lower all of the non-terminator instructions. 472 for (BasicBlock::iterator I = Begin; I != End; ++I) 473 if (!isa<TerminatorInst>(I)) 474 SDL->visit(*I); 475 476 // Ensure that all instructions which are used outside of their defining 477 // blocks are available as virtual registers. Invoke is handled elsewhere. 478 for (BasicBlock::iterator I = Begin; I != End; ++I) 479 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 480 SDL->CopyToExportRegsIfNeeded(I); 481 482 // Handle PHI nodes in successor blocks. 483 if (End == LLVMBB->end()) { 484 HandlePHINodesInSuccessorBlocks(LLVMBB); 485 486 // Lower the terminator after the copies are emitted. 487 SDL->visit(*LLVMBB->getTerminator()); 488 } 489 490 // Make sure the root of the DAG is up-to-date. 491 CurDAG->setRoot(SDL->getControlRoot()); 492 493 // Check whether calls in this block are real tail calls. Fix up CALL nodes 494 // with correct tailcall attribute so that the target can rely on the tailcall 495 // attribute indicating whether the call is really eligible for tail call 496 // optimization. 497 if (PerformTailCallOpt) 498 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI); 499 500 // Final step, emit the lowered DAG as machine code. 501 CodeGenAndEmitDAG(); 502 SDL->clear(); 503} 504 505void SelectionDAGISel::ComputeLiveOutVRegInfo() { 506 SmallPtrSet<SDNode*, 128> VisitedNodes; 507 SmallVector<SDNode*, 128> Worklist; 508 509 Worklist.push_back(CurDAG->getRoot().getNode()); 510 511 APInt Mask; 512 APInt KnownZero; 513 APInt KnownOne; 514 515 while (!Worklist.empty()) { 516 SDNode *N = Worklist.back(); 517 Worklist.pop_back(); 518 519 // If we've already seen this node, ignore it. 520 if (!VisitedNodes.insert(N)) 521 continue; 522 523 // Otherwise, add all chain operands to the worklist. 524 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 525 if (N->getOperand(i).getValueType() == MVT::Other) 526 Worklist.push_back(N->getOperand(i).getNode()); 527 528 // If this is a CopyToReg with a vreg dest, process it. 529 if (N->getOpcode() != ISD::CopyToReg) 530 continue; 531 532 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 533 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 534 continue; 535 536 // Ignore non-scalar or non-integer values. 537 SDValue Src = N->getOperand(2); 538 MVT SrcVT = Src.getValueType(); 539 if (!SrcVT.isInteger() || SrcVT.isVector()) 540 continue; 541 542 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 543 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 544 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 545 546 // Only install this information if it tells us something. 547 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 548 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 549 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo(); 550 if (DestReg >= FLI.LiveOutRegInfo.size()) 551 FLI.LiveOutRegInfo.resize(DestReg+1); 552 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg]; 553 LOI.NumSignBits = NumSignBits; 554 LOI.KnownOne = KnownOne; 555 LOI.KnownZero = KnownZero; 556 } 557 } 558} 559 560void SelectionDAGISel::CodeGenAndEmitDAG() { 561 std::string GroupName; 562 if (TimePassesIsEnabled) 563 GroupName = "Instruction Selection and Scheduling"; 564 std::string BlockName; 565 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 566 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 567 ViewSUnitDAGs) 568 BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' + 569 BB->getBasicBlock()->getName(); 570 571 DOUT << "Initial selection DAG:\n"; 572 DEBUG(CurDAG->dump()); 573 574 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 575 576 // Run the DAG combiner in pre-legalize mode. 577 if (TimePassesIsEnabled) { 578 NamedRegionTimer T("DAG Combining 1", GroupName); 579 CurDAG->Combine(Unrestricted, *AA, OptLevel); 580 } else { 581 CurDAG->Combine(Unrestricted, *AA, OptLevel); 582 } 583 584 DOUT << "Optimized lowered selection DAG:\n"; 585 DEBUG(CurDAG->dump()); 586 587 // Second step, hack on the DAG until it only uses operations and types that 588 // the target supports. 589 if (!DisableLegalizeTypes) { 590 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 591 BlockName); 592 593 bool Changed; 594 if (TimePassesIsEnabled) { 595 NamedRegionTimer T("Type Legalization", GroupName); 596 Changed = CurDAG->LegalizeTypes(); 597 } else { 598 Changed = CurDAG->LegalizeTypes(); 599 } 600 601 DOUT << "Type-legalized selection DAG:\n"; 602 DEBUG(CurDAG->dump()); 603 604 if (Changed) { 605 if (ViewDAGCombineLT) 606 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 607 608 // Run the DAG combiner in post-type-legalize mode. 609 if (TimePassesIsEnabled) { 610 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 611 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 612 } else { 613 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 614 } 615 616 DOUT << "Optimized type-legalized selection DAG:\n"; 617 DEBUG(CurDAG->dump()); 618 } 619 } 620 621 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 622 623 if (TimePassesIsEnabled) { 624 NamedRegionTimer T("DAG Legalization", GroupName); 625 CurDAG->Legalize(DisableLegalizeTypes, OptLevel); 626 } else { 627 CurDAG->Legalize(DisableLegalizeTypes, OptLevel); 628 } 629 630 DOUT << "Legalized selection DAG:\n"; 631 DEBUG(CurDAG->dump()); 632 633 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 634 635 // Run the DAG combiner in post-legalize mode. 636 if (TimePassesIsEnabled) { 637 NamedRegionTimer T("DAG Combining 2", GroupName); 638 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 639 } else { 640 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 641 } 642 643 DOUT << "Optimized legalized selection DAG:\n"; 644 DEBUG(CurDAG->dump()); 645 646 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 647 648 if (OptLevel != 0) 649 ComputeLiveOutVRegInfo(); 650 651 // Third, instruction select all of the operations to machine code, adding the 652 // code to the MachineBasicBlock. 653 if (TimePassesIsEnabled) { 654 NamedRegionTimer T("Instruction Selection", GroupName); 655 InstructionSelect(); 656 } else { 657 InstructionSelect(); 658 } 659 660 DOUT << "Selected selection DAG:\n"; 661 DEBUG(CurDAG->dump()); 662 663 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 664 665 // Schedule machine code. 666 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 667 if (TimePassesIsEnabled) { 668 NamedRegionTimer T("Instruction Scheduling", GroupName); 669 Scheduler->Run(CurDAG, BB, BB->end()); 670 } else { 671 Scheduler->Run(CurDAG, BB, BB->end()); 672 } 673 674 if (ViewSUnitDAGs) Scheduler->viewGraph(); 675 676 // Emit machine code to BB. This can change 'BB' to the last block being 677 // inserted into. 678 if (TimePassesIsEnabled) { 679 NamedRegionTimer T("Instruction Creation", GroupName); 680 BB = Scheduler->EmitSchedule(); 681 } else { 682 BB = Scheduler->EmitSchedule(); 683 } 684 685 // Free the scheduler state. 686 if (TimePassesIsEnabled) { 687 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 688 delete Scheduler; 689 } else { 690 delete Scheduler; 691 } 692 693 DOUT << "Selected machine code:\n"; 694 DEBUG(BB->dump()); 695} 696 697void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 698 MachineFunction &MF, 699 MachineModuleInfo *MMI, 700 DwarfWriter *DW, 701 const TargetInstrInfo &TII) { 702 // Initialize the Fast-ISel state, if needed. 703 FastISel *FastIS = 0; 704 if (EnableFastISel) 705 FastIS = TLI.createFastISel(MF, MMI, DW, 706 FuncInfo->ValueMap, 707 FuncInfo->MBBMap, 708 FuncInfo->StaticAllocaMap 709#ifndef NDEBUG 710 , FuncInfo->CatchInfoLost 711#endif 712 ); 713 714 // Iterate over all basic blocks in the function. 715 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 716 BasicBlock *LLVMBB = &*I; 717 BB = FuncInfo->MBBMap[LLVMBB]; 718 719 BasicBlock::iterator const Begin = LLVMBB->begin(); 720 BasicBlock::iterator const End = LLVMBB->end(); 721 BasicBlock::iterator BI = Begin; 722 723 // Lower any arguments needed in this block if this is the entry block. 724 bool SuppressFastISel = false; 725 if (LLVMBB == &Fn.getEntryBlock()) { 726 LowerArguments(LLVMBB); 727 728 // If any of the arguments has the byval attribute, forgo 729 // fast-isel in the entry block. 730 if (FastIS) { 731 unsigned j = 1; 732 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 733 I != E; ++I, ++j) 734 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 735 if (EnableFastISelVerbose || EnableFastISelAbort) 736 cerr << "FastISel skips entry block due to byval argument\n"; 737 SuppressFastISel = true; 738 break; 739 } 740 } 741 } 742 743 if (MMI && BB->isLandingPad()) { 744 // Add a label to mark the beginning of the landing pad. Deletion of the 745 // landing pad can thus be detected via the MachineModuleInfo. 746 unsigned LabelID = MMI->addLandingPad(BB); 747 748 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL); 749 BuildMI(BB, SDL->getCurDebugLoc(), II).addImm(LabelID); 750 751 // Mark exception register as live in. 752 unsigned Reg = TLI.getExceptionAddressRegister(); 753 if (Reg) BB->addLiveIn(Reg); 754 755 // Mark exception selector register as live in. 756 Reg = TLI.getExceptionSelectorRegister(); 757 if (Reg) BB->addLiveIn(Reg); 758 759 // FIXME: Hack around an exception handling flaw (PR1508): the personality 760 // function and list of typeids logically belong to the invoke (or, if you 761 // like, the basic block containing the invoke), and need to be associated 762 // with it in the dwarf exception handling tables. Currently however the 763 // information is provided by an intrinsic (eh.selector) that can be moved 764 // to unexpected places by the optimizers: if the unwind edge is critical, 765 // then breaking it can result in the intrinsics being in the successor of 766 // the landing pad, not the landing pad itself. This results in exceptions 767 // not being caught because no typeids are associated with the invoke. 768 // This may not be the only way things can go wrong, but it is the only way 769 // we try to work around for the moment. 770 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 771 772 if (Br && Br->isUnconditional()) { // Critical edge? 773 BasicBlock::iterator I, E; 774 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 775 if (isa<EHSelectorInst>(I)) 776 break; 777 778 if (I == E) 779 // No catch info found - try to extract some from the successor. 780 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 781 } 782 } 783 784 // Before doing SelectionDAG ISel, see if FastISel has been requested. 785 if (FastIS && !SuppressFastISel) { 786 // Emit code for any incoming arguments. This must happen before 787 // beginning FastISel on the entry block. 788 if (LLVMBB == &Fn.getEntryBlock()) { 789 CurDAG->setRoot(SDL->getControlRoot()); 790 CodeGenAndEmitDAG(); 791 SDL->clear(); 792 } 793 FastIS->startNewBlock(BB); 794 // Do FastISel on as many instructions as possible. 795 for (; BI != End; ++BI) { 796 // Just before the terminator instruction, insert instructions to 797 // feed PHI nodes in successor blocks. 798 if (isa<TerminatorInst>(BI)) 799 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 800 if (EnableFastISelVerbose || EnableFastISelAbort) { 801 cerr << "FastISel miss: "; 802 BI->dump(); 803 } 804 if (EnableFastISelAbort) 805 assert(0 && "FastISel didn't handle a PHI in a successor"); 806 break; 807 } 808 809 // First try normal tablegen-generated "fast" selection. 810 if (FastIS->SelectInstruction(BI)) 811 continue; 812 813 // Next, try calling the target to attempt to handle the instruction. 814 if (FastIS->TargetSelectInstruction(BI)) 815 continue; 816 817 // Then handle certain instructions as single-LLVM-Instruction blocks. 818 if (isa<CallInst>(BI)) { 819 if (EnableFastISelVerbose || EnableFastISelAbort) { 820 cerr << "FastISel missed call: "; 821 BI->dump(); 822 } 823 824 if (BI->getType() != Type::VoidTy) { 825 unsigned &R = FuncInfo->ValueMap[BI]; 826 if (!R) 827 R = FuncInfo->CreateRegForValue(BI); 828 } 829 830 SDL->setCurDebugLoc(FastIS->getCurDebugLoc()); 831 SelectBasicBlock(LLVMBB, BI, next(BI)); 832 // If the instruction was codegen'd with multiple blocks, 833 // inform the FastISel object where to resume inserting. 834 FastIS->setCurrentBlock(BB); 835 continue; 836 } 837 838 // Otherwise, give up on FastISel for the rest of the block. 839 // For now, be a little lenient about non-branch terminators. 840 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 841 if (EnableFastISelVerbose || EnableFastISelAbort) { 842 cerr << "FastISel miss: "; 843 BI->dump(); 844 } 845 if (EnableFastISelAbort) 846 // The "fast" selector couldn't handle something and bailed. 847 // For the purpose of debugging, just abort. 848 assert(0 && "FastISel didn't select the entire block"); 849 } 850 break; 851 } 852 } 853 854 // Run SelectionDAG instruction selection on the remainder of the block 855 // not handled by FastISel. If FastISel is not run, this is the entire 856 // block. 857 if (BI != End) { 858 // If FastISel is run and it has known DebugLoc then use it. 859 if (FastIS && !FastIS->getCurDebugLoc().isUnknown()) 860 SDL->setCurDebugLoc(FastIS->getCurDebugLoc()); 861 SelectBasicBlock(LLVMBB, BI, End); 862 } 863 864 FinishBasicBlock(); 865 } 866 867 delete FastIS; 868} 869 870void 871SelectionDAGISel::FinishBasicBlock() { 872 873 DOUT << "Target-post-processed machine code:\n"; 874 DEBUG(BB->dump()); 875 876 DOUT << "Total amount of phi nodes to update: " 877 << SDL->PHINodesToUpdate.size() << "\n"; 878 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) 879 DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first 880 << ", " << SDL->PHINodesToUpdate[i].second << ")\n";); 881 882 // Next, now that we know what the last MBB the LLVM BB expanded is, update 883 // PHI nodes in successors. 884 if (SDL->SwitchCases.empty() && 885 SDL->JTCases.empty() && 886 SDL->BitTestCases.empty()) { 887 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 888 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 889 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 890 "This is not a machine PHI node that we are updating!"); 891 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 892 false)); 893 PHI->addOperand(MachineOperand::CreateMBB(BB)); 894 } 895 SDL->PHINodesToUpdate.clear(); 896 return; 897 } 898 899 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) { 900 // Lower header first, if it wasn't already lowered 901 if (!SDL->BitTestCases[i].Emitted) { 902 // Set the current basic block to the mbb we wish to insert the code into 903 BB = SDL->BitTestCases[i].Parent; 904 SDL->setCurrentBasicBlock(BB); 905 // Emit the code 906 SDL->visitBitTestHeader(SDL->BitTestCases[i]); 907 CurDAG->setRoot(SDL->getRoot()); 908 CodeGenAndEmitDAG(); 909 SDL->clear(); 910 } 911 912 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) { 913 // Set the current basic block to the mbb we wish to insert the code into 914 BB = SDL->BitTestCases[i].Cases[j].ThisBB; 915 SDL->setCurrentBasicBlock(BB); 916 // Emit the code 917 if (j+1 != ej) 918 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB, 919 SDL->BitTestCases[i].Reg, 920 SDL->BitTestCases[i].Cases[j]); 921 else 922 SDL->visitBitTestCase(SDL->BitTestCases[i].Default, 923 SDL->BitTestCases[i].Reg, 924 SDL->BitTestCases[i].Cases[j]); 925 926 927 CurDAG->setRoot(SDL->getRoot()); 928 CodeGenAndEmitDAG(); 929 SDL->clear(); 930 } 931 932 // Update PHI Nodes 933 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 934 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 935 MachineBasicBlock *PHIBB = PHI->getParent(); 936 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 937 "This is not a machine PHI node that we are updating!"); 938 // This is "default" BB. We have two jumps to it. From "header" BB and 939 // from last "case" BB. 940 if (PHIBB == SDL->BitTestCases[i].Default) { 941 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 942 false)); 943 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent)); 944 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 945 false)); 946 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases. 947 back().ThisBB)); 948 } 949 // One of "cases" BB. 950 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); 951 j != ej; ++j) { 952 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB; 953 if (cBB->succ_end() != 954 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 955 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 956 false)); 957 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 958 } 959 } 960 } 961 } 962 SDL->BitTestCases.clear(); 963 964 // If the JumpTable record is filled in, then we need to emit a jump table. 965 // Updating the PHI nodes is tricky in this case, since we need to determine 966 // whether the PHI is a successor of the range check MBB or the jump table MBB 967 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) { 968 // Lower header first, if it wasn't already lowered 969 if (!SDL->JTCases[i].first.Emitted) { 970 // Set the current basic block to the mbb we wish to insert the code into 971 BB = SDL->JTCases[i].first.HeaderBB; 972 SDL->setCurrentBasicBlock(BB); 973 // Emit the code 974 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first); 975 CurDAG->setRoot(SDL->getRoot()); 976 CodeGenAndEmitDAG(); 977 SDL->clear(); 978 } 979 980 // Set the current basic block to the mbb we wish to insert the code into 981 BB = SDL->JTCases[i].second.MBB; 982 SDL->setCurrentBasicBlock(BB); 983 // Emit the code 984 SDL->visitJumpTable(SDL->JTCases[i].second); 985 CurDAG->setRoot(SDL->getRoot()); 986 CodeGenAndEmitDAG(); 987 SDL->clear(); 988 989 // Update PHI Nodes 990 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 991 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 992 MachineBasicBlock *PHIBB = PHI->getParent(); 993 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 994 "This is not a machine PHI node that we are updating!"); 995 // "default" BB. We can go there only from header BB. 996 if (PHIBB == SDL->JTCases[i].second.Default) { 997 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 998 false)); 999 PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB)); 1000 } 1001 // JT BB. Just iterate over successors here 1002 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 1003 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 1004 false)); 1005 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1006 } 1007 } 1008 } 1009 SDL->JTCases.clear(); 1010 1011 // If the switch block involved a branch to one of the actual successors, we 1012 // need to update PHI nodes in that block. 1013 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 1014 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 1015 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 1016 "This is not a machine PHI node that we are updating!"); 1017 if (BB->isSuccessor(PHI->getParent())) { 1018 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 1019 false)); 1020 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1021 } 1022 } 1023 1024 // If we generated any switch lowering information, build and codegen any 1025 // additional DAGs necessary. 1026 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) { 1027 // Set the current basic block to the mbb we wish to insert the code into 1028 BB = SDL->SwitchCases[i].ThisBB; 1029 SDL->setCurrentBasicBlock(BB); 1030 1031 // Emit the code 1032 SDL->visitSwitchCase(SDL->SwitchCases[i]); 1033 CurDAG->setRoot(SDL->getRoot()); 1034 CodeGenAndEmitDAG(); 1035 SDL->clear(); 1036 1037 // Handle any PHI nodes in successors of this chunk, as if we were coming 1038 // from the original BB before switch expansion. Note that PHI nodes can 1039 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1040 // handle them the right number of times. 1041 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1042 for (MachineBasicBlock::iterator Phi = BB->begin(); 1043 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 1044 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 1045 for (unsigned pn = 0; ; ++pn) { 1046 assert(pn != SDL->PHINodesToUpdate.size() && 1047 "Didn't find PHI entry!"); 1048 if (SDL->PHINodesToUpdate[pn].first == Phi) { 1049 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn]. 1050 second, false)); 1051 Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB)); 1052 break; 1053 } 1054 } 1055 } 1056 1057 // Don't process RHS if same block as LHS. 1058 if (BB == SDL->SwitchCases[i].FalseBB) 1059 SDL->SwitchCases[i].FalseBB = 0; 1060 1061 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1062 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB; 1063 SDL->SwitchCases[i].FalseBB = 0; 1064 } 1065 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0); 1066 } 1067 SDL->SwitchCases.clear(); 1068 1069 SDL->PHINodesToUpdate.clear(); 1070} 1071 1072 1073/// Create the scheduler. If a specific scheduler was specified 1074/// via the SchedulerRegistry, use it, otherwise select the 1075/// one preferred by the target. 1076/// 1077ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1078 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1079 1080 if (!Ctor) { 1081 Ctor = ISHeuristic; 1082 RegisterScheduler::setDefault(Ctor); 1083 } 1084 1085 return Ctor(this, OptLevel); 1086} 1087 1088ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1089 return new ScheduleHazardRecognizer(); 1090} 1091 1092//===----------------------------------------------------------------------===// 1093// Helper functions used by the generated instruction selector. 1094//===----------------------------------------------------------------------===// 1095// Calls to these methods are generated by tblgen. 1096 1097/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1098/// the dag combiner simplified the 255, we still want to match. RHS is the 1099/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1100/// specified in the .td file (e.g. 255). 1101bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1102 int64_t DesiredMaskS) const { 1103 const APInt &ActualMask = RHS->getAPIntValue(); 1104 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1105 1106 // If the actual mask exactly matches, success! 1107 if (ActualMask == DesiredMask) 1108 return true; 1109 1110 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1111 if (ActualMask.intersects(~DesiredMask)) 1112 return false; 1113 1114 // Otherwise, the DAG Combiner may have proven that the value coming in is 1115 // either already zero or is not demanded. Check for known zero input bits. 1116 APInt NeededMask = DesiredMask & ~ActualMask; 1117 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1118 return true; 1119 1120 // TODO: check to see if missing bits are just not demanded. 1121 1122 // Otherwise, this pattern doesn't match. 1123 return false; 1124} 1125 1126/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1127/// the dag combiner simplified the 255, we still want to match. RHS is the 1128/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1129/// specified in the .td file (e.g. 255). 1130bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1131 int64_t DesiredMaskS) const { 1132 const APInt &ActualMask = RHS->getAPIntValue(); 1133 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1134 1135 // If the actual mask exactly matches, success! 1136 if (ActualMask == DesiredMask) 1137 return true; 1138 1139 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1140 if (ActualMask.intersects(~DesiredMask)) 1141 return false; 1142 1143 // Otherwise, the DAG Combiner may have proven that the value coming in is 1144 // either already zero or is not demanded. Check for known zero input bits. 1145 APInt NeededMask = DesiredMask & ~ActualMask; 1146 1147 APInt KnownZero, KnownOne; 1148 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1149 1150 // If all the missing bits in the or are already known to be set, match! 1151 if ((NeededMask & KnownOne) == NeededMask) 1152 return true; 1153 1154 // TODO: check to see if missing bits are just not demanded. 1155 1156 // Otherwise, this pattern doesn't match. 1157 return false; 1158} 1159 1160 1161/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1162/// by tblgen. Others should not call it. 1163void SelectionDAGISel:: 1164SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1165 std::vector<SDValue> InOps; 1166 std::swap(InOps, Ops); 1167 1168 Ops.push_back(InOps[0]); // input chain. 1169 Ops.push_back(InOps[1]); // input asm string. 1170 1171 unsigned i = 2, e = InOps.size(); 1172 if (InOps[e-1].getValueType() == MVT::Flag) 1173 --e; // Don't process a flag operand if it is here. 1174 1175 while (i != e) { 1176 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1177 if ((Flags & 7) != 4 /*MEM*/) { 1178 // Just skip over this operand, copying the operands verbatim. 1179 Ops.insert(Ops.end(), InOps.begin()+i, 1180 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1181 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1182 } else { 1183 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1184 "Memory operand with multiple values?"); 1185 // Otherwise, this is a memory operand. Ask the target to select it. 1186 std::vector<SDValue> SelOps; 1187 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1188 cerr << "Could not match memory address. Inline asm failure!\n"; 1189 exit(1); 1190 } 1191 1192 // Add this to the output node. 1193 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy(); 1194 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1195 IntPtrTy)); 1196 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1197 i += 2; 1198 } 1199 } 1200 1201 // Add the flag input back if present. 1202 if (e != InOps.size()) 1203 Ops.push_back(InOps.back()); 1204} 1205 1206char SelectionDAGISel::ID = 0; 1207