SelectionDAGISel.cpp revision 61b7cea126a0178045839093c98f7a75b6620b72
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/CodeGen/FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/Module.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetIntrinsicInfo.h" 42#include "llvm/Target/TargetInstrInfo.h" 43#include "llvm/Target/TargetLowering.h" 44#include "llvm/Target/TargetMachine.h" 45#include "llvm/Target/TargetOptions.h" 46#include "llvm/Support/Compiler.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/Timer.h" 50#include "llvm/Support/raw_ostream.h" 51#include "llvm/ADT/Statistic.h" 52#include <algorithm> 53using namespace llvm; 54 55STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 56STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 57 58static cl::opt<bool> 59EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 60 cl::desc("Enable verbose messages in the \"fast\" " 61 "instruction selector")); 62static cl::opt<bool> 63EnableFastISelAbort("fast-isel-abort", cl::Hidden, 64 cl::desc("Enable abort calls when \"fast\" instruction fails")); 65 66#ifndef NDEBUG 67static cl::opt<bool> 68ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 69 cl::desc("Pop up a window to show dags before the first " 70 "dag combine pass")); 71static cl::opt<bool> 72ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 73 cl::desc("Pop up a window to show dags before legalize types")); 74static cl::opt<bool> 75ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 76 cl::desc("Pop up a window to show dags before legalize")); 77static cl::opt<bool> 78ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 79 cl::desc("Pop up a window to show dags before the second " 80 "dag combine pass")); 81static cl::opt<bool> 82ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 83 cl::desc("Pop up a window to show dags before the post legalize types" 84 " dag combine pass")); 85static cl::opt<bool> 86ViewISelDAGs("view-isel-dags", cl::Hidden, 87 cl::desc("Pop up a window to show isel dags as they are selected")); 88static cl::opt<bool> 89ViewSchedDAGs("view-sched-dags", cl::Hidden, 90 cl::desc("Pop up a window to show sched dags as they are processed")); 91static cl::opt<bool> 92ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 93 cl::desc("Pop up a window to show SUnit dags after they are processed")); 94#else 95static const bool ViewDAGCombine1 = false, 96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 97 ViewDAGCombine2 = false, 98 ViewDAGCombineLT = false, 99 ViewISelDAGs = false, ViewSchedDAGs = false, 100 ViewSUnitDAGs = false; 101#endif 102 103//===---------------------------------------------------------------------===// 104/// 105/// RegisterScheduler class - Track the registration of instruction schedulers. 106/// 107//===---------------------------------------------------------------------===// 108MachinePassRegistry RegisterScheduler::Registry; 109 110//===---------------------------------------------------------------------===// 111/// 112/// ISHeuristic command line option for instruction schedulers. 113/// 114//===---------------------------------------------------------------------===// 115static cl::opt<RegisterScheduler::FunctionPassCtor, false, 116 RegisterPassParser<RegisterScheduler> > 117ISHeuristic("pre-RA-sched", 118 cl::init(&createDefaultScheduler), 119 cl::desc("Instruction schedulers available (before register" 120 " allocation):")); 121 122static RegisterScheduler 123defaultListDAGScheduler("default", "Best scheduler for the target", 124 createDefaultScheduler); 125 126namespace llvm { 127 //===--------------------------------------------------------------------===// 128 /// createDefaultScheduler - This creates an instruction scheduler appropriate 129 /// for the target. 130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 131 CodeGenOpt::Level OptLevel) { 132 const TargetLowering &TLI = IS->getTargetLowering(); 133 134 if (OptLevel == CodeGenOpt::None) 135 return createFastDAGScheduler(IS, OptLevel); 136 if (TLI.getSchedulingPreference() == Sched::Latency) 137 return createTDListDAGScheduler(IS, OptLevel); 138 if (TLI.getSchedulingPreference() == Sched::RegPressure) 139 return createBURRListDAGScheduler(IS, OptLevel); 140 assert(TLI.getSchedulingPreference() == Sched::Hybrid && 141 "Unknown sched type!"); 142 return createHybridListDAGScheduler(IS, OptLevel); 143 } 144} 145 146// EmitInstrWithCustomInserter - This method should be implemented by targets 147// that mark instructions with the 'usesCustomInserter' flag. These 148// instructions are special in various ways, which require special support to 149// insert. The specified MachineInstr is created but not inserted into any 150// basic blocks, and this method is called to expand it into a sequence of 151// instructions, potentially also creating new basic blocks and control flow. 152// When new basic blocks are inserted and the edges from MBB to its successors 153// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 154// DenseMap. 155MachineBasicBlock * 156TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 157 MachineBasicBlock *MBB) const { 158#ifndef NDEBUG 159 dbgs() << "If a target marks an instruction with " 160 "'usesCustomInserter', it must implement " 161 "TargetLowering::EmitInstrWithCustomInserter!"; 162#endif 163 llvm_unreachable(0); 164 return 0; 165} 166 167//===----------------------------------------------------------------------===// 168// SelectionDAGISel code 169//===----------------------------------------------------------------------===// 170 171SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) : 172 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 173 FuncInfo(new FunctionLoweringInfo(TLI)), 174 CurDAG(new SelectionDAG(tm)), 175 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 176 GFI(), 177 OptLevel(OL), 178 DAGSize(0) 179{} 180 181SelectionDAGISel::~SelectionDAGISel() { 182 delete SDB; 183 delete CurDAG; 184 delete FuncInfo; 185} 186 187void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 188 AU.addRequired<AliasAnalysis>(); 189 AU.addPreserved<AliasAnalysis>(); 190 AU.addRequired<GCModuleInfo>(); 191 AU.addPreserved<GCModuleInfo>(); 192 MachineFunctionPass::getAnalysisUsage(AU); 193} 194 195/// FunctionCallsSetJmp - Return true if the function has a call to setjmp or 196/// other function that gcc recognizes as "returning twice". This is used to 197/// limit code-gen optimizations on the machine function. 198/// 199/// FIXME: Remove after <rdar://problem/8031714> is fixed. 200static bool FunctionCallsSetJmp(const Function *F) { 201 const Module *M = F->getParent(); 202 static const char *ReturnsTwiceFns[] = { 203 "setjmp", 204 "sigsetjmp", 205 "setjmp_syscall", 206 "savectx", 207 "qsetjmp", 208 "vfork", 209 "getcontext" 210 }; 211#define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *) 212 213 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I) 214 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) { 215 if (!Callee->use_empty()) 216 for (Value::const_use_iterator 217 I = Callee->use_begin(), E = Callee->use_end(); 218 I != E; ++I) 219 if (const CallInst *CI = dyn_cast<CallInst>(I)) 220 if (CI->getParent()->getParent() == F) 221 return true; 222 } 223 224 return false; 225#undef NUM_RETURNS_TWICE_FNS 226} 227 228bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 229 // Do some sanity-checking on the command-line options. 230 assert((!EnableFastISelVerbose || EnableFastISel) && 231 "-fast-isel-verbose requires -fast-isel"); 232 assert((!EnableFastISelAbort || EnableFastISel) && 233 "-fast-isel-abort requires -fast-isel"); 234 235 const Function &Fn = *mf.getFunction(); 236 const TargetInstrInfo &TII = *TM.getInstrInfo(); 237 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 238 239 MF = &mf; 240 RegInfo = &MF->getRegInfo(); 241 AA = &getAnalysis<AliasAnalysis>(); 242 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 243 244 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 245 246 CurDAG->init(*MF); 247 FuncInfo->set(Fn, *MF); 248 SDB->init(GFI, *AA); 249 250 SelectAllBasicBlocks(Fn); 251 252 // If the first basic block in the function has live ins that need to be 253 // copied into vregs, emit the copies into the top of the block before 254 // emitting the code for the block. 255 MachineBasicBlock *EntryMBB = MF->begin(); 256 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 257 258 DenseMap<unsigned, unsigned> LiveInMap; 259 if (!FuncInfo->ArgDbgValues.empty()) 260 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 261 E = RegInfo->livein_end(); LI != E; ++LI) 262 if (LI->second) 263 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 264 265 // Insert DBG_VALUE instructions for function arguments to the entry block. 266 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 267 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 268 unsigned Reg = MI->getOperand(0).getReg(); 269 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 270 EntryMBB->insert(EntryMBB->begin(), MI); 271 else { 272 MachineInstr *Def = RegInfo->getVRegDef(Reg); 273 MachineBasicBlock::iterator InsertPos = Def; 274 // FIXME: VR def may not be in entry block. 275 Def->getParent()->insert(llvm::next(InsertPos), MI); 276 } 277 278 // If Reg is live-in then update debug info to track its copy in a vreg. 279 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 280 if (LDI != LiveInMap.end()) { 281 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 282 MachineBasicBlock::iterator InsertPos = Def; 283 const MDNode *Variable = 284 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 285 unsigned Offset = MI->getOperand(1).getImm(); 286 // Def is never a terminator here, so it is ok to increment InsertPos. 287 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 288 TII.get(TargetOpcode::DBG_VALUE)) 289 .addReg(LDI->second, RegState::Debug) 290 .addImm(Offset).addMetadata(Variable); 291 } 292 } 293 294 // Determine if there are any calls in this machine function. 295 MachineFrameInfo *MFI = MF->getFrameInfo(); 296 if (!MFI->hasCalls()) { 297 for (MachineFunction::const_iterator 298 I = MF->begin(), E = MF->end(); I != E; ++I) { 299 const MachineBasicBlock *MBB = I; 300 for (MachineBasicBlock::const_iterator 301 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 302 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode()); 303 if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) { 304 MFI->setHasCalls(true); 305 goto done; 306 } 307 } 308 } 309 done:; 310 } 311 312 // Determine if there is a call to setjmp in the machine function. 313 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn)); 314 315 // Release function-specific state. SDB and CurDAG are already cleared 316 // at this point. 317 FuncInfo->clear(); 318 319 return true; 320} 321 322void 323SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 324 BasicBlock::const_iterator End, 325 bool &HadTailCall) { 326 // Lower all of the non-terminator instructions. If a call is emitted 327 // as a tail call, cease emitting nodes for this block. Terminators 328 // are handled below. 329 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 330 SDB->visit(*I); 331 332 // Make sure the root of the DAG is up-to-date. 333 CurDAG->setRoot(SDB->getControlRoot()); 334 HadTailCall = SDB->HasTailCall; 335 SDB->clear(); 336 337 // Final step, emit the lowered DAG as machine code. 338 CodeGenAndEmitDAG(); 339} 340 341namespace { 342/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 343/// nodes from the worklist. 344class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 345 SmallVector<SDNode*, 128> &Worklist; 346 SmallPtrSet<SDNode*, 128> &InWorklist; 347public: 348 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 349 SmallPtrSet<SDNode*, 128> &inwl) 350 : Worklist(wl), InWorklist(inwl) {} 351 352 void RemoveFromWorklist(SDNode *N) { 353 if (!InWorklist.erase(N)) return; 354 355 SmallVector<SDNode*, 128>::iterator I = 356 std::find(Worklist.begin(), Worklist.end(), N); 357 assert(I != Worklist.end() && "Not in worklist"); 358 359 *I = Worklist.back(); 360 Worklist.pop_back(); 361 } 362 363 virtual void NodeDeleted(SDNode *N, SDNode *E) { 364 RemoveFromWorklist(N); 365 } 366 367 virtual void NodeUpdated(SDNode *N) { 368 // Ignore updates. 369 } 370}; 371} 372 373void SelectionDAGISel::ComputeLiveOutVRegInfo() { 374 SmallPtrSet<SDNode*, 128> VisitedNodes; 375 SmallVector<SDNode*, 128> Worklist; 376 377 Worklist.push_back(CurDAG->getRoot().getNode()); 378 379 APInt Mask; 380 APInt KnownZero; 381 APInt KnownOne; 382 383 do { 384 SDNode *N = Worklist.pop_back_val(); 385 386 // If we've already seen this node, ignore it. 387 if (!VisitedNodes.insert(N)) 388 continue; 389 390 // Otherwise, add all chain operands to the worklist. 391 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 392 if (N->getOperand(i).getValueType() == MVT::Other) 393 Worklist.push_back(N->getOperand(i).getNode()); 394 395 // If this is a CopyToReg with a vreg dest, process it. 396 if (N->getOpcode() != ISD::CopyToReg) 397 continue; 398 399 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 400 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 401 continue; 402 403 // Ignore non-scalar or non-integer values. 404 SDValue Src = N->getOperand(2); 405 EVT SrcVT = Src.getValueType(); 406 if (!SrcVT.isInteger() || SrcVT.isVector()) 407 continue; 408 409 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 410 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 411 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 412 413 // Only install this information if it tells us something. 414 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 415 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 416 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 417 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 418 FunctionLoweringInfo::LiveOutInfo &LOI = 419 FuncInfo->LiveOutRegInfo[DestReg]; 420 LOI.NumSignBits = NumSignBits; 421 LOI.KnownOne = KnownOne; 422 LOI.KnownZero = KnownZero; 423 } 424 } while (!Worklist.empty()); 425} 426 427void SelectionDAGISel::CodeGenAndEmitDAG() { 428 std::string GroupName; 429 if (TimePassesIsEnabled) 430 GroupName = "Instruction Selection and Scheduling"; 431 std::string BlockName; 432 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 433 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 434 ViewSUnitDAGs) 435 BlockName = MF->getFunction()->getNameStr() + ":" + 436 FuncInfo->MBB->getBasicBlock()->getNameStr(); 437 438 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump()); 439 440 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 441 442 // Run the DAG combiner in pre-legalize mode. 443 { 444 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 445 CurDAG->Combine(Unrestricted, *AA, OptLevel); 446 } 447 448 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump()); 449 450 // Second step, hack on the DAG until it only uses operations and types that 451 // the target supports. 452 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 453 BlockName); 454 455 bool Changed; 456 { 457 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 458 Changed = CurDAG->LegalizeTypes(); 459 } 460 461 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump()); 462 463 if (Changed) { 464 if (ViewDAGCombineLT) 465 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 466 467 // Run the DAG combiner in post-type-legalize mode. 468 { 469 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 470 TimePassesIsEnabled); 471 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 472 } 473 474 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"; 475 CurDAG->dump()); 476 } 477 478 { 479 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 480 Changed = CurDAG->LegalizeVectors(); 481 } 482 483 if (Changed) { 484 { 485 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 486 CurDAG->LegalizeTypes(); 487 } 488 489 if (ViewDAGCombineLT) 490 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 491 492 // Run the DAG combiner in post-type-legalize mode. 493 { 494 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 495 TimePassesIsEnabled); 496 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 497 } 498 499 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"; 500 CurDAG->dump()); 501 } 502 503 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 504 505 { 506 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 507 CurDAG->Legalize(OptLevel); 508 } 509 510 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump()); 511 512 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 513 514 // Run the DAG combiner in post-legalize mode. 515 { 516 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 517 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 518 } 519 520 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump()); 521 522 if (OptLevel != CodeGenOpt::None) 523 ComputeLiveOutVRegInfo(); 524 525 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 526 527 // Third, instruction select all of the operations to machine code, adding the 528 // code to the MachineBasicBlock. 529 { 530 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 531 DoInstructionSelection(); 532 } 533 534 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump()); 535 536 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 537 538 // Schedule machine code. 539 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 540 { 541 NamedRegionTimer T("Instruction Scheduling", GroupName, 542 TimePassesIsEnabled); 543 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt); 544 } 545 546 if (ViewSUnitDAGs) Scheduler->viewGraph(); 547 548 // Emit machine code to BB. This can change 'BB' to the last block being 549 // inserted into. 550 { 551 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 552 FuncInfo->MBB = Scheduler->EmitSchedule(); 553 FuncInfo->InsertPt = Scheduler->InsertPos; 554 } 555 556 // Free the scheduler state. 557 { 558 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 559 TimePassesIsEnabled); 560 delete Scheduler; 561 } 562 563 // Free the SelectionDAG state, now that we're finished with it. 564 CurDAG->clear(); 565} 566 567void SelectionDAGISel::DoInstructionSelection() { 568 DEBUG(errs() << "===== Instruction selection begins:\n"); 569 570 PreprocessISelDAG(); 571 572 // Select target instructions for the DAG. 573 { 574 // Number all nodes with a topological order and set DAGSize. 575 DAGSize = CurDAG->AssignTopologicalOrder(); 576 577 // Create a dummy node (which is not added to allnodes), that adds 578 // a reference to the root node, preventing it from being deleted, 579 // and tracking any changes of the root. 580 HandleSDNode Dummy(CurDAG->getRoot()); 581 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 582 ++ISelPosition; 583 584 // The AllNodes list is now topological-sorted. Visit the 585 // nodes by starting at the end of the list (the root of the 586 // graph) and preceding back toward the beginning (the entry 587 // node). 588 while (ISelPosition != CurDAG->allnodes_begin()) { 589 SDNode *Node = --ISelPosition; 590 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 591 // but there are currently some corner cases that it misses. Also, this 592 // makes it theoretically possible to disable the DAGCombiner. 593 if (Node->use_empty()) 594 continue; 595 596 SDNode *ResNode = Select(Node); 597 598 // FIXME: This is pretty gross. 'Select' should be changed to not return 599 // anything at all and this code should be nuked with a tactical strike. 600 601 // If node should not be replaced, continue with the next one. 602 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 603 continue; 604 // Replace node. 605 if (ResNode) 606 ReplaceUses(Node, ResNode); 607 608 // If after the replacement this node is not used any more, 609 // remove this dead node. 610 if (Node->use_empty()) { // Don't delete EntryToken, etc. 611 ISelUpdater ISU(ISelPosition); 612 CurDAG->RemoveDeadNode(Node, &ISU); 613 } 614 } 615 616 CurDAG->setRoot(Dummy.getValue()); 617 } 618 619 DEBUG(errs() << "===== Instruction selection ends:\n"); 620 621 PostprocessISelDAG(); 622} 623 624/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 625/// do other setup for EH landing-pad blocks. 626void SelectionDAGISel::PrepareEHLandingPad() { 627 // Add a label to mark the beginning of the landing pad. Deletion of the 628 // landing pad can thus be detected via the MachineModuleInfo. 629 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB); 630 631 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 632 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 633 .addSym(Label); 634 635 // Mark exception register as live in. 636 unsigned Reg = TLI.getExceptionAddressRegister(); 637 if (Reg) FuncInfo->MBB->addLiveIn(Reg); 638 639 // Mark exception selector register as live in. 640 Reg = TLI.getExceptionSelectorRegister(); 641 if (Reg) FuncInfo->MBB->addLiveIn(Reg); 642 643 // FIXME: Hack around an exception handling flaw (PR1508): the personality 644 // function and list of typeids logically belong to the invoke (or, if you 645 // like, the basic block containing the invoke), and need to be associated 646 // with it in the dwarf exception handling tables. Currently however the 647 // information is provided by an intrinsic (eh.selector) that can be moved 648 // to unexpected places by the optimizers: if the unwind edge is critical, 649 // then breaking it can result in the intrinsics being in the successor of 650 // the landing pad, not the landing pad itself. This results 651 // in exceptions not being caught because no typeids are associated with 652 // the invoke. This may not be the only way things can go wrong, but it 653 // is the only way we try to work around for the moment. 654 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock(); 655 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 656 657 if (Br && Br->isUnconditional()) { // Critical edge? 658 BasicBlock::const_iterator I, E; 659 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 660 if (isa<EHSelectorInst>(I)) 661 break; 662 663 if (I == E) 664 // No catch info found - try to extract some from the successor. 665 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 666 } 667} 668 669void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 670 // Initialize the Fast-ISel state, if needed. 671 FastISel *FastIS = 0; 672 if (EnableFastISel) 673 FastIS = TLI.createFastISel(*FuncInfo); 674 675 // Iterate over all basic blocks in the function. 676 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 677 const BasicBlock *LLVMBB = &*I; 678 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 679 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 680 681 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 682 BasicBlock::const_iterator const End = LLVMBB->end(); 683 BasicBlock::const_iterator BI = End; 684 685 // Before doing SelectionDAG ISel, see if FastISel has been requested. 686 if (FastIS) { 687 FastIS->startNewBlock(); 688 689 // Do FastISel on as many instructions as possible. 690 for (; BI != Begin; --BI) { 691 const Instruction *Inst = llvm::prior(BI); 692 693 // If we no longer require this instruction, skip it. 694 if (!Inst->mayWriteToMemory() && 695 !isa<TerminatorInst>(Inst) && 696 !isa<DbgInfoIntrinsic>(Inst) && 697 !FuncInfo->isExportedInst(Inst)) 698 continue; 699 700 // Bottom-up: reset the insert pos at the top, after any local-value 701 // instructions. 702 MachineBasicBlock::iterator LVIP = FastIS->getLastLocalValue(); 703 if (LVIP != FuncInfo->MBB->end()) 704 FuncInfo->InsertPt = next(LVIP); 705 else 706 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 707 708 // Try to select the instruction with FastISel. 709 if (FastIS->SelectInstruction(Inst)) 710 continue; 711 712 // Then handle certain instructions as single-LLVM-Instruction blocks. 713 if (isa<CallInst>(Inst)) { 714 ++NumFastIselFailures; 715 if (EnableFastISelVerbose || EnableFastISelAbort) { 716 dbgs() << "FastISel missed call: "; 717 Inst->dump(); 718 } 719 720 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 721 unsigned &R = FuncInfo->ValueMap[Inst]; 722 if (!R) 723 R = FuncInfo->CreateRegs(Inst->getType()); 724 } 725 726 bool HadTailCall = false; 727 SelectBasicBlock(Inst, BI, HadTailCall); 728 729 // If the call was emitted as a tail call, we're done with the block. 730 if (HadTailCall) { 731 --BI; 732 break; 733 } 734 735 continue; 736 } 737 738 // Otherwise, give up on FastISel for the rest of the block. 739 // For now, be a little lenient about non-branch terminators. 740 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) { 741 ++NumFastIselFailures; 742 if (EnableFastISelVerbose || EnableFastISelAbort) { 743 dbgs() << "FastISel miss: "; 744 Inst->dump(); 745 } 746 if (EnableFastISelAbort) 747 // The "fast" selector couldn't handle something and bailed. 748 // For the purpose of debugging, just abort. 749 llvm_unreachable("FastISel didn't select the entire block"); 750 } 751 break; 752 } 753 } 754 755 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 756 757 // Setup an EH landing-pad block. 758 if (FuncInfo->MBB->isLandingPad()) 759 PrepareEHLandingPad(); 760 761 // Lower any arguments needed in this block if this is the entry block. 762 if (LLVMBB == &Fn.getEntryBlock()) 763 LowerArguments(LLVMBB); 764 765 // Run SelectionDAG instruction selection on the remainder of the block 766 // not handled by FastISel. If FastISel is not run, this is the entire 767 // block. 768 bool HadTailCall; 769 SelectBasicBlock(Begin, BI, HadTailCall); 770 771 FinishBasicBlock(); 772 FuncInfo->PHINodesToUpdate.clear(); 773 } 774 775 delete FastIS; 776} 777 778void 779SelectionDAGISel::FinishBasicBlock() { 780 781 DEBUG(dbgs() << "Total amount of phi nodes to update: " 782 << FuncInfo->PHINodesToUpdate.size() << "\n"; 783 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 784 dbgs() << "Node " << i << " : (" 785 << FuncInfo->PHINodesToUpdate[i].first 786 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 787 788 // Next, now that we know what the last MBB the LLVM BB expanded is, update 789 // PHI nodes in successors. 790 if (SDB->SwitchCases.empty() && 791 SDB->JTCases.empty() && 792 SDB->BitTestCases.empty()) { 793 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 794 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 795 assert(PHI->isPHI() && 796 "This is not a machine PHI node that we are updating!"); 797 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 798 continue; 799 PHI->addOperand( 800 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 801 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 802 } 803 return; 804 } 805 806 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 807 // Lower header first, if it wasn't already lowered 808 if (!SDB->BitTestCases[i].Emitted) { 809 // Set the current basic block to the mbb we wish to insert the code into 810 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 811 FuncInfo->InsertPt = FuncInfo->MBB->end(); 812 // Emit the code 813 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 814 CurDAG->setRoot(SDB->getRoot()); 815 SDB->clear(); 816 CodeGenAndEmitDAG(); 817 } 818 819 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 820 // Set the current basic block to the mbb we wish to insert the code into 821 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 822 FuncInfo->InsertPt = FuncInfo->MBB->end(); 823 // Emit the code 824 if (j+1 != ej) 825 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 826 SDB->BitTestCases[i].Reg, 827 SDB->BitTestCases[i].Cases[j], 828 FuncInfo->MBB); 829 else 830 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 831 SDB->BitTestCases[i].Reg, 832 SDB->BitTestCases[i].Cases[j], 833 FuncInfo->MBB); 834 835 836 CurDAG->setRoot(SDB->getRoot()); 837 SDB->clear(); 838 CodeGenAndEmitDAG(); 839 } 840 841 // Update PHI Nodes 842 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 843 pi != pe; ++pi) { 844 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 845 MachineBasicBlock *PHIBB = PHI->getParent(); 846 assert(PHI->isPHI() && 847 "This is not a machine PHI node that we are updating!"); 848 // This is "default" BB. We have two jumps to it. From "header" BB and 849 // from last "case" BB. 850 if (PHIBB == SDB->BitTestCases[i].Default) { 851 PHI->addOperand(MachineOperand:: 852 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 853 false)); 854 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 855 PHI->addOperand(MachineOperand:: 856 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 857 false)); 858 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 859 back().ThisBB)); 860 } 861 // One of "cases" BB. 862 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 863 j != ej; ++j) { 864 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 865 if (cBB->isSuccessor(PHIBB)) { 866 PHI->addOperand(MachineOperand:: 867 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 868 false)); 869 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 870 } 871 } 872 } 873 } 874 SDB->BitTestCases.clear(); 875 876 // If the JumpTable record is filled in, then we need to emit a jump table. 877 // Updating the PHI nodes is tricky in this case, since we need to determine 878 // whether the PHI is a successor of the range check MBB or the jump table MBB 879 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 880 // Lower header first, if it wasn't already lowered 881 if (!SDB->JTCases[i].first.Emitted) { 882 // Set the current basic block to the mbb we wish to insert the code into 883 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 884 FuncInfo->InsertPt = FuncInfo->MBB->end(); 885 // Emit the code 886 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 887 FuncInfo->MBB); 888 CurDAG->setRoot(SDB->getRoot()); 889 SDB->clear(); 890 CodeGenAndEmitDAG(); 891 } 892 893 // Set the current basic block to the mbb we wish to insert the code into 894 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 895 FuncInfo->InsertPt = FuncInfo->MBB->end(); 896 // Emit the code 897 SDB->visitJumpTable(SDB->JTCases[i].second); 898 CurDAG->setRoot(SDB->getRoot()); 899 SDB->clear(); 900 CodeGenAndEmitDAG(); 901 902 // Update PHI Nodes 903 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 904 pi != pe; ++pi) { 905 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 906 MachineBasicBlock *PHIBB = PHI->getParent(); 907 assert(PHI->isPHI() && 908 "This is not a machine PHI node that we are updating!"); 909 // "default" BB. We can go there only from header BB. 910 if (PHIBB == SDB->JTCases[i].second.Default) { 911 PHI->addOperand 912 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 913 false)); 914 PHI->addOperand 915 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 916 } 917 // JT BB. Just iterate over successors here 918 if (FuncInfo->MBB->isSuccessor(PHIBB)) { 919 PHI->addOperand 920 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 921 false)); 922 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 923 } 924 } 925 } 926 SDB->JTCases.clear(); 927 928 // If the switch block involved a branch to one of the actual successors, we 929 // need to update PHI nodes in that block. 930 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 931 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 932 assert(PHI->isPHI() && 933 "This is not a machine PHI node that we are updating!"); 934 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) { 935 PHI->addOperand( 936 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 937 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 938 } 939 } 940 941 // If we generated any switch lowering information, build and codegen any 942 // additional DAGs necessary. 943 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 944 // Set the current basic block to the mbb we wish to insert the code into 945 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 946 FuncInfo->InsertPt = FuncInfo->MBB->end(); 947 948 // Determine the unique successors. 949 SmallVector<MachineBasicBlock *, 2> Succs; 950 Succs.push_back(SDB->SwitchCases[i].TrueBB); 951 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 952 Succs.push_back(SDB->SwitchCases[i].FalseBB); 953 954 // Emit the code. Note that this could result in ThisBB being split, so 955 // we need to check for updates. 956 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 957 CurDAG->setRoot(SDB->getRoot()); 958 SDB->clear(); 959 CodeGenAndEmitDAG(); 960 ThisBB = FuncInfo->MBB; 961 962 // Handle any PHI nodes in successors of this chunk, as if we were coming 963 // from the original BB before switch expansion. Note that PHI nodes can 964 // occur multiple times in PHINodesToUpdate. We have to be very careful to 965 // handle them the right number of times. 966 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 967 FuncInfo->MBB = Succs[i]; 968 FuncInfo->InsertPt = FuncInfo->MBB->end(); 969 // FuncInfo->MBB may have been removed from the CFG if a branch was 970 // constant folded. 971 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 972 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin(); 973 Phi != FuncInfo->MBB->end() && Phi->isPHI(); 974 ++Phi) { 975 // This value for this PHI node is recorded in PHINodesToUpdate. 976 for (unsigned pn = 0; ; ++pn) { 977 assert(pn != FuncInfo->PHINodesToUpdate.size() && 978 "Didn't find PHI entry!"); 979 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 980 Phi->addOperand(MachineOperand:: 981 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 982 false)); 983 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 984 break; 985 } 986 } 987 } 988 } 989 } 990 } 991 SDB->SwitchCases.clear(); 992} 993 994 995/// Create the scheduler. If a specific scheduler was specified 996/// via the SchedulerRegistry, use it, otherwise select the 997/// one preferred by the target. 998/// 999ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1000 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1001 1002 if (!Ctor) { 1003 Ctor = ISHeuristic; 1004 RegisterScheduler::setDefault(Ctor); 1005 } 1006 1007 return Ctor(this, OptLevel); 1008} 1009 1010ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1011 return new ScheduleHazardRecognizer(); 1012} 1013 1014//===----------------------------------------------------------------------===// 1015// Helper functions used by the generated instruction selector. 1016//===----------------------------------------------------------------------===// 1017// Calls to these methods are generated by tblgen. 1018 1019/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1020/// the dag combiner simplified the 255, we still want to match. RHS is the 1021/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1022/// specified in the .td file (e.g. 255). 1023bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1024 int64_t DesiredMaskS) const { 1025 const APInt &ActualMask = RHS->getAPIntValue(); 1026 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1027 1028 // If the actual mask exactly matches, success! 1029 if (ActualMask == DesiredMask) 1030 return true; 1031 1032 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1033 if (ActualMask.intersects(~DesiredMask)) 1034 return false; 1035 1036 // Otherwise, the DAG Combiner may have proven that the value coming in is 1037 // either already zero or is not demanded. Check for known zero input bits. 1038 APInt NeededMask = DesiredMask & ~ActualMask; 1039 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1040 return true; 1041 1042 // TODO: check to see if missing bits are just not demanded. 1043 1044 // Otherwise, this pattern doesn't match. 1045 return false; 1046} 1047 1048/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1049/// the dag combiner simplified the 255, we still want to match. RHS is the 1050/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1051/// specified in the .td file (e.g. 255). 1052bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1053 int64_t DesiredMaskS) const { 1054 const APInt &ActualMask = RHS->getAPIntValue(); 1055 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1056 1057 // If the actual mask exactly matches, success! 1058 if (ActualMask == DesiredMask) 1059 return true; 1060 1061 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1062 if (ActualMask.intersects(~DesiredMask)) 1063 return false; 1064 1065 // Otherwise, the DAG Combiner may have proven that the value coming in is 1066 // either already zero or is not demanded. Check for known zero input bits. 1067 APInt NeededMask = DesiredMask & ~ActualMask; 1068 1069 APInt KnownZero, KnownOne; 1070 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1071 1072 // If all the missing bits in the or are already known to be set, match! 1073 if ((NeededMask & KnownOne) == NeededMask) 1074 return true; 1075 1076 // TODO: check to see if missing bits are just not demanded. 1077 1078 // Otherwise, this pattern doesn't match. 1079 return false; 1080} 1081 1082 1083/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1084/// by tblgen. Others should not call it. 1085void SelectionDAGISel:: 1086SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1087 std::vector<SDValue> InOps; 1088 std::swap(InOps, Ops); 1089 1090 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1091 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1092 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1093 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3 1094 1095 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1096 if (InOps[e-1].getValueType() == MVT::Flag) 1097 --e; // Don't process a flag operand if it is here. 1098 1099 while (i != e) { 1100 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1101 if (!InlineAsm::isMemKind(Flags)) { 1102 // Just skip over this operand, copying the operands verbatim. 1103 Ops.insert(Ops.end(), InOps.begin()+i, 1104 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1105 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1106 } else { 1107 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1108 "Memory operand with multiple values?"); 1109 // Otherwise, this is a memory operand. Ask the target to select it. 1110 std::vector<SDValue> SelOps; 1111 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1112 report_fatal_error("Could not match memory address. Inline asm" 1113 " failure!"); 1114 1115 // Add this to the output node. 1116 unsigned NewFlags = 1117 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1118 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1119 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1120 i += 2; 1121 } 1122 } 1123 1124 // Add the flag input back if present. 1125 if (e != InOps.size()) 1126 Ops.push_back(InOps.back()); 1127} 1128 1129/// findFlagUse - Return use of EVT::Flag value produced by the specified 1130/// SDNode. 1131/// 1132static SDNode *findFlagUse(SDNode *N) { 1133 unsigned FlagResNo = N->getNumValues()-1; 1134 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1135 SDUse &Use = I.getUse(); 1136 if (Use.getResNo() == FlagResNo) 1137 return Use.getUser(); 1138 } 1139 return NULL; 1140} 1141 1142/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1143/// This function recursively traverses up the operand chain, ignoring 1144/// certain nodes. 1145static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1146 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1147 bool IgnoreChains) { 1148 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1149 // greater than all of its (recursive) operands. If we scan to a point where 1150 // 'use' is smaller than the node we're scanning for, then we know we will 1151 // never find it. 1152 // 1153 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1154 // happen because we scan down to newly selected nodes in the case of flag 1155 // uses. 1156 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1157 return false; 1158 1159 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1160 // won't fail if we scan it again. 1161 if (!Visited.insert(Use)) 1162 return false; 1163 1164 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1165 // Ignore chain uses, they are validated by HandleMergeInputChains. 1166 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1167 continue; 1168 1169 SDNode *N = Use->getOperand(i).getNode(); 1170 if (N == Def) { 1171 if (Use == ImmedUse || Use == Root) 1172 continue; // We are not looking for immediate use. 1173 assert(N != Root); 1174 return true; 1175 } 1176 1177 // Traverse up the operand chain. 1178 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1179 return true; 1180 } 1181 return false; 1182} 1183 1184/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1185/// operand node N of U during instruction selection that starts at Root. 1186bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1187 SDNode *Root) const { 1188 if (OptLevel == CodeGenOpt::None) return false; 1189 return N.hasOneUse(); 1190} 1191 1192/// IsLegalToFold - Returns true if the specific operand node N of 1193/// U can be folded during instruction selection that starts at Root. 1194bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1195 CodeGenOpt::Level OptLevel, 1196 bool IgnoreChains) { 1197 if (OptLevel == CodeGenOpt::None) return false; 1198 1199 // If Root use can somehow reach N through a path that that doesn't contain 1200 // U then folding N would create a cycle. e.g. In the following 1201 // diagram, Root can reach N through X. If N is folded into into Root, then 1202 // X is both a predecessor and a successor of U. 1203 // 1204 // [N*] // 1205 // ^ ^ // 1206 // / \ // 1207 // [U*] [X]? // 1208 // ^ ^ // 1209 // \ / // 1210 // \ / // 1211 // [Root*] // 1212 // 1213 // * indicates nodes to be folded together. 1214 // 1215 // If Root produces a flag, then it gets (even more) interesting. Since it 1216 // will be "glued" together with its flag use in the scheduler, we need to 1217 // check if it might reach N. 1218 // 1219 // [N*] // 1220 // ^ ^ // 1221 // / \ // 1222 // [U*] [X]? // 1223 // ^ ^ // 1224 // \ \ // 1225 // \ | // 1226 // [Root*] | // 1227 // ^ | // 1228 // f | // 1229 // | / // 1230 // [Y] / // 1231 // ^ / // 1232 // f / // 1233 // | / // 1234 // [FU] // 1235 // 1236 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1237 // (call it Fold), then X is a predecessor of FU and a successor of 1238 // Fold. But since Fold and FU are flagged together, this will create 1239 // a cycle in the scheduling graph. 1240 1241 // If the node has flags, walk down the graph to the "lowest" node in the 1242 // flagged set. 1243 EVT VT = Root->getValueType(Root->getNumValues()-1); 1244 while (VT == MVT::Flag) { 1245 SDNode *FU = findFlagUse(Root); 1246 if (FU == NULL) 1247 break; 1248 Root = FU; 1249 VT = Root->getValueType(Root->getNumValues()-1); 1250 1251 // If our query node has a flag result with a use, we've walked up it. If 1252 // the user (which has already been selected) has a chain or indirectly uses 1253 // the chain, our WalkChainUsers predicate will not consider it. Because of 1254 // this, we cannot ignore chains in this predicate. 1255 IgnoreChains = false; 1256 } 1257 1258 1259 SmallPtrSet<SDNode*, 16> Visited; 1260 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1261} 1262 1263SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1264 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1265 SelectInlineAsmMemoryOperands(Ops); 1266 1267 std::vector<EVT> VTs; 1268 VTs.push_back(MVT::Other); 1269 VTs.push_back(MVT::Flag); 1270 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1271 VTs, &Ops[0], Ops.size()); 1272 New->setNodeId(-1); 1273 return New.getNode(); 1274} 1275 1276SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1277 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1278} 1279 1280/// GetVBR - decode a vbr encoding whose top bit is set. 1281ALWAYS_INLINE static uint64_t 1282GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1283 assert(Val >= 128 && "Not a VBR"); 1284 Val &= 127; // Remove first vbr bit. 1285 1286 unsigned Shift = 7; 1287 uint64_t NextBits; 1288 do { 1289 NextBits = MatcherTable[Idx++]; 1290 Val |= (NextBits&127) << Shift; 1291 Shift += 7; 1292 } while (NextBits & 128); 1293 1294 return Val; 1295} 1296 1297 1298/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1299/// interior flag and chain results to use the new flag and chain results. 1300void SelectionDAGISel:: 1301UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1302 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1303 SDValue InputFlag, 1304 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1305 bool isMorphNodeTo) { 1306 SmallVector<SDNode*, 4> NowDeadNodes; 1307 1308 ISelUpdater ISU(ISelPosition); 1309 1310 // Now that all the normal results are replaced, we replace the chain and 1311 // flag results if present. 1312 if (!ChainNodesMatched.empty()) { 1313 assert(InputChain.getNode() != 0 && 1314 "Matched input chains but didn't produce a chain"); 1315 // Loop over all of the nodes we matched that produced a chain result. 1316 // Replace all the chain results with the final chain we ended up with. 1317 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1318 SDNode *ChainNode = ChainNodesMatched[i]; 1319 1320 // If this node was already deleted, don't look at it. 1321 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1322 continue; 1323 1324 // Don't replace the results of the root node if we're doing a 1325 // MorphNodeTo. 1326 if (ChainNode == NodeToMatch && isMorphNodeTo) 1327 continue; 1328 1329 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1330 if (ChainVal.getValueType() == MVT::Flag) 1331 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1332 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1333 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1334 1335 // If the node became dead and we haven't already seen it, delete it. 1336 if (ChainNode->use_empty() && 1337 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1338 NowDeadNodes.push_back(ChainNode); 1339 } 1340 } 1341 1342 // If the result produces a flag, update any flag results in the matched 1343 // pattern with the flag result. 1344 if (InputFlag.getNode() != 0) { 1345 // Handle any interior nodes explicitly marked. 1346 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1347 SDNode *FRN = FlagResultNodesMatched[i]; 1348 1349 // If this node was already deleted, don't look at it. 1350 if (FRN->getOpcode() == ISD::DELETED_NODE) 1351 continue; 1352 1353 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1354 "Doesn't have a flag result"); 1355 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1356 InputFlag, &ISU); 1357 1358 // If the node became dead and we haven't already seen it, delete it. 1359 if (FRN->use_empty() && 1360 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1361 NowDeadNodes.push_back(FRN); 1362 } 1363 } 1364 1365 if (!NowDeadNodes.empty()) 1366 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1367 1368 DEBUG(errs() << "ISEL: Match complete!\n"); 1369} 1370 1371enum ChainResult { 1372 CR_Simple, 1373 CR_InducesCycle, 1374 CR_LeadsToInteriorNode 1375}; 1376 1377/// WalkChainUsers - Walk down the users of the specified chained node that is 1378/// part of the pattern we're matching, looking at all of the users we find. 1379/// This determines whether something is an interior node, whether we have a 1380/// non-pattern node in between two pattern nodes (which prevent folding because 1381/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1382/// between pattern nodes (in which case the TF becomes part of the pattern). 1383/// 1384/// The walk we do here is guaranteed to be small because we quickly get down to 1385/// already selected nodes "below" us. 1386static ChainResult 1387WalkChainUsers(SDNode *ChainedNode, 1388 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1389 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1390 ChainResult Result = CR_Simple; 1391 1392 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1393 E = ChainedNode->use_end(); UI != E; ++UI) { 1394 // Make sure the use is of the chain, not some other value we produce. 1395 if (UI.getUse().getValueType() != MVT::Other) continue; 1396 1397 SDNode *User = *UI; 1398 1399 // If we see an already-selected machine node, then we've gone beyond the 1400 // pattern that we're selecting down into the already selected chunk of the 1401 // DAG. 1402 if (User->isMachineOpcode() || 1403 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1404 continue; 1405 1406 if (User->getOpcode() == ISD::CopyToReg || 1407 User->getOpcode() == ISD::CopyFromReg || 1408 User->getOpcode() == ISD::INLINEASM || 1409 User->getOpcode() == ISD::EH_LABEL) { 1410 // If their node ID got reset to -1 then they've already been selected. 1411 // Treat them like a MachineOpcode. 1412 if (User->getNodeId() == -1) 1413 continue; 1414 } 1415 1416 // If we have a TokenFactor, we handle it specially. 1417 if (User->getOpcode() != ISD::TokenFactor) { 1418 // If the node isn't a token factor and isn't part of our pattern, then it 1419 // must be a random chained node in between two nodes we're selecting. 1420 // This happens when we have something like: 1421 // x = load ptr 1422 // call 1423 // y = x+4 1424 // store y -> ptr 1425 // Because we structurally match the load/store as a read/modify/write, 1426 // but the call is chained between them. We cannot fold in this case 1427 // because it would induce a cycle in the graph. 1428 if (!std::count(ChainedNodesInPattern.begin(), 1429 ChainedNodesInPattern.end(), User)) 1430 return CR_InducesCycle; 1431 1432 // Otherwise we found a node that is part of our pattern. For example in: 1433 // x = load ptr 1434 // y = x+4 1435 // store y -> ptr 1436 // This would happen when we're scanning down from the load and see the 1437 // store as a user. Record that there is a use of ChainedNode that is 1438 // part of the pattern and keep scanning uses. 1439 Result = CR_LeadsToInteriorNode; 1440 InteriorChainedNodes.push_back(User); 1441 continue; 1442 } 1443 1444 // If we found a TokenFactor, there are two cases to consider: first if the 1445 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1446 // uses of the TF are in our pattern) we just want to ignore it. Second, 1447 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1448 // [Load chain] 1449 // ^ 1450 // | 1451 // [Load] 1452 // ^ ^ 1453 // | \ DAG's like cheese 1454 // / \ do you? 1455 // / | 1456 // [TokenFactor] [Op] 1457 // ^ ^ 1458 // | | 1459 // \ / 1460 // \ / 1461 // [Store] 1462 // 1463 // In this case, the TokenFactor becomes part of our match and we rewrite it 1464 // as a new TokenFactor. 1465 // 1466 // To distinguish these two cases, do a recursive walk down the uses. 1467 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1468 case CR_Simple: 1469 // If the uses of the TokenFactor are just already-selected nodes, ignore 1470 // it, it is "below" our pattern. 1471 continue; 1472 case CR_InducesCycle: 1473 // If the uses of the TokenFactor lead to nodes that are not part of our 1474 // pattern that are not selected, folding would turn this into a cycle, 1475 // bail out now. 1476 return CR_InducesCycle; 1477 case CR_LeadsToInteriorNode: 1478 break; // Otherwise, keep processing. 1479 } 1480 1481 // Okay, we know we're in the interesting interior case. The TokenFactor 1482 // is now going to be considered part of the pattern so that we rewrite its 1483 // uses (it may have uses that are not part of the pattern) with the 1484 // ultimate chain result of the generated code. We will also add its chain 1485 // inputs as inputs to the ultimate TokenFactor we create. 1486 Result = CR_LeadsToInteriorNode; 1487 ChainedNodesInPattern.push_back(User); 1488 InteriorChainedNodes.push_back(User); 1489 continue; 1490 } 1491 1492 return Result; 1493} 1494 1495/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1496/// operation for when the pattern matched at least one node with a chains. The 1497/// input vector contains a list of all of the chained nodes that we match. We 1498/// must determine if this is a valid thing to cover (i.e. matching it won't 1499/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1500/// be used as the input node chain for the generated nodes. 1501static SDValue 1502HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1503 SelectionDAG *CurDAG) { 1504 // Walk all of the chained nodes we've matched, recursively scanning down the 1505 // users of the chain result. This adds any TokenFactor nodes that are caught 1506 // in between chained nodes to the chained and interior nodes list. 1507 SmallVector<SDNode*, 3> InteriorChainedNodes; 1508 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1509 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1510 InteriorChainedNodes) == CR_InducesCycle) 1511 return SDValue(); // Would induce a cycle. 1512 } 1513 1514 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1515 // that we are interested in. Form our input TokenFactor node. 1516 SmallVector<SDValue, 3> InputChains; 1517 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1518 // Add the input chain of this node to the InputChains list (which will be 1519 // the operands of the generated TokenFactor) if it's not an interior node. 1520 SDNode *N = ChainNodesMatched[i]; 1521 if (N->getOpcode() != ISD::TokenFactor) { 1522 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1523 continue; 1524 1525 // Otherwise, add the input chain. 1526 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1527 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1528 InputChains.push_back(InChain); 1529 continue; 1530 } 1531 1532 // If we have a token factor, we want to add all inputs of the token factor 1533 // that are not part of the pattern we're matching. 1534 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1535 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1536 N->getOperand(op).getNode())) 1537 InputChains.push_back(N->getOperand(op)); 1538 } 1539 } 1540 1541 SDValue Res; 1542 if (InputChains.size() == 1) 1543 return InputChains[0]; 1544 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1545 MVT::Other, &InputChains[0], InputChains.size()); 1546} 1547 1548/// MorphNode - Handle morphing a node in place for the selector. 1549SDNode *SelectionDAGISel:: 1550MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1551 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1552 // It is possible we're using MorphNodeTo to replace a node with no 1553 // normal results with one that has a normal result (or we could be 1554 // adding a chain) and the input could have flags and chains as well. 1555 // In this case we need to shift the operands down. 1556 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1557 // than the old isel though. 1558 int OldFlagResultNo = -1, OldChainResultNo = -1; 1559 1560 unsigned NTMNumResults = Node->getNumValues(); 1561 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1562 OldFlagResultNo = NTMNumResults-1; 1563 if (NTMNumResults != 1 && 1564 Node->getValueType(NTMNumResults-2) == MVT::Other) 1565 OldChainResultNo = NTMNumResults-2; 1566 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1567 OldChainResultNo = NTMNumResults-1; 1568 1569 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1570 // that this deletes operands of the old node that become dead. 1571 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1572 1573 // MorphNodeTo can operate in two ways: if an existing node with the 1574 // specified operands exists, it can just return it. Otherwise, it 1575 // updates the node in place to have the requested operands. 1576 if (Res == Node) { 1577 // If we updated the node in place, reset the node ID. To the isel, 1578 // this should be just like a newly allocated machine node. 1579 Res->setNodeId(-1); 1580 } 1581 1582 unsigned ResNumResults = Res->getNumValues(); 1583 // Move the flag if needed. 1584 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1585 (unsigned)OldFlagResultNo != ResNumResults-1) 1586 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1587 SDValue(Res, ResNumResults-1)); 1588 1589 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1590 --ResNumResults; 1591 1592 // Move the chain reference if needed. 1593 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1594 (unsigned)OldChainResultNo != ResNumResults-1) 1595 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1596 SDValue(Res, ResNumResults-1)); 1597 1598 // Otherwise, no replacement happened because the node already exists. Replace 1599 // Uses of the old node with the new one. 1600 if (Res != Node) 1601 CurDAG->ReplaceAllUsesWith(Node, Res); 1602 1603 return Res; 1604} 1605 1606/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1607ALWAYS_INLINE static bool 1608CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1609 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1610 // Accept if it is exactly the same as a previously recorded node. 1611 unsigned RecNo = MatcherTable[MatcherIndex++]; 1612 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1613 return N == RecordedNodes[RecNo]; 1614} 1615 1616/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1617ALWAYS_INLINE static bool 1618CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1619 SelectionDAGISel &SDISel) { 1620 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1621} 1622 1623/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1624ALWAYS_INLINE static bool 1625CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1626 SelectionDAGISel &SDISel, SDNode *N) { 1627 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1628} 1629 1630ALWAYS_INLINE static bool 1631CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1632 SDNode *N) { 1633 uint16_t Opc = MatcherTable[MatcherIndex++]; 1634 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1635 return N->getOpcode() == Opc; 1636} 1637 1638ALWAYS_INLINE static bool 1639CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1640 SDValue N, const TargetLowering &TLI) { 1641 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1642 if (N.getValueType() == VT) return true; 1643 1644 // Handle the case when VT is iPTR. 1645 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1646} 1647 1648ALWAYS_INLINE static bool 1649CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1650 SDValue N, const TargetLowering &TLI, 1651 unsigned ChildNo) { 1652 if (ChildNo >= N.getNumOperands()) 1653 return false; // Match fails if out of range child #. 1654 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1655} 1656 1657 1658ALWAYS_INLINE static bool 1659CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1660 SDValue N) { 1661 return cast<CondCodeSDNode>(N)->get() == 1662 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1663} 1664 1665ALWAYS_INLINE static bool 1666CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1667 SDValue N, const TargetLowering &TLI) { 1668 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1669 if (cast<VTSDNode>(N)->getVT() == VT) 1670 return true; 1671 1672 // Handle the case when VT is iPTR. 1673 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1674} 1675 1676ALWAYS_INLINE static bool 1677CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1678 SDValue N) { 1679 int64_t Val = MatcherTable[MatcherIndex++]; 1680 if (Val & 128) 1681 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1682 1683 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1684 return C != 0 && C->getSExtValue() == Val; 1685} 1686 1687ALWAYS_INLINE static bool 1688CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1689 SDValue N, SelectionDAGISel &SDISel) { 1690 int64_t Val = MatcherTable[MatcherIndex++]; 1691 if (Val & 128) 1692 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1693 1694 if (N->getOpcode() != ISD::AND) return false; 1695 1696 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1697 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1698} 1699 1700ALWAYS_INLINE static bool 1701CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1702 SDValue N, SelectionDAGISel &SDISel) { 1703 int64_t Val = MatcherTable[MatcherIndex++]; 1704 if (Val & 128) 1705 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1706 1707 if (N->getOpcode() != ISD::OR) return false; 1708 1709 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1710 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1711} 1712 1713/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1714/// scope, evaluate the current node. If the current predicate is known to 1715/// fail, set Result=true and return anything. If the current predicate is 1716/// known to pass, set Result=false and return the MatcherIndex to continue 1717/// with. If the current predicate is unknown, set Result=false and return the 1718/// MatcherIndex to continue with. 1719static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1720 unsigned Index, SDValue N, 1721 bool &Result, SelectionDAGISel &SDISel, 1722 SmallVectorImpl<SDValue> &RecordedNodes){ 1723 switch (Table[Index++]) { 1724 default: 1725 Result = false; 1726 return Index-1; // Could not evaluate this predicate. 1727 case SelectionDAGISel::OPC_CheckSame: 1728 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1729 return Index; 1730 case SelectionDAGISel::OPC_CheckPatternPredicate: 1731 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1732 return Index; 1733 case SelectionDAGISel::OPC_CheckPredicate: 1734 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1735 return Index; 1736 case SelectionDAGISel::OPC_CheckOpcode: 1737 Result = !::CheckOpcode(Table, Index, N.getNode()); 1738 return Index; 1739 case SelectionDAGISel::OPC_CheckType: 1740 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1741 return Index; 1742 case SelectionDAGISel::OPC_CheckChild0Type: 1743 case SelectionDAGISel::OPC_CheckChild1Type: 1744 case SelectionDAGISel::OPC_CheckChild2Type: 1745 case SelectionDAGISel::OPC_CheckChild3Type: 1746 case SelectionDAGISel::OPC_CheckChild4Type: 1747 case SelectionDAGISel::OPC_CheckChild5Type: 1748 case SelectionDAGISel::OPC_CheckChild6Type: 1749 case SelectionDAGISel::OPC_CheckChild7Type: 1750 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1751 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1752 return Index; 1753 case SelectionDAGISel::OPC_CheckCondCode: 1754 Result = !::CheckCondCode(Table, Index, N); 1755 return Index; 1756 case SelectionDAGISel::OPC_CheckValueType: 1757 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1758 return Index; 1759 case SelectionDAGISel::OPC_CheckInteger: 1760 Result = !::CheckInteger(Table, Index, N); 1761 return Index; 1762 case SelectionDAGISel::OPC_CheckAndImm: 1763 Result = !::CheckAndImm(Table, Index, N, SDISel); 1764 return Index; 1765 case SelectionDAGISel::OPC_CheckOrImm: 1766 Result = !::CheckOrImm(Table, Index, N, SDISel); 1767 return Index; 1768 } 1769} 1770 1771namespace { 1772 1773struct MatchScope { 1774 /// FailIndex - If this match fails, this is the index to continue with. 1775 unsigned FailIndex; 1776 1777 /// NodeStack - The node stack when the scope was formed. 1778 SmallVector<SDValue, 4> NodeStack; 1779 1780 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1781 unsigned NumRecordedNodes; 1782 1783 /// NumMatchedMemRefs - The number of matched memref entries. 1784 unsigned NumMatchedMemRefs; 1785 1786 /// InputChain/InputFlag - The current chain/flag 1787 SDValue InputChain, InputFlag; 1788 1789 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1790 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1791}; 1792 1793} 1794 1795SDNode *SelectionDAGISel:: 1796SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1797 unsigned TableSize) { 1798 // FIXME: Should these even be selected? Handle these cases in the caller? 1799 switch (NodeToMatch->getOpcode()) { 1800 default: 1801 break; 1802 case ISD::EntryToken: // These nodes remain the same. 1803 case ISD::BasicBlock: 1804 case ISD::Register: 1805 //case ISD::VALUETYPE: 1806 //case ISD::CONDCODE: 1807 case ISD::HANDLENODE: 1808 case ISD::MDNODE_SDNODE: 1809 case ISD::TargetConstant: 1810 case ISD::TargetConstantFP: 1811 case ISD::TargetConstantPool: 1812 case ISD::TargetFrameIndex: 1813 case ISD::TargetExternalSymbol: 1814 case ISD::TargetBlockAddress: 1815 case ISD::TargetJumpTable: 1816 case ISD::TargetGlobalTLSAddress: 1817 case ISD::TargetGlobalAddress: 1818 case ISD::TokenFactor: 1819 case ISD::CopyFromReg: 1820 case ISD::CopyToReg: 1821 case ISD::EH_LABEL: 1822 NodeToMatch->setNodeId(-1); // Mark selected. 1823 return 0; 1824 case ISD::AssertSext: 1825 case ISD::AssertZext: 1826 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1827 NodeToMatch->getOperand(0)); 1828 return 0; 1829 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1830 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1831 } 1832 1833 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1834 1835 // Set up the node stack with NodeToMatch as the only node on the stack. 1836 SmallVector<SDValue, 8> NodeStack; 1837 SDValue N = SDValue(NodeToMatch, 0); 1838 NodeStack.push_back(N); 1839 1840 // MatchScopes - Scopes used when matching, if a match failure happens, this 1841 // indicates where to continue checking. 1842 SmallVector<MatchScope, 8> MatchScopes; 1843 1844 // RecordedNodes - This is the set of nodes that have been recorded by the 1845 // state machine. 1846 SmallVector<SDValue, 8> RecordedNodes; 1847 1848 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1849 // pattern. 1850 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1851 1852 // These are the current input chain and flag for use when generating nodes. 1853 // Various Emit operations change these. For example, emitting a copytoreg 1854 // uses and updates these. 1855 SDValue InputChain, InputFlag; 1856 1857 // ChainNodesMatched - If a pattern matches nodes that have input/output 1858 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1859 // which ones they are. The result is captured into this list so that we can 1860 // update the chain results when the pattern is complete. 1861 SmallVector<SDNode*, 3> ChainNodesMatched; 1862 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1863 1864 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1865 NodeToMatch->dump(CurDAG); 1866 errs() << '\n'); 1867 1868 // Determine where to start the interpreter. Normally we start at opcode #0, 1869 // but if the state machine starts with an OPC_SwitchOpcode, then we 1870 // accelerate the first lookup (which is guaranteed to be hot) with the 1871 // OpcodeOffset table. 1872 unsigned MatcherIndex = 0; 1873 1874 if (!OpcodeOffset.empty()) { 1875 // Already computed the OpcodeOffset table, just index into it. 1876 if (N.getOpcode() < OpcodeOffset.size()) 1877 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1878 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1879 1880 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1881 // Otherwise, the table isn't computed, but the state machine does start 1882 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1883 // is the first time we're selecting an instruction. 1884 unsigned Idx = 1; 1885 while (1) { 1886 // Get the size of this case. 1887 unsigned CaseSize = MatcherTable[Idx++]; 1888 if (CaseSize & 128) 1889 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1890 if (CaseSize == 0) break; 1891 1892 // Get the opcode, add the index to the table. 1893 uint16_t Opc = MatcherTable[Idx++]; 1894 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 1895 if (Opc >= OpcodeOffset.size()) 1896 OpcodeOffset.resize((Opc+1)*2); 1897 OpcodeOffset[Opc] = Idx; 1898 Idx += CaseSize; 1899 } 1900 1901 // Okay, do the lookup for the first opcode. 1902 if (N.getOpcode() < OpcodeOffset.size()) 1903 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1904 } 1905 1906 while (1) { 1907 assert(MatcherIndex < TableSize && "Invalid index"); 1908#ifndef NDEBUG 1909 unsigned CurrentOpcodeIndex = MatcherIndex; 1910#endif 1911 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 1912 switch (Opcode) { 1913 case OPC_Scope: { 1914 // Okay, the semantics of this operation are that we should push a scope 1915 // then evaluate the first child. However, pushing a scope only to have 1916 // the first check fail (which then pops it) is inefficient. If we can 1917 // determine immediately that the first check (or first several) will 1918 // immediately fail, don't even bother pushing a scope for them. 1919 unsigned FailIndex; 1920 1921 while (1) { 1922 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 1923 if (NumToSkip & 128) 1924 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 1925 // Found the end of the scope with no match. 1926 if (NumToSkip == 0) { 1927 FailIndex = 0; 1928 break; 1929 } 1930 1931 FailIndex = MatcherIndex+NumToSkip; 1932 1933 unsigned MatcherIndexOfPredicate = MatcherIndex; 1934 (void)MatcherIndexOfPredicate; // silence warning. 1935 1936 // If we can't evaluate this predicate without pushing a scope (e.g. if 1937 // it is a 'MoveParent') or if the predicate succeeds on this node, we 1938 // push the scope and evaluate the full predicate chain. 1939 bool Result; 1940 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 1941 Result, *this, RecordedNodes); 1942 if (!Result) 1943 break; 1944 1945 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 1946 << "index " << MatcherIndexOfPredicate 1947 << ", continuing at " << FailIndex << "\n"); 1948 ++NumDAGIselRetries; 1949 1950 // Otherwise, we know that this case of the Scope is guaranteed to fail, 1951 // move to the next case. 1952 MatcherIndex = FailIndex; 1953 } 1954 1955 // If the whole scope failed to match, bail. 1956 if (FailIndex == 0) break; 1957 1958 // Push a MatchScope which indicates where to go if the first child fails 1959 // to match. 1960 MatchScope NewEntry; 1961 NewEntry.FailIndex = FailIndex; 1962 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 1963 NewEntry.NumRecordedNodes = RecordedNodes.size(); 1964 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 1965 NewEntry.InputChain = InputChain; 1966 NewEntry.InputFlag = InputFlag; 1967 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 1968 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 1969 MatchScopes.push_back(NewEntry); 1970 continue; 1971 } 1972 case OPC_RecordNode: 1973 // Remember this node, it may end up being an operand in the pattern. 1974 RecordedNodes.push_back(N); 1975 continue; 1976 1977 case OPC_RecordChild0: case OPC_RecordChild1: 1978 case OPC_RecordChild2: case OPC_RecordChild3: 1979 case OPC_RecordChild4: case OPC_RecordChild5: 1980 case OPC_RecordChild6: case OPC_RecordChild7: { 1981 unsigned ChildNo = Opcode-OPC_RecordChild0; 1982 if (ChildNo >= N.getNumOperands()) 1983 break; // Match fails if out of range child #. 1984 1985 RecordedNodes.push_back(N->getOperand(ChildNo)); 1986 continue; 1987 } 1988 case OPC_RecordMemRef: 1989 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 1990 continue; 1991 1992 case OPC_CaptureFlagInput: 1993 // If the current node has an input flag, capture it in InputFlag. 1994 if (N->getNumOperands() != 0 && 1995 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 1996 InputFlag = N->getOperand(N->getNumOperands()-1); 1997 continue; 1998 1999 case OPC_MoveChild: { 2000 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2001 if (ChildNo >= N.getNumOperands()) 2002 break; // Match fails if out of range child #. 2003 N = N.getOperand(ChildNo); 2004 NodeStack.push_back(N); 2005 continue; 2006 } 2007 2008 case OPC_MoveParent: 2009 // Pop the current node off the NodeStack. 2010 NodeStack.pop_back(); 2011 assert(!NodeStack.empty() && "Node stack imbalance!"); 2012 N = NodeStack.back(); 2013 continue; 2014 2015 case OPC_CheckSame: 2016 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2017 continue; 2018 case OPC_CheckPatternPredicate: 2019 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2020 continue; 2021 case OPC_CheckPredicate: 2022 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2023 N.getNode())) 2024 break; 2025 continue; 2026 case OPC_CheckComplexPat: { 2027 unsigned CPNum = MatcherTable[MatcherIndex++]; 2028 unsigned RecNo = MatcherTable[MatcherIndex++]; 2029 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2030 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2031 RecordedNodes)) 2032 break; 2033 continue; 2034 } 2035 case OPC_CheckOpcode: 2036 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2037 continue; 2038 2039 case OPC_CheckType: 2040 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2041 continue; 2042 2043 case OPC_SwitchOpcode: { 2044 unsigned CurNodeOpcode = N.getOpcode(); 2045 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2046 unsigned CaseSize; 2047 while (1) { 2048 // Get the size of this case. 2049 CaseSize = MatcherTable[MatcherIndex++]; 2050 if (CaseSize & 128) 2051 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2052 if (CaseSize == 0) break; 2053 2054 uint16_t Opc = MatcherTable[MatcherIndex++]; 2055 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2056 2057 // If the opcode matches, then we will execute this case. 2058 if (CurNodeOpcode == Opc) 2059 break; 2060 2061 // Otherwise, skip over this case. 2062 MatcherIndex += CaseSize; 2063 } 2064 2065 // If no cases matched, bail out. 2066 if (CaseSize == 0) break; 2067 2068 // Otherwise, execute the case we found. 2069 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2070 << " to " << MatcherIndex << "\n"); 2071 continue; 2072 } 2073 2074 case OPC_SwitchType: { 2075 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2076 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2077 unsigned CaseSize; 2078 while (1) { 2079 // Get the size of this case. 2080 CaseSize = MatcherTable[MatcherIndex++]; 2081 if (CaseSize & 128) 2082 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2083 if (CaseSize == 0) break; 2084 2085 MVT::SimpleValueType CaseVT = 2086 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2087 if (CaseVT == MVT::iPTR) 2088 CaseVT = TLI.getPointerTy().SimpleTy; 2089 2090 // If the VT matches, then we will execute this case. 2091 if (CurNodeVT == CaseVT) 2092 break; 2093 2094 // Otherwise, skip over this case. 2095 MatcherIndex += CaseSize; 2096 } 2097 2098 // If no cases matched, bail out. 2099 if (CaseSize == 0) break; 2100 2101 // Otherwise, execute the case we found. 2102 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2103 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2104 continue; 2105 } 2106 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2107 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2108 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2109 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2110 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2111 Opcode-OPC_CheckChild0Type)) 2112 break; 2113 continue; 2114 case OPC_CheckCondCode: 2115 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2116 continue; 2117 case OPC_CheckValueType: 2118 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2119 continue; 2120 case OPC_CheckInteger: 2121 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2122 continue; 2123 case OPC_CheckAndImm: 2124 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2125 continue; 2126 case OPC_CheckOrImm: 2127 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2128 continue; 2129 2130 case OPC_CheckFoldableChainNode: { 2131 assert(NodeStack.size() != 1 && "No parent node"); 2132 // Verify that all intermediate nodes between the root and this one have 2133 // a single use. 2134 bool HasMultipleUses = false; 2135 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2136 if (!NodeStack[i].hasOneUse()) { 2137 HasMultipleUses = true; 2138 break; 2139 } 2140 if (HasMultipleUses) break; 2141 2142 // Check to see that the target thinks this is profitable to fold and that 2143 // we can fold it without inducing cycles in the graph. 2144 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2145 NodeToMatch) || 2146 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2147 NodeToMatch, OptLevel, 2148 true/*We validate our own chains*/)) 2149 break; 2150 2151 continue; 2152 } 2153 case OPC_EmitInteger: { 2154 MVT::SimpleValueType VT = 2155 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2156 int64_t Val = MatcherTable[MatcherIndex++]; 2157 if (Val & 128) 2158 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2159 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2160 continue; 2161 } 2162 case OPC_EmitRegister: { 2163 MVT::SimpleValueType VT = 2164 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2165 unsigned RegNo = MatcherTable[MatcherIndex++]; 2166 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2167 continue; 2168 } 2169 2170 case OPC_EmitConvertToTarget: { 2171 // Convert from IMM/FPIMM to target version. 2172 unsigned RecNo = MatcherTable[MatcherIndex++]; 2173 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2174 SDValue Imm = RecordedNodes[RecNo]; 2175 2176 if (Imm->getOpcode() == ISD::Constant) { 2177 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2178 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2179 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2180 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2181 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2182 } 2183 2184 RecordedNodes.push_back(Imm); 2185 continue; 2186 } 2187 2188 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2189 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2190 // These are space-optimized forms of OPC_EmitMergeInputChains. 2191 assert(InputChain.getNode() == 0 && 2192 "EmitMergeInputChains should be the first chain producing node"); 2193 assert(ChainNodesMatched.empty() && 2194 "Should only have one EmitMergeInputChains per match"); 2195 2196 // Read all of the chained nodes. 2197 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2198 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2199 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2200 2201 // FIXME: What if other value results of the node have uses not matched 2202 // by this pattern? 2203 if (ChainNodesMatched.back() != NodeToMatch && 2204 !RecordedNodes[RecNo].hasOneUse()) { 2205 ChainNodesMatched.clear(); 2206 break; 2207 } 2208 2209 // Merge the input chains if they are not intra-pattern references. 2210 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2211 2212 if (InputChain.getNode() == 0) 2213 break; // Failed to merge. 2214 continue; 2215 } 2216 2217 case OPC_EmitMergeInputChains: { 2218 assert(InputChain.getNode() == 0 && 2219 "EmitMergeInputChains should be the first chain producing node"); 2220 // This node gets a list of nodes we matched in the input that have 2221 // chains. We want to token factor all of the input chains to these nodes 2222 // together. However, if any of the input chains is actually one of the 2223 // nodes matched in this pattern, then we have an intra-match reference. 2224 // Ignore these because the newly token factored chain should not refer to 2225 // the old nodes. 2226 unsigned NumChains = MatcherTable[MatcherIndex++]; 2227 assert(NumChains != 0 && "Can't TF zero chains"); 2228 2229 assert(ChainNodesMatched.empty() && 2230 "Should only have one EmitMergeInputChains per match"); 2231 2232 // Read all of the chained nodes. 2233 for (unsigned i = 0; i != NumChains; ++i) { 2234 unsigned RecNo = MatcherTable[MatcherIndex++]; 2235 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2236 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2237 2238 // FIXME: What if other value results of the node have uses not matched 2239 // by this pattern? 2240 if (ChainNodesMatched.back() != NodeToMatch && 2241 !RecordedNodes[RecNo].hasOneUse()) { 2242 ChainNodesMatched.clear(); 2243 break; 2244 } 2245 } 2246 2247 // If the inner loop broke out, the match fails. 2248 if (ChainNodesMatched.empty()) 2249 break; 2250 2251 // Merge the input chains if they are not intra-pattern references. 2252 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2253 2254 if (InputChain.getNode() == 0) 2255 break; // Failed to merge. 2256 2257 continue; 2258 } 2259 2260 case OPC_EmitCopyToReg: { 2261 unsigned RecNo = MatcherTable[MatcherIndex++]; 2262 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2263 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2264 2265 if (InputChain.getNode() == 0) 2266 InputChain = CurDAG->getEntryNode(); 2267 2268 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2269 DestPhysReg, RecordedNodes[RecNo], 2270 InputFlag); 2271 2272 InputFlag = InputChain.getValue(1); 2273 continue; 2274 } 2275 2276 case OPC_EmitNodeXForm: { 2277 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2278 unsigned RecNo = MatcherTable[MatcherIndex++]; 2279 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2280 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2281 continue; 2282 } 2283 2284 case OPC_EmitNode: 2285 case OPC_MorphNodeTo: { 2286 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2287 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2288 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2289 // Get the result VT list. 2290 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2291 SmallVector<EVT, 4> VTs; 2292 for (unsigned i = 0; i != NumVTs; ++i) { 2293 MVT::SimpleValueType VT = 2294 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2295 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2296 VTs.push_back(VT); 2297 } 2298 2299 if (EmitNodeInfo & OPFL_Chain) 2300 VTs.push_back(MVT::Other); 2301 if (EmitNodeInfo & OPFL_FlagOutput) 2302 VTs.push_back(MVT::Flag); 2303 2304 // This is hot code, so optimize the two most common cases of 1 and 2 2305 // results. 2306 SDVTList VTList; 2307 if (VTs.size() == 1) 2308 VTList = CurDAG->getVTList(VTs[0]); 2309 else if (VTs.size() == 2) 2310 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2311 else 2312 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2313 2314 // Get the operand list. 2315 unsigned NumOps = MatcherTable[MatcherIndex++]; 2316 SmallVector<SDValue, 8> Ops; 2317 for (unsigned i = 0; i != NumOps; ++i) { 2318 unsigned RecNo = MatcherTable[MatcherIndex++]; 2319 if (RecNo & 128) 2320 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2321 2322 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2323 Ops.push_back(RecordedNodes[RecNo]); 2324 } 2325 2326 // If there are variadic operands to add, handle them now. 2327 if (EmitNodeInfo & OPFL_VariadicInfo) { 2328 // Determine the start index to copy from. 2329 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2330 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2331 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2332 "Invalid variadic node"); 2333 // Copy all of the variadic operands, not including a potential flag 2334 // input. 2335 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2336 i != e; ++i) { 2337 SDValue V = NodeToMatch->getOperand(i); 2338 if (V.getValueType() == MVT::Flag) break; 2339 Ops.push_back(V); 2340 } 2341 } 2342 2343 // If this has chain/flag inputs, add them. 2344 if (EmitNodeInfo & OPFL_Chain) 2345 Ops.push_back(InputChain); 2346 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2347 Ops.push_back(InputFlag); 2348 2349 // Create the node. 2350 SDNode *Res = 0; 2351 if (Opcode != OPC_MorphNodeTo) { 2352 // If this is a normal EmitNode command, just create the new node and 2353 // add the results to the RecordedNodes list. 2354 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2355 VTList, Ops.data(), Ops.size()); 2356 2357 // Add all the non-flag/non-chain results to the RecordedNodes list. 2358 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2359 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2360 RecordedNodes.push_back(SDValue(Res, i)); 2361 } 2362 2363 } else { 2364 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2365 EmitNodeInfo); 2366 } 2367 2368 // If the node had chain/flag results, update our notion of the current 2369 // chain and flag. 2370 if (EmitNodeInfo & OPFL_FlagOutput) { 2371 InputFlag = SDValue(Res, VTs.size()-1); 2372 if (EmitNodeInfo & OPFL_Chain) 2373 InputChain = SDValue(Res, VTs.size()-2); 2374 } else if (EmitNodeInfo & OPFL_Chain) 2375 InputChain = SDValue(Res, VTs.size()-1); 2376 2377 // If the OPFL_MemRefs flag is set on this node, slap all of the 2378 // accumulated memrefs onto it. 2379 // 2380 // FIXME: This is vastly incorrect for patterns with multiple outputs 2381 // instructions that access memory and for ComplexPatterns that match 2382 // loads. 2383 if (EmitNodeInfo & OPFL_MemRefs) { 2384 MachineSDNode::mmo_iterator MemRefs = 2385 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2386 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2387 cast<MachineSDNode>(Res) 2388 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2389 } 2390 2391 DEBUG(errs() << " " 2392 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2393 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2394 2395 // If this was a MorphNodeTo then we're completely done! 2396 if (Opcode == OPC_MorphNodeTo) { 2397 // Update chain and flag uses. 2398 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2399 InputFlag, FlagResultNodesMatched, true); 2400 return Res; 2401 } 2402 2403 continue; 2404 } 2405 2406 case OPC_MarkFlagResults: { 2407 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2408 2409 // Read and remember all the flag-result nodes. 2410 for (unsigned i = 0; i != NumNodes; ++i) { 2411 unsigned RecNo = MatcherTable[MatcherIndex++]; 2412 if (RecNo & 128) 2413 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2414 2415 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2416 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2417 } 2418 continue; 2419 } 2420 2421 case OPC_CompleteMatch: { 2422 // The match has been completed, and any new nodes (if any) have been 2423 // created. Patch up references to the matched dag to use the newly 2424 // created nodes. 2425 unsigned NumResults = MatcherTable[MatcherIndex++]; 2426 2427 for (unsigned i = 0; i != NumResults; ++i) { 2428 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2429 if (ResSlot & 128) 2430 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2431 2432 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2433 SDValue Res = RecordedNodes[ResSlot]; 2434 2435 assert(i < NodeToMatch->getNumValues() && 2436 NodeToMatch->getValueType(i) != MVT::Other && 2437 NodeToMatch->getValueType(i) != MVT::Flag && 2438 "Invalid number of results to complete!"); 2439 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2440 NodeToMatch->getValueType(i) == MVT::iPTR || 2441 Res.getValueType() == MVT::iPTR || 2442 NodeToMatch->getValueType(i).getSizeInBits() == 2443 Res.getValueType().getSizeInBits()) && 2444 "invalid replacement"); 2445 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2446 } 2447 2448 // If the root node defines a flag, add it to the flag nodes to update 2449 // list. 2450 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2451 FlagResultNodesMatched.push_back(NodeToMatch); 2452 2453 // Update chain and flag uses. 2454 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2455 InputFlag, FlagResultNodesMatched, false); 2456 2457 assert(NodeToMatch->use_empty() && 2458 "Didn't replace all uses of the node?"); 2459 2460 // FIXME: We just return here, which interacts correctly with SelectRoot 2461 // above. We should fix this to not return an SDNode* anymore. 2462 return 0; 2463 } 2464 } 2465 2466 // If the code reached this point, then the match failed. See if there is 2467 // another child to try in the current 'Scope', otherwise pop it until we 2468 // find a case to check. 2469 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2470 ++NumDAGIselRetries; 2471 while (1) { 2472 if (MatchScopes.empty()) { 2473 CannotYetSelect(NodeToMatch); 2474 return 0; 2475 } 2476 2477 // Restore the interpreter state back to the point where the scope was 2478 // formed. 2479 MatchScope &LastScope = MatchScopes.back(); 2480 RecordedNodes.resize(LastScope.NumRecordedNodes); 2481 NodeStack.clear(); 2482 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2483 N = NodeStack.back(); 2484 2485 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2486 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2487 MatcherIndex = LastScope.FailIndex; 2488 2489 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2490 2491 InputChain = LastScope.InputChain; 2492 InputFlag = LastScope.InputFlag; 2493 if (!LastScope.HasChainNodesMatched) 2494 ChainNodesMatched.clear(); 2495 if (!LastScope.HasFlagResultNodesMatched) 2496 FlagResultNodesMatched.clear(); 2497 2498 // Check to see what the offset is at the new MatcherIndex. If it is zero 2499 // we have reached the end of this scope, otherwise we have another child 2500 // in the current scope to try. 2501 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2502 if (NumToSkip & 128) 2503 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2504 2505 // If we have another child in this scope to match, update FailIndex and 2506 // try it. 2507 if (NumToSkip != 0) { 2508 LastScope.FailIndex = MatcherIndex+NumToSkip; 2509 break; 2510 } 2511 2512 // End of this scope, pop it and try the next child in the containing 2513 // scope. 2514 MatchScopes.pop_back(); 2515 } 2516 } 2517} 2518 2519 2520 2521void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2522 std::string msg; 2523 raw_string_ostream Msg(msg); 2524 Msg << "Cannot yet select: "; 2525 2526 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2527 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2528 N->getOpcode() != ISD::INTRINSIC_VOID) { 2529 N->printrFull(Msg, CurDAG); 2530 } else { 2531 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2532 unsigned iid = 2533 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2534 if (iid < Intrinsic::num_intrinsics) 2535 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2536 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2537 Msg << "target intrinsic %" << TII->getName(iid); 2538 else 2539 Msg << "unknown intrinsic #" << iid; 2540 } 2541 report_fatal_error(Msg.str()); 2542} 2543 2544char SelectionDAGISel::ID = 0; 2545