SelectionDAGISel.cpp revision 6411e3e62ea9dfe23f5fa24b9d6a84da7ec70a98
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/FastISel.h" 32#include "llvm/CodeGen/GCStrategy.h" 33#include "llvm/CodeGen/GCMetadata.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineFunctionAnalysis.h" 36#include "llvm/CodeGen/MachineFrameInfo.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineJumpTableInfo.h" 39#include "llvm/CodeGen/MachineModuleInfo.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 42#include "llvm/CodeGen/SchedulerRegistry.h" 43#include "llvm/CodeGen/SelectionDAG.h" 44#include "llvm/CodeGen/DwarfWriter.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameInfo.h" 48#include "llvm/Target/TargetIntrinsicInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetLowering.h" 51#include "llvm/Target/TargetMachine.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/Timer.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62static cl::opt<bool> 63EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 64 cl::desc("Enable verbose messages in the \"fast\" " 65 "instruction selector")); 66static cl::opt<bool> 67EnableFastISelAbort("fast-isel-abort", cl::Hidden, 68 cl::desc("Enable abort calls when \"fast\" instruction fails")); 69static cl::opt<bool> 70SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 71 cl::desc("Schedule copies of livein registers"), 72 cl::init(false)); 73 74#ifndef NDEBUG 75static cl::opt<bool> 76ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the first " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before legalize types")); 82static cl::opt<bool> 83ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize")); 85static cl::opt<bool> 86ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before the second " 88 "dag combine pass")); 89static cl::opt<bool> 90ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 91 cl::desc("Pop up a window to show dags before the post legalize types" 92 " dag combine pass")); 93static cl::opt<bool> 94ViewISelDAGs("view-isel-dags", cl::Hidden, 95 cl::desc("Pop up a window to show isel dags as they are selected")); 96static cl::opt<bool> 97ViewSchedDAGs("view-sched-dags", cl::Hidden, 98 cl::desc("Pop up a window to show sched dags as they are processed")); 99static cl::opt<bool> 100ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 101 cl::desc("Pop up a window to show SUnit dags after they are processed")); 102#else 103static const bool ViewDAGCombine1 = false, 104 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 105 ViewDAGCombine2 = false, 106 ViewDAGCombineLT = false, 107 ViewISelDAGs = false, ViewSchedDAGs = false, 108 ViewSUnitDAGs = false; 109#endif 110 111//===---------------------------------------------------------------------===// 112/// 113/// RegisterScheduler class - Track the registration of instruction schedulers. 114/// 115//===---------------------------------------------------------------------===// 116MachinePassRegistry RegisterScheduler::Registry; 117 118//===---------------------------------------------------------------------===// 119/// 120/// ISHeuristic command line option for instruction schedulers. 121/// 122//===---------------------------------------------------------------------===// 123static cl::opt<RegisterScheduler::FunctionPassCtor, false, 124 RegisterPassParser<RegisterScheduler> > 125ISHeuristic("pre-RA-sched", 126 cl::init(&createDefaultScheduler), 127 cl::desc("Instruction schedulers available (before register" 128 " allocation):")); 129 130static RegisterScheduler 131defaultListDAGScheduler("default", "Best scheduler for the target", 132 createDefaultScheduler); 133 134namespace llvm { 135 //===--------------------------------------------------------------------===// 136 /// createDefaultScheduler - This creates an instruction scheduler appropriate 137 /// for the target. 138 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 139 CodeGenOpt::Level OptLevel) { 140 const TargetLowering &TLI = IS->getTargetLowering(); 141 142 if (OptLevel == CodeGenOpt::None) 143 return createFastDAGScheduler(IS, OptLevel); 144 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 145 return createTDListDAGScheduler(IS, OptLevel); 146 assert(TLI.getSchedulingPreference() == 147 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 148 return createBURRListDAGScheduler(IS, OptLevel); 149 } 150} 151 152// EmitInstrWithCustomInserter - This method should be implemented by targets 153// that mark instructions with the 'usesCustomInserter' flag. These 154// instructions are special in various ways, which require special support to 155// insert. The specified MachineInstr is created but not inserted into any 156// basic blocks, and this method is called to expand it into a sequence of 157// instructions, potentially also creating new basic blocks and control flow. 158// When new basic blocks are inserted and the edges from MBB to its successors 159// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 160// DenseMap. 161MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 162 MachineBasicBlock *MBB, 163 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 164#ifndef NDEBUG 165 dbgs() << "If a target marks an instruction with " 166 "'usesCustomInserter', it must implement " 167 "TargetLowering::EmitInstrWithCustomInserter!"; 168#endif 169 llvm_unreachable(0); 170 return 0; 171} 172 173/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 174/// physical register has only a single copy use, then coalesced the copy 175/// if possible. 176static void EmitLiveInCopy(MachineBasicBlock *MBB, 177 MachineBasicBlock::iterator &InsertPos, 178 unsigned VirtReg, unsigned PhysReg, 179 const TargetRegisterClass *RC, 180 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 181 const MachineRegisterInfo &MRI, 182 const TargetRegisterInfo &TRI, 183 const TargetInstrInfo &TII) { 184 unsigned NumUses = 0; 185 MachineInstr *UseMI = NULL; 186 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 187 UE = MRI.use_end(); UI != UE; ++UI) { 188 UseMI = &*UI; 189 if (++NumUses > 1) 190 break; 191 } 192 193 // If the number of uses is not one, or the use is not a move instruction, 194 // don't coalesce. Also, only coalesce away a virtual register to virtual 195 // register copy. 196 bool Coalesced = false; 197 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 198 if (NumUses == 1 && 199 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 200 TargetRegisterInfo::isVirtualRegister(DstReg)) { 201 VirtReg = DstReg; 202 Coalesced = true; 203 } 204 205 // Now find an ideal location to insert the copy. 206 MachineBasicBlock::iterator Pos = InsertPos; 207 while (Pos != MBB->begin()) { 208 MachineInstr *PrevMI = prior(Pos); 209 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 210 // copyRegToReg might emit multiple instructions to do a copy. 211 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 212 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 213 // This is what the BB looks like right now: 214 // r1024 = mov r0 215 // ... 216 // r1 = mov r1024 217 // 218 // We want to insert "r1025 = mov r1". Inserting this copy below the 219 // move to r1024 makes it impossible for that move to be coalesced. 220 // 221 // r1025 = mov r1 222 // r1024 = mov r0 223 // ... 224 // r1 = mov 1024 225 // r2 = mov 1025 226 break; // Woot! Found a good location. 227 --Pos; 228 } 229 230 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 231 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 232 (void) Emitted; 233 234 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 235 if (Coalesced) { 236 if (&*InsertPos == UseMI) ++InsertPos; 237 MBB->erase(UseMI); 238 } 239} 240 241/// EmitLiveInCopies - If this is the first basic block in the function, 242/// and if it has live ins that need to be copied into vregs, emit the 243/// copies into the block. 244static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 245 const MachineRegisterInfo &MRI, 246 const TargetRegisterInfo &TRI, 247 const TargetInstrInfo &TII) { 248 if (SchedLiveInCopies) { 249 // Emit the copies at a heuristically-determined location in the block. 250 DenseMap<MachineInstr*, unsigned> CopyRegMap; 251 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 252 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 253 E = MRI.livein_end(); LI != E; ++LI) 254 if (LI->second) { 255 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 256 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 257 RC, CopyRegMap, MRI, TRI, TII); 258 } 259 } else { 260 // Emit the copies into the top of the block. 261 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 262 E = MRI.livein_end(); LI != E; ++LI) 263 if (LI->second) { 264 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 265 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 266 LI->second, LI->first, RC, RC); 267 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 268 (void) Emitted; 269 } 270 } 271} 272 273//===----------------------------------------------------------------------===// 274// SelectionDAGISel code 275//===----------------------------------------------------------------------===// 276 277SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 278 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 279 FuncInfo(new FunctionLoweringInfo(TLI)), 280 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 281 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 282 GFI(), 283 OptLevel(OL), 284 DAGSize(0) 285{} 286 287SelectionDAGISel::~SelectionDAGISel() { 288 delete SDB; 289 delete CurDAG; 290 delete FuncInfo; 291} 292 293unsigned SelectionDAGISel::MakeReg(EVT VT) { 294 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 295} 296 297void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 298 AU.addRequired<AliasAnalysis>(); 299 AU.addPreserved<AliasAnalysis>(); 300 AU.addRequired<GCModuleInfo>(); 301 AU.addPreserved<GCModuleInfo>(); 302 AU.addRequired<DwarfWriter>(); 303 AU.addPreserved<DwarfWriter>(); 304 MachineFunctionPass::getAnalysisUsage(AU); 305} 306 307bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 308 Function &Fn = *mf.getFunction(); 309 310 // Do some sanity-checking on the command-line options. 311 assert((!EnableFastISelVerbose || EnableFastISel) && 312 "-fast-isel-verbose requires -fast-isel"); 313 assert((!EnableFastISelAbort || EnableFastISel) && 314 "-fast-isel-abort requires -fast-isel"); 315 316 // Get alias analysis for load/store combining. 317 AA = &getAnalysis<AliasAnalysis>(); 318 319 MF = &mf; 320 const TargetInstrInfo &TII = *TM.getInstrInfo(); 321 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 322 323 if (Fn.hasGC()) 324 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 325 else 326 GFI = 0; 327 RegInfo = &MF->getRegInfo(); 328 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 329 330 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 331 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 332 CurDAG->init(*MF, MMI, DW); 333 FuncInfo->set(Fn, *MF, EnableFastISel); 334 SDB->init(GFI, *AA); 335 336 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 337 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 338 // Mark landing pad. 339 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 340 341 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 342 343 // If the first basic block in the function has live ins that need to be 344 // copied into vregs, emit the copies into the top of the block before 345 // emitting the code for the block. 346 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 347 348 // Add function live-ins to entry block live-in set. 349 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 350 E = RegInfo->livein_end(); I != E; ++I) 351 MF->begin()->addLiveIn(I->first); 352 353#ifndef NDEBUG 354 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 355 "Not all catch info was assigned to a landing pad!"); 356#endif 357 358 FuncInfo->clear(); 359 360 return true; 361} 362 363/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 364/// attached with this instruction. 365static void SetDebugLoc(unsigned MDDbgKind, Instruction *I, 366 SelectionDAGBuilder *SDB, 367 FastISel *FastIS, MachineFunction *MF) { 368 if (isa<DbgInfoIntrinsic>(I)) return; 369 370 if (MDNode *Dbg = I->getMetadata(MDDbgKind)) { 371 DILocation DILoc(Dbg); 372 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo()); 373 374 SDB->setCurDebugLoc(Loc); 375 376 if (FastIS) 377 FastIS->setCurDebugLoc(Loc); 378 379 // If the function doesn't have a default debug location yet, set 380 // it. This is kind of a hack. 381 if (MF->getDefaultDebugLoc().isUnknown()) 382 MF->setDefaultDebugLoc(Loc); 383 } 384} 385 386/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 387static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 388 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc()); 389 if (FastIS) 390 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc()); 391} 392 393void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 394 BasicBlock::iterator Begin, 395 BasicBlock::iterator End, 396 bool &HadTailCall) { 397 SDB->setCurrentBasicBlock(BB); 398 unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg"); 399 400 // Lower all of the non-terminator instructions. If a call is emitted 401 // as a tail call, cease emitting nodes for this block. 402 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 403 SetDebugLoc(MDDbgKind, I, SDB, 0, MF); 404 405 if (!isa<TerminatorInst>(I)) { 406 SDB->visit(*I); 407 408 // Set the current debug location back to "unknown" so that it doesn't 409 // spuriously apply to subsequent instructions. 410 ResetDebugLoc(SDB, 0); 411 } 412 } 413 414 if (!SDB->HasTailCall) { 415 // Ensure that all instructions which are used outside of their defining 416 // blocks are available as virtual registers. Invoke is handled elsewhere. 417 for (BasicBlock::iterator I = Begin; I != End; ++I) 418 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 419 SDB->CopyToExportRegsIfNeeded(I); 420 421 // Handle PHI nodes in successor blocks. 422 if (End == LLVMBB->end()) { 423 HandlePHINodesInSuccessorBlocks(LLVMBB); 424 425 // Lower the terminator after the copies are emitted. 426 SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF); 427 SDB->visit(*LLVMBB->getTerminator()); 428 ResetDebugLoc(SDB, 0); 429 } 430 } 431 432 // Make sure the root of the DAG is up-to-date. 433 CurDAG->setRoot(SDB->getControlRoot()); 434 435 // Final step, emit the lowered DAG as machine code. 436 CodeGenAndEmitDAG(); 437 HadTailCall = SDB->HasTailCall; 438 SDB->clear(); 439} 440 441namespace { 442/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 443/// nodes from the worklist. 444class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 445 SmallVector<SDNode*, 128> &Worklist; 446public: 447 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl) : Worklist(wl) {} 448 449 virtual void NodeDeleted(SDNode *N, SDNode *E) { 450 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N), 451 Worklist.end()); 452 } 453 454 virtual void NodeUpdated(SDNode *N) { 455 // Ignore updates. 456 } 457}; 458} 459 460/// TrivialTruncElim - Eliminate some trivial nops that can result from 461/// ShrinkDemandedOps: (trunc (ext n)) -> n. 462static bool TrivialTruncElim(SDValue Op, 463 TargetLowering::TargetLoweringOpt &TLO) { 464 SDValue N0 = Op.getOperand(0); 465 EVT VT = Op.getValueType(); 466 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 467 N0.getOpcode() == ISD::SIGN_EXTEND || 468 N0.getOpcode() == ISD::ANY_EXTEND) && 469 N0.getOperand(0).getValueType() == VT) { 470 return TLO.CombineTo(Op, N0.getOperand(0)); 471 } 472 return false; 473} 474 475/// ShrinkDemandedOps - A late transformation pass that shrink expressions 476/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 477/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 478void SelectionDAGISel::ShrinkDemandedOps() { 479 SmallVector<SDNode*, 128> Worklist; 480 481 // Add all the dag nodes to the worklist. 482 Worklist.reserve(CurDAG->allnodes_size()); 483 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 484 E = CurDAG->allnodes_end(); I != E; ++I) 485 Worklist.push_back(I); 486 487 APInt Mask; 488 APInt KnownZero; 489 APInt KnownOne; 490 491 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true); 492 while (!Worklist.empty()) { 493 SDNode *N = Worklist.pop_back_val(); 494 495 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 496 CurDAG->DeleteNode(N); 497 continue; 498 } 499 500 // Run ShrinkDemandedOp on scalar binary operations. 501 if (N->getNumValues() == 1 && 502 N->getValueType(0).isSimple() && N->getValueType(0).isInteger()) { 503 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 504 APInt Demanded = APInt::getAllOnesValue(BitWidth); 505 APInt KnownZero, KnownOne; 506 if (TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 507 KnownZero, KnownOne, TLO) || 508 (N->getOpcode() == ISD::TRUNCATE && 509 TrivialTruncElim(SDValue(N, 0), TLO))) { 510 // Revisit the node. 511 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N), 512 Worklist.end()); 513 Worklist.push_back(N); 514 515 // Replace the old value with the new one. 516 DEBUG(errs() << "\nReplacing "; 517 TLO.Old.getNode()->dump(CurDAG); 518 errs() << "\nWith: "; 519 TLO.New.getNode()->dump(CurDAG); 520 errs() << '\n'); 521 522 Worklist.push_back(TLO.New.getNode()); 523 524 SDOPsWorkListRemover DeadNodes(Worklist); 525 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 526 527 if (TLO.Old.getNode()->use_empty()) { 528 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 529 i != e; ++i) { 530 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 531 if (OpNode->hasOneUse()) { 532 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), 533 OpNode), Worklist.end()); 534 Worklist.push_back(OpNode); 535 } 536 } 537 538 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), 539 TLO.Old.getNode()), Worklist.end()); 540 CurDAG->DeleteNode(TLO.Old.getNode()); 541 } 542 } 543 } 544 } 545} 546 547void SelectionDAGISel::ComputeLiveOutVRegInfo() { 548 SmallPtrSet<SDNode*, 128> VisitedNodes; 549 SmallVector<SDNode*, 128> Worklist; 550 551 Worklist.push_back(CurDAG->getRoot().getNode()); 552 553 APInt Mask; 554 APInt KnownZero; 555 APInt KnownOne; 556 557 do { 558 SDNode *N = Worklist.pop_back_val(); 559 560 // If we've already seen this node, ignore it. 561 if (!VisitedNodes.insert(N)) 562 continue; 563 564 // Otherwise, add all chain operands to the worklist. 565 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 566 if (N->getOperand(i).getValueType() == MVT::Other) 567 Worklist.push_back(N->getOperand(i).getNode()); 568 569 // If this is a CopyToReg with a vreg dest, process it. 570 if (N->getOpcode() != ISD::CopyToReg) 571 continue; 572 573 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 574 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 575 continue; 576 577 // Ignore non-scalar or non-integer values. 578 SDValue Src = N->getOperand(2); 579 EVT SrcVT = Src.getValueType(); 580 if (!SrcVT.isInteger() || SrcVT.isVector()) 581 continue; 582 583 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 584 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 585 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 586 587 // Only install this information if it tells us something. 588 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 589 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 590 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 591 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 592 FunctionLoweringInfo::LiveOutInfo &LOI = 593 FuncInfo->LiveOutRegInfo[DestReg]; 594 LOI.NumSignBits = NumSignBits; 595 LOI.KnownOne = KnownOne; 596 LOI.KnownZero = KnownZero; 597 } 598 } while (!Worklist.empty()); 599} 600 601void SelectionDAGISel::CodeGenAndEmitDAG() { 602 std::string GroupName; 603 if (TimePassesIsEnabled) 604 GroupName = "Instruction Selection and Scheduling"; 605 std::string BlockName; 606 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 607 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 608 ViewSUnitDAGs) 609 BlockName = MF->getFunction()->getNameStr() + ":" + 610 BB->getBasicBlock()->getNameStr(); 611 612 DEBUG(dbgs() << "Initial selection DAG:\n"); 613 DEBUG(CurDAG->dump()); 614 615 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 616 617 // Run the DAG combiner in pre-legalize mode. 618 if (TimePassesIsEnabled) { 619 NamedRegionTimer T("DAG Combining 1", GroupName); 620 CurDAG->Combine(Unrestricted, *AA, OptLevel); 621 } else { 622 CurDAG->Combine(Unrestricted, *AA, OptLevel); 623 } 624 625 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 626 DEBUG(CurDAG->dump()); 627 628 // Second step, hack on the DAG until it only uses operations and types that 629 // the target supports. 630 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 631 BlockName); 632 633 bool Changed; 634 if (TimePassesIsEnabled) { 635 NamedRegionTimer T("Type Legalization", GroupName); 636 Changed = CurDAG->LegalizeTypes(); 637 } else { 638 Changed = CurDAG->LegalizeTypes(); 639 } 640 641 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 642 DEBUG(CurDAG->dump()); 643 644 if (Changed) { 645 if (ViewDAGCombineLT) 646 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 647 648 // Run the DAG combiner in post-type-legalize mode. 649 if (TimePassesIsEnabled) { 650 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 651 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 652 } else { 653 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 654 } 655 656 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 657 DEBUG(CurDAG->dump()); 658 } 659 660 if (TimePassesIsEnabled) { 661 NamedRegionTimer T("Vector Legalization", GroupName); 662 Changed = CurDAG->LegalizeVectors(); 663 } else { 664 Changed = CurDAG->LegalizeVectors(); 665 } 666 667 if (Changed) { 668 if (TimePassesIsEnabled) { 669 NamedRegionTimer T("Type Legalization 2", GroupName); 670 CurDAG->LegalizeTypes(); 671 } else { 672 CurDAG->LegalizeTypes(); 673 } 674 675 if (ViewDAGCombineLT) 676 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 677 678 // Run the DAG combiner in post-type-legalize mode. 679 if (TimePassesIsEnabled) { 680 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 681 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 682 } else { 683 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 684 } 685 686 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 687 DEBUG(CurDAG->dump()); 688 } 689 690 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 691 692 if (TimePassesIsEnabled) { 693 NamedRegionTimer T("DAG Legalization", GroupName); 694 CurDAG->Legalize(OptLevel); 695 } else { 696 CurDAG->Legalize(OptLevel); 697 } 698 699 DEBUG(dbgs() << "Legalized selection DAG:\n"); 700 DEBUG(CurDAG->dump()); 701 702 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 703 704 // Run the DAG combiner in post-legalize mode. 705 if (TimePassesIsEnabled) { 706 NamedRegionTimer T("DAG Combining 2", GroupName); 707 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 708 } else { 709 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 710 } 711 712 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 713 DEBUG(CurDAG->dump()); 714 715 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 716 717 if (OptLevel != CodeGenOpt::None) { 718 ShrinkDemandedOps(); 719 ComputeLiveOutVRegInfo(); 720 } 721 722 // Third, instruction select all of the operations to machine code, adding the 723 // code to the MachineBasicBlock. 724 if (TimePassesIsEnabled) { 725 NamedRegionTimer T("Instruction Selection", GroupName); 726 DoInstructionSelection(); 727 } else { 728 DoInstructionSelection(); 729 } 730 731 DEBUG(dbgs() << "Selected selection DAG:\n"); 732 DEBUG(CurDAG->dump()); 733 734 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 735 736 // Schedule machine code. 737 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 738 if (TimePassesIsEnabled) { 739 NamedRegionTimer T("Instruction Scheduling", GroupName); 740 Scheduler->Run(CurDAG, BB, BB->end()); 741 } else { 742 Scheduler->Run(CurDAG, BB, BB->end()); 743 } 744 745 if (ViewSUnitDAGs) Scheduler->viewGraph(); 746 747 // Emit machine code to BB. This can change 'BB' to the last block being 748 // inserted into. 749 if (TimePassesIsEnabled) { 750 NamedRegionTimer T("Instruction Creation", GroupName); 751 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 752 } else { 753 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 754 } 755 756 // Free the scheduler state. 757 if (TimePassesIsEnabled) { 758 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 759 delete Scheduler; 760 } else { 761 delete Scheduler; 762 } 763 764 DEBUG(dbgs() << "Selected machine code:\n"); 765 DEBUG(BB->dump()); 766} 767 768void SelectionDAGISel::DoInstructionSelection() { 769 DEBUG(errs() << "===== Instruction selection begins:\n"); 770 771 PreprocessISelDAG(); 772 773 // Select target instructions for the DAG. 774 { 775 // Number all nodes with a topological order and set DAGSize. 776 DAGSize = CurDAG->AssignTopologicalOrder(); 777 778 // Create a dummy node (which is not added to allnodes), that adds 779 // a reference to the root node, preventing it from being deleted, 780 // and tracking any changes of the root. 781 HandleSDNode Dummy(CurDAG->getRoot()); 782 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 783 ++ISelPosition; 784 785 // The AllNodes list is now topological-sorted. Visit the 786 // nodes by starting at the end of the list (the root of the 787 // graph) and preceding back toward the beginning (the entry 788 // node). 789 while (ISelPosition != CurDAG->allnodes_begin()) { 790 SDNode *Node = --ISelPosition; 791 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 792 // but there are currently some corner cases that it misses. Also, this 793 // makes it theoretically possible to disable the DAGCombiner. 794 if (Node->use_empty()) 795 continue; 796 797 SDNode *ResNode = Select(Node); 798 799 // If node should not be replaced, continue with the next one. 800 if (ResNode == Node) 801 continue; 802 // Replace node. 803 if (ResNode) 804 ReplaceUses(Node, ResNode); 805 806 // If after the replacement this node is not used any more, 807 // remove this dead node. 808 if (Node->use_empty()) { // Don't delete EntryToken, etc. 809 ISelUpdater ISU(ISelPosition); 810 CurDAG->RemoveDeadNode(Node, &ISU); 811 } 812 } 813 814 CurDAG->setRoot(Dummy.getValue()); 815 } 816 DEBUG(errs() << "===== Instruction selection ends:\n"); 817 818 PostprocessISelDAG(); 819 820 // FIXME: This shouldn't be needed, remove it. 821 CurDAG->RemoveDeadNodes(); 822} 823 824 825void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 826 MachineFunction &MF, 827 MachineModuleInfo *MMI, 828 DwarfWriter *DW, 829 const TargetInstrInfo &TII) { 830 // Initialize the Fast-ISel state, if needed. 831 FastISel *FastIS = 0; 832 if (EnableFastISel) 833 FastIS = TLI.createFastISel(MF, MMI, DW, 834 FuncInfo->ValueMap, 835 FuncInfo->MBBMap, 836 FuncInfo->StaticAllocaMap 837#ifndef NDEBUG 838 , FuncInfo->CatchInfoLost 839#endif 840 ); 841 842 unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg"); 843 844 // Iterate over all basic blocks in the function. 845 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 846 BasicBlock *LLVMBB = &*I; 847 BB = FuncInfo->MBBMap[LLVMBB]; 848 849 BasicBlock::iterator const Begin = LLVMBB->begin(); 850 BasicBlock::iterator const End = LLVMBB->end(); 851 BasicBlock::iterator BI = Begin; 852 853 // Lower any arguments needed in this block if this is the entry block. 854 bool SuppressFastISel = false; 855 if (LLVMBB == &Fn.getEntryBlock()) { 856 LowerArguments(LLVMBB); 857 858 // If any of the arguments has the byval attribute, forgo 859 // fast-isel in the entry block. 860 if (FastIS) { 861 unsigned j = 1; 862 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 863 I != E; ++I, ++j) 864 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 865 if (EnableFastISelVerbose || EnableFastISelAbort) 866 dbgs() << "FastISel skips entry block due to byval argument\n"; 867 SuppressFastISel = true; 868 break; 869 } 870 } 871 } 872 873 if (MMI && BB->isLandingPad()) { 874 // Add a label to mark the beginning of the landing pad. Deletion of the 875 // landing pad can thus be detected via the MachineModuleInfo. 876 unsigned LabelID = MMI->addLandingPad(BB); 877 878 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL); 879 BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID); 880 881 // Mark exception register as live in. 882 unsigned Reg = TLI.getExceptionAddressRegister(); 883 if (Reg) BB->addLiveIn(Reg); 884 885 // Mark exception selector register as live in. 886 Reg = TLI.getExceptionSelectorRegister(); 887 if (Reg) BB->addLiveIn(Reg); 888 889 // FIXME: Hack around an exception handling flaw (PR1508): the personality 890 // function and list of typeids logically belong to the invoke (or, if you 891 // like, the basic block containing the invoke), and need to be associated 892 // with it in the dwarf exception handling tables. Currently however the 893 // information is provided by an intrinsic (eh.selector) that can be moved 894 // to unexpected places by the optimizers: if the unwind edge is critical, 895 // then breaking it can result in the intrinsics being in the successor of 896 // the landing pad, not the landing pad itself. This results 897 // in exceptions not being caught because no typeids are associated with 898 // the invoke. This may not be the only way things can go wrong, but it 899 // is the only way we try to work around for the moment. 900 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 901 902 if (Br && Br->isUnconditional()) { // Critical edge? 903 BasicBlock::iterator I, E; 904 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 905 if (isa<EHSelectorInst>(I)) 906 break; 907 908 if (I == E) 909 // No catch info found - try to extract some from the successor. 910 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 911 } 912 } 913 914 // Before doing SelectionDAG ISel, see if FastISel has been requested. 915 if (FastIS && !SuppressFastISel) { 916 // Emit code for any incoming arguments. This must happen before 917 // beginning FastISel on the entry block. 918 if (LLVMBB == &Fn.getEntryBlock()) { 919 CurDAG->setRoot(SDB->getControlRoot()); 920 CodeGenAndEmitDAG(); 921 SDB->clear(); 922 } 923 FastIS->startNewBlock(BB); 924 // Do FastISel on as many instructions as possible. 925 for (; BI != End; ++BI) { 926 // Just before the terminator instruction, insert instructions to 927 // feed PHI nodes in successor blocks. 928 if (isa<TerminatorInst>(BI)) 929 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 930 ResetDebugLoc(SDB, FastIS); 931 if (EnableFastISelVerbose || EnableFastISelAbort) { 932 dbgs() << "FastISel miss: "; 933 BI->dump(); 934 } 935 assert(!EnableFastISelAbort && 936 "FastISel didn't handle a PHI in a successor"); 937 break; 938 } 939 940 SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF); 941 942 // Try to select the instruction with FastISel. 943 if (FastIS->SelectInstruction(BI)) { 944 ResetDebugLoc(SDB, FastIS); 945 continue; 946 } 947 948 // Clear out the debug location so that it doesn't carry over to 949 // unrelated instructions. 950 ResetDebugLoc(SDB, FastIS); 951 952 // Then handle certain instructions as single-LLVM-Instruction blocks. 953 if (isa<CallInst>(BI)) { 954 if (EnableFastISelVerbose || EnableFastISelAbort) { 955 dbgs() << "FastISel missed call: "; 956 BI->dump(); 957 } 958 959 if (!BI->getType()->isVoidTy()) { 960 unsigned &R = FuncInfo->ValueMap[BI]; 961 if (!R) 962 R = FuncInfo->CreateRegForValue(BI); 963 } 964 965 bool HadTailCall = false; 966 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 967 968 // If the call was emitted as a tail call, we're done with the block. 969 if (HadTailCall) { 970 BI = End; 971 break; 972 } 973 974 // If the instruction was codegen'd with multiple blocks, 975 // inform the FastISel object where to resume inserting. 976 FastIS->setCurrentBlock(BB); 977 continue; 978 } 979 980 // Otherwise, give up on FastISel for the rest of the block. 981 // For now, be a little lenient about non-branch terminators. 982 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 983 if (EnableFastISelVerbose || EnableFastISelAbort) { 984 dbgs() << "FastISel miss: "; 985 BI->dump(); 986 } 987 if (EnableFastISelAbort) 988 // The "fast" selector couldn't handle something and bailed. 989 // For the purpose of debugging, just abort. 990 llvm_unreachable("FastISel didn't select the entire block"); 991 } 992 break; 993 } 994 } 995 996 // Run SelectionDAG instruction selection on the remainder of the block 997 // not handled by FastISel. If FastISel is not run, this is the entire 998 // block. 999 if (BI != End) { 1000 bool HadTailCall; 1001 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 1002 } 1003 1004 FinishBasicBlock(); 1005 } 1006 1007 delete FastIS; 1008} 1009 1010void 1011SelectionDAGISel::FinishBasicBlock() { 1012 1013 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 1014 DEBUG(BB->dump()); 1015 1016 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1017 << SDB->PHINodesToUpdate.size() << "\n"); 1018 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 1019 dbgs() << "Node " << i << " : (" 1020 << SDB->PHINodesToUpdate[i].first 1021 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 1022 1023 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1024 // PHI nodes in successors. 1025 if (SDB->SwitchCases.empty() && 1026 SDB->JTCases.empty() && 1027 SDB->BitTestCases.empty()) { 1028 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1029 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1030 assert(PHI->isPHI() && 1031 "This is not a machine PHI node that we are updating!"); 1032 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1033 false)); 1034 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1035 } 1036 SDB->PHINodesToUpdate.clear(); 1037 return; 1038 } 1039 1040 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1041 // Lower header first, if it wasn't already lowered 1042 if (!SDB->BitTestCases[i].Emitted) { 1043 // Set the current basic block to the mbb we wish to insert the code into 1044 BB = SDB->BitTestCases[i].Parent; 1045 SDB->setCurrentBasicBlock(BB); 1046 // Emit the code 1047 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 1048 CurDAG->setRoot(SDB->getRoot()); 1049 CodeGenAndEmitDAG(); 1050 SDB->clear(); 1051 } 1052 1053 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1054 // Set the current basic block to the mbb we wish to insert the code into 1055 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 1056 SDB->setCurrentBasicBlock(BB); 1057 // Emit the code 1058 if (j+1 != ej) 1059 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 1060 SDB->BitTestCases[i].Reg, 1061 SDB->BitTestCases[i].Cases[j]); 1062 else 1063 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 1064 SDB->BitTestCases[i].Reg, 1065 SDB->BitTestCases[i].Cases[j]); 1066 1067 1068 CurDAG->setRoot(SDB->getRoot()); 1069 CodeGenAndEmitDAG(); 1070 SDB->clear(); 1071 } 1072 1073 // Update PHI Nodes 1074 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1075 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1076 MachineBasicBlock *PHIBB = PHI->getParent(); 1077 assert(PHI->isPHI() && 1078 "This is not a machine PHI node that we are updating!"); 1079 // This is "default" BB. We have two jumps to it. From "header" BB and 1080 // from last "case" BB. 1081 if (PHIBB == SDB->BitTestCases[i].Default) { 1082 PHI->addOperand(MachineOperand:: 1083 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1084 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1085 PHI->addOperand(MachineOperand:: 1086 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1087 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1088 back().ThisBB)); 1089 } 1090 // One of "cases" BB. 1091 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1092 j != ej; ++j) { 1093 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1094 if (cBB->isSuccessor(PHIBB)) { 1095 PHI->addOperand(MachineOperand:: 1096 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1097 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1098 } 1099 } 1100 } 1101 } 1102 SDB->BitTestCases.clear(); 1103 1104 // If the JumpTable record is filled in, then we need to emit a jump table. 1105 // Updating the PHI nodes is tricky in this case, since we need to determine 1106 // whether the PHI is a successor of the range check MBB or the jump table MBB 1107 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1108 // Lower header first, if it wasn't already lowered 1109 if (!SDB->JTCases[i].first.Emitted) { 1110 // Set the current basic block to the mbb we wish to insert the code into 1111 BB = SDB->JTCases[i].first.HeaderBB; 1112 SDB->setCurrentBasicBlock(BB); 1113 // Emit the code 1114 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 1115 CurDAG->setRoot(SDB->getRoot()); 1116 CodeGenAndEmitDAG(); 1117 SDB->clear(); 1118 } 1119 1120 // Set the current basic block to the mbb we wish to insert the code into 1121 BB = SDB->JTCases[i].second.MBB; 1122 SDB->setCurrentBasicBlock(BB); 1123 // Emit the code 1124 SDB->visitJumpTable(SDB->JTCases[i].second); 1125 CurDAG->setRoot(SDB->getRoot()); 1126 CodeGenAndEmitDAG(); 1127 SDB->clear(); 1128 1129 // Update PHI Nodes 1130 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1131 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1132 MachineBasicBlock *PHIBB = PHI->getParent(); 1133 assert(PHI->isPHI() && 1134 "This is not a machine PHI node that we are updating!"); 1135 // "default" BB. We can go there only from header BB. 1136 if (PHIBB == SDB->JTCases[i].second.Default) { 1137 PHI->addOperand 1138 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1139 PHI->addOperand 1140 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1141 } 1142 // JT BB. Just iterate over successors here 1143 if (BB->isSuccessor(PHIBB)) { 1144 PHI->addOperand 1145 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1146 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1147 } 1148 } 1149 } 1150 SDB->JTCases.clear(); 1151 1152 // If the switch block involved a branch to one of the actual successors, we 1153 // need to update PHI nodes in that block. 1154 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1155 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1156 assert(PHI->isPHI() && 1157 "This is not a machine PHI node that we are updating!"); 1158 if (BB->isSuccessor(PHI->getParent())) { 1159 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1160 false)); 1161 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1162 } 1163 } 1164 1165 // If we generated any switch lowering information, build and codegen any 1166 // additional DAGs necessary. 1167 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1168 // Set the current basic block to the mbb we wish to insert the code into 1169 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1170 SDB->setCurrentBasicBlock(BB); 1171 1172 // Emit the code 1173 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1174 CurDAG->setRoot(SDB->getRoot()); 1175 CodeGenAndEmitDAG(); 1176 1177 // Handle any PHI nodes in successors of this chunk, as if we were coming 1178 // from the original BB before switch expansion. Note that PHI nodes can 1179 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1180 // handle them the right number of times. 1181 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1182 // If new BB's are created during scheduling, the edges may have been 1183 // updated. That is, the edge from ThisBB to BB may have been split and 1184 // BB's predecessor is now another block. 1185 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1186 SDB->EdgeMapping.find(BB); 1187 if (EI != SDB->EdgeMapping.end()) 1188 ThisBB = EI->second; 1189 1190 // BB may have been removed from the CFG if a branch was constant folded. 1191 if (ThisBB->isSuccessor(BB)) { 1192 for (MachineBasicBlock::iterator Phi = BB->begin(); 1193 Phi != BB->end() && Phi->isPHI(); 1194 ++Phi) { 1195 // This value for this PHI node is recorded in PHINodesToUpdate. 1196 for (unsigned pn = 0; ; ++pn) { 1197 assert(pn != SDB->PHINodesToUpdate.size() && 1198 "Didn't find PHI entry!"); 1199 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1200 Phi->addOperand(MachineOperand:: 1201 CreateReg(SDB->PHINodesToUpdate[pn].second, 1202 false)); 1203 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1204 break; 1205 } 1206 } 1207 } 1208 } 1209 1210 // Don't process RHS if same block as LHS. 1211 if (BB == SDB->SwitchCases[i].FalseBB) 1212 SDB->SwitchCases[i].FalseBB = 0; 1213 1214 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1215 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1216 SDB->SwitchCases[i].FalseBB = 0; 1217 } 1218 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1219 SDB->clear(); 1220 } 1221 SDB->SwitchCases.clear(); 1222 1223 SDB->PHINodesToUpdate.clear(); 1224} 1225 1226 1227/// Create the scheduler. If a specific scheduler was specified 1228/// via the SchedulerRegistry, use it, otherwise select the 1229/// one preferred by the target. 1230/// 1231ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1232 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1233 1234 if (!Ctor) { 1235 Ctor = ISHeuristic; 1236 RegisterScheduler::setDefault(Ctor); 1237 } 1238 1239 return Ctor(this, OptLevel); 1240} 1241 1242ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1243 return new ScheduleHazardRecognizer(); 1244} 1245 1246//===----------------------------------------------------------------------===// 1247// Helper functions used by the generated instruction selector. 1248//===----------------------------------------------------------------------===// 1249// Calls to these methods are generated by tblgen. 1250 1251/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1252/// the dag combiner simplified the 255, we still want to match. RHS is the 1253/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1254/// specified in the .td file (e.g. 255). 1255bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1256 int64_t DesiredMaskS) const { 1257 const APInt &ActualMask = RHS->getAPIntValue(); 1258 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1259 1260 // If the actual mask exactly matches, success! 1261 if (ActualMask == DesiredMask) 1262 return true; 1263 1264 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1265 if (ActualMask.intersects(~DesiredMask)) 1266 return false; 1267 1268 // Otherwise, the DAG Combiner may have proven that the value coming in is 1269 // either already zero or is not demanded. Check for known zero input bits. 1270 APInt NeededMask = DesiredMask & ~ActualMask; 1271 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1272 return true; 1273 1274 // TODO: check to see if missing bits are just not demanded. 1275 1276 // Otherwise, this pattern doesn't match. 1277 return false; 1278} 1279 1280/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1281/// the dag combiner simplified the 255, we still want to match. RHS is the 1282/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1283/// specified in the .td file (e.g. 255). 1284bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1285 int64_t DesiredMaskS) const { 1286 const APInt &ActualMask = RHS->getAPIntValue(); 1287 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1288 1289 // If the actual mask exactly matches, success! 1290 if (ActualMask == DesiredMask) 1291 return true; 1292 1293 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1294 if (ActualMask.intersects(~DesiredMask)) 1295 return false; 1296 1297 // Otherwise, the DAG Combiner may have proven that the value coming in is 1298 // either already zero or is not demanded. Check for known zero input bits. 1299 APInt NeededMask = DesiredMask & ~ActualMask; 1300 1301 APInt KnownZero, KnownOne; 1302 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1303 1304 // If all the missing bits in the or are already known to be set, match! 1305 if ((NeededMask & KnownOne) == NeededMask) 1306 return true; 1307 1308 // TODO: check to see if missing bits are just not demanded. 1309 1310 // Otherwise, this pattern doesn't match. 1311 return false; 1312} 1313 1314 1315/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1316/// by tblgen. Others should not call it. 1317void SelectionDAGISel:: 1318SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1319 std::vector<SDValue> InOps; 1320 std::swap(InOps, Ops); 1321 1322 Ops.push_back(InOps[0]); // input chain. 1323 Ops.push_back(InOps[1]); // input asm string. 1324 1325 unsigned i = 2, e = InOps.size(); 1326 if (InOps[e-1].getValueType() == MVT::Flag) 1327 --e; // Don't process a flag operand if it is here. 1328 1329 while (i != e) { 1330 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1331 if ((Flags & 7) != 4 /*MEM*/) { 1332 // Just skip over this operand, copying the operands verbatim. 1333 Ops.insert(Ops.end(), InOps.begin()+i, 1334 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1335 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1336 } else { 1337 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1338 "Memory operand with multiple values?"); 1339 // Otherwise, this is a memory operand. Ask the target to select it. 1340 std::vector<SDValue> SelOps; 1341 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1342 llvm_report_error("Could not match memory address. Inline asm" 1343 " failure!"); 1344 } 1345 1346 // Add this to the output node. 1347 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1348 MVT::i32)); 1349 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1350 i += 2; 1351 } 1352 } 1353 1354 // Add the flag input back if present. 1355 if (e != InOps.size()) 1356 Ops.push_back(InOps.back()); 1357} 1358 1359/// findFlagUse - Return use of EVT::Flag value produced by the specified 1360/// SDNode. 1361/// 1362static SDNode *findFlagUse(SDNode *N) { 1363 unsigned FlagResNo = N->getNumValues()-1; 1364 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1365 SDUse &Use = I.getUse(); 1366 if (Use.getResNo() == FlagResNo) 1367 return Use.getUser(); 1368 } 1369 return NULL; 1370} 1371 1372/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1373/// This function recursively traverses up the operand chain, ignoring 1374/// certain nodes. 1375static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1376 SDNode *Root, 1377 SmallPtrSet<SDNode*, 16> &Visited) { 1378 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1379 // greater than all of its (recursive) operands. If we scan to a point where 1380 // 'use' is smaller than the node we're scanning for, then we know we will 1381 // never find it. 1382 // 1383 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1384 // happen because we scan down to newly selected nodes in the case of flag 1385 // uses. 1386 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1387 return false; 1388 1389 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1390 // won't fail if we scan it again. 1391 if (!Visited.insert(Use)) 1392 return false; 1393 1394 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1395 SDNode *N = Use->getOperand(i).getNode(); 1396 if (N == Def) { 1397 if (Use == ImmedUse || Use == Root) 1398 continue; // We are not looking for immediate use. 1399 assert(N != Root); 1400 return true; 1401 } 1402 1403 // Traverse up the operand chain. 1404 if (findNonImmUse(N, Def, ImmedUse, Root, Visited)) 1405 return true; 1406 } 1407 return false; 1408} 1409 1410/// isNonImmUse - Start searching from Root up the DAG to check is Def can 1411/// be reached. Return true if that's the case. However, ignore direct uses 1412/// by ImmedUse (which would be U in the example illustrated in 1413/// IsLegalToFold) and by Root (which can happen in the store case). 1414/// FIXME: to be really generic, we should allow direct use by any node 1415/// that is being folded. But realisticly since we only fold loads which 1416/// have one non-chain use, we only need to watch out for load/op/store 1417/// and load/op/cmp case where the root (store / cmp) may reach the load via 1418/// its chain operand. 1419static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) { 1420 SmallPtrSet<SDNode*, 16> Visited; 1421 return findNonImmUse(Root, Def, ImmedUse, Root, Visited); 1422} 1423 1424/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1425/// operand node N of U during instruction selection that starts at Root. 1426bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1427 SDNode *Root) const { 1428 if (OptLevel == CodeGenOpt::None) return false; 1429 return N.hasOneUse(); 1430} 1431 1432/// IsLegalToFold - Returns true if the specific operand node N of 1433/// U can be folded during instruction selection that starts at Root. 1434bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const { 1435 if (OptLevel == CodeGenOpt::None) return false; 1436 1437 // If Root use can somehow reach N through a path that that doesn't contain 1438 // U then folding N would create a cycle. e.g. In the following 1439 // diagram, Root can reach N through X. If N is folded into into Root, then 1440 // X is both a predecessor and a successor of U. 1441 // 1442 // [N*] // 1443 // ^ ^ // 1444 // / \ // 1445 // [U*] [X]? // 1446 // ^ ^ // 1447 // \ / // 1448 // \ / // 1449 // [Root*] // 1450 // 1451 // * indicates nodes to be folded together. 1452 // 1453 // If Root produces a flag, then it gets (even more) interesting. Since it 1454 // will be "glued" together with its flag use in the scheduler, we need to 1455 // check if it might reach N. 1456 // 1457 // [N*] // 1458 // ^ ^ // 1459 // / \ // 1460 // [U*] [X]? // 1461 // ^ ^ // 1462 // \ \ // 1463 // \ | // 1464 // [Root*] | // 1465 // ^ | // 1466 // f | // 1467 // | / // 1468 // [Y] / // 1469 // ^ / // 1470 // f / // 1471 // | / // 1472 // [FU] // 1473 // 1474 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1475 // (call it Fold), then X is a predecessor of FU and a successor of 1476 // Fold. But since Fold and FU are flagged together, this will create 1477 // a cycle in the scheduling graph. 1478 1479 EVT VT = Root->getValueType(Root->getNumValues()-1); 1480 while (VT == MVT::Flag) { 1481 SDNode *FU = findFlagUse(Root); 1482 if (FU == NULL) 1483 break; 1484 Root = FU; 1485 VT = Root->getValueType(Root->getNumValues()-1); 1486 } 1487 1488 return !isNonImmUse(Root, N.getNode(), U); 1489} 1490 1491SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1492 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1493 SelectInlineAsmMemoryOperands(Ops); 1494 1495 std::vector<EVT> VTs; 1496 VTs.push_back(MVT::Other); 1497 VTs.push_back(MVT::Flag); 1498 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1499 VTs, &Ops[0], Ops.size()); 1500 return New.getNode(); 1501} 1502 1503SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1504 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1505} 1506 1507SDNode *SelectionDAGISel::Select_EH_LABEL(SDNode *N) { 1508 SDValue Chain = N->getOperand(0); 1509 unsigned C = cast<LabelSDNode>(N)->getLabelID(); 1510 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32); 1511 return CurDAG->SelectNodeTo(N, TargetOpcode::EH_LABEL, 1512 MVT::Other, Tmp, Chain); 1513} 1514 1515/// GetVBR - decode a vbr encoding whose top bit is set. 1516ALWAYS_INLINE static uint64_t 1517GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1518 assert(Val >= 128 && "Not a VBR"); 1519 Val &= 127; // Remove first vbr bit. 1520 1521 unsigned Shift = 7; 1522 uint64_t NextBits; 1523 do { 1524 NextBits = MatcherTable[Idx++]; 1525 Val |= (NextBits&127) << Shift; 1526 Shift += 7; 1527 } while (NextBits & 128); 1528 1529 return Val; 1530} 1531 1532 1533/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1534/// interior flag and chain results to use the new flag and chain results. 1535static void UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1536 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1537 SDValue InputFlag, 1538 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1539 bool isMorphNodeTo, SelectionDAG *CurDAG) { 1540 // Now that all the normal results are replaced, we replace the chain and 1541 // flag results if present. 1542 if (!ChainNodesMatched.empty()) { 1543 assert(InputChain.getNode() != 0 && 1544 "Matched input chains but didn't produce a chain"); 1545 // Loop over all of the nodes we matched that produced a chain result. 1546 // Replace all the chain results with the final chain we ended up with. 1547 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1548 SDNode *ChainNode = ChainNodesMatched[i]; 1549 1550 // Don't replace the results of the root node if we're doing a 1551 // MorphNodeTo. 1552 if (ChainNode == NodeToMatch && isMorphNodeTo) 1553 continue; 1554 1555 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1556 if (ChainVal.getValueType() == MVT::Flag) 1557 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1558 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1559 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1560 } 1561 } 1562 1563 // If the result produces a flag, update any flag results in the matched 1564 // pattern with the flag result. 1565 if (InputFlag.getNode() != 0) { 1566 // Handle any interior nodes explicitly marked. 1567 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1568 SDNode *FRN = FlagResultNodesMatched[i]; 1569 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1570 "Doesn't have a flag result"); 1571 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1572 InputFlag); 1573 } 1574 } 1575 1576 DEBUG(errs() << "ISEL: Match complete!\n"); 1577} 1578 1579enum ChainResult { 1580 CR_Simple, 1581 CR_InducesCycle, 1582 CR_LeadsToInteriorNode 1583}; 1584 1585/// WalkChainUsers - Walk down the users of the specified chained node that is 1586/// part of the pattern we're matching, looking at all of the users we find. 1587/// This determines whether something is an interior node, whether we have a 1588/// non-pattern node in between two pattern nodes (which prevent folding because 1589/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1590/// between pattern nodes (in which case the TF becomes part of the pattern). 1591/// 1592/// The walk we do here is guaranteed to be small because we quickly get down to 1593/// already selected nodes "below" us. 1594static ChainResult 1595WalkChainUsers(SDNode *ChainedNode, 1596 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1597 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1598 ChainResult Result = CR_Simple; 1599 1600 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1601 E = ChainedNode->use_end(); UI != E; ++UI) { 1602 // Make sure the use is of the chain, not some other value we produce. 1603 if (UI.getUse().getValueType() != MVT::Other) continue; 1604 1605 SDNode *User = *UI; 1606 1607 // If we see an already-selected machine node, then we've gone beyond the 1608 // pattern that we're selecting down into the already selected chunk of the 1609 // DAG. 1610 if (User->isMachineOpcode() || 1611 User->getOpcode() == ISD::CopyToReg || 1612 User->getOpcode() == ISD::CopyFromReg || 1613 User->getOpcode() == ISD::INLINEASM || 1614 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1615 continue; 1616 1617 // If we have a TokenFactor, we handle it specially. 1618 if (User->getOpcode() != ISD::TokenFactor) { 1619 // If the node isn't a token factor and isn't part of our pattern, then it 1620 // must be a random chained node in between two nodes we're selecting. 1621 // This happens when we have something like: 1622 // x = load ptr 1623 // call 1624 // y = x+4 1625 // store y -> ptr 1626 // Because we structurally match the load/store as a read/modify/write, 1627 // but the call is chained between them. We cannot fold in this case 1628 // because it would induce a cycle in the graph. 1629 if (!std::count(ChainedNodesInPattern.begin(), 1630 ChainedNodesInPattern.end(), User)) 1631 return CR_InducesCycle; 1632 1633 // Otherwise we found a node that is part of our pattern. For example in: 1634 // x = load ptr 1635 // y = x+4 1636 // store y -> ptr 1637 // This would happen when we're scanning down from the load and see the 1638 // store as a user. Record that there is a use of ChainedNode that is 1639 // part of the pattern and keep scanning uses. 1640 Result = CR_LeadsToInteriorNode; 1641 InteriorChainedNodes.push_back(User); 1642 continue; 1643 } 1644 1645 // If we found a TokenFactor, there are two cases to consider: first if the 1646 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1647 // uses of the TF are in our pattern) we just want to ignore it. Second, 1648 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1649 // [Load chain] 1650 // ^ 1651 // | 1652 // [Load] 1653 // ^ ^ 1654 // | \ DAG's like cheese 1655 // / \ do you? 1656 // / | 1657 // [TokenFactor] [Op] 1658 // ^ ^ 1659 // | | 1660 // \ / 1661 // \ / 1662 // [Store] 1663 // 1664 // In this case, the TokenFactor becomes part of our match and we rewrite it 1665 // as a new TokenFactor. 1666 // 1667 // To distinguish these two cases, do a recursive walk down the uses. 1668 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1669 case CR_Simple: 1670 // If the uses of the TokenFactor are just already-selected nodes, ignore 1671 // it, it is "below" our pattern. 1672 continue; 1673 case CR_InducesCycle: 1674 // If the uses of the TokenFactor lead to nodes that are not part of our 1675 // pattern that are not selected, folding would turn this into a cycle, 1676 // bail out now. 1677 return CR_InducesCycle; 1678 case CR_LeadsToInteriorNode: 1679 break; // Otherwise, keep processing. 1680 } 1681 1682 // Okay, we know we're in the interesting interior case. The TokenFactor 1683 // is now going to be considered part of the pattern so that we rewrite its 1684 // uses (it may have uses that are not part of the pattern) with the 1685 // ultimate chain result of the generated code. We will also add its chain 1686 // inputs as inputs to the ultimate TokenFactor we create. 1687 Result = CR_LeadsToInteriorNode; 1688 ChainedNodesInPattern.push_back(User); 1689 InteriorChainedNodes.push_back(User); 1690 continue; 1691 } 1692 1693 return Result; 1694} 1695 1696/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1697/// operation for when the pattern matched multiple nodes with chains. The 1698/// input vector contains a list of all of the chained nodes that we match. We 1699/// must determine if this is a valid thing to cover (i.e. matching it won't 1700/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1701/// be used as the input node chain for the generated nodes. 1702static SDValue 1703HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1704 SelectionDAG *CurDAG) { 1705 assert(ChainNodesMatched.size() > 1 && 1706 "Should only happen for multi chain node case"); 1707 1708 // Walk all of the chained nodes we've matched, recursively scanning down the 1709 // users of the chain result. This adds any TokenFactor nodes that are caught 1710 // in between chained nodes to the chained and interior nodes list. 1711 SmallVector<SDNode*, 3> InteriorChainedNodes; 1712 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1713 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1714 InteriorChainedNodes) == CR_InducesCycle) 1715 return SDValue(); // Would induce a cycle. 1716 } 1717 1718 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1719 // that we are interested in. Form our input TokenFactor node. 1720 SmallVector<SDValue, 3> InputChains; 1721 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1722 // Add the input chain of this node to the InputChains list (which will be 1723 // the operands of the generated TokenFactor) if it's not an interior node. 1724 SDNode *N = ChainNodesMatched[i]; 1725 if (N->getOpcode() != ISD::TokenFactor) { 1726 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1727 continue; 1728 1729 // Otherwise, add the input chain. 1730 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1731 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1732 InputChains.push_back(InChain); 1733 continue; 1734 } 1735 1736 // If we have a token factor, we want to add all inputs of the token factor 1737 // that are not part of the pattern we're matching. 1738 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1739 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1740 N->getOperand(op).getNode())) 1741 InputChains.push_back(N->getOperand(op)); 1742 } 1743 } 1744 1745 SDValue Res; 1746 if (InputChains.size() == 1) 1747 return InputChains[0]; 1748 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1749 MVT::Other, &InputChains[0], InputChains.size()); 1750} 1751 1752struct MatchScope { 1753 /// FailIndex - If this match fails, this is the index to continue with. 1754 unsigned FailIndex; 1755 1756 /// NodeStack - The node stack when the scope was formed. 1757 SmallVector<SDValue, 4> NodeStack; 1758 1759 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1760 unsigned NumRecordedNodes; 1761 1762 /// NumMatchedMemRefs - The number of matched memref entries. 1763 unsigned NumMatchedMemRefs; 1764 1765 /// InputChain/InputFlag - The current chain/flag 1766 SDValue InputChain, InputFlag; 1767 1768 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1769 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1770}; 1771 1772SDNode *SelectionDAGISel:: 1773SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1774 unsigned TableSize) { 1775 // FIXME: Should these even be selected? Handle these cases in the caller? 1776 switch (NodeToMatch->getOpcode()) { 1777 default: 1778 break; 1779 case ISD::EntryToken: // These nodes remain the same. 1780 case ISD::BasicBlock: 1781 case ISD::Register: 1782 case ISD::HANDLENODE: 1783 case ISD::TargetConstant: 1784 case ISD::TargetConstantFP: 1785 case ISD::TargetConstantPool: 1786 case ISD::TargetFrameIndex: 1787 case ISD::TargetExternalSymbol: 1788 case ISD::TargetBlockAddress: 1789 case ISD::TargetJumpTable: 1790 case ISD::TargetGlobalTLSAddress: 1791 case ISD::TargetGlobalAddress: 1792 case ISD::TokenFactor: 1793 case ISD::CopyFromReg: 1794 case ISD::CopyToReg: 1795 return 0; 1796 case ISD::AssertSext: 1797 case ISD::AssertZext: 1798 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1799 NodeToMatch->getOperand(0)); 1800 return 0; 1801 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1802 case ISD::EH_LABEL: return Select_EH_LABEL(NodeToMatch); 1803 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1804 } 1805 1806 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1807 1808 // Set up the node stack with NodeToMatch as the only node on the stack. 1809 SmallVector<SDValue, 8> NodeStack; 1810 SDValue N = SDValue(NodeToMatch, 0); 1811 NodeStack.push_back(N); 1812 1813 // MatchScopes - Scopes used when matching, if a match failure happens, this 1814 // indicates where to continue checking. 1815 SmallVector<MatchScope, 8> MatchScopes; 1816 1817 // RecordedNodes - This is the set of nodes that have been recorded by the 1818 // state machine. 1819 SmallVector<SDValue, 8> RecordedNodes; 1820 1821 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1822 // pattern. 1823 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1824 1825 // These are the current input chain and flag for use when generating nodes. 1826 // Various Emit operations change these. For example, emitting a copytoreg 1827 // uses and updates these. 1828 SDValue InputChain, InputFlag; 1829 1830 // ChainNodesMatched - If a pattern matches nodes that have input/output 1831 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1832 // which ones they are. The result is captured into this list so that we can 1833 // update the chain results when the pattern is complete. 1834 SmallVector<SDNode*, 3> ChainNodesMatched; 1835 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1836 1837 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1838 NodeToMatch->dump(CurDAG); 1839 errs() << '\n'); 1840 1841 // Determine where to start the interpreter. Normally we start at opcode #0, 1842 // but if the state machine starts with an OPC_SwitchOpcode, then we 1843 // accelerate the first lookup (which is guaranteed to be hot) with the 1844 // OpcodeOffset table. 1845 unsigned MatcherIndex = 0; 1846 1847 if (!OpcodeOffset.empty()) { 1848 // Already computed the OpcodeOffset table, just index into it. 1849 if (N.getOpcode() < OpcodeOffset.size()) 1850 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1851 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1852 1853 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1854 // Otherwise, the table isn't computed, but the state machine does start 1855 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1856 // is the first time we're selecting an instruction. 1857 unsigned Idx = 1; 1858 while (1) { 1859 // Get the size of this case. 1860 unsigned CaseSize = MatcherTable[Idx++]; 1861 if (CaseSize & 128) 1862 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1863 if (CaseSize == 0) break; 1864 1865 // Get the opcode, add the index to the table. 1866 unsigned Opc = MatcherTable[Idx++]; 1867 if (Opc >= OpcodeOffset.size()) 1868 OpcodeOffset.resize((Opc+1)*2); 1869 OpcodeOffset[Opc] = Idx; 1870 Idx += CaseSize; 1871 } 1872 1873 // Okay, do the lookup for the first opcode. 1874 if (N.getOpcode() < OpcodeOffset.size()) 1875 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1876 } 1877 1878 while (1) { 1879 assert(MatcherIndex < TableSize && "Invalid index"); 1880 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 1881 switch (Opcode) { 1882 case OPC_Scope: { 1883 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 1884 if (NumToSkip & 128) 1885 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 1886 assert(NumToSkip != 0 && 1887 "First entry of OPC_Scope shouldn't be 0, scope has no children?"); 1888 1889 // Push a MatchScope which indicates where to go if the first child fails 1890 // to match. 1891 MatchScope NewEntry; 1892 NewEntry.FailIndex = MatcherIndex+NumToSkip; 1893 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 1894 NewEntry.NumRecordedNodes = RecordedNodes.size(); 1895 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 1896 NewEntry.InputChain = InputChain; 1897 NewEntry.InputFlag = InputFlag; 1898 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 1899 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 1900 MatchScopes.push_back(NewEntry); 1901 continue; 1902 } 1903 case OPC_RecordNode: 1904 // Remember this node, it may end up being an operand in the pattern. 1905 RecordedNodes.push_back(N); 1906 continue; 1907 1908 case OPC_RecordChild0: case OPC_RecordChild1: 1909 case OPC_RecordChild2: case OPC_RecordChild3: 1910 case OPC_RecordChild4: case OPC_RecordChild5: 1911 case OPC_RecordChild6: case OPC_RecordChild7: { 1912 unsigned ChildNo = Opcode-OPC_RecordChild0; 1913 if (ChildNo >= N.getNumOperands()) 1914 break; // Match fails if out of range child #. 1915 1916 RecordedNodes.push_back(N->getOperand(ChildNo)); 1917 continue; 1918 } 1919 case OPC_RecordMemRef: 1920 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 1921 continue; 1922 1923 case OPC_CaptureFlagInput: 1924 // If the current node has an input flag, capture it in InputFlag. 1925 if (N->getNumOperands() != 0 && 1926 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 1927 InputFlag = N->getOperand(N->getNumOperands()-1); 1928 continue; 1929 1930 case OPC_MoveChild: { 1931 unsigned ChildNo = MatcherTable[MatcherIndex++]; 1932 if (ChildNo >= N.getNumOperands()) 1933 break; // Match fails if out of range child #. 1934 N = N.getOperand(ChildNo); 1935 NodeStack.push_back(N); 1936 continue; 1937 } 1938 1939 case OPC_MoveParent: 1940 // Pop the current node off the NodeStack. 1941 NodeStack.pop_back(); 1942 assert(!NodeStack.empty() && "Node stack imbalance!"); 1943 N = NodeStack.back(); 1944 continue; 1945 1946 case OPC_CheckSame: { 1947 // Accept if it is exactly the same as a previously recorded node. 1948 unsigned RecNo = MatcherTable[MatcherIndex++]; 1949 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1950 if (N != RecordedNodes[RecNo]) break; 1951 continue; 1952 } 1953 case OPC_CheckPatternPredicate: 1954 if (!CheckPatternPredicate(MatcherTable[MatcherIndex++])) break; 1955 continue; 1956 case OPC_CheckPredicate: 1957 if (!CheckNodePredicate(N.getNode(), MatcherTable[MatcherIndex++])) break; 1958 continue; 1959 case OPC_CheckComplexPat: 1960 if (!CheckComplexPattern(NodeToMatch, N, 1961 MatcherTable[MatcherIndex++], RecordedNodes)) 1962 break; 1963 continue; 1964 case OPC_CheckOpcode: 1965 if (N->getOpcode() != MatcherTable[MatcherIndex++]) break; 1966 continue; 1967 1968 case OPC_SwitchOpcode: { 1969 unsigned CurNodeOpcode = N.getOpcode(); 1970 1971 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 1972 1973 unsigned CaseSize; 1974 while (1) { 1975 // Get the size of this case. 1976 CaseSize = MatcherTable[MatcherIndex++]; 1977 if (CaseSize & 128) 1978 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 1979 if (CaseSize == 0) break; 1980 1981 // If the opcode matches, then we will execute this case. 1982 if (CurNodeOpcode == MatcherTable[MatcherIndex++]) 1983 break; 1984 1985 // Otherwise, skip over this case. 1986 MatcherIndex += CaseSize; 1987 } 1988 1989 // If we failed to match, bail out. 1990 if (CaseSize == 0) break; 1991 1992 // Otherwise, execute the case we found. 1993 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 1994 << " to " << MatcherIndex << "\n"); 1995 continue; 1996 } 1997 1998 case OPC_CheckType: { 1999 MVT::SimpleValueType VT = 2000 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2001 if (N.getValueType() != VT) { 2002 // Handle the case when VT is iPTR. 2003 if (VT != MVT::iPTR || N.getValueType() != TLI.getPointerTy()) 2004 break; 2005 } 2006 continue; 2007 } 2008 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2009 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2010 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2011 case OPC_CheckChild6Type: case OPC_CheckChild7Type: { 2012 unsigned ChildNo = Opcode-OPC_CheckChild0Type; 2013 if (ChildNo >= N.getNumOperands()) 2014 break; // Match fails if out of range child #. 2015 2016 MVT::SimpleValueType VT = 2017 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2018 EVT ChildVT = N.getOperand(ChildNo).getValueType(); 2019 if (ChildVT != VT) { 2020 // Handle the case when VT is iPTR. 2021 if (VT != MVT::iPTR || ChildVT != TLI.getPointerTy()) 2022 break; 2023 } 2024 continue; 2025 } 2026 case OPC_CheckCondCode: 2027 if (cast<CondCodeSDNode>(N)->get() != 2028 (ISD::CondCode)MatcherTable[MatcherIndex++]) break; 2029 continue; 2030 case OPC_CheckValueType: { 2031 MVT::SimpleValueType VT = 2032 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2033 if (cast<VTSDNode>(N)->getVT() != VT) { 2034 // Handle the case when VT is iPTR. 2035 if (VT != MVT::iPTR || cast<VTSDNode>(N)->getVT() != TLI.getPointerTy()) 2036 break; 2037 } 2038 continue; 2039 } 2040 case OPC_CheckInteger: { 2041 int64_t Val = MatcherTable[MatcherIndex++]; 2042 if (Val & 128) 2043 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2044 2045 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2046 if (C == 0 || C->getSExtValue() != Val) 2047 break; 2048 continue; 2049 } 2050 case OPC_CheckAndImm: { 2051 int64_t Val = MatcherTable[MatcherIndex++]; 2052 if (Val & 128) 2053 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2054 2055 if (N->getOpcode() != ISD::AND) break; 2056 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2057 if (C == 0 || !CheckAndMask(N.getOperand(0), C, Val)) 2058 break; 2059 continue; 2060 } 2061 case OPC_CheckOrImm: { 2062 int64_t Val = MatcherTable[MatcherIndex++]; 2063 if (Val & 128) 2064 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2065 2066 if (N->getOpcode() != ISD::OR) break; 2067 2068 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2069 if (C == 0 || !CheckOrMask(N.getOperand(0), C, Val)) 2070 break; 2071 continue; 2072 } 2073 2074 case OPC_CheckFoldableChainNode: { 2075 assert(NodeStack.size() != 1 && "No parent node"); 2076 // Verify that all intermediate nodes between the root and this one have 2077 // a single use. 2078 bool HasMultipleUses = false; 2079 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2080 if (!NodeStack[i].hasOneUse()) { 2081 HasMultipleUses = true; 2082 break; 2083 } 2084 if (HasMultipleUses) break; 2085 2086 // Check to see that the target thinks this is profitable to fold and that 2087 // we can fold it without inducing cycles in the graph. 2088 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2089 NodeToMatch) || 2090 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2091 NodeToMatch)) 2092 break; 2093 2094 continue; 2095 } 2096 case OPC_EmitInteger: { 2097 MVT::SimpleValueType VT = 2098 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2099 int64_t Val = MatcherTable[MatcherIndex++]; 2100 if (Val & 128) 2101 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2102 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2103 continue; 2104 } 2105 case OPC_EmitRegister: { 2106 MVT::SimpleValueType VT = 2107 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2108 unsigned RegNo = MatcherTable[MatcherIndex++]; 2109 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2110 continue; 2111 } 2112 2113 case OPC_EmitConvertToTarget: { 2114 // Convert from IMM/FPIMM to target version. 2115 unsigned RecNo = MatcherTable[MatcherIndex++]; 2116 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2117 SDValue Imm = RecordedNodes[RecNo]; 2118 2119 if (Imm->getOpcode() == ISD::Constant) { 2120 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2121 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2122 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2123 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2124 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2125 } 2126 2127 RecordedNodes.push_back(Imm); 2128 continue; 2129 } 2130 2131 case OPC_EmitMergeInputChains: { 2132 assert(InputChain.getNode() == 0 && 2133 "EmitMergeInputChains should be the first chain producing node"); 2134 // This node gets a list of nodes we matched in the input that have 2135 // chains. We want to token factor all of the input chains to these nodes 2136 // together. However, if any of the input chains is actually one of the 2137 // nodes matched in this pattern, then we have an intra-match reference. 2138 // Ignore these because the newly token factored chain should not refer to 2139 // the old nodes. 2140 unsigned NumChains = MatcherTable[MatcherIndex++]; 2141 assert(NumChains != 0 && "Can't TF zero chains"); 2142 2143 assert(ChainNodesMatched.empty() && 2144 "Should only have one EmitMergeInputChains per match"); 2145 2146 // Handle the first chain. 2147 unsigned RecNo = MatcherTable[MatcherIndex++]; 2148 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2149 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2150 2151 // If the chained node is not the root, we can't fold it if it has 2152 // multiple uses. 2153 // FIXME: What if other value results of the node have uses not matched by 2154 // this pattern? 2155 if (ChainNodesMatched.back() != NodeToMatch && 2156 !RecordedNodes[RecNo].hasOneUse()) { 2157 ChainNodesMatched.clear(); 2158 break; 2159 } 2160 2161 // The common case here is that we have exactly one chain, which is really 2162 // cheap to handle, just do it. 2163 if (NumChains == 1) { 2164 InputChain = RecordedNodes[RecNo].getOperand(0); 2165 assert(InputChain.getValueType() == MVT::Other && "Not a chain"); 2166 continue; 2167 } 2168 2169 // Read all of the chained nodes. 2170 for (unsigned i = 1; i != NumChains; ++i) { 2171 RecNo = MatcherTable[MatcherIndex++]; 2172 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2173 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2174 2175 // FIXME: What if other value results of the node have uses not matched 2176 // by this pattern? 2177 if (ChainNodesMatched.back() != NodeToMatch && 2178 !RecordedNodes[RecNo].hasOneUse()) { 2179 ChainNodesMatched.clear(); 2180 break; 2181 } 2182 } 2183 2184 // If the inner loop broke out, the match fails. 2185 if (ChainNodesMatched.empty()) 2186 break; 2187 2188 // Merge the input chains if they are not intra-pattern references. 2189 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2190 2191 if (InputChain.getNode() == 0) 2192 break; // Failed to merge. 2193 2194 continue; 2195 } 2196 2197 case OPC_EmitCopyToReg: { 2198 unsigned RecNo = MatcherTable[MatcherIndex++]; 2199 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2200 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2201 2202 if (InputChain.getNode() == 0) 2203 InputChain = CurDAG->getEntryNode(); 2204 2205 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2206 DestPhysReg, RecordedNodes[RecNo], 2207 InputFlag); 2208 2209 InputFlag = InputChain.getValue(1); 2210 continue; 2211 } 2212 2213 case OPC_EmitNodeXForm: { 2214 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2215 unsigned RecNo = MatcherTable[MatcherIndex++]; 2216 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2217 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2218 continue; 2219 } 2220 2221 case OPC_EmitNode: 2222 case OPC_MorphNodeTo: { 2223 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2224 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2225 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2226 // Get the result VT list. 2227 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2228 SmallVector<EVT, 4> VTs; 2229 for (unsigned i = 0; i != NumVTs; ++i) { 2230 MVT::SimpleValueType VT = 2231 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2232 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2233 VTs.push_back(VT); 2234 } 2235 2236 if (EmitNodeInfo & OPFL_Chain) 2237 VTs.push_back(MVT::Other); 2238 if (EmitNodeInfo & OPFL_FlagOutput) 2239 VTs.push_back(MVT::Flag); 2240 2241 // This is hot code, so optimize the two most common cases of 1 and 2 2242 // results. 2243 SDVTList VTList; 2244 if (VTs.size() == 1) 2245 VTList = CurDAG->getVTList(VTs[0]); 2246 else if (VTs.size() == 2) 2247 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2248 else 2249 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2250 2251 // Get the operand list. 2252 unsigned NumOps = MatcherTable[MatcherIndex++]; 2253 SmallVector<SDValue, 8> Ops; 2254 for (unsigned i = 0; i != NumOps; ++i) { 2255 unsigned RecNo = MatcherTable[MatcherIndex++]; 2256 if (RecNo & 128) 2257 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2258 2259 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2260 Ops.push_back(RecordedNodes[RecNo]); 2261 } 2262 2263 // If there are variadic operands to add, handle them now. 2264 if (EmitNodeInfo & OPFL_VariadicInfo) { 2265 // Determine the start index to copy from. 2266 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2267 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2268 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2269 "Invalid variadic node"); 2270 // Copy all of the variadic operands, not including a potential flag 2271 // input. 2272 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2273 i != e; ++i) { 2274 SDValue V = NodeToMatch->getOperand(i); 2275 if (V.getValueType() == MVT::Flag) break; 2276 Ops.push_back(V); 2277 } 2278 } 2279 2280 // If this has chain/flag inputs, add them. 2281 if (EmitNodeInfo & OPFL_Chain) 2282 Ops.push_back(InputChain); 2283 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2284 Ops.push_back(InputFlag); 2285 2286 // Create the node. 2287 SDNode *Res = 0; 2288 if (Opcode != OPC_MorphNodeTo) { 2289 // If this is a normal EmitNode command, just create the new node and 2290 // add the results to the RecordedNodes list. 2291 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2292 VTList, Ops.data(), Ops.size()); 2293 2294 // Add all the non-flag/non-chain results to the RecordedNodes list. 2295 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2296 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2297 RecordedNodes.push_back(SDValue(Res, i)); 2298 } 2299 2300 } else { 2301 // It is possible we're using MorphNodeTo to replace a node with no 2302 // normal results with one that has a normal result (or we could be 2303 // adding a chain) and the input could have flags and chains as well. 2304 // In this case we need to shifting the operands down. 2305 // FIXME: This is a horrible hack and broken in obscure cases, no worse 2306 // than the old isel though. We should sink this into MorphNodeTo. 2307 int OldFlagResultNo = -1, OldChainResultNo = -1; 2308 2309 unsigned NTMNumResults = NodeToMatch->getNumValues(); 2310 if (NodeToMatch->getValueType(NTMNumResults-1) == MVT::Flag) { 2311 OldFlagResultNo = NTMNumResults-1; 2312 if (NTMNumResults != 1 && 2313 NodeToMatch->getValueType(NTMNumResults-2) == MVT::Other) 2314 OldChainResultNo = NTMNumResults-2; 2315 } else if (NodeToMatch->getValueType(NTMNumResults-1) == MVT::Other) 2316 OldChainResultNo = NTMNumResults-1; 2317 2318 // FIXME: If this matches multiple nodes it will just leave them here 2319 // dead with noone to love them. These dead nodes can block future 2320 // matches (!). 2321 Res = CurDAG->MorphNodeTo(NodeToMatch, ~TargetOpc, VTList, 2322 Ops.data(), Ops.size()); 2323 2324 // MorphNodeTo can operate in two ways: if an existing node with the 2325 // specified operands exists, it can just return it. Otherwise, it 2326 // updates the node in place to have the requested operands. 2327 if (Res == NodeToMatch) { 2328 // If we updated the node in place, reset the node ID. To the isel, 2329 // this should be just like a newly allocated machine node. 2330 Res->setNodeId(-1); 2331 } 2332 2333 unsigned ResNumResults = Res->getNumValues(); 2334 // Move the flag if needed. 2335 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 2336 (unsigned)OldFlagResultNo != ResNumResults-1) 2337 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 2338 OldFlagResultNo), 2339 SDValue(Res, ResNumResults-1)); 2340 2341 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 2342 --ResNumResults; 2343 2344 // Move the chain reference if needed. 2345 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 2346 (unsigned)OldChainResultNo != ResNumResults-1) 2347 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 2348 OldChainResultNo), 2349 SDValue(Res, ResNumResults-1)); 2350 2351 if (Res != NodeToMatch) { 2352 // Otherwise, no replacement happened because the node already exists. 2353 CurDAG->ReplaceAllUsesWith(NodeToMatch, Res); 2354 } 2355 } 2356 2357 // If the node had chain/flag results, update our notion of the current 2358 // chain and flag. 2359 if (VTs.back() == MVT::Flag) { 2360 InputFlag = SDValue(Res, VTs.size()-1); 2361 if (EmitNodeInfo & OPFL_Chain) 2362 InputChain = SDValue(Res, VTs.size()-2); 2363 } else if (EmitNodeInfo & OPFL_Chain) 2364 InputChain = SDValue(Res, VTs.size()-1); 2365 2366 // If the OPFL_MemRefs flag is set on this node, slap all of the 2367 // accumulated memrefs onto it. 2368 // 2369 // FIXME: This is vastly incorrect for patterns with multiple outputs 2370 // instructions that access memory and for ComplexPatterns that match 2371 // loads. 2372 if (EmitNodeInfo & OPFL_MemRefs) { 2373 MachineSDNode::mmo_iterator MemRefs = 2374 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2375 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2376 cast<MachineSDNode>(Res) 2377 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2378 } 2379 2380 DEBUG(errs() << " " 2381 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2382 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2383 2384 // If this was a MorphNodeTo then we're completely done! 2385 if (Opcode == OPC_MorphNodeTo) { 2386 // Update chain and flag uses. 2387 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2388 InputFlag, FlagResultNodesMatched, true, CurDAG); 2389 return 0; 2390 } 2391 2392 continue; 2393 } 2394 2395 case OPC_MarkFlagResults: { 2396 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2397 2398 // Read and remember all the flag-result nodes. 2399 for (unsigned i = 0; i != NumNodes; ++i) { 2400 unsigned RecNo = MatcherTable[MatcherIndex++]; 2401 if (RecNo & 128) 2402 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2403 2404 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2405 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2406 } 2407 continue; 2408 } 2409 2410 case OPC_CompleteMatch: { 2411 // The match has been completed, and any new nodes (if any) have been 2412 // created. Patch up references to the matched dag to use the newly 2413 // created nodes. 2414 unsigned NumResults = MatcherTable[MatcherIndex++]; 2415 2416 for (unsigned i = 0; i != NumResults; ++i) { 2417 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2418 if (ResSlot & 128) 2419 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2420 2421 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2422 SDValue Res = RecordedNodes[ResSlot]; 2423 2424 // FIXME2: Eliminate this horrible hack by fixing the 'Gen' program 2425 // after (parallel) on input patterns are removed. This would also 2426 // allow us to stop encoding #results in OPC_CompleteMatch's table 2427 // entry. 2428 if (NodeToMatch->getNumValues() <= i || 2429 NodeToMatch->getValueType(i) == MVT::Other || 2430 NodeToMatch->getValueType(i) == MVT::Flag) 2431 break; 2432 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2433 NodeToMatch->getValueType(i) == MVT::iPTR || 2434 Res.getValueType() == MVT::iPTR || 2435 NodeToMatch->getValueType(i).getSizeInBits() == 2436 Res.getValueType().getSizeInBits()) && 2437 "invalid replacement"); 2438 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2439 } 2440 2441 // If the root node defines a flag, add it to the flag nodes to update 2442 // list. 2443 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2444 FlagResultNodesMatched.push_back(NodeToMatch); 2445 2446 // Update chain and flag uses. 2447 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2448 InputFlag, FlagResultNodesMatched, false, CurDAG); 2449 2450 assert(NodeToMatch->use_empty() && 2451 "Didn't replace all uses of the node?"); 2452 2453 // FIXME: We just return here, which interacts correctly with SelectRoot 2454 // above. We should fix this to not return an SDNode* anymore. 2455 return 0; 2456 } 2457 } 2458 2459 // If the code reached this point, then the match failed. See if there is 2460 // another child to try in the current 'Scope', otherwise pop it until we 2461 // find a case to check. 2462 while (1) { 2463 if (MatchScopes.empty()) { 2464 CannotYetSelect(NodeToMatch); 2465 return 0; 2466 } 2467 2468 // Restore the interpreter state back to the point where the scope was 2469 // formed. 2470 MatchScope &LastScope = MatchScopes.back(); 2471 RecordedNodes.resize(LastScope.NumRecordedNodes); 2472 NodeStack.clear(); 2473 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2474 N = NodeStack.back(); 2475 2476 DEBUG(errs() << " Match failed at index " << MatcherIndex 2477 << " continuing at " << LastScope.FailIndex << "\n"); 2478 2479 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2480 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2481 MatcherIndex = LastScope.FailIndex; 2482 2483 InputChain = LastScope.InputChain; 2484 InputFlag = LastScope.InputFlag; 2485 if (!LastScope.HasChainNodesMatched) 2486 ChainNodesMatched.clear(); 2487 if (!LastScope.HasFlagResultNodesMatched) 2488 FlagResultNodesMatched.clear(); 2489 2490 // Check to see what the offset is at the new MatcherIndex. If it is zero 2491 // we have reached the end of this scope, otherwise we have another child 2492 // in the current scope to try. 2493 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2494 if (NumToSkip & 128) 2495 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2496 2497 // If we have another child in this scope to match, update FailIndex and 2498 // try it. 2499 if (NumToSkip != 0) { 2500 LastScope.FailIndex = MatcherIndex+NumToSkip; 2501 break; 2502 } 2503 2504 // End of this scope, pop it and try the next child in the containing 2505 // scope. 2506 MatchScopes.pop_back(); 2507 } 2508 } 2509} 2510 2511 2512 2513void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2514 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN || 2515 N->getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2516 N->getOpcode() == ISD::INTRINSIC_VOID) 2517 return CannotYetSelectIntrinsic(N); 2518 2519 std::string msg; 2520 raw_string_ostream Msg(msg); 2521 Msg << "Cannot yet select: "; 2522 N->printrFull(Msg, CurDAG); 2523 llvm_report_error(Msg.str()); 2524} 2525 2526void SelectionDAGISel::CannotYetSelectIntrinsic(SDNode *N) { 2527 dbgs() << "Cannot yet select: "; 2528 unsigned iid = 2529 cast<ConstantSDNode>(N->getOperand(N->getOperand(0).getValueType() == 2530 MVT::Other))->getZExtValue(); 2531 if (iid < Intrinsic::num_intrinsics) 2532 llvm_report_error("Cannot yet select: intrinsic %" + 2533 Intrinsic::getName((Intrinsic::ID)iid)); 2534 else if (const TargetIntrinsicInfo *tii = TM.getIntrinsicInfo()) 2535 llvm_report_error(Twine("Cannot yet select: target intrinsic %") + 2536 tii->getName(iid)); 2537} 2538 2539char SelectionDAGISel::ID = 0; 2540