SelectionDAGISel.cpp revision 657484f494edbac571ce2a91b8ac227e5011321d
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "ScheduleDAGSDNodes.h" 17#include "SelectionDAGBuilder.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/Statistic.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/BranchProbabilityInfo.h" 22#include "llvm/Analysis/CFG.h" 23#include "llvm/Analysis/TargetTransformInfo.h" 24#include "llvm/CodeGen/FastISel.h" 25#include "llvm/CodeGen/FunctionLoweringInfo.h" 26#include "llvm/CodeGen/GCMetadata.h" 27#include "llvm/CodeGen/GCStrategy.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineModuleInfo.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/DebugInfo.h" 37#include "llvm/IR/Constants.h" 38#include "llvm/IR/Function.h" 39#include "llvm/IR/InlineAsm.h" 40#include "llvm/IR/Instructions.h" 41#include "llvm/IR/IntrinsicInst.h" 42#include "llvm/IR/Intrinsics.h" 43#include "llvm/IR/LLVMContext.h" 44#include "llvm/IR/Module.h" 45#include "llvm/Support/Compiler.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/ErrorHandling.h" 48#include "llvm/Support/Timer.h" 49#include "llvm/Support/raw_ostream.h" 50#include "llvm/Target/TargetInstrInfo.h" 51#include "llvm/Target/TargetIntrinsicInfo.h" 52#include "llvm/Target/TargetLibraryInfo.h" 53#include "llvm/Target/TargetLowering.h" 54#include "llvm/Target/TargetMachine.h" 55#include "llvm/Target/TargetOptions.h" 56#include "llvm/Target/TargetRegisterInfo.h" 57#include "llvm/Target/TargetSubtargetInfo.h" 58#include "llvm/Transforms/Utils/BasicBlockUtils.h" 59#include <algorithm> 60using namespace llvm; 61 62STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 63STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 64STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 65STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 66STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 67STATISTIC(NumEntryBlocks, "Number of entry blocks encountered"); 68STATISTIC(NumFastIselFailLowerArguments, 69 "Number of entry blocks where fast isel failed to lower arguments"); 70 71#ifndef NDEBUG 72static cl::opt<bool> 73EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 74 cl::desc("Enable extra verbose messages in the \"fast\" " 75 "instruction selector")); 76 77 // Terminators 78STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 79STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 80STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 81STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 82STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 83STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 84STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 85 86 // Standard binary operators... 87STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 88STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 89STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 90STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 91STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 92STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 93STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 94STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 95STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 96STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 97STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 98STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 99 100 // Logical operators... 101STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 102STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 103STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 104 105 // Memory instructions... 106STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 107STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 108STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 109STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 110STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 111STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 112STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 113 114 // Convert instructions... 115STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 116STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 117STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 118STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 119STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 120STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 121STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 122STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 123STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 124STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 125STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 126STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 127 128 // Other instructions... 129STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 130STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 131STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 132STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 133STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 134STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 135STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 136STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 137STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 138STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 139STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 140STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 141STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 142STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 143STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 144#endif 145 146static cl::opt<bool> 147EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 148 cl::desc("Enable verbose messages in the \"fast\" " 149 "instruction selector")); 150static cl::opt<bool> 151EnableFastISelAbort("fast-isel-abort", cl::Hidden, 152 cl::desc("Enable abort calls when \"fast\" instruction selection " 153 "fails to lower an instruction")); 154static cl::opt<bool> 155EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden, 156 cl::desc("Enable abort calls when \"fast\" instruction selection " 157 "fails to lower a formal argument")); 158 159static cl::opt<bool> 160UseMBPI("use-mbpi", 161 cl::desc("use Machine Branch Probability Info"), 162 cl::init(true), cl::Hidden); 163 164#ifndef NDEBUG 165static cl::opt<bool> 166ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 167 cl::desc("Pop up a window to show dags before the first " 168 "dag combine pass")); 169static cl::opt<bool> 170ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 171 cl::desc("Pop up a window to show dags before legalize types")); 172static cl::opt<bool> 173ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 174 cl::desc("Pop up a window to show dags before legalize")); 175static cl::opt<bool> 176ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 177 cl::desc("Pop up a window to show dags before the second " 178 "dag combine pass")); 179static cl::opt<bool> 180ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 181 cl::desc("Pop up a window to show dags before the post legalize types" 182 " dag combine pass")); 183static cl::opt<bool> 184ViewISelDAGs("view-isel-dags", cl::Hidden, 185 cl::desc("Pop up a window to show isel dags as they are selected")); 186static cl::opt<bool> 187ViewSchedDAGs("view-sched-dags", cl::Hidden, 188 cl::desc("Pop up a window to show sched dags as they are processed")); 189static cl::opt<bool> 190ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 191 cl::desc("Pop up a window to show SUnit dags after they are processed")); 192#else 193static const bool ViewDAGCombine1 = false, 194 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 195 ViewDAGCombine2 = false, 196 ViewDAGCombineLT = false, 197 ViewISelDAGs = false, ViewSchedDAGs = false, 198 ViewSUnitDAGs = false; 199#endif 200 201//===---------------------------------------------------------------------===// 202/// 203/// RegisterScheduler class - Track the registration of instruction schedulers. 204/// 205//===---------------------------------------------------------------------===// 206MachinePassRegistry RegisterScheduler::Registry; 207 208//===---------------------------------------------------------------------===// 209/// 210/// ISHeuristic command line option for instruction schedulers. 211/// 212//===---------------------------------------------------------------------===// 213static cl::opt<RegisterScheduler::FunctionPassCtor, false, 214 RegisterPassParser<RegisterScheduler> > 215ISHeuristic("pre-RA-sched", 216 cl::init(&createDefaultScheduler), 217 cl::desc("Instruction schedulers available (before register" 218 " allocation):")); 219 220static RegisterScheduler 221defaultListDAGScheduler("default", "Best scheduler for the target", 222 createDefaultScheduler); 223 224namespace llvm { 225 //===--------------------------------------------------------------------===// 226 /// createDefaultScheduler - This creates an instruction scheduler appropriate 227 /// for the target. 228 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 229 CodeGenOpt::Level OptLevel) { 230 const TargetLowering *TLI = IS->getTargetLowering(); 231 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 232 233 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() || 234 TLI->getSchedulingPreference() == Sched::Source) 235 return createSourceListDAGScheduler(IS, OptLevel); 236 if (TLI->getSchedulingPreference() == Sched::RegPressure) 237 return createBURRListDAGScheduler(IS, OptLevel); 238 if (TLI->getSchedulingPreference() == Sched::Hybrid) 239 return createHybridListDAGScheduler(IS, OptLevel); 240 if (TLI->getSchedulingPreference() == Sched::VLIW) 241 return createVLIWDAGScheduler(IS, OptLevel); 242 assert(TLI->getSchedulingPreference() == Sched::ILP && 243 "Unknown sched type!"); 244 return createILPListDAGScheduler(IS, OptLevel); 245 } 246} 247 248// EmitInstrWithCustomInserter - This method should be implemented by targets 249// that mark instructions with the 'usesCustomInserter' flag. These 250// instructions are special in various ways, which require special support to 251// insert. The specified MachineInstr is created but not inserted into any 252// basic blocks, and this method is called to expand it into a sequence of 253// instructions, potentially also creating new basic blocks and control flow. 254// When new basic blocks are inserted and the edges from MBB to its successors 255// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 256// DenseMap. 257MachineBasicBlock * 258TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 259 MachineBasicBlock *MBB) const { 260#ifndef NDEBUG 261 dbgs() << "If a target marks an instruction with " 262 "'usesCustomInserter', it must implement " 263 "TargetLowering::EmitInstrWithCustomInserter!"; 264#endif 265 llvm_unreachable(0); 266} 267 268void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 269 SDNode *Node) const { 270 assert(!MI->hasPostISelHook() && 271 "If a target marks an instruction with 'hasPostISelHook', " 272 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 273} 274 275//===----------------------------------------------------------------------===// 276// SelectionDAGISel code 277//===----------------------------------------------------------------------===// 278 279SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, 280 CodeGenOpt::Level OL) : 281 MachineFunctionPass(ID), TM(tm), 282 FuncInfo(new FunctionLoweringInfo(TM)), 283 CurDAG(new SelectionDAG(tm, OL)), 284 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 285 GFI(), 286 OptLevel(OL), 287 DAGSize(0) { 288 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 289 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 290 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 291 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 292 } 293 294SelectionDAGISel::~SelectionDAGISel() { 295 delete SDB; 296 delete CurDAG; 297 delete FuncInfo; 298} 299 300void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 301 AU.addRequired<AliasAnalysis>(); 302 AU.addPreserved<AliasAnalysis>(); 303 AU.addRequired<GCModuleInfo>(); 304 AU.addPreserved<GCModuleInfo>(); 305 AU.addRequired<TargetLibraryInfo>(); 306 if (UseMBPI && OptLevel != CodeGenOpt::None) 307 AU.addRequired<BranchProbabilityInfo>(); 308 MachineFunctionPass::getAnalysisUsage(AU); 309} 310 311/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 312/// may trap on it. In this case we have to split the edge so that the path 313/// through the predecessor block that doesn't go to the phi block doesn't 314/// execute the possibly trapping instruction. 315/// 316/// This is required for correctness, so it must be done at -O0. 317/// 318static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 319 // Loop for blocks with phi nodes. 320 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 321 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 322 if (PN == 0) continue; 323 324 ReprocessBlock: 325 // For each block with a PHI node, check to see if any of the input values 326 // are potentially trapping constant expressions. Constant expressions are 327 // the only potentially trapping value that can occur as the argument to a 328 // PHI. 329 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 330 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 331 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 332 if (CE == 0 || !CE->canTrap()) continue; 333 334 // The only case we have to worry about is when the edge is critical. 335 // Since this block has a PHI Node, we assume it has multiple input 336 // edges: check to see if the pred has multiple successors. 337 BasicBlock *Pred = PN->getIncomingBlock(i); 338 if (Pred->getTerminator()->getNumSuccessors() == 1) 339 continue; 340 341 // Okay, we have to split this edge. 342 SplitCriticalEdge(Pred->getTerminator(), 343 GetSuccessorNumber(Pred, BB), SDISel, true); 344 goto ReprocessBlock; 345 } 346 } 347} 348 349bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 350 // Do some sanity-checking on the command-line options. 351 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 352 "-fast-isel-verbose requires -fast-isel"); 353 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 354 "-fast-isel-abort requires -fast-isel"); 355 356 const Function &Fn = *mf.getFunction(); 357 const TargetInstrInfo &TII = *TM.getInstrInfo(); 358 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 359 360 MF = &mf; 361 RegInfo = &MF->getRegInfo(); 362 AA = &getAnalysis<AliasAnalysis>(); 363 LibInfo = &getAnalysis<TargetLibraryInfo>(); 364 TTI = getAnalysisIfAvailable<TargetTransformInfo>(); 365 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 366 367 TargetSubtargetInfo &ST = 368 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 369 ST.resetSubtargetFeatures(MF); 370 TM.resetTargetOptions(MF); 371 372 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 373 374 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 375 376 CurDAG->init(*MF, TTI); 377 FuncInfo->set(Fn, *MF); 378 379 if (UseMBPI && OptLevel != CodeGenOpt::None) 380 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 381 else 382 FuncInfo->BPI = 0; 383 384 SDB->init(GFI, *AA, LibInfo); 385 386 MF->setHasMSInlineAsm(false); 387 SelectAllBasicBlocks(Fn); 388 389 // If the first basic block in the function has live ins that need to be 390 // copied into vregs, emit the copies into the top of the block before 391 // emitting the code for the block. 392 MachineBasicBlock *EntryMBB = MF->begin(); 393 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 394 395 DenseMap<unsigned, unsigned> LiveInMap; 396 if (!FuncInfo->ArgDbgValues.empty()) 397 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 398 E = RegInfo->livein_end(); LI != E; ++LI) 399 if (LI->second) 400 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 401 402 // Insert DBG_VALUE instructions for function arguments to the entry block. 403 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 404 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 405 bool hasFI = MI->getOperand(0).isFI(); 406 unsigned Reg = hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg(); 407 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 408 EntryMBB->insert(EntryMBB->begin(), MI); 409 else { 410 MachineInstr *Def = RegInfo->getVRegDef(Reg); 411 MachineBasicBlock::iterator InsertPos = Def; 412 // FIXME: VR def may not be in entry block. 413 Def->getParent()->insert(llvm::next(InsertPos), MI); 414 } 415 416 // If Reg is live-in then update debug info to track its copy in a vreg. 417 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 418 if (LDI != LiveInMap.end()) { 419 assert(!hasFI && "There's no handling of frame pointer updating here yet " 420 "- add if needed"); 421 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 422 MachineBasicBlock::iterator InsertPos = Def; 423 const MDNode *Variable = 424 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 425 bool IsIndirect = MI->getOperand(1).isImm(); 426 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; 427 // Def is never a terminator here, so it is ok to increment InsertPos. 428 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 429 TII.get(TargetOpcode::DBG_VALUE), 430 IsIndirect, 431 LDI->second, Offset, Variable); 432 433 // If this vreg is directly copied into an exported register then 434 // that COPY instructions also need DBG_VALUE, if it is the only 435 // user of LDI->second. 436 MachineInstr *CopyUseMI = NULL; 437 for (MachineRegisterInfo::use_iterator 438 UI = RegInfo->use_begin(LDI->second); 439 MachineInstr *UseMI = UI.skipInstruction();) { 440 if (UseMI->isDebugValue()) continue; 441 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 442 CopyUseMI = UseMI; continue; 443 } 444 // Otherwise this is another use or second copy use. 445 CopyUseMI = NULL; break; 446 } 447 if (CopyUseMI) { 448 MachineInstr *NewMI = 449 BuildMI(*MF, CopyUseMI->getDebugLoc(), 450 TII.get(TargetOpcode::DBG_VALUE), 451 IsIndirect, 452 CopyUseMI->getOperand(0).getReg(), 453 Offset, Variable); 454 MachineBasicBlock::iterator Pos = CopyUseMI; 455 EntryMBB->insertAfter(Pos, NewMI); 456 } 457 } 458 } 459 460 // Determine if there are any calls in this machine function. 461 MachineFrameInfo *MFI = MF->getFrameInfo(); 462 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E; 463 ++I) { 464 465 if (MFI->hasCalls() && MF->hasMSInlineAsm()) 466 break; 467 468 const MachineBasicBlock *MBB = I; 469 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end(); 470 II != IE; ++II) { 471 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 472 if ((MCID.isCall() && !MCID.isReturn()) || 473 II->isStackAligningInlineAsm()) { 474 MFI->setHasCalls(true); 475 } 476 if (II->isMSInlineAsm()) { 477 MF->setHasMSInlineAsm(true); 478 } 479 } 480 } 481 482 // Determine if there is a call to setjmp in the machine function. 483 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 484 485 // Replace forward-declared registers with the registers containing 486 // the desired value. 487 MachineRegisterInfo &MRI = MF->getRegInfo(); 488 for (DenseMap<unsigned, unsigned>::iterator 489 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 490 I != E; ++I) { 491 unsigned From = I->first; 492 unsigned To = I->second; 493 // If To is also scheduled to be replaced, find what its ultimate 494 // replacement is. 495 for (;;) { 496 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 497 if (J == E) break; 498 To = J->second; 499 } 500 // Make sure the new register has a sufficiently constrained register class. 501 if (TargetRegisterInfo::isVirtualRegister(From) && 502 TargetRegisterInfo::isVirtualRegister(To)) 503 MRI.constrainRegClass(To, MRI.getRegClass(From)); 504 // Replace it. 505 MRI.replaceRegWith(From, To); 506 } 507 508 // Freeze the set of reserved registers now that MachineFrameInfo has been 509 // set up. All the information required by getReservedRegs() should be 510 // available now. 511 MRI.freezeReservedRegs(*MF); 512 513 // Release function-specific state. SDB and CurDAG are already cleared 514 // at this point. 515 FuncInfo->clear(); 516 517 return true; 518} 519 520void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 521 BasicBlock::const_iterator End, 522 bool &HadTailCall) { 523 // Lower all of the non-terminator instructions. If a call is emitted 524 // as a tail call, cease emitting nodes for this block. Terminators 525 // are handled below. 526 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 527 SDB->visit(*I); 528 529 // Make sure the root of the DAG is up-to-date. 530 CurDAG->setRoot(SDB->getControlRoot()); 531 HadTailCall = SDB->HasTailCall; 532 SDB->clear(); 533 534 // Final step, emit the lowered DAG as machine code. 535 CodeGenAndEmitDAG(); 536} 537 538void SelectionDAGISel::ComputeLiveOutVRegInfo() { 539 SmallPtrSet<SDNode*, 128> VisitedNodes; 540 SmallVector<SDNode*, 128> Worklist; 541 542 Worklist.push_back(CurDAG->getRoot().getNode()); 543 544 APInt KnownZero; 545 APInt KnownOne; 546 547 do { 548 SDNode *N = Worklist.pop_back_val(); 549 550 // If we've already seen this node, ignore it. 551 if (!VisitedNodes.insert(N)) 552 continue; 553 554 // Otherwise, add all chain operands to the worklist. 555 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 556 if (N->getOperand(i).getValueType() == MVT::Other) 557 Worklist.push_back(N->getOperand(i).getNode()); 558 559 // If this is a CopyToReg with a vreg dest, process it. 560 if (N->getOpcode() != ISD::CopyToReg) 561 continue; 562 563 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 564 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 565 continue; 566 567 // Ignore non-scalar or non-integer values. 568 SDValue Src = N->getOperand(2); 569 EVT SrcVT = Src.getValueType(); 570 if (!SrcVT.isInteger() || SrcVT.isVector()) 571 continue; 572 573 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 574 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 575 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 576 } while (!Worklist.empty()); 577} 578 579void SelectionDAGISel::CodeGenAndEmitDAG() { 580 std::string GroupName; 581 if (TimePassesIsEnabled) 582 GroupName = "Instruction Selection and Scheduling"; 583 std::string BlockName; 584 int BlockNumber = -1; 585 (void)BlockNumber; 586#ifdef NDEBUG 587 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 588 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 589 ViewSUnitDAGs) 590#endif 591 { 592 BlockNumber = FuncInfo->MBB->getNumber(); 593 BlockName = MF->getName().str() + ":" + 594 FuncInfo->MBB->getBasicBlock()->getName().str(); 595 } 596 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 597 << " '" << BlockName << "'\n"; CurDAG->dump()); 598 599 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 600 601 // Run the DAG combiner in pre-legalize mode. 602 { 603 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 604 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 605 } 606 607 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 608 << " '" << BlockName << "'\n"; CurDAG->dump()); 609 610 // Second step, hack on the DAG until it only uses operations and types that 611 // the target supports. 612 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 613 BlockName); 614 615 bool Changed; 616 { 617 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 618 Changed = CurDAG->LegalizeTypes(); 619 } 620 621 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 622 << " '" << BlockName << "'\n"; CurDAG->dump()); 623 624 if (Changed) { 625 if (ViewDAGCombineLT) 626 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 627 628 // Run the DAG combiner in post-type-legalize mode. 629 { 630 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 631 TimePassesIsEnabled); 632 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 633 } 634 635 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 636 << " '" << BlockName << "'\n"; CurDAG->dump()); 637 638 } 639 640 { 641 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 642 Changed = CurDAG->LegalizeVectors(); 643 } 644 645 if (Changed) { 646 { 647 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 648 CurDAG->LegalizeTypes(); 649 } 650 651 if (ViewDAGCombineLT) 652 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 653 654 // Run the DAG combiner in post-type-legalize mode. 655 { 656 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 657 TimePassesIsEnabled); 658 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 659 } 660 661 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 662 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 663 } 664 665 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 666 667 { 668 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 669 CurDAG->Legalize(); 670 } 671 672 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 673 << " '" << BlockName << "'\n"; CurDAG->dump()); 674 675 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 676 677 // Run the DAG combiner in post-legalize mode. 678 { 679 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 680 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 681 } 682 683 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 684 << " '" << BlockName << "'\n"; CurDAG->dump()); 685 686 if (OptLevel != CodeGenOpt::None) 687 ComputeLiveOutVRegInfo(); 688 689 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 690 691 // Third, instruction select all of the operations to machine code, adding the 692 // code to the MachineBasicBlock. 693 { 694 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 695 DoInstructionSelection(); 696 } 697 698 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 699 << " '" << BlockName << "'\n"; CurDAG->dump()); 700 701 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 702 703 // Schedule machine code. 704 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 705 { 706 NamedRegionTimer T("Instruction Scheduling", GroupName, 707 TimePassesIsEnabled); 708 Scheduler->Run(CurDAG, FuncInfo->MBB); 709 } 710 711 if (ViewSUnitDAGs) Scheduler->viewGraph(); 712 713 // Emit machine code to BB. This can change 'BB' to the last block being 714 // inserted into. 715 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 716 { 717 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 718 719 // FuncInfo->InsertPt is passed by reference and set to the end of the 720 // scheduled instructions. 721 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 722 } 723 724 // If the block was split, make sure we update any references that are used to 725 // update PHI nodes later on. 726 if (FirstMBB != LastMBB) 727 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 728 729 // Free the scheduler state. 730 { 731 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 732 TimePassesIsEnabled); 733 delete Scheduler; 734 } 735 736 // Free the SelectionDAG state, now that we're finished with it. 737 CurDAG->clear(); 738} 739 740namespace { 741/// ISelUpdater - helper class to handle updates of the instruction selection 742/// graph. 743class ISelUpdater : public SelectionDAG::DAGUpdateListener { 744 SelectionDAG::allnodes_iterator &ISelPosition; 745public: 746 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 747 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 748 749 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 750 /// deleted is the current ISelPosition node, update ISelPosition. 751 /// 752 virtual void NodeDeleted(SDNode *N, SDNode *E) { 753 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 754 ++ISelPosition; 755 } 756}; 757} // end anonymous namespace 758 759void SelectionDAGISel::DoInstructionSelection() { 760 DEBUG(dbgs() << "===== Instruction selection begins: BB#" 761 << FuncInfo->MBB->getNumber() 762 << " '" << FuncInfo->MBB->getName() << "'\n"); 763 764 PreprocessISelDAG(); 765 766 // Select target instructions for the DAG. 767 { 768 // Number all nodes with a topological order and set DAGSize. 769 DAGSize = CurDAG->AssignTopologicalOrder(); 770 771 // Create a dummy node (which is not added to allnodes), that adds 772 // a reference to the root node, preventing it from being deleted, 773 // and tracking any changes of the root. 774 HandleSDNode Dummy(CurDAG->getRoot()); 775 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 776 ++ISelPosition; 777 778 // Make sure that ISelPosition gets properly updated when nodes are deleted 779 // in calls made from this function. 780 ISelUpdater ISU(*CurDAG, ISelPosition); 781 782 // The AllNodes list is now topological-sorted. Visit the 783 // nodes by starting at the end of the list (the root of the 784 // graph) and preceding back toward the beginning (the entry 785 // node). 786 while (ISelPosition != CurDAG->allnodes_begin()) { 787 SDNode *Node = --ISelPosition; 788 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 789 // but there are currently some corner cases that it misses. Also, this 790 // makes it theoretically possible to disable the DAGCombiner. 791 if (Node->use_empty()) 792 continue; 793 794 SDNode *ResNode = Select(Node); 795 796 // FIXME: This is pretty gross. 'Select' should be changed to not return 797 // anything at all and this code should be nuked with a tactical strike. 798 799 // If node should not be replaced, continue with the next one. 800 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 801 continue; 802 // Replace node. 803 if (ResNode) { 804 ReplaceUses(Node, ResNode); 805 } 806 807 // If after the replacement this node is not used any more, 808 // remove this dead node. 809 if (Node->use_empty()) // Don't delete EntryToken, etc. 810 CurDAG->RemoveDeadNode(Node); 811 } 812 813 CurDAG->setRoot(Dummy.getValue()); 814 } 815 816 DEBUG(dbgs() << "===== Instruction selection ends:\n"); 817 818 PostprocessISelDAG(); 819} 820 821/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 822/// do other setup for EH landing-pad blocks. 823void SelectionDAGISel::PrepareEHLandingPad() { 824 MachineBasicBlock *MBB = FuncInfo->MBB; 825 826 // Add a label to mark the beginning of the landing pad. Deletion of the 827 // landing pad can thus be detected via the MachineModuleInfo. 828 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 829 830 // Assign the call site to the landing pad's begin label. 831 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 832 833 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 834 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 835 .addSym(Label); 836 837 // Mark exception register as live in. 838 const TargetLowering *TLI = getTargetLowering(); 839 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy()); 840 if (unsigned Reg = TLI->getExceptionPointerRegister()) 841 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC); 842 843 // Mark exception selector register as live in. 844 if (unsigned Reg = TLI->getExceptionSelectorRegister()) 845 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC); 846} 847 848/// isFoldedOrDeadInstruction - Return true if the specified instruction is 849/// side-effect free and is either dead or folded into a generated instruction. 850/// Return false if it needs to be emitted. 851static bool isFoldedOrDeadInstruction(const Instruction *I, 852 FunctionLoweringInfo *FuncInfo) { 853 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 854 !isa<TerminatorInst>(I) && // Terminators aren't folded. 855 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 856 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 857 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 858} 859 860#ifndef NDEBUG 861// Collect per Instruction statistics for fast-isel misses. Only those 862// instructions that cause the bail are accounted for. It does not account for 863// instructions higher in the block. Thus, summing the per instructions stats 864// will not add up to what is reported by NumFastIselFailures. 865static void collectFailStats(const Instruction *I) { 866 switch (I->getOpcode()) { 867 default: assert (0 && "<Invalid operator> "); 868 869 // Terminators 870 case Instruction::Ret: NumFastIselFailRet++; return; 871 case Instruction::Br: NumFastIselFailBr++; return; 872 case Instruction::Switch: NumFastIselFailSwitch++; return; 873 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 874 case Instruction::Invoke: NumFastIselFailInvoke++; return; 875 case Instruction::Resume: NumFastIselFailResume++; return; 876 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 877 878 // Standard binary operators... 879 case Instruction::Add: NumFastIselFailAdd++; return; 880 case Instruction::FAdd: NumFastIselFailFAdd++; return; 881 case Instruction::Sub: NumFastIselFailSub++; return; 882 case Instruction::FSub: NumFastIselFailFSub++; return; 883 case Instruction::Mul: NumFastIselFailMul++; return; 884 case Instruction::FMul: NumFastIselFailFMul++; return; 885 case Instruction::UDiv: NumFastIselFailUDiv++; return; 886 case Instruction::SDiv: NumFastIselFailSDiv++; return; 887 case Instruction::FDiv: NumFastIselFailFDiv++; return; 888 case Instruction::URem: NumFastIselFailURem++; return; 889 case Instruction::SRem: NumFastIselFailSRem++; return; 890 case Instruction::FRem: NumFastIselFailFRem++; return; 891 892 // Logical operators... 893 case Instruction::And: NumFastIselFailAnd++; return; 894 case Instruction::Or: NumFastIselFailOr++; return; 895 case Instruction::Xor: NumFastIselFailXor++; return; 896 897 // Memory instructions... 898 case Instruction::Alloca: NumFastIselFailAlloca++; return; 899 case Instruction::Load: NumFastIselFailLoad++; return; 900 case Instruction::Store: NumFastIselFailStore++; return; 901 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 902 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 903 case Instruction::Fence: NumFastIselFailFence++; return; 904 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 905 906 // Convert instructions... 907 case Instruction::Trunc: NumFastIselFailTrunc++; return; 908 case Instruction::ZExt: NumFastIselFailZExt++; return; 909 case Instruction::SExt: NumFastIselFailSExt++; return; 910 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 911 case Instruction::FPExt: NumFastIselFailFPExt++; return; 912 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 913 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 914 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 915 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 916 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 917 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 918 case Instruction::BitCast: NumFastIselFailBitCast++; return; 919 920 // Other instructions... 921 case Instruction::ICmp: NumFastIselFailICmp++; return; 922 case Instruction::FCmp: NumFastIselFailFCmp++; return; 923 case Instruction::PHI: NumFastIselFailPHI++; return; 924 case Instruction::Select: NumFastIselFailSelect++; return; 925 case Instruction::Call: NumFastIselFailCall++; return; 926 case Instruction::Shl: NumFastIselFailShl++; return; 927 case Instruction::LShr: NumFastIselFailLShr++; return; 928 case Instruction::AShr: NumFastIselFailAShr++; return; 929 case Instruction::VAArg: NumFastIselFailVAArg++; return; 930 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 931 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 932 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 933 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 934 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 935 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 936 } 937} 938#endif 939 940void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 941 // Initialize the Fast-ISel state, if needed. 942 FastISel *FastIS = 0; 943 if (TM.Options.EnableFastISel) 944 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo); 945 946 // Iterate over all basic blocks in the function. 947 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 948 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 949 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 950 const BasicBlock *LLVMBB = *I; 951 952 if (OptLevel != CodeGenOpt::None) { 953 bool AllPredsVisited = true; 954 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 955 PI != PE; ++PI) { 956 if (!FuncInfo->VisitedBBs.count(*PI)) { 957 AllPredsVisited = false; 958 break; 959 } 960 } 961 962 if (AllPredsVisited) { 963 for (BasicBlock::const_iterator I = LLVMBB->begin(); 964 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 965 FuncInfo->ComputePHILiveOutRegInfo(PN); 966 } else { 967 for (BasicBlock::const_iterator I = LLVMBB->begin(); 968 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 969 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 970 } 971 972 FuncInfo->VisitedBBs.insert(LLVMBB); 973 } 974 975 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 976 BasicBlock::const_iterator const End = LLVMBB->end(); 977 BasicBlock::const_iterator BI = End; 978 979 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 980 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 981 982 // Setup an EH landing-pad block. 983 FuncInfo->ExceptionPointerVirtReg = 0; 984 FuncInfo->ExceptionSelectorVirtReg = 0; 985 if (FuncInfo->MBB->isLandingPad()) 986 PrepareEHLandingPad(); 987 988 // Before doing SelectionDAG ISel, see if FastISel has been requested. 989 if (FastIS) { 990 FastIS->startNewBlock(); 991 992 // Emit code for any incoming arguments. This must happen before 993 // beginning FastISel on the entry block. 994 if (LLVMBB == &Fn.getEntryBlock()) { 995 ++NumEntryBlocks; 996 997 // Lower any arguments needed in this block if this is the entry block. 998 if (!FastIS->LowerArguments()) { 999 // Fast isel failed to lower these arguments 1000 ++NumFastIselFailLowerArguments; 1001 if (EnableFastISelAbortArgs) 1002 llvm_unreachable("FastISel didn't lower all arguments"); 1003 1004 // Use SelectionDAG argument lowering 1005 LowerArguments(Fn); 1006 CurDAG->setRoot(SDB->getControlRoot()); 1007 SDB->clear(); 1008 CodeGenAndEmitDAG(); 1009 } 1010 1011 // If we inserted any instructions at the beginning, make a note of 1012 // where they are, so we can be sure to emit subsequent instructions 1013 // after them. 1014 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1015 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 1016 else 1017 FastIS->setLastLocalValue(0); 1018 } 1019 1020 unsigned NumFastIselRemaining = std::distance(Begin, End); 1021 // Do FastISel on as many instructions as possible. 1022 for (; BI != Begin; --BI) { 1023 const Instruction *Inst = llvm::prior(BI); 1024 1025 // If we no longer require this instruction, skip it. 1026 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1027 --NumFastIselRemaining; 1028 continue; 1029 } 1030 1031 // Bottom-up: reset the insert pos at the top, after any local-value 1032 // instructions. 1033 FastIS->recomputeInsertPt(); 1034 1035 // Try to select the instruction with FastISel. 1036 if (FastIS->SelectInstruction(Inst)) { 1037 --NumFastIselRemaining; 1038 ++NumFastIselSuccess; 1039 // If fast isel succeeded, skip over all the folded instructions, and 1040 // then see if there is a load right before the selected instructions. 1041 // Try to fold the load if so. 1042 const Instruction *BeforeInst = Inst; 1043 while (BeforeInst != Begin) { 1044 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 1045 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1046 break; 1047 } 1048 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1049 BeforeInst->hasOneUse() && 1050 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) { 1051 // If we succeeded, don't re-select the load. 1052 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 1053 --NumFastIselRemaining; 1054 ++NumFastIselSuccess; 1055 } 1056 continue; 1057 } 1058 1059#ifndef NDEBUG 1060 if (EnableFastISelVerbose2) 1061 collectFailStats(Inst); 1062#endif 1063 1064 // Then handle certain instructions as single-LLVM-Instruction blocks. 1065 if (isa<CallInst>(Inst)) { 1066 1067 if (EnableFastISelVerbose || EnableFastISelAbort) { 1068 dbgs() << "FastISel missed call: "; 1069 Inst->dump(); 1070 } 1071 1072 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1073 unsigned &R = FuncInfo->ValueMap[Inst]; 1074 if (!R) 1075 R = FuncInfo->CreateRegs(Inst->getType()); 1076 } 1077 1078 bool HadTailCall = false; 1079 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1080 SelectBasicBlock(Inst, BI, HadTailCall); 1081 1082 // If the call was emitted as a tail call, we're done with the block. 1083 // We also need to delete any previously emitted instructions. 1084 if (HadTailCall) { 1085 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1086 --BI; 1087 break; 1088 } 1089 1090 // Recompute NumFastIselRemaining as Selection DAG instruction 1091 // selection may have handled the call, input args, etc. 1092 unsigned RemainingNow = std::distance(Begin, BI); 1093 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1094 NumFastIselRemaining = RemainingNow; 1095 continue; 1096 } 1097 1098 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1099 // Don't abort, and use a different message for terminator misses. 1100 NumFastIselFailures += NumFastIselRemaining; 1101 if (EnableFastISelVerbose || EnableFastISelAbort) { 1102 dbgs() << "FastISel missed terminator: "; 1103 Inst->dump(); 1104 } 1105 } else { 1106 NumFastIselFailures += NumFastIselRemaining; 1107 if (EnableFastISelVerbose || EnableFastISelAbort) { 1108 dbgs() << "FastISel miss: "; 1109 Inst->dump(); 1110 } 1111 if (EnableFastISelAbort) 1112 // The "fast" selector couldn't handle something and bailed. 1113 // For the purpose of debugging, just abort. 1114 llvm_unreachable("FastISel didn't select the entire block"); 1115 } 1116 break; 1117 } 1118 1119 FastIS->recomputeInsertPt(); 1120 } else { 1121 // Lower any arguments needed in this block if this is the entry block. 1122 if (LLVMBB == &Fn.getEntryBlock()) { 1123 ++NumEntryBlocks; 1124 LowerArguments(Fn); 1125 } 1126 } 1127 1128 if (Begin != BI) 1129 ++NumDAGBlocks; 1130 else 1131 ++NumFastIselBlocks; 1132 1133 if (Begin != BI) { 1134 // Run SelectionDAG instruction selection on the remainder of the block 1135 // not handled by FastISel. If FastISel is not run, this is the entire 1136 // block. 1137 bool HadTailCall; 1138 SelectBasicBlock(Begin, BI, HadTailCall); 1139 } 1140 1141 FinishBasicBlock(); 1142 FuncInfo->PHINodesToUpdate.clear(); 1143 } 1144 1145 delete FastIS; 1146 SDB->clearDanglingDebugInfo(); 1147 SDB->SPDescriptor.resetPerFunctionState(); 1148} 1149 1150/// Find the split point at which to splice the end of BB into its success stack 1151/// protector check machine basic block. 1152static MachineBasicBlock::iterator 1153FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) { 1154 MachineFunction *MF = BB->getParent(); 1155 MachineRegisterInfo &MRI = MF->getRegInfo(); 1156 const TargetMachine &TM = MF->getTarget(); 1157 const TargetInstrInfo *TII = TM.getInstrInfo(); 1158 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); 1159 1160 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator(); 1161 if (SplitPoint == BB->begin()) 1162 return SplitPoint; 1163 1164 MachineBasicBlock::iterator Start = BB->begin(); 1165 MachineBasicBlock::iterator Previous = SplitPoint; 1166 --Previous; 1167 1168 while (Previous->isCopy() || Previous->isImplicitDef()) { 1169 MachineInstr::mop_iterator OPI = Previous->operands_begin(); 1170 1171 if (!OPI->isReg() || !OPI->isDef() || 1172 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) && 1173 !Previous->isImplicitDef())) 1174 break; 1175 1176 SplitPoint = Previous; 1177 if (Previous == Start) 1178 break; 1179 --Previous; 1180 } 1181 1182 return SplitPoint; 1183} 1184 1185void 1186SelectionDAGISel::FinishBasicBlock() { 1187 1188 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1189 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1190 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1191 dbgs() << "Node " << i << " : (" 1192 << FuncInfo->PHINodesToUpdate[i].first 1193 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1194 1195 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() && 1196 SDB->JTCases.empty() && 1197 SDB->BitTestCases.empty(); 1198 1199 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1200 // PHI nodes in successors. 1201 if (MustUpdatePHINodes) { 1202 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1203 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1204 assert(PHI->isPHI() && 1205 "This is not a machine PHI node that we are updating!"); 1206 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1207 continue; 1208 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1209 } 1210 } 1211 1212 // Handle stack protector. 1213 if (SDB->SPDescriptor.shouldEmitStackProtector()) { 1214 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB(); 1215 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB(); 1216 1217 // Find the split point to split the parent mbb. At the same time copy all 1218 // physical registers used in the tail of parent mbb into virtual registers 1219 // before the split point and back into physical registers after the split 1220 // point. This prevents us needing to deal with Live-ins and many other 1221 // register allocation issues caused by us splitting the parent mbb. The 1222 // register allocator will clean up said virtual copies later on. 1223 MachineBasicBlock::iterator SplitPoint = 1224 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc()); 1225 1226 // Splice the terminator of ParentMBB into SuccessMBB. 1227 SuccessMBB->splice(SuccessMBB->end(), ParentMBB, 1228 SplitPoint, 1229 ParentMBB->end()); 1230 1231 // Add compare/jump on neq/jump to the parent BB. 1232 FuncInfo->MBB = ParentMBB; 1233 FuncInfo->InsertPt = ParentMBB->end(); 1234 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB); 1235 CurDAG->setRoot(SDB->getRoot()); 1236 SDB->clear(); 1237 CodeGenAndEmitDAG(); 1238 1239 // CodeGen Failure MBB if we have not codegened it yet. 1240 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB(); 1241 if (!FailureMBB->size()) { 1242 FuncInfo->MBB = FailureMBB; 1243 FuncInfo->InsertPt = FailureMBB->end(); 1244 SDB->visitSPDescriptorFailure(SDB->SPDescriptor); 1245 CurDAG->setRoot(SDB->getRoot()); 1246 SDB->clear(); 1247 CodeGenAndEmitDAG(); 1248 } 1249 1250 // Clear the Per-BB State. 1251 SDB->SPDescriptor.resetPerBBState(); 1252 } 1253 1254 // If we updated PHI Nodes, return early. 1255 if (MustUpdatePHINodes) 1256 return; 1257 1258 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1259 // Lower header first, if it wasn't already lowered 1260 if (!SDB->BitTestCases[i].Emitted) { 1261 // Set the current basic block to the mbb we wish to insert the code into 1262 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1263 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1264 // Emit the code 1265 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1266 CurDAG->setRoot(SDB->getRoot()); 1267 SDB->clear(); 1268 CodeGenAndEmitDAG(); 1269 } 1270 1271 uint32_t UnhandledWeight = 0; 1272 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1273 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1274 1275 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1276 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1277 // Set the current basic block to the mbb we wish to insert the code into 1278 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1279 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1280 // Emit the code 1281 if (j+1 != ej) 1282 SDB->visitBitTestCase(SDB->BitTestCases[i], 1283 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1284 UnhandledWeight, 1285 SDB->BitTestCases[i].Reg, 1286 SDB->BitTestCases[i].Cases[j], 1287 FuncInfo->MBB); 1288 else 1289 SDB->visitBitTestCase(SDB->BitTestCases[i], 1290 SDB->BitTestCases[i].Default, 1291 UnhandledWeight, 1292 SDB->BitTestCases[i].Reg, 1293 SDB->BitTestCases[i].Cases[j], 1294 FuncInfo->MBB); 1295 1296 1297 CurDAG->setRoot(SDB->getRoot()); 1298 SDB->clear(); 1299 CodeGenAndEmitDAG(); 1300 } 1301 1302 // Update PHI Nodes 1303 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1304 pi != pe; ++pi) { 1305 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1306 MachineBasicBlock *PHIBB = PHI->getParent(); 1307 assert(PHI->isPHI() && 1308 "This is not a machine PHI node that we are updating!"); 1309 // This is "default" BB. We have two jumps to it. From "header" BB and 1310 // from last "case" BB. 1311 if (PHIBB == SDB->BitTestCases[i].Default) 1312 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1313 .addMBB(SDB->BitTestCases[i].Parent) 1314 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1315 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1316 // One of "cases" BB. 1317 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1318 j != ej; ++j) { 1319 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1320 if (cBB->isSuccessor(PHIBB)) 1321 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1322 } 1323 } 1324 } 1325 SDB->BitTestCases.clear(); 1326 1327 // If the JumpTable record is filled in, then we need to emit a jump table. 1328 // Updating the PHI nodes is tricky in this case, since we need to determine 1329 // whether the PHI is a successor of the range check MBB or the jump table MBB 1330 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1331 // Lower header first, if it wasn't already lowered 1332 if (!SDB->JTCases[i].first.Emitted) { 1333 // Set the current basic block to the mbb we wish to insert the code into 1334 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1335 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1336 // Emit the code 1337 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1338 FuncInfo->MBB); 1339 CurDAG->setRoot(SDB->getRoot()); 1340 SDB->clear(); 1341 CodeGenAndEmitDAG(); 1342 } 1343 1344 // Set the current basic block to the mbb we wish to insert the code into 1345 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1346 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1347 // Emit the code 1348 SDB->visitJumpTable(SDB->JTCases[i].second); 1349 CurDAG->setRoot(SDB->getRoot()); 1350 SDB->clear(); 1351 CodeGenAndEmitDAG(); 1352 1353 // Update PHI Nodes 1354 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1355 pi != pe; ++pi) { 1356 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1357 MachineBasicBlock *PHIBB = PHI->getParent(); 1358 assert(PHI->isPHI() && 1359 "This is not a machine PHI node that we are updating!"); 1360 // "default" BB. We can go there only from header BB. 1361 if (PHIBB == SDB->JTCases[i].second.Default) 1362 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1363 .addMBB(SDB->JTCases[i].first.HeaderBB); 1364 // JT BB. Just iterate over successors here 1365 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1366 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1367 } 1368 } 1369 SDB->JTCases.clear(); 1370 1371 // If the switch block involved a branch to one of the actual successors, we 1372 // need to update PHI nodes in that block. 1373 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1374 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1375 assert(PHI->isPHI() && 1376 "This is not a machine PHI node that we are updating!"); 1377 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 1378 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1379 } 1380 1381 // If we generated any switch lowering information, build and codegen any 1382 // additional DAGs necessary. 1383 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1384 // Set the current basic block to the mbb we wish to insert the code into 1385 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1386 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1387 1388 // Determine the unique successors. 1389 SmallVector<MachineBasicBlock *, 2> Succs; 1390 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1391 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1392 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1393 1394 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1395 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1396 CurDAG->setRoot(SDB->getRoot()); 1397 SDB->clear(); 1398 CodeGenAndEmitDAG(); 1399 1400 // Remember the last block, now that any splitting is done, for use in 1401 // populating PHI nodes in successors. 1402 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1403 1404 // Handle any PHI nodes in successors of this chunk, as if we were coming 1405 // from the original BB before switch expansion. Note that PHI nodes can 1406 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1407 // handle them the right number of times. 1408 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1409 FuncInfo->MBB = Succs[i]; 1410 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1411 // FuncInfo->MBB may have been removed from the CFG if a branch was 1412 // constant folded. 1413 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1414 for (MachineBasicBlock::iterator 1415 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1416 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1417 MachineInstrBuilder PHI(*MF, MBBI); 1418 // This value for this PHI node is recorded in PHINodesToUpdate. 1419 for (unsigned pn = 0; ; ++pn) { 1420 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1421 "Didn't find PHI entry!"); 1422 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1423 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1424 break; 1425 } 1426 } 1427 } 1428 } 1429 } 1430 } 1431 SDB->SwitchCases.clear(); 1432} 1433 1434 1435/// Create the scheduler. If a specific scheduler was specified 1436/// via the SchedulerRegistry, use it, otherwise select the 1437/// one preferred by the target. 1438/// 1439ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1440 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1441 1442 if (!Ctor) { 1443 Ctor = ISHeuristic; 1444 RegisterScheduler::setDefault(Ctor); 1445 } 1446 1447 return Ctor(this, OptLevel); 1448} 1449 1450//===----------------------------------------------------------------------===// 1451// Helper functions used by the generated instruction selector. 1452//===----------------------------------------------------------------------===// 1453// Calls to these methods are generated by tblgen. 1454 1455/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1456/// the dag combiner simplified the 255, we still want to match. RHS is the 1457/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1458/// specified in the .td file (e.g. 255). 1459bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1460 int64_t DesiredMaskS) const { 1461 const APInt &ActualMask = RHS->getAPIntValue(); 1462 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1463 1464 // If the actual mask exactly matches, success! 1465 if (ActualMask == DesiredMask) 1466 return true; 1467 1468 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1469 if (ActualMask.intersects(~DesiredMask)) 1470 return false; 1471 1472 // Otherwise, the DAG Combiner may have proven that the value coming in is 1473 // either already zero or is not demanded. Check for known zero input bits. 1474 APInt NeededMask = DesiredMask & ~ActualMask; 1475 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1476 return true; 1477 1478 // TODO: check to see if missing bits are just not demanded. 1479 1480 // Otherwise, this pattern doesn't match. 1481 return false; 1482} 1483 1484/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1485/// the dag combiner simplified the 255, we still want to match. RHS is the 1486/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1487/// specified in the .td file (e.g. 255). 1488bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1489 int64_t DesiredMaskS) const { 1490 const APInt &ActualMask = RHS->getAPIntValue(); 1491 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1492 1493 // If the actual mask exactly matches, success! 1494 if (ActualMask == DesiredMask) 1495 return true; 1496 1497 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1498 if (ActualMask.intersects(~DesiredMask)) 1499 return false; 1500 1501 // Otherwise, the DAG Combiner may have proven that the value coming in is 1502 // either already zero or is not demanded. Check for known zero input bits. 1503 APInt NeededMask = DesiredMask & ~ActualMask; 1504 1505 APInt KnownZero, KnownOne; 1506 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 1507 1508 // If all the missing bits in the or are already known to be set, match! 1509 if ((NeededMask & KnownOne) == NeededMask) 1510 return true; 1511 1512 // TODO: check to see if missing bits are just not demanded. 1513 1514 // Otherwise, this pattern doesn't match. 1515 return false; 1516} 1517 1518 1519/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1520/// by tblgen. Others should not call it. 1521void SelectionDAGISel:: 1522SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1523 std::vector<SDValue> InOps; 1524 std::swap(InOps, Ops); 1525 1526 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1527 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1528 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1529 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1530 1531 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1532 if (InOps[e-1].getValueType() == MVT::Glue) 1533 --e; // Don't process a glue operand if it is here. 1534 1535 while (i != e) { 1536 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1537 if (!InlineAsm::isMemKind(Flags)) { 1538 // Just skip over this operand, copying the operands verbatim. 1539 Ops.insert(Ops.end(), InOps.begin()+i, 1540 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1541 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1542 } else { 1543 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1544 "Memory operand with multiple values?"); 1545 // Otherwise, this is a memory operand. Ask the target to select it. 1546 std::vector<SDValue> SelOps; 1547 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1548 report_fatal_error("Could not match memory address. Inline asm" 1549 " failure!"); 1550 1551 // Add this to the output node. 1552 unsigned NewFlags = 1553 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1554 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1555 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1556 i += 2; 1557 } 1558 } 1559 1560 // Add the glue input back if present. 1561 if (e != InOps.size()) 1562 Ops.push_back(InOps.back()); 1563} 1564 1565/// findGlueUse - Return use of MVT::Glue value produced by the specified 1566/// SDNode. 1567/// 1568static SDNode *findGlueUse(SDNode *N) { 1569 unsigned FlagResNo = N->getNumValues()-1; 1570 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1571 SDUse &Use = I.getUse(); 1572 if (Use.getResNo() == FlagResNo) 1573 return Use.getUser(); 1574 } 1575 return NULL; 1576} 1577 1578/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1579/// This function recursively traverses up the operand chain, ignoring 1580/// certain nodes. 1581static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1582 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1583 bool IgnoreChains) { 1584 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1585 // greater than all of its (recursive) operands. If we scan to a point where 1586 // 'use' is smaller than the node we're scanning for, then we know we will 1587 // never find it. 1588 // 1589 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1590 // happen because we scan down to newly selected nodes in the case of glue 1591 // uses. 1592 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1593 return false; 1594 1595 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1596 // won't fail if we scan it again. 1597 if (!Visited.insert(Use)) 1598 return false; 1599 1600 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1601 // Ignore chain uses, they are validated by HandleMergeInputChains. 1602 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1603 continue; 1604 1605 SDNode *N = Use->getOperand(i).getNode(); 1606 if (N == Def) { 1607 if (Use == ImmedUse || Use == Root) 1608 continue; // We are not looking for immediate use. 1609 assert(N != Root); 1610 return true; 1611 } 1612 1613 // Traverse up the operand chain. 1614 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1615 return true; 1616 } 1617 return false; 1618} 1619 1620/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1621/// operand node N of U during instruction selection that starts at Root. 1622bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1623 SDNode *Root) const { 1624 if (OptLevel == CodeGenOpt::None) return false; 1625 return N.hasOneUse(); 1626} 1627 1628/// IsLegalToFold - Returns true if the specific operand node N of 1629/// U can be folded during instruction selection that starts at Root. 1630bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1631 CodeGenOpt::Level OptLevel, 1632 bool IgnoreChains) { 1633 if (OptLevel == CodeGenOpt::None) return false; 1634 1635 // If Root use can somehow reach N through a path that that doesn't contain 1636 // U then folding N would create a cycle. e.g. In the following 1637 // diagram, Root can reach N through X. If N is folded into into Root, then 1638 // X is both a predecessor and a successor of U. 1639 // 1640 // [N*] // 1641 // ^ ^ // 1642 // / \ // 1643 // [U*] [X]? // 1644 // ^ ^ // 1645 // \ / // 1646 // \ / // 1647 // [Root*] // 1648 // 1649 // * indicates nodes to be folded together. 1650 // 1651 // If Root produces glue, then it gets (even more) interesting. Since it 1652 // will be "glued" together with its glue use in the scheduler, we need to 1653 // check if it might reach N. 1654 // 1655 // [N*] // 1656 // ^ ^ // 1657 // / \ // 1658 // [U*] [X]? // 1659 // ^ ^ // 1660 // \ \ // 1661 // \ | // 1662 // [Root*] | // 1663 // ^ | // 1664 // f | // 1665 // | / // 1666 // [Y] / // 1667 // ^ / // 1668 // f / // 1669 // | / // 1670 // [GU] // 1671 // 1672 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1673 // (call it Fold), then X is a predecessor of GU and a successor of 1674 // Fold. But since Fold and GU are glued together, this will create 1675 // a cycle in the scheduling graph. 1676 1677 // If the node has glue, walk down the graph to the "lowest" node in the 1678 // glueged set. 1679 EVT VT = Root->getValueType(Root->getNumValues()-1); 1680 while (VT == MVT::Glue) { 1681 SDNode *GU = findGlueUse(Root); 1682 if (GU == NULL) 1683 break; 1684 Root = GU; 1685 VT = Root->getValueType(Root->getNumValues()-1); 1686 1687 // If our query node has a glue result with a use, we've walked up it. If 1688 // the user (which has already been selected) has a chain or indirectly uses 1689 // the chain, our WalkChainUsers predicate will not consider it. Because of 1690 // this, we cannot ignore chains in this predicate. 1691 IgnoreChains = false; 1692 } 1693 1694 1695 SmallPtrSet<SDNode*, 16> Visited; 1696 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1697} 1698 1699SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1700 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1701 SelectInlineAsmMemoryOperands(Ops); 1702 1703 EVT VTs[] = { MVT::Other, MVT::Glue }; 1704 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), 1705 VTs, &Ops[0], Ops.size()); 1706 New->setNodeId(-1); 1707 return New.getNode(); 1708} 1709 1710SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1711 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1712} 1713 1714/// GetVBR - decode a vbr encoding whose top bit is set. 1715LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1716GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1717 assert(Val >= 128 && "Not a VBR"); 1718 Val &= 127; // Remove first vbr bit. 1719 1720 unsigned Shift = 7; 1721 uint64_t NextBits; 1722 do { 1723 NextBits = MatcherTable[Idx++]; 1724 Val |= (NextBits&127) << Shift; 1725 Shift += 7; 1726 } while (NextBits & 128); 1727 1728 return Val; 1729} 1730 1731 1732/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1733/// interior glue and chain results to use the new glue and chain results. 1734void SelectionDAGISel:: 1735UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1736 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1737 SDValue InputGlue, 1738 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1739 bool isMorphNodeTo) { 1740 SmallVector<SDNode*, 4> NowDeadNodes; 1741 1742 // Now that all the normal results are replaced, we replace the chain and 1743 // glue results if present. 1744 if (!ChainNodesMatched.empty()) { 1745 assert(InputChain.getNode() != 0 && 1746 "Matched input chains but didn't produce a chain"); 1747 // Loop over all of the nodes we matched that produced a chain result. 1748 // Replace all the chain results with the final chain we ended up with. 1749 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1750 SDNode *ChainNode = ChainNodesMatched[i]; 1751 1752 // If this node was already deleted, don't look at it. 1753 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1754 continue; 1755 1756 // Don't replace the results of the root node if we're doing a 1757 // MorphNodeTo. 1758 if (ChainNode == NodeToMatch && isMorphNodeTo) 1759 continue; 1760 1761 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1762 if (ChainVal.getValueType() == MVT::Glue) 1763 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1764 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1765 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1766 1767 // If the node became dead and we haven't already seen it, delete it. 1768 if (ChainNode->use_empty() && 1769 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1770 NowDeadNodes.push_back(ChainNode); 1771 } 1772 } 1773 1774 // If the result produces glue, update any glue results in the matched 1775 // pattern with the glue result. 1776 if (InputGlue.getNode() != 0) { 1777 // Handle any interior nodes explicitly marked. 1778 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1779 SDNode *FRN = GlueResultNodesMatched[i]; 1780 1781 // If this node was already deleted, don't look at it. 1782 if (FRN->getOpcode() == ISD::DELETED_NODE) 1783 continue; 1784 1785 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1786 "Doesn't have a glue result"); 1787 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1788 InputGlue); 1789 1790 // If the node became dead and we haven't already seen it, delete it. 1791 if (FRN->use_empty() && 1792 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1793 NowDeadNodes.push_back(FRN); 1794 } 1795 } 1796 1797 if (!NowDeadNodes.empty()) 1798 CurDAG->RemoveDeadNodes(NowDeadNodes); 1799 1800 DEBUG(dbgs() << "ISEL: Match complete!\n"); 1801} 1802 1803enum ChainResult { 1804 CR_Simple, 1805 CR_InducesCycle, 1806 CR_LeadsToInteriorNode 1807}; 1808 1809/// WalkChainUsers - Walk down the users of the specified chained node that is 1810/// part of the pattern we're matching, looking at all of the users we find. 1811/// This determines whether something is an interior node, whether we have a 1812/// non-pattern node in between two pattern nodes (which prevent folding because 1813/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1814/// between pattern nodes (in which case the TF becomes part of the pattern). 1815/// 1816/// The walk we do here is guaranteed to be small because we quickly get down to 1817/// already selected nodes "below" us. 1818static ChainResult 1819WalkChainUsers(const SDNode *ChainedNode, 1820 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1821 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1822 ChainResult Result = CR_Simple; 1823 1824 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1825 E = ChainedNode->use_end(); UI != E; ++UI) { 1826 // Make sure the use is of the chain, not some other value we produce. 1827 if (UI.getUse().getValueType() != MVT::Other) continue; 1828 1829 SDNode *User = *UI; 1830 1831 // If we see an already-selected machine node, then we've gone beyond the 1832 // pattern that we're selecting down into the already selected chunk of the 1833 // DAG. 1834 if (User->isMachineOpcode() || 1835 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1836 continue; 1837 1838 unsigned UserOpcode = User->getOpcode(); 1839 if (UserOpcode == ISD::CopyToReg || 1840 UserOpcode == ISD::CopyFromReg || 1841 UserOpcode == ISD::INLINEASM || 1842 UserOpcode == ISD::EH_LABEL || 1843 UserOpcode == ISD::LIFETIME_START || 1844 UserOpcode == ISD::LIFETIME_END) { 1845 // If their node ID got reset to -1 then they've already been selected. 1846 // Treat them like a MachineOpcode. 1847 if (User->getNodeId() == -1) 1848 continue; 1849 } 1850 1851 // If we have a TokenFactor, we handle it specially. 1852 if (User->getOpcode() != ISD::TokenFactor) { 1853 // If the node isn't a token factor and isn't part of our pattern, then it 1854 // must be a random chained node in between two nodes we're selecting. 1855 // This happens when we have something like: 1856 // x = load ptr 1857 // call 1858 // y = x+4 1859 // store y -> ptr 1860 // Because we structurally match the load/store as a read/modify/write, 1861 // but the call is chained between them. We cannot fold in this case 1862 // because it would induce a cycle in the graph. 1863 if (!std::count(ChainedNodesInPattern.begin(), 1864 ChainedNodesInPattern.end(), User)) 1865 return CR_InducesCycle; 1866 1867 // Otherwise we found a node that is part of our pattern. For example in: 1868 // x = load ptr 1869 // y = x+4 1870 // store y -> ptr 1871 // This would happen when we're scanning down from the load and see the 1872 // store as a user. Record that there is a use of ChainedNode that is 1873 // part of the pattern and keep scanning uses. 1874 Result = CR_LeadsToInteriorNode; 1875 InteriorChainedNodes.push_back(User); 1876 continue; 1877 } 1878 1879 // If we found a TokenFactor, there are two cases to consider: first if the 1880 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1881 // uses of the TF are in our pattern) we just want to ignore it. Second, 1882 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1883 // [Load chain] 1884 // ^ 1885 // | 1886 // [Load] 1887 // ^ ^ 1888 // | \ DAG's like cheese 1889 // / \ do you? 1890 // / | 1891 // [TokenFactor] [Op] 1892 // ^ ^ 1893 // | | 1894 // \ / 1895 // \ / 1896 // [Store] 1897 // 1898 // In this case, the TokenFactor becomes part of our match and we rewrite it 1899 // as a new TokenFactor. 1900 // 1901 // To distinguish these two cases, do a recursive walk down the uses. 1902 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1903 case CR_Simple: 1904 // If the uses of the TokenFactor are just already-selected nodes, ignore 1905 // it, it is "below" our pattern. 1906 continue; 1907 case CR_InducesCycle: 1908 // If the uses of the TokenFactor lead to nodes that are not part of our 1909 // pattern that are not selected, folding would turn this into a cycle, 1910 // bail out now. 1911 return CR_InducesCycle; 1912 case CR_LeadsToInteriorNode: 1913 break; // Otherwise, keep processing. 1914 } 1915 1916 // Okay, we know we're in the interesting interior case. The TokenFactor 1917 // is now going to be considered part of the pattern so that we rewrite its 1918 // uses (it may have uses that are not part of the pattern) with the 1919 // ultimate chain result of the generated code. We will also add its chain 1920 // inputs as inputs to the ultimate TokenFactor we create. 1921 Result = CR_LeadsToInteriorNode; 1922 ChainedNodesInPattern.push_back(User); 1923 InteriorChainedNodes.push_back(User); 1924 continue; 1925 } 1926 1927 return Result; 1928} 1929 1930/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1931/// operation for when the pattern matched at least one node with a chains. The 1932/// input vector contains a list of all of the chained nodes that we match. We 1933/// must determine if this is a valid thing to cover (i.e. matching it won't 1934/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1935/// be used as the input node chain for the generated nodes. 1936static SDValue 1937HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1938 SelectionDAG *CurDAG) { 1939 // Walk all of the chained nodes we've matched, recursively scanning down the 1940 // users of the chain result. This adds any TokenFactor nodes that are caught 1941 // in between chained nodes to the chained and interior nodes list. 1942 SmallVector<SDNode*, 3> InteriorChainedNodes; 1943 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1944 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1945 InteriorChainedNodes) == CR_InducesCycle) 1946 return SDValue(); // Would induce a cycle. 1947 } 1948 1949 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1950 // that we are interested in. Form our input TokenFactor node. 1951 SmallVector<SDValue, 3> InputChains; 1952 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1953 // Add the input chain of this node to the InputChains list (which will be 1954 // the operands of the generated TokenFactor) if it's not an interior node. 1955 SDNode *N = ChainNodesMatched[i]; 1956 if (N->getOpcode() != ISD::TokenFactor) { 1957 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1958 continue; 1959 1960 // Otherwise, add the input chain. 1961 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1962 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1963 InputChains.push_back(InChain); 1964 continue; 1965 } 1966 1967 // If we have a token factor, we want to add all inputs of the token factor 1968 // that are not part of the pattern we're matching. 1969 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1970 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1971 N->getOperand(op).getNode())) 1972 InputChains.push_back(N->getOperand(op)); 1973 } 1974 } 1975 1976 SDValue Res; 1977 if (InputChains.size() == 1) 1978 return InputChains[0]; 1979 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]), 1980 MVT::Other, &InputChains[0], InputChains.size()); 1981} 1982 1983/// MorphNode - Handle morphing a node in place for the selector. 1984SDNode *SelectionDAGISel:: 1985MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1986 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1987 // It is possible we're using MorphNodeTo to replace a node with no 1988 // normal results with one that has a normal result (or we could be 1989 // adding a chain) and the input could have glue and chains as well. 1990 // In this case we need to shift the operands down. 1991 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1992 // than the old isel though. 1993 int OldGlueResultNo = -1, OldChainResultNo = -1; 1994 1995 unsigned NTMNumResults = Node->getNumValues(); 1996 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 1997 OldGlueResultNo = NTMNumResults-1; 1998 if (NTMNumResults != 1 && 1999 Node->getValueType(NTMNumResults-2) == MVT::Other) 2000 OldChainResultNo = NTMNumResults-2; 2001 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 2002 OldChainResultNo = NTMNumResults-1; 2003 2004 // Call the underlying SelectionDAG routine to do the transmogrification. Note 2005 // that this deletes operands of the old node that become dead. 2006 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 2007 2008 // MorphNodeTo can operate in two ways: if an existing node with the 2009 // specified operands exists, it can just return it. Otherwise, it 2010 // updates the node in place to have the requested operands. 2011 if (Res == Node) { 2012 // If we updated the node in place, reset the node ID. To the isel, 2013 // this should be just like a newly allocated machine node. 2014 Res->setNodeId(-1); 2015 } 2016 2017 unsigned ResNumResults = Res->getNumValues(); 2018 // Move the glue if needed. 2019 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 2020 (unsigned)OldGlueResultNo != ResNumResults-1) 2021 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 2022 SDValue(Res, ResNumResults-1)); 2023 2024 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 2025 --ResNumResults; 2026 2027 // Move the chain reference if needed. 2028 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 2029 (unsigned)OldChainResultNo != ResNumResults-1) 2030 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 2031 SDValue(Res, ResNumResults-1)); 2032 2033 // Otherwise, no replacement happened because the node already exists. Replace 2034 // Uses of the old node with the new one. 2035 if (Res != Node) 2036 CurDAG->ReplaceAllUsesWith(Node, Res); 2037 2038 return Res; 2039} 2040 2041/// CheckSame - Implements OP_CheckSame. 2042LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2043CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2044 SDValue N, 2045 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2046 // Accept if it is exactly the same as a previously recorded node. 2047 unsigned RecNo = MatcherTable[MatcherIndex++]; 2048 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2049 return N == RecordedNodes[RecNo].first; 2050} 2051 2052/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2053LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2054CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2055 const SelectionDAGISel &SDISel) { 2056 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 2057} 2058 2059/// CheckNodePredicate - Implements OP_CheckNodePredicate. 2060LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2061CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2062 const SelectionDAGISel &SDISel, SDNode *N) { 2063 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2064} 2065 2066LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2067CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2068 SDNode *N) { 2069 uint16_t Opc = MatcherTable[MatcherIndex++]; 2070 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2071 return N->getOpcode() == Opc; 2072} 2073 2074LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2075CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2076 SDValue N, const TargetLowering *TLI) { 2077 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2078 if (N.getValueType() == VT) return true; 2079 2080 // Handle the case when VT is iPTR. 2081 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(); 2082} 2083 2084LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2085CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2086 SDValue N, const TargetLowering *TLI, 2087 unsigned ChildNo) { 2088 if (ChildNo >= N.getNumOperands()) 2089 return false; // Match fails if out of range child #. 2090 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2091} 2092 2093LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2094CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2095 SDValue N) { 2096 return cast<CondCodeSDNode>(N)->get() == 2097 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2098} 2099 2100LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2101CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2102 SDValue N, const TargetLowering *TLI) { 2103 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2104 if (cast<VTSDNode>(N)->getVT() == VT) 2105 return true; 2106 2107 // Handle the case when VT is iPTR. 2108 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(); 2109} 2110 2111LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2112CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2113 SDValue N) { 2114 int64_t Val = MatcherTable[MatcherIndex++]; 2115 if (Val & 128) 2116 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2117 2118 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2119 return C != 0 && C->getSExtValue() == Val; 2120} 2121 2122LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2123CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2124 SDValue N, const SelectionDAGISel &SDISel) { 2125 int64_t Val = MatcherTable[MatcherIndex++]; 2126 if (Val & 128) 2127 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2128 2129 if (N->getOpcode() != ISD::AND) return false; 2130 2131 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2132 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2133} 2134 2135LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2136CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2137 SDValue N, const SelectionDAGISel &SDISel) { 2138 int64_t Val = MatcherTable[MatcherIndex++]; 2139 if (Val & 128) 2140 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2141 2142 if (N->getOpcode() != ISD::OR) return false; 2143 2144 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2145 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2146} 2147 2148/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2149/// scope, evaluate the current node. If the current predicate is known to 2150/// fail, set Result=true and return anything. If the current predicate is 2151/// known to pass, set Result=false and return the MatcherIndex to continue 2152/// with. If the current predicate is unknown, set Result=false and return the 2153/// MatcherIndex to continue with. 2154static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2155 unsigned Index, SDValue N, 2156 bool &Result, 2157 const SelectionDAGISel &SDISel, 2158 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2159 switch (Table[Index++]) { 2160 default: 2161 Result = false; 2162 return Index-1; // Could not evaluate this predicate. 2163 case SelectionDAGISel::OPC_CheckSame: 2164 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2165 return Index; 2166 case SelectionDAGISel::OPC_CheckPatternPredicate: 2167 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2168 return Index; 2169 case SelectionDAGISel::OPC_CheckPredicate: 2170 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2171 return Index; 2172 case SelectionDAGISel::OPC_CheckOpcode: 2173 Result = !::CheckOpcode(Table, Index, N.getNode()); 2174 return Index; 2175 case SelectionDAGISel::OPC_CheckType: 2176 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering()); 2177 return Index; 2178 case SelectionDAGISel::OPC_CheckChild0Type: 2179 case SelectionDAGISel::OPC_CheckChild1Type: 2180 case SelectionDAGISel::OPC_CheckChild2Type: 2181 case SelectionDAGISel::OPC_CheckChild3Type: 2182 case SelectionDAGISel::OPC_CheckChild4Type: 2183 case SelectionDAGISel::OPC_CheckChild5Type: 2184 case SelectionDAGISel::OPC_CheckChild6Type: 2185 case SelectionDAGISel::OPC_CheckChild7Type: 2186 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(), 2187 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2188 return Index; 2189 case SelectionDAGISel::OPC_CheckCondCode: 2190 Result = !::CheckCondCode(Table, Index, N); 2191 return Index; 2192 case SelectionDAGISel::OPC_CheckValueType: 2193 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering()); 2194 return Index; 2195 case SelectionDAGISel::OPC_CheckInteger: 2196 Result = !::CheckInteger(Table, Index, N); 2197 return Index; 2198 case SelectionDAGISel::OPC_CheckAndImm: 2199 Result = !::CheckAndImm(Table, Index, N, SDISel); 2200 return Index; 2201 case SelectionDAGISel::OPC_CheckOrImm: 2202 Result = !::CheckOrImm(Table, Index, N, SDISel); 2203 return Index; 2204 } 2205} 2206 2207namespace { 2208 2209struct MatchScope { 2210 /// FailIndex - If this match fails, this is the index to continue with. 2211 unsigned FailIndex; 2212 2213 /// NodeStack - The node stack when the scope was formed. 2214 SmallVector<SDValue, 4> NodeStack; 2215 2216 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2217 unsigned NumRecordedNodes; 2218 2219 /// NumMatchedMemRefs - The number of matched memref entries. 2220 unsigned NumMatchedMemRefs; 2221 2222 /// InputChain/InputGlue - The current chain/glue 2223 SDValue InputChain, InputGlue; 2224 2225 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2226 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2227}; 2228 2229} 2230 2231SDNode *SelectionDAGISel:: 2232SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2233 unsigned TableSize) { 2234 // FIXME: Should these even be selected? Handle these cases in the caller? 2235 switch (NodeToMatch->getOpcode()) { 2236 default: 2237 break; 2238 case ISD::EntryToken: // These nodes remain the same. 2239 case ISD::BasicBlock: 2240 case ISD::Register: 2241 case ISD::RegisterMask: 2242 //case ISD::VALUETYPE: 2243 //case ISD::CONDCODE: 2244 case ISD::HANDLENODE: 2245 case ISD::MDNODE_SDNODE: 2246 case ISD::TargetConstant: 2247 case ISD::TargetConstantFP: 2248 case ISD::TargetConstantPool: 2249 case ISD::TargetFrameIndex: 2250 case ISD::TargetExternalSymbol: 2251 case ISD::TargetBlockAddress: 2252 case ISD::TargetJumpTable: 2253 case ISD::TargetGlobalTLSAddress: 2254 case ISD::TargetGlobalAddress: 2255 case ISD::TokenFactor: 2256 case ISD::CopyFromReg: 2257 case ISD::CopyToReg: 2258 case ISD::EH_LABEL: 2259 case ISD::LIFETIME_START: 2260 case ISD::LIFETIME_END: 2261 NodeToMatch->setNodeId(-1); // Mark selected. 2262 return 0; 2263 case ISD::AssertSext: 2264 case ISD::AssertZext: 2265 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2266 NodeToMatch->getOperand(0)); 2267 return 0; 2268 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2269 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2270 } 2271 2272 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2273 2274 // Set up the node stack with NodeToMatch as the only node on the stack. 2275 SmallVector<SDValue, 8> NodeStack; 2276 SDValue N = SDValue(NodeToMatch, 0); 2277 NodeStack.push_back(N); 2278 2279 // MatchScopes - Scopes used when matching, if a match failure happens, this 2280 // indicates where to continue checking. 2281 SmallVector<MatchScope, 8> MatchScopes; 2282 2283 // RecordedNodes - This is the set of nodes that have been recorded by the 2284 // state machine. The second value is the parent of the node, or null if the 2285 // root is recorded. 2286 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2287 2288 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2289 // pattern. 2290 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2291 2292 // These are the current input chain and glue for use when generating nodes. 2293 // Various Emit operations change these. For example, emitting a copytoreg 2294 // uses and updates these. 2295 SDValue InputChain, InputGlue; 2296 2297 // ChainNodesMatched - If a pattern matches nodes that have input/output 2298 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2299 // which ones they are. The result is captured into this list so that we can 2300 // update the chain results when the pattern is complete. 2301 SmallVector<SDNode*, 3> ChainNodesMatched; 2302 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2303 2304 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: "; 2305 NodeToMatch->dump(CurDAG); 2306 dbgs() << '\n'); 2307 2308 // Determine where to start the interpreter. Normally we start at opcode #0, 2309 // but if the state machine starts with an OPC_SwitchOpcode, then we 2310 // accelerate the first lookup (which is guaranteed to be hot) with the 2311 // OpcodeOffset table. 2312 unsigned MatcherIndex = 0; 2313 2314 if (!OpcodeOffset.empty()) { 2315 // Already computed the OpcodeOffset table, just index into it. 2316 if (N.getOpcode() < OpcodeOffset.size()) 2317 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2318 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2319 2320 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2321 // Otherwise, the table isn't computed, but the state machine does start 2322 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2323 // is the first time we're selecting an instruction. 2324 unsigned Idx = 1; 2325 while (1) { 2326 // Get the size of this case. 2327 unsigned CaseSize = MatcherTable[Idx++]; 2328 if (CaseSize & 128) 2329 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2330 if (CaseSize == 0) break; 2331 2332 // Get the opcode, add the index to the table. 2333 uint16_t Opc = MatcherTable[Idx++]; 2334 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2335 if (Opc >= OpcodeOffset.size()) 2336 OpcodeOffset.resize((Opc+1)*2); 2337 OpcodeOffset[Opc] = Idx; 2338 Idx += CaseSize; 2339 } 2340 2341 // Okay, do the lookup for the first opcode. 2342 if (N.getOpcode() < OpcodeOffset.size()) 2343 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2344 } 2345 2346 while (1) { 2347 assert(MatcherIndex < TableSize && "Invalid index"); 2348#ifndef NDEBUG 2349 unsigned CurrentOpcodeIndex = MatcherIndex; 2350#endif 2351 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2352 switch (Opcode) { 2353 case OPC_Scope: { 2354 // Okay, the semantics of this operation are that we should push a scope 2355 // then evaluate the first child. However, pushing a scope only to have 2356 // the first check fail (which then pops it) is inefficient. If we can 2357 // determine immediately that the first check (or first several) will 2358 // immediately fail, don't even bother pushing a scope for them. 2359 unsigned FailIndex; 2360 2361 while (1) { 2362 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2363 if (NumToSkip & 128) 2364 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2365 // Found the end of the scope with no match. 2366 if (NumToSkip == 0) { 2367 FailIndex = 0; 2368 break; 2369 } 2370 2371 FailIndex = MatcherIndex+NumToSkip; 2372 2373 unsigned MatcherIndexOfPredicate = MatcherIndex; 2374 (void)MatcherIndexOfPredicate; // silence warning. 2375 2376 // If we can't evaluate this predicate without pushing a scope (e.g. if 2377 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2378 // push the scope and evaluate the full predicate chain. 2379 bool Result; 2380 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2381 Result, *this, RecordedNodes); 2382 if (!Result) 2383 break; 2384 2385 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at " 2386 << "index " << MatcherIndexOfPredicate 2387 << ", continuing at " << FailIndex << "\n"); 2388 ++NumDAGIselRetries; 2389 2390 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2391 // move to the next case. 2392 MatcherIndex = FailIndex; 2393 } 2394 2395 // If the whole scope failed to match, bail. 2396 if (FailIndex == 0) break; 2397 2398 // Push a MatchScope which indicates where to go if the first child fails 2399 // to match. 2400 MatchScope NewEntry; 2401 NewEntry.FailIndex = FailIndex; 2402 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2403 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2404 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2405 NewEntry.InputChain = InputChain; 2406 NewEntry.InputGlue = InputGlue; 2407 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2408 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2409 MatchScopes.push_back(NewEntry); 2410 continue; 2411 } 2412 case OPC_RecordNode: { 2413 // Remember this node, it may end up being an operand in the pattern. 2414 SDNode *Parent = 0; 2415 if (NodeStack.size() > 1) 2416 Parent = NodeStack[NodeStack.size()-2].getNode(); 2417 RecordedNodes.push_back(std::make_pair(N, Parent)); 2418 continue; 2419 } 2420 2421 case OPC_RecordChild0: case OPC_RecordChild1: 2422 case OPC_RecordChild2: case OPC_RecordChild3: 2423 case OPC_RecordChild4: case OPC_RecordChild5: 2424 case OPC_RecordChild6: case OPC_RecordChild7: { 2425 unsigned ChildNo = Opcode-OPC_RecordChild0; 2426 if (ChildNo >= N.getNumOperands()) 2427 break; // Match fails if out of range child #. 2428 2429 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2430 N.getNode())); 2431 continue; 2432 } 2433 case OPC_RecordMemRef: 2434 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2435 continue; 2436 2437 case OPC_CaptureGlueInput: 2438 // If the current node has an input glue, capture it in InputGlue. 2439 if (N->getNumOperands() != 0 && 2440 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2441 InputGlue = N->getOperand(N->getNumOperands()-1); 2442 continue; 2443 2444 case OPC_MoveChild: { 2445 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2446 if (ChildNo >= N.getNumOperands()) 2447 break; // Match fails if out of range child #. 2448 N = N.getOperand(ChildNo); 2449 NodeStack.push_back(N); 2450 continue; 2451 } 2452 2453 case OPC_MoveParent: 2454 // Pop the current node off the NodeStack. 2455 NodeStack.pop_back(); 2456 assert(!NodeStack.empty() && "Node stack imbalance!"); 2457 N = NodeStack.back(); 2458 continue; 2459 2460 case OPC_CheckSame: 2461 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2462 continue; 2463 case OPC_CheckPatternPredicate: 2464 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2465 continue; 2466 case OPC_CheckPredicate: 2467 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2468 N.getNode())) 2469 break; 2470 continue; 2471 case OPC_CheckComplexPat: { 2472 unsigned CPNum = MatcherTable[MatcherIndex++]; 2473 unsigned RecNo = MatcherTable[MatcherIndex++]; 2474 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2475 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2476 RecordedNodes[RecNo].first, CPNum, 2477 RecordedNodes)) 2478 break; 2479 continue; 2480 } 2481 case OPC_CheckOpcode: 2482 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2483 continue; 2484 2485 case OPC_CheckType: 2486 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2487 break; 2488 continue; 2489 2490 case OPC_SwitchOpcode: { 2491 unsigned CurNodeOpcode = N.getOpcode(); 2492 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2493 unsigned CaseSize; 2494 while (1) { 2495 // Get the size of this case. 2496 CaseSize = MatcherTable[MatcherIndex++]; 2497 if (CaseSize & 128) 2498 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2499 if (CaseSize == 0) break; 2500 2501 uint16_t Opc = MatcherTable[MatcherIndex++]; 2502 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2503 2504 // If the opcode matches, then we will execute this case. 2505 if (CurNodeOpcode == Opc) 2506 break; 2507 2508 // Otherwise, skip over this case. 2509 MatcherIndex += CaseSize; 2510 } 2511 2512 // If no cases matched, bail out. 2513 if (CaseSize == 0) break; 2514 2515 // Otherwise, execute the case we found. 2516 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart 2517 << " to " << MatcherIndex << "\n"); 2518 continue; 2519 } 2520 2521 case OPC_SwitchType: { 2522 MVT CurNodeVT = N.getSimpleValueType(); 2523 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2524 unsigned CaseSize; 2525 while (1) { 2526 // Get the size of this case. 2527 CaseSize = MatcherTable[MatcherIndex++]; 2528 if (CaseSize & 128) 2529 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2530 if (CaseSize == 0) break; 2531 2532 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2533 if (CaseVT == MVT::iPTR) 2534 CaseVT = getTargetLowering()->getPointerTy(); 2535 2536 // If the VT matches, then we will execute this case. 2537 if (CurNodeVT == CaseVT) 2538 break; 2539 2540 // Otherwise, skip over this case. 2541 MatcherIndex += CaseSize; 2542 } 2543 2544 // If no cases matched, bail out. 2545 if (CaseSize == 0) break; 2546 2547 // Otherwise, execute the case we found. 2548 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2549 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2550 continue; 2551 } 2552 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2553 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2554 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2555 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2556 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(), 2557 Opcode-OPC_CheckChild0Type)) 2558 break; 2559 continue; 2560 case OPC_CheckCondCode: 2561 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2562 continue; 2563 case OPC_CheckValueType: 2564 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2565 break; 2566 continue; 2567 case OPC_CheckInteger: 2568 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2569 continue; 2570 case OPC_CheckAndImm: 2571 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2572 continue; 2573 case OPC_CheckOrImm: 2574 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2575 continue; 2576 2577 case OPC_CheckFoldableChainNode: { 2578 assert(NodeStack.size() != 1 && "No parent node"); 2579 // Verify that all intermediate nodes between the root and this one have 2580 // a single use. 2581 bool HasMultipleUses = false; 2582 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2583 if (!NodeStack[i].hasOneUse()) { 2584 HasMultipleUses = true; 2585 break; 2586 } 2587 if (HasMultipleUses) break; 2588 2589 // Check to see that the target thinks this is profitable to fold and that 2590 // we can fold it without inducing cycles in the graph. 2591 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2592 NodeToMatch) || 2593 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2594 NodeToMatch, OptLevel, 2595 true/*We validate our own chains*/)) 2596 break; 2597 2598 continue; 2599 } 2600 case OPC_EmitInteger: { 2601 MVT::SimpleValueType VT = 2602 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2603 int64_t Val = MatcherTable[MatcherIndex++]; 2604 if (Val & 128) 2605 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2606 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2607 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2608 continue; 2609 } 2610 case OPC_EmitRegister: { 2611 MVT::SimpleValueType VT = 2612 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2613 unsigned RegNo = MatcherTable[MatcherIndex++]; 2614 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2615 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2616 continue; 2617 } 2618 case OPC_EmitRegister2: { 2619 // For targets w/ more than 256 register names, the register enum 2620 // values are stored in two bytes in the matcher table (just like 2621 // opcodes). 2622 MVT::SimpleValueType VT = 2623 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2624 unsigned RegNo = MatcherTable[MatcherIndex++]; 2625 RegNo |= MatcherTable[MatcherIndex++] << 8; 2626 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2627 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2628 continue; 2629 } 2630 2631 case OPC_EmitConvertToTarget: { 2632 // Convert from IMM/FPIMM to target version. 2633 unsigned RecNo = MatcherTable[MatcherIndex++]; 2634 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2635 SDValue Imm = RecordedNodes[RecNo].first; 2636 2637 if (Imm->getOpcode() == ISD::Constant) { 2638 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 2639 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true); 2640 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2641 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2642 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true); 2643 } 2644 2645 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2646 continue; 2647 } 2648 2649 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2650 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2651 // These are space-optimized forms of OPC_EmitMergeInputChains. 2652 assert(InputChain.getNode() == 0 && 2653 "EmitMergeInputChains should be the first chain producing node"); 2654 assert(ChainNodesMatched.empty() && 2655 "Should only have one EmitMergeInputChains per match"); 2656 2657 // Read all of the chained nodes. 2658 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2659 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2660 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2661 2662 // FIXME: What if other value results of the node have uses not matched 2663 // by this pattern? 2664 if (ChainNodesMatched.back() != NodeToMatch && 2665 !RecordedNodes[RecNo].first.hasOneUse()) { 2666 ChainNodesMatched.clear(); 2667 break; 2668 } 2669 2670 // Merge the input chains if they are not intra-pattern references. 2671 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2672 2673 if (InputChain.getNode() == 0) 2674 break; // Failed to merge. 2675 continue; 2676 } 2677 2678 case OPC_EmitMergeInputChains: { 2679 assert(InputChain.getNode() == 0 && 2680 "EmitMergeInputChains should be the first chain producing node"); 2681 // This node gets a list of nodes we matched in the input that have 2682 // chains. We want to token factor all of the input chains to these nodes 2683 // together. However, if any of the input chains is actually one of the 2684 // nodes matched in this pattern, then we have an intra-match reference. 2685 // Ignore these because the newly token factored chain should not refer to 2686 // the old nodes. 2687 unsigned NumChains = MatcherTable[MatcherIndex++]; 2688 assert(NumChains != 0 && "Can't TF zero chains"); 2689 2690 assert(ChainNodesMatched.empty() && 2691 "Should only have one EmitMergeInputChains per match"); 2692 2693 // Read all of the chained nodes. 2694 for (unsigned i = 0; i != NumChains; ++i) { 2695 unsigned RecNo = MatcherTable[MatcherIndex++]; 2696 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2697 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2698 2699 // FIXME: What if other value results of the node have uses not matched 2700 // by this pattern? 2701 if (ChainNodesMatched.back() != NodeToMatch && 2702 !RecordedNodes[RecNo].first.hasOneUse()) { 2703 ChainNodesMatched.clear(); 2704 break; 2705 } 2706 } 2707 2708 // If the inner loop broke out, the match fails. 2709 if (ChainNodesMatched.empty()) 2710 break; 2711 2712 // Merge the input chains if they are not intra-pattern references. 2713 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2714 2715 if (InputChain.getNode() == 0) 2716 break; // Failed to merge. 2717 2718 continue; 2719 } 2720 2721 case OPC_EmitCopyToReg: { 2722 unsigned RecNo = MatcherTable[MatcherIndex++]; 2723 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2724 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2725 2726 if (InputChain.getNode() == 0) 2727 InputChain = CurDAG->getEntryNode(); 2728 2729 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch), 2730 DestPhysReg, RecordedNodes[RecNo].first, 2731 InputGlue); 2732 2733 InputGlue = InputChain.getValue(1); 2734 continue; 2735 } 2736 2737 case OPC_EmitNodeXForm: { 2738 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2739 unsigned RecNo = MatcherTable[MatcherIndex++]; 2740 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2741 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2742 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2743 continue; 2744 } 2745 2746 case OPC_EmitNode: 2747 case OPC_MorphNodeTo: { 2748 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2749 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2750 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2751 // Get the result VT list. 2752 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2753 SmallVector<EVT, 4> VTs; 2754 for (unsigned i = 0; i != NumVTs; ++i) { 2755 MVT::SimpleValueType VT = 2756 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2757 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy; 2758 VTs.push_back(VT); 2759 } 2760 2761 if (EmitNodeInfo & OPFL_Chain) 2762 VTs.push_back(MVT::Other); 2763 if (EmitNodeInfo & OPFL_GlueOutput) 2764 VTs.push_back(MVT::Glue); 2765 2766 // This is hot code, so optimize the two most common cases of 1 and 2 2767 // results. 2768 SDVTList VTList; 2769 if (VTs.size() == 1) 2770 VTList = CurDAG->getVTList(VTs[0]); 2771 else if (VTs.size() == 2) 2772 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2773 else 2774 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2775 2776 // Get the operand list. 2777 unsigned NumOps = MatcherTable[MatcherIndex++]; 2778 SmallVector<SDValue, 8> Ops; 2779 for (unsigned i = 0; i != NumOps; ++i) { 2780 unsigned RecNo = MatcherTable[MatcherIndex++]; 2781 if (RecNo & 128) 2782 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2783 2784 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2785 Ops.push_back(RecordedNodes[RecNo].first); 2786 } 2787 2788 // If there are variadic operands to add, handle them now. 2789 if (EmitNodeInfo & OPFL_VariadicInfo) { 2790 // Determine the start index to copy from. 2791 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2792 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2793 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2794 "Invalid variadic node"); 2795 // Copy all of the variadic operands, not including a potential glue 2796 // input. 2797 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2798 i != e; ++i) { 2799 SDValue V = NodeToMatch->getOperand(i); 2800 if (V.getValueType() == MVT::Glue) break; 2801 Ops.push_back(V); 2802 } 2803 } 2804 2805 // If this has chain/glue inputs, add them. 2806 if (EmitNodeInfo & OPFL_Chain) 2807 Ops.push_back(InputChain); 2808 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2809 Ops.push_back(InputGlue); 2810 2811 // Create the node. 2812 SDNode *Res = 0; 2813 if (Opcode != OPC_MorphNodeTo) { 2814 // If this is a normal EmitNode command, just create the new node and 2815 // add the results to the RecordedNodes list. 2816 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch), 2817 VTList, Ops); 2818 2819 // Add all the non-glue/non-chain results to the RecordedNodes list. 2820 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2821 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2822 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2823 (SDNode*) 0)); 2824 } 2825 2826 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 2827 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2828 EmitNodeInfo); 2829 } else { 2830 // NodeToMatch was eliminated by CSE when the target changed the DAG. 2831 // We will visit the equivalent node later. 2832 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 2833 return 0; 2834 } 2835 2836 // If the node had chain/glue results, update our notion of the current 2837 // chain and glue. 2838 if (EmitNodeInfo & OPFL_GlueOutput) { 2839 InputGlue = SDValue(Res, VTs.size()-1); 2840 if (EmitNodeInfo & OPFL_Chain) 2841 InputChain = SDValue(Res, VTs.size()-2); 2842 } else if (EmitNodeInfo & OPFL_Chain) 2843 InputChain = SDValue(Res, VTs.size()-1); 2844 2845 // If the OPFL_MemRefs glue is set on this node, slap all of the 2846 // accumulated memrefs onto it. 2847 // 2848 // FIXME: This is vastly incorrect for patterns with multiple outputs 2849 // instructions that access memory and for ComplexPatterns that match 2850 // loads. 2851 if (EmitNodeInfo & OPFL_MemRefs) { 2852 // Only attach load or store memory operands if the generated 2853 // instruction may load or store. 2854 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2855 bool mayLoad = MCID.mayLoad(); 2856 bool mayStore = MCID.mayStore(); 2857 2858 unsigned NumMemRefs = 0; 2859 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 2860 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2861 if ((*I)->isLoad()) { 2862 if (mayLoad) 2863 ++NumMemRefs; 2864 } else if ((*I)->isStore()) { 2865 if (mayStore) 2866 ++NumMemRefs; 2867 } else { 2868 ++NumMemRefs; 2869 } 2870 } 2871 2872 MachineSDNode::mmo_iterator MemRefs = 2873 MF->allocateMemRefsArray(NumMemRefs); 2874 2875 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 2876 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 2877 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2878 if ((*I)->isLoad()) { 2879 if (mayLoad) 2880 *MemRefsPos++ = *I; 2881 } else if ((*I)->isStore()) { 2882 if (mayStore) 2883 *MemRefsPos++ = *I; 2884 } else { 2885 *MemRefsPos++ = *I; 2886 } 2887 } 2888 2889 cast<MachineSDNode>(Res) 2890 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 2891 } 2892 2893 DEBUG(dbgs() << " " 2894 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2895 << " node: "; Res->dump(CurDAG); dbgs() << "\n"); 2896 2897 // If this was a MorphNodeTo then we're completely done! 2898 if (Opcode == OPC_MorphNodeTo) { 2899 // Update chain and glue uses. 2900 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2901 InputGlue, GlueResultNodesMatched, true); 2902 return Res; 2903 } 2904 2905 continue; 2906 } 2907 2908 case OPC_MarkGlueResults: { 2909 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2910 2911 // Read and remember all the glue-result nodes. 2912 for (unsigned i = 0; i != NumNodes; ++i) { 2913 unsigned RecNo = MatcherTable[MatcherIndex++]; 2914 if (RecNo & 128) 2915 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2916 2917 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2918 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2919 } 2920 continue; 2921 } 2922 2923 case OPC_CompleteMatch: { 2924 // The match has been completed, and any new nodes (if any) have been 2925 // created. Patch up references to the matched dag to use the newly 2926 // created nodes. 2927 unsigned NumResults = MatcherTable[MatcherIndex++]; 2928 2929 for (unsigned i = 0; i != NumResults; ++i) { 2930 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2931 if (ResSlot & 128) 2932 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2933 2934 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2935 SDValue Res = RecordedNodes[ResSlot].first; 2936 2937 assert(i < NodeToMatch->getNumValues() && 2938 NodeToMatch->getValueType(i) != MVT::Other && 2939 NodeToMatch->getValueType(i) != MVT::Glue && 2940 "Invalid number of results to complete!"); 2941 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2942 NodeToMatch->getValueType(i) == MVT::iPTR || 2943 Res.getValueType() == MVT::iPTR || 2944 NodeToMatch->getValueType(i).getSizeInBits() == 2945 Res.getValueType().getSizeInBits()) && 2946 "invalid replacement"); 2947 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2948 } 2949 2950 // If the root node defines glue, add it to the glue nodes to update list. 2951 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2952 GlueResultNodesMatched.push_back(NodeToMatch); 2953 2954 // Update chain and glue uses. 2955 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2956 InputGlue, GlueResultNodesMatched, false); 2957 2958 assert(NodeToMatch->use_empty() && 2959 "Didn't replace all uses of the node?"); 2960 2961 // FIXME: We just return here, which interacts correctly with SelectRoot 2962 // above. We should fix this to not return an SDNode* anymore. 2963 return 0; 2964 } 2965 } 2966 2967 // If the code reached this point, then the match failed. See if there is 2968 // another child to try in the current 'Scope', otherwise pop it until we 2969 // find a case to check. 2970 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2971 ++NumDAGIselRetries; 2972 while (1) { 2973 if (MatchScopes.empty()) { 2974 CannotYetSelect(NodeToMatch); 2975 return 0; 2976 } 2977 2978 // Restore the interpreter state back to the point where the scope was 2979 // formed. 2980 MatchScope &LastScope = MatchScopes.back(); 2981 RecordedNodes.resize(LastScope.NumRecordedNodes); 2982 NodeStack.clear(); 2983 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2984 N = NodeStack.back(); 2985 2986 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2987 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2988 MatcherIndex = LastScope.FailIndex; 2989 2990 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); 2991 2992 InputChain = LastScope.InputChain; 2993 InputGlue = LastScope.InputGlue; 2994 if (!LastScope.HasChainNodesMatched) 2995 ChainNodesMatched.clear(); 2996 if (!LastScope.HasGlueResultNodesMatched) 2997 GlueResultNodesMatched.clear(); 2998 2999 // Check to see what the offset is at the new MatcherIndex. If it is zero 3000 // we have reached the end of this scope, otherwise we have another child 3001 // in the current scope to try. 3002 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 3003 if (NumToSkip & 128) 3004 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 3005 3006 // If we have another child in this scope to match, update FailIndex and 3007 // try it. 3008 if (NumToSkip != 0) { 3009 LastScope.FailIndex = MatcherIndex+NumToSkip; 3010 break; 3011 } 3012 3013 // End of this scope, pop it and try the next child in the containing 3014 // scope. 3015 MatchScopes.pop_back(); 3016 } 3017 } 3018} 3019 3020 3021 3022void SelectionDAGISel::CannotYetSelect(SDNode *N) { 3023 std::string msg; 3024 raw_string_ostream Msg(msg); 3025 Msg << "Cannot select: "; 3026 3027 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 3028 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 3029 N->getOpcode() != ISD::INTRINSIC_VOID) { 3030 N->printrFull(Msg, CurDAG); 3031 Msg << "\nIn function: " << MF->getName(); 3032 } else { 3033 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 3034 unsigned iid = 3035 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 3036 if (iid < Intrinsic::num_intrinsics) 3037 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 3038 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 3039 Msg << "target intrinsic %" << TII->getName(iid); 3040 else 3041 Msg << "unknown intrinsic #" << iid; 3042 } 3043 report_fatal_error(Msg.str()); 3044} 3045 3046char SelectionDAGISel::ID = 0; 3047