SelectionDAGISel.cpp revision 69e6a8d5a8c486bcdd2c19238171b01d470ba45f
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/Collector.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetData.h" 40#include "llvm/Target/TargetFrameInfo.h" 41#include "llvm/Target/TargetInstrInfo.h" 42#include "llvm/Target/TargetLowering.h" 43#include "llvm/Target/TargetMachine.h" 44#include "llvm/Target/TargetOptions.h" 45#include "llvm/Support/MathExtras.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/Compiler.h" 48#include <algorithm> 49using namespace llvm; 50 51#ifndef NDEBUG 52static cl::opt<bool> 53ViewISelDAGs("view-isel-dags", cl::Hidden, 54 cl::desc("Pop up a window to show isel dags as they are selected")); 55static cl::opt<bool> 56ViewSchedDAGs("view-sched-dags", cl::Hidden, 57 cl::desc("Pop up a window to show sched dags as they are processed")); 58static cl::opt<bool> 59ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 60 cl::desc("Pop up a window to show SUnit dags after they are processed")); 61#else 62static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0; 63#endif 64 65//===---------------------------------------------------------------------===// 66/// 67/// RegisterScheduler class - Track the registration of instruction schedulers. 68/// 69//===---------------------------------------------------------------------===// 70MachinePassRegistry RegisterScheduler::Registry; 71 72//===---------------------------------------------------------------------===// 73/// 74/// ISHeuristic command line option for instruction schedulers. 75/// 76//===---------------------------------------------------------------------===// 77namespace { 78 cl::opt<RegisterScheduler::FunctionPassCtor, false, 79 RegisterPassParser<RegisterScheduler> > 80 ISHeuristic("pre-RA-sched", 81 cl::init(&createDefaultScheduler), 82 cl::desc("Instruction schedulers available (before register" 83 " allocation):")); 84 85 static RegisterScheduler 86 defaultListDAGScheduler("default", " Best scheduler for the target", 87 createDefaultScheduler); 88} // namespace 89 90namespace { struct AsmOperandInfo; } 91 92namespace { 93 /// RegsForValue - This struct represents the physical registers that a 94 /// particular value is assigned and the type information about the value. 95 /// This is needed because values can be promoted into larger registers and 96 /// expanded into multiple smaller registers than the value. 97 struct VISIBILITY_HIDDEN RegsForValue { 98 /// Regs - This list holds the register (for legal and promoted values) 99 /// or register set (for expanded values) that the value should be assigned 100 /// to. 101 std::vector<unsigned> Regs; 102 103 /// RegVT - The value type of each register. 104 /// 105 MVT::ValueType RegVT; 106 107 /// ValueVT - The value type of the LLVM value, which may be promoted from 108 /// RegVT or made from merging the two expanded parts. 109 MVT::ValueType ValueVT; 110 111 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 112 113 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 114 : RegVT(regvt), ValueVT(valuevt) { 115 Regs.push_back(Reg); 116 } 117 RegsForValue(const std::vector<unsigned> ®s, 118 MVT::ValueType regvt, MVT::ValueType valuevt) 119 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 120 } 121 122 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 123 /// this value and returns the result as a ValueVT value. This uses 124 /// Chain/Flag as the input and updates them for the output Chain/Flag. 125 /// If the Flag pointer is NULL, no flag is used. 126 SDOperand getCopyFromRegs(SelectionDAG &DAG, 127 SDOperand &Chain, SDOperand *Flag) const; 128 129 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 130 /// specified value into the registers specified by this object. This uses 131 /// Chain/Flag as the input and updates them for the output Chain/Flag. 132 /// If the Flag pointer is NULL, no flag is used. 133 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 134 SDOperand &Chain, SDOperand *Flag) const; 135 136 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 137 /// operand list. This adds the code marker and includes the number of 138 /// values added into it. 139 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 140 std::vector<SDOperand> &Ops) const; 141 }; 142} 143 144namespace llvm { 145 //===--------------------------------------------------------------------===// 146 /// createDefaultScheduler - This creates an instruction scheduler appropriate 147 /// for the target. 148 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 149 SelectionDAG *DAG, 150 MachineBasicBlock *BB) { 151 TargetLowering &TLI = IS->getTargetLowering(); 152 153 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 154 return createTDListDAGScheduler(IS, DAG, BB); 155 } else { 156 assert(TLI.getSchedulingPreference() == 157 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 158 return createBURRListDAGScheduler(IS, DAG, BB); 159 } 160 } 161 162 163 //===--------------------------------------------------------------------===// 164 /// FunctionLoweringInfo - This contains information that is global to a 165 /// function that is used when lowering a region of the function. 166 class FunctionLoweringInfo { 167 public: 168 TargetLowering &TLI; 169 Function &Fn; 170 MachineFunction &MF; 171 MachineRegisterInfo &RegInfo; 172 173 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 174 175 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 176 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 177 178 /// ValueMap - Since we emit code for the function a basic block at a time, 179 /// we must remember which virtual registers hold the values for 180 /// cross-basic-block values. 181 DenseMap<const Value*, unsigned> ValueMap; 182 183 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 184 /// the entry block. This allows the allocas to be efficiently referenced 185 /// anywhere in the function. 186 std::map<const AllocaInst*, int> StaticAllocaMap; 187 188#ifndef NDEBUG 189 SmallSet<Instruction*, 8> CatchInfoLost; 190 SmallSet<Instruction*, 8> CatchInfoFound; 191#endif 192 193 unsigned MakeReg(MVT::ValueType VT) { 194 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT)); 195 } 196 197 /// isExportedInst - Return true if the specified value is an instruction 198 /// exported from its block. 199 bool isExportedInst(const Value *V) { 200 return ValueMap.count(V); 201 } 202 203 unsigned CreateRegForValue(const Value *V); 204 205 unsigned InitializeRegForValue(const Value *V) { 206 unsigned &R = ValueMap[V]; 207 assert(R == 0 && "Already initialized this value register!"); 208 return R = CreateRegForValue(V); 209 } 210 }; 211} 212 213/// isSelector - Return true if this instruction is a call to the 214/// eh.selector intrinsic. 215static bool isSelector(Instruction *I) { 216 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 217 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 || 218 II->getIntrinsicID() == Intrinsic::eh_selector_i64); 219 return false; 220} 221 222/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 223/// PHI nodes or outside of the basic block that defines it, or used by a 224/// switch or atomic instruction, which may expand to multiple basic blocks. 225static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 226 if (isa<PHINode>(I)) return true; 227 BasicBlock *BB = I->getParent(); 228 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 229 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 230 // FIXME: Remove switchinst special case. 231 isa<SwitchInst>(*UI)) 232 return true; 233 return false; 234} 235 236/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 237/// entry block, return true. This includes arguments used by switches, since 238/// the switch may expand into multiple basic blocks. 239static bool isOnlyUsedInEntryBlock(Argument *A) { 240 BasicBlock *Entry = A->getParent()->begin(); 241 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 242 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 243 return false; // Use not in entry block. 244 return true; 245} 246 247FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 248 Function &fn, MachineFunction &mf) 249 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) { 250 251 // Create a vreg for each argument register that is not dead and is used 252 // outside of the entry block for the function. 253 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 254 AI != E; ++AI) 255 if (!isOnlyUsedInEntryBlock(AI)) 256 InitializeRegForValue(AI); 257 258 // Initialize the mapping of values to registers. This is only set up for 259 // instruction values that are used outside of the block that defines 260 // them. 261 Function::iterator BB = Fn.begin(), EB = Fn.end(); 262 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 263 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 264 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 265 const Type *Ty = AI->getAllocatedType(); 266 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 267 unsigned Align = 268 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 269 AI->getAlignment()); 270 271 TySize *= CUI->getZExtValue(); // Get total allocated size. 272 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 273 StaticAllocaMap[AI] = 274 MF.getFrameInfo()->CreateStackObject(TySize, Align); 275 } 276 277 for (; BB != EB; ++BB) 278 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 279 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 280 if (!isa<AllocaInst>(I) || 281 !StaticAllocaMap.count(cast<AllocaInst>(I))) 282 InitializeRegForValue(I); 283 284 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 285 // also creates the initial PHI MachineInstrs, though none of the input 286 // operands are populated. 287 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 288 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 289 MBBMap[BB] = MBB; 290 MF.getBasicBlockList().push_back(MBB); 291 292 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 293 // appropriate. 294 PHINode *PN; 295 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 296 if (PN->use_empty()) continue; 297 298 MVT::ValueType VT = TLI.getValueType(PN->getType()); 299 unsigned NumRegisters = TLI.getNumRegisters(VT); 300 unsigned PHIReg = ValueMap[PN]; 301 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 302 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 303 for (unsigned i = 0; i != NumRegisters; ++i) 304 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 305 } 306 } 307} 308 309/// CreateRegForValue - Allocate the appropriate number of virtual registers of 310/// the correctly promoted or expanded types. Assign these registers 311/// consecutive vreg numbers and return the first assigned number. 312unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 313 MVT::ValueType VT = TLI.getValueType(V->getType()); 314 315 unsigned NumRegisters = TLI.getNumRegisters(VT); 316 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 317 318 unsigned R = MakeReg(RegisterVT); 319 for (unsigned i = 1; i != NumRegisters; ++i) 320 MakeReg(RegisterVT); 321 322 return R; 323} 324 325//===----------------------------------------------------------------------===// 326/// SelectionDAGLowering - This is the common target-independent lowering 327/// implementation that is parameterized by a TargetLowering object. 328/// Also, targets can overload any lowering method. 329/// 330namespace llvm { 331class SelectionDAGLowering { 332 MachineBasicBlock *CurMBB; 333 334 DenseMap<const Value*, SDOperand> NodeMap; 335 336 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 337 /// them up and then emit token factor nodes when possible. This allows us to 338 /// get simple disambiguation between loads without worrying about alias 339 /// analysis. 340 std::vector<SDOperand> PendingLoads; 341 342 /// Case - A struct to record the Value for a switch case, and the 343 /// case's target basic block. 344 struct Case { 345 Constant* Low; 346 Constant* High; 347 MachineBasicBlock* BB; 348 349 Case() : Low(0), High(0), BB(0) { } 350 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 351 Low(low), High(high), BB(bb) { } 352 uint64_t size() const { 353 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 354 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 355 return (rHigh - rLow + 1ULL); 356 } 357 }; 358 359 struct CaseBits { 360 uint64_t Mask; 361 MachineBasicBlock* BB; 362 unsigned Bits; 363 364 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 365 Mask(mask), BB(bb), Bits(bits) { } 366 }; 367 368 typedef std::vector<Case> CaseVector; 369 typedef std::vector<CaseBits> CaseBitsVector; 370 typedef CaseVector::iterator CaseItr; 371 typedef std::pair<CaseItr, CaseItr> CaseRange; 372 373 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 374 /// of conditional branches. 375 struct CaseRec { 376 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 377 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 378 379 /// CaseBB - The MBB in which to emit the compare and branch 380 MachineBasicBlock *CaseBB; 381 /// LT, GE - If nonzero, we know the current case value must be less-than or 382 /// greater-than-or-equal-to these Constants. 383 Constant *LT; 384 Constant *GE; 385 /// Range - A pair of iterators representing the range of case values to be 386 /// processed at this point in the binary search tree. 387 CaseRange Range; 388 }; 389 390 typedef std::vector<CaseRec> CaseRecVector; 391 392 /// The comparison function for sorting the switch case values in the vector. 393 /// WARNING: Case ranges should be disjoint! 394 struct CaseCmp { 395 bool operator () (const Case& C1, const Case& C2) { 396 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 397 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 398 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 399 return CI1->getValue().slt(CI2->getValue()); 400 } 401 }; 402 403 struct CaseBitsCmp { 404 bool operator () (const CaseBits& C1, const CaseBits& C2) { 405 return C1.Bits > C2.Bits; 406 } 407 }; 408 409 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 410 411public: 412 // TLI - This is information that describes the available target features we 413 // need for lowering. This indicates when operations are unavailable, 414 // implemented with a libcall, etc. 415 TargetLowering &TLI; 416 SelectionDAG &DAG; 417 const TargetData *TD; 418 AliasAnalysis &AA; 419 420 /// SwitchCases - Vector of CaseBlock structures used to communicate 421 /// SwitchInst code generation information. 422 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 423 /// JTCases - Vector of JumpTable structures used to communicate 424 /// SwitchInst code generation information. 425 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 426 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 427 428 /// FuncInfo - Information about the function as a whole. 429 /// 430 FunctionLoweringInfo &FuncInfo; 431 432 /// GCI - Garbage collection metadata for the function. 433 CollectorMetadata *GCI; 434 435 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 436 AliasAnalysis &aa, 437 FunctionLoweringInfo &funcinfo, 438 CollectorMetadata *gci) 439 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa), 440 FuncInfo(funcinfo), GCI(gci) { 441 } 442 443 /// getRoot - Return the current virtual root of the Selection DAG. 444 /// 445 SDOperand getRoot() { 446 if (PendingLoads.empty()) 447 return DAG.getRoot(); 448 449 if (PendingLoads.size() == 1) { 450 SDOperand Root = PendingLoads[0]; 451 DAG.setRoot(Root); 452 PendingLoads.clear(); 453 return Root; 454 } 455 456 // Otherwise, we have to make a token factor node. 457 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 458 &PendingLoads[0], PendingLoads.size()); 459 PendingLoads.clear(); 460 DAG.setRoot(Root); 461 return Root; 462 } 463 464 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 465 466 void visit(Instruction &I) { visit(I.getOpcode(), I); } 467 468 void visit(unsigned Opcode, User &I) { 469 // Note: this doesn't use InstVisitor, because it has to work with 470 // ConstantExpr's in addition to instructions. 471 switch (Opcode) { 472 default: assert(0 && "Unknown instruction type encountered!"); 473 abort(); 474 // Build the switch statement using the Instruction.def file. 475#define HANDLE_INST(NUM, OPCODE, CLASS) \ 476 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 477#include "llvm/Instruction.def" 478 } 479 } 480 481 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 482 483 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 484 const Value *SV, SDOperand Root, 485 bool isVolatile, unsigned Alignment); 486 487 SDOperand getValue(const Value *V); 488 489 void setValue(const Value *V, SDOperand NewN) { 490 SDOperand &N = NodeMap[V]; 491 assert(N.Val == 0 && "Already set a value for this node!"); 492 N = NewN; 493 } 494 495 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 496 std::set<unsigned> &OutputRegs, 497 std::set<unsigned> &InputRegs); 498 499 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 500 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 501 unsigned Opc); 502 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 503 void ExportFromCurrentBlock(Value *V); 504 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall, 505 MachineBasicBlock *LandingPad = NULL); 506 507 // Terminator instructions. 508 void visitRet(ReturnInst &I); 509 void visitBr(BranchInst &I); 510 void visitSwitch(SwitchInst &I); 511 void visitUnreachable(UnreachableInst &I) { /* noop */ } 512 513 // Helpers for visitSwitch 514 bool handleSmallSwitchRange(CaseRec& CR, 515 CaseRecVector& WorkList, 516 Value* SV, 517 MachineBasicBlock* Default); 518 bool handleJTSwitchCase(CaseRec& CR, 519 CaseRecVector& WorkList, 520 Value* SV, 521 MachineBasicBlock* Default); 522 bool handleBTSplitSwitchCase(CaseRec& CR, 523 CaseRecVector& WorkList, 524 Value* SV, 525 MachineBasicBlock* Default); 526 bool handleBitTestsSwitchCase(CaseRec& CR, 527 CaseRecVector& WorkList, 528 Value* SV, 529 MachineBasicBlock* Default); 530 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 531 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 532 void visitBitTestCase(MachineBasicBlock* NextMBB, 533 unsigned Reg, 534 SelectionDAGISel::BitTestCase &B); 535 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 536 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 537 SelectionDAGISel::JumpTableHeader &JTH); 538 539 // These all get lowered before this pass. 540 void visitInvoke(InvokeInst &I); 541 void visitUnwind(UnwindInst &I); 542 543 void visitBinary(User &I, unsigned OpCode); 544 void visitShift(User &I, unsigned Opcode); 545 void visitAdd(User &I) { 546 if (I.getType()->isFPOrFPVector()) 547 visitBinary(I, ISD::FADD); 548 else 549 visitBinary(I, ISD::ADD); 550 } 551 void visitSub(User &I); 552 void visitMul(User &I) { 553 if (I.getType()->isFPOrFPVector()) 554 visitBinary(I, ISD::FMUL); 555 else 556 visitBinary(I, ISD::MUL); 557 } 558 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 559 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 560 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 561 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 562 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 563 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 564 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 565 void visitOr (User &I) { visitBinary(I, ISD::OR); } 566 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 567 void visitShl (User &I) { visitShift(I, ISD::SHL); } 568 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 569 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 570 void visitICmp(User &I); 571 void visitFCmp(User &I); 572 // Visit the conversion instructions 573 void visitTrunc(User &I); 574 void visitZExt(User &I); 575 void visitSExt(User &I); 576 void visitFPTrunc(User &I); 577 void visitFPExt(User &I); 578 void visitFPToUI(User &I); 579 void visitFPToSI(User &I); 580 void visitUIToFP(User &I); 581 void visitSIToFP(User &I); 582 void visitPtrToInt(User &I); 583 void visitIntToPtr(User &I); 584 void visitBitCast(User &I); 585 586 void visitExtractElement(User &I); 587 void visitInsertElement(User &I); 588 void visitShuffleVector(User &I); 589 590 void visitGetElementPtr(User &I); 591 void visitSelect(User &I); 592 593 void visitMalloc(MallocInst &I); 594 void visitFree(FreeInst &I); 595 void visitAlloca(AllocaInst &I); 596 void visitLoad(LoadInst &I); 597 void visitStore(StoreInst &I); 598 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 599 void visitCall(CallInst &I); 600 void visitInlineAsm(CallSite CS); 601 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 602 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 603 604 void visitVAStart(CallInst &I); 605 void visitVAArg(VAArgInst &I); 606 void visitVAEnd(CallInst &I); 607 void visitVACopy(CallInst &I); 608 609 void visitMemIntrinsic(CallInst &I, unsigned Op); 610 611 void visitGetResult(GetResultInst &I) { 612 assert (0 && "getresult unimplemented"); 613 } 614 615 void visitUserOp1(Instruction &I) { 616 assert(0 && "UserOp1 should not exist at instruction selection time!"); 617 abort(); 618 } 619 void visitUserOp2(Instruction &I) { 620 assert(0 && "UserOp2 should not exist at instruction selection time!"); 621 abort(); 622 } 623}; 624} // end namespace llvm 625 626 627/// getCopyFromParts - Create a value that contains the specified legal parts 628/// combined into the value they represent. If the parts combine to a type 629/// larger then ValueVT then AssertOp can be used to specify whether the extra 630/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 631/// (ISD::AssertSext). Likewise TruncExact is used for floating point types to 632/// indicate that the extra bits can be discarded without losing precision. 633static SDOperand getCopyFromParts(SelectionDAG &DAG, 634 const SDOperand *Parts, 635 unsigned NumParts, 636 MVT::ValueType PartVT, 637 MVT::ValueType ValueVT, 638 ISD::NodeType AssertOp = ISD::DELETED_NODE, 639 bool TruncExact = false) { 640 assert(NumParts > 0 && "No parts to assemble!"); 641 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 642 SDOperand Val = Parts[0]; 643 644 if (NumParts > 1) { 645 // Assemble the value from multiple parts. 646 if (!MVT::isVector(ValueVT)) { 647 unsigned PartBits = MVT::getSizeInBits(PartVT); 648 unsigned ValueBits = MVT::getSizeInBits(ValueVT); 649 650 // Assemble the power of 2 part. 651 unsigned RoundParts = NumParts & (NumParts - 1) ? 652 1 << Log2_32(NumParts) : NumParts; 653 unsigned RoundBits = PartBits * RoundParts; 654 MVT::ValueType RoundVT = RoundBits == ValueBits ? 655 ValueVT : MVT::getIntegerType(RoundBits); 656 SDOperand Lo, Hi; 657 658 if (RoundParts > 2) { 659 MVT::ValueType HalfVT = MVT::getIntegerType(RoundBits/2); 660 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT); 661 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2, 662 PartVT, HalfVT); 663 } else { 664 Lo = Parts[0]; 665 Hi = Parts[1]; 666 } 667 if (TLI.isBigEndian()) 668 std::swap(Lo, Hi); 669 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi); 670 671 if (RoundParts < NumParts) { 672 // Assemble the trailing non-power-of-2 part. 673 unsigned OddParts = NumParts - RoundParts; 674 MVT::ValueType OddVT = MVT::getIntegerType(OddParts * PartBits); 675 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT); 676 677 // Combine the round and odd parts. 678 Lo = Val; 679 if (TLI.isBigEndian()) 680 std::swap(Lo, Hi); 681 MVT::ValueType TotalVT = MVT::getIntegerType(NumParts * PartBits); 682 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi); 683 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi, 684 DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()), 685 TLI.getShiftAmountTy())); 686 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo); 687 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi); 688 } 689 } else { 690 // Handle a multi-element vector. 691 MVT::ValueType IntermediateVT, RegisterVT; 692 unsigned NumIntermediates; 693 unsigned NumRegs = 694 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 695 RegisterVT); 696 697 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 698 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 699 assert(RegisterVT == Parts[0].getValueType() && 700 "Part type doesn't match part!"); 701 702 // Assemble the parts into intermediate operands. 703 SmallVector<SDOperand, 8> Ops(NumIntermediates); 704 if (NumIntermediates == NumParts) { 705 // If the register was not expanded, truncate or copy the value, 706 // as appropriate. 707 for (unsigned i = 0; i != NumParts; ++i) 708 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 709 PartVT, IntermediateVT); 710 } else if (NumParts > 0) { 711 // If the intermediate type was expanded, build the intermediate operands 712 // from the parts. 713 assert(NumParts % NumIntermediates == 0 && 714 "Must expand into a divisible number of parts!"); 715 unsigned Factor = NumParts / NumIntermediates; 716 for (unsigned i = 0; i != NumIntermediates; ++i) 717 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 718 PartVT, IntermediateVT); 719 } 720 721 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 722 // operands. 723 Val = DAG.getNode(MVT::isVector(IntermediateVT) ? 724 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, 725 ValueVT, &Ops[0], NumIntermediates); 726 } 727 } 728 729 // There is now one part, held in Val. Correct it to match ValueVT. 730 PartVT = Val.getValueType(); 731 732 if (PartVT == ValueVT) 733 return Val; 734 735 if (MVT::isVector(PartVT)) { 736 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!"); 737 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 738 } 739 740 if (MVT::isVector(ValueVT)) { 741 assert(MVT::getVectorElementType(ValueVT) == PartVT && 742 MVT::getVectorNumElements(ValueVT) == 1 && 743 "Only trivial scalar-to-vector conversions should get here!"); 744 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val); 745 } 746 747 if (MVT::isInteger(PartVT) && 748 MVT::isInteger(ValueVT)) { 749 if (MVT::getSizeInBits(ValueVT) < MVT::getSizeInBits(PartVT)) { 750 // For a truncate, see if we have any information to 751 // indicate whether the truncated bits will always be 752 // zero or sign-extension. 753 if (AssertOp != ISD::DELETED_NODE) 754 Val = DAG.getNode(AssertOp, PartVT, Val, 755 DAG.getValueType(ValueVT)); 756 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 757 } else { 758 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 759 } 760 } 761 762 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) 763 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, 764 DAG.getIntPtrConstant(TruncExact)); 765 766 if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT)) 767 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 768 769 assert(0 && "Unknown mismatch!"); 770} 771 772/// getCopyToParts - Create a series of nodes that contain the specified value 773/// split into legal parts. If the parts contain more bits than Val, then, for 774/// integers, ExtendKind can be used to specify how to generate the extra bits. 775static void getCopyToParts(SelectionDAG &DAG, 776 SDOperand Val, 777 SDOperand *Parts, 778 unsigned NumParts, 779 MVT::ValueType PartVT, 780 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 781 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 782 MVT::ValueType PtrVT = TLI.getPointerTy(); 783 MVT::ValueType ValueVT = Val.getValueType(); 784 unsigned PartBits = MVT::getSizeInBits(PartVT); 785 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 786 787 if (!NumParts) 788 return; 789 790 if (!MVT::isVector(ValueVT)) { 791 if (PartVT == ValueVT) { 792 assert(NumParts == 1 && "No-op copy with multiple parts!"); 793 Parts[0] = Val; 794 return; 795 } 796 797 if (NumParts * PartBits > MVT::getSizeInBits(ValueVT)) { 798 // If the parts cover more bits than the value has, promote the value. 799 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) { 800 assert(NumParts == 1 && "Do not know what to promote to!"); 801 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 802 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 803 ValueVT = MVT::getIntegerType(NumParts * PartBits); 804 Val = DAG.getNode(ExtendKind, ValueVT, Val); 805 } else { 806 assert(0 && "Unknown mismatch!"); 807 } 808 } else if (PartBits == MVT::getSizeInBits(ValueVT)) { 809 // Different types of the same size. 810 assert(NumParts == 1 && PartVT != ValueVT); 811 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 812 } else if (NumParts * PartBits < MVT::getSizeInBits(ValueVT)) { 813 // If the parts cover less bits than value has, truncate the value. 814 if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 815 ValueVT = MVT::getIntegerType(NumParts * PartBits); 816 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 817 } else { 818 assert(0 && "Unknown mismatch!"); 819 } 820 } 821 822 // The value may have changed - recompute ValueVT. 823 ValueVT = Val.getValueType(); 824 assert(NumParts * PartBits == MVT::getSizeInBits(ValueVT) && 825 "Failed to tile the value with PartVT!"); 826 827 if (NumParts == 1) { 828 assert(PartVT == ValueVT && "Type conversion failed!"); 829 Parts[0] = Val; 830 return; 831 } 832 833 // Expand the value into multiple parts. 834 if (NumParts & (NumParts - 1)) { 835 // The number of parts is not a power of 2. Split off and copy the tail. 836 assert(MVT::isInteger(PartVT) && MVT::isInteger(ValueVT) && 837 "Do not know what to expand to!"); 838 unsigned RoundParts = 1 << Log2_32(NumParts); 839 unsigned RoundBits = RoundParts * PartBits; 840 unsigned OddParts = NumParts - RoundParts; 841 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val, 842 DAG.getConstant(RoundBits, 843 TLI.getShiftAmountTy())); 844 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT); 845 if (TLI.isBigEndian()) 846 // The odd parts were reversed by getCopyToParts - unreverse them. 847 std::reverse(Parts + RoundParts, Parts + NumParts); 848 NumParts = RoundParts; 849 ValueVT = MVT::getIntegerType(NumParts * PartBits); 850 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 851 } 852 853 // The number of parts is a power of 2. Repeatedly bisect the value using 854 // EXTRACT_ELEMENT. 855 Parts[0] = Val; 856 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 857 for (unsigned i = 0; i < NumParts; i += StepSize) { 858 unsigned ThisBits = StepSize * PartBits / 2; 859 MVT::ValueType ThisVT = 860 ThisBits == PartBits ? PartVT : MVT::getIntegerType (ThisBits); 861 862 Parts[i+StepSize/2] = 863 DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Parts[i], 864 DAG.getConstant(1, PtrVT)); 865 Parts[i] = 866 DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Parts[i], 867 DAG.getConstant(0, PtrVT)); 868 } 869 } 870 871 if (TLI.isBigEndian()) 872 std::reverse(Parts, Parts + NumParts); 873 874 return; 875 } 876 877 // Vector ValueVT. 878 if (NumParts == 1) { 879 if (PartVT != ValueVT) { 880 if (MVT::isVector(PartVT)) { 881 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 882 } else { 883 assert(MVT::getVectorElementType(ValueVT) == PartVT && 884 MVT::getVectorNumElements(ValueVT) == 1 && 885 "Only trivial vector-to-scalar conversions should get here!"); 886 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val, 887 DAG.getConstant(0, PtrVT)); 888 } 889 } 890 891 Parts[0] = Val; 892 return; 893 } 894 895 // Handle a multi-element vector. 896 MVT::ValueType IntermediateVT, RegisterVT; 897 unsigned NumIntermediates; 898 unsigned NumRegs = 899 DAG.getTargetLoweringInfo() 900 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 901 RegisterVT); 902 unsigned NumElements = MVT::getVectorNumElements(ValueVT); 903 904 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 905 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 906 907 // Split the vector into intermediate operands. 908 SmallVector<SDOperand, 8> Ops(NumIntermediates); 909 for (unsigned i = 0; i != NumIntermediates; ++i) 910 if (MVT::isVector(IntermediateVT)) 911 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 912 IntermediateVT, Val, 913 DAG.getConstant(i * (NumElements / NumIntermediates), 914 PtrVT)); 915 else 916 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 917 IntermediateVT, Val, 918 DAG.getConstant(i, PtrVT)); 919 920 // Split the intermediate operands into legal parts. 921 if (NumParts == NumIntermediates) { 922 // If the register was not expanded, promote or copy the value, 923 // as appropriate. 924 for (unsigned i = 0; i != NumParts; ++i) 925 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 926 } else if (NumParts > 0) { 927 // If the intermediate type was expanded, split each the value into 928 // legal parts. 929 assert(NumParts % NumIntermediates == 0 && 930 "Must expand into a divisible number of parts!"); 931 unsigned Factor = NumParts / NumIntermediates; 932 for (unsigned i = 0; i != NumIntermediates; ++i) 933 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 934 } 935} 936 937 938SDOperand SelectionDAGLowering::getValue(const Value *V) { 939 SDOperand &N = NodeMap[V]; 940 if (N.Val) return N; 941 942 const Type *VTy = V->getType(); 943 MVT::ValueType VT = TLI.getValueType(VTy); 944 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 945 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 946 visit(CE->getOpcode(), *CE); 947 SDOperand N1 = NodeMap[V]; 948 assert(N1.Val && "visit didn't populate the ValueMap!"); 949 return N1; 950 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 951 return N = DAG.getGlobalAddress(GV, VT); 952 } else if (isa<ConstantPointerNull>(C)) { 953 return N = DAG.getConstant(0, TLI.getPointerTy()); 954 } else if (isa<UndefValue>(C)) { 955 if (!isa<VectorType>(VTy)) 956 return N = DAG.getNode(ISD::UNDEF, VT); 957 958 // Create a BUILD_VECTOR of undef nodes. 959 const VectorType *PTy = cast<VectorType>(VTy); 960 unsigned NumElements = PTy->getNumElements(); 961 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 962 963 SmallVector<SDOperand, 8> Ops; 964 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 965 966 // Create a VConstant node with generic Vector type. 967 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 968 return N = DAG.getNode(ISD::BUILD_VECTOR, VT, 969 &Ops[0], Ops.size()); 970 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 971 return N = DAG.getConstantFP(CFP->getValueAPF(), VT); 972 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 973 unsigned NumElements = PTy->getNumElements(); 974 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 975 976 // Now that we know the number and type of the elements, push a 977 // Constant or ConstantFP node onto the ops list for each element of 978 // the vector constant. 979 SmallVector<SDOperand, 8> Ops; 980 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 981 for (unsigned i = 0; i != NumElements; ++i) 982 Ops.push_back(getValue(CP->getOperand(i))); 983 } else { 984 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 985 SDOperand Op; 986 if (MVT::isFloatingPoint(PVT)) 987 Op = DAG.getConstantFP(0, PVT); 988 else 989 Op = DAG.getConstant(0, PVT); 990 Ops.assign(NumElements, Op); 991 } 992 993 // Create a BUILD_VECTOR node. 994 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 995 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], 996 Ops.size()); 997 } else { 998 // Canonicalize all constant ints to be unsigned. 999 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT); 1000 } 1001 } 1002 1003 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1004 std::map<const AllocaInst*, int>::iterator SI = 1005 FuncInfo.StaticAllocaMap.find(AI); 1006 if (SI != FuncInfo.StaticAllocaMap.end()) 1007 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1008 } 1009 1010 unsigned InReg = FuncInfo.ValueMap[V]; 1011 assert(InReg && "Value not in map!"); 1012 1013 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 1014 unsigned NumRegs = TLI.getNumRegisters(VT); 1015 1016 std::vector<unsigned> Regs(NumRegs); 1017 for (unsigned i = 0; i != NumRegs; ++i) 1018 Regs[i] = InReg + i; 1019 1020 RegsForValue RFV(Regs, RegisterVT, VT); 1021 SDOperand Chain = DAG.getEntryNode(); 1022 1023 return RFV.getCopyFromRegs(DAG, Chain, NULL); 1024} 1025 1026 1027void SelectionDAGLowering::visitRet(ReturnInst &I) { 1028 if (I.getNumOperands() == 0) { 1029 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 1030 return; 1031 } 1032 SmallVector<SDOperand, 8> NewValues; 1033 NewValues.push_back(getRoot()); 1034 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 1035 SDOperand RetOp = getValue(I.getOperand(i)); 1036 MVT::ValueType VT = RetOp.getValueType(); 1037 1038 // FIXME: C calling convention requires the return type to be promoted to 1039 // at least 32-bit. But this is not necessary for non-C calling conventions. 1040 if (MVT::isInteger(VT)) { 1041 MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32); 1042 if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT)) 1043 VT = MinVT; 1044 } 1045 1046 unsigned NumParts = TLI.getNumRegisters(VT); 1047 MVT::ValueType PartVT = TLI.getRegisterType(VT); 1048 SmallVector<SDOperand, 4> Parts(NumParts); 1049 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1050 1051 const Function *F = I.getParent()->getParent(); 1052 if (F->paramHasAttr(0, ParamAttr::SExt)) 1053 ExtendKind = ISD::SIGN_EXTEND; 1054 else if (F->paramHasAttr(0, ParamAttr::ZExt)) 1055 ExtendKind = ISD::ZERO_EXTEND; 1056 1057 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, ExtendKind); 1058 1059 for (unsigned i = 0; i < NumParts; ++i) { 1060 NewValues.push_back(Parts[i]); 1061 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 1062 } 1063 } 1064 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 1065 &NewValues[0], NewValues.size())); 1066} 1067 1068/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1069/// the current basic block, add it to ValueMap now so that we'll get a 1070/// CopyTo/FromReg. 1071void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 1072 // No need to export constants. 1073 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1074 1075 // Already exported? 1076 if (FuncInfo.isExportedInst(V)) return; 1077 1078 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1079 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 1080} 1081 1082bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 1083 const BasicBlock *FromBB) { 1084 // The operands of the setcc have to be in this block. We don't know 1085 // how to export them from some other block. 1086 if (Instruction *VI = dyn_cast<Instruction>(V)) { 1087 // Can export from current BB. 1088 if (VI->getParent() == FromBB) 1089 return true; 1090 1091 // Is already exported, noop. 1092 return FuncInfo.isExportedInst(V); 1093 } 1094 1095 // If this is an argument, we can export it if the BB is the entry block or 1096 // if it is already exported. 1097 if (isa<Argument>(V)) { 1098 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1099 return true; 1100 1101 // Otherwise, can only export this if it is already exported. 1102 return FuncInfo.isExportedInst(V); 1103 } 1104 1105 // Otherwise, constants can always be exported. 1106 return true; 1107} 1108 1109static bool InBlock(const Value *V, const BasicBlock *BB) { 1110 if (const Instruction *I = dyn_cast<Instruction>(V)) 1111 return I->getParent() == BB; 1112 return true; 1113} 1114 1115/// FindMergedConditions - If Cond is an expression like 1116void SelectionDAGLowering::FindMergedConditions(Value *Cond, 1117 MachineBasicBlock *TBB, 1118 MachineBasicBlock *FBB, 1119 MachineBasicBlock *CurBB, 1120 unsigned Opc) { 1121 // If this node is not part of the or/and tree, emit it as a branch. 1122 Instruction *BOp = dyn_cast<Instruction>(Cond); 1123 1124 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1125 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1126 BOp->getParent() != CurBB->getBasicBlock() || 1127 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1128 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1129 const BasicBlock *BB = CurBB->getBasicBlock(); 1130 1131 // If the leaf of the tree is a comparison, merge the condition into 1132 // the caseblock. 1133 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1134 // The operands of the cmp have to be in this block. We don't know 1135 // how to export them from some other block. If this is the first block 1136 // of the sequence, no exporting is needed. 1137 (CurBB == CurMBB || 1138 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1139 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1140 BOp = cast<Instruction>(Cond); 1141 ISD::CondCode Condition; 1142 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1143 switch (IC->getPredicate()) { 1144 default: assert(0 && "Unknown icmp predicate opcode!"); 1145 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1146 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1147 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1148 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1149 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1150 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1151 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1152 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1153 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1154 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1155 } 1156 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1157 ISD::CondCode FPC, FOC; 1158 switch (FC->getPredicate()) { 1159 default: assert(0 && "Unknown fcmp predicate opcode!"); 1160 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1161 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1162 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1163 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1164 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1165 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1166 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1167 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 1168 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 1169 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1170 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1171 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1172 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1173 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1174 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1175 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1176 } 1177 if (FiniteOnlyFPMath()) 1178 Condition = FOC; 1179 else 1180 Condition = FPC; 1181 } else { 1182 Condition = ISD::SETEQ; // silence warning. 1183 assert(0 && "Unknown compare instruction"); 1184 } 1185 1186 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1187 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1188 SwitchCases.push_back(CB); 1189 return; 1190 } 1191 1192 // Create a CaseBlock record representing this branch. 1193 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1194 NULL, TBB, FBB, CurBB); 1195 SwitchCases.push_back(CB); 1196 return; 1197 } 1198 1199 1200 // Create TmpBB after CurBB. 1201 MachineFunction::iterator BBI = CurBB; 1202 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 1203 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 1204 1205 if (Opc == Instruction::Or) { 1206 // Codegen X | Y as: 1207 // jmp_if_X TBB 1208 // jmp TmpBB 1209 // TmpBB: 1210 // jmp_if_Y TBB 1211 // jmp FBB 1212 // 1213 1214 // Emit the LHS condition. 1215 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1216 1217 // Emit the RHS condition into TmpBB. 1218 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1219 } else { 1220 assert(Opc == Instruction::And && "Unknown merge op!"); 1221 // Codegen X & Y as: 1222 // jmp_if_X TmpBB 1223 // jmp FBB 1224 // TmpBB: 1225 // jmp_if_Y TBB 1226 // jmp FBB 1227 // 1228 // This requires creation of TmpBB after CurBB. 1229 1230 // Emit the LHS condition. 1231 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1232 1233 // Emit the RHS condition into TmpBB. 1234 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1235 } 1236} 1237 1238/// If the set of cases should be emitted as a series of branches, return true. 1239/// If we should emit this as a bunch of and/or'd together conditions, return 1240/// false. 1241static bool 1242ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1243 if (Cases.size() != 2) return true; 1244 1245 // If this is two comparisons of the same values or'd or and'd together, they 1246 // will get folded into a single comparison, so don't emit two blocks. 1247 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1248 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1249 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1250 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1251 return false; 1252 } 1253 1254 return true; 1255} 1256 1257void SelectionDAGLowering::visitBr(BranchInst &I) { 1258 // Update machine-CFG edges. 1259 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1260 1261 // Figure out which block is immediately after the current one. 1262 MachineBasicBlock *NextBlock = 0; 1263 MachineFunction::iterator BBI = CurMBB; 1264 if (++BBI != CurMBB->getParent()->end()) 1265 NextBlock = BBI; 1266 1267 if (I.isUnconditional()) { 1268 // If this is not a fall-through branch, emit the branch. 1269 if (Succ0MBB != NextBlock) 1270 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1271 DAG.getBasicBlock(Succ0MBB))); 1272 1273 // Update machine-CFG edges. 1274 CurMBB->addSuccessor(Succ0MBB); 1275 return; 1276 } 1277 1278 // If this condition is one of the special cases we handle, do special stuff 1279 // now. 1280 Value *CondVal = I.getCondition(); 1281 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1282 1283 // If this is a series of conditions that are or'd or and'd together, emit 1284 // this as a sequence of branches instead of setcc's with and/or operations. 1285 // For example, instead of something like: 1286 // cmp A, B 1287 // C = seteq 1288 // cmp D, E 1289 // F = setle 1290 // or C, F 1291 // jnz foo 1292 // Emit: 1293 // cmp A, B 1294 // je foo 1295 // cmp D, E 1296 // jle foo 1297 // 1298 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1299 if (BOp->hasOneUse() && 1300 (BOp->getOpcode() == Instruction::And || 1301 BOp->getOpcode() == Instruction::Or)) { 1302 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1303 // If the compares in later blocks need to use values not currently 1304 // exported from this block, export them now. This block should always 1305 // be the first entry. 1306 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1307 1308 // Allow some cases to be rejected. 1309 if (ShouldEmitAsBranches(SwitchCases)) { 1310 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1311 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1312 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1313 } 1314 1315 // Emit the branch for this block. 1316 visitSwitchCase(SwitchCases[0]); 1317 SwitchCases.erase(SwitchCases.begin()); 1318 return; 1319 } 1320 1321 // Okay, we decided not to do this, remove any inserted MBB's and clear 1322 // SwitchCases. 1323 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1324 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1325 1326 SwitchCases.clear(); 1327 } 1328 } 1329 1330 // Create a CaseBlock record representing this branch. 1331 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1332 NULL, Succ0MBB, Succ1MBB, CurMBB); 1333 // Use visitSwitchCase to actually insert the fast branch sequence for this 1334 // cond branch. 1335 visitSwitchCase(CB); 1336} 1337 1338/// visitSwitchCase - Emits the necessary code to represent a single node in 1339/// the binary search tree resulting from lowering a switch instruction. 1340void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1341 SDOperand Cond; 1342 SDOperand CondLHS = getValue(CB.CmpLHS); 1343 1344 // Build the setcc now. 1345 if (CB.CmpMHS == NULL) { 1346 // Fold "(X == true)" to X and "(X == false)" to !X to 1347 // handle common cases produced by branch lowering. 1348 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1349 Cond = CondLHS; 1350 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1351 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1352 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1353 } else 1354 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1355 } else { 1356 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1357 1358 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1359 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1360 1361 SDOperand CmpOp = getValue(CB.CmpMHS); 1362 MVT::ValueType VT = CmpOp.getValueType(); 1363 1364 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1365 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1366 } else { 1367 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1368 Cond = DAG.getSetCC(MVT::i1, SUB, 1369 DAG.getConstant(High-Low, VT), ISD::SETULE); 1370 } 1371 1372 } 1373 1374 // Set NextBlock to be the MBB immediately after the current one, if any. 1375 // This is used to avoid emitting unnecessary branches to the next block. 1376 MachineBasicBlock *NextBlock = 0; 1377 MachineFunction::iterator BBI = CurMBB; 1378 if (++BBI != CurMBB->getParent()->end()) 1379 NextBlock = BBI; 1380 1381 // If the lhs block is the next block, invert the condition so that we can 1382 // fall through to the lhs instead of the rhs block. 1383 if (CB.TrueBB == NextBlock) { 1384 std::swap(CB.TrueBB, CB.FalseBB); 1385 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1386 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1387 } 1388 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1389 DAG.getBasicBlock(CB.TrueBB)); 1390 if (CB.FalseBB == NextBlock) 1391 DAG.setRoot(BrCond); 1392 else 1393 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1394 DAG.getBasicBlock(CB.FalseBB))); 1395 // Update successor info 1396 CurMBB->addSuccessor(CB.TrueBB); 1397 CurMBB->addSuccessor(CB.FalseBB); 1398} 1399 1400/// visitJumpTable - Emit JumpTable node in the current MBB 1401void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1402 // Emit the code for the jump table 1403 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1404 MVT::ValueType PTy = TLI.getPointerTy(); 1405 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1406 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1407 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1408 Table, Index)); 1409 return; 1410} 1411 1412/// visitJumpTableHeader - This function emits necessary code to produce index 1413/// in the JumpTable from switch case. 1414void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1415 SelectionDAGISel::JumpTableHeader &JTH) { 1416 // Subtract the lowest switch case value from the value being switched on 1417 // and conditional branch to default mbb if the result is greater than the 1418 // difference between smallest and largest cases. 1419 SDOperand SwitchOp = getValue(JTH.SValue); 1420 MVT::ValueType VT = SwitchOp.getValueType(); 1421 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1422 DAG.getConstant(JTH.First, VT)); 1423 1424 // The SDNode we just created, which holds the value being switched on 1425 // minus the the smallest case value, needs to be copied to a virtual 1426 // register so it can be used as an index into the jump table in a 1427 // subsequent basic block. This value may be smaller or larger than the 1428 // target's pointer type, and therefore require extension or truncating. 1429 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 1430 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1431 else 1432 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1433 1434 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1435 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1436 JT.Reg = JumpTableReg; 1437 1438 // Emit the range check for the jump table, and branch to the default 1439 // block for the switch statement if the value being switched on exceeds 1440 // the largest case in the switch. 1441 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1442 DAG.getConstant(JTH.Last-JTH.First,VT), 1443 ISD::SETUGT); 1444 1445 // Set NextBlock to be the MBB immediately after the current one, if any. 1446 // This is used to avoid emitting unnecessary branches to the next block. 1447 MachineBasicBlock *NextBlock = 0; 1448 MachineFunction::iterator BBI = CurMBB; 1449 if (++BBI != CurMBB->getParent()->end()) 1450 NextBlock = BBI; 1451 1452 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1453 DAG.getBasicBlock(JT.Default)); 1454 1455 if (JT.MBB == NextBlock) 1456 DAG.setRoot(BrCond); 1457 else 1458 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1459 DAG.getBasicBlock(JT.MBB))); 1460 1461 return; 1462} 1463 1464/// visitBitTestHeader - This function emits necessary code to produce value 1465/// suitable for "bit tests" 1466void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1467 // Subtract the minimum value 1468 SDOperand SwitchOp = getValue(B.SValue); 1469 MVT::ValueType VT = SwitchOp.getValueType(); 1470 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1471 DAG.getConstant(B.First, VT)); 1472 1473 // Check range 1474 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1475 DAG.getConstant(B.Range, VT), 1476 ISD::SETUGT); 1477 1478 SDOperand ShiftOp; 1479 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy())) 1480 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1481 else 1482 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1483 1484 // Make desired shift 1485 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1486 DAG.getConstant(1, TLI.getPointerTy()), 1487 ShiftOp); 1488 1489 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1490 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1491 B.Reg = SwitchReg; 1492 1493 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1494 DAG.getBasicBlock(B.Default)); 1495 1496 // Set NextBlock to be the MBB immediately after the current one, if any. 1497 // This is used to avoid emitting unnecessary branches to the next block. 1498 MachineBasicBlock *NextBlock = 0; 1499 MachineFunction::iterator BBI = CurMBB; 1500 if (++BBI != CurMBB->getParent()->end()) 1501 NextBlock = BBI; 1502 1503 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1504 if (MBB == NextBlock) 1505 DAG.setRoot(BrRange); 1506 else 1507 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1508 DAG.getBasicBlock(MBB))); 1509 1510 CurMBB->addSuccessor(B.Default); 1511 CurMBB->addSuccessor(MBB); 1512 1513 return; 1514} 1515 1516/// visitBitTestCase - this function produces one "bit test" 1517void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1518 unsigned Reg, 1519 SelectionDAGISel::BitTestCase &B) { 1520 // Emit bit tests and jumps 1521 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1522 1523 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1524 SwitchVal, 1525 DAG.getConstant(B.Mask, 1526 TLI.getPointerTy())); 1527 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, 1528 DAG.getConstant(0, TLI.getPointerTy()), 1529 ISD::SETNE); 1530 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1531 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1532 1533 // Set NextBlock to be the MBB immediately after the current one, if any. 1534 // This is used to avoid emitting unnecessary branches to the next block. 1535 MachineBasicBlock *NextBlock = 0; 1536 MachineFunction::iterator BBI = CurMBB; 1537 if (++BBI != CurMBB->getParent()->end()) 1538 NextBlock = BBI; 1539 1540 if (NextMBB == NextBlock) 1541 DAG.setRoot(BrAnd); 1542 else 1543 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1544 DAG.getBasicBlock(NextMBB))); 1545 1546 CurMBB->addSuccessor(B.TargetBB); 1547 CurMBB->addSuccessor(NextMBB); 1548 1549 return; 1550} 1551 1552void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1553 // Retrieve successors. 1554 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1555 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1556 1557 if (isa<InlineAsm>(I.getCalledValue())) 1558 visitInlineAsm(&I); 1559 else 1560 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad); 1561 1562 // If the value of the invoke is used outside of its defining block, make it 1563 // available as a virtual register. 1564 if (!I.use_empty()) { 1565 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1566 if (VMI != FuncInfo.ValueMap.end()) 1567 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second)); 1568 } 1569 1570 // Drop into normal successor. 1571 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1572 DAG.getBasicBlock(Return))); 1573 1574 // Update successor info 1575 CurMBB->addSuccessor(Return); 1576 CurMBB->addSuccessor(LandingPad); 1577} 1578 1579void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1580} 1581 1582/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1583/// small case ranges). 1584bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1585 CaseRecVector& WorkList, 1586 Value* SV, 1587 MachineBasicBlock* Default) { 1588 Case& BackCase = *(CR.Range.second-1); 1589 1590 // Size is the number of Cases represented by this range. 1591 unsigned Size = CR.Range.second - CR.Range.first; 1592 if (Size > 3) 1593 return false; 1594 1595 // Get the MachineFunction which holds the current MBB. This is used when 1596 // inserting any additional MBBs necessary to represent the switch. 1597 MachineFunction *CurMF = CurMBB->getParent(); 1598 1599 // Figure out which block is immediately after the current one. 1600 MachineBasicBlock *NextBlock = 0; 1601 MachineFunction::iterator BBI = CR.CaseBB; 1602 1603 if (++BBI != CurMBB->getParent()->end()) 1604 NextBlock = BBI; 1605 1606 // TODO: If any two of the cases has the same destination, and if one value 1607 // is the same as the other, but has one bit unset that the other has set, 1608 // use bit manipulation to do two compares at once. For example: 1609 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1610 1611 // Rearrange the case blocks so that the last one falls through if possible. 1612 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1613 // The last case block won't fall through into 'NextBlock' if we emit the 1614 // branches in this order. See if rearranging a case value would help. 1615 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1616 if (I->BB == NextBlock) { 1617 std::swap(*I, BackCase); 1618 break; 1619 } 1620 } 1621 } 1622 1623 // Create a CaseBlock record representing a conditional branch to 1624 // the Case's target mbb if the value being switched on SV is equal 1625 // to C. 1626 MachineBasicBlock *CurBlock = CR.CaseBB; 1627 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1628 MachineBasicBlock *FallThrough; 1629 if (I != E-1) { 1630 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1631 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1632 } else { 1633 // If the last case doesn't match, go to the default block. 1634 FallThrough = Default; 1635 } 1636 1637 Value *RHS, *LHS, *MHS; 1638 ISD::CondCode CC; 1639 if (I->High == I->Low) { 1640 // This is just small small case range :) containing exactly 1 case 1641 CC = ISD::SETEQ; 1642 LHS = SV; RHS = I->High; MHS = NULL; 1643 } else { 1644 CC = ISD::SETLE; 1645 LHS = I->Low; MHS = SV; RHS = I->High; 1646 } 1647 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1648 I->BB, FallThrough, CurBlock); 1649 1650 // If emitting the first comparison, just call visitSwitchCase to emit the 1651 // code into the current block. Otherwise, push the CaseBlock onto the 1652 // vector to be later processed by SDISel, and insert the node's MBB 1653 // before the next MBB. 1654 if (CurBlock == CurMBB) 1655 visitSwitchCase(CB); 1656 else 1657 SwitchCases.push_back(CB); 1658 1659 CurBlock = FallThrough; 1660 } 1661 1662 return true; 1663} 1664 1665static inline bool areJTsAllowed(const TargetLowering &TLI) { 1666 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1667 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1668} 1669 1670/// handleJTSwitchCase - Emit jumptable for current switch case range 1671bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1672 CaseRecVector& WorkList, 1673 Value* SV, 1674 MachineBasicBlock* Default) { 1675 Case& FrontCase = *CR.Range.first; 1676 Case& BackCase = *(CR.Range.second-1); 1677 1678 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1679 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1680 1681 uint64_t TSize = 0; 1682 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1683 I!=E; ++I) 1684 TSize += I->size(); 1685 1686 if (!areJTsAllowed(TLI) || TSize <= 3) 1687 return false; 1688 1689 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1690 if (Density < 0.4) 1691 return false; 1692 1693 DOUT << "Lowering jump table\n" 1694 << "First entry: " << First << ". Last entry: " << Last << "\n" 1695 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1696 1697 // Get the MachineFunction which holds the current MBB. This is used when 1698 // inserting any additional MBBs necessary to represent the switch. 1699 MachineFunction *CurMF = CurMBB->getParent(); 1700 1701 // Figure out which block is immediately after the current one. 1702 MachineBasicBlock *NextBlock = 0; 1703 MachineFunction::iterator BBI = CR.CaseBB; 1704 1705 if (++BBI != CurMBB->getParent()->end()) 1706 NextBlock = BBI; 1707 1708 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1709 1710 // Create a new basic block to hold the code for loading the address 1711 // of the jump table, and jumping to it. Update successor information; 1712 // we will either branch to the default case for the switch, or the jump 1713 // table. 1714 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1715 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1716 CR.CaseBB->addSuccessor(Default); 1717 CR.CaseBB->addSuccessor(JumpTableBB); 1718 1719 // Build a vector of destination BBs, corresponding to each target 1720 // of the jump table. If the value of the jump table slot corresponds to 1721 // a case statement, push the case's BB onto the vector, otherwise, push 1722 // the default BB. 1723 std::vector<MachineBasicBlock*> DestBBs; 1724 int64_t TEI = First; 1725 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1726 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1727 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1728 1729 if ((Low <= TEI) && (TEI <= High)) { 1730 DestBBs.push_back(I->BB); 1731 if (TEI==High) 1732 ++I; 1733 } else { 1734 DestBBs.push_back(Default); 1735 } 1736 } 1737 1738 // Update successor info. Add one edge to each unique successor. 1739 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1740 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1741 E = DestBBs.end(); I != E; ++I) { 1742 if (!SuccsHandled[(*I)->getNumber()]) { 1743 SuccsHandled[(*I)->getNumber()] = true; 1744 JumpTableBB->addSuccessor(*I); 1745 } 1746 } 1747 1748 // Create a jump table index for this jump table, or return an existing 1749 // one. 1750 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1751 1752 // Set the jump table information so that we can codegen it as a second 1753 // MachineBasicBlock 1754 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1755 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1756 (CR.CaseBB == CurMBB)); 1757 if (CR.CaseBB == CurMBB) 1758 visitJumpTableHeader(JT, JTH); 1759 1760 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1761 1762 return true; 1763} 1764 1765/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1766/// 2 subtrees. 1767bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1768 CaseRecVector& WorkList, 1769 Value* SV, 1770 MachineBasicBlock* Default) { 1771 // Get the MachineFunction which holds the current MBB. This is used when 1772 // inserting any additional MBBs necessary to represent the switch. 1773 MachineFunction *CurMF = CurMBB->getParent(); 1774 1775 // Figure out which block is immediately after the current one. 1776 MachineBasicBlock *NextBlock = 0; 1777 MachineFunction::iterator BBI = CR.CaseBB; 1778 1779 if (++BBI != CurMBB->getParent()->end()) 1780 NextBlock = BBI; 1781 1782 Case& FrontCase = *CR.Range.first; 1783 Case& BackCase = *(CR.Range.second-1); 1784 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1785 1786 // Size is the number of Cases represented by this range. 1787 unsigned Size = CR.Range.second - CR.Range.first; 1788 1789 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1790 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1791 double FMetric = 0; 1792 CaseItr Pivot = CR.Range.first + Size/2; 1793 1794 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1795 // (heuristically) allow us to emit JumpTable's later. 1796 uint64_t TSize = 0; 1797 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1798 I!=E; ++I) 1799 TSize += I->size(); 1800 1801 uint64_t LSize = FrontCase.size(); 1802 uint64_t RSize = TSize-LSize; 1803 DOUT << "Selecting best pivot: \n" 1804 << "First: " << First << ", Last: " << Last <<"\n" 1805 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1806 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1807 J!=E; ++I, ++J) { 1808 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1809 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1810 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1811 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1812 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1813 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1814 // Should always split in some non-trivial place 1815 DOUT <<"=>Step\n" 1816 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1817 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1818 << "Metric: " << Metric << "\n"; 1819 if (FMetric < Metric) { 1820 Pivot = J; 1821 FMetric = Metric; 1822 DOUT << "Current metric set to: " << FMetric << "\n"; 1823 } 1824 1825 LSize += J->size(); 1826 RSize -= J->size(); 1827 } 1828 if (areJTsAllowed(TLI)) { 1829 // If our case is dense we *really* should handle it earlier! 1830 assert((FMetric > 0) && "Should handle dense range earlier!"); 1831 } else { 1832 Pivot = CR.Range.first + Size/2; 1833 } 1834 1835 CaseRange LHSR(CR.Range.first, Pivot); 1836 CaseRange RHSR(Pivot, CR.Range.second); 1837 Constant *C = Pivot->Low; 1838 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1839 1840 // We know that we branch to the LHS if the Value being switched on is 1841 // less than the Pivot value, C. We use this to optimize our binary 1842 // tree a bit, by recognizing that if SV is greater than or equal to the 1843 // LHS's Case Value, and that Case Value is exactly one less than the 1844 // Pivot's Value, then we can branch directly to the LHS's Target, 1845 // rather than creating a leaf node for it. 1846 if ((LHSR.second - LHSR.first) == 1 && 1847 LHSR.first->High == CR.GE && 1848 cast<ConstantInt>(C)->getSExtValue() == 1849 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1850 TrueBB = LHSR.first->BB; 1851 } else { 1852 TrueBB = new MachineBasicBlock(LLVMBB); 1853 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1854 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1855 } 1856 1857 // Similar to the optimization above, if the Value being switched on is 1858 // known to be less than the Constant CR.LT, and the current Case Value 1859 // is CR.LT - 1, then we can branch directly to the target block for 1860 // the current Case Value, rather than emitting a RHS leaf node for it. 1861 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1862 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1863 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1864 FalseBB = RHSR.first->BB; 1865 } else { 1866 FalseBB = new MachineBasicBlock(LLVMBB); 1867 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1868 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1869 } 1870 1871 // Create a CaseBlock record representing a conditional branch to 1872 // the LHS node if the value being switched on SV is less than C. 1873 // Otherwise, branch to LHS. 1874 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1875 TrueBB, FalseBB, CR.CaseBB); 1876 1877 if (CR.CaseBB == CurMBB) 1878 visitSwitchCase(CB); 1879 else 1880 SwitchCases.push_back(CB); 1881 1882 return true; 1883} 1884 1885/// handleBitTestsSwitchCase - if current case range has few destination and 1886/// range span less, than machine word bitwidth, encode case range into series 1887/// of masks and emit bit tests with these masks. 1888bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1889 CaseRecVector& WorkList, 1890 Value* SV, 1891 MachineBasicBlock* Default){ 1892 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); 1893 1894 Case& FrontCase = *CR.Range.first; 1895 Case& BackCase = *(CR.Range.second-1); 1896 1897 // Get the MachineFunction which holds the current MBB. This is used when 1898 // inserting any additional MBBs necessary to represent the switch. 1899 MachineFunction *CurMF = CurMBB->getParent(); 1900 1901 unsigned numCmps = 0; 1902 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1903 I!=E; ++I) { 1904 // Single case counts one, case range - two. 1905 if (I->Low == I->High) 1906 numCmps +=1; 1907 else 1908 numCmps +=2; 1909 } 1910 1911 // Count unique destinations 1912 SmallSet<MachineBasicBlock*, 4> Dests; 1913 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1914 Dests.insert(I->BB); 1915 if (Dests.size() > 3) 1916 // Don't bother the code below, if there are too much unique destinations 1917 return false; 1918 } 1919 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1920 << "Total number of comparisons: " << numCmps << "\n"; 1921 1922 // Compute span of values. 1923 Constant* minValue = FrontCase.Low; 1924 Constant* maxValue = BackCase.High; 1925 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1926 cast<ConstantInt>(minValue)->getSExtValue(); 1927 DOUT << "Compare range: " << range << "\n" 1928 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1929 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1930 1931 if (range>=IntPtrBits || 1932 (!(Dests.size() == 1 && numCmps >= 3) && 1933 !(Dests.size() == 2 && numCmps >= 5) && 1934 !(Dests.size() >= 3 && numCmps >= 6))) 1935 return false; 1936 1937 DOUT << "Emitting bit tests\n"; 1938 int64_t lowBound = 0; 1939 1940 // Optimize the case where all the case values fit in a 1941 // word without having to subtract minValue. In this case, 1942 // we can optimize away the subtraction. 1943 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1944 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1945 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1946 } else { 1947 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1948 } 1949 1950 CaseBitsVector CasesBits; 1951 unsigned i, count = 0; 1952 1953 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1954 MachineBasicBlock* Dest = I->BB; 1955 for (i = 0; i < count; ++i) 1956 if (Dest == CasesBits[i].BB) 1957 break; 1958 1959 if (i == count) { 1960 assert((count < 3) && "Too much destinations to test!"); 1961 CasesBits.push_back(CaseBits(0, Dest, 0)); 1962 count++; 1963 } 1964 1965 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1966 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1967 1968 for (uint64_t j = lo; j <= hi; j++) { 1969 CasesBits[i].Mask |= 1ULL << j; 1970 CasesBits[i].Bits++; 1971 } 1972 1973 } 1974 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1975 1976 SelectionDAGISel::BitTestInfo BTC; 1977 1978 // Figure out which block is immediately after the current one. 1979 MachineFunction::iterator BBI = CR.CaseBB; 1980 ++BBI; 1981 1982 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1983 1984 DOUT << "Cases:\n"; 1985 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1986 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1987 << ", BB: " << CasesBits[i].BB << "\n"; 1988 1989 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1990 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1991 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1992 CaseBB, 1993 CasesBits[i].BB)); 1994 } 1995 1996 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 1997 -1U, (CR.CaseBB == CurMBB), 1998 CR.CaseBB, Default, BTC); 1999 2000 if (CR.CaseBB == CurMBB) 2001 visitBitTestHeader(BTB); 2002 2003 BitTestCases.push_back(BTB); 2004 2005 return true; 2006} 2007 2008 2009// Clusterify - Transform simple list of Cases into list of CaseRange's 2010unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 2011 const SwitchInst& SI) { 2012 unsigned numCmps = 0; 2013 2014 // Start with "simple" cases 2015 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 2016 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2017 Cases.push_back(Case(SI.getSuccessorValue(i), 2018 SI.getSuccessorValue(i), 2019 SMBB)); 2020 } 2021 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2022 2023 // Merge case into clusters 2024 if (Cases.size()>=2) 2025 // Must recompute end() each iteration because it may be 2026 // invalidated by erase if we hold on to it 2027 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 2028 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 2029 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 2030 MachineBasicBlock* nextBB = J->BB; 2031 MachineBasicBlock* currentBB = I->BB; 2032 2033 // If the two neighboring cases go to the same destination, merge them 2034 // into a single case. 2035 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 2036 I->High = J->High; 2037 J = Cases.erase(J); 2038 } else { 2039 I = J++; 2040 } 2041 } 2042 2043 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2044 if (I->Low != I->High) 2045 // A range counts double, since it requires two compares. 2046 ++numCmps; 2047 } 2048 2049 return numCmps; 2050} 2051 2052void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 2053 // Figure out which block is immediately after the current one. 2054 MachineBasicBlock *NextBlock = 0; 2055 MachineFunction::iterator BBI = CurMBB; 2056 2057 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2058 2059 // If there is only the default destination, branch to it if it is not the 2060 // next basic block. Otherwise, just fall through. 2061 if (SI.getNumOperands() == 2) { 2062 // Update machine-CFG edges. 2063 2064 // If this is not a fall-through branch, emit the branch. 2065 if (Default != NextBlock) 2066 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 2067 DAG.getBasicBlock(Default))); 2068 2069 CurMBB->addSuccessor(Default); 2070 return; 2071 } 2072 2073 // If there are any non-default case statements, create a vector of Cases 2074 // representing each one, and sort the vector so that we can efficiently 2075 // create a binary search tree from them. 2076 CaseVector Cases; 2077 unsigned numCmps = Clusterify(Cases, SI); 2078 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 2079 << ". Total compares: " << numCmps << "\n"; 2080 2081 // Get the Value to be switched on and default basic blocks, which will be 2082 // inserted into CaseBlock records, representing basic blocks in the binary 2083 // search tree. 2084 Value *SV = SI.getOperand(0); 2085 2086 // Push the initial CaseRec onto the worklist 2087 CaseRecVector WorkList; 2088 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 2089 2090 while (!WorkList.empty()) { 2091 // Grab a record representing a case range to process off the worklist 2092 CaseRec CR = WorkList.back(); 2093 WorkList.pop_back(); 2094 2095 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 2096 continue; 2097 2098 // If the range has few cases (two or less) emit a series of specific 2099 // tests. 2100 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 2101 continue; 2102 2103 // If the switch has more than 5 blocks, and at least 40% dense, and the 2104 // target supports indirect branches, then emit a jump table rather than 2105 // lowering the switch to a binary tree of conditional branches. 2106 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 2107 continue; 2108 2109 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2110 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2111 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 2112 } 2113} 2114 2115 2116void SelectionDAGLowering::visitSub(User &I) { 2117 // -0.0 - X --> fneg 2118 const Type *Ty = I.getType(); 2119 if (isa<VectorType>(Ty)) { 2120 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2121 const VectorType *DestTy = cast<VectorType>(I.getType()); 2122 const Type *ElTy = DestTy->getElementType(); 2123 if (ElTy->isFloatingPoint()) { 2124 unsigned VL = DestTy->getNumElements(); 2125 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2126 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2127 if (CV == CNZ) { 2128 SDOperand Op2 = getValue(I.getOperand(1)); 2129 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2130 return; 2131 } 2132 } 2133 } 2134 } 2135 if (Ty->isFloatingPoint()) { 2136 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2137 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2138 SDOperand Op2 = getValue(I.getOperand(1)); 2139 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2140 return; 2141 } 2142 } 2143 2144 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2145} 2146 2147void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2148 SDOperand Op1 = getValue(I.getOperand(0)); 2149 SDOperand Op2 = getValue(I.getOperand(1)); 2150 2151 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2152} 2153 2154void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2155 SDOperand Op1 = getValue(I.getOperand(0)); 2156 SDOperand Op2 = getValue(I.getOperand(1)); 2157 2158 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) < 2159 MVT::getSizeInBits(Op2.getValueType())) 2160 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2161 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 2162 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2163 2164 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2165} 2166 2167void SelectionDAGLowering::visitICmp(User &I) { 2168 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2169 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2170 predicate = IC->getPredicate(); 2171 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2172 predicate = ICmpInst::Predicate(IC->getPredicate()); 2173 SDOperand Op1 = getValue(I.getOperand(0)); 2174 SDOperand Op2 = getValue(I.getOperand(1)); 2175 ISD::CondCode Opcode; 2176 switch (predicate) { 2177 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2178 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2179 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2180 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2181 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2182 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2183 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2184 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2185 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2186 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2187 default: 2188 assert(!"Invalid ICmp predicate value"); 2189 Opcode = ISD::SETEQ; 2190 break; 2191 } 2192 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2193} 2194 2195void SelectionDAGLowering::visitFCmp(User &I) { 2196 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2197 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2198 predicate = FC->getPredicate(); 2199 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2200 predicate = FCmpInst::Predicate(FC->getPredicate()); 2201 SDOperand Op1 = getValue(I.getOperand(0)); 2202 SDOperand Op2 = getValue(I.getOperand(1)); 2203 ISD::CondCode Condition, FOC, FPC; 2204 switch (predicate) { 2205 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2206 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2207 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2208 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2209 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2210 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2211 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2212 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 2213 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 2214 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2215 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2216 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2217 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2218 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2219 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2220 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2221 default: 2222 assert(!"Invalid FCmp predicate value"); 2223 FOC = FPC = ISD::SETFALSE; 2224 break; 2225 } 2226 if (FiniteOnlyFPMath()) 2227 Condition = FOC; 2228 else 2229 Condition = FPC; 2230 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2231} 2232 2233void SelectionDAGLowering::visitSelect(User &I) { 2234 SDOperand Cond = getValue(I.getOperand(0)); 2235 SDOperand TrueVal = getValue(I.getOperand(1)); 2236 SDOperand FalseVal = getValue(I.getOperand(2)); 2237 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2238 TrueVal, FalseVal)); 2239} 2240 2241 2242void SelectionDAGLowering::visitTrunc(User &I) { 2243 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2244 SDOperand N = getValue(I.getOperand(0)); 2245 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2246 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2247} 2248 2249void SelectionDAGLowering::visitZExt(User &I) { 2250 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2251 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2252 SDOperand N = getValue(I.getOperand(0)); 2253 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2254 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2255} 2256 2257void SelectionDAGLowering::visitSExt(User &I) { 2258 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2259 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2260 SDOperand N = getValue(I.getOperand(0)); 2261 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2262 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2263} 2264 2265void SelectionDAGLowering::visitFPTrunc(User &I) { 2266 // FPTrunc is never a no-op cast, no need to check 2267 SDOperand N = getValue(I.getOperand(0)); 2268 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2269 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0))); 2270} 2271 2272void SelectionDAGLowering::visitFPExt(User &I){ 2273 // FPTrunc is never a no-op cast, no need to check 2274 SDOperand N = getValue(I.getOperand(0)); 2275 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2276 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2277} 2278 2279void SelectionDAGLowering::visitFPToUI(User &I) { 2280 // FPToUI is never a no-op cast, no need to check 2281 SDOperand N = getValue(I.getOperand(0)); 2282 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2283 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2284} 2285 2286void SelectionDAGLowering::visitFPToSI(User &I) { 2287 // FPToSI is never a no-op cast, no need to check 2288 SDOperand N = getValue(I.getOperand(0)); 2289 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2290 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2291} 2292 2293void SelectionDAGLowering::visitUIToFP(User &I) { 2294 // UIToFP is never a no-op cast, no need to check 2295 SDOperand N = getValue(I.getOperand(0)); 2296 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2297 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2298} 2299 2300void SelectionDAGLowering::visitSIToFP(User &I){ 2301 // UIToFP is never a no-op cast, no need to check 2302 SDOperand N = getValue(I.getOperand(0)); 2303 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2304 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2305} 2306 2307void SelectionDAGLowering::visitPtrToInt(User &I) { 2308 // What to do depends on the size of the integer and the size of the pointer. 2309 // We can either truncate, zero extend, or no-op, accordingly. 2310 SDOperand N = getValue(I.getOperand(0)); 2311 MVT::ValueType SrcVT = N.getValueType(); 2312 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2313 SDOperand Result; 2314 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2315 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2316 else 2317 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2318 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2319 setValue(&I, Result); 2320} 2321 2322void SelectionDAGLowering::visitIntToPtr(User &I) { 2323 // What to do depends on the size of the integer and the size of the pointer. 2324 // We can either truncate, zero extend, or no-op, accordingly. 2325 SDOperand N = getValue(I.getOperand(0)); 2326 MVT::ValueType SrcVT = N.getValueType(); 2327 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2328 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2329 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2330 else 2331 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2332 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2333} 2334 2335void SelectionDAGLowering::visitBitCast(User &I) { 2336 SDOperand N = getValue(I.getOperand(0)); 2337 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2338 2339 // BitCast assures us that source and destination are the same size so this 2340 // is either a BIT_CONVERT or a no-op. 2341 if (DestVT != N.getValueType()) 2342 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2343 else 2344 setValue(&I, N); // noop cast. 2345} 2346 2347void SelectionDAGLowering::visitInsertElement(User &I) { 2348 SDOperand InVec = getValue(I.getOperand(0)); 2349 SDOperand InVal = getValue(I.getOperand(1)); 2350 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2351 getValue(I.getOperand(2))); 2352 2353 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2354 TLI.getValueType(I.getType()), 2355 InVec, InVal, InIdx)); 2356} 2357 2358void SelectionDAGLowering::visitExtractElement(User &I) { 2359 SDOperand InVec = getValue(I.getOperand(0)); 2360 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2361 getValue(I.getOperand(1))); 2362 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2363 TLI.getValueType(I.getType()), InVec, InIdx)); 2364} 2365 2366void SelectionDAGLowering::visitShuffleVector(User &I) { 2367 SDOperand V1 = getValue(I.getOperand(0)); 2368 SDOperand V2 = getValue(I.getOperand(1)); 2369 SDOperand Mask = getValue(I.getOperand(2)); 2370 2371 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2372 TLI.getValueType(I.getType()), 2373 V1, V2, Mask)); 2374} 2375 2376 2377void SelectionDAGLowering::visitGetElementPtr(User &I) { 2378 SDOperand N = getValue(I.getOperand(0)); 2379 const Type *Ty = I.getOperand(0)->getType(); 2380 2381 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2382 OI != E; ++OI) { 2383 Value *Idx = *OI; 2384 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2385 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2386 if (Field) { 2387 // N = N + Offset 2388 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2389 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2390 DAG.getIntPtrConstant(Offset)); 2391 } 2392 Ty = StTy->getElementType(Field); 2393 } else { 2394 Ty = cast<SequentialType>(Ty)->getElementType(); 2395 2396 // If this is a constant subscript, handle it quickly. 2397 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2398 if (CI->getZExtValue() == 0) continue; 2399 uint64_t Offs = 2400 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2401 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2402 DAG.getIntPtrConstant(Offs)); 2403 continue; 2404 } 2405 2406 // N = N + Idx * ElementSize; 2407 uint64_t ElementSize = TD->getABITypeSize(Ty); 2408 SDOperand IdxN = getValue(Idx); 2409 2410 // If the index is smaller or larger than intptr_t, truncate or extend 2411 // it. 2412 if (IdxN.getValueType() < N.getValueType()) { 2413 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2414 } else if (IdxN.getValueType() > N.getValueType()) 2415 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2416 2417 // If this is a multiply by a power of two, turn it into a shl 2418 // immediately. This is a very common case. 2419 if (isPowerOf2_64(ElementSize)) { 2420 unsigned Amt = Log2_64(ElementSize); 2421 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2422 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2423 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2424 continue; 2425 } 2426 2427 SDOperand Scale = DAG.getIntPtrConstant(ElementSize); 2428 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2429 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2430 } 2431 } 2432 setValue(&I, N); 2433} 2434 2435void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2436 // If this is a fixed sized alloca in the entry block of the function, 2437 // allocate it statically on the stack. 2438 if (FuncInfo.StaticAllocaMap.count(&I)) 2439 return; // getValue will auto-populate this. 2440 2441 const Type *Ty = I.getAllocatedType(); 2442 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 2443 unsigned Align = 2444 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2445 I.getAlignment()); 2446 2447 SDOperand AllocSize = getValue(I.getArraySize()); 2448 MVT::ValueType IntPtr = TLI.getPointerTy(); 2449 if (IntPtr < AllocSize.getValueType()) 2450 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2451 else if (IntPtr > AllocSize.getValueType()) 2452 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2453 2454 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2455 DAG.getIntPtrConstant(TySize)); 2456 2457 // Handle alignment. If the requested alignment is less than or equal to 2458 // the stack alignment, ignore it. If the size is greater than or equal to 2459 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2460 unsigned StackAlign = 2461 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2462 if (Align <= StackAlign) 2463 Align = 0; 2464 2465 // Round the size of the allocation up to the stack alignment size 2466 // by add SA-1 to the size. 2467 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2468 DAG.getIntPtrConstant(StackAlign-1)); 2469 // Mask out the low bits for alignment purposes. 2470 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2471 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2472 2473 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2474 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2475 MVT::Other); 2476 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2477 setValue(&I, DSA); 2478 DAG.setRoot(DSA.getValue(1)); 2479 2480 // Inform the Frame Information that we have just allocated a variable-sized 2481 // object. 2482 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2483} 2484 2485void SelectionDAGLowering::visitLoad(LoadInst &I) { 2486 SDOperand Ptr = getValue(I.getOperand(0)); 2487 2488 SDOperand Root; 2489 if (I.isVolatile()) 2490 Root = getRoot(); 2491 else { 2492 // Do not serialize non-volatile loads against each other. 2493 Root = DAG.getRoot(); 2494 } 2495 2496 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2497 Root, I.isVolatile(), I.getAlignment())); 2498} 2499 2500SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2501 const Value *SV, SDOperand Root, 2502 bool isVolatile, 2503 unsigned Alignment) { 2504 SDOperand L = 2505 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2506 isVolatile, Alignment); 2507 2508 if (isVolatile) 2509 DAG.setRoot(L.getValue(1)); 2510 else 2511 PendingLoads.push_back(L.getValue(1)); 2512 2513 return L; 2514} 2515 2516 2517void SelectionDAGLowering::visitStore(StoreInst &I) { 2518 Value *SrcV = I.getOperand(0); 2519 SDOperand Src = getValue(SrcV); 2520 SDOperand Ptr = getValue(I.getOperand(1)); 2521 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2522 I.isVolatile(), I.getAlignment())); 2523} 2524 2525/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2526/// node. 2527void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2528 unsigned Intrinsic) { 2529 bool HasChain = !I.doesNotAccessMemory(); 2530 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 2531 2532 // Build the operand list. 2533 SmallVector<SDOperand, 8> Ops; 2534 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2535 if (OnlyLoad) { 2536 // We don't need to serialize loads against other loads. 2537 Ops.push_back(DAG.getRoot()); 2538 } else { 2539 Ops.push_back(getRoot()); 2540 } 2541 } 2542 2543 // Add the intrinsic ID as an integer operand. 2544 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2545 2546 // Add all operands of the call to the operand list. 2547 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2548 SDOperand Op = getValue(I.getOperand(i)); 2549 assert(TLI.isTypeLegal(Op.getValueType()) && 2550 "Intrinsic uses a non-legal type?"); 2551 Ops.push_back(Op); 2552 } 2553 2554 std::vector<MVT::ValueType> VTs; 2555 if (I.getType() != Type::VoidTy) { 2556 MVT::ValueType VT = TLI.getValueType(I.getType()); 2557 if (MVT::isVector(VT)) { 2558 const VectorType *DestTy = cast<VectorType>(I.getType()); 2559 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2560 2561 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2562 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2563 } 2564 2565 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2566 VTs.push_back(VT); 2567 } 2568 if (HasChain) 2569 VTs.push_back(MVT::Other); 2570 2571 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2572 2573 // Create the node. 2574 SDOperand Result; 2575 if (!HasChain) 2576 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2577 &Ops[0], Ops.size()); 2578 else if (I.getType() != Type::VoidTy) 2579 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2580 &Ops[0], Ops.size()); 2581 else 2582 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2583 &Ops[0], Ops.size()); 2584 2585 if (HasChain) { 2586 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2587 if (OnlyLoad) 2588 PendingLoads.push_back(Chain); 2589 else 2590 DAG.setRoot(Chain); 2591 } 2592 if (I.getType() != Type::VoidTy) { 2593 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2594 MVT::ValueType VT = TLI.getValueType(PTy); 2595 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 2596 } 2597 setValue(&I, Result); 2598 } 2599} 2600 2601/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 2602static GlobalVariable *ExtractTypeInfo (Value *V) { 2603 V = IntrinsicInst::StripPointerCasts(V); 2604 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 2605 assert ((GV || isa<ConstantPointerNull>(V)) && 2606 "TypeInfo must be a global variable or NULL"); 2607 return GV; 2608} 2609 2610/// addCatchInfo - Extract the personality and type infos from an eh.selector 2611/// call, and add them to the specified machine basic block. 2612static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 2613 MachineBasicBlock *MBB) { 2614 // Inform the MachineModuleInfo of the personality for this landing pad. 2615 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 2616 assert(CE->getOpcode() == Instruction::BitCast && 2617 isa<Function>(CE->getOperand(0)) && 2618 "Personality should be a function"); 2619 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 2620 2621 // Gather all the type infos for this landing pad and pass them along to 2622 // MachineModuleInfo. 2623 std::vector<GlobalVariable *> TyInfo; 2624 unsigned N = I.getNumOperands(); 2625 2626 for (unsigned i = N - 1; i > 2; --i) { 2627 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 2628 unsigned FilterLength = CI->getZExtValue(); 2629 unsigned FirstCatch = i + FilterLength + !FilterLength; 2630 assert (FirstCatch <= N && "Invalid filter length"); 2631 2632 if (FirstCatch < N) { 2633 TyInfo.reserve(N - FirstCatch); 2634 for (unsigned j = FirstCatch; j < N; ++j) 2635 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2636 MMI->addCatchTypeInfo(MBB, TyInfo); 2637 TyInfo.clear(); 2638 } 2639 2640 if (!FilterLength) { 2641 // Cleanup. 2642 MMI->addCleanup(MBB); 2643 } else { 2644 // Filter. 2645 TyInfo.reserve(FilterLength - 1); 2646 for (unsigned j = i + 1; j < FirstCatch; ++j) 2647 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2648 MMI->addFilterTypeInfo(MBB, TyInfo); 2649 TyInfo.clear(); 2650 } 2651 2652 N = i; 2653 } 2654 } 2655 2656 if (N > 3) { 2657 TyInfo.reserve(N - 3); 2658 for (unsigned j = 3; j < N; ++j) 2659 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2660 MMI->addCatchTypeInfo(MBB, TyInfo); 2661 } 2662} 2663 2664/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2665/// we want to emit this as a call to a named external function, return the name 2666/// otherwise lower it and return null. 2667const char * 2668SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2669 switch (Intrinsic) { 2670 default: 2671 // By default, turn this into a target intrinsic node. 2672 visitTargetIntrinsic(I, Intrinsic); 2673 return 0; 2674 case Intrinsic::vastart: visitVAStart(I); return 0; 2675 case Intrinsic::vaend: visitVAEnd(I); return 0; 2676 case Intrinsic::vacopy: visitVACopy(I); return 0; 2677 case Intrinsic::returnaddress: 2678 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2679 getValue(I.getOperand(1)))); 2680 return 0; 2681 case Intrinsic::frameaddress: 2682 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2683 getValue(I.getOperand(1)))); 2684 return 0; 2685 case Intrinsic::setjmp: 2686 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2687 break; 2688 case Intrinsic::longjmp: 2689 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2690 break; 2691 case Intrinsic::memcpy_i32: 2692 case Intrinsic::memcpy_i64: 2693 visitMemIntrinsic(I, ISD::MEMCPY); 2694 return 0; 2695 case Intrinsic::memset_i32: 2696 case Intrinsic::memset_i64: 2697 visitMemIntrinsic(I, ISD::MEMSET); 2698 return 0; 2699 case Intrinsic::memmove_i32: 2700 case Intrinsic::memmove_i64: 2701 visitMemIntrinsic(I, ISD::MEMMOVE); 2702 return 0; 2703 2704 case Intrinsic::dbg_stoppoint: { 2705 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2706 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2707 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2708 SDOperand Ops[5]; 2709 2710 Ops[0] = getRoot(); 2711 Ops[1] = getValue(SPI.getLineValue()); 2712 Ops[2] = getValue(SPI.getColumnValue()); 2713 2714 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2715 assert(DD && "Not a debug information descriptor"); 2716 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2717 2718 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2719 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2720 2721 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2722 } 2723 2724 return 0; 2725 } 2726 case Intrinsic::dbg_region_start: { 2727 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2728 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2729 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2730 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2731 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2732 DAG.getConstant(LabelID, MVT::i32), 2733 DAG.getConstant(0, MVT::i32))); 2734 } 2735 2736 return 0; 2737 } 2738 case Intrinsic::dbg_region_end: { 2739 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2740 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2741 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2742 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2743 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2744 DAG.getConstant(LabelID, MVT::i32), 2745 DAG.getConstant(0, MVT::i32))); 2746 } 2747 2748 return 0; 2749 } 2750 case Intrinsic::dbg_func_start: { 2751 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2752 if (!MMI) return 0; 2753 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2754 Value *SP = FSI.getSubprogram(); 2755 if (SP && MMI->Verify(SP)) { 2756 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is 2757 // what (most?) gdb expects. 2758 DebugInfoDesc *DD = MMI->getDescFor(SP); 2759 assert(DD && "Not a debug information descriptor"); 2760 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD); 2761 const CompileUnitDesc *CompileUnit = Subprogram->getFile(); 2762 unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(), 2763 CompileUnit->getFileName()); 2764 // Record the source line but does create a label. It will be emitted 2765 // at asm emission time. 2766 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile); 2767 } 2768 2769 return 0; 2770 } 2771 case Intrinsic::dbg_declare: { 2772 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2773 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2774 Value *Variable = DI.getVariable(); 2775 if (MMI && Variable && MMI->Verify(Variable)) 2776 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(), 2777 getValue(DI.getAddress()), getValue(Variable))); 2778 return 0; 2779 } 2780 2781 case Intrinsic::eh_exception: { 2782 if (ExceptionHandling) { 2783 if (!CurMBB->isLandingPad()) { 2784 // FIXME: Mark exception register as live in. Hack for PR1508. 2785 unsigned Reg = TLI.getExceptionAddressRegister(); 2786 if (Reg) CurMBB->addLiveIn(Reg); 2787 } 2788 // Insert the EXCEPTIONADDR instruction. 2789 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2790 SDOperand Ops[1]; 2791 Ops[0] = DAG.getRoot(); 2792 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2793 setValue(&I, Op); 2794 DAG.setRoot(Op.getValue(1)); 2795 } else { 2796 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2797 } 2798 return 0; 2799 } 2800 2801 case Intrinsic::eh_selector_i32: 2802 case Intrinsic::eh_selector_i64: { 2803 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2804 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ? 2805 MVT::i32 : MVT::i64); 2806 2807 if (ExceptionHandling && MMI) { 2808 if (CurMBB->isLandingPad()) 2809 addCatchInfo(I, MMI, CurMBB); 2810 else { 2811#ifndef NDEBUG 2812 FuncInfo.CatchInfoLost.insert(&I); 2813#endif 2814 // FIXME: Mark exception selector register as live in. Hack for PR1508. 2815 unsigned Reg = TLI.getExceptionSelectorRegister(); 2816 if (Reg) CurMBB->addLiveIn(Reg); 2817 } 2818 2819 // Insert the EHSELECTION instruction. 2820 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 2821 SDOperand Ops[2]; 2822 Ops[0] = getValue(I.getOperand(1)); 2823 Ops[1] = getRoot(); 2824 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2825 setValue(&I, Op); 2826 DAG.setRoot(Op.getValue(1)); 2827 } else { 2828 setValue(&I, DAG.getConstant(0, VT)); 2829 } 2830 2831 return 0; 2832 } 2833 2834 case Intrinsic::eh_typeid_for_i32: 2835 case Intrinsic::eh_typeid_for_i64: { 2836 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2837 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? 2838 MVT::i32 : MVT::i64); 2839 2840 if (MMI) { 2841 // Find the type id for the given typeinfo. 2842 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 2843 2844 unsigned TypeID = MMI->getTypeIDFor(GV); 2845 setValue(&I, DAG.getConstant(TypeID, VT)); 2846 } else { 2847 // Return something different to eh_selector. 2848 setValue(&I, DAG.getConstant(1, VT)); 2849 } 2850 2851 return 0; 2852 } 2853 2854 case Intrinsic::eh_return: { 2855 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2856 2857 if (MMI && ExceptionHandling) { 2858 MMI->setCallsEHReturn(true); 2859 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, 2860 MVT::Other, 2861 getRoot(), 2862 getValue(I.getOperand(1)), 2863 getValue(I.getOperand(2)))); 2864 } else { 2865 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2866 } 2867 2868 return 0; 2869 } 2870 2871 case Intrinsic::eh_unwind_init: { 2872 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 2873 MMI->setCallsUnwindInit(true); 2874 } 2875 2876 return 0; 2877 } 2878 2879 case Intrinsic::eh_dwarf_cfa: { 2880 if (ExceptionHandling) { 2881 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType(); 2882 SDOperand CfaArg; 2883 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 2884 CfaArg = DAG.getNode(ISD::TRUNCATE, 2885 TLI.getPointerTy(), getValue(I.getOperand(1))); 2886 else 2887 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, 2888 TLI.getPointerTy(), getValue(I.getOperand(1))); 2889 2890 SDOperand Offset = DAG.getNode(ISD::ADD, 2891 TLI.getPointerTy(), 2892 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, 2893 TLI.getPointerTy()), 2894 CfaArg); 2895 setValue(&I, DAG.getNode(ISD::ADD, 2896 TLI.getPointerTy(), 2897 DAG.getNode(ISD::FRAMEADDR, 2898 TLI.getPointerTy(), 2899 DAG.getConstant(0, 2900 TLI.getPointerTy())), 2901 Offset)); 2902 } else { 2903 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2904 } 2905 2906 return 0; 2907 } 2908 2909 case Intrinsic::sqrt: 2910 setValue(&I, DAG.getNode(ISD::FSQRT, 2911 getValue(I.getOperand(1)).getValueType(), 2912 getValue(I.getOperand(1)))); 2913 return 0; 2914 case Intrinsic::powi: 2915 setValue(&I, DAG.getNode(ISD::FPOWI, 2916 getValue(I.getOperand(1)).getValueType(), 2917 getValue(I.getOperand(1)), 2918 getValue(I.getOperand(2)))); 2919 return 0; 2920 case Intrinsic::sin: 2921 setValue(&I, DAG.getNode(ISD::FSIN, 2922 getValue(I.getOperand(1)).getValueType(), 2923 getValue(I.getOperand(1)))); 2924 return 0; 2925 case Intrinsic::cos: 2926 setValue(&I, DAG.getNode(ISD::FCOS, 2927 getValue(I.getOperand(1)).getValueType(), 2928 getValue(I.getOperand(1)))); 2929 return 0; 2930 case Intrinsic::pow: 2931 setValue(&I, DAG.getNode(ISD::FPOW, 2932 getValue(I.getOperand(1)).getValueType(), 2933 getValue(I.getOperand(1)), 2934 getValue(I.getOperand(2)))); 2935 return 0; 2936 case Intrinsic::pcmarker: { 2937 SDOperand Tmp = getValue(I.getOperand(1)); 2938 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2939 return 0; 2940 } 2941 case Intrinsic::readcyclecounter: { 2942 SDOperand Op = getRoot(); 2943 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2944 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2945 &Op, 1); 2946 setValue(&I, Tmp); 2947 DAG.setRoot(Tmp.getValue(1)); 2948 return 0; 2949 } 2950 case Intrinsic::part_select: { 2951 // Currently not implemented: just abort 2952 assert(0 && "part_select intrinsic not implemented"); 2953 abort(); 2954 } 2955 case Intrinsic::part_set: { 2956 // Currently not implemented: just abort 2957 assert(0 && "part_set intrinsic not implemented"); 2958 abort(); 2959 } 2960 case Intrinsic::bswap: 2961 setValue(&I, DAG.getNode(ISD::BSWAP, 2962 getValue(I.getOperand(1)).getValueType(), 2963 getValue(I.getOperand(1)))); 2964 return 0; 2965 case Intrinsic::cttz: { 2966 SDOperand Arg = getValue(I.getOperand(1)); 2967 MVT::ValueType Ty = Arg.getValueType(); 2968 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2969 setValue(&I, result); 2970 return 0; 2971 } 2972 case Intrinsic::ctlz: { 2973 SDOperand Arg = getValue(I.getOperand(1)); 2974 MVT::ValueType Ty = Arg.getValueType(); 2975 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2976 setValue(&I, result); 2977 return 0; 2978 } 2979 case Intrinsic::ctpop: { 2980 SDOperand Arg = getValue(I.getOperand(1)); 2981 MVT::ValueType Ty = Arg.getValueType(); 2982 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2983 setValue(&I, result); 2984 return 0; 2985 } 2986 case Intrinsic::stacksave: { 2987 SDOperand Op = getRoot(); 2988 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2989 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2990 setValue(&I, Tmp); 2991 DAG.setRoot(Tmp.getValue(1)); 2992 return 0; 2993 } 2994 case Intrinsic::stackrestore: { 2995 SDOperand Tmp = getValue(I.getOperand(1)); 2996 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2997 return 0; 2998 } 2999 case Intrinsic::prefetch: 3000 // FIXME: Currently discarding prefetches. 3001 return 0; 3002 3003 case Intrinsic::var_annotation: 3004 // Discard annotate attributes 3005 return 0; 3006 3007 case Intrinsic::init_trampoline: { 3008 const Function *F = 3009 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2))); 3010 3011 SDOperand Ops[6]; 3012 Ops[0] = getRoot(); 3013 Ops[1] = getValue(I.getOperand(1)); 3014 Ops[2] = getValue(I.getOperand(2)); 3015 Ops[3] = getValue(I.getOperand(3)); 3016 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 3017 Ops[5] = DAG.getSrcValue(F); 3018 3019 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE, 3020 DAG.getNodeValueTypes(TLI.getPointerTy(), 3021 MVT::Other), 2, 3022 Ops, 6); 3023 3024 setValue(&I, Tmp); 3025 DAG.setRoot(Tmp.getValue(1)); 3026 return 0; 3027 } 3028 3029 case Intrinsic::gcroot: 3030 if (GCI) { 3031 Value *Alloca = I.getOperand(1); 3032 Constant *TypeMap = cast<Constant>(I.getOperand(2)); 3033 3034 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val); 3035 GCI->addStackRoot(FI->getIndex(), TypeMap); 3036 } 3037 return 0; 3038 3039 case Intrinsic::gcread: 3040 case Intrinsic::gcwrite: 3041 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!"); 3042 return 0; 3043 3044 case Intrinsic::flt_rounds: { 3045 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32)); 3046 return 0; 3047 } 3048 3049 case Intrinsic::trap: { 3050 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot())); 3051 return 0; 3052 } 3053 case Intrinsic::memory_barrier: { 3054 SDOperand Ops[6]; 3055 Ops[0] = getRoot(); 3056 for (int x = 1; x < 6; ++x) 3057 Ops[x] = getValue(I.getOperand(x)); 3058 3059 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6)); 3060 return 0; 3061 } 3062 case Intrinsic::atomic_lcs: { 3063 SDOperand Root = getRoot(); 3064 SDOperand O3 = getValue(I.getOperand(3)); 3065 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LCS, Root, 3066 getValue(I.getOperand(1)), 3067 getValue(I.getOperand(2)), 3068 O3, O3.getValueType()); 3069 setValue(&I, L); 3070 DAG.setRoot(L.getValue(1)); 3071 return 0; 3072 } 3073 case Intrinsic::atomic_las: { 3074 SDOperand Root = getRoot(); 3075 SDOperand O2 = getValue(I.getOperand(2)); 3076 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LAS, Root, 3077 getValue(I.getOperand(1)), 3078 O2, O2.getValueType()); 3079 setValue(&I, L); 3080 DAG.setRoot(L.getValue(1)); 3081 return 0; 3082 } 3083 case Intrinsic::atomic_swap: { 3084 SDOperand Root = getRoot(); 3085 SDOperand O2 = getValue(I.getOperand(2)); 3086 SDOperand L = DAG.getAtomic(ISD::ATOMIC_SWAP, Root, 3087 getValue(I.getOperand(1)), 3088 O2, O2.getValueType()); 3089 setValue(&I, L); 3090 DAG.setRoot(L.getValue(1)); 3091 return 0; 3092 } 3093 3094 } 3095} 3096 3097 3098void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee, 3099 bool IsTailCall, 3100 MachineBasicBlock *LandingPad) { 3101 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 3102 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 3103 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3104 unsigned BeginLabel = 0, EndLabel = 0; 3105 3106 TargetLowering::ArgListTy Args; 3107 TargetLowering::ArgListEntry Entry; 3108 Args.reserve(CS.arg_size()); 3109 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 3110 i != e; ++i) { 3111 SDOperand ArgNode = getValue(*i); 3112 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 3113 3114 unsigned attrInd = i - CS.arg_begin() + 1; 3115 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt); 3116 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt); 3117 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg); 3118 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet); 3119 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest); 3120 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal); 3121 Args.push_back(Entry); 3122 } 3123 3124 bool MarkTryRange = LandingPad || 3125 // C++ requires special handling of 'nounwind' calls. 3126 (CS.doesNotThrow()); 3127 3128 if (MarkTryRange && ExceptionHandling && MMI) { 3129 // Insert a label before the invoke call to mark the try range. This can be 3130 // used to detect deletion of the invoke via the MachineModuleInfo. 3131 BeginLabel = MMI->NextLabelID(); 3132 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 3133 DAG.getConstant(BeginLabel, MVT::i32), 3134 DAG.getConstant(1, MVT::i32))); 3135 } 3136 3137 std::pair<SDOperand,SDOperand> Result = 3138 TLI.LowerCallTo(getRoot(), CS.getType(), 3139 CS.paramHasAttr(0, ParamAttr::SExt), 3140 CS.paramHasAttr(0, ParamAttr::ZExt), 3141 FTy->isVarArg(), CS.getCallingConv(), IsTailCall, 3142 Callee, Args, DAG); 3143 if (CS.getType() != Type::VoidTy) 3144 setValue(CS.getInstruction(), Result.first); 3145 DAG.setRoot(Result.second); 3146 3147 if (MarkTryRange && ExceptionHandling && MMI) { 3148 // Insert a label at the end of the invoke call to mark the try range. This 3149 // can be used to detect deletion of the invoke via the MachineModuleInfo. 3150 EndLabel = MMI->NextLabelID(); 3151 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 3152 DAG.getConstant(EndLabel, MVT::i32), 3153 DAG.getConstant(1, MVT::i32))); 3154 3155 // Inform MachineModuleInfo of range. 3156 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 3157 } 3158} 3159 3160 3161void SelectionDAGLowering::visitCall(CallInst &I) { 3162 const char *RenameFn = 0; 3163 if (Function *F = I.getCalledFunction()) { 3164 if (F->isDeclaration()) { 3165 if (unsigned IID = F->getIntrinsicID()) { 3166 RenameFn = visitIntrinsicCall(I, IID); 3167 if (!RenameFn) 3168 return; 3169 } 3170 } 3171 3172 // Check for well-known libc/libm calls. If the function is internal, it 3173 // can't be a library call. 3174 unsigned NameLen = F->getNameLen(); 3175 if (!F->hasInternalLinkage() && NameLen) { 3176 const char *NameStr = F->getNameStart(); 3177 if (NameStr[0] == 'c' && 3178 ((NameLen == 8 && !strcmp(NameStr, "copysign")) || 3179 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) { 3180 if (I.getNumOperands() == 3 && // Basic sanity checks. 3181 I.getOperand(1)->getType()->isFloatingPoint() && 3182 I.getType() == I.getOperand(1)->getType() && 3183 I.getType() == I.getOperand(2)->getType()) { 3184 SDOperand LHS = getValue(I.getOperand(1)); 3185 SDOperand RHS = getValue(I.getOperand(2)); 3186 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 3187 LHS, RHS)); 3188 return; 3189 } 3190 } else if (NameStr[0] == 'f' && 3191 ((NameLen == 4 && !strcmp(NameStr, "fabs")) || 3192 (NameLen == 5 && !strcmp(NameStr, "fabsf")) || 3193 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) { 3194 if (I.getNumOperands() == 2 && // Basic sanity checks. 3195 I.getOperand(1)->getType()->isFloatingPoint() && 3196 I.getType() == I.getOperand(1)->getType()) { 3197 SDOperand Tmp = getValue(I.getOperand(1)); 3198 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 3199 return; 3200 } 3201 } else if (NameStr[0] == 's' && 3202 ((NameLen == 3 && !strcmp(NameStr, "sin")) || 3203 (NameLen == 4 && !strcmp(NameStr, "sinf")) || 3204 (NameLen == 4 && !strcmp(NameStr, "sinl")))) { 3205 if (I.getNumOperands() == 2 && // Basic sanity checks. 3206 I.getOperand(1)->getType()->isFloatingPoint() && 3207 I.getType() == I.getOperand(1)->getType()) { 3208 SDOperand Tmp = getValue(I.getOperand(1)); 3209 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 3210 return; 3211 } 3212 } else if (NameStr[0] == 'c' && 3213 ((NameLen == 3 && !strcmp(NameStr, "cos")) || 3214 (NameLen == 4 && !strcmp(NameStr, "cosf")) || 3215 (NameLen == 4 && !strcmp(NameStr, "cosl")))) { 3216 if (I.getNumOperands() == 2 && // Basic sanity checks. 3217 I.getOperand(1)->getType()->isFloatingPoint() && 3218 I.getType() == I.getOperand(1)->getType()) { 3219 SDOperand Tmp = getValue(I.getOperand(1)); 3220 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 3221 return; 3222 } 3223 } 3224 } 3225 } else if (isa<InlineAsm>(I.getOperand(0))) { 3226 visitInlineAsm(&I); 3227 return; 3228 } 3229 3230 SDOperand Callee; 3231 if (!RenameFn) 3232 Callee = getValue(I.getOperand(0)); 3233 else 3234 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 3235 3236 LowerCallTo(&I, Callee, I.isTailCall()); 3237} 3238 3239 3240/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 3241/// this value and returns the result as a ValueVT value. This uses 3242/// Chain/Flag as the input and updates them for the output Chain/Flag. 3243/// If the Flag pointer is NULL, no flag is used. 3244SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 3245 SDOperand &Chain, SDOperand *Flag)const{ 3246 // Copy the legal parts from the registers. 3247 unsigned NumParts = Regs.size(); 3248 SmallVector<SDOperand, 8> Parts(NumParts); 3249 for (unsigned i = 0; i != NumParts; ++i) { 3250 SDOperand Part = Flag ? 3251 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) : 3252 DAG.getCopyFromReg(Chain, Regs[i], RegVT); 3253 Chain = Part.getValue(1); 3254 if (Flag) 3255 *Flag = Part.getValue(2); 3256 Parts[i] = Part; 3257 } 3258 3259 // Assemble the legal parts into the final value. 3260 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT); 3261} 3262 3263/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 3264/// specified value into the registers specified by this object. This uses 3265/// Chain/Flag as the input and updates them for the output Chain/Flag. 3266/// If the Flag pointer is NULL, no flag is used. 3267void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 3268 SDOperand &Chain, SDOperand *Flag) const { 3269 // Get the list of the values's legal parts. 3270 unsigned NumParts = Regs.size(); 3271 SmallVector<SDOperand, 8> Parts(NumParts); 3272 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT); 3273 3274 // Copy the parts into the registers. 3275 for (unsigned i = 0; i != NumParts; ++i) { 3276 SDOperand Part = Flag ? 3277 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) : 3278 DAG.getCopyToReg(Chain, Regs[i], Parts[i]); 3279 Chain = Part.getValue(0); 3280 if (Flag) 3281 *Flag = Part.getValue(1); 3282 } 3283} 3284 3285/// AddInlineAsmOperands - Add this value to the specified inlineasm node 3286/// operand list. This adds the code marker and includes the number of 3287/// values added into it. 3288void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 3289 std::vector<SDOperand> &Ops) const { 3290 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3291 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3292 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 3293 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 3294} 3295 3296/// isAllocatableRegister - If the specified register is safe to allocate, 3297/// i.e. it isn't a stack pointer or some other special register, return the 3298/// register class for the register. Otherwise, return null. 3299static const TargetRegisterClass * 3300isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3301 const TargetLowering &TLI, 3302 const TargetRegisterInfo *TRI) { 3303 MVT::ValueType FoundVT = MVT::Other; 3304 const TargetRegisterClass *FoundRC = 0; 3305 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 3306 E = TRI->regclass_end(); RCI != E; ++RCI) { 3307 MVT::ValueType ThisVT = MVT::Other; 3308 3309 const TargetRegisterClass *RC = *RCI; 3310 // If none of the the value types for this register class are valid, we 3311 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3312 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3313 I != E; ++I) { 3314 if (TLI.isTypeLegal(*I)) { 3315 // If we have already found this register in a different register class, 3316 // choose the one with the largest VT specified. For example, on 3317 // PowerPC, we favor f64 register classes over f32. 3318 if (FoundVT == MVT::Other || 3319 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 3320 ThisVT = *I; 3321 break; 3322 } 3323 } 3324 } 3325 3326 if (ThisVT == MVT::Other) continue; 3327 3328 // NOTE: This isn't ideal. In particular, this might allocate the 3329 // frame pointer in functions that need it (due to them not being taken 3330 // out of allocation, because a variable sized allocation hasn't been seen 3331 // yet). This is a slight code pessimization, but should still work. 3332 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3333 E = RC->allocation_order_end(MF); I != E; ++I) 3334 if (*I == Reg) { 3335 // We found a matching register class. Keep looking at others in case 3336 // we find one with larger registers that this physreg is also in. 3337 FoundRC = RC; 3338 FoundVT = ThisVT; 3339 break; 3340 } 3341 } 3342 return FoundRC; 3343} 3344 3345 3346namespace { 3347/// AsmOperandInfo - This contains information for each constraint that we are 3348/// lowering. 3349struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 3350 /// ConstraintCode - This contains the actual string for the code, like "m". 3351 std::string ConstraintCode; 3352 3353 /// ConstraintType - Information about the constraint code, e.g. Register, 3354 /// RegisterClass, Memory, Other, Unknown. 3355 TargetLowering::ConstraintType ConstraintType; 3356 3357 /// CallOperand/CallOperandval - If this is the result output operand or a 3358 /// clobber, this is null, otherwise it is the incoming operand to the 3359 /// CallInst. This gets modified as the asm is processed. 3360 SDOperand CallOperand; 3361 Value *CallOperandVal; 3362 3363 /// ConstraintVT - The ValueType for the operand value. 3364 MVT::ValueType ConstraintVT; 3365 3366 /// AssignedRegs - If this is a register or register class operand, this 3367 /// contains the set of register corresponding to the operand. 3368 RegsForValue AssignedRegs; 3369 3370 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3371 : InlineAsm::ConstraintInfo(info), 3372 ConstraintType(TargetLowering::C_Unknown), 3373 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) { 3374 } 3375 3376 void ComputeConstraintToUse(const TargetLowering &TLI); 3377 3378 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3379 /// busy in OutputRegs/InputRegs. 3380 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3381 std::set<unsigned> &OutputRegs, 3382 std::set<unsigned> &InputRegs, 3383 const TargetRegisterInfo &TRI) const { 3384 if (isOutReg) { 3385 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 3386 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 3387 } 3388 if (isInReg) { 3389 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 3390 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 3391 } 3392 } 3393 3394private: 3395 /// MarkRegAndAliases - Mark the specified register and all aliases in the 3396 /// specified set. 3397 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 3398 const TargetRegisterInfo &TRI) { 3399 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 3400 Regs.insert(Reg); 3401 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 3402 for (; *Aliases; ++Aliases) 3403 Regs.insert(*Aliases); 3404 } 3405}; 3406} // end anon namespace. 3407 3408/// getConstraintGenerality - Return an integer indicating how general CT is. 3409static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3410 switch (CT) { 3411 default: assert(0 && "Unknown constraint type!"); 3412 case TargetLowering::C_Other: 3413 case TargetLowering::C_Unknown: 3414 return 0; 3415 case TargetLowering::C_Register: 3416 return 1; 3417 case TargetLowering::C_RegisterClass: 3418 return 2; 3419 case TargetLowering::C_Memory: 3420 return 3; 3421 } 3422} 3423 3424void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) { 3425 assert(!Codes.empty() && "Must have at least one constraint"); 3426 3427 std::string *Current = &Codes[0]; 3428 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current); 3429 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common. 3430 ConstraintCode = *Current; 3431 ConstraintType = CurType; 3432 } else { 3433 unsigned CurGenerality = getConstraintGenerality(CurType); 3434 3435 // If we have multiple constraints, try to pick the most general one ahead 3436 // of time. This isn't a wonderful solution, but handles common cases. 3437 for (unsigned j = 1, e = Codes.size(); j != e; ++j) { 3438 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]); 3439 unsigned ThisGenerality = getConstraintGenerality(ThisType); 3440 if (ThisGenerality > CurGenerality) { 3441 // This constraint letter is more general than the previous one, 3442 // use it. 3443 CurType = ThisType; 3444 Current = &Codes[j]; 3445 CurGenerality = ThisGenerality; 3446 } 3447 } 3448 3449 ConstraintCode = *Current; 3450 ConstraintType = CurType; 3451 } 3452 3453 if (ConstraintCode == "X") { 3454 if (isa<BasicBlock>(CallOperandVal) || isa<ConstantInt>(CallOperandVal)) 3455 return; 3456 // This matches anything. Labels and constants we handle elsewhere 3457 // ('X' is the only thing that matches labels). Otherwise, try to 3458 // resolve it to something we know about by looking at the actual 3459 // operand type. 3460 std::string s = ""; 3461 TLI.lowerXConstraint(ConstraintVT, s); 3462 if (s!="") { 3463 ConstraintCode = s; 3464 ConstraintType = TLI.getConstraintType(ConstraintCode); 3465 } 3466 } 3467} 3468 3469 3470/// GetRegistersForValue - Assign registers (virtual or physical) for the 3471/// specified operand. We prefer to assign virtual registers, to allow the 3472/// register allocator handle the assignment process. However, if the asm uses 3473/// features that we can't model on machineinstrs, we have SDISel do the 3474/// allocation. This produces generally horrible, but correct, code. 3475/// 3476/// OpInfo describes the operand. 3477/// HasEarlyClobber is true if there are any early clobber constraints (=&r) 3478/// or any explicitly clobbered registers. 3479/// Input and OutputRegs are the set of already allocated physical registers. 3480/// 3481void SelectionDAGLowering:: 3482GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 3483 std::set<unsigned> &OutputRegs, 3484 std::set<unsigned> &InputRegs) { 3485 // Compute whether this value requires an input register, an output register, 3486 // or both. 3487 bool isOutReg = false; 3488 bool isInReg = false; 3489 switch (OpInfo.Type) { 3490 case InlineAsm::isOutput: 3491 isOutReg = true; 3492 3493 // If this is an early-clobber output, or if there is an input 3494 // constraint that matches this, we need to reserve the input register 3495 // so no other inputs allocate to it. 3496 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3497 break; 3498 case InlineAsm::isInput: 3499 isInReg = true; 3500 isOutReg = false; 3501 break; 3502 case InlineAsm::isClobber: 3503 isOutReg = true; 3504 isInReg = true; 3505 break; 3506 } 3507 3508 3509 MachineFunction &MF = DAG.getMachineFunction(); 3510 std::vector<unsigned> Regs; 3511 3512 // If this is a constraint for a single physreg, or a constraint for a 3513 // register class, find it. 3514 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3515 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3516 OpInfo.ConstraintVT); 3517 3518 unsigned NumRegs = 1; 3519 if (OpInfo.ConstraintVT != MVT::Other) 3520 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3521 MVT::ValueType RegVT; 3522 MVT::ValueType ValueVT = OpInfo.ConstraintVT; 3523 3524 3525 // If this is a constraint for a specific physical register, like {r17}, 3526 // assign it now. 3527 if (PhysReg.first) { 3528 if (OpInfo.ConstraintVT == MVT::Other) 3529 ValueVT = *PhysReg.second->vt_begin(); 3530 3531 // Get the actual register value type. This is important, because the user 3532 // may have asked for (e.g.) the AX register in i32 type. We need to 3533 // remember that AX is actually i16 to get the right extension. 3534 RegVT = *PhysReg.second->vt_begin(); 3535 3536 // This is a explicit reference to a physical register. 3537 Regs.push_back(PhysReg.first); 3538 3539 // If this is an expanded reference, add the rest of the regs to Regs. 3540 if (NumRegs != 1) { 3541 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3542 TargetRegisterClass::iterator E = PhysReg.second->end(); 3543 for (; *I != PhysReg.first; ++I) 3544 assert(I != E && "Didn't find reg!"); 3545 3546 // Already added the first reg. 3547 --NumRegs; ++I; 3548 for (; NumRegs; --NumRegs, ++I) { 3549 assert(I != E && "Ran out of registers to allocate!"); 3550 Regs.push_back(*I); 3551 } 3552 } 3553 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3554 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 3555 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 3556 return; 3557 } 3558 3559 // Otherwise, if this was a reference to an LLVM register class, create vregs 3560 // for this reference. 3561 std::vector<unsigned> RegClassRegs; 3562 const TargetRegisterClass *RC = PhysReg.second; 3563 if (RC) { 3564 // If this is an early clobber or tied register, our regalloc doesn't know 3565 // how to maintain the constraint. If it isn't, go ahead and create vreg 3566 // and let the regalloc do the right thing. 3567 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 3568 // If there is some other early clobber and this is an input register, 3569 // then we are forced to pre-allocate the input reg so it doesn't 3570 // conflict with the earlyclobber. 3571 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 3572 RegVT = *PhysReg.second->vt_begin(); 3573 3574 if (OpInfo.ConstraintVT == MVT::Other) 3575 ValueVT = RegVT; 3576 3577 // Create the appropriate number of virtual registers. 3578 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 3579 for (; NumRegs; --NumRegs) 3580 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second)); 3581 3582 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3583 return; 3584 } 3585 3586 // Otherwise, we can't allocate it. Let the code below figure out how to 3587 // maintain these constraints. 3588 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3589 3590 } else { 3591 // This is a reference to a register class that doesn't directly correspond 3592 // to an LLVM register class. Allocate NumRegs consecutive, available, 3593 // registers from the class. 3594 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3595 OpInfo.ConstraintVT); 3596 } 3597 3598 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 3599 unsigned NumAllocated = 0; 3600 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3601 unsigned Reg = RegClassRegs[i]; 3602 // See if this register is available. 3603 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3604 (isInReg && InputRegs.count(Reg))) { // Already used. 3605 // Make sure we find consecutive registers. 3606 NumAllocated = 0; 3607 continue; 3608 } 3609 3610 // Check to see if this register is allocatable (i.e. don't give out the 3611 // stack pointer). 3612 if (RC == 0) { 3613 RC = isAllocatableRegister(Reg, MF, TLI, TRI); 3614 if (!RC) { // Couldn't allocate this register. 3615 // Reset NumAllocated to make sure we return consecutive registers. 3616 NumAllocated = 0; 3617 continue; 3618 } 3619 } 3620 3621 // Okay, this register is good, we can use it. 3622 ++NumAllocated; 3623 3624 // If we allocated enough consecutive registers, succeed. 3625 if (NumAllocated == NumRegs) { 3626 unsigned RegStart = (i-NumAllocated)+1; 3627 unsigned RegEnd = i+1; 3628 // Mark all of the allocated registers used. 3629 for (unsigned i = RegStart; i != RegEnd; ++i) 3630 Regs.push_back(RegClassRegs[i]); 3631 3632 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 3633 OpInfo.ConstraintVT); 3634 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 3635 return; 3636 } 3637 } 3638 3639 // Otherwise, we couldn't allocate enough registers for this. 3640 return; 3641} 3642 3643 3644/// visitInlineAsm - Handle a call to an InlineAsm object. 3645/// 3646void SelectionDAGLowering::visitInlineAsm(CallSite CS) { 3647 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 3648 3649 /// ConstraintOperands - Information about all of the constraints. 3650 std::vector<AsmOperandInfo> ConstraintOperands; 3651 3652 SDOperand Chain = getRoot(); 3653 SDOperand Flag; 3654 3655 std::set<unsigned> OutputRegs, InputRegs; 3656 3657 // Do a prepass over the constraints, canonicalizing them, and building up the 3658 // ConstraintOperands list. 3659 std::vector<InlineAsm::ConstraintInfo> 3660 ConstraintInfos = IA->ParseConstraints(); 3661 3662 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 3663 // constraint. If so, we can't let the register allocator allocate any input 3664 // registers, because it will not know to avoid the earlyclobbered output reg. 3665 bool SawEarlyClobber = false; 3666 3667 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 3668 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3669 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 3670 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 3671 3672 MVT::ValueType OpVT = MVT::Other; 3673 3674 // Compute the value type for each operand. 3675 switch (OpInfo.Type) { 3676 case InlineAsm::isOutput: 3677 if (!OpInfo.isIndirect) { 3678 // The return value of the call is this value. As such, there is no 3679 // corresponding argument. 3680 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 3681 OpVT = TLI.getValueType(CS.getType()); 3682 } else { 3683 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 3684 } 3685 break; 3686 case InlineAsm::isInput: 3687 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 3688 break; 3689 case InlineAsm::isClobber: 3690 // Nothing to do. 3691 break; 3692 } 3693 3694 // If this is an input or an indirect output, process the call argument. 3695 // BasicBlocks are labels, currently appearing only in asm's. 3696 if (OpInfo.CallOperandVal) { 3697 if (isa<BasicBlock>(OpInfo.CallOperandVal)) 3698 OpInfo.CallOperand = 3699 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>( 3700 OpInfo.CallOperandVal)]); 3701 else { 3702 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 3703 const Type *OpTy = OpInfo.CallOperandVal->getType(); 3704 // If this is an indirect operand, the operand is a pointer to the 3705 // accessed type. 3706 if (OpInfo.isIndirect) 3707 OpTy = cast<PointerType>(OpTy)->getElementType(); 3708 3709 // If OpTy is not a first-class value, it may be a struct/union that we 3710 // can tile with integers. 3711 if (!OpTy->isFirstClassType() && OpTy->isSized()) { 3712 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3713 switch (BitSize) { 3714 default: break; 3715 case 1: 3716 case 8: 3717 case 16: 3718 case 32: 3719 case 64: 3720 OpTy = IntegerType::get(BitSize); 3721 break; 3722 } 3723 } 3724 3725 OpVT = TLI.getValueType(OpTy, true); 3726 } 3727 } 3728 3729 OpInfo.ConstraintVT = OpVT; 3730 3731 // Compute the constraint code and ConstraintType to use. 3732 OpInfo.ComputeConstraintToUse(TLI); 3733 3734 // Keep track of whether we see an earlyclobber. 3735 SawEarlyClobber |= OpInfo.isEarlyClobber; 3736 3737 // If we see a clobber of a register, it is an early clobber. 3738 if (!SawEarlyClobber && 3739 OpInfo.Type == InlineAsm::isClobber && 3740 OpInfo.ConstraintType == TargetLowering::C_Register) { 3741 // Note that we want to ignore things that we don't trick here, like 3742 // dirflag, fpsr, flags, etc. 3743 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3744 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3745 OpInfo.ConstraintVT); 3746 if (PhysReg.first || PhysReg.second) { 3747 // This is a register we know of. 3748 SawEarlyClobber = true; 3749 } 3750 } 3751 3752 // If this is a memory input, and if the operand is not indirect, do what we 3753 // need to to provide an address for the memory input. 3754 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 3755 !OpInfo.isIndirect) { 3756 assert(OpInfo.Type == InlineAsm::isInput && 3757 "Can only indirectify direct input operands!"); 3758 3759 // Memory operands really want the address of the value. If we don't have 3760 // an indirect input, put it in the constpool if we can, otherwise spill 3761 // it to a stack slot. 3762 3763 // If the operand is a float, integer, or vector constant, spill to a 3764 // constant pool entry to get its address. 3765 Value *OpVal = OpInfo.CallOperandVal; 3766 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 3767 isa<ConstantVector>(OpVal)) { 3768 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 3769 TLI.getPointerTy()); 3770 } else { 3771 // Otherwise, create a stack slot and emit a store to it before the 3772 // asm. 3773 const Type *Ty = OpVal->getType(); 3774 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 3775 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3776 MachineFunction &MF = DAG.getMachineFunction(); 3777 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3778 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3779 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 3780 OpInfo.CallOperand = StackSlot; 3781 } 3782 3783 // There is no longer a Value* corresponding to this operand. 3784 OpInfo.CallOperandVal = 0; 3785 // It is now an indirect operand. 3786 OpInfo.isIndirect = true; 3787 } 3788 3789 // If this constraint is for a specific register, allocate it before 3790 // anything else. 3791 if (OpInfo.ConstraintType == TargetLowering::C_Register) 3792 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3793 } 3794 ConstraintInfos.clear(); 3795 3796 3797 // Second pass - Loop over all of the operands, assigning virtual or physregs 3798 // to registerclass operands. 3799 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3800 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3801 3802 // C_Register operands have already been allocated, Other/Memory don't need 3803 // to be. 3804 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 3805 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3806 } 3807 3808 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 3809 std::vector<SDOperand> AsmNodeOperands; 3810 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3811 AsmNodeOperands.push_back( 3812 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 3813 3814 3815 // Loop over all of the inputs, copying the operand values into the 3816 // appropriate registers and processing the output regs. 3817 RegsForValue RetValRegs; 3818 3819 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 3820 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3821 3822 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3823 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3824 3825 switch (OpInfo.Type) { 3826 case InlineAsm::isOutput: { 3827 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 3828 OpInfo.ConstraintType != TargetLowering::C_Register) { 3829 // Memory output, or 'other' output (e.g. 'X' constraint). 3830 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 3831 3832 // Add information to the INLINEASM node to know about this output. 3833 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3834 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3835 TLI.getPointerTy())); 3836 AsmNodeOperands.push_back(OpInfo.CallOperand); 3837 break; 3838 } 3839 3840 // Otherwise, this is a register or register class output. 3841 3842 // Copy the output from the appropriate register. Find a register that 3843 // we can use. 3844 if (OpInfo.AssignedRegs.Regs.empty()) { 3845 cerr << "Couldn't allocate output reg for contraint '" 3846 << OpInfo.ConstraintCode << "'!\n"; 3847 exit(1); 3848 } 3849 3850 if (!OpInfo.isIndirect) { 3851 // This is the result value of the call. 3852 assert(RetValRegs.Regs.empty() && 3853 "Cannot have multiple output constraints yet!"); 3854 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 3855 RetValRegs = OpInfo.AssignedRegs; 3856 } else { 3857 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 3858 OpInfo.CallOperandVal)); 3859 } 3860 3861 // Add information to the INLINEASM node to know that this register is 3862 // set. 3863 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 3864 AsmNodeOperands); 3865 break; 3866 } 3867 case InlineAsm::isInput: { 3868 SDOperand InOperandVal = OpInfo.CallOperand; 3869 3870 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 3871 // If this is required to match an output register we have already set, 3872 // just use its register. 3873 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 3874 3875 // Scan until we find the definition we already emitted of this operand. 3876 // When we find it, create a RegsForValue operand. 3877 unsigned CurOp = 2; // The first operand. 3878 for (; OperandNo; --OperandNo) { 3879 // Advance to the next operand. 3880 unsigned NumOps = 3881 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3882 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3883 (NumOps & 7) == 4 /*MEM*/) && 3884 "Skipped past definitions?"); 3885 CurOp += (NumOps>>3)+1; 3886 } 3887 3888 unsigned NumOps = 3889 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3890 if ((NumOps & 7) == 2 /*REGDEF*/) { 3891 // Add NumOps>>3 registers to MatchedRegs. 3892 RegsForValue MatchedRegs; 3893 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3894 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3895 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3896 unsigned Reg = 3897 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3898 MatchedRegs.Regs.push_back(Reg); 3899 } 3900 3901 // Use the produced MatchedRegs object to 3902 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3903 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3904 break; 3905 } else { 3906 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3907 assert((NumOps >> 3) == 1 && "Unexpected number of operands"); 3908 // Add information to the INLINEASM node to know about this input. 3909 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3910 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3911 TLI.getPointerTy())); 3912 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 3913 break; 3914 } 3915 } 3916 3917 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 3918 assert(!OpInfo.isIndirect && 3919 "Don't know how to handle indirect other inputs yet!"); 3920 3921 std::vector<SDOperand> Ops; 3922 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 3923 Ops, DAG); 3924 if (Ops.empty()) { 3925 cerr << "Invalid operand for inline asm constraint '" 3926 << OpInfo.ConstraintCode << "'!\n"; 3927 exit(1); 3928 } 3929 3930 // Add information to the INLINEASM node to know about this input. 3931 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 3932 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3933 TLI.getPointerTy())); 3934 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 3935 break; 3936 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 3937 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 3938 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 3939 "Memory operands expect pointer values"); 3940 3941 // Add information to the INLINEASM node to know about this input. 3942 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3943 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3944 TLI.getPointerTy())); 3945 AsmNodeOperands.push_back(InOperandVal); 3946 break; 3947 } 3948 3949 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 3950 OpInfo.ConstraintType == TargetLowering::C_Register) && 3951 "Unknown constraint type!"); 3952 assert(!OpInfo.isIndirect && 3953 "Don't know how to handle indirect register inputs yet!"); 3954 3955 // Copy the input into the appropriate registers. 3956 assert(!OpInfo.AssignedRegs.Regs.empty() && 3957 "Couldn't allocate input reg!"); 3958 3959 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3960 3961 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 3962 AsmNodeOperands); 3963 break; 3964 } 3965 case InlineAsm::isClobber: { 3966 // Add the clobbered value to the operand list, so that the register 3967 // allocator is aware that the physreg got clobbered. 3968 if (!OpInfo.AssignedRegs.Regs.empty()) 3969 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 3970 AsmNodeOperands); 3971 break; 3972 } 3973 } 3974 } 3975 3976 // Finish up input operands. 3977 AsmNodeOperands[0] = Chain; 3978 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3979 3980 Chain = DAG.getNode(ISD::INLINEASM, 3981 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3982 &AsmNodeOperands[0], AsmNodeOperands.size()); 3983 Flag = Chain.getValue(1); 3984 3985 // If this asm returns a register value, copy the result from that register 3986 // and set it as the value of the call. 3987 if (!RetValRegs.Regs.empty()) { 3988 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 3989 3990 // If the result of the inline asm is a vector, it may have the wrong 3991 // width/num elts. Make sure to convert it to the right type with 3992 // bit_convert. 3993 if (MVT::isVector(Val.getValueType())) { 3994 const VectorType *VTy = cast<VectorType>(CS.getType()); 3995 MVT::ValueType DesiredVT = TLI.getValueType(VTy); 3996 3997 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val); 3998 } 3999 4000 setValue(CS.getInstruction(), Val); 4001 } 4002 4003 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 4004 4005 // Process indirect outputs, first output all of the flagged copies out of 4006 // physregs. 4007 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 4008 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 4009 Value *Ptr = IndirectStoresToEmit[i].second; 4010 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 4011 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 4012 } 4013 4014 // Emit the non-flagged stores from the physregs. 4015 SmallVector<SDOperand, 8> OutChains; 4016 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 4017 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 4018 getValue(StoresToEmit[i].second), 4019 StoresToEmit[i].second, 0)); 4020 if (!OutChains.empty()) 4021 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4022 &OutChains[0], OutChains.size()); 4023 DAG.setRoot(Chain); 4024} 4025 4026 4027void SelectionDAGLowering::visitMalloc(MallocInst &I) { 4028 SDOperand Src = getValue(I.getOperand(0)); 4029 4030 MVT::ValueType IntPtr = TLI.getPointerTy(); 4031 4032 if (IntPtr < Src.getValueType()) 4033 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 4034 else if (IntPtr > Src.getValueType()) 4035 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 4036 4037 // Scale the source by the type size. 4038 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType()); 4039 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 4040 Src, DAG.getIntPtrConstant(ElementSize)); 4041 4042 TargetLowering::ArgListTy Args; 4043 TargetLowering::ArgListEntry Entry; 4044 Entry.Node = Src; 4045 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 4046 Args.push_back(Entry); 4047 4048 std::pair<SDOperand,SDOperand> Result = 4049 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C, 4050 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG); 4051 setValue(&I, Result.first); // Pointers always fit in registers 4052 DAG.setRoot(Result.second); 4053} 4054 4055void SelectionDAGLowering::visitFree(FreeInst &I) { 4056 TargetLowering::ArgListTy Args; 4057 TargetLowering::ArgListEntry Entry; 4058 Entry.Node = getValue(I.getOperand(0)); 4059 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 4060 Args.push_back(Entry); 4061 MVT::ValueType IntPtr = TLI.getPointerTy(); 4062 std::pair<SDOperand,SDOperand> Result = 4063 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, 4064 CallingConv::C, true, 4065 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 4066 DAG.setRoot(Result.second); 4067} 4068 4069// EmitInstrWithCustomInserter - This method should be implemented by targets 4070// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 4071// instructions are special in various ways, which require special support to 4072// insert. The specified MachineInstr is created but not inserted into any 4073// basic blocks, and the scheduler passes ownership of it to this method. 4074MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4075 MachineBasicBlock *MBB) { 4076 cerr << "If a target marks an instruction with " 4077 << "'usesCustomDAGSchedInserter', it must implement " 4078 << "TargetLowering::EmitInstrWithCustomInserter!\n"; 4079 abort(); 4080 return 0; 4081} 4082 4083void SelectionDAGLowering::visitVAStart(CallInst &I) { 4084 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 4085 getValue(I.getOperand(1)), 4086 DAG.getSrcValue(I.getOperand(1)))); 4087} 4088 4089void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 4090 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 4091 getValue(I.getOperand(0)), 4092 DAG.getSrcValue(I.getOperand(0))); 4093 setValue(&I, V); 4094 DAG.setRoot(V.getValue(1)); 4095} 4096 4097void SelectionDAGLowering::visitVAEnd(CallInst &I) { 4098 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 4099 getValue(I.getOperand(1)), 4100 DAG.getSrcValue(I.getOperand(1)))); 4101} 4102 4103void SelectionDAGLowering::visitVACopy(CallInst &I) { 4104 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 4105 getValue(I.getOperand(1)), 4106 getValue(I.getOperand(2)), 4107 DAG.getSrcValue(I.getOperand(1)), 4108 DAG.getSrcValue(I.getOperand(2)))); 4109} 4110 4111/// TargetLowering::LowerArguments - This is the default LowerArguments 4112/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 4113/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 4114/// integrated into SDISel. 4115std::vector<SDOperand> 4116TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 4117 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 4118 std::vector<SDOperand> Ops; 4119 Ops.push_back(DAG.getRoot()); 4120 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 4121 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 4122 4123 // Add one result value for each formal argument. 4124 std::vector<MVT::ValueType> RetVals; 4125 unsigned j = 1; 4126 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 4127 I != E; ++I, ++j) { 4128 MVT::ValueType VT = getValueType(I->getType()); 4129 unsigned Flags = ISD::ParamFlags::NoFlagSet; 4130 unsigned OriginalAlignment = 4131 getTargetData()->getABITypeAlignment(I->getType()); 4132 4133 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 4134 // that is zero extended! 4135 if (F.paramHasAttr(j, ParamAttr::ZExt)) 4136 Flags &= ~(ISD::ParamFlags::SExt); 4137 if (F.paramHasAttr(j, ParamAttr::SExt)) 4138 Flags |= ISD::ParamFlags::SExt; 4139 if (F.paramHasAttr(j, ParamAttr::InReg)) 4140 Flags |= ISD::ParamFlags::InReg; 4141 if (F.paramHasAttr(j, ParamAttr::StructRet)) 4142 Flags |= ISD::ParamFlags::StructReturn; 4143 if (F.paramHasAttr(j, ParamAttr::ByVal)) { 4144 Flags |= ISD::ParamFlags::ByVal; 4145 const PointerType *Ty = cast<PointerType>(I->getType()); 4146 const Type *ElementTy = Ty->getElementType(); 4147 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy)); 4148 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); 4149 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs); 4150 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs); 4151 } 4152 if (F.paramHasAttr(j, ParamAttr::Nest)) 4153 Flags |= ISD::ParamFlags::Nest; 4154 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs); 4155 4156 MVT::ValueType RegisterVT = getRegisterType(VT); 4157 unsigned NumRegs = getNumRegisters(VT); 4158 for (unsigned i = 0; i != NumRegs; ++i) { 4159 RetVals.push_back(RegisterVT); 4160 // if it isn't first piece, alignment must be 1 4161 if (i > 0) 4162 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 4163 (1 << ISD::ParamFlags::OrigAlignmentOffs); 4164 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4165 } 4166 } 4167 4168 RetVals.push_back(MVT::Other); 4169 4170 // Create the node. 4171 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 4172 DAG.getVTList(&RetVals[0], RetVals.size()), 4173 &Ops[0], Ops.size()).Val; 4174 4175 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but 4176 // allows exposing the loads that may be part of the argument access to the 4177 // first DAGCombiner pass. 4178 SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG); 4179 4180 // The number of results should match up, except that the lowered one may have 4181 // an extra flag result. 4182 assert((Result->getNumValues() == TmpRes.Val->getNumValues() || 4183 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() && 4184 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag)) 4185 && "Lowering produced unexpected number of results!"); 4186 Result = TmpRes.Val; 4187 4188 unsigned NumArgRegs = Result->getNumValues() - 1; 4189 DAG.setRoot(SDOperand(Result, NumArgRegs)); 4190 4191 // Set up the return result vector. 4192 Ops.clear(); 4193 unsigned i = 0; 4194 unsigned Idx = 1; 4195 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 4196 ++I, ++Idx) { 4197 MVT::ValueType VT = getValueType(I->getType()); 4198 MVT::ValueType PartVT = getRegisterType(VT); 4199 4200 unsigned NumParts = getNumRegisters(VT); 4201 SmallVector<SDOperand, 4> Parts(NumParts); 4202 for (unsigned j = 0; j != NumParts; ++j) 4203 Parts[j] = SDOperand(Result, i++); 4204 4205 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4206 if (F.paramHasAttr(Idx, ParamAttr::SExt)) 4207 AssertOp = ISD::AssertSext; 4208 else if (F.paramHasAttr(Idx, ParamAttr::ZExt)) 4209 AssertOp = ISD::AssertZext; 4210 4211 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT, 4212 AssertOp, true)); 4213 } 4214 assert(i == NumArgRegs && "Argument register count mismatch!"); 4215 return Ops; 4216} 4217 4218 4219/// TargetLowering::LowerCallTo - This is the default LowerCallTo 4220/// implementation, which just inserts an ISD::CALL node, which is later custom 4221/// lowered by the target to something concrete. FIXME: When all targets are 4222/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 4223std::pair<SDOperand, SDOperand> 4224TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 4225 bool RetSExt, bool RetZExt, bool isVarArg, 4226 unsigned CallingConv, bool isTailCall, 4227 SDOperand Callee, 4228 ArgListTy &Args, SelectionDAG &DAG) { 4229 SmallVector<SDOperand, 32> Ops; 4230 Ops.push_back(Chain); // Op#0 - Chain 4231 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 4232 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 4233 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 4234 Ops.push_back(Callee); 4235 4236 // Handle all of the outgoing arguments. 4237 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 4238 MVT::ValueType VT = getValueType(Args[i].Ty); 4239 SDOperand Op = Args[i].Node; 4240 unsigned Flags = ISD::ParamFlags::NoFlagSet; 4241 unsigned OriginalAlignment = 4242 getTargetData()->getABITypeAlignment(Args[i].Ty); 4243 4244 if (Args[i].isSExt) 4245 Flags |= ISD::ParamFlags::SExt; 4246 if (Args[i].isZExt) 4247 Flags |= ISD::ParamFlags::ZExt; 4248 if (Args[i].isInReg) 4249 Flags |= ISD::ParamFlags::InReg; 4250 if (Args[i].isSRet) 4251 Flags |= ISD::ParamFlags::StructReturn; 4252 if (Args[i].isByVal) { 4253 Flags |= ISD::ParamFlags::ByVal; 4254 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 4255 const Type *ElementTy = Ty->getElementType(); 4256 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy)); 4257 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); 4258 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs); 4259 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs); 4260 } 4261 if (Args[i].isNest) 4262 Flags |= ISD::ParamFlags::Nest; 4263 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs; 4264 4265 MVT::ValueType PartVT = getRegisterType(VT); 4266 unsigned NumParts = getNumRegisters(VT); 4267 SmallVector<SDOperand, 4> Parts(NumParts); 4268 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 4269 4270 if (Args[i].isSExt) 4271 ExtendKind = ISD::SIGN_EXTEND; 4272 else if (Args[i].isZExt) 4273 ExtendKind = ISD::ZERO_EXTEND; 4274 4275 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind); 4276 4277 for (unsigned i = 0; i != NumParts; ++i) { 4278 // if it isn't first piece, alignment must be 1 4279 unsigned MyFlags = Flags; 4280 if (i != 0) 4281 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) | 4282 (1 << ISD::ParamFlags::OrigAlignmentOffs); 4283 4284 Ops.push_back(Parts[i]); 4285 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32)); 4286 } 4287 } 4288 4289 // Figure out the result value types. 4290 MVT::ValueType VT = getValueType(RetTy); 4291 MVT::ValueType RegisterVT = getRegisterType(VT); 4292 unsigned NumRegs = getNumRegisters(VT); 4293 SmallVector<MVT::ValueType, 4> RetTys(NumRegs); 4294 for (unsigned i = 0; i != NumRegs; ++i) 4295 RetTys[i] = RegisterVT; 4296 4297 RetTys.push_back(MVT::Other); // Always has a chain. 4298 4299 // Create the CALL node. 4300 SDOperand Res = DAG.getNode(ISD::CALL, 4301 DAG.getVTList(&RetTys[0], NumRegs + 1), 4302 &Ops[0], Ops.size()); 4303 Chain = Res.getValue(NumRegs); 4304 4305 // Gather up the call result into a single value. 4306 if (RetTy != Type::VoidTy) { 4307 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4308 4309 if (RetSExt) 4310 AssertOp = ISD::AssertSext; 4311 else if (RetZExt) 4312 AssertOp = ISD::AssertZext; 4313 4314 SmallVector<SDOperand, 4> Results(NumRegs); 4315 for (unsigned i = 0; i != NumRegs; ++i) 4316 Results[i] = Res.getValue(i); 4317 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, 4318 AssertOp, true); 4319 } 4320 4321 return std::make_pair(Res, Chain); 4322} 4323 4324SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4325 assert(0 && "LowerOperation not implemented for this target!"); 4326 abort(); 4327 return SDOperand(); 4328} 4329 4330SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 4331 SelectionDAG &DAG) { 4332 assert(0 && "CustomPromoteOperation not implemented for this target!"); 4333 abort(); 4334 return SDOperand(); 4335} 4336 4337/// getMemsetValue - Vectorized representation of the memset value 4338/// operand. 4339static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 4340 SelectionDAG &DAG) { 4341 MVT::ValueType CurVT = VT; 4342 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 4343 uint64_t Val = C->getValue() & 255; 4344 unsigned Shift = 8; 4345 while (CurVT != MVT::i8) { 4346 Val = (Val << Shift) | Val; 4347 Shift <<= 1; 4348 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4349 } 4350 return DAG.getConstant(Val, VT); 4351 } else { 4352 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4353 unsigned Shift = 8; 4354 while (CurVT != MVT::i8) { 4355 Value = 4356 DAG.getNode(ISD::OR, VT, 4357 DAG.getNode(ISD::SHL, VT, Value, 4358 DAG.getConstant(Shift, MVT::i8)), Value); 4359 Shift <<= 1; 4360 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4361 } 4362 4363 return Value; 4364 } 4365} 4366 4367/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4368/// used when a memcpy is turned into a memset when the source is a constant 4369/// string ptr. 4370static SDOperand getMemsetStringVal(MVT::ValueType VT, 4371 SelectionDAG &DAG, TargetLowering &TLI, 4372 std::string &Str, unsigned Offset) { 4373 uint64_t Val = 0; 4374 unsigned MSB = MVT::getSizeInBits(VT) / 8; 4375 if (TLI.isLittleEndian()) 4376 Offset = Offset + MSB - 1; 4377 for (unsigned i = 0; i != MSB; ++i) { 4378 Val = (Val << 8) | (unsigned char)Str[Offset]; 4379 Offset += TLI.isLittleEndian() ? -1 : 1; 4380 } 4381 return DAG.getConstant(Val, VT); 4382} 4383 4384/// getMemBasePlusOffset - Returns base and offset node for the 4385static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4386 SelectionDAG &DAG, TargetLowering &TLI) { 4387 MVT::ValueType VT = Base.getValueType(); 4388 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4389} 4390 4391/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4392/// to replace the memset / memcpy is below the threshold. It also returns the 4393/// types of the sequence of memory ops to perform memset / memcpy. 4394static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4395 unsigned Limit, uint64_t Size, 4396 unsigned Align, TargetLowering &TLI) { 4397 MVT::ValueType VT; 4398 4399 if (TLI.allowsUnalignedMemoryAccesses()) { 4400 VT = MVT::i64; 4401 } else { 4402 switch (Align & 7) { 4403 case 0: 4404 VT = MVT::i64; 4405 break; 4406 case 4: 4407 VT = MVT::i32; 4408 break; 4409 case 2: 4410 VT = MVT::i16; 4411 break; 4412 default: 4413 VT = MVT::i8; 4414 break; 4415 } 4416 } 4417 4418 MVT::ValueType LVT = MVT::i64; 4419 while (!TLI.isTypeLegal(LVT)) 4420 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4421 assert(MVT::isInteger(LVT)); 4422 4423 if (VT > LVT) 4424 VT = LVT; 4425 4426 unsigned NumMemOps = 0; 4427 while (Size != 0) { 4428 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4429 while (VTSize > Size) { 4430 VT = (MVT::ValueType)((unsigned)VT - 1); 4431 VTSize >>= 1; 4432 } 4433 assert(MVT::isInteger(VT)); 4434 4435 if (++NumMemOps > Limit) 4436 return false; 4437 MemOps.push_back(VT); 4438 Size -= VTSize; 4439 } 4440 4441 return true; 4442} 4443 4444void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4445 SDOperand Op1 = getValue(I.getOperand(1)); 4446 SDOperand Op2 = getValue(I.getOperand(2)); 4447 SDOperand Op3 = getValue(I.getOperand(3)); 4448 SDOperand Op4 = getValue(I.getOperand(4)); 4449 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4450 if (Align == 0) Align = 1; 4451 4452 // If the source and destination are known to not be aliases, we can 4453 // lower memmove as memcpy. 4454 if (Op == ISD::MEMMOVE) { 4455 uint64_t Size = -1ULL; 4456 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 4457 Size = C->getValue(); 4458 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) == 4459 AliasAnalysis::NoAlias) 4460 Op = ISD::MEMCPY; 4461 } 4462 4463 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4464 std::vector<MVT::ValueType> MemOps; 4465 4466 // Expand memset / memcpy to a series of load / store ops 4467 // if the size operand falls below a certain threshold. 4468 SmallVector<SDOperand, 8> OutChains; 4469 switch (Op) { 4470 default: break; // Do nothing for now. 4471 case ISD::MEMSET: { 4472 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4473 Size->getValue(), Align, TLI)) { 4474 unsigned NumMemOps = MemOps.size(); 4475 unsigned Offset = 0; 4476 for (unsigned i = 0; i < NumMemOps; i++) { 4477 MVT::ValueType VT = MemOps[i]; 4478 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4479 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4480 SDOperand Store = DAG.getStore(getRoot(), Value, 4481 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4482 I.getOperand(1), Offset); 4483 OutChains.push_back(Store); 4484 Offset += VTSize; 4485 } 4486 } 4487 break; 4488 } 4489 case ISD::MEMCPY: { 4490 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4491 Size->getValue(), Align, TLI)) { 4492 unsigned NumMemOps = MemOps.size(); 4493 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4494 GlobalAddressSDNode *G = NULL; 4495 std::string Str; 4496 bool CopyFromStr = false; 4497 4498 if (Op2.getOpcode() == ISD::GlobalAddress) 4499 G = cast<GlobalAddressSDNode>(Op2); 4500 else if (Op2.getOpcode() == ISD::ADD && 4501 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4502 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4503 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4504 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4505 } 4506 if (G) { 4507 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4508 if (GV && GV->isConstant()) { 4509 Str = GV->getStringValue(false); 4510 if (!Str.empty()) { 4511 CopyFromStr = true; 4512 SrcOff += SrcDelta; 4513 } 4514 } 4515 } 4516 4517 for (unsigned i = 0; i < NumMemOps; i++) { 4518 MVT::ValueType VT = MemOps[i]; 4519 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4520 SDOperand Value, Chain, Store; 4521 4522 if (CopyFromStr) { 4523 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4524 Chain = getRoot(); 4525 Store = 4526 DAG.getStore(Chain, Value, 4527 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4528 I.getOperand(1), DstOff); 4529 } else { 4530 Value = DAG.getLoad(VT, getRoot(), 4531 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4532 I.getOperand(2), SrcOff, false, Align); 4533 Chain = Value.getValue(1); 4534 Store = 4535 DAG.getStore(Chain, Value, 4536 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4537 I.getOperand(1), DstOff, false, Align); 4538 } 4539 OutChains.push_back(Store); 4540 SrcOff += VTSize; 4541 DstOff += VTSize; 4542 } 4543 } 4544 break; 4545 } 4546 } 4547 4548 if (!OutChains.empty()) { 4549 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4550 &OutChains[0], OutChains.size())); 4551 return; 4552 } 4553 } 4554 4555 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1); 4556 SDOperand Node; 4557 switch(Op) { 4558 default: 4559 assert(0 && "Unknown Op"); 4560 case ISD::MEMCPY: 4561 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4562 break; 4563 case ISD::MEMMOVE: 4564 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4565 break; 4566 case ISD::MEMSET: 4567 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4568 break; 4569 } 4570 DAG.setRoot(Node); 4571} 4572 4573//===----------------------------------------------------------------------===// 4574// SelectionDAGISel code 4575//===----------------------------------------------------------------------===// 4576 4577unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4578 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 4579} 4580 4581void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4582 AU.addRequired<AliasAnalysis>(); 4583 AU.addRequired<CollectorModuleMetadata>(); 4584 AU.setPreservesAll(); 4585} 4586 4587 4588 4589bool SelectionDAGISel::runOnFunction(Function &Fn) { 4590 // Get alias analysis for load/store combining. 4591 AA = &getAnalysis<AliasAnalysis>(); 4592 4593 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4594 if (MF.getFunction()->hasCollector()) 4595 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction()); 4596 else 4597 GCI = 0; 4598 RegInfo = &MF.getRegInfo(); 4599 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4600 4601 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4602 4603 if (ExceptionHandling) 4604 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4605 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4606 // Mark landing pad. 4607 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4608 4609 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4610 SelectBasicBlock(I, MF, FuncInfo); 4611 4612 // Add function live-ins to entry block live-in set. 4613 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4614 BB = FuncInfo.MBBMap[EntryBB]; 4615 if (!RegInfo->livein_empty()) 4616 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 4617 E = RegInfo->livein_end(); I != E; ++I) 4618 BB->addLiveIn(I->first); 4619 4620#ifndef NDEBUG 4621 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4622 "Not all catch info was assigned to a landing pad!"); 4623#endif 4624 4625 return true; 4626} 4627 4628SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4629 unsigned Reg) { 4630 SDOperand Op = getValue(V); 4631 assert((Op.getOpcode() != ISD::CopyFromReg || 4632 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4633 "Copy from a reg to the same reg!"); 4634 4635 MVT::ValueType SrcVT = Op.getValueType(); 4636 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT); 4637 unsigned NumRegs = TLI.getNumRegisters(SrcVT); 4638 SmallVector<SDOperand, 8> Regs(NumRegs); 4639 SmallVector<SDOperand, 8> Chains(NumRegs); 4640 4641 // Copy the value by legal parts into sequential virtual registers. 4642 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT); 4643 for (unsigned i = 0; i != NumRegs; ++i) 4644 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); 4645 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 4646} 4647 4648void SelectionDAGISel:: 4649LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4650 std::vector<SDOperand> &UnorderedChains) { 4651 // If this is the entry block, emit arguments. 4652 Function &F = *LLVMBB->getParent(); 4653 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4654 SDOperand OldRoot = SDL.DAG.getRoot(); 4655 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4656 4657 unsigned a = 0; 4658 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4659 AI != E; ++AI, ++a) 4660 if (!AI->use_empty()) { 4661 SDL.setValue(AI, Args[a]); 4662 4663 // If this argument is live outside of the entry block, insert a copy from 4664 // whereever we got it to the vreg that other BB's will reference it as. 4665 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4666 if (VMI != FuncInfo.ValueMap.end()) { 4667 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4668 UnorderedChains.push_back(Copy); 4669 } 4670 } 4671 4672 // Finally, if the target has anything special to do, allow it to do so. 4673 // FIXME: this should insert code into the DAG! 4674 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4675} 4676 4677static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4678 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4679 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4680 if (isSelector(I)) { 4681 // Apply the catch info to DestBB. 4682 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4683#ifndef NDEBUG 4684 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 4685 FLI.CatchInfoFound.insert(I); 4686#endif 4687 } 4688} 4689 4690/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 4691/// DAG and fixes their tailcall attribute operand. 4692static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 4693 TargetLowering& TLI) { 4694 SDNode * Ret = NULL; 4695 SDOperand Terminator = DAG.getRoot(); 4696 4697 // Find RET node. 4698 if (Terminator.getOpcode() == ISD::RET) { 4699 Ret = Terminator.Val; 4700 } 4701 4702 // Fix tail call attribute of CALL nodes. 4703 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 4704 BI = prior(DAG.allnodes_end()); BI != BE; --BI) { 4705 if (BI->getOpcode() == ISD::CALL) { 4706 SDOperand OpRet(Ret, 0); 4707 SDOperand OpCall(static_cast<SDNode*>(BI), 0); 4708 bool isMarkedTailCall = 4709 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0; 4710 // If CALL node has tail call attribute set to true and the call is not 4711 // eligible (no RET or the target rejects) the attribute is fixed to 4712 // false. The TargetLowering::IsEligibleForTailCallOptimization function 4713 // must correctly identify tail call optimizable calls. 4714 if (isMarkedTailCall && 4715 (Ret==NULL || 4716 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) { 4717 SmallVector<SDOperand, 32> Ops; 4718 unsigned idx=0; 4719 for(SDNode::op_iterator I =OpCall.Val->op_begin(), 4720 E=OpCall.Val->op_end(); I!=E; I++, idx++) { 4721 if (idx!=3) 4722 Ops.push_back(*I); 4723 else 4724 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy())); 4725 } 4726 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 4727 } 4728 } 4729 } 4730} 4731 4732void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4733 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4734 FunctionLoweringInfo &FuncInfo) { 4735 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI); 4736 4737 std::vector<SDOperand> UnorderedChains; 4738 4739 // Lower any arguments needed in this block if this is the entry block. 4740 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4741 LowerArguments(LLVMBB, SDL, UnorderedChains); 4742 4743 BB = FuncInfo.MBBMap[LLVMBB]; 4744 SDL.setCurrentBasicBlock(BB); 4745 4746 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4747 4748 if (ExceptionHandling && MMI && BB->isLandingPad()) { 4749 // Add a label to mark the beginning of the landing pad. Deletion of the 4750 // landing pad can thus be detected via the MachineModuleInfo. 4751 unsigned LabelID = MMI->addLandingPad(BB); 4752 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 4753 DAG.getConstant(LabelID, MVT::i32), 4754 DAG.getConstant(1, MVT::i32))); 4755 4756 // Mark exception register as live in. 4757 unsigned Reg = TLI.getExceptionAddressRegister(); 4758 if (Reg) BB->addLiveIn(Reg); 4759 4760 // Mark exception selector register as live in. 4761 Reg = TLI.getExceptionSelectorRegister(); 4762 if (Reg) BB->addLiveIn(Reg); 4763 4764 // FIXME: Hack around an exception handling flaw (PR1508): the personality 4765 // function and list of typeids logically belong to the invoke (or, if you 4766 // like, the basic block containing the invoke), and need to be associated 4767 // with it in the dwarf exception handling tables. Currently however the 4768 // information is provided by an intrinsic (eh.selector) that can be moved 4769 // to unexpected places by the optimizers: if the unwind edge is critical, 4770 // then breaking it can result in the intrinsics being in the successor of 4771 // the landing pad, not the landing pad itself. This results in exceptions 4772 // not being caught because no typeids are associated with the invoke. 4773 // This may not be the only way things can go wrong, but it is the only way 4774 // we try to work around for the moment. 4775 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 4776 4777 if (Br && Br->isUnconditional()) { // Critical edge? 4778 BasicBlock::iterator I, E; 4779 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 4780 if (isSelector(I)) 4781 break; 4782 4783 if (I == E) 4784 // No catch info found - try to extract some from the successor. 4785 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 4786 } 4787 } 4788 4789 // Lower all of the non-terminator instructions. 4790 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4791 I != E; ++I) 4792 SDL.visit(*I); 4793 4794 // Ensure that all instructions which are used outside of their defining 4795 // blocks are available as virtual registers. Invoke is handled elsewhere. 4796 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4797 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 4798 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4799 if (VMI != FuncInfo.ValueMap.end()) 4800 UnorderedChains.push_back( 4801 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4802 } 4803 4804 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4805 // ensure constants are generated when needed. Remember the virtual registers 4806 // that need to be added to the Machine PHI nodes as input. We cannot just 4807 // directly add them, because expansion might result in multiple MBB's for one 4808 // BB. As such, the start of the BB might correspond to a different MBB than 4809 // the end. 4810 // 4811 TerminatorInst *TI = LLVMBB->getTerminator(); 4812 4813 // Emit constants only once even if used by multiple PHI nodes. 4814 std::map<Constant*, unsigned> ConstantsOut; 4815 4816 // Vector bool would be better, but vector<bool> is really slow. 4817 std::vector<unsigned char> SuccsHandled; 4818 if (TI->getNumSuccessors()) 4819 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4820 4821 // Check successor nodes' PHI nodes that expect a constant to be available 4822 // from this block. 4823 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4824 BasicBlock *SuccBB = TI->getSuccessor(succ); 4825 if (!isa<PHINode>(SuccBB->begin())) continue; 4826 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4827 4828 // If this terminator has multiple identical successors (common for 4829 // switches), only handle each succ once. 4830 unsigned SuccMBBNo = SuccMBB->getNumber(); 4831 if (SuccsHandled[SuccMBBNo]) continue; 4832 SuccsHandled[SuccMBBNo] = true; 4833 4834 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4835 PHINode *PN; 4836 4837 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4838 // nodes and Machine PHI nodes, but the incoming operands have not been 4839 // emitted yet. 4840 for (BasicBlock::iterator I = SuccBB->begin(); 4841 (PN = dyn_cast<PHINode>(I)); ++I) { 4842 // Ignore dead phi's. 4843 if (PN->use_empty()) continue; 4844 4845 unsigned Reg; 4846 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4847 4848 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4849 unsigned &RegOut = ConstantsOut[C]; 4850 if (RegOut == 0) { 4851 RegOut = FuncInfo.CreateRegForValue(C); 4852 UnorderedChains.push_back( 4853 SDL.CopyValueToVirtualRegister(C, RegOut)); 4854 } 4855 Reg = RegOut; 4856 } else { 4857 Reg = FuncInfo.ValueMap[PHIOp]; 4858 if (Reg == 0) { 4859 assert(isa<AllocaInst>(PHIOp) && 4860 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4861 "Didn't codegen value into a register!??"); 4862 Reg = FuncInfo.CreateRegForValue(PHIOp); 4863 UnorderedChains.push_back( 4864 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4865 } 4866 } 4867 4868 // Remember that this register needs to added to the machine PHI node as 4869 // the input for this MBB. 4870 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4871 unsigned NumRegisters = TLI.getNumRegisters(VT); 4872 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 4873 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4874 } 4875 } 4876 ConstantsOut.clear(); 4877 4878 // Turn all of the unordered chains into one factored node. 4879 if (!UnorderedChains.empty()) { 4880 SDOperand Root = SDL.getRoot(); 4881 if (Root.getOpcode() != ISD::EntryToken) { 4882 unsigned i = 0, e = UnorderedChains.size(); 4883 for (; i != e; ++i) { 4884 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4885 if (UnorderedChains[i].Val->getOperand(0) == Root) 4886 break; // Don't add the root if we already indirectly depend on it. 4887 } 4888 4889 if (i == e) 4890 UnorderedChains.push_back(Root); 4891 } 4892 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4893 &UnorderedChains[0], UnorderedChains.size())); 4894 } 4895 4896 // Lower the terminator after the copies are emitted. 4897 SDL.visit(*LLVMBB->getTerminator()); 4898 4899 // Copy over any CaseBlock records that may now exist due to SwitchInst 4900 // lowering, as well as any jump table information. 4901 SwitchCases.clear(); 4902 SwitchCases = SDL.SwitchCases; 4903 JTCases.clear(); 4904 JTCases = SDL.JTCases; 4905 BitTestCases.clear(); 4906 BitTestCases = SDL.BitTestCases; 4907 4908 // Make sure the root of the DAG is up-to-date. 4909 DAG.setRoot(SDL.getRoot()); 4910 4911 // Check whether calls in this block are real tail calls. Fix up CALL nodes 4912 // with correct tailcall attribute so that the target can rely on the tailcall 4913 // attribute indicating whether the call is really eligible for tail call 4914 // optimization. 4915 CheckDAGForTailCallsAndFixThem(DAG, TLI); 4916} 4917 4918void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4919 DOUT << "Lowered selection DAG:\n"; 4920 DEBUG(DAG.dump()); 4921 4922 // Run the DAG combiner in pre-legalize mode. 4923 DAG.Combine(false, *AA); 4924 4925 DOUT << "Optimized lowered selection DAG:\n"; 4926 DEBUG(DAG.dump()); 4927 4928 // Second step, hack on the DAG until it only uses operations and types that 4929 // the target supports. 4930#if 0 // Enable this some day. 4931 DAG.LegalizeTypes(); 4932 // Someday even later, enable a dag combine pass here. 4933#endif 4934 DAG.Legalize(); 4935 4936 DOUT << "Legalized selection DAG:\n"; 4937 DEBUG(DAG.dump()); 4938 4939 // Run the DAG combiner in post-legalize mode. 4940 DAG.Combine(true, *AA); 4941 4942 DOUT << "Optimized legalized selection DAG:\n"; 4943 DEBUG(DAG.dump()); 4944 4945 if (ViewISelDAGs) DAG.viewGraph(); 4946 4947 // Third, instruction select all of the operations to machine code, adding the 4948 // code to the MachineBasicBlock. 4949 InstructionSelectBasicBlock(DAG); 4950 4951 DOUT << "Selected machine code:\n"; 4952 DEBUG(BB->dump()); 4953} 4954 4955void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4956 FunctionLoweringInfo &FuncInfo) { 4957 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4958 { 4959 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4960 CurDAG = &DAG; 4961 4962 // First step, lower LLVM code to some DAG. This DAG may use operations and 4963 // types that are not supported by the target. 4964 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4965 4966 // Second step, emit the lowered DAG as machine code. 4967 CodeGenAndEmitDAG(DAG); 4968 } 4969 4970 DOUT << "Total amount of phi nodes to update: " 4971 << PHINodesToUpdate.size() << "\n"; 4972 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4973 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4974 << ", " << PHINodesToUpdate[i].second << ")\n";); 4975 4976 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4977 // PHI nodes in successors. 4978 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4979 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4980 MachineInstr *PHI = PHINodesToUpdate[i].first; 4981 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4982 "This is not a machine PHI node that we are updating!"); 4983 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 4984 false)); 4985 PHI->addOperand(MachineOperand::CreateMBB(BB)); 4986 } 4987 return; 4988 } 4989 4990 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4991 // Lower header first, if it wasn't already lowered 4992 if (!BitTestCases[i].Emitted) { 4993 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4994 CurDAG = &HSDAG; 4995 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); 4996 // Set the current basic block to the mbb we wish to insert the code into 4997 BB = BitTestCases[i].Parent; 4998 HSDL.setCurrentBasicBlock(BB); 4999 // Emit the code 5000 HSDL.visitBitTestHeader(BitTestCases[i]); 5001 HSDAG.setRoot(HSDL.getRoot()); 5002 CodeGenAndEmitDAG(HSDAG); 5003 } 5004 5005 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 5006 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 5007 CurDAG = &BSDAG; 5008 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI); 5009 // Set the current basic block to the mbb we wish to insert the code into 5010 BB = BitTestCases[i].Cases[j].ThisBB; 5011 BSDL.setCurrentBasicBlock(BB); 5012 // Emit the code 5013 if (j+1 != ej) 5014 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 5015 BitTestCases[i].Reg, 5016 BitTestCases[i].Cases[j]); 5017 else 5018 BSDL.visitBitTestCase(BitTestCases[i].Default, 5019 BitTestCases[i].Reg, 5020 BitTestCases[i].Cases[j]); 5021 5022 5023 BSDAG.setRoot(BSDL.getRoot()); 5024 CodeGenAndEmitDAG(BSDAG); 5025 } 5026 5027 // Update PHI Nodes 5028 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 5029 MachineInstr *PHI = PHINodesToUpdate[pi].first; 5030 MachineBasicBlock *PHIBB = PHI->getParent(); 5031 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5032 "This is not a machine PHI node that we are updating!"); 5033 // This is "default" BB. We have two jumps to it. From "header" BB and 5034 // from last "case" BB. 5035 if (PHIBB == BitTestCases[i].Default) { 5036 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5037 false)); 5038 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent)); 5039 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5040 false)); 5041 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases. 5042 back().ThisBB)); 5043 } 5044 // One of "cases" BB. 5045 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 5046 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 5047 if (cBB->succ_end() != 5048 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 5049 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5050 false)); 5051 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 5052 } 5053 } 5054 } 5055 } 5056 5057 // If the JumpTable record is filled in, then we need to emit a jump table. 5058 // Updating the PHI nodes is tricky in this case, since we need to determine 5059 // whether the PHI is a successor of the range check MBB or the jump table MBB 5060 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 5061 // Lower header first, if it wasn't already lowered 5062 if (!JTCases[i].first.Emitted) { 5063 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 5064 CurDAG = &HSDAG; 5065 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); 5066 // Set the current basic block to the mbb we wish to insert the code into 5067 BB = JTCases[i].first.HeaderBB; 5068 HSDL.setCurrentBasicBlock(BB); 5069 // Emit the code 5070 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 5071 HSDAG.setRoot(HSDL.getRoot()); 5072 CodeGenAndEmitDAG(HSDAG); 5073 } 5074 5075 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 5076 CurDAG = &JSDAG; 5077 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI); 5078 // Set the current basic block to the mbb we wish to insert the code into 5079 BB = JTCases[i].second.MBB; 5080 JSDL.setCurrentBasicBlock(BB); 5081 // Emit the code 5082 JSDL.visitJumpTable(JTCases[i].second); 5083 JSDAG.setRoot(JSDL.getRoot()); 5084 CodeGenAndEmitDAG(JSDAG); 5085 5086 // Update PHI Nodes 5087 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 5088 MachineInstr *PHI = PHINodesToUpdate[pi].first; 5089 MachineBasicBlock *PHIBB = PHI->getParent(); 5090 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5091 "This is not a machine PHI node that we are updating!"); 5092 // "default" BB. We can go there only from header BB. 5093 if (PHIBB == JTCases[i].second.Default) { 5094 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5095 false)); 5096 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB)); 5097 } 5098 // JT BB. Just iterate over successors here 5099 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 5100 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5101 false)); 5102 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5103 } 5104 } 5105 } 5106 5107 // If the switch block involved a branch to one of the actual successors, we 5108 // need to update PHI nodes in that block. 5109 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 5110 MachineInstr *PHI = PHINodesToUpdate[i].first; 5111 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5112 "This is not a machine PHI node that we are updating!"); 5113 if (BB->isSuccessor(PHI->getParent())) { 5114 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 5115 false)); 5116 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5117 } 5118 } 5119 5120 // If we generated any switch lowering information, build and codegen any 5121 // additional DAGs necessary. 5122 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 5123 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 5124 CurDAG = &SDAG; 5125 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI); 5126 5127 // Set the current basic block to the mbb we wish to insert the code into 5128 BB = SwitchCases[i].ThisBB; 5129 SDL.setCurrentBasicBlock(BB); 5130 5131 // Emit the code 5132 SDL.visitSwitchCase(SwitchCases[i]); 5133 SDAG.setRoot(SDL.getRoot()); 5134 CodeGenAndEmitDAG(SDAG); 5135 5136 // Handle any PHI nodes in successors of this chunk, as if we were coming 5137 // from the original BB before switch expansion. Note that PHI nodes can 5138 // occur multiple times in PHINodesToUpdate. We have to be very careful to 5139 // handle them the right number of times. 5140 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 5141 for (MachineBasicBlock::iterator Phi = BB->begin(); 5142 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 5143 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 5144 for (unsigned pn = 0; ; ++pn) { 5145 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 5146 if (PHINodesToUpdate[pn].first == Phi) { 5147 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn]. 5148 second, false)); 5149 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB)); 5150 break; 5151 } 5152 } 5153 } 5154 5155 // Don't process RHS if same block as LHS. 5156 if (BB == SwitchCases[i].FalseBB) 5157 SwitchCases[i].FalseBB = 0; 5158 5159 // If we haven't handled the RHS, do so now. Otherwise, we're done. 5160 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 5161 SwitchCases[i].FalseBB = 0; 5162 } 5163 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 5164 } 5165} 5166 5167 5168//===----------------------------------------------------------------------===// 5169/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 5170/// target node in the graph. 5171void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 5172 if (ViewSchedDAGs) DAG.viewGraph(); 5173 5174 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 5175 5176 if (!Ctor) { 5177 Ctor = ISHeuristic; 5178 RegisterScheduler::setDefault(Ctor); 5179 } 5180 5181 ScheduleDAG *SL = Ctor(this, &DAG, BB); 5182 BB = SL->Run(); 5183 5184 if (ViewSUnitDAGs) SL->viewGraph(); 5185 5186 delete SL; 5187} 5188 5189 5190HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 5191 return new HazardRecognizer(); 5192} 5193 5194//===----------------------------------------------------------------------===// 5195// Helper functions used by the generated instruction selector. 5196//===----------------------------------------------------------------------===// 5197// Calls to these methods are generated by tblgen. 5198 5199/// CheckAndMask - The isel is trying to match something like (and X, 255). If 5200/// the dag combiner simplified the 255, we still want to match. RHS is the 5201/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 5202/// specified in the .td file (e.g. 255). 5203bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 5204 int64_t DesiredMaskS) const { 5205 uint64_t ActualMask = RHS->getValue(); 5206 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 5207 5208 // If the actual mask exactly matches, success! 5209 if (ActualMask == DesiredMask) 5210 return true; 5211 5212 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5213 if (ActualMask & ~DesiredMask) 5214 return false; 5215 5216 // Otherwise, the DAG Combiner may have proven that the value coming in is 5217 // either already zero or is not demanded. Check for known zero input bits. 5218 uint64_t NeededMask = DesiredMask & ~ActualMask; 5219 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 5220 return true; 5221 5222 // TODO: check to see if missing bits are just not demanded. 5223 5224 // Otherwise, this pattern doesn't match. 5225 return false; 5226} 5227 5228/// CheckOrMask - The isel is trying to match something like (or X, 255). If 5229/// the dag combiner simplified the 255, we still want to match. RHS is the 5230/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 5231/// specified in the .td file (e.g. 255). 5232bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 5233 int64_t DesiredMaskS) const { 5234 uint64_t ActualMask = RHS->getValue(); 5235 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 5236 5237 // If the actual mask exactly matches, success! 5238 if (ActualMask == DesiredMask) 5239 return true; 5240 5241 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5242 if (ActualMask & ~DesiredMask) 5243 return false; 5244 5245 // Otherwise, the DAG Combiner may have proven that the value coming in is 5246 // either already zero or is not demanded. Check for known zero input bits. 5247 uint64_t NeededMask = DesiredMask & ~ActualMask; 5248 5249 uint64_t KnownZero, KnownOne; 5250 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 5251 5252 // If all the missing bits in the or are already known to be set, match! 5253 if ((NeededMask & KnownOne) == NeededMask) 5254 return true; 5255 5256 // TODO: check to see if missing bits are just not demanded. 5257 5258 // Otherwise, this pattern doesn't match. 5259 return false; 5260} 5261 5262 5263/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 5264/// by tblgen. Others should not call it. 5265void SelectionDAGISel:: 5266SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 5267 std::vector<SDOperand> InOps; 5268 std::swap(InOps, Ops); 5269 5270 Ops.push_back(InOps[0]); // input chain. 5271 Ops.push_back(InOps[1]); // input asm string. 5272 5273 unsigned i = 2, e = InOps.size(); 5274 if (InOps[e-1].getValueType() == MVT::Flag) 5275 --e; // Don't process a flag operand if it is here. 5276 5277 while (i != e) { 5278 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 5279 if ((Flags & 7) != 4 /*MEM*/) { 5280 // Just skip over this operand, copying the operands verbatim. 5281 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 5282 i += (Flags >> 3) + 1; 5283 } else { 5284 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 5285 // Otherwise, this is a memory operand. Ask the target to select it. 5286 std::vector<SDOperand> SelOps; 5287 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 5288 cerr << "Could not match memory address. Inline asm failure!\n"; 5289 exit(1); 5290 } 5291 5292 // Add this to the output node. 5293 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 5294 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 5295 IntPtrTy)); 5296 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 5297 i += 2; 5298 } 5299 } 5300 5301 // Add the flag input back if present. 5302 if (e != InOps.size()) 5303 Ops.push_back(InOps.back()); 5304} 5305 5306char SelectionDAGISel::ID = 0; 5307