SelectionDAGISel.cpp revision 6ad8256d769f352103b6101c7090e4bfc0389330
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/MachineModuleInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/CodeGen/SSARegMap.h" 37#include "llvm/Target/MRegisterInfo.h" 38#include "llvm/Target/TargetData.h" 39#include "llvm/Target/TargetFrameInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Compiler.h" 47#include <algorithm> 48using namespace llvm; 49 50#ifndef NDEBUG 51static cl::opt<bool> 52ViewISelDAGs("view-isel-dags", cl::Hidden, 53 cl::desc("Pop up a window to show isel dags as they are selected")); 54static cl::opt<bool> 55ViewSchedDAGs("view-sched-dags", cl::Hidden, 56 cl::desc("Pop up a window to show sched dags as they are processed")); 57#else 58static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0; 59#endif 60 61//===---------------------------------------------------------------------===// 62/// 63/// RegisterScheduler class - Track the registration of instruction schedulers. 64/// 65//===---------------------------------------------------------------------===// 66MachinePassRegistry RegisterScheduler::Registry; 67 68//===---------------------------------------------------------------------===// 69/// 70/// ISHeuristic command line option for instruction schedulers. 71/// 72//===---------------------------------------------------------------------===// 73namespace { 74 cl::opt<RegisterScheduler::FunctionPassCtor, false, 75 RegisterPassParser<RegisterScheduler> > 76 ISHeuristic("sched", 77 cl::init(&createDefaultScheduler), 78 cl::desc("Instruction schedulers available:")); 79 80 static RegisterScheduler 81 defaultListDAGScheduler("default", " Best scheduler for the target", 82 createDefaultScheduler); 83} // namespace 84 85namespace { struct AsmOperandInfo; } 86 87namespace { 88 /// RegsForValue - This struct represents the physical registers that a 89 /// particular value is assigned and the type information about the value. 90 /// This is needed because values can be promoted into larger registers and 91 /// expanded into multiple smaller registers than the value. 92 struct VISIBILITY_HIDDEN RegsForValue { 93 /// Regs - This list hold the register (for legal and promoted values) 94 /// or register set (for expanded values) that the value should be assigned 95 /// to. 96 std::vector<unsigned> Regs; 97 98 /// RegVT - The value type of each register. 99 /// 100 MVT::ValueType RegVT; 101 102 /// ValueVT - The value type of the LLVM value, which may be promoted from 103 /// RegVT or made from merging the two expanded parts. 104 MVT::ValueType ValueVT; 105 106 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 107 108 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 109 : RegVT(regvt), ValueVT(valuevt) { 110 Regs.push_back(Reg); 111 } 112 RegsForValue(const std::vector<unsigned> ®s, 113 MVT::ValueType regvt, MVT::ValueType valuevt) 114 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 115 } 116 117 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 118 /// this value and returns the result as a ValueVT value. This uses 119 /// Chain/Flag as the input and updates them for the output Chain/Flag. 120 SDOperand getCopyFromRegs(SelectionDAG &DAG, 121 SDOperand &Chain, SDOperand &Flag) const; 122 123 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 124 /// specified value into the registers specified by this object. This uses 125 /// Chain/Flag as the input and updates them for the output Chain/Flag. 126 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 127 SDOperand &Chain, SDOperand &Flag, 128 MVT::ValueType PtrVT) const; 129 130 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 131 /// operand list. This adds the code marker and includes the number of 132 /// values added into it. 133 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 134 std::vector<SDOperand> &Ops) const; 135 }; 136} 137 138namespace llvm { 139 //===--------------------------------------------------------------------===// 140 /// createDefaultScheduler - This creates an instruction scheduler appropriate 141 /// for the target. 142 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 143 SelectionDAG *DAG, 144 MachineBasicBlock *BB) { 145 TargetLowering &TLI = IS->getTargetLowering(); 146 147 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 148 return createTDListDAGScheduler(IS, DAG, BB); 149 } else { 150 assert(TLI.getSchedulingPreference() == 151 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 152 return createBURRListDAGScheduler(IS, DAG, BB); 153 } 154 } 155 156 157 //===--------------------------------------------------------------------===// 158 /// FunctionLoweringInfo - This contains information that is global to a 159 /// function that is used when lowering a region of the function. 160 class FunctionLoweringInfo { 161 public: 162 TargetLowering &TLI; 163 Function &Fn; 164 MachineFunction &MF; 165 SSARegMap *RegMap; 166 167 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 168 169 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 170 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 171 172 /// ValueMap - Since we emit code for the function a basic block at a time, 173 /// we must remember which virtual registers hold the values for 174 /// cross-basic-block values. 175 DenseMap<const Value*, unsigned> ValueMap; 176 177 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 178 /// the entry block. This allows the allocas to be efficiently referenced 179 /// anywhere in the function. 180 std::map<const AllocaInst*, int> StaticAllocaMap; 181 182 unsigned MakeReg(MVT::ValueType VT) { 183 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 184 } 185 186 /// isExportedInst - Return true if the specified value is an instruction 187 /// exported from its block. 188 bool isExportedInst(const Value *V) { 189 return ValueMap.count(V); 190 } 191 192 unsigned CreateRegForValue(const Value *V); 193 194 unsigned InitializeRegForValue(const Value *V) { 195 unsigned &R = ValueMap[V]; 196 assert(R == 0 && "Already initialized this value register!"); 197 return R = CreateRegForValue(V); 198 } 199 }; 200} 201 202/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 203/// PHI nodes or outside of the basic block that defines it, or used by a 204/// switch instruction, which may expand to multiple basic blocks. 205static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 206 if (isa<PHINode>(I)) return true; 207 BasicBlock *BB = I->getParent(); 208 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 209 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 210 // FIXME: Remove switchinst special case. 211 isa<SwitchInst>(*UI)) 212 return true; 213 return false; 214} 215 216/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 217/// entry block, return true. This includes arguments used by switches, since 218/// the switch may expand into multiple basic blocks. 219static bool isOnlyUsedInEntryBlock(Argument *A) { 220 BasicBlock *Entry = A->getParent()->begin(); 221 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 222 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 223 return false; // Use not in entry block. 224 return true; 225} 226 227FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 228 Function &fn, MachineFunction &mf) 229 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 230 231 // Create a vreg for each argument register that is not dead and is used 232 // outside of the entry block for the function. 233 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 234 AI != E; ++AI) 235 if (!isOnlyUsedInEntryBlock(AI)) 236 InitializeRegForValue(AI); 237 238 // Initialize the mapping of values to registers. This is only set up for 239 // instruction values that are used outside of the block that defines 240 // them. 241 Function::iterator BB = Fn.begin(), EB = Fn.end(); 242 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 243 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 244 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 245 const Type *Ty = AI->getAllocatedType(); 246 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 247 unsigned Align = 248 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 249 AI->getAlignment()); 250 251 TySize *= CUI->getZExtValue(); // Get total allocated size. 252 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 253 StaticAllocaMap[AI] = 254 MF.getFrameInfo()->CreateStackObject(TySize, Align); 255 } 256 257 for (; BB != EB; ++BB) 258 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 259 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 260 if (!isa<AllocaInst>(I) || 261 !StaticAllocaMap.count(cast<AllocaInst>(I))) 262 InitializeRegForValue(I); 263 264 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 265 // also creates the initial PHI MachineInstrs, though none of the input 266 // operands are populated. 267 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 268 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 269 MBBMap[BB] = MBB; 270 MF.getBasicBlockList().push_back(MBB); 271 272 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 273 // appropriate. 274 PHINode *PN; 275 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 276 if (PN->use_empty()) continue; 277 278 MVT::ValueType VT = TLI.getValueType(PN->getType()); 279 unsigned NumElements; 280 if (VT != MVT::Vector) 281 NumElements = TLI.getNumElements(VT); 282 else { 283 MVT::ValueType VT1,VT2; 284 NumElements = 285 TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()), 286 VT1, VT2); 287 } 288 unsigned PHIReg = ValueMap[PN]; 289 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 290 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 291 for (unsigned i = 0; i != NumElements; ++i) 292 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 293 } 294 } 295} 296 297/// CreateRegForValue - Allocate the appropriate number of virtual registers of 298/// the correctly promoted or expanded types. Assign these registers 299/// consecutive vreg numbers and return the first assigned number. 300unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 301 MVT::ValueType VT = TLI.getValueType(V->getType()); 302 303 // The number of multiples of registers that we need, to, e.g., split up 304 // a <2 x int64> -> 4 x i32 registers. 305 unsigned NumVectorRegs = 1; 306 307 // If this is a vector type, figure out what type it will decompose into 308 // and how many of the elements it will use. 309 if (VT == MVT::Vector) { 310 const VectorType *PTy = cast<VectorType>(V->getType()); 311 unsigned NumElts = PTy->getNumElements(); 312 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType()); 313 MVT::ValueType VecTy = getVectorType(EltTy, NumElts); 314 315 // Divide the input until we get to a supported size. This will always 316 // end with a scalar if the target doesn't support vectors. 317 while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) { 318 NumElts >>= 1; 319 NumVectorRegs <<= 1; 320 VecTy = getVectorType(EltTy, NumElts); 321 } 322 323 // Check that VecTy isn't a 1-element vector. 324 if (NumElts == 1 && VecTy == MVT::Other) 325 VT = EltTy; 326 else 327 VT = VecTy; 328 } 329 330 // The common case is that we will only create one register for this 331 // value. If we have that case, create and return the virtual register. 332 unsigned NV = TLI.getNumElements(VT); 333 if (NV == 1) { 334 // If we are promoting this value, pick the next largest supported type. 335 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT); 336 unsigned Reg = MakeReg(PromotedType); 337 // If this is a vector of supported or promoted types (e.g. 4 x i16), 338 // create all of the registers. 339 for (unsigned i = 1; i != NumVectorRegs; ++i) 340 MakeReg(PromotedType); 341 return Reg; 342 } 343 344 // If this value is represented with multiple target registers, make sure 345 // to create enough consecutive registers of the right (smaller) type. 346 VT = TLI.getTypeToExpandTo(VT); 347 unsigned R = MakeReg(VT); 348 for (unsigned i = 1; i != NV*NumVectorRegs; ++i) 349 MakeReg(VT); 350 return R; 351} 352 353//===----------------------------------------------------------------------===// 354/// SelectionDAGLowering - This is the common target-independent lowering 355/// implementation that is parameterized by a TargetLowering object. 356/// Also, targets can overload any lowering method. 357/// 358namespace llvm { 359class SelectionDAGLowering { 360 MachineBasicBlock *CurMBB; 361 362 DenseMap<const Value*, SDOperand> NodeMap; 363 364 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 365 /// them up and then emit token factor nodes when possible. This allows us to 366 /// get simple disambiguation between loads without worrying about alias 367 /// analysis. 368 std::vector<SDOperand> PendingLoads; 369 370 /// Case - A struct to record the Value for a switch case, and the 371 /// case's target basic block. 372 struct Case { 373 Constant* Low; 374 Constant* High; 375 MachineBasicBlock* BB; 376 377 Case() : Low(0), High(0), BB(0) { } 378 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 379 Low(low), High(high), BB(bb) { } 380 uint64_t size() const { 381 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 382 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 383 return (rHigh - rLow + 1ULL); 384 } 385 }; 386 387 struct CaseBits { 388 uint64_t Mask; 389 MachineBasicBlock* BB; 390 unsigned Bits; 391 392 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 393 Mask(mask), BB(bb), Bits(bits) { } 394 }; 395 396 typedef std::vector<Case> CaseVector; 397 typedef std::vector<CaseBits> CaseBitsVector; 398 typedef CaseVector::iterator CaseItr; 399 typedef std::pair<CaseItr, CaseItr> CaseRange; 400 401 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 402 /// of conditional branches. 403 struct CaseRec { 404 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 405 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 406 407 /// CaseBB - The MBB in which to emit the compare and branch 408 MachineBasicBlock *CaseBB; 409 /// LT, GE - If nonzero, we know the current case value must be less-than or 410 /// greater-than-or-equal-to these Constants. 411 Constant *LT; 412 Constant *GE; 413 /// Range - A pair of iterators representing the range of case values to be 414 /// processed at this point in the binary search tree. 415 CaseRange Range; 416 }; 417 418 typedef std::vector<CaseRec> CaseRecVector; 419 420 /// The comparison function for sorting the switch case values in the vector. 421 /// WARNING: Case ranges should be disjoint! 422 struct CaseCmp { 423 bool operator () (const Case& C1, const Case& C2) { 424 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 425 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 426 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 427 return CI1->getValue().slt(CI2->getValue()); 428 } 429 }; 430 431 struct CaseBitsCmp { 432 bool operator () (const CaseBits& C1, const CaseBits& C2) { 433 return C1.Bits > C2.Bits; 434 } 435 }; 436 437 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 438 439public: 440 // TLI - This is information that describes the available target features we 441 // need for lowering. This indicates when operations are unavailable, 442 // implemented with a libcall, etc. 443 TargetLowering &TLI; 444 SelectionDAG &DAG; 445 const TargetData *TD; 446 447 /// SwitchCases - Vector of CaseBlock structures used to communicate 448 /// SwitchInst code generation information. 449 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 450 /// JTCases - Vector of JumpTable structures used to communicate 451 /// SwitchInst code generation information. 452 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 453 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 454 455 /// FuncInfo - Information about the function as a whole. 456 /// 457 FunctionLoweringInfo &FuncInfo; 458 459 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 460 FunctionLoweringInfo &funcinfo) 461 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), 462 FuncInfo(funcinfo) { 463 } 464 465 /// getRoot - Return the current virtual root of the Selection DAG. 466 /// 467 SDOperand getRoot() { 468 if (PendingLoads.empty()) 469 return DAG.getRoot(); 470 471 if (PendingLoads.size() == 1) { 472 SDOperand Root = PendingLoads[0]; 473 DAG.setRoot(Root); 474 PendingLoads.clear(); 475 return Root; 476 } 477 478 // Otherwise, we have to make a token factor node. 479 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 480 &PendingLoads[0], PendingLoads.size()); 481 PendingLoads.clear(); 482 DAG.setRoot(Root); 483 return Root; 484 } 485 486 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 487 488 void visit(Instruction &I) { visit(I.getOpcode(), I); } 489 490 void visit(unsigned Opcode, User &I) { 491 // Note: this doesn't use InstVisitor, because it has to work with 492 // ConstantExpr's in addition to instructions. 493 switch (Opcode) { 494 default: assert(0 && "Unknown instruction type encountered!"); 495 abort(); 496 // Build the switch statement using the Instruction.def file. 497#define HANDLE_INST(NUM, OPCODE, CLASS) \ 498 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 499#include "llvm/Instruction.def" 500 } 501 } 502 503 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 504 505 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 506 const Value *SV, SDOperand Root, 507 bool isVolatile, unsigned Alignment); 508 509 SDOperand getIntPtrConstant(uint64_t Val) { 510 return DAG.getConstant(Val, TLI.getPointerTy()); 511 } 512 513 SDOperand getValue(const Value *V); 514 515 void setValue(const Value *V, SDOperand NewN) { 516 SDOperand &N = NodeMap[V]; 517 assert(N.Val == 0 && "Already set a value for this node!"); 518 N = NewN; 519 } 520 521 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 522 std::set<unsigned> &OutputRegs, 523 std::set<unsigned> &InputRegs); 524 525 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 526 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 527 unsigned Opc); 528 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 529 void ExportFromCurrentBlock(Value *V); 530 void LowerCallTo(Instruction &I, 531 const Type *CalledValueTy, unsigned CallingConv, 532 bool IsTailCall, SDOperand Callee, unsigned OpIdx); 533 534 // Terminator instructions. 535 void visitRet(ReturnInst &I); 536 void visitBr(BranchInst &I); 537 void visitSwitch(SwitchInst &I); 538 void visitUnreachable(UnreachableInst &I) { /* noop */ } 539 540 // Helpers for visitSwitch 541 bool handleSmallSwitchRange(CaseRec& CR, 542 CaseRecVector& WorkList, 543 Value* SV, 544 MachineBasicBlock* Default); 545 bool handleJTSwitchCase(CaseRec& CR, 546 CaseRecVector& WorkList, 547 Value* SV, 548 MachineBasicBlock* Default); 549 bool handleBTSplitSwitchCase(CaseRec& CR, 550 CaseRecVector& WorkList, 551 Value* SV, 552 MachineBasicBlock* Default); 553 bool handleBitTestsSwitchCase(CaseRec& CR, 554 CaseRecVector& WorkList, 555 Value* SV, 556 MachineBasicBlock* Default); 557 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 558 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 559 void visitBitTestCase(MachineBasicBlock* NextMBB, 560 unsigned Reg, 561 SelectionDAGISel::BitTestCase &B); 562 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 563 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 564 SelectionDAGISel::JumpTableHeader &JTH); 565 566 // These all get lowered before this pass. 567 void visitInvoke(InvokeInst &I); 568 void visitInvoke(InvokeInst &I, bool AsTerminator); 569 void visitUnwind(UnwindInst &I); 570 571 void visitScalarBinary(User &I, unsigned OpCode); 572 void visitVectorBinary(User &I, unsigned OpCode); 573 void visitEitherBinary(User &I, unsigned ScalarOp, unsigned VectorOp); 574 void visitShift(User &I, unsigned Opcode); 575 void visitAdd(User &I) { 576 if (isa<VectorType>(I.getType())) 577 visitVectorBinary(I, ISD::VADD); 578 else if (I.getType()->isFloatingPoint()) 579 visitScalarBinary(I, ISD::FADD); 580 else 581 visitScalarBinary(I, ISD::ADD); 582 } 583 void visitSub(User &I); 584 void visitMul(User &I) { 585 if (isa<VectorType>(I.getType())) 586 visitVectorBinary(I, ISD::VMUL); 587 else if (I.getType()->isFloatingPoint()) 588 visitScalarBinary(I, ISD::FMUL); 589 else 590 visitScalarBinary(I, ISD::MUL); 591 } 592 void visitURem(User &I) { visitScalarBinary(I, ISD::UREM); } 593 void visitSRem(User &I) { visitScalarBinary(I, ISD::SREM); } 594 void visitFRem(User &I) { visitScalarBinary(I, ISD::FREM); } 595 void visitUDiv(User &I) { visitEitherBinary(I, ISD::UDIV, ISD::VUDIV); } 596 void visitSDiv(User &I) { visitEitherBinary(I, ISD::SDIV, ISD::VSDIV); } 597 void visitFDiv(User &I) { visitEitherBinary(I, ISD::FDIV, ISD::VSDIV); } 598 void visitAnd (User &I) { visitEitherBinary(I, ISD::AND, ISD::VAND ); } 599 void visitOr (User &I) { visitEitherBinary(I, ISD::OR, ISD::VOR ); } 600 void visitXor (User &I) { visitEitherBinary(I, ISD::XOR, ISD::VXOR ); } 601 void visitShl (User &I) { visitShift(I, ISD::SHL); } 602 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 603 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 604 void visitICmp(User &I); 605 void visitFCmp(User &I); 606 // Visit the conversion instructions 607 void visitTrunc(User &I); 608 void visitZExt(User &I); 609 void visitSExt(User &I); 610 void visitFPTrunc(User &I); 611 void visitFPExt(User &I); 612 void visitFPToUI(User &I); 613 void visitFPToSI(User &I); 614 void visitUIToFP(User &I); 615 void visitSIToFP(User &I); 616 void visitPtrToInt(User &I); 617 void visitIntToPtr(User &I); 618 void visitBitCast(User &I); 619 620 void visitExtractElement(User &I); 621 void visitInsertElement(User &I); 622 void visitShuffleVector(User &I); 623 624 void visitGetElementPtr(User &I); 625 void visitSelect(User &I); 626 627 void visitMalloc(MallocInst &I); 628 void visitFree(FreeInst &I); 629 void visitAlloca(AllocaInst &I); 630 void visitLoad(LoadInst &I); 631 void visitStore(StoreInst &I); 632 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 633 void visitCall(CallInst &I); 634 void visitInlineAsm(CallInst &I); 635 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 636 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 637 638 void visitVAStart(CallInst &I); 639 void visitVAArg(VAArgInst &I); 640 void visitVAEnd(CallInst &I); 641 void visitVACopy(CallInst &I); 642 643 void visitMemIntrinsic(CallInst &I, unsigned Op); 644 645 void visitUserOp1(Instruction &I) { 646 assert(0 && "UserOp1 should not exist at instruction selection time!"); 647 abort(); 648 } 649 void visitUserOp2(Instruction &I) { 650 assert(0 && "UserOp2 should not exist at instruction selection time!"); 651 abort(); 652 } 653}; 654} // end namespace llvm 655 656SDOperand SelectionDAGLowering::getValue(const Value *V) { 657 SDOperand &N = NodeMap[V]; 658 if (N.Val) return N; 659 660 const Type *VTy = V->getType(); 661 MVT::ValueType VT = TLI.getValueType(VTy); 662 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 663 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 664 visit(CE->getOpcode(), *CE); 665 SDOperand N1 = NodeMap[V]; 666 assert(N1.Val && "visit didn't populate the ValueMap!"); 667 return N1; 668 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 669 return N = DAG.getGlobalAddress(GV, VT); 670 } else if (isa<ConstantPointerNull>(C)) { 671 return N = DAG.getConstant(0, TLI.getPointerTy()); 672 } else if (isa<UndefValue>(C)) { 673 if (!isa<VectorType>(VTy)) 674 return N = DAG.getNode(ISD::UNDEF, VT); 675 676 // Create a VBUILD_VECTOR of undef nodes. 677 const VectorType *PTy = cast<VectorType>(VTy); 678 unsigned NumElements = PTy->getNumElements(); 679 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 680 681 SmallVector<SDOperand, 8> Ops; 682 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 683 684 // Create a VConstant node with generic Vector type. 685 Ops.push_back(DAG.getConstant(NumElements, MVT::i32)); 686 Ops.push_back(DAG.getValueType(PVT)); 687 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 688 &Ops[0], Ops.size()); 689 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 690 return N = DAG.getConstantFP(CFP->getValue(), VT); 691 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 692 unsigned NumElements = PTy->getNumElements(); 693 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 694 695 // Now that we know the number and type of the elements, push a 696 // Constant or ConstantFP node onto the ops list for each element of 697 // the packed constant. 698 SmallVector<SDOperand, 8> Ops; 699 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 700 for (unsigned i = 0; i != NumElements; ++i) 701 Ops.push_back(getValue(CP->getOperand(i))); 702 } else { 703 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!"); 704 SDOperand Op; 705 if (MVT::isFloatingPoint(PVT)) 706 Op = DAG.getConstantFP(0, PVT); 707 else 708 Op = DAG.getConstant(0, PVT); 709 Ops.assign(NumElements, Op); 710 } 711 712 // Create a VBUILD_VECTOR node with generic Vector type. 713 Ops.push_back(DAG.getConstant(NumElements, MVT::i32)); 714 Ops.push_back(DAG.getValueType(PVT)); 715 return NodeMap[V] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], 716 Ops.size()); 717 } else { 718 // Canonicalize all constant ints to be unsigned. 719 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT); 720 } 721 } 722 723 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 724 std::map<const AllocaInst*, int>::iterator SI = 725 FuncInfo.StaticAllocaMap.find(AI); 726 if (SI != FuncInfo.StaticAllocaMap.end()) 727 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 728 } 729 730 unsigned InReg = FuncInfo.ValueMap[V]; 731 assert(InReg && "Value not in map!"); 732 733 // If this type is not legal, make it so now. 734 if (VT != MVT::Vector) { 735 if (TLI.getTypeAction(VT) == TargetLowering::Expand) { 736 // Source must be expanded. This input value is actually coming from the 737 // register pair InReg and InReg+1. 738 MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT); 739 unsigned NumVals = TLI.getNumElements(VT); 740 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); 741 if (NumVals == 1) 742 N = DAG.getNode(ISD::BIT_CONVERT, VT, N); 743 else { 744 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!"); 745 N = DAG.getNode(ISD::BUILD_PAIR, VT, N, 746 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT)); 747 } 748 } else { 749 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT); 750 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); 751 if (TLI.getTypeAction(VT) == TargetLowering::Promote) // Promotion case 752 N = MVT::isFloatingPoint(VT) 753 ? DAG.getNode(ISD::FP_ROUND, VT, N) 754 : DAG.getNode(ISD::TRUNCATE, VT, N); 755 } 756 } else { 757 // Otherwise, if this is a vector, make it available as a generic vector 758 // here. 759 MVT::ValueType PTyElementVT, PTyLegalElementVT; 760 const VectorType *PTy = cast<VectorType>(VTy); 761 unsigned NE = TLI.getVectorTypeBreakdown(PTy, PTyElementVT, 762 PTyLegalElementVT); 763 764 // Build a VBUILD_VECTOR with the input registers. 765 SmallVector<SDOperand, 8> Ops; 766 if (PTyElementVT == PTyLegalElementVT) { 767 // If the value types are legal, just VBUILD the CopyFromReg nodes. 768 for (unsigned i = 0; i != NE; ++i) 769 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 770 PTyElementVT)); 771 } else if (PTyElementVT < PTyLegalElementVT) { 772 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate. 773 for (unsigned i = 0; i != NE; ++i) { 774 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 775 PTyElementVT); 776 if (MVT::isFloatingPoint(PTyElementVT)) 777 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op); 778 else 779 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op); 780 Ops.push_back(Op); 781 } 782 } else { 783 // If the register was expanded, use BUILD_PAIR. 784 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!"); 785 for (unsigned i = 0; i != NE/2; ++i) { 786 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 787 PTyElementVT); 788 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 789 PTyElementVT); 790 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1)); 791 } 792 } 793 794 Ops.push_back(DAG.getConstant(NE, MVT::i32)); 795 Ops.push_back(DAG.getValueType(PTyLegalElementVT)); 796 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 797 798 // Finally, use a VBIT_CONVERT to make this available as the appropriate 799 // vector type. 800 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, 801 DAG.getConstant(PTy->getNumElements(), 802 MVT::i32), 803 DAG.getValueType(TLI.getValueType(PTy->getElementType()))); 804 } 805 806 return N; 807} 808 809 810void SelectionDAGLowering::visitRet(ReturnInst &I) { 811 if (I.getNumOperands() == 0) { 812 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 813 return; 814 } 815 SmallVector<SDOperand, 8> NewValues; 816 NewValues.push_back(getRoot()); 817 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 818 SDOperand RetOp = getValue(I.getOperand(i)); 819 820 // If this is an integer return value, we need to promote it ourselves to 821 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather 822 // than sign/zero. 823 // FIXME: C calling convention requires the return type to be promoted to 824 // at least 32-bit. But this is not necessary for non-C calling conventions. 825 if (MVT::isInteger(RetOp.getValueType()) && 826 RetOp.getValueType() < MVT::i64) { 827 MVT::ValueType TmpVT; 828 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 829 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 830 else 831 TmpVT = MVT::i32; 832 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType(); 833 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 834 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 835 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt)) 836 ExtendKind = ISD::SIGN_EXTEND; 837 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt)) 838 ExtendKind = ISD::ZERO_EXTEND; 839 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp); 840 } 841 NewValues.push_back(RetOp); 842 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 843 } 844 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 845 &NewValues[0], NewValues.size())); 846} 847 848/// ExportFromCurrentBlock - If this condition isn't known to be exported from 849/// the current basic block, add it to ValueMap now so that we'll get a 850/// CopyTo/FromReg. 851void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 852 // No need to export constants. 853 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 854 855 // Already exported? 856 if (FuncInfo.isExportedInst(V)) return; 857 858 unsigned Reg = FuncInfo.InitializeRegForValue(V); 859 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 860} 861 862bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 863 const BasicBlock *FromBB) { 864 // The operands of the setcc have to be in this block. We don't know 865 // how to export them from some other block. 866 if (Instruction *VI = dyn_cast<Instruction>(V)) { 867 // Can export from current BB. 868 if (VI->getParent() == FromBB) 869 return true; 870 871 // Is already exported, noop. 872 return FuncInfo.isExportedInst(V); 873 } 874 875 // If this is an argument, we can export it if the BB is the entry block or 876 // if it is already exported. 877 if (isa<Argument>(V)) { 878 if (FromBB == &FromBB->getParent()->getEntryBlock()) 879 return true; 880 881 // Otherwise, can only export this if it is already exported. 882 return FuncInfo.isExportedInst(V); 883 } 884 885 // Otherwise, constants can always be exported. 886 return true; 887} 888 889static bool InBlock(const Value *V, const BasicBlock *BB) { 890 if (const Instruction *I = dyn_cast<Instruction>(V)) 891 return I->getParent() == BB; 892 return true; 893} 894 895/// FindMergedConditions - If Cond is an expression like 896void SelectionDAGLowering::FindMergedConditions(Value *Cond, 897 MachineBasicBlock *TBB, 898 MachineBasicBlock *FBB, 899 MachineBasicBlock *CurBB, 900 unsigned Opc) { 901 // If this node is not part of the or/and tree, emit it as a branch. 902 Instruction *BOp = dyn_cast<Instruction>(Cond); 903 904 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 905 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 906 BOp->getParent() != CurBB->getBasicBlock() || 907 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 908 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 909 const BasicBlock *BB = CurBB->getBasicBlock(); 910 911 // If the leaf of the tree is a comparison, merge the condition into 912 // the caseblock. 913 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 914 // The operands of the cmp have to be in this block. We don't know 915 // how to export them from some other block. If this is the first block 916 // of the sequence, no exporting is needed. 917 (CurBB == CurMBB || 918 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 919 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 920 BOp = cast<Instruction>(Cond); 921 ISD::CondCode Condition; 922 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 923 switch (IC->getPredicate()) { 924 default: assert(0 && "Unknown icmp predicate opcode!"); 925 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 926 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 927 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 928 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 929 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 930 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 931 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 932 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 933 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 934 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 935 } 936 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 937 ISD::CondCode FPC, FOC; 938 switch (FC->getPredicate()) { 939 default: assert(0 && "Unknown fcmp predicate opcode!"); 940 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 941 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 942 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 943 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 944 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 945 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 946 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 947 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 948 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 949 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 950 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 951 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 952 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 953 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 954 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 955 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 956 } 957 if (FiniteOnlyFPMath()) 958 Condition = FOC; 959 else 960 Condition = FPC; 961 } else { 962 Condition = ISD::SETEQ; // silence warning. 963 assert(0 && "Unknown compare instruction"); 964 } 965 966 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 967 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 968 SwitchCases.push_back(CB); 969 return; 970 } 971 972 // Create a CaseBlock record representing this branch. 973 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 974 NULL, TBB, FBB, CurBB); 975 SwitchCases.push_back(CB); 976 return; 977 } 978 979 980 // Create TmpBB after CurBB. 981 MachineFunction::iterator BBI = CurBB; 982 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 983 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 984 985 if (Opc == Instruction::Or) { 986 // Codegen X | Y as: 987 // jmp_if_X TBB 988 // jmp TmpBB 989 // TmpBB: 990 // jmp_if_Y TBB 991 // jmp FBB 992 // 993 994 // Emit the LHS condition. 995 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 996 997 // Emit the RHS condition into TmpBB. 998 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 999 } else { 1000 assert(Opc == Instruction::And && "Unknown merge op!"); 1001 // Codegen X & Y as: 1002 // jmp_if_X TmpBB 1003 // jmp FBB 1004 // TmpBB: 1005 // jmp_if_Y TBB 1006 // jmp FBB 1007 // 1008 // This requires creation of TmpBB after CurBB. 1009 1010 // Emit the LHS condition. 1011 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1012 1013 // Emit the RHS condition into TmpBB. 1014 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1015 } 1016} 1017 1018/// If the set of cases should be emitted as a series of branches, return true. 1019/// If we should emit this as a bunch of and/or'd together conditions, return 1020/// false. 1021static bool 1022ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1023 if (Cases.size() != 2) return true; 1024 1025 // If this is two comparisons of the same values or'd or and'd together, they 1026 // will get folded into a single comparison, so don't emit two blocks. 1027 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1028 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1029 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1030 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1031 return false; 1032 } 1033 1034 return true; 1035} 1036 1037void SelectionDAGLowering::visitBr(BranchInst &I) { 1038 // Update machine-CFG edges. 1039 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1040 1041 // Figure out which block is immediately after the current one. 1042 MachineBasicBlock *NextBlock = 0; 1043 MachineFunction::iterator BBI = CurMBB; 1044 if (++BBI != CurMBB->getParent()->end()) 1045 NextBlock = BBI; 1046 1047 if (I.isUnconditional()) { 1048 // If this is not a fall-through branch, emit the branch. 1049 if (Succ0MBB != NextBlock) 1050 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1051 DAG.getBasicBlock(Succ0MBB))); 1052 1053 // Update machine-CFG edges. 1054 CurMBB->addSuccessor(Succ0MBB); 1055 1056 return; 1057 } 1058 1059 // If this condition is one of the special cases we handle, do special stuff 1060 // now. 1061 Value *CondVal = I.getCondition(); 1062 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1063 1064 // If this is a series of conditions that are or'd or and'd together, emit 1065 // this as a sequence of branches instead of setcc's with and/or operations. 1066 // For example, instead of something like: 1067 // cmp A, B 1068 // C = seteq 1069 // cmp D, E 1070 // F = setle 1071 // or C, F 1072 // jnz foo 1073 // Emit: 1074 // cmp A, B 1075 // je foo 1076 // cmp D, E 1077 // jle foo 1078 // 1079 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1080 if (BOp->hasOneUse() && 1081 (BOp->getOpcode() == Instruction::And || 1082 BOp->getOpcode() == Instruction::Or)) { 1083 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1084 // If the compares in later blocks need to use values not currently 1085 // exported from this block, export them now. This block should always 1086 // be the first entry. 1087 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1088 1089 // Allow some cases to be rejected. 1090 if (ShouldEmitAsBranches(SwitchCases)) { 1091 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1092 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1093 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1094 } 1095 1096 // Emit the branch for this block. 1097 visitSwitchCase(SwitchCases[0]); 1098 SwitchCases.erase(SwitchCases.begin()); 1099 return; 1100 } 1101 1102 // Okay, we decided not to do this, remove any inserted MBB's and clear 1103 // SwitchCases. 1104 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1105 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1106 1107 SwitchCases.clear(); 1108 } 1109 } 1110 1111 // Create a CaseBlock record representing this branch. 1112 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1113 NULL, Succ0MBB, Succ1MBB, CurMBB); 1114 // Use visitSwitchCase to actually insert the fast branch sequence for this 1115 // cond branch. 1116 visitSwitchCase(CB); 1117} 1118 1119/// visitSwitchCase - Emits the necessary code to represent a single node in 1120/// the binary search tree resulting from lowering a switch instruction. 1121void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1122 SDOperand Cond; 1123 SDOperand CondLHS = getValue(CB.CmpLHS); 1124 1125 // Build the setcc now. 1126 if (CB.CmpMHS == NULL) { 1127 // Fold "(X == true)" to X and "(X == false)" to !X to 1128 // handle common cases produced by branch lowering. 1129 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1130 Cond = CondLHS; 1131 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1132 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1133 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1134 } else 1135 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1136 } else { 1137 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1138 1139 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1140 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1141 1142 SDOperand CmpOp = getValue(CB.CmpMHS); 1143 MVT::ValueType VT = CmpOp.getValueType(); 1144 1145 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1146 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1147 } else { 1148 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1149 Cond = DAG.getSetCC(MVT::i1, SUB, 1150 DAG.getConstant(High-Low, VT), ISD::SETULE); 1151 } 1152 1153 } 1154 1155 // Set NextBlock to be the MBB immediately after the current one, if any. 1156 // This is used to avoid emitting unnecessary branches to the next block. 1157 MachineBasicBlock *NextBlock = 0; 1158 MachineFunction::iterator BBI = CurMBB; 1159 if (++BBI != CurMBB->getParent()->end()) 1160 NextBlock = BBI; 1161 1162 // If the lhs block is the next block, invert the condition so that we can 1163 // fall through to the lhs instead of the rhs block. 1164 if (CB.TrueBB == NextBlock) { 1165 std::swap(CB.TrueBB, CB.FalseBB); 1166 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1167 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1168 } 1169 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1170 DAG.getBasicBlock(CB.TrueBB)); 1171 if (CB.FalseBB == NextBlock) 1172 DAG.setRoot(BrCond); 1173 else 1174 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1175 DAG.getBasicBlock(CB.FalseBB))); 1176 // Update successor info 1177 CurMBB->addSuccessor(CB.TrueBB); 1178 CurMBB->addSuccessor(CB.FalseBB); 1179} 1180 1181/// visitJumpTable - Emit JumpTable node in the current MBB 1182void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1183 // Emit the code for the jump table 1184 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1185 MVT::ValueType PTy = TLI.getPointerTy(); 1186 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1187 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1188 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1189 Table, Index)); 1190 return; 1191} 1192 1193/// visitJumpTableHeader - This function emits necessary code to produce index 1194/// in the JumpTable from switch case. 1195void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1196 SelectionDAGISel::JumpTableHeader &JTH) { 1197 // Subtract the lowest switch case value from the value being switched on 1198 // and conditional branch to default mbb if the result is greater than the 1199 // difference between smallest and largest cases. 1200 SDOperand SwitchOp = getValue(JTH.SValue); 1201 MVT::ValueType VT = SwitchOp.getValueType(); 1202 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1203 DAG.getConstant(JTH.First, VT)); 1204 1205 // The SDNode we just created, which holds the value being switched on 1206 // minus the the smallest case value, needs to be copied to a virtual 1207 // register so it can be used as an index into the jump table in a 1208 // subsequent basic block. This value may be smaller or larger than the 1209 // target's pointer type, and therefore require extension or truncating. 1210 if (VT > TLI.getPointerTy()) 1211 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1212 else 1213 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1214 1215 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1216 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1217 JT.Reg = JumpTableReg; 1218 1219 // Emit the range check for the jump table, and branch to the default 1220 // block for the switch statement if the value being switched on exceeds 1221 // the largest case in the switch. 1222 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1223 DAG.getConstant(JTH.Last-JTH.First,VT), 1224 ISD::SETUGT); 1225 1226 // Set NextBlock to be the MBB immediately after the current one, if any. 1227 // This is used to avoid emitting unnecessary branches to the next block. 1228 MachineBasicBlock *NextBlock = 0; 1229 MachineFunction::iterator BBI = CurMBB; 1230 if (++BBI != CurMBB->getParent()->end()) 1231 NextBlock = BBI; 1232 1233 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1234 DAG.getBasicBlock(JT.Default)); 1235 1236 if (JT.MBB == NextBlock) 1237 DAG.setRoot(BrCond); 1238 else 1239 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1240 DAG.getBasicBlock(JT.MBB))); 1241 1242 return; 1243} 1244 1245/// visitBitTestHeader - This function emits necessary code to produce value 1246/// suitable for "bit tests" 1247void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1248 // Subtract the minimum value 1249 SDOperand SwitchOp = getValue(B.SValue); 1250 MVT::ValueType VT = SwitchOp.getValueType(); 1251 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1252 DAG.getConstant(B.First, VT)); 1253 1254 // Check range 1255 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1256 DAG.getConstant(B.Range, VT), 1257 ISD::SETUGT); 1258 1259 SDOperand ShiftOp; 1260 if (VT > TLI.getShiftAmountTy()) 1261 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1262 else 1263 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1264 1265 // Make desired shift 1266 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1267 DAG.getConstant(1, TLI.getPointerTy()), 1268 ShiftOp); 1269 1270 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1271 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1272 B.Reg = SwitchReg; 1273 1274 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1275 DAG.getBasicBlock(B.Default)); 1276 1277 // Set NextBlock to be the MBB immediately after the current one, if any. 1278 // This is used to avoid emitting unnecessary branches to the next block. 1279 MachineBasicBlock *NextBlock = 0; 1280 MachineFunction::iterator BBI = CurMBB; 1281 if (++BBI != CurMBB->getParent()->end()) 1282 NextBlock = BBI; 1283 1284 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1285 if (MBB == NextBlock) 1286 DAG.setRoot(BrRange); 1287 else 1288 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1289 DAG.getBasicBlock(MBB))); 1290 1291 CurMBB->addSuccessor(B.Default); 1292 CurMBB->addSuccessor(MBB); 1293 1294 return; 1295} 1296 1297/// visitBitTestCase - this function produces one "bit test" 1298void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1299 unsigned Reg, 1300 SelectionDAGISel::BitTestCase &B) { 1301 // Emit bit tests and jumps 1302 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1303 1304 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1305 SwitchVal, 1306 DAG.getConstant(B.Mask, 1307 TLI.getPointerTy())); 1308 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, 1309 DAG.getConstant(0, TLI.getPointerTy()), 1310 ISD::SETNE); 1311 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1312 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1313 1314 // Set NextBlock to be the MBB immediately after the current one, if any. 1315 // This is used to avoid emitting unnecessary branches to the next block. 1316 MachineBasicBlock *NextBlock = 0; 1317 MachineFunction::iterator BBI = CurMBB; 1318 if (++BBI != CurMBB->getParent()->end()) 1319 NextBlock = BBI; 1320 1321 if (NextMBB == NextBlock) 1322 DAG.setRoot(BrAnd); 1323 else 1324 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1325 DAG.getBasicBlock(NextMBB))); 1326 1327 CurMBB->addSuccessor(B.TargetBB); 1328 CurMBB->addSuccessor(NextMBB); 1329 1330 return; 1331} 1332 1333void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1334 assert(0 && "Should never be visited directly"); 1335} 1336void SelectionDAGLowering::visitInvoke(InvokeInst &I, bool AsTerminator) { 1337 // Retrieve successors. 1338 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1339 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1340 1341 if (!AsTerminator) { 1342 // Mark landing pad so that it doesn't get deleted in branch folding. 1343 LandingPad->setIsLandingPad(); 1344 1345 // Insert a label before the invoke call to mark the try range. 1346 // This can be used to detect deletion of the invoke via the 1347 // MachineModuleInfo. 1348 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1349 unsigned BeginLabel = MMI->NextLabelID(); 1350 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 1351 DAG.getConstant(BeginLabel, MVT::i32))); 1352 1353 LowerCallTo(I, I.getCalledValue()->getType(), 1354 I.getCallingConv(), 1355 false, 1356 getValue(I.getOperand(0)), 1357 3); 1358 1359 // Insert a label before the invoke call to mark the try range. 1360 // This can be used to detect deletion of the invoke via the 1361 // MachineModuleInfo. 1362 unsigned EndLabel = MMI->NextLabelID(); 1363 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 1364 DAG.getConstant(EndLabel, MVT::i32))); 1365 1366 // Inform MachineModuleInfo of range. 1367 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 1368 1369 // Update successor info 1370 CurMBB->addSuccessor(Return); 1371 CurMBB->addSuccessor(LandingPad); 1372 } else { 1373 // Drop into normal successor. 1374 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1375 DAG.getBasicBlock(Return))); 1376 } 1377} 1378 1379void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1380} 1381 1382/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1383/// small case ranges). 1384bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1385 CaseRecVector& WorkList, 1386 Value* SV, 1387 MachineBasicBlock* Default) { 1388 Case& BackCase = *(CR.Range.second-1); 1389 1390 // Size is the number of Cases represented by this range. 1391 unsigned Size = CR.Range.second - CR.Range.first; 1392 if (Size > 3) 1393 return false; 1394 1395 // Get the MachineFunction which holds the current MBB. This is used when 1396 // inserting any additional MBBs necessary to represent the switch. 1397 MachineFunction *CurMF = CurMBB->getParent(); 1398 1399 // Figure out which block is immediately after the current one. 1400 MachineBasicBlock *NextBlock = 0; 1401 MachineFunction::iterator BBI = CR.CaseBB; 1402 1403 if (++BBI != CurMBB->getParent()->end()) 1404 NextBlock = BBI; 1405 1406 // TODO: If any two of the cases has the same destination, and if one value 1407 // is the same as the other, but has one bit unset that the other has set, 1408 // use bit manipulation to do two compares at once. For example: 1409 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1410 1411 // Rearrange the case blocks so that the last one falls through if possible. 1412 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1413 // The last case block won't fall through into 'NextBlock' if we emit the 1414 // branches in this order. See if rearranging a case value would help. 1415 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1416 if (I->BB == NextBlock) { 1417 std::swap(*I, BackCase); 1418 break; 1419 } 1420 } 1421 } 1422 1423 // Create a CaseBlock record representing a conditional branch to 1424 // the Case's target mbb if the value being switched on SV is equal 1425 // to C. 1426 MachineBasicBlock *CurBlock = CR.CaseBB; 1427 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1428 MachineBasicBlock *FallThrough; 1429 if (I != E-1) { 1430 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1431 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1432 } else { 1433 // If the last case doesn't match, go to the default block. 1434 FallThrough = Default; 1435 } 1436 1437 Value *RHS, *LHS, *MHS; 1438 ISD::CondCode CC; 1439 if (I->High == I->Low) { 1440 // This is just small small case range :) containing exactly 1 case 1441 CC = ISD::SETEQ; 1442 LHS = SV; RHS = I->High; MHS = NULL; 1443 } else { 1444 CC = ISD::SETLE; 1445 LHS = I->Low; MHS = SV; RHS = I->High; 1446 } 1447 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1448 I->BB, FallThrough, CurBlock); 1449 1450 // If emitting the first comparison, just call visitSwitchCase to emit the 1451 // code into the current block. Otherwise, push the CaseBlock onto the 1452 // vector to be later processed by SDISel, and insert the node's MBB 1453 // before the next MBB. 1454 if (CurBlock == CurMBB) 1455 visitSwitchCase(CB); 1456 else 1457 SwitchCases.push_back(CB); 1458 1459 CurBlock = FallThrough; 1460 } 1461 1462 return true; 1463} 1464 1465/// handleJTSwitchCase - Emit jumptable for current switch case range 1466bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1467 CaseRecVector& WorkList, 1468 Value* SV, 1469 MachineBasicBlock* Default) { 1470 Case& FrontCase = *CR.Range.first; 1471 Case& BackCase = *(CR.Range.second-1); 1472 1473 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1474 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1475 1476 uint64_t TSize = 0; 1477 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1478 I!=E; ++I) 1479 TSize += I->size(); 1480 1481 if ((!TLI.isOperationLegal(ISD::BR_JT, MVT::Other) && 1482 !TLI.isOperationLegal(ISD::BRIND, MVT::Other)) || 1483 TSize <= 3) 1484 return false; 1485 1486 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1487 if (Density < 0.4) 1488 return false; 1489 1490 DOUT << "Lowering jump table\n" 1491 << "First entry: " << First << ". Last entry: " << Last << "\n" 1492 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1493 1494 // Get the MachineFunction which holds the current MBB. This is used when 1495 // inserting any additional MBBs necessary to represent the switch. 1496 MachineFunction *CurMF = CurMBB->getParent(); 1497 1498 // Figure out which block is immediately after the current one. 1499 MachineBasicBlock *NextBlock = 0; 1500 MachineFunction::iterator BBI = CR.CaseBB; 1501 1502 if (++BBI != CurMBB->getParent()->end()) 1503 NextBlock = BBI; 1504 1505 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1506 1507 // Create a new basic block to hold the code for loading the address 1508 // of the jump table, and jumping to it. Update successor information; 1509 // we will either branch to the default case for the switch, or the jump 1510 // table. 1511 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1512 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1513 CR.CaseBB->addSuccessor(Default); 1514 CR.CaseBB->addSuccessor(JumpTableBB); 1515 1516 // Build a vector of destination BBs, corresponding to each target 1517 // of the jump table. If the value of the jump table slot corresponds to 1518 // a case statement, push the case's BB onto the vector, otherwise, push 1519 // the default BB. 1520 std::vector<MachineBasicBlock*> DestBBs; 1521 int64_t TEI = First; 1522 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1523 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1524 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1525 1526 if ((Low <= TEI) && (TEI <= High)) { 1527 DestBBs.push_back(I->BB); 1528 if (TEI==High) 1529 ++I; 1530 } else { 1531 DestBBs.push_back(Default); 1532 } 1533 } 1534 1535 // Update successor info. Add one edge to each unique successor. 1536 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1537 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1538 E = DestBBs.end(); I != E; ++I) { 1539 if (!SuccsHandled[(*I)->getNumber()]) { 1540 SuccsHandled[(*I)->getNumber()] = true; 1541 JumpTableBB->addSuccessor(*I); 1542 } 1543 } 1544 1545 // Create a jump table index for this jump table, or return an existing 1546 // one. 1547 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1548 1549 // Set the jump table information so that we can codegen it as a second 1550 // MachineBasicBlock 1551 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1552 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1553 (CR.CaseBB == CurMBB)); 1554 if (CR.CaseBB == CurMBB) 1555 visitJumpTableHeader(JT, JTH); 1556 1557 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1558 1559 return true; 1560} 1561 1562/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1563/// 2 subtrees. 1564bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1565 CaseRecVector& WorkList, 1566 Value* SV, 1567 MachineBasicBlock* Default) { 1568 // Get the MachineFunction which holds the current MBB. This is used when 1569 // inserting any additional MBBs necessary to represent the switch. 1570 MachineFunction *CurMF = CurMBB->getParent(); 1571 1572 // Figure out which block is immediately after the current one. 1573 MachineBasicBlock *NextBlock = 0; 1574 MachineFunction::iterator BBI = CR.CaseBB; 1575 1576 if (++BBI != CurMBB->getParent()->end()) 1577 NextBlock = BBI; 1578 1579 Case& FrontCase = *CR.Range.first; 1580 Case& BackCase = *(CR.Range.second-1); 1581 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1582 1583 // Size is the number of Cases represented by this range. 1584 unsigned Size = CR.Range.second - CR.Range.first; 1585 1586 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1587 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1588 double FMetric = 0; 1589 CaseItr Pivot = CR.Range.first + Size/2; 1590 1591 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1592 // (heuristically) allow us to emit JumpTable's later. 1593 uint64_t TSize = 0; 1594 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1595 I!=E; ++I) 1596 TSize += I->size(); 1597 1598 uint64_t LSize = FrontCase.size(); 1599 uint64_t RSize = TSize-LSize; 1600 DOUT << "Selecting best pivot: \n" 1601 << "First: " << First << ", Last: " << Last <<"\n" 1602 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1603 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1604 J!=E; ++I, ++J) { 1605 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1606 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1607 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1608 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1609 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1610 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1611 // Should always split in some non-trivial place 1612 DOUT <<"=>Step\n" 1613 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1614 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1615 << "Metric: " << Metric << "\n"; 1616 if (FMetric < Metric) { 1617 Pivot = J; 1618 FMetric = Metric; 1619 DOUT << "Current metric set to: " << FMetric << "\n"; 1620 } 1621 1622 LSize += J->size(); 1623 RSize -= J->size(); 1624 } 1625 // If our case is dense we *really* should handle it earlier! 1626 assert((FMetric > 0) && "Should handle dense range earlier!"); 1627 1628 CaseRange LHSR(CR.Range.first, Pivot); 1629 CaseRange RHSR(Pivot, CR.Range.second); 1630 Constant *C = Pivot->Low; 1631 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1632 1633 // We know that we branch to the LHS if the Value being switched on is 1634 // less than the Pivot value, C. We use this to optimize our binary 1635 // tree a bit, by recognizing that if SV is greater than or equal to the 1636 // LHS's Case Value, and that Case Value is exactly one less than the 1637 // Pivot's Value, then we can branch directly to the LHS's Target, 1638 // rather than creating a leaf node for it. 1639 if ((LHSR.second - LHSR.first) == 1 && 1640 LHSR.first->High == CR.GE && 1641 cast<ConstantInt>(C)->getSExtValue() == 1642 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1643 TrueBB = LHSR.first->BB; 1644 } else { 1645 TrueBB = new MachineBasicBlock(LLVMBB); 1646 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1647 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1648 } 1649 1650 // Similar to the optimization above, if the Value being switched on is 1651 // known to be less than the Constant CR.LT, and the current Case Value 1652 // is CR.LT - 1, then we can branch directly to the target block for 1653 // the current Case Value, rather than emitting a RHS leaf node for it. 1654 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1655 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1656 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1657 FalseBB = RHSR.first->BB; 1658 } else { 1659 FalseBB = new MachineBasicBlock(LLVMBB); 1660 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1661 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1662 } 1663 1664 // Create a CaseBlock record representing a conditional branch to 1665 // the LHS node if the value being switched on SV is less than C. 1666 // Otherwise, branch to LHS. 1667 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1668 TrueBB, FalseBB, CR.CaseBB); 1669 1670 if (CR.CaseBB == CurMBB) 1671 visitSwitchCase(CB); 1672 else 1673 SwitchCases.push_back(CB); 1674 1675 return true; 1676} 1677 1678/// handleBitTestsSwitchCase - if current case range has few destination and 1679/// range span less, than machine word bitwidth, encode case range into series 1680/// of masks and emit bit tests with these masks. 1681bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1682 CaseRecVector& WorkList, 1683 Value* SV, 1684 MachineBasicBlock* Default){ 1685 unsigned IntPtrBits = getSizeInBits(TLI.getPointerTy()); 1686 1687 Case& FrontCase = *CR.Range.first; 1688 Case& BackCase = *(CR.Range.second-1); 1689 1690 // Get the MachineFunction which holds the current MBB. This is used when 1691 // inserting any additional MBBs necessary to represent the switch. 1692 MachineFunction *CurMF = CurMBB->getParent(); 1693 1694 unsigned numCmps = 0; 1695 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1696 I!=E; ++I) { 1697 // Single case counts one, case range - two. 1698 if (I->Low == I->High) 1699 numCmps +=1; 1700 else 1701 numCmps +=2; 1702 } 1703 1704 // Count unique destinations 1705 SmallSet<MachineBasicBlock*, 4> Dests; 1706 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1707 Dests.insert(I->BB); 1708 if (Dests.size() > 3) 1709 // Don't bother the code below, if there are too much unique destinations 1710 return false; 1711 } 1712 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1713 << "Total number of comparisons: " << numCmps << "\n"; 1714 1715 // Compute span of values. 1716 Constant* minValue = FrontCase.Low; 1717 Constant* maxValue = BackCase.High; 1718 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1719 cast<ConstantInt>(minValue)->getSExtValue(); 1720 DOUT << "Compare range: " << range << "\n" 1721 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1722 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1723 1724 if (range>=IntPtrBits || 1725 (!(Dests.size() == 1 && numCmps >= 3) && 1726 !(Dests.size() == 2 && numCmps >= 5) && 1727 !(Dests.size() >= 3 && numCmps >= 6))) 1728 return false; 1729 1730 DOUT << "Emitting bit tests\n"; 1731 int64_t lowBound = 0; 1732 1733 // Optimize the case where all the case values fit in a 1734 // word without having to subtract minValue. In this case, 1735 // we can optimize away the subtraction. 1736 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1737 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1738 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1739 } else { 1740 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1741 } 1742 1743 CaseBitsVector CasesBits; 1744 unsigned i, count = 0; 1745 1746 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1747 MachineBasicBlock* Dest = I->BB; 1748 for (i = 0; i < count; ++i) 1749 if (Dest == CasesBits[i].BB) 1750 break; 1751 1752 if (i == count) { 1753 assert((count < 3) && "Too much destinations to test!"); 1754 CasesBits.push_back(CaseBits(0, Dest, 0)); 1755 count++; 1756 } 1757 1758 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1759 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1760 1761 for (uint64_t j = lo; j <= hi; j++) { 1762 CasesBits[i].Mask |= 1ULL << j; 1763 CasesBits[i].Bits++; 1764 } 1765 1766 } 1767 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1768 1769 SelectionDAGISel::BitTestInfo BTC; 1770 1771 // Figure out which block is immediately after the current one. 1772 MachineFunction::iterator BBI = CR.CaseBB; 1773 ++BBI; 1774 1775 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1776 1777 DOUT << "Cases:\n"; 1778 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1779 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1780 << ", BB: " << CasesBits[i].BB << "\n"; 1781 1782 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1783 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1784 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1785 CaseBB, 1786 CasesBits[i].BB)); 1787 } 1788 1789 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 1790 -1U, (CR.CaseBB == CurMBB), 1791 CR.CaseBB, Default, BTC); 1792 1793 if (CR.CaseBB == CurMBB) 1794 visitBitTestHeader(BTB); 1795 1796 BitTestCases.push_back(BTB); 1797 1798 return true; 1799} 1800 1801 1802// Clusterify - Transform simple list of Cases into list of CaseRange's 1803unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 1804 const SwitchInst& SI) { 1805 unsigned numCmps = 0; 1806 1807 // Start with "simple" cases 1808 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 1809 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1810 Cases.push_back(Case(SI.getSuccessorValue(i), 1811 SI.getSuccessorValue(i), 1812 SMBB)); 1813 } 1814 sort(Cases.begin(), Cases.end(), CaseCmp()); 1815 1816 // Merge case into clusters 1817 if (Cases.size()>=2) 1818 for (CaseItr I=Cases.begin(), J=++(Cases.begin()), E=Cases.end(); J!=E; ) { 1819 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 1820 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 1821 MachineBasicBlock* nextBB = J->BB; 1822 MachineBasicBlock* currentBB = I->BB; 1823 1824 // If the two neighboring cases go to the same destination, merge them 1825 // into a single case. 1826 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 1827 I->High = J->High; 1828 J = Cases.erase(J); 1829 } else { 1830 I = J++; 1831 } 1832 } 1833 1834 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1835 if (I->Low != I->High) 1836 // A range counts double, since it requires two compares. 1837 ++numCmps; 1838 } 1839 1840 return numCmps; 1841} 1842 1843void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 1844 // Figure out which block is immediately after the current one. 1845 MachineBasicBlock *NextBlock = 0; 1846 MachineFunction::iterator BBI = CurMBB; 1847 1848 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 1849 1850 // If there is only the default destination, branch to it if it is not the 1851 // next basic block. Otherwise, just fall through. 1852 if (SI.getNumOperands() == 2) { 1853 // Update machine-CFG edges. 1854 1855 // If this is not a fall-through branch, emit the branch. 1856 if (Default != NextBlock) 1857 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1858 DAG.getBasicBlock(Default))); 1859 1860 CurMBB->addSuccessor(Default); 1861 return; 1862 } 1863 1864 // If there are any non-default case statements, create a vector of Cases 1865 // representing each one, and sort the vector so that we can efficiently 1866 // create a binary search tree from them. 1867 CaseVector Cases; 1868 unsigned numCmps = Clusterify(Cases, SI); 1869 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 1870 << ". Total compares: " << numCmps << "\n"; 1871 1872 // Get the Value to be switched on and default basic blocks, which will be 1873 // inserted into CaseBlock records, representing basic blocks in the binary 1874 // search tree. 1875 Value *SV = SI.getOperand(0); 1876 1877 // Push the initial CaseRec onto the worklist 1878 CaseRecVector WorkList; 1879 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1880 1881 while (!WorkList.empty()) { 1882 // Grab a record representing a case range to process off the worklist 1883 CaseRec CR = WorkList.back(); 1884 WorkList.pop_back(); 1885 1886 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 1887 continue; 1888 1889 // If the range has few cases (two or less) emit a series of specific 1890 // tests. 1891 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 1892 continue; 1893 1894 // If the switch has more than 5 blocks, and at least 40% dense, and the 1895 // target supports indirect branches, then emit a jump table rather than 1896 // lowering the switch to a binary tree of conditional branches. 1897 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 1898 continue; 1899 1900 // Emit binary tree. We need to pick a pivot, and push left and right ranges 1901 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 1902 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 1903 } 1904} 1905 1906 1907void SelectionDAGLowering::visitSub(User &I) { 1908 // -0.0 - X --> fneg 1909 const Type *Ty = I.getType(); 1910 if (isa<VectorType>(Ty)) { 1911 visitVectorBinary(I, ISD::VSUB); 1912 } else if (Ty->isFloatingPoint()) { 1913 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 1914 if (CFP->isExactlyValue(-0.0)) { 1915 SDOperand Op2 = getValue(I.getOperand(1)); 1916 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 1917 return; 1918 } 1919 visitScalarBinary(I, ISD::FSUB); 1920 } else 1921 visitScalarBinary(I, ISD::SUB); 1922} 1923 1924void SelectionDAGLowering::visitScalarBinary(User &I, unsigned OpCode) { 1925 SDOperand Op1 = getValue(I.getOperand(0)); 1926 SDOperand Op2 = getValue(I.getOperand(1)); 1927 1928 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 1929} 1930 1931void 1932SelectionDAGLowering::visitVectorBinary(User &I, unsigned OpCode) { 1933 assert(isa<VectorType>(I.getType())); 1934 const VectorType *Ty = cast<VectorType>(I.getType()); 1935 SDOperand Typ = DAG.getValueType(TLI.getValueType(Ty->getElementType())); 1936 1937 setValue(&I, DAG.getNode(OpCode, MVT::Vector, 1938 getValue(I.getOperand(0)), 1939 getValue(I.getOperand(1)), 1940 DAG.getConstant(Ty->getNumElements(), MVT::i32), 1941 Typ)); 1942} 1943 1944void SelectionDAGLowering::visitEitherBinary(User &I, unsigned ScalarOp, 1945 unsigned VectorOp) { 1946 if (isa<VectorType>(I.getType())) 1947 visitVectorBinary(I, VectorOp); 1948 else 1949 visitScalarBinary(I, ScalarOp); 1950} 1951 1952void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 1953 SDOperand Op1 = getValue(I.getOperand(0)); 1954 SDOperand Op2 = getValue(I.getOperand(1)); 1955 1956 if (TLI.getShiftAmountTy() < Op2.getValueType()) 1957 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 1958 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 1959 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 1960 1961 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 1962} 1963 1964void SelectionDAGLowering::visitICmp(User &I) { 1965 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 1966 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 1967 predicate = IC->getPredicate(); 1968 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 1969 predicate = ICmpInst::Predicate(IC->getPredicate()); 1970 SDOperand Op1 = getValue(I.getOperand(0)); 1971 SDOperand Op2 = getValue(I.getOperand(1)); 1972 ISD::CondCode Opcode; 1973 switch (predicate) { 1974 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 1975 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 1976 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 1977 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 1978 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 1979 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 1980 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 1981 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 1982 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 1983 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 1984 default: 1985 assert(!"Invalid ICmp predicate value"); 1986 Opcode = ISD::SETEQ; 1987 break; 1988 } 1989 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 1990} 1991 1992void SelectionDAGLowering::visitFCmp(User &I) { 1993 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 1994 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 1995 predicate = FC->getPredicate(); 1996 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 1997 predicate = FCmpInst::Predicate(FC->getPredicate()); 1998 SDOperand Op1 = getValue(I.getOperand(0)); 1999 SDOperand Op2 = getValue(I.getOperand(1)); 2000 ISD::CondCode Condition, FOC, FPC; 2001 switch (predicate) { 2002 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2003 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2004 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2005 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2006 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2007 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2008 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2009 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 2010 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 2011 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2012 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2013 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2014 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2015 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2016 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2017 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2018 default: 2019 assert(!"Invalid FCmp predicate value"); 2020 FOC = FPC = ISD::SETFALSE; 2021 break; 2022 } 2023 if (FiniteOnlyFPMath()) 2024 Condition = FOC; 2025 else 2026 Condition = FPC; 2027 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2028} 2029 2030void SelectionDAGLowering::visitSelect(User &I) { 2031 SDOperand Cond = getValue(I.getOperand(0)); 2032 SDOperand TrueVal = getValue(I.getOperand(1)); 2033 SDOperand FalseVal = getValue(I.getOperand(2)); 2034 if (!isa<VectorType>(I.getType())) { 2035 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2036 TrueVal, FalseVal)); 2037 } else { 2038 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal, 2039 *(TrueVal.Val->op_end()-2), 2040 *(TrueVal.Val->op_end()-1))); 2041 } 2042} 2043 2044 2045void SelectionDAGLowering::visitTrunc(User &I) { 2046 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2047 SDOperand N = getValue(I.getOperand(0)); 2048 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2049 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2050} 2051 2052void SelectionDAGLowering::visitZExt(User &I) { 2053 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2054 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2055 SDOperand N = getValue(I.getOperand(0)); 2056 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2057 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2058} 2059 2060void SelectionDAGLowering::visitSExt(User &I) { 2061 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2062 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2063 SDOperand N = getValue(I.getOperand(0)); 2064 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2065 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2066} 2067 2068void SelectionDAGLowering::visitFPTrunc(User &I) { 2069 // FPTrunc is never a no-op cast, no need to check 2070 SDOperand N = getValue(I.getOperand(0)); 2071 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2072 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 2073} 2074 2075void SelectionDAGLowering::visitFPExt(User &I){ 2076 // FPTrunc is never a no-op cast, no need to check 2077 SDOperand N = getValue(I.getOperand(0)); 2078 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2079 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2080} 2081 2082void SelectionDAGLowering::visitFPToUI(User &I) { 2083 // FPToUI is never a no-op cast, no need to check 2084 SDOperand N = getValue(I.getOperand(0)); 2085 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2086 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2087} 2088 2089void SelectionDAGLowering::visitFPToSI(User &I) { 2090 // FPToSI is never a no-op cast, no need to check 2091 SDOperand N = getValue(I.getOperand(0)); 2092 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2093 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2094} 2095 2096void SelectionDAGLowering::visitUIToFP(User &I) { 2097 // UIToFP is never a no-op cast, no need to check 2098 SDOperand N = getValue(I.getOperand(0)); 2099 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2100 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2101} 2102 2103void SelectionDAGLowering::visitSIToFP(User &I){ 2104 // UIToFP is never a no-op cast, no need to check 2105 SDOperand N = getValue(I.getOperand(0)); 2106 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2107 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2108} 2109 2110void SelectionDAGLowering::visitPtrToInt(User &I) { 2111 // What to do depends on the size of the integer and the size of the pointer. 2112 // We can either truncate, zero extend, or no-op, accordingly. 2113 SDOperand N = getValue(I.getOperand(0)); 2114 MVT::ValueType SrcVT = N.getValueType(); 2115 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2116 SDOperand Result; 2117 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2118 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2119 else 2120 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2121 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2122 setValue(&I, Result); 2123} 2124 2125void SelectionDAGLowering::visitIntToPtr(User &I) { 2126 // What to do depends on the size of the integer and the size of the pointer. 2127 // We can either truncate, zero extend, or no-op, accordingly. 2128 SDOperand N = getValue(I.getOperand(0)); 2129 MVT::ValueType SrcVT = N.getValueType(); 2130 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2131 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2132 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2133 else 2134 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2135 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2136} 2137 2138void SelectionDAGLowering::visitBitCast(User &I) { 2139 SDOperand N = getValue(I.getOperand(0)); 2140 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2141 if (DestVT == MVT::Vector) { 2142 // This is a cast to a vector from something else. 2143 // Get information about the output vector. 2144 const VectorType *DestTy = cast<VectorType>(I.getType()); 2145 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2146 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N, 2147 DAG.getConstant(DestTy->getNumElements(),MVT::i32), 2148 DAG.getValueType(EltVT))); 2149 return; 2150 } 2151 MVT::ValueType SrcVT = N.getValueType(); 2152 if (SrcVT == MVT::Vector) { 2153 // This is a cast from a vctor to something else. 2154 // Get information about the input vector. 2155 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N)); 2156 return; 2157 } 2158 2159 // BitCast assures us that source and destination are the same size so this 2160 // is either a BIT_CONVERT or a no-op. 2161 if (DestVT != N.getValueType()) 2162 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2163 else 2164 setValue(&I, N); // noop cast. 2165} 2166 2167void SelectionDAGLowering::visitInsertElement(User &I) { 2168 SDOperand InVec = getValue(I.getOperand(0)); 2169 SDOperand InVal = getValue(I.getOperand(1)); 2170 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2171 getValue(I.getOperand(2))); 2172 2173 SDOperand Num = *(InVec.Val->op_end()-2); 2174 SDOperand Typ = *(InVec.Val->op_end()-1); 2175 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector, 2176 InVec, InVal, InIdx, Num, Typ)); 2177} 2178 2179void SelectionDAGLowering::visitExtractElement(User &I) { 2180 SDOperand InVec = getValue(I.getOperand(0)); 2181 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2182 getValue(I.getOperand(1))); 2183 SDOperand Typ = *(InVec.Val->op_end()-1); 2184 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, 2185 TLI.getValueType(I.getType()), InVec, InIdx)); 2186} 2187 2188void SelectionDAGLowering::visitShuffleVector(User &I) { 2189 SDOperand V1 = getValue(I.getOperand(0)); 2190 SDOperand V2 = getValue(I.getOperand(1)); 2191 SDOperand Mask = getValue(I.getOperand(2)); 2192 2193 SDOperand Num = *(V1.Val->op_end()-2); 2194 SDOperand Typ = *(V2.Val->op_end()-1); 2195 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 2196 V1, V2, Mask, Num, Typ)); 2197} 2198 2199 2200void SelectionDAGLowering::visitGetElementPtr(User &I) { 2201 SDOperand N = getValue(I.getOperand(0)); 2202 const Type *Ty = I.getOperand(0)->getType(); 2203 2204 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2205 OI != E; ++OI) { 2206 Value *Idx = *OI; 2207 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2208 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2209 if (Field) { 2210 // N = N + Offset 2211 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2212 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2213 getIntPtrConstant(Offset)); 2214 } 2215 Ty = StTy->getElementType(Field); 2216 } else { 2217 Ty = cast<SequentialType>(Ty)->getElementType(); 2218 2219 // If this is a constant subscript, handle it quickly. 2220 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2221 if (CI->getZExtValue() == 0) continue; 2222 uint64_t Offs = 2223 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2224 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 2225 continue; 2226 } 2227 2228 // N = N + Idx * ElementSize; 2229 uint64_t ElementSize = TD->getTypeSize(Ty); 2230 SDOperand IdxN = getValue(Idx); 2231 2232 // If the index is smaller or larger than intptr_t, truncate or extend 2233 // it. 2234 if (IdxN.getValueType() < N.getValueType()) { 2235 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2236 } else if (IdxN.getValueType() > N.getValueType()) 2237 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2238 2239 // If this is a multiply by a power of two, turn it into a shl 2240 // immediately. This is a very common case. 2241 if (isPowerOf2_64(ElementSize)) { 2242 unsigned Amt = Log2_64(ElementSize); 2243 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2244 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2245 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2246 continue; 2247 } 2248 2249 SDOperand Scale = getIntPtrConstant(ElementSize); 2250 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2251 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2252 } 2253 } 2254 setValue(&I, N); 2255} 2256 2257void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2258 // If this is a fixed sized alloca in the entry block of the function, 2259 // allocate it statically on the stack. 2260 if (FuncInfo.StaticAllocaMap.count(&I)) 2261 return; // getValue will auto-populate this. 2262 2263 const Type *Ty = I.getAllocatedType(); 2264 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 2265 unsigned Align = 2266 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2267 I.getAlignment()); 2268 2269 SDOperand AllocSize = getValue(I.getArraySize()); 2270 MVT::ValueType IntPtr = TLI.getPointerTy(); 2271 if (IntPtr < AllocSize.getValueType()) 2272 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2273 else if (IntPtr > AllocSize.getValueType()) 2274 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2275 2276 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2277 getIntPtrConstant(TySize)); 2278 2279 // Handle alignment. If the requested alignment is less than or equal to the 2280 // stack alignment, ignore it and round the size of the allocation up to the 2281 // stack alignment size. If the size is greater than the stack alignment, we 2282 // note this in the DYNAMIC_STACKALLOC node. 2283 unsigned StackAlign = 2284 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2285 if (Align <= StackAlign) { 2286 Align = 0; 2287 // Add SA-1 to the size. 2288 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2289 getIntPtrConstant(StackAlign-1)); 2290 // Mask out the low bits for alignment purposes. 2291 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2292 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2293 } 2294 2295 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 2296 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2297 MVT::Other); 2298 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2299 setValue(&I, DSA); 2300 DAG.setRoot(DSA.getValue(1)); 2301 2302 // Inform the Frame Information that we have just allocated a variable-sized 2303 // object. 2304 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2305} 2306 2307void SelectionDAGLowering::visitLoad(LoadInst &I) { 2308 SDOperand Ptr = getValue(I.getOperand(0)); 2309 2310 SDOperand Root; 2311 if (I.isVolatile()) 2312 Root = getRoot(); 2313 else { 2314 // Do not serialize non-volatile loads against each other. 2315 Root = DAG.getRoot(); 2316 } 2317 2318 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2319 Root, I.isVolatile(), I.getAlignment())); 2320} 2321 2322SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2323 const Value *SV, SDOperand Root, 2324 bool isVolatile, 2325 unsigned Alignment) { 2326 SDOperand L; 2327 if (const VectorType *PTy = dyn_cast<VectorType>(Ty)) { 2328 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 2329 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, 2330 DAG.getSrcValue(SV)); 2331 } else { 2332 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2333 isVolatile, Alignment); 2334 } 2335 2336 if (isVolatile) 2337 DAG.setRoot(L.getValue(1)); 2338 else 2339 PendingLoads.push_back(L.getValue(1)); 2340 2341 return L; 2342} 2343 2344 2345void SelectionDAGLowering::visitStore(StoreInst &I) { 2346 Value *SrcV = I.getOperand(0); 2347 SDOperand Src = getValue(SrcV); 2348 SDOperand Ptr = getValue(I.getOperand(1)); 2349 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2350 I.isVolatile(), I.getAlignment())); 2351} 2352 2353/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot 2354/// access memory and has no other side effects at all. 2355static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) { 2356#define GET_NO_MEMORY_INTRINSICS 2357#include "llvm/Intrinsics.gen" 2358#undef GET_NO_MEMORY_INTRINSICS 2359 return false; 2360} 2361 2362// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't 2363// have any side-effects or if it only reads memory. 2364static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) { 2365#define GET_SIDE_EFFECT_INFO 2366#include "llvm/Intrinsics.gen" 2367#undef GET_SIDE_EFFECT_INFO 2368 return false; 2369} 2370 2371/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2372/// node. 2373void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2374 unsigned Intrinsic) { 2375 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic); 2376 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic); 2377 2378 // Build the operand list. 2379 SmallVector<SDOperand, 8> Ops; 2380 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2381 if (OnlyLoad) { 2382 // We don't need to serialize loads against other loads. 2383 Ops.push_back(DAG.getRoot()); 2384 } else { 2385 Ops.push_back(getRoot()); 2386 } 2387 } 2388 2389 // Add the intrinsic ID as an integer operand. 2390 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2391 2392 // Add all operands of the call to the operand list. 2393 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2394 SDOperand Op = getValue(I.getOperand(i)); 2395 2396 // If this is a vector type, force it to the right vector type. 2397 if (Op.getValueType() == MVT::Vector) { 2398 const VectorType *OpTy = cast<VectorType>(I.getOperand(i)->getType()); 2399 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType()); 2400 2401 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements()); 2402 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?"); 2403 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op); 2404 } 2405 2406 assert(TLI.isTypeLegal(Op.getValueType()) && 2407 "Intrinsic uses a non-legal type?"); 2408 Ops.push_back(Op); 2409 } 2410 2411 std::vector<MVT::ValueType> VTs; 2412 if (I.getType() != Type::VoidTy) { 2413 MVT::ValueType VT = TLI.getValueType(I.getType()); 2414 if (VT == MVT::Vector) { 2415 const VectorType *DestTy = cast<VectorType>(I.getType()); 2416 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2417 2418 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2419 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2420 } 2421 2422 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2423 VTs.push_back(VT); 2424 } 2425 if (HasChain) 2426 VTs.push_back(MVT::Other); 2427 2428 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2429 2430 // Create the node. 2431 SDOperand Result; 2432 if (!HasChain) 2433 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2434 &Ops[0], Ops.size()); 2435 else if (I.getType() != Type::VoidTy) 2436 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2437 &Ops[0], Ops.size()); 2438 else 2439 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2440 &Ops[0], Ops.size()); 2441 2442 if (HasChain) { 2443 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2444 if (OnlyLoad) 2445 PendingLoads.push_back(Chain); 2446 else 2447 DAG.setRoot(Chain); 2448 } 2449 if (I.getType() != Type::VoidTy) { 2450 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2451 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType()); 2452 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 2453 DAG.getConstant(PTy->getNumElements(), MVT::i32), 2454 DAG.getValueType(EVT)); 2455 } 2456 setValue(&I, Result); 2457 } 2458} 2459 2460/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2461/// we want to emit this as a call to a named external function, return the name 2462/// otherwise lower it and return null. 2463const char * 2464SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2465 switch (Intrinsic) { 2466 default: 2467 // By default, turn this into a target intrinsic node. 2468 visitTargetIntrinsic(I, Intrinsic); 2469 return 0; 2470 case Intrinsic::vastart: visitVAStart(I); return 0; 2471 case Intrinsic::vaend: visitVAEnd(I); return 0; 2472 case Intrinsic::vacopy: visitVACopy(I); return 0; 2473 case Intrinsic::returnaddress: 2474 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2475 getValue(I.getOperand(1)))); 2476 return 0; 2477 case Intrinsic::frameaddress: 2478 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2479 getValue(I.getOperand(1)))); 2480 return 0; 2481 case Intrinsic::setjmp: 2482 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2483 break; 2484 case Intrinsic::longjmp: 2485 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2486 break; 2487 case Intrinsic::memcpy_i32: 2488 case Intrinsic::memcpy_i64: 2489 visitMemIntrinsic(I, ISD::MEMCPY); 2490 return 0; 2491 case Intrinsic::memset_i32: 2492 case Intrinsic::memset_i64: 2493 visitMemIntrinsic(I, ISD::MEMSET); 2494 return 0; 2495 case Intrinsic::memmove_i32: 2496 case Intrinsic::memmove_i64: 2497 visitMemIntrinsic(I, ISD::MEMMOVE); 2498 return 0; 2499 2500 case Intrinsic::dbg_stoppoint: { 2501 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2502 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2503 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2504 SDOperand Ops[5]; 2505 2506 Ops[0] = getRoot(); 2507 Ops[1] = getValue(SPI.getLineValue()); 2508 Ops[2] = getValue(SPI.getColumnValue()); 2509 2510 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2511 assert(DD && "Not a debug information descriptor"); 2512 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2513 2514 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2515 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2516 2517 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2518 } 2519 2520 return 0; 2521 } 2522 case Intrinsic::dbg_region_start: { 2523 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2524 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2525 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2526 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2527 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2528 DAG.getConstant(LabelID, MVT::i32))); 2529 } 2530 2531 return 0; 2532 } 2533 case Intrinsic::dbg_region_end: { 2534 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2535 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2536 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2537 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2538 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2539 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2540 } 2541 2542 return 0; 2543 } 2544 case Intrinsic::dbg_func_start: { 2545 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2546 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2547 if (MMI && FSI.getSubprogram() && 2548 MMI->Verify(FSI.getSubprogram())) { 2549 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram()); 2550 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2551 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2552 } 2553 2554 return 0; 2555 } 2556 case Intrinsic::dbg_declare: { 2557 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2558 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2559 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) { 2560 SDOperand AddressOp = getValue(DI.getAddress()); 2561 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 2562 MMI->RecordVariable(DI.getVariable(), FI->getIndex()); 2563 } 2564 2565 return 0; 2566 } 2567 2568 case Intrinsic::eh_exception: { 2569 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2570 2571 if (MMI) { 2572 // Add a label to mark the beginning of the landing pad. Deletion of the 2573 // landing pad can thus be detected via the MachineModuleInfo. 2574 unsigned LabelID = MMI->addLandingPad(CurMBB); 2575 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 2576 DAG.getConstant(LabelID, MVT::i32))); 2577 2578 // Mark exception register as live in. 2579 unsigned Reg = TLI.getExceptionAddressRegister(); 2580 if (Reg) CurMBB->addLiveIn(Reg); 2581 2582 // Insert the EXCEPTIONADDR instruction. 2583 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2584 SDOperand Ops[1]; 2585 Ops[0] = DAG.getRoot(); 2586 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2587 setValue(&I, Op); 2588 DAG.setRoot(Op.getValue(1)); 2589 } else { 2590 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2591 } 2592 return 0; 2593 } 2594 2595 case Intrinsic::eh_selector: 2596 case Intrinsic::eh_filter:{ 2597 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2598 2599 if (MMI) { 2600 // Inform the MachineModuleInfo of the personality for this landing pad. 2601 ConstantExpr *CE = dyn_cast<ConstantExpr>(I.getOperand(2)); 2602 assert(CE && CE->getOpcode() == Instruction::BitCast && 2603 isa<Function>(CE->getOperand(0)) && 2604 "Personality should be a function"); 2605 MMI->addPersonality(CurMBB, cast<Function>(CE->getOperand(0))); 2606 if (Intrinsic == Intrinsic::eh_filter) 2607 MMI->setIsFilterLandingPad(CurMBB); 2608 2609 // Gather all the type infos for this landing pad and pass them along to 2610 // MachineModuleInfo. 2611 std::vector<GlobalVariable *> TyInfo; 2612 for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) { 2613 Constant *C = cast<Constant>(I.getOperand(i)); 2614 if (GlobalVariable *GV = dyn_cast<GlobalVariable>(C)) { 2615 TyInfo.push_back(GV); 2616 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 2617 assert(CE->getOpcode() == Instruction::BitCast && 2618 isa<GlobalVariable>(CE->getOperand(0)) 2619 && "TypeInfo must be a global variable or NULL"); 2620 TyInfo.push_back(cast<GlobalVariable>(CE->getOperand(0))); 2621 } else { 2622 ConstantInt *CI = dyn_cast<ConstantInt>(C); 2623 assert(CI && CI->isNullValue() && 2624 "TypeInfo must be a global variable or NULL"); 2625 TyInfo.push_back(NULL); 2626 } 2627 } 2628 MMI->addCatchTypeInfo(CurMBB, TyInfo); 2629 2630 // Mark exception selector register as live in. 2631 unsigned Reg = TLI.getExceptionSelectorRegister(); 2632 if (Reg) CurMBB->addLiveIn(Reg); 2633 2634 // Insert the EHSELECTION instruction. 2635 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2636 SDOperand Ops[2]; 2637 Ops[0] = getValue(I.getOperand(1)); 2638 Ops[1] = getRoot(); 2639 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2640 setValue(&I, Op); 2641 DAG.setRoot(Op.getValue(1)); 2642 } else { 2643 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2644 } 2645 2646 return 0; 2647 } 2648 2649 case Intrinsic::eh_typeid_for: { 2650 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2651 2652 if (MMI) { 2653 // Find the type id for the given typeinfo. 2654 GlobalVariable *GV = NULL; 2655 ConstantExpr *CE = dyn_cast<ConstantExpr>(I.getOperand(1)); 2656 if (CE && CE->getOpcode() == Instruction::BitCast && 2657 isa<GlobalVariable>(CE->getOperand(0))) { 2658 GV = cast<GlobalVariable>(CE->getOperand(0)); 2659 } else { 2660 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1)); 2661 assert(CI && CI->getZExtValue() == 0 && 2662 "TypeInfo must be a global variable typeinfo or NULL"); 2663 GV = NULL; 2664 } 2665 2666 unsigned TypeID = MMI->getTypeIDFor(GV); 2667 setValue(&I, DAG.getConstant(TypeID, MVT::i32)); 2668 } else { 2669 setValue(&I, DAG.getConstant(0, MVT::i32)); 2670 } 2671 2672 return 0; 2673 } 2674 2675 case Intrinsic::sqrt_f32: 2676 case Intrinsic::sqrt_f64: 2677 setValue(&I, DAG.getNode(ISD::FSQRT, 2678 getValue(I.getOperand(1)).getValueType(), 2679 getValue(I.getOperand(1)))); 2680 return 0; 2681 case Intrinsic::powi_f32: 2682 case Intrinsic::powi_f64: 2683 setValue(&I, DAG.getNode(ISD::FPOWI, 2684 getValue(I.getOperand(1)).getValueType(), 2685 getValue(I.getOperand(1)), 2686 getValue(I.getOperand(2)))); 2687 return 0; 2688 case Intrinsic::pcmarker: { 2689 SDOperand Tmp = getValue(I.getOperand(1)); 2690 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2691 return 0; 2692 } 2693 case Intrinsic::readcyclecounter: { 2694 SDOperand Op = getRoot(); 2695 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2696 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2697 &Op, 1); 2698 setValue(&I, Tmp); 2699 DAG.setRoot(Tmp.getValue(1)); 2700 return 0; 2701 } 2702 case Intrinsic::part_select: { 2703 // Currently not implemented: just abort 2704 assert(0 && "part_select intrinsic not implemented"); 2705 abort(); 2706 } 2707 case Intrinsic::part_set: { 2708 // Currently not implemented: just abort 2709 assert(0 && "part_set intrinsic not implemented"); 2710 abort(); 2711 } 2712 case Intrinsic::bswap: 2713 setValue(&I, DAG.getNode(ISD::BSWAP, 2714 getValue(I.getOperand(1)).getValueType(), 2715 getValue(I.getOperand(1)))); 2716 return 0; 2717 case Intrinsic::cttz: { 2718 SDOperand Arg = getValue(I.getOperand(1)); 2719 MVT::ValueType Ty = Arg.getValueType(); 2720 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2721 if (Ty < MVT::i32) 2722 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2723 else if (Ty > MVT::i32) 2724 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2725 setValue(&I, result); 2726 return 0; 2727 } 2728 case Intrinsic::ctlz: { 2729 SDOperand Arg = getValue(I.getOperand(1)); 2730 MVT::ValueType Ty = Arg.getValueType(); 2731 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2732 if (Ty < MVT::i32) 2733 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2734 else if (Ty > MVT::i32) 2735 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2736 setValue(&I, result); 2737 return 0; 2738 } 2739 case Intrinsic::ctpop: { 2740 SDOperand Arg = getValue(I.getOperand(1)); 2741 MVT::ValueType Ty = Arg.getValueType(); 2742 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2743 if (Ty < MVT::i32) 2744 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2745 else if (Ty > MVT::i32) 2746 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2747 setValue(&I, result); 2748 return 0; 2749 } 2750 case Intrinsic::stacksave: { 2751 SDOperand Op = getRoot(); 2752 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2753 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2754 setValue(&I, Tmp); 2755 DAG.setRoot(Tmp.getValue(1)); 2756 return 0; 2757 } 2758 case Intrinsic::stackrestore: { 2759 SDOperand Tmp = getValue(I.getOperand(1)); 2760 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2761 return 0; 2762 } 2763 case Intrinsic::prefetch: 2764 // FIXME: Currently discarding prefetches. 2765 return 0; 2766 } 2767} 2768 2769 2770void SelectionDAGLowering::LowerCallTo(Instruction &I, 2771 const Type *CalledValueTy, 2772 unsigned CallingConv, 2773 bool IsTailCall, 2774 SDOperand Callee, unsigned OpIdx) { 2775 const PointerType *PT = cast<PointerType>(CalledValueTy); 2776 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 2777 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 2778 2779 TargetLowering::ArgListTy Args; 2780 TargetLowering::ArgListEntry Entry; 2781 Args.reserve(I.getNumOperands()); 2782 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) { 2783 Value *Arg = I.getOperand(i); 2784 SDOperand ArgNode = getValue(Arg); 2785 Entry.Node = ArgNode; Entry.Ty = Arg->getType(); 2786 Entry.isSExt = Attrs && Attrs->paramHasAttr(i, ParamAttr::SExt); 2787 Entry.isZExt = Attrs && Attrs->paramHasAttr(i, ParamAttr::ZExt); 2788 Entry.isInReg = Attrs && Attrs->paramHasAttr(i, ParamAttr::InReg); 2789 Entry.isSRet = Attrs && Attrs->paramHasAttr(i, ParamAttr::StructRet); 2790 Args.push_back(Entry); 2791 } 2792 2793 std::pair<SDOperand,SDOperand> Result = 2794 TLI.LowerCallTo(getRoot(), I.getType(), 2795 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt), 2796 FTy->isVarArg(), CallingConv, IsTailCall, 2797 Callee, Args, DAG); 2798 if (I.getType() != Type::VoidTy) 2799 setValue(&I, Result.first); 2800 DAG.setRoot(Result.second); 2801} 2802 2803 2804void SelectionDAGLowering::visitCall(CallInst &I) { 2805 const char *RenameFn = 0; 2806 if (Function *F = I.getCalledFunction()) { 2807 if (F->isDeclaration()) 2808 if (unsigned IID = F->getIntrinsicID()) { 2809 RenameFn = visitIntrinsicCall(I, IID); 2810 if (!RenameFn) 2811 return; 2812 } else { // Not an LLVM intrinsic. 2813 const std::string &Name = F->getName(); 2814 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) { 2815 if (I.getNumOperands() == 3 && // Basic sanity checks. 2816 I.getOperand(1)->getType()->isFloatingPoint() && 2817 I.getType() == I.getOperand(1)->getType() && 2818 I.getType() == I.getOperand(2)->getType()) { 2819 SDOperand LHS = getValue(I.getOperand(1)); 2820 SDOperand RHS = getValue(I.getOperand(2)); 2821 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 2822 LHS, RHS)); 2823 return; 2824 } 2825 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) { 2826 if (I.getNumOperands() == 2 && // Basic sanity checks. 2827 I.getOperand(1)->getType()->isFloatingPoint() && 2828 I.getType() == I.getOperand(1)->getType()) { 2829 SDOperand Tmp = getValue(I.getOperand(1)); 2830 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 2831 return; 2832 } 2833 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) { 2834 if (I.getNumOperands() == 2 && // Basic sanity checks. 2835 I.getOperand(1)->getType()->isFloatingPoint() && 2836 I.getType() == I.getOperand(1)->getType()) { 2837 SDOperand Tmp = getValue(I.getOperand(1)); 2838 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 2839 return; 2840 } 2841 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) { 2842 if (I.getNumOperands() == 2 && // Basic sanity checks. 2843 I.getOperand(1)->getType()->isFloatingPoint() && 2844 I.getType() == I.getOperand(1)->getType()) { 2845 SDOperand Tmp = getValue(I.getOperand(1)); 2846 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 2847 return; 2848 } 2849 } 2850 } 2851 } else if (isa<InlineAsm>(I.getOperand(0))) { 2852 visitInlineAsm(I); 2853 return; 2854 } 2855 2856 SDOperand Callee; 2857 if (!RenameFn) 2858 Callee = getValue(I.getOperand(0)); 2859 else 2860 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 2861 2862 LowerCallTo(I, I.getCalledValue()->getType(), 2863 I.getCallingConv(), 2864 I.isTailCall(), 2865 Callee, 2866 1); 2867} 2868 2869 2870SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 2871 SDOperand &Chain, SDOperand &Flag)const{ 2872 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag); 2873 Chain = Val.getValue(1); 2874 Flag = Val.getValue(2); 2875 2876 // If the result was expanded, copy from the top part. 2877 if (Regs.size() > 1) { 2878 assert(Regs.size() == 2 && 2879 "Cannot expand to more than 2 elts yet!"); 2880 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag); 2881 Chain = Hi.getValue(1); 2882 Flag = Hi.getValue(2); 2883 if (DAG.getTargetLoweringInfo().isLittleEndian()) 2884 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 2885 else 2886 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val); 2887 } 2888 2889 // Otherwise, if the return value was promoted or extended, truncate it to the 2890 // appropriate type. 2891 if (RegVT == ValueVT) 2892 return Val; 2893 2894 if (MVT::isVector(RegVT)) { 2895 assert(ValueVT == MVT::Vector && "Unknown vector conversion!"); 2896 return DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val, 2897 DAG.getConstant(MVT::getVectorNumElements(RegVT), 2898 MVT::i32), 2899 DAG.getValueType(MVT::getVectorBaseType(RegVT))); 2900 } 2901 2902 if (MVT::isInteger(RegVT)) { 2903 if (ValueVT < RegVT) 2904 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 2905 else 2906 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 2907 } 2908 2909 assert(MVT::isFloatingPoint(RegVT) && MVT::isFloatingPoint(ValueVT)); 2910 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 2911} 2912 2913/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 2914/// specified value into the registers specified by this object. This uses 2915/// Chain/Flag as the input and updates them for the output Chain/Flag. 2916void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 2917 SDOperand &Chain, SDOperand &Flag, 2918 MVT::ValueType PtrVT) const { 2919 if (Regs.size() == 1) { 2920 // If there is a single register and the types differ, this must be 2921 // a promotion. 2922 if (RegVT != ValueVT) { 2923 if (MVT::isVector(RegVT)) { 2924 assert(Val.getValueType() == MVT::Vector &&"Not a vector-vector cast?"); 2925 Val = DAG.getNode(ISD::VBIT_CONVERT, RegVT, Val); 2926 } else if (MVT::isInteger(RegVT) && MVT::isInteger(Val.getValueType())) { 2927 if (RegVT < ValueVT) 2928 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val); 2929 else 2930 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val); 2931 } else if (MVT::isFloatingPoint(RegVT) && 2932 MVT::isFloatingPoint(Val.getValueType())) { 2933 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val); 2934 } else if (MVT::getSizeInBits(RegVT) == 2935 MVT::getSizeInBits(Val.getValueType())) { 2936 Val = DAG.getNode(ISD::BIT_CONVERT, RegVT, Val); 2937 } else { 2938 assert(0 && "Unknown mismatch!"); 2939 } 2940 } 2941 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag); 2942 Flag = Chain.getValue(1); 2943 } else { 2944 std::vector<unsigned> R(Regs); 2945 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 2946 std::reverse(R.begin(), R.end()); 2947 2948 for (unsigned i = 0, e = R.size(); i != e; ++i) { 2949 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val, 2950 DAG.getConstant(i, PtrVT)); 2951 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag); 2952 Flag = Chain.getValue(1); 2953 } 2954 } 2955} 2956 2957/// AddInlineAsmOperands - Add this value to the specified inlineasm node 2958/// operand list. This adds the code marker and includes the number of 2959/// values added into it. 2960void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 2961 std::vector<SDOperand> &Ops) const { 2962 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 2963 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 2964 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 2965 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 2966} 2967 2968/// isAllocatableRegister - If the specified register is safe to allocate, 2969/// i.e. it isn't a stack pointer or some other special register, return the 2970/// register class for the register. Otherwise, return null. 2971static const TargetRegisterClass * 2972isAllocatableRegister(unsigned Reg, MachineFunction &MF, 2973 const TargetLowering &TLI, const MRegisterInfo *MRI) { 2974 MVT::ValueType FoundVT = MVT::Other; 2975 const TargetRegisterClass *FoundRC = 0; 2976 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 2977 E = MRI->regclass_end(); RCI != E; ++RCI) { 2978 MVT::ValueType ThisVT = MVT::Other; 2979 2980 const TargetRegisterClass *RC = *RCI; 2981 // If none of the the value types for this register class are valid, we 2982 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2983 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2984 I != E; ++I) { 2985 if (TLI.isTypeLegal(*I)) { 2986 // If we have already found this register in a different register class, 2987 // choose the one with the largest VT specified. For example, on 2988 // PowerPC, we favor f64 register classes over f32. 2989 if (FoundVT == MVT::Other || 2990 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 2991 ThisVT = *I; 2992 break; 2993 } 2994 } 2995 } 2996 2997 if (ThisVT == MVT::Other) continue; 2998 2999 // NOTE: This isn't ideal. In particular, this might allocate the 3000 // frame pointer in functions that need it (due to them not being taken 3001 // out of allocation, because a variable sized allocation hasn't been seen 3002 // yet). This is a slight code pessimization, but should still work. 3003 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3004 E = RC->allocation_order_end(MF); I != E; ++I) 3005 if (*I == Reg) { 3006 // We found a matching register class. Keep looking at others in case 3007 // we find one with larger registers that this physreg is also in. 3008 FoundRC = RC; 3009 FoundVT = ThisVT; 3010 break; 3011 } 3012 } 3013 return FoundRC; 3014} 3015 3016 3017namespace { 3018/// AsmOperandInfo - This contains information for each constraint that we are 3019/// lowering. 3020struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 3021 /// ConstraintCode - This contains the actual string for the code, like "m". 3022 std::string ConstraintCode; 3023 3024 /// ConstraintType - Information about the constraint code, e.g. Register, 3025 /// RegisterClass, Memory, Other, Unknown. 3026 TargetLowering::ConstraintType ConstraintType; 3027 3028 /// CallOperand/CallOperandval - If this is the result output operand or a 3029 /// clobber, this is null, otherwise it is the incoming operand to the 3030 /// CallInst. This gets modified as the asm is processed. 3031 SDOperand CallOperand; 3032 Value *CallOperandVal; 3033 3034 /// ConstraintVT - The ValueType for the operand value. 3035 MVT::ValueType ConstraintVT; 3036 3037 /// AssignedRegs - If this is a register or register class operand, this 3038 /// contains the set of register corresponding to the operand. 3039 RegsForValue AssignedRegs; 3040 3041 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3042 : InlineAsm::ConstraintInfo(info), 3043 ConstraintType(TargetLowering::C_Unknown), 3044 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) { 3045 } 3046 3047 void ComputeConstraintToUse(const TargetLowering &TLI); 3048 3049 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3050 /// busy in OutputRegs/InputRegs. 3051 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3052 std::set<unsigned> &OutputRegs, 3053 std::set<unsigned> &InputRegs) const { 3054 if (isOutReg) 3055 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3056 if (isInReg) 3057 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3058 } 3059}; 3060} // end anon namespace. 3061 3062/// getConstraintGenerality - Return an integer indicating how general CT is. 3063static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3064 switch (CT) { 3065 default: assert(0 && "Unknown constraint type!"); 3066 case TargetLowering::C_Other: 3067 case TargetLowering::C_Unknown: 3068 return 0; 3069 case TargetLowering::C_Register: 3070 return 1; 3071 case TargetLowering::C_RegisterClass: 3072 return 2; 3073 case TargetLowering::C_Memory: 3074 return 3; 3075 } 3076} 3077 3078void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) { 3079 assert(!Codes.empty() && "Must have at least one constraint"); 3080 3081 std::string *Current = &Codes[0]; 3082 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current); 3083 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common. 3084 ConstraintCode = *Current; 3085 ConstraintType = CurType; 3086 return; 3087 } 3088 3089 unsigned CurGenerality = getConstraintGenerality(CurType); 3090 3091 // If we have multiple constraints, try to pick the most general one ahead 3092 // of time. This isn't a wonderful solution, but handles common cases. 3093 for (unsigned j = 1, e = Codes.size(); j != e; ++j) { 3094 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]); 3095 unsigned ThisGenerality = getConstraintGenerality(ThisType); 3096 if (ThisGenerality > CurGenerality) { 3097 // This constraint letter is more general than the previous one, 3098 // use it. 3099 CurType = ThisType; 3100 Current = &Codes[j]; 3101 CurGenerality = ThisGenerality; 3102 } 3103 } 3104 3105 ConstraintCode = *Current; 3106 ConstraintType = CurType; 3107} 3108 3109 3110void SelectionDAGLowering:: 3111GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 3112 std::set<unsigned> &OutputRegs, 3113 std::set<unsigned> &InputRegs) { 3114 // Compute whether this value requires an input register, an output register, 3115 // or both. 3116 bool isOutReg = false; 3117 bool isInReg = false; 3118 switch (OpInfo.Type) { 3119 case InlineAsm::isOutput: 3120 isOutReg = true; 3121 3122 // If this is an early-clobber output, or if there is an input 3123 // constraint that matches this, we need to reserve the input register 3124 // so no other inputs allocate to it. 3125 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3126 break; 3127 case InlineAsm::isInput: 3128 isInReg = true; 3129 isOutReg = false; 3130 break; 3131 case InlineAsm::isClobber: 3132 isOutReg = true; 3133 isInReg = true; 3134 break; 3135 } 3136 3137 3138 MachineFunction &MF = DAG.getMachineFunction(); 3139 std::vector<unsigned> Regs; 3140 3141 // If this is a constraint for a single physreg, or a constraint for a 3142 // register class, find it. 3143 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3144 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3145 OpInfo.ConstraintVT); 3146 3147 unsigned NumRegs = 1; 3148 if (OpInfo.ConstraintVT != MVT::Other) 3149 NumRegs = TLI.getNumElements(OpInfo.ConstraintVT); 3150 MVT::ValueType RegVT; 3151 MVT::ValueType ValueVT = OpInfo.ConstraintVT; 3152 3153 3154 // If this is a constraint for a specific physical register, like {r17}, 3155 // assign it now. 3156 if (PhysReg.first) { 3157 if (OpInfo.ConstraintVT == MVT::Other) 3158 ValueVT = *PhysReg.second->vt_begin(); 3159 3160 // Get the actual register value type. This is important, because the user 3161 // may have asked for (e.g.) the AX register in i32 type. We need to 3162 // remember that AX is actually i16 to get the right extension. 3163 RegVT = *PhysReg.second->vt_begin(); 3164 3165 // This is a explicit reference to a physical register. 3166 Regs.push_back(PhysReg.first); 3167 3168 // If this is an expanded reference, add the rest of the regs to Regs. 3169 if (NumRegs != 1) { 3170 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3171 TargetRegisterClass::iterator E = PhysReg.second->end(); 3172 for (; *I != PhysReg.first; ++I) 3173 assert(I != E && "Didn't find reg!"); 3174 3175 // Already added the first reg. 3176 --NumRegs; ++I; 3177 for (; NumRegs; --NumRegs, ++I) { 3178 assert(I != E && "Ran out of registers to allocate!"); 3179 Regs.push_back(*I); 3180 } 3181 } 3182 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3183 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3184 return; 3185 } 3186 3187 // Otherwise, if this was a reference to an LLVM register class, create vregs 3188 // for this reference. 3189 std::vector<unsigned> RegClassRegs; 3190 if (PhysReg.second) { 3191 // If this is an early clobber or tied register, our regalloc doesn't know 3192 // how to maintain the constraint. If it isn't, go ahead and create vreg 3193 // and let the regalloc do the right thing. 3194 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 3195 // If there is some other early clobber and this is an input register, 3196 // then we are forced to pre-allocate the input reg so it doesn't 3197 // conflict with the earlyclobber. 3198 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 3199 RegVT = *PhysReg.second->vt_begin(); 3200 3201 if (OpInfo.ConstraintVT == MVT::Other) 3202 ValueVT = RegVT; 3203 3204 // Create the appropriate number of virtual registers. 3205 SSARegMap *RegMap = MF.getSSARegMap(); 3206 for (; NumRegs; --NumRegs) 3207 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second)); 3208 3209 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3210 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3211 return; 3212 } 3213 3214 // Otherwise, we can't allocate it. Let the code below figure out how to 3215 // maintain these constraints. 3216 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3217 3218 } else { 3219 // This is a reference to a register class that doesn't directly correspond 3220 // to an LLVM register class. Allocate NumRegs consecutive, available, 3221 // registers from the class. 3222 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3223 OpInfo.ConstraintVT); 3224 } 3225 3226 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 3227 unsigned NumAllocated = 0; 3228 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3229 unsigned Reg = RegClassRegs[i]; 3230 // See if this register is available. 3231 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3232 (isInReg && InputRegs.count(Reg))) { // Already used. 3233 // Make sure we find consecutive registers. 3234 NumAllocated = 0; 3235 continue; 3236 } 3237 3238 // Check to see if this register is allocatable (i.e. don't give out the 3239 // stack pointer). 3240 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI); 3241 if (!RC) { 3242 // Make sure we find consecutive registers. 3243 NumAllocated = 0; 3244 continue; 3245 } 3246 3247 // Okay, this register is good, we can use it. 3248 ++NumAllocated; 3249 3250 // If we allocated enough consecutive registers, succeed. 3251 if (NumAllocated == NumRegs) { 3252 unsigned RegStart = (i-NumAllocated)+1; 3253 unsigned RegEnd = i+1; 3254 // Mark all of the allocated registers used. 3255 for (unsigned i = RegStart; i != RegEnd; ++i) 3256 Regs.push_back(RegClassRegs[i]); 3257 3258 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 3259 OpInfo.ConstraintVT); 3260 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3261 return; 3262 } 3263 } 3264 3265 // Otherwise, we couldn't allocate enough registers for this. 3266 return; 3267} 3268 3269 3270/// visitInlineAsm - Handle a call to an InlineAsm object. 3271/// 3272void SelectionDAGLowering::visitInlineAsm(CallInst &I) { 3273 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0)); 3274 3275 /// ConstraintOperands - Information about all of the constraints. 3276 std::vector<AsmOperandInfo> ConstraintOperands; 3277 3278 SDOperand Chain = getRoot(); 3279 SDOperand Flag; 3280 3281 std::set<unsigned> OutputRegs, InputRegs; 3282 3283 // Do a prepass over the constraints, canonicalizing them, and building up the 3284 // ConstraintOperands list. 3285 std::vector<InlineAsm::ConstraintInfo> 3286 ConstraintInfos = IA->ParseConstraints(); 3287 3288 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 3289 // constraint. If so, we can't let the register allocator allocate any input 3290 // registers, because it will not know to avoid the earlyclobbered output reg. 3291 bool SawEarlyClobber = false; 3292 3293 unsigned OpNo = 1; // OpNo - The operand of the CallInst. 3294 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3295 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 3296 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 3297 3298 MVT::ValueType OpVT = MVT::Other; 3299 3300 // Compute the value type for each operand. 3301 switch (OpInfo.Type) { 3302 case InlineAsm::isOutput: 3303 if (!OpInfo.isIndirect) { 3304 // The return value of the call is this value. As such, there is no 3305 // corresponding argument. 3306 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3307 OpVT = TLI.getValueType(I.getType()); 3308 } else { 3309 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3310 } 3311 break; 3312 case InlineAsm::isInput: 3313 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3314 break; 3315 case InlineAsm::isClobber: 3316 // Nothing to do. 3317 break; 3318 } 3319 3320 // If this is an input or an indirect output, process the call argument. 3321 if (OpInfo.CallOperandVal) { 3322 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 3323 const Type *OpTy = OpInfo.CallOperandVal->getType(); 3324 // If this is an indirect operand, the operand is a pointer to the 3325 // accessed type. 3326 if (OpInfo.isIndirect) 3327 OpTy = cast<PointerType>(OpTy)->getElementType(); 3328 3329 // If OpTy is not a first-class value, it may be a struct/union that we 3330 // can tile with integers. 3331 if (!OpTy->isFirstClassType() && OpTy->isSized()) { 3332 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3333 switch (BitSize) { 3334 default: break; 3335 case 1: 3336 case 8: 3337 case 16: 3338 case 32: 3339 case 64: 3340 OpTy = IntegerType::get(BitSize); 3341 break; 3342 } 3343 } 3344 3345 OpVT = TLI.getValueType(OpTy, true); 3346 } 3347 3348 OpInfo.ConstraintVT = OpVT; 3349 3350 // Compute the constraint code and ConstraintType to use. 3351 OpInfo.ComputeConstraintToUse(TLI); 3352 3353 // Keep track of whether we see an earlyclobber. 3354 SawEarlyClobber |= OpInfo.isEarlyClobber; 3355 3356 // If this is a memory input, and if the operand is not indirect, do what we 3357 // need to to provide an address for the memory input. 3358 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 3359 !OpInfo.isIndirect) { 3360 assert(OpInfo.Type == InlineAsm::isInput && 3361 "Can only indirectify direct input operands!"); 3362 3363 // Memory operands really want the address of the value. If we don't have 3364 // an indirect input, put it in the constpool if we can, otherwise spill 3365 // it to a stack slot. 3366 3367 // If the operand is a float, integer, or vector constant, spill to a 3368 // constant pool entry to get its address. 3369 Value *OpVal = OpInfo.CallOperandVal; 3370 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 3371 isa<ConstantVector>(OpVal)) { 3372 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 3373 TLI.getPointerTy()); 3374 } else { 3375 // Otherwise, create a stack slot and emit a store to it before the 3376 // asm. 3377 const Type *Ty = OpVal->getType(); 3378 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3379 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3380 MachineFunction &MF = DAG.getMachineFunction(); 3381 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3382 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3383 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 3384 OpInfo.CallOperand = StackSlot; 3385 } 3386 3387 // There is no longer a Value* corresponding to this operand. 3388 OpInfo.CallOperandVal = 0; 3389 // It is now an indirect operand. 3390 OpInfo.isIndirect = true; 3391 } 3392 3393 // If this constraint is for a specific register, allocate it before 3394 // anything else. 3395 if (OpInfo.ConstraintType == TargetLowering::C_Register) 3396 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3397 } 3398 ConstraintInfos.clear(); 3399 3400 3401 // Second pass - Loop over all of the operands, assigning virtual or physregs 3402 // to registerclass operands. 3403 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3404 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3405 3406 // C_Register operands have already been allocated, Other/Memory don't need 3407 // to be. 3408 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 3409 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3410 } 3411 3412 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 3413 std::vector<SDOperand> AsmNodeOperands; 3414 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3415 AsmNodeOperands.push_back( 3416 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 3417 3418 3419 // Loop over all of the inputs, copying the operand values into the 3420 // appropriate registers and processing the output regs. 3421 RegsForValue RetValRegs; 3422 3423 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 3424 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3425 3426 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3427 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3428 3429 switch (OpInfo.Type) { 3430 case InlineAsm::isOutput: { 3431 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 3432 OpInfo.ConstraintType != TargetLowering::C_Register) { 3433 // Memory output, or 'other' output (e.g. 'X' constraint). 3434 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 3435 3436 // Add information to the INLINEASM node to know about this output. 3437 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3438 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 3439 AsmNodeOperands.push_back(OpInfo.CallOperand); 3440 break; 3441 } 3442 3443 // Otherwise, this is a register or register class output. 3444 3445 // Copy the output from the appropriate register. Find a register that 3446 // we can use. 3447 if (OpInfo.AssignedRegs.Regs.empty()) { 3448 cerr << "Couldn't allocate output reg for contraint '" 3449 << OpInfo.ConstraintCode << "'!\n"; 3450 exit(1); 3451 } 3452 3453 if (!OpInfo.isIndirect) { 3454 // This is the result value of the call. 3455 assert(RetValRegs.Regs.empty() && 3456 "Cannot have multiple output constraints yet!"); 3457 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3458 RetValRegs = OpInfo.AssignedRegs; 3459 } else { 3460 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 3461 OpInfo.CallOperandVal)); 3462 } 3463 3464 // Add information to the INLINEASM node to know that this register is 3465 // set. 3466 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 3467 AsmNodeOperands); 3468 break; 3469 } 3470 case InlineAsm::isInput: { 3471 SDOperand InOperandVal = OpInfo.CallOperand; 3472 3473 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 3474 // If this is required to match an output register we have already set, 3475 // just use its register. 3476 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 3477 3478 // Scan until we find the definition we already emitted of this operand. 3479 // When we find it, create a RegsForValue operand. 3480 unsigned CurOp = 2; // The first operand. 3481 for (; OperandNo; --OperandNo) { 3482 // Advance to the next operand. 3483 unsigned NumOps = 3484 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3485 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3486 (NumOps & 7) == 4 /*MEM*/) && 3487 "Skipped past definitions?"); 3488 CurOp += (NumOps>>3)+1; 3489 } 3490 3491 unsigned NumOps = 3492 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3493 if ((NumOps & 7) == 2 /*REGDEF*/) { 3494 // Add NumOps>>3 registers to MatchedRegs. 3495 RegsForValue MatchedRegs; 3496 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3497 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3498 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3499 unsigned Reg = 3500 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3501 MatchedRegs.Regs.push_back(Reg); 3502 } 3503 3504 // Use the produced MatchedRegs object to 3505 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, 3506 TLI.getPointerTy()); 3507 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3508 break; 3509 } else { 3510 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3511 assert(0 && "matching constraints for memory operands unimp"); 3512 } 3513 } 3514 3515 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 3516 assert(!OpInfo.isIndirect && 3517 "Don't know how to handle indirect other inputs yet!"); 3518 3519 InOperandVal = TLI.isOperandValidForConstraint(InOperandVal, 3520 OpInfo.ConstraintCode[0], 3521 DAG); 3522 if (!InOperandVal.Val) { 3523 cerr << "Invalid operand for inline asm constraint '" 3524 << OpInfo.ConstraintCode << "'!\n"; 3525 exit(1); 3526 } 3527 3528 // Add information to the INLINEASM node to know about this input. 3529 unsigned ResOpType = 3 /*IMM*/ | (1 << 3); 3530 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 3531 AsmNodeOperands.push_back(InOperandVal); 3532 break; 3533 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 3534 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 3535 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 3536 "Memory operands expect pointer values"); 3537 3538 // Add information to the INLINEASM node to know about this input. 3539 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3540 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 3541 AsmNodeOperands.push_back(InOperandVal); 3542 break; 3543 } 3544 3545 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 3546 OpInfo.ConstraintType == TargetLowering::C_Register) && 3547 "Unknown constraint type!"); 3548 assert(!OpInfo.isIndirect && 3549 "Don't know how to handle indirect register inputs yet!"); 3550 3551 // Copy the input into the appropriate registers. 3552 assert(!OpInfo.AssignedRegs.Regs.empty() && 3553 "Couldn't allocate input reg!"); 3554 3555 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, 3556 TLI.getPointerTy()); 3557 3558 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 3559 AsmNodeOperands); 3560 break; 3561 } 3562 case InlineAsm::isClobber: { 3563 // Add the clobbered value to the operand list, so that the register 3564 // allocator is aware that the physreg got clobbered. 3565 if (!OpInfo.AssignedRegs.Regs.empty()) 3566 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 3567 AsmNodeOperands); 3568 break; 3569 } 3570 } 3571 } 3572 3573 // Finish up input operands. 3574 AsmNodeOperands[0] = Chain; 3575 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3576 3577 Chain = DAG.getNode(ISD::INLINEASM, 3578 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3579 &AsmNodeOperands[0], AsmNodeOperands.size()); 3580 Flag = Chain.getValue(1); 3581 3582 // If this asm returns a register value, copy the result from that register 3583 // and set it as the value of the call. 3584 if (!RetValRegs.Regs.empty()) { 3585 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, Flag); 3586 3587 // If the result of the inline asm is a vector, it may have the wrong 3588 // width/num elts. Make sure to convert it to the right type with 3589 // vbit_convert. 3590 if (Val.getValueType() == MVT::Vector) { 3591 const VectorType *VTy = cast<VectorType>(I.getType()); 3592 unsigned DesiredNumElts = VTy->getNumElements(); 3593 MVT::ValueType DesiredEltVT = TLI.getValueType(VTy->getElementType()); 3594 3595 Val = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val, 3596 DAG.getConstant(DesiredNumElts, MVT::i32), 3597 DAG.getValueType(DesiredEltVT)); 3598 } 3599 3600 setValue(&I, Val); 3601 } 3602 3603 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 3604 3605 // Process indirect outputs, first output all of the flagged copies out of 3606 // physregs. 3607 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 3608 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 3609 Value *Ptr = IndirectStoresToEmit[i].second; 3610 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag); 3611 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 3612 } 3613 3614 // Emit the non-flagged stores from the physregs. 3615 SmallVector<SDOperand, 8> OutChains; 3616 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 3617 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 3618 getValue(StoresToEmit[i].second), 3619 StoresToEmit[i].second, 0)); 3620 if (!OutChains.empty()) 3621 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3622 &OutChains[0], OutChains.size()); 3623 DAG.setRoot(Chain); 3624} 3625 3626 3627void SelectionDAGLowering::visitMalloc(MallocInst &I) { 3628 SDOperand Src = getValue(I.getOperand(0)); 3629 3630 MVT::ValueType IntPtr = TLI.getPointerTy(); 3631 3632 if (IntPtr < Src.getValueType()) 3633 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 3634 else if (IntPtr > Src.getValueType()) 3635 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 3636 3637 // Scale the source by the type size. 3638 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType()); 3639 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 3640 Src, getIntPtrConstant(ElementSize)); 3641 3642 TargetLowering::ArgListTy Args; 3643 TargetLowering::ArgListEntry Entry; 3644 Entry.Node = Src; 3645 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3646 Args.push_back(Entry); 3647 3648 std::pair<SDOperand,SDOperand> Result = 3649 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true, 3650 DAG.getExternalSymbol("malloc", IntPtr), 3651 Args, DAG); 3652 setValue(&I, Result.first); // Pointers always fit in registers 3653 DAG.setRoot(Result.second); 3654} 3655 3656void SelectionDAGLowering::visitFree(FreeInst &I) { 3657 TargetLowering::ArgListTy Args; 3658 TargetLowering::ArgListEntry Entry; 3659 Entry.Node = getValue(I.getOperand(0)); 3660 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3661 Args.push_back(Entry); 3662 MVT::ValueType IntPtr = TLI.getPointerTy(); 3663 std::pair<SDOperand,SDOperand> Result = 3664 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true, 3665 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 3666 DAG.setRoot(Result.second); 3667} 3668 3669// InsertAtEndOfBasicBlock - This method should be implemented by targets that 3670// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 3671// instructions are special in various ways, which require special support to 3672// insert. The specified MachineInstr is created but not inserted into any 3673// basic blocks, and the scheduler passes ownership of it to this method. 3674MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3675 MachineBasicBlock *MBB) { 3676 cerr << "If a target marks an instruction with " 3677 << "'usesCustomDAGSchedInserter', it must implement " 3678 << "TargetLowering::InsertAtEndOfBasicBlock!\n"; 3679 abort(); 3680 return 0; 3681} 3682 3683void SelectionDAGLowering::visitVAStart(CallInst &I) { 3684 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 3685 getValue(I.getOperand(1)), 3686 DAG.getSrcValue(I.getOperand(1)))); 3687} 3688 3689void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 3690 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 3691 getValue(I.getOperand(0)), 3692 DAG.getSrcValue(I.getOperand(0))); 3693 setValue(&I, V); 3694 DAG.setRoot(V.getValue(1)); 3695} 3696 3697void SelectionDAGLowering::visitVAEnd(CallInst &I) { 3698 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 3699 getValue(I.getOperand(1)), 3700 DAG.getSrcValue(I.getOperand(1)))); 3701} 3702 3703void SelectionDAGLowering::visitVACopy(CallInst &I) { 3704 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 3705 getValue(I.getOperand(1)), 3706 getValue(I.getOperand(2)), 3707 DAG.getSrcValue(I.getOperand(1)), 3708 DAG.getSrcValue(I.getOperand(2)))); 3709} 3710 3711/// ExpandScalarFormalArgs - Recursively expand the formal_argument node, either 3712/// bit_convert it or join a pair of them with a BUILD_PAIR when appropriate. 3713static SDOperand ExpandScalarFormalArgs(MVT::ValueType VT, SDNode *Arg, 3714 unsigned &i, SelectionDAG &DAG, 3715 TargetLowering &TLI) { 3716 if (TLI.getTypeAction(VT) != TargetLowering::Expand) 3717 return SDOperand(Arg, i++); 3718 3719 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT); 3720 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT); 3721 if (NumVals == 1) { 3722 return DAG.getNode(ISD::BIT_CONVERT, VT, 3723 ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI)); 3724 } else if (NumVals == 2) { 3725 SDOperand Lo = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI); 3726 SDOperand Hi = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI); 3727 if (!TLI.isLittleEndian()) 3728 std::swap(Lo, Hi); 3729 return DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 3730 } else { 3731 // Value scalarized into many values. Unimp for now. 3732 assert(0 && "Cannot expand i64 -> i16 yet!"); 3733 } 3734 return SDOperand(); 3735} 3736 3737/// TargetLowering::LowerArguments - This is the default LowerArguments 3738/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 3739/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 3740/// integrated into SDISel. 3741std::vector<SDOperand> 3742TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 3743 const FunctionType *FTy = F.getFunctionType(); 3744 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 3745 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 3746 std::vector<SDOperand> Ops; 3747 Ops.push_back(DAG.getRoot()); 3748 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 3749 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 3750 3751 // Add one result value for each formal argument. 3752 std::vector<MVT::ValueType> RetVals; 3753 unsigned j = 1; 3754 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 3755 I != E; ++I, ++j) { 3756 MVT::ValueType VT = getValueType(I->getType()); 3757 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3758 unsigned OriginalAlignment = 3759 getTargetData()->getABITypeAlignment(I->getType()); 3760 3761 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 3762 // that is zero extended! 3763 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt)) 3764 Flags &= ~(ISD::ParamFlags::SExt); 3765 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt)) 3766 Flags |= ISD::ParamFlags::SExt; 3767 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg)) 3768 Flags |= ISD::ParamFlags::InReg; 3769 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet)) 3770 Flags |= ISD::ParamFlags::StructReturn; 3771 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs); 3772 3773 switch (getTypeAction(VT)) { 3774 default: assert(0 && "Unknown type action!"); 3775 case Legal: 3776 RetVals.push_back(VT); 3777 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3778 break; 3779 case Promote: 3780 RetVals.push_back(getTypeToTransformTo(VT)); 3781 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3782 break; 3783 case Expand: 3784 if (VT != MVT::Vector) { 3785 // If this is a large integer, it needs to be broken up into small 3786 // integers. Figure out what the destination type is and how many small 3787 // integers it turns into. 3788 MVT::ValueType NVT = getTypeToExpandTo(VT); 3789 unsigned NumVals = getNumElements(VT); 3790 for (unsigned i = 0; i != NumVals; ++i) { 3791 RetVals.push_back(NVT); 3792 // if it isn't first piece, alignment must be 1 3793 if (i > 0) 3794 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3795 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3796 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3797 } 3798 } else { 3799 // Otherwise, this is a vector type. We only support legal vectors 3800 // right now. 3801 unsigned NumElems = cast<VectorType>(I->getType())->getNumElements(); 3802 const Type *EltTy = cast<VectorType>(I->getType())->getElementType(); 3803 3804 // Figure out if there is a Packed type corresponding to this Vector 3805 // type. If so, convert to the vector type. 3806 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 3807 if (TVT != MVT::Other && isTypeLegal(TVT)) { 3808 RetVals.push_back(TVT); 3809 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3810 } else { 3811 assert(0 && "Don't support illegal by-val vector arguments yet!"); 3812 } 3813 } 3814 break; 3815 } 3816 } 3817 3818 RetVals.push_back(MVT::Other); 3819 3820 // Create the node. 3821 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 3822 DAG.getNodeValueTypes(RetVals), RetVals.size(), 3823 &Ops[0], Ops.size()).Val; 3824 3825 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1)); 3826 3827 // Set up the return result vector. 3828 Ops.clear(); 3829 unsigned i = 0; 3830 unsigned Idx = 1; 3831 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 3832 ++I, ++Idx) { 3833 MVT::ValueType VT = getValueType(I->getType()); 3834 3835 switch (getTypeAction(VT)) { 3836 default: assert(0 && "Unknown type action!"); 3837 case Legal: 3838 Ops.push_back(SDOperand(Result, i++)); 3839 break; 3840 case Promote: { 3841 SDOperand Op(Result, i++); 3842 if (MVT::isInteger(VT)) { 3843 if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt)) 3844 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, 3845 DAG.getValueType(VT)); 3846 else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt)) 3847 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, 3848 DAG.getValueType(VT)); 3849 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3850 } else { 3851 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3852 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 3853 } 3854 Ops.push_back(Op); 3855 break; 3856 } 3857 case Expand: 3858 if (VT != MVT::Vector) { 3859 // If this is a large integer or a floating point node that needs to be 3860 // expanded, it needs to be reassembled from small integers. Figure out 3861 // what the source elt type is and how many small integers it is. 3862 Ops.push_back(ExpandScalarFormalArgs(VT, Result, i, DAG, *this)); 3863 } else { 3864 // Otherwise, this is a vector type. We only support legal vectors 3865 // right now. 3866 const VectorType *PTy = cast<VectorType>(I->getType()); 3867 unsigned NumElems = PTy->getNumElements(); 3868 const Type *EltTy = PTy->getElementType(); 3869 3870 // Figure out if there is a Packed type corresponding to this Vector 3871 // type. If so, convert to the vector type. 3872 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 3873 if (TVT != MVT::Other && isTypeLegal(TVT)) { 3874 SDOperand N = SDOperand(Result, i++); 3875 // Handle copies from generic vectors to registers. 3876 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, 3877 DAG.getConstant(NumElems, MVT::i32), 3878 DAG.getValueType(getValueType(EltTy))); 3879 Ops.push_back(N); 3880 } else { 3881 assert(0 && "Don't support illegal by-val vector arguments yet!"); 3882 abort(); 3883 } 3884 } 3885 break; 3886 } 3887 } 3888 return Ops; 3889} 3890 3891 3892/// ExpandScalarCallArgs - Recursively expand call argument node by 3893/// bit_converting it or extract a pair of elements from the larger node. 3894static void ExpandScalarCallArgs(MVT::ValueType VT, SDOperand Arg, 3895 unsigned Flags, 3896 SmallVector<SDOperand, 32> &Ops, 3897 SelectionDAG &DAG, 3898 TargetLowering &TLI, 3899 bool isFirst = true) { 3900 3901 if (TLI.getTypeAction(VT) != TargetLowering::Expand) { 3902 // if it isn't first piece, alignment must be 1 3903 if (!isFirst) 3904 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3905 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3906 Ops.push_back(Arg); 3907 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3908 return; 3909 } 3910 3911 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT); 3912 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT); 3913 if (NumVals == 1) { 3914 Arg = DAG.getNode(ISD::BIT_CONVERT, EVT, Arg); 3915 ExpandScalarCallArgs(EVT, Arg, Flags, Ops, DAG, TLI, isFirst); 3916 } else if (NumVals == 2) { 3917 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg, 3918 DAG.getConstant(0, TLI.getPointerTy())); 3919 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg, 3920 DAG.getConstant(1, TLI.getPointerTy())); 3921 if (!TLI.isLittleEndian()) 3922 std::swap(Lo, Hi); 3923 ExpandScalarCallArgs(EVT, Lo, Flags, Ops, DAG, TLI, isFirst); 3924 ExpandScalarCallArgs(EVT, Hi, Flags, Ops, DAG, TLI, false); 3925 } else { 3926 // Value scalarized into many values. Unimp for now. 3927 assert(0 && "Cannot expand i64 -> i16 yet!"); 3928 } 3929} 3930 3931/// TargetLowering::LowerCallTo - This is the default LowerCallTo 3932/// implementation, which just inserts an ISD::CALL node, which is later custom 3933/// lowered by the target to something concrete. FIXME: When all targets are 3934/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 3935std::pair<SDOperand, SDOperand> 3936TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 3937 bool RetTyIsSigned, bool isVarArg, 3938 unsigned CallingConv, bool isTailCall, 3939 SDOperand Callee, 3940 ArgListTy &Args, SelectionDAG &DAG) { 3941 SmallVector<SDOperand, 32> Ops; 3942 Ops.push_back(Chain); // Op#0 - Chain 3943 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 3944 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 3945 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 3946 Ops.push_back(Callee); 3947 3948 // Handle all of the outgoing arguments. 3949 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 3950 MVT::ValueType VT = getValueType(Args[i].Ty); 3951 SDOperand Op = Args[i].Node; 3952 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3953 unsigned OriginalAlignment = 3954 getTargetData()->getABITypeAlignment(Args[i].Ty); 3955 3956 if (Args[i].isSExt) 3957 Flags |= ISD::ParamFlags::SExt; 3958 if (Args[i].isZExt) 3959 Flags |= ISD::ParamFlags::ZExt; 3960 if (Args[i].isInReg) 3961 Flags |= ISD::ParamFlags::InReg; 3962 if (Args[i].isSRet) 3963 Flags |= ISD::ParamFlags::StructReturn; 3964 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs; 3965 3966 switch (getTypeAction(VT)) { 3967 default: assert(0 && "Unknown type action!"); 3968 case Legal: 3969 Ops.push_back(Op); 3970 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3971 break; 3972 case Promote: 3973 if (MVT::isInteger(VT)) { 3974 unsigned ExtOp; 3975 if (Args[i].isSExt) 3976 ExtOp = ISD::SIGN_EXTEND; 3977 else if (Args[i].isZExt) 3978 ExtOp = ISD::ZERO_EXTEND; 3979 else 3980 ExtOp = ISD::ANY_EXTEND; 3981 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 3982 } else { 3983 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3984 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 3985 } 3986 Ops.push_back(Op); 3987 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3988 break; 3989 case Expand: 3990 if (VT != MVT::Vector) { 3991 // If this is a large integer, it needs to be broken down into small 3992 // integers. Figure out what the source elt type is and how many small 3993 // integers it is. 3994 ExpandScalarCallArgs(VT, Op, Flags, Ops, DAG, *this); 3995 } else { 3996 // Otherwise, this is a vector type. We only support legal vectors 3997 // right now. 3998 const VectorType *PTy = cast<VectorType>(Args[i].Ty); 3999 unsigned NumElems = PTy->getNumElements(); 4000 const Type *EltTy = PTy->getElementType(); 4001 4002 // Figure out if there is a Packed type corresponding to this Vector 4003 // type. If so, convert to the vector type. 4004 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 4005 if (TVT != MVT::Other && isTypeLegal(TVT)) { 4006 // Insert a VBIT_CONVERT of the MVT::Vector type to the vector type. 4007 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op); 4008 Ops.push_back(Op); 4009 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4010 } else { 4011 assert(0 && "Don't support illegal by-val vector call args yet!"); 4012 abort(); 4013 } 4014 } 4015 break; 4016 } 4017 } 4018 4019 // Figure out the result value types. 4020 SmallVector<MVT::ValueType, 4> RetTys; 4021 4022 if (RetTy != Type::VoidTy) { 4023 MVT::ValueType VT = getValueType(RetTy); 4024 switch (getTypeAction(VT)) { 4025 default: assert(0 && "Unknown type action!"); 4026 case Legal: 4027 RetTys.push_back(VT); 4028 break; 4029 case Promote: 4030 RetTys.push_back(getTypeToTransformTo(VT)); 4031 break; 4032 case Expand: 4033 if (VT != MVT::Vector) { 4034 // If this is a large integer, it needs to be reassembled from small 4035 // integers. Figure out what the source elt type is and how many small 4036 // integers it is. 4037 MVT::ValueType NVT = getTypeToExpandTo(VT); 4038 unsigned NumVals = getNumElements(VT); 4039 for (unsigned i = 0; i != NumVals; ++i) 4040 RetTys.push_back(NVT); 4041 } else { 4042 // Otherwise, this is a vector type. We only support legal vectors 4043 // right now. 4044 const VectorType *PTy = cast<VectorType>(RetTy); 4045 unsigned NumElems = PTy->getNumElements(); 4046 const Type *EltTy = PTy->getElementType(); 4047 4048 // Figure out if there is a Packed type corresponding to this Vector 4049 // type. If so, convert to the vector type. 4050 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 4051 if (TVT != MVT::Other && isTypeLegal(TVT)) { 4052 RetTys.push_back(TVT); 4053 } else { 4054 assert(0 && "Don't support illegal by-val vector call results yet!"); 4055 abort(); 4056 } 4057 } 4058 } 4059 } 4060 4061 RetTys.push_back(MVT::Other); // Always has a chain. 4062 4063 // Finally, create the CALL node. 4064 SDOperand Res = DAG.getNode(ISD::CALL, 4065 DAG.getVTList(&RetTys[0], RetTys.size()), 4066 &Ops[0], Ops.size()); 4067 4068 // This returns a pair of operands. The first element is the 4069 // return value for the function (if RetTy is not VoidTy). The second 4070 // element is the outgoing token chain. 4071 SDOperand ResVal; 4072 if (RetTys.size() != 1) { 4073 MVT::ValueType VT = getValueType(RetTy); 4074 if (RetTys.size() == 2) { 4075 ResVal = Res; 4076 4077 // If this value was promoted, truncate it down. 4078 if (ResVal.getValueType() != VT) { 4079 if (VT == MVT::Vector) { 4080 // Insert a VBIT_CONVERT to convert from the packed result type to the 4081 // MVT::Vector type. 4082 unsigned NumElems = cast<VectorType>(RetTy)->getNumElements(); 4083 const Type *EltTy = cast<VectorType>(RetTy)->getElementType(); 4084 4085 // Figure out if there is a Packed type corresponding to this Vector 4086 // type. If so, convert to the vector type. 4087 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy),NumElems); 4088 if (TVT != MVT::Other && isTypeLegal(TVT)) { 4089 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a 4090 // "N x PTyElementVT" MVT::Vector type. 4091 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal, 4092 DAG.getConstant(NumElems, MVT::i32), 4093 DAG.getValueType(getValueType(EltTy))); 4094 } else { 4095 abort(); 4096 } 4097 } else if (MVT::isInteger(VT)) { 4098 unsigned AssertOp = ISD::AssertSext; 4099 if (!RetTyIsSigned) 4100 AssertOp = ISD::AssertZext; 4101 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal, 4102 DAG.getValueType(VT)); 4103 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal); 4104 } else { 4105 assert(MVT::isFloatingPoint(VT)); 4106 if (getTypeAction(VT) == Expand) 4107 ResVal = DAG.getNode(ISD::BIT_CONVERT, VT, ResVal); 4108 else 4109 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal); 4110 } 4111 } 4112 } else if (RetTys.size() == 3) { 4113 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT, 4114 Res.getValue(0), Res.getValue(1)); 4115 4116 } else { 4117 assert(0 && "Case not handled yet!"); 4118 } 4119 } 4120 4121 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1)); 4122} 4123 4124SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4125 assert(0 && "LowerOperation not implemented for this target!"); 4126 abort(); 4127 return SDOperand(); 4128} 4129 4130SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 4131 SelectionDAG &DAG) { 4132 assert(0 && "CustomPromoteOperation not implemented for this target!"); 4133 abort(); 4134 return SDOperand(); 4135} 4136 4137/// getMemsetValue - Vectorized representation of the memset value 4138/// operand. 4139static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 4140 SelectionDAG &DAG) { 4141 MVT::ValueType CurVT = VT; 4142 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 4143 uint64_t Val = C->getValue() & 255; 4144 unsigned Shift = 8; 4145 while (CurVT != MVT::i8) { 4146 Val = (Val << Shift) | Val; 4147 Shift <<= 1; 4148 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4149 } 4150 return DAG.getConstant(Val, VT); 4151 } else { 4152 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4153 unsigned Shift = 8; 4154 while (CurVT != MVT::i8) { 4155 Value = 4156 DAG.getNode(ISD::OR, VT, 4157 DAG.getNode(ISD::SHL, VT, Value, 4158 DAG.getConstant(Shift, MVT::i8)), Value); 4159 Shift <<= 1; 4160 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4161 } 4162 4163 return Value; 4164 } 4165} 4166 4167/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4168/// used when a memcpy is turned into a memset when the source is a constant 4169/// string ptr. 4170static SDOperand getMemsetStringVal(MVT::ValueType VT, 4171 SelectionDAG &DAG, TargetLowering &TLI, 4172 std::string &Str, unsigned Offset) { 4173 uint64_t Val = 0; 4174 unsigned MSB = getSizeInBits(VT) / 8; 4175 if (TLI.isLittleEndian()) 4176 Offset = Offset + MSB - 1; 4177 for (unsigned i = 0; i != MSB; ++i) { 4178 Val = (Val << 8) | (unsigned char)Str[Offset]; 4179 Offset += TLI.isLittleEndian() ? -1 : 1; 4180 } 4181 return DAG.getConstant(Val, VT); 4182} 4183 4184/// getMemBasePlusOffset - Returns base and offset node for the 4185static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4186 SelectionDAG &DAG, TargetLowering &TLI) { 4187 MVT::ValueType VT = Base.getValueType(); 4188 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4189} 4190 4191/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4192/// to replace the memset / memcpy is below the threshold. It also returns the 4193/// types of the sequence of memory ops to perform memset / memcpy. 4194static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4195 unsigned Limit, uint64_t Size, 4196 unsigned Align, TargetLowering &TLI) { 4197 MVT::ValueType VT; 4198 4199 if (TLI.allowsUnalignedMemoryAccesses()) { 4200 VT = MVT::i64; 4201 } else { 4202 switch (Align & 7) { 4203 case 0: 4204 VT = MVT::i64; 4205 break; 4206 case 4: 4207 VT = MVT::i32; 4208 break; 4209 case 2: 4210 VT = MVT::i16; 4211 break; 4212 default: 4213 VT = MVT::i8; 4214 break; 4215 } 4216 } 4217 4218 MVT::ValueType LVT = MVT::i64; 4219 while (!TLI.isTypeLegal(LVT)) 4220 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4221 assert(MVT::isInteger(LVT)); 4222 4223 if (VT > LVT) 4224 VT = LVT; 4225 4226 unsigned NumMemOps = 0; 4227 while (Size != 0) { 4228 unsigned VTSize = getSizeInBits(VT) / 8; 4229 while (VTSize > Size) { 4230 VT = (MVT::ValueType)((unsigned)VT - 1); 4231 VTSize >>= 1; 4232 } 4233 assert(MVT::isInteger(VT)); 4234 4235 if (++NumMemOps > Limit) 4236 return false; 4237 MemOps.push_back(VT); 4238 Size -= VTSize; 4239 } 4240 4241 return true; 4242} 4243 4244void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4245 SDOperand Op1 = getValue(I.getOperand(1)); 4246 SDOperand Op2 = getValue(I.getOperand(2)); 4247 SDOperand Op3 = getValue(I.getOperand(3)); 4248 SDOperand Op4 = getValue(I.getOperand(4)); 4249 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4250 if (Align == 0) Align = 1; 4251 4252 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4253 std::vector<MVT::ValueType> MemOps; 4254 4255 // Expand memset / memcpy to a series of load / store ops 4256 // if the size operand falls below a certain threshold. 4257 SmallVector<SDOperand, 8> OutChains; 4258 switch (Op) { 4259 default: break; // Do nothing for now. 4260 case ISD::MEMSET: { 4261 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4262 Size->getValue(), Align, TLI)) { 4263 unsigned NumMemOps = MemOps.size(); 4264 unsigned Offset = 0; 4265 for (unsigned i = 0; i < NumMemOps; i++) { 4266 MVT::ValueType VT = MemOps[i]; 4267 unsigned VTSize = getSizeInBits(VT) / 8; 4268 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4269 SDOperand Store = DAG.getStore(getRoot(), Value, 4270 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4271 I.getOperand(1), Offset); 4272 OutChains.push_back(Store); 4273 Offset += VTSize; 4274 } 4275 } 4276 break; 4277 } 4278 case ISD::MEMCPY: { 4279 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4280 Size->getValue(), Align, TLI)) { 4281 unsigned NumMemOps = MemOps.size(); 4282 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4283 GlobalAddressSDNode *G = NULL; 4284 std::string Str; 4285 bool CopyFromStr = false; 4286 4287 if (Op2.getOpcode() == ISD::GlobalAddress) 4288 G = cast<GlobalAddressSDNode>(Op2); 4289 else if (Op2.getOpcode() == ISD::ADD && 4290 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4291 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4292 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4293 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4294 } 4295 if (G) { 4296 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4297 if (GV && GV->isConstant()) { 4298 Str = GV->getStringValue(false); 4299 if (!Str.empty()) { 4300 CopyFromStr = true; 4301 SrcOff += SrcDelta; 4302 } 4303 } 4304 } 4305 4306 for (unsigned i = 0; i < NumMemOps; i++) { 4307 MVT::ValueType VT = MemOps[i]; 4308 unsigned VTSize = getSizeInBits(VT) / 8; 4309 SDOperand Value, Chain, Store; 4310 4311 if (CopyFromStr) { 4312 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4313 Chain = getRoot(); 4314 Store = 4315 DAG.getStore(Chain, Value, 4316 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4317 I.getOperand(1), DstOff); 4318 } else { 4319 Value = DAG.getLoad(VT, getRoot(), 4320 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4321 I.getOperand(2), SrcOff); 4322 Chain = Value.getValue(1); 4323 Store = 4324 DAG.getStore(Chain, Value, 4325 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4326 I.getOperand(1), DstOff); 4327 } 4328 OutChains.push_back(Store); 4329 SrcOff += VTSize; 4330 DstOff += VTSize; 4331 } 4332 } 4333 break; 4334 } 4335 } 4336 4337 if (!OutChains.empty()) { 4338 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4339 &OutChains[0], OutChains.size())); 4340 return; 4341 } 4342 } 4343 4344 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4)); 4345} 4346 4347//===----------------------------------------------------------------------===// 4348// SelectionDAGISel code 4349//===----------------------------------------------------------------------===// 4350 4351unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4352 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 4353} 4354 4355void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4356 AU.addRequired<AliasAnalysis>(); 4357 AU.setPreservesAll(); 4358} 4359 4360 4361 4362bool SelectionDAGISel::runOnFunction(Function &Fn) { 4363 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4364 RegMap = MF.getSSARegMap(); 4365 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4366 4367 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4368 4369 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4370 SelectBasicBlock(I, MF, FuncInfo); 4371 4372 // Add function live-ins to entry block live-in set. 4373 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4374 BB = FuncInfo.MBBMap[EntryBB]; 4375 if (!MF.livein_empty()) 4376 for (MachineFunction::livein_iterator I = MF.livein_begin(), 4377 E = MF.livein_end(); I != E; ++I) 4378 BB->addLiveIn(I->first); 4379 4380 return true; 4381} 4382 4383SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4384 unsigned Reg) { 4385 SDOperand Op = getValue(V); 4386 assert((Op.getOpcode() != ISD::CopyFromReg || 4387 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4388 "Copy from a reg to the same reg!"); 4389 4390 // If this type is not legal, we must make sure to not create an invalid 4391 // register use. 4392 MVT::ValueType SrcVT = Op.getValueType(); 4393 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT); 4394 if (SrcVT == DestVT) { 4395 return DAG.getCopyToReg(getRoot(), Reg, Op); 4396 } else if (SrcVT == MVT::Vector) { 4397 // Handle copies from generic vectors to registers. 4398 MVT::ValueType PTyElementVT, PTyLegalElementVT; 4399 unsigned NE = TLI.getVectorTypeBreakdown(cast<VectorType>(V->getType()), 4400 PTyElementVT, PTyLegalElementVT); 4401 4402 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT" 4403 // MVT::Vector type. 4404 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op, 4405 DAG.getConstant(NE, MVT::i32), 4406 DAG.getValueType(PTyElementVT)); 4407 4408 // Loop over all of the elements of the resultant vector, 4409 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then 4410 // copying them into output registers. 4411 SmallVector<SDOperand, 8> OutChains; 4412 SDOperand Root = getRoot(); 4413 for (unsigned i = 0; i != NE; ++i) { 4414 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT, 4415 Op, DAG.getConstant(i, TLI.getPointerTy())); 4416 if (PTyElementVT == PTyLegalElementVT) { 4417 // Elements are legal. 4418 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); 4419 } else if (PTyLegalElementVT > PTyElementVT) { 4420 // Elements are promoted. 4421 if (MVT::isFloatingPoint(PTyLegalElementVT)) 4422 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt); 4423 else 4424 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt); 4425 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); 4426 } else { 4427 // Elements are expanded. 4428 // The src value is expanded into multiple registers. 4429 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, 4430 Elt, DAG.getConstant(0, TLI.getPointerTy())); 4431 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, 4432 Elt, DAG.getConstant(1, TLI.getPointerTy())); 4433 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo)); 4434 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi)); 4435 } 4436 } 4437 return DAG.getNode(ISD::TokenFactor, MVT::Other, 4438 &OutChains[0], OutChains.size()); 4439 } else if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) { 4440 // The src value is promoted to the register. 4441 if (MVT::isFloatingPoint(SrcVT)) 4442 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op); 4443 else 4444 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op); 4445 return DAG.getCopyToReg(getRoot(), Reg, Op); 4446 } else { 4447 DestVT = TLI.getTypeToExpandTo(SrcVT); 4448 unsigned NumVals = TLI.getNumElements(SrcVT); 4449 if (NumVals == 1) 4450 return DAG.getCopyToReg(getRoot(), Reg, 4451 DAG.getNode(ISD::BIT_CONVERT, DestVT, Op)); 4452 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!"); 4453 // The src value is expanded into multiple registers. 4454 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 4455 Op, DAG.getConstant(0, TLI.getPointerTy())); 4456 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 4457 Op, DAG.getConstant(1, TLI.getPointerTy())); 4458 Op = DAG.getCopyToReg(getRoot(), Reg, Lo); 4459 return DAG.getCopyToReg(Op, Reg+1, Hi); 4460 } 4461} 4462 4463void SelectionDAGISel:: 4464LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4465 std::vector<SDOperand> &UnorderedChains) { 4466 // If this is the entry block, emit arguments. 4467 Function &F = *LLVMBB->getParent(); 4468 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4469 SDOperand OldRoot = SDL.DAG.getRoot(); 4470 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4471 4472 unsigned a = 0; 4473 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4474 AI != E; ++AI, ++a) 4475 if (!AI->use_empty()) { 4476 SDL.setValue(AI, Args[a]); 4477 4478 // If this argument is live outside of the entry block, insert a copy from 4479 // whereever we got it to the vreg that other BB's will reference it as. 4480 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4481 if (VMI != FuncInfo.ValueMap.end()) { 4482 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4483 UnorderedChains.push_back(Copy); 4484 } 4485 } 4486 4487 // Finally, if the target has anything special to do, allow it to do so. 4488 // FIXME: this should insert code into the DAG! 4489 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4490} 4491 4492void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4493 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4494 FunctionLoweringInfo &FuncInfo) { 4495 SelectionDAGLowering SDL(DAG, TLI, FuncInfo); 4496 4497 std::vector<SDOperand> UnorderedChains; 4498 4499 // Lower any arguments needed in this block if this is the entry block. 4500 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4501 LowerArguments(LLVMBB, SDL, UnorderedChains); 4502 4503 BB = FuncInfo.MBBMap[LLVMBB]; 4504 SDL.setCurrentBasicBlock(BB); 4505 4506 // Lower all of the non-terminator instructions. 4507 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4508 I != E; ++I) 4509 SDL.visit(*I); 4510 4511 // Lower call part of invoke. 4512 InvokeInst *Invoke = dyn_cast<InvokeInst>(LLVMBB->getTerminator()); 4513 if (Invoke) SDL.visitInvoke(*Invoke, false); 4514 4515 // Ensure that all instructions which are used outside of their defining 4516 // blocks are available as virtual registers. 4517 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4518 if (!I->use_empty() && !isa<PHINode>(I)) { 4519 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4520 if (VMI != FuncInfo.ValueMap.end()) 4521 UnorderedChains.push_back( 4522 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4523 } 4524 4525 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4526 // ensure constants are generated when needed. Remember the virtual registers 4527 // that need to be added to the Machine PHI nodes as input. We cannot just 4528 // directly add them, because expansion might result in multiple MBB's for one 4529 // BB. As such, the start of the BB might correspond to a different MBB than 4530 // the end. 4531 // 4532 TerminatorInst *TI = LLVMBB->getTerminator(); 4533 4534 // Emit constants only once even if used by multiple PHI nodes. 4535 std::map<Constant*, unsigned> ConstantsOut; 4536 4537 // Vector bool would be better, but vector<bool> is really slow. 4538 std::vector<unsigned char> SuccsHandled; 4539 if (TI->getNumSuccessors()) 4540 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4541 4542 // Check successor nodes PHI nodes that expect a constant to be available from 4543 // this block. 4544 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4545 BasicBlock *SuccBB = TI->getSuccessor(succ); 4546 if (!isa<PHINode>(SuccBB->begin())) continue; 4547 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4548 4549 // If this terminator has multiple identical successors (common for 4550 // switches), only handle each succ once. 4551 unsigned SuccMBBNo = SuccMBB->getNumber(); 4552 if (SuccsHandled[SuccMBBNo]) continue; 4553 SuccsHandled[SuccMBBNo] = true; 4554 4555 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4556 PHINode *PN; 4557 4558 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4559 // nodes and Machine PHI nodes, but the incoming operands have not been 4560 // emitted yet. 4561 for (BasicBlock::iterator I = SuccBB->begin(); 4562 (PN = dyn_cast<PHINode>(I)); ++I) { 4563 // Ignore dead phi's. 4564 if (PN->use_empty()) continue; 4565 4566 unsigned Reg; 4567 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4568 4569 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4570 unsigned &RegOut = ConstantsOut[C]; 4571 if (RegOut == 0) { 4572 RegOut = FuncInfo.CreateRegForValue(C); 4573 UnorderedChains.push_back( 4574 SDL.CopyValueToVirtualRegister(C, RegOut)); 4575 } 4576 Reg = RegOut; 4577 } else { 4578 Reg = FuncInfo.ValueMap[PHIOp]; 4579 if (Reg == 0) { 4580 assert(isa<AllocaInst>(PHIOp) && 4581 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4582 "Didn't codegen value into a register!??"); 4583 Reg = FuncInfo.CreateRegForValue(PHIOp); 4584 UnorderedChains.push_back( 4585 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4586 } 4587 } 4588 4589 // Remember that this register needs to added to the machine PHI node as 4590 // the input for this MBB. 4591 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4592 unsigned NumElements; 4593 if (VT != MVT::Vector) 4594 NumElements = TLI.getNumElements(VT); 4595 else { 4596 MVT::ValueType VT1,VT2; 4597 NumElements = 4598 TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()), 4599 VT1, VT2); 4600 } 4601 for (unsigned i = 0, e = NumElements; i != e; ++i) 4602 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4603 } 4604 } 4605 ConstantsOut.clear(); 4606 4607 // Turn all of the unordered chains into one factored node. 4608 if (!UnorderedChains.empty()) { 4609 SDOperand Root = SDL.getRoot(); 4610 if (Root.getOpcode() != ISD::EntryToken) { 4611 unsigned i = 0, e = UnorderedChains.size(); 4612 for (; i != e; ++i) { 4613 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4614 if (UnorderedChains[i].Val->getOperand(0) == Root) 4615 break; // Don't add the root if we already indirectly depend on it. 4616 } 4617 4618 if (i == e) 4619 UnorderedChains.push_back(Root); 4620 } 4621 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4622 &UnorderedChains[0], UnorderedChains.size())); 4623 } 4624 4625 // Lower the terminator after the copies are emitted. 4626 if (Invoke) { 4627 // Just the branch part of invoke. 4628 SDL.visitInvoke(*Invoke, true); 4629 } else { 4630 SDL.visit(*LLVMBB->getTerminator()); 4631 } 4632 4633 // Copy over any CaseBlock records that may now exist due to SwitchInst 4634 // lowering, as well as any jump table information. 4635 SwitchCases.clear(); 4636 SwitchCases = SDL.SwitchCases; 4637 JTCases.clear(); 4638 JTCases = SDL.JTCases; 4639 BitTestCases.clear(); 4640 BitTestCases = SDL.BitTestCases; 4641 4642 // Make sure the root of the DAG is up-to-date. 4643 DAG.setRoot(SDL.getRoot()); 4644} 4645 4646void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4647 // Get alias analysis for load/store combining. 4648 AliasAnalysis &AA = getAnalysis<AliasAnalysis>(); 4649 4650 // Run the DAG combiner in pre-legalize mode. 4651 DAG.Combine(false, AA); 4652 4653 DOUT << "Lowered selection DAG:\n"; 4654 DEBUG(DAG.dump()); 4655 4656 // Second step, hack on the DAG until it only uses operations and types that 4657 // the target supports. 4658 DAG.Legalize(); 4659 4660 DOUT << "Legalized selection DAG:\n"; 4661 DEBUG(DAG.dump()); 4662 4663 // Run the DAG combiner in post-legalize mode. 4664 DAG.Combine(true, AA); 4665 4666 if (ViewISelDAGs) DAG.viewGraph(); 4667 4668 // Third, instruction select all of the operations to machine code, adding the 4669 // code to the MachineBasicBlock. 4670 InstructionSelectBasicBlock(DAG); 4671 4672 DOUT << "Selected machine code:\n"; 4673 DEBUG(BB->dump()); 4674} 4675 4676void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4677 FunctionLoweringInfo &FuncInfo) { 4678 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4679 { 4680 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4681 CurDAG = &DAG; 4682 4683 // First step, lower LLVM code to some DAG. This DAG may use operations and 4684 // types that are not supported by the target. 4685 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4686 4687 // Second step, emit the lowered DAG as machine code. 4688 CodeGenAndEmitDAG(DAG); 4689 } 4690 4691 DOUT << "Total amount of phi nodes to update: " 4692 << PHINodesToUpdate.size() << "\n"; 4693 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4694 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4695 << ", " << PHINodesToUpdate[i].second << ")\n";); 4696 4697 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4698 // PHI nodes in successors. 4699 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4700 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4701 MachineInstr *PHI = PHINodesToUpdate[i].first; 4702 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4703 "This is not a machine PHI node that we are updating!"); 4704 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4705 PHI->addMachineBasicBlockOperand(BB); 4706 } 4707 return; 4708 } 4709 4710 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4711 // Lower header first, if it wasn't already lowered 4712 if (!BitTestCases[i].Emitted) { 4713 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4714 CurDAG = &HSDAG; 4715 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo); 4716 // Set the current basic block to the mbb we wish to insert the code into 4717 BB = BitTestCases[i].Parent; 4718 HSDL.setCurrentBasicBlock(BB); 4719 // Emit the code 4720 HSDL.visitBitTestHeader(BitTestCases[i]); 4721 HSDAG.setRoot(HSDL.getRoot()); 4722 CodeGenAndEmitDAG(HSDAG); 4723 } 4724 4725 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4726 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4727 CurDAG = &BSDAG; 4728 SelectionDAGLowering BSDL(BSDAG, TLI, FuncInfo); 4729 // Set the current basic block to the mbb we wish to insert the code into 4730 BB = BitTestCases[i].Cases[j].ThisBB; 4731 BSDL.setCurrentBasicBlock(BB); 4732 // Emit the code 4733 if (j+1 != ej) 4734 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 4735 BitTestCases[i].Reg, 4736 BitTestCases[i].Cases[j]); 4737 else 4738 BSDL.visitBitTestCase(BitTestCases[i].Default, 4739 BitTestCases[i].Reg, 4740 BitTestCases[i].Cases[j]); 4741 4742 4743 BSDAG.setRoot(BSDL.getRoot()); 4744 CodeGenAndEmitDAG(BSDAG); 4745 } 4746 4747 // Update PHI Nodes 4748 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4749 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4750 MachineBasicBlock *PHIBB = PHI->getParent(); 4751 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4752 "This is not a machine PHI node that we are updating!"); 4753 // This is "default" BB. We have two jumps to it. From "header" BB and 4754 // from last "case" BB. 4755 if (PHIBB == BitTestCases[i].Default) { 4756 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4757 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent); 4758 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4759 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB); 4760 } 4761 // One of "cases" BB. 4762 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4763 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 4764 if (cBB->succ_end() != 4765 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 4766 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4767 PHI->addMachineBasicBlockOperand(cBB); 4768 } 4769 } 4770 } 4771 } 4772 4773 // If the JumpTable record is filled in, then we need to emit a jump table. 4774 // Updating the PHI nodes is tricky in this case, since we need to determine 4775 // whether the PHI is a successor of the range check MBB or the jump table MBB 4776 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 4777 // Lower header first, if it wasn't already lowered 4778 if (!JTCases[i].first.Emitted) { 4779 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4780 CurDAG = &HSDAG; 4781 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo); 4782 // Set the current basic block to the mbb we wish to insert the code into 4783 BB = JTCases[i].first.HeaderBB; 4784 HSDL.setCurrentBasicBlock(BB); 4785 // Emit the code 4786 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 4787 HSDAG.setRoot(HSDL.getRoot()); 4788 CodeGenAndEmitDAG(HSDAG); 4789 } 4790 4791 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4792 CurDAG = &JSDAG; 4793 SelectionDAGLowering JSDL(JSDAG, TLI, FuncInfo); 4794 // Set the current basic block to the mbb we wish to insert the code into 4795 BB = JTCases[i].second.MBB; 4796 JSDL.setCurrentBasicBlock(BB); 4797 // Emit the code 4798 JSDL.visitJumpTable(JTCases[i].second); 4799 JSDAG.setRoot(JSDL.getRoot()); 4800 CodeGenAndEmitDAG(JSDAG); 4801 4802 // Update PHI Nodes 4803 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4804 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4805 MachineBasicBlock *PHIBB = PHI->getParent(); 4806 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4807 "This is not a machine PHI node that we are updating!"); 4808 // "default" BB. We can go there only from header BB. 4809 if (PHIBB == JTCases[i].second.Default) { 4810 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4811 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB); 4812 } 4813 // JT BB. Just iterate over successors here 4814 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 4815 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4816 PHI->addMachineBasicBlockOperand(BB); 4817 } 4818 } 4819 } 4820 4821 // If the switch block involved a branch to one of the actual successors, we 4822 // need to update PHI nodes in that block. 4823 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4824 MachineInstr *PHI = PHINodesToUpdate[i].first; 4825 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4826 "This is not a machine PHI node that we are updating!"); 4827 if (BB->isSuccessor(PHI->getParent())) { 4828 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4829 PHI->addMachineBasicBlockOperand(BB); 4830 } 4831 } 4832 4833 // If we generated any switch lowering information, build and codegen any 4834 // additional DAGs necessary. 4835 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 4836 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4837 CurDAG = &SDAG; 4838 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 4839 4840 // Set the current basic block to the mbb we wish to insert the code into 4841 BB = SwitchCases[i].ThisBB; 4842 SDL.setCurrentBasicBlock(BB); 4843 4844 // Emit the code 4845 SDL.visitSwitchCase(SwitchCases[i]); 4846 SDAG.setRoot(SDL.getRoot()); 4847 CodeGenAndEmitDAG(SDAG); 4848 4849 // Handle any PHI nodes in successors of this chunk, as if we were coming 4850 // from the original BB before switch expansion. Note that PHI nodes can 4851 // occur multiple times in PHINodesToUpdate. We have to be very careful to 4852 // handle them the right number of times. 4853 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 4854 for (MachineBasicBlock::iterator Phi = BB->begin(); 4855 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 4856 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 4857 for (unsigned pn = 0; ; ++pn) { 4858 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 4859 if (PHINodesToUpdate[pn].first == Phi) { 4860 Phi->addRegOperand(PHINodesToUpdate[pn].second, false); 4861 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB); 4862 break; 4863 } 4864 } 4865 } 4866 4867 // Don't process RHS if same block as LHS. 4868 if (BB == SwitchCases[i].FalseBB) 4869 SwitchCases[i].FalseBB = 0; 4870 4871 // If we haven't handled the RHS, do so now. Otherwise, we're done. 4872 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 4873 SwitchCases[i].FalseBB = 0; 4874 } 4875 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 4876 } 4877} 4878 4879 4880//===----------------------------------------------------------------------===// 4881/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 4882/// target node in the graph. 4883void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 4884 if (ViewSchedDAGs) DAG.viewGraph(); 4885 4886 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 4887 4888 if (!Ctor) { 4889 Ctor = ISHeuristic; 4890 RegisterScheduler::setDefault(Ctor); 4891 } 4892 4893 ScheduleDAG *SL = Ctor(this, &DAG, BB); 4894 BB = SL->Run(); 4895 delete SL; 4896} 4897 4898 4899HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 4900 return new HazardRecognizer(); 4901} 4902 4903//===----------------------------------------------------------------------===// 4904// Helper functions used by the generated instruction selector. 4905//===----------------------------------------------------------------------===// 4906// Calls to these methods are generated by tblgen. 4907 4908/// CheckAndMask - The isel is trying to match something like (and X, 255). If 4909/// the dag combiner simplified the 255, we still want to match. RHS is the 4910/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 4911/// specified in the .td file (e.g. 255). 4912bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 4913 int64_t DesiredMaskS) { 4914 uint64_t ActualMask = RHS->getValue(); 4915 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4916 4917 // If the actual mask exactly matches, success! 4918 if (ActualMask == DesiredMask) 4919 return true; 4920 4921 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4922 if (ActualMask & ~DesiredMask) 4923 return false; 4924 4925 // Otherwise, the DAG Combiner may have proven that the value coming in is 4926 // either already zero or is not demanded. Check for known zero input bits. 4927 uint64_t NeededMask = DesiredMask & ~ActualMask; 4928 if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask)) 4929 return true; 4930 4931 // TODO: check to see if missing bits are just not demanded. 4932 4933 // Otherwise, this pattern doesn't match. 4934 return false; 4935} 4936 4937/// CheckOrMask - The isel is trying to match something like (or X, 255). If 4938/// the dag combiner simplified the 255, we still want to match. RHS is the 4939/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 4940/// specified in the .td file (e.g. 255). 4941bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 4942 int64_t DesiredMaskS) { 4943 uint64_t ActualMask = RHS->getValue(); 4944 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4945 4946 // If the actual mask exactly matches, success! 4947 if (ActualMask == DesiredMask) 4948 return true; 4949 4950 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4951 if (ActualMask & ~DesiredMask) 4952 return false; 4953 4954 // Otherwise, the DAG Combiner may have proven that the value coming in is 4955 // either already zero or is not demanded. Check for known zero input bits. 4956 uint64_t NeededMask = DesiredMask & ~ActualMask; 4957 4958 uint64_t KnownZero, KnownOne; 4959 getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 4960 4961 // If all the missing bits in the or are already known to be set, match! 4962 if ((NeededMask & KnownOne) == NeededMask) 4963 return true; 4964 4965 // TODO: check to see if missing bits are just not demanded. 4966 4967 // Otherwise, this pattern doesn't match. 4968 return false; 4969} 4970 4971 4972/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 4973/// by tblgen. Others should not call it. 4974void SelectionDAGISel:: 4975SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 4976 std::vector<SDOperand> InOps; 4977 std::swap(InOps, Ops); 4978 4979 Ops.push_back(InOps[0]); // input chain. 4980 Ops.push_back(InOps[1]); // input asm string. 4981 4982 unsigned i = 2, e = InOps.size(); 4983 if (InOps[e-1].getValueType() == MVT::Flag) 4984 --e; // Don't process a flag operand if it is here. 4985 4986 while (i != e) { 4987 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 4988 if ((Flags & 7) != 4 /*MEM*/) { 4989 // Just skip over this operand, copying the operands verbatim. 4990 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 4991 i += (Flags >> 3) + 1; 4992 } else { 4993 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 4994 // Otherwise, this is a memory operand. Ask the target to select it. 4995 std::vector<SDOperand> SelOps; 4996 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 4997 cerr << "Could not match memory address. Inline asm failure!\n"; 4998 exit(1); 4999 } 5000 5001 // Add this to the output node. 5002 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 5003 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 5004 IntPtrTy)); 5005 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 5006 i += 2; 5007 } 5008 } 5009 5010 // Add the flag input back if present. 5011 if (e != InOps.size()) 5012 Ops.push_back(InOps.back()); 5013} 5014 5015const char SelectionDAGISel::ID = 0; 5016