SelectionDAGISel.cpp revision 6ddf8ed6fe2d0aa5e15f7b9ad7e5049e2223bbd1
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "llvm/CodeGen/ScheduleDAG.h" 17#include "llvm/CallingConv.h" 18#include "llvm/Constants.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Function.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/InlineAsm.h" 23#include "llvm/Instructions.h" 24#include "llvm/Intrinsics.h" 25#include "llvm/IntrinsicInst.h" 26#include "llvm/CodeGen/IntrinsicLowering.h" 27#include "llvm/CodeGen/MachineDebugInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineJumpTableInfo.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/SchedulerRegistry.h" 33#include "llvm/CodeGen/SelectionDAG.h" 34#include "llvm/CodeGen/SSARegMap.h" 35#include "llvm/Target/MRegisterInfo.h" 36#include "llvm/Target/TargetData.h" 37#include "llvm/Target/TargetFrameInfo.h" 38#include "llvm/Target/TargetInstrInfo.h" 39#include "llvm/Target/TargetLowering.h" 40#include "llvm/Target/TargetMachine.h" 41#include "llvm/Target/TargetOptions.h" 42#include "llvm/Transforms/Utils/BasicBlockUtils.h" 43#include "llvm/Support/MathExtras.h" 44#include "llvm/Support/Debug.h" 45#include "llvm/Support/Compiler.h" 46#include <map> 47#include <set> 48#include <iostream> 49#include <algorithm> 50using namespace llvm; 51 52#ifndef NDEBUG 53static cl::opt<bool> 54ViewISelDAGs("view-isel-dags", cl::Hidden, 55 cl::desc("Pop up a window to show isel dags as they are selected")); 56static cl::opt<bool> 57ViewSchedDAGs("view-sched-dags", cl::Hidden, 58 cl::desc("Pop up a window to show sched dags as they are processed")); 59#else 60static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0; 61#endif 62 63 64//===---------------------------------------------------------------------===// 65/// 66/// RegisterScheduler class - Track the registration of instruction schedulers. 67/// 68//===---------------------------------------------------------------------===// 69MachinePassRegistry RegisterScheduler::Registry; 70 71//===---------------------------------------------------------------------===// 72/// 73/// ISHeuristic command line option for instruction schedulers. 74/// 75//===---------------------------------------------------------------------===// 76namespace { 77 cl::opt<RegisterScheduler::FunctionPassCtor, false, 78 RegisterPassParser<RegisterScheduler> > 79 ISHeuristic("sched", 80 cl::init(&createDefaultScheduler), 81 cl::desc("Instruction schedulers available:")); 82 83 static RegisterScheduler 84 defaultListDAGScheduler("default", " Best scheduler for the target", 85 createDefaultScheduler); 86} // namespace 87 88namespace { 89 /// RegsForValue - This struct represents the physical registers that a 90 /// particular value is assigned and the type information about the value. 91 /// This is needed because values can be promoted into larger registers and 92 /// expanded into multiple smaller registers than the value. 93 struct VISIBILITY_HIDDEN RegsForValue { 94 /// Regs - This list hold the register (for legal and promoted values) 95 /// or register set (for expanded values) that the value should be assigned 96 /// to. 97 std::vector<unsigned> Regs; 98 99 /// RegVT - The value type of each register. 100 /// 101 MVT::ValueType RegVT; 102 103 /// ValueVT - The value type of the LLVM value, which may be promoted from 104 /// RegVT or made from merging the two expanded parts. 105 MVT::ValueType ValueVT; 106 107 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 108 109 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 110 : RegVT(regvt), ValueVT(valuevt) { 111 Regs.push_back(Reg); 112 } 113 RegsForValue(const std::vector<unsigned> ®s, 114 MVT::ValueType regvt, MVT::ValueType valuevt) 115 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 116 } 117 118 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 119 /// this value and returns the result as a ValueVT value. This uses 120 /// Chain/Flag as the input and updates them for the output Chain/Flag. 121 SDOperand getCopyFromRegs(SelectionDAG &DAG, 122 SDOperand &Chain, SDOperand &Flag) const; 123 124 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 125 /// specified value into the registers specified by this object. This uses 126 /// Chain/Flag as the input and updates them for the output Chain/Flag. 127 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 128 SDOperand &Chain, SDOperand &Flag, 129 MVT::ValueType PtrVT) const; 130 131 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 132 /// operand list. This adds the code marker and includes the number of 133 /// values added into it. 134 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 135 std::vector<SDOperand> &Ops) const; 136 }; 137} 138 139namespace llvm { 140 //===--------------------------------------------------------------------===// 141 /// createDefaultScheduler - This creates an instruction scheduler appropriate 142 /// for the target. 143 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 144 SelectionDAG *DAG, 145 MachineBasicBlock *BB) { 146 TargetLowering &TLI = IS->getTargetLowering(); 147 148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 149 return createTDListDAGScheduler(IS, DAG, BB); 150 } else { 151 assert(TLI.getSchedulingPreference() == 152 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 153 return createBURRListDAGScheduler(IS, DAG, BB); 154 } 155 } 156 157 158 //===--------------------------------------------------------------------===// 159 /// FunctionLoweringInfo - This contains information that is global to a 160 /// function that is used when lowering a region of the function. 161 class FunctionLoweringInfo { 162 public: 163 TargetLowering &TLI; 164 Function &Fn; 165 MachineFunction &MF; 166 SSARegMap *RegMap; 167 168 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 169 170 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 171 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 172 173 /// ValueMap - Since we emit code for the function a basic block at a time, 174 /// we must remember which virtual registers hold the values for 175 /// cross-basic-block values. 176 std::map<const Value*, unsigned> ValueMap; 177 178 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 179 /// the entry block. This allows the allocas to be efficiently referenced 180 /// anywhere in the function. 181 std::map<const AllocaInst*, int> StaticAllocaMap; 182 183 unsigned MakeReg(MVT::ValueType VT) { 184 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 185 } 186 187 unsigned CreateRegForValue(const Value *V); 188 189 unsigned InitializeRegForValue(const Value *V) { 190 unsigned &R = ValueMap[V]; 191 assert(R == 0 && "Already initialized this value register!"); 192 return R = CreateRegForValue(V); 193 } 194 }; 195} 196 197/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 198/// PHI nodes or outside of the basic block that defines it, or used by a 199/// switch instruction, which may expand to multiple basic blocks. 200static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 201 if (isa<PHINode>(I)) return true; 202 BasicBlock *BB = I->getParent(); 203 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 204 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 205 isa<SwitchInst>(*UI)) 206 return true; 207 return false; 208} 209 210/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 211/// entry block, return true. This includes arguments used by switches, since 212/// the switch may expand into multiple basic blocks. 213static bool isOnlyUsedInEntryBlock(Argument *A) { 214 BasicBlock *Entry = A->getParent()->begin(); 215 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 216 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 217 return false; // Use not in entry block. 218 return true; 219} 220 221FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 222 Function &fn, MachineFunction &mf) 223 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 224 225 // Create a vreg for each argument register that is not dead and is used 226 // outside of the entry block for the function. 227 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 228 AI != E; ++AI) 229 if (!isOnlyUsedInEntryBlock(AI)) 230 InitializeRegForValue(AI); 231 232 // Initialize the mapping of values to registers. This is only set up for 233 // instruction values that are used outside of the block that defines 234 // them. 235 Function::iterator BB = Fn.begin(), EB = Fn.end(); 236 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 237 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 238 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) { 239 const Type *Ty = AI->getAllocatedType(); 240 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 241 unsigned Align = 242 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty), 243 AI->getAlignment()); 244 245 // If the alignment of the value is smaller than the size of the value, 246 // and if the size of the value is particularly small (<= 8 bytes), 247 // round up to the size of the value for potentially better performance. 248 // 249 // FIXME: This could be made better with a preferred alignment hook in 250 // TargetData. It serves primarily to 8-byte align doubles for X86. 251 if (Align < TySize && TySize <= 8) Align = TySize; 252 TySize *= CUI->getValue(); // Get total allocated size. 253 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 254 StaticAllocaMap[AI] = 255 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 256 } 257 258 for (; BB != EB; ++BB) 259 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 260 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 261 if (!isa<AllocaInst>(I) || 262 !StaticAllocaMap.count(cast<AllocaInst>(I))) 263 InitializeRegForValue(I); 264 265 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 266 // also creates the initial PHI MachineInstrs, though none of the input 267 // operands are populated. 268 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 269 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 270 MBBMap[BB] = MBB; 271 MF.getBasicBlockList().push_back(MBB); 272 273 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 274 // appropriate. 275 PHINode *PN; 276 for (BasicBlock::iterator I = BB->begin(); 277 (PN = dyn_cast<PHINode>(I)); ++I) 278 if (!PN->use_empty()) { 279 MVT::ValueType VT = TLI.getValueType(PN->getType()); 280 unsigned NumElements; 281 if (VT != MVT::Vector) 282 NumElements = TLI.getNumElements(VT); 283 else { 284 MVT::ValueType VT1,VT2; 285 NumElements = 286 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()), 287 VT1, VT2); 288 } 289 unsigned PHIReg = ValueMap[PN]; 290 assert(PHIReg &&"PHI node does not have an assigned virtual register!"); 291 for (unsigned i = 0; i != NumElements; ++i) 292 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i); 293 } 294 } 295} 296 297/// CreateRegForValue - Allocate the appropriate number of virtual registers of 298/// the correctly promoted or expanded types. Assign these registers 299/// consecutive vreg numbers and return the first assigned number. 300unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 301 MVT::ValueType VT = TLI.getValueType(V->getType()); 302 303 // The number of multiples of registers that we need, to, e.g., split up 304 // a <2 x int64> -> 4 x i32 registers. 305 unsigned NumVectorRegs = 1; 306 307 // If this is a packed type, figure out what type it will decompose into 308 // and how many of the elements it will use. 309 if (VT == MVT::Vector) { 310 const PackedType *PTy = cast<PackedType>(V->getType()); 311 unsigned NumElts = PTy->getNumElements(); 312 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType()); 313 314 // Divide the input until we get to a supported size. This will always 315 // end with a scalar if the target doesn't support vectors. 316 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) { 317 NumElts >>= 1; 318 NumVectorRegs <<= 1; 319 } 320 if (NumElts == 1) 321 VT = EltTy; 322 else 323 VT = getVectorType(EltTy, NumElts); 324 } 325 326 // The common case is that we will only create one register for this 327 // value. If we have that case, create and return the virtual register. 328 unsigned NV = TLI.getNumElements(VT); 329 if (NV == 1) { 330 // If we are promoting this value, pick the next largest supported type. 331 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT); 332 unsigned Reg = MakeReg(PromotedType); 333 // If this is a vector of supported or promoted types (e.g. 4 x i16), 334 // create all of the registers. 335 for (unsigned i = 1; i != NumVectorRegs; ++i) 336 MakeReg(PromotedType); 337 return Reg; 338 } 339 340 // If this value is represented with multiple target registers, make sure 341 // to create enough consecutive registers of the right (smaller) type. 342 unsigned NT = VT-1; // Find the type to use. 343 while (TLI.getNumElements((MVT::ValueType)NT) != 1) 344 --NT; 345 346 unsigned R = MakeReg((MVT::ValueType)NT); 347 for (unsigned i = 1; i != NV*NumVectorRegs; ++i) 348 MakeReg((MVT::ValueType)NT); 349 return R; 350} 351 352//===----------------------------------------------------------------------===// 353/// SelectionDAGLowering - This is the common target-independent lowering 354/// implementation that is parameterized by a TargetLowering object. 355/// Also, targets can overload any lowering method. 356/// 357namespace llvm { 358class SelectionDAGLowering { 359 MachineBasicBlock *CurMBB; 360 361 std::map<const Value*, SDOperand> NodeMap; 362 363 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 364 /// them up and then emit token factor nodes when possible. This allows us to 365 /// get simple disambiguation between loads without worrying about alias 366 /// analysis. 367 std::vector<SDOperand> PendingLoads; 368 369 /// Case - A pair of values to record the Value for a switch case, and the 370 /// case's target basic block. 371 typedef std::pair<Constant*, MachineBasicBlock*> Case; 372 typedef std::vector<Case>::iterator CaseItr; 373 typedef std::pair<CaseItr, CaseItr> CaseRange; 374 375 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 376 /// of conditional branches. 377 struct CaseRec { 378 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 379 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 380 381 /// CaseBB - The MBB in which to emit the compare and branch 382 MachineBasicBlock *CaseBB; 383 /// LT, GE - If nonzero, we know the current case value must be less-than or 384 /// greater-than-or-equal-to these Constants. 385 Constant *LT; 386 Constant *GE; 387 /// Range - A pair of iterators representing the range of case values to be 388 /// processed at this point in the binary search tree. 389 CaseRange Range; 390 }; 391 392 /// The comparison function for sorting Case values. 393 struct CaseCmp { 394 bool operator () (const Case& C1, const Case& C2) { 395 if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first)) 396 return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue(); 397 398 const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first); 399 return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue(); 400 } 401 }; 402 403public: 404 // TLI - This is information that describes the available target features we 405 // need for lowering. This indicates when operations are unavailable, 406 // implemented with a libcall, etc. 407 TargetLowering &TLI; 408 SelectionDAG &DAG; 409 const TargetData *TD; 410 411 /// SwitchCases - Vector of CaseBlock structures used to communicate 412 /// SwitchInst code generation information. 413 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 414 SelectionDAGISel::JumpTable JT; 415 416 /// FuncInfo - Information about the function as a whole. 417 /// 418 FunctionLoweringInfo &FuncInfo; 419 420 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 421 FunctionLoweringInfo &funcinfo) 422 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), 423 JT(0,0,0,0), FuncInfo(funcinfo) { 424 } 425 426 /// getRoot - Return the current virtual root of the Selection DAG. 427 /// 428 SDOperand getRoot() { 429 if (PendingLoads.empty()) 430 return DAG.getRoot(); 431 432 if (PendingLoads.size() == 1) { 433 SDOperand Root = PendingLoads[0]; 434 DAG.setRoot(Root); 435 PendingLoads.clear(); 436 return Root; 437 } 438 439 // Otherwise, we have to make a token factor node. 440 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 441 &PendingLoads[0], PendingLoads.size()); 442 PendingLoads.clear(); 443 DAG.setRoot(Root); 444 return Root; 445 } 446 447 void visit(Instruction &I) { visit(I.getOpcode(), I); } 448 449 void visit(unsigned Opcode, User &I) { 450 switch (Opcode) { 451 default: assert(0 && "Unknown instruction type encountered!"); 452 abort(); 453 // Build the switch statement using the Instruction.def file. 454#define HANDLE_INST(NUM, OPCODE, CLASS) \ 455 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 456#include "llvm/Instruction.def" 457 } 458 } 459 460 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 461 462 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 463 SDOperand SrcValue, SDOperand Root, 464 bool isVolatile); 465 466 SDOperand getIntPtrConstant(uint64_t Val) { 467 return DAG.getConstant(Val, TLI.getPointerTy()); 468 } 469 470 SDOperand getValue(const Value *V); 471 472 const SDOperand &setValue(const Value *V, SDOperand NewN) { 473 SDOperand &N = NodeMap[V]; 474 assert(N.Val == 0 && "Already set a value for this node!"); 475 return N = NewN; 476 } 477 478 RegsForValue GetRegistersForValue(const std::string &ConstrCode, 479 MVT::ValueType VT, 480 bool OutReg, bool InReg, 481 std::set<unsigned> &OutputRegs, 482 std::set<unsigned> &InputRegs); 483 484 // Terminator instructions. 485 void visitRet(ReturnInst &I); 486 void visitBr(BranchInst &I); 487 void visitSwitch(SwitchInst &I); 488 void visitUnreachable(UnreachableInst &I) { /* noop */ } 489 490 // Helper for visitSwitch 491 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 492 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 493 494 // These all get lowered before this pass. 495 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); } 496 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); } 497 498 void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp); 499 void visitShift(User &I, unsigned Opcode); 500 void visitAdd(User &I) { 501 visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD); 502 } 503 void visitSub(User &I); 504 void visitMul(User &I) { 505 visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL); 506 } 507 void visitDiv(User &I) { 508 const Type *Ty = I.getType(); 509 visitBinary(I, 510 Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV, 511 Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV); 512 } 513 void visitRem(User &I) { 514 const Type *Ty = I.getType(); 515 visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0); 516 } 517 void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); } 518 void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); } 519 void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); } 520 void visitShl(User &I) { visitShift(I, ISD::SHL); } 521 void visitShr(User &I) { 522 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA); 523 } 524 525 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc, 526 ISD::CondCode FPOpc); 527 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ, 528 ISD::SETOEQ); } 529 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE, 530 ISD::SETUNE); } 531 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE, 532 ISD::SETOLE); } 533 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE, 534 ISD::SETOGE); } 535 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT, 536 ISD::SETOLT); } 537 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT, 538 ISD::SETOGT); } 539 540 void visitExtractElement(User &I); 541 void visitInsertElement(User &I); 542 void visitShuffleVector(User &I); 543 544 void visitGetElementPtr(User &I); 545 void visitCast(User &I); 546 void visitSelect(User &I); 547 548 void visitMalloc(MallocInst &I); 549 void visitFree(FreeInst &I); 550 void visitAlloca(AllocaInst &I); 551 void visitLoad(LoadInst &I); 552 void visitStore(StoreInst &I); 553 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 554 void visitCall(CallInst &I); 555 void visitInlineAsm(CallInst &I); 556 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 557 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 558 559 void visitVAStart(CallInst &I); 560 void visitVAArg(VAArgInst &I); 561 void visitVAEnd(CallInst &I); 562 void visitVACopy(CallInst &I); 563 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress); 564 565 void visitMemIntrinsic(CallInst &I, unsigned Op); 566 567 void visitUserOp1(Instruction &I) { 568 assert(0 && "UserOp1 should not exist at instruction selection time!"); 569 abort(); 570 } 571 void visitUserOp2(Instruction &I) { 572 assert(0 && "UserOp2 should not exist at instruction selection time!"); 573 abort(); 574 } 575}; 576} // end namespace llvm 577 578SDOperand SelectionDAGLowering::getValue(const Value *V) { 579 SDOperand &N = NodeMap[V]; 580 if (N.Val) return N; 581 582 const Type *VTy = V->getType(); 583 MVT::ValueType VT = TLI.getValueType(VTy); 584 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 585 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 586 visit(CE->getOpcode(), *CE); 587 assert(N.Val && "visit didn't populate the ValueMap!"); 588 return N; 589 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 590 return N = DAG.getGlobalAddress(GV, VT); 591 } else if (isa<ConstantPointerNull>(C)) { 592 return N = DAG.getConstant(0, TLI.getPointerTy()); 593 } else if (isa<UndefValue>(C)) { 594 if (!isa<PackedType>(VTy)) 595 return N = DAG.getNode(ISD::UNDEF, VT); 596 597 // Create a VBUILD_VECTOR of undef nodes. 598 const PackedType *PTy = cast<PackedType>(VTy); 599 unsigned NumElements = PTy->getNumElements(); 600 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 601 602 SmallVector<SDOperand, 8> Ops; 603 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 604 605 // Create a VConstant node with generic Vector type. 606 Ops.push_back(DAG.getConstant(NumElements, MVT::i32)); 607 Ops.push_back(DAG.getValueType(PVT)); 608 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 609 &Ops[0], Ops.size()); 610 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 611 return N = DAG.getConstantFP(CFP->getValue(), VT); 612 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) { 613 unsigned NumElements = PTy->getNumElements(); 614 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 615 616 // Now that we know the number and type of the elements, push a 617 // Constant or ConstantFP node onto the ops list for each element of 618 // the packed constant. 619 SmallVector<SDOperand, 8> Ops; 620 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) { 621 for (unsigned i = 0; i != NumElements; ++i) 622 Ops.push_back(getValue(CP->getOperand(i))); 623 } else { 624 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!"); 625 SDOperand Op; 626 if (MVT::isFloatingPoint(PVT)) 627 Op = DAG.getConstantFP(0, PVT); 628 else 629 Op = DAG.getConstant(0, PVT); 630 Ops.assign(NumElements, Op); 631 } 632 633 // Create a VBUILD_VECTOR node with generic Vector type. 634 Ops.push_back(DAG.getConstant(NumElements, MVT::i32)); 635 Ops.push_back(DAG.getValueType(PVT)); 636 return N = DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector,&Ops[0],Ops.size()); 637 } else { 638 // Canonicalize all constant ints to be unsigned. 639 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT); 640 } 641 } 642 643 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 644 std::map<const AllocaInst*, int>::iterator SI = 645 FuncInfo.StaticAllocaMap.find(AI); 646 if (SI != FuncInfo.StaticAllocaMap.end()) 647 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 648 } 649 650 std::map<const Value*, unsigned>::const_iterator VMI = 651 FuncInfo.ValueMap.find(V); 652 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!"); 653 654 unsigned InReg = VMI->second; 655 656 // If this type is not legal, make it so now. 657 if (VT != MVT::Vector) { 658 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT); 659 660 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); 661 if (DestVT < VT) { 662 // Source must be expanded. This input value is actually coming from the 663 // register pair VMI->second and VMI->second+1. 664 N = DAG.getNode(ISD::BUILD_PAIR, VT, N, 665 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT)); 666 } else if (DestVT > VT) { // Promotion case 667 if (MVT::isFloatingPoint(VT)) 668 N = DAG.getNode(ISD::FP_ROUND, VT, N); 669 else 670 N = DAG.getNode(ISD::TRUNCATE, VT, N); 671 } 672 } else { 673 // Otherwise, if this is a vector, make it available as a generic vector 674 // here. 675 MVT::ValueType PTyElementVT, PTyLegalElementVT; 676 const PackedType *PTy = cast<PackedType>(VTy); 677 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT, 678 PTyLegalElementVT); 679 680 // Build a VBUILD_VECTOR with the input registers. 681 SmallVector<SDOperand, 8> Ops; 682 if (PTyElementVT == PTyLegalElementVT) { 683 // If the value types are legal, just VBUILD the CopyFromReg nodes. 684 for (unsigned i = 0; i != NE; ++i) 685 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 686 PTyElementVT)); 687 } else if (PTyElementVT < PTyLegalElementVT) { 688 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate. 689 for (unsigned i = 0; i != NE; ++i) { 690 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 691 PTyElementVT); 692 if (MVT::isFloatingPoint(PTyElementVT)) 693 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op); 694 else 695 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op); 696 Ops.push_back(Op); 697 } 698 } else { 699 // If the register was expanded, use BUILD_PAIR. 700 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!"); 701 for (unsigned i = 0; i != NE/2; ++i) { 702 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 703 PTyElementVT); 704 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 705 PTyElementVT); 706 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1)); 707 } 708 } 709 710 Ops.push_back(DAG.getConstant(NE, MVT::i32)); 711 Ops.push_back(DAG.getValueType(PTyLegalElementVT)); 712 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 713 714 // Finally, use a VBIT_CONVERT to make this available as the appropriate 715 // vector type. 716 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, 717 DAG.getConstant(PTy->getNumElements(), 718 MVT::i32), 719 DAG.getValueType(TLI.getValueType(PTy->getElementType()))); 720 } 721 722 return N; 723} 724 725 726void SelectionDAGLowering::visitRet(ReturnInst &I) { 727 if (I.getNumOperands() == 0) { 728 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 729 return; 730 } 731 SmallVector<SDOperand, 8> NewValues; 732 NewValues.push_back(getRoot()); 733 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 734 SDOperand RetOp = getValue(I.getOperand(i)); 735 bool isSigned = I.getOperand(i)->getType()->isSigned(); 736 737 // If this is an integer return value, we need to promote it ourselves to 738 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather 739 // than sign/zero. 740 // FIXME: C calling convention requires the return type to be promoted to 741 // at least 32-bit. But this is not necessary for non-C calling conventions. 742 if (MVT::isInteger(RetOp.getValueType()) && 743 RetOp.getValueType() < MVT::i64) { 744 MVT::ValueType TmpVT; 745 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 746 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 747 else 748 TmpVT = MVT::i32; 749 750 if (isSigned) 751 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp); 752 else 753 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp); 754 } 755 NewValues.push_back(RetOp); 756 NewValues.push_back(DAG.getConstant(isSigned, MVT::i32)); 757 } 758 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 759 &NewValues[0], NewValues.size())); 760} 761 762void SelectionDAGLowering::visitBr(BranchInst &I) { 763 // Update machine-CFG edges. 764 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 765 CurMBB->addSuccessor(Succ0MBB); 766 767 // Figure out which block is immediately after the current one. 768 MachineBasicBlock *NextBlock = 0; 769 MachineFunction::iterator BBI = CurMBB; 770 if (++BBI != CurMBB->getParent()->end()) 771 NextBlock = BBI; 772 773 if (I.isUnconditional()) { 774 // If this is not a fall-through branch, emit the branch. 775 if (Succ0MBB != NextBlock) 776 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 777 DAG.getBasicBlock(Succ0MBB))); 778 } else { 779 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 780 CurMBB->addSuccessor(Succ1MBB); 781 782 SDOperand Cond = getValue(I.getCondition()); 783 if (Succ1MBB == NextBlock) { 784 // If the condition is false, fall through. This means we should branch 785 // if the condition is true to Succ #0. 786 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 787 Cond, DAG.getBasicBlock(Succ0MBB))); 788 } else if (Succ0MBB == NextBlock) { 789 // If the condition is true, fall through. This means we should branch if 790 // the condition is false to Succ #1. Invert the condition first. 791 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 792 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 793 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 794 Cond, DAG.getBasicBlock(Succ1MBB))); 795 } else { 796 std::vector<SDOperand> Ops; 797 Ops.push_back(getRoot()); 798 // If the false case is the current basic block, then this is a self 799 // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it 800 // adds an extra instruction in the loop. Instead, invert the 801 // condition and emit "Loop: ... br!cond Loop; br Out. 802 if (CurMBB == Succ1MBB) { 803 std::swap(Succ0MBB, Succ1MBB); 804 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 805 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 806 } 807 SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 808 DAG.getBasicBlock(Succ0MBB)); 809 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True, 810 DAG.getBasicBlock(Succ1MBB))); 811 } 812 } 813} 814 815/// visitSwitchCase - Emits the necessary code to represent a single node in 816/// the binary search tree resulting from lowering a switch instruction. 817void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 818 SDOperand SwitchOp = getValue(CB.SwitchV); 819 SDOperand CaseOp = getValue(CB.CaseC); 820 SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC); 821 822 // Set NextBlock to be the MBB immediately after the current one, if any. 823 // This is used to avoid emitting unnecessary branches to the next block. 824 MachineBasicBlock *NextBlock = 0; 825 MachineFunction::iterator BBI = CurMBB; 826 if (++BBI != CurMBB->getParent()->end()) 827 NextBlock = BBI; 828 829 // If the lhs block is the next block, invert the condition so that we can 830 // fall through to the lhs instead of the rhs block. 831 if (CB.LHSBB == NextBlock) { 832 std::swap(CB.LHSBB, CB.RHSBB); 833 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 834 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 835 } 836 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 837 DAG.getBasicBlock(CB.LHSBB)); 838 if (CB.RHSBB == NextBlock) 839 DAG.setRoot(BrCond); 840 else 841 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 842 DAG.getBasicBlock(CB.RHSBB))); 843 // Update successor info 844 CurMBB->addSuccessor(CB.LHSBB); 845 CurMBB->addSuccessor(CB.RHSBB); 846} 847 848/// visitSwitchCase - Emits the necessary code to represent a single node in 849/// the binary search tree resulting from lowering a switch instruction. 850void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 851 // FIXME: Need to emit different code for PIC vs. Non-PIC, specifically, 852 // we need to add the address of the jump table to the value loaded, since 853 // the entries in the jump table will be differences rather than absolute 854 // addresses. 855 856 // Emit the code for the jump table 857 MVT::ValueType PTy = TLI.getPointerTy(); 858 assert((PTy == MVT::i32 || PTy == MVT::i64) && 859 "Jump table entries are 32-bit values"); 860 // PIC jump table entries are 32-bit values. 861 unsigned EntrySize = 862 (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) 863 ? 4 : MVT::getSizeInBits(PTy)/8; 864 SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 865 SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy, 866 DAG.getConstant(EntrySize, PTy)); 867 SDOperand TAB = DAG.getJumpTable(JT.JTI,PTy); 868 SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, TAB); 869 SDOperand LD = DAG.getLoad(MVT::i32, Copy.getValue(1), ADD, 870 DAG.getSrcValue(0)); 871 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 872 ADD = DAG.getNode(ISD::ADD, PTy, 873 ((PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD), TAB); 874 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), ADD)); 875 } else { 876 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD)); 877 } 878} 879 880void SelectionDAGLowering::visitSwitch(SwitchInst &I) { 881 // Figure out which block is immediately after the current one. 882 MachineBasicBlock *NextBlock = 0; 883 MachineFunction::iterator BBI = CurMBB; 884 if (++BBI != CurMBB->getParent()->end()) 885 NextBlock = BBI; 886 887 // If there is only the default destination, branch to it if it is not the 888 // next basic block. Otherwise, just fall through. 889 if (I.getNumOperands() == 2) { 890 // Update machine-CFG edges. 891 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()]; 892 // If this is not a fall-through branch, emit the branch. 893 if (DefaultMBB != NextBlock) 894 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 895 DAG.getBasicBlock(DefaultMBB))); 896 CurMBB->addSuccessor(DefaultMBB); 897 return; 898 } 899 900 // If there are any non-default case statements, create a vector of Cases 901 // representing each one, and sort the vector so that we can efficiently 902 // create a binary search tree from them. 903 std::vector<Case> Cases; 904 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) { 905 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)]; 906 Cases.push_back(Case(I.getSuccessorValue(i), SMBB)); 907 } 908 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 909 910 // Get the Value to be switched on and default basic blocks, which will be 911 // inserted into CaseBlock records, representing basic blocks in the binary 912 // search tree. 913 Value *SV = I.getOperand(0); 914 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()]; 915 916 // Get the MachineFunction which holds the current MBB. This is used during 917 // emission of jump tables, and when inserting any additional MBBs necessary 918 // to represent the switch. 919 MachineFunction *CurMF = CurMBB->getParent(); 920 const BasicBlock *LLVMBB = CurMBB->getBasicBlock(); 921 922 // If the switch has more than 5 blocks, and at least 31.25% dense, and the 923 // target supports indirect branches, then emit a jump table rather than 924 // lowering the switch to a binary tree of conditional branches. 925 if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) && 926 Cases.size() > 5) { 927 uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue(); 928 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getRawValue(); 929 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL); 930 931 if (Density >= 0.3125) { 932 // Create a new basic block to hold the code for loading the address 933 // of the jump table, and jumping to it. Update successor information; 934 // we will either branch to the default case for the switch, or the jump 935 // table. 936 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 937 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 938 CurMBB->addSuccessor(Default); 939 CurMBB->addSuccessor(JumpTableBB); 940 941 // Subtract the lowest switch case value from the value being switched on 942 // and conditional branch to default mbb if the result is greater than the 943 // difference between smallest and largest cases. 944 SDOperand SwitchOp = getValue(SV); 945 MVT::ValueType VT = SwitchOp.getValueType(); 946 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 947 DAG.getConstant(First, VT)); 948 949 // The SDNode we just created, which holds the value being switched on 950 // minus the the smallest case value, needs to be copied to a virtual 951 // register so it can be used as an index into the jump table in a 952 // subsequent basic block. This value may be smaller or larger than the 953 // target's pointer type, and therefore require extension or truncating. 954 if (VT > TLI.getPointerTy()) 955 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 956 else 957 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 958 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 959 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 960 961 // Emit the range check for the jump table, and branch to the default 962 // block for the switch statement if the value being switched on exceeds 963 // the largest case in the switch. 964 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 965 DAG.getConstant(Last-First,VT), ISD::SETUGT); 966 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 967 DAG.getBasicBlock(Default))); 968 969 // Build a vector of destination BBs, corresponding to each target 970 // of the jump table. If the value of the jump table slot corresponds to 971 // a case statement, push the case's BB onto the vector, otherwise, push 972 // the default BB. 973 std::set<MachineBasicBlock*> UniqueBBs; 974 std::vector<MachineBasicBlock*> DestBBs; 975 uint64_t TEI = First; 976 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) { 977 if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) { 978 DestBBs.push_back(ii->second); 979 UniqueBBs.insert(ii->second); 980 ++ii; 981 } else { 982 DestBBs.push_back(Default); 983 UniqueBBs.insert(Default); 984 } 985 } 986 987 // Update successor info 988 for (std::set<MachineBasicBlock*>::iterator ii = UniqueBBs.begin(), 989 ee = UniqueBBs.end(); ii != ee; ++ii) 990 JumpTableBB->addSuccessor(*ii); 991 992 // Create a jump table index for this jump table, or return an existing 993 // one. 994 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 995 996 // Set the jump table information so that we can codegen it as a second 997 // MachineBasicBlock 998 JT.Reg = JumpTableReg; 999 JT.JTI = JTI; 1000 JT.MBB = JumpTableBB; 1001 JT.Default = Default; 1002 return; 1003 } 1004 } 1005 1006 // Push the initial CaseRec onto the worklist 1007 std::vector<CaseRec> CaseVec; 1008 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1009 1010 while (!CaseVec.empty()) { 1011 // Grab a record representing a case range to process off the worklist 1012 CaseRec CR = CaseVec.back(); 1013 CaseVec.pop_back(); 1014 1015 // Size is the number of Cases represented by this range. If Size is 1, 1016 // then we are processing a leaf of the binary search tree. Otherwise, 1017 // we need to pick a pivot, and push left and right ranges onto the 1018 // worklist. 1019 unsigned Size = CR.Range.second - CR.Range.first; 1020 1021 if (Size == 1) { 1022 // Create a CaseBlock record representing a conditional branch to 1023 // the Case's target mbb if the value being switched on SV is equal 1024 // to C. Otherwise, branch to default. 1025 Constant *C = CR.Range.first->first; 1026 MachineBasicBlock *Target = CR.Range.first->second; 1027 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default, 1028 CR.CaseBB); 1029 // If the MBB representing the leaf node is the current MBB, then just 1030 // call visitSwitchCase to emit the code into the current block. 1031 // Otherwise, push the CaseBlock onto the vector to be later processed 1032 // by SDISel, and insert the node's MBB before the next MBB. 1033 if (CR.CaseBB == CurMBB) 1034 visitSwitchCase(CB); 1035 else { 1036 SwitchCases.push_back(CB); 1037 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB); 1038 } 1039 } else { 1040 // split case range at pivot 1041 CaseItr Pivot = CR.Range.first + (Size / 2); 1042 CaseRange LHSR(CR.Range.first, Pivot); 1043 CaseRange RHSR(Pivot, CR.Range.second); 1044 Constant *C = Pivot->first; 1045 MachineBasicBlock *RHSBB = 0, *LHSBB = 0; 1046 // We know that we branch to the LHS if the Value being switched on is 1047 // less than the Pivot value, C. We use this to optimize our binary 1048 // tree a bit, by recognizing that if SV is greater than or equal to the 1049 // LHS's Case Value, and that Case Value is exactly one less than the 1050 // Pivot's Value, then we can branch directly to the LHS's Target, 1051 // rather than creating a leaf node for it. 1052 if ((LHSR.second - LHSR.first) == 1 && 1053 LHSR.first->first == CR.GE && 1054 cast<ConstantIntegral>(C)->getRawValue() == 1055 (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) { 1056 LHSBB = LHSR.first->second; 1057 } else { 1058 LHSBB = new MachineBasicBlock(LLVMBB); 1059 CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR)); 1060 } 1061 // Similar to the optimization above, if the Value being switched on is 1062 // known to be less than the Constant CR.LT, and the current Case Value 1063 // is CR.LT - 1, then we can branch directly to the target block for 1064 // the current Case Value, rather than emitting a RHS leaf node for it. 1065 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1066 cast<ConstantIntegral>(RHSR.first->first)->getRawValue() == 1067 (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) { 1068 RHSBB = RHSR.first->second; 1069 } else { 1070 RHSBB = new MachineBasicBlock(LLVMBB); 1071 CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR)); 1072 } 1073 // Create a CaseBlock record representing a conditional branch to 1074 // the LHS node if the value being switched on SV is less than C. 1075 // Otherwise, branch to LHS. 1076 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT; 1077 SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB); 1078 if (CR.CaseBB == CurMBB) 1079 visitSwitchCase(CB); 1080 else { 1081 SwitchCases.push_back(CB); 1082 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB); 1083 } 1084 } 1085 } 1086} 1087 1088void SelectionDAGLowering::visitSub(User &I) { 1089 // -0.0 - X --> fneg 1090 if (I.getType()->isFloatingPoint()) { 1091 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 1092 if (CFP->isExactlyValue(-0.0)) { 1093 SDOperand Op2 = getValue(I.getOperand(1)); 1094 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 1095 return; 1096 } 1097 } 1098 visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB); 1099} 1100 1101void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp, 1102 unsigned VecOp) { 1103 const Type *Ty = I.getType(); 1104 SDOperand Op1 = getValue(I.getOperand(0)); 1105 SDOperand Op2 = getValue(I.getOperand(1)); 1106 1107 if (Ty->isIntegral()) { 1108 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2)); 1109 } else if (Ty->isFloatingPoint()) { 1110 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2)); 1111 } else { 1112 const PackedType *PTy = cast<PackedType>(Ty); 1113 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32); 1114 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType())); 1115 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ)); 1116 } 1117} 1118 1119void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 1120 SDOperand Op1 = getValue(I.getOperand(0)); 1121 SDOperand Op2 = getValue(I.getOperand(1)); 1122 1123 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 1124 1125 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 1126} 1127 1128void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode, 1129 ISD::CondCode UnsignedOpcode, 1130 ISD::CondCode FPOpcode) { 1131 SDOperand Op1 = getValue(I.getOperand(0)); 1132 SDOperand Op2 = getValue(I.getOperand(1)); 1133 ISD::CondCode Opcode = SignedOpcode; 1134 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint()) 1135 Opcode = FPOpcode; 1136 else if (I.getOperand(0)->getType()->isUnsigned()) 1137 Opcode = UnsignedOpcode; 1138 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 1139} 1140 1141void SelectionDAGLowering::visitSelect(User &I) { 1142 SDOperand Cond = getValue(I.getOperand(0)); 1143 SDOperand TrueVal = getValue(I.getOperand(1)); 1144 SDOperand FalseVal = getValue(I.getOperand(2)); 1145 if (!isa<PackedType>(I.getType())) { 1146 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 1147 TrueVal, FalseVal)); 1148 } else { 1149 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal, 1150 *(TrueVal.Val->op_end()-2), 1151 *(TrueVal.Val->op_end()-1))); 1152 } 1153} 1154 1155void SelectionDAGLowering::visitCast(User &I) { 1156 SDOperand N = getValue(I.getOperand(0)); 1157 MVT::ValueType SrcVT = N.getValueType(); 1158 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1159 1160 if (DestVT == MVT::Vector) { 1161 // This is a cast to a vector from something else. This is always a bit 1162 // convert. Get information about the input vector. 1163 const PackedType *DestTy = cast<PackedType>(I.getType()); 1164 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 1165 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N, 1166 DAG.getConstant(DestTy->getNumElements(),MVT::i32), 1167 DAG.getValueType(EltVT))); 1168 } else if (SrcVT == DestVT) { 1169 setValue(&I, N); // noop cast. 1170 } else if (DestVT == MVT::i1) { 1171 // Cast to bool is a comparison against zero, not truncation to zero. 1172 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) : 1173 DAG.getConstantFP(0.0, N.getValueType()); 1174 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE)); 1175 } else if (isInteger(SrcVT)) { 1176 if (isInteger(DestVT)) { // Int -> Int cast 1177 if (DestVT < SrcVT) // Truncating cast? 1178 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 1179 else if (I.getOperand(0)->getType()->isSigned()) 1180 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 1181 else 1182 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 1183 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast 1184 if (I.getOperand(0)->getType()->isSigned()) 1185 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 1186 else 1187 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 1188 } else { 1189 assert(0 && "Unknown cast!"); 1190 } 1191 } else if (isFloatingPoint(SrcVT)) { 1192 if (isFloatingPoint(DestVT)) { // FP -> FP cast 1193 if (DestVT < SrcVT) // Rounding cast? 1194 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 1195 else 1196 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 1197 } else if (isInteger(DestVT)) { // FP -> Int cast. 1198 if (I.getType()->isSigned()) 1199 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 1200 else 1201 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 1202 } else { 1203 assert(0 && "Unknown cast!"); 1204 } 1205 } else { 1206 assert(SrcVT == MVT::Vector && "Unknown cast!"); 1207 assert(DestVT != MVT::Vector && "Casts to vector already handled!"); 1208 // This is a cast from a vector to something else. This is always a bit 1209 // convert. Get information about the input vector. 1210 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N)); 1211 } 1212} 1213 1214void SelectionDAGLowering::visitInsertElement(User &I) { 1215 SDOperand InVec = getValue(I.getOperand(0)); 1216 SDOperand InVal = getValue(I.getOperand(1)); 1217 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 1218 getValue(I.getOperand(2))); 1219 1220 SDOperand Num = *(InVec.Val->op_end()-2); 1221 SDOperand Typ = *(InVec.Val->op_end()-1); 1222 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector, 1223 InVec, InVal, InIdx, Num, Typ)); 1224} 1225 1226void SelectionDAGLowering::visitExtractElement(User &I) { 1227 SDOperand InVec = getValue(I.getOperand(0)); 1228 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 1229 getValue(I.getOperand(1))); 1230 SDOperand Typ = *(InVec.Val->op_end()-1); 1231 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, 1232 TLI.getValueType(I.getType()), InVec, InIdx)); 1233} 1234 1235void SelectionDAGLowering::visitShuffleVector(User &I) { 1236 SDOperand V1 = getValue(I.getOperand(0)); 1237 SDOperand V2 = getValue(I.getOperand(1)); 1238 SDOperand Mask = getValue(I.getOperand(2)); 1239 1240 SDOperand Num = *(V1.Val->op_end()-2); 1241 SDOperand Typ = *(V2.Val->op_end()-1); 1242 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 1243 V1, V2, Mask, Num, Typ)); 1244} 1245 1246 1247void SelectionDAGLowering::visitGetElementPtr(User &I) { 1248 SDOperand N = getValue(I.getOperand(0)); 1249 const Type *Ty = I.getOperand(0)->getType(); 1250 1251 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 1252 OI != E; ++OI) { 1253 Value *Idx = *OI; 1254 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 1255 unsigned Field = cast<ConstantUInt>(Idx)->getValue(); 1256 if (Field) { 1257 // N = N + Offset 1258 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field]; 1259 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 1260 getIntPtrConstant(Offset)); 1261 } 1262 Ty = StTy->getElementType(Field); 1263 } else { 1264 Ty = cast<SequentialType>(Ty)->getElementType(); 1265 1266 // If this is a constant subscript, handle it quickly. 1267 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 1268 if (CI->getRawValue() == 0) continue; 1269 1270 uint64_t Offs; 1271 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI)) 1272 Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue(); 1273 else 1274 Offs = TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue(); 1275 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 1276 continue; 1277 } 1278 1279 // N = N + Idx * ElementSize; 1280 uint64_t ElementSize = TD->getTypeSize(Ty); 1281 SDOperand IdxN = getValue(Idx); 1282 1283 // If the index is smaller or larger than intptr_t, truncate or extend 1284 // it. 1285 if (IdxN.getValueType() < N.getValueType()) { 1286 if (Idx->getType()->isSigned()) 1287 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 1288 else 1289 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN); 1290 } else if (IdxN.getValueType() > N.getValueType()) 1291 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 1292 1293 // If this is a multiply by a power of two, turn it into a shl 1294 // immediately. This is a very common case. 1295 if (isPowerOf2_64(ElementSize)) { 1296 unsigned Amt = Log2_64(ElementSize); 1297 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 1298 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 1299 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 1300 continue; 1301 } 1302 1303 SDOperand Scale = getIntPtrConstant(ElementSize); 1304 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 1305 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 1306 } 1307 } 1308 setValue(&I, N); 1309} 1310 1311void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 1312 // If this is a fixed sized alloca in the entry block of the function, 1313 // allocate it statically on the stack. 1314 if (FuncInfo.StaticAllocaMap.count(&I)) 1315 return; // getValue will auto-populate this. 1316 1317 const Type *Ty = I.getAllocatedType(); 1318 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 1319 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty), 1320 I.getAlignment()); 1321 1322 SDOperand AllocSize = getValue(I.getArraySize()); 1323 MVT::ValueType IntPtr = TLI.getPointerTy(); 1324 if (IntPtr < AllocSize.getValueType()) 1325 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 1326 else if (IntPtr > AllocSize.getValueType()) 1327 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 1328 1329 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 1330 getIntPtrConstant(TySize)); 1331 1332 // Handle alignment. If the requested alignment is less than or equal to the 1333 // stack alignment, ignore it and round the size of the allocation up to the 1334 // stack alignment size. If the size is greater than the stack alignment, we 1335 // note this in the DYNAMIC_STACKALLOC node. 1336 unsigned StackAlign = 1337 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1338 if (Align <= StackAlign) { 1339 Align = 0; 1340 // Add SA-1 to the size. 1341 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 1342 getIntPtrConstant(StackAlign-1)); 1343 // Mask out the low bits for alignment purposes. 1344 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 1345 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 1346 } 1347 1348 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 1349 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 1350 MVT::Other); 1351 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 1352 DAG.setRoot(setValue(&I, DSA).getValue(1)); 1353 1354 // Inform the Frame Information that we have just allocated a variable-sized 1355 // object. 1356 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 1357} 1358 1359void SelectionDAGLowering::visitLoad(LoadInst &I) { 1360 SDOperand Ptr = getValue(I.getOperand(0)); 1361 1362 SDOperand Root; 1363 if (I.isVolatile()) 1364 Root = getRoot(); 1365 else { 1366 // Do not serialize non-volatile loads against each other. 1367 Root = DAG.getRoot(); 1368 } 1369 1370 setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)), 1371 Root, I.isVolatile())); 1372} 1373 1374SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 1375 SDOperand SrcValue, SDOperand Root, 1376 bool isVolatile) { 1377 SDOperand L; 1378 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) { 1379 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 1380 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue); 1381 } else { 1382 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue); 1383 } 1384 1385 if (isVolatile) 1386 DAG.setRoot(L.getValue(1)); 1387 else 1388 PendingLoads.push_back(L.getValue(1)); 1389 1390 return L; 1391} 1392 1393 1394void SelectionDAGLowering::visitStore(StoreInst &I) { 1395 Value *SrcV = I.getOperand(0); 1396 SDOperand Src = getValue(SrcV); 1397 SDOperand Ptr = getValue(I.getOperand(1)); 1398 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr, 1399 DAG.getSrcValue(I.getOperand(1)))); 1400} 1401 1402/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot 1403/// access memory and has no other side effects at all. 1404static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) { 1405#define GET_NO_MEMORY_INTRINSICS 1406#include "llvm/Intrinsics.gen" 1407#undef GET_NO_MEMORY_INTRINSICS 1408 return false; 1409} 1410 1411// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't 1412// have any side-effects or if it only reads memory. 1413static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) { 1414#define GET_SIDE_EFFECT_INFO 1415#include "llvm/Intrinsics.gen" 1416#undef GET_SIDE_EFFECT_INFO 1417 return false; 1418} 1419 1420/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 1421/// node. 1422void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 1423 unsigned Intrinsic) { 1424 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic); 1425 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic); 1426 1427 // Build the operand list. 1428 SmallVector<SDOperand, 8> Ops; 1429 if (HasChain) { // If this intrinsic has side-effects, chainify it. 1430 if (OnlyLoad) { 1431 // We don't need to serialize loads against other loads. 1432 Ops.push_back(DAG.getRoot()); 1433 } else { 1434 Ops.push_back(getRoot()); 1435 } 1436 } 1437 1438 // Add the intrinsic ID as an integer operand. 1439 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 1440 1441 // Add all operands of the call to the operand list. 1442 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 1443 SDOperand Op = getValue(I.getOperand(i)); 1444 1445 // If this is a vector type, force it to the right packed type. 1446 if (Op.getValueType() == MVT::Vector) { 1447 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType()); 1448 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType()); 1449 1450 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements()); 1451 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?"); 1452 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op); 1453 } 1454 1455 assert(TLI.isTypeLegal(Op.getValueType()) && 1456 "Intrinsic uses a non-legal type?"); 1457 Ops.push_back(Op); 1458 } 1459 1460 std::vector<MVT::ValueType> VTs; 1461 if (I.getType() != Type::VoidTy) { 1462 MVT::ValueType VT = TLI.getValueType(I.getType()); 1463 if (VT == MVT::Vector) { 1464 const PackedType *DestTy = cast<PackedType>(I.getType()); 1465 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 1466 1467 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 1468 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 1469 } 1470 1471 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 1472 VTs.push_back(VT); 1473 } 1474 if (HasChain) 1475 VTs.push_back(MVT::Other); 1476 1477 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 1478 1479 // Create the node. 1480 SDOperand Result; 1481 if (!HasChain) 1482 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 1483 &Ops[0], Ops.size()); 1484 else if (I.getType() != Type::VoidTy) 1485 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 1486 &Ops[0], Ops.size()); 1487 else 1488 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 1489 &Ops[0], Ops.size()); 1490 1491 if (HasChain) { 1492 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 1493 if (OnlyLoad) 1494 PendingLoads.push_back(Chain); 1495 else 1496 DAG.setRoot(Chain); 1497 } 1498 if (I.getType() != Type::VoidTy) { 1499 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) { 1500 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType()); 1501 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 1502 DAG.getConstant(PTy->getNumElements(), MVT::i32), 1503 DAG.getValueType(EVT)); 1504 } 1505 setValue(&I, Result); 1506 } 1507} 1508 1509/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 1510/// we want to emit this as a call to a named external function, return the name 1511/// otherwise lower it and return null. 1512const char * 1513SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 1514 switch (Intrinsic) { 1515 default: 1516 // By default, turn this into a target intrinsic node. 1517 visitTargetIntrinsic(I, Intrinsic); 1518 return 0; 1519 case Intrinsic::vastart: visitVAStart(I); return 0; 1520 case Intrinsic::vaend: visitVAEnd(I); return 0; 1521 case Intrinsic::vacopy: visitVACopy(I); return 0; 1522 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0; 1523 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0; 1524 case Intrinsic::setjmp: 1525 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp(); 1526 break; 1527 case Intrinsic::longjmp: 1528 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp(); 1529 break; 1530 case Intrinsic::memcpy_i32: 1531 case Intrinsic::memcpy_i64: 1532 visitMemIntrinsic(I, ISD::MEMCPY); 1533 return 0; 1534 case Intrinsic::memset_i32: 1535 case Intrinsic::memset_i64: 1536 visitMemIntrinsic(I, ISD::MEMSET); 1537 return 0; 1538 case Intrinsic::memmove_i32: 1539 case Intrinsic::memmove_i64: 1540 visitMemIntrinsic(I, ISD::MEMMOVE); 1541 return 0; 1542 1543 case Intrinsic::dbg_stoppoint: { 1544 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1545 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 1546 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) { 1547 SDOperand Ops[5]; 1548 1549 Ops[0] = getRoot(); 1550 Ops[1] = getValue(SPI.getLineValue()); 1551 Ops[2] = getValue(SPI.getColumnValue()); 1552 1553 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext()); 1554 assert(DD && "Not a debug information descriptor"); 1555 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 1556 1557 Ops[3] = DAG.getString(CompileUnit->getFileName()); 1558 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 1559 1560 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 1561 } 1562 1563 return 0; 1564 } 1565 case Intrinsic::dbg_region_start: { 1566 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1567 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 1568 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) { 1569 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext()); 1570 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(), 1571 DAG.getConstant(LabelID, MVT::i32))); 1572 } 1573 1574 return 0; 1575 } 1576 case Intrinsic::dbg_region_end: { 1577 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1578 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 1579 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) { 1580 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext()); 1581 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, 1582 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 1583 } 1584 1585 return 0; 1586 } 1587 case Intrinsic::dbg_func_start: { 1588 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1589 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 1590 if (DebugInfo && FSI.getSubprogram() && 1591 DebugInfo->Verify(FSI.getSubprogram())) { 1592 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram()); 1593 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, 1594 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 1595 } 1596 1597 return 0; 1598 } 1599 case Intrinsic::dbg_declare: { 1600 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1601 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 1602 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) { 1603 SDOperand AddressOp = getValue(DI.getAddress()); 1604 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 1605 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex()); 1606 } 1607 1608 return 0; 1609 } 1610 1611 case Intrinsic::isunordered_f32: 1612 case Intrinsic::isunordered_f64: 1613 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)), 1614 getValue(I.getOperand(2)), ISD::SETUO)); 1615 return 0; 1616 1617 case Intrinsic::sqrt_f32: 1618 case Intrinsic::sqrt_f64: 1619 setValue(&I, DAG.getNode(ISD::FSQRT, 1620 getValue(I.getOperand(1)).getValueType(), 1621 getValue(I.getOperand(1)))); 1622 return 0; 1623 case Intrinsic::powi_f32: 1624 case Intrinsic::powi_f64: 1625 setValue(&I, DAG.getNode(ISD::FPOWI, 1626 getValue(I.getOperand(1)).getValueType(), 1627 getValue(I.getOperand(1)), 1628 getValue(I.getOperand(2)))); 1629 return 0; 1630 case Intrinsic::pcmarker: { 1631 SDOperand Tmp = getValue(I.getOperand(1)); 1632 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 1633 return 0; 1634 } 1635 case Intrinsic::readcyclecounter: { 1636 SDOperand Op = getRoot(); 1637 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 1638 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 1639 &Op, 1); 1640 setValue(&I, Tmp); 1641 DAG.setRoot(Tmp.getValue(1)); 1642 return 0; 1643 } 1644 case Intrinsic::bswap_i16: 1645 case Intrinsic::bswap_i32: 1646 case Intrinsic::bswap_i64: 1647 setValue(&I, DAG.getNode(ISD::BSWAP, 1648 getValue(I.getOperand(1)).getValueType(), 1649 getValue(I.getOperand(1)))); 1650 return 0; 1651 case Intrinsic::cttz_i8: 1652 case Intrinsic::cttz_i16: 1653 case Intrinsic::cttz_i32: 1654 case Intrinsic::cttz_i64: 1655 setValue(&I, DAG.getNode(ISD::CTTZ, 1656 getValue(I.getOperand(1)).getValueType(), 1657 getValue(I.getOperand(1)))); 1658 return 0; 1659 case Intrinsic::ctlz_i8: 1660 case Intrinsic::ctlz_i16: 1661 case Intrinsic::ctlz_i32: 1662 case Intrinsic::ctlz_i64: 1663 setValue(&I, DAG.getNode(ISD::CTLZ, 1664 getValue(I.getOperand(1)).getValueType(), 1665 getValue(I.getOperand(1)))); 1666 return 0; 1667 case Intrinsic::ctpop_i8: 1668 case Intrinsic::ctpop_i16: 1669 case Intrinsic::ctpop_i32: 1670 case Intrinsic::ctpop_i64: 1671 setValue(&I, DAG.getNode(ISD::CTPOP, 1672 getValue(I.getOperand(1)).getValueType(), 1673 getValue(I.getOperand(1)))); 1674 return 0; 1675 case Intrinsic::stacksave: { 1676 SDOperand Op = getRoot(); 1677 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 1678 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 1679 setValue(&I, Tmp); 1680 DAG.setRoot(Tmp.getValue(1)); 1681 return 0; 1682 } 1683 case Intrinsic::stackrestore: { 1684 SDOperand Tmp = getValue(I.getOperand(1)); 1685 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 1686 return 0; 1687 } 1688 case Intrinsic::prefetch: 1689 // FIXME: Currently discarding prefetches. 1690 return 0; 1691 } 1692} 1693 1694 1695void SelectionDAGLowering::visitCall(CallInst &I) { 1696 const char *RenameFn = 0; 1697 if (Function *F = I.getCalledFunction()) { 1698 if (F->isExternal()) 1699 if (unsigned IID = F->getIntrinsicID()) { 1700 RenameFn = visitIntrinsicCall(I, IID); 1701 if (!RenameFn) 1702 return; 1703 } else { // Not an LLVM intrinsic. 1704 const std::string &Name = F->getName(); 1705 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) { 1706 if (I.getNumOperands() == 3 && // Basic sanity checks. 1707 I.getOperand(1)->getType()->isFloatingPoint() && 1708 I.getType() == I.getOperand(1)->getType() && 1709 I.getType() == I.getOperand(2)->getType()) { 1710 SDOperand LHS = getValue(I.getOperand(1)); 1711 SDOperand RHS = getValue(I.getOperand(2)); 1712 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 1713 LHS, RHS)); 1714 return; 1715 } 1716 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) { 1717 if (I.getNumOperands() == 2 && // Basic sanity checks. 1718 I.getOperand(1)->getType()->isFloatingPoint() && 1719 I.getType() == I.getOperand(1)->getType()) { 1720 SDOperand Tmp = getValue(I.getOperand(1)); 1721 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 1722 return; 1723 } 1724 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) { 1725 if (I.getNumOperands() == 2 && // Basic sanity checks. 1726 I.getOperand(1)->getType()->isFloatingPoint() && 1727 I.getType() == I.getOperand(1)->getType()) { 1728 SDOperand Tmp = getValue(I.getOperand(1)); 1729 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 1730 return; 1731 } 1732 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) { 1733 if (I.getNumOperands() == 2 && // Basic sanity checks. 1734 I.getOperand(1)->getType()->isFloatingPoint() && 1735 I.getType() == I.getOperand(1)->getType()) { 1736 SDOperand Tmp = getValue(I.getOperand(1)); 1737 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 1738 return; 1739 } 1740 } 1741 } 1742 } else if (isa<InlineAsm>(I.getOperand(0))) { 1743 visitInlineAsm(I); 1744 return; 1745 } 1746 1747 SDOperand Callee; 1748 if (!RenameFn) 1749 Callee = getValue(I.getOperand(0)); 1750 else 1751 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 1752 std::vector<std::pair<SDOperand, const Type*> > Args; 1753 Args.reserve(I.getNumOperands()); 1754 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 1755 Value *Arg = I.getOperand(i); 1756 SDOperand ArgNode = getValue(Arg); 1757 Args.push_back(std::make_pair(ArgNode, Arg->getType())); 1758 } 1759 1760 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType()); 1761 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1762 1763 std::pair<SDOperand,SDOperand> Result = 1764 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(), 1765 I.isTailCall(), Callee, Args, DAG); 1766 if (I.getType() != Type::VoidTy) 1767 setValue(&I, Result.first); 1768 DAG.setRoot(Result.second); 1769} 1770 1771SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 1772 SDOperand &Chain, SDOperand &Flag)const{ 1773 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag); 1774 Chain = Val.getValue(1); 1775 Flag = Val.getValue(2); 1776 1777 // If the result was expanded, copy from the top part. 1778 if (Regs.size() > 1) { 1779 assert(Regs.size() == 2 && 1780 "Cannot expand to more than 2 elts yet!"); 1781 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag); 1782 Chain = Val.getValue(1); 1783 Flag = Val.getValue(2); 1784 if (DAG.getTargetLoweringInfo().isLittleEndian()) 1785 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 1786 else 1787 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val); 1788 } 1789 1790 // Otherwise, if the return value was promoted or extended, truncate it to the 1791 // appropriate type. 1792 if (RegVT == ValueVT) 1793 return Val; 1794 1795 if (MVT::isInteger(RegVT)) { 1796 if (ValueVT < RegVT) 1797 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 1798 else 1799 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 1800 } else { 1801 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 1802 } 1803} 1804 1805/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 1806/// specified value into the registers specified by this object. This uses 1807/// Chain/Flag as the input and updates them for the output Chain/Flag. 1808void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 1809 SDOperand &Chain, SDOperand &Flag, 1810 MVT::ValueType PtrVT) const { 1811 if (Regs.size() == 1) { 1812 // If there is a single register and the types differ, this must be 1813 // a promotion. 1814 if (RegVT != ValueVT) { 1815 if (MVT::isInteger(RegVT)) { 1816 if (RegVT < ValueVT) 1817 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val); 1818 else 1819 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val); 1820 } else 1821 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val); 1822 } 1823 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag); 1824 Flag = Chain.getValue(1); 1825 } else { 1826 std::vector<unsigned> R(Regs); 1827 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 1828 std::reverse(R.begin(), R.end()); 1829 1830 for (unsigned i = 0, e = R.size(); i != e; ++i) { 1831 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val, 1832 DAG.getConstant(i, PtrVT)); 1833 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag); 1834 Flag = Chain.getValue(1); 1835 } 1836 } 1837} 1838 1839/// AddInlineAsmOperands - Add this value to the specified inlineasm node 1840/// operand list. This adds the code marker and includes the number of 1841/// values added into it. 1842void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 1843 std::vector<SDOperand> &Ops) const { 1844 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32)); 1845 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 1846 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 1847} 1848 1849/// isAllocatableRegister - If the specified register is safe to allocate, 1850/// i.e. it isn't a stack pointer or some other special register, return the 1851/// register class for the register. Otherwise, return null. 1852static const TargetRegisterClass * 1853isAllocatableRegister(unsigned Reg, MachineFunction &MF, 1854 const TargetLowering &TLI, const MRegisterInfo *MRI) { 1855 MVT::ValueType FoundVT = MVT::Other; 1856 const TargetRegisterClass *FoundRC = 0; 1857 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 1858 E = MRI->regclass_end(); RCI != E; ++RCI) { 1859 MVT::ValueType ThisVT = MVT::Other; 1860 1861 const TargetRegisterClass *RC = *RCI; 1862 // If none of the the value types for this register class are valid, we 1863 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1864 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1865 I != E; ++I) { 1866 if (TLI.isTypeLegal(*I)) { 1867 // If we have already found this register in a different register class, 1868 // choose the one with the largest VT specified. For example, on 1869 // PowerPC, we favor f64 register classes over f32. 1870 if (FoundVT == MVT::Other || 1871 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 1872 ThisVT = *I; 1873 break; 1874 } 1875 } 1876 } 1877 1878 if (ThisVT == MVT::Other) continue; 1879 1880 // NOTE: This isn't ideal. In particular, this might allocate the 1881 // frame pointer in functions that need it (due to them not being taken 1882 // out of allocation, because a variable sized allocation hasn't been seen 1883 // yet). This is a slight code pessimization, but should still work. 1884 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 1885 E = RC->allocation_order_end(MF); I != E; ++I) 1886 if (*I == Reg) { 1887 // We found a matching register class. Keep looking at others in case 1888 // we find one with larger registers that this physreg is also in. 1889 FoundRC = RC; 1890 FoundVT = ThisVT; 1891 break; 1892 } 1893 } 1894 return FoundRC; 1895} 1896 1897RegsForValue SelectionDAGLowering:: 1898GetRegistersForValue(const std::string &ConstrCode, 1899 MVT::ValueType VT, bool isOutReg, bool isInReg, 1900 std::set<unsigned> &OutputRegs, 1901 std::set<unsigned> &InputRegs) { 1902 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 1903 TLI.getRegForInlineAsmConstraint(ConstrCode, VT); 1904 std::vector<unsigned> Regs; 1905 1906 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1; 1907 MVT::ValueType RegVT; 1908 MVT::ValueType ValueVT = VT; 1909 1910 if (PhysReg.first) { 1911 if (VT == MVT::Other) 1912 ValueVT = *PhysReg.second->vt_begin(); 1913 1914 // Get the actual register value type. This is important, because the user 1915 // may have asked for (e.g.) the AX register in i32 type. We need to 1916 // remember that AX is actually i16 to get the right extension. 1917 RegVT = *PhysReg.second->vt_begin(); 1918 1919 // This is a explicit reference to a physical register. 1920 Regs.push_back(PhysReg.first); 1921 1922 // If this is an expanded reference, add the rest of the regs to Regs. 1923 if (NumRegs != 1) { 1924 TargetRegisterClass::iterator I = PhysReg.second->begin(); 1925 TargetRegisterClass::iterator E = PhysReg.second->end(); 1926 for (; *I != PhysReg.first; ++I) 1927 assert(I != E && "Didn't find reg!"); 1928 1929 // Already added the first reg. 1930 --NumRegs; ++I; 1931 for (; NumRegs; --NumRegs, ++I) { 1932 assert(I != E && "Ran out of registers to allocate!"); 1933 Regs.push_back(*I); 1934 } 1935 } 1936 return RegsForValue(Regs, RegVT, ValueVT); 1937 } 1938 1939 // This is a reference to a register class. Allocate NumRegs consecutive, 1940 // available, registers from the class. 1941 std::vector<unsigned> RegClassRegs = 1942 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT); 1943 1944 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 1945 MachineFunction &MF = *CurMBB->getParent(); 1946 unsigned NumAllocated = 0; 1947 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 1948 unsigned Reg = RegClassRegs[i]; 1949 // See if this register is available. 1950 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 1951 (isInReg && InputRegs.count(Reg))) { // Already used. 1952 // Make sure we find consecutive registers. 1953 NumAllocated = 0; 1954 continue; 1955 } 1956 1957 // Check to see if this register is allocatable (i.e. don't give out the 1958 // stack pointer). 1959 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI); 1960 if (!RC) { 1961 // Make sure we find consecutive registers. 1962 NumAllocated = 0; 1963 continue; 1964 } 1965 1966 // Okay, this register is good, we can use it. 1967 ++NumAllocated; 1968 1969 // If we allocated enough consecutive 1970 if (NumAllocated == NumRegs) { 1971 unsigned RegStart = (i-NumAllocated)+1; 1972 unsigned RegEnd = i+1; 1973 // Mark all of the allocated registers used. 1974 for (unsigned i = RegStart; i != RegEnd; ++i) { 1975 unsigned Reg = RegClassRegs[i]; 1976 Regs.push_back(Reg); 1977 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used. 1978 if (isInReg) InputRegs.insert(Reg); // Mark reg used. 1979 } 1980 1981 return RegsForValue(Regs, *RC->vt_begin(), VT); 1982 } 1983 } 1984 1985 // Otherwise, we couldn't allocate enough registers for this. 1986 return RegsForValue(); 1987} 1988 1989 1990/// visitInlineAsm - Handle a call to an InlineAsm object. 1991/// 1992void SelectionDAGLowering::visitInlineAsm(CallInst &I) { 1993 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0)); 1994 1995 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 1996 MVT::Other); 1997 1998 // Note, we treat inline asms both with and without side-effects as the same. 1999 // If an inline asm doesn't have side effects and doesn't access memory, we 2000 // could not choose to not chain it. 2001 bool hasSideEffects = IA->hasSideEffects(); 2002 2003 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 2004 std::vector<MVT::ValueType> ConstraintVTs; 2005 2006 /// AsmNodeOperands - A list of pairs. The first element is a register, the 2007 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set 2008 /// if it is a def of that register. 2009 std::vector<SDOperand> AsmNodeOperands; 2010 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 2011 AsmNodeOperands.push_back(AsmStr); 2012 2013 SDOperand Chain = getRoot(); 2014 SDOperand Flag; 2015 2016 // We fully assign registers here at isel time. This is not optimal, but 2017 // should work. For register classes that correspond to LLVM classes, we 2018 // could let the LLVM RA do its thing, but we currently don't. Do a prepass 2019 // over the constraints, collecting fixed registers that we know we can't use. 2020 std::set<unsigned> OutputRegs, InputRegs; 2021 unsigned OpNum = 1; 2022 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) { 2023 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!"); 2024 std::string &ConstraintCode = Constraints[i].Codes[0]; 2025 2026 MVT::ValueType OpVT; 2027 2028 // Compute the value type for each operand and add it to ConstraintVTs. 2029 switch (Constraints[i].Type) { 2030 case InlineAsm::isOutput: 2031 if (!Constraints[i].isIndirectOutput) { 2032 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 2033 OpVT = TLI.getValueType(I.getType()); 2034 } else { 2035 const Type *OpTy = I.getOperand(OpNum)->getType(); 2036 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType()); 2037 OpNum++; // Consumes a call operand. 2038 } 2039 break; 2040 case InlineAsm::isInput: 2041 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType()); 2042 OpNum++; // Consumes a call operand. 2043 break; 2044 case InlineAsm::isClobber: 2045 OpVT = MVT::Other; 2046 break; 2047 } 2048 2049 ConstraintVTs.push_back(OpVT); 2050 2051 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0) 2052 continue; // Not assigned a fixed reg. 2053 2054 // Build a list of regs that this operand uses. This always has a single 2055 // element for promoted/expanded operands. 2056 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT, 2057 false, false, 2058 OutputRegs, InputRegs); 2059 2060 switch (Constraints[i].Type) { 2061 case InlineAsm::isOutput: 2062 // We can't assign any other output to this register. 2063 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2064 // If this is an early-clobber output, it cannot be assigned to the same 2065 // value as the input reg. 2066 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput) 2067 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2068 break; 2069 case InlineAsm::isInput: 2070 // We can't assign any other input to this register. 2071 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2072 break; 2073 case InlineAsm::isClobber: 2074 // Clobbered regs cannot be used as inputs or outputs. 2075 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2076 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2077 break; 2078 } 2079 } 2080 2081 // Loop over all of the inputs, copying the operand values into the 2082 // appropriate registers and processing the output regs. 2083 RegsForValue RetValRegs; 2084 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 2085 OpNum = 1; 2086 2087 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) { 2088 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!"); 2089 std::string &ConstraintCode = Constraints[i].Codes[0]; 2090 2091 switch (Constraints[i].Type) { 2092 case InlineAsm::isOutput: { 2093 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass; 2094 if (ConstraintCode.size() == 1) // not a physreg name. 2095 CTy = TLI.getConstraintType(ConstraintCode[0]); 2096 2097 if (CTy == TargetLowering::C_Memory) { 2098 // Memory output. 2099 SDOperand InOperandVal = getValue(I.getOperand(OpNum)); 2100 2101 // Check that the operand (the address to store to) isn't a float. 2102 if (!MVT::isInteger(InOperandVal.getValueType())) 2103 assert(0 && "MATCH FAIL!"); 2104 2105 if (!Constraints[i].isIndirectOutput) 2106 assert(0 && "MATCH FAIL!"); 2107 2108 OpNum++; // Consumes a call operand. 2109 2110 // Extend/truncate to the right pointer type if needed. 2111 MVT::ValueType PtrType = TLI.getPointerTy(); 2112 if (InOperandVal.getValueType() < PtrType) 2113 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal); 2114 else if (InOperandVal.getValueType() > PtrType) 2115 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal); 2116 2117 // Add information to the INLINEASM node to know about this output. 2118 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 2119 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 2120 AsmNodeOperands.push_back(InOperandVal); 2121 break; 2122 } 2123 2124 // Otherwise, this is a register output. 2125 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!"); 2126 2127 // If this is an early-clobber output, or if there is an input 2128 // constraint that matches this, we need to reserve the input register 2129 // so no other inputs allocate to it. 2130 bool UsesInputRegister = false; 2131 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput) 2132 UsesInputRegister = true; 2133 2134 // Copy the output from the appropriate register. Find a register that 2135 // we can use. 2136 RegsForValue Regs = 2137 GetRegistersForValue(ConstraintCode, ConstraintVTs[i], 2138 true, UsesInputRegister, 2139 OutputRegs, InputRegs); 2140 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!"); 2141 2142 if (!Constraints[i].isIndirectOutput) { 2143 assert(RetValRegs.Regs.empty() && 2144 "Cannot have multiple output constraints yet!"); 2145 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 2146 RetValRegs = Regs; 2147 } else { 2148 IndirectStoresToEmit.push_back(std::make_pair(Regs, 2149 I.getOperand(OpNum))); 2150 OpNum++; // Consumes a call operand. 2151 } 2152 2153 // Add information to the INLINEASM node to know that this register is 2154 // set. 2155 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands); 2156 break; 2157 } 2158 case InlineAsm::isInput: { 2159 SDOperand InOperandVal = getValue(I.getOperand(OpNum)); 2160 OpNum++; // Consumes a call operand. 2161 2162 if (isdigit(ConstraintCode[0])) { // Matching constraint? 2163 // If this is required to match an output register we have already set, 2164 // just use its register. 2165 unsigned OperandNo = atoi(ConstraintCode.c_str()); 2166 2167 // Scan until we find the definition we already emitted of this operand. 2168 // When we find it, create a RegsForValue operand. 2169 unsigned CurOp = 2; // The first operand. 2170 for (; OperandNo; --OperandNo) { 2171 // Advance to the next operand. 2172 unsigned NumOps = 2173 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 2174 assert(((NumOps & 7) == 2 /*REGDEF*/ || 2175 (NumOps & 7) == 4 /*MEM*/) && 2176 "Skipped past definitions?"); 2177 CurOp += (NumOps>>3)+1; 2178 } 2179 2180 unsigned NumOps = 2181 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 2182 assert((NumOps & 7) == 2 /*REGDEF*/ && 2183 "Skipped past definitions?"); 2184 2185 // Add NumOps>>3 registers to MatchedRegs. 2186 RegsForValue MatchedRegs; 2187 MatchedRegs.ValueVT = InOperandVal.getValueType(); 2188 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 2189 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 2190 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 2191 MatchedRegs.Regs.push_back(Reg); 2192 } 2193 2194 // Use the produced MatchedRegs object to 2195 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, 2196 TLI.getPointerTy()); 2197 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 2198 break; 2199 } 2200 2201 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass; 2202 if (ConstraintCode.size() == 1) // not a physreg name. 2203 CTy = TLI.getConstraintType(ConstraintCode[0]); 2204 2205 if (CTy == TargetLowering::C_Other) { 2206 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0])) 2207 assert(0 && "MATCH FAIL!"); 2208 2209 // Add information to the INLINEASM node to know about this input. 2210 unsigned ResOpType = 3 /*IMM*/ | (1 << 3); 2211 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 2212 AsmNodeOperands.push_back(InOperandVal); 2213 break; 2214 } else if (CTy == TargetLowering::C_Memory) { 2215 // Memory input. 2216 2217 // Check that the operand isn't a float. 2218 if (!MVT::isInteger(InOperandVal.getValueType())) 2219 assert(0 && "MATCH FAIL!"); 2220 2221 // Extend/truncate to the right pointer type if needed. 2222 MVT::ValueType PtrType = TLI.getPointerTy(); 2223 if (InOperandVal.getValueType() < PtrType) 2224 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal); 2225 else if (InOperandVal.getValueType() > PtrType) 2226 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal); 2227 2228 // Add information to the INLINEASM node to know about this input. 2229 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 2230 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 2231 AsmNodeOperands.push_back(InOperandVal); 2232 break; 2233 } 2234 2235 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!"); 2236 2237 // Copy the input into the appropriate registers. 2238 RegsForValue InRegs = 2239 GetRegistersForValue(ConstraintCode, ConstraintVTs[i], 2240 false, true, OutputRegs, InputRegs); 2241 // FIXME: should be match fail. 2242 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!"); 2243 2244 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy()); 2245 2246 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands); 2247 break; 2248 } 2249 case InlineAsm::isClobber: { 2250 RegsForValue ClobberedRegs = 2251 GetRegistersForValue(ConstraintCode, MVT::Other, false, false, 2252 OutputRegs, InputRegs); 2253 // Add the clobbered value to the operand list, so that the register 2254 // allocator is aware that the physreg got clobbered. 2255 if (!ClobberedRegs.Regs.empty()) 2256 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands); 2257 break; 2258 } 2259 } 2260 } 2261 2262 // Finish up input operands. 2263 AsmNodeOperands[0] = Chain; 2264 if (Flag.Val) AsmNodeOperands.push_back(Flag); 2265 2266 Chain = DAG.getNode(ISD::INLINEASM, 2267 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 2268 &AsmNodeOperands[0], AsmNodeOperands.size()); 2269 Flag = Chain.getValue(1); 2270 2271 // If this asm returns a register value, copy the result from that register 2272 // and set it as the value of the call. 2273 if (!RetValRegs.Regs.empty()) 2274 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag)); 2275 2276 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 2277 2278 // Process indirect outputs, first output all of the flagged copies out of 2279 // physregs. 2280 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 2281 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 2282 Value *Ptr = IndirectStoresToEmit[i].second; 2283 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag); 2284 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 2285 } 2286 2287 // Emit the non-flagged stores from the physregs. 2288 SmallVector<SDOperand, 8> OutChains; 2289 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 2290 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 2291 StoresToEmit[i].first, 2292 getValue(StoresToEmit[i].second), 2293 DAG.getSrcValue(StoresToEmit[i].second))); 2294 if (!OutChains.empty()) 2295 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2296 &OutChains[0], OutChains.size()); 2297 DAG.setRoot(Chain); 2298} 2299 2300 2301void SelectionDAGLowering::visitMalloc(MallocInst &I) { 2302 SDOperand Src = getValue(I.getOperand(0)); 2303 2304 MVT::ValueType IntPtr = TLI.getPointerTy(); 2305 2306 if (IntPtr < Src.getValueType()) 2307 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 2308 else if (IntPtr > Src.getValueType()) 2309 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 2310 2311 // Scale the source by the type size. 2312 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType()); 2313 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 2314 Src, getIntPtrConstant(ElementSize)); 2315 2316 std::vector<std::pair<SDOperand, const Type*> > Args; 2317 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType())); 2318 2319 std::pair<SDOperand,SDOperand> Result = 2320 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true, 2321 DAG.getExternalSymbol("malloc", IntPtr), 2322 Args, DAG); 2323 setValue(&I, Result.first); // Pointers always fit in registers 2324 DAG.setRoot(Result.second); 2325} 2326 2327void SelectionDAGLowering::visitFree(FreeInst &I) { 2328 std::vector<std::pair<SDOperand, const Type*> > Args; 2329 Args.push_back(std::make_pair(getValue(I.getOperand(0)), 2330 TLI.getTargetData()->getIntPtrType())); 2331 MVT::ValueType IntPtr = TLI.getPointerTy(); 2332 std::pair<SDOperand,SDOperand> Result = 2333 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true, 2334 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 2335 DAG.setRoot(Result.second); 2336} 2337 2338// InsertAtEndOfBasicBlock - This method should be implemented by targets that 2339// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 2340// instructions are special in various ways, which require special support to 2341// insert. The specified MachineInstr is created but not inserted into any 2342// basic blocks, and the scheduler passes ownership of it to this method. 2343MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 2344 MachineBasicBlock *MBB) { 2345 std::cerr << "If a target marks an instruction with " 2346 "'usesCustomDAGSchedInserter', it must implement " 2347 "TargetLowering::InsertAtEndOfBasicBlock!\n"; 2348 abort(); 2349 return 0; 2350} 2351 2352void SelectionDAGLowering::visitVAStart(CallInst &I) { 2353 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 2354 getValue(I.getOperand(1)), 2355 DAG.getSrcValue(I.getOperand(1)))); 2356} 2357 2358void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 2359 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 2360 getValue(I.getOperand(0)), 2361 DAG.getSrcValue(I.getOperand(0))); 2362 setValue(&I, V); 2363 DAG.setRoot(V.getValue(1)); 2364} 2365 2366void SelectionDAGLowering::visitVAEnd(CallInst &I) { 2367 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 2368 getValue(I.getOperand(1)), 2369 DAG.getSrcValue(I.getOperand(1)))); 2370} 2371 2372void SelectionDAGLowering::visitVACopy(CallInst &I) { 2373 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 2374 getValue(I.getOperand(1)), 2375 getValue(I.getOperand(2)), 2376 DAG.getSrcValue(I.getOperand(1)), 2377 DAG.getSrcValue(I.getOperand(2)))); 2378} 2379 2380/// TargetLowering::LowerArguments - This is the default LowerArguments 2381/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 2382/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 2383/// integrated into SDISel. 2384std::vector<SDOperand> 2385TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 2386 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 2387 std::vector<SDOperand> Ops; 2388 Ops.push_back(DAG.getRoot()); 2389 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 2390 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 2391 2392 // Add one result value for each formal argument. 2393 std::vector<MVT::ValueType> RetVals; 2394 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 2395 MVT::ValueType VT = getValueType(I->getType()); 2396 2397 switch (getTypeAction(VT)) { 2398 default: assert(0 && "Unknown type action!"); 2399 case Legal: 2400 RetVals.push_back(VT); 2401 break; 2402 case Promote: 2403 RetVals.push_back(getTypeToTransformTo(VT)); 2404 break; 2405 case Expand: 2406 if (VT != MVT::Vector) { 2407 // If this is a large integer, it needs to be broken up into small 2408 // integers. Figure out what the destination type is and how many small 2409 // integers it turns into. 2410 MVT::ValueType NVT = getTypeToTransformTo(VT); 2411 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); 2412 for (unsigned i = 0; i != NumVals; ++i) 2413 RetVals.push_back(NVT); 2414 } else { 2415 // Otherwise, this is a vector type. We only support legal vectors 2416 // right now. 2417 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements(); 2418 const Type *EltTy = cast<PackedType>(I->getType())->getElementType(); 2419 2420 // Figure out if there is a Packed type corresponding to this Vector 2421 // type. If so, convert to the packed type. 2422 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2423 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2424 RetVals.push_back(TVT); 2425 } else { 2426 assert(0 && "Don't support illegal by-val vector arguments yet!"); 2427 } 2428 } 2429 break; 2430 } 2431 } 2432 2433 RetVals.push_back(MVT::Other); 2434 2435 // Create the node. 2436 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 2437 DAG.getNodeValueTypes(RetVals), RetVals.size(), 2438 &Ops[0], Ops.size()).Val; 2439 2440 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1)); 2441 2442 // Set up the return result vector. 2443 Ops.clear(); 2444 unsigned i = 0; 2445 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 2446 MVT::ValueType VT = getValueType(I->getType()); 2447 2448 switch (getTypeAction(VT)) { 2449 default: assert(0 && "Unknown type action!"); 2450 case Legal: 2451 Ops.push_back(SDOperand(Result, i++)); 2452 break; 2453 case Promote: { 2454 SDOperand Op(Result, i++); 2455 if (MVT::isInteger(VT)) { 2456 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 2457 : ISD::AssertZext; 2458 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT)); 2459 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2460 } else { 2461 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 2462 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 2463 } 2464 Ops.push_back(Op); 2465 break; 2466 } 2467 case Expand: 2468 if (VT != MVT::Vector) { 2469 // If this is a large integer, it needs to be reassembled from small 2470 // integers. Figure out what the source elt type is and how many small 2471 // integers it is. 2472 MVT::ValueType NVT = getTypeToTransformTo(VT); 2473 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); 2474 if (NumVals == 2) { 2475 SDOperand Lo = SDOperand(Result, i++); 2476 SDOperand Hi = SDOperand(Result, i++); 2477 2478 if (!isLittleEndian()) 2479 std::swap(Lo, Hi); 2480 2481 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi)); 2482 } else { 2483 // Value scalarized into many values. Unimp for now. 2484 assert(0 && "Cannot expand i64 -> i16 yet!"); 2485 } 2486 } else { 2487 // Otherwise, this is a vector type. We only support legal vectors 2488 // right now. 2489 const PackedType *PTy = cast<PackedType>(I->getType()); 2490 unsigned NumElems = PTy->getNumElements(); 2491 const Type *EltTy = PTy->getElementType(); 2492 2493 // Figure out if there is a Packed type corresponding to this Vector 2494 // type. If so, convert to the packed type. 2495 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2496 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2497 SDOperand N = SDOperand(Result, i++); 2498 // Handle copies from generic vectors to registers. 2499 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, 2500 DAG.getConstant(NumElems, MVT::i32), 2501 DAG.getValueType(getValueType(EltTy))); 2502 Ops.push_back(N); 2503 } else { 2504 assert(0 && "Don't support illegal by-val vector arguments yet!"); 2505 abort(); 2506 } 2507 } 2508 break; 2509 } 2510 } 2511 return Ops; 2512} 2513 2514 2515/// TargetLowering::LowerCallTo - This is the default LowerCallTo 2516/// implementation, which just inserts an ISD::CALL node, which is later custom 2517/// lowered by the target to something concrete. FIXME: When all targets are 2518/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 2519std::pair<SDOperand, SDOperand> 2520TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 2521 unsigned CallingConv, bool isTailCall, 2522 SDOperand Callee, 2523 ArgListTy &Args, SelectionDAG &DAG) { 2524 SmallVector<SDOperand, 32> Ops; 2525 Ops.push_back(Chain); // Op#0 - Chain 2526 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 2527 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 2528 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 2529 Ops.push_back(Callee); 2530 2531 // Handle all of the outgoing arguments. 2532 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 2533 MVT::ValueType VT = getValueType(Args[i].second); 2534 SDOperand Op = Args[i].first; 2535 bool isSigned = Args[i].second->isSigned(); 2536 switch (getTypeAction(VT)) { 2537 default: assert(0 && "Unknown type action!"); 2538 case Legal: 2539 Ops.push_back(Op); 2540 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2541 break; 2542 case Promote: 2543 if (MVT::isInteger(VT)) { 2544 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 2545 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 2546 } else { 2547 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 2548 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 2549 } 2550 Ops.push_back(Op); 2551 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2552 break; 2553 case Expand: 2554 if (VT != MVT::Vector) { 2555 // If this is a large integer, it needs to be broken down into small 2556 // integers. Figure out what the source elt type is and how many small 2557 // integers it is. 2558 MVT::ValueType NVT = getTypeToTransformTo(VT); 2559 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); 2560 if (NumVals == 2) { 2561 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op, 2562 DAG.getConstant(0, getPointerTy())); 2563 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op, 2564 DAG.getConstant(1, getPointerTy())); 2565 if (!isLittleEndian()) 2566 std::swap(Lo, Hi); 2567 2568 Ops.push_back(Lo); 2569 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2570 Ops.push_back(Hi); 2571 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2572 } else { 2573 // Value scalarized into many values. Unimp for now. 2574 assert(0 && "Cannot expand i64 -> i16 yet!"); 2575 } 2576 } else { 2577 // Otherwise, this is a vector type. We only support legal vectors 2578 // right now. 2579 const PackedType *PTy = cast<PackedType>(Args[i].second); 2580 unsigned NumElems = PTy->getNumElements(); 2581 const Type *EltTy = PTy->getElementType(); 2582 2583 // Figure out if there is a Packed type corresponding to this Vector 2584 // type. If so, convert to the packed type. 2585 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2586 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2587 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type. 2588 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op); 2589 Ops.push_back(Op); 2590 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2591 } else { 2592 assert(0 && "Don't support illegal by-val vector call args yet!"); 2593 abort(); 2594 } 2595 } 2596 break; 2597 } 2598 } 2599 2600 // Figure out the result value types. 2601 SmallVector<MVT::ValueType, 4> RetTys; 2602 2603 if (RetTy != Type::VoidTy) { 2604 MVT::ValueType VT = getValueType(RetTy); 2605 switch (getTypeAction(VT)) { 2606 default: assert(0 && "Unknown type action!"); 2607 case Legal: 2608 RetTys.push_back(VT); 2609 break; 2610 case Promote: 2611 RetTys.push_back(getTypeToTransformTo(VT)); 2612 break; 2613 case Expand: 2614 if (VT != MVT::Vector) { 2615 // If this is a large integer, it needs to be reassembled from small 2616 // integers. Figure out what the source elt type is and how many small 2617 // integers it is. 2618 MVT::ValueType NVT = getTypeToTransformTo(VT); 2619 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); 2620 for (unsigned i = 0; i != NumVals; ++i) 2621 RetTys.push_back(NVT); 2622 } else { 2623 // Otherwise, this is a vector type. We only support legal vectors 2624 // right now. 2625 const PackedType *PTy = cast<PackedType>(RetTy); 2626 unsigned NumElems = PTy->getNumElements(); 2627 const Type *EltTy = PTy->getElementType(); 2628 2629 // Figure out if there is a Packed type corresponding to this Vector 2630 // type. If so, convert to the packed type. 2631 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2632 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2633 RetTys.push_back(TVT); 2634 } else { 2635 assert(0 && "Don't support illegal by-val vector call results yet!"); 2636 abort(); 2637 } 2638 } 2639 } 2640 } 2641 2642 RetTys.push_back(MVT::Other); // Always has a chain. 2643 2644 // Finally, create the CALL node. 2645 SDOperand Res = DAG.getNode(ISD::CALL, 2646 DAG.getVTList(&RetTys[0], RetTys.size()), 2647 &Ops[0], Ops.size()); 2648 2649 // This returns a pair of operands. The first element is the 2650 // return value for the function (if RetTy is not VoidTy). The second 2651 // element is the outgoing token chain. 2652 SDOperand ResVal; 2653 if (RetTys.size() != 1) { 2654 MVT::ValueType VT = getValueType(RetTy); 2655 if (RetTys.size() == 2) { 2656 ResVal = Res; 2657 2658 // If this value was promoted, truncate it down. 2659 if (ResVal.getValueType() != VT) { 2660 if (VT == MVT::Vector) { 2661 // Insert a VBITCONVERT to convert from the packed result type to the 2662 // MVT::Vector type. 2663 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements(); 2664 const Type *EltTy = cast<PackedType>(RetTy)->getElementType(); 2665 2666 // Figure out if there is a Packed type corresponding to this Vector 2667 // type. If so, convert to the packed type. 2668 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2669 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2670 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a 2671 // "N x PTyElementVT" MVT::Vector type. 2672 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal, 2673 DAG.getConstant(NumElems, MVT::i32), 2674 DAG.getValueType(getValueType(EltTy))); 2675 } else { 2676 abort(); 2677 } 2678 } else if (MVT::isInteger(VT)) { 2679 unsigned AssertOp = RetTy->isSigned() ? 2680 ISD::AssertSext : ISD::AssertZext; 2681 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal, 2682 DAG.getValueType(VT)); 2683 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal); 2684 } else { 2685 assert(MVT::isFloatingPoint(VT)); 2686 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal); 2687 } 2688 } 2689 } else if (RetTys.size() == 3) { 2690 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT, 2691 Res.getValue(0), Res.getValue(1)); 2692 2693 } else { 2694 assert(0 && "Case not handled yet!"); 2695 } 2696 } 2697 2698 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1)); 2699} 2700 2701 2702 2703// It is always conservatively correct for llvm.returnaddress and 2704// llvm.frameaddress to return 0. 2705// 2706// FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be 2707// expanded to 0 if the target wants. 2708std::pair<SDOperand, SDOperand> 2709TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, 2710 unsigned Depth, SelectionDAG &DAG) { 2711 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain); 2712} 2713 2714SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 2715 assert(0 && "LowerOperation not implemented for this target!"); 2716 abort(); 2717 return SDOperand(); 2718} 2719 2720SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 2721 SelectionDAG &DAG) { 2722 assert(0 && "CustomPromoteOperation not implemented for this target!"); 2723 abort(); 2724 return SDOperand(); 2725} 2726 2727void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) { 2728 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue(); 2729 std::pair<SDOperand,SDOperand> Result = 2730 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG); 2731 setValue(&I, Result.first); 2732 DAG.setRoot(Result.second); 2733} 2734 2735/// getMemsetValue - Vectorized representation of the memset value 2736/// operand. 2737static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 2738 SelectionDAG &DAG) { 2739 MVT::ValueType CurVT = VT; 2740 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2741 uint64_t Val = C->getValue() & 255; 2742 unsigned Shift = 8; 2743 while (CurVT != MVT::i8) { 2744 Val = (Val << Shift) | Val; 2745 Shift <<= 1; 2746 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 2747 } 2748 return DAG.getConstant(Val, VT); 2749 } else { 2750 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 2751 unsigned Shift = 8; 2752 while (CurVT != MVT::i8) { 2753 Value = 2754 DAG.getNode(ISD::OR, VT, 2755 DAG.getNode(ISD::SHL, VT, Value, 2756 DAG.getConstant(Shift, MVT::i8)), Value); 2757 Shift <<= 1; 2758 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 2759 } 2760 2761 return Value; 2762 } 2763} 2764 2765/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2766/// used when a memcpy is turned into a memset when the source is a constant 2767/// string ptr. 2768static SDOperand getMemsetStringVal(MVT::ValueType VT, 2769 SelectionDAG &DAG, TargetLowering &TLI, 2770 std::string &Str, unsigned Offset) { 2771 MVT::ValueType CurVT = VT; 2772 uint64_t Val = 0; 2773 unsigned MSB = getSizeInBits(VT) / 8; 2774 if (TLI.isLittleEndian()) 2775 Offset = Offset + MSB - 1; 2776 for (unsigned i = 0; i != MSB; ++i) { 2777 Val = (Val << 8) | Str[Offset]; 2778 Offset += TLI.isLittleEndian() ? -1 : 1; 2779 } 2780 return DAG.getConstant(Val, VT); 2781} 2782 2783/// getMemBasePlusOffset - Returns base and offset node for the 2784static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 2785 SelectionDAG &DAG, TargetLowering &TLI) { 2786 MVT::ValueType VT = Base.getValueType(); 2787 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 2788} 2789 2790/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2791/// to replace the memset / memcpy is below the threshold. It also returns the 2792/// types of the sequence of memory ops to perform memset / memcpy. 2793static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 2794 unsigned Limit, uint64_t Size, 2795 unsigned Align, TargetLowering &TLI) { 2796 MVT::ValueType VT; 2797 2798 if (TLI.allowsUnalignedMemoryAccesses()) { 2799 VT = MVT::i64; 2800 } else { 2801 switch (Align & 7) { 2802 case 0: 2803 VT = MVT::i64; 2804 break; 2805 case 4: 2806 VT = MVT::i32; 2807 break; 2808 case 2: 2809 VT = MVT::i16; 2810 break; 2811 default: 2812 VT = MVT::i8; 2813 break; 2814 } 2815 } 2816 2817 MVT::ValueType LVT = MVT::i64; 2818 while (!TLI.isTypeLegal(LVT)) 2819 LVT = (MVT::ValueType)((unsigned)LVT - 1); 2820 assert(MVT::isInteger(LVT)); 2821 2822 if (VT > LVT) 2823 VT = LVT; 2824 2825 unsigned NumMemOps = 0; 2826 while (Size != 0) { 2827 unsigned VTSize = getSizeInBits(VT) / 8; 2828 while (VTSize > Size) { 2829 VT = (MVT::ValueType)((unsigned)VT - 1); 2830 VTSize >>= 1; 2831 } 2832 assert(MVT::isInteger(VT)); 2833 2834 if (++NumMemOps > Limit) 2835 return false; 2836 MemOps.push_back(VT); 2837 Size -= VTSize; 2838 } 2839 2840 return true; 2841} 2842 2843void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 2844 SDOperand Op1 = getValue(I.getOperand(1)); 2845 SDOperand Op2 = getValue(I.getOperand(2)); 2846 SDOperand Op3 = getValue(I.getOperand(3)); 2847 SDOperand Op4 = getValue(I.getOperand(4)); 2848 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 2849 if (Align == 0) Align = 1; 2850 2851 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 2852 std::vector<MVT::ValueType> MemOps; 2853 2854 // Expand memset / memcpy to a series of load / store ops 2855 // if the size operand falls below a certain threshold. 2856 SmallVector<SDOperand, 8> OutChains; 2857 switch (Op) { 2858 default: break; // Do nothing for now. 2859 case ISD::MEMSET: { 2860 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 2861 Size->getValue(), Align, TLI)) { 2862 unsigned NumMemOps = MemOps.size(); 2863 unsigned Offset = 0; 2864 for (unsigned i = 0; i < NumMemOps; i++) { 2865 MVT::ValueType VT = MemOps[i]; 2866 unsigned VTSize = getSizeInBits(VT) / 8; 2867 SDOperand Value = getMemsetValue(Op2, VT, DAG); 2868 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(), 2869 Value, 2870 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 2871 DAG.getSrcValue(I.getOperand(1), Offset)); 2872 OutChains.push_back(Store); 2873 Offset += VTSize; 2874 } 2875 } 2876 break; 2877 } 2878 case ISD::MEMCPY: { 2879 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 2880 Size->getValue(), Align, TLI)) { 2881 unsigned NumMemOps = MemOps.size(); 2882 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 2883 GlobalAddressSDNode *G = NULL; 2884 std::string Str; 2885 bool CopyFromStr = false; 2886 2887 if (Op2.getOpcode() == ISD::GlobalAddress) 2888 G = cast<GlobalAddressSDNode>(Op2); 2889 else if (Op2.getOpcode() == ISD::ADD && 2890 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 2891 Op2.getOperand(1).getOpcode() == ISD::Constant) { 2892 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 2893 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 2894 } 2895 if (G) { 2896 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2897 if (GV) { 2898 Str = GV->getStringValue(false); 2899 if (!Str.empty()) { 2900 CopyFromStr = true; 2901 SrcOff += SrcDelta; 2902 } 2903 } 2904 } 2905 2906 for (unsigned i = 0; i < NumMemOps; i++) { 2907 MVT::ValueType VT = MemOps[i]; 2908 unsigned VTSize = getSizeInBits(VT) / 8; 2909 SDOperand Value, Chain, Store; 2910 2911 if (CopyFromStr) { 2912 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 2913 Chain = getRoot(); 2914 Store = 2915 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, 2916 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 2917 DAG.getSrcValue(I.getOperand(1), DstOff)); 2918 } else { 2919 Value = DAG.getLoad(VT, getRoot(), 2920 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 2921 DAG.getSrcValue(I.getOperand(2), SrcOff)); 2922 Chain = Value.getValue(1); 2923 Store = 2924 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, 2925 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 2926 DAG.getSrcValue(I.getOperand(1), DstOff)); 2927 } 2928 OutChains.push_back(Store); 2929 SrcOff += VTSize; 2930 DstOff += VTSize; 2931 } 2932 } 2933 break; 2934 } 2935 } 2936 2937 if (!OutChains.empty()) { 2938 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 2939 &OutChains[0], OutChains.size())); 2940 return; 2941 } 2942 } 2943 2944 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4)); 2945} 2946 2947//===----------------------------------------------------------------------===// 2948// SelectionDAGISel code 2949//===----------------------------------------------------------------------===// 2950 2951unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 2952 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 2953} 2954 2955void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 2956 // FIXME: we only modify the CFG to split critical edges. This 2957 // updates dom and loop info. 2958} 2959 2960 2961/// OptimizeNoopCopyExpression - We have determined that the specified cast 2962/// instruction is a noop copy (e.g. it's casting from one pointer type to 2963/// another, int->uint, or int->sbyte on PPC. 2964/// 2965/// Return true if any changes are made. 2966static bool OptimizeNoopCopyExpression(CastInst *CI) { 2967 BasicBlock *DefBB = CI->getParent(); 2968 2969 /// InsertedCasts - Only insert a cast in each block once. 2970 std::map<BasicBlock*, CastInst*> InsertedCasts; 2971 2972 bool MadeChange = false; 2973 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end(); 2974 UI != E; ) { 2975 Use &TheUse = UI.getUse(); 2976 Instruction *User = cast<Instruction>(*UI); 2977 2978 // Figure out which BB this cast is used in. For PHI's this is the 2979 // appropriate predecessor block. 2980 BasicBlock *UserBB = User->getParent(); 2981 if (PHINode *PN = dyn_cast<PHINode>(User)) { 2982 unsigned OpVal = UI.getOperandNo()/2; 2983 UserBB = PN->getIncomingBlock(OpVal); 2984 } 2985 2986 // Preincrement use iterator so we don't invalidate it. 2987 ++UI; 2988 2989 // If this user is in the same block as the cast, don't change the cast. 2990 if (UserBB == DefBB) continue; 2991 2992 // If we have already inserted a cast into this block, use it. 2993 CastInst *&InsertedCast = InsertedCasts[UserBB]; 2994 2995 if (!InsertedCast) { 2996 BasicBlock::iterator InsertPt = UserBB->begin(); 2997 while (isa<PHINode>(InsertPt)) ++InsertPt; 2998 2999 InsertedCast = 3000 new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt); 3001 MadeChange = true; 3002 } 3003 3004 // Replace a use of the cast with a use of the new casat. 3005 TheUse = InsertedCast; 3006 } 3007 3008 // If we removed all uses, nuke the cast. 3009 if (CI->use_empty()) 3010 CI->eraseFromParent(); 3011 3012 return MadeChange; 3013} 3014 3015/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset, 3016/// casting to the type of GEPI. 3017static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB, 3018 Instruction *GEPI, Value *Ptr, 3019 Value *PtrOffset) { 3020 if (V) return V; // Already computed. 3021 3022 BasicBlock::iterator InsertPt; 3023 if (BB == GEPI->getParent()) { 3024 // If insert into the GEP's block, insert right after the GEP. 3025 InsertPt = GEPI; 3026 ++InsertPt; 3027 } else { 3028 // Otherwise, insert at the top of BB, after any PHI nodes 3029 InsertPt = BB->begin(); 3030 while (isa<PHINode>(InsertPt)) ++InsertPt; 3031 } 3032 3033 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into 3034 // BB so that there is only one value live across basic blocks (the cast 3035 // operand). 3036 if (CastInst *CI = dyn_cast<CastInst>(Ptr)) 3037 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType())) 3038 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt); 3039 3040 // Add the offset, cast it to the right type. 3041 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt); 3042 return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt); 3043} 3044 3045/// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to 3046/// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One 3047/// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's 3048/// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to 3049/// sink PtrOffset into user blocks where doing so will likely allow us to fold 3050/// the constant add into a load or store instruction. Additionally, if a user 3051/// is a pointer-pointer cast, we look through it to find its users. 3052static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr, 3053 Constant *PtrOffset, BasicBlock *DefBB, 3054 GetElementPtrInst *GEPI, 3055 std::map<BasicBlock*,Instruction*> &InsertedExprs) { 3056 while (!RepPtr->use_empty()) { 3057 Instruction *User = cast<Instruction>(RepPtr->use_back()); 3058 3059 // If the user is a Pointer-Pointer cast, recurse. 3060 if (isa<CastInst>(User) && isa<PointerType>(User->getType())) { 3061 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs); 3062 3063 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we 3064 // could invalidate an iterator. 3065 User->setOperand(0, UndefValue::get(RepPtr->getType())); 3066 continue; 3067 } 3068 3069 // If this is a load of the pointer, or a store through the pointer, emit 3070 // the increment into the load/store block. 3071 Instruction *NewVal; 3072 if (isa<LoadInst>(User) || 3073 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) { 3074 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()], 3075 User->getParent(), GEPI, 3076 Ptr, PtrOffset); 3077 } else { 3078 // If this use is not foldable into the addressing mode, use a version 3079 // emitted in the GEP block. 3080 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI, 3081 Ptr, PtrOffset); 3082 } 3083 3084 if (GEPI->getType() != RepPtr->getType()) { 3085 BasicBlock::iterator IP = NewVal; 3086 ++IP; 3087 NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP); 3088 } 3089 User->replaceUsesOfWith(RepPtr, NewVal); 3090 } 3091} 3092 3093 3094/// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction 3095/// selection, we want to be a bit careful about some things. In particular, if 3096/// we have a GEP instruction that is used in a different block than it is 3097/// defined, the addressing expression of the GEP cannot be folded into loads or 3098/// stores that use it. In this case, decompose the GEP and move constant 3099/// indices into blocks that use it. 3100static bool OptimizeGEPExpression(GetElementPtrInst *GEPI, 3101 const TargetData *TD) { 3102 // If this GEP is only used inside the block it is defined in, there is no 3103 // need to rewrite it. 3104 bool isUsedOutsideDefBB = false; 3105 BasicBlock *DefBB = GEPI->getParent(); 3106 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end(); 3107 UI != E; ++UI) { 3108 if (cast<Instruction>(*UI)->getParent() != DefBB) { 3109 isUsedOutsideDefBB = true; 3110 break; 3111 } 3112 } 3113 if (!isUsedOutsideDefBB) return false; 3114 3115 // If this GEP has no non-zero constant indices, there is nothing we can do, 3116 // ignore it. 3117 bool hasConstantIndex = false; 3118 bool hasVariableIndex = false; 3119 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1, 3120 E = GEPI->op_end(); OI != E; ++OI) { 3121 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) { 3122 if (CI->getRawValue()) { 3123 hasConstantIndex = true; 3124 break; 3125 } 3126 } else { 3127 hasVariableIndex = true; 3128 } 3129 } 3130 3131 // If this is a "GEP X, 0, 0, 0", turn this into a cast. 3132 if (!hasConstantIndex && !hasVariableIndex) { 3133 Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(), 3134 GEPI->getName(), GEPI); 3135 GEPI->replaceAllUsesWith(NC); 3136 GEPI->eraseFromParent(); 3137 return true; 3138 } 3139 3140 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses. 3141 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0))) 3142 return false; 3143 3144 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the 3145 // constant offset (which we now know is non-zero) and deal with it later. 3146 uint64_t ConstantOffset = 0; 3147 const Type *UIntPtrTy = TD->getIntPtrType(); 3148 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI); 3149 const Type *Ty = GEPI->getOperand(0)->getType(); 3150 3151 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1, 3152 E = GEPI->op_end(); OI != E; ++OI) { 3153 Value *Idx = *OI; 3154 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 3155 unsigned Field = cast<ConstantUInt>(Idx)->getValue(); 3156 if (Field) 3157 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field]; 3158 Ty = StTy->getElementType(Field); 3159 } else { 3160 Ty = cast<SequentialType>(Ty)->getElementType(); 3161 3162 // Handle constant subscripts. 3163 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3164 if (CI->getRawValue() == 0) continue; 3165 3166 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI)) 3167 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue(); 3168 else 3169 ConstantOffset+=TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue(); 3170 continue; 3171 } 3172 3173 // Ptr = Ptr + Idx * ElementSize; 3174 3175 // Cast Idx to UIntPtrTy if needed. 3176 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI); 3177 3178 uint64_t ElementSize = TD->getTypeSize(Ty); 3179 // Mask off bits that should not be set. 3180 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits()); 3181 Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize); 3182 3183 // Multiply by the element size and add to the base. 3184 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI); 3185 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI); 3186 } 3187 } 3188 3189 // Make sure that the offset fits in uintptr_t. 3190 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits()); 3191 Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset); 3192 3193 // Okay, we have now emitted all of the variable index parts to the BB that 3194 // the GEP is defined in. Loop over all of the using instructions, inserting 3195 // an "add Ptr, ConstantOffset" into each block that uses it and update the 3196 // instruction to use the newly computed value, making GEPI dead. When the 3197 // user is a load or store instruction address, we emit the add into the user 3198 // block, otherwise we use a canonical version right next to the gep (these 3199 // won't be foldable as addresses, so we might as well share the computation). 3200 3201 std::map<BasicBlock*,Instruction*> InsertedExprs; 3202 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs); 3203 3204 // Finally, the GEP is dead, remove it. 3205 GEPI->eraseFromParent(); 3206 3207 return true; 3208} 3209 3210bool SelectionDAGISel::runOnFunction(Function &Fn) { 3211 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 3212 RegMap = MF.getSSARegMap(); 3213 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n"); 3214 3215 // First, split all critical edges for PHI nodes with incoming values that are 3216 // constants, this way the load of the constant into a vreg will not be placed 3217 // into MBBs that are used some other way. 3218 // 3219 // In this pass we also look for GEP and cast instructions that are used 3220 // across basic blocks and rewrite them to improve basic-block-at-a-time 3221 // selection. 3222 // 3223 // 3224 bool MadeChange = true; 3225 while (MadeChange) { 3226 MadeChange = false; 3227 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 3228 PHINode *PN; 3229 BasicBlock::iterator BBI; 3230 for (BBI = BB->begin(); (PN = dyn_cast<PHINode>(BBI)); ++BBI) 3231 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) 3232 if (isa<Constant>(PN->getIncomingValue(i))) 3233 SplitCriticalEdge(PN->getIncomingBlock(i), BB); 3234 3235 for (BasicBlock::iterator E = BB->end(); BBI != E; ) { 3236 Instruction *I = BBI++; 3237 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) { 3238 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData()); 3239 } else if (CastInst *CI = dyn_cast<CastInst>(I)) { 3240 // If this is a noop copy, sink it into user blocks to reduce the number 3241 // of virtual registers that must be created and coallesced. 3242 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType()); 3243 MVT::ValueType DstVT = TLI.getValueType(CI->getType()); 3244 3245 // This is an fp<->int conversion? 3246 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT)) 3247 continue; 3248 3249 // If this is an extension, it will be a zero or sign extension, which 3250 // isn't a noop. 3251 if (SrcVT < DstVT) continue; 3252 3253 // If these values will be promoted, find out what they will be promoted 3254 // to. This helps us consider truncates on PPC as noop copies when they 3255 // are. 3256 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) 3257 SrcVT = TLI.getTypeToTransformTo(SrcVT); 3258 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote) 3259 DstVT = TLI.getTypeToTransformTo(DstVT); 3260 3261 // If, after promotion, these are the same types, this is a noop copy. 3262 if (SrcVT == DstVT) 3263 MadeChange |= OptimizeNoopCopyExpression(CI); 3264 } 3265 } 3266 } 3267 } 3268 3269 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 3270 3271 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 3272 SelectBasicBlock(I, MF, FuncInfo); 3273 3274 return true; 3275} 3276 3277 3278SDOperand SelectionDAGISel:: 3279CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) { 3280 SDOperand Op = SDL.getValue(V); 3281 assert((Op.getOpcode() != ISD::CopyFromReg || 3282 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 3283 "Copy from a reg to the same reg!"); 3284 3285 // If this type is not legal, we must make sure to not create an invalid 3286 // register use. 3287 MVT::ValueType SrcVT = Op.getValueType(); 3288 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT); 3289 SelectionDAG &DAG = SDL.DAG; 3290 if (SrcVT == DestVT) { 3291 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op); 3292 } else if (SrcVT == MVT::Vector) { 3293 // Handle copies from generic vectors to registers. 3294 MVT::ValueType PTyElementVT, PTyLegalElementVT; 3295 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()), 3296 PTyElementVT, PTyLegalElementVT); 3297 3298 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT" 3299 // MVT::Vector type. 3300 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op, 3301 DAG.getConstant(NE, MVT::i32), 3302 DAG.getValueType(PTyElementVT)); 3303 3304 // Loop over all of the elements of the resultant vector, 3305 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then 3306 // copying them into output registers. 3307 SmallVector<SDOperand, 8> OutChains; 3308 SDOperand Root = SDL.getRoot(); 3309 for (unsigned i = 0; i != NE; ++i) { 3310 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT, 3311 Op, DAG.getConstant(i, TLI.getPointerTy())); 3312 if (PTyElementVT == PTyLegalElementVT) { 3313 // Elements are legal. 3314 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); 3315 } else if (PTyLegalElementVT > PTyElementVT) { 3316 // Elements are promoted. 3317 if (MVT::isFloatingPoint(PTyLegalElementVT)) 3318 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt); 3319 else 3320 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt); 3321 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); 3322 } else { 3323 // Elements are expanded. 3324 // The src value is expanded into multiple registers. 3325 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, 3326 Elt, DAG.getConstant(0, TLI.getPointerTy())); 3327 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, 3328 Elt, DAG.getConstant(1, TLI.getPointerTy())); 3329 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo)); 3330 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi)); 3331 } 3332 } 3333 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3334 &OutChains[0], OutChains.size()); 3335 } else if (SrcVT < DestVT) { 3336 // The src value is promoted to the register. 3337 if (MVT::isFloatingPoint(SrcVT)) 3338 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op); 3339 else 3340 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op); 3341 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op); 3342 } else { 3343 // The src value is expanded into multiple registers. 3344 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 3345 Op, DAG.getConstant(0, TLI.getPointerTy())); 3346 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 3347 Op, DAG.getConstant(1, TLI.getPointerTy())); 3348 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo); 3349 return DAG.getCopyToReg(Op, Reg+1, Hi); 3350 } 3351} 3352 3353void SelectionDAGISel:: 3354LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL, 3355 std::vector<SDOperand> &UnorderedChains) { 3356 // If this is the entry block, emit arguments. 3357 Function &F = *BB->getParent(); 3358 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 3359 SDOperand OldRoot = SDL.DAG.getRoot(); 3360 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 3361 3362 unsigned a = 0; 3363 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 3364 AI != E; ++AI, ++a) 3365 if (!AI->use_empty()) { 3366 SDL.setValue(AI, Args[a]); 3367 3368 // If this argument is live outside of the entry block, insert a copy from 3369 // whereever we got it to the vreg that other BB's will reference it as. 3370 if (FuncInfo.ValueMap.count(AI)) { 3371 SDOperand Copy = 3372 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]); 3373 UnorderedChains.push_back(Copy); 3374 } 3375 } 3376 3377 // Finally, if the target has anything special to do, allow it to do so. 3378 // FIXME: this should insert code into the DAG! 3379 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 3380} 3381 3382void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 3383 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 3384 FunctionLoweringInfo &FuncInfo) { 3385 SelectionDAGLowering SDL(DAG, TLI, FuncInfo); 3386 3387 std::vector<SDOperand> UnorderedChains; 3388 3389 // Lower any arguments needed in this block if this is the entry block. 3390 if (LLVMBB == &LLVMBB->getParent()->front()) 3391 LowerArguments(LLVMBB, SDL, UnorderedChains); 3392 3393 BB = FuncInfo.MBBMap[LLVMBB]; 3394 SDL.setCurrentBasicBlock(BB); 3395 3396 // Lower all of the non-terminator instructions. 3397 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 3398 I != E; ++I) 3399 SDL.visit(*I); 3400 3401 // Ensure that all instructions which are used outside of their defining 3402 // blocks are available as virtual registers. 3403 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 3404 if (!I->use_empty() && !isa<PHINode>(I)) { 3405 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 3406 if (VMI != FuncInfo.ValueMap.end()) 3407 UnorderedChains.push_back( 3408 CopyValueToVirtualRegister(SDL, I, VMI->second)); 3409 } 3410 3411 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 3412 // ensure constants are generated when needed. Remember the virtual registers 3413 // that need to be added to the Machine PHI nodes as input. We cannot just 3414 // directly add them, because expansion might result in multiple MBB's for one 3415 // BB. As such, the start of the BB might correspond to a different MBB than 3416 // the end. 3417 // 3418 3419 // Emit constants only once even if used by multiple PHI nodes. 3420 std::map<Constant*, unsigned> ConstantsOut; 3421 3422 // Check successor nodes PHI nodes that expect a constant to be available from 3423 // this block. 3424 TerminatorInst *TI = LLVMBB->getTerminator(); 3425 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 3426 BasicBlock *SuccBB = TI->getSuccessor(succ); 3427 if (!isa<PHINode>(SuccBB->begin())) continue; 3428 3429 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin(); 3430 PHINode *PN; 3431 3432 // At this point we know that there is a 1-1 correspondence between LLVM PHI 3433 // nodes and Machine PHI nodes, but the incoming operands have not been 3434 // emitted yet. 3435 for (BasicBlock::iterator I = SuccBB->begin(); 3436 (PN = dyn_cast<PHINode>(I)); ++I) 3437 if (!PN->use_empty()) { 3438 unsigned Reg; 3439 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 3440 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 3441 unsigned &RegOut = ConstantsOut[C]; 3442 if (RegOut == 0) { 3443 RegOut = FuncInfo.CreateRegForValue(C); 3444 UnorderedChains.push_back( 3445 CopyValueToVirtualRegister(SDL, C, RegOut)); 3446 } 3447 Reg = RegOut; 3448 } else { 3449 Reg = FuncInfo.ValueMap[PHIOp]; 3450 if (Reg == 0) { 3451 assert(isa<AllocaInst>(PHIOp) && 3452 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 3453 "Didn't codegen value into a register!??"); 3454 Reg = FuncInfo.CreateRegForValue(PHIOp); 3455 UnorderedChains.push_back( 3456 CopyValueToVirtualRegister(SDL, PHIOp, Reg)); 3457 } 3458 } 3459 3460 // Remember that this register needs to added to the machine PHI node as 3461 // the input for this MBB. 3462 MVT::ValueType VT = TLI.getValueType(PN->getType()); 3463 unsigned NumElements; 3464 if (VT != MVT::Vector) 3465 NumElements = TLI.getNumElements(VT); 3466 else { 3467 MVT::ValueType VT1,VT2; 3468 NumElements = 3469 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()), 3470 VT1, VT2); 3471 } 3472 for (unsigned i = 0, e = NumElements; i != e; ++i) 3473 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 3474 } 3475 } 3476 ConstantsOut.clear(); 3477 3478 // Turn all of the unordered chains into one factored node. 3479 if (!UnorderedChains.empty()) { 3480 SDOperand Root = SDL.getRoot(); 3481 if (Root.getOpcode() != ISD::EntryToken) { 3482 unsigned i = 0, e = UnorderedChains.size(); 3483 for (; i != e; ++i) { 3484 assert(UnorderedChains[i].Val->getNumOperands() > 1); 3485 if (UnorderedChains[i].Val->getOperand(0) == Root) 3486 break; // Don't add the root if we already indirectly depend on it. 3487 } 3488 3489 if (i == e) 3490 UnorderedChains.push_back(Root); 3491 } 3492 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 3493 &UnorderedChains[0], UnorderedChains.size())); 3494 } 3495 3496 // Lower the terminator after the copies are emitted. 3497 SDL.visit(*LLVMBB->getTerminator()); 3498 3499 // Copy over any CaseBlock records that may now exist due to SwitchInst 3500 // lowering, as well as any jump table information. 3501 SwitchCases.clear(); 3502 SwitchCases = SDL.SwitchCases; 3503 JT = SDL.JT; 3504 3505 // Make sure the root of the DAG is up-to-date. 3506 DAG.setRoot(SDL.getRoot()); 3507} 3508 3509void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 3510 // Run the DAG combiner in pre-legalize mode. 3511 DAG.Combine(false); 3512 3513 DEBUG(std::cerr << "Lowered selection DAG:\n"); 3514 DEBUG(DAG.dump()); 3515 3516 // Second step, hack on the DAG until it only uses operations and types that 3517 // the target supports. 3518 DAG.Legalize(); 3519 3520 DEBUG(std::cerr << "Legalized selection DAG:\n"); 3521 DEBUG(DAG.dump()); 3522 3523 // Run the DAG combiner in post-legalize mode. 3524 DAG.Combine(true); 3525 3526 if (ViewISelDAGs) DAG.viewGraph(); 3527 3528 // Third, instruction select all of the operations to machine code, adding the 3529 // code to the MachineBasicBlock. 3530 InstructionSelectBasicBlock(DAG); 3531 3532 DEBUG(std::cerr << "Selected machine code:\n"); 3533 DEBUG(BB->dump()); 3534} 3535 3536void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 3537 FunctionLoweringInfo &FuncInfo) { 3538 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 3539 { 3540 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>()); 3541 CurDAG = &DAG; 3542 3543 // First step, lower LLVM code to some DAG. This DAG may use operations and 3544 // types that are not supported by the target. 3545 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 3546 3547 // Second step, emit the lowered DAG as machine code. 3548 CodeGenAndEmitDAG(DAG); 3549 } 3550 3551 // Next, now that we know what the last MBB the LLVM BB expanded is, update 3552 // PHI nodes in successors. 3553 if (SwitchCases.empty() && JT.Reg == 0) { 3554 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 3555 MachineInstr *PHI = PHINodesToUpdate[i].first; 3556 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 3557 "This is not a machine PHI node that we are updating!"); 3558 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 3559 PHI->addMachineBasicBlockOperand(BB); 3560 } 3561 return; 3562 } 3563 3564 // If the JumpTable record is filled in, then we need to emit a jump table. 3565 // Updating the PHI nodes is tricky in this case, since we need to determine 3566 // whether the PHI is a successor of the range check MBB or the jump table MBB 3567 if (JT.Reg) { 3568 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch"); 3569 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>()); 3570 CurDAG = &SDAG; 3571 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 3572 MachineBasicBlock *RangeBB = BB; 3573 // Set the current basic block to the mbb we wish to insert the code into 3574 BB = JT.MBB; 3575 SDL.setCurrentBasicBlock(BB); 3576 // Emit the code 3577 SDL.visitJumpTable(JT); 3578 SDAG.setRoot(SDL.getRoot()); 3579 CodeGenAndEmitDAG(SDAG); 3580 // Update PHI Nodes 3581 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 3582 MachineInstr *PHI = PHINodesToUpdate[pi].first; 3583 MachineBasicBlock *PHIBB = PHI->getParent(); 3584 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 3585 "This is not a machine PHI node that we are updating!"); 3586 if (PHIBB == JT.Default) { 3587 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 3588 PHI->addMachineBasicBlockOperand(RangeBB); 3589 } 3590 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 3591 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 3592 PHI->addMachineBasicBlockOperand(BB); 3593 } 3594 } 3595 return; 3596 } 3597 3598 // If we generated any switch lowering information, build and codegen any 3599 // additional DAGs necessary. 3600 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 3601 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>()); 3602 CurDAG = &SDAG; 3603 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 3604 3605 // Set the current basic block to the mbb we wish to insert the code into 3606 BB = SwitchCases[i].ThisBB; 3607 SDL.setCurrentBasicBlock(BB); 3608 3609 // Emit the code 3610 SDL.visitSwitchCase(SwitchCases[i]); 3611 SDAG.setRoot(SDL.getRoot()); 3612 CodeGenAndEmitDAG(SDAG); 3613 3614 // Handle any PHI nodes in successors of this chunk, as if we were coming 3615 // from the original BB before switch expansion. Note that PHI nodes can 3616 // occur multiple times in PHINodesToUpdate. We have to be very careful to 3617 // handle them the right number of times. 3618 while ((BB = SwitchCases[i].LHSBB)) { // Handle LHS and RHS. 3619 for (MachineBasicBlock::iterator Phi = BB->begin(); 3620 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 3621 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 3622 for (unsigned pn = 0; ; ++pn) { 3623 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 3624 if (PHINodesToUpdate[pn].first == Phi) { 3625 Phi->addRegOperand(PHINodesToUpdate[pn].second, false); 3626 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB); 3627 break; 3628 } 3629 } 3630 } 3631 3632 // Don't process RHS if same block as LHS. 3633 if (BB == SwitchCases[i].RHSBB) 3634 SwitchCases[i].RHSBB = 0; 3635 3636 // If we haven't handled the RHS, do so now. Otherwise, we're done. 3637 SwitchCases[i].LHSBB = SwitchCases[i].RHSBB; 3638 SwitchCases[i].RHSBB = 0; 3639 } 3640 assert(SwitchCases[i].LHSBB == 0 && SwitchCases[i].RHSBB == 0); 3641 } 3642} 3643 3644 3645//===----------------------------------------------------------------------===// 3646/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 3647/// target node in the graph. 3648void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 3649 if (ViewSchedDAGs) DAG.viewGraph(); 3650 3651 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 3652 3653 if (!Ctor) { 3654 Ctor = ISHeuristic; 3655 RegisterScheduler::setDefault(Ctor); 3656 } 3657 3658 ScheduleDAG *SL = Ctor(this, &DAG, BB); 3659 BB = SL->Run(); 3660 delete SL; 3661} 3662 3663 3664HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 3665 return new HazardRecognizer(); 3666} 3667 3668 3669/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 3670/// by tblgen. Others should not call it. 3671void SelectionDAGISel:: 3672SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 3673 std::vector<SDOperand> InOps; 3674 std::swap(InOps, Ops); 3675 3676 Ops.push_back(InOps[0]); // input chain. 3677 Ops.push_back(InOps[1]); // input asm string. 3678 3679 unsigned i = 2, e = InOps.size(); 3680 if (InOps[e-1].getValueType() == MVT::Flag) 3681 --e; // Don't process a flag operand if it is here. 3682 3683 while (i != e) { 3684 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 3685 if ((Flags & 7) != 4 /*MEM*/) { 3686 // Just skip over this operand, copying the operands verbatim. 3687 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 3688 i += (Flags >> 3) + 1; 3689 } else { 3690 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 3691 // Otherwise, this is a memory operand. Ask the target to select it. 3692 std::vector<SDOperand> SelOps; 3693 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 3694 std::cerr << "Could not match memory address. Inline asm failure!\n"; 3695 exit(1); 3696 } 3697 3698 // Add this to the output node. 3699 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32)); 3700 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 3701 i += 2; 3702 } 3703 } 3704 3705 // Add the flag input back if present. 3706 if (e != InOps.size()) 3707 Ops.push_back(InOps.back()); 3708} 3709