SelectionDAGISel.cpp revision 6f498b0a8eeb69a9aa20319e2c803b1d58525547
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/Collector.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetData.h" 40#include "llvm/Target/TargetFrameInfo.h" 41#include "llvm/Target/TargetInstrInfo.h" 42#include "llvm/Target/TargetLowering.h" 43#include "llvm/Target/TargetMachine.h" 44#include "llvm/Target/TargetOptions.h" 45#include "llvm/Support/Compiler.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/MathExtras.h" 48#include "llvm/Support/Timer.h" 49#include <algorithm> 50using namespace llvm; 51 52static cl::opt<bool> 53EnableValueProp("enable-value-prop", cl::Hidden); 54static cl::opt<bool> 55EnableLegalizeTypes("enable-legalize-types", cl::Hidden); 56 57 58#ifndef NDEBUG 59static cl::opt<bool> 60ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 61 cl::desc("Pop up a window to show dags before the first " 62 "dag combine pass")); 63static cl::opt<bool> 64ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 65 cl::desc("Pop up a window to show dags before legalize types")); 66static cl::opt<bool> 67ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 68 cl::desc("Pop up a window to show dags before legalize")); 69static cl::opt<bool> 70ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 71 cl::desc("Pop up a window to show dags before the second " 72 "dag combine pass")); 73static cl::opt<bool> 74ViewISelDAGs("view-isel-dags", cl::Hidden, 75 cl::desc("Pop up a window to show isel dags as they are selected")); 76static cl::opt<bool> 77ViewSchedDAGs("view-sched-dags", cl::Hidden, 78 cl::desc("Pop up a window to show sched dags as they are processed")); 79static cl::opt<bool> 80ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 81 cl::desc("Pop up a window to show SUnit dags after they are processed")); 82#else 83static const bool ViewDAGCombine1 = false, 84 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 85 ViewDAGCombine2 = false, 86 ViewISelDAGs = false, ViewSchedDAGs = false, 87 ViewSUnitDAGs = false; 88#endif 89 90//===---------------------------------------------------------------------===// 91/// 92/// RegisterScheduler class - Track the registration of instruction schedulers. 93/// 94//===---------------------------------------------------------------------===// 95MachinePassRegistry RegisterScheduler::Registry; 96 97//===---------------------------------------------------------------------===// 98/// 99/// ISHeuristic command line option for instruction schedulers. 100/// 101//===---------------------------------------------------------------------===// 102static cl::opt<RegisterScheduler::FunctionPassCtor, false, 103 RegisterPassParser<RegisterScheduler> > 104ISHeuristic("pre-RA-sched", 105 cl::init(&createDefaultScheduler), 106 cl::desc("Instruction schedulers available (before register" 107 " allocation):")); 108 109static RegisterScheduler 110defaultListDAGScheduler("default", " Best scheduler for the target", 111 createDefaultScheduler); 112 113namespace { struct SDISelAsmOperandInfo; } 114 115/// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence 116/// insertvalue or extractvalue indices that identify a member, return 117/// the linearized index of the start of the member. 118/// 119static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty, 120 const unsigned *Indices, 121 const unsigned *IndicesEnd, 122 unsigned CurIndex = 0) { 123 // Base case: We're done. 124 if (Indices && Indices == IndicesEnd) 125 return CurIndex; 126 127 // Given a struct type, recursively traverse the elements. 128 if (const StructType *STy = dyn_cast<StructType>(Ty)) { 129 for (StructType::element_iterator EB = STy->element_begin(), 130 EI = EB, 131 EE = STy->element_end(); 132 EI != EE; ++EI) { 133 if (Indices && *Indices == unsigned(EI - EB)) 134 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex); 135 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex); 136 } 137 } 138 // Given an array type, recursively traverse the elements. 139 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 140 const Type *EltTy = ATy->getElementType(); 141 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) { 142 if (Indices && *Indices == i) 143 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex); 144 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex); 145 } 146 } 147 // We haven't found the type we're looking for, so keep searching. 148 return CurIndex + 1; 149} 150 151/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of 152/// MVTs that represent all the individual underlying 153/// non-aggregate types that comprise it. 154/// 155/// If Offsets is non-null, it points to a vector to be filled in 156/// with the in-memory offsets of each of the individual values. 157/// 158static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty, 159 SmallVectorImpl<MVT> &ValueVTs, 160 SmallVectorImpl<uint64_t> *Offsets = 0, 161 uint64_t StartingOffset = 0) { 162 // Given a struct type, recursively traverse the elements. 163 if (const StructType *STy = dyn_cast<StructType>(Ty)) { 164 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy); 165 for (StructType::element_iterator EB = STy->element_begin(), 166 EI = EB, 167 EE = STy->element_end(); 168 EI != EE; ++EI) 169 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets, 170 StartingOffset + SL->getElementOffset(EI - EB)); 171 return; 172 } 173 // Given an array type, recursively traverse the elements. 174 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 175 const Type *EltTy = ATy->getElementType(); 176 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy); 177 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) 178 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets, 179 StartingOffset + i * EltSize); 180 return; 181 } 182 // Base case: we can get an MVT for this LLVM IR type. 183 ValueVTs.push_back(TLI.getValueType(Ty)); 184 if (Offsets) 185 Offsets->push_back(StartingOffset); 186} 187 188namespace { 189 /// RegsForValue - This struct represents the registers (physical or virtual) 190 /// that a particular set of values is assigned, and the type information about 191 /// the value. The most common situation is to represent one value at a time, 192 /// but struct or array values are handled element-wise as multiple values. 193 /// The splitting of aggregates is performed recursively, so that we never 194 /// have aggregate-typed registers. The values at this point do not necessarily 195 /// have legal types, so each value may require one or more registers of some 196 /// legal type. 197 /// 198 struct VISIBILITY_HIDDEN RegsForValue { 199 /// TLI - The TargetLowering object. 200 /// 201 const TargetLowering *TLI; 202 203 /// ValueVTs - The value types of the values, which may not be legal, and 204 /// may need be promoted or synthesized from one or more registers. 205 /// 206 SmallVector<MVT, 4> ValueVTs; 207 208 /// RegVTs - The value types of the registers. This is the same size as 209 /// ValueVTs and it records, for each value, what the type of the assigned 210 /// register or registers are. (Individual values are never synthesized 211 /// from more than one type of register.) 212 /// 213 /// With virtual registers, the contents of RegVTs is redundant with TLI's 214 /// getRegisterType member function, however when with physical registers 215 /// it is necessary to have a separate record of the types. 216 /// 217 SmallVector<MVT, 4> RegVTs; 218 219 /// Regs - This list holds the registers assigned to the values. 220 /// Each legal or promoted value requires one register, and each 221 /// expanded value requires multiple registers. 222 /// 223 SmallVector<unsigned, 4> Regs; 224 225 RegsForValue() : TLI(0) {} 226 227 RegsForValue(const TargetLowering &tli, 228 const SmallVector<unsigned, 4> ®s, 229 MVT regvt, MVT valuevt) 230 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 231 RegsForValue(const TargetLowering &tli, 232 const SmallVector<unsigned, 4> ®s, 233 const SmallVector<MVT, 4> ®vts, 234 const SmallVector<MVT, 4> &valuevts) 235 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {} 236 RegsForValue(const TargetLowering &tli, 237 unsigned Reg, const Type *Ty) : TLI(&tli) { 238 ComputeValueVTs(tli, Ty, ValueVTs); 239 240 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 241 MVT ValueVT = ValueVTs[Value]; 242 unsigned NumRegs = TLI->getNumRegisters(ValueVT); 243 MVT RegisterVT = TLI->getRegisterType(ValueVT); 244 for (unsigned i = 0; i != NumRegs; ++i) 245 Regs.push_back(Reg + i); 246 RegVTs.push_back(RegisterVT); 247 Reg += NumRegs; 248 } 249 } 250 251 /// append - Add the specified values to this one. 252 void append(const RegsForValue &RHS) { 253 TLI = RHS.TLI; 254 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 255 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 256 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 257 } 258 259 260 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 261 /// this value and returns the result as a ValueVTs value. This uses 262 /// Chain/Flag as the input and updates them for the output Chain/Flag. 263 /// If the Flag pointer is NULL, no flag is used. 264 SDValue getCopyFromRegs(SelectionDAG &DAG, 265 SDValue &Chain, SDValue *Flag) const; 266 267 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 268 /// specified value into the registers specified by this object. This uses 269 /// Chain/Flag as the input and updates them for the output Chain/Flag. 270 /// If the Flag pointer is NULL, no flag is used. 271 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, 272 SDValue &Chain, SDValue *Flag) const; 273 274 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 275 /// operand list. This adds the code marker and includes the number of 276 /// values added into it. 277 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 278 std::vector<SDValue> &Ops) const; 279 }; 280} 281 282namespace llvm { 283 //===--------------------------------------------------------------------===// 284 /// createDefaultScheduler - This creates an instruction scheduler appropriate 285 /// for the target. 286 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 287 SelectionDAG *DAG, 288 MachineBasicBlock *BB, 289 bool Fast) { 290 TargetLowering &TLI = IS->getTargetLowering(); 291 292 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 293 return createTDListDAGScheduler(IS, DAG, BB, Fast); 294 } else { 295 assert(TLI.getSchedulingPreference() == 296 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 297 return createBURRListDAGScheduler(IS, DAG, BB, Fast); 298 } 299 } 300 301 302 //===--------------------------------------------------------------------===// 303 /// FunctionLoweringInfo - This contains information that is global to a 304 /// function that is used when lowering a region of the function. 305 class FunctionLoweringInfo { 306 public: 307 TargetLowering &TLI; 308 Function &Fn; 309 MachineFunction &MF; 310 MachineRegisterInfo &RegInfo; 311 312 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 313 314 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 315 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 316 317 /// ValueMap - Since we emit code for the function a basic block at a time, 318 /// we must remember which virtual registers hold the values for 319 /// cross-basic-block values. 320 DenseMap<const Value*, unsigned> ValueMap; 321 322 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 323 /// the entry block. This allows the allocas to be efficiently referenced 324 /// anywhere in the function. 325 std::map<const AllocaInst*, int> StaticAllocaMap; 326 327#ifndef NDEBUG 328 SmallSet<Instruction*, 8> CatchInfoLost; 329 SmallSet<Instruction*, 8> CatchInfoFound; 330#endif 331 332 unsigned MakeReg(MVT VT) { 333 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT)); 334 } 335 336 /// isExportedInst - Return true if the specified value is an instruction 337 /// exported from its block. 338 bool isExportedInst(const Value *V) { 339 return ValueMap.count(V); 340 } 341 342 unsigned CreateRegForValue(const Value *V); 343 344 unsigned InitializeRegForValue(const Value *V) { 345 unsigned &R = ValueMap[V]; 346 assert(R == 0 && "Already initialized this value register!"); 347 return R = CreateRegForValue(V); 348 } 349 350 struct LiveOutInfo { 351 unsigned NumSignBits; 352 APInt KnownOne, KnownZero; 353 LiveOutInfo() : NumSignBits(0) {} 354 }; 355 356 /// LiveOutRegInfo - Information about live out vregs, indexed by their 357 /// register number offset by 'FirstVirtualRegister'. 358 std::vector<LiveOutInfo> LiveOutRegInfo; 359 }; 360} 361 362/// isSelector - Return true if this instruction is a call to the 363/// eh.selector intrinsic. 364static bool isSelector(Instruction *I) { 365 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 366 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 || 367 II->getIntrinsicID() == Intrinsic::eh_selector_i64); 368 return false; 369} 370 371/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 372/// PHI nodes or outside of the basic block that defines it, or used by a 373/// switch or atomic instruction, which may expand to multiple basic blocks. 374static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 375 if (isa<PHINode>(I)) return true; 376 BasicBlock *BB = I->getParent(); 377 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 378 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 379 // FIXME: Remove switchinst special case. 380 isa<SwitchInst>(*UI)) 381 return true; 382 return false; 383} 384 385/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 386/// entry block, return true. This includes arguments used by switches, since 387/// the switch may expand into multiple basic blocks. 388static bool isOnlyUsedInEntryBlock(Argument *A) { 389 BasicBlock *Entry = A->getParent()->begin(); 390 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 391 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 392 return false; // Use not in entry block. 393 return true; 394} 395 396FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 397 Function &fn, MachineFunction &mf) 398 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) { 399 400 // Create a vreg for each argument register that is not dead and is used 401 // outside of the entry block for the function. 402 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 403 AI != E; ++AI) 404 if (!isOnlyUsedInEntryBlock(AI)) 405 InitializeRegForValue(AI); 406 407 // Initialize the mapping of values to registers. This is only set up for 408 // instruction values that are used outside of the block that defines 409 // them. 410 Function::iterator BB = Fn.begin(), EB = Fn.end(); 411 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 412 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 413 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 414 const Type *Ty = AI->getAllocatedType(); 415 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 416 unsigned Align = 417 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 418 AI->getAlignment()); 419 420 TySize *= CUI->getZExtValue(); // Get total allocated size. 421 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 422 StaticAllocaMap[AI] = 423 MF.getFrameInfo()->CreateStackObject(TySize, Align); 424 } 425 426 for (; BB != EB; ++BB) 427 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 428 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 429 if (!isa<AllocaInst>(I) || 430 !StaticAllocaMap.count(cast<AllocaInst>(I))) 431 InitializeRegForValue(I); 432 433 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 434 // also creates the initial PHI MachineInstrs, though none of the input 435 // operands are populated. 436 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 437 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB); 438 MBBMap[BB] = MBB; 439 MF.push_back(MBB); 440 441 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 442 // appropriate. 443 PHINode *PN; 444 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 445 if (PN->use_empty()) continue; 446 447 unsigned PHIReg = ValueMap[PN]; 448 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 449 450 SmallVector<MVT, 4> ValueVTs; 451 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 452 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 453 MVT VT = ValueVTs[vti]; 454 unsigned NumRegisters = TLI.getNumRegisters(VT); 455 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 456 for (unsigned i = 0; i != NumRegisters; ++i) 457 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 458 PHIReg += NumRegisters; 459 } 460 } 461 } 462} 463 464/// CreateRegForValue - Allocate the appropriate number of virtual registers of 465/// the correctly promoted or expanded types. Assign these registers 466/// consecutive vreg numbers and return the first assigned number. 467/// 468/// In the case that the given value has struct or array type, this function 469/// will assign registers for each member or element. 470/// 471unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 472 SmallVector<MVT, 4> ValueVTs; 473 ComputeValueVTs(TLI, V->getType(), ValueVTs); 474 475 unsigned FirstReg = 0; 476 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 477 MVT ValueVT = ValueVTs[Value]; 478 MVT RegisterVT = TLI.getRegisterType(ValueVT); 479 480 unsigned NumRegs = TLI.getNumRegisters(ValueVT); 481 for (unsigned i = 0; i != NumRegs; ++i) { 482 unsigned R = MakeReg(RegisterVT); 483 if (!FirstReg) FirstReg = R; 484 } 485 } 486 return FirstReg; 487} 488 489//===----------------------------------------------------------------------===// 490/// SelectionDAGLowering - This is the common target-independent lowering 491/// implementation that is parameterized by a TargetLowering object. 492/// Also, targets can overload any lowering method. 493/// 494namespace llvm { 495class SelectionDAGLowering { 496 MachineBasicBlock *CurMBB; 497 498 DenseMap<const Value*, SDValue> NodeMap; 499 500 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 501 /// them up and then emit token factor nodes when possible. This allows us to 502 /// get simple disambiguation between loads without worrying about alias 503 /// analysis. 504 SmallVector<SDValue, 8> PendingLoads; 505 506 /// PendingExports - CopyToReg nodes that copy values to virtual registers 507 /// for export to other blocks need to be emitted before any terminator 508 /// instruction, but they have no other ordering requirements. We bunch them 509 /// up and the emit a single tokenfactor for them just before terminator 510 /// instructions. 511 std::vector<SDValue> PendingExports; 512 513 /// Case - A struct to record the Value for a switch case, and the 514 /// case's target basic block. 515 struct Case { 516 Constant* Low; 517 Constant* High; 518 MachineBasicBlock* BB; 519 520 Case() : Low(0), High(0), BB(0) { } 521 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 522 Low(low), High(high), BB(bb) { } 523 uint64_t size() const { 524 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 525 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 526 return (rHigh - rLow + 1ULL); 527 } 528 }; 529 530 struct CaseBits { 531 uint64_t Mask; 532 MachineBasicBlock* BB; 533 unsigned Bits; 534 535 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 536 Mask(mask), BB(bb), Bits(bits) { } 537 }; 538 539 typedef std::vector<Case> CaseVector; 540 typedef std::vector<CaseBits> CaseBitsVector; 541 typedef CaseVector::iterator CaseItr; 542 typedef std::pair<CaseItr, CaseItr> CaseRange; 543 544 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 545 /// of conditional branches. 546 struct CaseRec { 547 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 548 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 549 550 /// CaseBB - The MBB in which to emit the compare and branch 551 MachineBasicBlock *CaseBB; 552 /// LT, GE - If nonzero, we know the current case value must be less-than or 553 /// greater-than-or-equal-to these Constants. 554 Constant *LT; 555 Constant *GE; 556 /// Range - A pair of iterators representing the range of case values to be 557 /// processed at this point in the binary search tree. 558 CaseRange Range; 559 }; 560 561 typedef std::vector<CaseRec> CaseRecVector; 562 563 /// The comparison function for sorting the switch case values in the vector. 564 /// WARNING: Case ranges should be disjoint! 565 struct CaseCmp { 566 bool operator () (const Case& C1, const Case& C2) { 567 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 568 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 569 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 570 return CI1->getValue().slt(CI2->getValue()); 571 } 572 }; 573 574 struct CaseBitsCmp { 575 bool operator () (const CaseBits& C1, const CaseBits& C2) { 576 return C1.Bits > C2.Bits; 577 } 578 }; 579 580 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 581 582public: 583 // TLI - This is information that describes the available target features we 584 // need for lowering. This indicates when operations are unavailable, 585 // implemented with a libcall, etc. 586 TargetLowering &TLI; 587 SelectionDAG &DAG; 588 const TargetData *TD; 589 AliasAnalysis &AA; 590 591 /// SwitchCases - Vector of CaseBlock structures used to communicate 592 /// SwitchInst code generation information. 593 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 594 /// JTCases - Vector of JumpTable structures used to communicate 595 /// SwitchInst code generation information. 596 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 597 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 598 599 /// FuncInfo - Information about the function as a whole. 600 /// 601 FunctionLoweringInfo &FuncInfo; 602 603 /// GCI - Garbage collection metadata for the function. 604 CollectorMetadata *GCI; 605 606 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 607 AliasAnalysis &aa, 608 FunctionLoweringInfo &funcinfo, 609 CollectorMetadata *gci) 610 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa), 611 FuncInfo(funcinfo), GCI(gci) { 612 } 613 614 /// getRoot - Return the current virtual root of the Selection DAG, 615 /// flushing any PendingLoad items. This must be done before emitting 616 /// a store or any other node that may need to be ordered after any 617 /// prior load instructions. 618 /// 619 SDValue getRoot() { 620 if (PendingLoads.empty()) 621 return DAG.getRoot(); 622 623 if (PendingLoads.size() == 1) { 624 SDValue Root = PendingLoads[0]; 625 DAG.setRoot(Root); 626 PendingLoads.clear(); 627 return Root; 628 } 629 630 // Otherwise, we have to make a token factor node. 631 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 632 &PendingLoads[0], PendingLoads.size()); 633 PendingLoads.clear(); 634 DAG.setRoot(Root); 635 return Root; 636 } 637 638 /// getControlRoot - Similar to getRoot, but instead of flushing all the 639 /// PendingLoad items, flush all the PendingExports items. It is necessary 640 /// to do this before emitting a terminator instruction. 641 /// 642 SDValue getControlRoot() { 643 SDValue Root = DAG.getRoot(); 644 645 if (PendingExports.empty()) 646 return Root; 647 648 // Turn all of the CopyToReg chains into one factored node. 649 if (Root.getOpcode() != ISD::EntryToken) { 650 unsigned i = 0, e = PendingExports.size(); 651 for (; i != e; ++i) { 652 assert(PendingExports[i].Val->getNumOperands() > 1); 653 if (PendingExports[i].Val->getOperand(0) == Root) 654 break; // Don't add the root if we already indirectly depend on it. 655 } 656 657 if (i == e) 658 PendingExports.push_back(Root); 659 } 660 661 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 662 &PendingExports[0], 663 PendingExports.size()); 664 PendingExports.clear(); 665 DAG.setRoot(Root); 666 return Root; 667 } 668 669 void CopyValueToVirtualRegister(Value *V, unsigned Reg); 670 671 void visit(Instruction &I) { visit(I.getOpcode(), I); } 672 673 void visit(unsigned Opcode, User &I) { 674 // Note: this doesn't use InstVisitor, because it has to work with 675 // ConstantExpr's in addition to instructions. 676 switch (Opcode) { 677 default: assert(0 && "Unknown instruction type encountered!"); 678 abort(); 679 // Build the switch statement using the Instruction.def file. 680#define HANDLE_INST(NUM, OPCODE, CLASS) \ 681 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 682#include "llvm/Instruction.def" 683 } 684 } 685 686 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 687 688 SDValue getValue(const Value *V); 689 690 void setValue(const Value *V, SDValue NewN) { 691 SDValue &N = NodeMap[V]; 692 assert(N.Val == 0 && "Already set a value for this node!"); 693 N = NewN; 694 } 695 696 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber, 697 std::set<unsigned> &OutputRegs, 698 std::set<unsigned> &InputRegs); 699 700 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 701 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 702 unsigned Opc); 703 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 704 void ExportFromCurrentBlock(Value *V); 705 void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall, 706 MachineBasicBlock *LandingPad = NULL); 707 708 // Terminator instructions. 709 void visitRet(ReturnInst &I); 710 void visitBr(BranchInst &I); 711 void visitSwitch(SwitchInst &I); 712 void visitUnreachable(UnreachableInst &I) { /* noop */ } 713 714 // Helpers for visitSwitch 715 bool handleSmallSwitchRange(CaseRec& CR, 716 CaseRecVector& WorkList, 717 Value* SV, 718 MachineBasicBlock* Default); 719 bool handleJTSwitchCase(CaseRec& CR, 720 CaseRecVector& WorkList, 721 Value* SV, 722 MachineBasicBlock* Default); 723 bool handleBTSplitSwitchCase(CaseRec& CR, 724 CaseRecVector& WorkList, 725 Value* SV, 726 MachineBasicBlock* Default); 727 bool handleBitTestsSwitchCase(CaseRec& CR, 728 CaseRecVector& WorkList, 729 Value* SV, 730 MachineBasicBlock* Default); 731 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 732 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 733 void visitBitTestCase(MachineBasicBlock* NextMBB, 734 unsigned Reg, 735 SelectionDAGISel::BitTestCase &B); 736 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 737 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 738 SelectionDAGISel::JumpTableHeader &JTH); 739 740 // These all get lowered before this pass. 741 void visitInvoke(InvokeInst &I); 742 void visitUnwind(UnwindInst &I); 743 744 void visitBinary(User &I, unsigned OpCode); 745 void visitShift(User &I, unsigned Opcode); 746 void visitAdd(User &I) { 747 if (I.getType()->isFPOrFPVector()) 748 visitBinary(I, ISD::FADD); 749 else 750 visitBinary(I, ISD::ADD); 751 } 752 void visitSub(User &I); 753 void visitMul(User &I) { 754 if (I.getType()->isFPOrFPVector()) 755 visitBinary(I, ISD::FMUL); 756 else 757 visitBinary(I, ISD::MUL); 758 } 759 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 760 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 761 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 762 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 763 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 764 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 765 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 766 void visitOr (User &I) { visitBinary(I, ISD::OR); } 767 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 768 void visitShl (User &I) { visitShift(I, ISD::SHL); } 769 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 770 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 771 void visitICmp(User &I); 772 void visitFCmp(User &I); 773 void visitVICmp(User &I); 774 void visitVFCmp(User &I); 775 // Visit the conversion instructions 776 void visitTrunc(User &I); 777 void visitZExt(User &I); 778 void visitSExt(User &I); 779 void visitFPTrunc(User &I); 780 void visitFPExt(User &I); 781 void visitFPToUI(User &I); 782 void visitFPToSI(User &I); 783 void visitUIToFP(User &I); 784 void visitSIToFP(User &I); 785 void visitPtrToInt(User &I); 786 void visitIntToPtr(User &I); 787 void visitBitCast(User &I); 788 789 void visitExtractElement(User &I); 790 void visitInsertElement(User &I); 791 void visitShuffleVector(User &I); 792 793 void visitExtractValue(ExtractValueInst &I); 794 void visitInsertValue(InsertValueInst &I); 795 796 void visitGetElementPtr(User &I); 797 void visitSelect(User &I); 798 799 void visitMalloc(MallocInst &I); 800 void visitFree(FreeInst &I); 801 void visitAlloca(AllocaInst &I); 802 void visitLoad(LoadInst &I); 803 void visitStore(StoreInst &I); 804 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 805 void visitCall(CallInst &I); 806 void visitInlineAsm(CallSite CS); 807 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 808 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 809 810 void visitVAStart(CallInst &I); 811 void visitVAArg(VAArgInst &I); 812 void visitVAEnd(CallInst &I); 813 void visitVACopy(CallInst &I); 814 815 void visitUserOp1(Instruction &I) { 816 assert(0 && "UserOp1 should not exist at instruction selection time!"); 817 abort(); 818 } 819 void visitUserOp2(Instruction &I) { 820 assert(0 && "UserOp2 should not exist at instruction selection time!"); 821 abort(); 822 } 823 824private: 825 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op); 826 827}; 828} // end namespace llvm 829 830 831/// getCopyFromParts - Create a value that contains the specified legal parts 832/// combined into the value they represent. If the parts combine to a type 833/// larger then ValueVT then AssertOp can be used to specify whether the extra 834/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 835/// (ISD::AssertSext). 836static SDValue getCopyFromParts(SelectionDAG &DAG, 837 const SDValue *Parts, 838 unsigned NumParts, 839 MVT PartVT, 840 MVT ValueVT, 841 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 842 assert(NumParts > 0 && "No parts to assemble!"); 843 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 844 SDValue Val = Parts[0]; 845 846 if (NumParts > 1) { 847 // Assemble the value from multiple parts. 848 if (!ValueVT.isVector()) { 849 unsigned PartBits = PartVT.getSizeInBits(); 850 unsigned ValueBits = ValueVT.getSizeInBits(); 851 852 // Assemble the power of 2 part. 853 unsigned RoundParts = NumParts & (NumParts - 1) ? 854 1 << Log2_32(NumParts) : NumParts; 855 unsigned RoundBits = PartBits * RoundParts; 856 MVT RoundVT = RoundBits == ValueBits ? 857 ValueVT : MVT::getIntegerVT(RoundBits); 858 SDValue Lo, Hi; 859 860 if (RoundParts > 2) { 861 MVT HalfVT = MVT::getIntegerVT(RoundBits/2); 862 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT); 863 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2, 864 PartVT, HalfVT); 865 } else { 866 Lo = Parts[0]; 867 Hi = Parts[1]; 868 } 869 if (TLI.isBigEndian()) 870 std::swap(Lo, Hi); 871 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi); 872 873 if (RoundParts < NumParts) { 874 // Assemble the trailing non-power-of-2 part. 875 unsigned OddParts = NumParts - RoundParts; 876 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits); 877 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT); 878 879 // Combine the round and odd parts. 880 Lo = Val; 881 if (TLI.isBigEndian()) 882 std::swap(Lo, Hi); 883 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits); 884 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi); 885 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi, 886 DAG.getConstant(Lo.getValueType().getSizeInBits(), 887 TLI.getShiftAmountTy())); 888 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo); 889 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi); 890 } 891 } else { 892 // Handle a multi-element vector. 893 MVT IntermediateVT, RegisterVT; 894 unsigned NumIntermediates; 895 unsigned NumRegs = 896 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 897 RegisterVT); 898 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 899 NumParts = NumRegs; // Silence a compiler warning. 900 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 901 assert(RegisterVT == Parts[0].getValueType() && 902 "Part type doesn't match part!"); 903 904 // Assemble the parts into intermediate operands. 905 SmallVector<SDValue, 8> Ops(NumIntermediates); 906 if (NumIntermediates == NumParts) { 907 // If the register was not expanded, truncate or copy the value, 908 // as appropriate. 909 for (unsigned i = 0; i != NumParts; ++i) 910 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 911 PartVT, IntermediateVT); 912 } else if (NumParts > 0) { 913 // If the intermediate type was expanded, build the intermediate operands 914 // from the parts. 915 assert(NumParts % NumIntermediates == 0 && 916 "Must expand into a divisible number of parts!"); 917 unsigned Factor = NumParts / NumIntermediates; 918 for (unsigned i = 0; i != NumIntermediates; ++i) 919 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 920 PartVT, IntermediateVT); 921 } 922 923 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 924 // operands. 925 Val = DAG.getNode(IntermediateVT.isVector() ? 926 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, 927 ValueVT, &Ops[0], NumIntermediates); 928 } 929 } 930 931 // There is now one part, held in Val. Correct it to match ValueVT. 932 PartVT = Val.getValueType(); 933 934 if (PartVT == ValueVT) 935 return Val; 936 937 if (PartVT.isVector()) { 938 assert(ValueVT.isVector() && "Unknown vector conversion!"); 939 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 940 } 941 942 if (ValueVT.isVector()) { 943 assert(ValueVT.getVectorElementType() == PartVT && 944 ValueVT.getVectorNumElements() == 1 && 945 "Only trivial scalar-to-vector conversions should get here!"); 946 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val); 947 } 948 949 if (PartVT.isInteger() && 950 ValueVT.isInteger()) { 951 if (ValueVT.bitsLT(PartVT)) { 952 // For a truncate, see if we have any information to 953 // indicate whether the truncated bits will always be 954 // zero or sign-extension. 955 if (AssertOp != ISD::DELETED_NODE) 956 Val = DAG.getNode(AssertOp, PartVT, Val, 957 DAG.getValueType(ValueVT)); 958 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 959 } else { 960 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 961 } 962 } 963 964 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 965 if (ValueVT.bitsLT(Val.getValueType())) 966 // FP_ROUND's are always exact here. 967 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, 968 DAG.getIntPtrConstant(1)); 969 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val); 970 } 971 972 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 973 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 974 975 assert(0 && "Unknown mismatch!"); 976 return SDValue(); 977} 978 979/// getCopyToParts - Create a series of nodes that contain the specified value 980/// split into legal parts. If the parts contain more bits than Val, then, for 981/// integers, ExtendKind can be used to specify how to generate the extra bits. 982static void getCopyToParts(SelectionDAG &DAG, 983 SDValue Val, 984 SDValue *Parts, 985 unsigned NumParts, 986 MVT PartVT, 987 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 988 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 989 MVT PtrVT = TLI.getPointerTy(); 990 MVT ValueVT = Val.getValueType(); 991 unsigned PartBits = PartVT.getSizeInBits(); 992 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 993 994 if (!NumParts) 995 return; 996 997 if (!ValueVT.isVector()) { 998 if (PartVT == ValueVT) { 999 assert(NumParts == 1 && "No-op copy with multiple parts!"); 1000 Parts[0] = Val; 1001 return; 1002 } 1003 1004 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 1005 // If the parts cover more bits than the value has, promote the value. 1006 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 1007 assert(NumParts == 1 && "Do not know what to promote to!"); 1008 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 1009 } else if (PartVT.isInteger() && ValueVT.isInteger()) { 1010 ValueVT = MVT::getIntegerVT(NumParts * PartBits); 1011 Val = DAG.getNode(ExtendKind, ValueVT, Val); 1012 } else { 1013 assert(0 && "Unknown mismatch!"); 1014 } 1015 } else if (PartBits == ValueVT.getSizeInBits()) { 1016 // Different types of the same size. 1017 assert(NumParts == 1 && PartVT != ValueVT); 1018 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 1019 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 1020 // If the parts cover less bits than value has, truncate the value. 1021 if (PartVT.isInteger() && ValueVT.isInteger()) { 1022 ValueVT = MVT::getIntegerVT(NumParts * PartBits); 1023 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 1024 } else { 1025 assert(0 && "Unknown mismatch!"); 1026 } 1027 } 1028 1029 // The value may have changed - recompute ValueVT. 1030 ValueVT = Val.getValueType(); 1031 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 1032 "Failed to tile the value with PartVT!"); 1033 1034 if (NumParts == 1) { 1035 assert(PartVT == ValueVT && "Type conversion failed!"); 1036 Parts[0] = Val; 1037 return; 1038 } 1039 1040 // Expand the value into multiple parts. 1041 if (NumParts & (NumParts - 1)) { 1042 // The number of parts is not a power of 2. Split off and copy the tail. 1043 assert(PartVT.isInteger() && ValueVT.isInteger() && 1044 "Do not know what to expand to!"); 1045 unsigned RoundParts = 1 << Log2_32(NumParts); 1046 unsigned RoundBits = RoundParts * PartBits; 1047 unsigned OddParts = NumParts - RoundParts; 1048 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val, 1049 DAG.getConstant(RoundBits, 1050 TLI.getShiftAmountTy())); 1051 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT); 1052 if (TLI.isBigEndian()) 1053 // The odd parts were reversed by getCopyToParts - unreverse them. 1054 std::reverse(Parts + RoundParts, Parts + NumParts); 1055 NumParts = RoundParts; 1056 ValueVT = MVT::getIntegerVT(NumParts * PartBits); 1057 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 1058 } 1059 1060 // The number of parts is a power of 2. Repeatedly bisect the value using 1061 // EXTRACT_ELEMENT. 1062 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, 1063 MVT::getIntegerVT(ValueVT.getSizeInBits()), 1064 Val); 1065 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 1066 for (unsigned i = 0; i < NumParts; i += StepSize) { 1067 unsigned ThisBits = StepSize * PartBits / 2; 1068 MVT ThisVT = MVT::getIntegerVT (ThisBits); 1069 SDValue &Part0 = Parts[i]; 1070 SDValue &Part1 = Parts[i+StepSize/2]; 1071 1072 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0, 1073 DAG.getConstant(1, PtrVT)); 1074 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0, 1075 DAG.getConstant(0, PtrVT)); 1076 1077 if (ThisBits == PartBits && ThisVT != PartVT) { 1078 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0); 1079 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1); 1080 } 1081 } 1082 } 1083 1084 if (TLI.isBigEndian()) 1085 std::reverse(Parts, Parts + NumParts); 1086 1087 return; 1088 } 1089 1090 // Vector ValueVT. 1091 if (NumParts == 1) { 1092 if (PartVT != ValueVT) { 1093 if (PartVT.isVector()) { 1094 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 1095 } else { 1096 assert(ValueVT.getVectorElementType() == PartVT && 1097 ValueVT.getVectorNumElements() == 1 && 1098 "Only trivial vector-to-scalar conversions should get here!"); 1099 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val, 1100 DAG.getConstant(0, PtrVT)); 1101 } 1102 } 1103 1104 Parts[0] = Val; 1105 return; 1106 } 1107 1108 // Handle a multi-element vector. 1109 MVT IntermediateVT, RegisterVT; 1110 unsigned NumIntermediates; 1111 unsigned NumRegs = 1112 DAG.getTargetLoweringInfo() 1113 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 1114 RegisterVT); 1115 unsigned NumElements = ValueVT.getVectorNumElements(); 1116 1117 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 1118 NumParts = NumRegs; // Silence a compiler warning. 1119 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 1120 1121 // Split the vector into intermediate operands. 1122 SmallVector<SDValue, 8> Ops(NumIntermediates); 1123 for (unsigned i = 0; i != NumIntermediates; ++i) 1124 if (IntermediateVT.isVector()) 1125 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 1126 IntermediateVT, Val, 1127 DAG.getConstant(i * (NumElements / NumIntermediates), 1128 PtrVT)); 1129 else 1130 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 1131 IntermediateVT, Val, 1132 DAG.getConstant(i, PtrVT)); 1133 1134 // Split the intermediate operands into legal parts. 1135 if (NumParts == NumIntermediates) { 1136 // If the register was not expanded, promote or copy the value, 1137 // as appropriate. 1138 for (unsigned i = 0; i != NumParts; ++i) 1139 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 1140 } else if (NumParts > 0) { 1141 // If the intermediate type was expanded, split each the value into 1142 // legal parts. 1143 assert(NumParts % NumIntermediates == 0 && 1144 "Must expand into a divisible number of parts!"); 1145 unsigned Factor = NumParts / NumIntermediates; 1146 for (unsigned i = 0; i != NumIntermediates; ++i) 1147 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 1148 } 1149} 1150 1151 1152SDValue SelectionDAGLowering::getValue(const Value *V) { 1153 SDValue &N = NodeMap[V]; 1154 if (N.Val) return N; 1155 1156 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 1157 MVT VT = TLI.getValueType(V->getType(), true); 1158 1159 if (ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1160 return N = DAG.getConstant(CI->getValue(), VT); 1161 1162 if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1163 return N = DAG.getGlobalAddress(GV, VT); 1164 1165 if (isa<ConstantPointerNull>(C)) 1166 return N = DAG.getConstant(0, TLI.getPointerTy()); 1167 1168 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1169 return N = DAG.getConstantFP(CFP->getValueAPF(), VT); 1170 1171 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) && 1172 !V->getType()->isAggregateType()) 1173 return N = DAG.getNode(ISD::UNDEF, VT); 1174 1175 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1176 visit(CE->getOpcode(), *CE); 1177 SDValue N1 = NodeMap[V]; 1178 assert(N1.Val && "visit didn't populate the ValueMap!"); 1179 return N1; 1180 } 1181 1182 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1183 SmallVector<SDValue, 4> Constants; 1184 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1185 OI != OE; ++OI) { 1186 SDNode *Val = getValue(*OI).Val; 1187 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1188 Constants.push_back(SDValue(Val, i)); 1189 } 1190 return DAG.getMergeValues(&Constants[0], Constants.size()); 1191 } 1192 1193 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) { 1194 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1195 "Unknown struct or array constant!"); 1196 1197 SmallVector<MVT, 4> ValueVTs; 1198 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1199 unsigned NumElts = ValueVTs.size(); 1200 if (NumElts == 0) 1201 return SDValue(); // empty struct 1202 SmallVector<SDValue, 4> Constants(NumElts); 1203 for (unsigned i = 0; i != NumElts; ++i) { 1204 MVT EltVT = ValueVTs[i]; 1205 if (isa<UndefValue>(C)) 1206 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT); 1207 else if (EltVT.isFloatingPoint()) 1208 Constants[i] = DAG.getConstantFP(0, EltVT); 1209 else 1210 Constants[i] = DAG.getConstant(0, EltVT); 1211 } 1212 return DAG.getMergeValues(&Constants[0], NumElts); 1213 } 1214 1215 const VectorType *VecTy = cast<VectorType>(V->getType()); 1216 unsigned NumElements = VecTy->getNumElements(); 1217 1218 // Now that we know the number and type of the elements, get that number of 1219 // elements into the Ops array based on what kind of constant it is. 1220 SmallVector<SDValue, 16> Ops; 1221 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1222 for (unsigned i = 0; i != NumElements; ++i) 1223 Ops.push_back(getValue(CP->getOperand(i))); 1224 } else { 1225 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1226 "Unknown vector constant!"); 1227 MVT EltVT = TLI.getValueType(VecTy->getElementType()); 1228 1229 SDValue Op; 1230 if (isa<UndefValue>(C)) 1231 Op = DAG.getNode(ISD::UNDEF, EltVT); 1232 else if (EltVT.isFloatingPoint()) 1233 Op = DAG.getConstantFP(0, EltVT); 1234 else 1235 Op = DAG.getConstant(0, EltVT); 1236 Ops.assign(NumElements, Op); 1237 } 1238 1239 // Create a BUILD_VECTOR node. 1240 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1241 } 1242 1243 // If this is a static alloca, generate it as the frameindex instead of 1244 // computation. 1245 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1246 std::map<const AllocaInst*, int>::iterator SI = 1247 FuncInfo.StaticAllocaMap.find(AI); 1248 if (SI != FuncInfo.StaticAllocaMap.end()) 1249 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1250 } 1251 1252 unsigned InReg = FuncInfo.ValueMap[V]; 1253 assert(InReg && "Value not in map!"); 1254 1255 RegsForValue RFV(TLI, InReg, V->getType()); 1256 SDValue Chain = DAG.getEntryNode(); 1257 return RFV.getCopyFromRegs(DAG, Chain, NULL); 1258} 1259 1260 1261void SelectionDAGLowering::visitRet(ReturnInst &I) { 1262 if (I.getNumOperands() == 0) { 1263 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot())); 1264 return; 1265 } 1266 1267 SmallVector<SDValue, 8> NewValues; 1268 NewValues.push_back(getControlRoot()); 1269 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 1270 SDValue RetOp = getValue(I.getOperand(i)); 1271 1272 SmallVector<MVT, 4> ValueVTs; 1273 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs); 1274 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) { 1275 MVT VT = ValueVTs[j]; 1276 1277 // FIXME: C calling convention requires the return type to be promoted to 1278 // at least 32-bit. But this is not necessary for non-C calling conventions. 1279 if (VT.isInteger()) { 1280 MVT MinVT = TLI.getRegisterType(MVT::i32); 1281 if (VT.bitsLT(MinVT)) 1282 VT = MinVT; 1283 } 1284 1285 unsigned NumParts = TLI.getNumRegisters(VT); 1286 MVT PartVT = TLI.getRegisterType(VT); 1287 SmallVector<SDValue, 4> Parts(NumParts); 1288 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1289 1290 const Function *F = I.getParent()->getParent(); 1291 if (F->paramHasAttr(0, ParamAttr::SExt)) 1292 ExtendKind = ISD::SIGN_EXTEND; 1293 else if (F->paramHasAttr(0, ParamAttr::ZExt)) 1294 ExtendKind = ISD::ZERO_EXTEND; 1295 1296 getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j), 1297 &Parts[0], NumParts, PartVT, ExtendKind); 1298 1299 for (unsigned i = 0; i < NumParts; ++i) { 1300 NewValues.push_back(Parts[i]); 1301 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy())); 1302 } 1303 } 1304 } 1305 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 1306 &NewValues[0], NewValues.size())); 1307} 1308 1309/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1310/// the current basic block, add it to ValueMap now so that we'll get a 1311/// CopyTo/FromReg. 1312void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 1313 // No need to export constants. 1314 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1315 1316 // Already exported? 1317 if (FuncInfo.isExportedInst(V)) return; 1318 1319 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1320 CopyValueToVirtualRegister(V, Reg); 1321} 1322 1323bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 1324 const BasicBlock *FromBB) { 1325 // The operands of the setcc have to be in this block. We don't know 1326 // how to export them from some other block. 1327 if (Instruction *VI = dyn_cast<Instruction>(V)) { 1328 // Can export from current BB. 1329 if (VI->getParent() == FromBB) 1330 return true; 1331 1332 // Is already exported, noop. 1333 return FuncInfo.isExportedInst(V); 1334 } 1335 1336 // If this is an argument, we can export it if the BB is the entry block or 1337 // if it is already exported. 1338 if (isa<Argument>(V)) { 1339 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1340 return true; 1341 1342 // Otherwise, can only export this if it is already exported. 1343 return FuncInfo.isExportedInst(V); 1344 } 1345 1346 // Otherwise, constants can always be exported. 1347 return true; 1348} 1349 1350static bool InBlock(const Value *V, const BasicBlock *BB) { 1351 if (const Instruction *I = dyn_cast<Instruction>(V)) 1352 return I->getParent() == BB; 1353 return true; 1354} 1355 1356/// FindMergedConditions - If Cond is an expression like 1357void SelectionDAGLowering::FindMergedConditions(Value *Cond, 1358 MachineBasicBlock *TBB, 1359 MachineBasicBlock *FBB, 1360 MachineBasicBlock *CurBB, 1361 unsigned Opc) { 1362 // If this node is not part of the or/and tree, emit it as a branch. 1363 Instruction *BOp = dyn_cast<Instruction>(Cond); 1364 1365 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1366 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1367 BOp->getParent() != CurBB->getBasicBlock() || 1368 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1369 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1370 const BasicBlock *BB = CurBB->getBasicBlock(); 1371 1372 // If the leaf of the tree is a comparison, merge the condition into 1373 // the caseblock. 1374 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1375 // The operands of the cmp have to be in this block. We don't know 1376 // how to export them from some other block. If this is the first block 1377 // of the sequence, no exporting is needed. 1378 (CurBB == CurMBB || 1379 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1380 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1381 BOp = cast<Instruction>(Cond); 1382 ISD::CondCode Condition; 1383 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1384 switch (IC->getPredicate()) { 1385 default: assert(0 && "Unknown icmp predicate opcode!"); 1386 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1387 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1388 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1389 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1390 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1391 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1392 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1393 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1394 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1395 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1396 } 1397 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1398 ISD::CondCode FPC, FOC; 1399 switch (FC->getPredicate()) { 1400 default: assert(0 && "Unknown fcmp predicate opcode!"); 1401 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1402 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1403 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1404 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1405 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1406 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1407 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1408 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 1409 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 1410 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1411 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1412 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1413 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1414 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1415 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1416 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1417 } 1418 if (FiniteOnlyFPMath()) 1419 Condition = FOC; 1420 else 1421 Condition = FPC; 1422 } else { 1423 Condition = ISD::SETEQ; // silence warning. 1424 assert(0 && "Unknown compare instruction"); 1425 } 1426 1427 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1428 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1429 SwitchCases.push_back(CB); 1430 return; 1431 } 1432 1433 // Create a CaseBlock record representing this branch. 1434 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1435 NULL, TBB, FBB, CurBB); 1436 SwitchCases.push_back(CB); 1437 return; 1438 } 1439 1440 1441 // Create TmpBB after CurBB. 1442 MachineFunction::iterator BBI = CurBB; 1443 MachineFunction &MF = DAG.getMachineFunction(); 1444 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1445 CurBB->getParent()->insert(++BBI, TmpBB); 1446 1447 if (Opc == Instruction::Or) { 1448 // Codegen X | Y as: 1449 // jmp_if_X TBB 1450 // jmp TmpBB 1451 // TmpBB: 1452 // jmp_if_Y TBB 1453 // jmp FBB 1454 // 1455 1456 // Emit the LHS condition. 1457 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1458 1459 // Emit the RHS condition into TmpBB. 1460 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1461 } else { 1462 assert(Opc == Instruction::And && "Unknown merge op!"); 1463 // Codegen X & Y as: 1464 // jmp_if_X TmpBB 1465 // jmp FBB 1466 // TmpBB: 1467 // jmp_if_Y TBB 1468 // jmp FBB 1469 // 1470 // This requires creation of TmpBB after CurBB. 1471 1472 // Emit the LHS condition. 1473 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1474 1475 // Emit the RHS condition into TmpBB. 1476 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1477 } 1478} 1479 1480/// If the set of cases should be emitted as a series of branches, return true. 1481/// If we should emit this as a bunch of and/or'd together conditions, return 1482/// false. 1483static bool 1484ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1485 if (Cases.size() != 2) return true; 1486 1487 // If this is two comparisons of the same values or'd or and'd together, they 1488 // will get folded into a single comparison, so don't emit two blocks. 1489 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1490 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1491 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1492 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1493 return false; 1494 } 1495 1496 return true; 1497} 1498 1499void SelectionDAGLowering::visitBr(BranchInst &I) { 1500 // Update machine-CFG edges. 1501 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1502 1503 // Figure out which block is immediately after the current one. 1504 MachineBasicBlock *NextBlock = 0; 1505 MachineFunction::iterator BBI = CurMBB; 1506 if (++BBI != CurMBB->getParent()->end()) 1507 NextBlock = BBI; 1508 1509 if (I.isUnconditional()) { 1510 // Update machine-CFG edges. 1511 CurMBB->addSuccessor(Succ0MBB); 1512 1513 // If this is not a fall-through branch, emit the branch. 1514 if (Succ0MBB != NextBlock) 1515 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), 1516 DAG.getBasicBlock(Succ0MBB))); 1517 return; 1518 } 1519 1520 // If this condition is one of the special cases we handle, do special stuff 1521 // now. 1522 Value *CondVal = I.getCondition(); 1523 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1524 1525 // If this is a series of conditions that are or'd or and'd together, emit 1526 // this as a sequence of branches instead of setcc's with and/or operations. 1527 // For example, instead of something like: 1528 // cmp A, B 1529 // C = seteq 1530 // cmp D, E 1531 // F = setle 1532 // or C, F 1533 // jnz foo 1534 // Emit: 1535 // cmp A, B 1536 // je foo 1537 // cmp D, E 1538 // jle foo 1539 // 1540 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1541 if (BOp->hasOneUse() && 1542 (BOp->getOpcode() == Instruction::And || 1543 BOp->getOpcode() == Instruction::Or)) { 1544 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1545 // If the compares in later blocks need to use values not currently 1546 // exported from this block, export them now. This block should always 1547 // be the first entry. 1548 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1549 1550 // Allow some cases to be rejected. 1551 if (ShouldEmitAsBranches(SwitchCases)) { 1552 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1553 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1554 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1555 } 1556 1557 // Emit the branch for this block. 1558 visitSwitchCase(SwitchCases[0]); 1559 SwitchCases.erase(SwitchCases.begin()); 1560 return; 1561 } 1562 1563 // Okay, we decided not to do this, remove any inserted MBB's and clear 1564 // SwitchCases. 1565 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1566 CurMBB->getParent()->erase(SwitchCases[i].ThisBB); 1567 1568 SwitchCases.clear(); 1569 } 1570 } 1571 1572 // Create a CaseBlock record representing this branch. 1573 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1574 NULL, Succ0MBB, Succ1MBB, CurMBB); 1575 // Use visitSwitchCase to actually insert the fast branch sequence for this 1576 // cond branch. 1577 visitSwitchCase(CB); 1578} 1579 1580/// visitSwitchCase - Emits the necessary code to represent a single node in 1581/// the binary search tree resulting from lowering a switch instruction. 1582void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1583 SDValue Cond; 1584 SDValue CondLHS = getValue(CB.CmpLHS); 1585 1586 // Build the setcc now. 1587 if (CB.CmpMHS == NULL) { 1588 // Fold "(X == true)" to X and "(X == false)" to !X to 1589 // handle common cases produced by branch lowering. 1590 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1591 Cond = CondLHS; 1592 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1593 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1594 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1595 } else 1596 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1597 } else { 1598 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1599 1600 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1601 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1602 1603 SDValue CmpOp = getValue(CB.CmpMHS); 1604 MVT VT = CmpOp.getValueType(); 1605 1606 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1607 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1608 } else { 1609 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1610 Cond = DAG.getSetCC(MVT::i1, SUB, 1611 DAG.getConstant(High-Low, VT), ISD::SETULE); 1612 } 1613 } 1614 1615 // Update successor info 1616 CurMBB->addSuccessor(CB.TrueBB); 1617 CurMBB->addSuccessor(CB.FalseBB); 1618 1619 // Set NextBlock to be the MBB immediately after the current one, if any. 1620 // This is used to avoid emitting unnecessary branches to the next block. 1621 MachineBasicBlock *NextBlock = 0; 1622 MachineFunction::iterator BBI = CurMBB; 1623 if (++BBI != CurMBB->getParent()->end()) 1624 NextBlock = BBI; 1625 1626 // If the lhs block is the next block, invert the condition so that we can 1627 // fall through to the lhs instead of the rhs block. 1628 if (CB.TrueBB == NextBlock) { 1629 std::swap(CB.TrueBB, CB.FalseBB); 1630 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1631 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1632 } 1633 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond, 1634 DAG.getBasicBlock(CB.TrueBB)); 1635 if (CB.FalseBB == NextBlock) 1636 DAG.setRoot(BrCond); 1637 else 1638 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1639 DAG.getBasicBlock(CB.FalseBB))); 1640} 1641 1642/// visitJumpTable - Emit JumpTable node in the current MBB 1643void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1644 // Emit the code for the jump table 1645 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1646 MVT PTy = TLI.getPointerTy(); 1647 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy); 1648 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1649 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1650 Table, Index)); 1651 return; 1652} 1653 1654/// visitJumpTableHeader - This function emits necessary code to produce index 1655/// in the JumpTable from switch case. 1656void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1657 SelectionDAGISel::JumpTableHeader &JTH) { 1658 // Subtract the lowest switch case value from the value being switched on 1659 // and conditional branch to default mbb if the result is greater than the 1660 // difference between smallest and largest cases. 1661 SDValue SwitchOp = getValue(JTH.SValue); 1662 MVT VT = SwitchOp.getValueType(); 1663 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1664 DAG.getConstant(JTH.First, VT)); 1665 1666 // The SDNode we just created, which holds the value being switched on 1667 // minus the the smallest case value, needs to be copied to a virtual 1668 // register so it can be used as an index into the jump table in a 1669 // subsequent basic block. This value may be smaller or larger than the 1670 // target's pointer type, and therefore require extension or truncating. 1671 if (VT.bitsGT(TLI.getPointerTy())) 1672 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1673 else 1674 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1675 1676 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1677 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp); 1678 JT.Reg = JumpTableReg; 1679 1680 // Emit the range check for the jump table, and branch to the default 1681 // block for the switch statement if the value being switched on exceeds 1682 // the largest case in the switch. 1683 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB, 1684 DAG.getConstant(JTH.Last-JTH.First,VT), 1685 ISD::SETUGT); 1686 1687 // Set NextBlock to be the MBB immediately after the current one, if any. 1688 // This is used to avoid emitting unnecessary branches to the next block. 1689 MachineBasicBlock *NextBlock = 0; 1690 MachineFunction::iterator BBI = CurMBB; 1691 if (++BBI != CurMBB->getParent()->end()) 1692 NextBlock = BBI; 1693 1694 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1695 DAG.getBasicBlock(JT.Default)); 1696 1697 if (JT.MBB == NextBlock) 1698 DAG.setRoot(BrCond); 1699 else 1700 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1701 DAG.getBasicBlock(JT.MBB))); 1702 1703 return; 1704} 1705 1706/// visitBitTestHeader - This function emits necessary code to produce value 1707/// suitable for "bit tests" 1708void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1709 // Subtract the minimum value 1710 SDValue SwitchOp = getValue(B.SValue); 1711 MVT VT = SwitchOp.getValueType(); 1712 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1713 DAG.getConstant(B.First, VT)); 1714 1715 // Check range 1716 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB, 1717 DAG.getConstant(B.Range, VT), 1718 ISD::SETUGT); 1719 1720 SDValue ShiftOp; 1721 if (VT.bitsGT(TLI.getShiftAmountTy())) 1722 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1723 else 1724 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1725 1726 // Make desired shift 1727 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1728 DAG.getConstant(1, TLI.getPointerTy()), 1729 ShiftOp); 1730 1731 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1732 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal); 1733 B.Reg = SwitchReg; 1734 1735 // Set NextBlock to be the MBB immediately after the current one, if any. 1736 // This is used to avoid emitting unnecessary branches to the next block. 1737 MachineBasicBlock *NextBlock = 0; 1738 MachineFunction::iterator BBI = CurMBB; 1739 if (++BBI != CurMBB->getParent()->end()) 1740 NextBlock = BBI; 1741 1742 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1743 1744 CurMBB->addSuccessor(B.Default); 1745 CurMBB->addSuccessor(MBB); 1746 1747 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1748 DAG.getBasicBlock(B.Default)); 1749 1750 if (MBB == NextBlock) 1751 DAG.setRoot(BrRange); 1752 else 1753 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1754 DAG.getBasicBlock(MBB))); 1755 1756 return; 1757} 1758 1759/// visitBitTestCase - this function produces one "bit test" 1760void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1761 unsigned Reg, 1762 SelectionDAGISel::BitTestCase &B) { 1763 // Emit bit tests and jumps 1764 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg, 1765 TLI.getPointerTy()); 1766 1767 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal, 1768 DAG.getConstant(B.Mask, TLI.getPointerTy())); 1769 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp, 1770 DAG.getConstant(0, TLI.getPointerTy()), 1771 ISD::SETNE); 1772 1773 CurMBB->addSuccessor(B.TargetBB); 1774 CurMBB->addSuccessor(NextMBB); 1775 1776 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), 1777 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1778 1779 // Set NextBlock to be the MBB immediately after the current one, if any. 1780 // This is used to avoid emitting unnecessary branches to the next block. 1781 MachineBasicBlock *NextBlock = 0; 1782 MachineFunction::iterator BBI = CurMBB; 1783 if (++BBI != CurMBB->getParent()->end()) 1784 NextBlock = BBI; 1785 1786 if (NextMBB == NextBlock) 1787 DAG.setRoot(BrAnd); 1788 else 1789 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1790 DAG.getBasicBlock(NextMBB))); 1791 1792 return; 1793} 1794 1795void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1796 // Retrieve successors. 1797 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1798 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1799 1800 if (isa<InlineAsm>(I.getCalledValue())) 1801 visitInlineAsm(&I); 1802 else 1803 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad); 1804 1805 // If the value of the invoke is used outside of its defining block, make it 1806 // available as a virtual register. 1807 if (!I.use_empty()) { 1808 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1809 if (VMI != FuncInfo.ValueMap.end()) 1810 CopyValueToVirtualRegister(&I, VMI->second); 1811 } 1812 1813 // Update successor info 1814 CurMBB->addSuccessor(Return); 1815 CurMBB->addSuccessor(LandingPad); 1816 1817 // Drop into normal successor. 1818 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), 1819 DAG.getBasicBlock(Return))); 1820} 1821 1822void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1823} 1824 1825/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1826/// small case ranges). 1827bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1828 CaseRecVector& WorkList, 1829 Value* SV, 1830 MachineBasicBlock* Default) { 1831 Case& BackCase = *(CR.Range.second-1); 1832 1833 // Size is the number of Cases represented by this range. 1834 unsigned Size = CR.Range.second - CR.Range.first; 1835 if (Size > 3) 1836 return false; 1837 1838 // Get the MachineFunction which holds the current MBB. This is used when 1839 // inserting any additional MBBs necessary to represent the switch. 1840 MachineFunction *CurMF = CurMBB->getParent(); 1841 1842 // Figure out which block is immediately after the current one. 1843 MachineBasicBlock *NextBlock = 0; 1844 MachineFunction::iterator BBI = CR.CaseBB; 1845 1846 if (++BBI != CurMBB->getParent()->end()) 1847 NextBlock = BBI; 1848 1849 // TODO: If any two of the cases has the same destination, and if one value 1850 // is the same as the other, but has one bit unset that the other has set, 1851 // use bit manipulation to do two compares at once. For example: 1852 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1853 1854 // Rearrange the case blocks so that the last one falls through if possible. 1855 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1856 // The last case block won't fall through into 'NextBlock' if we emit the 1857 // branches in this order. See if rearranging a case value would help. 1858 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1859 if (I->BB == NextBlock) { 1860 std::swap(*I, BackCase); 1861 break; 1862 } 1863 } 1864 } 1865 1866 // Create a CaseBlock record representing a conditional branch to 1867 // the Case's target mbb if the value being switched on SV is equal 1868 // to C. 1869 MachineBasicBlock *CurBlock = CR.CaseBB; 1870 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1871 MachineBasicBlock *FallThrough; 1872 if (I != E-1) { 1873 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1874 CurMF->insert(BBI, FallThrough); 1875 } else { 1876 // If the last case doesn't match, go to the default block. 1877 FallThrough = Default; 1878 } 1879 1880 Value *RHS, *LHS, *MHS; 1881 ISD::CondCode CC; 1882 if (I->High == I->Low) { 1883 // This is just small small case range :) containing exactly 1 case 1884 CC = ISD::SETEQ; 1885 LHS = SV; RHS = I->High; MHS = NULL; 1886 } else { 1887 CC = ISD::SETLE; 1888 LHS = I->Low; MHS = SV; RHS = I->High; 1889 } 1890 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1891 I->BB, FallThrough, CurBlock); 1892 1893 // If emitting the first comparison, just call visitSwitchCase to emit the 1894 // code into the current block. Otherwise, push the CaseBlock onto the 1895 // vector to be later processed by SDISel, and insert the node's MBB 1896 // before the next MBB. 1897 if (CurBlock == CurMBB) 1898 visitSwitchCase(CB); 1899 else 1900 SwitchCases.push_back(CB); 1901 1902 CurBlock = FallThrough; 1903 } 1904 1905 return true; 1906} 1907 1908static inline bool areJTsAllowed(const TargetLowering &TLI) { 1909 return !DisableJumpTables && 1910 (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1911 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1912} 1913 1914/// handleJTSwitchCase - Emit jumptable for current switch case range 1915bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1916 CaseRecVector& WorkList, 1917 Value* SV, 1918 MachineBasicBlock* Default) { 1919 Case& FrontCase = *CR.Range.first; 1920 Case& BackCase = *(CR.Range.second-1); 1921 1922 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1923 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1924 1925 uint64_t TSize = 0; 1926 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1927 I!=E; ++I) 1928 TSize += I->size(); 1929 1930 if (!areJTsAllowed(TLI) || TSize <= 3) 1931 return false; 1932 1933 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1934 if (Density < 0.4) 1935 return false; 1936 1937 DOUT << "Lowering jump table\n" 1938 << "First entry: " << First << ". Last entry: " << Last << "\n" 1939 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1940 1941 // Get the MachineFunction which holds the current MBB. This is used when 1942 // inserting any additional MBBs necessary to represent the switch. 1943 MachineFunction *CurMF = CurMBB->getParent(); 1944 1945 // Figure out which block is immediately after the current one. 1946 MachineBasicBlock *NextBlock = 0; 1947 MachineFunction::iterator BBI = CR.CaseBB; 1948 1949 if (++BBI != CurMBB->getParent()->end()) 1950 NextBlock = BBI; 1951 1952 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1953 1954 // Create a new basic block to hold the code for loading the address 1955 // of the jump table, and jumping to it. Update successor information; 1956 // we will either branch to the default case for the switch, or the jump 1957 // table. 1958 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1959 CurMF->insert(BBI, JumpTableBB); 1960 CR.CaseBB->addSuccessor(Default); 1961 CR.CaseBB->addSuccessor(JumpTableBB); 1962 1963 // Build a vector of destination BBs, corresponding to each target 1964 // of the jump table. If the value of the jump table slot corresponds to 1965 // a case statement, push the case's BB onto the vector, otherwise, push 1966 // the default BB. 1967 std::vector<MachineBasicBlock*> DestBBs; 1968 int64_t TEI = First; 1969 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1970 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1971 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1972 1973 if ((Low <= TEI) && (TEI <= High)) { 1974 DestBBs.push_back(I->BB); 1975 if (TEI==High) 1976 ++I; 1977 } else { 1978 DestBBs.push_back(Default); 1979 } 1980 } 1981 1982 // Update successor info. Add one edge to each unique successor. 1983 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1984 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1985 E = DestBBs.end(); I != E; ++I) { 1986 if (!SuccsHandled[(*I)->getNumber()]) { 1987 SuccsHandled[(*I)->getNumber()] = true; 1988 JumpTableBB->addSuccessor(*I); 1989 } 1990 } 1991 1992 // Create a jump table index for this jump table, or return an existing 1993 // one. 1994 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1995 1996 // Set the jump table information so that we can codegen it as a second 1997 // MachineBasicBlock 1998 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1999 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 2000 (CR.CaseBB == CurMBB)); 2001 if (CR.CaseBB == CurMBB) 2002 visitJumpTableHeader(JT, JTH); 2003 2004 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 2005 2006 return true; 2007} 2008 2009/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2010/// 2 subtrees. 2011bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 2012 CaseRecVector& WorkList, 2013 Value* SV, 2014 MachineBasicBlock* Default) { 2015 // Get the MachineFunction which holds the current MBB. This is used when 2016 // inserting any additional MBBs necessary to represent the switch. 2017 MachineFunction *CurMF = CurMBB->getParent(); 2018 2019 // Figure out which block is immediately after the current one. 2020 MachineBasicBlock *NextBlock = 0; 2021 MachineFunction::iterator BBI = CR.CaseBB; 2022 2023 if (++BBI != CurMBB->getParent()->end()) 2024 NextBlock = BBI; 2025 2026 Case& FrontCase = *CR.Range.first; 2027 Case& BackCase = *(CR.Range.second-1); 2028 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2029 2030 // Size is the number of Cases represented by this range. 2031 unsigned Size = CR.Range.second - CR.Range.first; 2032 2033 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 2034 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 2035 double FMetric = 0; 2036 CaseItr Pivot = CR.Range.first + Size/2; 2037 2038 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2039 // (heuristically) allow us to emit JumpTable's later. 2040 uint64_t TSize = 0; 2041 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2042 I!=E; ++I) 2043 TSize += I->size(); 2044 2045 uint64_t LSize = FrontCase.size(); 2046 uint64_t RSize = TSize-LSize; 2047 DOUT << "Selecting best pivot: \n" 2048 << "First: " << First << ", Last: " << Last <<"\n" 2049 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 2050 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2051 J!=E; ++I, ++J) { 2052 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 2053 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 2054 assert((RBegin-LEnd>=1) && "Invalid case distance"); 2055 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 2056 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 2057 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 2058 // Should always split in some non-trivial place 2059 DOUT <<"=>Step\n" 2060 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 2061 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 2062 << "Metric: " << Metric << "\n"; 2063 if (FMetric < Metric) { 2064 Pivot = J; 2065 FMetric = Metric; 2066 DOUT << "Current metric set to: " << FMetric << "\n"; 2067 } 2068 2069 LSize += J->size(); 2070 RSize -= J->size(); 2071 } 2072 if (areJTsAllowed(TLI)) { 2073 // If our case is dense we *really* should handle it earlier! 2074 assert((FMetric > 0) && "Should handle dense range earlier!"); 2075 } else { 2076 Pivot = CR.Range.first + Size/2; 2077 } 2078 2079 CaseRange LHSR(CR.Range.first, Pivot); 2080 CaseRange RHSR(Pivot, CR.Range.second); 2081 Constant *C = Pivot->Low; 2082 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2083 2084 // We know that we branch to the LHS if the Value being switched on is 2085 // less than the Pivot value, C. We use this to optimize our binary 2086 // tree a bit, by recognizing that if SV is greater than or equal to the 2087 // LHS's Case Value, and that Case Value is exactly one less than the 2088 // Pivot's Value, then we can branch directly to the LHS's Target, 2089 // rather than creating a leaf node for it. 2090 if ((LHSR.second - LHSR.first) == 1 && 2091 LHSR.first->High == CR.GE && 2092 cast<ConstantInt>(C)->getSExtValue() == 2093 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 2094 TrueBB = LHSR.first->BB; 2095 } else { 2096 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2097 CurMF->insert(BBI, TrueBB); 2098 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2099 } 2100 2101 // Similar to the optimization above, if the Value being switched on is 2102 // known to be less than the Constant CR.LT, and the current Case Value 2103 // is CR.LT - 1, then we can branch directly to the target block for 2104 // the current Case Value, rather than emitting a RHS leaf node for it. 2105 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2106 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 2107 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 2108 FalseBB = RHSR.first->BB; 2109 } else { 2110 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2111 CurMF->insert(BBI, FalseBB); 2112 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2113 } 2114 2115 // Create a CaseBlock record representing a conditional branch to 2116 // the LHS node if the value being switched on SV is less than C. 2117 // Otherwise, branch to LHS. 2118 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 2119 TrueBB, FalseBB, CR.CaseBB); 2120 2121 if (CR.CaseBB == CurMBB) 2122 visitSwitchCase(CB); 2123 else 2124 SwitchCases.push_back(CB); 2125 2126 return true; 2127} 2128 2129/// handleBitTestsSwitchCase - if current case range has few destination and 2130/// range span less, than machine word bitwidth, encode case range into series 2131/// of masks and emit bit tests with these masks. 2132bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 2133 CaseRecVector& WorkList, 2134 Value* SV, 2135 MachineBasicBlock* Default){ 2136 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits(); 2137 2138 Case& FrontCase = *CR.Range.first; 2139 Case& BackCase = *(CR.Range.second-1); 2140 2141 // Get the MachineFunction which holds the current MBB. This is used when 2142 // inserting any additional MBBs necessary to represent the switch. 2143 MachineFunction *CurMF = CurMBB->getParent(); 2144 2145 unsigned numCmps = 0; 2146 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2147 I!=E; ++I) { 2148 // Single case counts one, case range - two. 2149 if (I->Low == I->High) 2150 numCmps +=1; 2151 else 2152 numCmps +=2; 2153 } 2154 2155 // Count unique destinations 2156 SmallSet<MachineBasicBlock*, 4> Dests; 2157 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2158 Dests.insert(I->BB); 2159 if (Dests.size() > 3) 2160 // Don't bother the code below, if there are too much unique destinations 2161 return false; 2162 } 2163 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 2164 << "Total number of comparisons: " << numCmps << "\n"; 2165 2166 // Compute span of values. 2167 Constant* minValue = FrontCase.Low; 2168 Constant* maxValue = BackCase.High; 2169 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 2170 cast<ConstantInt>(minValue)->getSExtValue(); 2171 DOUT << "Compare range: " << range << "\n" 2172 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 2173 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 2174 2175 if (range>=IntPtrBits || 2176 (!(Dests.size() == 1 && numCmps >= 3) && 2177 !(Dests.size() == 2 && numCmps >= 5) && 2178 !(Dests.size() >= 3 && numCmps >= 6))) 2179 return false; 2180 2181 DOUT << "Emitting bit tests\n"; 2182 int64_t lowBound = 0; 2183 2184 // Optimize the case where all the case values fit in a 2185 // word without having to subtract minValue. In this case, 2186 // we can optimize away the subtraction. 2187 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 2188 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 2189 range = cast<ConstantInt>(maxValue)->getSExtValue(); 2190 } else { 2191 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 2192 } 2193 2194 CaseBitsVector CasesBits; 2195 unsigned i, count = 0; 2196 2197 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2198 MachineBasicBlock* Dest = I->BB; 2199 for (i = 0; i < count; ++i) 2200 if (Dest == CasesBits[i].BB) 2201 break; 2202 2203 if (i == count) { 2204 assert((count < 3) && "Too much destinations to test!"); 2205 CasesBits.push_back(CaseBits(0, Dest, 0)); 2206 count++; 2207 } 2208 2209 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 2210 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 2211 2212 for (uint64_t j = lo; j <= hi; j++) { 2213 CasesBits[i].Mask |= 1ULL << j; 2214 CasesBits[i].Bits++; 2215 } 2216 2217 } 2218 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2219 2220 SelectionDAGISel::BitTestInfo BTC; 2221 2222 // Figure out which block is immediately after the current one. 2223 MachineFunction::iterator BBI = CR.CaseBB; 2224 ++BBI; 2225 2226 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2227 2228 DOUT << "Cases:\n"; 2229 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2230 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 2231 << ", BB: " << CasesBits[i].BB << "\n"; 2232 2233 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2234 CurMF->insert(BBI, CaseBB); 2235 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 2236 CaseBB, 2237 CasesBits[i].BB)); 2238 } 2239 2240 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 2241 -1U, (CR.CaseBB == CurMBB), 2242 CR.CaseBB, Default, BTC); 2243 2244 if (CR.CaseBB == CurMBB) 2245 visitBitTestHeader(BTB); 2246 2247 BitTestCases.push_back(BTB); 2248 2249 return true; 2250} 2251 2252 2253/// Clusterify - Transform simple list of Cases into list of CaseRange's 2254unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 2255 const SwitchInst& SI) { 2256 unsigned numCmps = 0; 2257 2258 // Start with "simple" cases 2259 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 2260 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2261 Cases.push_back(Case(SI.getSuccessorValue(i), 2262 SI.getSuccessorValue(i), 2263 SMBB)); 2264 } 2265 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2266 2267 // Merge case into clusters 2268 if (Cases.size()>=2) 2269 // Must recompute end() each iteration because it may be 2270 // invalidated by erase if we hold on to it 2271 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 2272 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 2273 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 2274 MachineBasicBlock* nextBB = J->BB; 2275 MachineBasicBlock* currentBB = I->BB; 2276 2277 // If the two neighboring cases go to the same destination, merge them 2278 // into a single case. 2279 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 2280 I->High = J->High; 2281 J = Cases.erase(J); 2282 } else { 2283 I = J++; 2284 } 2285 } 2286 2287 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2288 if (I->Low != I->High) 2289 // A range counts double, since it requires two compares. 2290 ++numCmps; 2291 } 2292 2293 return numCmps; 2294} 2295 2296void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 2297 // Figure out which block is immediately after the current one. 2298 MachineBasicBlock *NextBlock = 0; 2299 MachineFunction::iterator BBI = CurMBB; 2300 2301 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2302 2303 // If there is only the default destination, branch to it if it is not the 2304 // next basic block. Otherwise, just fall through. 2305 if (SI.getNumOperands() == 2) { 2306 // Update machine-CFG edges. 2307 2308 // If this is not a fall-through branch, emit the branch. 2309 CurMBB->addSuccessor(Default); 2310 if (Default != NextBlock) 2311 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), 2312 DAG.getBasicBlock(Default))); 2313 2314 return; 2315 } 2316 2317 // If there are any non-default case statements, create a vector of Cases 2318 // representing each one, and sort the vector so that we can efficiently 2319 // create a binary search tree from them. 2320 CaseVector Cases; 2321 unsigned numCmps = Clusterify(Cases, SI); 2322 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 2323 << ". Total compares: " << numCmps << "\n"; 2324 2325 // Get the Value to be switched on and default basic blocks, which will be 2326 // inserted into CaseBlock records, representing basic blocks in the binary 2327 // search tree. 2328 Value *SV = SI.getOperand(0); 2329 2330 // Push the initial CaseRec onto the worklist 2331 CaseRecVector WorkList; 2332 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 2333 2334 while (!WorkList.empty()) { 2335 // Grab a record representing a case range to process off the worklist 2336 CaseRec CR = WorkList.back(); 2337 WorkList.pop_back(); 2338 2339 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 2340 continue; 2341 2342 // If the range has few cases (two or less) emit a series of specific 2343 // tests. 2344 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 2345 continue; 2346 2347 // If the switch has more than 5 blocks, and at least 40% dense, and the 2348 // target supports indirect branches, then emit a jump table rather than 2349 // lowering the switch to a binary tree of conditional branches. 2350 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 2351 continue; 2352 2353 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2354 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2355 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 2356 } 2357} 2358 2359 2360void SelectionDAGLowering::visitSub(User &I) { 2361 // -0.0 - X --> fneg 2362 const Type *Ty = I.getType(); 2363 if (isa<VectorType>(Ty)) { 2364 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2365 const VectorType *DestTy = cast<VectorType>(I.getType()); 2366 const Type *ElTy = DestTy->getElementType(); 2367 if (ElTy->isFloatingPoint()) { 2368 unsigned VL = DestTy->getNumElements(); 2369 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2370 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2371 if (CV == CNZ) { 2372 SDValue Op2 = getValue(I.getOperand(1)); 2373 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2374 return; 2375 } 2376 } 2377 } 2378 } 2379 if (Ty->isFloatingPoint()) { 2380 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2381 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2382 SDValue Op2 = getValue(I.getOperand(1)); 2383 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2384 return; 2385 } 2386 } 2387 2388 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2389} 2390 2391void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2392 SDValue Op1 = getValue(I.getOperand(0)); 2393 SDValue Op2 = getValue(I.getOperand(1)); 2394 2395 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2396} 2397 2398void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2399 SDValue Op1 = getValue(I.getOperand(0)); 2400 SDValue Op2 = getValue(I.getOperand(1)); 2401 if (!isa<VectorType>(I.getType())) { 2402 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType())) 2403 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2404 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType())) 2405 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2406 } 2407 2408 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2409} 2410 2411void SelectionDAGLowering::visitICmp(User &I) { 2412 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2413 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2414 predicate = IC->getPredicate(); 2415 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2416 predicate = ICmpInst::Predicate(IC->getPredicate()); 2417 SDValue Op1 = getValue(I.getOperand(0)); 2418 SDValue Op2 = getValue(I.getOperand(1)); 2419 ISD::CondCode Opcode; 2420 switch (predicate) { 2421 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2422 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2423 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2424 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2425 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2426 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2427 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2428 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2429 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2430 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2431 default: 2432 assert(!"Invalid ICmp predicate value"); 2433 Opcode = ISD::SETEQ; 2434 break; 2435 } 2436 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2437} 2438 2439void SelectionDAGLowering::visitFCmp(User &I) { 2440 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2441 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2442 predicate = FC->getPredicate(); 2443 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2444 predicate = FCmpInst::Predicate(FC->getPredicate()); 2445 SDValue Op1 = getValue(I.getOperand(0)); 2446 SDValue Op2 = getValue(I.getOperand(1)); 2447 ISD::CondCode Condition, FOC, FPC; 2448 switch (predicate) { 2449 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2450 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2451 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2452 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2453 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2454 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2455 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2456 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 2457 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 2458 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2459 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2460 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2461 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2462 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2463 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2464 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2465 default: 2466 assert(!"Invalid FCmp predicate value"); 2467 FOC = FPC = ISD::SETFALSE; 2468 break; 2469 } 2470 if (FiniteOnlyFPMath()) 2471 Condition = FOC; 2472 else 2473 Condition = FPC; 2474 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2475} 2476 2477void SelectionDAGLowering::visitVICmp(User &I) { 2478 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2479 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I)) 2480 predicate = IC->getPredicate(); 2481 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2482 predicate = ICmpInst::Predicate(IC->getPredicate()); 2483 SDValue Op1 = getValue(I.getOperand(0)); 2484 SDValue Op2 = getValue(I.getOperand(1)); 2485 ISD::CondCode Opcode; 2486 switch (predicate) { 2487 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2488 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2489 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2490 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2491 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2492 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2493 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2494 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2495 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2496 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2497 default: 2498 assert(!"Invalid ICmp predicate value"); 2499 Opcode = ISD::SETEQ; 2500 break; 2501 } 2502 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode)); 2503} 2504 2505void SelectionDAGLowering::visitVFCmp(User &I) { 2506 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2507 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I)) 2508 predicate = FC->getPredicate(); 2509 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2510 predicate = FCmpInst::Predicate(FC->getPredicate()); 2511 SDValue Op1 = getValue(I.getOperand(0)); 2512 SDValue Op2 = getValue(I.getOperand(1)); 2513 ISD::CondCode Condition, FOC, FPC; 2514 switch (predicate) { 2515 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2516 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2517 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2518 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2519 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2520 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2521 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2522 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 2523 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 2524 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2525 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2526 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2527 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2528 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2529 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2530 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2531 default: 2532 assert(!"Invalid VFCmp predicate value"); 2533 FOC = FPC = ISD::SETFALSE; 2534 break; 2535 } 2536 if (FiniteOnlyFPMath()) 2537 Condition = FOC; 2538 else 2539 Condition = FPC; 2540 2541 MVT DestVT = TLI.getValueType(I.getType()); 2542 2543 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition)); 2544} 2545 2546void SelectionDAGLowering::visitSelect(User &I) { 2547 SDValue Cond = getValue(I.getOperand(0)); 2548 SDValue TrueVal = getValue(I.getOperand(1)); 2549 SDValue FalseVal = getValue(I.getOperand(2)); 2550 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2551 TrueVal, FalseVal)); 2552} 2553 2554 2555void SelectionDAGLowering::visitTrunc(User &I) { 2556 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2557 SDValue N = getValue(I.getOperand(0)); 2558 MVT DestVT = TLI.getValueType(I.getType()); 2559 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2560} 2561 2562void SelectionDAGLowering::visitZExt(User &I) { 2563 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2564 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2565 SDValue N = getValue(I.getOperand(0)); 2566 MVT DestVT = TLI.getValueType(I.getType()); 2567 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2568} 2569 2570void SelectionDAGLowering::visitSExt(User &I) { 2571 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2572 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2573 SDValue N = getValue(I.getOperand(0)); 2574 MVT DestVT = TLI.getValueType(I.getType()); 2575 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2576} 2577 2578void SelectionDAGLowering::visitFPTrunc(User &I) { 2579 // FPTrunc is never a no-op cast, no need to check 2580 SDValue N = getValue(I.getOperand(0)); 2581 MVT DestVT = TLI.getValueType(I.getType()); 2582 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0))); 2583} 2584 2585void SelectionDAGLowering::visitFPExt(User &I){ 2586 // FPTrunc is never a no-op cast, no need to check 2587 SDValue N = getValue(I.getOperand(0)); 2588 MVT DestVT = TLI.getValueType(I.getType()); 2589 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2590} 2591 2592void SelectionDAGLowering::visitFPToUI(User &I) { 2593 // FPToUI is never a no-op cast, no need to check 2594 SDValue N = getValue(I.getOperand(0)); 2595 MVT DestVT = TLI.getValueType(I.getType()); 2596 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2597} 2598 2599void SelectionDAGLowering::visitFPToSI(User &I) { 2600 // FPToSI is never a no-op cast, no need to check 2601 SDValue N = getValue(I.getOperand(0)); 2602 MVT DestVT = TLI.getValueType(I.getType()); 2603 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2604} 2605 2606void SelectionDAGLowering::visitUIToFP(User &I) { 2607 // UIToFP is never a no-op cast, no need to check 2608 SDValue N = getValue(I.getOperand(0)); 2609 MVT DestVT = TLI.getValueType(I.getType()); 2610 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2611} 2612 2613void SelectionDAGLowering::visitSIToFP(User &I){ 2614 // UIToFP is never a no-op cast, no need to check 2615 SDValue N = getValue(I.getOperand(0)); 2616 MVT DestVT = TLI.getValueType(I.getType()); 2617 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2618} 2619 2620void SelectionDAGLowering::visitPtrToInt(User &I) { 2621 // What to do depends on the size of the integer and the size of the pointer. 2622 // We can either truncate, zero extend, or no-op, accordingly. 2623 SDValue N = getValue(I.getOperand(0)); 2624 MVT SrcVT = N.getValueType(); 2625 MVT DestVT = TLI.getValueType(I.getType()); 2626 SDValue Result; 2627 if (DestVT.bitsLT(SrcVT)) 2628 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2629 else 2630 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2631 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2632 setValue(&I, Result); 2633} 2634 2635void SelectionDAGLowering::visitIntToPtr(User &I) { 2636 // What to do depends on the size of the integer and the size of the pointer. 2637 // We can either truncate, zero extend, or no-op, accordingly. 2638 SDValue N = getValue(I.getOperand(0)); 2639 MVT SrcVT = N.getValueType(); 2640 MVT DestVT = TLI.getValueType(I.getType()); 2641 if (DestVT.bitsLT(SrcVT)) 2642 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2643 else 2644 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2645 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2646} 2647 2648void SelectionDAGLowering::visitBitCast(User &I) { 2649 SDValue N = getValue(I.getOperand(0)); 2650 MVT DestVT = TLI.getValueType(I.getType()); 2651 2652 // BitCast assures us that source and destination are the same size so this 2653 // is either a BIT_CONVERT or a no-op. 2654 if (DestVT != N.getValueType()) 2655 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2656 else 2657 setValue(&I, N); // noop cast. 2658} 2659 2660void SelectionDAGLowering::visitInsertElement(User &I) { 2661 SDValue InVec = getValue(I.getOperand(0)); 2662 SDValue InVal = getValue(I.getOperand(1)); 2663 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2664 getValue(I.getOperand(2))); 2665 2666 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2667 TLI.getValueType(I.getType()), 2668 InVec, InVal, InIdx)); 2669} 2670 2671void SelectionDAGLowering::visitExtractElement(User &I) { 2672 SDValue InVec = getValue(I.getOperand(0)); 2673 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2674 getValue(I.getOperand(1))); 2675 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2676 TLI.getValueType(I.getType()), InVec, InIdx)); 2677} 2678 2679void SelectionDAGLowering::visitShuffleVector(User &I) { 2680 SDValue V1 = getValue(I.getOperand(0)); 2681 SDValue V2 = getValue(I.getOperand(1)); 2682 SDValue Mask = getValue(I.getOperand(2)); 2683 2684 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2685 TLI.getValueType(I.getType()), 2686 V1, V2, Mask)); 2687} 2688 2689void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) { 2690 const Value *Op0 = I.getOperand(0); 2691 const Value *Op1 = I.getOperand(1); 2692 const Type *AggTy = I.getType(); 2693 const Type *ValTy = Op1->getType(); 2694 bool IntoUndef = isa<UndefValue>(Op0); 2695 bool FromUndef = isa<UndefValue>(Op1); 2696 2697 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2698 I.idx_begin(), I.idx_end()); 2699 2700 SmallVector<MVT, 4> AggValueVTs; 2701 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2702 SmallVector<MVT, 4> ValValueVTs; 2703 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2704 2705 unsigned NumAggValues = AggValueVTs.size(); 2706 unsigned NumValValues = ValValueVTs.size(); 2707 SmallVector<SDValue, 4> Values(NumAggValues); 2708 2709 SDValue Agg = getValue(Op0); 2710 SDValue Val = getValue(Op1); 2711 unsigned i = 0; 2712 // Copy the beginning value(s) from the original aggregate. 2713 for (; i != LinearIndex; ++i) 2714 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : 2715 SDValue(Agg.Val, Agg.ResNo + i); 2716 // Copy values from the inserted value(s). 2717 for (; i != LinearIndex + NumValValues; ++i) 2718 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : 2719 SDValue(Val.Val, Val.ResNo + i - LinearIndex); 2720 // Copy remaining value(s) from the original aggregate. 2721 for (; i != NumAggValues; ++i) 2722 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : 2723 SDValue(Agg.Val, Agg.ResNo + i); 2724 2725 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues), 2726 &Values[0], NumAggValues)); 2727} 2728 2729void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) { 2730 const Value *Op0 = I.getOperand(0); 2731 const Type *AggTy = Op0->getType(); 2732 const Type *ValTy = I.getType(); 2733 bool OutOfUndef = isa<UndefValue>(Op0); 2734 2735 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2736 I.idx_begin(), I.idx_end()); 2737 2738 SmallVector<MVT, 4> ValValueVTs; 2739 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2740 2741 unsigned NumValValues = ValValueVTs.size(); 2742 SmallVector<SDValue, 4> Values(NumValValues); 2743 2744 SDValue Agg = getValue(Op0); 2745 // Copy out the selected value(s). 2746 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2747 Values[i - LinearIndex] = 2748 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) : 2749 SDValue(Agg.Val, Agg.ResNo + i); 2750 2751 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues), 2752 &Values[0], NumValValues)); 2753} 2754 2755 2756void SelectionDAGLowering::visitGetElementPtr(User &I) { 2757 SDValue N = getValue(I.getOperand(0)); 2758 const Type *Ty = I.getOperand(0)->getType(); 2759 2760 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2761 OI != E; ++OI) { 2762 Value *Idx = *OI; 2763 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2764 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2765 if (Field) { 2766 // N = N + Offset 2767 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2768 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2769 DAG.getIntPtrConstant(Offset)); 2770 } 2771 Ty = StTy->getElementType(Field); 2772 } else { 2773 Ty = cast<SequentialType>(Ty)->getElementType(); 2774 2775 // If this is a constant subscript, handle it quickly. 2776 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2777 if (CI->getZExtValue() == 0) continue; 2778 uint64_t Offs = 2779 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2780 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2781 DAG.getIntPtrConstant(Offs)); 2782 continue; 2783 } 2784 2785 // N = N + Idx * ElementSize; 2786 uint64_t ElementSize = TD->getABITypeSize(Ty); 2787 SDValue IdxN = getValue(Idx); 2788 2789 // If the index is smaller or larger than intptr_t, truncate or extend 2790 // it. 2791 if (IdxN.getValueType().bitsLT(N.getValueType())) { 2792 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2793 } else if (IdxN.getValueType().bitsGT(N.getValueType())) 2794 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2795 2796 // If this is a multiply by a power of two, turn it into a shl 2797 // immediately. This is a very common case. 2798 if (isPowerOf2_64(ElementSize)) { 2799 unsigned Amt = Log2_64(ElementSize); 2800 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2801 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2802 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2803 continue; 2804 } 2805 2806 SDValue Scale = DAG.getIntPtrConstant(ElementSize); 2807 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2808 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2809 } 2810 } 2811 setValue(&I, N); 2812} 2813 2814void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2815 // If this is a fixed sized alloca in the entry block of the function, 2816 // allocate it statically on the stack. 2817 if (FuncInfo.StaticAllocaMap.count(&I)) 2818 return; // getValue will auto-populate this. 2819 2820 const Type *Ty = I.getAllocatedType(); 2821 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 2822 unsigned Align = 2823 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2824 I.getAlignment()); 2825 2826 SDValue AllocSize = getValue(I.getArraySize()); 2827 MVT IntPtr = TLI.getPointerTy(); 2828 if (IntPtr.bitsLT(AllocSize.getValueType())) 2829 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2830 else if (IntPtr.bitsGT(AllocSize.getValueType())) 2831 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2832 2833 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2834 DAG.getIntPtrConstant(TySize)); 2835 2836 // Handle alignment. If the requested alignment is less than or equal to 2837 // the stack alignment, ignore it. If the size is greater than or equal to 2838 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2839 unsigned StackAlign = 2840 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2841 if (Align <= StackAlign) 2842 Align = 0; 2843 2844 // Round the size of the allocation up to the stack alignment size 2845 // by add SA-1 to the size. 2846 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2847 DAG.getIntPtrConstant(StackAlign-1)); 2848 // Mask out the low bits for alignment purposes. 2849 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2850 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2851 2852 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2853 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2854 MVT::Other); 2855 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2856 setValue(&I, DSA); 2857 DAG.setRoot(DSA.getValue(1)); 2858 2859 // Inform the Frame Information that we have just allocated a variable-sized 2860 // object. 2861 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2862} 2863 2864void SelectionDAGLowering::visitLoad(LoadInst &I) { 2865 const Value *SV = I.getOperand(0); 2866 SDValue Ptr = getValue(SV); 2867 2868 const Type *Ty = I.getType(); 2869 bool isVolatile = I.isVolatile(); 2870 unsigned Alignment = I.getAlignment(); 2871 2872 SmallVector<MVT, 4> ValueVTs; 2873 SmallVector<uint64_t, 4> Offsets; 2874 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2875 unsigned NumValues = ValueVTs.size(); 2876 if (NumValues == 0) 2877 return; 2878 2879 SDValue Root; 2880 bool ConstantMemory = false; 2881 if (I.isVolatile()) 2882 // Serialize volatile loads with other side effects. 2883 Root = getRoot(); 2884 else if (AA.pointsToConstantMemory(SV)) { 2885 // Do not serialize (non-volatile) loads of constant memory with anything. 2886 Root = DAG.getEntryNode(); 2887 ConstantMemory = true; 2888 } else { 2889 // Do not serialize non-volatile loads against each other. 2890 Root = DAG.getRoot(); 2891 } 2892 2893 SmallVector<SDValue, 4> Values(NumValues); 2894 SmallVector<SDValue, 4> Chains(NumValues); 2895 MVT PtrVT = Ptr.getValueType(); 2896 for (unsigned i = 0; i != NumValues; ++i) { 2897 SDValue L = DAG.getLoad(ValueVTs[i], Root, 2898 DAG.getNode(ISD::ADD, PtrVT, Ptr, 2899 DAG.getConstant(Offsets[i], PtrVT)), 2900 SV, Offsets[i], 2901 isVolatile, Alignment); 2902 Values[i] = L; 2903 Chains[i] = L.getValue(1); 2904 } 2905 2906 if (!ConstantMemory) { 2907 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2908 &Chains[0], NumValues); 2909 if (isVolatile) 2910 DAG.setRoot(Chain); 2911 else 2912 PendingLoads.push_back(Chain); 2913 } 2914 2915 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues), 2916 &Values[0], NumValues)); 2917} 2918 2919 2920void SelectionDAGLowering::visitStore(StoreInst &I) { 2921 Value *SrcV = I.getOperand(0); 2922 Value *PtrV = I.getOperand(1); 2923 2924 SmallVector<MVT, 4> ValueVTs; 2925 SmallVector<uint64_t, 4> Offsets; 2926 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 2927 unsigned NumValues = ValueVTs.size(); 2928 if (NumValues == 0) 2929 return; 2930 2931 // Get the lowered operands. Note that we do this after 2932 // checking if NumResults is zero, because with zero results 2933 // the operands won't have values in the map. 2934 SDValue Src = getValue(SrcV); 2935 SDValue Ptr = getValue(PtrV); 2936 2937 SDValue Root = getRoot(); 2938 SmallVector<SDValue, 4> Chains(NumValues); 2939 MVT PtrVT = Ptr.getValueType(); 2940 bool isVolatile = I.isVolatile(); 2941 unsigned Alignment = I.getAlignment(); 2942 for (unsigned i = 0; i != NumValues; ++i) 2943 Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i), 2944 DAG.getNode(ISD::ADD, PtrVT, Ptr, 2945 DAG.getConstant(Offsets[i], PtrVT)), 2946 PtrV, Offsets[i], 2947 isVolatile, Alignment); 2948 2949 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues)); 2950} 2951 2952/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2953/// node. 2954void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2955 unsigned Intrinsic) { 2956 bool HasChain = !I.doesNotAccessMemory(); 2957 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 2958 2959 // Build the operand list. 2960 SmallVector<SDValue, 8> Ops; 2961 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2962 if (OnlyLoad) { 2963 // We don't need to serialize loads against other loads. 2964 Ops.push_back(DAG.getRoot()); 2965 } else { 2966 Ops.push_back(getRoot()); 2967 } 2968 } 2969 2970 // Add the intrinsic ID as an integer operand. 2971 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2972 2973 // Add all operands of the call to the operand list. 2974 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2975 SDValue Op = getValue(I.getOperand(i)); 2976 assert(TLI.isTypeLegal(Op.getValueType()) && 2977 "Intrinsic uses a non-legal type?"); 2978 Ops.push_back(Op); 2979 } 2980 2981 std::vector<MVT> VTs; 2982 if (I.getType() != Type::VoidTy) { 2983 MVT VT = TLI.getValueType(I.getType()); 2984 if (VT.isVector()) { 2985 const VectorType *DestTy = cast<VectorType>(I.getType()); 2986 MVT EltVT = TLI.getValueType(DestTy->getElementType()); 2987 2988 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements()); 2989 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2990 } 2991 2992 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2993 VTs.push_back(VT); 2994 } 2995 if (HasChain) 2996 VTs.push_back(MVT::Other); 2997 2998 const MVT *VTList = DAG.getNodeValueTypes(VTs); 2999 3000 // Create the node. 3001 SDValue Result; 3002 if (!HasChain) 3003 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 3004 &Ops[0], Ops.size()); 3005 else if (I.getType() != Type::VoidTy) 3006 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 3007 &Ops[0], Ops.size()); 3008 else 3009 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 3010 &Ops[0], Ops.size()); 3011 3012 if (HasChain) { 3013 SDValue Chain = Result.getValue(Result.Val->getNumValues()-1); 3014 if (OnlyLoad) 3015 PendingLoads.push_back(Chain); 3016 else 3017 DAG.setRoot(Chain); 3018 } 3019 if (I.getType() != Type::VoidTy) { 3020 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3021 MVT VT = TLI.getValueType(PTy); 3022 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 3023 } 3024 setValue(&I, Result); 3025 } 3026} 3027 3028/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 3029static GlobalVariable *ExtractTypeInfo (Value *V) { 3030 V = V->stripPointerCasts(); 3031 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 3032 assert ((GV || isa<ConstantPointerNull>(V)) && 3033 "TypeInfo must be a global variable or NULL"); 3034 return GV; 3035} 3036 3037/// addCatchInfo - Extract the personality and type infos from an eh.selector 3038/// call, and add them to the specified machine basic block. 3039static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 3040 MachineBasicBlock *MBB) { 3041 // Inform the MachineModuleInfo of the personality for this landing pad. 3042 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 3043 assert(CE->getOpcode() == Instruction::BitCast && 3044 isa<Function>(CE->getOperand(0)) && 3045 "Personality should be a function"); 3046 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 3047 3048 // Gather all the type infos for this landing pad and pass them along to 3049 // MachineModuleInfo. 3050 std::vector<GlobalVariable *> TyInfo; 3051 unsigned N = I.getNumOperands(); 3052 3053 for (unsigned i = N - 1; i > 2; --i) { 3054 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 3055 unsigned FilterLength = CI->getZExtValue(); 3056 unsigned FirstCatch = i + FilterLength + !FilterLength; 3057 assert (FirstCatch <= N && "Invalid filter length"); 3058 3059 if (FirstCatch < N) { 3060 TyInfo.reserve(N - FirstCatch); 3061 for (unsigned j = FirstCatch; j < N; ++j) 3062 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 3063 MMI->addCatchTypeInfo(MBB, TyInfo); 3064 TyInfo.clear(); 3065 } 3066 3067 if (!FilterLength) { 3068 // Cleanup. 3069 MMI->addCleanup(MBB); 3070 } else { 3071 // Filter. 3072 TyInfo.reserve(FilterLength - 1); 3073 for (unsigned j = i + 1; j < FirstCatch; ++j) 3074 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 3075 MMI->addFilterTypeInfo(MBB, TyInfo); 3076 TyInfo.clear(); 3077 } 3078 3079 N = i; 3080 } 3081 } 3082 3083 if (N > 3) { 3084 TyInfo.reserve(N - 3); 3085 for (unsigned j = 3; j < N; ++j) 3086 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 3087 MMI->addCatchTypeInfo(MBB, TyInfo); 3088 } 3089} 3090 3091 3092/// Inlined utility function to implement binary input atomic intrinsics for 3093// visitIntrinsicCall: I is a call instruction 3094// Op is the associated NodeType for I 3095const char * 3096SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) { 3097 SDValue Root = getRoot(); 3098 SDValue L = DAG.getAtomic(Op, Root, 3099 getValue(I.getOperand(1)), 3100 getValue(I.getOperand(2)), 3101 I.getOperand(1)); 3102 setValue(&I, L); 3103 DAG.setRoot(L.getValue(1)); 3104 return 0; 3105} 3106 3107/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 3108/// we want to emit this as a call to a named external function, return the name 3109/// otherwise lower it and return null. 3110const char * 3111SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 3112 switch (Intrinsic) { 3113 default: 3114 // By default, turn this into a target intrinsic node. 3115 visitTargetIntrinsic(I, Intrinsic); 3116 return 0; 3117 case Intrinsic::vastart: visitVAStart(I); return 0; 3118 case Intrinsic::vaend: visitVAEnd(I); return 0; 3119 case Intrinsic::vacopy: visitVACopy(I); return 0; 3120 case Intrinsic::returnaddress: 3121 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 3122 getValue(I.getOperand(1)))); 3123 return 0; 3124 case Intrinsic::frameaddress: 3125 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 3126 getValue(I.getOperand(1)))); 3127 return 0; 3128 case Intrinsic::setjmp: 3129 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 3130 break; 3131 case Intrinsic::longjmp: 3132 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 3133 break; 3134 case Intrinsic::memcpy_i32: 3135 case Intrinsic::memcpy_i64: { 3136 SDValue Op1 = getValue(I.getOperand(1)); 3137 SDValue Op2 = getValue(I.getOperand(2)); 3138 SDValue Op3 = getValue(I.getOperand(3)); 3139 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3140 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false, 3141 I.getOperand(1), 0, I.getOperand(2), 0)); 3142 return 0; 3143 } 3144 case Intrinsic::memset_i32: 3145 case Intrinsic::memset_i64: { 3146 SDValue Op1 = getValue(I.getOperand(1)); 3147 SDValue Op2 = getValue(I.getOperand(2)); 3148 SDValue Op3 = getValue(I.getOperand(3)); 3149 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3150 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align, 3151 I.getOperand(1), 0)); 3152 return 0; 3153 } 3154 case Intrinsic::memmove_i32: 3155 case Intrinsic::memmove_i64: { 3156 SDValue Op1 = getValue(I.getOperand(1)); 3157 SDValue Op2 = getValue(I.getOperand(2)); 3158 SDValue Op3 = getValue(I.getOperand(3)); 3159 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3160 3161 // If the source and destination are known to not be aliases, we can 3162 // lower memmove as memcpy. 3163 uint64_t Size = -1ULL; 3164 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 3165 Size = C->getValue(); 3166 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) == 3167 AliasAnalysis::NoAlias) { 3168 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false, 3169 I.getOperand(1), 0, I.getOperand(2), 0)); 3170 return 0; 3171 } 3172 3173 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align, 3174 I.getOperand(1), 0, I.getOperand(2), 0)); 3175 return 0; 3176 } 3177 case Intrinsic::dbg_stoppoint: { 3178 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3179 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 3180 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 3181 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 3182 assert(DD && "Not a debug information descriptor"); 3183 DAG.setRoot(DAG.getDbgStopPoint(getRoot(), 3184 SPI.getLine(), 3185 SPI.getColumn(), 3186 cast<CompileUnitDesc>(DD))); 3187 } 3188 3189 return 0; 3190 } 3191 case Intrinsic::dbg_region_start: { 3192 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3193 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 3194 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 3195 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 3196 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); 3197 } 3198 3199 return 0; 3200 } 3201 case Intrinsic::dbg_region_end: { 3202 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3203 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 3204 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 3205 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 3206 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); 3207 } 3208 3209 return 0; 3210 } 3211 case Intrinsic::dbg_func_start: { 3212 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3213 if (!MMI) return 0; 3214 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 3215 Value *SP = FSI.getSubprogram(); 3216 if (SP && MMI->Verify(SP)) { 3217 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is 3218 // what (most?) gdb expects. 3219 DebugInfoDesc *DD = MMI->getDescFor(SP); 3220 assert(DD && "Not a debug information descriptor"); 3221 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD); 3222 const CompileUnitDesc *CompileUnit = Subprogram->getFile(); 3223 unsigned SrcFile = MMI->RecordSource(CompileUnit); 3224 // Record the source line but does create a label. It will be emitted 3225 // at asm emission time. 3226 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile); 3227 } 3228 3229 return 0; 3230 } 3231 case Intrinsic::dbg_declare: { 3232 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3233 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 3234 Value *Variable = DI.getVariable(); 3235 if (MMI && Variable && MMI->Verify(Variable)) 3236 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(), 3237 getValue(DI.getAddress()), getValue(Variable))); 3238 return 0; 3239 } 3240 3241 case Intrinsic::eh_exception: { 3242 if (!CurMBB->isLandingPad()) { 3243 // FIXME: Mark exception register as live in. Hack for PR1508. 3244 unsigned Reg = TLI.getExceptionAddressRegister(); 3245 if (Reg) CurMBB->addLiveIn(Reg); 3246 } 3247 // Insert the EXCEPTIONADDR instruction. 3248 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 3249 SDValue Ops[1]; 3250 Ops[0] = DAG.getRoot(); 3251 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 3252 setValue(&I, Op); 3253 DAG.setRoot(Op.getValue(1)); 3254 return 0; 3255 } 3256 3257 case Intrinsic::eh_selector_i32: 3258 case Intrinsic::eh_selector_i64: { 3259 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3260 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ? 3261 MVT::i32 : MVT::i64); 3262 3263 if (MMI) { 3264 if (CurMBB->isLandingPad()) 3265 addCatchInfo(I, MMI, CurMBB); 3266 else { 3267#ifndef NDEBUG 3268 FuncInfo.CatchInfoLost.insert(&I); 3269#endif 3270 // FIXME: Mark exception selector register as live in. Hack for PR1508. 3271 unsigned Reg = TLI.getExceptionSelectorRegister(); 3272 if (Reg) CurMBB->addLiveIn(Reg); 3273 } 3274 3275 // Insert the EHSELECTION instruction. 3276 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 3277 SDValue Ops[2]; 3278 Ops[0] = getValue(I.getOperand(1)); 3279 Ops[1] = getRoot(); 3280 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 3281 setValue(&I, Op); 3282 DAG.setRoot(Op.getValue(1)); 3283 } else { 3284 setValue(&I, DAG.getConstant(0, VT)); 3285 } 3286 3287 return 0; 3288 } 3289 3290 case Intrinsic::eh_typeid_for_i32: 3291 case Intrinsic::eh_typeid_for_i64: { 3292 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3293 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? 3294 MVT::i32 : MVT::i64); 3295 3296 if (MMI) { 3297 // Find the type id for the given typeinfo. 3298 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 3299 3300 unsigned TypeID = MMI->getTypeIDFor(GV); 3301 setValue(&I, DAG.getConstant(TypeID, VT)); 3302 } else { 3303 // Return something different to eh_selector. 3304 setValue(&I, DAG.getConstant(1, VT)); 3305 } 3306 3307 return 0; 3308 } 3309 3310 case Intrinsic::eh_return: { 3311 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3312 3313 if (MMI) { 3314 MMI->setCallsEHReturn(true); 3315 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, 3316 MVT::Other, 3317 getControlRoot(), 3318 getValue(I.getOperand(1)), 3319 getValue(I.getOperand(2)))); 3320 } else { 3321 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 3322 } 3323 3324 return 0; 3325 } 3326 3327 case Intrinsic::eh_unwind_init: { 3328 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 3329 MMI->setCallsUnwindInit(true); 3330 } 3331 3332 return 0; 3333 } 3334 3335 case Intrinsic::eh_dwarf_cfa: { 3336 MVT VT = getValue(I.getOperand(1)).getValueType(); 3337 SDValue CfaArg; 3338 if (VT.bitsGT(TLI.getPointerTy())) 3339 CfaArg = DAG.getNode(ISD::TRUNCATE, 3340 TLI.getPointerTy(), getValue(I.getOperand(1))); 3341 else 3342 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, 3343 TLI.getPointerTy(), getValue(I.getOperand(1))); 3344 3345 SDValue Offset = DAG.getNode(ISD::ADD, 3346 TLI.getPointerTy(), 3347 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, 3348 TLI.getPointerTy()), 3349 CfaArg); 3350 setValue(&I, DAG.getNode(ISD::ADD, 3351 TLI.getPointerTy(), 3352 DAG.getNode(ISD::FRAMEADDR, 3353 TLI.getPointerTy(), 3354 DAG.getConstant(0, 3355 TLI.getPointerTy())), 3356 Offset)); 3357 return 0; 3358 } 3359 3360 case Intrinsic::sqrt: 3361 setValue(&I, DAG.getNode(ISD::FSQRT, 3362 getValue(I.getOperand(1)).getValueType(), 3363 getValue(I.getOperand(1)))); 3364 return 0; 3365 case Intrinsic::powi: 3366 setValue(&I, DAG.getNode(ISD::FPOWI, 3367 getValue(I.getOperand(1)).getValueType(), 3368 getValue(I.getOperand(1)), 3369 getValue(I.getOperand(2)))); 3370 return 0; 3371 case Intrinsic::sin: 3372 setValue(&I, DAG.getNode(ISD::FSIN, 3373 getValue(I.getOperand(1)).getValueType(), 3374 getValue(I.getOperand(1)))); 3375 return 0; 3376 case Intrinsic::cos: 3377 setValue(&I, DAG.getNode(ISD::FCOS, 3378 getValue(I.getOperand(1)).getValueType(), 3379 getValue(I.getOperand(1)))); 3380 return 0; 3381 case Intrinsic::pow: 3382 setValue(&I, DAG.getNode(ISD::FPOW, 3383 getValue(I.getOperand(1)).getValueType(), 3384 getValue(I.getOperand(1)), 3385 getValue(I.getOperand(2)))); 3386 return 0; 3387 case Intrinsic::pcmarker: { 3388 SDValue Tmp = getValue(I.getOperand(1)); 3389 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 3390 return 0; 3391 } 3392 case Intrinsic::readcyclecounter: { 3393 SDValue Op = getRoot(); 3394 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 3395 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 3396 &Op, 1); 3397 setValue(&I, Tmp); 3398 DAG.setRoot(Tmp.getValue(1)); 3399 return 0; 3400 } 3401 case Intrinsic::part_select: { 3402 // Currently not implemented: just abort 3403 assert(0 && "part_select intrinsic not implemented"); 3404 abort(); 3405 } 3406 case Intrinsic::part_set: { 3407 // Currently not implemented: just abort 3408 assert(0 && "part_set intrinsic not implemented"); 3409 abort(); 3410 } 3411 case Intrinsic::bswap: 3412 setValue(&I, DAG.getNode(ISD::BSWAP, 3413 getValue(I.getOperand(1)).getValueType(), 3414 getValue(I.getOperand(1)))); 3415 return 0; 3416 case Intrinsic::cttz: { 3417 SDValue Arg = getValue(I.getOperand(1)); 3418 MVT Ty = Arg.getValueType(); 3419 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg); 3420 setValue(&I, result); 3421 return 0; 3422 } 3423 case Intrinsic::ctlz: { 3424 SDValue Arg = getValue(I.getOperand(1)); 3425 MVT Ty = Arg.getValueType(); 3426 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg); 3427 setValue(&I, result); 3428 return 0; 3429 } 3430 case Intrinsic::ctpop: { 3431 SDValue Arg = getValue(I.getOperand(1)); 3432 MVT Ty = Arg.getValueType(); 3433 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg); 3434 setValue(&I, result); 3435 return 0; 3436 } 3437 case Intrinsic::stacksave: { 3438 SDValue Op = getRoot(); 3439 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, 3440 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 3441 setValue(&I, Tmp); 3442 DAG.setRoot(Tmp.getValue(1)); 3443 return 0; 3444 } 3445 case Intrinsic::stackrestore: { 3446 SDValue Tmp = getValue(I.getOperand(1)); 3447 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 3448 return 0; 3449 } 3450 case Intrinsic::var_annotation: 3451 // Discard annotate attributes 3452 return 0; 3453 3454 case Intrinsic::init_trampoline: { 3455 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts()); 3456 3457 SDValue Ops[6]; 3458 Ops[0] = getRoot(); 3459 Ops[1] = getValue(I.getOperand(1)); 3460 Ops[2] = getValue(I.getOperand(2)); 3461 Ops[3] = getValue(I.getOperand(3)); 3462 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 3463 Ops[5] = DAG.getSrcValue(F); 3464 3465 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, 3466 DAG.getNodeValueTypes(TLI.getPointerTy(), 3467 MVT::Other), 2, 3468 Ops, 6); 3469 3470 setValue(&I, Tmp); 3471 DAG.setRoot(Tmp.getValue(1)); 3472 return 0; 3473 } 3474 3475 case Intrinsic::gcroot: 3476 if (GCI) { 3477 Value *Alloca = I.getOperand(1); 3478 Constant *TypeMap = cast<Constant>(I.getOperand(2)); 3479 3480 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val); 3481 GCI->addStackRoot(FI->getIndex(), TypeMap); 3482 } 3483 return 0; 3484 3485 case Intrinsic::gcread: 3486 case Intrinsic::gcwrite: 3487 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!"); 3488 return 0; 3489 3490 case Intrinsic::flt_rounds: { 3491 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32)); 3492 return 0; 3493 } 3494 3495 case Intrinsic::trap: { 3496 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot())); 3497 return 0; 3498 } 3499 case Intrinsic::prefetch: { 3500 SDValue Ops[4]; 3501 Ops[0] = getRoot(); 3502 Ops[1] = getValue(I.getOperand(1)); 3503 Ops[2] = getValue(I.getOperand(2)); 3504 Ops[3] = getValue(I.getOperand(3)); 3505 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4)); 3506 return 0; 3507 } 3508 3509 case Intrinsic::memory_barrier: { 3510 SDValue Ops[6]; 3511 Ops[0] = getRoot(); 3512 for (int x = 1; x < 6; ++x) 3513 Ops[x] = getValue(I.getOperand(x)); 3514 3515 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6)); 3516 return 0; 3517 } 3518 case Intrinsic::atomic_cmp_swap: { 3519 SDValue Root = getRoot(); 3520 SDValue L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root, 3521 getValue(I.getOperand(1)), 3522 getValue(I.getOperand(2)), 3523 getValue(I.getOperand(3)), 3524 I.getOperand(1)); 3525 setValue(&I, L); 3526 DAG.setRoot(L.getValue(1)); 3527 return 0; 3528 } 3529 case Intrinsic::atomic_load_add: 3530 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 3531 case Intrinsic::atomic_load_sub: 3532 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 3533 case Intrinsic::atomic_load_and: 3534 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 3535 case Intrinsic::atomic_load_or: 3536 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 3537 case Intrinsic::atomic_load_xor: 3538 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 3539 case Intrinsic::atomic_load_nand: 3540 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 3541 case Intrinsic::atomic_load_min: 3542 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 3543 case Intrinsic::atomic_load_max: 3544 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 3545 case Intrinsic::atomic_load_umin: 3546 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 3547 case Intrinsic::atomic_load_umax: 3548 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 3549 case Intrinsic::atomic_swap: 3550 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 3551 } 3552} 3553 3554 3555void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee, 3556 bool IsTailCall, 3557 MachineBasicBlock *LandingPad) { 3558 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 3559 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 3560 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3561 unsigned BeginLabel = 0, EndLabel = 0; 3562 3563 TargetLowering::ArgListTy Args; 3564 TargetLowering::ArgListEntry Entry; 3565 Args.reserve(CS.arg_size()); 3566 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 3567 i != e; ++i) { 3568 SDValue ArgNode = getValue(*i); 3569 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 3570 3571 unsigned attrInd = i - CS.arg_begin() + 1; 3572 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt); 3573 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt); 3574 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg); 3575 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet); 3576 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest); 3577 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal); 3578 Entry.Alignment = CS.getParamAlignment(attrInd); 3579 Args.push_back(Entry); 3580 } 3581 3582 if (LandingPad && MMI) { 3583 // Insert a label before the invoke call to mark the try range. This can be 3584 // used to detect deletion of the invoke via the MachineModuleInfo. 3585 BeginLabel = MMI->NextLabelID(); 3586 // Both PendingLoads and PendingExports must be flushed here; 3587 // this call might not return. 3588 (void)getRoot(); 3589 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel)); 3590 } 3591 3592 std::pair<SDValue,SDValue> Result = 3593 TLI.LowerCallTo(getRoot(), CS.getType(), 3594 CS.paramHasAttr(0, ParamAttr::SExt), 3595 CS.paramHasAttr(0, ParamAttr::ZExt), 3596 FTy->isVarArg(), CS.getCallingConv(), IsTailCall, 3597 Callee, Args, DAG); 3598 if (CS.getType() != Type::VoidTy) 3599 setValue(CS.getInstruction(), Result.first); 3600 DAG.setRoot(Result.second); 3601 3602 if (LandingPad && MMI) { 3603 // Insert a label at the end of the invoke call to mark the try range. This 3604 // can be used to detect deletion of the invoke via the MachineModuleInfo. 3605 EndLabel = MMI->NextLabelID(); 3606 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel)); 3607 3608 // Inform MachineModuleInfo of range. 3609 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 3610 } 3611} 3612 3613 3614void SelectionDAGLowering::visitCall(CallInst &I) { 3615 const char *RenameFn = 0; 3616 if (Function *F = I.getCalledFunction()) { 3617 if (F->isDeclaration()) { 3618 if (unsigned IID = F->getIntrinsicID()) { 3619 RenameFn = visitIntrinsicCall(I, IID); 3620 if (!RenameFn) 3621 return; 3622 } 3623 } 3624 3625 // Check for well-known libc/libm calls. If the function is internal, it 3626 // can't be a library call. 3627 unsigned NameLen = F->getNameLen(); 3628 if (!F->hasInternalLinkage() && NameLen) { 3629 const char *NameStr = F->getNameStart(); 3630 if (NameStr[0] == 'c' && 3631 ((NameLen == 8 && !strcmp(NameStr, "copysign")) || 3632 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) { 3633 if (I.getNumOperands() == 3 && // Basic sanity checks. 3634 I.getOperand(1)->getType()->isFloatingPoint() && 3635 I.getType() == I.getOperand(1)->getType() && 3636 I.getType() == I.getOperand(2)->getType()) { 3637 SDValue LHS = getValue(I.getOperand(1)); 3638 SDValue RHS = getValue(I.getOperand(2)); 3639 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 3640 LHS, RHS)); 3641 return; 3642 } 3643 } else if (NameStr[0] == 'f' && 3644 ((NameLen == 4 && !strcmp(NameStr, "fabs")) || 3645 (NameLen == 5 && !strcmp(NameStr, "fabsf")) || 3646 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) { 3647 if (I.getNumOperands() == 2 && // Basic sanity checks. 3648 I.getOperand(1)->getType()->isFloatingPoint() && 3649 I.getType() == I.getOperand(1)->getType()) { 3650 SDValue Tmp = getValue(I.getOperand(1)); 3651 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 3652 return; 3653 } 3654 } else if (NameStr[0] == 's' && 3655 ((NameLen == 3 && !strcmp(NameStr, "sin")) || 3656 (NameLen == 4 && !strcmp(NameStr, "sinf")) || 3657 (NameLen == 4 && !strcmp(NameStr, "sinl")))) { 3658 if (I.getNumOperands() == 2 && // Basic sanity checks. 3659 I.getOperand(1)->getType()->isFloatingPoint() && 3660 I.getType() == I.getOperand(1)->getType()) { 3661 SDValue Tmp = getValue(I.getOperand(1)); 3662 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 3663 return; 3664 } 3665 } else if (NameStr[0] == 'c' && 3666 ((NameLen == 3 && !strcmp(NameStr, "cos")) || 3667 (NameLen == 4 && !strcmp(NameStr, "cosf")) || 3668 (NameLen == 4 && !strcmp(NameStr, "cosl")))) { 3669 if (I.getNumOperands() == 2 && // Basic sanity checks. 3670 I.getOperand(1)->getType()->isFloatingPoint() && 3671 I.getType() == I.getOperand(1)->getType()) { 3672 SDValue Tmp = getValue(I.getOperand(1)); 3673 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 3674 return; 3675 } 3676 } 3677 } 3678 } else if (isa<InlineAsm>(I.getOperand(0))) { 3679 visitInlineAsm(&I); 3680 return; 3681 } 3682 3683 SDValue Callee; 3684 if (!RenameFn) 3685 Callee = getValue(I.getOperand(0)); 3686 else 3687 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 3688 3689 LowerCallTo(&I, Callee, I.isTailCall()); 3690} 3691 3692 3693/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 3694/// this value and returns the result as a ValueVT value. This uses 3695/// Chain/Flag as the input and updates them for the output Chain/Flag. 3696/// If the Flag pointer is NULL, no flag is used. 3697SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 3698 SDValue &Chain, 3699 SDValue *Flag) const { 3700 // Assemble the legal parts into the final values. 3701 SmallVector<SDValue, 4> Values(ValueVTs.size()); 3702 SmallVector<SDValue, 8> Parts; 3703 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 3704 // Copy the legal parts from the registers. 3705 MVT ValueVT = ValueVTs[Value]; 3706 unsigned NumRegs = TLI->getNumRegisters(ValueVT); 3707 MVT RegisterVT = RegVTs[Value]; 3708 3709 Parts.resize(NumRegs); 3710 for (unsigned i = 0; i != NumRegs; ++i) { 3711 SDValue P; 3712 if (Flag == 0) 3713 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT); 3714 else { 3715 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag); 3716 *Flag = P.getValue(2); 3717 } 3718 Chain = P.getValue(1); 3719 3720 // If the source register was virtual and if we know something about it, 3721 // add an assert node. 3722 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && 3723 RegisterVT.isInteger() && !RegisterVT.isVector()) { 3724 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; 3725 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 3726 if (FLI.LiveOutRegInfo.size() > SlotNo) { 3727 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo]; 3728 3729 unsigned RegSize = RegisterVT.getSizeInBits(); 3730 unsigned NumSignBits = LOI.NumSignBits; 3731 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 3732 3733 // FIXME: We capture more information than the dag can represent. For 3734 // now, just use the tightest assertzext/assertsext possible. 3735 bool isSExt = true; 3736 MVT FromVT(MVT::Other); 3737 if (NumSignBits == RegSize) 3738 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 3739 else if (NumZeroBits >= RegSize-1) 3740 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 3741 else if (NumSignBits > RegSize-8) 3742 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 3743 else if (NumZeroBits >= RegSize-9) 3744 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 3745 else if (NumSignBits > RegSize-16) 3746 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 3747 else if (NumZeroBits >= RegSize-17) 3748 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 3749 else if (NumSignBits > RegSize-32) 3750 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 3751 else if (NumZeroBits >= RegSize-33) 3752 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 3753 3754 if (FromVT != MVT::Other) { 3755 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, 3756 RegisterVT, P, DAG.getValueType(FromVT)); 3757 3758 } 3759 } 3760 } 3761 3762 Parts[Part+i] = P; 3763 } 3764 3765 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT, 3766 ValueVT); 3767 Part += NumRegs; 3768 } 3769 3770 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 3771 &Values[0], ValueVTs.size()); 3772} 3773 3774/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 3775/// specified value into the registers specified by this object. This uses 3776/// Chain/Flag as the input and updates them for the output Chain/Flag. 3777/// If the Flag pointer is NULL, no flag is used. 3778void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, 3779 SDValue &Chain, SDValue *Flag) const { 3780 // Get the list of the values's legal parts. 3781 unsigned NumRegs = Regs.size(); 3782 SmallVector<SDValue, 8> Parts(NumRegs); 3783 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 3784 MVT ValueVT = ValueVTs[Value]; 3785 unsigned NumParts = TLI->getNumRegisters(ValueVT); 3786 MVT RegisterVT = RegVTs[Value]; 3787 3788 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value), 3789 &Parts[Part], NumParts, RegisterVT); 3790 Part += NumParts; 3791 } 3792 3793 // Copy the parts into the registers. 3794 SmallVector<SDValue, 8> Chains(NumRegs); 3795 for (unsigned i = 0; i != NumRegs; ++i) { 3796 SDValue Part; 3797 if (Flag == 0) 3798 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]); 3799 else { 3800 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag); 3801 *Flag = Part.getValue(1); 3802 } 3803 Chains[i] = Part.getValue(0); 3804 } 3805 3806 if (NumRegs == 1 || Flag) 3807 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 3808 // flagged to it. That is the CopyToReg nodes and the user are considered 3809 // a single scheduling unit. If we create a TokenFactor and return it as 3810 // chain, then the TokenFactor is both a predecessor (operand) of the 3811 // user as well as a successor (the TF operands are flagged to the user). 3812 // c1, f1 = CopyToReg 3813 // c2, f2 = CopyToReg 3814 // c3 = TokenFactor c1, c2 3815 // ... 3816 // = op c3, ..., f2 3817 Chain = Chains[NumRegs-1]; 3818 else 3819 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 3820} 3821 3822/// AddInlineAsmOperands - Add this value to the specified inlineasm node 3823/// operand list. This adds the code marker and includes the number of 3824/// values added into it. 3825void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 3826 std::vector<SDValue> &Ops) const { 3827 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3828 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3829 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 3830 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]); 3831 MVT RegisterVT = RegVTs[Value]; 3832 for (unsigned i = 0; i != NumRegs; ++i) 3833 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 3834 } 3835} 3836 3837/// isAllocatableRegister - If the specified register is safe to allocate, 3838/// i.e. it isn't a stack pointer or some other special register, return the 3839/// register class for the register. Otherwise, return null. 3840static const TargetRegisterClass * 3841isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3842 const TargetLowering &TLI, 3843 const TargetRegisterInfo *TRI) { 3844 MVT FoundVT = MVT::Other; 3845 const TargetRegisterClass *FoundRC = 0; 3846 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 3847 E = TRI->regclass_end(); RCI != E; ++RCI) { 3848 MVT ThisVT = MVT::Other; 3849 3850 const TargetRegisterClass *RC = *RCI; 3851 // If none of the the value types for this register class are valid, we 3852 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3853 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3854 I != E; ++I) { 3855 if (TLI.isTypeLegal(*I)) { 3856 // If we have already found this register in a different register class, 3857 // choose the one with the largest VT specified. For example, on 3858 // PowerPC, we favor f64 register classes over f32. 3859 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 3860 ThisVT = *I; 3861 break; 3862 } 3863 } 3864 } 3865 3866 if (ThisVT == MVT::Other) continue; 3867 3868 // NOTE: This isn't ideal. In particular, this might allocate the 3869 // frame pointer in functions that need it (due to them not being taken 3870 // out of allocation, because a variable sized allocation hasn't been seen 3871 // yet). This is a slight code pessimization, but should still work. 3872 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3873 E = RC->allocation_order_end(MF); I != E; ++I) 3874 if (*I == Reg) { 3875 // We found a matching register class. Keep looking at others in case 3876 // we find one with larger registers that this physreg is also in. 3877 FoundRC = RC; 3878 FoundVT = ThisVT; 3879 break; 3880 } 3881 } 3882 return FoundRC; 3883} 3884 3885 3886namespace { 3887/// AsmOperandInfo - This contains information for each constraint that we are 3888/// lowering. 3889struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 3890 /// CallOperand - If this is the result output operand or a clobber 3891 /// this is null, otherwise it is the incoming operand to the CallInst. 3892 /// This gets modified as the asm is processed. 3893 SDValue CallOperand; 3894 3895 /// AssignedRegs - If this is a register or register class operand, this 3896 /// contains the set of register corresponding to the operand. 3897 RegsForValue AssignedRegs; 3898 3899 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3900 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 3901 } 3902 3903 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3904 /// busy in OutputRegs/InputRegs. 3905 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3906 std::set<unsigned> &OutputRegs, 3907 std::set<unsigned> &InputRegs, 3908 const TargetRegisterInfo &TRI) const { 3909 if (isOutReg) { 3910 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 3911 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 3912 } 3913 if (isInReg) { 3914 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 3915 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 3916 } 3917 } 3918 3919private: 3920 /// MarkRegAndAliases - Mark the specified register and all aliases in the 3921 /// specified set. 3922 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 3923 const TargetRegisterInfo &TRI) { 3924 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 3925 Regs.insert(Reg); 3926 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 3927 for (; *Aliases; ++Aliases) 3928 Regs.insert(*Aliases); 3929 } 3930}; 3931} // end anon namespace. 3932 3933 3934/// GetRegistersForValue - Assign registers (virtual or physical) for the 3935/// specified operand. We prefer to assign virtual registers, to allow the 3936/// register allocator handle the assignment process. However, if the asm uses 3937/// features that we can't model on machineinstrs, we have SDISel do the 3938/// allocation. This produces generally horrible, but correct, code. 3939/// 3940/// OpInfo describes the operand. 3941/// HasEarlyClobber is true if there are any early clobber constraints (=&r) 3942/// or any explicitly clobbered registers. 3943/// Input and OutputRegs are the set of already allocated physical registers. 3944/// 3945void SelectionDAGLowering:: 3946GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber, 3947 std::set<unsigned> &OutputRegs, 3948 std::set<unsigned> &InputRegs) { 3949 // Compute whether this value requires an input register, an output register, 3950 // or both. 3951 bool isOutReg = false; 3952 bool isInReg = false; 3953 switch (OpInfo.Type) { 3954 case InlineAsm::isOutput: 3955 isOutReg = true; 3956 3957 // If this is an early-clobber output, or if there is an input 3958 // constraint that matches this, we need to reserve the input register 3959 // so no other inputs allocate to it. 3960 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3961 break; 3962 case InlineAsm::isInput: 3963 isInReg = true; 3964 isOutReg = false; 3965 break; 3966 case InlineAsm::isClobber: 3967 isOutReg = true; 3968 isInReg = true; 3969 break; 3970 } 3971 3972 3973 MachineFunction &MF = DAG.getMachineFunction(); 3974 SmallVector<unsigned, 4> Regs; 3975 3976 // If this is a constraint for a single physreg, or a constraint for a 3977 // register class, find it. 3978 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3979 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3980 OpInfo.ConstraintVT); 3981 3982 unsigned NumRegs = 1; 3983 if (OpInfo.ConstraintVT != MVT::Other) 3984 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3985 MVT RegVT; 3986 MVT ValueVT = OpInfo.ConstraintVT; 3987 3988 3989 // If this is a constraint for a specific physical register, like {r17}, 3990 // assign it now. 3991 if (PhysReg.first) { 3992 if (OpInfo.ConstraintVT == MVT::Other) 3993 ValueVT = *PhysReg.second->vt_begin(); 3994 3995 // Get the actual register value type. This is important, because the user 3996 // may have asked for (e.g.) the AX register in i32 type. We need to 3997 // remember that AX is actually i16 to get the right extension. 3998 RegVT = *PhysReg.second->vt_begin(); 3999 4000 // This is a explicit reference to a physical register. 4001 Regs.push_back(PhysReg.first); 4002 4003 // If this is an expanded reference, add the rest of the regs to Regs. 4004 if (NumRegs != 1) { 4005 TargetRegisterClass::iterator I = PhysReg.second->begin(); 4006 for (; *I != PhysReg.first; ++I) 4007 assert(I != PhysReg.second->end() && "Didn't find reg!"); 4008 4009 // Already added the first reg. 4010 --NumRegs; ++I; 4011 for (; NumRegs; --NumRegs, ++I) { 4012 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!"); 4013 Regs.push_back(*I); 4014 } 4015 } 4016 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); 4017 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4018 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 4019 return; 4020 } 4021 4022 // Otherwise, if this was a reference to an LLVM register class, create vregs 4023 // for this reference. 4024 std::vector<unsigned> RegClassRegs; 4025 const TargetRegisterClass *RC = PhysReg.second; 4026 if (RC) { 4027 // If this is an early clobber or tied register, our regalloc doesn't know 4028 // how to maintain the constraint. If it isn't, go ahead and create vreg 4029 // and let the regalloc do the right thing. 4030 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 4031 // If there is some other early clobber and this is an input register, 4032 // then we are forced to pre-allocate the input reg so it doesn't 4033 // conflict with the earlyclobber. 4034 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 4035 RegVT = *PhysReg.second->vt_begin(); 4036 4037 if (OpInfo.ConstraintVT == MVT::Other) 4038 ValueVT = RegVT; 4039 4040 // Create the appropriate number of virtual registers. 4041 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4042 for (; NumRegs; --NumRegs) 4043 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second)); 4044 4045 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); 4046 return; 4047 } 4048 4049 // Otherwise, we can't allocate it. Let the code below figure out how to 4050 // maintain these constraints. 4051 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 4052 4053 } else { 4054 // This is a reference to a register class that doesn't directly correspond 4055 // to an LLVM register class. Allocate NumRegs consecutive, available, 4056 // registers from the class. 4057 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 4058 OpInfo.ConstraintVT); 4059 } 4060 4061 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4062 unsigned NumAllocated = 0; 4063 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 4064 unsigned Reg = RegClassRegs[i]; 4065 // See if this register is available. 4066 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 4067 (isInReg && InputRegs.count(Reg))) { // Already used. 4068 // Make sure we find consecutive registers. 4069 NumAllocated = 0; 4070 continue; 4071 } 4072 4073 // Check to see if this register is allocatable (i.e. don't give out the 4074 // stack pointer). 4075 if (RC == 0) { 4076 RC = isAllocatableRegister(Reg, MF, TLI, TRI); 4077 if (!RC) { // Couldn't allocate this register. 4078 // Reset NumAllocated to make sure we return consecutive registers. 4079 NumAllocated = 0; 4080 continue; 4081 } 4082 } 4083 4084 // Okay, this register is good, we can use it. 4085 ++NumAllocated; 4086 4087 // If we allocated enough consecutive registers, succeed. 4088 if (NumAllocated == NumRegs) { 4089 unsigned RegStart = (i-NumAllocated)+1; 4090 unsigned RegEnd = i+1; 4091 // Mark all of the allocated registers used. 4092 for (unsigned i = RegStart; i != RegEnd; ++i) 4093 Regs.push_back(RegClassRegs[i]); 4094 4095 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(), 4096 OpInfo.ConstraintVT); 4097 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 4098 return; 4099 } 4100 } 4101 4102 // Otherwise, we couldn't allocate enough registers for this. 4103} 4104 4105 4106/// visitInlineAsm - Handle a call to an InlineAsm object. 4107/// 4108void SelectionDAGLowering::visitInlineAsm(CallSite CS) { 4109 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 4110 4111 /// ConstraintOperands - Information about all of the constraints. 4112 std::vector<SDISelAsmOperandInfo> ConstraintOperands; 4113 4114 SDValue Chain = getRoot(); 4115 SDValue Flag; 4116 4117 std::set<unsigned> OutputRegs, InputRegs; 4118 4119 // Do a prepass over the constraints, canonicalizing them, and building up the 4120 // ConstraintOperands list. 4121 std::vector<InlineAsm::ConstraintInfo> 4122 ConstraintInfos = IA->ParseConstraints(); 4123 4124 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 4125 // constraint. If so, we can't let the register allocator allocate any input 4126 // registers, because it will not know to avoid the earlyclobbered output reg. 4127 bool SawEarlyClobber = false; 4128 4129 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 4130 unsigned ResNo = 0; // ResNo - The result number of the next output. 4131 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 4132 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); 4133 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 4134 4135 MVT OpVT = MVT::Other; 4136 4137 // Compute the value type for each operand. 4138 switch (OpInfo.Type) { 4139 case InlineAsm::isOutput: 4140 // Indirect outputs just consume an argument. 4141 if (OpInfo.isIndirect) { 4142 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 4143 break; 4144 } 4145 // The return value of the call is this value. As such, there is no 4146 // corresponding argument. 4147 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 4148 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 4149 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 4150 } else { 4151 assert(ResNo == 0 && "Asm only has one result!"); 4152 OpVT = TLI.getValueType(CS.getType()); 4153 } 4154 ++ResNo; 4155 break; 4156 case InlineAsm::isInput: 4157 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 4158 break; 4159 case InlineAsm::isClobber: 4160 // Nothing to do. 4161 break; 4162 } 4163 4164 // If this is an input or an indirect output, process the call argument. 4165 // BasicBlocks are labels, currently appearing only in asm's. 4166 if (OpInfo.CallOperandVal) { 4167 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) 4168 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 4169 else { 4170 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 4171 const Type *OpTy = OpInfo.CallOperandVal->getType(); 4172 // If this is an indirect operand, the operand is a pointer to the 4173 // accessed type. 4174 if (OpInfo.isIndirect) 4175 OpTy = cast<PointerType>(OpTy)->getElementType(); 4176 4177 // If OpTy is not a single value, it may be a struct/union that we 4178 // can tile with integers. 4179 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 4180 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 4181 switch (BitSize) { 4182 default: break; 4183 case 1: 4184 case 8: 4185 case 16: 4186 case 32: 4187 case 64: 4188 OpTy = IntegerType::get(BitSize); 4189 break; 4190 } 4191 } 4192 4193 OpVT = TLI.getValueType(OpTy, true); 4194 } 4195 } 4196 4197 OpInfo.ConstraintVT = OpVT; 4198 4199 // Compute the constraint code and ConstraintType to use. 4200 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 4201 4202 // Keep track of whether we see an earlyclobber. 4203 SawEarlyClobber |= OpInfo.isEarlyClobber; 4204 4205 // If we see a clobber of a register, it is an early clobber. 4206 if (!SawEarlyClobber && 4207 OpInfo.Type == InlineAsm::isClobber && 4208 OpInfo.ConstraintType == TargetLowering::C_Register) { 4209 // Note that we want to ignore things that we don't trick here, like 4210 // dirflag, fpsr, flags, etc. 4211 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 4212 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 4213 OpInfo.ConstraintVT); 4214 if (PhysReg.first || PhysReg.second) { 4215 // This is a register we know of. 4216 SawEarlyClobber = true; 4217 } 4218 } 4219 4220 // If this is a memory input, and if the operand is not indirect, do what we 4221 // need to to provide an address for the memory input. 4222 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 4223 !OpInfo.isIndirect) { 4224 assert(OpInfo.Type == InlineAsm::isInput && 4225 "Can only indirectify direct input operands!"); 4226 4227 // Memory operands really want the address of the value. If we don't have 4228 // an indirect input, put it in the constpool if we can, otherwise spill 4229 // it to a stack slot. 4230 4231 // If the operand is a float, integer, or vector constant, spill to a 4232 // constant pool entry to get its address. 4233 Value *OpVal = OpInfo.CallOperandVal; 4234 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 4235 isa<ConstantVector>(OpVal)) { 4236 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 4237 TLI.getPointerTy()); 4238 } else { 4239 // Otherwise, create a stack slot and emit a store to it before the 4240 // asm. 4241 const Type *Ty = OpVal->getType(); 4242 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 4243 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 4244 MachineFunction &MF = DAG.getMachineFunction(); 4245 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 4246 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4247 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 4248 OpInfo.CallOperand = StackSlot; 4249 } 4250 4251 // There is no longer a Value* corresponding to this operand. 4252 OpInfo.CallOperandVal = 0; 4253 // It is now an indirect operand. 4254 OpInfo.isIndirect = true; 4255 } 4256 4257 // If this constraint is for a specific register, allocate it before 4258 // anything else. 4259 if (OpInfo.ConstraintType == TargetLowering::C_Register) 4260 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 4261 } 4262 ConstraintInfos.clear(); 4263 4264 4265 // Second pass - Loop over all of the operands, assigning virtual or physregs 4266 // to registerclass operands. 4267 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 4268 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 4269 4270 // C_Register operands have already been allocated, Other/Memory don't need 4271 // to be. 4272 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 4273 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 4274 } 4275 4276 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 4277 std::vector<SDValue> AsmNodeOperands; 4278 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 4279 AsmNodeOperands.push_back( 4280 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 4281 4282 4283 // Loop over all of the inputs, copying the operand values into the 4284 // appropriate registers and processing the output regs. 4285 RegsForValue RetValRegs; 4286 4287 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 4288 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 4289 4290 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 4291 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 4292 4293 switch (OpInfo.Type) { 4294 case InlineAsm::isOutput: { 4295 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 4296 OpInfo.ConstraintType != TargetLowering::C_Register) { 4297 // Memory output, or 'other' output (e.g. 'X' constraint). 4298 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 4299 4300 // Add information to the INLINEASM node to know about this output. 4301 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 4302 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4303 TLI.getPointerTy())); 4304 AsmNodeOperands.push_back(OpInfo.CallOperand); 4305 break; 4306 } 4307 4308 // Otherwise, this is a register or register class output. 4309 4310 // Copy the output from the appropriate register. Find a register that 4311 // we can use. 4312 if (OpInfo.AssignedRegs.Regs.empty()) { 4313 cerr << "Couldn't allocate output reg for constraint '" 4314 << OpInfo.ConstraintCode << "'!\n"; 4315 exit(1); 4316 } 4317 4318 // If this is an indirect operand, store through the pointer after the 4319 // asm. 4320 if (OpInfo.isIndirect) { 4321 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 4322 OpInfo.CallOperandVal)); 4323 } else { 4324 // This is the result value of the call. 4325 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 4326 // Concatenate this output onto the outputs list. 4327 RetValRegs.append(OpInfo.AssignedRegs); 4328 } 4329 4330 // Add information to the INLINEASM node to know that this register is 4331 // set. 4332 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 4333 AsmNodeOperands); 4334 break; 4335 } 4336 case InlineAsm::isInput: { 4337 SDValue InOperandVal = OpInfo.CallOperand; 4338 4339 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 4340 // If this is required to match an output register we have already set, 4341 // just use its register. 4342 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 4343 4344 // Scan until we find the definition we already emitted of this operand. 4345 // When we find it, create a RegsForValue operand. 4346 unsigned CurOp = 2; // The first operand. 4347 for (; OperandNo; --OperandNo) { 4348 // Advance to the next operand. 4349 unsigned NumOps = 4350 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 4351 assert(((NumOps & 7) == 2 /*REGDEF*/ || 4352 (NumOps & 7) == 4 /*MEM*/) && 4353 "Skipped past definitions?"); 4354 CurOp += (NumOps>>3)+1; 4355 } 4356 4357 unsigned NumOps = 4358 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 4359 if ((NumOps & 7) == 2 /*REGDEF*/) { 4360 // Add NumOps>>3 registers to MatchedRegs. 4361 RegsForValue MatchedRegs; 4362 MatchedRegs.TLI = &TLI; 4363 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 4364 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType()); 4365 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 4366 unsigned Reg = 4367 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 4368 MatchedRegs.Regs.push_back(Reg); 4369 } 4370 4371 // Use the produced MatchedRegs object to 4372 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 4373 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 4374 break; 4375 } else { 4376 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 4377 assert((NumOps >> 3) == 1 && "Unexpected number of operands"); 4378 // Add information to the INLINEASM node to know about this input. 4379 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 4380 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4381 TLI.getPointerTy())); 4382 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 4383 break; 4384 } 4385 } 4386 4387 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 4388 assert(!OpInfo.isIndirect && 4389 "Don't know how to handle indirect other inputs yet!"); 4390 4391 std::vector<SDValue> Ops; 4392 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 4393 Ops, DAG); 4394 if (Ops.empty()) { 4395 cerr << "Invalid operand for inline asm constraint '" 4396 << OpInfo.ConstraintCode << "'!\n"; 4397 exit(1); 4398 } 4399 4400 // Add information to the INLINEASM node to know about this input. 4401 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 4402 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4403 TLI.getPointerTy())); 4404 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 4405 break; 4406 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 4407 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 4408 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 4409 "Memory operands expect pointer values"); 4410 4411 // Add information to the INLINEASM node to know about this input. 4412 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 4413 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4414 TLI.getPointerTy())); 4415 AsmNodeOperands.push_back(InOperandVal); 4416 break; 4417 } 4418 4419 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 4420 OpInfo.ConstraintType == TargetLowering::C_Register) && 4421 "Unknown constraint type!"); 4422 assert(!OpInfo.isIndirect && 4423 "Don't know how to handle indirect register inputs yet!"); 4424 4425 // Copy the input into the appropriate registers. 4426 assert(!OpInfo.AssignedRegs.Regs.empty() && 4427 "Couldn't allocate input reg!"); 4428 4429 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 4430 4431 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 4432 AsmNodeOperands); 4433 break; 4434 } 4435 case InlineAsm::isClobber: { 4436 // Add the clobbered value to the operand list, so that the register 4437 // allocator is aware that the physreg got clobbered. 4438 if (!OpInfo.AssignedRegs.Regs.empty()) 4439 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 4440 AsmNodeOperands); 4441 break; 4442 } 4443 } 4444 } 4445 4446 // Finish up input operands. 4447 AsmNodeOperands[0] = Chain; 4448 if (Flag.Val) AsmNodeOperands.push_back(Flag); 4449 4450 Chain = DAG.getNode(ISD::INLINEASM, 4451 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 4452 &AsmNodeOperands[0], AsmNodeOperands.size()); 4453 Flag = Chain.getValue(1); 4454 4455 // If this asm returns a register value, copy the result from that register 4456 // and set it as the value of the call. 4457 if (!RetValRegs.Regs.empty()) { 4458 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 4459 4460 // If any of the results of the inline asm is a vector, it may have the 4461 // wrong width/num elts. This can happen for register classes that can 4462 // contain multiple different value types. The preg or vreg allocated may 4463 // not have the same VT as was expected. Convert it to the right type with 4464 // bit_convert. 4465 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) { 4466 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) { 4467 if (Val.Val->getValueType(i).isVector()) 4468 Val = DAG.getNode(ISD::BIT_CONVERT, 4469 TLI.getValueType(ResSTy->getElementType(i)), Val); 4470 } 4471 } else { 4472 if (Val.getValueType().isVector()) 4473 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()), 4474 Val); 4475 } 4476 4477 setValue(CS.getInstruction(), Val); 4478 } 4479 4480 std::vector<std::pair<SDValue, Value*> > StoresToEmit; 4481 4482 // Process indirect outputs, first output all of the flagged copies out of 4483 // physregs. 4484 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 4485 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 4486 Value *Ptr = IndirectStoresToEmit[i].second; 4487 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 4488 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 4489 } 4490 4491 // Emit the non-flagged stores from the physregs. 4492 SmallVector<SDValue, 8> OutChains; 4493 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 4494 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 4495 getValue(StoresToEmit[i].second), 4496 StoresToEmit[i].second, 0)); 4497 if (!OutChains.empty()) 4498 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4499 &OutChains[0], OutChains.size()); 4500 DAG.setRoot(Chain); 4501} 4502 4503 4504void SelectionDAGLowering::visitMalloc(MallocInst &I) { 4505 SDValue Src = getValue(I.getOperand(0)); 4506 4507 MVT IntPtr = TLI.getPointerTy(); 4508 4509 if (IntPtr.bitsLT(Src.getValueType())) 4510 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 4511 else if (IntPtr.bitsGT(Src.getValueType())) 4512 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 4513 4514 // Scale the source by the type size. 4515 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType()); 4516 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 4517 Src, DAG.getIntPtrConstant(ElementSize)); 4518 4519 TargetLowering::ArgListTy Args; 4520 TargetLowering::ArgListEntry Entry; 4521 Entry.Node = Src; 4522 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 4523 Args.push_back(Entry); 4524 4525 std::pair<SDValue,SDValue> Result = 4526 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C, 4527 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG); 4528 setValue(&I, Result.first); // Pointers always fit in registers 4529 DAG.setRoot(Result.second); 4530} 4531 4532void SelectionDAGLowering::visitFree(FreeInst &I) { 4533 TargetLowering::ArgListTy Args; 4534 TargetLowering::ArgListEntry Entry; 4535 Entry.Node = getValue(I.getOperand(0)); 4536 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 4537 Args.push_back(Entry); 4538 MVT IntPtr = TLI.getPointerTy(); 4539 std::pair<SDValue,SDValue> Result = 4540 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, 4541 CallingConv::C, true, 4542 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 4543 DAG.setRoot(Result.second); 4544} 4545 4546// EmitInstrWithCustomInserter - This method should be implemented by targets 4547// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 4548// instructions are special in various ways, which require special support to 4549// insert. The specified MachineInstr is created but not inserted into any 4550// basic blocks, and the scheduler passes ownership of it to this method. 4551MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4552 MachineBasicBlock *MBB) { 4553 cerr << "If a target marks an instruction with " 4554 << "'usesCustomDAGSchedInserter', it must implement " 4555 << "TargetLowering::EmitInstrWithCustomInserter!\n"; 4556 abort(); 4557 return 0; 4558} 4559 4560void SelectionDAGLowering::visitVAStart(CallInst &I) { 4561 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 4562 getValue(I.getOperand(1)), 4563 DAG.getSrcValue(I.getOperand(1)))); 4564} 4565 4566void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 4567 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 4568 getValue(I.getOperand(0)), 4569 DAG.getSrcValue(I.getOperand(0))); 4570 setValue(&I, V); 4571 DAG.setRoot(V.getValue(1)); 4572} 4573 4574void SelectionDAGLowering::visitVAEnd(CallInst &I) { 4575 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 4576 getValue(I.getOperand(1)), 4577 DAG.getSrcValue(I.getOperand(1)))); 4578} 4579 4580void SelectionDAGLowering::visitVACopy(CallInst &I) { 4581 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 4582 getValue(I.getOperand(1)), 4583 getValue(I.getOperand(2)), 4584 DAG.getSrcValue(I.getOperand(1)), 4585 DAG.getSrcValue(I.getOperand(2)))); 4586} 4587 4588/// TargetLowering::LowerArguments - This is the default LowerArguments 4589/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 4590/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 4591/// integrated into SDISel. 4592void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, 4593 SmallVectorImpl<SDValue> &ArgValues) { 4594 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 4595 SmallVector<SDValue, 3+16> Ops; 4596 Ops.push_back(DAG.getRoot()); 4597 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 4598 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 4599 4600 // Add one result value for each formal argument. 4601 SmallVector<MVT, 16> RetVals; 4602 unsigned j = 1; 4603 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 4604 I != E; ++I, ++j) { 4605 SmallVector<MVT, 4> ValueVTs; 4606 ComputeValueVTs(*this, I->getType(), ValueVTs); 4607 for (unsigned Value = 0, NumValues = ValueVTs.size(); 4608 Value != NumValues; ++Value) { 4609 MVT VT = ValueVTs[Value]; 4610 const Type *ArgTy = VT.getTypeForMVT(); 4611 ISD::ArgFlagsTy Flags; 4612 unsigned OriginalAlignment = 4613 getTargetData()->getABITypeAlignment(ArgTy); 4614 4615 if (F.paramHasAttr(j, ParamAttr::ZExt)) 4616 Flags.setZExt(); 4617 if (F.paramHasAttr(j, ParamAttr::SExt)) 4618 Flags.setSExt(); 4619 if (F.paramHasAttr(j, ParamAttr::InReg)) 4620 Flags.setInReg(); 4621 if (F.paramHasAttr(j, ParamAttr::StructRet)) 4622 Flags.setSRet(); 4623 if (F.paramHasAttr(j, ParamAttr::ByVal)) { 4624 Flags.setByVal(); 4625 const PointerType *Ty = cast<PointerType>(I->getType()); 4626 const Type *ElementTy = Ty->getElementType(); 4627 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 4628 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); 4629 // For ByVal, alignment should be passed from FE. BE will guess if 4630 // this info is not there but there are cases it cannot get right. 4631 if (F.getParamAlignment(j)) 4632 FrameAlign = F.getParamAlignment(j); 4633 Flags.setByValAlign(FrameAlign); 4634 Flags.setByValSize(FrameSize); 4635 } 4636 if (F.paramHasAttr(j, ParamAttr::Nest)) 4637 Flags.setNest(); 4638 Flags.setOrigAlign(OriginalAlignment); 4639 4640 MVT RegisterVT = getRegisterType(VT); 4641 unsigned NumRegs = getNumRegisters(VT); 4642 for (unsigned i = 0; i != NumRegs; ++i) { 4643 RetVals.push_back(RegisterVT); 4644 ISD::ArgFlagsTy MyFlags = Flags; 4645 if (NumRegs > 1 && i == 0) 4646 MyFlags.setSplit(); 4647 // if it isn't first piece, alignment must be 1 4648 else if (i > 0) 4649 MyFlags.setOrigAlign(1); 4650 Ops.push_back(DAG.getArgFlags(MyFlags)); 4651 } 4652 } 4653 } 4654 4655 RetVals.push_back(MVT::Other); 4656 4657 // Create the node. 4658 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 4659 DAG.getVTList(&RetVals[0], RetVals.size()), 4660 &Ops[0], Ops.size()).Val; 4661 4662 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but 4663 // allows exposing the loads that may be part of the argument access to the 4664 // first DAGCombiner pass. 4665 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG); 4666 4667 // The number of results should match up, except that the lowered one may have 4668 // an extra flag result. 4669 assert((Result->getNumValues() == TmpRes.Val->getNumValues() || 4670 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() && 4671 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag)) 4672 && "Lowering produced unexpected number of results!"); 4673 4674 // The FORMAL_ARGUMENTS node itself is likely no longer needed. 4675 if (Result != TmpRes.Val && Result->use_empty()) { 4676 HandleSDNode Dummy(DAG.getRoot()); 4677 DAG.RemoveDeadNode(Result); 4678 } 4679 4680 Result = TmpRes.Val; 4681 4682 unsigned NumArgRegs = Result->getNumValues() - 1; 4683 DAG.setRoot(SDValue(Result, NumArgRegs)); 4684 4685 // Set up the return result vector. 4686 unsigned i = 0; 4687 unsigned Idx = 1; 4688 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 4689 ++I, ++Idx) { 4690 SmallVector<MVT, 4> ValueVTs; 4691 ComputeValueVTs(*this, I->getType(), ValueVTs); 4692 for (unsigned Value = 0, NumValues = ValueVTs.size(); 4693 Value != NumValues; ++Value) { 4694 MVT VT = ValueVTs[Value]; 4695 MVT PartVT = getRegisterType(VT); 4696 4697 unsigned NumParts = getNumRegisters(VT); 4698 SmallVector<SDValue, 4> Parts(NumParts); 4699 for (unsigned j = 0; j != NumParts; ++j) 4700 Parts[j] = SDValue(Result, i++); 4701 4702 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4703 if (F.paramHasAttr(Idx, ParamAttr::SExt)) 4704 AssertOp = ISD::AssertSext; 4705 else if (F.paramHasAttr(Idx, ParamAttr::ZExt)) 4706 AssertOp = ISD::AssertZext; 4707 4708 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT, 4709 AssertOp)); 4710 } 4711 } 4712 assert(i == NumArgRegs && "Argument register count mismatch!"); 4713} 4714 4715 4716/// TargetLowering::LowerCallTo - This is the default LowerCallTo 4717/// implementation, which just inserts an ISD::CALL node, which is later custom 4718/// lowered by the target to something concrete. FIXME: When all targets are 4719/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 4720std::pair<SDValue, SDValue> 4721TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 4722 bool RetSExt, bool RetZExt, bool isVarArg, 4723 unsigned CallingConv, bool isTailCall, 4724 SDValue Callee, 4725 ArgListTy &Args, SelectionDAG &DAG) { 4726 SmallVector<SDValue, 32> Ops; 4727 Ops.push_back(Chain); // Op#0 - Chain 4728 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 4729 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 4730 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 4731 Ops.push_back(Callee); 4732 4733 // Handle all of the outgoing arguments. 4734 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 4735 SmallVector<MVT, 4> ValueVTs; 4736 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 4737 for (unsigned Value = 0, NumValues = ValueVTs.size(); 4738 Value != NumValues; ++Value) { 4739 MVT VT = ValueVTs[Value]; 4740 const Type *ArgTy = VT.getTypeForMVT(); 4741 SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value); 4742 ISD::ArgFlagsTy Flags; 4743 unsigned OriginalAlignment = 4744 getTargetData()->getABITypeAlignment(ArgTy); 4745 4746 if (Args[i].isZExt) 4747 Flags.setZExt(); 4748 if (Args[i].isSExt) 4749 Flags.setSExt(); 4750 if (Args[i].isInReg) 4751 Flags.setInReg(); 4752 if (Args[i].isSRet) 4753 Flags.setSRet(); 4754 if (Args[i].isByVal) { 4755 Flags.setByVal(); 4756 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 4757 const Type *ElementTy = Ty->getElementType(); 4758 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 4759 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); 4760 // For ByVal, alignment should come from FE. BE will guess if this 4761 // info is not there but there are cases it cannot get right. 4762 if (Args[i].Alignment) 4763 FrameAlign = Args[i].Alignment; 4764 Flags.setByValAlign(FrameAlign); 4765 Flags.setByValSize(FrameSize); 4766 } 4767 if (Args[i].isNest) 4768 Flags.setNest(); 4769 Flags.setOrigAlign(OriginalAlignment); 4770 4771 MVT PartVT = getRegisterType(VT); 4772 unsigned NumParts = getNumRegisters(VT); 4773 SmallVector<SDValue, 4> Parts(NumParts); 4774 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 4775 4776 if (Args[i].isSExt) 4777 ExtendKind = ISD::SIGN_EXTEND; 4778 else if (Args[i].isZExt) 4779 ExtendKind = ISD::ZERO_EXTEND; 4780 4781 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind); 4782 4783 for (unsigned i = 0; i != NumParts; ++i) { 4784 // if it isn't first piece, alignment must be 1 4785 ISD::ArgFlagsTy MyFlags = Flags; 4786 if (NumParts > 1 && i == 0) 4787 MyFlags.setSplit(); 4788 else if (i != 0) 4789 MyFlags.setOrigAlign(1); 4790 4791 Ops.push_back(Parts[i]); 4792 Ops.push_back(DAG.getArgFlags(MyFlags)); 4793 } 4794 } 4795 } 4796 4797 // Figure out the result value types. We start by making a list of 4798 // the potentially illegal return value types. 4799 SmallVector<MVT, 4> LoweredRetTys; 4800 SmallVector<MVT, 4> RetTys; 4801 ComputeValueVTs(*this, RetTy, RetTys); 4802 4803 // Then we translate that to a list of legal types. 4804 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4805 MVT VT = RetTys[I]; 4806 MVT RegisterVT = getRegisterType(VT); 4807 unsigned NumRegs = getNumRegisters(VT); 4808 for (unsigned i = 0; i != NumRegs; ++i) 4809 LoweredRetTys.push_back(RegisterVT); 4810 } 4811 4812 LoweredRetTys.push_back(MVT::Other); // Always has a chain. 4813 4814 // Create the CALL node. 4815 SDValue Res = DAG.getNode(ISD::CALL, 4816 DAG.getVTList(&LoweredRetTys[0], 4817 LoweredRetTys.size()), 4818 &Ops[0], Ops.size()); 4819 Chain = Res.getValue(LoweredRetTys.size() - 1); 4820 4821 // Gather up the call result into a single value. 4822 if (RetTy != Type::VoidTy) { 4823 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4824 4825 if (RetSExt) 4826 AssertOp = ISD::AssertSext; 4827 else if (RetZExt) 4828 AssertOp = ISD::AssertZext; 4829 4830 SmallVector<SDValue, 4> ReturnValues; 4831 unsigned RegNo = 0; 4832 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4833 MVT VT = RetTys[I]; 4834 MVT RegisterVT = getRegisterType(VT); 4835 unsigned NumRegs = getNumRegisters(VT); 4836 unsigned RegNoEnd = NumRegs + RegNo; 4837 SmallVector<SDValue, 4> Results; 4838 for (; RegNo != RegNoEnd; ++RegNo) 4839 Results.push_back(Res.getValue(RegNo)); 4840 SDValue ReturnValue = 4841 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, 4842 AssertOp); 4843 ReturnValues.push_back(ReturnValue); 4844 } 4845 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()), 4846 &ReturnValues[0], ReturnValues.size()); 4847 } 4848 4849 return std::make_pair(Res, Chain); 4850} 4851 4852SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 4853 assert(0 && "LowerOperation not implemented for this target!"); 4854 abort(); 4855 return SDValue(); 4856} 4857 4858 4859//===----------------------------------------------------------------------===// 4860// SelectionDAGISel code 4861//===----------------------------------------------------------------------===// 4862 4863unsigned SelectionDAGISel::MakeReg(MVT VT) { 4864 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 4865} 4866 4867void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4868 AU.addRequired<AliasAnalysis>(); 4869 AU.addRequired<CollectorModuleMetadata>(); 4870 AU.setPreservesAll(); 4871} 4872 4873bool SelectionDAGISel::runOnFunction(Function &Fn) { 4874 // Get alias analysis for load/store combining. 4875 AA = &getAnalysis<AliasAnalysis>(); 4876 4877 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4878 if (MF.getFunction()->hasCollector()) 4879 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction()); 4880 else 4881 GCI = 0; 4882 RegInfo = &MF.getRegInfo(); 4883 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4884 4885 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4886 4887 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4888 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4889 // Mark landing pad. 4890 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4891 4892 SelectAllBasicBlocks(Fn, MF, FuncInfo); 4893 4894 // Add function live-ins to entry block live-in set. 4895 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4896 BB = FuncInfo.MBBMap[EntryBB]; 4897 if (!RegInfo->livein_empty()) 4898 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 4899 E = RegInfo->livein_end(); I != E; ++I) 4900 BB->addLiveIn(I->first); 4901 4902#ifndef NDEBUG 4903 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4904 "Not all catch info was assigned to a landing pad!"); 4905#endif 4906 4907 return true; 4908} 4909 4910void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) { 4911 SDValue Op = getValue(V); 4912 assert((Op.getOpcode() != ISD::CopyFromReg || 4913 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4914 "Copy from a reg to the same reg!"); 4915 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 4916 4917 RegsForValue RFV(TLI, Reg, V->getType()); 4918 SDValue Chain = DAG.getEntryNode(); 4919 RFV.getCopyToRegs(Op, DAG, Chain, 0); 4920 PendingExports.push_back(Chain); 4921} 4922 4923void SelectionDAGISel:: 4924LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) { 4925 // If this is the entry block, emit arguments. 4926 Function &F = *LLVMBB->getParent(); 4927 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4928 SDValue OldRoot = SDL.DAG.getRoot(); 4929 SmallVector<SDValue, 16> Args; 4930 TLI.LowerArguments(F, SDL.DAG, Args); 4931 4932 unsigned a = 0; 4933 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4934 AI != E; ++AI) { 4935 SmallVector<MVT, 4> ValueVTs; 4936 ComputeValueVTs(TLI, AI->getType(), ValueVTs); 4937 unsigned NumValues = ValueVTs.size(); 4938 if (!AI->use_empty()) { 4939 SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues)); 4940 // If this argument is live outside of the entry block, insert a copy from 4941 // whereever we got it to the vreg that other BB's will reference it as. 4942 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4943 if (VMI != FuncInfo.ValueMap.end()) { 4944 SDL.CopyValueToVirtualRegister(AI, VMI->second); 4945 } 4946 } 4947 a += NumValues; 4948 } 4949 4950 // Finally, if the target has anything special to do, allow it to do so. 4951 // FIXME: this should insert code into the DAG! 4952 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4953} 4954 4955static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4956 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4957 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4958 if (isSelector(I)) { 4959 // Apply the catch info to DestBB. 4960 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4961#ifndef NDEBUG 4962 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 4963 FLI.CatchInfoFound.insert(I); 4964#endif 4965 } 4966} 4967 4968/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and 4969/// whether object offset >= 0. 4970static bool 4971IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) { 4972 if (!isa<FrameIndexSDNode>(Op)) return false; 4973 4974 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op); 4975 int FrameIdx = FrameIdxNode->getIndex(); 4976 return MFI->isFixedObjectIndex(FrameIdx) && 4977 MFI->getObjectOffset(FrameIdx) >= 0; 4978} 4979 4980/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could 4981/// possibly be overwritten when lowering the outgoing arguments in a tail 4982/// call. Currently the implementation of this call is very conservative and 4983/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with 4984/// virtual registers would be overwritten by direct lowering. 4985static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op, 4986 MachineFrameInfo * MFI) { 4987 RegisterSDNode * OpReg = NULL; 4988 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS || 4989 (Op.getOpcode()== ISD::CopyFromReg && 4990 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) && 4991 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) || 4992 (Op.getOpcode() == ISD::LOAD && 4993 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) || 4994 (Op.getOpcode() == ISD::MERGE_VALUES && 4995 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD && 4996 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo). 4997 getOperand(1)))) 4998 return true; 4999 return false; 5000} 5001 5002/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 5003/// DAG and fixes their tailcall attribute operand. 5004static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 5005 TargetLowering& TLI) { 5006 SDNode * Ret = NULL; 5007 SDValue Terminator = DAG.getRoot(); 5008 5009 // Find RET node. 5010 if (Terminator.getOpcode() == ISD::RET) { 5011 Ret = Terminator.Val; 5012 } 5013 5014 // Fix tail call attribute of CALL nodes. 5015 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 5016 BI = DAG.allnodes_end(); BI != BE; ) { 5017 --BI; 5018 if (BI->getOpcode() == ISD::CALL) { 5019 SDValue OpRet(Ret, 0); 5020 SDValue OpCall(BI, 0); 5021 bool isMarkedTailCall = 5022 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0; 5023 // If CALL node has tail call attribute set to true and the call is not 5024 // eligible (no RET or the target rejects) the attribute is fixed to 5025 // false. The TargetLowering::IsEligibleForTailCallOptimization function 5026 // must correctly identify tail call optimizable calls. 5027 if (!isMarkedTailCall) continue; 5028 if (Ret==NULL || 5029 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) { 5030 // Not eligible. Mark CALL node as non tail call. 5031 SmallVector<SDValue, 32> Ops; 5032 unsigned idx=0; 5033 for(SDNode::op_iterator I =OpCall.Val->op_begin(), 5034 E = OpCall.Val->op_end(); I != E; I++, idx++) { 5035 if (idx!=3) 5036 Ops.push_back(*I); 5037 else 5038 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy())); 5039 } 5040 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 5041 } else { 5042 // Look for tail call clobbered arguments. Emit a series of 5043 // copyto/copyfrom virtual register nodes to protect them. 5044 SmallVector<SDValue, 32> Ops; 5045 SDValue Chain = OpCall.getOperand(0), InFlag; 5046 unsigned idx=0; 5047 for(SDNode::op_iterator I = OpCall.Val->op_begin(), 5048 E = OpCall.Val->op_end(); I != E; I++, idx++) { 5049 SDValue Arg = *I; 5050 if (idx > 4 && (idx % 2)) { 5051 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))-> 5052 getArgFlags().isByVal(); 5053 MachineFunction &MF = DAG.getMachineFunction(); 5054 MachineFrameInfo *MFI = MF.getFrameInfo(); 5055 if (!isByVal && 5056 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) { 5057 MVT VT = Arg.getValueType(); 5058 unsigned VReg = MF.getRegInfo(). 5059 createVirtualRegister(TLI.getRegClassFor(VT)); 5060 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag); 5061 InFlag = Chain.getValue(1); 5062 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag); 5063 Chain = Arg.getValue(1); 5064 InFlag = Arg.getValue(2); 5065 } 5066 } 5067 Ops.push_back(Arg); 5068 } 5069 // Link in chain of CopyTo/CopyFromReg. 5070 Ops[0] = Chain; 5071 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 5072 } 5073 } 5074 } 5075} 5076 5077void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 5078 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 5079 FunctionLoweringInfo &FuncInfo) { 5080 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI); 5081 5082 // Lower any arguments needed in this block if this is the entry block. 5083 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 5084 LowerArguments(LLVMBB, SDL); 5085 5086 BB = FuncInfo.MBBMap[LLVMBB]; 5087 SDL.setCurrentBasicBlock(BB); 5088 5089 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 5090 5091 if (MMI && BB->isLandingPad()) { 5092 // Add a label to mark the beginning of the landing pad. Deletion of the 5093 // landing pad can thus be detected via the MachineModuleInfo. 5094 unsigned LabelID = MMI->addLandingPad(BB); 5095 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID)); 5096 5097 // Mark exception register as live in. 5098 unsigned Reg = TLI.getExceptionAddressRegister(); 5099 if (Reg) BB->addLiveIn(Reg); 5100 5101 // Mark exception selector register as live in. 5102 Reg = TLI.getExceptionSelectorRegister(); 5103 if (Reg) BB->addLiveIn(Reg); 5104 5105 // FIXME: Hack around an exception handling flaw (PR1508): the personality 5106 // function and list of typeids logically belong to the invoke (or, if you 5107 // like, the basic block containing the invoke), and need to be associated 5108 // with it in the dwarf exception handling tables. Currently however the 5109 // information is provided by an intrinsic (eh.selector) that can be moved 5110 // to unexpected places by the optimizers: if the unwind edge is critical, 5111 // then breaking it can result in the intrinsics being in the successor of 5112 // the landing pad, not the landing pad itself. This results in exceptions 5113 // not being caught because no typeids are associated with the invoke. 5114 // This may not be the only way things can go wrong, but it is the only way 5115 // we try to work around for the moment. 5116 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 5117 5118 if (Br && Br->isUnconditional()) { // Critical edge? 5119 BasicBlock::iterator I, E; 5120 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 5121 if (isSelector(I)) 5122 break; 5123 5124 if (I == E) 5125 // No catch info found - try to extract some from the successor. 5126 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 5127 } 5128 } 5129 5130 // Lower all of the non-terminator instructions. 5131 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 5132 I != E; ++I) 5133 SDL.visit(*I); 5134 5135 // Ensure that all instructions which are used outside of their defining 5136 // blocks are available as virtual registers. Invoke is handled elsewhere. 5137 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 5138 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 5139 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 5140 if (VMI != FuncInfo.ValueMap.end()) 5141 SDL.CopyValueToVirtualRegister(I, VMI->second); 5142 } 5143 5144 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 5145 // ensure constants are generated when needed. Remember the virtual registers 5146 // that need to be added to the Machine PHI nodes as input. We cannot just 5147 // directly add them, because expansion might result in multiple MBB's for one 5148 // BB. As such, the start of the BB might correspond to a different MBB than 5149 // the end. 5150 // 5151 TerminatorInst *TI = LLVMBB->getTerminator(); 5152 5153 // Emit constants only once even if used by multiple PHI nodes. 5154 std::map<Constant*, unsigned> ConstantsOut; 5155 5156 // Vector bool would be better, but vector<bool> is really slow. 5157 std::vector<unsigned char> SuccsHandled; 5158 if (TI->getNumSuccessors()) 5159 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 5160 5161 // Check successor nodes' PHI nodes that expect a constant to be available 5162 // from this block. 5163 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 5164 BasicBlock *SuccBB = TI->getSuccessor(succ); 5165 if (!isa<PHINode>(SuccBB->begin())) continue; 5166 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 5167 5168 // If this terminator has multiple identical successors (common for 5169 // switches), only handle each succ once. 5170 unsigned SuccMBBNo = SuccMBB->getNumber(); 5171 if (SuccsHandled[SuccMBBNo]) continue; 5172 SuccsHandled[SuccMBBNo] = true; 5173 5174 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 5175 PHINode *PN; 5176 5177 // At this point we know that there is a 1-1 correspondence between LLVM PHI 5178 // nodes and Machine PHI nodes, but the incoming operands have not been 5179 // emitted yet. 5180 for (BasicBlock::iterator I = SuccBB->begin(); 5181 (PN = dyn_cast<PHINode>(I)); ++I) { 5182 // Ignore dead phi's. 5183 if (PN->use_empty()) continue; 5184 5185 unsigned Reg; 5186 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 5187 5188 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 5189 unsigned &RegOut = ConstantsOut[C]; 5190 if (RegOut == 0) { 5191 RegOut = FuncInfo.CreateRegForValue(C); 5192 SDL.CopyValueToVirtualRegister(C, RegOut); 5193 } 5194 Reg = RegOut; 5195 } else { 5196 Reg = FuncInfo.ValueMap[PHIOp]; 5197 if (Reg == 0) { 5198 assert(isa<AllocaInst>(PHIOp) && 5199 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 5200 "Didn't codegen value into a register!??"); 5201 Reg = FuncInfo.CreateRegForValue(PHIOp); 5202 SDL.CopyValueToVirtualRegister(PHIOp, Reg); 5203 } 5204 } 5205 5206 // Remember that this register needs to added to the machine PHI node as 5207 // the input for this MBB. 5208 SmallVector<MVT, 4> ValueVTs; 5209 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 5210 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 5211 MVT VT = ValueVTs[vti]; 5212 unsigned NumRegisters = TLI.getNumRegisters(VT); 5213 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 5214 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 5215 Reg += NumRegisters; 5216 } 5217 } 5218 } 5219 ConstantsOut.clear(); 5220 5221 // Lower the terminator after the copies are emitted. 5222 SDL.visit(*LLVMBB->getTerminator()); 5223 5224 // Copy over any CaseBlock records that may now exist due to SwitchInst 5225 // lowering, as well as any jump table information. 5226 SwitchCases.clear(); 5227 SwitchCases = SDL.SwitchCases; 5228 JTCases.clear(); 5229 JTCases = SDL.JTCases; 5230 BitTestCases.clear(); 5231 BitTestCases = SDL.BitTestCases; 5232 5233 // Make sure the root of the DAG is up-to-date. 5234 DAG.setRoot(SDL.getControlRoot()); 5235 5236 // Check whether calls in this block are real tail calls. Fix up CALL nodes 5237 // with correct tailcall attribute so that the target can rely on the tailcall 5238 // attribute indicating whether the call is really eligible for tail call 5239 // optimization. 5240 CheckDAGForTailCallsAndFixThem(DAG, TLI); 5241} 5242 5243void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) { 5244 SmallPtrSet<SDNode*, 128> VisitedNodes; 5245 SmallVector<SDNode*, 128> Worklist; 5246 5247 Worklist.push_back(DAG.getRoot().Val); 5248 5249 APInt Mask; 5250 APInt KnownZero; 5251 APInt KnownOne; 5252 5253 while (!Worklist.empty()) { 5254 SDNode *N = Worklist.back(); 5255 Worklist.pop_back(); 5256 5257 // If we've already seen this node, ignore it. 5258 if (!VisitedNodes.insert(N)) 5259 continue; 5260 5261 // Otherwise, add all chain operands to the worklist. 5262 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5263 if (N->getOperand(i).getValueType() == MVT::Other) 5264 Worklist.push_back(N->getOperand(i).Val); 5265 5266 // If this is a CopyToReg with a vreg dest, process it. 5267 if (N->getOpcode() != ISD::CopyToReg) 5268 continue; 5269 5270 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 5271 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 5272 continue; 5273 5274 // Ignore non-scalar or non-integer values. 5275 SDValue Src = N->getOperand(2); 5276 MVT SrcVT = Src.getValueType(); 5277 if (!SrcVT.isInteger() || SrcVT.isVector()) 5278 continue; 5279 5280 unsigned NumSignBits = DAG.ComputeNumSignBits(Src); 5281 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 5282 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 5283 5284 // Only install this information if it tells us something. 5285 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 5286 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 5287 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 5288 if (DestReg >= FLI.LiveOutRegInfo.size()) 5289 FLI.LiveOutRegInfo.resize(DestReg+1); 5290 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg]; 5291 LOI.NumSignBits = NumSignBits; 5292 LOI.KnownOne = NumSignBits; 5293 LOI.KnownZero = NumSignBits; 5294 } 5295 } 5296} 5297 5298void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 5299 std::string GroupName; 5300 if (TimePassesIsEnabled) 5301 GroupName = "Instruction Selection and Scheduling"; 5302 std::string BlockName; 5303 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 5304 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs) 5305 BlockName = DAG.getMachineFunction().getFunction()->getName() + ':' + 5306 BB->getBasicBlock()->getName(); 5307 5308 DOUT << "Initial selection DAG:\n"; 5309 DEBUG(DAG.dump()); 5310 5311 if (ViewDAGCombine1) DAG.viewGraph("dag-combine1 input for " + BlockName); 5312 5313 // Run the DAG combiner in pre-legalize mode. 5314 if (TimePassesIsEnabled) { 5315 NamedRegionTimer T("DAG Combining 1", GroupName); 5316 DAG.Combine(false, *AA); 5317 } else { 5318 DAG.Combine(false, *AA); 5319 } 5320 5321 DOUT << "Optimized lowered selection DAG:\n"; 5322 DEBUG(DAG.dump()); 5323 5324 // Second step, hack on the DAG until it only uses operations and types that 5325 // the target supports. 5326 if (EnableLegalizeTypes) {// Enable this some day. 5327 if (ViewLegalizeTypesDAGs) DAG.viewGraph("legalize-types input for " + 5328 BlockName); 5329 5330 if (TimePassesIsEnabled) { 5331 NamedRegionTimer T("Type Legalization", GroupName); 5332 DAG.LegalizeTypes(); 5333 } else { 5334 DAG.LegalizeTypes(); 5335 } 5336 5337 DOUT << "Type-legalized selection DAG:\n"; 5338 DEBUG(DAG.dump()); 5339 5340 // TODO: enable a dag combine pass here. 5341 } 5342 5343 if (ViewLegalizeDAGs) DAG.viewGraph("legalize input for " + BlockName); 5344 5345 if (TimePassesIsEnabled) { 5346 NamedRegionTimer T("DAG Legalization", GroupName); 5347 DAG.Legalize(); 5348 } else { 5349 DAG.Legalize(); 5350 } 5351 5352 DOUT << "Legalized selection DAG:\n"; 5353 DEBUG(DAG.dump()); 5354 5355 if (ViewDAGCombine2) DAG.viewGraph("dag-combine2 input for " + BlockName); 5356 5357 // Run the DAG combiner in post-legalize mode. 5358 if (TimePassesIsEnabled) { 5359 NamedRegionTimer T("DAG Combining 2", GroupName); 5360 DAG.Combine(true, *AA); 5361 } else { 5362 DAG.Combine(true, *AA); 5363 } 5364 5365 DOUT << "Optimized legalized selection DAG:\n"; 5366 DEBUG(DAG.dump()); 5367 5368 if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName); 5369 5370 if (!FastISel && EnableValueProp) 5371 ComputeLiveOutVRegInfo(DAG); 5372 5373 // Third, instruction select all of the operations to machine code, adding the 5374 // code to the MachineBasicBlock. 5375 if (TimePassesIsEnabled) { 5376 NamedRegionTimer T("Instruction Selection", GroupName); 5377 InstructionSelect(DAG); 5378 } else { 5379 InstructionSelect(DAG); 5380 } 5381 5382 DOUT << "Selected selection DAG:\n"; 5383 DEBUG(DAG.dump()); 5384 5385 if (ViewSchedDAGs) DAG.viewGraph("scheduler input for " + BlockName); 5386 5387 // Schedule machine code. 5388 ScheduleDAG *Scheduler; 5389 if (TimePassesIsEnabled) { 5390 NamedRegionTimer T("Instruction Scheduling", GroupName); 5391 Scheduler = Schedule(DAG); 5392 } else { 5393 Scheduler = Schedule(DAG); 5394 } 5395 5396 if (ViewSUnitDAGs) Scheduler->viewGraph(); 5397 5398 // Emit machine code to BB. This can change 'BB' to the last block being 5399 // inserted into. 5400 if (TimePassesIsEnabled) { 5401 NamedRegionTimer T("Instruction Creation", GroupName); 5402 BB = Scheduler->EmitSchedule(); 5403 } else { 5404 BB = Scheduler->EmitSchedule(); 5405 } 5406 5407 // Free the scheduler state. 5408 if (TimePassesIsEnabled) { 5409 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 5410 delete Scheduler; 5411 } else { 5412 delete Scheduler; 5413 } 5414 5415 // Perform target specific isel post processing. 5416 if (TimePassesIsEnabled) { 5417 NamedRegionTimer T("Instruction Selection Post Processing", GroupName); 5418 InstructionSelectPostProcessing(); 5419 } else { 5420 InstructionSelectPostProcessing(); 5421 } 5422 5423 DOUT << "Selected machine code:\n"; 5424 DEBUG(BB->dump()); 5425} 5426 5427void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF, 5428 FunctionLoweringInfo &FuncInfo) { 5429 // Define NodeAllocator here so that memory allocation is reused for 5430 // each basic block. 5431 NodeAllocatorType NodeAllocator; 5432 5433 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 5434 SelectBasicBlock(I, MF, FuncInfo, NodeAllocator); 5435} 5436 5437void 5438SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 5439 FunctionLoweringInfo &FuncInfo, 5440 NodeAllocatorType &NodeAllocator) { 5441 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 5442 { 5443 SelectionDAG DAG(TLI, MF, FuncInfo, 5444 getAnalysisToUpdate<MachineModuleInfo>(), 5445 NodeAllocator); 5446 CurDAG = &DAG; 5447 5448 // First step, lower LLVM code to some DAG. This DAG may use operations and 5449 // types that are not supported by the target. 5450 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 5451 5452 // Second step, emit the lowered DAG as machine code. 5453 CodeGenAndEmitDAG(DAG); 5454 } 5455 5456 DOUT << "Total amount of phi nodes to update: " 5457 << PHINodesToUpdate.size() << "\n"; 5458 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 5459 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 5460 << ", " << PHINodesToUpdate[i].second << ")\n";); 5461 5462 // Next, now that we know what the last MBB the LLVM BB expanded is, update 5463 // PHI nodes in successors. 5464 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 5465 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 5466 MachineInstr *PHI = PHINodesToUpdate[i].first; 5467 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5468 "This is not a machine PHI node that we are updating!"); 5469 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 5470 false)); 5471 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5472 } 5473 return; 5474 } 5475 5476 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 5477 // Lower header first, if it wasn't already lowered 5478 if (!BitTestCases[i].Emitted) { 5479 SelectionDAG HSDAG(TLI, MF, FuncInfo, 5480 getAnalysisToUpdate<MachineModuleInfo>(), 5481 NodeAllocator); 5482 CurDAG = &HSDAG; 5483 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); 5484 // Set the current basic block to the mbb we wish to insert the code into 5485 BB = BitTestCases[i].Parent; 5486 HSDL.setCurrentBasicBlock(BB); 5487 // Emit the code 5488 HSDL.visitBitTestHeader(BitTestCases[i]); 5489 HSDAG.setRoot(HSDL.getRoot()); 5490 CodeGenAndEmitDAG(HSDAG); 5491 } 5492 5493 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 5494 SelectionDAG BSDAG(TLI, MF, FuncInfo, 5495 getAnalysisToUpdate<MachineModuleInfo>(), 5496 NodeAllocator); 5497 CurDAG = &BSDAG; 5498 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI); 5499 // Set the current basic block to the mbb we wish to insert the code into 5500 BB = BitTestCases[i].Cases[j].ThisBB; 5501 BSDL.setCurrentBasicBlock(BB); 5502 // Emit the code 5503 if (j+1 != ej) 5504 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 5505 BitTestCases[i].Reg, 5506 BitTestCases[i].Cases[j]); 5507 else 5508 BSDL.visitBitTestCase(BitTestCases[i].Default, 5509 BitTestCases[i].Reg, 5510 BitTestCases[i].Cases[j]); 5511 5512 5513 BSDAG.setRoot(BSDL.getRoot()); 5514 CodeGenAndEmitDAG(BSDAG); 5515 } 5516 5517 // Update PHI Nodes 5518 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 5519 MachineInstr *PHI = PHINodesToUpdate[pi].first; 5520 MachineBasicBlock *PHIBB = PHI->getParent(); 5521 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5522 "This is not a machine PHI node that we are updating!"); 5523 // This is "default" BB. We have two jumps to it. From "header" BB and 5524 // from last "case" BB. 5525 if (PHIBB == BitTestCases[i].Default) { 5526 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5527 false)); 5528 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent)); 5529 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5530 false)); 5531 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases. 5532 back().ThisBB)); 5533 } 5534 // One of "cases" BB. 5535 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 5536 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 5537 if (cBB->succ_end() != 5538 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 5539 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5540 false)); 5541 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 5542 } 5543 } 5544 } 5545 } 5546 5547 // If the JumpTable record is filled in, then we need to emit a jump table. 5548 // Updating the PHI nodes is tricky in this case, since we need to determine 5549 // whether the PHI is a successor of the range check MBB or the jump table MBB 5550 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 5551 // Lower header first, if it wasn't already lowered 5552 if (!JTCases[i].first.Emitted) { 5553 SelectionDAG HSDAG(TLI, MF, FuncInfo, 5554 getAnalysisToUpdate<MachineModuleInfo>(), 5555 NodeAllocator); 5556 CurDAG = &HSDAG; 5557 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); 5558 // Set the current basic block to the mbb we wish to insert the code into 5559 BB = JTCases[i].first.HeaderBB; 5560 HSDL.setCurrentBasicBlock(BB); 5561 // Emit the code 5562 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 5563 HSDAG.setRoot(HSDL.getRoot()); 5564 CodeGenAndEmitDAG(HSDAG); 5565 } 5566 5567 SelectionDAG JSDAG(TLI, MF, FuncInfo, 5568 getAnalysisToUpdate<MachineModuleInfo>(), 5569 NodeAllocator); 5570 CurDAG = &JSDAG; 5571 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI); 5572 // Set the current basic block to the mbb we wish to insert the code into 5573 BB = JTCases[i].second.MBB; 5574 JSDL.setCurrentBasicBlock(BB); 5575 // Emit the code 5576 JSDL.visitJumpTable(JTCases[i].second); 5577 JSDAG.setRoot(JSDL.getRoot()); 5578 CodeGenAndEmitDAG(JSDAG); 5579 5580 // Update PHI Nodes 5581 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 5582 MachineInstr *PHI = PHINodesToUpdate[pi].first; 5583 MachineBasicBlock *PHIBB = PHI->getParent(); 5584 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5585 "This is not a machine PHI node that we are updating!"); 5586 // "default" BB. We can go there only from header BB. 5587 if (PHIBB == JTCases[i].second.Default) { 5588 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5589 false)); 5590 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB)); 5591 } 5592 // JT BB. Just iterate over successors here 5593 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 5594 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5595 false)); 5596 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5597 } 5598 } 5599 } 5600 5601 // If the switch block involved a branch to one of the actual successors, we 5602 // need to update PHI nodes in that block. 5603 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 5604 MachineInstr *PHI = PHINodesToUpdate[i].first; 5605 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5606 "This is not a machine PHI node that we are updating!"); 5607 if (BB->isSuccessor(PHI->getParent())) { 5608 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 5609 false)); 5610 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5611 } 5612 } 5613 5614 // If we generated any switch lowering information, build and codegen any 5615 // additional DAGs necessary. 5616 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 5617 SelectionDAG SDAG(TLI, MF, FuncInfo, 5618 getAnalysisToUpdate<MachineModuleInfo>(), 5619 NodeAllocator); 5620 CurDAG = &SDAG; 5621 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI); 5622 5623 // Set the current basic block to the mbb we wish to insert the code into 5624 BB = SwitchCases[i].ThisBB; 5625 SDL.setCurrentBasicBlock(BB); 5626 5627 // Emit the code 5628 SDL.visitSwitchCase(SwitchCases[i]); 5629 SDAG.setRoot(SDL.getRoot()); 5630 CodeGenAndEmitDAG(SDAG); 5631 5632 // Handle any PHI nodes in successors of this chunk, as if we were coming 5633 // from the original BB before switch expansion. Note that PHI nodes can 5634 // occur multiple times in PHINodesToUpdate. We have to be very careful to 5635 // handle them the right number of times. 5636 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 5637 for (MachineBasicBlock::iterator Phi = BB->begin(); 5638 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 5639 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 5640 for (unsigned pn = 0; ; ++pn) { 5641 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 5642 if (PHINodesToUpdate[pn].first == Phi) { 5643 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn]. 5644 second, false)); 5645 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB)); 5646 break; 5647 } 5648 } 5649 } 5650 5651 // Don't process RHS if same block as LHS. 5652 if (BB == SwitchCases[i].FalseBB) 5653 SwitchCases[i].FalseBB = 0; 5654 5655 // If we haven't handled the RHS, do so now. Otherwise, we're done. 5656 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 5657 SwitchCases[i].FalseBB = 0; 5658 } 5659 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 5660 } 5661} 5662 5663 5664/// Schedule - Pick a safe ordering for instructions for each 5665/// target node in the graph. 5666/// 5667ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) { 5668 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 5669 5670 if (!Ctor) { 5671 Ctor = ISHeuristic; 5672 RegisterScheduler::setDefault(Ctor); 5673 } 5674 5675 ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel); 5676 Scheduler->Run(); 5677 5678 return Scheduler; 5679} 5680 5681 5682HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 5683 return new HazardRecognizer(); 5684} 5685 5686//===----------------------------------------------------------------------===// 5687// Helper functions used by the generated instruction selector. 5688//===----------------------------------------------------------------------===// 5689// Calls to these methods are generated by tblgen. 5690 5691/// CheckAndMask - The isel is trying to match something like (and X, 255). If 5692/// the dag combiner simplified the 255, we still want to match. RHS is the 5693/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 5694/// specified in the .td file (e.g. 255). 5695bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 5696 int64_t DesiredMaskS) const { 5697 const APInt &ActualMask = RHS->getAPIntValue(); 5698 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 5699 5700 // If the actual mask exactly matches, success! 5701 if (ActualMask == DesiredMask) 5702 return true; 5703 5704 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5705 if (ActualMask.intersects(~DesiredMask)) 5706 return false; 5707 5708 // Otherwise, the DAG Combiner may have proven that the value coming in is 5709 // either already zero or is not demanded. Check for known zero input bits. 5710 APInt NeededMask = DesiredMask & ~ActualMask; 5711 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 5712 return true; 5713 5714 // TODO: check to see if missing bits are just not demanded. 5715 5716 // Otherwise, this pattern doesn't match. 5717 return false; 5718} 5719 5720/// CheckOrMask - The isel is trying to match something like (or X, 255). If 5721/// the dag combiner simplified the 255, we still want to match. RHS is the 5722/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 5723/// specified in the .td file (e.g. 255). 5724bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 5725 int64_t DesiredMaskS) const { 5726 const APInt &ActualMask = RHS->getAPIntValue(); 5727 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 5728 5729 // If the actual mask exactly matches, success! 5730 if (ActualMask == DesiredMask) 5731 return true; 5732 5733 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5734 if (ActualMask.intersects(~DesiredMask)) 5735 return false; 5736 5737 // Otherwise, the DAG Combiner may have proven that the value coming in is 5738 // either already zero or is not demanded. Check for known zero input bits. 5739 APInt NeededMask = DesiredMask & ~ActualMask; 5740 5741 APInt KnownZero, KnownOne; 5742 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 5743 5744 // If all the missing bits in the or are already known to be set, match! 5745 if ((NeededMask & KnownOne) == NeededMask) 5746 return true; 5747 5748 // TODO: check to see if missing bits are just not demanded. 5749 5750 // Otherwise, this pattern doesn't match. 5751 return false; 5752} 5753 5754 5755/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 5756/// by tblgen. Others should not call it. 5757void SelectionDAGISel:: 5758SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SelectionDAG &DAG) { 5759 std::vector<SDValue> InOps; 5760 std::swap(InOps, Ops); 5761 5762 Ops.push_back(InOps[0]); // input chain. 5763 Ops.push_back(InOps[1]); // input asm string. 5764 5765 unsigned i = 2, e = InOps.size(); 5766 if (InOps[e-1].getValueType() == MVT::Flag) 5767 --e; // Don't process a flag operand if it is here. 5768 5769 while (i != e) { 5770 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 5771 if ((Flags & 7) != 4 /*MEM*/) { 5772 // Just skip over this operand, copying the operands verbatim. 5773 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 5774 i += (Flags >> 3) + 1; 5775 } else { 5776 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 5777 // Otherwise, this is a memory operand. Ask the target to select it. 5778 std::vector<SDValue> SelOps; 5779 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 5780 cerr << "Could not match memory address. Inline asm failure!\n"; 5781 exit(1); 5782 } 5783 5784 // Add this to the output node. 5785 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 5786 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 5787 IntPtrTy)); 5788 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 5789 i += 2; 5790 } 5791 } 5792 5793 // Add the flag input back if present. 5794 if (e != InOps.size()) 5795 Ops.push_back(InOps.back()); 5796} 5797 5798char SelectionDAGISel::ID = 0; 5799