SelectionDAGISel.cpp revision 76dd96eda05c0dc7dfc62b5b5fbdd20aae86808b
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "SelectionDAGBuild.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/Analysis/AliasAnalysis.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFunction.h" 33#include "llvm/CodeGen/MachineFrameInfo.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/ScheduleDAG.h" 39#include "llvm/CodeGen/SchedulerRegistry.h" 40#include "llvm/CodeGen/SelectionDAG.h" 41#include "llvm/Target/TargetRegisterInfo.h" 42#include "llvm/Target/TargetData.h" 43#include "llvm/Target/TargetFrameInfo.h" 44#include "llvm/Target/TargetInstrInfo.h" 45#include "llvm/Target/TargetLowering.h" 46#include "llvm/Target/TargetMachine.h" 47#include "llvm/Target/TargetOptions.h" 48#include "llvm/Support/Compiler.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/MathExtras.h" 51#include "llvm/Support/Timer.h" 52#include <algorithm> 53using namespace llvm; 54 55static cl::opt<bool> 56EnableValueProp("enable-value-prop", cl::Hidden); 57static cl::opt<bool> 58EnableLegalizeTypes("enable-legalize-types", cl::Hidden); 59static cl::opt<bool> 60EnableFastISel("fast-isel", cl::Hidden, 61 cl::desc("Enable the experimental \"fast\" instruction selector")); 62static cl::opt<bool> 63EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 64 cl::desc("Enable verbose messages in the experimental \"fast\" " 65 "instruction selector")); 66static cl::opt<bool> 67EnableFastISelAbort("fast-isel-abort", cl::Hidden, 68 cl::desc("Enable abort calls when \"fast\" instruction fails")); 69static cl::opt<bool> 70SchedLiveInCopies("schedule-livein-copies", 71 cl::desc("Schedule copies of livein registers"), 72 cl::init(false)); 73 74#ifndef NDEBUG 75static cl::opt<bool> 76ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the first " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before legalize types")); 82static cl::opt<bool> 83ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize")); 85static cl::opt<bool> 86ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before the second " 88 "dag combine pass")); 89static cl::opt<bool> 90ViewISelDAGs("view-isel-dags", cl::Hidden, 91 cl::desc("Pop up a window to show isel dags as they are selected")); 92static cl::opt<bool> 93ViewSchedDAGs("view-sched-dags", cl::Hidden, 94 cl::desc("Pop up a window to show sched dags as they are processed")); 95static cl::opt<bool> 96ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 97 cl::desc("Pop up a window to show SUnit dags after they are processed")); 98#else 99static const bool ViewDAGCombine1 = false, 100 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 101 ViewDAGCombine2 = false, 102 ViewISelDAGs = false, ViewSchedDAGs = false, 103 ViewSUnitDAGs = false; 104#endif 105 106//===---------------------------------------------------------------------===// 107/// 108/// RegisterScheduler class - Track the registration of instruction schedulers. 109/// 110//===---------------------------------------------------------------------===// 111MachinePassRegistry RegisterScheduler::Registry; 112 113//===---------------------------------------------------------------------===// 114/// 115/// ISHeuristic command line option for instruction schedulers. 116/// 117//===---------------------------------------------------------------------===// 118static cl::opt<RegisterScheduler::FunctionPassCtor, false, 119 RegisterPassParser<RegisterScheduler> > 120ISHeuristic("pre-RA-sched", 121 cl::init(&createDefaultScheduler), 122 cl::desc("Instruction schedulers available (before register" 123 " allocation):")); 124 125static RegisterScheduler 126defaultListDAGScheduler("default", " Best scheduler for the target", 127 createDefaultScheduler); 128 129namespace llvm { 130 //===--------------------------------------------------------------------===// 131 /// createDefaultScheduler - This creates an instruction scheduler appropriate 132 /// for the target. 133 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 134 SelectionDAG *DAG, 135 MachineBasicBlock *BB, 136 bool Fast) { 137 TargetLowering &TLI = IS->getTargetLowering(); 138 139 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 140 return createTDListDAGScheduler(IS, DAG, BB, Fast); 141 } else { 142 assert(TLI.getSchedulingPreference() == 143 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 144 return createBURRListDAGScheduler(IS, DAG, BB, Fast); 145 } 146 } 147} 148 149// EmitInstrWithCustomInserter - This method should be implemented by targets 150// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 151// instructions are special in various ways, which require special support to 152// insert. The specified MachineInstr is created but not inserted into any 153// basic blocks, and the scheduler passes ownership of it to this method. 154MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 155 MachineBasicBlock *MBB) { 156 cerr << "If a target marks an instruction with " 157 << "'usesCustomDAGSchedInserter', it must implement " 158 << "TargetLowering::EmitInstrWithCustomInserter!\n"; 159 abort(); 160 return 0; 161} 162 163/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 164/// physical register has only a single copy use, then coalesced the copy 165/// if possible. 166static void EmitLiveInCopy(MachineBasicBlock *MBB, 167 MachineBasicBlock::iterator &InsertPos, 168 unsigned VirtReg, unsigned PhysReg, 169 const TargetRegisterClass *RC, 170 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 171 const MachineRegisterInfo &MRI, 172 const TargetRegisterInfo &TRI, 173 const TargetInstrInfo &TII) { 174 unsigned NumUses = 0; 175 MachineInstr *UseMI = NULL; 176 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 177 UE = MRI.use_end(); UI != UE; ++UI) { 178 UseMI = &*UI; 179 if (++NumUses > 1) 180 break; 181 } 182 183 // If the number of uses is not one, or the use is not a move instruction, 184 // don't coalesce. Also, only coalesce away a virtual register to virtual 185 // register copy. 186 bool Coalesced = false; 187 unsigned SrcReg, DstReg; 188 if (NumUses == 1 && 189 TII.isMoveInstr(*UseMI, SrcReg, DstReg) && 190 TargetRegisterInfo::isVirtualRegister(DstReg)) { 191 VirtReg = DstReg; 192 Coalesced = true; 193 } 194 195 // Now find an ideal location to insert the copy. 196 MachineBasicBlock::iterator Pos = InsertPos; 197 while (Pos != MBB->begin()) { 198 MachineInstr *PrevMI = prior(Pos); 199 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 200 // copyRegToReg might emit multiple instructions to do a copy. 201 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 202 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 203 // This is what the BB looks like right now: 204 // r1024 = mov r0 205 // ... 206 // r1 = mov r1024 207 // 208 // We want to insert "r1025 = mov r1". Inserting this copy below the 209 // move to r1024 makes it impossible for that move to be coalesced. 210 // 211 // r1025 = mov r1 212 // r1024 = mov r0 213 // ... 214 // r1 = mov 1024 215 // r2 = mov 1025 216 break; // Woot! Found a good location. 217 --Pos; 218 } 219 220 TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 221 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 222 if (Coalesced) { 223 if (&*InsertPos == UseMI) ++InsertPos; 224 MBB->erase(UseMI); 225 } 226} 227 228/// EmitLiveInCopies - If this is the first basic block in the function, 229/// and if it has live ins that need to be copied into vregs, emit the 230/// copies into the block. 231static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 232 const MachineRegisterInfo &MRI, 233 const TargetRegisterInfo &TRI, 234 const TargetInstrInfo &TII) { 235 if (SchedLiveInCopies) { 236 // Emit the copies at a heuristically-determined location in the block. 237 DenseMap<MachineInstr*, unsigned> CopyRegMap; 238 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 239 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 240 E = MRI.livein_end(); LI != E; ++LI) 241 if (LI->second) { 242 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 243 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 244 RC, CopyRegMap, MRI, TRI, TII); 245 } 246 } else { 247 // Emit the copies into the top of the block. 248 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 249 E = MRI.livein_end(); LI != E; ++LI) 250 if (LI->second) { 251 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 252 TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 253 LI->second, LI->first, RC, RC); 254 } 255 } 256} 257 258//===----------------------------------------------------------------------===// 259// SelectionDAGISel code 260//===----------------------------------------------------------------------===// 261 262SelectionDAGISel::SelectionDAGISel(TargetLowering &tli, bool fast) : 263 FunctionPass(&ID), TLI(tli), 264 FuncInfo(new FunctionLoweringInfo(TLI)), 265 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 266 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)), 267 GFI(), 268 Fast(fast), 269 DAGSize(0) 270{} 271 272SelectionDAGISel::~SelectionDAGISel() { 273 delete SDL; 274 delete CurDAG; 275 delete FuncInfo; 276} 277 278unsigned SelectionDAGISel::MakeReg(MVT VT) { 279 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 280} 281 282void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 283 AU.addRequired<AliasAnalysis>(); 284 AU.addRequired<GCModuleInfo>(); 285 AU.setPreservesAll(); 286} 287 288bool SelectionDAGISel::runOnFunction(Function &Fn) { 289 // Do some sanity-checking on the command-line options. 290 assert((!EnableFastISelVerbose || EnableFastISel) && 291 "-fast-isel-verbose requires -fast-isel"); 292 assert((!EnableFastISelAbort || EnableFastISel) && 293 "-fast-isel-abort requires -fast-isel"); 294 295 // Get alias analysis for load/store combining. 296 AA = &getAnalysis<AliasAnalysis>(); 297 298 TargetMachine &TM = TLI.getTargetMachine(); 299 MachineFunction &MF = MachineFunction::construct(&Fn, TM); 300 const MachineRegisterInfo &MRI = MF.getRegInfo(); 301 const TargetInstrInfo &TII = *TM.getInstrInfo(); 302 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 303 304 if (MF.getFunction()->hasGC()) 305 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction()); 306 else 307 GFI = 0; 308 RegInfo = &MF.getRegInfo(); 309 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 310 311 FuncInfo->set(Fn, MF, EnableFastISel); 312 MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>(); 313 CurDAG->init(MF, MMI); 314 SDL->init(GFI, *AA); 315 316 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 317 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 318 // Mark landing pad. 319 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 320 321 SelectAllBasicBlocks(Fn, MF, MMI); 322 323 // If the first basic block in the function has live ins that need to be 324 // copied into vregs, emit the copies into the top of the block before 325 // emitting the code for the block. 326 EmitLiveInCopies(MF.begin(), MRI, TRI, TII); 327 328 // Add function live-ins to entry block live-in set. 329 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 330 E = RegInfo->livein_end(); I != E; ++I) 331 MF.begin()->addLiveIn(I->first); 332 333#ifndef NDEBUG 334 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 335 "Not all catch info was assigned to a landing pad!"); 336#endif 337 338 FuncInfo->clear(); 339 340 return true; 341} 342 343static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 344 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 345 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 346 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) { 347 // Apply the catch info to DestBB. 348 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]); 349#ifndef NDEBUG 350 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 351 FLI.CatchInfoFound.insert(EHSel); 352#endif 353 } 354} 355 356/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and 357/// whether object offset >= 0. 358static bool 359IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) { 360 if (!isa<FrameIndexSDNode>(Op)) return false; 361 362 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op); 363 int FrameIdx = FrameIdxNode->getIndex(); 364 return MFI->isFixedObjectIndex(FrameIdx) && 365 MFI->getObjectOffset(FrameIdx) >= 0; 366} 367 368/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could 369/// possibly be overwritten when lowering the outgoing arguments in a tail 370/// call. Currently the implementation of this call is very conservative and 371/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with 372/// virtual registers would be overwritten by direct lowering. 373static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op, 374 MachineFrameInfo * MFI) { 375 RegisterSDNode * OpReg = NULL; 376 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS || 377 (Op.getOpcode()== ISD::CopyFromReg && 378 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) && 379 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) || 380 (Op.getOpcode() == ISD::LOAD && 381 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) || 382 (Op.getOpcode() == ISD::MERGE_VALUES && 383 Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD && 384 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()). 385 getOperand(1)))) 386 return true; 387 return false; 388} 389 390/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 391/// DAG and fixes their tailcall attribute operand. 392static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 393 TargetLowering& TLI) { 394 SDNode * Ret = NULL; 395 SDValue Terminator = DAG.getRoot(); 396 397 // Find RET node. 398 if (Terminator.getOpcode() == ISD::RET) { 399 Ret = Terminator.getNode(); 400 } 401 402 // Fix tail call attribute of CALL nodes. 403 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 404 BI = DAG.allnodes_end(); BI != BE; ) { 405 --BI; 406 if (CallSDNode *TheCall = dyn_cast<CallSDNode>(BI)) { 407 SDValue OpRet(Ret, 0); 408 SDValue OpCall(BI, 0); 409 bool isMarkedTailCall = TheCall->isTailCall(); 410 // If CALL node has tail call attribute set to true and the call is not 411 // eligible (no RET or the target rejects) the attribute is fixed to 412 // false. The TargetLowering::IsEligibleForTailCallOptimization function 413 // must correctly identify tail call optimizable calls. 414 if (!isMarkedTailCall) continue; 415 if (Ret==NULL || 416 !TLI.IsEligibleForTailCallOptimization(TheCall, OpRet, DAG)) { 417 // Not eligible. Mark CALL node as non tail call. Note that we 418 // can modify the call node in place since calls are not CSE'd. 419 TheCall->setNotTailCall(); 420 } else { 421 // Look for tail call clobbered arguments. Emit a series of 422 // copyto/copyfrom virtual register nodes to protect them. 423 SmallVector<SDValue, 32> Ops; 424 SDValue Chain = TheCall->getChain(), InFlag; 425 Ops.push_back(Chain); 426 Ops.push_back(TheCall->getCallee()); 427 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) { 428 SDValue Arg = TheCall->getArg(i); 429 bool isByVal = TheCall->getArgFlags(i).isByVal(); 430 MachineFunction &MF = DAG.getMachineFunction(); 431 MachineFrameInfo *MFI = MF.getFrameInfo(); 432 if (!isByVal && 433 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) { 434 MVT VT = Arg.getValueType(); 435 unsigned VReg = MF.getRegInfo(). 436 createVirtualRegister(TLI.getRegClassFor(VT)); 437 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag); 438 InFlag = Chain.getValue(1); 439 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag); 440 Chain = Arg.getValue(1); 441 InFlag = Arg.getValue(2); 442 } 443 Ops.push_back(Arg); 444 Ops.push_back(TheCall->getArgFlagsVal(i)); 445 } 446 // Link in chain of CopyTo/CopyFromReg. 447 Ops[0] = Chain; 448 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 449 } 450 } 451 } 452} 453 454void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 455 BasicBlock::iterator Begin, 456 BasicBlock::iterator End) { 457 SDL->setCurrentBasicBlock(BB); 458 459 MachineModuleInfo *MMI = CurDAG->getMachineModuleInfo(); 460 461 if (MMI && BB->isLandingPad()) { 462 // Add a label to mark the beginning of the landing pad. Deletion of the 463 // landing pad can thus be detected via the MachineModuleInfo. 464 unsigned LabelID = MMI->addLandingPad(BB); 465 CurDAG->setRoot(CurDAG->getLabel(ISD::EH_LABEL, 466 CurDAG->getEntryNode(), LabelID)); 467 468 // Mark exception register as live in. 469 unsigned Reg = TLI.getExceptionAddressRegister(); 470 if (Reg) BB->addLiveIn(Reg); 471 472 // Mark exception selector register as live in. 473 Reg = TLI.getExceptionSelectorRegister(); 474 if (Reg) BB->addLiveIn(Reg); 475 476 // FIXME: Hack around an exception handling flaw (PR1508): the personality 477 // function and list of typeids logically belong to the invoke (or, if you 478 // like, the basic block containing the invoke), and need to be associated 479 // with it in the dwarf exception handling tables. Currently however the 480 // information is provided by an intrinsic (eh.selector) that can be moved 481 // to unexpected places by the optimizers: if the unwind edge is critical, 482 // then breaking it can result in the intrinsics being in the successor of 483 // the landing pad, not the landing pad itself. This results in exceptions 484 // not being caught because no typeids are associated with the invoke. 485 // This may not be the only way things can go wrong, but it is the only way 486 // we try to work around for the moment. 487 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 488 489 if (Br && Br->isUnconditional()) { // Critical edge? 490 BasicBlock::iterator I, E; 491 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 492 if (isa<EHSelectorInst>(I)) 493 break; 494 495 if (I == E) 496 // No catch info found - try to extract some from the successor. 497 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 498 } 499 } 500 501 // Lower all of the non-terminator instructions. 502 for (BasicBlock::iterator I = Begin; I != End; ++I) 503 if (!isa<TerminatorInst>(I)) 504 SDL->visit(*I); 505 506 // Ensure that all instructions which are used outside of their defining 507 // blocks are available as virtual registers. Invoke is handled elsewhere. 508 for (BasicBlock::iterator I = Begin; I != End; ++I) 509 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 510 DenseMap<const Value*,unsigned>::iterator VMI =FuncInfo->ValueMap.find(I); 511 if (VMI != FuncInfo->ValueMap.end()) 512 SDL->CopyValueToVirtualRegister(I, VMI->second); 513 } 514 515 // Handle PHI nodes in successor blocks. 516 if (End == LLVMBB->end()) { 517 HandlePHINodesInSuccessorBlocks(LLVMBB); 518 519 // Lower the terminator after the copies are emitted. 520 SDL->visit(*LLVMBB->getTerminator()); 521 } 522 523 // Make sure the root of the DAG is up-to-date. 524 CurDAG->setRoot(SDL->getControlRoot()); 525 526 // Check whether calls in this block are real tail calls. Fix up CALL nodes 527 // with correct tailcall attribute so that the target can rely on the tailcall 528 // attribute indicating whether the call is really eligible for tail call 529 // optimization. 530 if (PerformTailCallOpt) 531 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI); 532 533 // Final step, emit the lowered DAG as machine code. 534 CodeGenAndEmitDAG(); 535 SDL->clear(); 536} 537 538void SelectionDAGISel::ComputeLiveOutVRegInfo() { 539 SmallPtrSet<SDNode*, 128> VisitedNodes; 540 SmallVector<SDNode*, 128> Worklist; 541 542 Worklist.push_back(CurDAG->getRoot().getNode()); 543 544 APInt Mask; 545 APInt KnownZero; 546 APInt KnownOne; 547 548 while (!Worklist.empty()) { 549 SDNode *N = Worklist.back(); 550 Worklist.pop_back(); 551 552 // If we've already seen this node, ignore it. 553 if (!VisitedNodes.insert(N)) 554 continue; 555 556 // Otherwise, add all chain operands to the worklist. 557 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 558 if (N->getOperand(i).getValueType() == MVT::Other) 559 Worklist.push_back(N->getOperand(i).getNode()); 560 561 // If this is a CopyToReg with a vreg dest, process it. 562 if (N->getOpcode() != ISD::CopyToReg) 563 continue; 564 565 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 566 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 567 continue; 568 569 // Ignore non-scalar or non-integer values. 570 SDValue Src = N->getOperand(2); 571 MVT SrcVT = Src.getValueType(); 572 if (!SrcVT.isInteger() || SrcVT.isVector()) 573 continue; 574 575 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 576 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 577 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 578 579 // Only install this information if it tells us something. 580 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 581 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 582 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo(); 583 if (DestReg >= FLI.LiveOutRegInfo.size()) 584 FLI.LiveOutRegInfo.resize(DestReg+1); 585 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg]; 586 LOI.NumSignBits = NumSignBits; 587 LOI.KnownOne = NumSignBits; 588 LOI.KnownZero = NumSignBits; 589 } 590 } 591} 592 593void SelectionDAGISel::CodeGenAndEmitDAG() { 594 std::string GroupName; 595 if (TimePassesIsEnabled) 596 GroupName = "Instruction Selection and Scheduling"; 597 std::string BlockName; 598 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 599 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs) 600 BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' + 601 BB->getBasicBlock()->getName(); 602 603 DOUT << "Initial selection DAG:\n"; 604 DEBUG(CurDAG->dump()); 605 606 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 607 608 // Run the DAG combiner in pre-legalize mode. 609 if (TimePassesIsEnabled) { 610 NamedRegionTimer T("DAG Combining 1", GroupName); 611 CurDAG->Combine(false, *AA, Fast); 612 } else { 613 CurDAG->Combine(false, *AA, Fast); 614 } 615 616 DOUT << "Optimized lowered selection DAG:\n"; 617 DEBUG(CurDAG->dump()); 618 619 // Second step, hack on the DAG until it only uses operations and types that 620 // the target supports. 621 if (EnableLegalizeTypes) {// Enable this some day. 622 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 623 BlockName); 624 625 if (TimePassesIsEnabled) { 626 NamedRegionTimer T("Type Legalization", GroupName); 627 CurDAG->LegalizeTypes(); 628 } else { 629 CurDAG->LegalizeTypes(); 630 } 631 632 DOUT << "Type-legalized selection DAG:\n"; 633 DEBUG(CurDAG->dump()); 634 635 // TODO: enable a dag combine pass here. 636 } 637 638 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 639 640 if (TimePassesIsEnabled) { 641 NamedRegionTimer T("DAG Legalization", GroupName); 642 CurDAG->Legalize(); 643 } else { 644 CurDAG->Legalize(); 645 } 646 647 DOUT << "Legalized selection DAG:\n"; 648 DEBUG(CurDAG->dump()); 649 650 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 651 652 // Run the DAG combiner in post-legalize mode. 653 if (TimePassesIsEnabled) { 654 NamedRegionTimer T("DAG Combining 2", GroupName); 655 CurDAG->Combine(true, *AA, Fast); 656 } else { 657 CurDAG->Combine(true, *AA, Fast); 658 } 659 660 DOUT << "Optimized legalized selection DAG:\n"; 661 DEBUG(CurDAG->dump()); 662 663 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 664 665 if (!Fast && EnableValueProp) 666 ComputeLiveOutVRegInfo(); 667 668 // Third, instruction select all of the operations to machine code, adding the 669 // code to the MachineBasicBlock. 670 if (TimePassesIsEnabled) { 671 NamedRegionTimer T("Instruction Selection", GroupName); 672 InstructionSelect(); 673 } else { 674 InstructionSelect(); 675 } 676 677 DOUT << "Selected selection DAG:\n"; 678 DEBUG(CurDAG->dump()); 679 680 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 681 682 // Schedule machine code. 683 ScheduleDAG *Scheduler; 684 if (TimePassesIsEnabled) { 685 NamedRegionTimer T("Instruction Scheduling", GroupName); 686 Scheduler = Schedule(); 687 } else { 688 Scheduler = Schedule(); 689 } 690 691 if (ViewSUnitDAGs) Scheduler->viewGraph(); 692 693 // Emit machine code to BB. This can change 'BB' to the last block being 694 // inserted into. 695 if (TimePassesIsEnabled) { 696 NamedRegionTimer T("Instruction Creation", GroupName); 697 BB = Scheduler->EmitSchedule(); 698 } else { 699 BB = Scheduler->EmitSchedule(); 700 } 701 702 // Free the scheduler state. 703 if (TimePassesIsEnabled) { 704 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 705 delete Scheduler; 706 } else { 707 delete Scheduler; 708 } 709 710 DOUT << "Selected machine code:\n"; 711 DEBUG(BB->dump()); 712} 713 714void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF, 715 MachineModuleInfo *MMI) { 716 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 717 BasicBlock *LLVMBB = &*I; 718 BB = FuncInfo->MBBMap[LLVMBB]; 719 720 BasicBlock::iterator const Begin = LLVMBB->begin(); 721 BasicBlock::iterator const End = LLVMBB->end(); 722 BasicBlock::iterator BI = Begin; 723 724 // Lower any arguments needed in this block if this is the entry block. 725 if (LLVMBB == &Fn.getEntryBlock()) 726 LowerArguments(LLVMBB); 727 728 // Before doing SelectionDAG ISel, see if FastISel has been requested. 729 // FastISel doesn't support EH landing pads, which require special handling. 730 if (EnableFastISel && !BB->isLandingPad()) { 731 if (FastISel *F = TLI.createFastISel(*FuncInfo->MF, MMI, 732 FuncInfo->ValueMap, 733 FuncInfo->MBBMap, 734 FuncInfo->StaticAllocaMap)) { 735 // Emit code for any incoming arguments. This must happen before 736 // beginning FastISel on the entry block. 737 if (LLVMBB == &Fn.getEntryBlock()) { 738 CurDAG->setRoot(SDL->getControlRoot()); 739 CodeGenAndEmitDAG(); 740 SDL->clear(); 741 } 742 F->setCurrentBlock(BB); 743 // Do FastISel on as many instructions as possible. 744 for (; BI != End; ++BI) { 745 // Just before the terminator instruction, insert instructions to 746 // feed PHI nodes in successor blocks. 747 if (isa<TerminatorInst>(BI)) 748 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, F)) { 749 if (EnableFastISelVerbose || EnableFastISelAbort) { 750 cerr << "FastISel miss: "; 751 BI->dump(); 752 } 753 if (EnableFastISelAbort) 754 assert(0 && "FastISel didn't handle a PHI in a successor"); 755 break; 756 } 757 758 // First try normal tablegen-generated "fast" selection. 759 if (F->SelectInstruction(BI)) 760 continue; 761 762 // Next, try calling the target to attempt to handle the instruction. 763 if (F->TargetSelectInstruction(BI)) 764 continue; 765 766 // Then handle certain instructions as single-LLVM-Instruction blocks. 767 if (isa<CallInst>(BI)) { 768 if (BI->getType() != Type::VoidTy) { 769 unsigned &R = FuncInfo->ValueMap[BI]; 770 if (!R) 771 R = FuncInfo->CreateRegForValue(BI); 772 } 773 774 SelectBasicBlock(LLVMBB, BI, next(BI)); 775 continue; 776 } 777 778 // Otherwise, give up on FastISel for the rest of the block. 779 // For now, be a little lenient about non-branch terminators. 780 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 781 if (EnableFastISelVerbose || EnableFastISelAbort) { 782 cerr << "FastISel miss: "; 783 BI->dump(); 784 } 785 if (EnableFastISelAbort) 786 // The "fast" selector couldn't handle something and bailed. 787 // For the purpose of debugging, just abort. 788 assert(0 && "FastISel didn't select the entire block"); 789 } 790 break; 791 } 792 delete F; 793 } 794 } 795 796 // Run SelectionDAG instruction selection on the remainder of the block 797 // not handled by FastISel. If FastISel is not run, this is the entire 798 // block. 799 if (BI != End) 800 SelectBasicBlock(LLVMBB, BI, End); 801 802 FinishBasicBlock(); 803 } 804} 805 806void 807SelectionDAGISel::FinishBasicBlock() { 808 809 // Perform target specific isel post processing. 810 InstructionSelectPostProcessing(); 811 812 DOUT << "Target-post-processed machine code:\n"; 813 DEBUG(BB->dump()); 814 815 DOUT << "Total amount of phi nodes to update: " 816 << SDL->PHINodesToUpdate.size() << "\n"; 817 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) 818 DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first 819 << ", " << SDL->PHINodesToUpdate[i].second << ")\n";); 820 821 // Next, now that we know what the last MBB the LLVM BB expanded is, update 822 // PHI nodes in successors. 823 if (SDL->SwitchCases.empty() && 824 SDL->JTCases.empty() && 825 SDL->BitTestCases.empty()) { 826 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 827 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 828 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 829 "This is not a machine PHI node that we are updating!"); 830 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 831 false)); 832 PHI->addOperand(MachineOperand::CreateMBB(BB)); 833 } 834 SDL->PHINodesToUpdate.clear(); 835 return; 836 } 837 838 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) { 839 // Lower header first, if it wasn't already lowered 840 if (!SDL->BitTestCases[i].Emitted) { 841 // Set the current basic block to the mbb we wish to insert the code into 842 BB = SDL->BitTestCases[i].Parent; 843 SDL->setCurrentBasicBlock(BB); 844 // Emit the code 845 SDL->visitBitTestHeader(SDL->BitTestCases[i]); 846 CurDAG->setRoot(SDL->getRoot()); 847 CodeGenAndEmitDAG(); 848 SDL->clear(); 849 } 850 851 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) { 852 // Set the current basic block to the mbb we wish to insert the code into 853 BB = SDL->BitTestCases[i].Cases[j].ThisBB; 854 SDL->setCurrentBasicBlock(BB); 855 // Emit the code 856 if (j+1 != ej) 857 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB, 858 SDL->BitTestCases[i].Reg, 859 SDL->BitTestCases[i].Cases[j]); 860 else 861 SDL->visitBitTestCase(SDL->BitTestCases[i].Default, 862 SDL->BitTestCases[i].Reg, 863 SDL->BitTestCases[i].Cases[j]); 864 865 866 CurDAG->setRoot(SDL->getRoot()); 867 CodeGenAndEmitDAG(); 868 SDL->clear(); 869 } 870 871 // Update PHI Nodes 872 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 873 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 874 MachineBasicBlock *PHIBB = PHI->getParent(); 875 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 876 "This is not a machine PHI node that we are updating!"); 877 // This is "default" BB. We have two jumps to it. From "header" BB and 878 // from last "case" BB. 879 if (PHIBB == SDL->BitTestCases[i].Default) { 880 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 881 false)); 882 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent)); 883 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 884 false)); 885 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases. 886 back().ThisBB)); 887 } 888 // One of "cases" BB. 889 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); 890 j != ej; ++j) { 891 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB; 892 if (cBB->succ_end() != 893 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 894 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 895 false)); 896 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 897 } 898 } 899 } 900 } 901 SDL->BitTestCases.clear(); 902 903 // If the JumpTable record is filled in, then we need to emit a jump table. 904 // Updating the PHI nodes is tricky in this case, since we need to determine 905 // whether the PHI is a successor of the range check MBB or the jump table MBB 906 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) { 907 // Lower header first, if it wasn't already lowered 908 if (!SDL->JTCases[i].first.Emitted) { 909 // Set the current basic block to the mbb we wish to insert the code into 910 BB = SDL->JTCases[i].first.HeaderBB; 911 SDL->setCurrentBasicBlock(BB); 912 // Emit the code 913 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first); 914 CurDAG->setRoot(SDL->getRoot()); 915 CodeGenAndEmitDAG(); 916 SDL->clear(); 917 } 918 919 // Set the current basic block to the mbb we wish to insert the code into 920 BB = SDL->JTCases[i].second.MBB; 921 SDL->setCurrentBasicBlock(BB); 922 // Emit the code 923 SDL->visitJumpTable(SDL->JTCases[i].second); 924 CurDAG->setRoot(SDL->getRoot()); 925 CodeGenAndEmitDAG(); 926 SDL->clear(); 927 928 // Update PHI Nodes 929 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 930 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 931 MachineBasicBlock *PHIBB = PHI->getParent(); 932 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 933 "This is not a machine PHI node that we are updating!"); 934 // "default" BB. We can go there only from header BB. 935 if (PHIBB == SDL->JTCases[i].second.Default) { 936 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 937 false)); 938 PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB)); 939 } 940 // JT BB. Just iterate over successors here 941 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 942 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 943 false)); 944 PHI->addOperand(MachineOperand::CreateMBB(BB)); 945 } 946 } 947 } 948 SDL->JTCases.clear(); 949 950 // If the switch block involved a branch to one of the actual successors, we 951 // need to update PHI nodes in that block. 952 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 953 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 954 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 955 "This is not a machine PHI node that we are updating!"); 956 if (BB->isSuccessor(PHI->getParent())) { 957 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 958 false)); 959 PHI->addOperand(MachineOperand::CreateMBB(BB)); 960 } 961 } 962 963 // If we generated any switch lowering information, build and codegen any 964 // additional DAGs necessary. 965 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) { 966 // Set the current basic block to the mbb we wish to insert the code into 967 BB = SDL->SwitchCases[i].ThisBB; 968 SDL->setCurrentBasicBlock(BB); 969 970 // Emit the code 971 SDL->visitSwitchCase(SDL->SwitchCases[i]); 972 CurDAG->setRoot(SDL->getRoot()); 973 CodeGenAndEmitDAG(); 974 SDL->clear(); 975 976 // Handle any PHI nodes in successors of this chunk, as if we were coming 977 // from the original BB before switch expansion. Note that PHI nodes can 978 // occur multiple times in PHINodesToUpdate. We have to be very careful to 979 // handle them the right number of times. 980 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 981 for (MachineBasicBlock::iterator Phi = BB->begin(); 982 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 983 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 984 for (unsigned pn = 0; ; ++pn) { 985 assert(pn != SDL->PHINodesToUpdate.size() && 986 "Didn't find PHI entry!"); 987 if (SDL->PHINodesToUpdate[pn].first == Phi) { 988 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn]. 989 second, false)); 990 Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB)); 991 break; 992 } 993 } 994 } 995 996 // Don't process RHS if same block as LHS. 997 if (BB == SDL->SwitchCases[i].FalseBB) 998 SDL->SwitchCases[i].FalseBB = 0; 999 1000 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1001 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB; 1002 SDL->SwitchCases[i].FalseBB = 0; 1003 } 1004 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0); 1005 } 1006 SDL->SwitchCases.clear(); 1007 1008 SDL->PHINodesToUpdate.clear(); 1009} 1010 1011 1012/// Schedule - Pick a safe ordering for instructions for each 1013/// target node in the graph. 1014/// 1015ScheduleDAG *SelectionDAGISel::Schedule() { 1016 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1017 1018 if (!Ctor) { 1019 Ctor = ISHeuristic; 1020 RegisterScheduler::setDefault(Ctor); 1021 } 1022 1023 ScheduleDAG *Scheduler = Ctor(this, CurDAG, BB, Fast); 1024 Scheduler->Run(); 1025 1026 return Scheduler; 1027} 1028 1029 1030HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1031 return new HazardRecognizer(); 1032} 1033 1034//===----------------------------------------------------------------------===// 1035// Helper functions used by the generated instruction selector. 1036//===----------------------------------------------------------------------===// 1037// Calls to these methods are generated by tblgen. 1038 1039/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1040/// the dag combiner simplified the 255, we still want to match. RHS is the 1041/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1042/// specified in the .td file (e.g. 255). 1043bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1044 int64_t DesiredMaskS) const { 1045 const APInt &ActualMask = RHS->getAPIntValue(); 1046 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1047 1048 // If the actual mask exactly matches, success! 1049 if (ActualMask == DesiredMask) 1050 return true; 1051 1052 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1053 if (ActualMask.intersects(~DesiredMask)) 1054 return false; 1055 1056 // Otherwise, the DAG Combiner may have proven that the value coming in is 1057 // either already zero or is not demanded. Check for known zero input bits. 1058 APInt NeededMask = DesiredMask & ~ActualMask; 1059 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1060 return true; 1061 1062 // TODO: check to see if missing bits are just not demanded. 1063 1064 // Otherwise, this pattern doesn't match. 1065 return false; 1066} 1067 1068/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1069/// the dag combiner simplified the 255, we still want to match. RHS is the 1070/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1071/// specified in the .td file (e.g. 255). 1072bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1073 int64_t DesiredMaskS) const { 1074 const APInt &ActualMask = RHS->getAPIntValue(); 1075 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1076 1077 // If the actual mask exactly matches, success! 1078 if (ActualMask == DesiredMask) 1079 return true; 1080 1081 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1082 if (ActualMask.intersects(~DesiredMask)) 1083 return false; 1084 1085 // Otherwise, the DAG Combiner may have proven that the value coming in is 1086 // either already zero or is not demanded. Check for known zero input bits. 1087 APInt NeededMask = DesiredMask & ~ActualMask; 1088 1089 APInt KnownZero, KnownOne; 1090 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1091 1092 // If all the missing bits in the or are already known to be set, match! 1093 if ((NeededMask & KnownOne) == NeededMask) 1094 return true; 1095 1096 // TODO: check to see if missing bits are just not demanded. 1097 1098 // Otherwise, this pattern doesn't match. 1099 return false; 1100} 1101 1102 1103/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1104/// by tblgen. Others should not call it. 1105void SelectionDAGISel:: 1106SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1107 std::vector<SDValue> InOps; 1108 std::swap(InOps, Ops); 1109 1110 Ops.push_back(InOps[0]); // input chain. 1111 Ops.push_back(InOps[1]); // input asm string. 1112 1113 unsigned i = 2, e = InOps.size(); 1114 if (InOps[e-1].getValueType() == MVT::Flag) 1115 --e; // Don't process a flag operand if it is here. 1116 1117 while (i != e) { 1118 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1119 if ((Flags & 7) != 4 /*MEM*/ && 1120 (Flags & 7) != 7 /*MEM OVERLAPS EARLYCLOBBER*/) { 1121 // Just skip over this operand, copying the operands verbatim. 1122 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 1123 i += (Flags >> 3) + 1; 1124 } else { 1125 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 1126 // Otherwise, this is a memory operand. Ask the target to select it. 1127 std::vector<SDValue> SelOps; 1128 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1129 cerr << "Could not match memory address. Inline asm failure!\n"; 1130 exit(1); 1131 } 1132 1133 // Add this to the output node. 1134 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy(); 1135 Ops.push_back(CurDAG->getTargetConstant((Flags & 7) | (SelOps.size()<< 3), 1136 IntPtrTy)); 1137 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1138 i += 2; 1139 } 1140 } 1141 1142 // Add the flag input back if present. 1143 if (e != InOps.size()) 1144 Ops.push_back(InOps.back()); 1145} 1146 1147char SelectionDAGISel::ID = 0; 1148